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(** * Imp: Simple Imperative Programs *)
(** In this chapter, we begin a new direction that will continue for
the rest of the course. Up to now most of our attention has been
focused on various aspects of Coq itself, while from now on we'll
mostly be using Coq to formalize other things. (We'll continue to
pause from time to time to introduce a few additional aspects of
Coq.)
Our first case study is a _simple imperative programming language_
called Imp, embodying a tiny core fragment of conventional
mainstream languages such as C and Java. Here is a familiar
mathematical function written in Imp.
Z ::= X;;
Y ::= 1;;
WHILE not (Z = 0) DO
Y ::= Y * Z;;
Z ::= Z - 1
END
*)
(** This chapter looks at how to define the _syntax_ and _semantics_
of Imp; the chapters that follow develop a theory of _program
equivalence_ and introduce _Hoare Logic_, a widely used logic for
reasoning about imperative programs. *)
(* ####################################################### *)
(** *** Sflib *)
(** A minor technical point: Instead of asking Coq to import our
earlier definitions from chapter [Logic], we import a small library
called [Sflib.v], containing just a few definitions and theorems
from earlier chapters that we'll actually use in the rest of the
course. This change should be nearly invisible, since most of what's
missing from Sflib has identical definitions in the Coq standard
library. The main reason for doing it is to tidy the global Coq
environment so that, for example, it is easier to search for
relevant theorems. *)
Require Export SfLib.
(* ####################################################### *)
(** * Arithmetic and Boolean Expressions *)
(** We'll present Imp in three parts: first a core language of
_arithmetic and boolean expressions_, then an extension of these
expressions with _variables_, and finally a language of _commands_
including assignment, conditions, sequencing, and loops. *)
(* ####################################################### *)
(** ** Syntax *)
Module AExp.
(** These two definitions specify the _abstract syntax_ of
arithmetic and boolean expressions. *)
Inductive aexp : Type :=
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
Inductive bexp : Type :=
| BTrue : bexp
| BFalse : bexp
| BEq : aexp -> aexp -> bexp
| BLe : aexp -> aexp -> bexp
| BNot : bexp -> bexp
| BAnd : bexp -> bexp -> bexp.
(** In this chapter, we'll elide the translation from the
concrete syntax that a programmer would actually write to these
abstract syntax trees -- the process that, for example, would
translate the string ["1+2*3"] to the AST [APlus (ANum
1) (AMult (ANum 2) (ANum 3))]. The optional chapter [ImpParser]
develops a simple implementation of a lexical analyzer and parser
that can perform this translation. You do _not_ need to
understand that file to understand this one, but if you haven't
taken a course where these techniques are covered (e.g., a
compilers course) you may want to skim it. *)
(** For comparison, here's a conventional BNF (Backus-Naur Form)
grammar defining the same abstract syntax:
a ::= nat
| a + a
| a - a
| a * a
b ::= true
| false
| a = a
| a <= a
| b and b
| not b
*)
(** Compared to the Coq version above...
- The BNF is more informal -- for example, it gives some
suggestions about the surface syntax of expressions (like the
fact that the addition operation is written [+] and is an
infix symbol) while leaving other aspects of lexical analysis
and parsing (like the relative precedence of [+], [-], and
[*]) unspecified. Some additional information -- and human
intelligence -- would be required to turn this description
into a formal definition (when implementing a compiler, for
example).
The Coq version consistently omits all this information and
concentrates on the abstract syntax only.
- On the other hand, the BNF version is lighter and
easier to read. Its informality makes it flexible, which is
a huge advantage in situations like discussions at the
blackboard, where conveying general ideas is more important
than getting every detail nailed down precisely.
Indeed, there are dozens of BNF-like notations and people
switch freely among them, usually without bothering to say which
form of BNF they're using because there is no need to: a
rough-and-ready informal understanding is all that's
needed. *)
(** It's good to be comfortable with both sorts of notations:
informal ones for communicating between humans and formal ones for
carrying out implementations and proofs. *)
(* ####################################################### *)
(** ** Evaluation *)
(** _Evaluating_ an arithmetic expression produces a number. *)
Fixpoint aeval (a : aexp) : nat :=
match a with
| ANum n => n
| APlus a1 a2 => (aeval a1) + (aeval a2)
| AMinus a1 a2 => (aeval a1) - (aeval a2)
| AMult a1 a2 => (aeval a1) * (aeval a2)
end.
Example test_aeval1:
aeval (APlus (ANum 2) (ANum 2)) = 4.
Proof. reflexivity. Qed.
(** Similarly, evaluating a boolean expression yields a boolean. *)
Fixpoint beval (b : bexp) : bool :=
match b with
| BTrue => true
| BFalse => false
| BEq a1 a2 => beq_nat (aeval a1) (aeval a2)
| BLe a1 a2 => ble_nat (aeval a1) (aeval a2)
| BNot b1 => negb (beval b1)
| BAnd b1 b2 => andb (beval b1) (beval b2)
end.
(* ####################################################### *)
(** ** Optimization *)
(** We haven't defined very much yet, but we can already get
some mileage out of the definitions. Suppose we define a function
that takes an arithmetic expression and slightly simplifies it,
changing every occurrence of [0+e] (i.e., [(APlus (ANum 0) e])
into just [e]. *)
Fixpoint optimize_0plus (a:aexp) : aexp :=
match a with
| ANum n =>
ANum n
| APlus (ANum 0) e2 =>
optimize_0plus e2
| APlus e1 e2 =>
APlus (optimize_0plus e1) (optimize_0plus e2)
| AMinus e1 e2 =>
AMinus (optimize_0plus e1) (optimize_0plus e2)
| AMult e1 e2 =>
AMult (optimize_0plus e1) (optimize_0plus e2)
end.
(** To make sure our optimization is doing the right thing we
can test it on some examples and see if the output looks OK. *)
Example test_optimize_0plus:
optimize_0plus (APlus (ANum 2)
(APlus (ANum 0)
(APlus (ANum 0) (ANum 1))))
= APlus (ANum 2) (ANum 1).
Proof. reflexivity. Qed.
(** But if we want to be sure the optimization is correct --
i.e., that evaluating an optimized expression gives the same
result as the original -- we should prove it. *)
Theorem optimize_0plus_sound: forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a. induction a.
Case "ANum". reflexivity.
Case "APlus". destruct a1.
SCase "a1 = ANum n". destruct n.
SSCase "n = 0". simpl. apply IHa2.
SSCase "n <> 0". simpl. rewrite IHa2. reflexivity.
SCase "a1 = APlus a1_1 a1_2".
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
SCase "a1 = AMinus a1_1 a1_2".
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
SCase "a1 = AMult a1_1 a1_2".
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
Case "AMinus".
simpl. rewrite IHa1. rewrite IHa2. reflexivity.
Case "AMult".
simpl. rewrite IHa1. rewrite IHa2. reflexivity. Qed.
(* ####################################################### *)
(** * Coq Automation *)
(** The repetition in this last proof is starting to be a little
annoying. If either the language of arithmetic expressions or the
optimization being proved sound were significantly more complex,
it would begin to be a real problem.
So far, we've been doing all our proofs using just a small handful
of Coq's tactics and completely ignoring its powerful facilities
for constructing parts of proofs automatically. This section
introduces some of these facilities, and we will see more over the
next several chapters. Getting used to them will take some
energy -- Coq's automation is a power tool -- but it will allow us
to scale up our efforts to more complex definitions and more
interesting properties without becoming overwhelmed by boring,
repetitive, low-level details. *)
(* ####################################################### *)
(** ** Tacticals *)
(** _Tacticals_ is Coq's term for tactics that take other tactics as
arguments -- "higher-order tactics," if you will. *)
(* ####################################################### *)
(** *** The [repeat] Tactical *)
(** The [repeat] tactical takes another tactic and keeps applying
this tactic until the tactic fails. Here is an example showing
that [100] is even using repeat. *)
Theorem ev100 : ev 100.
Proof.
repeat (apply ev_SS). (* applies ev_SS 50 times,
until [apply ev_SS] fails *)
apply ev_0.
Qed.
(* Print ev100. *)
(** The [repeat T] tactic never fails; if the tactic [T] doesn't apply
to the original goal, then repeat still succeeds without changing
the original goal (it repeats zero times). *)
Theorem ev100' : ev 100.
Proof.
repeat (apply ev_0). (* doesn't fail, applies ev_0 zero times *)
repeat (apply ev_SS). apply ev_0. (* we can continue the proof *)
Qed.
(** The [repeat T] tactic does not have any bound on the number of
times it applies [T]. If [T] is a tactic that always succeeds then
repeat [T] will loop forever (e.g. [repeat simpl] loops forever
since [simpl] always succeeds). While Coq's term language is
guaranteed to terminate, Coq's tactic language is not! *)
(* ####################################################### *)
(** *** The [try] Tactical *)
(** If [T] is a tactic, then [try T] is a tactic that is just like [T]
except that, if [T] fails, [try T] _successfully_ does nothing at
all (instead of failing). *)
Theorem silly1 : forall ae, aeval ae = aeval ae.
Proof. try reflexivity. (* this just does [reflexivity] *) Qed.
Theorem silly2 : forall (P : Prop), P -> P.
Proof.
intros P HP.
try reflexivity. (* just [reflexivity] would have failed *)
apply HP. (* we can still finish the proof in some other way *)
Qed.
(** Using [try] in a completely manual proof is a bit silly, but
we'll see below that [try] is very useful for doing automated
proofs in conjunction with the [;] tactical. *)
(* ####################################################### *)
(** *** The [;] Tactical (Simple Form) *)
(** In its most commonly used form, the [;] tactical takes two tactics
as argument: [T;T'] first performs the tactic [T] and then
performs the tactic [T'] on _each subgoal_ generated by [T]. *)
(** For example, consider the following trivial lemma: *)
Lemma foo : forall n, ble_nat 0 n = true.
Proof.
intros.
destruct n.
(* Leaves two subgoals, which are discharged identically... *)
Case "n=0". simpl. reflexivity.
Case "n=Sn'". simpl. reflexivity.
Qed.
(** We can simplify this proof using the [;] tactical: *)
Lemma foo' : forall n, ble_nat 0 n = true.
Proof.
intros.
destruct n; (* [destruct] the current goal *)
simpl; (* then [simpl] each resulting subgoal *)
reflexivity. (* and do [reflexivity] on each resulting subgoal *)
Qed.
(** Using [try] and [;] together, we can get rid of the repetition in
the proof that was bothering us a little while ago. *)
Theorem optimize_0plus_sound': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
induction a;
(* Most cases follow directly by the IH *)
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity).
(* The remaining cases -- ANum and APlus -- are different *)
Case "ANum". reflexivity.
Case "APlus".
destruct a1;
(* Again, most cases follow directly by the IH *)
try (simpl; simpl in IHa1; rewrite IHa1;
rewrite IHa2; reflexivity).
(* The interesting case, on which the [try...] does nothing,
is when [e1 = ANum n]. In this case, we have to destruct
[n] (to see whether the optimization applies) and rewrite
with the induction hypothesis. *)
SCase "a1 = ANum n". destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(** Coq experts often use this "[...; try... ]" idiom after a tactic
like [induction] to take care of many similar cases all at once.
Naturally, this practice has an analog in informal proofs.
Here is an informal proof of this theorem that matches the
structure of the formal one:
_Theorem_: For all arithmetic expressions [a],
aeval (optimize_0plus a) = aeval a.
_Proof_: By induction on [a]. The [AMinus] and [AMult] cases
follow directly from the IH. The remaining cases are as follows:
- Suppose [a = ANum n] for some [n]. We must show
aeval (optimize_0plus (ANum n)) = aeval (ANum n).
This is immediate from the definition of [optimize_0plus].
- Suppose [a = APlus a1 a2] for some [a1] and [a2]. We
must show
aeval (optimize_0plus (APlus a1 a2))
= aeval (APlus a1 a2).
Consider the possible forms of [a1]. For most of them,
[optimize_0plus] simply calls itself recursively for the
subexpressions and rebuilds a new expression of the same form
as [a1]; in these cases, the result follows directly from the
IH.
The interesting case is when [a1 = ANum n] for some [n].
If [n = ANum 0], then
optimize_0plus (APlus a1 a2) = optimize_0plus a2
and the IH for [a2] is exactly what we need. On the other
hand, if [n = S n'] for some [n'], then again [optimize_0plus]
simply calls itself recursively, and the result follows from
the IH. [] *)
(** This proof can still be improved: the first case (for [a = ANum
n]) is very trivial -- even more trivial than the cases that we
said simply followed from the IH -- yet we have chosen to write it
out in full. It would be better and clearer to drop it and just
say, at the top, "Most cases are either immediate or direct from
the IH. The only interesting case is the one for [APlus]..." We
can make the same improvement in our formal proof too. Here's how
it looks: *)
Theorem optimize_0plus_sound'': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
induction a;
(* Most cases follow directly by the IH *)
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity);
(* ... or are immediate by definition *)
try reflexivity.
(* The interesting case is when a = APlus a1 a2. *)
Case "APlus".
destruct a1; try (simpl; simpl in IHa1; rewrite IHa1;
rewrite IHa2; reflexivity).
SCase "a1 = ANum n". destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(* ####################################################### *)
(** *** The [;] Tactical (General Form) *)
(** The [;] tactical has a more general than the simple [T;T'] we've
seen above, which is sometimes also useful. If [T], [T1], ...,
[Tn] are tactics, then
T; [T1 | T2 | ... | Tn]
is a tactic that first performs [T] and then performs [T1] on the
first subgoal generated by [T], performs [T2] on the second
subgoal, etc.
So [T;T'] is just special notation for the case when all of the
[Ti]'s are the same tactic; i.e. [T;T'] is just a shorthand for:
T; [T' | T' | ... | T']
*)
(* ####################################################### *)
(** ** Defining New Tactic Notations *)
(** Coq also provides several ways of "programming" tactic scripts.
- The [Tactic Notation] idiom illustrated below gives a handy
way to define "shorthand tactics" that bundle several tactics
into a single command.
- For more sophisticated programming, Coq offers a small
built-in programming language called [Ltac] with primitives
that can examine and modify the proof state. The details are
a bit too complicated to get into here (and it is generally
agreed that [Ltac] is not the most beautiful part of Coq's
design!), but they can be found in the reference manual, and
there are many examples of [Ltac] definitions in the Coq
standard library that you can use as examples.
- There is also an OCaml API, which can be used to build tactics
that access Coq's internal structures at a lower level, but
this is seldom worth the trouble for ordinary Coq users.
The [Tactic Notation] mechanism is the easiest to come to grips with,
and it offers plenty of power for many purposes. Here's an example.
*)
Tactic Notation "simpl_and_try" tactic(c) :=
simpl;
try c.
(** This defines a new tactical called [simpl_and_try] which
takes one tactic [c] as an argument, and is defined to be
equivalent to the tactic [simpl; try c]. For example, writing
"[simpl_and_try reflexivity.]" in a proof would be the same as
writing "[simpl; try reflexivity.]" *)
(** The next subsection gives a more sophisticated use of this
feature... *)
(* ####################################################### *)
(** *** Bulletproofing Case Analyses *)
(** Being able to deal with most of the cases of an [induction]
or [destruct] all at the same time is very convenient, but it can
also be a little confusing. One problem that often comes up is
that _maintaining_ proofs written in this style can be difficult.
For example, suppose that, later, we extended the definition of
[aexp] with another constructor that also required a special
argument. The above proof might break because Coq generated the
subgoals for this constructor before the one for [APlus], so that,
at the point when we start working on the [APlus] case, Coq is
actually expecting the argument for a completely different
constructor. What we'd like is to get a sensible error message
saying "I was expecting the [AFoo] case at this point, but the
proof script is talking about [APlus]." Here's a nice trick (due
to Aaron Bohannon) that smoothly achieves this. *)
Tactic Notation "aexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ANum" | Case_aux c "APlus"
| Case_aux c "AMinus" | Case_aux c "AMult" ].
(** ([Case_aux] implements the common functionality of [Case],
[SCase], [SSCase], etc. For example, [Case "foo"] is defined as
[Case_aux Case "foo".) *)
(** For example, if [a] is a variable of type [aexp], then doing
aexp_cases (induction a) Case
will perform an induction on [a] (the same as if we had just typed
[induction a]) and _also_ add a [Case] tag to each subgoal
generated by the [induction], labeling which constructor it comes
from. For example, here is yet another proof of
[optimize_0plus_sound], using [aexp_cases]: *)
Theorem optimize_0plus_sound''': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
aexp_cases (induction a) Case;
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity);
try reflexivity.
(* At this point, there is already an ["APlus"] case name
in the context. The [Case "APlus"] here in the proof
text has the effect of a sanity check: if the "Case"
string in the context is anything _other_ than ["APlus"]
(for example, because we added a clause to the definition
of [aexp] and forgot to change the proof) we'll get a
helpful error at this point telling us that this is now
the wrong case. *)
Case "APlus".
aexp_cases (destruct a1) SCase;
try (simpl; simpl in IHa1;
rewrite IHa1; rewrite IHa2; reflexivity).
SCase "ANum". destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(** **** Exercise: 3 stars (optimize_0plus_b) *)
(** Since the [optimize_0plus] tranformation doesn't change the value
of [aexp]s, we should be able to apply it to all the [aexp]s that
appear in a [bexp] without changing the [bexp]'s value. Write a
function which performs that transformation on [bexp]s, and prove
it is sound. Use the tacticals we've just seen to make the proof
as elegant as possible. *)
Print bexp.
Print aexp.
Print aeval.
Print optimize_0plus.
Fixpoint optimize_0plus_b (b : bexp) : bexp :=
match b with
| BEq l r => BEq (optimize_0plus l) (optimize_0plus r)
| BLe l r => BLe (optimize_0plus l) (optimize_0plus r)
| BNot v => BNot (optimize_0plus_b v)
| BAnd l r => BAnd (optimize_0plus_b l)(optimize_0plus_b r)
| c => c
end.
Theorem optimize_0plus_b_sound : forall b,
beval (optimize_0plus_b b) = beval b.
Proof.
intros b.
induction b; simpl; try ( repeat (rewrite optimize_0plus_sound); reflexivity).
rewrite IHb. reflexivity.
rewrite IHb1, IHb2. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 4 stars, optional (optimizer) *)
(** _Design exercise_: The optimization implemented by our
[optimize_0plus] function is only one of many imaginable
optimizations on arithmetic and boolean expressions. Write a more
sophisticated optimizer and prove it correct.
*)
Print aexp.
Fixpoint optimize_mult_2_sum (e: aexp) : aexp :=
match e with
| AMult (ANum 2) r => APlus r r
| AMult l (ANum 2) => APlus l l
| o => o
end.
Lemma either_2_or_not: forall n, n = 2 \/ n <> 2.
Proof.
intros n.
case n.
right. auto.
intros.
case n0.
right. auto.
intros n1.
case n1.
left. reflexivity.
intros n2.
right.
unfold not.
intro H.
inversion H.
Qed.
Theorem optimize_mult_2_sum_sound: forall e, aeval( optimize_mult_2_sum e ) = aeval( e ).
Proof.
intros e.
induction e; try reflexivity.
destruct e1, e2; try reflexivity.
assert (n = 2 \/ n <> 2).
apply either_2_or_not.
assert (n0 = 2 \/ n0 <> 2).
apply either_2_or_not.
inversion H.
inversion H0.
rewrite H1, H2.
reflexivity.
rewrite H1.
simpl. rewrite plus_0_r. reflexivity.
inversion H0. rewrite H2.
simpl.
case n.
reflexivity.
intro n1.
case n1.
reflexivity.
intro n2.
case n2.
reflexivity.
intro n3.
simpl.
induction n.
reflexivity.
y.
compute.
simpl.
rewrite H2.
simpl.
assert ( aeval e1 = 2 \/ aeval e1 <> 2).
apply either_2_or_not.
assert ( aeval e2 = 2 \/ aeval e2 <> 2).
apply either_2_or_not.
replace (aeval (AMult e1 e2)) with (aeval e1 * aeval e2).
inversion H. inversion H0.
compute.
auto.
unfold optimize_mult_2_sum.
simpl.
(** [] *)
(* ####################################################### *)
(** ** The [omega] Tactic *)
(** The [omega] tactic implements a decision procedure for a subset of
first-order logic called _Presburger arithmetic_. It is based on
the Omega algorithm invented in 1992 by William Pugh.
If the goal is a universally quantified formula made out of
- numeric constants, addition ([+] and [S]), subtraction ([-]
and [pred]), and multiplication by constants (this is what
makes it Presburger arithmetic),
- equality ([=] and [<>]) and inequality ([<=]), and
- the logical connectives [/\], [\/], [~], and [->],
then invoking [omega] will either solve the goal or tell you that
it is actually false. *)
Example silly_presburger_example : forall m n o p,
m + n <= n + o /\ o + 3 = p + 3 ->
m <= p.
Proof.
intros. omega.
Qed.
(** Liebniz wrote, "It is unworthy of excellent men to lose
hours like slaves in the labor of calculation which could be
relegated to anyone else if machines were used." We recommend
using the omega tactic whenever possible. *)
(* ####################################################### *)
(** ** A Few More Handy Tactics *)
(** Finally, here are some miscellaneous tactics that you may find
convenient.
- [clear H]: Delete hypothesis [H] from the context.
- [subst x]: Find an assumption [x = e] or [e = x] in the
context, replace [x] with [e] throughout the context and
current goal, and clear the assumption.
- [subst]: Substitute away _all_ assumptions of the form [x = e]
or [e = x].
- [rename... into...]: Change the name of a hypothesis in the
proof context. For example, if the context includes a variable
named [x], then [rename x into y] will change all occurrences
of [x] to [y].
- [assumption]: Try to find a hypothesis [H] in the context that
exactly matches the goal; if one is found, behave just like
[apply H].
- [contradiction]: Try to find a hypothesis [H] in the current
context that is logically equivalent to [False]. If one is
found, solve the goal.
- [constructor]: Try to find a constructor [c] (from some
[Inductive] definition in the current environment) that can be
applied to solve the current goal. If one is found, behave
like [apply c]. *)
(** We'll see many examples of these in the proofs below. *)
(* ####################################################### *)
(** * Evaluation as a Relation *)
(** We have presented [aeval] and [beval] as functions defined by
[Fixpoints]. Another way to think about evaluation -- one that we
will see is often more flexible -- is as a _relation_ between
expressions and their values. This leads naturally to [Inductive]
definitions like the following one for arithmetic
expressions... *)
Module aevalR_first_try.
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n: nat),
aevalR (ANum n) n
| E_APlus : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
| E_AMinus: forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMinus e1 e2) (n1 - n2)
| E_AMult : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMult e1 e2) (n1 * n2).
(** As is often the case with relations, we'll find it
convenient to define infix notation for [aevalR]. We'll write [e
|| n] to mean that arithmetic expression [e] evaluates to value
[n]. (This notation is one place where the limitation to ASCII
symbols becomes a little bothersome. The standard notation for
the evaluation relation is a double down-arrow. We'll typeset it
like this in the HTML version of the notes and use a double
vertical bar as the closest approximation in [.v] files.) *)
Notation "e '||' n" := (aevalR e n) : type_scope.
End aevalR_first_try.
(** In fact, Coq provides a way to use this notation in the definition
of [aevalR] itself. This avoids situations where we're working on
a proof involving statements in the form [e || n] but we have to
refer back to a definition written using the form [aevalR e n].
We do this by first "reserving" the notation, then giving the
definition together with a declaration of what the notation
means. *)
Reserved Notation "e '||' n" (at level 50, left associativity).
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (APlus e1 e2) || (n1 + n2)
| E_AMinus : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (AMinus e1 e2) || (n1 - n2)
| E_AMult : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (AMult e1 e2) || (n1 * n2)
where "e '||' n" := (aevalR e n) : type_scope.
Tactic Notation "aevalR_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_ANum" | Case_aux c "E_APlus"
| Case_aux c "E_AMinus" | Case_aux c "E_AMult" ].
(* ####################################################### *)
(** ** Inference Rule Notation *)
(** In informal discussions, it is convenient write the rules for
[aevalR] and similar relations in the more readable graphical form
of _inference rules_, where the premises above the line justify
the conclusion below the line (we have already seen them in the
Prop chapter). *)
(** For example, the constructor [E_APlus]...
| E_APlus : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
...would be written like this as an inference rule:
e1 || n1
e2 || n2
-------------------- (E_APlus)
APlus e1 e2 || n1+n2
*)
(** Formally, there is nothing very deep about inference rules:
they are just implications. You can read the rule name on the
right as the name of the constructor and read each of the
linebreaks between the premises above the line and the line itself
as [->]. All the variables mentioned in the rule ([e1], [n1],
etc.) are implicitly bound by universal quantifiers at the
beginning. (Such variables are often called _metavariables_ to
distinguish them from the variables of the language we are
defining. At the moment, our arithmetic expressions don't include
variables, but we'll soon be adding them.) The whole collection
of rules is understood as being wrapped in an [Inductive]
declaration (informally, this is either elided or else indicated
by saying something like "Let [aevalR] be the smallest relation
closed under the following rules..."). *)
(** For example, [||] is the smallest relation closed under these
rules:
----------- (E_ANum)
ANum n || n
e1 || n1
e2 || n2
-------------------- (E_APlus)
APlus e1 e2 || n1+n2
e1 || n1
e2 || n2
--------------------- (E_AMinus)
AMinus e1 e2 || n1-n2
e1 || n1
e2 || n2
-------------------- (E_AMult)
AMult e1 e2 || n1*n2
*)
(* ####################################################### *)
(** ** Equivalence of the Definitions *)
(** It is straightforward to prove that the relational and functional
definitions of evaluation agree on all possible arithmetic
expressions... *)
Theorem aeval_iff_aevalR : forall a n,
(a || n) <-> aeval a = n.
Proof.
split.
Case "->".
intros H.
aevalR_cases (induction H) SCase; simpl.
SCase "E_ANum".
reflexivity.
SCase "E_APlus".
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
SCase "E_AMinus".
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
SCase "E_AMult".
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
Case "<-".
generalize dependent n.
aexp_cases (induction a) SCase;
simpl; intros; subst.
SCase "ANum".
apply E_ANum.
SCase "APlus".
apply E_APlus.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
SCase "AMinus".
apply E_AMinus.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
SCase "AMult".
apply E_AMult.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
Qed.
(** Note: if you're reading the HTML file, you'll see an empty square box instead
of a proof for this theorem.
You can click on this box to "unfold" the text to see the proof.
Click on the unfolded to text to "fold" it back up to a box. We'll be using
this style frequently from now on to help keep the HTML easier to read.
The full proofs always appear in the .v files. *)
(** We can make the proof quite a bit shorter by making more
use of tacticals... *)
Theorem aeval_iff_aevalR' : forall a n,
(a || n) <-> aeval a = n.
Proof.
(* WORKED IN CLASS *)
split.
Case "->".
intros H; induction H; subst; reflexivity.
Case "<-".
generalize dependent n.
induction a; simpl; intros; subst; constructor;
try apply IHa1; try apply IHa2; reflexivity.
Qed.
(** **** Exercise: 3 stars (bevalR) *)
(** Write a relation [bevalR] in the same style as
[aevalR], and prove that it is equivalent to [beval].*)
(*
Inductive bevalR:
(* FILL IN HERE *)
*)
(** [] *)
End AExp.
(* ####################################################### *)
(** ** Computational vs. Relational Definitions *)
(** For the definitions of evaluation for arithmetic and boolean
expressions, the choice of whether to use functional or relational
definitions is mainly a matter of taste. In general, Coq has
somewhat better support for working with relations. On the other
hand, in some sense function definitions carry more information,
because functions are necessarily deterministic and defined on all
arguments; for a relation we have to show these properties
explicitly if we need them. Functions also take advantage of Coq's
computations mechanism.
However, there are circumstances where relational definitions of
evaluation are preferable to functional ones. *)
Module aevalR_division.
(** For example, suppose that we wanted to extend the arithmetic
operations by considering also a division operation:*)
Inductive aexp : Type :=
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp
| ADiv : aexp -> aexp -> aexp. (* <--- new *)
(** Extending the definition of [aeval] to handle this new operation
would not be straightforward (what should we return as the result
of [ADiv (ANum 5) (ANum 0)]?). But extending [aevalR] is
straightforward. *)
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (APlus a1 a2) || (n1 + n2)
| E_AMinus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMinus a1 a2) || (n1 - n2)
| E_AMult : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMult a1 a2) || (n1 * n2)
| E_ADiv : forall (a1 a2: aexp) (n1 n2 n3: nat),
(a1 || n1) -> (a2 || n2) -> (mult n2 n3 = n1) -> (ADiv a1 a2) || n3
where "a '||' n" := (aevalR a n) : type_scope.
End aevalR_division.
Module aevalR_extended.
Inductive aexp : Type :=
| AAny : aexp (* <--- NEW *)
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
(** Again, extending [aeval] would be tricky (because evaluation is
_not_ a deterministic function from expressions to numbers), but
extending [aevalR] is no problem: *)
Inductive aevalR : aexp -> nat -> Prop :=
| E_Any : forall (n:nat),
AAny || n (* <--- new *)
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (APlus a1 a2) || (n1 + n2)
| E_AMinus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMinus a1 a2) || (n1 - n2)
| E_AMult : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMult a1 a2) || (n1 * n2)
where "a '||' n" := (aevalR a n) : type_scope.
End aevalR_extended.
(** * Expressions With Variables *)
(** Let's turn our attention back to defining Imp. The next thing we
need to do is to enrich our arithmetic and boolean expressions
with variables. To keep things simple, we'll assume that all
variables are global and that they only hold numbers. *)
(* ##################################################### *)
(** ** Identifiers *)
(** To begin, we'll need to formalize _identifiers_ such as program
variables. We could use strings for this -- or, in a real
compiler, fancier structures like pointers into a symbol table.
But for simplicity let's just use natural numbers as identifiers. *)
(** (We hide this section in a module because these definitions are
actually in [SfLib], but we want to repeat them here so that we
can explain them.) *)
Module Id.
(** We define a new inductive datatype [Id] so that we won't confuse
identifiers and numbers. We use [sumbool] to define a computable
equality operator on [Id]. *)
Inductive id : Type :=
Id : nat -> id.
Theorem eq_id_dec : forall id1 id2 : id, {id1 = id2} + {id1 <> id2}.
Proof.
intros id1 id2.
destruct id1 as [n1]. destruct id2 as [n2].
destruct (eq_nat_dec n1 n2) as [Heq | Hneq].
Case "n1 = n2".
left. rewrite Heq. reflexivity.
Case "n1 <> n2".
right. intros contra. inversion contra. apply Hneq. apply H0.
Defined.
(** The following lemmas will be useful for rewriting terms involving [eq_id_dec]. *)
Lemma eq_id : forall (T:Type) x (p q:T),
(if eq_id_dec x x then p else q) = p.
Proof.
intros.
destruct (eq_id_dec x x).
Case "x = x".
reflexivity.
Case "x <> x (impossible)".
apply ex_falso_quodlibet; apply n; reflexivity. Qed.
(** **** Exercise: 1 star, optional (neq_id) *)
Lemma neq_id : forall (T:Type) x y (p q:T), x <> y ->
(if eq_id_dec x y then p else q) = q.
Proof.
intros T x y p q H.
destruct x, y.
destruct (eq_id_dec (Id n) (Id n0)).
contradiction.
reflexivity.
Qed.
(** [] *)
End Id.
(* ####################################################### *)
(** ** States *)
(** A _state_ represents the current values of all the variables at
some point in the execution of a program. *)
(** For simplicity (to avoid dealing with partial functions), we
let the state be defined for _all_ variables, even though any
given program is only going to mention a finite number of them. *)
Definition state := id -> nat.
Definition empty_state : state :=
fun _ => 0.
Definition update (st : state) (x : id) (n : nat) : state :=
fun x' => if eq_id_dec x x' then n else st x'.
(** For proofs involving states, we'll need several simple properties
of [update]. *)
(** **** Exercise: 1 star (update_eq) *)
Theorem update_eq : forall n x st,
(update st x n) x = n.
Proof.
intros n x st.
unfold update.
apply eq_id.
Qed.
(** [] *)
(** **** Exercise: 1 star (update_neq) *)
Theorem update_neq : forall x2 x1 n st,
x2 <> x1 ->
(update st x2 n) x1 = (st x1).
Proof.
intros x2 x1 n st H.
unfold update.
apply neq_id.
apply H.
Qed.
(** [] *)
(** **** Exercise: 1 star (update_example) *)
(** Before starting to play with tactics, make sure you understand
exactly what the theorem is saying! *)
Theorem update_example : forall (n:nat),
(update empty_state (Id 2) n) (Id 3) = 0.
Proof.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 1 star (update_shadow) *)
Theorem update_shadow : forall n1 n2 x1 x2 (st : state),
(update (update st x2 n1) x2 n2) x1 = (update st x2 n2) x1.
Proof.
intros n1 n2 x1 x2 st.
unfold update.
destruct x1, x2.
destruct (eq_id_dec (Id n0) (Id n)); reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars (update_same) *)
Theorem update_same : forall n1 x1 x2 (st : state),
st x1 = n1 ->
(update st x1 n1) x2 = st x2.
Proof.
intros n1 x1 x2 st H.
unfold update.
destruct (eq_id_dec x1 x2).
rewrite <-e, H. reflexivity.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars (update_permute) *)
Theorem update_permute : forall n1 n2 x1 x2 x3 st,
x2 <> x1 ->
(update (update st x2 n1) x1 n2) x3 = (update (update st x1 n2) x2 n1) x3.
Proof.
intros n1 n2 x1 x2 x3 st H.
unfold update.
destruct (eq_id_dec x1 x3).
destruct (eq_id_dec x2 x3).
apply ex_falso_quodlibet.
apply H.
rewrite e0, e.
reflexivity.
reflexivity.
reflexivity.
Qed.
(** [] *)
(* ################################################### *)
(** ** Syntax *)
(** We can add variables to the arithmetic expressions we had before by
simply adding one more constructor: *)
Inductive aexp : Type :=
| ANum : nat -> aexp
| AId : id -> aexp (* <----- NEW *)
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
Tactic Notation "aexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ANum" | Case_aux c "AId" | Case_aux c "APlus"
| Case_aux c "AMinus" | Case_aux c "AMult" ].
(** Defining a few variable names as notational shorthands will make
examples easier to read: *)
Definition X : id := Id 0.
Definition Y : id := Id 1.
Definition Z : id := Id 2.
(** (This convention for naming program variables ([X], [Y],
[Z]) clashes a bit with our earlier use of uppercase letters for
types. Since we're not using polymorphism heavily in this part of
the course, this overloading should not cause confusion.) *)
(** The definition of [bexp]s is the same as before (using the new
[aexp]s): *)
Inductive bexp : Type :=
| BTrue : bexp
| BFalse : bexp
| BEq : aexp -> aexp -> bexp
| BLe : aexp -> aexp -> bexp
| BNot : bexp -> bexp
| BAnd : bexp -> bexp -> bexp.
Tactic Notation "bexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "BTrue" | Case_aux c "BFalse" | Case_aux c "BEq"
| Case_aux c "BLe" | Case_aux c "BNot" | Case_aux c "BAnd" ].
(* ################################################### *)
(** ** Evaluation *)
(** The arith and boolean evaluators can be extended to handle
variables in the obvious way: *)
Fixpoint aeval (st : state) (a : aexp) : nat :=
match a with
| ANum n => n
| AId x => st x (* <----- NEW *)
| APlus a1 a2 => (aeval st a1) + (aeval st a2)
| AMinus a1 a2 => (aeval st a1) - (aeval st a2)
| AMult a1 a2 => (aeval st a1) * (aeval st a2)
end.
Fixpoint beval (st : state) (b : bexp) : bool :=
match b with
| BTrue => true
| BFalse => false
| BEq a1 a2 => beq_nat (aeval st a1) (aeval st a2)
| BLe a1 a2 => ble_nat (aeval st a1) (aeval st a2)
| BNot b1 => negb (beval st b1)
| BAnd b1 b2 => andb (beval st b1) (beval st b2)
end.
Example aexp1 :
aeval (update empty_state X 5)
(APlus (ANum 3) (AMult (AId X) (ANum 2)))
= 13.
Proof. reflexivity. Qed.
Example bexp1 :
beval (update empty_state X 5)
(BAnd BTrue (BNot (BLe (AId X) (ANum 4))))
= true.
Proof. reflexivity. Qed.
(* ####################################################### *)
(** * Commands *)
(** Now we are ready define the syntax and behavior of Imp
_commands_ (often called _statements_). *)
(* ################################################### *)
(** ** Syntax *)
(** Informally, commands [c] are described by the following BNF
grammar:
c ::= SKIP
| x ::= a
| c ; c
| WHILE b DO c END
| IFB b THEN c ELSE c FI
For example, here's the factorial function in Imp.
Z ::= X;
Y ::= 1;
WHILE not (Z = 0) DO
Y ::= Y * Z;
Z ::= Z - 1
END
When this command terminates, the variable [Y] will contain the
factorial of the initial value of [X].
*)
(** Here is the formal definition of the syntax of commands: *)
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";;"
| Case_aux c "IFB" | Case_aux c "WHILE" ].
(** As usual, we can use a few [Notation] declarations to make things
more readable. We need to be a bit careful to avoid conflicts
with Coq's built-in notations, so we'll keep this light -- in
particular, we won't introduce any notations for [aexps] and
[bexps] to avoid confusion with the numerical and boolean
operators we've already defined. We use the keyword [IFB] for
conditionals instead of [IF], for similar reasons. *)
Notation "'SKIP'" :=
CSkip.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' c1 'THEN' c2 'ELSE' c3 'FI'" :=
(CIf c1 c2 c3) (at level 80, right associativity).
(** For example, here is the factorial function again, written as a
formal definition to Coq: *)
Definition fact_in_coq : com :=
Z ::= AId X;;
Y ::= ANum 1;;
WHILE BNot (BEq (AId Z) (ANum 0)) DO
Y ::= AMult (AId Y) (AId Z);;
Z ::= AMinus (AId Z) (ANum 1)
END.
(* ####################################################### *)
(** ** Examples *)
(** Assignment: *)
Definition plus2 : com :=
X ::= (APlus (AId X) (ANum 2)).
Definition XtimesYinZ : com :=
Z ::= (AMult (AId X) (AId Y)).
Definition subtract_slowly_body : com :=
Z ::= AMinus (AId Z) (ANum 1) ;;
X ::= AMinus (AId X) (ANum 1).
(** Loops: *)
Definition subtract_slowly : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
subtract_slowly_body
END.
Definition subtract_3_from_5_slowly : com :=
X ::= ANum 3 ;;
Z ::= ANum 5 ;;
subtract_slowly.
(** An infinite loop: *)
Definition loop : com :=
WHILE BTrue DO
SKIP
END.
(* ################################################################ *)
(** * Evaluation *)
(** Next we need to define what it means to evaluate an Imp command.
The fact that [WHILE] loops don't necessarily terminate makes defining
an evaluation function tricky... *)
(* #################################### *)
(** ** Evaluation as a Function (Failed Attempt) *)
(** Here's an attempt at defining an evaluation function for commands,
omitting the [WHILE] case. *)
Fixpoint ceval_fun_no_while (st : state) (c : com) : state :=
match c with
| SKIP =>
st
| x ::= a1 =>
update st x (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_fun_no_while st c1 in
ceval_fun_no_while st' c2
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_fun_no_while st c1
else ceval_fun_no_while st c2
| WHILE b DO c END =>
st (* bogus *)
end.
(** In a traditional functional programming language like ML or
Haskell we could write the [WHILE] case as follows:
<<
Fixpoint ceval_fun (st : state) (c : com) : state :=
match c with
...
| WHILE b DO c END =>
if (beval st b1)
then ceval_fun st (c1; WHILE b DO c END)
else st
end.
>>
Coq doesn't accept such a definition ("Error: Cannot guess
decreasing argument of fix") because the function we want to
define is not guaranteed to terminate. Indeed, it doesn't always
terminate: for example, the full version of the [ceval_fun]
function applied to the [loop] program above would never
terminate. Since Coq is not just a functional programming
language, but also a consistent logic, any potentially
non-terminating function needs to be rejected. Here is
an (invalid!) Coq program showing what would go wrong if Coq
allowed non-terminating recursive functions:
<<
Fixpoint loop_false (n : nat) : False := loop_false n.
>>
That is, propositions like [False] would become provable
(e.g. [loop_false 0] would be a proof of [False]), which
would be a disaster for Coq's logical consistency.
Thus, because it doesn't terminate on all inputs, the full version
of [ceval_fun] cannot be written in Coq -- at least not without
additional tricks (see chapter [ImpCEvalFun] if curious). *)
(* #################################### *)
(** ** Evaluation as a Relation *)
(** Here's a better way: we define [ceval] as a _relation_ rather than
a _function_ -- i.e., we define it in [Prop] instead of [Type], as
we did for [aevalR] above. *)
(** This is an important change. Besides freeing us from the awkward
workarounds that would be needed to define evaluation as a
function, it gives us a lot more flexibility in the definition.
For example, if we added concurrency features to the language,
we'd want the definition of evaluation to be non-deterministic --
i.e., not only would it not be total, it would not even be a
partial function! *)
(** We'll use the notation [c / st || st'] for our [ceval] relation:
[c / st || st'] means that executing program [c] in a starting
state [st] results in an ending state [st']. This can be
pronounced "[c] takes state [st] to [st']".
---------------- (E_Skip)
SKIP / st || st
aeval st a1 = n
-------------------------------- (E_Ass)
x := a1 / st || (update st x n)
c1 / st || st'
c2 / st' || st''
------------------- (E_Seq)
c1;;c2 / st || st''
beval st b1 = true
c1 / st || st'
------------------------------------- (E_IfTrue)
IF b1 THEN c1 ELSE c2 FI / st || st'
beval st b1 = false
c2 / st || st'
------------------------------------- (E_IfFalse)
IF b1 THEN c1 ELSE c2 FI / st || st'
beval st b1 = false
------------------------------ (E_WhileEnd)
WHILE b DO c END / st || st
beval st b1 = true
c / st || st'
WHILE b DO c END / st' || st''
--------------------------------- (E_WhileLoop)
WHILE b DO c END / st || st''
*)
(** Here is the formal definition. (Make sure you understand
how it corresponds to the inference rules.) *)
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st,
SKIP / st || st
| E_Ass : forall st a1 n x,
aeval st a1 = n ->
(x ::= a1) / st || (update st x n)
| E_Seq : forall c1 c2 st st' st'',
c1 / st || st' ->
c2 / st' || st'' ->
(c1 ;; c2) / st || st''
| E_IfTrue : forall st st' b c1 c2,
beval st b = true ->
c1 / st || st' ->
(IFB b THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall st st' b c1 c2,
beval st b = false ->
c2 / st || st' ->
(IFB b THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall b st c,
beval st b = false ->
(WHILE b DO c END) / st || st
| E_WhileLoop : forall st st' st'' b c,
beval st b = true ->
c / st || st' ->
(WHILE b DO c END) / st' || st'' ->
(WHILE b DO c END) / st || st''
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop" ].
(** The cost of defining evaluation as a relation instead of a
function is that we now need to construct _proofs_ that some
program evaluates to some result state, rather than just letting
Coq's computation mechanism do it for us. *)
Example ceval_example1:
(X ::= ANum 2;;
IFB BLe (AId X) (ANum 1)
THEN Y ::= ANum 3
ELSE Z ::= ANum 4
FI)
/ empty_state
|| (update (update empty_state X 2) Z 4).
Proof.
(* We must supply the intermediate state *)
apply E_Seq with (update empty_state X 2).
Case "assignment command".
apply E_Ass. reflexivity.
Case "if command".
apply E_IfFalse.
reflexivity.
apply E_Ass. reflexivity. Qed.
(** **** Exercise: 2 stars (ceval_example2) *)
Example ceval_example2:
(X ::= ANum 0;; Y ::= ANum 1;; Z ::= ANum 2) / empty_state ||
(update (update (update empty_state X 0) Y 1) Z 2).
Proof.
apply E_Seq with (update empty_state X 0).
apply E_Ass.
reflexivity.
apply E_Seq with (update (update empty_state X 0) Y 1).
apply E_Ass. reflexivity.
apply E_Ass. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (pup_to_n) *)
(** Write an Imp program that sums the numbers from [1] to
[X] (inclusive: [1 + 2 + ... + X]) in the variable [Y].
Prove that this program executes as intended for X = 2
(this latter part is trickier than you might expect). *)
Definition pup_to_n : com := Admitted.
Theorem pup_to_2_ceval :
pup_to_n / (update empty_state X 2) ||
update (update (update (update (update (update empty_state
X 2) Y 0) Y 2) X 1) Y 3) X 0.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ####################################################### *)
(** ** Determinism of Evaluation *)
(** Changing from a computational to a relational definition of
evaluation is a good move because it allows us to escape from the
artificial requirement (imposed by Coq's restrictions on
[Fixpoint] definitions) that evaluation should be a total
function. But it also raises a question: Is the second definition
of evaluation actually a partial function? That is, is it
possible that, beginning from the same state [st], we could
evaluate some command [c] in different ways to reach two different
output states [st'] and [st'']?
In fact, this cannot happen: [ceval] is a partial function.
Here's the proof: *)
Theorem ceval_deterministic: forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2.
ceval_cases (induction E1) Case;
intros st2 E2; inversion E2; subst.
Case "E_Skip". reflexivity.
Case "E_Ass". reflexivity.
Case "E_Seq".
assert (st' = st'0) as EQ1.
SCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption.
Case "E_IfTrue".
SCase "b1 evaluates to true".
apply IHE1. assumption.
SCase "b1 evaluates to false (contradiction)".
rewrite H in H5. inversion H5.
Case "E_IfFalse".
SCase "b1 evaluates to true (contradiction)".
rewrite H in H5. inversion H5.
SCase "b1 evaluates to false".
apply IHE1. assumption.
Case "E_WhileEnd".
SCase "b1 evaluates to false".
reflexivity.
SCase "b1 evaluates to true (contradiction)".
rewrite H in H2. inversion H2.
Case "E_WhileLoop".
SCase "b1 evaluates to false (contradiction)".
rewrite H in H4. inversion H4.
SCase "b1 evaluates to true".
assert (st' = st'0) as EQ1.
SSCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption. Qed.
(* ####################################################### *)
(** * Reasoning About Imp Programs *)
(** We'll get much deeper into systematic techniques for reasoning
about Imp programs in the following chapters, but we can do quite
a bit just working with the bare definitions. *)
(* This section explores some examples. *)
Theorem plus2_spec : forall st n st',
st X = n ->
plus2 / st || st' ->
st' X = n + 2.
Proof.
intros st n st' HX Heval.
(* Inverting Heval essentially forces Coq to expand one
step of the ceval computation - in this case revealing
that st' must be st extended with the new value of X,
since plus2 is an assignment *)
inversion Heval. subst. clear Heval. simpl.
apply update_eq. Qed.
(** **** Exercise: 3 stars (XtimesYinZ_spec) *)
(** State and prove a specification of [XtimesYinZ]. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars (loop_never_stops) *)
Theorem loop_never_stops : forall st st',
~(loop / st || st').
Proof.
intros st st' contra. unfold loop in contra.
remember (WHILE BTrue DO SKIP END) as loopdef eqn:Heqloopdef.
(* Proceed by induction on the assumed derivation showing that
[loopdef] terminates. Most of the cases are immediately
contradictory (and so can be solved in one step with
[inversion]). *)
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (no_whilesR) *)
(** Consider the definition of the [no_whiles] property below: *)
Fixpoint no_whiles (c : com) : bool :=
match c with
| SKIP => true
| _ ::= _ => true
| c1 ;; c2 => andb (no_whiles c1) (no_whiles c2)
| IFB _ THEN ct ELSE cf FI => andb (no_whiles ct) (no_whiles cf)
| WHILE _ DO _ END => false
end.
(** This property yields [true] just on programs that
have no while loops. Using [Inductive], write a property
[no_whilesR] such that [no_whilesR c] is provable exactly when [c]
is a program with no while loops. Then prove its equivalence
with [no_whiles]. *)
Inductive no_whilesR: com -> Prop :=
(* FILL IN HERE *)
.
Theorem no_whiles_eqv:
forall c, no_whiles c = true <-> no_whilesR c.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars (no_whiles_terminating) *)
(** Imp programs that don't involve while loops always terminate.
State and prove a theorem that says this. *)
(** (Use either [no_whiles] or [no_whilesR], as you prefer.) *)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars (stack_compiler) *)
(** HP Calculators, programming languages like Forth and Postscript,
and abstract machines like the Java Virtual Machine all evaluate
arithmetic expressions using a stack. For instance, the expression
<<
(2*3)+(3*(4-2))
>>
would be entered as
<<
2 3 * 3 4 2 - * +
>>
and evaluated like this:
<<
[] | 2 3 * 3 4 2 - * +
[2] | 3 * 3 4 2 - * +
[3, 2] | * 3 4 2 - * +
[6] | 3 4 2 - * +
[3, 6] | 4 2 - * +
[4, 3, 6] | 2 - * +
[2, 4, 3, 6] | - * +
[2, 3, 6] | * +
[6, 6] | +
[12] |
>>
The task of this exercise is to write a small compiler that
translates [aexp]s into stack machine instructions.
The instruction set for our stack language will consist of the
following instructions:
- [SPush n]: Push the number [n] on the stack.
- [SLoad x]: Load the identifier [x] from the store and push it
on the stack
- [SPlus]: Pop the two top numbers from the stack, add them, and
push the result onto the stack.
- [SMinus]: Similar, but subtract.
- [SMult]: Similar, but multiply. *)
Inductive sinstr : Type :=
| SPush : nat -> sinstr
| SLoad : id -> sinstr
| SPlus : sinstr
| SMinus : sinstr
| SMult : sinstr.
(** Write a function to evaluate programs in the stack language. It
takes as input a state, a stack represented as a list of
numbers (top stack item is the head of the list), and a program
represented as a list of instructions, and returns the stack after
executing the program. Test your function on the examples below.
Note that the specification leaves unspecified what to do when
encountering an [SPlus], [SMinus], or [SMult] instruction if the
stack contains less than two elements. In a sense, it is
immaterial what we do, since our compiler will never emit such a
malformed program. *)
Fixpoint s_execute (st : state) (stack : list nat)
(prog : list sinstr)
: list nat :=
(* FILL IN HERE *) admit.
Example s_execute1 :
s_execute empty_state []
[SPush 5; SPush 3; SPush 1; SMinus]
= [2; 5].
(* FILL IN HERE *) Admitted.
Example s_execute2 :
s_execute (update empty_state X 3) [3;4]
[SPush 4; SLoad X; SMult; SPlus]
= [15; 4].
(* FILL IN HERE *) Admitted.
(** Next, write a function which compiles an [aexp] into a stack
machine program. The effect of running the program should be the
same as pushing the value of the expression on the stack. *)
Fixpoint s_compile (e : aexp) : list sinstr :=
(* FILL IN HERE *) admit.
(** After you've defined [s_compile], uncomment the following to test
that it works. *)
(*
Example s_compile1 :
s_compile (AMinus (AId X) (AMult (ANum 2) (AId Y)))
= [SLoad X; SPush 2; SLoad Y; SMult; SMinus].
Proof. reflexivity. Qed.
*)
(** [] *)
(** **** Exercise: 3 stars, advanced (stack_compiler_correct) *)
(** The task of this exercise is to prove the correctness of the
calculator implemented in the previous exercise. Remember that
the specification left unspecified what to do when encountering an
[SPlus], [SMinus], or [SMult] instruction if the stack contains
less than two elements. (In order to make your correctness proof
easier you may find it useful to go back and change your
implementation!)
Prove the following theorem, stating that the [compile] function
behaves correctly. You will need to start by stating a more
general lemma to get a usable induction hypothesis; the main
theorem will then be a simple corollary of this lemma. *)
Theorem s_compile_correct : forall (st : state) (e : aexp),
s_execute st [] (s_compile e) = [ aeval st e ].
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 5 stars, advanced (break_imp) *)
Module BreakImp.
(** Imperative languages such as C or Java often have a [break] or
similar statement for interrupting the execution of loops. In this
exercise we will consider how to add [break] to Imp.
First, we need to enrich the language of commands with an
additional case. *)
Inductive com : Type :=
| CSkip : com
| CBreak : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "BREAK" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" ].
Notation "'SKIP'" :=
CSkip.
Notation "'BREAK'" :=
CBreak.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' c1 'THEN' c2 'ELSE' c3 'FI'" :=
(CIf c1 c2 c3) (at level 80, right associativity).
(** Next, we need to define the behavior of [BREAK]. Informally,
whenever [BREAK] is executed in a sequence of commands, it stops
the execution of that sequence and signals that the innermost
enclosing loop (if any) should terminate. If there aren't any
enclosing loops, then the whole program simply terminates. The
final state should be the same as the one in which the [BREAK]
statement was executed.
One important point is what to do when there are multiple loops
enclosing a given [BREAK]. In those cases, [BREAK] should only
terminate the _innermost_ loop where it occurs. Thus, after
executing the following piece of code...
X ::= 0;
Y ::= 1;
WHILE 0 <> Y DO
WHILE TRUE DO
BREAK
END;
X ::= 1;
Y ::= Y - 1
END
... the value of [X] should be [1], and not [0].
One way of expressing this behavior is to add another parameter to
the evaluation relation that specifies whether evaluation of a
command executes a [BREAK] statement: *)
Inductive status : Type :=
| SContinue : status
| SBreak : status.
Reserved Notation "c1 '/' st '||' s '/' st'"
(at level 40, st, s at level 39).
(** Intuitively, [c / st || s / st'] means that, if [c] is started in
state [st], then it terminates in state [st'] and either signals
that any surrounding loop (or the whole program) should exit
immediately ([s = SBreak]) or that execution should continue
normally ([s = SContinue]).
The definition of the "[c / st || s / st']" relation is very
similar to the one we gave above for the regular evaluation
relation ([c / st || s / st']) -- we just need to handle the
termination signals appropriately:
- If the command is [SKIP], then the state doesn't change, and
execution of any enclosing loop can continue normally.
- If the command is [BREAK], the state stays unchanged, but we
signal a [SBreak].
- If the command is an assignment, then we update the binding for
that variable in the state accordingly and signal that execution
can continue normally.
- If the command is of the form [IF b THEN c1 ELSE c2 FI], then
the state is updated as in the original semantics of Imp, except
that we also propagate the signal from the execution of
whichever branch was taken.
- If the command is a sequence [c1 ; c2], we first execute
[c1]. If this yields a [SBreak], we skip the execution of [c2]
and propagate the [SBreak] signal to the surrounding context;
the resulting state should be the same as the one obtained by
executing [c1] alone. Otherwise, we execute [c2] on the state
obtained after executing [c1], and propagate the signal that was
generated there.
- Finally, for a loop of the form [WHILE b DO c END], the
semantics is almost the same as before. The only difference is
that, when [b] evaluates to true, we execute [c] and check the
signal that it raises. If that signal is [SContinue], then the
execution proceeds as in the original semantics. Otherwise, we
stop the execution of the loop, and the resulting state is the
same as the one resulting from the execution of the current
iteration. In either case, since [BREAK] only terminates the
innermost loop, [WHILE] signals [SContinue]. *)
(** Based on the above description, complete the definition of the
[ceval] relation. *)
Inductive ceval : com -> state -> status -> state -> Prop :=
| E_Skip : forall st,
CSkip / st || SContinue / st
(* FILL IN HERE *)
where "c1 '/' st '||' s '/' st'" := (ceval c1 st s st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip"
(* FILL IN HERE *)
].
(** Now the following properties of your definition of [ceval]: *)
Theorem break_ignore : forall c st st' s,
(BREAK; c) / st || s / st' ->
st = st'.
Proof.
(* FILL IN HERE *) Admitted.
Theorem while_continue : forall b c st st' s,
(WHILE b DO c END) / st || s / st' ->
s = SContinue.
Proof.
(* FILL IN HERE *) Admitted.
Theorem while_stops_on_break : forall b c st st',
beval st b = true ->
c / st || SBreak / st' ->
(WHILE b DO c END) / st || SContinue / st'.
Proof.
(* FILL IN HERE *) Admitted.
Theorem while_break_true : forall b c st st',
(WHILE b DO c END) / st || SContinue / st' ->
beval st' b = true ->
exists st'', c / st'' || SBreak / st'.
Proof.
(* FILL IN HERE *) Admitted.
Theorem ceval_deterministic: forall (c:com) st st1 st2 s1 s2,
c / st || s1 / st1 ->
c / st || s2 / st2 ->
st1 = st2 /\ s1 = s2.
Proof.
(* FILL IN HERE *) Admitted.
End BreakImp.
(** [] *)
(** **** Exercise: 3 stars, optional (short_circuit) *)
(** Most modern programming languages use a "short-circuit" evaluation
rule for boolean [and]: to evaluate [BAnd b1 b2], first evaluate
[b1]. If it evaluates to [false], then the entire [BAnd]
expression evaluates to [false] immediately, without evaluating
[b2]. Otherwise, [b2] is evaluated to determine the result of the
[BAnd] expression.
Write an alternate version of [beval] that performs short-circuit
evaluation of [BAnd] in this manner, and prove that it is
equivalent to [beval]. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 4 stars, optional (add_for_loop) *)
(** Add C-style [for] loops to the language of commands, update the
[ceval] definition to define the semantics of [for] loops, and add
cases for [for] loops as needed so that all the proofs in this file
are accepted by Coq.
A [for] loop should be parameterized by (a) a statement executed
initially, (b) a test that is run on each iteration of the loop to
determine whether the loop should continue, (c) a statement
executed at the end of each loop iteration, and (d) a statement
that makes up the body of the loop. (You don't need to worry
about making up a concrete Notation for [for] loops, but feel free
to play with this too if you like.) *)
(* FILL IN HERE *)
(** [] *)
(* <$Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
|
(** * ImpCEvalFun: Evaluation Function for Imp *)
(* $Date: 2013-07-01 18:48:47 -0400 (Mon, 01 Jul 2013) $ *)
(* #################################### *)
(** * Evaluation Function *)
Require Import Imp.
(** Here's a first try at an evaluation function for commands,
omitting [WHILE]. *)
Fixpoint ceval_step1 (st : state) (c : com) : state :=
match c with
| SKIP =>
st
| l ::= a1 =>
update st l (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_step1 st c1 in
ceval_step1 st' c2
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step1 st c1
else ceval_step1 st c2
| WHILE b1 DO c1 END =>
st (* bogus *)
end.
(** In a traditional functional programming language like ML or
Haskell we could write the WHILE case as follows:
<<
| WHILE b1 DO c1 END =>
if (beval st b1)
then ceval_step1 st (c1;; WHILE b1 DO c1 END)
else st
>>
Coq doesn't accept such a definition ([Error: Cannot guess
decreasing argument of fix]) because the function we want to
define is not guaranteed to terminate. Indeed, the changed
[ceval_step1] function applied to the [loop] program from [Imp.v] would
never terminate. Since Coq is not just a functional programming
language, but also a consistent logic, any potentially
non-terminating function needs to be rejected. Here is an
invalid(!) Coq program showing what would go wrong if Coq allowed
non-terminating recursive functions:
<<
Fixpoint loop_false (n : nat) : False := loop_false n.
>>
That is, propositions like [False] would become
provable (e.g. [loop_false 0] would be a proof of [False]), which
would be a disaster for Coq's logical consistency.
Thus, because it doesn't terminate on all inputs, the full version
of [ceval_step1] cannot be written in Coq -- at least not
without one additional trick... *)
(** Second try, using an extra numeric argument as a "step index" to
ensure that evaluation always terminates. *)
Fixpoint ceval_step2 (st : state) (c : com) (i : nat) : state :=
match i with
| O => empty_state
| S i' =>
match c with
| SKIP =>
st
| l ::= a1 =>
update st l (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_step2 st c1 i' in
ceval_step2 st' c2 i'
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step2 st c1 i'
else ceval_step2 st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then let st' := ceval_step2 st c1 i' in
ceval_step2 st' c i'
else st
end
end.
(** _Note_: It is tempting to think that the index [i] here is
counting the "number of steps of evaluation." But if you look
closely you'll see that this is not the case: for example, in the
rule for sequencing, the same [i] is passed to both recursive
calls. Understanding the exact way that [i] is treated will be
important in the proof of [ceval__ceval_step], which is given as
an exercise below. *)
(** Third try, returning an [option state] instead of just a [state]
so that we can distinguish between normal and abnormal
termination. *)
Fixpoint ceval_step3 (st : state) (c : com) (i : nat)
: option state :=
match i with
| O => None
| S i' =>
match c with
| SKIP =>
Some st
| l ::= a1 =>
Some (update st l (aeval st a1))
| c1 ;; c2 =>
match (ceval_step3 st c1 i') with
| Some st' => ceval_step3 st' c2 i'
| None => None
end
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step3 st c1 i'
else ceval_step3 st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then match (ceval_step3 st c1 i') with
| Some st' => ceval_step3 st' c i'
| None => None
end
else Some st
end
end.
(** We can improve the readability of this definition by introducing a
bit of auxiliary notation to hide the "plumbing" involved in
repeatedly matching against optional states. *)
Notation "'LETOPT' x <== e1 'IN' e2"
:= (match e1 with
| Some x => e2
| None => None
end)
(right associativity, at level 60).
Fixpoint ceval_step (st : state) (c : com) (i : nat)
: option state :=
match i with
| O => None
| S i' =>
match c with
| SKIP =>
Some st
| l ::= a1 =>
Some (update st l (aeval st a1))
| c1 ;; c2 =>
LETOPT st' <== ceval_step st c1 i' IN
ceval_step st' c2 i'
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step st c1 i'
else ceval_step st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then LETOPT st' <== ceval_step st c1 i' IN
ceval_step st' c i'
else Some st
end
end.
Definition test_ceval (st:state) (c:com) :=
match ceval_step st c 500 with
| None => None
| Some st => Some (st X, st Y, st Z)
end.
(* Eval compute in
(test_ceval empty_state
(X ::= ANum 2;;
IFB BLe (AId X) (ANum 1)
THEN Y ::= ANum 3
ELSE Z ::= ANum 4
FI)).
====>
Some (2, 0, 4) *)
(** **** Exercise: 2 stars (pup_to_n) *)
(** Write an Imp program that sums the numbers from [1] to
[X] (inclusive: [1 + 2 + ... + X]) in the variable [Y]. Make sure
your solution satisfies the test that follows. *)
Definition pup_to_n : com :=
(* FILL IN HERE *) admit.
(*
Example pup_to_n_1 :
test_ceval (update empty_state X 5) pup_to_n
= Some (0, 15, 0).
Proof. reflexivity. Qed.
*)
(** [] *)
(** **** Exercise: 2 stars, optional (peven) *)
(** Write a [While] program that sets [Z] to [0] if [X] is even and
sets [Z] to [1] otherwise. Use [ceval_test] to test your
program. *)
(* FILL IN HERE *)
(** [] *)
(* ################################################################ *)
(** * Equivalence of Relational and Step-Indexed Evaluation *)
(** As with arithmetic and boolean expressions, we'd hope that
the two alternative definitions of evaluation actually boil down
to the same thing. This section shows that this is the case.
Make sure you understand the statements of the theorems and can
follow the structure of the proofs. *)
Theorem ceval_step__ceval: forall c st st',
(exists i, ceval_step st c i = Some st') ->
c / st || st'.
Proof.
intros c st st' H.
inversion H as [i E].
clear H.
generalize dependent st'.
generalize dependent st.
generalize dependent c.
induction i as [| i' ].
Case "i = 0 -- contradictory".
intros c st st' H. inversion H.
Case "i = S i'".
intros c st st' H.
com_cases (destruct c) SCase;
simpl in H; inversion H; subst; clear H.
SCase "SKIP". apply E_Skip.
SCase "::=". apply E_Ass. reflexivity.
SCase ";;".
destruct (ceval_step st c1 i') eqn:Heqr1.
SSCase "Evaluation of r1 terminates normally".
apply E_Seq with s.
apply IHi'. rewrite Heqr1. reflexivity.
apply IHi'. simpl in H1. assumption.
SSCase "Otherwise -- contradiction".
inversion H1.
SCase "IFB".
destruct (beval st b) eqn:Heqr.
SSCase "r = true".
apply E_IfTrue. rewrite Heqr. reflexivity.
apply IHi'. assumption.
SSCase "r = false".
apply E_IfFalse. rewrite Heqr. reflexivity.
apply IHi'. assumption.
SCase "WHILE". destruct (beval st b) eqn :Heqr.
SSCase "r = true".
destruct (ceval_step st c i') eqn:Heqr1.
SSSCase "r1 = Some s".
apply E_WhileLoop with s. rewrite Heqr. reflexivity.
apply IHi'. rewrite Heqr1. reflexivity.
apply IHi'. simpl in H1. assumption.
SSSCase "r1 = None".
inversion H1.
SSCase "r = false".
inversion H1.
apply E_WhileEnd.
rewrite <- Heqr. subst. reflexivity. Qed.
(** **** Exercise: 4 stars (ceval_step__ceval_inf) *)
(** Write an informal proof of [ceval_step__ceval], following the
usual template. (The template for case analysis on an inductively
defined value should look the same as for induction, except that
there is no induction hypothesis.) Make your proof communicate
the main ideas to a human reader; do not simply transcribe the
steps of the formal proof.
(* FILL IN HERE *)
[]
*)
Theorem ceval_step_more: forall i1 i2 st st' c,
i1 <= i2 ->
ceval_step st c i1 = Some st' ->
ceval_step st c i2 = Some st'.
Proof.
induction i1 as [|i1']; intros i2 st st' c Hle Hceval.
Case "i1 = 0".
simpl in Hceval. inversion Hceval.
Case "i1 = S i1'".
destruct i2 as [|i2']. inversion Hle.
assert (Hle': i1' <= i2') by omega.
com_cases (destruct c) SCase.
SCase "SKIP".
simpl in Hceval. inversion Hceval.
reflexivity.
SCase "::=".
simpl in Hceval. inversion Hceval.
reflexivity.
SCase ";;".
simpl in Hceval. simpl.
destruct (ceval_step st c1 i1') eqn:Heqst1'o.
SSCase "st1'o = Some".
apply (IHi1' i2') in Heqst1'o; try assumption.
rewrite Heqst1'o. simpl. simpl in Hceval.
apply (IHi1' i2') in Hceval; try assumption.
SSCase "st1'o = None".
inversion Hceval.
SCase "IFB".
simpl in Hceval. simpl.
destruct (beval st b); apply (IHi1' i2') in Hceval; assumption.
SCase "WHILE".
simpl in Hceval. simpl.
destruct (beval st b); try assumption.
destruct (ceval_step st c i1') eqn: Heqst1'o.
SSCase "st1'o = Some".
apply (IHi1' i2') in Heqst1'o; try assumption.
rewrite -> Heqst1'o. simpl. simpl in Hceval.
apply (IHi1' i2') in Hceval; try assumption.
SSCase "i1'o = None".
simpl in Hceval. inversion Hceval. Qed.
(** **** Exercise: 3 stars (ceval__ceval_step) *)
(** Finish the following proof. You'll need [ceval_step_more] in a
few places, as well as some basic facts about [<=] and [plus]. *)
Theorem ceval__ceval_step: forall c st st',
c / st || st' ->
exists i, ceval_step st c i = Some st'.
Proof.
intros c st st' Hce.
ceval_cases (induction Hce) Case.
(* FILL IN HERE *) Admitted.
(** [] *)
Theorem ceval_and_ceval_step_coincide: forall c st st',
c / st || st'
<-> exists i, ceval_step st c i = Some st'.
Proof.
intros c st st'.
split. apply ceval__ceval_step. apply ceval_step__ceval.
Qed.
(* ####################################################### *)
(** * Determinism of Evaluation (Simpler Proof) *)
(** Here's a slicker proof showing that the evaluation relation is
deterministic, using the fact that the relational and step-indexed
definition of evaluation are the same. *)
Theorem ceval_deterministic' : forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 He1 He2.
apply ceval__ceval_step in He1.
apply ceval__ceval_step in He2.
inversion He1 as [i1 E1].
inversion He2 as [i2 E2].
apply ceval_step_more with (i2 := i1 + i2) in E1.
apply ceval_step_more with (i2 := i1 + i2) in E2.
rewrite E1 in E2. inversion E2. reflexivity.
omega. omega. Qed.
|
(** * Priqueue: Priority Queues *)
(** A _priority queue_ is an abstract data type with the following operations:
- [ empty: priqueue ]
- [ insert: key -> priqueue -> priqueue ]
- [ delete_max: priqueue -> option (key * priqueue) ]
The idea is that you can find (and remove) the highest-priority element.
Priority queues have applications in:
- Discrete-event simulations: The highest-priority event is the
one whose scheduled time is the earliest. Simulating one event
causes new events to be scheduled in the future.
- Sorting: _heap sort_ puts all the elements in a priority queue,
then removes them one at a time.
- Computational geometry: algorithms such as _convex hull_ use
priority queues.
- Graph algorithms: Dijkstra's algorithm for finding the shortest path
uses a priority queue.
We will be considering _mergeable_ priority queues, with one
additional operator:
- [ merge: priqueue -> priqueue -> priqueue ]
The classic data structure for priority queues is the "heap", a balanced
binary tree in which the the key at any node is _bigger_ than all the
keys in nodes below it. With heaps, [empty] is constant time,
[insert] and [delete_max] are logN time. But [merge] takes NlogN
time, as one must take all the elements out of one queue and
insert them into the other queue.
Another way to do priority queues is by _balanced binary search trees_
(such as red-black trees); again, [empty] is constant time,
[insert] and [delete_max] are logN time, and [merge] takes NlogN
time, as one must take all the elements out of one queue and
insert them into the other queue.
In the _Binom_ chapter we will examine an algorithm in which
[empty] is constant time, [insert], [delete_max], and [merge]
are logN time.
In _this_ chapter we will consider a much simpler (and slower)
implementation, using unsorted lists, in which:
- [empty] takes constant time
- [insert] takes constant time
- [delete_max] takes linear time
- [merge] takes linear time
*)
(* ################################################################# *)
(** * Module Signature *)
(** This is the "signature" of a correct implementation of priority queues
where the keys are natural numbers. Using [nat] for the key type is
a bit silly, since the comparison function Nat.ltb takes linear time
in the value of the numbers! But you have already seen in the
[Extract] chapter how to define these kinds of algorithms
on key types that have efficient comparisons, so in this chapter
(and the [Binom] chapter) we simply won't worry about the
time per comparison. *)
From VFA Require Import Perm.
Module Type PRIQUEUE.
Parameter priqueue: Type.
Definition key := nat.
Parameter empty: priqueue.
Parameter insert: key -> priqueue -> priqueue.
Parameter delete_max: priqueue -> option (key * priqueue).
Parameter merge: priqueue -> priqueue -> priqueue.
Parameter priq: priqueue -> Prop.
Parameter Abs: priqueue -> list key -> Prop.
Axiom can_relate: forall p, priq p -> exists al, Abs p al.
Axiom abs_perm: forall p al bl,
priq p -> Abs p al -> Abs p bl -> Permutation al bl.
Axiom empty_priq: priq empty.
Axiom empty_relate: Abs empty nil.
Axiom insert_priq: forall k p, priq p -> priq (insert k p).
Axiom insert_relate:
forall p al k, priq p -> Abs p al -> Abs (insert k p) (k::al).
Axiom delete_max_None_relate:
forall p, priq p -> (Abs p nil <-> delete_max p = None).
Axiom delete_max_Some_priq:
forall p q k, priq p -> delete_max p = Some(k,q) -> priq q.
Axiom delete_max_Some_relate:
forall (p q: priqueue) k (pl ql: list key), priq p ->
Abs p pl ->
delete_max p = Some (k,q) ->
Abs q ql ->
Permutation pl (k::ql) /\ Forall (ge k) ql.
Axiom merge_priq: forall p q, priq p -> priq q -> priq (merge p q).
Axiom merge_relate:
forall p q pl ql al,
priq p -> priq q ->
Abs p pl -> Abs q ql -> Abs (merge p q) al ->
Permutation al (pl++ql).
End PRIQUEUE.
(** Take some time to consider whether this is the right specification!
As always, if we get the specification wrong, then proofs of
"correctness" are not so useful.
*)
(* ################################################################# *)
(** * Implementation *)
Module List_Priqueue <: PRIQUEUE.
(** Now we are responsible for providing [Definitions] of all
those [Parameters], and proving [Theorems] for all those [Axioms],
so that the values in the [Module] match the types in
the [Module Type]. If we try to [End List_Priqueue] before
everything is provided, we'll get an error. Uncomment the next
line and try it!
*)
(* End List_Priqueue. *)
(* ================================================================= *)
(** ** Some Preliminaries *)
(** A copy of the [select] function from Selection.v, but
getting the max element instead of the min element: *)
Fixpoint select (i: nat) (l: list nat) : nat * list nat :=
match l with
| nil => (i, nil)
| h::t => if i >=? h
then let (j, l') := select i t in (j, h::l')
else let (j,l') := select h t in (j, i::l')
end.
(** **** Exercise: 3 stars (select_perm_and_friends) *)
Lemma select_perm: forall i l,
let (j,r) := select i l in
Permutation (i::l) (j::r).
Proof. (* Copy your proof from Selection.v, and change one character. *)
intros i l; revert i.
induction l; intros; simpl in *.
(* FILL IN HERE *) Admitted.
Lemma select_biggest_aux:
forall i al j bl,
Forall (fun x => j >= x) bl ->
select i al = (j,bl) ->
j >= i.
Proof. (* Copy your proof of [select_smallest_aux] from Selection.v, and edit. *)
(* FILL IN HERE *) Admitted.
Theorem select_biggest:
forall i al j bl, select i al = (j,bl) ->
Forall (fun x => j >= x) bl.
Proof. (* Copy your proof of [select_smallest] from Selection.v, and edit. *)
intros i al; revert i; induction al; intros; simpl in *.
(* FILL IN HERE *) admit.
bdestruct (i >=? a).
*
destruct (select i al) eqn:?H.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ================================================================= *)
(** ** The Program *)
Definition key := nat.
Definition priqueue := list key.
Definition empty : priqueue := nil.
Definition insert (k: key)(p: priqueue) := k::p.
Definition delete_max (p: priqueue) :=
match p with
| i::p' => Some (select i p')
| nil => None
end.
Definition merge (p q: priqueue) : priqueue := p++q.
(* ################################################################# *)
(** * Predicates on Priority Queues *)
(* ================================================================= *)
(** ** The Representation Invariant *)
(** In this implementation of priority queues as unsorted lists,
the representation invariant is trivial. *)
Definition priq (p: priqueue) := True.
(** The abstraction relation is trivial too. *)
Inductive Abs': priqueue -> list key -> Prop :=
Abs_intro: forall p, Abs' p p.
Definition Abs := Abs'.
(* ================================================================= *)
(** ** Sanity Checks on the Abstraction Relation *)
Lemma can_relate : forall p, priq p -> exists al, Abs p al.
Proof.
intros. exists p; constructor.
Qed.
(** When the [Abs] relation says, "priority queue [p] contains elements [al]",
it is free to report the elements in any order. It could even relate [p]
to two different lists [al] and [bl], as long as one is a permutation of
the other. *)
Lemma abs_perm: forall p al bl,
priq p -> Abs p al -> Abs p bl -> Permutation al bl.
Proof.
intros.
inv H0. inv H1. apply Permutation_refl.
Qed.
(* ================================================================= *)
(** ** Characterizations of the Operations on Queues *)
Lemma empty_priq: priq empty.
Proof. constructor. Qed.
Lemma empty_relate: Abs empty nil.
Proof. constructor. Qed.
Lemma insert_priq: forall k p, priq p -> priq (insert k p).
Proof. intros; constructor. Qed.
Lemma insert_relate:
forall p al k, priq p -> Abs p al -> Abs (insert k p) (k::al).
Proof. intros. unfold insert. inv H0. constructor. Qed.
Lemma delete_max_Some_priq:
forall p q k, priq p -> delete_max p = Some(k,q) -> priq q.
Proof. constructor. Qed.
(** **** Exercise: 2 stars (simple_priq_proofs) *)
Lemma delete_max_None_relate:
forall p, priq p ->
(Abs p nil <-> delete_max p = None).
Proof.
(* FILL IN HERE *) Admitted.
Lemma delete_max_Some_relate:
forall (p q: priqueue) k (pl ql: list key), priq p ->
Abs p pl ->
delete_max p = Some (k,q) ->
Abs q ql ->
Permutation pl (k::ql) /\ Forall (ge k) ql.
Proof.
(* FILL IN HERE *) Admitted.
Lemma merge_priq:
forall p q, priq p -> priq q -> priq (merge p q).
Proof. intros. constructor. Qed.
Lemma merge_relate:
forall p q pl ql al,
priq p -> priq q ->
Abs p pl -> Abs q ql -> Abs (merge p q) al ->
Permutation al (pl++ql).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End List_Priqueue.
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: M.63c
// \ \ Application: netgen
// / / Filename: fifo_xlnx_32x36_2clk.v
// /___/ /\ Timestamp: Fri Oct 15 00:50:08 2010
// \ \ / \
// \___\/\___\
//
// Command : -intstyle ise -w -sim -ofmt verilog /tmp/_cg/fifo_xlnx_32x36_2clk.ngc /tmp/_cg/fifo_xlnx_32x36_2clk.v
// Device : 3s2000fg456-5
// Input file : /tmp/_cg/fifo_xlnx_32x36_2clk.ngc
// Output file : /tmp/_cg/fifo_xlnx_32x36_2clk.v
// # of Modules : 1
// Design Name : fifo_xlnx_32x36_2clk
// Xilinx : /opt/Xilinx/12.2/ISE_DS/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module fifo_xlnx_32x36_2clk (
rd_en, almost_full, prog_full, wr_en, full, empty, wr_clk, rst, rd_clk, dout, din
)/* synthesis syn_black_box syn_noprune=1 */;
input rd_en;
output almost_full;
output prog_full;
input wr_en;
output full;
output empty;
input wr_clk;
input rst;
input rd_clk;
output [35 : 0] dout;
input [35 : 0] din;
// synthesis translate_off
wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i62_392 ;
wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000156_391 ;
wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000079_390 ;
wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000063_389 ;
wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000027_388 ;
wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i26_387 ;
wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000069_386 ;
wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 ;
wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000067_384 ;
wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000026_383 ;
wire \BU2/U0/grf.rf/gl0.wr/wpntr/count_not0001 ;
wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000063_381 ;
wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000158_380 ;
wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000115_379 ;
wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000062_378 ;
wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000026_377 ;
wire \BU2/U0/grf.rf/gl0.rd/rpntr/count_not0001 ;
wire \BU2/U0/grf.rf/gl0.rd/rpntr/N11 ;
wire \BU2/U0/grf.rf/gl0.wr/wpntr/N11 ;
wire \BU2/N16 ;
wire \BU2/N14 ;
wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000 ;
wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ;
wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000 ;
wire \BU2/U0/grf.rf/mem/dout_i_not0001 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N147 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N145 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N143 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N141 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N137 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N135 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N139 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N133 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N131 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N129 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N127 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N123 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N121 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N125 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N119 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N117 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N115 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N113 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N109 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N107 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N111 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N103 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N101 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N105 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N97 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N95 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N99 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N93 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N91 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N89 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N87 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N83 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N81 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N85 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N79 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N77 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N75 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N73 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N69 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N67 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N71 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N65 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N63 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N61 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N59 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N55 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N53 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N57 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N51 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N49 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N47 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N45 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N41 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N39 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N43 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N37 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N35 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N33 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N31 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N27 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N25 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N29 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N23 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N21 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N19 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N17 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N13 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N11 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N15 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N9 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N7 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/N5 ;
wire \BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ;
wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count2 ;
wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count ;
wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count1 ;
wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count3 ;
wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count4 ;
wire \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_mux0003 ;
wire \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_not0001 ;
wire \BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ;
wire \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb_176 ;
wire \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 ;
wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count2 ;
wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count ;
wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count1 ;
wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count3 ;
wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count4 ;
wire \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ;
wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0003 ;
wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0002 ;
wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0001 ;
wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0000 ;
wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0003 ;
wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0002 ;
wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0001 ;
wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0000 ;
wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003_120 ;
wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 ;
wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0001 ;
wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0000 ;
wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003_110 ;
wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 ;
wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0001 ;
wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0000 ;
wire \BU2/U0/grf.rf/rstblk/wr_rst_comb ;
wire \BU2/U0/grf.rf/rstblk/rd_rst_comb ;
wire \BU2/U0/grf.rf/rstblk/wr_rst_asreg_95 ;
wire \BU2/U0/grf.rf/rstblk/rd_rst_asreg_94 ;
wire \BU2/U0/grf.rf/rstblk/rst_d1_93 ;
wire \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2_92 ;
wire \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_91 ;
wire \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2_90 ;
wire \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_89 ;
wire \BU2/U0/grf.rf/rstblk/rst_d2_88 ;
wire \BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ;
wire \BU2/U0/grf.rf/rstblk/rst_d3_86 ;
wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ;
wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000 ;
wire \BU2/N1 ;
wire NLW_VCC_P_UNCONNECTED;
wire NLW_GND_G_UNCONNECTED;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM72_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM71_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM70_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM69_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM67_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM66_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM68_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM65_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM64_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM63_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM62_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM60_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM59_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM61_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM58_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM57_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM56_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM55_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM53_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM52_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM54_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM50_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM49_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM51_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM47_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM46_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM48_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM45_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM44_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM43_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM42_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM40_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM39_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM41_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM38_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM37_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM36_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM35_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM33_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM32_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM34_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM31_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM30_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM29_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM28_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM26_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM25_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM27_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM24_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM23_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM22_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM21_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM19_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM18_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM20_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM17_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM16_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM15_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM14_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM12_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM11_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM13_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM10_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM9_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM8_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM7_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM5_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM4_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM6_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM3_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM2_SPO_UNCONNECTED ;
wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM1_SPO_UNCONNECTED ;
wire [35 : 0] din_2;
wire [35 : 0] dout_3;
wire [35 : 0] \BU2/U0/grf.rf/mem/gdm.dm/dout_i ;
wire [35 : 0] \BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 ;
wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 ;
wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 ;
wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 ;
wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/wpntr/count ;
wire [5 : 4] \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad ;
wire [5 : 1] \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut ;
wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy ;
wire [5 : 4] \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 ;
wire [1 : 0] \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state ;
wire [1 : 0] \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 ;
wire [4 : 0] \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 ;
wire [4 : 0] \BU2/U0/grf.rf/gl0.rd/rpntr/count ;
wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc ;
wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc ;
wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 ;
wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg ;
wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 ;
wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg ;
wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin ;
wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin ;
wire [1 : 0] \BU2/U0/grf.rf/rstblk/wr_rst_reg ;
wire [2 : 0] \BU2/U0/grf.rf/rstblk/rd_rst_reg ;
wire [0 : 0] \BU2/rd_data_count ;
assign
dout[35] = dout_3[35],
dout[34] = dout_3[34],
dout[33] = dout_3[33],
dout[32] = dout_3[32],
dout[31] = dout_3[31],
dout[30] = dout_3[30],
dout[29] = dout_3[29],
dout[28] = dout_3[28],
dout[27] = dout_3[27],
dout[26] = dout_3[26],
dout[25] = dout_3[25],
dout[24] = dout_3[24],
dout[23] = dout_3[23],
dout[22] = dout_3[22],
dout[21] = dout_3[21],
dout[20] = dout_3[20],
dout[19] = dout_3[19],
dout[18] = dout_3[18],
dout[17] = dout_3[17],
dout[16] = dout_3[16],
dout[15] = dout_3[15],
dout[14] = dout_3[14],
dout[13] = dout_3[13],
dout[12] = dout_3[12],
dout[11] = dout_3[11],
dout[10] = dout_3[10],
dout[9] = dout_3[9],
dout[8] = dout_3[8],
dout[7] = dout_3[7],
dout[6] = dout_3[6],
dout[5] = dout_3[5],
dout[4] = dout_3[4],
dout[3] = dout_3[3],
dout[2] = dout_3[2],
dout[1] = dout_3[1],
dout[0] = dout_3[0],
din_2[35] = din[35],
din_2[34] = din[34],
din_2[33] = din[33],
din_2[32] = din[32],
din_2[31] = din[31],
din_2[30] = din[30],
din_2[29] = din[29],
din_2[28] = din[28],
din_2[27] = din[27],
din_2[26] = din[26],
din_2[25] = din[25],
din_2[24] = din[24],
din_2[23] = din[23],
din_2[22] = din[22],
din_2[21] = din[21],
din_2[20] = din[20],
din_2[19] = din[19],
din_2[18] = din[18],
din_2[17] = din[17],
din_2[16] = din[16],
din_2[15] = din[15],
din_2[14] = din[14],
din_2[13] = din[13],
din_2[12] = din[12],
din_2[11] = din[11],
din_2[10] = din[10],
din_2[9] = din[9],
din_2[8] = din[8],
din_2[7] = din[7],
din_2[6] = din[6],
din_2[5] = din[5],
din_2[4] = din[4],
din_2[3] = din[3],
din_2[2] = din[2],
din_2[1] = din[1],
din_2[0] = din[0];
VCC VCC_0 (
.P(NLW_VCC_P_UNCONNECTED)
);
GND GND_1 (
.G(NLW_GND_G_UNCONNECTED)
);
LUT3_L #(
.INIT ( 8'h90 ))
\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000063 (
.I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0]),
.I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.I2(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000062_378 ),
.LO(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000063_381 )
);
LUT4_L #(
.INIT ( 16'h9000 ))
\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000079 (
.I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]),
.I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]),
.I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000063_389 ),
.I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000027_388 ),
.LO(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000079_390 )
);
LUT4_L #(
.INIT ( 16'h9000 ))
\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000069 (
.I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]),
.I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
.I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000067_384 ),
.I3(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
.LO(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000069_386 )
);
LUT4_L #(
.INIT ( 16'h8421 ))
\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i62 (
.I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [2]),
.I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [3]),
.I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]),
.I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]),
.LO(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i62_392 )
);
LUT4_L #(
.INIT ( 16'h8241 ))
\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000156 (
.I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1]),
.I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2]),
.I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]),
.I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]),
.LO(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000156_391 )
);
LUT3_L #(
.INIT ( 8'h7F ))
\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<3>111 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
.I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]),
.I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]),
.LO(\BU2/U0/grf.rf/gl0.rd/rpntr/N11 )
);
LUT3_L #(
.INIT ( 8'h7F ))
\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<3>111 (
.I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
.I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]),
.I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]),
.LO(\BU2/U0/grf.rf/gl0.wr/wpntr/N11 )
);
LUT2_L #(
.INIT ( 4'h6 ))
\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003_SW0 (
.I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]),
.I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]),
.LO(\BU2/N16 )
);
LUT2_L #(
.INIT ( 4'h6 ))
\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003_SW0 (
.I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]),
.I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]),
.LO(\BU2/N14 )
);
INV \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<0>11_INV_0 (
.I(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
.O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count )
);
INV \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<0>11_INV_0 (
.I(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
.O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count )
);
LUT2 #(
.INIT ( 4'h2 ))
\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_1 (
.I0(wr_en),
.I1(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ),
.O(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 )
);
LUT4 #(
.INIT ( 16'h2333 ))
\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_1 (
.I0(rd_en),
.I1(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ),
.I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]),
.I3(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]),
.O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 )
);
LUT4 #(
.INIT ( 16'h6AAA ))
\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<3>12 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]),
.I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
.I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]),
.I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]),
.O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count3 )
);
LUT4 #(
.INIT ( 16'h6AAA ))
\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<3>12 (
.I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]),
.I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
.I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]),
.I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]),
.O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count3 )
);
LUT3 #(
.INIT ( 8'h08 ))
\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1 (
.I0(wr_en),
.I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]),
.I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 )
);
LUT3 #(
.INIT ( 8'h10 ))
\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl (
.I0(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ),
.I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]),
.I2(wr_en),
.O(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 )
);
LUT2 #(
.INIT ( 4'h9 ))
\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<5> (
.I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]),
.I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]),
.O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [5])
);
LUT4 #(
.INIT ( 16'h9000 ))
\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i78 (
.I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [0]),
.I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]),
.I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i62_392 ),
.I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i26_387 ),
.O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 )
);
LUT4 #(
.INIT ( 16'h9000 ))
\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000158 (
.I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0]),
.I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
.I2(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000156_391 ),
.I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_not0001 ),
.O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000158_380 )
);
LUT2 #(
.INIT ( 4'h9 ))
\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<4> (
.I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]),
.I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]),
.O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [4])
);
LUT2 #(
.INIT ( 4'h9 ))
\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<3> (
.I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]),
.I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]),
.O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [3])
);
LUT2 #(
.INIT ( 4'h9 ))
\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<2> (
.I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]),
.I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]),
.O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [2])
);
LUT2 #(
.INIT ( 4'h9 ))
\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<1> (
.I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]),
.I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]),
.O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [1])
);
LUT4 #(
.INIT ( 16'h5450 ))
\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000105 (
.I0(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ),
.I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_not0001 ),
.I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000079_390 ),
.I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 ),
.O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000 )
);
LUT4 #(
.INIT ( 16'h9009 ))
\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000063 (
.I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]),
.I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]),
.I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]),
.I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]),
.O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000063_389 )
);
LUT4 #(
.INIT ( 16'h9009 ))
\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000027 (
.I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]),
.I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]),
.I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]),
.I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]),
.O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000027_388 )
);
LUT4 #(
.INIT ( 16'h8421 ))
\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i26 (
.I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [1]),
.I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [4]),
.I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]),
.I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]),
.O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i26_387 )
);
LUT4 #(
.INIT ( 16'h5450 ))
\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000107 (
.I0(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ),
.I1(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000026_383 ),
.I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 ),
.I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000069_386 ),
.O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000 )
);
LUT4 #(
.INIT ( 16'h9009 ))
\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000067 (
.I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]),
.I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]),
.I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]),
.I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]),
.O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000067_384 )
);
LUT4 #(
.INIT ( 16'h9009 ))
\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000026 (
.I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]),
.I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]),
.I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]),
.I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]),
.O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000026_383 )
);
LUT2 #(
.INIT ( 4'h2 ))
\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1 (
.I0(wr_en),
.I1(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ),
.O(\BU2/U0/grf.rf/gl0.wr/wpntr/count_not0001 )
);
LUT4 #(
.INIT ( 16'hECA0 ))
\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000183 (
.I0(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000115_379 ),
.I1(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000026_377 ),
.I2(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000158_380 ),
.I3(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000063_381 ),
.O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000 )
);
LUT4 #(
.INIT ( 16'h9009 ))
\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000115 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]),
.I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4]),
.I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]),
.I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3]),
.O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000115_379 )
);
LUT4 #(
.INIT ( 16'h8421 ))
\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000062 (
.I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2]),
.I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3]),
.I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000062_378 )
);
LUT4 #(
.INIT ( 16'h8241 ))
\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000026 (
.I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1]),
.I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4]),
.I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000026_377 )
);
LUT4 #(
.INIT ( 16'h2333 ))
\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21 (
.I0(rd_en),
.I1(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ),
.I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]),
.I3(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]),
.O(\BU2/U0/grf.rf/gl0.rd/rpntr/count_not0001 )
);
LUT3 #(
.INIT ( 8'hA6 ))
\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<4>11 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]),
.I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]),
.I2(\BU2/U0/grf.rf/gl0.rd/rpntr/N11 ),
.O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count4 )
);
LUT3 #(
.INIT ( 8'hA6 ))
\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<4>11 (
.I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]),
.I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]),
.I2(\BU2/U0/grf.rf/gl0.wr/wpntr/N11 ),
.O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count4 )
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX11 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N5 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N7 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [0])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1011 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N45 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N47 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [10])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1111 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N9 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N11 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [1])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX11111 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N49 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N51 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [11])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1211 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N53 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N55 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [12])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1311 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N57 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N59 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [13])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1411 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N61 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N63 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [14])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1511 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N65 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N67 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [15])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1611 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N69 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N71 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [16])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1711 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N73 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N75 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [17])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1811 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N77 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N79 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [18])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1911 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N81 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N83 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [19])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2011 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N85 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N87 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [20])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2111 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N13 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N15 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [2])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX21111 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N89 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N91 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [21])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2211 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N93 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N95 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [22])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2311 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N97 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N99 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [23])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2411 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N101 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N103 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [24])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2511 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N105 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N107 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [25])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2611 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N109 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N111 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [26])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2711 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N113 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N115 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [27])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2811 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N117 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N119 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [28])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2911 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N121 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N123 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [29])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3011 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N125 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N127 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [30])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3111 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N17 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N19 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [3])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX31111 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N129 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N131 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [31])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3211 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N133 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N135 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [32])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3311 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N137 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N139 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [33])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3411 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N141 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N143 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [34])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3511 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N145 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N147 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [35])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX411 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N21 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N23 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [4])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX511 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N25 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N27 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [5])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX611 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N29 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N31 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [6])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX711 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N33 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N35 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [7])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX811 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N37 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N39 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [8])
);
LUT3 #(
.INIT ( 8'hE4 ))
\BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX911 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/mem/gdm.dm/N41 ),
.I2(\BU2/U0/grf.rf/mem/gdm.dm/N43 ),
.O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [9])
);
LUT4 #(
.INIT ( 16'h6996 ))
\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003 (
.I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [1]),
.I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [0]),
.I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]),
.I3(\BU2/N16 ),
.O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003_110 )
);
LUT4 #(
.INIT ( 16'h6996 ))
\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003 (
.I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [1]),
.I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [0]),
.I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]),
.I3(\BU2/N14 ),
.O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003_120 )
);
LUT3 #(
.INIT ( 8'hA2 ))
\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_REGOUT_EN11 (
.I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]),
.I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]),
.I2(rd_en),
.O(\BU2/U0/grf.rf/mem/dout_i_not0001 )
);
LUT2 #(
.INIT ( 4'hD ))
\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_not00011 (
.I0(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ),
.I1(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ),
.O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_not0001 )
);
LUT4 #(
.INIT ( 16'h8E8A ))
\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux00001 (
.I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb_176 ),
.I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]),
.I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]),
.I3(rd_en),
.O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 )
);
LUT4 #(
.INIT ( 16'h6996 ))
\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00021 (
.I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]),
.I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [1]),
.I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]),
.I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]),
.O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 )
);
LUT4 #(
.INIT ( 16'h6996 ))
\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00021 (
.I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]),
.I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [1]),
.I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]),
.I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]),
.O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 )
);
LUT4 #(
.INIT ( 16'h40FF ))
\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001<0>1 (
.I0(rd_en),
.I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]),
.I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]),
.I3(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ),
.O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [0])
);
LUT3 #(
.INIT ( 8'h6A ))
\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<2>11 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]),
.I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
.I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]),
.O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count2 )
);
LUT3 #(
.INIT ( 8'h6A ))
\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<2>11 (
.I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]),
.I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
.I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]),
.O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count2 )
);
LUT3 #(
.INIT ( 8'h96 ))
\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00011 (
.I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]),
.I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]),
.I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]),
.O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0001 )
);
LUT3 #(
.INIT ( 8'h96 ))
\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00011 (
.I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]),
.I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]),
.I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]),
.O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0001 )
);
LUT3 #(
.INIT ( 8'hF2 ))
\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001<1>1 (
.I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]),
.I1(rd_en),
.I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]),
.O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [1])
);
LUT3 #(
.INIT ( 8'h08 ))
\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_mux00031 (
.I0(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [4]),
.I1(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [5]),
.I2(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ),
.O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_mux0003 )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0000_Result1 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0000 )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0001_Result1 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0001 )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0002_Result1 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0002 )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0003_Result1 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0003 )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0000_Result1 (
.I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]),
.I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0000 )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0001_Result1 (
.I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0001 )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0002_Result1 (
.I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0002 )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0003_Result1 (
.I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0003 )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<1>11 (
.I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
.I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]),
.O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<1>11 (
.I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]),
.I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
.O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00001 (
.I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]),
.I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]),
.O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0000 )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00001 (
.I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]),
.I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]),
.O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0000 )
);
LUT2 #(
.INIT ( 4'h4 ))
\BU2/U0/grf.rf/rstblk/rd_rst_comb1 (
.I0(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2_90 ),
.I1(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_94 ),
.O(\BU2/U0/grf.rf/rstblk/rd_rst_comb )
);
LUT2 #(
.INIT ( 4'h4 ))
\BU2/U0/grf.rf/rstblk/wr_rst_comb1 (
.I0(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2_92 ),
.I1(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_95 ),
.O(\BU2/U0/grf.rf/rstblk/wr_rst_comb )
);
FDPE #(
.INIT ( 1'b1 ))
\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i (
.C(wr_clk),
.CE(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_not0001 ),
.D(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000 ),
.PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ),
.Q(almost_full)
);
FDP #(
.INIT ( 1'b1 ))
\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i (
.C(wr_clk),
.D(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000 ),
.PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ),
.Q(full)
);
FDP #(
.INIT ( 1'b1 ))
\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i (
.C(wr_clk),
.D(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000 ),
.PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ),
.Q(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 )
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_0 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [0]),
.Q(dout_3[0])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_1 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [1]),
.Q(dout_3[1])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_2 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [2]),
.Q(dout_3[2])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_3 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [3]),
.Q(dout_3[3])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_4 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [4]),
.Q(dout_3[4])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_5 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [5]),
.Q(dout_3[5])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_6 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [6]),
.Q(dout_3[6])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_7 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [7]),
.Q(dout_3[7])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_8 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [8]),
.Q(dout_3[8])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_9 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [9]),
.Q(dout_3[9])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_10 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [10]),
.Q(dout_3[10])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_11 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [11]),
.Q(dout_3[11])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_12 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [12]),
.Q(dout_3[12])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_13 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [13]),
.Q(dout_3[13])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_14 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [14]),
.Q(dout_3[14])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_15 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [15]),
.Q(dout_3[15])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_16 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [16]),
.Q(dout_3[16])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_17 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [17]),
.Q(dout_3[17])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_18 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [18]),
.Q(dout_3[18])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_19 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [19]),
.Q(dout_3[19])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_20 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [20]),
.Q(dout_3[20])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_21 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [21]),
.Q(dout_3[21])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_22 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [22]),
.Q(dout_3[22])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_23 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [23]),
.Q(dout_3[23])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_24 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [24]),
.Q(dout_3[24])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_25 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [25]),
.Q(dout_3[25])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_26 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [26]),
.Q(dout_3[26])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_27 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [27]),
.Q(dout_3[27])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_28 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [28]),
.Q(dout_3[28])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_29 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [29]),
.Q(dout_3[29])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_30 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [30]),
.Q(dout_3[30])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_31 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [31]),
.Q(dout_3[31])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_32 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [32]),
.Q(dout_3[32])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_33 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [33]),
.Q(dout_3[33])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_34 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [34]),
.Q(dout_3[34])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/dout_i_35 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [35]),
.Q(dout_3[35])
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM72 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[35]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM72_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N147 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM71 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[35]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM71_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N145 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM70 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[34]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM70_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N143 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM69 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[34]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM69_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N141 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM67 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[33]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM67_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N137 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM66 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[32]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM66_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N135 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM68 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[33]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM68_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N139 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM65 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[32]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM65_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N133 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM64 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[31]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM64_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N131 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM63 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[31]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM63_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N129 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM62 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[30]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM62_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N127 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM60 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[29]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM60_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N123 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM59 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[29]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM59_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N121 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM61 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[30]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM61_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N125 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM58 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[28]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM58_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N119 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM57 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[28]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM57_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N117 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM56 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[27]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM56_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N115 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM55 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[27]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM55_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N113 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM53 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[26]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM53_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N109 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM52 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[25]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM52_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N107 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM54 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[26]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM54_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N111 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM50 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[24]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM50_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N103 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM49 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[24]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM49_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N101 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM51 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[25]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM51_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N105 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM47 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[23]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM47_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N97 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM46 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[22]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM46_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N95 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM48 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[23]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM48_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N99 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM45 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[22]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM45_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N93 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM44 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[21]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM44_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N91 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM43 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[21]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM43_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N89 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM42 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[20]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM42_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N87 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM40 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[19]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM40_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N83 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM39 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[19]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM39_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N81 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM41 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[20]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM41_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N85 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM38 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[18]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM38_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N79 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM37 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[18]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM37_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N77 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM36 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[17]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM36_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N75 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM35 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[17]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM35_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N73 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM33 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[16]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM33_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N69 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM32 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[15]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM32_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N67 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM34 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[16]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM34_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N71 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM31 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[15]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM31_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N65 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM30 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[14]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM30_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N63 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM29 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[14]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM29_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N61 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM28 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[13]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM28_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N59 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM26 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[12]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM26_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N55 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM25 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[12]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM25_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N53 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM27 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[13]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM27_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N57 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM24 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[11]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM24_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N51 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM23 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[11]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM23_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N49 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM22 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[10]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM22_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N47 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM21 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[10]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM21_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N45 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM19 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[9]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM19_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N41 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM18 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[8]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM18_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N39 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM20 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[9]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM20_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N43 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM17 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[8]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM17_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N37 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM16 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[7]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM16_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N35 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM15 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[7]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM15_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N33 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM14 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[6]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM14_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N31 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM12 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[5]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM12_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N27 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM11 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[5]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM11_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N25 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM13 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[6]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM13_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N29 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM10 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[4]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM10_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N23 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM9 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[4]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM9_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N21 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM8 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[3]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM8_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N19 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM7 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[3]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM7_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N17 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM5 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[2]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM5_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N13 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM4 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[1]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM4_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N11 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM6 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[2]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM6_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N15 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM3 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[1]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM3_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N9 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM2 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[0]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM2_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N7 )
);
RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM1 (
.A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
.A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
.A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
.A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
.D(din_2[0]),
.DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
.DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
.DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
.DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
.WCLK(wr_clk),
.WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
.SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM1_SPO_UNCONNECTED ),
.DPO(\BU2/U0/grf.rf/mem/gdm.dm/N5 )
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_35 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [35]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [35])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_34 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [34]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [34])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_33 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [33]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [33])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_32 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [32]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [32])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_31 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [31]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [31])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_30 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [30]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [30])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_29 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [29]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [29])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_28 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [28]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [28])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_27 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [27]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [27])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_26 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [26]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [26])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_25 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [25]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [25])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_24 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [24]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [24])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_23 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [23]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [23])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_22 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [22]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [22])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_21 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [21]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [21])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_20 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [20]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [20])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_19 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [19]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [19])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_18 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [18]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [18])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_17 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [17]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [17])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_16 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [16]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [16])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_15 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [15]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [15])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_14 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [14]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [14])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_13 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [13]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [13])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_12 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [12]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [12])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_11 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [11]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [11])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_10 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [10]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [10])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_9 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [9]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [9])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_8 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [8]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [8])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_7 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [7]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [7])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_6 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [6]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [6])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_5 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [5]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [5])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_4 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [4]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [4])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_3 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [3]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [3])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_2 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [2]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [2])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_1 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [1]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [1])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/mem/gdm.dm/dout_i_0 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
.D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [0]),
.Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [0])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_0 (
.C(wr_clk),
.CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
.D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]),
.Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_1 (
.C(wr_clk),
.CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
.D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]),
.Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_2 (
.C(wr_clk),
.CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
.D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]),
.Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_3 (
.C(wr_clk),
.CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
.D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]),
.Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_4 (
.C(wr_clk),
.CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
.D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]),
.Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_4 (
.C(wr_clk),
.CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
.D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [4]),
.Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_3 (
.C(wr_clk),
.CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
.D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [3]),
.Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_1 (
.C(wr_clk),
.CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
.D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [1]),
.Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1])
);
FDPE #(
.INIT ( 1'b1 ))
\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_0 (
.C(wr_clk),
.CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
.D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [0]),
.PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
.Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_2 (
.C(wr_clk),
.CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
.D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [2]),
.Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_4 (
.C(wr_clk),
.CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
.D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]),
.Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [4])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_3 (
.C(wr_clk),
.CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
.D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]),
.Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [3])
);
FDPE #(
.INIT ( 1'b1 ))
\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_1 (
.C(wr_clk),
.CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
.D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]),
.PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
.Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [1])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_0 (
.C(wr_clk),
.CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
.D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
.Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [0])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_2 (
.C(wr_clk),
.CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
.D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]),
.Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [2])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gl0.wr/wpntr/count_2 (
.C(wr_clk),
.CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
.D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count2 ),
.Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2])
);
FDPE #(
.INIT ( 1'b1 ))
\BU2/U0/grf.rf/gl0.wr/wpntr/count_0 (
.C(wr_clk),
.CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
.D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count ),
.PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
.Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0])
);
FDPE #(
.INIT ( 1'b1 ))
\BU2/U0/grf.rf/gl0.wr/wpntr/count_1 (
.C(wr_clk),
.CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
.D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count1 ),
.PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
.Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gl0.wr/wpntr/count_3 (
.C(wr_clk),
.CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
.D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count3 ),
.Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gl0.wr/wpntr/count_4 (
.C(wr_clk),
.CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
.D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count4 ),
.Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4])
);
FDPE #(
.INIT ( 1'b1 ))
\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i (
.C(wr_clk),
.CE(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_not0001 ),
.D(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_mux0003 ),
.PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ),
.Q(prog_full)
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_4 (
.C(wr_clk),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
.D(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [4]),
.Q(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [4])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_5 (
.C(wr_clk),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
.D(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [5]),
.Q(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [5])
);
MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<0> (
.CI(\BU2/N1 ),
.DI(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
.S(\BU2/rd_data_count [0]),
.O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [0])
);
MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<1> (
.CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [0]),
.DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]),
.S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [1]),
.O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [1])
);
MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<2> (
.CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [1]),
.DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]),
.S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [2]),
.O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [2])
);
MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<3> (
.CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [2]),
.DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]),
.S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [3]),
.O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [3])
);
MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<4> (
.CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [3]),
.DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]),
.S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [4]),
.O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [4])
);
XORCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_xor<4> (
.CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [3]),
.LI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [4]),
.O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [4])
);
XORCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_xor<5> (
.CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [4]),
.LI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [5]),
.O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [5])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_0 (
.C(rd_clk),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
.D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [1]),
.Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_1 (
.C(rd_clk),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
.D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [0]),
.Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1])
);
FDP #(
.INIT ( 1'b1 ))
\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i (
.C(rd_clk),
.D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 ),
.PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
.Q(empty)
);
FDP #(
.INIT ( 1'b1 ))
\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb (
.C(rd_clk),
.D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 ),
.PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
.Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb_176 )
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_0 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
.D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
.Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_1 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
.D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]),
.Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_2 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
.D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]),
.Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_3 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
.D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]),
.Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_4 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
.D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]),
.Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gl0.rd/rpntr/count_2 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
.D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count2 ),
.Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2])
);
FDPE #(
.INIT ( 1'b1 ))
\BU2/U0/grf.rf/gl0.rd/rpntr/count_0 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count ),
.PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
.Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gl0.rd/rpntr/count_1 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
.D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count1 ),
.Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gl0.rd/rpntr/count_3 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
.D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count3 ),
.Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3])
);
FDCE #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gl0.rd/rpntr/count_4 (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
.D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count4 ),
.Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_0 (
.C(wr_clk),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
.D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0003 ),
.Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [0])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_1 (
.C(wr_clk),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
.D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0002 ),
.Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [1])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_2 (
.C(wr_clk),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
.D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0001 ),
.Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [2])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_3 (
.C(wr_clk),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
.D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0000 ),
.Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [3])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_4 (
.C(wr_clk),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
.D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]),
.Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [4])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_0 (
.C(rd_clk),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
.D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0003 ),
.Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [0])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_1 (
.C(rd_clk),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
.D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0002 ),
.Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [1])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_2 (
.C(rd_clk),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
.D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0001 ),
.Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [2])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_3 (
.C(rd_clk),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
.D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0000 ),
.Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [3])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_4 (
.C(rd_clk),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
.D(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
.Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [4])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_0 (
.C(wr_clk),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
.D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [0]),
.Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [0])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_1 (
.C(wr_clk),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
.D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [1]),
.Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [1])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_2 (
.C(wr_clk),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
.D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [2]),
.Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [2])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_3 (
.C(wr_clk),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
.D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [3]),
.Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [3])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_4 (
.C(wr_clk),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
.D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [4]),
.Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [4])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_0 (
.C(rd_clk),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
.D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [0]),
.Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [0])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_1 (
.C(rd_clk),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
.D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [1]),
.Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [1])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_2 (
.C(rd_clk),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
.D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [2]),
.Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [2])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_3 (
.C(rd_clk),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
.D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [3]),
.Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [3])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_4 (
.C(rd_clk),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
.D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [4]),
.Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [4])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_0 (
.C(wr_clk),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
.D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [0]),
.Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [0])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_1 (
.C(wr_clk),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
.D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [1]),
.Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [1])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_2 (
.C(wr_clk),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
.D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [2]),
.Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_3 (
.C(wr_clk),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
.D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [3]),
.Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_4 (
.C(wr_clk),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
.D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [4]),
.Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_0 (
.C(rd_clk),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
.D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [0]),
.Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [0])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_1 (
.C(rd_clk),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
.D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [1]),
.Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [1])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_2 (
.C(rd_clk),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
.D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [2]),
.Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_3 (
.C(rd_clk),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
.D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [3]),
.Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_4 (
.C(rd_clk),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
.D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [4]),
.Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_0 (
.C(rd_clk),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
.D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003_120 ),
.Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_1 (
.C(rd_clk),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
.D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 ),
.Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_2 (
.C(rd_clk),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
.D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0001 ),
.Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_3 (
.C(rd_clk),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
.D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0000 ),
.Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_4 (
.C(rd_clk),
.CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
.D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]),
.Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_0 (
.C(wr_clk),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
.D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003_110 ),
.Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_1 (
.C(wr_clk),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
.D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 ),
.Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_2 (
.C(wr_clk),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
.D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0001 ),
.Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_3 (
.C(wr_clk),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
.D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0000 ),
.Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3])
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_4 (
.C(wr_clk),
.CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
.D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]),
.Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4])
);
FDP #(
.INIT ( 1'b1 ))
\BU2/U0/grf.rf/rstblk/wr_rst_reg_0 (
.C(wr_clk),
.D(\BU2/rd_data_count [0]),
.PRE(\BU2/U0/grf.rf/rstblk/wr_rst_comb ),
.Q(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0])
);
FDP #(
.INIT ( 1'b1 ))
\BU2/U0/grf.rf/rstblk/wr_rst_reg_1 (
.C(wr_clk),
.D(\BU2/rd_data_count [0]),
.PRE(\BU2/U0/grf.rf/rstblk/wr_rst_comb ),
.Q(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1])
);
FDP #(
.INIT ( 1'b1 ))
\BU2/U0/grf.rf/rstblk/rd_rst_reg_0 (
.C(rd_clk),
.D(\BU2/rd_data_count [0]),
.PRE(\BU2/U0/grf.rf/rstblk/rd_rst_comb ),
.Q(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0])
);
FDP #(
.INIT ( 1'b1 ))
\BU2/U0/grf.rf/rstblk/rd_rst_reg_1 (
.C(rd_clk),
.D(\BU2/rd_data_count [0]),
.PRE(\BU2/U0/grf.rf/rstblk/rd_rst_comb ),
.Q(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1])
);
FDP #(
.INIT ( 1'b1 ))
\BU2/U0/grf.rf/rstblk/rd_rst_reg_2 (
.C(rd_clk),
.D(\BU2/rd_data_count [0]),
.PRE(\BU2/U0/grf.rf/rstblk/rd_rst_comb ),
.Q(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2])
);
FDP #(
.INIT ( 1'b1 ))
\BU2/U0/grf.rf/rstblk/rst_d1 (
.C(wr_clk),
.D(\BU2/rd_data_count [0]),
.PRE(rst),
.Q(\BU2/U0/grf.rf/rstblk/rst_d1_93 )
);
FDPE \BU2/U0/grf.rf/rstblk/rd_rst_asreg (
.C(rd_clk),
.CE(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_89 ),
.D(\BU2/rd_data_count [0]),
.PRE(rst),
.Q(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_94 )
);
FD #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1 (
.C(wr_clk),
.D(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_95 ),
.Q(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_91 )
);
FDPE \BU2/U0/grf.rf/rstblk/wr_rst_asreg (
.C(wr_clk),
.CE(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_91 ),
.D(\BU2/rd_data_count [0]),
.PRE(rst),
.Q(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_95 )
);
FD #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1 (
.C(rd_clk),
.D(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_94 ),
.Q(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_89 )
);
FDP #(
.INIT ( 1'b1 ))
\BU2/U0/grf.rf/rstblk/rst_d2 (
.C(wr_clk),
.D(\BU2/U0/grf.rf/rstblk/rst_d1_93 ),
.PRE(rst),
.Q(\BU2/U0/grf.rf/rstblk/rst_d2_88 )
);
FD #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2 (
.C(wr_clk),
.D(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_91 ),
.Q(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2_92 )
);
FD #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2 (
.C(rd_clk),
.D(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_89 ),
.Q(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2_90 )
);
FDP #(
.INIT ( 1'b1 ))
\BU2/U0/grf.rf/rstblk/rst_d3 (
.C(wr_clk),
.D(\BU2/U0/grf.rf/rstblk/rst_d2_88 ),
.PRE(rst),
.Q(\BU2/U0/grf.rf/rstblk/rst_d3_86 )
);
FDC #(
.INIT ( 1'b0 ))
\BU2/U0/grf.rf/rstblk/RST_FULL_GEN (
.C(wr_clk),
.CLR(rst),
.D(\BU2/U0/grf.rf/rstblk/rst_d3_86 ),
.Q(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 )
);
FDP #(
.INIT ( 1'b1 ))
\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i (
.C(rd_clk),
.D(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000 ),
.PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
.Q(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 )
);
VCC \BU2/XST_VCC (
.P(\BU2/N1 )
);
GND \BU2/XST_GND (
.G(\BU2/rd_data_count [0])
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
////////////////////////////////////////////////////////////
//-----------------------------------------------------------------------------
//
// Description:
// Optimized Mux using MUXF7/8.
// Any mux ratio.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// mux_enc
//
//--------------------------------------------------------------------------
`ifndef AXIS_INFRASTRUCTURE_V1_0_MUX_ENC_V
`define AXIS_INFRASTRUCTURE_V1_0_MUX_ENC_V
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axis_infrastructure_v1_1_0_mux_enc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_RATIO = 4,
// Mux select ratio. Can be any binary value (>= 1)
parameter integer C_SEL_WIDTH = 2,
// Log2-ceiling of C_RATIO (>= 1)
parameter integer C_DATA_WIDTH = 1
// Data width for comparator (>= 1)
)
(
input wire [C_SEL_WIDTH-1:0] S,
input wire [C_RATIO*C_DATA_WIDTH-1:0] A,
output wire [C_DATA_WIDTH-1:0] O,
input wire OE
);
wire [C_DATA_WIDTH-1:0] o_i;
genvar bit_cnt;
function [C_DATA_WIDTH-1:0] f_mux
(
input [C_SEL_WIDTH-1:0] s,
input [C_RATIO*C_DATA_WIDTH-1:0] a
);
integer i;
reg [C_RATIO*C_DATA_WIDTH-1:0] carry;
begin
carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc
carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] =
carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] |
({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]);
end
f_mux = carry[C_DATA_WIDTH*C_RATIO-1:C_DATA_WIDTH*(C_RATIO-1)];
end
endfunction
function [C_DATA_WIDTH-1:0] f_mux4
(
input [1:0] s,
input [4*C_DATA_WIDTH-1:0] a
);
integer i;
reg [4*C_DATA_WIDTH-1:0] carry;
begin
carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0];
for (i=1;i<4;i=i+1) begin : gen_carrychain_enc
carry[i*C_DATA_WIDTH +: C_DATA_WIDTH] =
carry[(i-1)*C_DATA_WIDTH +: C_DATA_WIDTH] |
({C_DATA_WIDTH{(s==i)?1'b1:1'b0}} & a[i*C_DATA_WIDTH +: C_DATA_WIDTH]);
end
f_mux4 = carry[C_DATA_WIDTH*4-1:C_DATA_WIDTH*3];
end
endfunction
assign O = o_i & {C_DATA_WIDTH{OE}}; // OE is gated AFTER any MUXF7/8 (can only optimize forward into downstream logic)
generate
if ( C_RATIO < 2 ) begin : gen_bypass
assign o_i = A;
end else if ( C_FAMILY == "rtl" || C_RATIO < 5 ) begin : gen_rtl
assign o_i = f_mux(S, A);
end else begin : gen_fpga
wire [C_DATA_WIDTH-1:0] l;
wire [C_DATA_WIDTH-1:0] h;
wire [C_DATA_WIDTH-1:0] ll;
wire [C_DATA_WIDTH-1:0] lh;
wire [C_DATA_WIDTH-1:0] hl;
wire [C_DATA_WIDTH-1:0] hh;
case (C_RATIO)
1, 5, 9, 13:
assign hh = A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH];
2, 6, 10, 14:
assign hh = S[0] ?
A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ;
3, 7, 11, 15:
assign hh = S[1] ?
A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
(S[0] ?
A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] );
4, 8, 12, 16:
assign hh = S[1] ?
(S[0] ?
A[(C_RATIO-1)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-2)*C_DATA_WIDTH +: C_DATA_WIDTH] ) :
(S[0] ?
A[(C_RATIO-3)*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[(C_RATIO-4)*C_DATA_WIDTH +: C_DATA_WIDTH] );
17:
assign hh = S[1] ?
(S[0] ?
A[15*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[14*C_DATA_WIDTH +: C_DATA_WIDTH] ) :
(S[0] ?
A[13*C_DATA_WIDTH +: C_DATA_WIDTH] :
A[12*C_DATA_WIDTH +: C_DATA_WIDTH] );
default:
assign hh = 0;
endcase
case (C_RATIO)
5, 6, 7, 8: begin
assign l = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_5_8
MUXF7 mux_s2_inst
(
.I0 (l[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[2]),
.O (o_i[bit_cnt])
);
end
end
9, 10, 11, 12: begin
assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_9_12
MUXF7 muxf_s2_low_inst
(
.I0 (ll[bit_cnt]),
.I1 (lh[bit_cnt]),
.S (S[2]),
.O (l[bit_cnt])
);
MUXF8 muxf_s3_inst
(
.I0 (l[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[3]),
.O (o_i[bit_cnt])
);
end
end
13,14,15,16: begin
assign ll = f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]);
assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_13_16
MUXF7 muxf_s2_low_inst
(
.I0 (ll[bit_cnt]),
.I1 (lh[bit_cnt]),
.S (S[2]),
.O (l[bit_cnt])
);
MUXF7 muxf_s2_hi_inst
(
.I0 (hl[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[2]),
.O (h[bit_cnt])
);
MUXF8 muxf_s3_inst
(
.I0 (l[bit_cnt]),
.I1 (h[bit_cnt]),
.S (S[3]),
.O (o_i[bit_cnt])
);
end
end
17: begin
assign ll = S[4] ? A[16*C_DATA_WIDTH +: C_DATA_WIDTH] : f_mux4(S[1:0], A[0 +: 4*C_DATA_WIDTH]); // 5-input mux
assign lh = f_mux4(S[1:0], A[4*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
assign hl = f_mux4(S[1:0], A[8*C_DATA_WIDTH +: 4*C_DATA_WIDTH]);
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : gen_mux_17
MUXF7 muxf_s2_low_inst
(
.I0 (ll[bit_cnt]),
.I1 (lh[bit_cnt]),
.S (S[2]),
.O (l[bit_cnt])
);
MUXF7 muxf_s2_hi_inst
(
.I0 (hl[bit_cnt]),
.I1 (hh[bit_cnt]),
.S (S[2]),
.O (h[bit_cnt])
);
MUXF8 muxf_s3_inst
(
.I0 (l[bit_cnt]),
.I1 (h[bit_cnt]),
.S (S[3]),
.O (o_i[bit_cnt])
);
end
end
default: // If RATIO > 17, use RTL
assign o_i = f_mux(S, A);
endcase
end // gen_fpga
endgenerate
endmodule
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Module Name: mask_to_zero
// Description: Selects active region from input data, bit reverses and masks LS
// bits to zero depending on the position of the leading zero identified
// by lzd.v
//////////////////////////////////////////////////////////////////////////////////
module mask_to_zero(
input clk,
input [14:0] data_in,
input [5:0] lz_pos,
output [14:0] data_out
);
wire [14:0] data_in_rev;
reg [14:0] data_in_r = 15'd0;
reg [14:0] data = 15'd0;
assign data_in_rev = {data_in[0], data_in[1], data_in[2], data_in[3], data_in[4],
data_in[5], data_in[6], data_in[7], data_in[8], data_in[9],
data_in[10], data_in[11], data_in[12], data_in[13], data_in[14]};
always @ (posedge clk) begin
data_in_r <= data_in_rev;
case (lz_pos)
6'd61: data <= data_in_r & 15'b111111111111111;
6'd60: data <= data_in_r & 15'b011111111111111;
6'd59: data <= data_in_r & 15'b101111111111111;
6'd58: data <= data_in_r & 15'b110111111111111;
6'd57: data <= data_in_r & 15'b111011111111111;
6'd56: data <= data_in_r & 15'b111101111111111;
6'd55: data <= data_in_r & 15'b111110111111111;
6'd54: data <= data_in_r & 15'b111111011111111;
6'd53: data <= data_in_r & 15'b111111101111111;
6'd52: data <= data_in_r & 15'b111111110111111;
6'd51: data <= data_in_r & 15'b111111111011111;
6'd50: data <= data_in_r & 15'b111111111101111;
6'd49: data <= data_in_r & 15'b111111111110111;
6'd48: data <= data_in_r & 15'b111111111111011;
6'd47: data <= data_in_r & 15'b111111111111101;
6'd46: data <= data_in_r & 15'b111111111111110;
default: data <= data_in_r & 15'b111111111111111;
endcase
end
assign data_out = data;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/23/2016 11:26:28 AM
// Design Name:
// Module Name: Sgf_Multiplication
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Sgf_Multiplication
//#(parameter SW = 24)
#(parameter SW = 54)
(
input wire clk,
input wire rst,
input wire load_b_i,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] sgf_result_o
);
//wire [SW-1:0] Data_A_i;
//wire [SW-1:0] Data_B_i;
//wire [2*(SW/2)-1:0] result_left_mult;
//wire [2*(SW/2+1)-1:0] result_right_mult;
wire [SW/2+1:0] result_A_adder;
//wire [SW/2+1:0] Q_result_A_adder;
wire [SW/2+1:0] result_B_adder;
//wire [SW/2+1:0] Q_result_B_adder;
//wire [2*(SW/2+2)-1:0] result_middle_mult;
wire [2*(SW/2)-1:0] Q_left;
wire [2*(SW/2+1)-1:0] Q_right;
wire [2*(SW/2+2)-1:0] Q_middle;
wire [2*(SW/2+2)-1:0] S_A;
wire [2*(SW/2+2)-1:0] S_B;
wire [4*(SW/2)+2:0] Result;
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 =2'b00;
assign zero2 =4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
wire [4*(SW/2)-1:0] sgf_r;
assign rightside1 = (SW/2) *1'b0;
assign rightside2 = (SW/2+1)*1'b0;
localparam half = SW/2;
//localparam level1=4;
//localparam level2=5;
////////////////////////////////////
generate
case (SW%2)
0:begin
//////////////////////////////////even//////////////////////////////////
//Multiplier for left side and right side
multiplier #(.W(SW/2)/*,.level(level1)*/) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(/*result_left_mult*/Q_left)
);
/*RegisterAdd #(.W(SW)) leftreg( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_left_mult),
.Q(Q_left)
);//*/
multiplier #(.W(SW/2)/*,.level(level1)*/) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(/*result_right_mult[2*(SW/2)-1:0]*/Q_right[2*(SW/2)-1:0])
);
/*RegisterAdd #(.W(SW)) rightreg( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_right_mult[2*(SW/2)-1:0]),
.Q(Q_right[2*(SW/2)-1:0])
);//*/
//Adders for middle
adder #(.W(SW/2)) A_operation (
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder[SW/2:0])
);
adder #(.W(SW/2)) B_operation (
.Data_A_i(Data_B_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder[SW/2:0])
);
//segmentation registers for 64 bits
/*RegisterAdd #(.W(SW/2+1)) preAreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_A_adder[SW/2:0]),
.Q(Q_result_A_adder[SW/2:0])
);//
RegisterAdd #(.W(SW/2+1)) preBreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_B_adder[SW/2:0]),
.Q(Q_result_B_adder[SW/2:0])
);//*/
//multiplication for middle
multiplier #(.W(SW/2+1)/*,.level(level1)*/) middle (
.clk(clk),
.Data_A_i(/*Q_result_A_adder[SW/2:0]*/result_A_adder[SW/2:0]),
.Data_B_i(/*Q_result_B_adder[SW/2:0]*/result_B_adder[SW/2:0]),
.Data_S_o(/*result_middle_mult[2*(SW/2)+1:0]*/Q_middle[2*(SW/2)+1:0])
);
//segmentation registers array
/*RegisterAdd #(.W(SW+2)) midreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_middle_mult[2*(SW/2)+1:0]),
.Q(Q_middle[2*(SW/2)+1:0])
);//*/
///Subtractors for middle
substractor #(.W(SW+2)) Subtr_1 (
.Data_A_i(/*result_middle_mult//*/Q_middle[2*(SW/2)+1:0]),
.Data_B_i({zero1, /*result_left_mult//*/Q_left}),
.Data_S_o(S_A[2*(SW/2)+1:0])
);
substractor #(.W(SW+2)) Subtr_2 (
.Data_A_i(S_A[2*(SW/2)+1:0]),
.Data_B_i({zero1, /*result_right_mult//*/Q_right[2*(SW/2)-1:0]}),
.Data_S_o(S_B[2*(SW/2)+1:0])
);
//Final adder
adder #(.W(4*(SW/2))) Final(
.Data_A_i({/*result_left_mult,result_right_mult*/Q_left,Q_right[2*(SW/2)-1:0]}),
.Data_B_i({S_B[2*(SW/2)+1:0],rightside1}),
.Data_S_o(Result[4*(SW/2):0])
);
//Final Register
RegisterAdd #(.W(4*(SW/2))) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[4*(SW/2)-1:0]),
.Q({sgf_result_o})
);
end
1:begin
//////////////////////////////////odd//////////////////////////////////
//Multiplier for left side and right side
multiplier #(.W(SW/2)/*,.level(level2)*/) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(/*result_left_mult*/Q_left)
);
/*RegisterAdd #(.W(2*(SW/2))) leftreg( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_left_mult),
.Q(Q_left)
);//*/
multiplier #(.W((SW/2)+1)/*,.level(level2)*/) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(/*result_right_mult*/Q_right)
);
/*RegisterAdd #(.W(2*((SW/2)+1))) rightreg( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_right_mult),
.Q(Q_right)
);//*/
//Adders for middle
adder #(.W(SW/2+1)) A_operation (
.Data_A_i({1'b0,Data_A_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder)
);
adder #(.W(SW/2+1)) B_operation (
.Data_A_i({1'b0,Data_B_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder)
);
//segmentation registers for 64 bits
/*RegisterAdd #(.W(SW/2+2)) preAreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_A_adder),
.Q(Q_result_A_adder)
);//
RegisterAdd #(.W(SW/2+2)) preBreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_B_adder),
.Q(Q_result_B_adder)
);//*/
//multiplication for middle
multiplier #(.W(SW/2+2)/*,.level(level2)*/) middle (
.clk(clk),
.Data_A_i(/*Q_result_A_adder*/result_A_adder),
.Data_B_i(/*Q_result_B_adder*/result_B_adder),
.Data_S_o(/*result_middle_mult*/Q_middle)
);
//segmentation registers array
/*RegisterAdd #(.W(2*((SW/2)+2))) midreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_middle_mult),
.Q(Q_middle)
);//*/
///Subtractors for middle
substractor #(.W(2*(SW/2+2))) Subtr_1 (
.Data_A_i(/*result_middle_mult//*/Q_middle),
.Data_B_i({zero2, /*result_left_mult//*/Q_left}),
.Data_S_o(S_A)
);
substractor #(.W(2*(SW/2+2))) Subtr_2 (
.Data_A_i(S_A),
.Data_B_i({zero1, /*result_right_mult//*/Q_right}),
.Data_S_o(S_B)
);
//Final adder
adder #(.W(4*(SW/2)+2)) Final(
.Data_A_i({/*result_left_mult,result_right_mult*/Q_left,Q_right}),
.Data_B_i({S_B,rightside2}),
.Data_S_o(Result[4*(SW/2)+2:0])
);
//Final Register
RegisterAdd #(.W(4*(SW/2)+2)) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[2*SW-1:0]),
.Q({sgf_result_o})
);
end
endcase
endgenerate
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003,2004 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Serial Control Bus from Cypress chip
module serial_io
( input master_clk,
input serial_clock,
input serial_data_in,
input enable,
input reset,
inout wire serial_data_out,
output reg [6:0] serial_addr,
output reg [31:0] serial_data,
output wire serial_strobe,
input wire [31:0] readback_0,
input wire [31:0] readback_1,
input wire [31:0] readback_2,
input wire [31:0] readback_3,
input wire [31:0] readback_4,
input wire [31:0] readback_5,
input wire [31:0] readback_6,
input wire [31:0] readback_7
);
reg is_read;
reg [7:0] ser_ctr;
reg write_done;
assign serial_data_out = is_read ? serial_data[31] : 1'bz;
always @(posedge serial_clock, posedge reset, negedge enable)
if(reset)
ser_ctr <= #1 8'd0;
else if(~enable)
ser_ctr <= #1 8'd0;
else if(ser_ctr == 39)
ser_ctr <= #1 8'd0;
else
ser_ctr <= #1 ser_ctr + 8'd1;
always @(posedge serial_clock, posedge reset, negedge enable)
if(reset)
is_read <= #1 1'b0;
else if(~enable)
is_read <= #1 1'b0;
else if((ser_ctr == 7)&&(serial_addr[6]==1))
is_read <= #1 1'b1;
always @(posedge serial_clock, posedge reset)
if(reset)
begin
serial_addr <= #1 7'b0;
serial_data <= #1 32'b0;
write_done <= #1 1'b0;
end
else if(~enable)
begin
//serial_addr <= #1 7'b0;
//serial_data <= #1 32'b0;
write_done <= #1 1'b0;
end
else
begin
if(~is_read && (ser_ctr == 39))
write_done <= #1 1'b1;
else
write_done <= #1 1'b0;
if(is_read & (ser_ctr==8))
case (serial_addr)
7'd1: serial_data <= #1 readback_0;
7'd2: serial_data <= #1 readback_1;
7'd3: serial_data <= #1 readback_2;
7'd4: serial_data <= #1 readback_3;
7'd5: serial_data <= #1 readback_4;
7'd6: serial_data <= #1 readback_5;
7'd7: serial_data <= #1 readback_6;
7'd8: serial_data <= #1 readback_7;
default: serial_data <= #1 32'd0;
endcase // case(serial_addr)
else if(ser_ctr >= 8)
serial_data <= #1 {serial_data[30:0],serial_data_in};
else if(ser_ctr < 8)
serial_addr <= #1 {serial_addr[5:0],serial_data_in};
end // else: !if(~enable)
reg enable_d1, enable_d2;
always @(posedge master_clk)
begin
enable_d1 <= #1 enable;
enable_d2 <= #1 enable_d1;
end
assign serial_strobe = enable_d2 & ~enable_d1;
endmodule // serial_io
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: reorder_queue_input.v
// Version: 1.00
// Verilog Standard: Verilog-2005
// Description: Input stage to the reorder-queue.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "trellis.vh"
`timescale 1ns / 1ps
module reorder_queue_input
#(parameter C_PCI_DATA_WIDTH = 9'd128,
parameter C_TAG_WIDTH = 5, // Number of outstanding requests
parameter C_TAG_DW_COUNT_WIDTH = 8,// Width of max count DWs per packet
parameter C_DATA_ADDR_STRIDE_WIDTH = 5,// Width of max num stored data addr positions per tag
parameter C_DATA_ADDR_WIDTH = 10, // Width of stored data address
// Local parameters
parameter C_PCI_DATA_WORD = C_PCI_DATA_WIDTH/32,
parameter C_PCI_DATA_WORD_WIDTH = clog2s(C_PCI_DATA_WORD),
parameter C_PCI_DATA_COUNT_WIDTH = clog2s(C_PCI_DATA_WORD+1),
parameter C_NUM_TAGS = 2**C_TAG_WIDTH)
(input CLK, // Clock
input RST, // Synchronous reset
input VALID, // Valid input packet
input [C_PCI_DATA_WIDTH-1:0] DATA, // Input packet payload data enable
input [(C_PCI_DATA_WIDTH/32)-1:0] DATA_EN, // Input packet payload data enable
input DATA_START_FLAG, // Input packet payload
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] DATA_START_OFFSET, // Input packet payload data enable count
input DATA_END_FLAG, // Input packet payload
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] DATA_END_OFFSET, // Input packet payload data enable count
input DONE, // Input packet done
input ERR, // Input packet has error
input [C_TAG_WIDTH-1:0] TAG, // Input packet tag (external tag)
output [C_NUM_TAGS-1:0] TAG_FINISH, // Bitmap of tags to finish
input [C_NUM_TAGS-1:0] TAG_CLEAR, // Bitmap of tags to clear
output [(C_DATA_ADDR_WIDTH*C_PCI_DATA_WORD)-1:0] STORED_DATA_ADDR, // Address of stored packet data for RAMs
output [C_PCI_DATA_WIDTH-1:0] STORED_DATA, // Stored packet data for RAMs
output [C_PCI_DATA_WORD-1:0] STORED_DATA_EN, // Stored packet data enable for RAMs
output PKT_VALID, // Valid flag for packet data
output [C_TAG_WIDTH-1:0] PKT_TAG, // Tag for stored packet data
output [C_TAG_DW_COUNT_WIDTH-1:0] PKT_WORDS, // Total count of stored packet payload in DWs
output PKT_WORDS_LTE1, // True if total count of stored packet payload is <= 4 DWs
output PKT_WORDS_LTE2, // True if total count of stored packet payload is <= 8 DWs
output PKT_DONE, // Stored packet done flag
output PKT_ERR); // Stored packet error flag
`include "functions.vh"
wire [C_PCI_DATA_COUNT_WIDTH-1:0] wDECount;
wire [C_PCI_DATA_WORD-1:0] wDE;
wire [C_PCI_DATA_WIDTH-1:0] wData;
wire [C_PCI_DATA_WORD-1:0] wStartMask;
wire [C_PCI_DATA_WORD-1:0] wEndMask;
reg [5:0] rValid=0;
reg [(C_PCI_DATA_WIDTH*5)-1:0] rData=0;
reg [(C_PCI_DATA_WORD*3)-1:0] rDE=0;
reg [(C_PCI_DATA_COUNT_WIDTH*2)-1:0] rDECount=0;
reg [5:0] rDone=0;
reg [5:0] rErr=0;
reg [(C_TAG_WIDTH*6)-1:0] rTag=0;
reg [C_PCI_DATA_WORD-1:0] rDEShift=0;
reg [(C_PCI_DATA_WORD*2)-1:0] rDEShifted=0;
reg rCountValid=0;
reg [C_NUM_TAGS-1:0] rCountRst=0;
reg [C_NUM_TAGS-1:0] rValidCount=0;
reg rUseCurrCount=0;
reg rUsePrevCount=0;
reg [C_TAG_DW_COUNT_WIDTH-1:0] rPrevCount=0;
reg [C_TAG_DW_COUNT_WIDTH-1:0] rCount=0;
wire [C_TAG_DW_COUNT_WIDTH-1:0] wCount;
wire [C_TAG_DW_COUNT_WIDTH-1:0] wCountClr = wCount & {C_TAG_DW_COUNT_WIDTH{rCountValid}};
reg [(C_TAG_DW_COUNT_WIDTH*3)-1:0] rWords=0;
reg [C_PCI_DATA_WORD_WIDTH-1:0] rShift=0;
reg [C_PCI_DATA_WORD_WIDTH-1:0] rShifted=0;
reg rPosValid=0;
reg [C_NUM_TAGS-1:0] rPosRst=0;
reg [C_NUM_TAGS-1:0] rValidPos=0;
reg rUseCurrPos=0;
reg rUsePrevPos=0;
reg [(C_DATA_ADDR_STRIDE_WIDTH*C_PCI_DATA_WORD)-1:0] rPrevPos=0;
reg [(C_DATA_ADDR_STRIDE_WIDTH*C_PCI_DATA_WORD)-1:0] rPosNow=0;
reg [(C_DATA_ADDR_STRIDE_WIDTH*C_PCI_DATA_WORD)-1:0] rPos=0;
wire [(C_DATA_ADDR_STRIDE_WIDTH*C_PCI_DATA_WORD)-1:0] wPos;
wire [(C_DATA_ADDR_STRIDE_WIDTH*C_PCI_DATA_WORD)-1:0] wPosClr = wPos & {C_DATA_ADDR_STRIDE_WIDTH*C_PCI_DATA_WORD{rPosValid}};
reg [(C_DATA_ADDR_WIDTH*C_PCI_DATA_WORD)-1:0] rAddr=0;
reg [(C_PCI_DATA_WORD_WIDTH+5)-1:0] rShiftUp=0;
reg [(C_PCI_DATA_WORD_WIDTH+5)-1:0] rShiftDown=0;
reg [C_DATA_ADDR_WIDTH-1:0] rBaseAddr=0;
reg [C_PCI_DATA_WIDTH-1:0] rDataShifted=0;
reg rLTE1Pkt=0;
reg rLTE2Pkt=0;
reg [C_NUM_TAGS-1:0] rFinish=0;
wire [31:0] wZero=32'd0;
integer i;
assign wDE = DATA_EN >> (DATA_START_FLAG ? DATA_START_OFFSET : 0);/* TODO: Could move this to the RX Engine*/
assign wData = DATA >> (DATA_START_FLAG ? {DATA_START_OFFSET,5'b0} : 0);
generate
if(C_PCI_DATA_WIDTH == 32) begin
assign wDECount = VALID ? 1 : 0;
end
if(C_PCI_DATA_WIDTH == 64) begin
assign wDECount = VALID ? DATA_EN[1] + DATA_EN[0] : 0;
end
if(C_PCI_DATA_WIDTH == 128) begin
assign wDECount = VALID ? DATA_EN[3] + DATA_EN[2] + DATA_EN[1] + DATA_EN[0] : 0;
end
if(C_PCI_DATA_WIDTH == 256) begin
assign wDECount = VALID ? DATA_EN[7] + DATA_EN[6] + DATA_EN[5] + DATA_EN[4] +
DATA_EN[3] + DATA_EN[2] + DATA_EN[1] + DATA_EN[0] : 0;
end
endgenerate
assign TAG_FINISH = rFinish;
assign STORED_DATA_ADDR = rAddr;
assign STORED_DATA = rDataShifted;
assign STORED_DATA_EN = rDEShifted[1*C_PCI_DATA_WORD +:C_PCI_DATA_WORD];
assign PKT_VALID = rValid[5];
assign PKT_TAG = rTag[5*C_TAG_WIDTH +:C_TAG_WIDTH];
assign PKT_WORDS = rWords[2*C_TAG_DW_COUNT_WIDTH +:C_TAG_DW_COUNT_WIDTH];
assign PKT_WORDS_LTE1 = rLTE1Pkt;
assign PKT_WORDS_LTE2 = rLTE2Pkt;
assign PKT_DONE = rDone[5];
assign PKT_ERR = rErr[5];
// Pipeline the input and intermediate data
always @ (posedge CLK) begin
if (RST) begin
rValid <= #1 0;
rTag <= #1 0;
end
else begin
rValid <= #1 (rValid<<1) | VALID;
rTag <= #1 (rTag<<C_TAG_WIDTH) | TAG;
end
rData <= #1 (rData<<C_PCI_DATA_WIDTH) | wData;
rDE <= #1 (rDE<<C_PCI_DATA_WORD) | wDE;//DATA_EN;
rDECount <= #1 (rDECount<<C_PCI_DATA_COUNT_WIDTH) | wDECount;//DATA_EN_COUNT;
rDone <= #1 (rDone<<1) | DONE;
rErr <= #1 (rErr<<1) | ERR;
rDEShifted <= #1 (rDEShifted<<C_PCI_DATA_WORD) | rDEShift;
rWords <= #1 (rWords<<C_TAG_DW_COUNT_WIDTH) | rCount;
rShifted <= #1 (rShifted<<C_PCI_DATA_WORD_WIDTH) | rShift;
end
// Input processing pipeline
always @ (posedge CLK) begin
// STAGE 0: Register the incoming data
// STAGE 1: Request existing count from RAM
// To cover the gap b/t reads and writes to RAM, next cycle we might need
// to use the existing or even the previous rCount value if the tags match.
rUseCurrCount <= #1 (rTag[0*C_TAG_WIDTH +:C_TAG_WIDTH] == rTag[1*C_TAG_WIDTH +:C_TAG_WIDTH] && rValid[1]);
rUsePrevCount <= #1 (rTag[0*C_TAG_WIDTH +:C_TAG_WIDTH] == rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH] && rValid[2]);
rPrevCount <= #1 rCount;
// See if we need to reset the count
rCountValid <= #1 (RST ? 1'd0 : rCountRst>>rTag[0*C_TAG_WIDTH +:C_TAG_WIDTH]);
rValidCount <= #1 (RST ? 0 : rValid[0]<<rTag[0*C_TAG_WIDTH +:C_TAG_WIDTH]);
// STAGE 2: Calculate new count (saves next cycle)
if (rUseCurrCount) begin
rShift <= #1 rCount[0 +:C_PCI_DATA_WORD_WIDTH];
rCount <= #1 rCount + rDECount[1*C_PCI_DATA_COUNT_WIDTH +:C_PCI_DATA_COUNT_WIDTH];
end
else if (rUsePrevCount) begin
rShift <= #1 rPrevCount[0 +:C_PCI_DATA_WORD_WIDTH];
rCount <= #1 rPrevCount + rDECount[1*C_PCI_DATA_COUNT_WIDTH +:C_PCI_DATA_COUNT_WIDTH];
end
else begin
rShift <= #1 wCountClr[0 +:C_PCI_DATA_WORD_WIDTH];
rCount <= #1 wCountClr + rDECount[1*C_PCI_DATA_COUNT_WIDTH +:C_PCI_DATA_COUNT_WIDTH];
end
// STAGE 3: Request existing positions from RAM
// Barrel shift the DE
rDEShift <= #1 (rDE[2*C_PCI_DATA_WORD +:C_PCI_DATA_WORD]<<rShift) |
(rDE[2*C_PCI_DATA_WORD +:C_PCI_DATA_WORD]>>(C_PCI_DATA_WORD-rShift));
// To cover the gap b/t reads and writes to RAM, next cycle we might need
// to use the existing or even the previous rPos values if the tags match.
rUseCurrPos <= #1 (rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH] == rTag[3*C_TAG_WIDTH +:C_TAG_WIDTH] && rValid[3]);
rUsePrevPos <= #1 (rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH] == rTag[4*C_TAG_WIDTH +:C_TAG_WIDTH] && rValid[4]);
for (i = 0; i < C_PCI_DATA_WORD; i = i + 1) begin
rPrevPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1
(RST ? wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] : rPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH]);
end
// See if we need to reset the positions
rPosValid <= #1 (RST ? 1'd0 : rPosRst>>rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH]);
rValidPos <= #1 (RST ? 0 : rValid[2]<<rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH]);
// STAGE 4: Calculate new positions (saves next cycle)
if (rUseCurrPos) begin
for (i = 0; i < C_PCI_DATA_WORD; i = i + 1) begin
rPosNow[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1
(RST ?
wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] :
rPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH]);
rPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1
(RST ?
wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] :
rPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] + rDEShift[i]);
end
end
else if (rUsePrevPos) begin
for (i = 0; i < C_PCI_DATA_WORD; i = i + 1) begin
rPosNow[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1
(RST ?
wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] :
rPrevPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH]);
rPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1
(RST ?
wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] :
rPrevPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] + rDEShift[i]);
end
end
else begin
for (i = 0; i < C_PCI_DATA_WORD; i = i + 1) begin
rPosNow[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1
(RST ?
wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] :
wPosClr[i*C_DATA_ADDR_STRIDE_WIDTH +:C_DATA_ADDR_STRIDE_WIDTH]);
rPos[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] <= #1
(RST ?
wZero[C_DATA_ADDR_STRIDE_WIDTH-1:0] :
wPosClr[i*C_DATA_ADDR_STRIDE_WIDTH +:C_DATA_ADDR_STRIDE_WIDTH] + rDEShift[i]);
end
end
// Calculate the base address offset
rBaseAddr <= #1 rTag[3*C_TAG_WIDTH +:C_TAG_WIDTH]<<C_DATA_ADDR_STRIDE_WIDTH;
// Calculate the shift amounts for barrel shifting payload data
rShiftUp <= #1 rShifted[0*C_PCI_DATA_WORD_WIDTH +:C_PCI_DATA_WORD_WIDTH]<<5;
rShiftDown <= #1 (C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0] - rShifted[0*C_PCI_DATA_WORD_WIDTH +:C_PCI_DATA_WORD_WIDTH])<<5;
// STAGE 5: Prepare to write data, final info
for (i = 0; i < C_PCI_DATA_WORD; i = i + 1) begin
rAddr[C_DATA_ADDR_WIDTH*i +:C_DATA_ADDR_WIDTH] <= #1
rPosNow[C_DATA_ADDR_STRIDE_WIDTH*i +:C_DATA_ADDR_STRIDE_WIDTH] + rBaseAddr;
end
rDataShifted <= #1 (rData[4*C_PCI_DATA_WIDTH +:C_PCI_DATA_WIDTH]<<rShiftUp) |
(rData[4*C_PCI_DATA_WIDTH +:C_PCI_DATA_WIDTH]>>rShiftDown);
rLTE1Pkt <= #1 (rWords[1*C_TAG_DW_COUNT_WIDTH +:C_TAG_DW_COUNT_WIDTH] <= C_PCI_DATA_WORD);
rLTE2Pkt <= #1 (rWords[1*C_TAG_DW_COUNT_WIDTH +:C_TAG_DW_COUNT_WIDTH] <= (C_PCI_DATA_WORD*2));
rFinish <= #1 (rValid[4] & (rDone[4] | rErr[4]))<<rTag[4*C_TAG_WIDTH +:C_TAG_WIDTH];
// STAGE 6: Write data, final info
end
// Reset the count and positions when needed
always @ (posedge CLK) begin
if (RST) begin
rCountRst <= #1 0;
rPosRst <= #1 0;
end
else begin
rCountRst <= #1 (rCountRst | rValidCount) & ~TAG_CLEAR;
rPosRst <= #1 (rPosRst | rValidPos) & ~TAG_CLEAR;
end
end
// RAM for counts
(* RAM_STYLE="DISTRIBUTED" *)
ram_1clk_1w_1r
#(
.C_RAM_WIDTH(C_TAG_DW_COUNT_WIDTH),
.C_RAM_DEPTH(C_NUM_TAGS))
countRam
(
.CLK(CLK),
.ADDRA(rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH]),
.WEA(rValid[2]),
.DINA(rCount),
.ADDRB(rTag[0*C_TAG_WIDTH +:C_TAG_WIDTH]),
.DOUTB(wCount)
);
// RAM for positions
(* RAM_STYLE="DISTRIBUTED" *)
ram_1clk_1w_1r
#(
.C_RAM_WIDTH(C_PCI_DATA_WORD*C_DATA_ADDR_STRIDE_WIDTH),
.C_RAM_DEPTH(C_NUM_TAGS))
posRam
(
.CLK(CLK),
.ADDRA(rTag[4*C_TAG_WIDTH +:C_TAG_WIDTH]),
.WEA(rValid[4]),
.DINA(rPos),
.ADDRB(rTag[2*C_TAG_WIDTH +:C_TAG_WIDTH]),
.DOUTB(wPos)
);
endmodule
// Local Variables:
// verilog-library-directories:("." "registers/" "../common/")
// End:
|
`include "hi_simulate.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
mod_type - modulation type
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_hi_simulate;
reg pck0;
reg [7:0] adc_d;
reg mod_type;
wire pwr_lo;
wire adc_clk;
reg ck_1356meg;
reg ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
hi_simulate #(5,200) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.mod_type(mod_type)
);
integer idx, i;
// main clock
always #5 begin
ck_1356megb = !ck_1356megb;
ck_1356meg = ck_1356megb;
end
always begin
@(negedge adc_clk) ;
adc_d = $random;
end
//crank DUT
task crank_dut;
begin
@(negedge ssp_clk) ;
ssp_dout = $random;
end
endtask
initial begin
// init inputs
ck_1356megb = 0;
// random values
adc_d = 0;
ssp_dout=1;
// shallow modulation off
mod_type=0;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
// shallow modulation on
mod_type=1;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
//////////////////////////////////////////////////////////////////////////////////
// SCFIFO_128x64_withCount for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: Single clock FIFO (128 width, 64 depth) wrapper
// Module Name: SCFIFO_128x64_withCount
// File Name: SCFIFO_128x64_withCount.v
//
// Version: v1.0.0
//
// Description: Standard FIFO, 1 cycle data out latency
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module SCFIFO_128x64_withCount
(
input iClock ,
input iReset ,
input [127:0] iPushData ,
input iPushEnable ,
output oIsFull ,
output [127:0] oPopData ,
input iPopEnable ,
output oIsEmpty ,
output [5:0] oDataCount
);
DPBSCFIFO128x64WC
Inst_DPBSCFIFO128x64WC
(
.clk (iClock ),
.srst (iReset ),
.din (iPushData ),
.wr_en (iPushEnable ),
.full (oIsFull ),
.dout (oPopData ),
.rd_en (iPopEnable ),
.empty (oIsEmpty ),
.data_count (oDataCount )
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2017 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [3:0] in = crc[3:0];
wire clken = crc[4];
wire rstn = !(cyc < 20 || (crc[11:8]==0));
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] ff_out; // From test of Test.v
wire [3:0] fg_out; // From test of Test.v
wire [3:0] fh_out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.ff_out (ff_out[3:0]),
.fg_out (fg_out[3:0]),
.fh_out (fh_out[3:0]),
// Inputs
.clk (clk),
.clken (clken),
.rstn (rstn),
.in (in[3:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {52'h0, ff_out, fg_out, fh_out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc<10) begin
sum <= '0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h77979747fd1b3a5a
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test
(/*AUTOARG*/
// Outputs
ff_out, fg_out, fh_out,
// Inputs
clk, clken, rstn, in
);
input clk;
input clken;
input rstn;
input [3:0] in;
output reg [3:0] ff_out;
reg [3:0] ff_10;
reg [3:0] ff_11;
reg [3:0] ff_12;
reg [3:0] ff_13;
always @(posedge clk) begin
if ((rstn == 0)) begin
ff_10 <= 0;
ff_11 <= 0;
ff_12 <= 0;
ff_13 <= 0;
end
else begin
ff_10 <= in;
ff_11 <= ff_10;
ff_12 <= ff_11;
ff_13 <= ff_12;
ff_out <= ff_13;
end
end
output reg [3:0] fg_out;
reg [3:0] fg_10;
reg [3:0] fg_11;
reg [3:0] fg_12;
reg [3:0] fg_13;
always @(posedge clk) begin
if (clken) begin
if ((rstn == 0)) begin
fg_10 <= 0;
fg_11 <= 0;
fg_12 <= 0;
fg_13 <= 0;
end
else begin
fg_10 <= in;
fg_11 <= fg_10;
fg_12 <= fg_11;
fg_13 <= fg_12;
fg_out <= fg_13;
end
end
end
output reg [3:0] fh_out;
reg [3:0] fh_10;
reg [3:0] fh_11;
reg [3:0] fh_12;
reg [3:0] fh_13;
always @(posedge clk) begin
if ((rstn == 0)) begin
fh_10 <= 0;
fh_11 <= 0;
fh_12 <= 0;
fh_13 <= 0;
end
else begin
if (clken) begin
fh_10 <= in;
fh_11 <= fh_10;
fh_12 <= fh_11;
fh_13[3:1] <= fh_12[3:1];
fh_13[0] <= fh_12[0];
fh_out <= fh_13;
end
end
end
endmodule
|
`timescale 1ns / 1ps
`include "constants.vh"
module tb_Absorb;
reg [263:0] state_in;
reg clk;
reg rst;
reg en;
reg [175:0] data;
wire [263:0] state_out;
wire rdy;
Absorb uut (
.state_in(state_in),
.state_out(state_out),
.clk(clk),
.rst(rst),
.en(en),
.rdy(rdy)
);
integer i;
integer databitlen;
integer counter;
initial begin
databitlen = 176;
data = "Hello WorldHello World";
counter = 0;
state_in = 0;
clk = 0;
rst = 1;
en = 0;
#100;
rst = 0;
$display("[INITIALIZING]");
// for (i=0; i<`nSBox; i=i+1) begin
// state_in = state_in | i<<(i*8);
// end
state_in = 0;
en = 1;
while (databitlen >= `rate) begin
$display("counter %d", counter);
for (i = 0; i < `R_SizeInBytes*8; i = i+8) begin
state_in[i+:8] = state_in[i+:8] ^ data[databitlen - (i+8) +:8];
$display("data: %d %h", databitlen - (i+8), data[databitlen - (i+8) +:8]);
end
$display("state in: %h", state_in);
$display("data: %h", data);
repeat(70*135) begin
#5;
end
if (rdy) begin
state_in = state_out;
$display("state_out: %h", state_out);
counter = counter + 1;
databitlen = databitlen - `rate;
end
end
end
always begin
#5; clk = !clk;
end
always @ (rdy) begin
if (rdy == 1) begin
state_in = state_out;
$display("state_out: %h", state_out);
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/17/2016 05:20:59 PM
// Design Name:
// Module Name: Priority_Codec_64
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Priority_Codec_64(
input wire [54:0] Data_Dec_i,
output reg [5:0] Data_Bin_o
);
always @(Data_Dec_i)
begin
Data_Bin_o=6'b000000;
if(~Data_Dec_i[54]) begin Data_Bin_o = 6'b000000;//0
end else if(~Data_Dec_i[53]) begin Data_Bin_o = 6'b000001;//1
end else if(~Data_Dec_i[52]) begin Data_Bin_o = 6'b000010;//2
end else if(~Data_Dec_i[51]) begin Data_Bin_o = 6'b000011;//3
end else if(~Data_Dec_i[50]) begin Data_Bin_o = 6'b000100;//4
end else if(~Data_Dec_i[49]) begin Data_Bin_o = 6'b000101;//5
end else if(~Data_Dec_i[48]) begin Data_Bin_o = 6'b000110;//6
end else if(~Data_Dec_i[47]) begin Data_Bin_o = 6'b000111;//7
end else if(~Data_Dec_i[46]) begin Data_Bin_o = 6'b001000;//8
end else if(~Data_Dec_i[45]) begin Data_Bin_o = 6'b001001;//9
end else if(~Data_Dec_i[44]) begin Data_Bin_o = 6'b001010;//10
end else if(~Data_Dec_i[43]) begin Data_Bin_o = 6'b001011;//11
end else if(~Data_Dec_i[42]) begin Data_Bin_o = 6'b001100;//12
end else if(~Data_Dec_i[41]) begin Data_Bin_o = 6'b001101;//13
end else if(~Data_Dec_i[40]) begin Data_Bin_o = 6'b001110;//14
end else if(~Data_Dec_i[39]) begin Data_Bin_o = 6'b001111;//15
end else if(~Data_Dec_i[38]) begin Data_Bin_o = 6'b010000;//16
end else if(~Data_Dec_i[37]) begin Data_Bin_o = 6'b010001;//17
end else if(~Data_Dec_i[36]) begin Data_Bin_o = 6'b010010;//18
end else if(~Data_Dec_i[35]) begin Data_Bin_o = 6'b010011;//19
end else if(~Data_Dec_i[34]) begin Data_Bin_o = 6'b010100;//20
end else if(~Data_Dec_i[33]) begin Data_Bin_o = 6'b010101;//21
end else if(~Data_Dec_i[32]) begin Data_Bin_o = 6'b010110;//22
end else if(~Data_Dec_i[31]) begin Data_Bin_o = 6'b010111;//23
end else if(~Data_Dec_i[30]) begin Data_Bin_o = 6'b011000;//24
end else if(~Data_Dec_i[29]) begin Data_Bin_o = 6'b010101;//25
end else if(~Data_Dec_i[28]) begin Data_Bin_o = 6'b010110;//26
end else if(~Data_Dec_i[27]) begin Data_Bin_o = 6'b010111;//27
end else if(~Data_Dec_i[26]) begin Data_Bin_o = 6'b011000;//28
end else if(~Data_Dec_i[25]) begin Data_Bin_o = 6'b011001;//29
end else if(~Data_Dec_i[24]) begin Data_Bin_o = 6'b011010;//30
end else if(~Data_Dec_i[23]) begin Data_Bin_o = 6'b011011;//31
end else if(~Data_Dec_i[22]) begin Data_Bin_o = 6'b011100;//32
end else if(~Data_Dec_i[21]) begin Data_Bin_o = 6'b011101;//33
end else if(~Data_Dec_i[20]) begin Data_Bin_o = 6'b011110;//34
end else if(~Data_Dec_i[19]) begin Data_Bin_o = 6'b011111;//35
end else if(~Data_Dec_i[18]) begin Data_Bin_o = 6'b100000;//36
end else if(~Data_Dec_i[17]) begin Data_Bin_o = 6'b100001;//37
end else if(~Data_Dec_i[16]) begin Data_Bin_o = 6'b100010;//38
end else if(~Data_Dec_i[15]) begin Data_Bin_o = 6'b100011;//39
end else if(~Data_Dec_i[14]) begin Data_Bin_o = 6'b100100;//40
end else if(~Data_Dec_i[13]) begin Data_Bin_o = 6'b100101;//41
end else if(~Data_Dec_i[12]) begin Data_Bin_o = 6'b100110;//42
end else if(~Data_Dec_i[11]) begin Data_Bin_o = 6'b100111;//43
end else if(~Data_Dec_i[10]) begin Data_Bin_o = 6'b101000;//44
end else if(~Data_Dec_i[9]) begin Data_Bin_o = 6'b101001;//45
end else if(~Data_Dec_i[8]) begin Data_Bin_o = 6'b101010;//46
end else if(~Data_Dec_i[7]) begin Data_Bin_o = 6'b101011;//47
end else if(~Data_Dec_i[6]) begin Data_Bin_o = 6'b101100;//48
end else if(~Data_Dec_i[5]) begin Data_Bin_o = 6'b101101;//49
end else if(~Data_Dec_i[4]) begin Data_Bin_o = 6'b101110;//50
end else if(~Data_Dec_i[3]) begin Data_Bin_o = 6'b101111;//51
end else if(~Data_Dec_i[2]) begin Data_Bin_o = 6'b110000;//52
end else if(~Data_Dec_i[1]) begin Data_Bin_o = 6'b110001;//53
end else if(~Data_Dec_i[0]) begin Data_Bin_o = 6'b110010;//54
end else begin Data_Bin_o = 6'b000000;//zero value
end
end
endmodule |
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// mpram_wrp.v: Multiported-RAM synthesis wrapper //
// //
// Author: Ameer M. Abdelhadi ([email protected], [email protected]) //
// SRAM-based Multi-ported RAMs; University of British Columbia (UBC), March 2013 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
// configure architectural parameters
`include "config.vh"
module mpram_wrp
#( parameter MEMD = `MEMD , // memory depth
parameter DATAW = `DATAW , // data width
parameter nRPORTS = `nRPORTS, // number of reading ports
parameter nWPORTS = `nWPORTS, // number of writing ports
parameter TYPE = `TYPE , // implementation type: REG, XOR, LVTREG, LVTBIN, LVT1HT, AUTO
parameter BYP = `BYP , // Bypassing type: NON, WAW, RAW, RDW
parameter IFILE = "" // initialization file, optional
)( input clk , // clock
input [nWPORTS-1:0 ] WEnb , // write enable for each writing port
input [`log2(MEMD)*nWPORTS-1:0] WAddr, // write addresses - packed from nWPORTS write ports
input [DATAW *nWPORTS-1:0] WData, // write data - packed from nWPORTS read ports
input [`log2(MEMD)*nRPORTS-1:0] RAddr, // read addresses - packed from nRPORTS read ports
output wire [DATAW *nRPORTS-1:0] RData); // read data - packed from nRPORTS read ports
// instantiate a multiported-RAM
mpram #( .MEMD (MEMD ), // positive integer: memory depth
.DATAW (DATAW ), // positive integer: data width
.nRPORTS(nRPORTS), // positive integer: number of reading ports
.nWPORTS(nWPORTS), // positive integer: number of writing ports
.TYPE (TYPE ), // text: multi-port RAM implementation type: "AUTO", "REG", "XOR", "LVTREG", "LVTBIN", or "LVT1HT"
// AUTO : Choose automatically based on the design parameters
// REG : Register-based multi-ported RAM
// XOR : XOR-based nulti-ported RAM
// LVTREG: Register-based LVT multi-ported RAM
// LVTBIN: Binary-coded I-LVT-based multi-ported RAM
// LVT1HT: Onehot-coded I-LVT-based multi-ported RAM
.BYP (BYP ), // text: Bypassing type: "NON", "WAW", "RAW", or "RDW"
// WAW: Allow Write-After-Write (need to bypass feedback ram)
// RAW: New data for Read-after-Write (need to bypass output ram)
// RDW: New data for Read-During-Write
.IFILE ("" )) // text: initializtion file, optional
mpram_inst ( .clk (clk ), // clock
.WEnb (WEnb ), // write enable for each writing port - input : [nWPORTS-1:0 ]
.WAddr (WAddr ), // write addresses - packed from nWPORTS write ports - input : [`log2(MEMD)*nWPORTS-1:0]
.WData (WData ), // write data - packed from nRPORTS read ports - output: [DATAW *nWPORTS-1:0]
.RAddr (RAddr ), // read addresses - packed from nRPORTS read ports - input : [`log2(MEMD)*nRPORTS-1:0]
.RData (RData )); // read data - packed from nRPORTS read ports - output: [DATAW *nRPORTS-1:0]
endmodule
|
// megafunction wizard: %ALTFP_COMPARE%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altfp_compare
// ============================================================
// File Name: float_cmp.v
// Megafunction Name(s):
// altfp_compare
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 178 05/31/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altfp_compare CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" PIPELINE=1 WIDTH_EXP=8 WIDTH_MAN=23 ageb aleb clk_en clock dataa datab
//VERSION_BEGIN 12.0 cbx_altfp_compare 2012:05:31:20:23:38:SJ cbx_cycloneii 2012:05:31:20:23:38:SJ cbx_lpm_add_sub 2012:05:31:20:23:38:SJ cbx_lpm_compare 2012:05:31:20:23:38:SJ cbx_mgl 2012:05:31:20:24:43:SJ cbx_stratix 2012:05:31:20:23:38:SJ cbx_stratixii 2012:05:31:20:23:38:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = lpm_compare 4 reg 2
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module float_cmp_altfp_compare_5ac
(
ageb,
aleb,
clk_en,
clock,
dataa,
datab) ;
output ageb;
output aleb;
input clk_en;
input clock;
input [31:0] dataa;
input [31:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg out_ageb_w_dffe3;
reg out_aleb_w_dffe3;
wire wire_cmpr1_aeb;
wire wire_cmpr1_agb;
wire wire_cmpr2_aeb;
wire wire_cmpr2_agb;
wire wire_cmpr3_aeb;
wire wire_cmpr3_agb;
wire wire_cmpr4_aeb;
wire wire_cmpr4_agb;
wire aclr;
wire aligned_dataa_sign_adjusted_dffe2_wi;
wire aligned_dataa_sign_adjusted_dffe2_wo;
wire aligned_dataa_sign_adjusted_w;
wire aligned_dataa_sign_dffe1_wi;
wire aligned_dataa_sign_dffe1_wo;
wire aligned_dataa_sign_w;
wire [30:0] aligned_dataa_w;
wire aligned_datab_sign_adjusted_dffe2_wi;
wire aligned_datab_sign_adjusted_dffe2_wo;
wire aligned_datab_sign_adjusted_w;
wire aligned_datab_sign_dffe1_wi;
wire aligned_datab_sign_dffe1_wo;
wire aligned_datab_sign_w;
wire [30:0] aligned_datab_w;
wire both_inputs_zero;
wire both_inputs_zero_dffe2_wi;
wire both_inputs_zero_dffe2_wo;
wire exp_a_all_one_dffe1_wi;
wire exp_a_all_one_dffe1_wo;
wire [7:0] exp_a_all_one_w;
wire exp_a_not_zero_dffe1_wi;
wire exp_a_not_zero_dffe1_wo;
wire [7:0] exp_a_not_zero_w;
wire [3:0] exp_aeb;
wire [3:0] exp_aeb_tmp_w;
wire exp_aeb_w;
wire exp_aeb_w_dffe2_wi;
wire exp_aeb_w_dffe2_wo;
wire [3:0] exp_agb;
wire [3:0] exp_agb_tmp_w;
wire exp_agb_w;
wire exp_agb_w_dffe2_wi;
wire exp_agb_w_dffe2_wo;
wire exp_b_all_one_dffe1_wi;
wire exp_b_all_one_dffe1_wo;
wire [7:0] exp_b_all_one_w;
wire exp_b_not_zero_dffe1_wi;
wire exp_b_not_zero_dffe1_wo;
wire [7:0] exp_b_not_zero_w;
wire [2:0] exp_eq_grp;
wire [3:0] exp_eq_gt_grp;
wire flip_outputs_dffe2_wi;
wire flip_outputs_dffe2_wo;
wire flip_outputs_w;
wire input_dataa_nan_dffe2_wi;
wire input_dataa_nan_dffe2_wo;
wire input_dataa_nan_w;
wire input_dataa_zero_w;
wire input_datab_nan_dffe2_wi;
wire input_datab_nan_dffe2_wo;
wire input_datab_nan_w;
wire input_datab_zero_w;
wire [1:0] man_a_not_zero_dffe1_wi;
wire [1:0] man_a_not_zero_dffe1_wo;
wire [1:0] man_a_not_zero_merge_w;
wire [22:0] man_a_not_zero_w;
wire [1:0] man_b_not_zero_dffe1_wi;
wire [1:0] man_b_not_zero_dffe1_wo;
wire [1:0] man_b_not_zero_merge_w;
wire [22:0] man_b_not_zero_w;
wire out_aeb_w;
wire out_agb_w;
wire out_ageb_dffe3_wi;
wire out_ageb_dffe3_wo;
wire out_ageb_w;
wire out_alb_w;
wire out_aleb_dffe3_wi;
wire out_aleb_dffe3_wo;
wire out_aleb_w;
wire out_unordered_w;
// synopsys translate_off
initial
out_ageb_w_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) out_ageb_w_dffe3 <= 1'b0;
else if (clk_en == 1'b1) out_ageb_w_dffe3 <= out_ageb_dffe3_wi;
// synopsys translate_off
initial
out_aleb_w_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) out_aleb_w_dffe3 <= 1'b0;
else if (clk_en == 1'b1) out_aleb_w_dffe3 <= out_aleb_dffe3_wi;
lpm_compare cmpr1
(
.aeb(wire_cmpr1_aeb),
.agb(wire_cmpr1_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.dataa(aligned_dataa_w[30:23]),
.datab(aligned_datab_w[30:23])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cmpr1.lpm_representation = "UNSIGNED",
cmpr1.lpm_width = 8,
cmpr1.lpm_type = "lpm_compare";
lpm_compare cmpr2
(
.aeb(wire_cmpr2_aeb),
.agb(wire_cmpr2_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.dataa(aligned_dataa_w[22:15]),
.datab(aligned_datab_w[22:15])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cmpr2.lpm_representation = "UNSIGNED",
cmpr2.lpm_width = 8,
cmpr2.lpm_type = "lpm_compare";
lpm_compare cmpr3
(
.aeb(wire_cmpr3_aeb),
.agb(wire_cmpr3_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.dataa(aligned_dataa_w[14:7]),
.datab(aligned_datab_w[14:7])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cmpr3.lpm_representation = "UNSIGNED",
cmpr3.lpm_width = 8,
cmpr3.lpm_type = "lpm_compare";
lpm_compare cmpr4
(
.aeb(wire_cmpr4_aeb),
.agb(wire_cmpr4_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.dataa(aligned_dataa_w[6:0]),
.datab(aligned_datab_w[6:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cmpr4.lpm_representation = "UNSIGNED",
cmpr4.lpm_width = 7,
cmpr4.lpm_type = "lpm_compare";
assign
aclr = 1'b0,
ageb = out_ageb_dffe3_wo,
aleb = out_aleb_dffe3_wo,
aligned_dataa_sign_adjusted_dffe2_wi = aligned_dataa_sign_adjusted_w,
aligned_dataa_sign_adjusted_dffe2_wo = aligned_dataa_sign_adjusted_dffe2_wi,
aligned_dataa_sign_adjusted_w = (aligned_dataa_sign_dffe1_wo & (~ input_dataa_zero_w)),
aligned_dataa_sign_dffe1_wi = aligned_dataa_sign_w,
aligned_dataa_sign_dffe1_wo = aligned_dataa_sign_dffe1_wi,
aligned_dataa_sign_w = dataa[31],
aligned_dataa_w = {dataa[30:0]},
aligned_datab_sign_adjusted_dffe2_wi = aligned_datab_sign_adjusted_w,
aligned_datab_sign_adjusted_dffe2_wo = aligned_datab_sign_adjusted_dffe2_wi,
aligned_datab_sign_adjusted_w = (aligned_datab_sign_dffe1_wo & (~ input_datab_zero_w)),
aligned_datab_sign_dffe1_wi = aligned_datab_sign_w,
aligned_datab_sign_dffe1_wo = aligned_datab_sign_dffe1_wi,
aligned_datab_sign_w = datab[31],
aligned_datab_w = {datab[30:0]},
both_inputs_zero = (input_dataa_zero_w & input_datab_zero_w),
both_inputs_zero_dffe2_wi = both_inputs_zero,
both_inputs_zero_dffe2_wo = both_inputs_zero_dffe2_wi,
exp_a_all_one_dffe1_wi = exp_a_all_one_w[7],
exp_a_all_one_dffe1_wo = exp_a_all_one_dffe1_wi,
exp_a_all_one_w = {(dataa[30] & exp_a_all_one_w[6]), (dataa[29] & exp_a_all_one_w[5]), (dataa[28] & exp_a_all_one_w[4]), (dataa[27] & exp_a_all_one_w[3]), (dataa[26] & exp_a_all_one_w[2]), (dataa[25] & exp_a_all_one_w[1]), (dataa[24] & exp_a_all_one_w[0]), dataa[23]},
exp_a_not_zero_dffe1_wi = exp_a_not_zero_w[7],
exp_a_not_zero_dffe1_wo = exp_a_not_zero_dffe1_wi,
exp_a_not_zero_w = {(dataa[30] | exp_a_not_zero_w[6]), (dataa[29] | exp_a_not_zero_w[5]), (dataa[28] | exp_a_not_zero_w[4]), (dataa[27] | exp_a_not_zero_w[3]), (dataa[26] | exp_a_not_zero_w[2]), (dataa[25] | exp_a_not_zero_w[1]), (dataa[24] | exp_a_not_zero_w[0]), dataa[23]},
exp_aeb = {wire_cmpr4_aeb, wire_cmpr3_aeb, wire_cmpr2_aeb, wire_cmpr1_aeb},
exp_aeb_tmp_w = {(exp_aeb[3] & exp_aeb_tmp_w[2]), (exp_aeb[2] & exp_aeb_tmp_w[1]), (exp_aeb[1] & exp_aeb_tmp_w[0]), exp_aeb[0]},
exp_aeb_w = exp_aeb_tmp_w[3],
exp_aeb_w_dffe2_wi = exp_aeb_w,
exp_aeb_w_dffe2_wo = exp_aeb_w_dffe2_wi,
exp_agb = {wire_cmpr4_agb, wire_cmpr3_agb, wire_cmpr2_agb, wire_cmpr1_agb},
exp_agb_tmp_w = {(exp_agb_tmp_w[2] | exp_eq_gt_grp[3]), (exp_agb_tmp_w[1] | exp_eq_gt_grp[2]), (exp_agb_tmp_w[0] | exp_eq_gt_grp[1]), exp_eq_gt_grp[0]},
exp_agb_w = exp_agb_tmp_w[3],
exp_agb_w_dffe2_wi = exp_agb_w,
exp_agb_w_dffe2_wo = exp_agb_w_dffe2_wi,
exp_b_all_one_dffe1_wi = exp_b_all_one_w[7],
exp_b_all_one_dffe1_wo = exp_b_all_one_dffe1_wi,
exp_b_all_one_w = {(datab[30] & exp_b_all_one_w[6]), (datab[29] & exp_b_all_one_w[5]), (datab[28] & exp_b_all_one_w[4]), (datab[27] & exp_b_all_one_w[3]), (datab[26] & exp_b_all_one_w[2]), (datab[25] & exp_b_all_one_w[1]), (datab[24] & exp_b_all_one_w[0]), datab[23]},
exp_b_not_zero_dffe1_wi = exp_b_not_zero_w[7],
exp_b_not_zero_dffe1_wo = exp_b_not_zero_dffe1_wi,
exp_b_not_zero_w = {(datab[30] | exp_b_not_zero_w[6]), (datab[29] | exp_b_not_zero_w[5]), (datab[28] | exp_b_not_zero_w[4]), (datab[27] | exp_b_not_zero_w[3]), (datab[26] | exp_b_not_zero_w[2]), (datab[25] | exp_b_not_zero_w[1]), (datab[24] | exp_b_not_zero_w[0]), datab[23]},
exp_eq_grp = {(exp_eq_grp[1] & exp_aeb[2]), (exp_eq_grp[0] & exp_aeb[1]), exp_aeb[0]},
exp_eq_gt_grp = {(exp_eq_grp[2] & exp_agb[3]), (exp_eq_grp[1] & exp_agb[2]), (exp_eq_grp[0] & exp_agb[1]), exp_agb[0]},
flip_outputs_dffe2_wi = flip_outputs_w,
flip_outputs_dffe2_wo = flip_outputs_dffe2_wi,
flip_outputs_w = (aligned_dataa_sign_adjusted_w & aligned_datab_sign_adjusted_w),
input_dataa_nan_dffe2_wi = input_dataa_nan_w,
input_dataa_nan_dffe2_wo = input_dataa_nan_dffe2_wi,
input_dataa_nan_w = (exp_a_all_one_dffe1_wo & man_a_not_zero_merge_w[1]),
input_dataa_zero_w = (~ exp_a_not_zero_dffe1_wo),
input_datab_nan_dffe2_wi = input_datab_nan_w,
input_datab_nan_dffe2_wo = input_datab_nan_dffe2_wi,
input_datab_nan_w = (exp_b_all_one_dffe1_wo & man_b_not_zero_merge_w[1]),
input_datab_zero_w = (~ exp_b_not_zero_dffe1_wo),
man_a_not_zero_dffe1_wi = {man_a_not_zero_w[22], man_a_not_zero_w[11]},
man_a_not_zero_dffe1_wo = man_a_not_zero_dffe1_wi,
man_a_not_zero_merge_w = {(man_a_not_zero_dffe1_wo[1] | man_a_not_zero_merge_w[0]), man_a_not_zero_dffe1_wo[0]},
man_a_not_zero_w = {(dataa[22] | man_a_not_zero_w[21]), (dataa[21] | man_a_not_zero_w[20]), (dataa[20] | man_a_not_zero_w[19]), (dataa[19] | man_a_not_zero_w[18]), (dataa[18] | man_a_not_zero_w[17]), (dataa[17] | man_a_not_zero_w[16]), (dataa[16] | man_a_not_zero_w[15]), (dataa[15] | man_a_not_zero_w[14]), (dataa[14] | man_a_not_zero_w[13]), (dataa[13] | man_a_not_zero_w[12]), dataa[12], (dataa[11] | man_a_not_zero_w[10]), (dataa[10] | man_a_not_zero_w[9]), (dataa[9] | man_a_not_zero_w[8]), (dataa[8] | man_a_not_zero_w[7]), (dataa[7] | man_a_not_zero_w[6]), (dataa[6] | man_a_not_zero_w[5]), (dataa[5] | man_a_not_zero_w[4]), (dataa[4] | man_a_not_zero_w[3]), (dataa[3] | man_a_not_zero_w[2]), (dataa[2] | man_a_not_zero_w[1]), (dataa[1] | man_a_not_zero_w[0]), dataa[0]},
man_b_not_zero_dffe1_wi = {man_b_not_zero_w[22], man_b_not_zero_w[11]},
man_b_not_zero_dffe1_wo = man_b_not_zero_dffe1_wi,
man_b_not_zero_merge_w = {(man_b_not_zero_dffe1_wo[1] | man_b_not_zero_merge_w[0]), man_b_not_zero_dffe1_wo[0]},
man_b_not_zero_w = {(datab[22] | man_b_not_zero_w[21]), (datab[21] | man_b_not_zero_w[20]), (datab[20] | man_b_not_zero_w[19]), (datab[19] | man_b_not_zero_w[18]), (datab[18] | man_b_not_zero_w[17]), (datab[17] | man_b_not_zero_w[16]), (datab[16] | man_b_not_zero_w[15]), (datab[15] | man_b_not_zero_w[14]), (datab[14] | man_b_not_zero_w[13]), (datab[13] | man_b_not_zero_w[12]), datab[12], (datab[11] | man_b_not_zero_w[10]), (datab[10] | man_b_not_zero_w[9]), (datab[9] | man_b_not_zero_w[8]), (datab[8] | man_b_not_zero_w[7]), (datab[7] | man_b_not_zero_w[6]), (datab[6] | man_b_not_zero_w[5]), (datab[5] | man_b_not_zero_w[4]), (datab[4] | man_b_not_zero_w[3]), (datab[3] | man_b_not_zero_w[2]), (datab[2] | man_b_not_zero_w[1]), (datab[1] | man_b_not_zero_w[0]), datab[0]},
out_aeb_w = ((((~ (aligned_dataa_sign_adjusted_dffe2_wo ^ aligned_datab_sign_adjusted_dffe2_wo)) & exp_aeb_w_dffe2_wo) | both_inputs_zero_dffe2_wo) & (~ out_unordered_w)),
out_agb_w = (((((~ aligned_dataa_sign_adjusted_dffe2_wo) & aligned_datab_sign_adjusted_dffe2_wo) | ((exp_agb_w_dffe2_wo & (~ aligned_dataa_sign_adjusted_dffe2_wo)) & (~ both_inputs_zero_dffe2_wo))) | ((flip_outputs_dffe2_wo & (~ exp_agb_w_dffe2_wo)) & (~ out_aeb_w))) & (~ out_unordered_w)),
out_ageb_dffe3_wi = out_ageb_w,
out_ageb_dffe3_wo = out_ageb_w_dffe3,
out_ageb_w = ((out_agb_w | out_aeb_w) & (~ out_unordered_w)),
out_alb_w = (((~ out_agb_w) & (~ out_aeb_w)) & (~ out_unordered_w)),
out_aleb_dffe3_wi = out_aleb_w,
out_aleb_dffe3_wo = out_aleb_w_dffe3,
out_aleb_w = ((out_alb_w | out_aeb_w) & (~ out_unordered_w)),
out_unordered_w = (input_dataa_nan_dffe2_wo | input_datab_nan_dffe2_wo);
endmodule //float_cmp_altfp_compare_5ac
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module float_cmp (
clk_en,
clock,
dataa,
datab,
ageb,
aleb);
input clk_en;
input clock;
input [31:0] dataa;
input [31:0] datab;
output ageb;
output aleb;
wire sub_wire0;
wire sub_wire1;
wire aleb = sub_wire0;
wire ageb = sub_wire1;
float_cmp_altfp_compare_5ac float_cmp_altfp_compare_5ac_component (
.clk_en (clk_en),
.clock (clock),
.datab (datab),
.dataa (dataa),
.aleb (sub_wire0),
.ageb (sub_wire1));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: FPM_FORMAT NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
// Retrieval info: USED_PORT: ageb 0 0 0 0 OUTPUT NODEFVAL "ageb"
// Retrieval info: USED_PORT: aleb 0 0 0 0 OUTPUT NODEFVAL "aleb"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
// Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
// Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
// Retrieval info: CONNECT: ageb 0 0 0 0 @ageb 0 0 0 0
// Retrieval info: CONNECT: aleb 0 0 0 0 @aleb 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL float_cmp.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL float_cmp.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL float_cmp.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL float_cmp.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL float_cmp_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL float_cmp_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: spll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module spll (
areset,
inclk0,
c0,
c1,
locked);
input areset;
input inclk0;
output c0;
output c1;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "5"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "25.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "50.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "spll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "40000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "Left_Right"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "7"
// Retrieval info: USED_PORT: @clk 0 0 7 0 OUTPUT_CLK_EXT VCC "@clk[6..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL spll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL spll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL spll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL spll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL spll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL spll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL spll_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
wire one = '1;
wire z0 = 'z;
wire z1 = 'z;
wire z2 = 'z;
wire z3 = 'z;
wire tog = cyc[0];
// verilator lint_off PINMISSING
t_tri0 tri0a (.line(`__LINE__), .expval(1'b0)); // Pin missing
t_tri0 tri0b (.line(`__LINE__), .expval(1'b0), .tn());
t_tri0 tri0z (.line(`__LINE__), .expval(1'b0), .tn(z0));
t_tri0 tri0Z (.line(`__LINE__), .expval(1'b0), .tn(1'bz));
t_tri0 tri0c (.line(`__LINE__), .expval(1'b0), .tn(1'b0));
t_tri0 tri0d (.line(`__LINE__), .expval(1'b1), .tn(1'b1)); // Warning would be reasonable given tri0 connect
t_tri0 tri0e (.line(`__LINE__), .expval(1'b0), .tn(~one));
t_tri0 tri0f (.line(`__LINE__), .expval(1'b1), .tn(one));
t_tri0 tri0g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog));
t_tri0 tri0h (.line(`__LINE__), .expval(cyc[0]), .tn(tog));
t_tri1 tri1a (.line(`__LINE__), .expval(1'b1)); // Pin missing
t_tri1 tri1b (.line(`__LINE__), .expval(1'b1), .tn());
t_tri1 tri1z (.line(`__LINE__), .expval(1'b1), .tn(z1));
t_tri1 tri1Z (.line(`__LINE__), .expval(1'b1), .tn(1'bz));
t_tri1 tri1c (.line(`__LINE__), .expval(1'b0), .tn(1'b0)); // Warning would be reasonable given tri1 connect
t_tri1 tri1d (.line(`__LINE__), .expval(1'b1), .tn(1'b1));
t_tri1 tri1e (.line(`__LINE__), .expval(1'b0), .tn(~one));
t_tri1 tri1f (.line(`__LINE__), .expval(1'b1), .tn(one));
t_tri1 tri1g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog));
t_tri1 tri1h (.line(`__LINE__), .expval(cyc[0]), .tn(tog));
t_tri2 tri2a (.line(`__LINE__), .expval(1'b0)); // Pin missing
t_tri2 tri2b (.line(`__LINE__), .expval(1'b0), .tn());
t_tri2 tri2z (.line(`__LINE__), .expval(1'b0), .tn(z2));
t_tri2 tri2Z (.line(`__LINE__), .expval(1'b0), .tn(1'bz));
t_tri2 tri2c (.line(`__LINE__), .expval(1'b0), .tn(1'b0));
t_tri2 tri2d (.line(`__LINE__), .expval(1'b1), .tn(1'b1));
t_tri2 tri2e (.line(`__LINE__), .expval(1'b0), .tn(~one));
t_tri2 tri2f (.line(`__LINE__), .expval(1'b1), .tn(one));
t_tri2 tri2g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog));
t_tri2 tri2h (.line(`__LINE__), .expval(cyc[0]), .tn(tog));
t_tri3 tri3a (.line(`__LINE__), .expval(1'b1)); // Pin missing
t_tri3 tri3b (.line(`__LINE__), .expval(1'b1), .tn());
t_tri3 tri3z (.line(`__LINE__), .expval(1'b1), .tn(z3));
t_tri3 tri3Z (.line(`__LINE__), .expval(1'b1), .tn(1'bz));
t_tri3 tri3c (.line(`__LINE__), .expval(1'b0), .tn(1'b0));
t_tri3 tri3d (.line(`__LINE__), .expval(1'b1), .tn(1'b1));
t_tri3 tri3e (.line(`__LINE__), .expval(1'b0), .tn(~one));
t_tri3 tri3f (.line(`__LINE__), .expval(1'b1), .tn(one));
t_tri3 tri3g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog));
t_tri3 tri3h (.line(`__LINE__), .expval(cyc[0]), .tn(tog));
// verilator lint_on PINMISSING
// Test loop
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module t_tri0
(line, expval, tn);
input integer line;
input expval;
input tn; // Illegal to be inout; spec requires net connection to any inout
tri0 tn;
wire clk = t.clk;
always @(posedge clk) if (tn !== expval) begin
$display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop;
end
endmodule
module t_tri1
(line, expval, tn);
input integer line;
input expval;
input tn;
tri1 tn;
wire clk = t.clk;
always @(posedge clk) if (tn !== expval) begin
$display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop;
end
endmodule
module t_tri2
(line, expval, tn);
input integer line;
input expval;
input tn;
pulldown(tn);
wire clk = t.clk;
always @(posedge clk) if (tn !== expval) begin
$display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop;
end
endmodule
module t_tri3
(line, expval, tn);
input integer line;
input expval;
input tn;
pullup(tn);
wire clk = t.clk;
always @(negedge clk) if (tn !== expval) begin
$display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop;
end
endmodule
|
// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Description: SRL based FIFO for AXIS/AXI Channels.
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_axic_srl_fifo #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_FAMILY = "virtex7",
parameter integer C_PAYLOAD_WIDTH = 1,
parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire aclk, // Clock
input wire aresetn, // Reset
input wire [C_PAYLOAD_WIDTH-1:0] s_payload, // Input data
input wire s_valid, // Input data valid
output reg s_ready, // Input data ready
output wire [C_PAYLOAD_WIDTH-1:0] m_payload, // Output data
output reg m_valid, // Output data valid
input wire m_ready // Output data ready
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
// ceiling logb2
function integer f_clogb2 (input integer size);
integer s;
begin
s = size;
s = s - 1;
for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
s = s >> 1;
end
endfunction // clogb2
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [LP_LOG_FIFO_DEPTH-1:0] fifo_index;
wire [4-1:0] fifo_addr;
wire push;
wire pop ;
reg areset_r1;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
always @(posedge aclk) begin
areset_r1 <= ~aresetn;
end
always @(posedge aclk) begin
if (~aresetn) begin
fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};
end
else begin
fifo_index <= push & ~pop ? fifo_index + 1'b1 :
~push & pop ? fifo_index - 1'b1 :
fifo_index;
end
end
assign push = s_valid & s_ready;
always @(posedge aclk) begin
if (~aresetn) begin
s_ready <= 1'b0;
end
else begin
s_ready <= areset_r1 ? 1'b1 :
push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :
~push & pop ? 1'b1 :
s_ready;
end
end
assign pop = m_valid & m_ready;
always @(posedge aclk) begin
if (~aresetn) begin
m_valid <= 1'b0;
end
else begin
m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :
push & ~pop ? 1'b1 :
m_valid;
end
end
generate
if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr
assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};
end
else begin : gen_fifo_addr
assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
end
endgenerate
generate
genvar i;
for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit
SRL16E
u_srl_fifo(
.Q ( m_payload[i] ) ,
.A0 ( fifo_addr[0] ) ,
.A1 ( fifo_addr[1] ) ,
.A2 ( fifo_addr[2] ) ,
.A3 ( fifo_addr[3] ) ,
.CE ( push ) ,
.CLK ( aclk ) ,
.D ( s_payload[i] )
);
end
endgenerate
endmodule
`default_nettype wire
|
`timescale 1 ns / 1 ps
`include "pmod_io_switch_v1_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define S00_AXI_MAX_BURST_LENGTH 1
`define S00_AXI_DATA_BUS_WIDTH 32
`define S00_AXI_ADDRESS_BUS_WIDTH 32
`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8
module pmod_io_switch_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S00_AXI AXI4 Lite Local Reg
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
reg [3-1:0] S00_AXI_mtestProtection_lite;
integer S00_AXI_mtestvectorlite; // Master side testvector
integer S00_AXI_mtestdatasizelite;
integer result_slave_lite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
`define S_AXI_DATA_BUS_WIDTH 32
task automatic COMPARE_LITE_DATA;
input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S00_AXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S00_AXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S00_AXI_mtestvectorlite = 0;
S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
S00_AXI_mtestProtection_lite = 0;
S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
S00_AXI_mtestdatasizelite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_rd_data_lite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S00_AXI_test_data_lite[0] = 32'h0101FFFF;
S00_AXI_test_data_lite[1] = 32'habcd0001;
S00_AXI_test_data_lite[2] = 32'hdead0011;
S00_AXI_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S00_AXI_TEST();
end
endmodule
|
//
`default_nettype none
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
(* altera_attribute = "-name MESSAGE_DISABLE 14130" *) module ddr_ctrl_ip_phy_alt_mem_phy (
//Clock and reset inputs:
pll_ref_clk,
global_reset_n,
soft_reset_n,
// Used to indicate PLL loss of lock for system reset management:
reset_request_n,
// Clock and reset for the controller interface:
ctl_clk,
ctl_reset_n,
// Write data interface:
ctl_dqs_burst,
ctl_wdata_valid,
ctl_wdata,
ctl_dm,
ctl_wlat,
// Address and command interface:
ctl_addr,
ctl_ba,
ctl_cas_n,
ctl_cke,
ctl_cs_n,
ctl_odt,
ctl_ras_n,
ctl_we_n,
ctl_rst_n,
ctl_mem_clk_disable,
// Read data interface:
ctl_doing_rd,
ctl_rdata,
ctl_rdata_valid,
ctl_rlat,
//re-calibration request & configuration:
ctl_cal_req,
ctl_cal_byte_lane_sel_n,
//Calibration status interface:
ctl_cal_success,
ctl_cal_fail,
ctl_cal_warning,
//ports to memory device(s):
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_cs_n,
mem_dm,
mem_odt,
mem_ras_n,
mem_we_n,
mem_clk,
mem_clk_n,
mem_reset_n,
// Bidirectional Memory interface signals:
mem_dq,
mem_dqs,
mem_dqs_n,
// Auxiliary clocks. Some systems may need these for debugging
// purposes, or for full-rate to half-rate bridge interfaces
aux_half_rate_clk,
aux_full_rate_clk,
// Debug interface:- ALTERA USE ONLY
dbg_clk,
dbg_reset_n,
dbg_addr,
dbg_wr,
dbg_rd,
dbg_cs,
dbg_wr_data,
dbg_rd_data,
dbg_waitrequest
);
// Default parameter values :
parameter FAMILY = "CYCLONEIII";
parameter MEM_IF_MEMTYPE = "DDR2";
parameter LEVELLING = 0; // RFU
parameter SPEED_GRADE = "C6";
parameter DLL_DELAY_BUFFER_MODE = "HIGH";
parameter DLL_DELAY_CHAIN_LENGTH = 8;
parameter DQS_DELAY_CTL_WIDTH = 6;
parameter DQS_OUT_MODE = "DELAY_CHAIN2";
parameter DQS_PHASE = 9000;
parameter DQS_PHASE_SETTING = 2;
parameter DWIDTH_RATIO = 4;
parameter MEM_IF_DWIDTH = 64;
parameter MEM_IF_ADDR_WIDTH = 13;
parameter MEM_IF_BANKADDR_WIDTH = 3;
parameter MEM_IF_CS_WIDTH = 2;
parameter MEM_IF_DM_WIDTH = 8;
parameter MEM_IF_DM_PINS_EN = 1;
parameter MEM_IF_DQ_PER_DQS = 8;
parameter MEM_IF_DQS_WIDTH = 8;
parameter MEM_IF_OCT_EN = 0;
parameter MEM_IF_CLK_PAIR_COUNT = 3;
parameter MEM_IF_CLK_PS = 4000;
parameter MEM_IF_CLK_PS_STR = "4000 ps";
parameter MEM_IF_MR_0 = 0;
parameter MEM_IF_MR_1 = 0;
parameter MEM_IF_MR_2 = 0;
parameter MEM_IF_MR_3 = 0;
parameter MEM_IF_PRESET_RLAT = 0;
parameter PLL_STEPS_PER_CYCLE = 24;
parameter SCAN_CLK_DIVIDE_BY = 4;
parameter REDUCE_SIM_TIME = 0;
parameter CAPABILITIES = 0;
parameter TINIT_TCK = 40000;
parameter TINIT_RST = 100000;
parameter DBG_A_WIDTH = 13;
parameter SEQ_STRING_ID = "seq_name";
parameter MEM_IF_CS_PER_RANK = 1; // duplicates CS, CKE, ODT, sequencer still controls 1 rank, but it is subdivided from controller perspective.
parameter MEM_IF_RANKS_PER_SLOT = 1; // how ranks are arranged into slot - needed for odt setting in the sequencer
parameter MEM_IF_RDV_PER_CHIP = 0; // multiple chips, and which gives valid data
parameter GENERATE_ADDITIONAL_DBG_RTL = 0; // DDR2 sequencer specific
parameter CAPTURE_PHASE_OFFSET = 0;
parameter MEM_IF_ADDR_CMD_PHASE = 0;
parameter DLL_EXPORT_IMPORT = "NONE";
parameter MEM_IF_DQSN_EN = 1;
parameter RANK_HAS_ADDR_SWAP = 0;
//
localparam phy_report_prefix = "ddr_ctrl_ip_phy_alt_mem_phy (top level) : ";
// function to set the USE_MEM_CLK_FOR_ADDR_CMD_CLK localparam based on MEM_IF_ADDR_CMD_PHASE
function integer set_mem_clk_for_ac_clk (input reg [23:0] addr_cmd_phase);
integer return_value;
begin
return_value = 0;
case (addr_cmd_phase)
0, 180 : return_value = 1;
90, 270 : return_value = 0;
default : begin
//synthesis translate_off
$display(phy_report_prefix, "Illegal value set on MEM_IF_ADDR_CMD_PHASE parameter: ", addr_cmd_phase);
$stop;
//synthesis translate_on
end
endcase
set_mem_clk_for_ac_clk = return_value;
end
endfunction
// function to set the ADDR_CMD_NEGEDGE_EN localparam based on MEM_IF_ADDR_CMD_PHASE
function integer set_ac_negedge_en(input reg [23:0] addr_cmd_phase);
integer return_value;
begin
return_value = 0;
case (addr_cmd_phase)
90, 180 : return_value = 1;
0, 270 : return_value = 0;
default : begin
//synthesis translate_off
$display(phy_report_prefix, "Illegal value set on MEM_IF_ADDR_CMD_PHASE parameter: ", addr_cmd_phase);
$stop;
//synthesis translate_on
end
endcase
set_ac_negedge_en = return_value;
end
endfunction
localparam USE_MEM_CLK_FOR_ADDR_CMD_CLK = set_mem_clk_for_ac_clk(MEM_IF_ADDR_CMD_PHASE);
localparam ADDR_CMD_NEGEDGE_EN = set_ac_negedge_en(MEM_IF_ADDR_CMD_PHASE);
localparam LOCAL_IF_DWIDTH = MEM_IF_DWIDTH*DWIDTH_RATIO;
localparam LOCAL_IF_CLK_PS = MEM_IF_CLK_PS/(DWIDTH_RATIO/2);
localparam PLL_REF_CLK_PS = LOCAL_IF_CLK_PS;
localparam MEM_IF_DQS_CAPTURE_EN = 0;
localparam ADDR_COUNT_WIDTH = 4;
localparam RDP_RESYNC_LAT_CTL_EN = 0;
localparam DEDICATED_MEMORY_CLK_EN = 0;
localparam ADV_LAT_WIDTH = 5;
localparam CAPTURE_MIMIC_PATH = 0;
localparam DDR_MIMIC_PATH_EN = 1;
localparam MIMIC_DEBUG_EN = 0;
localparam NUM_MIMIC_SAMPLE_CYCLES = 6;
localparam NUM_DEBUG_SAMPLES_TO_STORE = 4096;
localparam ASYNCHRONOUS_AVALON_CLOCK = 1;
localparam RDV_INITIAL_LAT = 23;
localparam RDP_INITIAL_LAT = (DWIDTH_RATIO == 2 ? 5:6);
localparam RESYNC_PIPELINE_DEPTH = 0;
localparam CLOCK_INDEX_WIDTH = 3;
localparam OCT_LAT_WIDTH = ADV_LAT_WIDTH;
// I/O Signal definitions :
// Clock and reset I/O :
input wire pll_ref_clk;
input wire global_reset_n;
input wire soft_reset_n;
// This is the PLL locked signal :
output wire reset_request_n;
// The controller must use this phy_clk to interface to the PHY. It is
// optional as to whether the remainder of the system uses it :
output wire ctl_clk;
output wire ctl_reset_n;
// new AFI I/Os - write data i/f:
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 -1 : 0] ctl_dqs_burst;
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 -1 : 0] ctl_wdata_valid;
input wire [MEM_IF_DWIDTH * DWIDTH_RATIO -1 : 0] ctl_wdata;
input wire [MEM_IF_DM_WIDTH * DWIDTH_RATIO -1 : 0] ctl_dm;
output wire [4 : 0] ctl_wlat;
// new AFI I/Os - addr/cmd i/f:
input wire [MEM_IF_ADDR_WIDTH * DWIDTH_RATIO/2 -1 : 0] ctl_addr;
input wire [MEM_IF_BANKADDR_WIDTH * DWIDTH_RATIO/2 -1 : 0] ctl_ba;
input wire [1 * DWIDTH_RATIO/2 -1 : 0] ctl_cas_n;
input wire [MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1:0] ctl_cke;
input wire [MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1:0] ctl_cs_n;
input wire [MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1:0] ctl_odt;
input wire [1 * DWIDTH_RATIO/2 -1 : 0] ctl_ras_n;
input wire [1 * DWIDTH_RATIO/2 -1 : 0] ctl_we_n;
input wire [DWIDTH_RATIO/2 - 1 : 0] ctl_rst_n;
input wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] ctl_mem_clk_disable;
// new AFI I/Os - read data i/f:
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO / 2 -1 : 0] ctl_doing_rd;
output wire [MEM_IF_DWIDTH * DWIDTH_RATIO -1 : 0] ctl_rdata;
output wire [DWIDTH_RATIO / 2 -1 : 0] ctl_rdata_valid;
output wire [4 : 0] ctl_rlat;
// re-calibration request and configuration:
input wire ctl_cal_req;
input wire [MEM_IF_DQS_WIDTH * MEM_IF_CS_WIDTH - 1 : 0] ctl_cal_byte_lane_sel_n;
// new AFI I/Os - status interface:
output wire ctl_cal_success;
output wire ctl_cal_fail;
output wire ctl_cal_warning;
//Outputs to DIMM :
output wire [MEM_IF_ADDR_WIDTH - 1 : 0] mem_addr;
output wire [MEM_IF_BANKADDR_WIDTH - 1 : 0] mem_ba;
output wire mem_cas_n;
output wire [MEM_IF_CS_WIDTH - 1 : 0] mem_cke;
output wire [MEM_IF_CS_WIDTH - 1 : 0] mem_cs_n;
wire [MEM_IF_DWIDTH - 1 : 0] mem_d;
output wire [MEM_IF_DM_WIDTH - 1 : 0] mem_dm;
output wire [MEM_IF_CS_WIDTH - 1 : 0] mem_odt;
output wire mem_ras_n;
output wire mem_we_n;
output wire mem_reset_n;
//The mem_clks are outputs, but one is sometimes used for the mimic_path, so
//is looped back in. Therefore defining as an inout ensures no errors in Quartus :
inout wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mem_clk;
inout wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mem_clk_n;
//Bidirectional:
inout tri [MEM_IF_DWIDTH - 1 : 0] mem_dq;
inout tri [MEM_IF_DWIDTH / MEM_IF_DQ_PER_DQS - 1 : 0] mem_dqs;
inout tri [MEM_IF_DWIDTH / MEM_IF_DQ_PER_DQS - 1 : 0] mem_dqs_n;
// AVALON MM Slave -- debug IF
input wire dbg_clk;
input wire dbg_reset_n;
input wire [DBG_A_WIDTH -1 : 0] dbg_addr;
input wire dbg_wr;
input wire dbg_rd;
input wire dbg_cs;
input wire [31 : 0] dbg_wr_data;
output wire [31 : 0] dbg_rd_data;
output wire dbg_waitrequest;
// Auxillary clocks. These do not have to be connected if the system
// doesn't require them :
output wire aux_half_rate_clk;
output wire aux_full_rate_clk;
// Internal signal declarations :
// Clocks :
// full-rate memory clock
wire mem_clk_2x;
// half-rate memory clock
wire mem_clk_1x;
// write_clk_2x is a full-rate write clock. It is -90 degress aligned to the
// system clock :
wire write_clk_2x;
wire phy_clk_1x_src;
wire phy_clk_1x;
wire ac_clk_2x;
wire cs_n_clk_2x;
wire resync_clk_2x;
wire measure_clk_1x;
wire measure_clk_2x;
wire half_rate_clk;
wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dedicated_dll_delay_ctrl;
// resets, async assert, de-assert is sync'd to each clock domain
wire reset_mem_clk_2x_n;
wire reset_rdp_phy_clk_1x_n;
wire reset_phy_clk_1x_n;
wire reset_ac_clk_2x_n;
wire reset_cs_n_clk_2x_n;
wire reset_mimic_2x_n;
wire reset_resync_clk_2x_n;
wire reset_seq_n;
wire reset_measure_clk_1x_n;
wire reset_measure_clk_2x_n;
wire reset_write_clk_2x_n;
// Misc signals :
wire phs_shft_busy;
wire pll_seq_reconfig_busy;
// Sequencer signals
wire seq_mmc_start;
wire seq_pll_inc_dec_n;
wire seq_pll_start_reconfig;
wire [CLOCK_INDEX_WIDTH - 1 : 0] seq_pll_select;
wire [MEM_IF_DQS_WIDTH -1 : 0] seq_rdp_dec_read_lat_1x;
wire [MEM_IF_DQS_WIDTH -1 : 0] seq_rdp_inc_read_lat_1x;
wire seq_rdp_reset_req_n;
wire seq_ac_sel;
wire [MEM_IF_ADDR_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_ac_addr;
wire [MEM_IF_BANKADDR_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_ac_ba;
wire [DWIDTH_RATIO/2 -1 : 0] seq_ac_cas_n;
wire [DWIDTH_RATIO/2 -1 : 0] seq_ac_ras_n;
wire [DWIDTH_RATIO/2 -1 : 0] seq_ac_we_n;
wire [MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_ac_cke;
wire [MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_ac_cs_n;
wire [MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_ac_odt;
wire [DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 : 0 ] seq_wdp_dm;
wire [MEM_IF_DQS_WIDTH * (DWIDTH_RATIO/2) - 1 : 0] seq_wdp_dqs_burst;
wire [MEM_IF_DWIDTH * DWIDTH_RATIO - 1 : 0 ] seq_wdp_wdata;
wire [MEM_IF_DQS_WIDTH * (DWIDTH_RATIO/2) - 1 : 0] seq_wdp_wdata_valid;
wire [DWIDTH_RATIO - 1 :0] seq_wdp_dqs;
wire seq_wdp_ovride;
wire [MEM_IF_DQS_WIDTH * (DWIDTH_RATIO/2) - 1 : 0] oct_rsst_sel;
wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_doing_rd;
wire seq_rdata_valid_lat_inc;
wire seq_rdata_valid_lat_dec;
wire [DWIDTH_RATIO/2 - 1 : 0] seq_rdata_valid;
reg [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dedicated_dll_delay_ctrl_r;
// set pll clock index of resync and mimic clocks
wire [CLOCK_INDEX_WIDTH - 1 : 0] pll_resync_clk_index;
wire [CLOCK_INDEX_WIDTH - 1 : 0] pll_measure_clk_index;
// Mimic signals :
wire mmc_seq_done;
wire mmc_seq_value;
wire mimic_data;
wire mux_seq_controller_ready;
wire mux_seq_wdata_req;
// Read datapath signals :
// Connections from the IOE to the read datapath :
wire [MEM_IF_DWIDTH - 1 : 0] dio_rdata_h_2x;
wire [MEM_IF_DWIDTH - 1 : 0] dio_rdata_l_2x;
// Write datapath signals :
// wires from the wdp to the dpio :
wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata3_1x;
wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata2_1x;
wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata1_1x;
wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata0_1x;
wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata_h_2x;
wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata_l_2x;
wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata_oe_2x;
wire [(LOCAL_IF_DWIDTH/8) - 1 : 0] ctl_mem_be;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_wdata_oe_h_1x;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_wdata_oe_l_1x;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs3_1x;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs2_1x;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs1_1x;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs0_1x;
wire [(MEM_IF_DQS_WIDTH) - 1 : 0] wdp_wdqs_2x;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs_oe_h_1x;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs_oe_l_1x;
wire [(MEM_IF_DQS_WIDTH) - 1 : 0] wdp_wdqs_oe_2x;
wire [MEM_IF_DM_WIDTH -1 : 0] wdp_dm3_1x;
wire [MEM_IF_DM_WIDTH -1 : 0] wdp_dm2_1x;
wire [MEM_IF_DM_WIDTH -1 : 0] wdp_dm1_1x;
wire [MEM_IF_DM_WIDTH -1 : 0] wdp_dm0_1x;
wire [MEM_IF_DM_WIDTH -1 : 0] wdp_dm_h_2x;
wire [MEM_IF_DM_WIDTH -1 : 0] wdp_dm_l_2x;
wire [MEM_IF_DQS_WIDTH -1 : 0] wdp_oct_h_1x;
wire [MEM_IF_DQS_WIDTH -1 : 0] wdp_oct_l_1x;
wire [MEM_IF_DQS_WIDTH -1 : 0] seq_dqs_add_2t_delay;
wire ctl_add_1t_ac_lat_internal;
wire ctl_add_1t_odt_lat_internal;
wire ctl_add_intermediate_regs_internal;
wire ctl_negedge_en_internal;
wire ctl_mem_dqs_burst;
wire [MEM_IF_DWIDTH*DWIDTH_RATIO - 1 : 0] ctl_mem_wdata;
wire ctl_mem_wdata_valid;
// These ports are tied off for DDR,DDR2,DDR3. Registers are used to reduce Quartus warnings :
(* preserve *) reg [3 : 0] ctl_mem_dqs = 4'b1100;
wire [MEM_IF_CS_WIDTH - 1 : 0] int_rank_has_addr_swap;
//SIII declarations :
//Outputs from the dp_io block to the read_dp block :
wire [MEM_IF_DWIDTH - 1 : 0] dio_rdata3_1x;
wire [MEM_IF_DWIDTH - 1 : 0] dio_rdata2_1x;
wire [MEM_IF_DWIDTH - 1 : 0] dio_rdata1_1x;
wire [MEM_IF_DWIDTH - 1 : 0] dio_rdata0_1x;
reg [DWIDTH_RATIO/2 - 1 : 0] rdv_pipe_ip;
reg [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] merged_doing_rd;
wire [OCT_LAT_WIDTH - 1 : 0] seq_oct_oct_delay; // oct_lat
wire [OCT_LAT_WIDTH - 1 : 0] seq_oct_oct_extend; //oct_extend_duration
wire seq_oct_val;
wire seq_mem_clk_disable;
wire [DWIDTH_RATIO/2 - 1 : 0] seq_ac_rst_n;
wire dqs_delay_update_en;
wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dlloffset_offsetctrl_out;
// Generate auxillary clocks:
generate
// Half-rate mode :
if (DWIDTH_RATIO == 4)
begin
assign aux_half_rate_clk = phy_clk_1x;
assign aux_full_rate_clk = mem_clk_2x;
end
// Full-rate mode :
else
begin
assign aux_half_rate_clk = half_rate_clk;
assign aux_full_rate_clk = phy_clk_1x;
end
endgenerate
// The top level I/O should not have the "Nx" clock domain suffices, so this is
// assigned here. Also note that to avoid delta delay issues both the external and
// internal phy_clks are assigned to a common 'src' clock :
assign ctl_clk = phy_clk_1x_src;
assign phy_clk_1x = phy_clk_1x_src;
assign ctl_reset_n = reset_phy_clk_1x_n;
// Instance I/O modules :
//
ddr_ctrl_ip_phy_alt_mem_phy_dp_io #(
.MEM_IF_CLK_PS (MEM_IF_CLK_PS),
.MEM_IF_BANKADDR_WIDTH (MEM_IF_BANKADDR_WIDTH),
.MEM_IF_CS_WIDTH (MEM_IF_CS_WIDTH),
.MEM_IF_DWIDTH (MEM_IF_DWIDTH),
.MEM_IF_DM_WIDTH (MEM_IF_DM_WIDTH),
.MEM_IF_DM_PINS_EN (MEM_IF_DM_PINS_EN),
.MEM_IF_DQ_PER_DQS (MEM_IF_DQ_PER_DQS),
.MEM_IF_DQS_CAPTURE_EN (MEM_IF_DQS_CAPTURE_EN),
.MEM_IF_DQS_WIDTH (MEM_IF_DQS_WIDTH),
.MEM_IF_ROWADDR_WIDTH (MEM_IF_ADDR_WIDTH),
.DLL_DELAY_BUFFER_MODE (DLL_DELAY_BUFFER_MODE),
.DQS_OUT_MODE (DQS_OUT_MODE),
.DQS_PHASE (DQS_PHASE)
) dpio (
.reset_resync_clk_2x_n (reset_resync_clk_2x_n),
.resync_clk_2x (resync_clk_2x),
.mem_clk_2x (mem_clk_2x),
.write_clk_2x (write_clk_2x),
.mem_dm (mem_dm),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs),
.dio_rdata_h_2x (dio_rdata_h_2x),
.dio_rdata_l_2x (dio_rdata_l_2x),
.wdp_dm_h_2x (wdp_dm_h_2x),
.wdp_dm_l_2x (wdp_dm_l_2x),
.wdp_wdata_h_2x (wdp_wdata_h_2x),
.wdp_wdata_l_2x (wdp_wdata_l_2x),
.wdp_wdata_oe_2x (wdp_wdata_oe_2x),
.wdp_wdqs_2x (wdp_wdqs_2x),
.wdp_wdqs_oe_2x (wdp_wdqs_oe_2x)
);
// Instance the read datapath :
//
ddr_ctrl_ip_phy_alt_mem_phy_read_dp #(
.ADDR_COUNT_WIDTH (ADDR_COUNT_WIDTH),
.BIDIR_DPINS (1),
.DWIDTH_RATIO (DWIDTH_RATIO),
.MEM_IF_CLK_PS (MEM_IF_CLK_PS),
.FAMILY (FAMILY),
.LOCAL_IF_DWIDTH (LOCAL_IF_DWIDTH),
.MEM_IF_DQ_PER_DQS (MEM_IF_DQ_PER_DQS),
.MEM_IF_DQS_WIDTH (MEM_IF_DQS_WIDTH),
.MEM_IF_DWIDTH (MEM_IF_DWIDTH),
.RDP_INITIAL_LAT (RDP_INITIAL_LAT),
.RDP_RESYNC_LAT_CTL_EN (RDP_RESYNC_LAT_CTL_EN),
.RESYNC_PIPELINE_DEPTH (RESYNC_PIPELINE_DEPTH)
) rdp (
.phy_clk_1x (phy_clk_1x),
.resync_clk_2x (resync_clk_2x),
.reset_phy_clk_1x_n (reset_rdp_phy_clk_1x_n),
.reset_resync_clk_2x_n (reset_resync_clk_2x_n),
.seq_rdp_dec_read_lat_1x (seq_rdp_dec_read_lat_1x[0]),
.seq_rdp_dmx_swap (1'b0),
.seq_rdp_inc_read_lat_1x (seq_rdp_inc_read_lat_1x[0]),
.dio_rdata_h_2x (dio_rdata_h_2x),
.dio_rdata_l_2x (dio_rdata_l_2x),
.ctl_mem_rdata (ctl_rdata)
);
// enhancements a different delay per dqs group may be implemented using the
// full vector
// Instance the write datapath :
generate
// Half-rate Write datapath :
if (DWIDTH_RATIO == 4)
begin : half_rate_wdp_gen
//
ddr_ctrl_ip_phy_alt_mem_phy_write_dp #(
.BIDIR_DPINS (1),
.LOCAL_IF_DRATE ("HALF"),
.LOCAL_IF_DWIDTH (LOCAL_IF_DWIDTH),
.MEM_IF_DM_WIDTH (MEM_IF_DM_WIDTH),
.MEM_IF_DQ_PER_DQS (MEM_IF_DQ_PER_DQS),
.MEM_IF_DQS_WIDTH (MEM_IF_DQS_WIDTH),
.GENERATE_WRITE_DQS (1),
.MEM_IF_DWIDTH (MEM_IF_DWIDTH),
.DWIDTH_RATIO (DWIDTH_RATIO)
) wdp (
.phy_clk_1x (phy_clk_1x),
.mem_clk_2x (mem_clk_2x),
.write_clk_2x (write_clk_2x),
.reset_phy_clk_1x_n (reset_phy_clk_1x_n),
.reset_mem_clk_2x_n (reset_mem_clk_2x_n),
.reset_write_clk_2x_n (reset_write_clk_2x_n),
.ctl_mem_be (ctl_dm),
.ctl_mem_dqs_burst (ctl_dqs_burst),
.ctl_mem_wdata (ctl_wdata),
.ctl_mem_wdata_valid (ctl_wdata_valid),
.seq_be (seq_wdp_dm),
.seq_dqs_burst (seq_wdp_dqs_burst),
.seq_wdata (seq_wdp_wdata),
.seq_wdata_valid (seq_wdp_wdata_valid),
.seq_ctl_sel (seq_wdp_ovride),
.wdp_wdata_h_2x (wdp_wdata_h_2x),
.wdp_wdata_l_2x (wdp_wdata_l_2x),
.wdp_wdata_oe_2x (wdp_wdata_oe_2x),
.wdp_wdqs_2x (wdp_wdqs_2x),
.wdp_wdqs_oe_2x (wdp_wdqs_oe_2x),
.wdp_dm_h_2x (wdp_dm_h_2x),
.wdp_dm_l_2x (wdp_dm_l_2x)
);
end
// Full-rate :
else
begin : full_rate_wdp_gen
//
ddr_ctrl_ip_phy_alt_mem_phy_write_dp_fr #(
.BIDIR_DPINS (1),
.LOCAL_IF_DRATE ("FULL"),
.LOCAL_IF_DWIDTH (LOCAL_IF_DWIDTH),
.MEM_IF_DM_WIDTH (MEM_IF_DM_WIDTH),
.MEM_IF_DQ_PER_DQS (MEM_IF_DQ_PER_DQS),
.MEM_IF_DQS_WIDTH (MEM_IF_DQS_WIDTH),
.GENERATE_WRITE_DQS (1),
.MEM_IF_DWIDTH (MEM_IF_DWIDTH),
.DWIDTH_RATIO (DWIDTH_RATIO)
) wdp (
.phy_clk_1x (phy_clk_1x),
.mem_clk_2x (mem_clk_2x),
.write_clk_2x (write_clk_2x),
.reset_phy_clk_1x_n (reset_phy_clk_1x_n),
.reset_mem_clk_2x_n (reset_mem_clk_2x_n),
.reset_write_clk_2x_n (reset_write_clk_2x_n),
.ctl_mem_be (ctl_dm),
.ctl_mem_dqs_burst (ctl_dqs_burst),
.ctl_mem_wdata (ctl_wdata),
.ctl_mem_wdata_valid (ctl_wdata_valid),
.seq_be (seq_wdp_dm),
.seq_dqs_burst (seq_wdp_dqs_burst),
.seq_wdata (seq_wdp_wdata),
.seq_wdata_valid (seq_wdp_wdata_valid),
.seq_ctl_sel (seq_wdp_ovride),
.wdp_wdata_h_2x (wdp_wdata_h_2x),
.wdp_wdata_l_2x (wdp_wdata_l_2x),
.wdp_wdata_oe_2x (wdp_wdata_oe_2x),
.wdp_wdqs_2x (wdp_wdqs_2x),
.wdp_wdqs_oe_2x (wdp_wdqs_oe_2x),
.wdp_dm_h_2x (wdp_dm_h_2x),
.wdp_dm_l_2x (wdp_dm_l_2x)
);
end
endgenerate
// Instance the address and command :
generate
// Half-rate address and command :
if (DWIDTH_RATIO == 4)
begin : half_rate_adc_gen
//
ddr_ctrl_ip_phy_alt_mem_phy_addr_cmd #(
.DWIDTH_RATIO (DWIDTH_RATIO),
.MEM_ADDR_CMD_BUS_COUNT (1),
.MEM_IF_BANKADDR_WIDTH (MEM_IF_BANKADDR_WIDTH),
.MEM_IF_CS_WIDTH (MEM_IF_CS_WIDTH),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.MEM_IF_ROWADDR_WIDTH (MEM_IF_ADDR_WIDTH)
) adc (
.ac_clk_2x (ac_clk_2x),
.cs_n_clk_2x (cs_n_clk_2x),
.phy_clk_1x (phy_clk_1x),
.reset_ac_clk_2x_n (reset_ac_clk_2x_n),
.reset_cs_n_clk_2x_n (reset_cs_n_clk_2x_n),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat_internal),
.ctl_add_1t_odt_lat (ctl_add_1t_odt_lat_internal),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs_internal),
// .ctl_negedge_en (ctl_negedge_en_internal),
.ctl_negedge_en (ADDR_CMD_NEGEDGE_EN[0 : 0]),
.ctl_mem_addr_h (ctl_addr[MEM_IF_ADDR_WIDTH -1 : 0]),
.ctl_mem_addr_l (ctl_addr[(MEM_IF_ADDR_WIDTH * DWIDTH_RATIO/2) -1 : MEM_IF_ADDR_WIDTH]),
.ctl_mem_ba_h (ctl_ba[MEM_IF_BANKADDR_WIDTH -1 : 0]),
.ctl_mem_ba_l (ctl_ba[MEM_IF_BANKADDR_WIDTH * DWIDTH_RATIO/2 -1 : MEM_IF_BANKADDR_WIDTH]),
.ctl_mem_cas_n_h (ctl_cas_n[0]),
.ctl_mem_cas_n_l (ctl_cas_n[1]),
.ctl_mem_cke_h (ctl_cke[MEM_IF_CS_WIDTH - 1 : 0]),
.ctl_mem_cke_l (ctl_cke[MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1 : MEM_IF_CS_WIDTH]),
.ctl_mem_cs_n_h (ctl_cs_n[MEM_IF_CS_WIDTH - 1 : 0]),
.ctl_mem_cs_n_l (ctl_cs_n[MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1 : MEM_IF_CS_WIDTH]),
.ctl_mem_odt_h (ctl_odt[MEM_IF_CS_WIDTH - 1 : 0]),
.ctl_mem_odt_l (ctl_odt[MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1 : MEM_IF_CS_WIDTH]),
.ctl_mem_ras_n_h (ctl_ras_n[0]),
.ctl_mem_ras_n_l (ctl_ras_n[1]),
.ctl_mem_we_n_h (ctl_we_n[0]),
.ctl_mem_we_n_l (ctl_we_n[1]),
.seq_addr_h (seq_ac_addr[MEM_IF_ADDR_WIDTH -1 : 0]),
.seq_addr_l (seq_ac_addr[MEM_IF_ADDR_WIDTH * DWIDTH_RATIO/2 -1 : MEM_IF_ADDR_WIDTH]),
.seq_ba_h (seq_ac_ba[MEM_IF_BANKADDR_WIDTH -1 : 0]),
.seq_ba_l (seq_ac_ba[MEM_IF_BANKADDR_WIDTH * DWIDTH_RATIO/2 -1 : MEM_IF_BANKADDR_WIDTH]),
.seq_cas_n_h (seq_ac_cas_n[0]),
.seq_cas_n_l (seq_ac_cas_n[1]),
.seq_cke_h (seq_ac_cke[MEM_IF_CS_WIDTH - 1 : 0]),
.seq_cke_l (seq_ac_cke[MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1 : MEM_IF_CS_WIDTH]),
.seq_cs_n_h (seq_ac_cs_n[MEM_IF_CS_WIDTH - 1 : 0]),
.seq_cs_n_l (seq_ac_cs_n[MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1 : MEM_IF_CS_WIDTH]),
.seq_odt_h (seq_ac_odt[MEM_IF_CS_WIDTH - 1 : 0]),
.seq_odt_l (seq_ac_odt[MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1 : MEM_IF_CS_WIDTH]),
.seq_ras_n_h (seq_ac_ras_n[0]),
.seq_ras_n_l (seq_ac_ras_n[1]),
.seq_we_n_h (seq_ac_we_n[0]),
.seq_we_n_l (seq_ac_we_n[1]),
.seq_ac_sel (seq_ac_sel),
.mem_addr (mem_addr),
.mem_ba (mem_ba),
.mem_cas_n (mem_cas_n),
.mem_cke (mem_cke),
.mem_cs_n (mem_cs_n),
.mem_odt (mem_odt),
.mem_ras_n (mem_ras_n),
.mem_we_n (mem_we_n)
);
end
// Full-rate :
else
begin : full_rate_adc_gen
//
ddr_ctrl_ip_phy_alt_mem_phy_addr_cmd #(
.DWIDTH_RATIO (DWIDTH_RATIO),
.MEM_ADDR_CMD_BUS_COUNT (1),
.MEM_IF_BANKADDR_WIDTH (MEM_IF_BANKADDR_WIDTH),
.MEM_IF_CS_WIDTH (MEM_IF_CS_WIDTH),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.MEM_IF_ROWADDR_WIDTH (MEM_IF_ADDR_WIDTH)
) adc (
.ac_clk_2x (ac_clk_2x),
.cs_n_clk_2x (cs_n_clk_2x),
.phy_clk_1x (phy_clk_1x),
.reset_ac_clk_2x_n (reset_ac_clk_2x_n),
.reset_cs_n_clk_2x_n (reset_cs_n_clk_2x_n),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat_internal),
.ctl_add_1t_odt_lat (ctl_add_1t_odt_lat_internal),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs_internal),
// .ctl_negedge_en (ctl_negedge_en_internal),
.ctl_negedge_en (ADDR_CMD_NEGEDGE_EN[0 : 0]),
.ctl_mem_addr_h (),
.ctl_mem_addr_l (ctl_addr[MEM_IF_ADDR_WIDTH -1 : 0]),
.ctl_mem_ba_h (),
.ctl_mem_ba_l (ctl_ba[MEM_IF_BANKADDR_WIDTH -1 : 0]),
.ctl_mem_cas_n_h (),
.ctl_mem_cas_n_l (ctl_cas_n[0]),
.ctl_mem_cke_h (),
.ctl_mem_cke_l (ctl_cke[MEM_IF_CS_WIDTH - 1 : 0]),
.ctl_mem_cs_n_h (),
.ctl_mem_cs_n_l (ctl_cs_n[MEM_IF_CS_WIDTH - 1 : 0]),
.ctl_mem_odt_h (),
.ctl_mem_odt_l (ctl_odt[MEM_IF_CS_WIDTH - 1 : 0]),
.ctl_mem_ras_n_h (),
.ctl_mem_ras_n_l (ctl_ras_n[0]),
.ctl_mem_we_n_h (),
.ctl_mem_we_n_l (ctl_we_n[0]),
.seq_addr_h (),
.seq_addr_l (seq_ac_addr[MEM_IF_ADDR_WIDTH -1 : 0]),
.seq_ba_h (),
.seq_ba_l (seq_ac_ba[MEM_IF_BANKADDR_WIDTH -1 : 0]),
.seq_cas_n_h (),
.seq_cas_n_l (seq_ac_cas_n[0]),
.seq_cke_h (),
.seq_cke_l (seq_ac_cke[MEM_IF_CS_WIDTH - 1 : 0]),
.seq_cs_n_h (),
.seq_cs_n_l (seq_ac_cs_n[MEM_IF_CS_WIDTH - 1 : 0]),
.seq_odt_h (),
.seq_odt_l (seq_ac_odt[MEM_IF_CS_WIDTH - 1 : 0]),
.seq_ras_n_h (),
.seq_ras_n_l (seq_ac_ras_n[0]),
.seq_we_n_h (),
.seq_we_n_l (seq_ac_we_n[0]),
.seq_ac_sel (seq_ac_sel),
.mem_addr (mem_addr),
.mem_ba (mem_ba),
.mem_cas_n (mem_cas_n),
.mem_cke (mem_cke),
.mem_cs_n (mem_cs_n),
.mem_odt (mem_odt),
.mem_ras_n (mem_ras_n),
.mem_we_n (mem_we_n)
);
end
endgenerate
assign int_rank_has_addr_swap = RANK_HAS_ADDR_SWAP[MEM_IF_CS_WIDTH - 1 : 0];
assign pll_resync_clk_index = 5;
assign pll_measure_clk_index = 4;
//
ddr_ctrl_ip_phy_alt_mem_phy_seq_wrapper
//
seq_wrapper (
.phy_clk_1x (phy_clk_1x),
.reset_phy_clk_1x_n (reset_phy_clk_1x_n),
.ctl_cal_success (ctl_cal_success),
.ctl_cal_fail (ctl_cal_fail),
.ctl_cal_warning (ctl_cal_warning),
.ctl_cal_req (ctl_cal_req),
.int_RANK_HAS_ADDR_SWAP (int_rank_has_addr_swap),
.ctl_cal_byte_lane_sel_n (ctl_cal_byte_lane_sel_n),
.seq_pll_inc_dec_n (seq_pll_inc_dec_n),
.seq_pll_start_reconfig (seq_pll_start_reconfig),
.seq_pll_select (seq_pll_select),
.phs_shft_busy (phs_shft_busy),
.pll_resync_clk_index (pll_resync_clk_index),
.pll_measure_clk_index (pll_measure_clk_index),
.sc_clk_dp (),
.scan_enable_dqs_config (),
.scan_update (),
.scan_din (),
.scan_enable_ck (),
.scan_enable_dqs (),
.scan_enable_dqsn (),
.scan_enable_dq (),
.scan_enable_dm (),
.hr_rsc_clk (1'b0), // Halfrate resync clock not required for non-SIII style families.
.seq_ac_addr (seq_ac_addr),
.seq_ac_ba (seq_ac_ba),
.seq_ac_cas_n (seq_ac_cas_n),
.seq_ac_ras_n (seq_ac_ras_n),
.seq_ac_we_n (seq_ac_we_n),
.seq_ac_cke (seq_ac_cke),
.seq_ac_cs_n (seq_ac_cs_n),
.seq_ac_odt (seq_ac_odt),
.seq_ac_rst_n (seq_ac_rst_n),
.seq_ac_sel (seq_ac_sel),
.seq_mem_clk_disable (seq_mem_clk_disable),
.ctl_add_1t_ac_lat_internal (ctl_add_1t_ac_lat_internal),
.ctl_add_1t_odt_lat_internal (ctl_add_1t_odt_lat_internal),
.ctl_add_intermediate_regs_internal (ctl_add_intermediate_regs_internal),
.seq_rdv_doing_rd (seq_doing_rd),
.seq_rdp_reset_req_n (seq_rdp_reset_req_n),
.seq_rdp_inc_read_lat_1x (seq_rdp_inc_read_lat_1x),
.seq_rdp_dec_read_lat_1x (seq_rdp_dec_read_lat_1x),
.ctl_rdata (ctl_rdata),
.int_rdata_valid_1t (seq_rdata_valid),
.seq_rdata_valid_lat_inc (seq_rdata_valid_lat_inc),
.seq_rdata_valid_lat_dec (seq_rdata_valid_lat_dec),
.ctl_rlat (ctl_rlat),
.seq_poa_lat_dec_1x (),
.seq_poa_lat_inc_1x (),
.seq_poa_protection_override_1x (),
.seq_oct_oct_delay (seq_oct_oct_delay),
.seq_oct_oct_extend (seq_oct_oct_extend),
.seq_oct_val (seq_oct_val),
.seq_wdp_dqs_burst (seq_wdp_dqs_burst),
.seq_wdp_wdata_valid (seq_wdp_wdata_valid),
.seq_wdp_wdata (seq_wdp_wdata),
.seq_wdp_dm (seq_wdp_dm),
.seq_wdp_dqs (seq_wdp_dqs),
.seq_wdp_ovride (seq_wdp_ovride),
.seq_dqs_add_2t_delay (seq_dqs_add_2t_delay),
.ctl_wlat (ctl_wlat),
.seq_mmc_start (seq_mmc_start),
.mmc_seq_done (mmc_seq_done),
.mmc_seq_value (mmc_seq_value),
.mem_err_out_n (1'b1),
.parity_error_n (),
.dbg_clk (dbg_clk),
.dbg_reset_n (dbg_reset_n),
.dbg_addr (dbg_addr),
.dbg_wr (dbg_wr),
.dbg_rd (dbg_rd),
.dbg_cs (dbg_cs),
.dbg_wr_data (dbg_wr_data),
.dbg_rd_data (dbg_rd_data),
.dbg_waitrequest (dbg_waitrequest)
);
// Generate rdata_valid for sequencer and control blocks
//
ddr_ctrl_ip_phy_alt_mem_phy_rdata_valid #(
.FAMILY (FAMILY),
.MEM_IF_DQS_WIDTH (MEM_IF_DQS_WIDTH),
.RDATA_VALID_AWIDTH (5),
.RDATA_VALID_INITIAL_LAT (RDV_INITIAL_LAT),
.DWIDTH_RATIO (DWIDTH_RATIO)
) rdv_pipe (
.phy_clk_1x (phy_clk_1x),
.reset_phy_clk_1x_n (reset_rdp_phy_clk_1x_n),
.seq_rdata_valid_lat_dec (seq_rdata_valid_lat_dec),
.seq_rdata_valid_lat_inc (seq_rdata_valid_lat_inc),
.seq_doing_rd (seq_doing_rd),
.ctl_doing_rd (ctl_doing_rd),
.ctl_cal_success (ctl_cal_success),
.ctl_rdata_valid (ctl_rdata_valid),
.seq_rdata_valid (seq_rdata_valid)
);
// Instance the CIII clock and reset :
//
ddr_ctrl_ip_phy_alt_mem_phy_clk_reset #(
.AC_PHASE (MEM_IF_ADDR_CMD_PHASE),
.CLOCK_INDEX_WIDTH (CLOCK_INDEX_WIDTH),
.CAPTURE_MIMIC_PATH (CAPTURE_MIMIC_PATH),
.DDR_MIMIC_PATH_EN (DDR_MIMIC_PATH_EN),
.DEDICATED_MEMORY_CLK_EN (DEDICATED_MEMORY_CLK_EN),
.DLL_EXPORT_IMPORT (DLL_EXPORT_IMPORT),
.DWIDTH_RATIO (DWIDTH_RATIO),
.LOCAL_IF_CLK_PS (LOCAL_IF_CLK_PS),
.MEM_IF_CLK_PAIR_COUNT (MEM_IF_CLK_PAIR_COUNT),
.MEM_IF_CLK_PS (MEM_IF_CLK_PS),
.MEM_IF_CS_WIDTH (MEM_IF_CS_WIDTH),
.MEM_IF_DQ_PER_DQS (MEM_IF_DQ_PER_DQS),
.MEM_IF_DQS_WIDTH (MEM_IF_DQS_WIDTH),
.MEM_IF_DWIDTH (MEM_IF_DWIDTH),
.MIF_FILENAME ("PLL.MIF"),
.PLL_EXPORT_IMPORT ("NONE"),
.PLL_REF_CLK_PS (PLL_REF_CLK_PS),
.PLL_TYPE ("ENHANCED"),
.SPEED_GRADE ("C6"),
.DLL_DELAY_BUFFER_MODE (DLL_DELAY_BUFFER_MODE),
.DLL_DELAY_CHAIN_LENGTH (DLL_DELAY_CHAIN_LENGTH),
.DQS_OUT_MODE (DQS_OUT_MODE),
.DQS_PHASE (DQS_PHASE),
.SCAN_CLK_DIVIDE_BY (SCAN_CLK_DIVIDE_BY),
.USE_MEM_CLK_FOR_ADDR_CMD_CLK (USE_MEM_CLK_FOR_ADDR_CMD_CLK)
) clk (
.pll_ref_clk (pll_ref_clk),
.global_reset_n (global_reset_n),
.soft_reset_n (soft_reset_n),
.seq_rdp_reset_req_n (seq_rdp_reset_req_n),
.ac_clk_2x (ac_clk_2x),
.measure_clk_2x (measure_clk_2x),
.mem_clk_2x (mem_clk_2x),
.mem_clk (mem_clk),
.mem_clk_n (mem_clk_n),
.phy_clk_1x (phy_clk_1x_src),
.resync_clk_2x (resync_clk_2x),
.cs_n_clk_2x (cs_n_clk_2x),
.write_clk_2x (write_clk_2x),
.half_rate_clk (half_rate_clk),
.reset_ac_clk_2x_n (reset_ac_clk_2x_n),
.reset_measure_clk_2x_n (reset_measure_clk_2x_n),
.reset_mem_clk_2x_n (reset_mem_clk_2x_n),
.reset_phy_clk_1x_n (reset_phy_clk_1x_n),
.reset_resync_clk_2x_n (reset_resync_clk_2x_n),
.reset_write_clk_2x_n (reset_write_clk_2x_n),
.reset_cs_n_clk_2x_n (reset_cs_n_clk_2x_n),
.reset_rdp_phy_clk_1x_n (reset_rdp_phy_clk_1x_n),
.mem_reset_n (mem_reset_n),
.reset_request_n (reset_request_n),
.phs_shft_busy (phs_shft_busy),
.seq_pll_inc_dec_n (seq_pll_inc_dec_n),
.seq_pll_select (seq_pll_select),
.seq_pll_start_reconfig (seq_pll_start_reconfig),
.mimic_data_2x (mimic_data),
.seq_clk_disable (seq_mem_clk_disable),
.ctrl_clk_disable (ctl_mem_clk_disable)
);
// Instance the mimic block :
//
ddr_ctrl_ip_phy_alt_mem_phy_mimic #(
.NUM_MIMIC_SAMPLE_CYCLES (NUM_MIMIC_SAMPLE_CYCLES)
) mmc (
.measure_clk (measure_clk_2x),
.reset_measure_clk_n (reset_measure_clk_2x_n),
.mimic_data_in (mimic_data),
.seq_mmc_start (seq_mmc_start),
.mmc_seq_done (mmc_seq_done),
.mmc_seq_value (mmc_seq_value)
);
// If required, instance the Mimic debug block. If the debug block is used, a top level input
// for mimic_recapture_debug_data should be created.
generate
if (MIMIC_DEBUG_EN == 1)
begin : create_mimic_debug_ram
//
ddr_ctrl_ip_phy_alt_mem_phy_mimic_debug #(
.NUM_DEBUG_SAMPLES_TO_STORE (NUM_DEBUG_SAMPLES_TO_STORE),
.PLL_STEPS_PER_CYCLE (PLL_STEPS_PER_CYCLE)
) mmc_debug (
.measure_clk (measure_clk_1x),
.reset_measure_clk_n (reset_measure_clk_1x_n),
.mmc_seq_done (mmc_seq_done),
.mmc_seq_value (mmc_seq_value),
.mimic_recapture_debug_data (1'b0)
);
end
endgenerate
endmodule
`default_nettype wire
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr_ctrl_ip_phy_alt_mem_phy_clk_reset (
pll_ref_clk,
global_reset_n,
soft_reset_n,
seq_rdp_reset_req_n,
ac_clk_2x,
measure_clk_2x,
mem_clk_2x,
mem_clk,
mem_clk_n,
phy_clk_1x,
resync_clk_2x,
cs_n_clk_2x,
write_clk_2x,
half_rate_clk,
reset_ac_clk_2x_n,
reset_measure_clk_2x_n,
reset_mem_clk_2x_n,
reset_phy_clk_1x_n,
reset_resync_clk_2x_n,
reset_write_clk_2x_n,
reset_cs_n_clk_2x_n,
reset_rdp_phy_clk_1x_n,
mem_reset_n,
reset_request_n, // new output
phs_shft_busy,
seq_pll_inc_dec_n,
seq_pll_select,
seq_pll_start_reconfig,
mimic_data_2x,
seq_clk_disable,
ctrl_clk_disable
) /* synthesis altera_attribute="SUPPRESS_DA_RULE_INTERNAL=\"R101,C104\"" */;
// Note the peculiar ranging below is necessary to use a generated CASE statement
// later in the code :
parameter AC_PHASE = "MEM_CLK";
parameter CLOCK_INDEX_WIDTH = 3;
parameter [0:0] CAPTURE_MIMIC_PATH = 0;
parameter [0:0] DDR_MIMIC_PATH_EN = 1;
parameter [0:0] DEDICATED_MEMORY_CLK_EN = 0;
parameter DLL_EXPORT_IMPORT = "NONE";
parameter DWIDTH_RATIO = 4;
parameter LOCAL_IF_CLK_PS = 4000;
parameter MEM_IF_CLK_PAIR_COUNT = 3;
parameter MEM_IF_CLK_PS = 4000;
parameter MEM_IF_CS_WIDTH = 2;
parameter MEM_IF_DQ_PER_DQS = 8;
parameter MEM_IF_DQS_WIDTH = 8;
parameter MEM_IF_DWIDTH = 64;
parameter MIF_FILENAME = "PLL.MIF";
parameter PLL_EXPORT_IMPORT = "NONE";
parameter PLL_REF_CLK_PS = 4000;
parameter PLL_TYPE = "ENHANCED";
parameter SPEED_GRADE = "C3";
parameter DLL_DELAY_BUFFER_MODE = "HIGH";
parameter DLL_DELAY_CHAIN_LENGTH = 10;
parameter DQS_OUT_MODE = "DELAY_CHAIN2";
parameter DQS_PHASE = 72;
parameter SCAN_CLK_DIVIDE_BY = 2;
parameter USE_MEM_CLK_FOR_ADDR_CMD_CLK = 1;
// Clock/reset inputs :
input wire global_reset_n;
input wire pll_ref_clk;
input wire soft_reset_n;
input wire seq_rdp_reset_req_n;
// Clock/reset outputs :
(* altera_attribute = "-name global_signal global_clock" *) output wire ac_clk_2x;
(* altera_attribute = "-name global_signal regional_clock" *) output wire measure_clk_2x;
(* altera_attribute = "-name global_signal global_clock" *) output wire mem_clk_2x;
inout wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mem_clk;
inout wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mem_clk_n;
(* altera_attribute = "-name global_signal global_clock" *) output wire phy_clk_1x;
(* altera_attribute = "-name global_signal regional_clock" *) output wire resync_clk_2x;
(* altera_attribute = "-name global_signal global_clock" *) output wire cs_n_clk_2x;
(* altera_attribute = "-name global_signal global_clock" *) output wire write_clk_2x;
output wire half_rate_clk;
output wire reset_ac_clk_2x_n;
output wire reset_measure_clk_2x_n;
output wire reset_mem_clk_2x_n;
output reg reset_phy_clk_1x_n;
output wire reset_resync_clk_2x_n;
output wire reset_write_clk_2x_n;
output wire reset_cs_n_clk_2x_n;
output wire reset_rdp_phy_clk_1x_n;
output wire mem_reset_n;
// This is the PLL locked signal :
output wire reset_request_n;
// Misc I/O :
output reg phs_shft_busy;
input wire seq_pll_inc_dec_n;
input wire [CLOCK_INDEX_WIDTH - 1 : 0 ] seq_pll_select;
input wire seq_pll_start_reconfig;
output wire mimic_data_2x;
input wire seq_clk_disable;
input wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] ctrl_clk_disable;
(*preserve*) reg seq_pll_start_reconfig_ams;
(*preserve*) reg seq_pll_start_reconfig_r;
(*preserve*) reg seq_pll_start_reconfig_2r;
(*preserve*) reg seq_pll_start_reconfig_3r;
wire pll_scanclk;
wire pll_scanread;
wire pll_scanwrite;
wire pll_scandata;
wire pll_scandone;
wire pll_scandataout;
reg pll_new_dir;
reg [2:0] pll_new_phase;
wire pll_phase_auto_calibrate_pulse;
reg [`CLK_PLL_RECONFIG_FSM_WIDTH-1:0] pll_reconfig_state;
reg pll_reconfig_initialised;
reg [CLOCK_INDEX_WIDTH - 1 : 0 ] pll_current_phase;
reg pll_current_dir;
reg [`CLK_PLL_RECONFIG_FSM_WIDTH-1:0] next_pll_reconfig_state;
reg next_pll_reconfig_initialised;
reg [CLOCK_INDEX_WIDTH - 1 : 0 ] next_pll_current_phase;
reg next_pll_current_dir;
(*preserve*) reg pll_reprogram_request_pulse; // 1 scan clk cycle long
(*preserve*) reg pll_reprogram_request_pulse_r;
(*preserve*) reg pll_reprogram_request_pulse_2r;
wire pll_reprogram_request_long_pulse; // 3 scan clk cycles long
(*preserve*) reg pll_reprogram_request;
wire pll_reconfig_busy;
reg pll_reconfig;
reg pll_reconfig_write_param;
reg [3:0] pll_reconfig_counter_type;
reg [8:0] pll_reconfig_data_in;
wire pll_locked;
wire phy_internal_reset_n;
wire pll_reset;
(*preserve*) reg global_pre_clear;
wire global_or_soft_reset_n;
(*preserve*) reg clk_div_reset_ams_n = 1'b0;
(*preserve*) reg clk_div_reset_ams_n_r = 1'b0;
(*preserve*) reg pll_reconfig_reset_ams_n = 1'b0;
(*preserve*) reg pll_reconfig_reset_ams_n_r = 1'b0;
(*preserve*) reg reset_master_ams;
wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mimic_data_2x_internal;
// Create the scan clock. This is a divided-down version of the PLL reference clock.
// The scan chain will have an Fmax of around 100MHz, and so initially the scan clock is
// created by a divide-by 4 circuit to allow plenty of margin with the expected reference
// clock frequency of 100MHz. This may be changed via the parameter.
reg [2:0] divider = 3'h0;
(*preserve*) reg scan_clk = 1'b0;
(*preserve*) reg global_reset_ams_n = 1'b0;
(*preserve*) reg global_reset_ams_n_r = 1'b0;
wire pll_phase_done;
(*preserve*) reg [2:0] seq_pll_start_reconfig_ccd_pipe;
(*preserve*) reg seq_pll_inc_dec_ccd;
(*preserve*) reg [CLOCK_INDEX_WIDTH - 1 : 0] seq_pll_select_ccd ;
wire pll_reconfig_reset_n;
wire clk_divider_reset_n;
// Output the PLL locked signal to be used as a reset_request_n - IE. reset when the PLL loses
// lock :
assign reset_request_n = pll_locked;
// Reset the scanclk clock divider if we either have a global_reset or the PLL loses lock
assign pll_reconfig_reset_n = global_reset_n && pll_locked;
// Clock divider circuit reset generation.
always @(posedge phy_clk_1x or negedge pll_reconfig_reset_n)
begin
if (pll_reconfig_reset_n == 1'b0)
begin
clk_div_reset_ams_n <= 1'b0;
clk_div_reset_ams_n_r <= 1'b0;
end
else
begin
clk_div_reset_ams_n <= 1'b1;
clk_div_reset_ams_n_r <= clk_div_reset_ams_n;
end
end
// PLL reconfig and synchronisation circuit reset generation.
always @(posedge scan_clk or negedge pll_reconfig_reset_n)
begin
if (pll_reconfig_reset_n == 1'b0)
begin
pll_reconfig_reset_ams_n <= 1'b0;
pll_reconfig_reset_ams_n_r <= 1'b0;
end
else
begin
pll_reconfig_reset_ams_n <= 1'b1;
pll_reconfig_reset_ams_n_r <= pll_reconfig_reset_ams_n;
end
end
// Create the scan clock. Used for PLL reconfiguring in this block.
// Clock divider reset is the direct output of the AMS flops :
assign clk_divider_reset_n = clk_div_reset_ams_n_r;
generate
if (SCAN_CLK_DIVIDE_BY == 1)
begin : no_scan_clk_divider
always @(phy_clk_1x)
begin
scan_clk = phy_clk_1x;
end
end
else
begin : gen_scan_clk
always @(posedge phy_clk_1x or negedge clk_divider_reset_n)
begin
if (clk_divider_reset_n == 1'b0)
begin
scan_clk <= 1'b0;
divider <= 3'h0;
end
else
begin
// This method of clock division does not require "divider" to be used
// as an intermediate clock:
if (divider == (SCAN_CLK_DIVIDE_BY / 2 - 1))
begin
scan_clk <= ~scan_clk; // Toggle
divider <= 3'h0;
end
else
begin
scan_clk <= scan_clk; // Do not toggle
divider <= divider + 3'h1;
end
end
end
end
endgenerate
// NB. This lookup table shall be different for CIII/SIII
// The PLL phasecounterselect is 3 bits wide, therefore hardcode the output to 3 bits :
function [2:0] lookup;
input [CLOCK_INDEX_WIDTH-1:0] seq_num;
begin
casez (seq_num)
3'b000 : lookup = 3'b010; // legal code
3'b001 : lookup = 3'b011; // legal code
3'b010 : lookup = 3'b111; // illegal - return code 3'b111
3'b011 : lookup = 3'b100; // legal code
3'b100 : lookup = 3'b110; // legal code
3'b101 : lookup = 3'b101; // legal code
3'b110 : lookup = 3'b111; // illegal - return code 3'b111
3'b111 : lookup = 3'b111; // illegal - return code 3'b111
default : lookup = 3'bxxx; // X propagation
endcase
end
endfunction
// Metastable-harden seq_pll_start_reconfig signal (from the phy clock domain). NB:
// by double-clocking this signal, it is not necessary to double-clock the
// seq_pll_inc_dec_n and seq_pll_select signals - since they will only get
// used on a positive edge of the metastable-hardened seq_pll_start_reconfig signal (so
// should be stable by that point).
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
seq_pll_inc_dec_ccd <= 1'b0;
seq_pll_select_ccd <= {CLOCK_INDEX_WIDTH{1'b0}};
seq_pll_start_reconfig_ccd_pipe <= 3'b000;
end
// Generate 'ccd' Cross Clock Domain signals :
else
begin
seq_pll_start_reconfig_ccd_pipe <= {seq_pll_start_reconfig_ccd_pipe[1:0], seq_pll_start_reconfig};
if (seq_pll_start_reconfig == 1'b1 && seq_pll_start_reconfig_ccd_pipe[0] == 1'b0)
begin
seq_pll_inc_dec_ccd <= seq_pll_inc_dec_n;
seq_pll_select_ccd <= seq_pll_select;
end
end
end
always @(posedge scan_clk or negedge pll_reconfig_reset_ams_n_r)
begin
if (pll_reconfig_reset_ams_n_r == 1'b0)
begin
seq_pll_start_reconfig_ams <= 1'b0;
seq_pll_start_reconfig_r <= 1'b0;
seq_pll_start_reconfig_2r <= 1'b0;
seq_pll_start_reconfig_3r <= 1'b0;
pll_reprogram_request_pulse <= 1'b0;
pll_reprogram_request_pulse_r <= 1'b0;
pll_reprogram_request_pulse_2r <= 1'b0;
pll_reprogram_request <= 1'b0;
end
else
begin
seq_pll_start_reconfig_ams <= seq_pll_start_reconfig_ccd_pipe[2];
seq_pll_start_reconfig_r <= seq_pll_start_reconfig_ams;
seq_pll_start_reconfig_2r <= seq_pll_start_reconfig_r;
seq_pll_start_reconfig_3r <= seq_pll_start_reconfig_2r;
pll_reprogram_request_pulse <= pll_phase_auto_calibrate_pulse;
pll_reprogram_request_pulse_r <= pll_reprogram_request_pulse;
pll_reprogram_request_pulse_2r <= pll_reprogram_request_pulse_r;
pll_reprogram_request <= pll_reprogram_request_long_pulse;
end
end
// Rising-edge detect to generate a single phase shift step
assign pll_phase_auto_calibrate_pulse = ~seq_pll_start_reconfig_3r && seq_pll_start_reconfig_2r;
// extend the phase shift request pulse to be 3 scan clk cycles long.
assign pll_reprogram_request_long_pulse = pll_reprogram_request_pulse || pll_reprogram_request_pulse_r || pll_reprogram_request_pulse_2r;
// Register the Phase step settings
always @(posedge scan_clk or negedge pll_reconfig_reset_ams_n_r)
begin
if (pll_reconfig_reset_ams_n_r == 1'b0)
begin
pll_new_dir <= 1'b0;
pll_new_phase <= 3'h0; // CIII PLL has 3bit phase select
end
else
begin
if (pll_phase_auto_calibrate_pulse)
begin
pll_new_dir <= seq_pll_inc_dec_ccd;
pll_new_phase <= lookup(seq_pll_select_ccd);
end
end
end
// generate the busy signal - just the inverse of the done o/p from the pll OR'd with the reprogram request (in case the done o/p is missed).
always @(posedge scan_clk or negedge pll_reconfig_reset_ams_n_r)
begin
if (pll_reconfig_reset_ams_n_r == 1'b0)
phs_shft_busy <= 1'b0;
else
phs_shft_busy <= pll_reprogram_request || ~pll_phase_done;
end
// Gate the soft reset input (from SOPC builder for example) with the PLL
// locked signal :
assign global_or_soft_reset_n = soft_reset_n && global_reset_n;
// Create the PHY internal reset signal :
assign phy_internal_reset_n = pll_locked && global_or_soft_reset_n;
// The PLL resets only on a global reset :
assign pll_reset = !global_reset_n;
generate
// Half-rate mode :
if (DWIDTH_RATIO == 4)
begin
//
ddr_ctrl_ip_phy_alt_mem_phy_pll pll(
.areset(pll_reset),
.inclk0(pll_ref_clk),
.phasecounterselect(pll_new_phase),
.phasestep(pll_reprogram_request),
.phaseupdown(pll_new_dir),
.scanclk(scan_clk),
.c0(phy_clk_1x),
.c1(mem_clk_2x),
.c2(write_clk_2x),
.c3(resync_clk_2x),
.c4(measure_clk_2x),
.locked(pll_locked),
.phasedone(pll_phase_done)
);
assign half_rate_clk = phy_clk_1x;
end
// Full-rate mode :
else
begin
//
ddr_ctrl_ip_phy_alt_mem_phy_pll pll(
.areset(pll_reset),
.inclk0(pll_ref_clk),
.phasecounterselect(pll_new_phase),
.phasestep(pll_reprogram_request),
.phaseupdown(pll_new_dir),
.scanclk(scan_clk),
.c0(half_rate_clk),
.c1(mem_clk_2x),
.c2(write_clk_2x),
.c3(resync_clk_2x),
.c4(measure_clk_2x),
.locked(pll_locked),
.phasedone(pll_phase_done)
);
// NB. phy_clk_1x is now full-rate, despite the "1x" naming convention :
assign phy_clk_1x = mem_clk_2x;
end
endgenerate
generate
if (USE_MEM_CLK_FOR_ADDR_CMD_CLK == 1)
begin
assign ac_clk_2x = mem_clk_2x;
assign cs_n_clk_2x = mem_clk_2x;
end
else
begin
assign ac_clk_2x = write_clk_2x;
assign cs_n_clk_2x = write_clk_2x;
end
endgenerate
//NB. cannot use altddio_out instantiations, as need the combout and regout outputs for mimic path.
generate
genvar clk_pair;
case ({DDR_MIMIC_PATH_EN, CAPTURE_MIMIC_PATH, DEDICATED_MEMORY_CLK_EN})
// Mimic path option 1 - this is the default configuration
default :
begin
for (clk_pair = 0 ; clk_pair < MEM_IF_CLK_PAIR_COUNT; clk_pair = clk_pair + 1)
begin : DDR_CLK_OUT
// Instance "mem_clk" output pad, with appropriate mimic path connections :
altddio_bidir #(
.extend_oe_disable ("UNUSED"),
.implement_input_in_lcell ("UNUSED"),
.intended_device_family ("Cyclone III"),
.invert_output ("OFF"),
.lpm_type ("altddio_bidir"),
.oe_reg ("UNUSED"),
.power_up_high ("OFF"),
.width (1)
)ddr_clk_out_p (
.padio (mem_clk[clk_pair]),
.outclock (~mem_clk_2x),
.inclock (measure_clk_2x),
.oe (1'b1),
.datain_h (1'b0),
.datain_l (1'b1),
.dataout_h (mimic_data_2x_internal[clk_pair]),
.dataout_l (),
.aclr (seq_clk_disable || ctrl_clk_disable[clk_pair]),
.aset (),
.combout (),
.dqsundelayedout (),
.inclocken (),
.oe_out (),
.outclocken (1'b1),
.sclr (1'b0),
.sset (1'b0)
);
// Instance "mem_clk_n" output pad, no mimic connections made as these are on the
// 'mem_clk' :
altddio_bidir #(
.extend_oe_disable ("UNUSED"),
.implement_input_in_lcell ("UNUSED"),
.intended_device_family ("Cyclone III"),
.invert_output ("OFF"),
.lpm_type ("altddio_bidir"),
.oe_reg ("UNUSED"),
.power_up_high ("OFF"),
.width (1)
)ddr_clk_out_n (
.padio (mem_clk_n[clk_pair]),
.outclock (mem_clk_2x),
.inclock (),
.oe (1'b1),
.datain_h (1'b0),
.datain_l (1'b1),
.dataout_h (),
.dataout_l (),
.aclr (seq_clk_disable || ctrl_clk_disable[clk_pair]),
.aset (),
.combout (),
.dqsundelayedout (),
.inclocken (),
.oe_out (),
.outclocken (1'b1),
.sclr (1'b0),
.sset (1'b0)
);
end //for
// Pick off the mimic data from the first internal mimic_data signal :
assign mimic_data_2x = mimic_data_2x_internal[0];
end // caseitem
endcase
endgenerate
// Master reset generation :
always @(posedge phy_clk_1x or negedge phy_internal_reset_n)
begin
if (phy_internal_reset_n == 1'b0)
begin
reset_master_ams <= 1'b0;
global_pre_clear <= 1'b0;
end
else
begin
reset_master_ams <= 1'b1;
global_pre_clear <= reset_master_ams;
end
end
// phy_clk reset generation :
always @(posedge phy_clk_1x or negedge global_pre_clear)
begin
if (global_pre_clear == 1'b0)
begin
reset_phy_clk_1x_n <= 1'b0;
end
else
begin
reset_phy_clk_1x_n <= global_pre_clear;
end
end
// NB. phy_clk reset is generated above.
// phy_clk reset generation for read datapaths :
//
ddr_ctrl_ip_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (2) ) reset_rdp_phy_clk_pipe(
.clock (phy_clk_1x),
.pre_clear (seq_rdp_reset_req_n && global_pre_clear),
.reset_out (reset_rdp_phy_clk_1x_n)
);
// mem_clk reset generation :
//
ddr_ctrl_ip_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (2) ) mem_pipe (
.clock (mem_clk_2x),
.pre_clear (global_pre_clear),
.reset_out (mem_reset_n)
);
// ac_clk_2x reset generation :
//
ddr_ctrl_ip_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (2) ) ac_clk_pipe_2x (
.clock (ac_clk_2x),
.pre_clear (global_pre_clear),
.reset_out (reset_ac_clk_2x_n)
);
// measure_clk_2x reset generation :
//
ddr_ctrl_ip_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (2) ) measure_clk_pipe (
.clock (measure_clk_2x),
.pre_clear (global_pre_clear),
.reset_out (reset_measure_clk_2x_n)
);
// mem_clk_2x reset generation :
//
ddr_ctrl_ip_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (4) ) mem_clk_pipe(
.clock (mem_clk_2x),
.pre_clear (global_pre_clear),
.reset_out (reset_mem_clk_2x_n)
);
// resync_clk_2x reset generation :
//
ddr_ctrl_ip_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (2) ) resync_clk_pipe(
.clock (resync_clk_2x),
.pre_clear (seq_rdp_reset_req_n && global_pre_clear),
.reset_out (reset_resync_clk_2x_n)
);
// write_clk_2x reset generation :
//
ddr_ctrl_ip_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (4) ) write_clk_pipe(
.clock (write_clk_2x),
.pre_clear (global_pre_clear),
.reset_out (reset_write_clk_2x_n)
);
// cs_clk_2x reset generation :
//
ddr_ctrl_ip_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (4) ) cs_n_clk_pipe_2x(
.clock (cs_n_clk_2x),
.pre_clear (global_pre_clear),
.reset_out (reset_cs_n_clk_2x_n)
);
endmodule
//
`default_nettype none
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr_ctrl_ip_phy_alt_mem_phy_ac (
clk_2x,
reset_2x_n,
phy_clk_1x,
ctl_add_1t_ac_lat,
ctl_negedge_en,
ctl_add_intermediate_regs,
period_sel,
seq_ac_sel,
ctl_ac_h,
ctl_ac_l,
seq_ac_h,
seq_ac_l,
mem_ac );
parameter POWER_UP_HIGH = 1;
parameter DWIDTH_RATIO = 4;
// NB. clk_2x could be either ac_clk_2x or cs_n_clk_2x :
input wire clk_2x;
input wire reset_2x_n;
input wire phy_clk_1x;
input wire ctl_add_1t_ac_lat;
input wire ctl_negedge_en;
input wire ctl_add_intermediate_regs;
input wire period_sel;
input wire seq_ac_sel;
input wire ctl_ac_h;
input wire ctl_ac_l;
input wire seq_ac_h;
input wire seq_ac_l;
output wire mem_ac;
(* preserve *) reg ac_h_r = POWER_UP_HIGH[0];
(* preserve *) reg ac_l_r = POWER_UP_HIGH[0];
(* preserve *) reg ac_h_2r = POWER_UP_HIGH[0];
(* preserve *) reg ac_l_2r = POWER_UP_HIGH[0];
(* preserve *) reg ac_1t = POWER_UP_HIGH[0];
(* preserve *) reg ac_2x = POWER_UP_HIGH[0];
(* preserve *) reg ac_2x_r = POWER_UP_HIGH[0];
(* preserve *) reg ac_2x_2r = POWER_UP_HIGH[0];
(* preserve *) reg ac_2x_mux = POWER_UP_HIGH[0];
reg ac_2x_retime = POWER_UP_HIGH[0];
reg ac_2x_retime_r = POWER_UP_HIGH[0];
reg ac_2x_deg_choice = POWER_UP_HIGH[0];
reg ac_h;
reg ac_l;
wire reset_2x ;
assign reset_2x = ~reset_2x_n;
generate
if (DWIDTH_RATIO == 4) //HR
begin : hr_mux_gen
// Half Rate DDR memory types require an extra cycle of latency :
always @(posedge phy_clk_1x)
begin
casez(seq_ac_sel)
1'b0 :
begin
ac_l <= ctl_ac_l;
ac_h <= ctl_ac_h;
end
1'b1 :
begin
ac_l <= seq_ac_l;
ac_h <= seq_ac_h;
end
endcase
end //always
end
else // FR
begin : fr_passthru_gen
// Note that "_h" is unused in full-rate and no latency
// is required :
always @*
begin
casez(seq_ac_sel)
1'b0 :
begin
ac_l <= ctl_ac_l;
end
1'b1 :
begin
ac_l <= seq_ac_l;
end
endcase
end
end
endgenerate
generate
if (DWIDTH_RATIO == 4)
begin : half_rate
// Initial registering of inputs :
always @(posedge phy_clk_1x)
begin
ac_h_r <= ac_h;
ac_l_r <= ac_l;
end
// Select high and low phases periodically to create the _2x signal :
always @*
begin
casez(period_sel)
1'b0 : ac_2x = ac_l_2r;
1'b1 : ac_2x = ac_h_2r;
default : ac_2x = 1'bx; // X propagaton
endcase
end
always @(posedge clk_2x)
begin
// Second stage of registering - on clk_2x
ac_h_2r <= ac_h_r;
ac_l_2r <= ac_l_r;
// 1t registering - used if ctl_add_1t_ac_lat is true
ac_1t <= ac_2x;
// AC_PHASE==270 requires an extra cycle of delay :
ac_2x_deg_choice <= ac_1t;
// If not at AC_PHASE==270, ctl_add_intermediate_regs shall be zero :
if (ctl_add_intermediate_regs == 1'b0)
begin
if (ctl_add_1t_ac_lat == 1'b1)
begin
ac_2x_r <= ac_1t;
end
else
begin
ac_2x_r <= ac_2x;
end
end
// If at AC_PHASE==270, ctl_add_intermediate_regs shall be one
// and an extra cycle delay is required :
else
begin
if (ctl_add_1t_ac_lat == 1'b1)
begin
ac_2x_r <= ac_2x_deg_choice;
end
else
begin
ac_2x_r <= ac_1t;
end
end
// Register the above output for use when ctl_negedge_en is set :
ac_2x_2r <= ac_2x_r;
end
// Determine whether to select the "_r" or "_2r" variant :
always @*
begin
casez(ctl_negedge_en)
1'b0 : ac_2x_mux = ac_2x_r;
1'b1 : ac_2x_mux = ac_2x_2r;
default : ac_2x_mux = 1'bx; // X propagaton
endcase
end
if (POWER_UP_HIGH == 1)
begin
altddio_out #(
.extend_oe_disable ("UNUSED"),
.intended_device_family ("Cyclone III"),
.lpm_hint ("UNUSED"),
.lpm_type ("altddio_out"),
.oe_reg ("UNUSED"),
.power_up_high ("ON"),
.width (1)
) addr_pin (
.aset (reset_2x),
.datain_h (ac_2x_mux),
.datain_l (ac_2x_r),
.dataout (mem_ac),
.oe (1'b1),
.outclock (clk_2x),
.outclocken (1'b1),
.aclr (),
.sset (),
.sclr (),
.oe_out ()
);
end
else
begin
altddio_out #(
.extend_oe_disable ("UNUSED"),
.intended_device_family ("Cyclone III"),
.lpm_hint ("UNUSED"),
.lpm_type ("altddio_out"),
.oe_reg ("UNUSED"),
.power_up_high ("OFF"),
.width (1)
) addr_pin (
.aclr (reset_2x),
.aset (),
.datain_h (ac_2x_mux),
.datain_l (ac_2x_r),
.dataout (mem_ac),
.oe (1'b1),
.outclock (clk_2x),
.outclocken (1'b1),
.sset (),
.sclr (),
.oe_out ()
);
end
end // Half-rate
// full-rate
else
begin : full_rate
always @(posedge phy_clk_1x)
begin
// 1t registering - only used if ctl_add_1t_ac_lat is true
ac_1t <= ac_l;
// add 1 addr_clock delay if "Add 1T" is set:
if (ctl_add_1t_ac_lat == 1'b1)
ac_2x <= ac_1t;
else
ac_2x <= ac_l;
end
always @(posedge clk_2x)
begin
ac_2x_deg_choice <= ac_2x;
end
// Note this is for 270 degree operation to align it to the correct clock phase.
always @*
begin
casez(ctl_add_intermediate_regs)
1'b0 : ac_2x_r = ac_2x;
1'b1 : ac_2x_r = ac_2x_deg_choice;
default : ac_2x_r = 1'bx; // X propagaton
endcase
end
always @(posedge clk_2x)
begin
ac_2x_2r <= ac_2x_r;
end
// Determine whether to select the "_r" or "_2r" variant :
always @*
begin
casez(ctl_negedge_en)
1'b0 : ac_2x_mux = ac_2x_r;
1'b1 : ac_2x_mux = ac_2x_2r;
default : ac_2x_mux = 1'bx; // X propagaton
endcase
end
if (POWER_UP_HIGH == 1)
begin
altddio_out #(
.extend_oe_disable ("UNUSED"),
.intended_device_family ("Cyclone III"),
.lpm_hint ("UNUSED"),
.lpm_type ("altddio_out"),
.oe_reg ("UNUSED"),
.power_up_high ("ON"),
.width (1)
) addr_pin (
.aset (reset_2x),
.datain_h (ac_2x_mux),
.datain_l (ac_2x_r),
.dataout (mem_ac),
.oe (1'b1),
.outclock (clk_2x),
.outclocken (1'b1),
.aclr (),
.sclr (),
.sset (),
.oe_out ()
);
end
else
begin
altddio_out #(
.extend_oe_disable ("UNUSED"),
.intended_device_family ("Cyclone III"),
.lpm_hint ("UNUSED"),
.lpm_type ("altddio_out"),
.oe_reg ("UNUSED"),
.power_up_high ("OFF"),
.width (1)
) addr_pin (
.aclr (reset_2x),
.datain_h (ac_2x_mux),
.datain_l (ac_2x_r),
.dataout (mem_ac),
.oe (1'b1),
.outclock (clk_2x),
.outclocken (1'b1),
.aset (),
.sclr (),
.sset (),
.oe_out ()
);
end // else: !if(POWER_UP_HIGH == 1)
end // block: full_rate
endgenerate
endmodule
`default_nettype wire
//
`default_nettype none
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr_ctrl_ip_phy_alt_mem_phy_addr_cmd (
ac_clk_2x,
cs_n_clk_2x,
phy_clk_1x,
reset_ac_clk_2x_n,
reset_cs_n_clk_2x_n,
// Addr/cmd interface from controller
ctl_add_1t_ac_lat,
ctl_add_1t_odt_lat,
ctl_add_intermediate_regs,
ctl_negedge_en,
ctl_mem_addr_h,
ctl_mem_addr_l,
ctl_mem_ba_h,
ctl_mem_ba_l,
ctl_mem_cas_n_h,
ctl_mem_cas_n_l,
ctl_mem_cke_h,
ctl_mem_cke_l,
ctl_mem_cs_n_h,
ctl_mem_cs_n_l,
ctl_mem_odt_h,
ctl_mem_odt_l,
ctl_mem_ras_n_h,
ctl_mem_ras_n_l,
ctl_mem_we_n_h,
ctl_mem_we_n_l,
// Interface from Sequencer, used for calibration
// as the MRS registers need to be controlled :
seq_addr_h,
seq_addr_l,
seq_ba_h,
seq_ba_l,
seq_cas_n_h,
seq_cas_n_l,
seq_cke_h,
seq_cke_l,
seq_cs_n_h,
seq_cs_n_l,
seq_odt_h,
seq_odt_l,
seq_ras_n_h,
seq_ras_n_l,
seq_we_n_h,
seq_we_n_l,
seq_ac_sel,
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_cs_n,
mem_odt,
mem_ras_n,
mem_we_n );
parameter DWIDTH_RATIO = 4;
parameter MEM_ADDR_CMD_BUS_COUNT = 1;
parameter MEM_IF_BANKADDR_WIDTH = 3;
parameter MEM_IF_CS_WIDTH = 2;
parameter MEM_IF_MEMTYPE = "DDR";
parameter MEM_IF_ROWADDR_WIDTH = 13;
input wire cs_n_clk_2x;
input wire ac_clk_2x;
input wire phy_clk_1x;
input wire reset_ac_clk_2x_n;
input wire reset_cs_n_clk_2x_n;
input wire [MEM_IF_ROWADDR_WIDTH -1:0] ctl_mem_addr_h;
input wire [MEM_IF_ROWADDR_WIDTH -1:0] ctl_mem_addr_l;
input wire ctl_add_1t_ac_lat;
input wire ctl_add_1t_odt_lat;
input wire ctl_negedge_en;
input wire ctl_add_intermediate_regs;
input wire [MEM_IF_BANKADDR_WIDTH - 1:0] ctl_mem_ba_h;
input wire [MEM_IF_BANKADDR_WIDTH - 1:0] ctl_mem_ba_l;
input wire ctl_mem_cas_n_h;
input wire ctl_mem_cas_n_l;
input wire [MEM_IF_CS_WIDTH - 1:0] ctl_mem_cke_h;
input wire [MEM_IF_CS_WIDTH - 1:0] ctl_mem_cke_l;
input wire [MEM_IF_CS_WIDTH - 1:0] ctl_mem_cs_n_h;
input wire [MEM_IF_CS_WIDTH - 1:0] ctl_mem_cs_n_l;
input wire [MEM_IF_CS_WIDTH - 1:0] ctl_mem_odt_h;
input wire [MEM_IF_CS_WIDTH - 1:0] ctl_mem_odt_l;
input wire ctl_mem_ras_n_h;
input wire ctl_mem_ras_n_l;
input wire ctl_mem_we_n_h;
input wire ctl_mem_we_n_l;
input wire [MEM_IF_ROWADDR_WIDTH -1:0] seq_addr_h;
input wire [MEM_IF_ROWADDR_WIDTH -1:0] seq_addr_l;
input wire [MEM_IF_BANKADDR_WIDTH - 1:0] seq_ba_h;
input wire [MEM_IF_BANKADDR_WIDTH - 1:0] seq_ba_l;
input wire seq_cas_n_h;
input wire seq_cas_n_l;
input wire [MEM_IF_CS_WIDTH - 1:0] seq_cke_h;
input wire [MEM_IF_CS_WIDTH - 1:0] seq_cke_l;
input wire [MEM_IF_CS_WIDTH - 1:0] seq_cs_n_h;
input wire [MEM_IF_CS_WIDTH - 1:0] seq_cs_n_l;
input wire [MEM_IF_CS_WIDTH - 1:0] seq_odt_h;
input wire [MEM_IF_CS_WIDTH - 1:0] seq_odt_l;
input wire seq_ras_n_h;
input wire seq_ras_n_l;
input wire seq_we_n_h;
input wire seq_we_n_l;
input wire seq_ac_sel;
output wire [MEM_IF_ROWADDR_WIDTH - 1 : 0] mem_addr;
output wire [MEM_IF_BANKADDR_WIDTH - 1 : 0] mem_ba;
output wire mem_cas_n;
output wire [MEM_IF_CS_WIDTH - 1 : 0] mem_cke;
output wire [MEM_IF_CS_WIDTH - 1 : 0] mem_cs_n;
output wire [MEM_IF_CS_WIDTH - 1 : 0] mem_odt;
output wire mem_ras_n;
output wire mem_we_n;
// Periodical select registers - per group of pins
reg [`ADC_NUM_PIN_GROUPS-1:0] count_addr = `ADC_NUM_PIN_GROUPS'b0;
reg [`ADC_NUM_PIN_GROUPS-1:0] count_addr_2x = `ADC_NUM_PIN_GROUPS'b0;
reg [`ADC_NUM_PIN_GROUPS-1:0] count_addr_2x_r = `ADC_NUM_PIN_GROUPS'b0;
reg [`ADC_NUM_PIN_GROUPS-1:0] period_sel_addr = `ADC_NUM_PIN_GROUPS'b0;
generate
genvar ia;
for (ia=0; ia<`ADC_NUM_PIN_GROUPS - 1; ia=ia+1)
begin : SELECTS
always @(posedge phy_clk_1x)
begin
count_addr[ia] <= ~count_addr[ia];
end
always @(posedge ac_clk_2x)
begin
count_addr_2x[ia] <= count_addr[ia];
count_addr_2x_r[ia] <= count_addr_2x[ia];
period_sel_addr[ia] <= ~(count_addr_2x_r[ia] ^ count_addr_2x[ia]);
end
end
endgenerate
//now generate cs_n period sel, off the dedicated cs_n clock :
always @(posedge phy_clk_1x)
begin
count_addr[`ADC_CS_N_PERIOD_SEL] <= ~count_addr[`ADC_CS_N_PERIOD_SEL];
end
always @(posedge cs_n_clk_2x)
begin
count_addr_2x [`ADC_CS_N_PERIOD_SEL] <= count_addr [`ADC_CS_N_PERIOD_SEL];
count_addr_2x_r[`ADC_CS_N_PERIOD_SEL] <= count_addr_2x[`ADC_CS_N_PERIOD_SEL];
period_sel_addr[`ADC_CS_N_PERIOD_SEL] <= ~(count_addr_2x_r[`ADC_CS_N_PERIOD_SEL] ^ count_addr_2x[`ADC_CS_N_PERIOD_SEL]);
end
// Create the ADDR I/O structure :
generate
genvar ib;
for (ib=0; ib<MEM_IF_ROWADDR_WIDTH; ib=ib+1)
begin : addr
//
ddr_ctrl_ip_phy_alt_mem_phy_ac # (
.POWER_UP_HIGH (1),
.DWIDTH_RATIO (DWIDTH_RATIO)
) addr_struct (
.clk_2x (ac_clk_2x),
.reset_2x_n (1'b1),
.phy_clk_1x (phy_clk_1x),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_negedge_en (ctl_negedge_en),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.period_sel (period_sel_addr[`ADC_ADDR_PERIOD_SEL]),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_addr_h[ib]),
.ctl_ac_l (ctl_mem_addr_l[ib]),
.seq_ac_h (seq_addr_h[ib]),
.seq_ac_l (seq_addr_l[ib]),
.mem_ac (mem_addr[ib])
);
end
endgenerate
// Create the BANK_ADDR I/O structure :
generate
genvar ic;
for (ic=0; ic<MEM_IF_BANKADDR_WIDTH; ic=ic+1)
begin : ba
//
ddr_ctrl_ip_phy_alt_mem_phy_ac #(
.POWER_UP_HIGH (0),
.DWIDTH_RATIO (DWIDTH_RATIO)
) ba_struct (
.clk_2x (ac_clk_2x),
.reset_2x_n (1'b1),
.phy_clk_1x (phy_clk_1x),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_negedge_en (ctl_negedge_en),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.period_sel (period_sel_addr[`ADC_BA_PERIOD_SEL]),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_ba_h[ic]),
.ctl_ac_l (ctl_mem_ba_l[ic]),
.seq_ac_h (seq_ba_h[ic]),
.seq_ac_l (seq_ba_l[ic]),
.mem_ac (mem_ba[ic])
);
end
endgenerate
// Create the CAS_N I/O structure :
//
ddr_ctrl_ip_phy_alt_mem_phy_ac #(
.POWER_UP_HIGH (1),
.DWIDTH_RATIO (DWIDTH_RATIO)
) cas_n_struct (
.clk_2x (ac_clk_2x),
.reset_2x_n (1'b1),
.phy_clk_1x (phy_clk_1x),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_negedge_en (ctl_negedge_en),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.period_sel (period_sel_addr[`ADC_CAS_N_PERIOD_SEL]),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_cas_n_h),
.ctl_ac_l (ctl_mem_cas_n_l),
.seq_ac_h (seq_cas_n_h),
.seq_ac_l (seq_cas_n_l),
.mem_ac (mem_cas_n)
);
// Create the CKE I/O structure :
generate
genvar id;
for (id=0; id<MEM_IF_CS_WIDTH; id=id+1)
begin : cke
//
ddr_ctrl_ip_phy_alt_mem_phy_ac # (
.POWER_UP_HIGH (0),
.DWIDTH_RATIO (DWIDTH_RATIO)
) cke_struct (
.clk_2x (ac_clk_2x),
.reset_2x_n (reset_ac_clk_2x_n),
.phy_clk_1x (phy_clk_1x),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_negedge_en (ctl_negedge_en),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.period_sel (period_sel_addr[`ADC_CKE_PERIOD_SEL]),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_cke_h[id]),
.ctl_ac_l (ctl_mem_cke_l[id]),
.seq_ac_h (seq_cke_h[id]),
.seq_ac_l (seq_cke_l[id]),
.mem_ac (mem_cke[id])
);
end
endgenerate
// Create the CS_N I/O structure. Note that the 2x clock is different.
generate
genvar ie;
for (ie=0; ie<MEM_IF_CS_WIDTH; ie=ie+1)
begin : cs_n
//
ddr_ctrl_ip_phy_alt_mem_phy_ac # (
.POWER_UP_HIGH (1),
.DWIDTH_RATIO (DWIDTH_RATIO)
) cs_n_struct (
.clk_2x (cs_n_clk_2x),
.reset_2x_n (reset_ac_clk_2x_n),
.phy_clk_1x (phy_clk_1x),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_negedge_en (ctl_negedge_en),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.period_sel (period_sel_addr[`ADC_CS_N_PERIOD_SEL]),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_cs_n_h[ie]),
.ctl_ac_l (ctl_mem_cs_n_l[ie]),
.seq_ac_h (seq_cs_n_h[ie]),
.seq_ac_l (seq_cs_n_l[ie]),
.mem_ac (mem_cs_n[ie])
);
end
endgenerate
// Create the ODT I/O structure :
generate
genvar ig;
if (MEM_IF_MEMTYPE != "DDR")
begin : gen_odt
for (ig=0; ig<MEM_IF_CS_WIDTH; ig=ig+1)
begin : odt
//
ddr_ctrl_ip_phy_alt_mem_phy_ac #(
.POWER_UP_HIGH (0),
.DWIDTH_RATIO (DWIDTH_RATIO)
) odt_struct (
.clk_2x (ac_clk_2x),
.reset_2x_n (1'b1),
.phy_clk_1x (phy_clk_1x),
.ctl_add_1t_ac_lat (ctl_add_1t_odt_lat),
.ctl_negedge_en (ctl_negedge_en),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.period_sel (period_sel_addr[`ADC_ODT_PERIOD_SEL]),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_odt_h[ig]),
.ctl_ac_l (ctl_mem_odt_l[ig]),
.seq_ac_h (seq_odt_h[ig]),
.seq_ac_l (seq_odt_l[ig]),
.mem_ac (mem_odt[ig])
);
end
end
endgenerate
// Create the RAS_N I/O structure :
//
ddr_ctrl_ip_phy_alt_mem_phy_ac # (
.POWER_UP_HIGH (1),
.DWIDTH_RATIO (DWIDTH_RATIO)
) ras_n_struct (
.clk_2x (ac_clk_2x),
.reset_2x_n (1'b1),
.phy_clk_1x (phy_clk_1x),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_negedge_en (ctl_negedge_en),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.period_sel (period_sel_addr[`ADC_RAS_N_PERIOD_SEL]),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_ras_n_h),
.ctl_ac_l (ctl_mem_ras_n_l),
.seq_ac_h (seq_ras_n_h),
.seq_ac_l (seq_ras_n_l),
.mem_ac (mem_ras_n)
);
// Create the WE_N I/O structure :
//
ddr_ctrl_ip_phy_alt_mem_phy_ac # (
.POWER_UP_HIGH (1),
.DWIDTH_RATIO (DWIDTH_RATIO)
) we_n_struct (
.clk_2x (ac_clk_2x),
.reset_2x_n (1'b1),
.phy_clk_1x (phy_clk_1x),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_negedge_en (ctl_negedge_en),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.period_sel (period_sel_addr[`ADC_WE_N_PERIOD_SEL]),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_we_n_h),
.ctl_ac_l (ctl_mem_we_n_l),
.seq_ac_h (seq_we_n_h),
.seq_ac_l (seq_we_n_l),
.mem_ac (mem_we_n)
);
endmodule
`default_nettype wire
/* Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details. */
/*////////////////////////////////////////////////////////////////////////////-
Title : Datapath IO elements
File: $RCSfile : alt_mem_phy_dp_io.v,v $
Last Modified : $Date: 2013/03/07 $
Revision : $Revision: #1 $
Abstract : NewPhy Datapath IO atoms. This block shall connect to both
the read and write datapath blocks, abstracting the I/O
elements from the remainder of the circuit. This file
instances atoms specific to Cyclone III.
////////////////////////////////////////////////////////////////////////////-*/
`include "alt_mem_phy_defines.v"
//DQS pin assignments
(* altera_attribute = " -name DQS_FREQUENCY 150.0MHz -to dqs[0].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[0].dq[0].dq_ibuf -from dqs[0].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[0].dq[1].dq_ibuf -from dqs[0].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[0].dq[2].dq_ibuf -from dqs[0].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[0].dq[3].dq_ibuf -from dqs[0].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[0].dq[4].dq_ibuf -from dqs[0].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[0].dq[5].dq_ibuf -from dqs[0].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[0].dq[6].dq_ibuf -from dqs[0].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[0].dq[7].dq_ibuf -from dqs[0].dqs_obuf; -name DQ_GROUP 9 -to dm[0].dm_obuf -from dqs[0].dqs_obuf; -name DQS_FREQUENCY 150.0MHz -to dqs[1].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[1].dq[0].dq_ibuf -from dqs[1].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[1].dq[1].dq_ibuf -from dqs[1].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[1].dq[2].dq_ibuf -from dqs[1].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[1].dq[3].dq_ibuf -from dqs[1].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[1].dq[4].dq_ibuf -from dqs[1].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[1].dq[5].dq_ibuf -from dqs[1].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[1].dq[6].dq_ibuf -from dqs[1].dqs_obuf; -name DQ_GROUP 9 -to dqs_group[1].dq[7].dq_ibuf -from dqs[1].dqs_obuf; -name DQ_GROUP 9 -to dm[1].dm_obuf -from dqs[1].dqs_obuf" *)
//
module ddr_ctrl_ip_phy_alt_mem_phy_dp_io (
reset_resync_clk_2x_n,
resync_clk_2x,
mem_clk_2x,
write_clk_2x,
mem_dm,
mem_dq,
mem_dqs,
dio_rdata_h_2x,
dio_rdata_l_2x,
wdp_dm_h_2x,
wdp_dm_l_2x,
wdp_wdata_h_2x,
wdp_wdata_l_2x,
wdp_wdata_oe_2x,
wdp_wdqs_2x,
wdp_wdqs_oe_2x
);
parameter MEM_IF_CLK_PS = 4000;
parameter MEM_IF_BANKADDR_WIDTH = 3;
parameter MEM_IF_CS_WIDTH = 2;
parameter MEM_IF_DWIDTH = 64;
parameter MEM_IF_DM_PINS_EN = 1;
parameter MEM_IF_DM_WIDTH = 8;
parameter MEM_IF_DQ_PER_DQS = 8;
parameter MEM_IF_DQS_CAPTURE_EN = 0;
parameter MEM_IF_DQS_WIDTH = 8;
parameter MEM_IF_ROWADDR_WIDTH = 13;
parameter DLL_DELAY_BUFFER_MODE = "HIGH";
parameter DQS_OUT_MODE = "DELAY_CHAIN2";
parameter DQS_PHASE = 72;
input wire reset_resync_clk_2x_n;
input wire resync_clk_2x;
input wire mem_clk_2x;
input wire write_clk_2x;
output wire [MEM_IF_DM_WIDTH - 1 : 0] mem_dm;
inout wire [MEM_IF_DWIDTH - 1 : 0] mem_dq;
inout wire [MEM_IF_DWIDTH / MEM_IF_DQ_PER_DQS - 1 : 0] mem_dqs;
(* preserve *) output reg [MEM_IF_DWIDTH - 1 : 0] dio_rdata_h_2x;
(* preserve *) output reg [MEM_IF_DWIDTH - 1 : 0] dio_rdata_l_2x;
input wire [MEM_IF_DM_WIDTH -1 : 0] wdp_dm_h_2x;
input wire [MEM_IF_DM_WIDTH -1 : 0] wdp_dm_l_2x;
input wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata_h_2x;
input wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata_l_2x;
input wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata_oe_2x;
input wire [(MEM_IF_DQS_WIDTH) - 1 : 0] wdp_wdqs_2x;
input wire [(MEM_IF_DQS_WIDTH) - 1 : 0] wdp_wdqs_oe_2x;
(* altera_attribute=" -name FAST_OUTPUT_ENABLE_REGISTER ON" *) reg [MEM_IF_DWIDTH - 1 : 0] wdp_wdata_oe_2x_r;
wire [MEM_IF_DWIDTH - 1 : 0] rdata_n_captured;
wire [MEM_IF_DWIDTH - 1 : 0] rdata_p_captured;
(* preserve *) wire [(MEM_IF_DQS_WIDTH) - 1 : 0] wdp_wdqs_oe_2x_r;
(* preserve *) reg [MEM_IF_DWIDTH - 1 : 0] rdata_n_ams;
(* preserve *) reg [MEM_IF_DWIDTH - 1 : 0] rdata_p_ams;
// Use DQS clock to register DQ read data
wire [(MEM_IF_DQS_WIDTH) - 1 : 0] dqs_clk;
wire [(MEM_IF_DQS_WIDTH) - 1 : 0] dq_capture_clk;
wire reset_resync_clk_2x;
wire [MEM_IF_DWIDTH - 1 : 0] dq_ddio_dataout;
wire [MEM_IF_DWIDTH - 1 : 0] dq_datain;
wire [MEM_IF_DWIDTH - 1 : 0] dm_ddio_dataout;
wire [MEM_IF_DWIDTH / MEM_IF_DQ_PER_DQS - 1 : 0] dqs_ddio_dataout;
genvar i,j;
// Create non-inverted reset for pads :
assign reset_resync_clk_2x = ~reset_resync_clk_2x_n;
// Read datapath functionality :
// synchronise to the resync_clk_2x_domain
always @(posedge resync_clk_2x)
begin
// Resynchronise :
// The comparison to 'X' is performed to prevent X's being captured in non-DQS mode
// and propagating into the sequencer's control logic. This can only occur when a Verilog SIMGEN
// model of the sequencer is being used :
if (|rdata_p_captured === 1'bX)
rdata_p_ams <= {MEM_IF_DWIDTH{1'b0}};
else
rdata_p_ams <= rdata_p_captured; // 'captured' is from the IOEs
if (|rdata_n_captured === 1'bX)
rdata_n_ams <= {MEM_IF_DWIDTH{1'b0}};
else
rdata_n_ams <= rdata_n_captured; // 'captured' is from the IOEs
// Output registers :
dio_rdata_h_2x <= rdata_p_ams;
dio_rdata_l_2x <= rdata_n_ams;
end
// Either use the DQS clock to capture, or the resync clock:
generate
if (MEM_IF_DQS_CAPTURE_EN == 1)
assign dq_capture_clk = ~dqs_clk;
else
assign dq_capture_clk = {MEM_IF_DQS_WIDTH{resync_clk_2x}};
endgenerate
// DQ pins and their logic
generate
// First generate each DQS group :
for (i=0; i<MEM_IF_DQS_WIDTH ; i=i+1)
begin : dqs_group
// Then generate DQ pins for each group :
for (j=0; j<MEM_IF_DQ_PER_DQS ; j=j+1)
begin : dq
// DDIO out :
cycloneiii_ddio_out # (
.power_up("low"),
.async_mode("none"),
.sync_mode("none"),
.lpm_type("cycloneiii_ddio_out"),
.use_new_clocking_model("true")
) dq_ddio_out (
.datainlo(wdp_wdata_l_2x[j+(i*MEM_IF_DQ_PER_DQS)]),
.datainhi(wdp_wdata_h_2x[j+(i*MEM_IF_DQ_PER_DQS)]),
.clkhi(write_clk_2x),
.clklo(write_clk_2x),
.clk(),
.muxsel(write_clk_2x),
.ena(1'b1),
.areset(),
.sreset(),
.dataout(dq_ddio_dataout[j+(i*MEM_IF_DQ_PER_DQS)]),
.dfflo(),
.dffhi(),
.devpor(),
.devclrn()
);
// Need to register OE :
always @(posedge write_clk_2x)
begin
wdp_wdata_oe_2x_r[j+(i*MEM_IF_DQ_PER_DQS)] <= wdp_wdata_oe_2x[j+(i*MEM_IF_DQ_PER_DQS)];
end
//The buffer itself (output side) :
cycloneiii_io_obuf dq_obuf (
.i(dq_ddio_dataout[j+(i*MEM_IF_DQ_PER_DQS)]),
.oe(wdp_wdata_oe_2x_r[j+(i*MEM_IF_DQ_PER_DQS)]),
.seriesterminationcontrol(),
.devoe(),
.o(mem_dq[j+(i*MEM_IF_DQ_PER_DQS)]), //pad
.obar()
);
//The buffer itself (input side) :
cycloneiii_io_ibuf # (
.simulate_z_as("gnd")
) dq_ibuf (
.i(mem_dq[j+(i*MEM_IF_DQ_PER_DQS)]),//pad
.ibar(),
.o(dq_datain[j+(i*MEM_IF_DQ_PER_DQS)])
);
// Read data input DDIO path :
altddio_in #( .intended_device_family ("Cyclone III"),
.lpm_hint ("UNUSED"),
.lpm_type ("altddio_in"),
.power_up_high ("OFF"),
.width (1)
) dqi (
.aclr (reset_resync_clk_2x),
.aset (),
.sset (),
.sclr (),
.datain (dq_datain[j+(i*MEM_IF_DQ_PER_DQS)]),
.dataout_h (rdata_n_captured[j+(i*MEM_IF_DQ_PER_DQS)]),
.dataout_l (rdata_p_captured[j+(i*MEM_IF_DQ_PER_DQS)]),
.inclock (dq_capture_clk[i]),
.inclocken (1'b1)
);
end
end
endgenerate
//////////////////////////////////////////////////////////////////////////////-
// DM Pin and its logic
//////////////////////////////////////////////////////////////////////////////-
generate
if (MEM_IF_DM_PINS_EN)
begin
for (i=0; i<MEM_IF_DM_WIDTH; i=i+1)
begin : dm
cycloneiii_ddio_out # (
.power_up("low"),
.async_mode("none"),
.sync_mode("none"),
.lpm_type("cycloneiii_ddio_out"),
.use_new_clocking_model("true")
) dm_ddio_out (
.datainlo(wdp_dm_l_2x[i]),
.datainhi(wdp_dm_h_2x[i]),
.clkhi(write_clk_2x),
.clklo(write_clk_2x),
.clk(),
.muxsel(write_clk_2x),
.ena(1'b1),
.areset(),
.sreset(),
.dataout(dm_ddio_dataout[i]),
.dfflo(),
.dffhi(),
.devpor(),
.devclrn()
);
cycloneiii_io_obuf dm_obuf (
.i(dm_ddio_dataout[i]),
.oe(1'b1),
.seriesterminationcontrol(),
.devoe(),
.o(mem_dm[i]), //pad
.obar()
);
end
end
endgenerate
// Note that for CIII DQS-capture mode is unsupported, and so DQS is only used
// as an output :
generate
for (i=0; i<(MEM_IF_DQS_WIDTH); i=i+1)
begin : dqs
cycloneiii_ddio_out # (
.power_up("low"),
.async_mode("none"),
.sync_mode("none"),
.lpm_type("cycloneiii_ddio_out"),
.use_new_clocking_model("true")
) dqs_ddio_out (
.datainlo(1'b0),
.datainhi(wdp_wdqs_2x[i]),
.clkhi(mem_clk_2x),
.clklo(mem_clk_2x),
.clk(),
.muxsel(mem_clk_2x),
.ena(1'b1),
.areset(),
.sreset(),
.dataout(dqs_ddio_dataout[i]),
.dfflo(),
.dffhi(),
.devpor(),
.devclrn()
);
// NB. Invert the OE input, as Quartus requires us to invert
// the OE input on the OBUF :
cycloneiii_ddio_oe # (
.power_up("low"),
.async_mode("none"),
.sync_mode("none"),
.lpm_type("cycloneiii_ddio_oe")
) dqsoe_ddio_oe (
.oe(~wdp_wdqs_oe_2x[i]),
.clk(mem_clk_2x),
.ena(1'b1),
.areset(),
.sreset(),
.dataout(wdp_wdqs_oe_2x_r[i]),
.dfflo(),
.dffhi(),
.devpor(),
.devclrn()
);
// Output buffer itself :
// OE input is active HIGH
cycloneiii_io_obuf dqs_obuf (
.i(dqs_ddio_dataout[i]),
.oe(~wdp_wdqs_oe_2x_r[i]),
.seriesterminationcontrol(),
.devoe(),
.o(mem_dqs[i]),
.obar()
);
end
endgenerate
endmodule
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr_ctrl_ip_phy_alt_mem_phy_read_dp ( phy_clk_1x,
resync_clk_2x,
reset_phy_clk_1x_n,
reset_resync_clk_2x_n,
seq_rdp_dec_read_lat_1x,
seq_rdp_dmx_swap,
seq_rdp_inc_read_lat_1x,
dio_rdata_h_2x,
dio_rdata_l_2x,
ctl_mem_rdata
);
parameter ADDR_COUNT_WIDTH = 4;
parameter BIDIR_DPINS = 1; // 0 for QDR only.
parameter DWIDTH_RATIO = 4;
parameter MEM_IF_CLK_PS = 4000;
parameter FAMILY = "Stratix II";
parameter LOCAL_IF_DWIDTH = 256;
parameter MEM_IF_DQ_PER_DQS = 8;
parameter MEM_IF_DQS_WIDTH = 8;
parameter MEM_IF_DWIDTH = 64;
parameter MEM_IF_PHY_NAME = "STRATIXII_DQS";
parameter RDP_INITIAL_LAT = 6;
parameter RDP_RESYNC_LAT_CTL_EN = 0;
parameter RESYNC_PIPELINE_DEPTH = 1;
localparam NUM_DQS_PINS = MEM_IF_DQS_WIDTH;
input wire phy_clk_1x;
input wire resync_clk_2x;
input wire reset_phy_clk_1x_n;
input wire reset_resync_clk_2x_n;
input wire seq_rdp_dec_read_lat_1x;
input wire seq_rdp_dmx_swap;
input wire seq_rdp_inc_read_lat_1x;
input wire [MEM_IF_DWIDTH-1 : 0] dio_rdata_h_2x;
input wire [MEM_IF_DWIDTH-1 : 0] dio_rdata_l_2x;
output wire [LOCAL_IF_DWIDTH-1 : 0] ctl_mem_rdata;
// concatonated read data :
wire [(2*MEM_IF_DWIDTH)-1 : 0] dio_rdata_2x;
reg [ADDR_COUNT_WIDTH - DWIDTH_RATIO/2 : 0] rd_ram_rd_addr;
reg [ADDR_COUNT_WIDTH - 1 : 0] rd_ram_wr_addr;
wire [(2*MEM_IF_DWIDTH)-1 : 0] rd_data_piped_2x;
reg inc_read_lat_sync_r;
reg dec_read_lat_sync_r;
// Optional AMS registers :
reg inc_read_lat_ams;
reg inc_read_lat_sync;
reg dec_read_lat_ams;
reg dec_read_lat_sync;
reg state;
reg dmx_swap_ams;
reg dmx_swap_sync;
reg dmx_swap_sync_r;
wire wr_addr_toggle_detect;
wire wr_addr_stall;
wire wr_addr_double_inc;
wire rd_addr_stall;
wire rd_addr_double_inc;
// Read data from ram, prior to mapping/re-ordering :
wire [LOCAL_IF_DWIDTH-1 : 0] ram_rdata_1x;
////////////////////////////////////////////////////////////////////////////////
// Write Address block
////////////////////////////////////////////////////////////////////////////////
// 'toggle detect' logic :
assign wr_addr_toggle_detect = !dmx_swap_sync_r && dmx_swap_sync;
// 'stall' logic :
assign wr_addr_stall = !(~state && wr_addr_toggle_detect);
// 'double_inc' logic :
assign wr_addr_double_inc = state && wr_addr_toggle_detect;
// Write address generation
// When no demux toggle - increment every clock cycle
// When demux toggle is detected,invert addr_stall
// if addr_stall is 1 then do nothing to address, else double increment this cycle.
always@ (posedge resync_clk_2x or negedge reset_resync_clk_2x_n)
begin
if (reset_resync_clk_2x_n == 0)
begin
rd_ram_wr_addr <= RDP_INITIAL_LAT[3:0];
state <= 1'b0;
dmx_swap_ams <= 1'b0;
dmx_swap_sync <= 1'b0;
dmx_swap_sync_r <= 1'b0;
end
else
begin
// Synchronise dmx_swap :
dmx_swap_ams <= seq_rdp_dmx_swap;
dmx_swap_sync <= dmx_swap_ams;
dmx_swap_sync_r <= dmx_swap_sync;
// RAM write address :
if (wr_addr_stall == 1'b1)
begin
rd_ram_wr_addr <= rd_ram_wr_addr + 1'b1 + wr_addr_double_inc;
end
// Maintain single bit state :
if (wr_addr_toggle_detect == 1'b1)
begin
state <= ~state;
end
end
end
////////////////////////////////////////////////////////////////////////////////
// Pipeline registers
////////////////////////////////////////////////////////////////////////////////
// Concatenate the input read data taking note of ram input datawidths
// This is concatenating rdata_p and rdata_n from a DQS group together so that the rest
// of the pipeline can use a single vector:
generate
genvar dqs_group_num;
for (dqs_group_num = 0; dqs_group_num < NUM_DQS_PINS ; dqs_group_num = dqs_group_num + 1)
begin : ddio_remap
assign dio_rdata_2x[2*MEM_IF_DQ_PER_DQS*dqs_group_num + 2*MEM_IF_DQ_PER_DQS-1: 2*MEM_IF_DQ_PER_DQS*dqs_group_num]
= { dio_rdata_l_2x[MEM_IF_DQ_PER_DQS*dqs_group_num + MEM_IF_DQ_PER_DQS-1: MEM_IF_DQ_PER_DQS*dqs_group_num],
dio_rdata_h_2x[MEM_IF_DQ_PER_DQS*dqs_group_num + MEM_IF_DQ_PER_DQS-1: MEM_IF_DQ_PER_DQS*dqs_group_num]
};
end
endgenerate
// Generate appropriate pipeline depth
generate
genvar i;
if (RESYNC_PIPELINE_DEPTH > 0)
begin : resync_pipeline_gen
// Declare pipeline registers
reg [(2*MEM_IF_DWIDTH)-1 : 0 ] pipeline_delay [0 : RESYNC_PIPELINE_DEPTH - 1] ;
for (i=0; i< RESYNC_PIPELINE_DEPTH; i = i + 1)
begin : PIPELINE
always @(posedge resync_clk_2x)
begin
if (i==0)
pipeline_delay[i] <= dio_rdata_2x;
else
pipeline_delay[i] <= pipeline_delay[i-1];
end //always
end //for
assign rd_data_piped_2x = pipeline_delay[RESYNC_PIPELINE_DEPTH-1];
end
// If pipeline registers are not configured, pass-thru :
else
begin : no_resync_pipe_gen
assign rd_data_piped_2x = dio_rdata_2x;
end
endgenerate
////////////////////////////////////////////////////////////////////////////////
// Instantiate the read_dp dpram
////////////////////////////////////////////////////////////////////////////////
generate
if (DWIDTH_RATIO == 4)
begin : half_rate_ram_gen
altsyncram #(
.address_reg_b ("CLOCK1"),
.clock_enable_input_a ("BYPASS"),
.clock_enable_input_b ("BYPASS"),
.clock_enable_output_b ("BYPASS"),
.intended_device_family (FAMILY),
.lpm_type ("altsyncram"),
.numwords_a ((2**ADDR_COUNT_WIDTH )),
.numwords_b ((2**ADDR_COUNT_WIDTH )/2),
.operation_mode ("DUAL_PORT"),
.outdata_aclr_b ("NONE"),
.outdata_reg_b ("CLOCK1"),
.power_up_uninitialized ("FALSE"),
.widthad_a (ADDR_COUNT_WIDTH),
.widthad_b (ADDR_COUNT_WIDTH - 1),
.width_a (MEM_IF_DWIDTH*2),
.width_b (MEM_IF_DWIDTH*4),
.width_byteena_a (1)
) altsyncram_component (
.wren_a (1'b1),
.clock0 (resync_clk_2x),
.clock1 (phy_clk_1x),
.address_a (rd_ram_wr_addr),
.address_b (rd_ram_rd_addr),
.data_a (rd_data_piped_2x),
.q_b (ram_rdata_1x),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (),
.clocken3 (),
.data_b ({(MEM_IF_DWIDTH*4){1'b1}}),
.q_a (),
.rden_b (1'b1),
.rden_a (),
.wren_b (1'b0),
.eccstatus ()
);
// Read data mapping :
genvar dqs_group_num_b;
for (dqs_group_num_b = 0; dqs_group_num_b < NUM_DQS_PINS ; dqs_group_num_b = dqs_group_num_b + 1)
begin : remap_logic
assign ctl_mem_rdata [MEM_IF_DWIDTH * 0 + dqs_group_num_b * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS -1 : MEM_IF_DWIDTH * 0 + dqs_group_num_b * MEM_IF_DQ_PER_DQS ] = ram_rdata_1x [ dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS - 1 : dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS ];
assign ctl_mem_rdata [MEM_IF_DWIDTH * 1 + dqs_group_num_b * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS -1 : MEM_IF_DWIDTH * 1 + dqs_group_num_b * MEM_IF_DQ_PER_DQS ] = ram_rdata_1x [ dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS + 2 * MEM_IF_DQ_PER_DQS - 1 : dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS ];
assign ctl_mem_rdata [MEM_IF_DWIDTH * 2 + dqs_group_num_b * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS -1 : MEM_IF_DWIDTH * 2 + dqs_group_num_b * MEM_IF_DQ_PER_DQS ] = ram_rdata_1x [ MEM_IF_DWIDTH * 2 + dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS - 1 : MEM_IF_DWIDTH * 2 + dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS ];
assign ctl_mem_rdata [MEM_IF_DWIDTH * 3 + dqs_group_num_b * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS -1 : MEM_IF_DWIDTH * 3 + dqs_group_num_b * MEM_IF_DQ_PER_DQS ] = ram_rdata_1x [ MEM_IF_DWIDTH * 2 + dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS + 2 * MEM_IF_DQ_PER_DQS - 1 : MEM_IF_DWIDTH * 2 + dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS ];
end
end // block: half_rate_dp
endgenerate
// full-rate
generate
if (DWIDTH_RATIO == 2)
begin : full_rate_ram_gen
altsyncram #(
.address_reg_b ("CLOCK1"),
.clock_enable_input_a ("BYPASS"),
.clock_enable_input_b ("BYPASS"),
.clock_enable_output_b ("BYPASS"),
.intended_device_family (FAMILY),
.lpm_type ("altsyncram"),
.numwords_a ((2**ADDR_COUNT_WIDTH )),
.numwords_b ((2**ADDR_COUNT_WIDTH )),
.operation_mode ("DUAL_PORT"),
.outdata_aclr_b ("NONE"),
.outdata_reg_b ("CLOCK1"),
.power_up_uninitialized ("FALSE"),
.widthad_a (ADDR_COUNT_WIDTH),
.widthad_b (ADDR_COUNT_WIDTH),
.width_a (MEM_IF_DWIDTH*2),
.width_b (MEM_IF_DWIDTH*2),
.width_byteena_a (1)
) altsyncram_component(
.wren_a (1'b1),
.clock0 (resync_clk_2x),
.clock1 (phy_clk_1x),
.address_a (rd_ram_wr_addr),
.address_b (rd_ram_rd_addr),
.data_a (rd_data_piped_2x),
.q_b (ram_rdata_1x),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (),
.clocken3 (),
.data_b ({(MEM_IF_DWIDTH*2){1'b1}}),
.q_a (),
.rden_b (1'b1),
.rden_a (),
.wren_b (1'b0),
.eccstatus ()
);
// Read data mapping :
genvar dqs_group_num_b;
for (dqs_group_num_b = 0; dqs_group_num_b < NUM_DQS_PINS ; dqs_group_num_b = dqs_group_num_b + 1)
begin : remap_logic
assign ctl_mem_rdata [MEM_IF_DWIDTH * 0 + dqs_group_num_b * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS -1 : MEM_IF_DWIDTH * 0 + dqs_group_num_b * MEM_IF_DQ_PER_DQS ] = ram_rdata_1x [ dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS - 1 : dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS ];
assign ctl_mem_rdata [MEM_IF_DWIDTH * 1 + dqs_group_num_b * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS -1 : MEM_IF_DWIDTH * 1 + dqs_group_num_b * MEM_IF_DQ_PER_DQS ] = ram_rdata_1x [ dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS + 2 * MEM_IF_DQ_PER_DQS - 1 : dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS ];
end
end // block: half_rate_dp
endgenerate
////////////////////////////////////////////////////////////////////////////////
// Read Address block
////////////////////////////////////////////////////////////////////////////////
// Optional Anti-metastability flops :
generate
if (RDP_RESYNC_LAT_CTL_EN == 1)
always@ (posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin : rd_addr_ams
if (reset_phy_clk_1x_n == 1'b0)
begin
inc_read_lat_ams <= 1'b0;
inc_read_lat_sync <= 1'b0;
inc_read_lat_sync_r <= 1'b0;
// Synchronise rd_lat_inc_1x :
dec_read_lat_ams <= 1'b0;
dec_read_lat_sync <= 1'b0;
dec_read_lat_sync_r <= 1'b0;
end
else
begin
// Synchronise rd_lat_inc_1x :
inc_read_lat_ams <= seq_rdp_inc_read_lat_1x;
inc_read_lat_sync <= inc_read_lat_ams;
inc_read_lat_sync_r <= inc_read_lat_sync;
// Synchronise rd_lat_inc_1x :
dec_read_lat_ams <= seq_rdp_dec_read_lat_1x;
dec_read_lat_sync <= dec_read_lat_ams;
dec_read_lat_sync_r <= dec_read_lat_sync;
end
end // always
// No anti-metastability protection required :
else
always@ (posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
inc_read_lat_sync_r <= 1'b0;
dec_read_lat_sync_r <= 1'b0;
end
else
begin
// No need to re-synchronise, just register for edge detect :
inc_read_lat_sync_r <= seq_rdp_inc_read_lat_1x;
dec_read_lat_sync_r <= seq_rdp_dec_read_lat_1x;
end
end
endgenerate
generate
if (RDP_RESYNC_LAT_CTL_EN == 1)
begin : lat_ctl_en_gen
// 'toggle detect' logic :
//assign rd_addr_double_inc = !inc_read_lat_sync_r && inc_read_lat_sync;
assign rd_addr_double_inc = ( !dec_read_lat_sync_r && dec_read_lat_sync );
// 'stall' logic :
// assign rd_addr_stall = !( !dec_read_lat_sync_r && dec_read_lat_sync );
assign rd_addr_stall = !inc_read_lat_sync_r && inc_read_lat_sync;
end
else
begin : no_lat_ctl_en_gen
// 'toggle detect' logic :
//assign rd_addr_double_inc = !inc_read_lat_sync_r && seq_rdp_inc_read_lat_1x;
assign rd_addr_double_inc = ( !dec_read_lat_sync_r && seq_rdp_dec_read_lat_1x );
// 'stall' logic :
//assign rd_addr_stall = !( !dec_read_lat_sync_r && seq_rdp_dec_read_lat_1x );
assign rd_addr_stall = !inc_read_lat_sync_r && seq_rdp_inc_read_lat_1x;
end
endgenerate
always@ (posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 0)
begin
rd_ram_rd_addr <= { ADDR_COUNT_WIDTH - DWIDTH_RATIO/2 {1'b0} };
end
else
begin
// RAM read address :
if (rd_addr_stall == 1'b0)
begin
rd_ram_rd_addr <= rd_ram_rd_addr + 1'b1 + rd_addr_double_inc;
end
end
end
endmodule
//
// Note, this write datapath logic matches both the spec, and what was done in
// the beta project.
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr_ctrl_ip_phy_alt_mem_phy_write_dp_fr(
// clocks
phy_clk_1x, // full-rate clock
mem_clk_2x, // full-rate clock
write_clk_2x, // full-rate clock
// active-low resets, sync'd to clock domain
reset_phy_clk_1x_n,
reset_mem_clk_2x_n,
reset_write_clk_2x_n,
// control i/f inputs
ctl_mem_be,
ctl_mem_dqs_burst,
ctl_mem_wdata,
ctl_mem_wdata_valid,
// seq i/f inputs :
seq_be,
seq_dqs_burst,
seq_wdata,
seq_wdata_valid,
seq_ctl_sel,
// outputs to IOEs
wdp_wdata_h_2x,
wdp_wdata_l_2x,
wdp_wdata_oe_2x,
wdp_wdqs_2x,
wdp_wdqs_oe_2x,
wdp_dm_h_2x,
wdp_dm_l_2x
);
// parameter declarations
parameter BIDIR_DPINS = 1;
parameter LOCAL_IF_DRATE = "FULL";
parameter LOCAL_IF_DWIDTH = 256;
parameter MEM_IF_DM_WIDTH = 8;
parameter MEM_IF_DQ_PER_DQS = 8;
parameter MEM_IF_DQS_WIDTH = 8;
parameter GENERATE_WRITE_DQS = 1;
parameter MEM_IF_DWIDTH = 64;
parameter DWIDTH_RATIO = 2;
parameter MEM_IF_DM_PINS_EN = 1;
// "internal" parameter, not to get propagated from higher levels...
parameter NUM_DUPLICATE_REGS = 4; // 1 per nibble to save registers
// clocks
input wire phy_clk_1x; // half-rate system clock
input wire mem_clk_2x; // full-rate memory clock
input wire write_clk_2x; // full-rate write clock
// resets, async assert, de-assert is sync'd to each clock domain
input wire reset_phy_clk_1x_n;
input wire reset_mem_clk_2x_n;
input wire reset_write_clk_2x_n;
// control i/f inputs
input wire [MEM_IF_DM_WIDTH * DWIDTH_RATIO - 1 : 0] ctl_mem_be; // byte enable == ~data mask
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] ctl_mem_dqs_burst; // dqs burst indication
input wire [MEM_IF_DWIDTH*DWIDTH_RATIO - 1 : 0] ctl_mem_wdata; // write data
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] ctl_mem_wdata_valid; // write data valid indication
// seq i/f inputs
input wire [MEM_IF_DM_WIDTH * DWIDTH_RATIO - 1 : 0] seq_be;
input wire [MEM_IF_DWIDTH * DWIDTH_RATIO - 1 : 0] seq_wdata;
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_dqs_burst;
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_wdata_valid;
input wire seq_ctl_sel;
(*preserve*) output reg [MEM_IF_DWIDTH - 1 : 0] wdp_wdata_h_2x; // wdata_h to IOE
(*preserve*) output reg [MEM_IF_DWIDTH - 1 : 0] wdp_wdata_l_2x; // wdata_l to IOE
output wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata_oe_2x; // OE to DQ pin
output reg [(MEM_IF_DQS_WIDTH) - 1 : 0] wdp_wdqs_2x; // DQS to IOE
output reg [(MEM_IF_DQS_WIDTH) - 1 : 0] wdp_wdqs_oe_2x; // OE to DQS pin
(*preserve*) output reg [MEM_IF_DM_WIDTH -1 : 0] wdp_dm_h_2x; // dm_h to IOE
(*preserve*) output reg [MEM_IF_DM_WIDTH -1 : 0] wdp_dm_l_2x; // dm_l to IOE
// internal reg declarations
// registers (on a per- DQS group basis) which sync the dqs_burst_1x to phy_clk or mem_clk_2x.
// They are used to generate the DQS signal and its OE.
(*preserve*) reg [MEM_IF_DQS_WIDTH -1 : 0] dqs_burst_1x_r;
(*preserve*) reg [MEM_IF_DQS_WIDTH -1 : 0] dqs_burst_2x_r1;
(*preserve*) reg [MEM_IF_DQS_WIDTH -1 : 0] dqs_burst_2x_r2;
(*preserve*) reg [MEM_IF_DQS_WIDTH -1 : 0] dqs_burst_2x_r3;
// registers to generate the dq_oe, on a per nibble basis, to save registers.
(*preserve*) reg [MEM_IF_DWIDTH/NUM_DUPLICATE_REGS -1 : 0 ] wdata_valid_1x_r1; // wdata_valid_1x, retimed in phy_clk_1x
(*preserve*) reg [MEM_IF_DWIDTH/NUM_DUPLICATE_REGS -1 : 0 ] wdata_valid_1x_r2; // wdata_valid_1x_r1, retimed in phy_clk_1x
(* preserve, altera_attribute = "-name ADV_NETLIST_OPT_ALLOWED \"NEVER ALLOW\"" *) reg [MEM_IF_DWIDTH/NUM_DUPLICATE_REGS -1 : 0 ] dq_oe_2x; // 1 per nibble, to save registers
reg [MEM_IF_DWIDTH - 1 : 0] wdp_wdata_oe_2x_int; // intermediate output, gets assigned to o/p signal
reg [LOCAL_IF_DWIDTH -1 : 0] mem_wdata_r1; // mem_wdata, retimed in phy_clk_1x
reg [LOCAL_IF_DWIDTH -1 : 0] mem_wdata_r2; // mem_wdata_r1, retimed in phy_clk_1x
// registers used to generate the mux select signal for wdata.
(*preserve*) reg [MEM_IF_DWIDTH/NUM_DUPLICATE_REGS -1 : 0 ] wdata_valid_1x_r; // 1 per nibble, to save registers
(*preserve*) reg [MEM_IF_DWIDTH/NUM_DUPLICATE_REGS -1 : 0 ] wdata_valid_2x_r1; // 1 per nibble, to save registers
(*preserve*) reg [MEM_IF_DWIDTH/NUM_DUPLICATE_REGS -1 : 0 ] wdata_valid_2x_r2; // 1 per nibble, to save registers
(*preserve*) reg [MEM_IF_DWIDTH/NUM_DUPLICATE_REGS -1 : 0 ] wdata_sel; // 1 per nibble, to save registers
// registers used to generate the dm mux select and dm signals
reg [MEM_IF_DM_WIDTH*DWIDTH_RATIO - 1 : 0] mem_dm_r1;
reg [MEM_IF_DM_WIDTH*DWIDTH_RATIO - 1 : 0] mem_dm_r2;
(*preserve*) reg wdata_dm_1x_r; // preserved, to stop merge with wdata_valid_1x_r
(*preserve*) reg wdata_dm_2x_r1; // preserved, to stop merge with wdata_valid_2x_r1
(*preserve*) reg wdata_dm_2x_r2; // preserved, to stop merge with wdata_valid_2x_r2
(*preserve*) reg dm_sel; // preserved, to stop merge with wdata_sel
// MUX outputs....
reg [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] mem_dqs_burst ;
reg [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] mem_wdata_valid;
reg [MEM_IF_DM_WIDTH * DWIDTH_RATIO - 1 : 0] mem_be ;
reg [MEM_IF_DWIDTH * DWIDTH_RATIO - 1 : 0] mem_wdata ;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_wdqs_oe_2x_int;
always @*
begin
// Select controller or sequencer according to the select signal :
if (seq_ctl_sel)
begin
mem_be = seq_be;
mem_wdata = seq_wdata;
mem_wdata_valid = seq_wdata_valid;
mem_dqs_burst = seq_dqs_burst;
end
else
begin
mem_be = ctl_mem_be;
mem_wdata = ctl_mem_wdata;
mem_wdata_valid = ctl_mem_wdata_valid;
mem_dqs_burst = ctl_mem_dqs_burst;
end
end
genvar a, b, c, d; // variable for generate statement
integer j; // variable for loop counters
/////////////////////////////////////////////////////////////////////////
// generate the following write DQS logic on a per DQS group basis.
// wdp_wdqs_2x and wdp_wdqs_oe_2x get output to the IOEs.
////////////////////////////////////////////////////////////////////////
generate
if (GENERATE_WRITE_DQS == 1)
begin
for (a=0; a<MEM_IF_DQS_WIDTH; a = a+1)
begin : gen_loop_dqs
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
wdp_wdqs_2x[a] <= 0;
wdp_wdqs_oe_2x[a] <= 0;
end
else
begin
wdp_wdqs_2x[a] <= wdp_wdqs_oe_2x[a];
wdp_wdqs_oe_2x[a] <= mem_dqs_burst;
end
end
end
end
endgenerate
///////////////////////////////////////////////////////////////////
// Generate the write DQ logic.
// These are internal registers which will be used to assign to:
// wdp_wdata_h_2x, wdp_wdata_l_2x, wdp_wdata_oe_2x
// (these get output to the IOEs).
//////////////////////////////////////////////////////////////////
// number of times to replicate mem_wdata_valid bits
parameter DQ_OE_REPS = MEM_IF_DQ_PER_DQS/NUM_DUPLICATE_REGS;
generate
for (a=0; a<MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS; a=a+1)
begin : gen_dq_oe_2x
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
dq_oe_2x[DQ_OE_REPS*(a+1)-1:DQ_OE_REPS*a] <= {(DQ_OE_REPS){1'b0}};
end
else
begin
dq_oe_2x[DQ_OE_REPS*(a+1)-1:DQ_OE_REPS*a] <= {(DQ_OE_REPS){mem_wdata_valid[a]}};
end
end
end
endgenerate
////////////////////////////////////////////////////////////////////////////////
// fanout the dq_oe_2x, which has one register per NUM_DUPLICATE_REGS
// (to save registers), to each bit of wdp_wdata_oe_2x_int and then
// assign to the output wire wdp_wdata_oe_2x( ie one oe for each DQ "pin").
////////////////////////////////////////////////////////////////////////////////
always @(dq_oe_2x)
begin
for (j=0; j<MEM_IF_DWIDTH; j=j+1)
begin
wdp_wdata_oe_2x_int[j] = dq_oe_2x[(j/NUM_DUPLICATE_REGS)];
end
end
assign wdp_wdata_oe_2x = wdp_wdata_oe_2x_int;
//////////////////////////////////////////////////////////////////////
// Write DQ mapping from mem_wdata to wdata_l_2x, wdata_h_2x
//////////////////////////////////////////////////////////////////////
generate
for (c=0; c<MEM_IF_DWIDTH; c=c+1)
begin : gen_wdata
always @(posedge phy_clk_1x)
begin
wdp_wdata_l_2x[c] <= mem_wdata[c + MEM_IF_DWIDTH];
wdp_wdata_h_2x[c] <= mem_wdata[c ];
end
end
endgenerate
///////////////////////////////////////////////////////
// Conditional generation of DM logic, based on generic
///////////////////////////////////////////////////////
generate
if (MEM_IF_DM_PINS_EN == 1'b1)
begin : dm_logic_enabled
///////////////////////////////////////////////////////////////////
// Write DM logic: assignment to wdp_dm_h_2x, wdp_dm_l_2x
///////////////////////////////////////////////////////////////////
// for loop inside a generate statement, but outside a procedural block
// is treated as a nested generate
for (d=0; d<MEM_IF_DM_WIDTH; d=d+1)
begin : gen_dm
always @(posedge phy_clk_1x)
begin
if (mem_wdata_valid[d] == 1'b1) // nb might need to duplicate to meet timing
begin
wdp_dm_l_2x[d] <= mem_be[d+MEM_IF_DM_WIDTH];
wdp_dm_h_2x[d] <= mem_be[d];
end
// To support writes of less than the burst length, mask data when invalid :
else
begin
wdp_dm_l_2x[d] <= 1'b1;
wdp_dm_h_2x[d] <= 1'b1;
end
end
end // block: gen_dm
end // block: dm_logic_enabled
endgenerate
endmodule
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
`default_nettype none
//
module ddr_ctrl_ip_phy_alt_mem_phy_rdata_valid ( // inputs
phy_clk_1x,
reset_phy_clk_1x_n,
seq_rdata_valid_lat_dec,
seq_rdata_valid_lat_inc,
seq_doing_rd,
ctl_doing_rd,
ctl_cal_success,
// outputs
ctl_rdata_valid,
seq_rdata_valid
);
parameter FAMILY = "CYCLONEIII";
parameter MEM_IF_DQS_WIDTH = 8;
parameter RDATA_VALID_AWIDTH = 5;
parameter RDATA_VALID_INITIAL_LAT = 16;
parameter DWIDTH_RATIO = 2;
localparam MAX_RDATA_VALID_DELAY = 2 ** RDATA_VALID_AWIDTH;
localparam RDV_DELAY_SHR_LEN = MAX_RDATA_VALID_DELAY*(DWIDTH_RATIO/2);
// clocks
input wire phy_clk_1x;
// resets
input wire reset_phy_clk_1x_n;
// control signals from sequencer
input wire seq_rdata_valid_lat_dec;
input wire seq_rdata_valid_lat_inc;
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO / 2 -1 : 0] seq_doing_rd;
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO / 2 -1 : 0] ctl_doing_rd;
input wire ctl_cal_success;
// output to IOE
output reg [DWIDTH_RATIO / 2 -1 : 0] ctl_rdata_valid;
output reg [DWIDTH_RATIO / 2 -1 : 0] seq_rdata_valid;
// Internal Signals / Variables
reg [RDATA_VALID_AWIDTH - 1 : 0] rd_addr;
reg [RDATA_VALID_AWIDTH - 1 : 0] wr_addr;
reg [RDATA_VALID_AWIDTH - 1 : 0] next_wr_addr;
reg [DWIDTH_RATIO/2 - 1 : 0] wr_data;
wire [DWIDTH_RATIO / 2 -1 : 0] int_rdata_valid;
reg [DWIDTH_RATIO/2 - 1 : 0] rdv_pipe_ip;
reg rdv_pipe_ip_beat2_r;
reg [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] merged_doing_rd;
reg seq_rdata_valid_lat_dec_1t;
reg seq_rdata_valid_lat_inc_1t;
reg bit_order_1x;
// Generate the input to the RDV delay.
// Also determine the data for the OCT control & postamble paths (merged_doing_rd)
generate
if (DWIDTH_RATIO == 4)
begin : merging_doing_rd_halfrate
always @*
begin
merged_doing_rd = seq_doing_rd | (ctl_doing_rd & {(2 * MEM_IF_DQS_WIDTH) {ctl_cal_success}});
rdv_pipe_ip[0] = | merged_doing_rd[ MEM_IF_DQS_WIDTH - 1 : 0];
rdv_pipe_ip[1] = | merged_doing_rd[2 * MEM_IF_DQS_WIDTH - 1 : MEM_IF_DQS_WIDTH];
end
end
else // DWIDTH_RATIO == 2
begin : merging_doing_rd_fullrate
always @*
begin
merged_doing_rd = seq_doing_rd | (ctl_doing_rd & { MEM_IF_DQS_WIDTH {ctl_cal_success}});
rdv_pipe_ip[0] = | merged_doing_rd[MEM_IF_DQS_WIDTH - 1 : 0];
end
end // else: !if(DWIDTH_RATIO == 4)
endgenerate
// Register inc/dec rdata_valid signals and generate bit_order_1x
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
seq_rdata_valid_lat_dec_1t <= 1'b0;
seq_rdata_valid_lat_inc_1t <= 1'b0;
bit_order_1x <= 1'b1;
end
else
begin
rdv_pipe_ip_beat2_r <= rdv_pipe_ip[DWIDTH_RATIO/2 - 1];
seq_rdata_valid_lat_dec_1t <= seq_rdata_valid_lat_dec;
seq_rdata_valid_lat_inc_1t <= seq_rdata_valid_lat_inc;
if (DWIDTH_RATIO == 2)
bit_order_1x <= 1'b0;
else if (seq_rdata_valid_lat_dec == 1'b1 && seq_rdata_valid_lat_dec_1t == 1'b0)
begin
bit_order_1x <= ~bit_order_1x;
end
else if (seq_rdata_valid_lat_inc == 1'b1 && seq_rdata_valid_lat_inc_1t == 1'b0)
begin
bit_order_1x <= ~bit_order_1x;
end
end
end
// write data
generate // based on DWIDTH RATIO
if (DWIDTH_RATIO == 4) // Half Rate
begin : halfrate_wdata_gen
always @* // combinational logic sensitivity
begin
if (bit_order_1x == 1'b0)
begin
wr_data = {rdv_pipe_ip[1], rdv_pipe_ip[0]};
end
else
begin
wr_data = {rdv_pipe_ip[0], rdv_pipe_ip_beat2_r};
end
end
end
else // Full-rate
begin : fullrate_wdata_gen
always @* // combinational logic sensitivity
begin
wr_data = rdv_pipe_ip;
end
end
endgenerate
// write address
always @*
begin
next_wr_addr = wr_addr + 1'b1;
if (seq_rdata_valid_lat_dec == 1'b1 && seq_rdata_valid_lat_dec_1t == 1'b0)
begin
if ((bit_order_1x == 1'b0) || (DWIDTH_RATIO == 2))
begin
next_wr_addr = wr_addr;
end
end
else if (seq_rdata_valid_lat_inc == 1'b1 && seq_rdata_valid_lat_inc_1t == 1'b0)
begin
if ((bit_order_1x == 1'b1) || (DWIDTH_RATIO ==2))
begin
next_wr_addr = wr_addr + 2'h2;
end
end
end
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
wr_addr <= RDATA_VALID_INITIAL_LAT[RDATA_VALID_AWIDTH - 1 : 0];
end
else
begin
wr_addr <= next_wr_addr;
end
end
// read address generator : just a free running counter.
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
rd_addr <= {RDATA_VALID_AWIDTH{1'b0}};
end
else
begin
rd_addr <= rd_addr + 1'b1; //inc address, can wrap
end
end
// altsyncram instance
altsyncram #(.
address_aclr_b ("NONE"),
.address_reg_b ("CLOCK0"),
.clock_enable_input_a ("BYPASS"),
.clock_enable_input_b ("BYPASS"),
.clock_enable_output_b ("BYPASS"),
.intended_device_family (FAMILY),
.lpm_type ("altsyncram"),
.numwords_a (2**RDATA_VALID_AWIDTH),
.numwords_b (2**RDATA_VALID_AWIDTH),
.operation_mode ("DUAL_PORT"),
.outdata_aclr_b ("NONE"),
.outdata_reg_b ("CLOCK0"),
.power_up_uninitialized ("FALSE"),
.widthad_a (RDATA_VALID_AWIDTH),
.widthad_b (RDATA_VALID_AWIDTH),
.width_a (DWIDTH_RATIO/2),
.width_b (DWIDTH_RATIO/2),
.width_byteena_a (1)
) altsyncram_component (
.wren_a (1'b1),
.clock0 (phy_clk_1x),
.address_a (wr_addr),
.address_b (rd_addr),
.data_a (wr_data),
.q_b (int_rdata_valid),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({(DWIDTH_RATIO/2){1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0)
);
// Generate read data valid enable signals for controller and seqencer
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
ctl_rdata_valid <= {(DWIDTH_RATIO/2){1'b0}};
seq_rdata_valid <= {(DWIDTH_RATIO/2){1'b0}};
end
else
begin
// shift the shift register by DWIDTH_RATIO locations
// rdv_delay_index plus (DWIDTH_RATIO/2)-1 bits counting down
ctl_rdata_valid <= int_rdata_valid & {(DWIDTH_RATIO/2){ctl_cal_success}};
seq_rdata_valid <= int_rdata_valid;
end
end
endmodule
`default_nettype wire
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr_ctrl_ip_phy_alt_mem_phy_mux (
phy_clk_1x,
reset_phy_clk_1x_n,
// MUX Outputs to controller :
ctl_address,
ctl_read_req,
ctl_wdata,
ctl_write_req,
ctl_size,
ctl_be,
ctl_refresh_req,
ctl_burstbegin,
// Controller inputs to the MUX :
ctl_ready,
ctl_wdata_req,
ctl_rdata,
ctl_rdata_valid,
ctl_refresh_ack,
ctl_init_done,
// MUX Select line :
ctl_usr_mode_rdy,
// MUX inputs from local interface :
local_address,
local_read_req,
local_wdata,
local_write_req,
local_size,
local_be,
local_refresh_req,
local_burstbegin,
// MUX outputs to sequencer :
mux_seq_controller_ready,
mux_seq_wdata_req,
// MUX inputs from sequencer :
seq_mux_address,
seq_mux_read_req,
seq_mux_wdata,
seq_mux_write_req,
seq_mux_size,
seq_mux_be,
seq_mux_refresh_req,
seq_mux_burstbegin,
// Changes made to accomodate new ports for self refresh/power-down & Auto precharge in HP Controller (User to PHY)
local_autopch_req,
local_powerdn_req,
local_self_rfsh_req,
local_powerdn_ack,
local_self_rfsh_ack,
// Changes made to accomodate new ports for self refresh/power-down & Auto precharge in HP Controller (PHY to Controller)
ctl_autopch_req,
ctl_powerdn_req,
ctl_self_rfsh_req,
ctl_powerdn_ack,
ctl_self_rfsh_ack,
// Also MUX some signals from the controller to the local interface :
local_ready,
local_wdata_req,
local_init_done,
local_rdata,
local_rdata_valid,
local_refresh_ack
);
parameter LOCAL_IF_AWIDTH = 26;
parameter LOCAL_IF_DWIDTH = 256;
parameter LOCAL_BURST_LEN_BITS = 1;
parameter MEM_IF_DQ_PER_DQS = 8;
parameter MEM_IF_DWIDTH = 64;
input wire phy_clk_1x;
input wire reset_phy_clk_1x_n;
// MUX Select line :
input wire ctl_usr_mode_rdy;
// MUX inputs from local interface :
input wire [LOCAL_IF_AWIDTH - 1 : 0] local_address;
input wire local_read_req;
input wire [LOCAL_IF_DWIDTH - 1 : 0] local_wdata;
input wire local_write_req;
input wire [LOCAL_BURST_LEN_BITS - 1 : 0] local_size;
input wire [(LOCAL_IF_DWIDTH/8) - 1 : 0] local_be;
input wire local_refresh_req;
input wire local_burstbegin;
// MUX inputs from sequencer :
input wire [LOCAL_IF_AWIDTH - 1 : 0] seq_mux_address;
input wire seq_mux_read_req;
input wire [LOCAL_IF_DWIDTH - 1 : 0] seq_mux_wdata;
input wire seq_mux_write_req;
input wire [LOCAL_BURST_LEN_BITS - 1 : 0] seq_mux_size;
input wire [(LOCAL_IF_DWIDTH/8) - 1:0] seq_mux_be;
input wire seq_mux_refresh_req;
input wire seq_mux_burstbegin;
// MUX Outputs to controller :
output reg [LOCAL_IF_AWIDTH - 1 : 0] ctl_address;
output reg ctl_read_req;
output reg [LOCAL_IF_DWIDTH - 1 : 0] ctl_wdata;
output reg ctl_write_req;
output reg [LOCAL_BURST_LEN_BITS - 1 : 0] ctl_size;
output reg [(LOCAL_IF_DWIDTH/8) - 1:0] ctl_be;
output reg ctl_refresh_req;
output reg ctl_burstbegin;
// The "ready" input from the controller shall be passed to either the
// local interface if in user mode, or the sequencer :
input wire ctl_ready;
output reg local_ready;
output reg mux_seq_controller_ready;
// The controller's "wdata req" output is similarly passed to either
// the local interface if in user mode, or the sequencer :
input wire ctl_wdata_req;
output reg local_wdata_req;
output reg mux_seq_wdata_req;
input wire ctl_init_done;
output reg local_init_done;
input wire [LOCAL_IF_DWIDTH - 1 : 0] ctl_rdata;
output reg [LOCAL_IF_DWIDTH - 1 : 0] local_rdata;
input wire ctl_rdata_valid;
output reg local_rdata_valid;
input wire ctl_refresh_ack;
output reg local_refresh_ack;
//-> Changes made to accomodate new ports for self refresh/power-down & Auto precharge in HP Controller (User to PHY)
input wire local_autopch_req;
input wire local_powerdn_req;
input wire local_self_rfsh_req;
output reg local_powerdn_ack;
output reg local_self_rfsh_ack;
// --> Changes made to accomodate new ports for self refresh/power-down & Auto precharge in HP Controller (PHY to Controller)
output reg ctl_autopch_req;
output reg ctl_powerdn_req;
output reg ctl_self_rfsh_req;
input wire ctl_powerdn_ack;
input wire ctl_self_rfsh_ack;
wire local_burstbegin_held;
reg burstbegin_hold;
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
burstbegin_hold <= 1'b0;
else
begin
if (local_ready == 1'b0 && (local_write_req == 1'b1 || local_read_req == 1'b1) && local_burstbegin == 1'b1)
burstbegin_hold <= 1'b1;
else if (local_ready == 1'b1 && (local_write_req == 1'b1 || local_read_req == 1'b1))
burstbegin_hold <= 1'b0;
end
end
// Gate the local burstbegin signal with the held version :
assign local_burstbegin_held = burstbegin_hold || local_burstbegin;
always @*
begin
if (ctl_usr_mode_rdy == 1'b1)
begin
// Pass local interface signals to the controller if ready :
ctl_address = local_address;
ctl_read_req = local_read_req;
ctl_wdata = local_wdata;
ctl_write_req = local_write_req;
ctl_size = local_size;
ctl_be = local_be;
ctl_refresh_req = local_refresh_req;
ctl_burstbegin = local_burstbegin_held;
// If in user mode, pass on the controller's ready
// and wdata request signals to the local interface :
local_ready = ctl_ready;
local_wdata_req = ctl_wdata_req;
local_init_done = ctl_init_done;
local_rdata = ctl_rdata;
local_rdata_valid = ctl_rdata_valid;
local_refresh_ack = ctl_refresh_ack;
// Whilst indicate to the sequencer that the controller is busy :
mux_seq_controller_ready = 1'b0;
mux_seq_wdata_req = 1'b0;
// Autopch_req & Local_power_req changes
ctl_autopch_req = local_autopch_req;
ctl_powerdn_req = local_powerdn_req;
ctl_self_rfsh_req = local_self_rfsh_req;
local_powerdn_ack = ctl_powerdn_ack;
local_self_rfsh_ack = ctl_self_rfsh_ack;
end
else
begin
// Pass local interface signals to the sequencer if not in user mode :
// NB. The controller will have more address bits than the sequencer, so
// these are zero padded :
ctl_address = seq_mux_address;
ctl_read_req = seq_mux_read_req;
ctl_wdata = seq_mux_wdata;
ctl_write_req = seq_mux_write_req;
ctl_size = seq_mux_size; // NB. Should be tied-off when the mux is instanced
ctl_be = seq_mux_be; // NB. Should be tied-off when the mux is instanced
ctl_refresh_req = local_refresh_req; // NB. Should be tied-off when the mux is instanced
ctl_burstbegin = seq_mux_burstbegin; // NB. Should be tied-off when the mux is instanced
// Indicate to the local IF that the controller is busy :
local_ready = 1'b0;
local_wdata_req = 1'b0;
local_init_done = 1'b0;
local_rdata = {LOCAL_IF_DWIDTH{1'b0}};
local_rdata_valid = 1'b0;
local_refresh_ack = ctl_refresh_ack;
// If not in user mode, pass on the controller's ready
// and wdata request signals to the sequencer :
mux_seq_controller_ready = ctl_ready;
mux_seq_wdata_req = ctl_wdata_req;
// Autopch_req & Local_power_req changes
ctl_autopch_req = 1'b0;
ctl_powerdn_req = 1'b0;
ctl_self_rfsh_req = local_self_rfsh_req;
local_powerdn_ack = 1'b0;
local_self_rfsh_ack = ctl_self_rfsh_ack;
end
end
endmodule
//
`default_nettype none
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
/* -----------------------------------------------------------------------------
// module description
---------------------------------------------------------------------------- */
//
module ddr_ctrl_ip_phy_alt_mem_phy_mimic(
//Inputs
//Clocks
measure_clk, // full rate clock from PLL
mimic_data_in, // Input against which the VT variations
// are tracked (e.g. memory clock)
// Active low reset
reset_measure_clk_n,
//Indicates that the mimic calibration sequence can start
seq_mmc_start, // from sequencer
//Outputs
mmc_seq_done, // mimic calibration finished for the current PLL phase
mmc_seq_value // result value of the mimic calibration
);
input wire measure_clk;
input wire mimic_data_in;
input wire reset_measure_clk_n;
input wire seq_mmc_start;
output wire mmc_seq_done;
output wire mmc_seq_value;
function integer clogb2;
input [31:0] value;
for (clogb2=0; value>0; clogb2=clogb2+1)
value = value >> 1;
endfunction // clogb2
// Parameters
parameter NUM_MIMIC_SAMPLE_CYCLES = 6;
parameter SHIFT_REG_COUNTER_WIDTH = clogb2(NUM_MIMIC_SAMPLE_CYCLES);
reg [`MIMIC_FSM_WIDTH-1:0] mimic_state;
reg [2:0] seq_mmc_start_metastable;
wire start_edge_detected;
(* altera_attribute=" -name fast_input_register OFF"*) reg [1:0] mimic_data_in_metastable;
wire mimic_data_in_sample;
wire shift_reg_data_out_all_ones;
reg mimic_done_out;
reg mimic_value_captured;
reg [SHIFT_REG_COUNTER_WIDTH : 0] shift_reg_counter;
reg shift_reg_enable;
wire shift_reg_data_in;
reg shift_reg_s_clr;
wire shift_reg_a_clr;
reg [NUM_MIMIC_SAMPLE_CYCLES -1 : 0] shift_reg_data_out;
// shift register which contains the sampled data
always @(posedge measure_clk or posedge shift_reg_a_clr)
begin
if (shift_reg_a_clr == 1'b1)
begin
shift_reg_data_out <= {NUM_MIMIC_SAMPLE_CYCLES{1'b0}};
end
else
begin
if (shift_reg_s_clr == 1'b1)
begin
shift_reg_data_out <= {NUM_MIMIC_SAMPLE_CYCLES{1'b0}};
end
else if (shift_reg_enable == 1'b1)
begin
shift_reg_data_out <= {(shift_reg_data_out[NUM_MIMIC_SAMPLE_CYCLES -2 : 0]), shift_reg_data_in};
end
end
end
// Metastable-harden mimic_start :
always @(posedge measure_clk or negedge reset_measure_clk_n)
begin
if (reset_measure_clk_n == 1'b0)
begin
seq_mmc_start_metastable <= 0;
end
else
begin
seq_mmc_start_metastable[0] <= seq_mmc_start;
seq_mmc_start_metastable[1] <= seq_mmc_start_metastable[0];
seq_mmc_start_metastable[2] <= seq_mmc_start_metastable[1];
end
end
assign start_edge_detected = seq_mmc_start_metastable[1]
&& !seq_mmc_start_metastable[2];
// Metastable-harden mimic_data_in :
always @(posedge measure_clk or negedge reset_measure_clk_n)
begin
if (reset_measure_clk_n == 1'b0)
begin
mimic_data_in_metastable <= 0;
end
//some mimic paths configurations have another flop inside the wysiwyg ioe
else
begin
mimic_data_in_metastable[0] <= mimic_data_in;
mimic_data_in_metastable[1] <= mimic_data_in_metastable[0];
end
end
assign mimic_data_in_sample = mimic_data_in_metastable[1];
// Main FSM :
always @(posedge measure_clk or negedge reset_measure_clk_n )
begin
if (reset_measure_clk_n == 1'b0)
begin
mimic_state <= `MIMIC_IDLE;
mimic_done_out <= 1'b0;
mimic_value_captured <= 1'b0;
shift_reg_counter <= 0;
shift_reg_enable <= 1'b0;
shift_reg_s_clr <= 1'b0;
end
else
begin
case (mimic_state)
`MIMIC_IDLE : begin
shift_reg_counter <= 0;
mimic_done_out <= 1'b0;
shift_reg_s_clr <= 1'b1;
shift_reg_enable <= 1'b1;
if (start_edge_detected == 1'b1)
begin
mimic_state <= `MIMIC_SAMPLE;
shift_reg_counter <= shift_reg_counter + 1'b1;
shift_reg_s_clr <= 1'b0;
end
else
begin
mimic_state <= `MIMIC_IDLE;
end
end // case: MIMIC_IDLE
`MIMIC_SAMPLE : begin
shift_reg_counter <= shift_reg_counter + 1'b1;
if (shift_reg_counter == NUM_MIMIC_SAMPLE_CYCLES + 1)
begin
mimic_done_out <= 1'b1;
mimic_value_captured <= shift_reg_data_out_all_ones; //captured only here
shift_reg_enable <= 1'b0;
shift_reg_counter <= shift_reg_counter;
mimic_state <= `MIMIC_SEND;
end
end // case: MIMIC_SAMPLE
`MIMIC_SEND : begin
mimic_done_out <= 1'b1; //redundant statement, here just for readibility
mimic_state <= `MIMIC_SEND1;
/* mimic_value_captured will not change during MIMIC_SEND
it will change next time mimic_done_out is asserted
mimic_done_out will be reset during MIMIC_IDLE
the purpose of the current state is to add one clock cycle
mimic_done_out will be active for 2 measure_clk clock cycles, i.e
the pulses duration will be just one sequencer clock cycle
(which is half rate) */
end // case: MIMIC_SEND
// MIMIC_SEND1 and MIMIC_SEND2 extend the mimic_done_out signal by another 2 measure_clk_2x cycles
// so it is a total of 4 measure clocks long (ie 2 half-rate clock cycles long in total)
`MIMIC_SEND1 : begin
mimic_done_out <= 1'b1; //redundant statement, here just for readibility
mimic_state <= `MIMIC_SEND2;
end
`MIMIC_SEND2 : begin
mimic_done_out <= 1'b1; //redundant statement, here just for readibility
mimic_state <= `MIMIC_IDLE;
end
default : begin
mimic_state <= `MIMIC_IDLE;
end
endcase
end
end
assign shift_reg_data_out_all_ones = (( & shift_reg_data_out) == 1'b1) ? 1'b1
: 1'b0;
// Shift Register assignments
assign shift_reg_data_in = mimic_data_in_sample;
assign shift_reg_a_clr = !reset_measure_clk_n;
// Output assignments
assign mmc_seq_done = mimic_done_out;
assign mmc_seq_value = mimic_value_captured;
endmodule
`default_nettype wire
//
/* -----------------------------------------------------------------------------
// module description
----------------------------------------------------------------------------- */
//
module ddr_ctrl_ip_phy_alt_mem_phy_mimic_debug(
// Inputs
// Clocks
measure_clk, // full rate clock from PLL
// Active low reset
reset_measure_clk_n,
mimic_recapture_debug_data, // from user board button
mmc_seq_done, // mimic calibration finished for the current PLL phase
mmc_seq_value // result value of the mimic calibration
);
// Parameters
parameter NUM_DEBUG_SAMPLES_TO_STORE = 4096; // can range from 4096 to 524288
parameter PLL_STEPS_PER_CYCLE = 24; // can range from 16 to 48
input wire measure_clk;
input wire reset_measure_clk_n;
input wire mimic_recapture_debug_data;
input wire mmc_seq_done;
input wire mmc_seq_value;
function integer clogb2;
input [31:0] value;
for (clogb2=0; value>0; clogb2=clogb2+1)
value = value >> 1;
endfunction // clogb2
parameter RAM_WR_ADDRESS_WIDTH = clogb2(NUM_DEBUG_SAMPLES_TO_STORE - 1); // can range from 12 to 19
reg s_clr_ram_wr_address_count;
reg [(clogb2(PLL_STEPS_PER_CYCLE)-1) : 0] mimic_sample_count;
reg [RAM_WR_ADDRESS_WIDTH-1 : 0 ] ram_write_address;
wire ram_wr_enable;
wire [0:0] debug_ram_data;
reg clear_ram_wr_enable;
reg [1:0] mimic_recapture_debug_data_metastable;
wire mimic_done_in_dbg; // for internal use, just 1 measure_clk cycles long
reg mmc_seq_done_r;
// generate mimic_done_in_debug : a single clock wide pulse based on the rising edge of mmc_seq_done:
always @ (posedge measure_clk or negedge reset_measure_clk_n)
begin
if (reset_measure_clk_n == 1'b0) // asynchronous reset (active low)
begin
mmc_seq_done_r <= 1'b0;
end
else
begin
mmc_seq_done_r <= mmc_seq_done;
end
end
assign mimic_done_in_dbg = mmc_seq_done && !mmc_seq_done_r;
assign ram_wr_enable = mimic_done_in_dbg && !clear_ram_wr_enable;
assign debug_ram_data[0] = mmc_seq_value;
altsyncram #(
.clock_enable_input_a ( "BYPASS"),
.clock_enable_output_a ( "BYPASS"),
.intended_device_family ( "Stratix II"),
.lpm_hint ( "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=MRAM"),
.lpm_type ( "altsyncram"),
.maximum_depth ( 4096),
.numwords_a ( 4096),
.operation_mode ( "SINGLE_PORT"),
.outdata_aclr_a ( "NONE"),
.outdata_reg_a ( "UNREGISTERED"),
.power_up_uninitialized ( "FALSE"),
.widthad_a ( 12),
.width_a ( 1),
.width_byteena_a ( 1)
)
altsyncram_component (
.wren_a ( ram_wr_enable),
.clock0 ( measure_clk),
.address_a ( ram_write_address),
.data_a ( debug_ram_data),
.q_a ( )
);
// Metastability_mimic_recapture_debug_data :
always @(posedge measure_clk or negedge reset_measure_clk_n)
begin
if (reset_measure_clk_n == 1'b0)
begin
mimic_recapture_debug_data_metastable <= 2'b0;
end
else
begin
mimic_recapture_debug_data_metastable[0] <= mimic_recapture_debug_data;
mimic_recapture_debug_data_metastable[1] <= mimic_recapture_debug_data_metastable[0];
end
end
//mimic_sample_counter :
always @(posedge measure_clk or negedge reset_measure_clk_n)
begin
if (reset_measure_clk_n == 1'b0)
begin
mimic_sample_count <= 0; // (others => '0');
end
else
begin
if (mimic_done_in_dbg == 1'b1)
begin
mimic_sample_count <= mimic_sample_count + 1'b1;
if (mimic_sample_count == PLL_STEPS_PER_CYCLE-1)
begin
mimic_sample_count <= 0; //(others => '0');
end
end
end
end
//RAMWrAddressCounter :
always @(posedge measure_clk or negedge reset_measure_clk_n)
begin
if (reset_measure_clk_n == 1'b0)
begin
ram_write_address <= 0; //(others => '0');
clear_ram_wr_enable <= 1'b0;
end
else
begin
if (s_clr_ram_wr_address_count == 1'b1) // then --Active high synchronous reset
begin
ram_write_address <= 0; //(others => '0');
clear_ram_wr_enable <= 1'b1;
end
else
begin
clear_ram_wr_enable <= 1'b0;
if (mimic_done_in_dbg == 1'b1)
begin
if (ram_write_address != NUM_DEBUG_SAMPLES_TO_STORE-1)
begin
ram_write_address <= ram_write_address + 1'b1;
end
else
begin
clear_ram_wr_enable <= 1'b1;
end
end
end
end
end
//ClearRAMWrAddressCounter :
always @(posedge measure_clk or negedge reset_measure_clk_n)
begin
if (reset_measure_clk_n == 1'b0)
begin
s_clr_ram_wr_address_count <= 1'b0;
end
else
begin
if (mimic_recapture_debug_data_metastable[1] == 1'b1)
begin
s_clr_ram_wr_address_count <= 1'b1;
end
else if (mimic_sample_count == 0)
begin
s_clr_ram_wr_address_count <= 1'b0;
end
end
end
endmodule
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr_ctrl_ip_phy_alt_mem_phy_reset_pipe (
input wire clock,
input wire pre_clear,
output wire reset_out
);
parameter PIPE_DEPTH = 4;
// Declare pipeline registers.
reg [PIPE_DEPTH - 1 : 0] ams_pipe;
integer i;
// begin : RESET_PIPE
always @(posedge clock or negedge pre_clear)
begin
if (pre_clear == 1'b0)
begin
ams_pipe <= 0;
end
else
begin
for (i=0; i< PIPE_DEPTH; i = i + 1)
begin
if (i==0)
ams_pipe[i] <= 1'b1;
else
ams_pipe[i] <= ams_pipe[i-1];
end
end // if-else
end // always
// end
assign reset_out = ams_pipe[PIPE_DEPTH-1];
endmodule
|
// Copyright (c) 2014 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Tests initialization of records with aggregate expressions.
// (based on the vhdl_struct_array test)
module vhdl_record_elab_test;
reg [15:0] in;
wire [15:0] out;
vhdl_record_elab dut(
.o_high1(out[15:12]), .o_low1(out[11:8]),
.o_high0(out[7:4]), .o_low0(out[3:0]),
.i_high1(in[15:12]), .i_low1(in[11:8]),
.i_high0(in[7:4]), .i_low0(in[3:0]));
initial begin
for (in = 0 ; in < 256 ; in = in+1) begin
#1 if (in !== out[15:0]) begin
$display("FAILED -- out=%h, in=%h", out, in);
$finish;
end
end
if (dut.dword_a[0].low !== 4'b0110 || dut.dword_a[0].high !== 4'b1001 ||
dut.dword_a[1].low !== 4'b0011 || dut.dword_a[1].high !== 4'b1100)
begin
$display("FAILED 2");
$finish;
end
$display("PASSED");
end
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1ps/1ps
module altera_pll_reconfig_core
#(
parameter reconf_width = 64,
parameter device_family = "Stratix V",
// MIF Streaming parameters
parameter RECONFIG_ADDR_WIDTH = 6,
parameter RECONFIG_DATA_WIDTH = 32,
parameter ROM_ADDR_WIDTH = 9,
parameter ROM_DATA_WIDTH = 32,
parameter ROM_NUM_WORDS = 512
) (
//input
input wire mgmt_clk,
input wire mgmt_reset,
//conduits
output wire [reconf_width-1:0] reconfig_to_pll,
input wire [reconf_width-1:0] reconfig_from_pll,
// user data (avalon-MM slave interface)
output wire [31:0] mgmt_readdata,
output wire mgmt_waitrequest,
input wire [5:0] mgmt_address,
input wire mgmt_read,
input wire mgmt_write,
input wire [31:0] mgmt_writedata,
//other
output wire mif_start_out,
output reg [ROM_ADDR_WIDTH-1:0] mif_base_addr
);
localparam mode_WR = 1'b0;
localparam mode_POLL = 1'b1;
localparam MODE_REG = 6'b000000;
localparam STATUS_REG = 6'b000001;
localparam START_REG = 6'b000010;
localparam N_REG = 6'b000011;
localparam M_REG = 6'b000100;
localparam C_COUNTERS_REG = 6'b000101;
localparam DPS_REG = 6'b000110;
localparam DSM_REG = 6'b000111;
localparam BWCTRL_REG = 6'b001000;
localparam CP_CURRENT_REG = 6'b001001;
localparam ANY_DPRIO = 6'b100000;
localparam CNT_BASE = 5'b001010;
localparam MIF_REG = 6'b011111;
//C Counters
localparam number_of_counters = 5'd18;
localparam CNT_0 = 1'd0, CNT_1 = 5'd1, CNT_2 = 5'd2,
CNT_3 = 5'd3, CNT_4 = 5'd4, CNT_5 = 5'd5,
CNT_6 = 5'd6, CNT_7 = 5'd7, CNT_8 = 5'd8,
CNT_9 = 5'd9, CNT_10 = 5'd10, CNT_11 = 5'd11,
CNT_12 = 5'd12, CNT_13 = 5'd13, CNT_14 = 5'd14,
CNT_15 = 5'd15, CNT_16 = 5'd16, CNT_17 = 5'd17;
//C counter addresses
localparam C_CNT_0_DIV_ADDR = 5'h00;
localparam C_CNT_0_DIV_ADDR_DPRIO_1 = 5'h11;
localparam C_CNT_0_3_BYPASS_EN_ADDR = 5'h15;
localparam C_CNT_0_3_ODD_DIV_EN_ADDR = 5'h17;
localparam C_CNT_4_17_BYPASS_EN_ADDR = 5'h14;
localparam C_CNT_4_17_ODD_DIV_EN_ADDR = 5'h16;
//N counter addresses
localparam N_CNT_DIV_ADDR = 5'h13;
localparam N_CNT_BYPASS_EN_ADDR = 5'h15;
localparam N_CNT_ODD_DIV_EN_ADDR = 5'h17;
//M counter addresses
localparam M_CNT_DIV_ADDR = 5'h12;
localparam M_CNT_BYPASS_EN_ADDR = 5'h15;
localparam M_CNT_ODD_DIV_EN_ADDR = 5'h17;
//DSM address
localparam DSM_K_FRACTIONAL_DIVISION_ADDR_0 = 5'h18;
localparam DSM_K_FRACTIONAL_DIVISION_ADDR_1 = 5'h19;
localparam DSM_K_READY_ADDR = 5'h17;
localparam DSM_K_DITHER_ADDR = 5'h17;
localparam DSM_OUT_SEL_ADDR = 6'h30;
//Other DSM params
localparam DSM_K_READY_BIT_INDEX = 4'd11;
//BWCTRL address
//Bit 0-3 of addr
localparam BWCTRL_ADDR = 6'h30;
//CP_CURRENT address
//Bit 0-2 of addr
localparam CP_CURRENT_ADDR = 6'h31;
localparam DPRIO_IDLE = 3'd0, ONE = 3'd1, TWO = 3'd2, THREE = 3'd3, FOUR = 3'd4,
FIVE = 3'd5, SIX = 3'd6, SEVEN = 3'd7, EIGHT = 4'd8, NINE = 4'd9, TEN = 4'd10,
ELEVEN = 4'd11, TWELVE = 4'd12, THIRTEEN = 4'd13, FOURTEEN = 4'd14, DPRIO_DONE = 4'd15;
localparam IDLE = 2'b00, WAIT_ON_LOCK = 2'b01, LOCKED = 2'b10;
wire clk;
wire reset;
wire gnd;
wire [5: 0] slave_address;
wire slave_read;
wire slave_write;
wire [31: 0] slave_writedata;
reg [31: 0] slave_readdata_d;
reg [31: 0] slave_readdata_q;
wire slave_waitrequest;
assign clk = mgmt_clk;
assign slave_address = mgmt_address;
assign slave_read = mgmt_read;
assign slave_write = mgmt_write;
assign slave_writedata = mgmt_writedata;
// Outputs
assign mgmt_readdata = slave_readdata_q;
assign mgmt_waitrequest = slave_waitrequest;
//internal signals
wire locked;
wire pll_start;
wire pll_start_valid;
reg status_read;
wire read_slave_mode_asserted;
wire pll_start_asserted;
reg [1:0] current_state;
reg [1:0] next_state;
reg slave_mode;
reg status;//0=busy, 1=ready
//user_mode_init user_mode_init_inst (clk, reset, dprio_mdio_dis, ser_shift_load);
//declaring the init wires. These will have 0 on them for 64 clk cycles
wire [ 5:0] init_dprio_address;
wire init_dprio_read;
wire [ 1:0] init_dprio_byteen;
wire init_dprio_write;
wire [15:0] init_dprio_writedata;
wire init_atpgmode;
wire init_mdio_dis;
wire init_scanen;
wire init_ser_shift_load;
wire dprio_init_done;
//DPRIO output signals after initialization is done
wire dprio_clk;
reg avmm_dprio_write;
reg avmm_dprio_read;
reg [5:0] avmm_dprio_address;
reg [15:0] avmm_dprio_writedata;
reg [1:0] avmm_dprio_byteen;
wire avmm_atpgmode;
wire avmm_mdio_dis;
wire avmm_scanen;
//Final output wires that are muxed between the init and avmm wires.
wire dprio_init_reset;
wire [5:0] dprio_address /*synthesis keep*/;
wire dprio_read/*synthesis keep*/;
wire [1:0] dprio_byteen/*synthesis keep*/;
wire dprio_write/*synthesis keep*/;
wire [15:0] dprio_writedata/*synthesis keep*/;
wire dprio_mdio_dis/*synthesis keep*/;
wire dprio_ser_shift_load/*synthesis keep*/;
wire dprio_atpgmode/*synthesis keep*/;
wire dprio_scanen/*synthesis keep*/;
//other PLL signals for dyn ph shift
wire phase_done/*synthesis keep*/;
wire phase_en/*synthesis keep*/;
wire up_dn/*synthesis keep*/;
wire [4:0] cnt_sel;
//DPRIO input signals
wire [15:0] dprio_readdata;
//internal logic signals
//storage registers for user sent data
reg dprio_temp_read_1;
reg dprio_temp_read_2;
reg dprio_start;
reg mif_start_assert;
reg dps_start_assert;
wire usr_valid_changes;
reg [3:0] dprio_cur_state;
reg [3:0] dprio_next_state;
reg [15:0] dprio_temp_m_n_c_readdata_1_d;
reg [15:0] dprio_temp_m_n_c_readdata_2_d;
reg [15:0] dprio_temp_m_n_c_readdata_1_q;
reg [15:0] dprio_temp_m_n_c_readdata_2_q;
reg dprio_write_done;
//C counters signals
reg [7:0] usr_c_cnt_lo;
reg [7:0] usr_c_cnt_hi;
reg usr_c_cnt_bypass_en;
reg usr_c_cnt_odd_duty_div_en;
reg [7:0] temp_c_cnt_lo [0:17];
reg [7:0] temp_c_cnt_hi [0:17];
reg temp_c_cnt_bypass_en [0:17];
reg temp_c_cnt_odd_duty_div_en [0:17];
reg any_c_cnt_changed;
reg all_c_cnt_done_q;
reg all_c_cnt_done_d;
reg [17:0] c_cnt_changed;
reg [17:0] c_cnt_done_d;
reg [17:0] c_cnt_done_q;
//N counter signals
reg [7:0] usr_n_cnt_lo;
reg [7:0] usr_n_cnt_hi;
reg usr_n_cnt_bypass_en;
reg usr_n_cnt_odd_duty_div_en;
reg n_cnt_changed;
reg n_cnt_done_d;
reg n_cnt_done_q;
//M counter signals
reg [7:0] usr_m_cnt_lo;
reg [7:0] usr_m_cnt_hi;
reg usr_m_cnt_bypass_en;
reg usr_m_cnt_odd_duty_div_en;
reg m_cnt_changed;
reg m_cnt_done_d;
reg m_cnt_done_q;
//dyn phase regs
reg [15:0] usr_num_shifts;
reg [4:0] usr_cnt_sel /*synthesis preserve*/;
reg usr_up_dn;
reg dps_changed;
wire dps_changed_valid;
wire dps_done;
//DSM Signals
reg [31:0] usr_k_value;
reg dsm_k_changed;
reg dsm_k_done_d;
reg dsm_k_done_q;
reg dsm_k_ready_false_done_d;
//BW signals
reg [3:0] usr_bwctrl_value;
reg bwctrl_changed;
reg bwctrl_done_d;
reg bwctrl_done_q;
//CP signals
reg [2:0] usr_cp_current_value;
reg cp_current_changed;
reg cp_current_done_d;
reg cp_current_done_q;
//Manual DPRIO signals
reg manual_dprio_done_q;
reg manual_dprio_done_d;
reg manual_dprio_changed;
reg [5:0] usr_dprio_address;
reg [15:0] usr_dprio_writedata_0;
reg usr_r_w;
//keeping track of which operation happened last
reg [5:0] operation_address;
// Address wires for all C_counter DPRIO registers
// These are outputs of LUTS, changing depending
// on whether PLL_0 or PLL_1 being used
//Fitter will tell if FPLL1 is being used
wire fpll_1;
// other
reg mif_reg_asserted;
// MAIN FSM
always @(posedge clk)
begin
if (reset)
begin
dprio_cur_state <= DPRIO_IDLE;
current_state <= IDLE;
end
else
begin
current_state <= next_state;
dprio_cur_state <= dprio_next_state;
end
end
always @(*)
begin
case(current_state)
IDLE:
begin
if (pll_start & !slave_waitrequest & usr_valid_changes)
next_state = WAIT_ON_LOCK;
else
next_state = IDLE;
end
WAIT_ON_LOCK:
begin
if (locked & dps_done & dprio_write_done) // received locked high from PLL
begin
if (slave_mode==mode_WR) //if the mode is waitrequest, then
// goto IDLE state directly
next_state = IDLE;
else
next_state = LOCKED; //otherwise go the locked state
end
else
next_state = WAIT_ON_LOCK;
end
LOCKED:
begin
if (status_read) // stay in LOCKED until user reads status
next_state = IDLE;
else
next_state = LOCKED;
end
default: next_state = 2'bxx;
endcase
end
// ask the pll to start reconfig
assign pll_start = (pll_start_asserted & (current_state==IDLE)) ;
assign pll_start_valid = (pll_start & (next_state==WAIT_ON_LOCK)) ;
// WRITE OPERATIONS
assign pll_start_asserted = slave_write & (slave_address == START_REG);
assign mif_start_out = pll_start & mif_reg_asserted;
//reading the mode register to determine what mode the slave will operate
//in.
always @(posedge clk)
begin
if (reset)
slave_mode <= mode_WR;
else if (slave_write & (slave_address == MODE_REG) & !slave_waitrequest)
slave_mode <= slave_writedata[0];
end
//record which values user wants to change.
//reading in the actual values that need to be reconfigged and sending
//them to the PLL
always @(posedge clk)
begin
if (reset)
begin
//reset all regs here
//BW signals reset
usr_bwctrl_value <= 0;
bwctrl_changed <= 0;
bwctrl_done_q <= 0;
//CP signals reset
usr_cp_current_value <= 0;
cp_current_changed <= 0;
cp_current_done_q <= 0;
//DSM signals reset
usr_k_value <= 0;
dsm_k_changed <= 0;
dsm_k_done_q <= 0;
//N counter signals reset
usr_n_cnt_lo <= 0;
usr_n_cnt_hi <= 0;
usr_n_cnt_bypass_en <= 0;
usr_n_cnt_odd_duty_div_en <= 0;
n_cnt_changed <= 0;
n_cnt_done_q <= 0;
//M counter signals reset
usr_m_cnt_lo <= 0;
usr_m_cnt_hi <= 0;
usr_m_cnt_bypass_en <= 0;
usr_m_cnt_odd_duty_div_en <= 0;
m_cnt_changed <= 0;
m_cnt_done_q <= 0;
//C counter signals reset
usr_c_cnt_lo <= 0;
usr_c_cnt_hi <= 0;
usr_c_cnt_bypass_en <= 0;
usr_c_cnt_odd_duty_div_en <= 0;
any_c_cnt_changed <= 0;
all_c_cnt_done_q <= 0;
c_cnt_done_q <= 0;
//generic signals
dprio_start <= 0;
mif_start_assert <= 0;
dps_start_assert <= 0;
dprio_temp_m_n_c_readdata_1_q <= 0;
dprio_temp_m_n_c_readdata_2_q <= 0;
c_cnt_done_q <= 0;
//DPS signals
usr_up_dn <= 0;
usr_cnt_sel <= 0;
usr_num_shifts <= 0;
dps_changed <= 0;
//manual DPRIO signals
manual_dprio_changed <= 0;
usr_dprio_address <= 0;
usr_dprio_writedata_0 <= 0;
usr_r_w <= 0;
operation_address <= 0;
mif_reg_asserted <= 0;
mif_base_addr <= 0;
end
else
begin
if (dprio_temp_read_1)
begin
dprio_temp_m_n_c_readdata_1_q <= dprio_temp_m_n_c_readdata_1_d;
end
if (dprio_temp_read_2)
begin
dprio_temp_m_n_c_readdata_2_q <= dprio_temp_m_n_c_readdata_2_d;
end
if ((dps_done)) dps_changed <= 0;
if (dsm_k_done_d) dsm_k_done_q <= dsm_k_done_d;
if (n_cnt_done_d) n_cnt_done_q <= n_cnt_done_d;
if (m_cnt_done_d) m_cnt_done_q <= m_cnt_done_d;
if (all_c_cnt_done_d) all_c_cnt_done_q <= all_c_cnt_done_d;
if (c_cnt_done_d != 0) c_cnt_done_q <= c_cnt_done_q | c_cnt_done_d;
if (bwctrl_done_d) bwctrl_done_q <= bwctrl_done_d;
if (cp_current_done_d) cp_current_done_q <= cp_current_done_d;
if (manual_dprio_done_d) manual_dprio_done_q <= manual_dprio_done_d;
if (mif_start_out == 1'b1)
mif_start_assert <= 0; // Signaled MIF block to start, so deassert on next cycle
if (dps_done != 1'b1)
dps_start_assert <= 0; // DPS has started, so dessert its start signal on next cycle
if (dprio_next_state == ONE)
dprio_start <= 0;
if (dprio_write_done)
begin
bwctrl_done_q <= 0;
cp_current_done_q <= 0;
dsm_k_done_q <= 0;
dsm_k_done_q <= 0;
n_cnt_done_q <= 0;
m_cnt_done_q <= 0;
all_c_cnt_done_q <= 0;
c_cnt_done_q <= 0;
dsm_k_changed <= 0;
n_cnt_changed <= 0;
m_cnt_changed <= 0;
any_c_cnt_changed <= 0;
bwctrl_changed <= 0;
cp_current_changed <= 0;
manual_dprio_changed <= 0;
manual_dprio_done_q <= 0;
if (dps_changed | dps_changed_valid | !dps_done )
begin
usr_cnt_sel <= usr_cnt_sel;
end
else
begin
usr_cnt_sel <= 0;
end
mif_reg_asserted <= 0;
end
else
begin
dsm_k_changed <= dsm_k_changed;
n_cnt_changed <= n_cnt_changed;
m_cnt_changed <= m_cnt_changed;
any_c_cnt_changed <= any_c_cnt_changed;
manual_dprio_changed <= manual_dprio_changed;
mif_reg_asserted <= mif_reg_asserted;
usr_cnt_sel <= usr_cnt_sel;
end
if(slave_write & !slave_waitrequest)
begin
case(slave_address)
//read in the values here from the user and act on them
DSM_REG:
begin
operation_address <= DSM_REG;
usr_k_value <= slave_writedata[31:0];
dsm_k_changed <= 1'b1;
dsm_k_done_q <= 0;
dprio_start <= 1'b1;
end
N_REG:
begin
operation_address <= N_REG;
usr_n_cnt_lo <= slave_writedata[7:0];
usr_n_cnt_hi <= slave_writedata[15:8];
usr_n_cnt_bypass_en <= slave_writedata[16];
usr_n_cnt_odd_duty_div_en <= slave_writedata[17];
n_cnt_changed <= 1'b1;
n_cnt_done_q <= 0;
dprio_start <= 1'b1;
end
M_REG:
begin
operation_address <= M_REG;
usr_m_cnt_lo <= slave_writedata[7:0];
usr_m_cnt_hi <= slave_writedata[15:8];
usr_m_cnt_bypass_en <= slave_writedata[16];
usr_m_cnt_odd_duty_div_en <= slave_writedata[17];
m_cnt_changed <= 1'b1;
m_cnt_done_q <= 0;
dprio_start <= 1'b1;
end
DPS_REG:
begin
operation_address <= DPS_REG;
usr_num_shifts <= slave_writedata[15:0];
usr_cnt_sel <= slave_writedata[20:16];
usr_up_dn <= slave_writedata[21];
dps_changed <= 1;
dps_start_assert <= 1;
end
C_COUNTERS_REG:
begin
operation_address <= C_COUNTERS_REG;
usr_c_cnt_lo <= slave_writedata[7:0];
usr_c_cnt_hi <= slave_writedata[15:8];
usr_c_cnt_bypass_en <= slave_writedata[16];
usr_c_cnt_odd_duty_div_en <= slave_writedata[17];
usr_cnt_sel <= slave_writedata[22:18];
any_c_cnt_changed <= 1'b1;
all_c_cnt_done_q <= 0;
dprio_start <= 1'b1;
end
BWCTRL_REG:
begin
usr_bwctrl_value <= slave_writedata[3:0];
bwctrl_changed <= 1'b1;
bwctrl_done_q <= 0;
dprio_start <= 1'b1;
operation_address <= BWCTRL_REG;
end
CP_CURRENT_REG:
begin
usr_cp_current_value <= slave_writedata[2:0];
cp_current_changed <= 1'b1;
cp_current_done_q <= 0;
dprio_start <= 1'b1;
operation_address <= CP_CURRENT_REG;
end
ANY_DPRIO:
begin
operation_address <= ANY_DPRIO;
manual_dprio_changed <= 1'b1;
usr_dprio_address <= slave_writedata[5:0];
usr_dprio_writedata_0 <= slave_writedata[21:6];
usr_r_w <= slave_writedata[22];
manual_dprio_done_q <= 0;
dprio_start <= 1'b1;
end
MIF_REG:
begin
mif_reg_asserted <= 1'b1;
mif_base_addr <= slave_writedata[ROM_ADDR_WIDTH-1:0];
mif_start_assert <= 1'b1;
end
endcase
end
end
end
//C Counter assigning values to the 2-d array of values for each C counter
reg [4:0] j;
always @(posedge clk)
begin
if (reset)
begin
c_cnt_changed[17:0] <= 0;
for (j = 0; j < number_of_counters; j = j + 1'b1)
begin : c_cnt_reset
temp_c_cnt_bypass_en[j] <= 0;
temp_c_cnt_odd_duty_div_en[j] <= 0;
temp_c_cnt_lo[j][7:0] <= 0;
temp_c_cnt_hi[j][7:0] <= 0;
end
end
else
begin
if (dprio_write_done)
begin
c_cnt_changed <= 0;
end
if (any_c_cnt_changed && (operation_address == C_COUNTERS_REG))
begin
case (cnt_sel)
CNT_0:
begin
temp_c_cnt_lo [0] <= usr_c_cnt_lo;
temp_c_cnt_hi [0] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [0] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [0] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [0] <= 1'b1;
end
CNT_1:
begin
temp_c_cnt_lo [1] <= usr_c_cnt_lo;
temp_c_cnt_hi [1] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [1] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [1] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [1] <= 1'b1;
end
CNT_2:
begin
temp_c_cnt_lo [2] <= usr_c_cnt_lo;
temp_c_cnt_hi [2] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [2] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [2] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [2] <= 1'b1;
end
CNT_3:
begin
temp_c_cnt_lo [3] <= usr_c_cnt_lo;
temp_c_cnt_hi [3] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [3] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [3] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [3] <= 1'b1;
end
CNT_4:
begin
temp_c_cnt_lo [4] <= usr_c_cnt_lo;
temp_c_cnt_hi [4] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [4] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [4] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [4] <= 1'b1;
end
CNT_5:
begin
temp_c_cnt_lo [5] <= usr_c_cnt_lo;
temp_c_cnt_hi [5] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [5] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [5] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [5] <= 1'b1;
end
CNT_6:
begin
temp_c_cnt_lo [6] <= usr_c_cnt_lo;
temp_c_cnt_hi [6] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [6] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [6] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [6] <= 1'b1;
end
CNT_7:
begin
temp_c_cnt_lo [7] <= usr_c_cnt_lo;
temp_c_cnt_hi [7] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [7] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [7] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [7] <= 1'b1;
end
CNT_8:
begin
temp_c_cnt_lo [8] <= usr_c_cnt_lo;
temp_c_cnt_hi [8] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [8] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [8] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [8] <= 1'b1;
end
CNT_9:
begin
temp_c_cnt_lo [9] <= usr_c_cnt_lo;
temp_c_cnt_hi [9] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [9] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [9] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [9] <= 1'b1;
end
CNT_10:
begin
temp_c_cnt_lo [10] <= usr_c_cnt_lo;
temp_c_cnt_hi [10] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [10] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [10] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [10] <= 1'b1;
end
CNT_11:
begin
temp_c_cnt_lo [11] <= usr_c_cnt_lo;
temp_c_cnt_hi [11] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [11] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [11] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [11] <= 1'b1;
end
CNT_12:
begin
temp_c_cnt_lo [12] <= usr_c_cnt_lo;
temp_c_cnt_hi [12] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [12] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [12] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [12] <= 1'b1;
end
CNT_13:
begin
temp_c_cnt_lo [13] <= usr_c_cnt_lo;
temp_c_cnt_hi [13] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [13] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [13] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [13] <= 1'b1;
end
CNT_14:
begin
temp_c_cnt_lo [14] <= usr_c_cnt_lo;
temp_c_cnt_hi [14] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [14] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [14] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [14] <= 1'b1;
end
CNT_15:
begin
temp_c_cnt_lo [15] <= usr_c_cnt_lo;
temp_c_cnt_hi [15] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [15] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [15] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [15] <= 1'b1;
end
CNT_16:
begin
temp_c_cnt_lo [16] <= usr_c_cnt_lo;
temp_c_cnt_hi [16] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [16] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [16] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [16] <= 1'b1;
end
CNT_17:
begin
temp_c_cnt_lo [17] <= usr_c_cnt_lo;
temp_c_cnt_hi [17] <= usr_c_cnt_hi;
temp_c_cnt_bypass_en [17] <= usr_c_cnt_bypass_en;
temp_c_cnt_odd_duty_div_en [17] <= usr_c_cnt_odd_duty_div_en;
c_cnt_changed [17] <= 1'b1;
end
endcase
end
end
end
//logic to handle which writes the user indicated and wants to start.
assign usr_valid_changes =dsm_k_changed| any_c_cnt_changed |n_cnt_changed | m_cnt_changed | dps_changed_valid |manual_dprio_changed |cp_current_changed|bwctrl_changed;
//start the reconfig operations by writing to the DPRIO
reg break_loop;
reg [4:0] i;
always @(*)
begin
dprio_temp_read_1 = 0;
dprio_temp_read_2 = 0;
dprio_temp_m_n_c_readdata_1_d = 0;
dprio_temp_m_n_c_readdata_2_d = 0;
break_loop = 0;
dprio_next_state = DPRIO_IDLE;
avmm_dprio_write = 0;
avmm_dprio_read = 0;
avmm_dprio_address = 0;
avmm_dprio_writedata = 0;
avmm_dprio_byteen = 0;
dprio_write_done = 1;
manual_dprio_done_d = 0;
n_cnt_done_d = 0;
dsm_k_done_d = 0;
dsm_k_ready_false_done_d = 0;
m_cnt_done_d = 0;
c_cnt_done_d[17:0] = 0;
all_c_cnt_done_d = 0;
bwctrl_done_d = 0;
cp_current_done_d = 0;
i = 0;
// Deassert dprio_write_done so it doesn't reset mif_reg_asserted (toggled writes)
if (dprio_start | mif_start_assert)
dprio_write_done = 0;
if (current_state == WAIT_ON_LOCK)
begin
case (dprio_cur_state)
ONE:
begin
if (n_cnt_changed & !n_cnt_done_q)
begin
dprio_write_done = 0;
avmm_dprio_write = 1'b1;
avmm_dprio_byteen = 2'b11;
dprio_next_state = TWO;
avmm_dprio_address = N_CNT_DIV_ADDR;
avmm_dprio_writedata[7:0] = usr_n_cnt_lo;
avmm_dprio_writedata[15:8] = usr_n_cnt_hi;
end
else if (m_cnt_changed & !m_cnt_done_q)
begin
dprio_write_done = 0;
avmm_dprio_write = 1'b1;
avmm_dprio_byteen = 2'b11;
dprio_next_state = TWO;
avmm_dprio_address = M_CNT_DIV_ADDR;
avmm_dprio_writedata[7:0] = usr_m_cnt_lo;
avmm_dprio_writedata[15:8] = usr_m_cnt_hi;
end
else if (any_c_cnt_changed & !all_c_cnt_done_q)
begin
for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1)
begin : c_cnt_write_hilo
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
dprio_write_done = 0;
avmm_dprio_write = 1'b1;
avmm_dprio_byteen = 2'b11;
dprio_next_state = TWO;
if (fpll_1) avmm_dprio_address = C_CNT_0_DIV_ADDR + C_CNT_0_DIV_ADDR_DPRIO_1 - i;
else avmm_dprio_address = C_CNT_0_DIV_ADDR + i;
avmm_dprio_writedata[7:0] = temp_c_cnt_lo[i];
avmm_dprio_writedata[15:8] = temp_c_cnt_hi[i];
//To break from the loop, since only one counter
//is addressed at a time
break_loop = 1'b1;
end
end
end
else if (dsm_k_changed & !dsm_k_done_q)
begin
dprio_write_done = 0;
avmm_dprio_write = 0;
dprio_next_state = TWO;
end
else if (bwctrl_changed & !bwctrl_done_q)
begin
dprio_write_done = 0;
avmm_dprio_write = 0;
dprio_next_state = TWO;
end
else if (cp_current_changed & !cp_current_done_q)
begin
dprio_write_done = 0;
avmm_dprio_write = 0;
dprio_next_state = TWO;
end
else if (manual_dprio_changed & !manual_dprio_done_q)
begin
dprio_write_done = 0;
avmm_dprio_byteen = 2'b11;
dprio_next_state = TWO;
avmm_dprio_write = usr_r_w;
avmm_dprio_address = usr_dprio_address;
avmm_dprio_writedata[15:0] = usr_dprio_writedata_0;
end
else dprio_next_state = DPRIO_IDLE;
end
TWO:
begin
//handle reading the two setting bits on n_cnt, then
//writing them back while preserving other bits.
//Issue two consecutive reads then wait; readLatency=3
dprio_write_done = 0;
dprio_next_state = THREE;
avmm_dprio_byteen = 2'b11;
avmm_dprio_read = 1'b1;
if (n_cnt_changed & !n_cnt_done_q)
begin
avmm_dprio_address = N_CNT_BYPASS_EN_ADDR;
end
else if (m_cnt_changed & !m_cnt_done_q)
begin
avmm_dprio_address = M_CNT_BYPASS_EN_ADDR;
end
else if (any_c_cnt_changed & !all_c_cnt_done_q)
begin
for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1)
begin : c_cnt_read_bypass
if (fpll_1)
begin
if (i > 13)
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR;
break_loop = 1'b1;
end
end
else
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR;
break_loop = 1'b1;
end
end
end
else
begin
if (i < 4)
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR;
break_loop = 1'b1;
end
end
else
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR;
break_loop = 1'b1;
end
end
end
end
end
//reading the K ready 16 bit word. Need to write 0 to it
//afterwards to indicate that K has not been done writing
else if (dsm_k_changed & !dsm_k_done_q)
begin
avmm_dprio_address = DSM_K_READY_ADDR;
dprio_next_state = FOUR;
end
else if (bwctrl_changed & !bwctrl_done_q)
begin
avmm_dprio_address = BWCTRL_ADDR;
dprio_next_state = FOUR;
end
else if (cp_current_changed & !cp_current_done_q)
begin
avmm_dprio_address = CP_CURRENT_ADDR;
dprio_next_state = FOUR;
end
else if (manual_dprio_changed & !manual_dprio_done_q)
begin
avmm_dprio_read = ~usr_r_w;
avmm_dprio_address = usr_dprio_address;
dprio_next_state = DPRIO_DONE;
end
else dprio_next_state = DPRIO_IDLE;
end
THREE:
begin
dprio_write_done = 0;
avmm_dprio_byteen = 2'b11;
avmm_dprio_read = 1'b1;
dprio_next_state = FOUR;
if (n_cnt_changed & !n_cnt_done_q)
begin
avmm_dprio_address = N_CNT_ODD_DIV_EN_ADDR;
end
else if (m_cnt_changed & !m_cnt_done_q)
begin
avmm_dprio_address = M_CNT_ODD_DIV_EN_ADDR;
end
else if (any_c_cnt_changed & !all_c_cnt_done_q)
begin
for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1)
begin : c_cnt_read_odd_div
if (fpll_1)
begin
if (i > 13)
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR;
break_loop = 1'b1;
end
end
else
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR;
break_loop = 1'b1;
end
end
end
else
begin
if (i < 4)
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR;
break_loop = 1'b1;
end
end
else
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR;
break_loop = 1'b1;
end
end
end
end
end
else dprio_next_state = DPRIO_IDLE;
end
FOUR:
begin
dprio_temp_read_1 = 1'b1;
dprio_write_done = 0;
if (cp_current_changed|bwctrl_changed|dsm_k_changed|n_cnt_changed|m_cnt_changed|any_c_cnt_changed)
begin
dprio_temp_m_n_c_readdata_1_d = dprio_readdata;
dprio_next_state = FIVE;
end
else dprio_next_state = DPRIO_IDLE;
end
FIVE:
begin
dprio_write_done = 0;
dprio_temp_read_2 = 1'b1;
if (cp_current_changed|bwctrl_changed|dsm_k_changed|n_cnt_changed|m_cnt_changed|any_c_cnt_changed)
begin
//this is where DSM ready value comes.
//Need to store in a register to be used later
dprio_temp_m_n_c_readdata_2_d = dprio_readdata;
dprio_next_state = SIX;
end
else dprio_next_state = DPRIO_IDLE;
end
SIX:
begin
dprio_write_done = 0;
avmm_dprio_write = 1'b1;
avmm_dprio_byteen = 2'b11;
dprio_next_state = SEVEN;
avmm_dprio_writedata = dprio_temp_m_n_c_readdata_1_q;
if (n_cnt_changed & !n_cnt_done_q)
begin
avmm_dprio_address = N_CNT_BYPASS_EN_ADDR;
avmm_dprio_writedata[5] = usr_n_cnt_bypass_en;
end
else if (m_cnt_changed & !m_cnt_done_q)
begin
avmm_dprio_address = M_CNT_BYPASS_EN_ADDR;
avmm_dprio_writedata[4] = usr_m_cnt_bypass_en;
end
else if (any_c_cnt_changed & !all_c_cnt_done_q)
begin
for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1)
begin : c_cnt_write_bypass
if (fpll_1)
begin
if (i > 13)
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR;
avmm_dprio_writedata[i-14] = temp_c_cnt_bypass_en[i];
break_loop = 1'b1;
end
end
else
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR;
avmm_dprio_writedata[i] = temp_c_cnt_bypass_en[i];
break_loop = 1'b1;
end
end
end
else
begin
if (i < 4)
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR;
avmm_dprio_writedata[3-i] = temp_c_cnt_bypass_en[i];
break_loop = 1'b1;
end
end
else
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR;
avmm_dprio_writedata[17-i] = temp_c_cnt_bypass_en[i];
break_loop = 1'b1;
end
end
end
end
end
else if (dsm_k_changed & !dsm_k_done_q)
begin
avmm_dprio_write = 0;
end
else if (bwctrl_changed & !bwctrl_done_q)
begin
avmm_dprio_write = 0;
end
else if (cp_current_changed & !cp_current_done_q)
begin
avmm_dprio_write = 0;
end
else dprio_next_state = DPRIO_IDLE;
end
SEVEN:
begin
dprio_write_done = 0;
dprio_next_state = EIGHT;
avmm_dprio_write = 1'b1;
avmm_dprio_byteen = 2'b11;
avmm_dprio_writedata = dprio_temp_m_n_c_readdata_2_q;
if (n_cnt_changed & !n_cnt_done_q)
begin
avmm_dprio_address = N_CNT_ODD_DIV_EN_ADDR;
avmm_dprio_writedata[5] = usr_n_cnt_odd_duty_div_en;
n_cnt_done_d = 1'b1;
end
else if (m_cnt_changed & !m_cnt_done_q)
begin
avmm_dprio_address = M_CNT_ODD_DIV_EN_ADDR;
avmm_dprio_writedata[4] = usr_m_cnt_odd_duty_div_en;
m_cnt_done_d = 1'b1;
end
else if (any_c_cnt_changed & !all_c_cnt_done_q)
begin
for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1)
begin : c_cnt_write_odd_div
if (fpll_1)
begin
if (i > 13)
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR;
avmm_dprio_writedata[i-14] = temp_c_cnt_odd_duty_div_en[i];
c_cnt_done_d[i] = 1'b1;
//have to OR the signals to prevent
//overwriting of previous dones
c_cnt_done_d = c_cnt_done_d | c_cnt_done_q;
break_loop = 1'b1;
end
end
else
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR;
avmm_dprio_writedata[i] = temp_c_cnt_odd_duty_div_en[i];
c_cnt_done_d[i] = 1'b1;
c_cnt_done_d = c_cnt_done_d | c_cnt_done_q;
break_loop = 1'b1;
end
end
end
else
begin
if (i < 4)
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR;
avmm_dprio_writedata[3-i] = temp_c_cnt_odd_duty_div_en[i];
c_cnt_done_d[i] = 1'b1;
//have to OR the signals to prevent
//overwriting of previous dones
c_cnt_done_d = c_cnt_done_d | c_cnt_done_q;
break_loop = 1'b1;
end
end
else
begin
if (c_cnt_changed[i] & !c_cnt_done_q[i])
begin
avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR;
avmm_dprio_writedata[17-i] = temp_c_cnt_odd_duty_div_en[i];
c_cnt_done_d[i] = 1'b1;
c_cnt_done_d = c_cnt_done_d | c_cnt_done_q;
break_loop = 1'b1;
end
end
end
end
end
else if (dsm_k_changed & !dsm_k_done_q)
begin
avmm_dprio_address = DSM_K_READY_ADDR;
avmm_dprio_writedata[DSM_K_READY_BIT_INDEX] = 1'b0;
dsm_k_ready_false_done_d = 1'b1;
end
else if (bwctrl_changed & !bwctrl_done_q)
begin
avmm_dprio_address = BWCTRL_ADDR;
avmm_dprio_writedata[3:0] = usr_bwctrl_value;
bwctrl_done_d = 1'b1;
end
else if (cp_current_changed & !cp_current_done_q)
begin
avmm_dprio_address = CP_CURRENT_ADDR;
avmm_dprio_writedata[2:0] = usr_cp_current_value;
cp_current_done_d = 1'b1;
end
//if all C_cnt that were changed are done, then assert all_c_cnt_done
if (c_cnt_done_d == c_cnt_changed)
all_c_cnt_done_d = 1'b1;
if (n_cnt_changed & n_cnt_done_d)
dprio_next_state = DPRIO_DONE;
if (any_c_cnt_changed & !all_c_cnt_done_d & !all_c_cnt_done_q)
dprio_next_state = ONE;
else if (m_cnt_changed & !m_cnt_done_d & !m_cnt_done_q)
dprio_next_state = ONE;
else if (dsm_k_changed & !dsm_k_ready_false_done_d)
dprio_next_state = TWO;
else if (dsm_k_changed & !dsm_k_done_q)
dprio_next_state = EIGHT;
else if (bwctrl_changed & !bwctrl_done_d)
dprio_next_state = TWO;
else if (cp_current_changed & !cp_current_done_d)
dprio_next_state = TWO;
else
begin
dprio_next_state = DPRIO_DONE;
dprio_write_done = 1'b1;
end
end
//finish the rest of the DSM reads/writes
//writing k value, writing k_ready to 1.
EIGHT:
begin
dprio_write_done = 0;
dprio_next_state = NINE;
avmm_dprio_write = 1'b1;
avmm_dprio_byteen = 2'b11;
if (dsm_k_changed & !dsm_k_done_q)
begin
avmm_dprio_address = DSM_K_FRACTIONAL_DIVISION_ADDR_0;
avmm_dprio_writedata[15:0] = usr_k_value[15:0];
end
end
NINE:
begin
dprio_write_done = 0;
dprio_next_state = TEN;
avmm_dprio_write = 1'b1;
avmm_dprio_byteen = 2'b11;
if (dsm_k_changed & !dsm_k_done_q)
begin
avmm_dprio_address = DSM_K_FRACTIONAL_DIVISION_ADDR_1;
avmm_dprio_writedata[15:0] = usr_k_value[31:16];
end
end
TEN:
begin
dprio_write_done = 0;
dprio_next_state = ONE;
avmm_dprio_write = 1'b1;
avmm_dprio_byteen = 2'b11;
if (dsm_k_changed & !dsm_k_done_q)
begin
avmm_dprio_address = DSM_K_READY_ADDR;
//already have the readdata for DSM_K_READY_ADDR since we read it
//earlier. Just reuse here
avmm_dprio_writedata = dprio_temp_m_n_c_readdata_2_q;
avmm_dprio_writedata[DSM_K_READY_BIT_INDEX] = 1'b1;
dsm_k_done_d = 1'b1;
end
end
DPRIO_DONE:
begin
dprio_write_done = 1'b1;
if (dprio_start) dprio_next_state = DPRIO_IDLE;
else dprio_next_state = DPRIO_DONE;
end
DPRIO_IDLE:
begin
if (dprio_start) dprio_next_state = ONE;
else dprio_next_state = DPRIO_IDLE;
end
default: dprio_next_state = 4'bxxxx;
endcase
end
end
//assert the waitreq signal according to the state of the slave
assign slave_waitrequest = (slave_mode==mode_WR) ? ((locked === 1'b1) ? (((current_state==WAIT_ON_LOCK) & !dprio_write_done) | !dps_done |reset|!dprio_init_done) : 1'b1) : 1'b0;
// Read operations
always @(*)
begin
status = 0;
if (slave_mode == mode_POLL)
//asserting status to 1 if the slave is done.
status = (current_state == LOCKED);
end
//************************************************************//
//************************************************************//
//******************** READ STATE MACHINE ********************//
//************************************************************//
//************************************************************//
reg [1:0] current_read_state;
reg [1:0] next_read_state;
reg [5:0] slave_address_int_d;
reg [5:0] slave_address_int_q;
reg dprio_read_1;
reg [5:0] dprio_address_1;
reg [1:0] dprio_byteen_1;
reg [4:0] usr_cnt_sel_1;
localparam READ = 2'b00, READ_WAIT = 2'b01, READ_IDLE = 2'b10;
always @(posedge clk)
begin
if (reset)
begin
current_read_state <= READ_IDLE;
slave_address_int_q <= 0;
slave_readdata_q <= 0;
end
else
begin
current_read_state <= next_read_state;
slave_address_int_q <= slave_address_int_d;
slave_readdata_q <= slave_readdata_d;
end
end
always @(*)
begin
dprio_read_1 = 0;
dprio_address_1 = 0;
dprio_byteen_1 = 0;
slave_address_int_d = 0;
slave_readdata_d = 0;
status_read = 0;
usr_cnt_sel_1 = 0;
case(current_read_state)
READ_IDLE:
begin
slave_address_int_d = 0;
next_read_state = READ_IDLE;
if ((current_state != WAIT_ON_LOCK) && slave_read)
begin
slave_address_int_d = slave_address;
if ((slave_address >= CNT_BASE) && (slave_address < CNT_BASE+18))
begin
next_read_state = READ_WAIT;
dprio_byteen_1 = 2'b11;
dprio_read_1 = 1'b1;
usr_cnt_sel_1 = (slave_address[4:0] - CNT_BASE);
if (fpll_1) dprio_address_1 = C_CNT_0_DIV_ADDR + C_CNT_0_DIV_ADDR_DPRIO_1 - cnt_sel;
else dprio_address_1 = C_CNT_0_DIV_ADDR + cnt_sel;
end
else
begin
case (slave_address)
MODE_REG:
begin
next_read_state = READ_WAIT;
slave_readdata_d = slave_mode;
end
STATUS_REG:
begin
next_read_state = READ_WAIT;
status_read = 1'b1;
slave_readdata_d = status;
end
N_REG:
begin
dprio_byteen_1 = 2'b11;
dprio_read_1 = 1'b1;
dprio_address_1 = N_CNT_DIV_ADDR;
next_read_state = READ_WAIT;
end
M_REG:
begin
dprio_byteen_1 = 2'b11;
dprio_read_1 = 1'b1;
dprio_address_1 = M_CNT_DIV_ADDR;
next_read_state = READ_WAIT;
end
BWCTRL_REG:
begin
dprio_byteen_1 = 2'b11;
dprio_read_1 = 1'b1;
dprio_address_1 = BWCTRL_ADDR;
next_read_state = READ_WAIT;
end
CP_CURRENT_REG:
begin
dprio_byteen_1 = 2'b11;
dprio_read_1 = 1'b1;
dprio_address_1 = CP_CURRENT_ADDR;
next_read_state = READ_WAIT;
end
default : next_read_state = READ_IDLE;
endcase
end
end
else
next_read_state = READ_IDLE;
end
READ_WAIT:
begin
next_read_state = READ;
slave_address_int_d = slave_address_int_q;
case (slave_address_int_q)
MODE_REG:
begin
slave_readdata_d = slave_readdata_q;
end
STATUS_REG:
begin
slave_readdata_d = slave_readdata_q;
end
endcase
end
READ:
begin
next_read_state = READ_IDLE;
slave_address_int_d = slave_address_int_q;
slave_readdata_d = dprio_readdata;
case (slave_address_int_q)
MODE_REG:
begin
slave_readdata_d = slave_readdata_q;
end
STATUS_REG:
begin
slave_readdata_d = slave_readdata_q;
end
BWCTRL_REG:
begin
slave_readdata_d = dprio_readdata[3:0];
end
CP_CURRENT_REG:
begin
slave_readdata_d = dprio_readdata[2:0];
end
endcase
end
default: next_read_state = 2'bxx;
endcase
end
dyn_phase_shift dyn_phase_shift_inst (
.clk(clk),
.reset(reset),
.phase_done(phase_done),
.pll_start_valid(pll_start_valid),
.dps_changed(dps_changed),
.dps_changed_valid(dps_changed_valid),
.dprio_write_done(dprio_write_done),
.usr_num_shifts(usr_num_shifts),
.usr_cnt_sel(usr_cnt_sel|usr_cnt_sel_1),
.usr_up_dn(usr_up_dn),
.locked(locked),
.dps_done(dps_done),
.phase_en(phase_en),
.up_dn(up_dn),
.cnt_sel(cnt_sel));
defparam dyn_phase_shift_inst.device_family = device_family;
assign dprio_clk = clk;
self_reset self_reset_inst (mgmt_reset, clk, reset, dprio_init_reset);
dprio_mux dprio_mux_inst (
.init_dprio_address(init_dprio_address),
.init_dprio_read(init_dprio_read),
.init_dprio_byteen(init_dprio_byteen),
.init_dprio_write(init_dprio_write),
.init_dprio_writedata(init_dprio_writedata),
.init_atpgmode(init_atpgmode),
.init_mdio_dis(init_mdio_dis),
.init_scanen(init_scanen),
.init_ser_shift_load(init_ser_shift_load),
.dprio_init_done(dprio_init_done),
// Inputs from avmm master
.avmm_dprio_address(avmm_dprio_address | dprio_address_1),
.avmm_dprio_read(avmm_dprio_read | dprio_read_1),
.avmm_dprio_byteen(avmm_dprio_byteen | dprio_byteen_1),
.avmm_dprio_write(avmm_dprio_write),
.avmm_dprio_writedata(avmm_dprio_writedata),
.avmm_atpgmode(avmm_atpgmode),
.avmm_mdio_dis(avmm_mdio_dis),
.avmm_scanen(avmm_scanen),
// Outputs to fpll
.dprio_address(dprio_address),
.dprio_read(dprio_read),
.dprio_byteen(dprio_byteen),
.dprio_write(dprio_write),
.dprio_writedata(dprio_writedata),
.atpgmode(dprio_atpgmode),
.mdio_dis(dprio_mdio_dis),
.scanen(dprio_scanen),
.ser_shift_load(dprio_ser_shift_load)
);
fpll_dprio_init fpll_dprio_init_inst (
.clk(clk),
.reset_n(~reset),
.locked(locked),
//outputs
.dprio_address(init_dprio_address),
.dprio_read(init_dprio_read),
.dprio_byteen(init_dprio_byteen),
.dprio_write(init_dprio_write),
.dprio_writedata(init_dprio_writedata),
.atpgmode(init_atpgmode),
.mdio_dis(init_mdio_dis),
.scanen(init_scanen),
.ser_shift_load(init_ser_shift_load),
.dprio_init_done(dprio_init_done));
//address luts, to be reconfigged by the Fitter
//FPLL_1 or 0 address lut
generic_lcell_comb lcell_fpll_0_1 (
.dataa(1'b0),
.combout (fpll_1));
defparam lcell_fpll_0_1.lut_mask = 64'hAAAAAAAAAAAAAAAA;
defparam lcell_fpll_0_1.dont_touch = "on";
defparam lcell_fpll_0_1.family = device_family;
wire dprio_read_combout;
generic_lcell_comb lcell_dprio_read (
.dataa(fpll_1),
.datab(dprio_read),
.datac(1'b0),
.datad(1'b0),
.datae(1'b0),
.dataf(1'b0),
.combout (dprio_read_combout));
defparam lcell_dprio_read.lut_mask = 64'hCCCCCCCCCCCCCCCC;
defparam lcell_dprio_read.dont_touch = "on";
defparam lcell_dprio_read.family = device_family;
//assign reconfig_to_pll signals
assign reconfig_to_pll[0] = dprio_clk;
assign reconfig_to_pll[1] = ~dprio_init_reset;
assign reconfig_to_pll[2] = dprio_write;
assign reconfig_to_pll[3] = dprio_read_combout;
assign reconfig_to_pll[9:4] = dprio_address;
assign reconfig_to_pll[25:10] = dprio_writedata;
assign reconfig_to_pll[27:26] = dprio_byteen;
assign reconfig_to_pll[28] = dprio_ser_shift_load;
assign reconfig_to_pll[29] = dprio_mdio_dis;
assign reconfig_to_pll[30] = phase_en;
assign reconfig_to_pll[31] = up_dn;
assign reconfig_to_pll[36:32] = cnt_sel;
assign reconfig_to_pll[37] = dprio_scanen;
assign reconfig_to_pll[38] = dprio_atpgmode;
//assign reconfig_to_pll[40:37] = clken;
assign reconfig_to_pll[63:39] = 0;
//assign reconfig_from_pll signals
assign dprio_readdata = reconfig_from_pll [15:0];
assign locked = reconfig_from_pll [16];
assign phase_done = reconfig_from_pll [17];
endmodule
module self_reset (input wire mgmt_reset, input wire clk, output wire reset, output wire init_reset);
localparam RESET_COUNTER_VALUE = 3'd2;
localparam INITIAL_WAIT_VALUE = 9'd340;
reg [9:0]counter;
reg local_reset;
reg usr_mode_init_wait;
initial
begin
local_reset = 1'b1;
counter = 0;
usr_mode_init_wait = 0;
end
always @(posedge clk)
begin
if (mgmt_reset)
begin
counter <= 0;
end
else
begin
if (!usr_mode_init_wait)
begin
if (counter == INITIAL_WAIT_VALUE)
begin
local_reset <= 0;
usr_mode_init_wait <= 1'b1;
counter <= 0;
end
else
begin
counter <= counter + 1'b1;
end
end
else
begin
if (counter == RESET_COUNTER_VALUE)
local_reset <= 0;
else
counter <= counter + 1'b1;
end
end
end
assign reset = mgmt_reset | local_reset;
assign init_reset = local_reset;
endmodule
module dprio_mux (
// Inputs from init block
input [ 5:0] init_dprio_address,
input init_dprio_read,
input [ 1:0] init_dprio_byteen,
input init_dprio_write,
input [15:0] init_dprio_writedata,
input init_atpgmode,
input init_mdio_dis,
input init_scanen,
input init_ser_shift_load,
input dprio_init_done,
// Inputs from avmm master
input [ 5:0] avmm_dprio_address,
input avmm_dprio_read,
input [ 1:0] avmm_dprio_byteen,
input avmm_dprio_write,
input [15:0] avmm_dprio_writedata,
input avmm_atpgmode,
input avmm_mdio_dis,
input avmm_scanen,
input avmm_ser_shift_load,
// Outputs to fpll
output [ 5:0] dprio_address,
output dprio_read,
output [ 1:0] dprio_byteen,
output dprio_write,
output [15:0] dprio_writedata,
output atpgmode,
output mdio_dis,
output scanen,
output ser_shift_load
);
assign dprio_address = dprio_init_done ? avmm_dprio_address : init_dprio_address;
assign dprio_read = dprio_init_done ? avmm_dprio_read : init_dprio_read;
assign dprio_byteen = dprio_init_done ? avmm_dprio_byteen : init_dprio_byteen;
assign dprio_write = dprio_init_done ? avmm_dprio_write : init_dprio_write;
assign dprio_writedata = dprio_init_done ? avmm_dprio_writedata : init_dprio_writedata;
assign atpgmode = init_atpgmode;
assign scanen = init_scanen;
assign mdio_dis = init_mdio_dis;
assign ser_shift_load = init_ser_shift_load ;
endmodule
module fpll_dprio_init (
input clk,
input reset_n,
input locked,
output [ 5:0] dprio_address,
output dprio_read,
output [ 1:0] dprio_byteen,
output dprio_write,
output [15:0] dprio_writedata,
output reg atpgmode,
output reg mdio_dis,
output reg scanen,
output reg ser_shift_load,
output reg dprio_init_done
);
reg [1:0] rst_n = 2'b00;
reg [6:0] count = 7'd0;
reg init_done_forever;
// Internal versions of control signals
wire int_mdio_dis;
wire int_ser_shift_load;
wire int_dprio_init_done;
wire int_atpgmode/*synthesis keep*/;
wire int_scanen/*synthesis keep*/;
assign dprio_address = count[6] ? 5'b0 : count[5:0] ;
assign dprio_byteen = 2'b11; // always enabled
assign dprio_write = ~count[6] & reset_n ; // write for first 64 cycles
assign dprio_read = 1'b0;
assign dprio_writedata = 16'd0;
assign int_ser_shift_load = count[6] ? |count[2:1] : 1'b1;
assign int_mdio_dis = count[6] ? ~count[2] : 1'b1;
assign int_dprio_init_done = ~init_done_forever ? (count[6] ? &count[2:0] : 1'b0)
: 1'b1;
assign int_atpgmode = 0;
assign int_scanen = 0;
initial begin
count = 7'd0;
init_done_forever = 0;
mdio_dis = 1'b1;
ser_shift_load = 1'b1;
dprio_init_done = 1'b0;
scanen = 1'b0;
atpgmode = 1'b0;
end
// reset synch.
always @(posedge clk or negedge reset_n)
if(!reset_n) rst_n <= 2'b00;
else rst_n <= {rst_n[0],1'b1};
// counter
always @(posedge clk)
begin
if (!rst_n[1])
init_done_forever <= 1'b0;
else
begin
if (count[6] && &count[1:0])
init_done_forever <= 1'b1;
end
end
always @(posedge clk or negedge rst_n[1])
begin
if(!rst_n[1])
begin
count <= 7'd0;
end
else if(~int_dprio_init_done)
begin
count <= count + 7'd1;
end
else
begin
count <= count;
end
end
// outputs
always @(posedge clk) begin
mdio_dis <= int_mdio_dis;
ser_shift_load <= int_ser_shift_load;
dprio_init_done <= int_dprio_init_done;
atpgmode <= int_atpgmode;
scanen <= int_scanen;
end
endmodule
module dyn_phase_shift
#(
parameter device_family = "Stratix V"
) (
input wire clk,
input wire reset,
input wire phase_done,
input wire pll_start_valid,
input wire dps_changed,
input wire dprio_write_done,
input wire [15:0] usr_num_shifts,
input wire [4:0] usr_cnt_sel,
input wire usr_up_dn,
input wire locked,
//output
output wire dps_done,
output reg phase_en,
output wire up_dn,
output wire dps_changed_valid,
output wire [4:0] cnt_sel);
reg first_phase_shift_d;
reg first_phase_shift_q;
reg [15:0] phase_en_counter;
reg [3:0] dps_current_state;
reg [3:0] dps_next_state;
localparam DPS_START = 4'd0, DPS_WAIT_PHASE_DONE = 4'd1, DPS_DONE = 4'd2, DPS_WAIT_PHASE_EN = 4'd3, DPS_WAIT_DPRIO_WRITING = 4'd4, DPS_CHANGED = 4'd5;
localparam PHASE_EN_WAIT_COUNTER = 5'd1;
reg [15:0] shifts_done_counter;
reg phase_done_final;
wire gnd /*synthesis keep*/;
//fsm
//always block controlling the state regs
always @(posedge clk)
begin
if (reset)
begin
dps_current_state <= DPS_DONE;
end
else
begin
dps_current_state <= dps_next_state;
end
end
//the combinational part. assigning the next state
//this turns on the phase_done_final signal when phase_done does this:
//_____ ______
// |______|
always @(*)
begin
phase_done_final = 0;
first_phase_shift_d = 0;
phase_en = 0;
dps_next_state = DPS_DONE;
case (dps_current_state)
DPS_START:
begin
phase_en = 1'b1;
dps_next_state = DPS_WAIT_PHASE_EN;
end
DPS_WAIT_PHASE_EN:
begin
phase_en = 1'b1;
if (first_phase_shift_q)
begin
first_phase_shift_d = 1'b1;
dps_next_state = DPS_WAIT_PHASE_EN;
end
else
begin
if (phase_en_counter == PHASE_EN_WAIT_COUNTER)
dps_next_state = DPS_WAIT_PHASE_DONE;
else dps_next_state = DPS_WAIT_PHASE_EN;
end
end
DPS_WAIT_PHASE_DONE:
begin
if (!phase_done | !locked)
begin
dps_next_state = DPS_WAIT_PHASE_DONE;
end
else
begin
if ((usr_num_shifts != shifts_done_counter) & (usr_num_shifts != 0))
begin
dps_next_state = DPS_START;
phase_done_final = 1'b1;
end
else
begin
dps_next_state = DPS_DONE;
end
end
end
DPS_DONE:
begin
phase_done_final = 0;
if (dps_changed)
dps_next_state = DPS_CHANGED;
else dps_next_state = DPS_DONE;
end
DPS_CHANGED:
begin
if (pll_start_valid)
dps_next_state = DPS_WAIT_DPRIO_WRITING;
else
dps_next_state = DPS_CHANGED;
end
DPS_WAIT_DPRIO_WRITING:
begin
if (dprio_write_done)
dps_next_state = DPS_START;
else
dps_next_state = DPS_WAIT_DPRIO_WRITING;
end
default: dps_next_state = 4'bxxxx;
endcase
end
always @(posedge clk)
begin
if (dps_current_state == DPS_WAIT_PHASE_DONE)
phase_en_counter <= 0;
else if (dps_current_state == DPS_WAIT_PHASE_EN)
phase_en_counter <= phase_en_counter + 1'b1;
if (reset)
begin
phase_en_counter <= 0;
shifts_done_counter <= 1'b1;
first_phase_shift_q <= 1;
end
else
begin
if (first_phase_shift_d)
first_phase_shift_q <= 0;
if (dps_done)
begin
shifts_done_counter <= 1'b1;
end
else
begin
if (phase_done_final & (dps_next_state!= DPS_DONE))
shifts_done_counter <= shifts_done_counter + 1'b1;
else
shifts_done_counter <= shifts_done_counter;
end
end
end
assign dps_changed_valid = (dps_current_state == DPS_CHANGED);
assign dps_done =(dps_current_state == DPS_DONE) | (dps_current_state == DPS_CHANGED);
assign up_dn = usr_up_dn;
assign gnd = 1'b0;
//cnt select luts (5)
generic_lcell_comb lcell_cnt_sel_0 (
.dataa(usr_cnt_sel[0]),
.datab(usr_cnt_sel[1]),
.datac(usr_cnt_sel[2]),
.datad(usr_cnt_sel[3]),
.datae(usr_cnt_sel[4]),
.dataf(gnd),
.combout (cnt_sel[0]));
defparam lcell_cnt_sel_0.lut_mask = 64'hAAAAAAAAAAAAAAAA;
defparam lcell_cnt_sel_0.dont_touch = "on";
defparam lcell_cnt_sel_0.family = device_family;
generic_lcell_comb lcell_cnt_sel_1 (
.dataa(usr_cnt_sel[0]),
.datab(usr_cnt_sel[1]),
.datac(usr_cnt_sel[2]),
.datad(usr_cnt_sel[3]),
.datae(usr_cnt_sel[4]),
.dataf(gnd),
.combout (cnt_sel[1]));
defparam lcell_cnt_sel_1.lut_mask = 64'hCCCCCCCCCCCCCCCC;
defparam lcell_cnt_sel_1.dont_touch = "on";
defparam lcell_cnt_sel_1.family = device_family;
generic_lcell_comb lcell_cnt_sel_2 (
.dataa(usr_cnt_sel[0]),
.datab(usr_cnt_sel[1]),
.datac(usr_cnt_sel[2]),
.datad(usr_cnt_sel[3]),
.datae(usr_cnt_sel[4]),
.dataf(gnd),
.combout (cnt_sel[2]));
defparam lcell_cnt_sel_2.lut_mask = 64'hF0F0F0F0F0F0F0F0;
defparam lcell_cnt_sel_2.dont_touch = "on";
defparam lcell_cnt_sel_2.family = device_family;
generic_lcell_comb lcell_cnt_sel_3 (
.dataa(usr_cnt_sel[0]),
.datab(usr_cnt_sel[1]),
.datac(usr_cnt_sel[2]),
.datad(usr_cnt_sel[3]),
.datae(usr_cnt_sel[4]),
.dataf(gnd),
.combout (cnt_sel[3]));
defparam lcell_cnt_sel_3.lut_mask = 64'hFF00FF00FF00FF00;
defparam lcell_cnt_sel_3.dont_touch = "on";
defparam lcell_cnt_sel_3.family = device_family;
generic_lcell_comb lcell_cnt_sel_4 (
.dataa(usr_cnt_sel[0]),
.datab(usr_cnt_sel[1]),
.datac(usr_cnt_sel[2]),
.datad(usr_cnt_sel[3]),
.datae(usr_cnt_sel[4]),
.dataf(gnd),
.combout (cnt_sel[4]));
defparam lcell_cnt_sel_4.lut_mask = 64'hFFFF0000FFFF0000;
defparam lcell_cnt_sel_4.dont_touch = "on";
defparam lcell_cnt_sel_4.family = device_family;
endmodule
module generic_lcell_comb
#(
//parameter
parameter family = "Stratix V",
parameter lut_mask = 64'hAAAAAAAAAAAAAAAA,
parameter dont_touch = "on"
) (
input dataa,
input datab,
input datac,
input datad,
input datae,
input dataf,
output combout
);
generate
if (family == "Stratix V")
begin
stratixv_lcell_comb lcell_inst (
.dataa(dataa),
.datab(datab),
.datac(datac),
.datad(datad),
.datae(datae),
.dataf(dataf),
.combout (combout));
defparam lcell_inst.lut_mask = lut_mask;
defparam lcell_inst.dont_touch = dont_touch;
end
else if (family == "Arria V")
begin
arriav_lcell_comb lcell_inst (
.dataa(dataa),
.datab(datab),
.datac(datac),
.datad(datad),
.datae(datae),
.dataf(dataf),
.combout (combout));
defparam lcell_inst.lut_mask = lut_mask;
defparam lcell_inst.dont_touch = dont_touch;
end
else if (family == "Arria V GZ")
begin
arriavgz_lcell_comb lcell_inst (
.dataa(dataa),
.datab(datab),
.datac(datac),
.datad(datad),
.datae(datae),
.dataf(dataf),
.combout (combout));
defparam lcell_inst.lut_mask = lut_mask;
defparam lcell_inst.dont_touch = dont_touch;
end
else if (family == "Cyclone V")
begin
cyclonev_lcell_comb lcell_inst (
.dataa(dataa),
.datab(datab),
.datac(datac),
.datad(datad),
.datae(datae),
.dataf(dataf),
.combout (combout));
defparam lcell_inst.lut_mask = lut_mask;
defparam lcell_inst.dont_touch = dont_touch;
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Teske Virtual System
// Engineer: Lucas Teske
//
// Create Date: 19:14:43 07/04/2013
// Design Name: LVDS 7-to-1 Serializer
// Module Name: lvds_clockgen
// GitHub: https://github.com/racerxdl/LVDS-7-to-1-Serializer
//////////////////////////////////////////////////////////////////////////////////
module lvds_clockgen(
input clk,
output clk35,
output nclk35,
output rstclk,
output dataclock,
output lvdsclk
);
// Clock: 1100011
wire clk_lckd;
wire clkdcm;
wire clo;
DCM_SP #(.CLKIN_PERIOD ("15.625"),
.DESKEW_ADJUST ("0"),
.CLKFX_MULTIPLY (7),
.CLKFX_DIVIDE (2))
dcm_clk (
.CLKIN (clk),
.CLKFB (clo),
.RST (1'b0),
.CLK0 (clkdcm),
.CLKFX (clk35),
.CLKFX180 (nclk35),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLK90 (),
.CLKDV (),
.PSDONE (),
.STATUS (),
.DSSEN (1'b0),
.PSINCDEC (1'b0),
.PSEN (1'b0),
.PSCLK (1'b0),
.LOCKED (clk_lckd)) ;
BUFG clk_bufg (.I(clkdcm), .O(clo) ) ;
assign not_clk_lckd = ~clk_lckd ;
FDP fd_rst_clk (.D(not_clk_lckd), .C(clo), .Q(rst_clk)) ;
// The LVDS Clock is 4:3, if you need 3:4 you can use 7'b0011100
serializer lvdsclkman (
.clk(clo),
.clk35(clk35),
.notclk35(nclk35),
.data(7'b1100011),
.rst(rst_clk),
.out(lvdsclk)
);
assign rstclk = rst_clk;
assign dataclock = clo;
endmodule
|
(** * Basics: Functional Programming in Coq *)
(* This library definition is included here temporarily
for backward compatibility with Coq 8.3.
Please ignore. *)
Definition admit {T: Type} : T. Admitted.
(* ###################################################################### *)
(** * Introduction *)
(** The functional programming style brings programming closer to
mathematics: If a procedure or method has no side effects, then
pretty much all you need to understand about it is how it maps
inputs to outputs -- that is, you can think of its behavior as
just computing a mathematical function. This is one reason for
the word "functional" in "functional programming." This direct
connection between programs and simple mathematical objects
supports both sound informal reasoning and formal proofs of
correctness.
The other sense in which functional programming is "functional" is
that it emphasizes the use of functions (or methods) as
_first-class_ values -- i.e., values that can be passed as
arguments to other functions, returned as results, stored in data
structures, etc. The recognition that functions can be treated as
data in this way enables a host of useful idioms, as we will see.
Other common features of functional languages include _algebraic
data types_ and _pattern matching_, which make it easy to construct
and manipulate rich data structures, and sophisticated
_polymorphic type systems_ that support abstraction and code
reuse. Coq shares all of these features.
*)
(* ###################################################################### *)
(** * Enumerated Types *)
(** One unusual aspect of Coq is that its set of built-in
features is _extremely_ small. For example, instead of providing
the usual palette of atomic data types (booleans, integers,
strings, etc.), Coq offers an extremely powerful mechanism for
defining new data types from scratch -- so powerful that all these
familiar types arise as instances.
Naturally, the Coq distribution comes with an extensive standard
library providing definitions of booleans, numbers, and many
common data structures like lists and hash tables. But there is
nothing magic or primitive about these library definitions: they
are ordinary user code.
To see how this works, let's start with a very simple example. *)
(* ###################################################################### *)
(** ** Days of the Week *)
(** The following declaration tells Coq that we are defining
a new set of data values -- a _type_. *)
Inductive day : Type :=
| monday : day
| tuesday : day
| wednesday : day
| thursday : day
| friday : day
| saturday : day
| sunday : day.
(** The type is called [day], and its members are [monday],
[tuesday], etc. The second through eighth lines of the definition
can be read "[monday] is a [day], [tuesday] is a [day], etc."
Having defined [day], we can write functions that operate on
days. *)
Definition next_weekday (d:day) : day :=
match d with
| monday => tuesday
| tuesday => wednesday
| wednesday => thursday
| thursday => friday
| friday => monday
| saturday => monday
| sunday => monday
end.
(** One thing to note is that the argument and return types of
this function are explicitly declared. Like most functional
programming languages, Coq can often work out these types even if
they are not given explicitly -- i.e., it performs some _type
inference_ -- but we'll always include them to make reading
easier. *)
(** Having defined a function, we should check that it works on
some examples. There are actually three different ways to do this
in Coq. First, we can use the command [Eval compute] to evaluate a
compound expression involving [next_weekday]. *)
Eval compute in (next_weekday friday).
(* ==> monday : day *)
Eval compute in (next_weekday (next_weekday saturday)).
(* ==> tuesday : day *)
(** If you have a computer handy, now would be an excellent
moment to fire up the Coq interpreter under your favorite IDE --
either CoqIde or Proof General -- and try this for yourself. Load
this file ([Basics.v]) from the book's accompanying Coq sources,
find the above example, submit it to Coq, and observe the
result. *)
(** The keyword [compute] tells Coq precisely how to
evaluate the expression we give it. For the moment, [compute] is
the only one we'll need; later on we'll see some alternatives that
are sometimes useful. *)
(** Second, we can record what we _expect_ the result to be in
the form of a Coq example: *)
Example test_next_weekday:
(next_weekday (next_weekday saturday)) = tuesday.
(** This declaration does two things: it makes an
assertion (that the second weekday after [saturday] is [tuesday]),
and it gives the assertion a name that can be used to refer to it
later. *)
(** Having made the assertion, we can also ask Coq to verify it,
like this: *)
Proof. simpl. reflexivity. Qed.
(** The details are not important for now (we'll come back to
them in a bit), but essentially this can be read as "The assertion
we've just made can be proved by observing that both sides of the
equality evaluate to the same thing, after some simplification." *)
(** Third, we can ask Coq to "extract," from a [Definition], a
program in some other, more conventional, programming
language (OCaml, Scheme, or Haskell) with a high-performance
compiler. This facility is very interesting, since it gives us a
way to construct _fully certified_ programs in mainstream
languages. Indeed, this is one of the main uses for which Coq was
developed. We'll come back to this topic in later chapters.
More information can also be found in the Coq'Art book by Bertot
and Casteran, as well as the Coq reference manual. *)
(* ###################################################################### *)
(** ** Booleans *)
(** In a similar way, we can define the type [bool] of booleans,
with members [true] and [false]. *)
Inductive bool : Type :=
| true : bool
| false : bool.
(** Although we are rolling our own booleans here for the sake
of building up everything from scratch, Coq does, of course,
provide a default implementation of the booleans in its standard
library, together with a multitude of useful functions and
lemmas. (Take a look at [Coq.Init.Datatypes] in the Coq library
documentation if you're interested.) Whenever possible, we'll
name our own definitions and theorems so that they exactly
coincide with the ones in the standard library. *)
(** Functions over booleans can be defined in the same way as
above: *)
Definition negb (b:bool) : bool :=
match b with
| true => false
| false => true
end.
Definition andb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => b2
| false => false
end.
Definition orb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => true
| false => b2
end.
(** The last two illustrate the syntax for multi-argument
function definitions. *)
(** The following four "unit tests" constitute a complete
specification -- a truth table -- for the [orb] function: *)
Example test_orb1: (orb true false) = true.
Proof. reflexivity. Qed.
Example test_orb2: (orb false false) = false.
Proof. reflexivity. Qed.
Example test_orb3: (orb false true) = true.
Proof. reflexivity. Qed.
Example test_orb4: (orb true true) = true.
Proof. reflexivity. Qed.
(** (Note that we've dropped the [simpl] in the proofs. It's not
actually needed because [reflexivity] will automatically perform
simplification.) *)
(** _A note on notation_: We use square brackets to delimit
fragments of Coq code in comments in .v files; this convention,
also used by the [coqdoc] documentation tool, keeps them visually
separate from the surrounding text. In the html version of the
files, these pieces of text appear in a [different font]. *)
(** The values [Admitted] and [admit] can be used to fill
a hole in an incomplete definition or proof. We'll use them in the
following exercises. In general, your job in the exercises is
to replace [admit] or [Admitted] with real definitions or proofs. *)
(** **** Exercise: 1 star (nandb) *)
(** Complete the definition of the following function, then make
sure that the [Example] assertions below can each be verified by
Coq. *)
(** This function should return [true] if either or both of
its inputs are [false]. *)
Definition nandb (b1:bool) (b2:bool) : bool :=
(* FILL IN HERE *) admit.
(** Remove "[Admitted.]" and fill in each proof with
"[Proof. reflexivity. Qed.]" *)
Example test_nandb1: (nandb true false) = true.
(* FILL IN HERE *) Admitted.
Example test_nandb2: (nandb false false) = true.
(* FILL IN HERE *) Admitted.
Example test_nandb3: (nandb false true) = true.
(* FILL IN HERE *) Admitted.
Example test_nandb4: (nandb true true) = false.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star (andb3) *)
(** Do the same for the [andb3] function below. This function should
return [true] when all of its inputs are [true], and [false]
otherwise. *)
Definition andb3 (b1:bool) (b2:bool) (b3:bool) : bool :=
(* FILL IN HERE *) admit.
Example test_andb31: (andb3 true true true) = true.
(* FILL IN HERE *) Admitted.
Example test_andb32: (andb3 false true true) = false.
(* FILL IN HERE *) Admitted.
Example test_andb33: (andb3 true false true) = false.
(* FILL IN HERE *) Admitted.
Example test_andb34: (andb3 true true false) = false.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** ** Function Types *)
(** The [Check] command causes Coq to print the type of an
expression. For example, the type of [negb true] is [bool]. *)
Check true.
(* ===> true : bool *)
Check (negb true).
(* ===> negb true : bool *)
(** Functions like [negb] itself are also data values, just like
[true] and [false]. Their types are called _function types_, and
they are written with arrows. *)
Check negb.
(* ===> negb : bool -> bool *)
(** The type of [negb], written [bool -> bool] and pronounced
"[bool] arrow [bool]," can be read, "Given an input of type
[bool], this function produces an output of type [bool]."
Similarly, the type of [andb], written [bool -> bool -> bool], can
be read, "Given two inputs, both of type [bool], this function
produces an output of type [bool]." *)
(* ###################################################################### *)
(** ** Numbers *)
(** _Technical digression_: Coq provides a fairly sophisticated
_module system_, to aid in organizing large developments. In this
course we won't need most of its features, but one is useful: If
we enclose a collection of declarations between [Module X] and
[End X] markers, then, in the remainder of the file after the
[End], these definitions will be referred to by names like [X.foo]
instead of just [foo]. Here, we use this feature to introduce the
definition of the type [nat] in an inner module so that it does
not shadow the one from the standard library. *)
Module Playground1.
(** The types we have defined so far are examples of "enumerated
types": their definitions explicitly enumerate a finite set of
elements. A more interesting way of defining a type is to give a
collection of "inductive rules" describing its elements. For
example, we can define the natural numbers as follows: *)
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
(** The clauses of this definition can be read:
- [O] is a natural number (note that this is the letter "[O]," not
the numeral "[0]").
- [S] is a "constructor" that takes a natural number and yields
another one -- that is, if [n] is a natural number, then [S n]
is too.
Let's look at this in a little more detail.
Every inductively defined set ([day], [nat], [bool], etc.) is
actually a set of _expressions_. The definition of [nat] says how
expressions in the set [nat] can be constructed:
- the expression [O] belongs to the set [nat];
- if [n] is an expression belonging to the set [nat], then [S n]
is also an expression belonging to the set [nat]; and
- expressions formed in these two ways are the only ones belonging
to the set [nat].
The same rules apply for our definitions of [day] and [bool]. The
annotations we used for their constructors are analogous to the
one for the [O] constructor, and indicate that each of those
constructors doesn't take any arguments. *)
(** These three conditions are the precise force of the
[Inductive] declaration. They imply that the expression [O], the
expression [S O], the expression [S (S O)], the expression
[S (S (S O))], and so on all belong to the set [nat], while other
expressions like [true], [andb true false], and [S (S false)] do
not.
We can write simple functions that pattern match on natural
numbers just as we did above -- for example, the predecessor
function: *)
Definition pred (n : nat) : nat :=
match n with
| O => O
| S n' => n'
end.
(** The second branch can be read: "if [n] has the form [S n']
for some [n'], then return [n']." *)
End Playground1.
Definition minustwo (n : nat) : nat :=
match n with
| O => O
| S O => O
| S (S n') => n'
end.
(** Because natural numbers are such a pervasive form of data,
Coq provides a tiny bit of built-in magic for parsing and printing
them: ordinary arabic numerals can be used as an alternative to
the "unary" notation defined by the constructors [S] and [O]. Coq
prints numbers in arabic form by default: *)
Check (S (S (S (S O)))).
Eval simpl in (minustwo 4).
(** The constructor [S] has the type [nat -> nat], just like the
functions [minustwo] and [pred]: *)
Check S.
Check pred.
Check minustwo.
(** These are all things that can be applied to a number to yield a
number. However, there is a fundamental difference: functions
like [pred] and [minustwo] come with _computation rules_ -- e.g.,
the definition of [pred] says that [pred 2] can be simplified to
[1] -- while the definition of [S] has no such behavior attached.
Although it is like a function in the sense that it can be applied
to an argument, it does not _do_ anything at all! *)
(** For most function definitions over numbers, pure pattern
matching is not enough: we also need recursion. For example, to
check that a number [n] is even, we may need to recursively check
whether [n-2] is even. To write such functions, we use the
keyword [Fixpoint]. *)
Fixpoint evenb (n:nat) : bool :=
match n with
| O => true
| S O => false
| S (S n') => evenb n'
end.
(** We can define [oddb] by a similar [Fixpoint] declaration, but here
is a simpler definition that will be a bit easier to work with: *)
Definition oddb (n:nat) : bool := negb (evenb n).
Example test_oddb1: (oddb (S O)) = true.
Proof. reflexivity. Qed.
Example test_oddb2: (oddb (S (S (S (S O))))) = false.
Proof. reflexivity. Qed.
(** Naturally, we can also define multi-argument functions by
recursion. (Once again, we use a module to avoid polluting the
namespace.) *)
Module Playground2.
Fixpoint plus (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus n' m)
end.
(** Adding three to two now gives us five, as we'd expect. *)
Eval simpl in (plus (S (S (S O))) (S (S O))).
(** The simplification that Coq performs to reach this conclusion can
be visualized as follows: *)
(* [plus (S (S (S O))) (S (S O))]
==> [S (plus (S (S O)) (S (S O)))] by the second clause of the [match]
==> [S (S (plus (S O) (S (S O))))] by the second clause of the [match]
==> [S (S (S (plus O (S (S O)))))] by the second clause of the [match]
==> [S (S (S (S (S O))))] by the first clause of the [match]
*)
(** As a notational convenience, if two or more arguments have
the same type, they can be written together. In the following
definition, [(n m : nat)] means just the same as if we had written
[(n : nat) (m : nat)]. *)
Fixpoint mult (n m : nat) : nat :=
match n with
| O => O
| S n' => plus m (mult n' m)
end.
Example test_mult1: (mult 3 3) = 9.
Proof. reflexivity. Qed.
(** You can match two expressions at once by putting a comma
between them: *)
Fixpoint minus (n m:nat) : nat :=
match n, m with
| O , _ => O
| S _ , O => n
| S n', S m' => minus n' m'
end.
(** The _ in the first line is a _wildcard pattern_. Writing _ in a
pattern is the same as writing some variable that doesn't get used
on the right-hand side. This avoids the need to invent a bogus
variable name. *)
End Playground2.
Fixpoint exp (base power : nat) : nat :=
match power with
| O => S O
| S p => mult base (exp base p)
end.
(** **** Exercise: 1 star (factorial) *)
(** Recall the standard factorial function:
<<
factorial(0) = 1
factorial(n) = n * factorial(n-1) (if n>0)
>>
Translate this into Coq. *)
Fixpoint factorial (n:nat) : nat :=
(* FILL IN HERE *) admit.
Example test_factorial1: (factorial 3) = 6.
(* FILL IN HERE *) Admitted.
Example test_factorial2: (factorial 5) = (mult 10 12).
(* FILL IN HERE *) Admitted.
(** [] *)
(** We can make numerical expressions a little easier to read and
write by introducing "notations" for addition, multiplication, and
subtraction. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x - y" := (minus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
Check ((0 + 1) + 1).
(** (The [level], [associativity], and [nat_scope] annotations
control how these notations are treated by Coq's parser. The
details are not important, but interested readers can refer to the
"More on Notation" subsection in the "Optional Material" section at
the end of this chapter.) *)
(** Note that these do not change the definitions we've already
made: they are simply instructions to the Coq parser to accept [x
+ y] in place of [plus x y] and, conversely, to the Coq
pretty-printer to display [plus x y] as [x + y]. *)
(** When we say that Coq comes with nothing built-in, we really
mean it: even equality testing for numbers is a user-defined
operation! *)
(** The [beq_nat] function tests [nat]ural numbers for [eq]uality,
yielding a [b]oolean. Note the use of nested [match]es (we could
also have used a simultaneous match, as we did in [minus].) *)
Fixpoint beq_nat (n m : nat) : bool :=
match n with
| O => match m with
| O => true
| S m' => false
end
| S n' => match m with
| O => false
| S m' => beq_nat n' m'
end
end.
(** Similarly, the [ble_nat] function tests [nat]ural numbers for
[l]ess-or-[e]qual, yielding a [b]oolean. *)
Fixpoint ble_nat (n m : nat) : bool :=
match n with
| O => true
| S n' =>
match m with
| O => false
| S m' => ble_nat n' m'
end
end.
Example test_ble_nat1: (ble_nat 2 2) = true.
Proof. reflexivity. Qed.
Example test_ble_nat2: (ble_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_ble_nat3: (ble_nat 4 2) = false.
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (blt_nat) *)
(** The [blt_nat] function tests [nat]ural numbers for [l]ess-[t]han,
yielding a [b]oolean. Instead of making up a new [Fixpoint] for
this one, define it in terms of a previously defined function.
Note: If you have trouble with the [simpl] tactic, try using
[compute], which is like [simpl] on steroids. However, there is a
simple, elegant solution for which [simpl] suffices. *)
Definition blt_nat (n m : nat) : bool :=
(* FILL IN HERE *) admit.
Example test_blt_nat1: (blt_nat 2 2) = false.
(* FILL IN HERE *) Admitted.
Example test_blt_nat2: (blt_nat 2 4) = true.
(* FILL IN HERE *) Admitted.
Example test_blt_nat3: (blt_nat 4 2) = false.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** * Proof by Simplification *)
(** Now that we've defined a few datatypes and functions, let's
turn to the question of how to state and prove properties of their
behavior. Actually, in a sense, we've already started doing this:
each [Example] in the previous sections makes a precise claim
about the behavior of some function on some particular inputs.
The proofs of these claims were always the same: use [reflexivity]
to check that both sides of the [=] simplify to identical values.
(By the way, it will be useful later to know that
[reflexivity] actually does somewhat more than [simpl] -- for
example, it tries "unfolding" defined terms, replacing them with
their right-hand sides. The reason for this difference is that,
when reflexivity succeeds, the whole goal is finished and we don't
need to look at whatever expanded expressions [reflexivity] has
found; by contrast, [simpl] is used in situations where we may
have to read and understand the new goal, so we would not want it
blindly expanding definitions.)
The same sort of "proof by simplification" can be used to prove
more interesting properties as well. For example, the fact that
[0] is a "neutral element" for [+] on the left can be proved
just by observing that [0 + n] reduces to [n] no matter what
[n] is, a fact that can be read directly off the definition of [plus].*)
Theorem plus_O_n : forall n : nat, 0 + n = n.
Proof.
intros n. reflexivity. Qed.
(** (_Note_: You may notice that the above statement looks
different in the original source file and the final html output. In Coq
files, we write the [forall] universal quantifier using the
"_forall_" reserved identifier. This gets printed as an
upside-down "A", the familiar symbol used in logic.) *)
(** The form of this theorem and proof are almost exactly the
same as the examples above; there are just a few differences.
First, we've used the keyword keyword [Theorem] instead of
[Example]. Indeed, the latter difference is purely a matter of
style; the keywords [Example] and [Theorem] (and a few others,
including [Lemma], [Fact], and [Remark]) mean exactly the same
thing to Coq.
Secondly, we've added the quantifier [forall n:nat], so that our
theorem talks about _all_ natural numbers [n]. In order to prove
theorems of this form, we need to to be able to reason by
_assuming_ the existence of an arbitrary natural number [n]. This
is achieved in the proof by [intros n], which moves the quantifier
from the goal to a "context" of current assumptions. In effect, we
start the proof by saying "OK, suppose [n] is some arbitrary number."
The keywords [intros], [simpl], and [reflexivity] are examples of
_tactics_. A tactic is a command that is used between [Proof] and
[Qed] to tell Coq how it should check the correctness of some
claim we are making. We will see several more tactics in the rest
of this lecture, and yet more in future lectures. *)
(** Step through these proofs in Coq and notice how the goal and
context change. *)
Theorem plus_1_l : forall n:nat, 1 + n = S n.
Proof.
intros n. reflexivity. Qed.
Theorem mult_0_l : forall n:nat, 0 * n = 0.
Proof.
intros n. reflexivity. Qed.
(** The [_l] suffix in the names of these theorems is
pronounced "on the left." *)
(* ###################################################################### *)
(** * Proof by Rewriting *)
(** Here is a slightly more interesting theorem: *)
Theorem plus_id_example : forall n m:nat,
n = m ->
n + n = m + m.
(** Instead of making a completely universal claim about all numbers
[n] and [m], this theorem talks about a more specialized property
that only holds when [n = m]. The arrow symbol is pronounced
"implies."
As before, we need to be able to reason by assuming the existence
of some numbers [n] and [m]. We also need to assume the hypothesis
[n = m]. The [intros] tactic will serve to move all three of these
from the goal into assumptions in the current context.
Since [n] and [m] are arbitrary numbers, we can't just use
simplification to prove this theorem. Instead, we prove it by
observing that, if we are assuming [n = m], then we can replace
[n] with [m] in the goal statement and obtain an equality with the
same expression on both sides. The tactic that tells Coq to
perform this replacement is called [rewrite]. *)
Proof.
intros n m. (* move both quantifiers into the context *)
intros H. (* move the hypothesis into the context *)
rewrite -> H. (* Rewrite the goal using the hypothesis *)
reflexivity. Qed.
(** The first line of the proof moves the universally quantified
variables [n] and [m] into the context. The second moves the
hypothesis [n = m] into the context and gives it the (arbitrary)
name [H]. The third tells Coq to rewrite the current goal ([n + n
= m + m]) by replacing the left side of the equality hypothesis
[H] with the right side.
(The arrow symbol in the [rewrite] has nothing to do with
implication: it tells Coq to apply the rewrite from left to right.
To rewrite from right to left, you can use [rewrite <-]. Try
making this change in the above proof and see what difference it
makes in Coq's behavior.) *)
(** **** Exercise: 1 star (plus_id_exercise) *)
(** Remove "[Admitted.]" and fill in the proof. *)
Theorem plus_id_exercise : forall n m o : nat,
n = m -> m = o -> n + m = m + o.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** As we've seen in earlier examples, the [Admitted] command
tells Coq that we want to skip trying to prove this theorem and
just accept it as a given. This can be useful for developing
longer proofs, since we can state subsidiary facts that we believe
will be useful for making some larger argument, use [Admitted] to
accept them on faith for the moment, and continue thinking about
the larger argument until we are sure it makes sense; then we can
go back and fill in the proofs we skipped. Be careful, though:
every time you say [Admitted] (or [admit]) you are leaving a door
open for total nonsense to enter Coq's nice, rigorous, formally
checked world! *)
(** We can also use the [rewrite] tactic with a previously proved
theorem instead of a hypothesis from the context. *)
Theorem mult_0_plus : forall n m : nat,
(0 + n) * m = n * m.
Proof.
intros n m.
rewrite -> plus_O_n.
reflexivity. Qed.
(** **** Exercise: 2 stars (mult_S_1) *)
Theorem mult_S_1 : forall n m : nat,
m = S n ->
m * (1 + n) = m * m.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** * Proof by Case Analysis *)
(** Of course, not everything can be proved by simple
calculation: In general, unknown, hypothetical values (arbitrary
numbers, booleans, lists, etc.) can block the calculation.
For example, if we try to prove the following fact using the
[simpl] tactic as above, we get stuck. *)
Theorem plus_1_neq_0_firsttry : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n.
simpl. (* does nothing! *)
Abort.
(** The reason for this is that the definitions of both
[beq_nat] and [+] begin by performing a [match] on their first
argument. But here, the first argument to [+] is the unknown
number [n] and the argument to [beq_nat] is the compound
expression [n + 1]; neither can be simplified.
What we need is to be able to consider the possible forms of [n]
separately. If [n] is [O], then we can calculate the final result
of [beq_nat (n + 1) 0] and check that it is, indeed, [false].
And if [n = S n'] for some [n'], then, although we don't know
exactly what number [n + 1] yields, we can calculate that, at
least, it will begin with one [S], and this is enough to calculate
that, again, [beq_nat (n + 1) 0] will yield [false].
The tactic that tells Coq to consider, separately, the cases where
[n = O] and where [n = S n'] is called [destruct]. *)
Theorem plus_1_neq_0 : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n. destruct n as [| n'].
reflexivity.
reflexivity. Qed.
(** The [destruct] generates _two_ subgoals, which we must then
prove, separately, in order to get Coq to accept the theorem as
proved. (No special command is needed for moving from one subgoal
to the other. When the first subgoal has been proved, it just
disappears and we are left with the other "in focus.") In this
proof, each of the subgoals is easily proved by a single use of
[reflexivity].
The annotation "[as [| n']]" is called an _intro pattern_. It
tells Coq what variable names to introduce in each subgoal. In
general, what goes between the square brackets is a _list_ of
lists of names, separated by [|]. Here, the first component is
empty, since the [O] constructor is nullary (it doesn't carry any
data). The second component gives a single name, [n'], since [S]
is a unary constructor.
The [destruct] tactic can be used with any inductively defined
datatype. For example, we use it here to prove that boolean
negation is involutive -- i.e., that negation is its own
inverse. *)
Theorem negb_involutive : forall b : bool,
negb (negb b) = b.
Proof.
intros b. destruct b.
reflexivity.
reflexivity. Qed.
(** Note that the [destruct] here has no [as] clause because
none of the subcases of the [destruct] need to bind any variables,
so there is no need to specify any names. (We could also have
written [as [|]], or [as []].) In fact, we can omit the [as]
clause from _any_ [destruct] and Coq will fill in variable names
automatically. Although this is convenient, it is arguably bad
style, since Coq often makes confusing choices of names when left
to its own devices. *)
(** **** Exercise: 1 star (zero_nbeq_plus_1) *)
Theorem zero_nbeq_plus_1 : forall n : nat,
beq_nat 0 (n + 1) = false.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** * More Exercises *)
(** **** Exercise: 2 stars (boolean functions) *)
(** Use the tactics you have learned so far to prove the following
theorem about boolean functions. *)
Theorem identity_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = x) ->
forall (b : bool), f (f b) = b.
Proof.
(* FILL IN HERE *) Admitted.
(** Now state and prove a theorem [negation_fn_applied_twice] similar
to the previous one but where the second hypothesis says that the
function [f] has the property that [f x = negb x].*)
(* FILL IN HERE *)
(** **** Exercise: 2 stars (andb_eq_orb) *)
(** Prove the following theorem. (You may want to first prove a
subsidiary lemma or two.) *)
Theorem andb_eq_orb :
forall (b c : bool),
(andb b c = orb b c) ->
b = c.
Proof.
(* FILL IN HERE *) Admitted.
(** **** Exercise: 3 stars (binary) *)
(** Consider a different, more efficient representation of natural
numbers using a binary rather than unary system. That is, instead
of saying that each natural number is either zero or the successor
of a natural number, we can say that each binary number is either
- zero,
- twice a binary number, or
- one more than twice a binary number.
(a) First, write an inductive definition of the type [bin]
corresponding to this description of binary numbers.
(Hint: Recall that the definition of [nat] from class,
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
says nothing about what [O] and [S] "mean." It just says "[O] is
in the set called [nat], and if [n] is in the set then so is [S
n]." The interpretation of [O] as zero and [S] as successor/plus
one comes from the way that we _use_ [nat] values, by writing
functions to do things with them, proving things about them, and
so on. Your definition of [bin] should be correspondingly simple;
it is the functions you will write next that will give it
mathematical meaning.)
(b) Next, write an increment function for binary numbers, and a
function to convert binary numbers to unary numbers.
(c) Write some unit tests for your increment and binary-to-unary
functions. Notice that incrementing a binary number and
then converting it to unary should yield the same result as first
converting it to unary and then incrementing.
*)
(* FILL IN HERE *)
(** [] *)
(* ###################################################################### *)
(** * Optional Material *)
(** ** More on Notation *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
(** For each notation-symbol in Coq we can specify its _precedence level_
and its _associativity_. The precedence level n can be specified by the
keywords [at level n] and it is helpful to disambiguate
expressions containing different symbols. The associativity is helpful
to disambiguate expressions containing more occurrences of the same
symbol. For example, the parameters specified above for [+] and [*]
say that the expression [1+2*3*4] is a shorthand for the expression
[(1+((2*3)*4))]. Coq uses precedence levels from 0 to 100, and
_left_, _right_, or _no_ associativity.
Each notation-symbol in Coq is also active in a _notation scope_.
Coq tries to guess what scope you mean, so when you write [S(O*O)]
it guesses [nat_scope], but when you write the cartesian
product (tuple) type [bool*bool] it guesses [type_scope].
Occasionally you have to help it out with percent-notation by
writing [(x*y)%nat], and sometimes in Coq's feedback to you it
will use [%nat] to indicate what scope a notation is in.
Notation scopes also apply to numeral notation (3,4,5, etc.), so you
may sometimes see [0%nat] which means [O], or [0%Z] which means the
Integer zero.
*)
(** ** [Fixpoint]s and Structural Recursion *)
Fixpoint plus' (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus' n' m)
end.
(** When Coq checks this definition, it notes that [plus'] is
"decreasing on 1st argument." What this means is that we are
performing a _structural recursion_ over the argument [n] -- i.e.,
that we make recursive calls only on strictly smaller values of
[n]. This implies that all calls to [plus'] will eventually
terminate. Coq demands that some argument of _every_ [Fixpoint]
definition is "decreasing".
This requirement is a fundamental feature of Coq's design: In
particular, it guarantees that every function that can be defined
in Coq will terminate on all inputs. However, because Coq's
"decreasing analysis" is not very sophisticated, it is sometimes
necessary to write functions in slightly unnatural ways. *)
(** **** Exercise: 2 stars, optional (decreasing) *)
(** To get a concrete sense of this, find a way to write a sensible
[Fixpoint] definition (of a simple function on numbers, say) that
_does_ terminate on all inputs, but that Coq will _not_ accept
because of this restriction. *)
(* FILL IN HERE *)
(** [] *)
(* $Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: fpu_out_dp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////////////
//
// FPU output datapath.
//
///////////////////////////////////////////////////////////////////////////////
module fpu_out_dp (
dest_rdy,
req_thread,
div_exc_out,
d8stg_fdivd,
d8stg_fdivs,
div_sign_out,
div_exp_out,
div_frac_out,
mul_exc_out,
m6stg_fmul_dbl_dst,
m6stg_fmuls,
mul_sign_out,
mul_exp_out,
mul_frac_out,
add_exc_out,
a6stg_fcmpop,
add_cc_out,
add_fcc_out,
a6stg_dbl_dst,
a6stg_sng_dst,
a6stg_long_dst,
a6stg_int_dst,
add_sign_out,
add_exp_out,
add_frac_out,
rclk,
fp_cpx_data_ca,
se,
si,
so
);
input [2:0] dest_rdy; // pipe with result request this cycle
input [1:0] req_thread; // thread ID of result req this cycle
input [4:0] div_exc_out; // divide pipe result- exception flags
input d8stg_fdivd; // divide double- divide stage 8
input d8stg_fdivs; // divide single- divide stage 8
input div_sign_out; // divide sign output
input [10:0] div_exp_out; // divide exponent output
input [51:0] div_frac_out; // divide fraction output
input [4:0] mul_exc_out; // multiply pipe result- exception flags
input m6stg_fmul_dbl_dst; // double precision multiply result
input m6stg_fmuls; // fmuls- multiply 6 stage
input mul_sign_out; // multiply sign output
input [10:0] mul_exp_out; // multiply exponent output
input [51:0] mul_frac_out; // multiply fraction output
input [4:0] add_exc_out; // add pipe result- exception flags
input a6stg_fcmpop; // compare- add 6 stage
input [1:0] add_cc_out; // add pipe result- condition
input [1:0] add_fcc_out; // add pipe input fcc passed through
input a6stg_dbl_dst; // float double result- add 6 stage
input a6stg_sng_dst; // float single result- add 6 stage
input a6stg_long_dst; // 64bit integer result- add 6 stage
input a6stg_int_dst; // 32bit integer result- add 6 stage
input add_sign_out; // add sign output
input [10:0] add_exp_out; // add exponent output
input [63:0] add_frac_out; // add fraction output
input rclk; // global clock
output [144:0] fp_cpx_data_ca; // FPU result to CPX
input se; // scan_enable
input si; // scan in
output so; // scan out
wire [63:0] add_out;
wire [63:0] mul_out;
wire [63:0] div_out;
wire [7:0] fp_cpx_data_ca_84_77_in;
wire [76:0] fp_cpx_data_ca_76_0_in;
wire [7:0] fp_cpx_data_ca_84_77;
wire [76:0] fp_cpx_data_ca_76_0;
wire [144:0] fp_cpx_data_ca;
wire se_l;
assign se_l = ~se;
clken_buf ckbuf_out_dp (
.clk(clk),
.rclk(rclk),
.enb_l(1'b0),
.tmb_l(se_l)
);
///////////////////////////////////////////////////////////////////////////////
//
// Add pipe output.
//
///////////////////////////////////////////////////////////////////////////////
assign add_out[63:0]= ({64{a6stg_dbl_dst}}
& {add_sign_out, add_exp_out[10:0],
add_frac_out[62:11]})
| ({64{a6stg_sng_dst}}
& {add_sign_out, add_exp_out[7:0],
add_frac_out[62:40], 32'b0})
| ({64{a6stg_long_dst}}
& add_frac_out[63:0])
| ({64{a6stg_int_dst}}
& {add_frac_out[63:32], 32'b0});
///////////////////////////////////////////////////////////////////////////////
//
// Multiply output.
//
///////////////////////////////////////////////////////////////////////////////
assign mul_out[63:0]= ({64{m6stg_fmul_dbl_dst}}
& {mul_sign_out, mul_exp_out[10:0],
mul_frac_out[51:0]})
| ({64{m6stg_fmuls}}
& {mul_sign_out, mul_exp_out[7:0],
mul_frac_out[51:29], 32'b0});
///////////////////////////////////////////////////////////////////////////////
//
// Divide output.
//
///////////////////////////////////////////////////////////////////////////////
assign div_out[63:0]= ({64{d8stg_fdivd}}
& {div_sign_out, div_exp_out[10:0],
div_frac_out[51:0]})
| ({64{d8stg_fdivs}}
& {div_sign_out, div_exp_out[7:0],
div_frac_out[51:29], 32'b0});
///////////////////////////////////////////////////////////////////////////////
//
// Choose the output data.
//
// Input to the CPX data (CA) stage.
//
///////////////////////////////////////////////////////////////////////////////
assign fp_cpx_data_ca_84_77_in[7:0]= ({8{(|dest_rdy)}}
& {1'b1, 4'b1000, 1'b0, req_thread[1:0]});
assign fp_cpx_data_ca_76_0_in[76:0]= ({77{dest_rdy[2]}}
& {div_exc_out[4:0], 8'b0, div_out[63:0]})
| ({77{dest_rdy[1]}}
& {mul_exc_out[4:0], 8'b0, mul_out[63:0]})
| ({77{dest_rdy[0]}}
& {add_exc_out[4:0], 2'b0, a6stg_fcmpop,
add_cc_out[1:0], add_fcc_out[1:0], 1'b0,
add_out[63:0]});
dff #(8) i_fp_cpx_data_ca_84_77 (
.din (fp_cpx_data_ca_84_77_in[7:0]),
.clk (clk),
.q (fp_cpx_data_ca_84_77[7:0]),
.se (se),
.si (),
.so ()
);
dff #(77) i_fp_cpx_data_ca_76_0 (
.din (fp_cpx_data_ca_76_0_in[76:0]),
.clk (clk),
.q (fp_cpx_data_ca_76_0[76:0]),
.se (se),
.si (),
.so ()
);
assign fp_cpx_data_ca[144:0]= {fp_cpx_data_ca_84_77[7:3],
3'b0,
fp_cpx_data_ca_84_77[2:0],
57'b0,
fp_cpx_data_ca_76_0[76:0]};
endmodule
|
// // (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_custom_mul_ll(
// this interface matches what hdlgen expects
input logic clock,
input logic resetn,
input logic enable,
input logic [31:0] dataa,
input logic [31:0] datab,
output logic [31:0] result
);
acl_fp_custom_mul_ll_hc_core #(
.HIGH_CAPACITY(0)
)
core(
.clock(clock),
.resetn(resetn),
.enable(enable),
.dataa(dataa),
.datab(datab),
.result(result)
);
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_11_0_pcie_top.v
// Version : 1.11
// Description: Solution wrapper for Virtex7 Hard Block for PCI Express
//
//
//
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module pcie_7x_v1_11_0_pcie_top # (
// PCIE_2_1 params
parameter PIPE_PIPELINE_STAGES = 0, // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
parameter [11:0] AER_BASE_PTR = 12'h140,
parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE",
parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE",
parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
parameter [15:0] AER_CAP_ID = 16'h0001,
parameter AER_CAP_MULTIHEADER = "FALSE",
parameter [11:0] AER_CAP_NEXTPTR = 12'h178,
parameter AER_CAP_ON = "FALSE",
parameter [23:0] AER_CAP_OPTIONAL_ERR_SUPPORT = 24'h000000,
parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE",
parameter [3:0] AER_CAP_VERSION = 4'h1,
parameter ALLOW_X8_GEN2 = "FALSE",
parameter [31:0] BAR0 = 32'hFFFFFF00,
parameter [31:0] BAR1 = 32'hFFFF0000,
parameter [31:0] BAR2 = 32'hFFFF000C,
parameter [31:0] BAR3 = 32'hFFFFFFFF,
parameter [31:0] BAR4 = 32'h00000000,
parameter [31:0] BAR5 = 32'h00000000,
parameter C_DATA_WIDTH = 64,
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1,
parameter KEEP_WIDTH = C_DATA_WIDTH / 8,
parameter [7:0] CAPABILITIES_PTR = 8'h40,
parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000,
parameter [23:0] CLASS_CODE = 24'h000000,
parameter CFG_ECRC_ERR_CPLSTAT = 0,
parameter CMD_INTX_IMPLEMENTED = "TRUE",
parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE",
parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h0,
parameter [6:0] CRM_MODULE_RSTS = 7'h00,
parameter DEV_CAP2_ARI_FORWARDING_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED = "FALSE",
parameter DEV_CAP2_CAS128_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED = "FALSE",
parameter DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED = "FALSE",
parameter DEV_CAP2_LTR_MECHANISM_SUPPORTED = "FALSE",
parameter [1:0] DEV_CAP2_MAX_ENDEND_TLP_PREFIXES = 2'h0,
parameter DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING = "FALSE",
parameter [1:0] DEV_CAP2_TPH_COMPLETER_SUPPORTED = 2'h0,
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE",
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE",
parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0,
parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 0,
parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE",
parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE",
parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2,
parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0,
parameter integer DEV_CAP_RSVD_14_12 = 0,
parameter integer DEV_CAP_RSVD_17_16 = 0,
parameter integer DEV_CAP_RSVD_31_29 = 0,
parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE",
parameter DEV_CONTROL_EXT_TAG_DEFAULT = "FALSE",
parameter DISABLE_ASPM_L1_TIMER = "FALSE",
parameter DISABLE_BAR_FILTERING = "FALSE",
parameter DISABLE_ERR_MSG = "FALSE",
parameter DISABLE_ID_CHECK = "FALSE",
parameter DISABLE_LANE_REVERSAL = "FALSE",
parameter DISABLE_LOCKED_FILTER = "FALSE",
parameter DISABLE_PPM_FILTER = "FALSE",
parameter DISABLE_RX_POISONED_RESP = "FALSE",
parameter DISABLE_RX_TC_FILTER = "FALSE",
parameter DISABLE_SCRAMBLING = "FALSE",
parameter [7:0] DNSTREAM_LINK_NUM = 8'h00,
parameter [11:0] DSN_BASE_PTR = 12'h100,
parameter [15:0] DSN_CAP_ID = 16'h0003,
parameter [11:0] DSN_CAP_NEXTPTR = 12'h10C,
parameter DSN_CAP_ON = "TRUE",
parameter [3:0] DSN_CAP_VERSION = 4'h1,
parameter [10:0] ENABLE_MSG_ROUTE = 11'h000,
parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE",
parameter ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED = "FALSE",
parameter ENTER_RVRY_EI_L0 = "TRUE",
parameter EXIT_LOOPBACK_ON_EI = "TRUE",
parameter [31:0] EXPANSION_ROM = 32'hFFFFF001,
parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F,
parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF,
parameter [7:0] HEADER_TYPE = 8'h00,
parameter [4:0] INFER_EI = 5'h00,
parameter [7:0] INTERRUPT_PIN = 8'h01,
parameter INTERRUPT_STAT_AUTO = "TRUE",
parameter IS_SWITCH = "FALSE",
parameter [9:0] LAST_CONFIG_DWORD = 10'h3FF,
parameter LINK_CAP_ASPM_OPTIONALITY = "TRUE",
parameter integer LINK_CAP_ASPM_SUPPORT = 1,
parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE",
parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE",
parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7,
parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7,
parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE",
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1,
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08,
parameter integer LINK_CAP_RSVD_23 = 0,
parameter integer LINK_CONTROL_RCB = 0,
parameter LINK_CTRL2_DEEMPHASIS = "FALSE",
parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE",
parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h2,
parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE",
parameter [14:0] LL_ACK_TIMEOUT = 15'h0000,
parameter LL_ACK_TIMEOUT_EN = "FALSE",
parameter integer LL_ACK_TIMEOUT_FUNC = 0,
parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000,
parameter LL_REPLAY_TIMEOUT_EN = "FALSE",
parameter integer LL_REPLAY_TIMEOUT_FUNC = 0,
parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'h01,
parameter MPS_FORCE = "FALSE",
parameter [7:0] MSIX_BASE_PTR = 8'h9C,
parameter [7:0] MSIX_CAP_ID = 8'h11,
parameter [7:0] MSIX_CAP_NEXTPTR = 8'h00,
parameter MSIX_CAP_ON = "FALSE",
parameter integer MSIX_CAP_PBA_BIR = 0,
parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h000,
parameter [7:0] MSI_BASE_PTR = 8'h48,
parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE",
parameter [7:0] MSI_CAP_ID = 8'h05,
parameter integer MSI_CAP_MULTIMSGCAP = 0,
parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0,
parameter [7:0] MSI_CAP_NEXTPTR = 8'h60,
parameter MSI_CAP_ON = "FALSE",
parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "TRUE",
parameter integer N_FTS_COMCLK_GEN1 = 255,
parameter integer N_FTS_COMCLK_GEN2 = 255,
parameter integer N_FTS_GEN1 = 255,
parameter integer N_FTS_GEN2 = 255,
parameter [7:0] PCIE_BASE_PTR = 8'h60,
parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10,
parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2,
parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0,
parameter [7:0] PCIE_CAP_NEXTPTR = 8'h9C,
parameter PCIE_CAP_ON = "TRUE",
parameter integer PCIE_CAP_RSVD_15_14 = 0,
parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE",
parameter integer PCIE_REVISION = 2,
parameter integer PL_AUTO_CONFIG = 0,
parameter PL_FAST_TRAIN = "FALSE",
parameter [14:0] PM_ASPML0S_TIMEOUT = 15'h0000,
parameter PM_ASPML0S_TIMEOUT_EN = "FALSE",
parameter integer PM_ASPML0S_TIMEOUT_FUNC = 0,
parameter PM_ASPM_FASTEXIT = "FALSE",
parameter [7:0] PM_BASE_PTR = 8'h40,
parameter integer PM_CAP_AUXCURRENT = 0,
parameter PM_CAP_D1SUPPORT = "TRUE",
parameter PM_CAP_D2SUPPORT = "TRUE",
parameter PM_CAP_DSI = "FALSE",
parameter [7:0] PM_CAP_ID = 8'h01,
parameter [7:0] PM_CAP_NEXTPTR = 8'h48,
parameter PM_CAP_ON = "TRUE",
parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F,
parameter PM_CAP_PME_CLOCK = "FALSE",
parameter integer PM_CAP_RSVD_04 = 0,
parameter integer PM_CAP_VERSION = 3,
parameter PM_CSR_B2B3 = "FALSE",
parameter PM_CSR_BPCCEN = "FALSE",
parameter PM_CSR_NOSOFTRST = "TRUE",
parameter [7:0] PM_DATA0 = 8'h01,
parameter [7:0] PM_DATA1 = 8'h01,
parameter [7:0] PM_DATA2 = 8'h01,
parameter [7:0] PM_DATA3 = 8'h01,
parameter [7:0] PM_DATA4 = 8'h01,
parameter [7:0] PM_DATA5 = 8'h01,
parameter [7:0] PM_DATA6 = 8'h01,
parameter [7:0] PM_DATA7 = 8'h01,
parameter [1:0] PM_DATA_SCALE0 = 2'h1,
parameter [1:0] PM_DATA_SCALE1 = 2'h1,
parameter [1:0] PM_DATA_SCALE2 = 2'h1,
parameter [1:0] PM_DATA_SCALE3 = 2'h1,
parameter [1:0] PM_DATA_SCALE4 = 2'h1,
parameter [1:0] PM_DATA_SCALE5 = 2'h1,
parameter [1:0] PM_DATA_SCALE6 = 2'h1,
parameter [1:0] PM_DATA_SCALE7 = 2'h1,
parameter PM_MF = "FALSE",
parameter [11:0] RBAR_BASE_PTR = 12'h178,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR0 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR1 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR2 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR3 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR4 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR5 = 5'h00,
parameter [15:0] RBAR_CAP_ID = 16'h0015,
parameter [2:0] RBAR_CAP_INDEX0 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX1 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX2 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX3 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX4 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX5 = 3'h0,
parameter [11:0] RBAR_CAP_NEXTPTR = 12'h000,
parameter RBAR_CAP_ON = "FALSE",
parameter [31:0] RBAR_CAP_SUP0 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP1 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP2 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP3 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP4 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP5 = 32'h00000000,
parameter [3:0] RBAR_CAP_VERSION = 4'h1,
parameter [2:0] RBAR_NUM = 3'h1,
parameter integer RECRC_CHK = 0,
parameter RECRC_CHK_TRIM = "FALSE",
parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE",
parameter [1:0] RP_AUTO_SPD = 2'h1,
parameter [4:0] RP_AUTO_SPD_LOOPCNT = 5'h1f,
parameter SELECT_DLL_IF = "FALSE",
parameter SIM_VERSION = "1.0",
parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE",
parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE",
parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE",
parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE",
parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE",
parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE",
parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE",
parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000,
parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE",
parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE",
parameter integer SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0,
parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00,
parameter integer SPARE_BIT0 = 0,
parameter integer SPARE_BIT1 = 0,
parameter integer SPARE_BIT2 = 0,
parameter integer SPARE_BIT3 = 0,
parameter integer SPARE_BIT4 = 0,
parameter integer SPARE_BIT5 = 0,
parameter integer SPARE_BIT6 = 0,
parameter integer SPARE_BIT7 = 0,
parameter integer SPARE_BIT8 = 0,
parameter [7:0] SPARE_BYTE0 = 8'h00,
parameter [7:0] SPARE_BYTE1 = 8'h00,
parameter [7:0] SPARE_BYTE2 = 8'h00,
parameter [7:0] SPARE_BYTE3 = 8'h00,
parameter [31:0] SPARE_WORD0 = 32'h00000000,
parameter [31:0] SPARE_WORD1 = 32'h00000000,
parameter [31:0] SPARE_WORD2 = 32'h00000000,
parameter [31:0] SPARE_WORD3 = 32'h00000000,
parameter SSL_MESSAGE_AUTO = "FALSE",
parameter TECRC_EP_INV = "FALSE",
parameter TL_RBYPASS = "FALSE",
parameter integer TL_RX_RAM_RADDR_LATENCY = 0,
parameter integer TL_RX_RAM_RDATA_LATENCY = 2,
parameter integer TL_RX_RAM_WRITE_LATENCY = 0,
parameter TL_TFC_DISABLE = "FALSE",
parameter TL_TX_CHECKS_DISABLE = "FALSE",
parameter integer TL_TX_RAM_RADDR_LATENCY = 0,
parameter integer TL_TX_RAM_RDATA_LATENCY = 2,
parameter integer TL_TX_RAM_WRITE_LATENCY = 0,
parameter TRN_DW = "FALSE",
parameter TRN_NP_FC = "FALSE",
parameter UPCONFIG_CAPABLE = "TRUE",
parameter UPSTREAM_FACING = "TRUE",
parameter UR_ATOMIC = "TRUE",
parameter UR_CFG1 = "TRUE",
parameter UR_INV_REQ = "TRUE",
parameter UR_PRS_RESPONSE = "TRUE",
parameter USER_CLK2_DIV2 = "FALSE",
parameter integer USER_CLK_FREQ = 3,
parameter USE_RID_PINS = "FALSE",
parameter VC0_CPL_INFINITE = "TRUE",
parameter [12:0] VC0_RX_RAM_LIMIT = 13'h03FF,
parameter integer VC0_TOTAL_CREDITS_CD = 127,
parameter integer VC0_TOTAL_CREDITS_CH = 31,
parameter integer VC0_TOTAL_CREDITS_NPD = 24,
parameter integer VC0_TOTAL_CREDITS_NPH = 12,
parameter integer VC0_TOTAL_CREDITS_PD = 288,
parameter integer VC0_TOTAL_CREDITS_PH = 32,
parameter integer VC0_TX_LASTPACKET = 31,
parameter [11:0] VC_BASE_PTR = 12'h10C,
parameter [15:0] VC_CAP_ID = 16'h0002,
parameter [11:0] VC_CAP_NEXTPTR = 12'h000,
parameter VC_CAP_ON = "FALSE",
parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE",
parameter [3:0] VC_CAP_VERSION = 4'h1,
parameter [11:0] VSEC_BASE_PTR = 12'h128,
parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234,
parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018,
parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1,
parameter [15:0] VSEC_CAP_ID = 16'h000B,
parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE",
parameter [11:0] VSEC_CAP_NEXTPTR = 12'h140,
parameter VSEC_CAP_ON = "FALSE",
parameter [3:0] VSEC_CAP_VERSION = 4'h1
)
(
// wrapper input
// Common
output user_clk_out,
input user_reset,
input user_lnk_up,
output trn_lnk_up,
output user_rst_n,
// Tx
output [5:0] tx_buf_av,
output tx_err_drop,
output tx_cfg_req,
output s_axis_tx_tready,
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep,
input [3:0] s_axis_tx_tuser,
input s_axis_tx_tlast,
input s_axis_tx_tvalid,
input tx_cfg_gnt,
// Rx
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep,
output m_axis_rx_tlast,
output m_axis_rx_tvalid,
input m_axis_rx_tready,
output [21:0] m_axis_rx_tuser,
input rx_np_ok,
input rx_np_req,
// Flow Control
output [11:0] fc_cpld,
output [7:0] fc_cplh,
output [11:0] fc_npd,
output [7:0] fc_nph,
output [11:0] fc_pd,
output [7:0] fc_ph,
input [2:0] fc_sel,
input wire [1:0] pl_directed_link_change,
input wire [1:0] pl_directed_link_width,
input wire pl_directed_link_speed,
input wire pl_directed_link_auton,
input wire pl_upstream_prefer_deemph,
input wire pl_downstream_deemph_source,
input wire pl_directed_ltssm_new_vld,
input wire [5:0] pl_directed_ltssm_new,
input wire pl_directed_ltssm_stall,
input wire cm_rst_n,
input wire func_lvl_rst_n,
input wire pl_transmit_hot_rst,
input wire [31:0] cfg_mgmt_di,
input wire [3:0] cfg_mgmt_byte_en_n,
input wire [9:0] cfg_mgmt_dwaddr,
input wire cfg_mgmt_wr_rw1c_as_rw_n,
input wire cfg_mgmt_wr_readonly_n,
input wire cfg_mgmt_wr_en_n,
input wire cfg_mgmt_rd_en_n,
input wire cfg_err_malformed_n,
input wire cfg_err_cor_n,
input wire cfg_err_ur_n,
input wire cfg_err_ecrc_n,
input wire cfg_err_cpl_timeout_n,
input wire cfg_err_cpl_abort_n,
input wire cfg_err_cpl_unexpect_n,
input wire cfg_err_poisoned_n,
input wire cfg_err_acs_n,
input wire cfg_err_atomic_egress_blocked_n,
input wire cfg_err_mc_blocked_n,
input wire cfg_err_internal_uncor_n,
input wire cfg_err_internal_cor_n,
input wire cfg_err_posted_n,
input wire cfg_err_locked_n,
input wire cfg_err_norecovery_n,
input wire [127:0] cfg_err_aer_headerlog,
input wire [47:0] cfg_err_tlp_cpl_header,
input wire cfg_interrupt_n,
input wire [7:0] cfg_interrupt_di,
input wire cfg_interrupt_assert_n,
input wire cfg_interrupt_stat_n,
input wire [7:0] cfg_ds_bus_number,
input wire [4:0] cfg_ds_device_number,
input wire [2:0] cfg_ds_function_number,
input wire [7:0] cfg_port_number,
input wire cfg_pm_halt_aspm_l0s_n,
input wire cfg_pm_halt_aspm_l1_n,
input wire cfg_pm_force_state_en_n,
input wire [1:0] cfg_pm_force_state,
input wire cfg_pm_wake_n,
input wire cfg_turnoff_ok,
input wire cfg_pm_send_pme_to_n,
input wire [4:0] cfg_pciecap_interrupt_msgnum,
input wire cfg_trn_pending,
input wire [2:0] cfg_force_mps,
input wire cfg_force_common_clock_off,
input wire cfg_force_extended_sync_on,
input wire [63:0] cfg_dsn,
input wire [4:0] cfg_aer_interrupt_msgnum,
input wire [15:0] cfg_dev_id,
input wire [15:0] cfg_vend_id,
input wire [7:0] cfg_rev_id,
input wire [15:0] cfg_subsys_id,
input wire [15:0] cfg_subsys_vend_id,
input wire drp_clk,
input wire drp_en,
input wire drp_we,
input wire [8:0] drp_addr,
input wire [15:0] drp_di,
output wire drp_rdy,
output wire [15:0] drp_do,
input wire [1:0] dbg_mode,
input wire dbg_sub_mode,
input wire [2:0] pl_dbg_mode ,
output wire pl_sel_lnk_rate,
output wire [1:0] pl_sel_lnk_width,
output wire [5:0] pl_ltssm_state,
output wire [1:0] pl_lane_reversal_mode,
output wire pl_phy_lnk_up,
output wire [2:0] pl_tx_pm_state,
output wire [1:0] pl_rx_pm_state,
output wire pl_link_upcfg_cap,
output wire pl_link_gen2_cap,
output wire pl_link_partner_gen2_supported,
output wire [2:0] pl_initial_link_width,
output wire pl_directed_change_done,
output wire pl_received_hot_rst,
output wire lnk_clk_en,
output wire [31:0] cfg_mgmt_do,
output wire cfg_mgmt_rd_wr_done,
output wire cfg_err_aer_headerlog_set,
output wire cfg_err_cpl_rdy,
output wire cfg_interrupt_rdy,
output wire [2:0] cfg_interrupt_mmenable,
output wire cfg_interrupt_msienable,
output wire [7:0] cfg_interrupt_do,
output wire cfg_interrupt_msixenable,
output wire cfg_interrupt_msixfm,
output wire [7:0] cfg_bus_number,
output wire [4:0] cfg_device_number,
output wire [2:0] cfg_function_number,
output wire [15:0] cfg_status,
output wire [15:0] cfg_command,
output wire [15:0] cfg_dstatus,
output wire [15:0] cfg_dcommand,
output wire [15:0] cfg_lstatus,
output wire [15:0] cfg_lcommand,
output wire [15:0] cfg_dcommand2,
output wire cfg_received_func_lvl_rst,
output wire cfg_msg_received,
output wire [15:0] cfg_msg_data,
output wire cfg_msg_received_err_cor,
output wire cfg_msg_received_err_non_fatal,
output wire cfg_msg_received_err_fatal,
output wire cfg_msg_received_assert_int_a,
output wire cfg_msg_received_deassert_int_a,
output wire cfg_msg_received_assert_int_b,
output wire cfg_msg_received_deassert_int_b,
output wire cfg_msg_received_assert_int_c,
output wire cfg_msg_received_deassert_int_c,
output wire cfg_msg_received_assert_int_d,
output wire cfg_msg_received_deassert_int_d,
output wire cfg_msg_received_pm_pme,
output wire cfg_msg_received_pme_to_ack,
output wire cfg_msg_received_pme_to,
output wire cfg_msg_received_setslotpowerlimit,
output wire cfg_msg_received_unlock,
output wire cfg_msg_received_pm_as_nak,
output wire cfg_to_turnoff,
output wire [2:0] cfg_pcie_link_state,
output wire cfg_pm_rcv_as_req_l1_n,
output wire cfg_pm_rcv_enter_l1_n,
output wire cfg_pm_rcv_enter_l23_n,
output wire cfg_pm_rcv_req_ack_n,
output wire [1:0] cfg_pmcsr_powerstate,
output wire cfg_pmcsr_pme_en,
output wire cfg_pmcsr_pme_status,
output wire cfg_transaction,
output wire cfg_transaction_type,
output wire [6:0] cfg_transaction_addr,
output wire cfg_command_io_enable,
output wire cfg_command_mem_enable,
output wire cfg_command_bus_master_enable,
output wire cfg_command_interrupt_disable,
output wire cfg_command_serr_en,
output wire cfg_bridge_serr_en,
output wire cfg_dev_status_corr_err_detected,
output wire cfg_dev_status_non_fatal_err_detected,
output wire cfg_dev_status_fatal_err_detected,
output wire cfg_dev_status_ur_detected,
output wire cfg_dev_control_corr_err_reporting_en,
output wire cfg_dev_control_non_fatal_reporting_en,
output wire cfg_dev_control_fatal_err_reporting_en,
output wire cfg_dev_control_ur_err_reporting_en,
output wire cfg_dev_control_enable_ro,
output wire [2:0] cfg_dev_control_max_payload,
output wire cfg_dev_control_ext_tag_en,
output wire cfg_dev_control_phantom_en,
output wire cfg_dev_control_aux_power_en,
output wire cfg_dev_control_no_snoop_en,
output wire [2:0] cfg_dev_control_max_read_req,
output wire [1:0] cfg_link_status_current_speed,
output wire [3:0] cfg_link_status_negotiated_width,
output wire cfg_link_status_link_training,
output wire cfg_link_status_dll_active,
output wire cfg_link_status_bandwidth_status,
output wire cfg_link_status_auto_bandwidth_status,
output wire [1:0] cfg_link_control_aspm_control,
output wire cfg_link_control_rcb,
output wire cfg_link_control_link_disable,
output wire cfg_link_control_retrain_link,
output wire cfg_link_control_common_clock,
output wire cfg_link_control_extended_sync,
output wire cfg_link_control_clock_pm_en,
output wire cfg_link_control_hw_auto_width_dis,
output wire cfg_link_control_bandwidth_int_en,
output wire cfg_link_control_auto_bandwidth_int_en,
output wire [3:0] cfg_dev_control2_cpl_timeout_val,
output wire cfg_dev_control2_cpl_timeout_dis,
output wire cfg_dev_control2_ari_forward_en,
output wire cfg_dev_control2_atomic_requester_en,
output wire cfg_dev_control2_atomic_egress_block,
output wire cfg_dev_control2_ido_req_en,
output wire cfg_dev_control2_ido_cpl_en,
output wire cfg_dev_control2_ltr_en,
output wire cfg_dev_control2_tlp_prefix_block,
output wire cfg_slot_control_electromech_il_ctl_pulse,
output wire cfg_root_control_syserr_corr_err_en,
output wire cfg_root_control_syserr_non_fatal_err_en,
output wire cfg_root_control_syserr_fatal_err_en,
output wire cfg_root_control_pme_int_en,
output wire cfg_aer_ecrc_check_en,
output wire cfg_aer_ecrc_gen_en,
output wire cfg_aer_rooterr_corr_err_reporting_en,
output wire cfg_aer_rooterr_non_fatal_err_reporting_en,
output wire cfg_aer_rooterr_fatal_err_reporting_en,
output wire cfg_aer_rooterr_corr_err_received,
output wire cfg_aer_rooterr_non_fatal_err_received,
output wire cfg_aer_rooterr_fatal_err_received,
output wire [6:0] cfg_vc_tcvc_map,
output wire [63:0] dbg_vec_a,
output wire [63:0] dbg_vec_b,
output wire [11:0] dbg_vec_c,
output wire dbg_sclr_a,
output wire dbg_sclr_b,
output wire dbg_sclr_c,
output wire dbg_sclr_d,
output wire dbg_sclr_e,
output wire dbg_sclr_f,
output wire dbg_sclr_g,
output wire dbg_sclr_h,
output wire dbg_sclr_i,
output wire dbg_sclr_j,
output wire dbg_sclr_k,
output wire [63:0] trn_rdllp_data,
output wire [1:0] trn_rdllp_src_rdy,
output wire [11:0] pl_dbg_vec,
input phy_rdy_n,
input pipe_clk,
input user_clk,
input user_clk2,
output wire pipe_rx0_polarity_gt,
output wire pipe_rx1_polarity_gt,
output wire pipe_rx2_polarity_gt,
output wire pipe_rx3_polarity_gt,
output wire pipe_rx4_polarity_gt,
output wire pipe_rx5_polarity_gt,
output wire pipe_rx6_polarity_gt,
output wire pipe_rx7_polarity_gt,
output wire pipe_tx_deemph_gt,
output wire [2:0] pipe_tx_margin_gt,
output wire pipe_tx_rate_gt,
output wire pipe_tx_rcvr_det_gt,
output wire [1:0] pipe_tx0_char_is_k_gt,
output wire pipe_tx0_compliance_gt,
output wire [15:0] pipe_tx0_data_gt,
output wire pipe_tx0_elec_idle_gt,
output wire [1:0] pipe_tx0_powerdown_gt,
output wire [1:0] pipe_tx1_char_is_k_gt,
output wire pipe_tx1_compliance_gt,
output wire [15:0] pipe_tx1_data_gt,
output wire pipe_tx1_elec_idle_gt,
output wire [1:0] pipe_tx1_powerdown_gt,
output wire [1:0] pipe_tx2_char_is_k_gt,
output wire pipe_tx2_compliance_gt,
output wire [15:0] pipe_tx2_data_gt,
output wire pipe_tx2_elec_idle_gt,
output wire [1:0] pipe_tx2_powerdown_gt,
output wire [1:0] pipe_tx3_char_is_k_gt,
output wire pipe_tx3_compliance_gt,
output wire [15:0] pipe_tx3_data_gt,
output wire pipe_tx3_elec_idle_gt,
output wire [1:0] pipe_tx3_powerdown_gt,
output wire [1:0] pipe_tx4_char_is_k_gt,
output wire pipe_tx4_compliance_gt,
output wire [15:0] pipe_tx4_data_gt,
output wire pipe_tx4_elec_idle_gt,
output wire [1:0] pipe_tx4_powerdown_gt,
output wire [1:0] pipe_tx5_char_is_k_gt,
output wire pipe_tx5_compliance_gt,
output wire [15:0] pipe_tx5_data_gt,
output wire pipe_tx5_elec_idle_gt,
output wire [1:0] pipe_tx5_powerdown_gt,
output wire [1:0] pipe_tx6_char_is_k_gt,
output wire pipe_tx6_compliance_gt,
output wire [15:0] pipe_tx6_data_gt,
output wire pipe_tx6_elec_idle_gt,
output wire [1:0] pipe_tx6_powerdown_gt,
output wire [1:0] pipe_tx7_char_is_k_gt,
output wire pipe_tx7_compliance_gt,
output wire [15:0] pipe_tx7_data_gt,
output wire pipe_tx7_elec_idle_gt,
output wire [1:0] pipe_tx7_powerdown_gt,
input wire pipe_rx0_chanisaligned_gt,
input wire [1:0] pipe_rx0_char_is_k_gt,
input wire [15:0] pipe_rx0_data_gt,
input wire pipe_rx0_elec_idle_gt,
input wire pipe_rx0_phy_status_gt,
input wire [2:0] pipe_rx0_status_gt,
input wire pipe_rx0_valid_gt,
input wire pipe_rx1_chanisaligned_gt,
input wire [1:0] pipe_rx1_char_is_k_gt,
input wire [15:0] pipe_rx1_data_gt,
input wire pipe_rx1_elec_idle_gt,
input wire pipe_rx1_phy_status_gt,
input wire [2:0] pipe_rx1_status_gt,
input wire pipe_rx1_valid_gt,
input wire pipe_rx2_chanisaligned_gt,
input wire [1:0] pipe_rx2_char_is_k_gt,
input wire [15:0] pipe_rx2_data_gt,
input wire pipe_rx2_elec_idle_gt,
input wire pipe_rx2_phy_status_gt,
input wire [2:0] pipe_rx2_status_gt,
input wire pipe_rx2_valid_gt,
input wire pipe_rx3_chanisaligned_gt,
input wire [1:0] pipe_rx3_char_is_k_gt,
input wire [15:0] pipe_rx3_data_gt,
input wire pipe_rx3_elec_idle_gt,
input wire pipe_rx3_phy_status_gt,
input wire [2:0] pipe_rx3_status_gt,
input wire pipe_rx3_valid_gt,
input wire pipe_rx4_chanisaligned_gt,
input wire [1:0] pipe_rx4_char_is_k_gt,
input wire [15:0] pipe_rx4_data_gt,
input wire pipe_rx4_elec_idle_gt,
input wire pipe_rx4_phy_status_gt,
input wire [2:0] pipe_rx4_status_gt,
input wire pipe_rx4_valid_gt,
input wire pipe_rx5_chanisaligned_gt,
input wire [1:0] pipe_rx5_char_is_k_gt,
input wire [15:0] pipe_rx5_data_gt,
input wire pipe_rx5_elec_idle_gt,
input wire pipe_rx5_phy_status_gt,
input wire [2:0] pipe_rx5_status_gt,
input wire pipe_rx5_valid_gt,
input wire pipe_rx6_chanisaligned_gt,
input wire [1:0] pipe_rx6_char_is_k_gt,
input wire [15:0] pipe_rx6_data_gt,
input wire pipe_rx6_elec_idle_gt,
input wire pipe_rx6_phy_status_gt,
input wire [2:0] pipe_rx6_status_gt,
input wire pipe_rx6_valid_gt,
input wire pipe_rx7_chanisaligned_gt,
input wire [1:0] pipe_rx7_char_is_k_gt,
input wire [15:0] pipe_rx7_data_gt,
input wire pipe_rx7_elec_idle_gt,
input wire pipe_rx7_phy_status_gt,
input wire [2:0] pipe_rx7_status_gt,
input wire pipe_rx7_valid_gt
);
//wire declaration
// TRN Interface
wire [C_DATA_WIDTH-1:0] trn_td;
wire [REM_WIDTH-1:0] trn_trem;
wire trn_tsof;
wire trn_teof;
wire trn_tsrc_rdy;
wire trn_tsrc_dsc;
wire trn_terrfwd;
wire trn_tecrc_gen;
wire trn_tstr;
wire trn_tcfg_gnt;
wire [C_DATA_WIDTH-1:0] trn_rd;
wire [REM_WIDTH-1:0] trn_rrem;
wire trn_rdst_rdy;
wire trn_rsof;
wire trn_reof;
wire trn_rsrc_rdy;
wire trn_rsrc_dsc;
wire trn_rerrfwd;
wire [7:0] trn_rbar_hit;
wire sys_reset_n_d;
wire [1:0] pipe_rx0_char_is_k;
wire [1:0] pipe_rx1_char_is_k;
wire [1:0] pipe_rx2_char_is_k;
wire [1:0] pipe_rx3_char_is_k;
wire [1:0] pipe_rx4_char_is_k;
wire [1:0] pipe_rx5_char_is_k;
wire [1:0] pipe_rx6_char_is_k;
wire [1:0] pipe_rx7_char_is_k;
wire pipe_rx0_valid;
wire pipe_rx1_valid;
wire pipe_rx2_valid;
wire pipe_rx3_valid;
wire pipe_rx4_valid;
wire pipe_rx5_valid;
wire pipe_rx6_valid;
wire pipe_rx7_valid;
wire [15:0] pipe_rx0_data;
wire [15:0] pipe_rx1_data;
wire [15:0] pipe_rx2_data;
wire [15:0] pipe_rx3_data;
wire [15:0] pipe_rx4_data;
wire [15:0] pipe_rx5_data;
wire [15:0] pipe_rx6_data;
wire [15:0] pipe_rx7_data;
wire pipe_rx0_chanisaligned;
wire pipe_rx1_chanisaligned;
wire pipe_rx2_chanisaligned;
wire pipe_rx3_chanisaligned;
wire pipe_rx4_chanisaligned;
wire pipe_rx5_chanisaligned;
wire pipe_rx6_chanisaligned;
wire pipe_rx7_chanisaligned;
wire [2:0] pipe_rx0_status;
wire [2:0] pipe_rx1_status;
wire [2:0] pipe_rx2_status;
wire [2:0] pipe_rx3_status;
wire [2:0] pipe_rx4_status;
wire [2:0] pipe_rx5_status;
wire [2:0] pipe_rx6_status;
wire [2:0] pipe_rx7_status;
wire pipe_rx0_phy_status;
wire pipe_rx1_phy_status;
wire pipe_rx2_phy_status;
wire pipe_rx3_phy_status;
wire pipe_rx4_phy_status;
wire pipe_rx5_phy_status;
wire pipe_rx6_phy_status;
wire pipe_rx7_phy_status;
wire pipe_rx0_elec_idle;
wire pipe_rx1_elec_idle;
wire pipe_rx2_elec_idle;
wire pipe_rx3_elec_idle;
wire pipe_rx4_elec_idle;
wire pipe_rx5_elec_idle;
wire pipe_rx6_elec_idle;
wire pipe_rx7_elec_idle;
wire pipe_tx_reset;
wire pipe_tx_rate;
wire pipe_tx_deemph;
wire [2:0] pipe_tx_margin;
wire pipe_rx0_polarity;
wire pipe_rx1_polarity;
wire pipe_rx2_polarity;
wire pipe_rx3_polarity;
wire pipe_rx4_polarity;
wire pipe_rx5_polarity;
wire pipe_rx6_polarity;
wire pipe_rx7_polarity;
wire pipe_tx0_compliance;
wire pipe_tx1_compliance;
wire pipe_tx2_compliance;
wire pipe_tx3_compliance;
wire pipe_tx4_compliance;
wire pipe_tx5_compliance;
wire pipe_tx6_compliance;
wire pipe_tx7_compliance;
wire [1:0] pipe_tx0_char_is_k;
wire [1:0] pipe_tx1_char_is_k;
wire [1:0] pipe_tx2_char_is_k;
wire [1:0] pipe_tx3_char_is_k;
wire [1:0] pipe_tx4_char_is_k;
wire [1:0] pipe_tx5_char_is_k;
wire [1:0] pipe_tx6_char_is_k;
wire [1:0] pipe_tx7_char_is_k;
wire [15:0] pipe_tx0_data;
wire [15:0] pipe_tx1_data;
wire [15:0] pipe_tx2_data;
wire [15:0] pipe_tx3_data;
wire [15:0] pipe_tx4_data;
wire [15:0] pipe_tx5_data;
wire [15:0] pipe_tx6_data;
wire [15:0] pipe_tx7_data;
wire pipe_tx0_elec_idle;
wire pipe_tx1_elec_idle;
wire pipe_tx2_elec_idle;
wire pipe_tx3_elec_idle;
wire pipe_tx4_elec_idle;
wire pipe_tx5_elec_idle;
wire pipe_tx6_elec_idle;
wire pipe_tx7_elec_idle;
wire [1:0] pipe_tx0_powerdown;
wire [1:0] pipe_tx1_powerdown;
wire [1:0] pipe_tx2_powerdown;
wire [1:0] pipe_tx3_powerdown;
wire [1:0] pipe_tx4_powerdown;
wire [1:0] pipe_tx5_powerdown;
wire [1:0] pipe_tx6_powerdown;
wire [1:0] pipe_tx7_powerdown;
wire cfg_received_func_lvl_rst_n;
wire cfg_err_cpl_rdy_n;
wire cfg_interrupt_rdy_n;
reg [7:0] cfg_bus_number_d;
reg [4:0] cfg_device_number_d;
reg [2:0] cfg_function_number_d;
wire cfg_mgmt_rd_wr_done_n;
wire pl_phy_lnk_up_n;
wire cfg_err_aer_headerlog_set_n;
assign cfg_received_func_lvl_rst = ~cfg_received_func_lvl_rst_n;
assign cfg_err_cpl_rdy = ~cfg_err_cpl_rdy_n;
assign cfg_interrupt_rdy = ~cfg_interrupt_rdy_n;
assign cfg_mgmt_rd_wr_done = ~cfg_mgmt_rd_wr_done_n;
assign pl_phy_lnk_up = ~pl_phy_lnk_up_n;
assign cfg_err_aer_headerlog_set = ~cfg_err_aer_headerlog_set_n;
assign cfg_to_turnoff = cfg_msg_received_pme_to;
assign cfg_status = {16'b0};
assign cfg_command = {5'b0,
cfg_command_interrupt_disable,
1'b0,
cfg_command_serr_en,
5'b0,
cfg_command_bus_master_enable,
cfg_command_mem_enable,
cfg_command_io_enable};
assign cfg_dstatus = {10'h0,
cfg_trn_pending,
1'b0,
cfg_dev_status_ur_detected,
cfg_dev_status_fatal_err_detected,
cfg_dev_status_non_fatal_err_detected,
cfg_dev_status_corr_err_detected};
assign cfg_dcommand = {1'b0,
cfg_dev_control_max_read_req,
cfg_dev_control_no_snoop_en,
cfg_dev_control_aux_power_en,
cfg_dev_control_phantom_en,
cfg_dev_control_ext_tag_en,
cfg_dev_control_max_payload,
cfg_dev_control_enable_ro,
cfg_dev_control_ur_err_reporting_en,
cfg_dev_control_fatal_err_reporting_en,
cfg_dev_control_non_fatal_reporting_en,
cfg_dev_control_corr_err_reporting_en };
assign cfg_lstatus = {cfg_link_status_auto_bandwidth_status,
cfg_link_status_bandwidth_status,
cfg_link_status_dll_active,
(LINK_STATUS_SLOT_CLOCK_CONFIG == "TRUE") ? 1'b1 : 1'b0,
cfg_link_status_link_training,
1'b0,
{2'b00, cfg_link_status_negotiated_width},
{2'b00, cfg_link_status_current_speed} };
assign cfg_lcommand = {4'b0,
cfg_link_control_auto_bandwidth_int_en,
cfg_link_control_bandwidth_int_en,
cfg_link_control_hw_auto_width_dis,
cfg_link_control_clock_pm_en,
cfg_link_control_extended_sync,
cfg_link_control_common_clock,
cfg_link_control_retrain_link,
cfg_link_control_link_disable,
cfg_link_control_rcb,
1'b0,
cfg_link_control_aspm_control};
assign cfg_bus_number = cfg_bus_number_d;
assign cfg_device_number = cfg_device_number_d;
assign cfg_function_number = cfg_function_number_d;
assign cfg_dcommand2 = {4'b0,
cfg_dev_control2_tlp_prefix_block,
cfg_dev_control2_ltr_en,
cfg_dev_control2_ido_cpl_en,
cfg_dev_control2_ido_req_en,
cfg_dev_control2_atomic_egress_block,
cfg_dev_control2_atomic_requester_en,
cfg_dev_control2_ari_forward_en,
cfg_dev_control2_cpl_timeout_dis,
cfg_dev_control2_cpl_timeout_val};
// Capture Bus/Device/Function number
always @(posedge user_clk_out) begin
if (~user_lnk_up)
begin
cfg_bus_number_d <= 8'b0;
end // if (~user_lnk_up)
else if (~cfg_msg_received)
begin
cfg_bus_number_d <= cfg_msg_data[15:8];
end // if (~cfg_msg_received)
end
always @(posedge user_clk_out) begin
if (~user_lnk_up)
begin
cfg_device_number_d <= 5'b0;
end // if (~user_lnk_up)
else if (~cfg_msg_received)
begin
cfg_device_number_d <= cfg_msg_data[7:3];
end // if (~cfg_msg_received)
end
always @(posedge user_clk_out) begin
if (~user_lnk_up)
begin
cfg_function_number_d <= 3'b0;
end // if (~user_lnk_up)
else if (~cfg_msg_received)
begin
cfg_function_number_d <= cfg_msg_data[2:0];
end // if (~cfg_msg_received)
end
pcie_7x_v1_11_0_axi_basic_top #(
.C_DATA_WIDTH (C_DATA_WIDTH), // RX/TX interface data width
.C_FAMILY ("X7"), // Targeted FPGA family
.C_ROOT_PORT ("FALSE"), // PCIe block is in root port mode
.C_PM_PRIORITY ("FALSE") // Disable TX packet boundary thrtl
) axi_basic_top (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
.s_axis_tx_tdata (s_axis_tx_tdata), // input
.s_axis_tx_tvalid (s_axis_tx_tvalid), // input
.s_axis_tx_tready (s_axis_tx_tready), // output
.s_axis_tx_tkeep (s_axis_tx_tkeep), // input
.s_axis_tx_tlast (s_axis_tx_tlast), // input
.s_axis_tx_tuser (s_axis_tx_tuser), // input
// AXI RX
//-----------
.m_axis_rx_tdata (m_axis_rx_tdata), // output
.m_axis_rx_tvalid (m_axis_rx_tvalid), // output
.m_axis_rx_tready (m_axis_rx_tready), // input
.m_axis_rx_tkeep (m_axis_rx_tkeep), // output
.m_axis_rx_tlast (m_axis_rx_tlast), // output
.m_axis_rx_tuser (m_axis_rx_tuser), // output
// User Misc.
//-----------
.user_turnoff_ok (cfg_turnoff_ok), // input
.user_tcfg_gnt (tx_cfg_gnt), // input
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
.trn_td (trn_td), // output
.trn_tsof (trn_tsof), // output
.trn_teof (trn_teof), // output
.trn_tsrc_rdy (trn_tsrc_rdy), // output
.trn_tdst_rdy (trn_tdst_rdy), // input
.trn_tsrc_dsc (trn_tsrc_dsc), // output
.trn_trem (trn_trem), // output
.trn_terrfwd (trn_terrfwd), // output
.trn_tstr (trn_tstr), // output
.trn_tbuf_av (tx_buf_av), // input
.trn_tecrc_gen (trn_tecrc_gen), // output
// TRN RX
//-----------
.trn_rd (trn_rd), // input
.trn_rsof (trn_rsof), // input
.trn_reof (trn_reof), // input
.trn_rsrc_rdy (trn_rsrc_rdy), // input
.trn_rdst_rdy (trn_rdst_rdy), // output
.trn_rsrc_dsc (trn_rsrc_dsc), // input
.trn_rrem (trn_rrem), // input
.trn_rerrfwd (trn_rerrfwd), // input
.trn_rbar_hit (trn_rbar_hit[6:0]), // input
.trn_recrc_err (trn_recrc_err), // input
// TRN Misc.
//-----------
.trn_tcfg_req ( tx_cfg_req ), // input
.trn_tcfg_gnt ( trn_tcfg_gnt), // output
.trn_lnk_up ( user_lnk_up), // input
// Fuji3/Virtex6 PM
//-----------
.cfg_pcie_link_state (cfg_pcie_link_state), // input
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to (1'b0), // input NOT USED FOR EP
.cfg_pmcsr_powerstate (cfg_pmcsr_powerstate), // input
.trn_rdllp_data (32'b0), // input - Not used in 7-series
.trn_rdllp_src_rdy (1'b0), // input -- Not used in 7-series
// Power Mgmt for S6/V6
//-----------
.cfg_to_turnoff (cfg_to_turnoff), // input
.cfg_turnoff_ok (cfg_turnoff_ok_w), // output
// System
//-----------
.user_clk (user_clk_out), // input
.user_rst (user_reset), // input
.np_counter () // output
);
//-------------------------------------------------------
// PCI Express Pipe Wrapper
//-------------------------------------------------------
pcie_7x_v1_11_0_pcie_7x # (
.AER_BASE_PTR ( AER_BASE_PTR ),
.AER_CAP_ECRC_CHECK_CAPABLE ( AER_CAP_ECRC_CHECK_CAPABLE ),
.AER_CAP_ECRC_GEN_CAPABLE( AER_CAP_ECRC_GEN_CAPABLE ),
.AER_CAP_ID ( AER_CAP_ID ),
.AER_CAP_MULTIHEADER ( AER_CAP_MULTIHEADER ),
.AER_CAP_NEXTPTR ( AER_CAP_NEXTPTR ),
.AER_CAP_ON ( AER_CAP_ON ),
.AER_CAP_OPTIONAL_ERR_SUPPORT ( AER_CAP_OPTIONAL_ERR_SUPPORT ),
.AER_CAP_PERMIT_ROOTERR_UPDATE ( AER_CAP_PERMIT_ROOTERR_UPDATE ),
.AER_CAP_VERSION ( AER_CAP_VERSION ),
.ALLOW_X8_GEN2 (ALLOW_X8_GEN2),
.BAR0 ( BAR0 ),
.BAR1 ( BAR1 ),
.BAR2 ( BAR2 ),
.BAR3 ( BAR3 ),
.BAR4 ( BAR4 ),
.BAR5 ( BAR5 ),
.C_DATA_WIDTH ( C_DATA_WIDTH ),
.CAPABILITIES_PTR( CAPABILITIES_PTR ),
.CFG_ECRC_ERR_CPLSTAT ( CFG_ECRC_ERR_CPLSTAT ),
.CARDBUS_CIS_POINTER ( CARDBUS_CIS_POINTER ),
.CLASS_CODE ( CLASS_CODE ),
.CMD_INTX_IMPLEMENTED ( CMD_INTX_IMPLEMENTED ),
.CPL_TIMEOUT_DISABLE_SUPPORTED ( CPL_TIMEOUT_DISABLE_SUPPORTED ),
.CPL_TIMEOUT_RANGES_SUPPORTED ( CPL_TIMEOUT_RANGES_SUPPORTED ),
.CRM_MODULE_RSTS (CRM_MODULE_RSTS),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ),
.DEV_CAP_ENDPOINT_L0S_LATENCY ( DEV_CAP_ENDPOINT_L0S_LATENCY ),
.DEV_CAP_ENDPOINT_L1_LATENCY ( DEV_CAP_ENDPOINT_L1_LATENCY ),
.DEV_CAP_EXT_TAG_SUPPORTED ( DEV_CAP_EXT_TAG_SUPPORTED ),
.DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ( DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ),
.DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ),
.DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ( DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ),
.DEV_CAP_ROLE_BASED_ERROR( DEV_CAP_ROLE_BASED_ERROR ),
.DEV_CAP_RSVD_14_12 ( DEV_CAP_RSVD_14_12 ),
.DEV_CAP_RSVD_17_16 ( DEV_CAP_RSVD_17_16 ),
.DEV_CAP_RSVD_31_29 ( DEV_CAP_RSVD_31_29 ),
.DEV_CONTROL_AUX_POWER_SUPPORTED ( DEV_CONTROL_AUX_POWER_SUPPORTED ),
.DEV_CONTROL_EXT_TAG_DEFAULT ( DEV_CONTROL_EXT_TAG_DEFAULT ),
.DISABLE_ASPM_L1_TIMER ( DISABLE_ASPM_L1_TIMER ),
.DISABLE_BAR_FILTERING ( DISABLE_BAR_FILTERING ),
.DISABLE_ID_CHECK( DISABLE_ID_CHECK ),
.DISABLE_LANE_REVERSAL ( DISABLE_LANE_REVERSAL ),
.DISABLE_RX_POISONED_RESP (DISABLE_RX_POISONED_RESP),
.DISABLE_RX_TC_FILTER ( DISABLE_RX_TC_FILTER ),
.DISABLE_SCRAMBLING ( DISABLE_SCRAMBLING ),
.DNSTREAM_LINK_NUM ( DNSTREAM_LINK_NUM ),
.DSN_BASE_PTR ( DSN_BASE_PTR ),
.DSN_CAP_ID ( DSN_CAP_ID ),
.DSN_CAP_NEXTPTR ( DSN_CAP_NEXTPTR ),
.DSN_CAP_ON ( DSN_CAP_ON ),
.DSN_CAP_VERSION ( DSN_CAP_VERSION ),
.DEV_CAP2_ARI_FORWARDING_SUPPORTED(DEV_CAP2_ARI_FORWARDING_SUPPORTED),
.DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED (DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED),
.DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED (DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED),
.DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED (DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED),
.DEV_CAP2_CAS128_COMPLETER_SUPPORTED (DEV_CAP2_CAS128_COMPLETER_SUPPORTED),
.DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED (DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED),
.DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED (DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED),
.DEV_CAP2_LTR_MECHANISM_SUPPORTED (DEV_CAP2_LTR_MECHANISM_SUPPORTED),
.DEV_CAP2_MAX_ENDEND_TLP_PREFIXES (DEV_CAP2_MAX_ENDEND_TLP_PREFIXES),
.DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING (DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING),
.DEV_CAP2_TPH_COMPLETER_SUPPORTED (DEV_CAP2_TPH_COMPLETER_SUPPORTED),
.DISABLE_ERR_MSG (DISABLE_ERR_MSG),
.DISABLE_LOCKED_FILTER (DISABLE_LOCKED_FILTER),
.DISABLE_PPM_FILTER (DISABLE_PPM_FILTER),
.ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED (ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED),
.ENABLE_MSG_ROUTE( ENABLE_MSG_ROUTE ),
.ENABLE_RX_TD_ECRC_TRIM ( ENABLE_RX_TD_ECRC_TRIM ),
.ENTER_RVRY_EI_L0( ENTER_RVRY_EI_L0 ),
.EXIT_LOOPBACK_ON_EI (EXIT_LOOPBACK_ON_EI),
.EXPANSION_ROM ( EXPANSION_ROM ),
.EXT_CFG_CAP_PTR ( EXT_CFG_CAP_PTR ),
.EXT_CFG_XP_CAP_PTR ( EXT_CFG_XP_CAP_PTR ),
.HEADER_TYPE ( HEADER_TYPE ),
.INFER_EI( INFER_EI ),
.INTERRUPT_PIN ( INTERRUPT_PIN ),
.INTERRUPT_STAT_AUTO (INTERRUPT_STAT_AUTO),
.IS_SWITCH ( IS_SWITCH ),
.LAST_CONFIG_DWORD ( LAST_CONFIG_DWORD ),
.LINK_CAP_ASPM_OPTIONALITY ( LINK_CAP_ASPM_OPTIONALITY ),
.LINK_CAP_ASPM_SUPPORT ( LINK_CAP_ASPM_SUPPORT ),
.LINK_CAP_CLOCK_POWER_MANAGEMENT ( LINK_CAP_CLOCK_POWER_MANAGEMENT ),
.LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ( LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_GEN2 ),
.LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP (LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP),
.LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.LINK_CAP_RSVD_23( LINK_CAP_RSVD_23 ),
.LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ( LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ),
.LINK_CONTROL_RCB( LINK_CONTROL_RCB ),
.LINK_CTRL2_DEEMPHASIS ( LINK_CTRL2_DEEMPHASIS ),
.LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ( LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ),
.LINK_CTRL2_TARGET_LINK_SPEED ( LINK_CTRL2_TARGET_LINK_SPEED ),
.LINK_STATUS_SLOT_CLOCK_CONFIG ( LINK_STATUS_SLOT_CLOCK_CONFIG ),
.LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ),
.LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ),
.LL_ACK_TIMEOUT_FUNC ( LL_ACK_TIMEOUT_FUNC ),
.LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ),
.LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ),
.LL_REPLAY_TIMEOUT_FUNC ( LL_REPLAY_TIMEOUT_FUNC ),
.LTSSM_MAX_LINK_WIDTH ( LTSSM_MAX_LINK_WIDTH ),
.MPS_FORCE (MPS_FORCE),
.MSI_BASE_PTR ( MSI_BASE_PTR ),
.MSI_CAP_ID ( MSI_CAP_ID ),
.MSI_CAP_MULTIMSGCAP ( MSI_CAP_MULTIMSGCAP ),
.MSI_CAP_MULTIMSG_EXTENSION ( MSI_CAP_MULTIMSG_EXTENSION ),
.MSI_CAP_NEXTPTR ( MSI_CAP_NEXTPTR ),
.MSI_CAP_ON ( MSI_CAP_ON ),
.MSI_CAP_PER_VECTOR_MASKING_CAPABLE ( MSI_CAP_PER_VECTOR_MASKING_CAPABLE ),
.MSI_CAP_64_BIT_ADDR_CAPABLE ( MSI_CAP_64_BIT_ADDR_CAPABLE ),
.MSIX_BASE_PTR ( MSIX_BASE_PTR ),
.MSIX_CAP_ID ( MSIX_CAP_ID ),
.MSIX_CAP_NEXTPTR( MSIX_CAP_NEXTPTR ),
.MSIX_CAP_ON ( MSIX_CAP_ON ),
.MSIX_CAP_PBA_BIR( MSIX_CAP_PBA_BIR ),
.MSIX_CAP_PBA_OFFSET ( MSIX_CAP_PBA_OFFSET ),
.MSIX_CAP_TABLE_BIR ( MSIX_CAP_TABLE_BIR ),
.MSIX_CAP_TABLE_OFFSET ( MSIX_CAP_TABLE_OFFSET ),
.MSIX_CAP_TABLE_SIZE ( MSIX_CAP_TABLE_SIZE ),
.N_FTS_COMCLK_GEN1 ( N_FTS_COMCLK_GEN1 ),
.N_FTS_COMCLK_GEN2 ( N_FTS_COMCLK_GEN2 ),
.N_FTS_GEN1 ( N_FTS_GEN1 ),
.N_FTS_GEN2 ( N_FTS_GEN2 ),
.PCIE_BASE_PTR ( PCIE_BASE_PTR ),
.PCIE_CAP_CAPABILITY_ID ( PCIE_CAP_CAPABILITY_ID ),
.PCIE_CAP_CAPABILITY_VERSION ( PCIE_CAP_CAPABILITY_VERSION ),
.PCIE_CAP_DEVICE_PORT_TYPE ( PCIE_CAP_DEVICE_PORT_TYPE ),
.PCIE_CAP_NEXTPTR( PCIE_CAP_NEXTPTR ),
.PCIE_CAP_ON ( PCIE_CAP_ON ),
.PCIE_CAP_RSVD_15_14 ( PCIE_CAP_RSVD_15_14 ),
.PCIE_CAP_SLOT_IMPLEMENTED ( PCIE_CAP_SLOT_IMPLEMENTED ),
.PCIE_REVISION ( PCIE_REVISION ),
.PL_AUTO_CONFIG ( PL_AUTO_CONFIG ),
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
.PM_ASPML0S_TIMEOUT ( PM_ASPML0S_TIMEOUT ),
.PM_ASPML0S_TIMEOUT_EN ( PM_ASPML0S_TIMEOUT_EN ),
.PM_ASPML0S_TIMEOUT_FUNC ( PM_ASPML0S_TIMEOUT_FUNC ),
.PM_ASPM_FASTEXIT ( PM_ASPM_FASTEXIT ),
.PM_BASE_PTR ( PM_BASE_PTR ),
.PM_CAP_AUXCURRENT ( PM_CAP_AUXCURRENT ),
.PM_CAP_D1SUPPORT( PM_CAP_D1SUPPORT ),
.PM_CAP_D2SUPPORT( PM_CAP_D2SUPPORT ),
.PM_CAP_DSI ( PM_CAP_DSI ),
.PM_CAP_ID ( PM_CAP_ID ),
.PM_CAP_NEXTPTR ( PM_CAP_NEXTPTR ),
.PM_CAP_ON ( PM_CAP_ON ),
.PM_CAP_PME_CLOCK( PM_CAP_PME_CLOCK ),
.PM_CAP_PMESUPPORT ( PM_CAP_PMESUPPORT ),
.PM_CAP_RSVD_04 ( PM_CAP_RSVD_04 ),
.PM_CAP_VERSION ( PM_CAP_VERSION ),
.PM_CSR_B2B3 ( PM_CSR_B2B3 ),
.PM_CSR_BPCCEN ( PM_CSR_BPCCEN ),
.PM_CSR_NOSOFTRST( PM_CSR_NOSOFTRST ),
.PM_DATA0( PM_DATA0 ),
.PM_DATA1( PM_DATA1 ),
.PM_DATA2( PM_DATA2 ),
.PM_DATA3( PM_DATA3 ),
.PM_DATA4( PM_DATA4 ),
.PM_DATA5( PM_DATA5 ),
.PM_DATA6( PM_DATA6 ),
.PM_DATA7( PM_DATA7 ),
.PM_DATA_SCALE0 ( PM_DATA_SCALE0 ),
.PM_DATA_SCALE1 ( PM_DATA_SCALE1 ),
.PM_DATA_SCALE2 ( PM_DATA_SCALE2 ),
.PM_DATA_SCALE3 ( PM_DATA_SCALE3 ),
.PM_DATA_SCALE4 ( PM_DATA_SCALE4 ),
.PM_DATA_SCALE5 ( PM_DATA_SCALE5 ),
.PM_DATA_SCALE6 ( PM_DATA_SCALE6 ),
.PM_DATA_SCALE7 ( PM_DATA_SCALE7 ),
.PM_MF (PM_MF),
.RBAR_BASE_PTR (RBAR_BASE_PTR),
.RBAR_CAP_CONTROL_ENCODEDBAR0 (RBAR_CAP_CONTROL_ENCODEDBAR0),
.RBAR_CAP_CONTROL_ENCODEDBAR1 (RBAR_CAP_CONTROL_ENCODEDBAR1),
.RBAR_CAP_CONTROL_ENCODEDBAR2 (RBAR_CAP_CONTROL_ENCODEDBAR2),
.RBAR_CAP_CONTROL_ENCODEDBAR3 (RBAR_CAP_CONTROL_ENCODEDBAR3),
.RBAR_CAP_CONTROL_ENCODEDBAR4 (RBAR_CAP_CONTROL_ENCODEDBAR4),
.RBAR_CAP_CONTROL_ENCODEDBAR5 (RBAR_CAP_CONTROL_ENCODEDBAR5),
.RBAR_CAP_ID (RBAR_CAP_ID),
.RBAR_CAP_INDEX0 (RBAR_CAP_INDEX0),
.RBAR_CAP_INDEX1 (RBAR_CAP_INDEX1),
.RBAR_CAP_INDEX2 (RBAR_CAP_INDEX2),
.RBAR_CAP_INDEX3 (RBAR_CAP_INDEX3),
.RBAR_CAP_INDEX4 (RBAR_CAP_INDEX4),
.RBAR_CAP_INDEX5 (RBAR_CAP_INDEX5),
.RBAR_CAP_NEXTPTR (RBAR_CAP_NEXTPTR),
.RBAR_CAP_ON (RBAR_CAP_ON),
.RBAR_CAP_SUP0 (RBAR_CAP_SUP0),
.RBAR_CAP_SUP1 (RBAR_CAP_SUP1),
.RBAR_CAP_SUP2 (RBAR_CAP_SUP2),
.RBAR_CAP_SUP3 (RBAR_CAP_SUP3),
.RBAR_CAP_SUP4 (RBAR_CAP_SUP4),
.RBAR_CAP_SUP5 (RBAR_CAP_SUP5),
.RBAR_CAP_VERSION (RBAR_CAP_VERSION),
.RBAR_NUM (RBAR_NUM),
.RECRC_CHK (RECRC_CHK),
.RECRC_CHK_TRIM (RECRC_CHK_TRIM),
.ROOT_CAP_CRS_SW_VISIBILITY ( ROOT_CAP_CRS_SW_VISIBILITY ),
.RP_AUTO_SPD ( RP_AUTO_SPD ),
.RP_AUTO_SPD_LOOPCNT ( RP_AUTO_SPD_LOOPCNT ),
.SELECT_DLL_IF ( SELECT_DLL_IF ),
.SLOT_CAP_ATT_BUTTON_PRESENT ( SLOT_CAP_ATT_BUTTON_PRESENT ),
.SLOT_CAP_ATT_INDICATOR_PRESENT ( SLOT_CAP_ATT_INDICATOR_PRESENT ),
.SLOT_CAP_ELEC_INTERLOCK_PRESENT ( SLOT_CAP_ELEC_INTERLOCK_PRESENT ),
.SLOT_CAP_HOTPLUG_CAPABLE( SLOT_CAP_HOTPLUG_CAPABLE ),
.SLOT_CAP_HOTPLUG_SURPRISE ( SLOT_CAP_HOTPLUG_SURPRISE ),
.SLOT_CAP_MRL_SENSOR_PRESENT ( SLOT_CAP_MRL_SENSOR_PRESENT ),
.SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ( SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ),
.SLOT_CAP_PHYSICAL_SLOT_NUM ( SLOT_CAP_PHYSICAL_SLOT_NUM ),
.SLOT_CAP_POWER_CONTROLLER_PRESENT ( SLOT_CAP_POWER_CONTROLLER_PRESENT ),
.SLOT_CAP_POWER_INDICATOR_PRESENT( SLOT_CAP_POWER_INDICATOR_PRESENT ),
.SLOT_CAP_SLOT_POWER_LIMIT_SCALE ( SLOT_CAP_SLOT_POWER_LIMIT_SCALE ),
.SLOT_CAP_SLOT_POWER_LIMIT_VALUE ( SLOT_CAP_SLOT_POWER_LIMIT_VALUE ),
.SPARE_BIT0 ( SPARE_BIT0 ),
.SPARE_BIT1 ( SPARE_BIT1 ),
.SPARE_BIT2 ( SPARE_BIT2 ),
.SPARE_BIT3 ( SPARE_BIT3 ),
.SPARE_BIT4 ( SPARE_BIT4 ),
.SPARE_BIT5 ( SPARE_BIT5 ),
.SPARE_BIT6 ( SPARE_BIT6 ),
.SPARE_BIT7 ( SPARE_BIT7 ),
.SPARE_BIT8 ( SPARE_BIT8 ),
.SPARE_BYTE0 ( SPARE_BYTE0 ),
.SPARE_BYTE1 ( SPARE_BYTE1 ),
.SPARE_BYTE2 ( SPARE_BYTE2 ),
.SPARE_BYTE3 ( SPARE_BYTE3 ),
.SPARE_WORD0 ( SPARE_WORD0 ),
.SPARE_WORD1 ( SPARE_WORD1 ),
.SPARE_WORD2 ( SPARE_WORD2 ),
.SPARE_WORD3 ( SPARE_WORD3 ),
.SSL_MESSAGE_AUTO (SSL_MESSAGE_AUTO),
.TECRC_EP_INV ( TECRC_EP_INV ),
.TL_RBYPASS(TL_RBYPASS),
.TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ),
.TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ),
.TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ),
.TL_TFC_DISABLE ( TL_TFC_DISABLE ),
.TL_TX_CHECKS_DISABLE ( TL_TX_CHECKS_DISABLE ),
.TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ),
.TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ),
.TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ),
.TRN_DW (TRN_DW),
.TRN_NP_FC (TRN_NP_FC),
.UPCONFIG_CAPABLE( UPCONFIG_CAPABLE ),
.UPSTREAM_FACING ( UPSTREAM_FACING ),
.UR_ATOMIC (UR_ATOMIC),
.UR_CFG1 (UR_CFG1),
.UR_INV_REQ(UR_INV_REQ),
.UR_PRS_RESPONSE (UR_PRS_RESPONSE),
.USER_CLK2_DIV2 (USER_CLK2_DIV2),
.USER_CLK_FREQ ( USER_CLK_FREQ ),
.USE_RID_PINS (USE_RID_PINS),
.VC0_CPL_INFINITE( VC0_CPL_INFINITE ),
.VC0_RX_RAM_LIMIT( VC0_RX_RAM_LIMIT ),
.VC0_TOTAL_CREDITS_CD ( VC0_TOTAL_CREDITS_CD ),
.VC0_TOTAL_CREDITS_CH ( VC0_TOTAL_CREDITS_CH ),
.VC0_TOTAL_CREDITS_NPD (VC0_TOTAL_CREDITS_NPD),
.VC0_TOTAL_CREDITS_NPH ( VC0_TOTAL_CREDITS_NPH ),
.VC0_TOTAL_CREDITS_PD ( VC0_TOTAL_CREDITS_PD ),
.VC0_TOTAL_CREDITS_PH ( VC0_TOTAL_CREDITS_PH ),
.VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ),
.VC_BASE_PTR ( VC_BASE_PTR ),
.VC_CAP_ID ( VC_CAP_ID ),
.VC_CAP_NEXTPTR ( VC_CAP_NEXTPTR ),
.VC_CAP_ON ( VC_CAP_ON ),
.VC_CAP_REJECT_SNOOP_TRANSACTIONS( VC_CAP_REJECT_SNOOP_TRANSACTIONS ),
.VC_CAP_VERSION ( VC_CAP_VERSION ),
.VSEC_BASE_PTR ( VSEC_BASE_PTR ),
.VSEC_CAP_HDR_ID ( VSEC_CAP_HDR_ID ),
.VSEC_CAP_HDR_LENGTH ( VSEC_CAP_HDR_LENGTH ),
.VSEC_CAP_HDR_REVISION ( VSEC_CAP_HDR_REVISION ),
.VSEC_CAP_ID ( VSEC_CAP_ID ),
.VSEC_CAP_IS_LINK_VISIBLE( VSEC_CAP_IS_LINK_VISIBLE ),
.VSEC_CAP_NEXTPTR( VSEC_CAP_NEXTPTR ),
.VSEC_CAP_ON ( VSEC_CAP_ON ),
.VSEC_CAP_VERSION( VSEC_CAP_VERSION )
) pcie_7x_i (
.trn_lnk_up ( trn_lnk_up ),
.trn_clk ( user_clk_out ),
.lnk_clk_en ( lnk_clk_en),
.user_rst_n ( user_rst_n ),
.received_func_lvl_rst_n ( cfg_received_func_lvl_rst_n ),
.sys_rst_n (~phy_rdy_n),
.pl_rst_n ( 1'b1 ),
.dl_rst_n ( 1'b1 ),
.tl_rst_n ( 1'b1 ),
.cm_sticky_rst_n ( 1'b1 ),
.func_lvl_rst_n ( func_lvl_rst_n ),
.cm_rst_n ( cm_rst_n ),
.trn_rbar_hit ( trn_rbar_hit ),
.trn_rd ( trn_rd ),
.trn_recrc_err ( trn_recrc_err ),
.trn_reof ( trn_reof ),
.trn_rerrfwd ( trn_rerrfwd ),
.trn_rrem ( trn_rrem ),
.trn_rsof ( trn_rsof ),
.trn_rsrc_dsc ( trn_rsrc_dsc ),
.trn_rsrc_rdy ( trn_rsrc_rdy ),
.trn_rdst_rdy ( trn_rdst_rdy ),
.trn_rnp_ok ( rx_np_ok ),
.trn_rnp_req ( rx_np_req ),
.trn_rfcp_ret ( 1'b1 ),
.trn_tbuf_av ( tx_buf_av ),
.trn_tcfg_req ( tx_cfg_req ),
.trn_tdllp_dst_rdy ( ),
.trn_tdst_rdy ( trn_tdst_rdy ),
.trn_terr_drop ( tx_err_drop ),
.trn_tcfg_gnt ( trn_tcfg_gnt ),
.trn_td ( trn_td ),
.trn_tdllp_data ( 32'b0 ),
.trn_tdllp_src_rdy ( 1'b0 ),
.trn_tecrc_gen ( trn_tecrc_gen ),
.trn_teof ( trn_teof ),
.trn_terrfwd ( trn_terrfwd ),
.trn_trem ( trn_trem),
.trn_tsof ( trn_tsof ),
.trn_tsrc_dsc ( trn_tsrc_dsc ),
.trn_tsrc_rdy ( trn_tsrc_rdy ),
.trn_tstr ( trn_tstr ),
.trn_fc_cpld ( fc_cpld ),
.trn_fc_cplh ( fc_cplh ),
.trn_fc_npd ( fc_npd ),
.trn_fc_nph ( fc_nph ),
.trn_fc_pd ( fc_pd ),
.trn_fc_ph ( fc_ph ),
.trn_fc_sel ( fc_sel ),
.cfg_dev_id (cfg_dev_id),
.cfg_vend_id (cfg_vend_id),
.cfg_rev_id (cfg_rev_id),
.cfg_subsys_id (cfg_subsys_id),
.cfg_subsys_vend_id (cfg_subsys_vend_id),
.cfg_pciecap_interrupt_msgnum (cfg_pciecap_interrupt_msgnum),
.cfg_bridge_serr_en (cfg_bridge_serr_en),
.cfg_command_bus_master_enable ( cfg_command_bus_master_enable ),
.cfg_command_interrupt_disable ( cfg_command_interrupt_disable ),
.cfg_command_io_enable ( cfg_command_io_enable ),
.cfg_command_mem_enable ( cfg_command_mem_enable ),
.cfg_command_serr_en ( cfg_command_serr_en ),
.cfg_dev_control_aux_power_en ( cfg_dev_control_aux_power_en ),
.cfg_dev_control_corr_err_reporting_en ( cfg_dev_control_corr_err_reporting_en ),
.cfg_dev_control_enable_ro ( cfg_dev_control_enable_ro ),
.cfg_dev_control_ext_tag_en ( cfg_dev_control_ext_tag_en ),
.cfg_dev_control_fatal_err_reporting_en ( cfg_dev_control_fatal_err_reporting_en ),
.cfg_dev_control_max_payload ( cfg_dev_control_max_payload ),
.cfg_dev_control_max_read_req ( cfg_dev_control_max_read_req ),
.cfg_dev_control_non_fatal_reporting_en ( cfg_dev_control_non_fatal_reporting_en ),
.cfg_dev_control_no_snoop_en ( cfg_dev_control_no_snoop_en ),
.cfg_dev_control_phantom_en ( cfg_dev_control_phantom_en ),
.cfg_dev_control_ur_err_reporting_en ( cfg_dev_control_ur_err_reporting_en ),
.cfg_dev_control2_cpl_timeout_dis ( cfg_dev_control2_cpl_timeout_dis ),
.cfg_dev_control2_cpl_timeout_val ( cfg_dev_control2_cpl_timeout_val ),
.cfg_dev_control2_ari_forward_en ( cfg_dev_control2_ari_forward_en),
.cfg_dev_control2_atomic_requester_en ( cfg_dev_control2_atomic_requester_en),
.cfg_dev_control2_atomic_egress_block ( cfg_dev_control2_atomic_egress_block),
.cfg_dev_control2_ido_req_en ( cfg_dev_control2_ido_req_en),
.cfg_dev_control2_ido_cpl_en ( cfg_dev_control2_ido_cpl_en),
.cfg_dev_control2_ltr_en ( cfg_dev_control2_ltr_en),
.cfg_dev_control2_tlp_prefix_block ( cfg_dev_control2_tlp_prefix_block),
.cfg_dev_status_corr_err_detected ( cfg_dev_status_corr_err_detected ),
.cfg_dev_status_fatal_err_detected ( cfg_dev_status_fatal_err_detected ),
.cfg_dev_status_non_fatal_err_detected ( cfg_dev_status_non_fatal_err_detected ),
.cfg_dev_status_ur_detected ( cfg_dev_status_ur_detected ),
.cfg_mgmt_do ( cfg_mgmt_do ),
.cfg_err_aer_headerlog_set_n ( cfg_err_aer_headerlog_set_n),
.cfg_err_aer_headerlog ( cfg_err_aer_headerlog),
.cfg_err_cpl_rdy_n ( cfg_err_cpl_rdy_n ),
.cfg_interrupt_do ( cfg_interrupt_do ),
.cfg_interrupt_mmenable ( cfg_interrupt_mmenable ),
.cfg_interrupt_msienable ( cfg_interrupt_msienable ),
.cfg_interrupt_msixenable ( cfg_interrupt_msixenable ),
.cfg_interrupt_msixfm ( cfg_interrupt_msixfm ),
.cfg_interrupt_rdy_n ( cfg_interrupt_rdy_n ),
.cfg_link_control_rcb ( cfg_link_control_rcb ),
.cfg_link_control_aspm_control ( cfg_link_control_aspm_control ),
.cfg_link_control_auto_bandwidth_int_en ( cfg_link_control_auto_bandwidth_int_en ),
.cfg_link_control_bandwidth_int_en ( cfg_link_control_bandwidth_int_en ),
.cfg_link_control_clock_pm_en ( cfg_link_control_clock_pm_en ),
.cfg_link_control_common_clock ( cfg_link_control_common_clock ),
.cfg_link_control_extended_sync ( cfg_link_control_extended_sync ),
.cfg_link_control_hw_auto_width_dis ( cfg_link_control_hw_auto_width_dis ),
.cfg_link_control_link_disable ( cfg_link_control_link_disable ),
.cfg_link_control_retrain_link ( cfg_link_control_retrain_link ),
.cfg_link_status_auto_bandwidth_status ( cfg_link_status_auto_bandwidth_status ),
.cfg_link_status_bandwidth_status ( cfg_link_status_bandwidth_status ),
.cfg_link_status_current_speed ( cfg_link_status_current_speed ),
.cfg_link_status_dll_active ( cfg_link_status_dll_active ),
.cfg_link_status_link_training ( cfg_link_status_link_training ),
.cfg_link_status_negotiated_width ( cfg_link_status_negotiated_width),
.cfg_msg_data ( cfg_msg_data ),
.cfg_msg_received ( cfg_msg_received ),
.cfg_msg_received_assert_int_a ( cfg_msg_received_assert_int_a),
.cfg_msg_received_assert_int_b ( cfg_msg_received_assert_int_b),
.cfg_msg_received_assert_int_c ( cfg_msg_received_assert_int_c),
.cfg_msg_received_assert_int_d ( cfg_msg_received_assert_int_d),
.cfg_msg_received_deassert_int_a ( cfg_msg_received_deassert_int_a),
.cfg_msg_received_deassert_int_b ( cfg_msg_received_deassert_int_b),
.cfg_msg_received_deassert_int_c ( cfg_msg_received_deassert_int_c),
.cfg_msg_received_deassert_int_d ( cfg_msg_received_deassert_int_d),
.cfg_msg_received_err_cor ( cfg_msg_received_err_cor),
.cfg_msg_received_err_fatal ( cfg_msg_received_err_fatal),
.cfg_msg_received_err_non_fatal ( cfg_msg_received_err_non_fatal),
.cfg_msg_received_pm_as_nak ( cfg_msg_received_pm_as_nak),
.cfg_msg_received_pme_to ( cfg_msg_received_pme_to ),
.cfg_msg_received_pme_to_ack ( cfg_msg_received_pme_to_ack),
.cfg_msg_received_pm_pme ( cfg_msg_received_pm_pme),
.cfg_msg_received_setslotpowerlimit ( cfg_msg_received_setslotpowerlimit),
.cfg_msg_received_unlock ( cfg_msg_received_unlock),
.cfg_pcie_link_state ( cfg_pcie_link_state ),
.cfg_pmcsr_pme_en ( cfg_pmcsr_pme_en),
.cfg_pmcsr_powerstate ( cfg_pmcsr_powerstate),
.cfg_pmcsr_pme_status ( cfg_pmcsr_pme_status),
.cfg_pm_rcv_as_req_l1_n ( cfg_pm_rcv_as_req_l1_n),
.cfg_pm_rcv_enter_l1_n ( cfg_pm_rcv_enter_l1_n),
.cfg_pm_rcv_enter_l23_n ( cfg_pm_rcv_enter_l23_n),
.cfg_pm_rcv_req_ack_n ( cfg_pm_rcv_req_ack_n),
.cfg_mgmt_rd_wr_done_n ( cfg_mgmt_rd_wr_done_n ),
.cfg_slot_control_electromech_il_ctl_pulse (cfg_slot_control_electromech_il_ctl_pulse),
.cfg_root_control_syserr_corr_err_en ( cfg_root_control_syserr_corr_err_en),
.cfg_root_control_syserr_non_fatal_err_en ( cfg_root_control_syserr_non_fatal_err_en),
.cfg_root_control_syserr_fatal_err_en ( cfg_root_control_syserr_fatal_err_en),
.cfg_root_control_pme_int_en ( cfg_root_control_pme_int_en ),
.cfg_aer_ecrc_check_en ( cfg_aer_ecrc_check_en ),
.cfg_aer_ecrc_gen_en ( cfg_aer_ecrc_gen_en ),
.cfg_aer_rooterr_corr_err_reporting_en ( cfg_aer_rooterr_corr_err_reporting_en),
.cfg_aer_rooterr_non_fatal_err_reporting_en( cfg_aer_rooterr_non_fatal_err_reporting_en),
.cfg_aer_rooterr_fatal_err_reporting_en ( cfg_aer_rooterr_fatal_err_reporting_en),
.cfg_aer_rooterr_corr_err_received ( cfg_aer_rooterr_corr_err_received),
.cfg_aer_rooterr_non_fatal_err_received ( cfg_aer_rooterr_non_fatal_err_received),
.cfg_aer_rooterr_fatal_err_received ( cfg_aer_rooterr_fatal_err_received),
.cfg_aer_interrupt_msgnum ( cfg_aer_interrupt_msgnum ),
.cfg_transaction ( cfg_transaction),
.cfg_transaction_addr ( cfg_transaction_addr),
.cfg_transaction_type ( cfg_transaction_type),
.cfg_vc_tcvc_map ( cfg_vc_tcvc_map),
.cfg_mgmt_byte_en_n ( cfg_mgmt_byte_en_n ),
.cfg_mgmt_di ( cfg_mgmt_di ),
.cfg_ds_bus_number ( cfg_ds_bus_number ),
.cfg_ds_device_number ( cfg_ds_device_number ),
.cfg_ds_function_number ( cfg_ds_function_number ),
.cfg_dsn ( cfg_dsn ),
.cfg_mgmt_dwaddr ( cfg_mgmt_dwaddr ),
.cfg_err_acs_n ( 1'b1 ),
.cfg_err_cor_n ( cfg_err_cor_n ),
.cfg_err_cpl_abort_n ( cfg_err_cpl_abort_n ),
.cfg_err_cpl_timeout_n ( cfg_err_cpl_timeout_n ),
.cfg_err_cpl_unexpect_n ( cfg_err_cpl_unexpect_n ),
.cfg_err_ecrc_n ( cfg_err_ecrc_n ),
.cfg_err_locked_n ( cfg_err_locked_n ),
.cfg_err_posted_n ( cfg_err_posted_n ),
.cfg_err_tlp_cpl_header ( cfg_err_tlp_cpl_header ),
.cfg_err_ur_n ( cfg_err_ur_n ),
.cfg_err_malformed_n ( cfg_err_malformed_n ),
.cfg_err_poisoned_n ( cfg_err_poisoned_n),
.cfg_err_atomic_egress_blocked_n ( cfg_err_atomic_egress_blocked_n ),
.cfg_err_mc_blocked_n ( cfg_err_mc_blocked_n ),
.cfg_err_internal_uncor_n ( cfg_err_internal_uncor_n ),
.cfg_err_internal_cor_n ( cfg_err_internal_cor_n ),
.cfg_err_norecovery_n ( cfg_err_norecovery_n ),
.cfg_interrupt_assert_n ( cfg_interrupt_assert_n ),
.cfg_interrupt_di ( cfg_interrupt_di ),
.cfg_interrupt_n ( cfg_interrupt_n ),
.cfg_interrupt_stat_n ( cfg_interrupt_stat_n),
.cfg_pm_send_pme_to_n ( cfg_pm_send_pme_to_n ),
.cfg_pm_turnoff_ok_n ( cfg_turnoff_ok_w ),
.cfg_pm_wake_n ( cfg_pm_wake_n ),
.cfg_pm_halt_aspm_l0s_n ( cfg_pm_halt_aspm_l0s_n ),
.cfg_pm_halt_aspm_l1_n ( cfg_pm_halt_aspm_l1_n ),
.cfg_pm_force_state_en_n ( cfg_pm_force_state_en_n ),
.cfg_pm_force_state ( cfg_pm_force_state ),
.cfg_force_mps ( cfg_force_mps ),
.cfg_force_common_clock_off ( cfg_force_common_clock_off ),
.cfg_force_extended_sync_on ( cfg_force_extended_sync_on ),
.cfg_port_number ( cfg_port_number ),
.cfg_mgmt_rd_en_n ( cfg_mgmt_rd_en_n ),
.cfg_trn_pending_n ( ~cfg_trn_pending ),
.cfg_mgmt_wr_en_n ( cfg_mgmt_wr_en_n ),
.cfg_mgmt_wr_readonly_n ( cfg_mgmt_wr_readonly_n ),
.cfg_mgmt_wr_rw1c_as_rw_n ( cfg_mgmt_wr_rw1c_as_rw_n ),
.pl_initial_link_width ( pl_initial_link_width ),
.pl_lane_reversal_mode ( pl_lane_reversal_mode ),
.pl_link_gen2_cap ( pl_link_gen2_cap ),
.pl_link_partner_gen2_supported ( pl_link_partner_gen2_supported ),
.pl_link_upcfg_cap ( pl_link_upcfg_cap ),
.pl_ltssm_state ( pl_ltssm_state ),
.pl_phy_lnk_up_n ( pl_phy_lnk_up_n ),
.pl_received_hot_rst ( pl_received_hot_rst ),
.pl_rx_pm_state ( pl_rx_pm_state ),
.pl_sel_lnk_rate ( pl_sel_lnk_rate),
.pl_sel_lnk_width ( pl_sel_lnk_width ),
.pl_tx_pm_state ( pl_tx_pm_state ),
.pl_directed_link_auton ( pl_directed_link_auton ),
.pl_directed_link_change ( pl_directed_link_change ),
.pl_directed_link_speed ( pl_directed_link_speed ),
.pl_directed_link_width ( pl_directed_link_width ),
.pl_downstream_deemph_source ( pl_downstream_deemph_source ),
.pl_upstream_prefer_deemph ( pl_upstream_prefer_deemph ),
.pl_transmit_hot_rst ( pl_transmit_hot_rst ),
.pl_directed_ltssm_new_vld ( pl_directed_ltssm_new_vld ),
.pl_directed_ltssm_new ( pl_directed_ltssm_new ),
.pl_directed_ltssm_stall ( pl_directed_ltssm_stall ),
.pl_directed_change_done ( pl_directed_change_done ),
.dbg_sclr_a ( dbg_sclr_a ),
.dbg_sclr_b ( dbg_sclr_b ),
.dbg_sclr_c ( dbg_sclr_c ),
.dbg_sclr_d ( dbg_sclr_d ),
.dbg_sclr_e ( dbg_sclr_e ),
.dbg_sclr_f ( dbg_sclr_f ),
.dbg_sclr_g ( dbg_sclr_g ),
.dbg_sclr_h ( dbg_sclr_h ),
.dbg_sclr_i ( dbg_sclr_i ),
.dbg_sclr_j ( dbg_sclr_j ),
.dbg_sclr_k ( dbg_sclr_k ),
.dbg_vec_a ( dbg_vec_a ),
.dbg_vec_b ( dbg_vec_b ),
.dbg_vec_c ( dbg_vec_c ),
.pl_dbg_vec ( pl_dbg_vec ),
.dbg_mode ( dbg_mode ),
.dbg_sub_mode ( dbg_sub_mode ),
.pl_dbg_mode ( pl_dbg_mode ),
.drp_do ( drp_do ),
.drp_rdy ( drp_rdy ),
.drp_clk ( drp_clk ),
.drp_addr ( drp_addr ),
.drp_en ( drp_en ),
.drp_di ( drp_di ),
.drp_we ( drp_we ),
.ll2_tlp_rcv ( 1'b0 ),
.ll2_send_enter_l1 ( 1'b0 ),
.ll2_send_enter_l23 ( 1'b0 ),
.ll2_send_as_req_l1 ( 1'b0 ),
.ll2_send_pm_ack ( 1'b0 ),
.ll2_suspend_now ( 1'b0 ),
.ll2_tfc_init1_seq ( ),
.ll2_tfc_init2_seq ( ),
.ll2_suspend_ok ( ),
.ll2_tx_idle ( ),
.ll2_link_status ( ),
.ll2_receiver_err ( ),
.ll2_protocol_err ( ),
.ll2_bad_tlp_err ( ),
.ll2_bad_dllp_err ( ),
.ll2_replay_ro_err ( ),
.ll2_replay_to_err ( ),
.tl2_ppm_suspend_req ( 1'b0 ),
.tl2_aspm_suspend_credit_check ( 1'b0 ),
.tl2_ppm_suspend_ok ( ),
.tl2_aspm_suspend_req ( ),
.tl2_aspm_suspend_credit_check_ok ( ),
.tl2_err_hdr ( ),
.tl2_err_malformed ( ),
.tl2_err_rxoverflow ( ),
.tl2_err_fcpe ( ),
.pl2_directed_lstate ( 5'b0 ),
.pl2_suspend_ok ( ),
.pl2_recovery ( ),
.pl2_rx_elec_idle ( ),
.pl2_rx_pm_state ( ),
.pl2_l0_req ( ),
.pl2_link_up ( ),
.pl2_receiver_err ( ),
.trn_rdllp_data (trn_rdllp_data ),
.trn_rdllp_src_rdy (trn_rdllp_src_rdy ),
.pipe_clk ( pipe_clk ),
.user_clk2 ( user_clk2 ),
.user_clk ( user_clk ),
.user_clk_prebuf ( 1'b0 ),
.user_clk_prebuf_en ( 1'b0 ),
.pipe_rx0_polarity ( pipe_rx0_polarity ),
.pipe_rx1_polarity ( pipe_rx1_polarity ),
.pipe_rx2_polarity ( pipe_rx2_polarity ),
.pipe_rx3_polarity ( pipe_rx3_polarity ),
.pipe_rx4_polarity ( pipe_rx4_polarity ),
.pipe_rx5_polarity ( pipe_rx5_polarity ),
.pipe_rx6_polarity ( pipe_rx6_polarity ),
.pipe_rx7_polarity ( pipe_rx7_polarity ),
.pipe_tx0_compliance ( pipe_tx0_compliance ),
.pipe_tx1_compliance ( pipe_tx1_compliance ),
.pipe_tx2_compliance ( pipe_tx2_compliance ),
.pipe_tx3_compliance ( pipe_tx3_compliance ),
.pipe_tx4_compliance ( pipe_tx4_compliance ),
.pipe_tx5_compliance ( pipe_tx5_compliance ),
.pipe_tx6_compliance ( pipe_tx6_compliance ),
.pipe_tx7_compliance ( pipe_tx7_compliance ),
.pipe_tx0_char_is_k ( pipe_tx0_char_is_k ),
.pipe_tx1_char_is_k ( pipe_tx1_char_is_k ),
.pipe_tx2_char_is_k ( pipe_tx2_char_is_k ),
.pipe_tx3_char_is_k ( pipe_tx3_char_is_k ),
.pipe_tx4_char_is_k ( pipe_tx4_char_is_k ),
.pipe_tx5_char_is_k ( pipe_tx5_char_is_k ),
.pipe_tx6_char_is_k ( pipe_tx6_char_is_k ),
.pipe_tx7_char_is_k ( pipe_tx7_char_is_k ),
.pipe_tx0_data ( pipe_tx0_data ),
.pipe_tx1_data ( pipe_tx1_data ),
.pipe_tx2_data ( pipe_tx2_data ),
.pipe_tx3_data ( pipe_tx3_data ),
.pipe_tx4_data ( pipe_tx4_data ),
.pipe_tx5_data ( pipe_tx5_data ),
.pipe_tx6_data ( pipe_tx6_data ),
.pipe_tx7_data ( pipe_tx7_data ),
.pipe_tx0_elec_idle ( pipe_tx0_elec_idle ),
.pipe_tx1_elec_idle ( pipe_tx1_elec_idle ),
.pipe_tx2_elec_idle ( pipe_tx2_elec_idle ),
.pipe_tx3_elec_idle ( pipe_tx3_elec_idle ),
.pipe_tx4_elec_idle ( pipe_tx4_elec_idle ),
.pipe_tx5_elec_idle ( pipe_tx5_elec_idle ),
.pipe_tx6_elec_idle ( pipe_tx6_elec_idle ),
.pipe_tx7_elec_idle ( pipe_tx7_elec_idle ),
.pipe_tx0_powerdown ( pipe_tx0_powerdown ),
.pipe_tx1_powerdown ( pipe_tx1_powerdown ),
.pipe_tx2_powerdown ( pipe_tx2_powerdown ),
.pipe_tx3_powerdown ( pipe_tx3_powerdown ),
.pipe_tx4_powerdown ( pipe_tx4_powerdown ),
.pipe_tx5_powerdown ( pipe_tx5_powerdown ),
.pipe_tx6_powerdown ( pipe_tx6_powerdown ),
.pipe_tx7_powerdown ( pipe_tx7_powerdown ),
.pipe_rx0_char_is_k ( pipe_rx0_char_is_k ),
.pipe_rx1_char_is_k ( pipe_rx1_char_is_k ),
.pipe_rx2_char_is_k ( pipe_rx2_char_is_k ),
.pipe_rx3_char_is_k ( pipe_rx3_char_is_k ),
.pipe_rx4_char_is_k ( pipe_rx4_char_is_k ),
.pipe_rx5_char_is_k ( pipe_rx5_char_is_k ),
.pipe_rx6_char_is_k ( pipe_rx6_char_is_k ),
.pipe_rx7_char_is_k ( pipe_rx7_char_is_k ),
.pipe_rx0_valid ( pipe_rx0_valid ),
.pipe_rx1_valid ( pipe_rx1_valid ),
.pipe_rx2_valid ( pipe_rx2_valid ),
.pipe_rx3_valid ( pipe_rx3_valid ),
.pipe_rx4_valid ( pipe_rx4_valid ),
.pipe_rx5_valid ( pipe_rx5_valid ),
.pipe_rx6_valid ( pipe_rx6_valid ),
.pipe_rx7_valid ( pipe_rx7_valid ),
.pipe_rx0_data ( pipe_rx0_data ),
.pipe_rx1_data ( pipe_rx1_data ),
.pipe_rx2_data ( pipe_rx2_data ),
.pipe_rx3_data ( pipe_rx3_data ),
.pipe_rx4_data ( pipe_rx4_data ),
.pipe_rx5_data ( pipe_rx5_data ),
.pipe_rx6_data ( pipe_rx6_data ),
.pipe_rx7_data ( pipe_rx7_data ),
.pipe_rx0_chanisaligned ( pipe_rx0_chanisaligned ),
.pipe_rx1_chanisaligned ( pipe_rx1_chanisaligned ),
.pipe_rx2_chanisaligned ( pipe_rx2_chanisaligned ),
.pipe_rx3_chanisaligned ( pipe_rx3_chanisaligned ),
.pipe_rx4_chanisaligned ( pipe_rx4_chanisaligned ),
.pipe_rx5_chanisaligned ( pipe_rx5_chanisaligned ),
.pipe_rx6_chanisaligned ( pipe_rx6_chanisaligned ),
.pipe_rx7_chanisaligned ( pipe_rx7_chanisaligned ),
.pipe_rx0_status ( pipe_rx0_status ),
.pipe_rx1_status ( pipe_rx1_status ),
.pipe_rx2_status ( pipe_rx2_status ),
.pipe_rx3_status ( pipe_rx3_status ),
.pipe_rx4_status ( pipe_rx4_status ),
.pipe_rx5_status ( pipe_rx5_status ),
.pipe_rx6_status ( pipe_rx6_status ),
.pipe_rx7_status ( pipe_rx7_status ),
.pipe_rx0_phy_status ( pipe_rx0_phy_status ),
.pipe_rx1_phy_status ( pipe_rx1_phy_status ),
.pipe_rx2_phy_status ( pipe_rx2_phy_status ),
.pipe_rx3_phy_status ( pipe_rx3_phy_status ),
.pipe_rx4_phy_status ( pipe_rx4_phy_status ),
.pipe_rx5_phy_status ( pipe_rx5_phy_status ),
.pipe_rx6_phy_status ( pipe_rx6_phy_status ),
.pipe_rx7_phy_status ( pipe_rx7_phy_status ),
.pipe_tx_deemph ( pipe_tx_deemph ),
.pipe_tx_margin ( pipe_tx_margin ),
.pipe_tx_reset ( pipe_tx_reset ),
.pipe_tx_rcvr_det ( pipe_tx_rcvr_det ),
.pipe_tx_rate ( pipe_tx_rate ),
.pipe_rx0_elec_idle ( pipe_rx0_elec_idle ),
.pipe_rx1_elec_idle ( pipe_rx1_elec_idle ),
.pipe_rx2_elec_idle ( pipe_rx2_elec_idle ),
.pipe_rx3_elec_idle ( pipe_rx3_elec_idle ),
.pipe_rx4_elec_idle ( pipe_rx4_elec_idle ),
.pipe_rx5_elec_idle ( pipe_rx5_elec_idle ),
.pipe_rx6_elec_idle ( pipe_rx6_elec_idle ),
.pipe_rx7_elec_idle ( pipe_rx7_elec_idle )
);
//------------------------------------------------------------------------------------------------------------------//
// PIPE Interface PIPELINE Module //
//------------------------------------------------------------------------------------------------------------------//
pcie_7x_v1_11_0_pcie_pipe_pipeline # (
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.PIPE_PIPELINE_STAGES ( PIPE_PIPELINE_STAGES )
)
pcie_pipe_pipeline_i (
// Pipe Per-Link Signals
.pipe_tx_rcvr_det_i (pipe_tx_rcvr_det),
.pipe_tx_reset_i (1'b0), //MV?
.pipe_tx_rate_i (pipe_tx_rate),
.pipe_tx_deemph_i (pipe_tx_deemph),
.pipe_tx_margin_i (pipe_tx_margin),
.pipe_tx_swing_i (1'b0),
.pipe_tx_rcvr_det_o (pipe_tx_rcvr_det_gt),
.pipe_tx_reset_o ( ),
.pipe_tx_rate_o (pipe_tx_rate_gt),
.pipe_tx_deemph_o (pipe_tx_deemph_gt),
.pipe_tx_margin_o (pipe_tx_margin_gt),
.pipe_tx_swing_o ( ),
// Pipe Per-Lane Signals - Lane 0
.pipe_rx0_char_is_k_o (pipe_rx0_char_is_k ),
.pipe_rx0_data_o (pipe_rx0_data ),
.pipe_rx0_valid_o (pipe_rx0_valid ),
.pipe_rx0_chanisaligned_o (pipe_rx0_chanisaligned ),
.pipe_rx0_status_o (pipe_rx0_status ),
.pipe_rx0_phy_status_o (pipe_rx0_phy_status ),
.pipe_rx0_elec_idle_i (pipe_rx0_elec_idle_gt ),
.pipe_rx0_polarity_i (pipe_rx0_polarity ),
.pipe_tx0_compliance_i (pipe_tx0_compliance ),
.pipe_tx0_char_is_k_i (pipe_tx0_char_is_k ),
.pipe_tx0_data_i (pipe_tx0_data ),
.pipe_tx0_elec_idle_i (pipe_tx0_elec_idle ),
.pipe_tx0_powerdown_i (pipe_tx0_powerdown ),
.pipe_rx0_char_is_k_i (pipe_rx0_char_is_k_gt ),
.pipe_rx0_data_i (pipe_rx0_data_gt ),
.pipe_rx0_valid_i (pipe_rx0_valid_gt ),
.pipe_rx0_chanisaligned_i (pipe_rx0_chanisaligned_gt),
.pipe_rx0_status_i (pipe_rx0_status_gt ),
.pipe_rx0_phy_status_i (pipe_rx0_phy_status_gt ),
.pipe_rx0_elec_idle_o (pipe_rx0_elec_idle ),
.pipe_rx0_polarity_o (pipe_rx0_polarity_gt ),
.pipe_tx0_compliance_o (pipe_tx0_compliance_gt ),
.pipe_tx0_char_is_k_o (pipe_tx0_char_is_k_gt ),
.pipe_tx0_data_o (pipe_tx0_data_gt ),
.pipe_tx0_elec_idle_o (pipe_tx0_elec_idle_gt ),
.pipe_tx0_powerdown_o (pipe_tx0_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 1
.pipe_rx1_char_is_k_o (pipe_rx1_char_is_k ),
.pipe_rx1_data_o (pipe_rx1_data ),
.pipe_rx1_valid_o (pipe_rx1_valid ),
.pipe_rx1_chanisaligned_o (pipe_rx1_chanisaligned ),
.pipe_rx1_status_o (pipe_rx1_status ),
.pipe_rx1_phy_status_o (pipe_rx1_phy_status ),
.pipe_rx1_elec_idle_i (pipe_rx1_elec_idle_gt ),
.pipe_rx1_polarity_i (pipe_rx1_polarity ),
.pipe_tx1_compliance_i (pipe_tx1_compliance ),
.pipe_tx1_char_is_k_i (pipe_tx1_char_is_k ),
.pipe_tx1_data_i (pipe_tx1_data ),
.pipe_tx1_elec_idle_i (pipe_tx1_elec_idle ),
.pipe_tx1_powerdown_i (pipe_tx1_powerdown ),
.pipe_rx1_char_is_k_i (pipe_rx1_char_is_k_gt ),
.pipe_rx1_data_i (pipe_rx1_data_gt ),
.pipe_rx1_valid_i (pipe_rx1_valid_gt ),
.pipe_rx1_chanisaligned_i (pipe_rx1_chanisaligned_gt),
.pipe_rx1_status_i (pipe_rx1_status_gt ),
.pipe_rx1_phy_status_i (pipe_rx1_phy_status_gt ),
.pipe_rx1_elec_idle_o (pipe_rx1_elec_idle ),
.pipe_rx1_polarity_o (pipe_rx1_polarity_gt ),
.pipe_tx1_compliance_o (pipe_tx1_compliance_gt ),
.pipe_tx1_char_is_k_o (pipe_tx1_char_is_k_gt ),
.pipe_tx1_data_o (pipe_tx1_data_gt ),
.pipe_tx1_elec_idle_o (pipe_tx1_elec_idle_gt ),
.pipe_tx1_powerdown_o (pipe_tx1_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 2
.pipe_rx2_char_is_k_o (pipe_rx2_char_is_k ),
.pipe_rx2_data_o (pipe_rx2_data ),
.pipe_rx2_valid_o (pipe_rx2_valid ),
.pipe_rx2_chanisaligned_o (pipe_rx2_chanisaligned ),
.pipe_rx2_status_o (pipe_rx2_status ),
.pipe_rx2_phy_status_o (pipe_rx2_phy_status ),
.pipe_rx2_elec_idle_i (pipe_rx2_elec_idle_gt ),
.pipe_rx2_polarity_i (pipe_rx2_polarity ),
.pipe_tx2_compliance_i (pipe_tx2_compliance ),
.pipe_tx2_char_is_k_i (pipe_tx2_char_is_k ),
.pipe_tx2_data_i (pipe_tx2_data ),
.pipe_tx2_elec_idle_i (pipe_tx2_elec_idle ),
.pipe_tx2_powerdown_i (pipe_tx2_powerdown ),
.pipe_rx2_char_is_k_i (pipe_rx2_char_is_k_gt ),
.pipe_rx2_data_i (pipe_rx2_data_gt ),
.pipe_rx2_valid_i (pipe_rx2_valid_gt ),
.pipe_rx2_chanisaligned_i (pipe_rx2_chanisaligned_gt),
.pipe_rx2_status_i (pipe_rx2_status_gt ),
.pipe_rx2_phy_status_i (pipe_rx2_phy_status_gt ),
.pipe_rx2_elec_idle_o (pipe_rx2_elec_idle ),
.pipe_rx2_polarity_o (pipe_rx2_polarity_gt ),
.pipe_tx2_compliance_o (pipe_tx2_compliance_gt ),
.pipe_tx2_char_is_k_o (pipe_tx2_char_is_k_gt ),
.pipe_tx2_data_o (pipe_tx2_data_gt ),
.pipe_tx2_elec_idle_o (pipe_tx2_elec_idle_gt ),
.pipe_tx2_powerdown_o (pipe_tx2_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 3
.pipe_rx3_char_is_k_o (pipe_rx3_char_is_k ),
.pipe_rx3_data_o (pipe_rx3_data ),
.pipe_rx3_valid_o (pipe_rx3_valid ),
.pipe_rx3_chanisaligned_o (pipe_rx3_chanisaligned ),
.pipe_rx3_status_o (pipe_rx3_status ),
.pipe_rx3_phy_status_o (pipe_rx3_phy_status ),
.pipe_rx3_elec_idle_i (pipe_rx3_elec_idle_gt ),
.pipe_rx3_polarity_i (pipe_rx3_polarity ),
.pipe_tx3_compliance_i (pipe_tx3_compliance ),
.pipe_tx3_char_is_k_i (pipe_tx3_char_is_k ),
.pipe_tx3_data_i (pipe_tx3_data ),
.pipe_tx3_elec_idle_i (pipe_tx3_elec_idle ),
.pipe_tx3_powerdown_i (pipe_tx3_powerdown ),
.pipe_rx3_char_is_k_i (pipe_rx3_char_is_k_gt ),
.pipe_rx3_data_i (pipe_rx3_data_gt ),
.pipe_rx3_valid_i (pipe_rx3_valid_gt ),
.pipe_rx3_chanisaligned_i (pipe_rx3_chanisaligned_gt),
.pipe_rx3_status_i (pipe_rx3_status_gt ),
.pipe_rx3_phy_status_i (pipe_rx3_phy_status_gt ),
.pipe_rx3_elec_idle_o (pipe_rx3_elec_idle ),
.pipe_rx3_polarity_o (pipe_rx3_polarity_gt ),
.pipe_tx3_compliance_o (pipe_tx3_compliance_gt ),
.pipe_tx3_char_is_k_o (pipe_tx3_char_is_k_gt ),
.pipe_tx3_data_o (pipe_tx3_data_gt ),
.pipe_tx3_elec_idle_o (pipe_tx3_elec_idle_gt ),
.pipe_tx3_powerdown_o (pipe_tx3_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 4
.pipe_rx4_char_is_k_o (pipe_rx4_char_is_k ),
.pipe_rx4_data_o (pipe_rx4_data ),
.pipe_rx4_valid_o (pipe_rx4_valid ),
.pipe_rx4_chanisaligned_o (pipe_rx4_chanisaligned ),
.pipe_rx4_status_o (pipe_rx4_status ),
.pipe_rx4_phy_status_o (pipe_rx4_phy_status ),
.pipe_rx4_elec_idle_i (pipe_rx4_elec_idle_gt ),
.pipe_rx4_polarity_i (pipe_rx4_polarity ),
.pipe_tx4_compliance_i (pipe_tx4_compliance ),
.pipe_tx4_char_is_k_i (pipe_tx4_char_is_k ),
.pipe_tx4_data_i (pipe_tx4_data ),
.pipe_tx4_elec_idle_i (pipe_tx4_elec_idle ),
.pipe_tx4_powerdown_i (pipe_tx4_powerdown ),
.pipe_rx4_char_is_k_i (pipe_rx4_char_is_k_gt ),
.pipe_rx4_data_i (pipe_rx4_data_gt ),
.pipe_rx4_valid_i (pipe_rx4_valid_gt ),
.pipe_rx4_chanisaligned_i (pipe_rx4_chanisaligned_gt),
.pipe_rx4_status_i (pipe_rx4_status_gt ),
.pipe_rx4_phy_status_i (pipe_rx4_phy_status_gt ),
.pipe_rx4_elec_idle_o (pipe_rx4_elec_idle ),
.pipe_rx4_polarity_o (pipe_rx4_polarity_gt ),
.pipe_tx4_compliance_o (pipe_tx4_compliance_gt ),
.pipe_tx4_char_is_k_o (pipe_tx4_char_is_k_gt ),
.pipe_tx4_data_o (pipe_tx4_data_gt ),
.pipe_tx4_elec_idle_o (pipe_tx4_elec_idle_gt ),
.pipe_tx4_powerdown_o (pipe_tx4_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 5
.pipe_rx5_char_is_k_o (pipe_rx5_char_is_k ),
.pipe_rx5_data_o (pipe_rx5_data ),
.pipe_rx5_valid_o (pipe_rx5_valid ),
.pipe_rx5_chanisaligned_o (pipe_rx5_chanisaligned ),
.pipe_rx5_status_o (pipe_rx5_status ),
.pipe_rx5_phy_status_o (pipe_rx5_phy_status ),
.pipe_rx5_elec_idle_i (pipe_rx5_elec_idle_gt ),
.pipe_rx5_polarity_i (pipe_rx5_polarity ),
.pipe_tx5_compliance_i (pipe_tx5_compliance ),
.pipe_tx5_char_is_k_i (pipe_tx5_char_is_k ),
.pipe_tx5_data_i (pipe_tx5_data ),
.pipe_tx5_elec_idle_i (pipe_tx5_elec_idle ),
.pipe_tx5_powerdown_i (pipe_tx5_powerdown ),
.pipe_rx5_char_is_k_i (pipe_rx5_char_is_k_gt ),
.pipe_rx5_data_i (pipe_rx5_data_gt ),
.pipe_rx5_valid_i (pipe_rx5_valid_gt ),
.pipe_rx5_chanisaligned_i (pipe_rx5_chanisaligned_gt),
.pipe_rx5_status_i (pipe_rx5_status_gt ),
.pipe_rx5_phy_status_i (pipe_rx5_phy_status_gt ),
.pipe_rx5_elec_idle_o (pipe_rx5_elec_idle ),
.pipe_rx5_polarity_o (pipe_rx5_polarity_gt ),
.pipe_tx5_compliance_o (pipe_tx5_compliance_gt ),
.pipe_tx5_char_is_k_o (pipe_tx5_char_is_k_gt ),
.pipe_tx5_data_o (pipe_tx5_data_gt ),
.pipe_tx5_elec_idle_o (pipe_tx5_elec_idle_gt ),
.pipe_tx5_powerdown_o (pipe_tx5_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 6
.pipe_rx6_char_is_k_o (pipe_rx6_char_is_k ),
.pipe_rx6_data_o (pipe_rx6_data ),
.pipe_rx6_valid_o (pipe_rx6_valid ),
.pipe_rx6_chanisaligned_o (pipe_rx6_chanisaligned ),
.pipe_rx6_status_o (pipe_rx6_status ),
.pipe_rx6_phy_status_o (pipe_rx6_phy_status ),
.pipe_rx6_elec_idle_i (pipe_rx6_elec_idle_gt ),
.pipe_rx6_polarity_i (pipe_rx6_polarity ),
.pipe_tx6_compliance_i (pipe_tx6_compliance ),
.pipe_tx6_char_is_k_i (pipe_tx6_char_is_k ),
.pipe_tx6_data_i (pipe_tx6_data ),
.pipe_tx6_elec_idle_i (pipe_tx6_elec_idle ),
.pipe_tx6_powerdown_i (pipe_tx6_powerdown ),
.pipe_rx6_char_is_k_i (pipe_rx6_char_is_k_gt ),
.pipe_rx6_data_i (pipe_rx6_data_gt ),
.pipe_rx6_valid_i (pipe_rx6_valid_gt ),
.pipe_rx6_chanisaligned_i (pipe_rx6_chanisaligned_gt),
.pipe_rx6_status_i (pipe_rx6_status_gt ),
.pipe_rx6_phy_status_i (pipe_rx6_phy_status_gt ),
.pipe_rx6_elec_idle_o (pipe_rx6_elec_idle ),
.pipe_rx6_polarity_o (pipe_rx6_polarity_gt ),
.pipe_tx6_compliance_o (pipe_tx6_compliance_gt ),
.pipe_tx6_char_is_k_o (pipe_tx6_char_is_k_gt ),
.pipe_tx6_data_o (pipe_tx6_data_gt ),
.pipe_tx6_elec_idle_o (pipe_tx6_elec_idle_gt ),
.pipe_tx6_powerdown_o (pipe_tx6_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 7
.pipe_rx7_char_is_k_o (pipe_rx7_char_is_k ),
.pipe_rx7_data_o (pipe_rx7_data ),
.pipe_rx7_valid_o (pipe_rx7_valid ),
.pipe_rx7_chanisaligned_o (pipe_rx7_chanisaligned ),
.pipe_rx7_status_o (pipe_rx7_status ),
.pipe_rx7_phy_status_o (pipe_rx7_phy_status ),
.pipe_rx7_elec_idle_i (pipe_rx7_elec_idle_gt ),
.pipe_rx7_polarity_i (pipe_rx7_polarity ),
.pipe_tx7_compliance_i (pipe_tx7_compliance ),
.pipe_tx7_char_is_k_i (pipe_tx7_char_is_k ),
.pipe_tx7_data_i (pipe_tx7_data ),
.pipe_tx7_elec_idle_i (pipe_tx7_elec_idle ),
.pipe_tx7_powerdown_i (pipe_tx7_powerdown ),
.pipe_rx7_char_is_k_i (pipe_rx7_char_is_k_gt ),
.pipe_rx7_data_i (pipe_rx7_data_gt ),
.pipe_rx7_valid_i (pipe_rx7_valid_gt ),
.pipe_rx7_chanisaligned_i (pipe_rx7_chanisaligned_gt),
.pipe_rx7_status_i (pipe_rx7_status_gt ),
.pipe_rx7_phy_status_i (pipe_rx7_phy_status_gt ),
.pipe_rx7_elec_idle_o (pipe_rx7_elec_idle ),
.pipe_rx7_polarity_o (pipe_rx7_polarity_gt ),
.pipe_tx7_compliance_o (pipe_tx7_compliance_gt ),
.pipe_tx7_char_is_k_o (pipe_tx7_char_is_k_gt ),
.pipe_tx7_data_o (pipe_tx7_data_gt ),
.pipe_tx7_elec_idle_o (pipe_tx7_elec_idle_gt ),
.pipe_tx7_powerdown_o (pipe_tx7_powerdown_gt ),
// Non PIPE signals
.pipe_clk (pipe_clk ),
.rst_n (phy_rdy_n )
);
endmodule
|
// test_pg.v
`timescale 1ns / 1ps
module test_pg;
reg clk = 0;
reg sync = 0;
reg reset = 1;
reg trigger = 0;
wire [4:0]signal;
// avalon interface
reg write_data = 0;
reg write_ctrl = 0;
reg read_ctrl = 0;
reg [7:0]address;
reg [31:0]writedata;
wire [31:0]readdata;
reg [1:0]byteenable = 2'b11;
task automatic pgwrite_data(input [7:0]a, input [15:0]d);
begin
@(posedge clk)
begin
#5;
write_data <= 1;
write_ctrl <= 0;
read_ctrl <= 0;
address <= a;
writedata <= {16'd0, d};
end
end
endtask
task automatic pgwrite_ctrl(input [7:0]a, input [31:0]d);
begin
@(posedge clk)
begin
#5;
write_data <= 0;
write_ctrl <= 1;
read_ctrl <= 0;
address <= a;
writedata <= d;
end
end
endtask
task automatic pgend();
begin
@(posedge clk)
begin
#5;
write_data <= 0;
write_ctrl <= 0;
read_ctrl <= 0;
address <= 8'dx;
writedata <= 32'dx;
end
end
endtask
always #10 clk <= ~clk;
integer n = 0;
always @(posedge clk)
begin
n <= n + 1;
sync <= !sync;
end
initial
begin
#25 reset = 0;
#20;
pgwrite_data( 0, { 5'b01000, 8'd1 } );
pgwrite_data( 1, { 5'b00100, 8'd2 } );
pgwrite_data( 2, { 5'b00010, 8'd3 } );
pgwrite_data( 3, { 5'b10001, 8'd4 } );
pgwrite_data( 4, { 5'b01111, 8'd1 } );
pgwrite_data( 5, { 5'b00100, 8'd1 } );
pgwrite_data( 6, { 5'b00010, 8'd5 } );
pgwrite_data( 7, { 5'b00001, 8'd0 } ); // stop
pgend();
pgwrite_ctrl( 1, 40); // period
pgwrite_ctrl( 0, {24'd0, 8'b10000000}); // loop
pgend();
#160 trigger = 1;
#40 trigger = 0;
#80 pgwrite_ctrl(0, {24'd0, 8'b10000001}); // start
pgend();
@(negedge pg.running);
#100 $stop(2);
end
patterngenerator pg
(
.csi_clock_clk(clk),
.csi_clock_reset(reset),
.avs_ctrl_address(address[0]),
.avs_ctrl_read(read_ctrl),
.avs_ctrl_readdata(readdata),
.avs_ctrl_write(write_ctrl),
.avs_ctrl_writedata(writedata),
.avs_data_address(address),
.avs_data_write(write_data),
.avs_data_byteenable(byteenable),
.avs_data_writedata(writedata[15:0]),
.clkena(sync),
.trigger(trigger),
.pgout(signal)
);
endmodule
|
// -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Data Up-Sizer
// Mirror data for simple accesses.
// Merge data for burst.
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// ddr_w_upsizer
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module mig_7series_v4_0_ddr_w_upsizer #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_S_AXI_DATA_WIDTH = 32'h00000020,
// Width of S_AXI_WDATA and S_AXI_RDATA.
// Format: Bit32;
// Range: 'h00000020, 'h00000040, 'h00000080, 'h00000100.
parameter C_M_AXI_DATA_WIDTH = 32'h00000040,
// Width of M_AXI_WDATA and M_AXI_RDATA.
// Assume greater than or equal to C_S_AXI_DATA_WIDTH.
// Format: Bit32;
// Range: 'h00000020, 'h00000040, 'h00000080, 'h00000100.
parameter integer C_M_AXI_REGISTER = 0,
// Clock output data.
// Range: 0, 1
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
// 1 = Propagate all USER signals, 0 = Dont propagate.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_PACKING_LEVEL = 1,
// 0 = Never pack (expander only); packing logic is omitted.
// 1 = Pack only when CACHE[1] (Modifiable) is high.
// 2 = Always pack, regardless of sub-size transaction or Modifiable bit.
// (Required when used as helper-core by mem-con.)
parameter integer C_SUPPORT_BURSTS = 1,
// Disabled when all connected masters and slaves are AxiLite,
// allowing logic to be simplified.
parameter integer C_S_AXI_BYTES_LOG = 3,
// Log2 of number of 32bit word on SI-side.
parameter integer C_M_AXI_BYTES_LOG = 3,
// Log2 of number of 32bit word on MI-side.
parameter integer C_RATIO = 2,
// Up-Sizing ratio for data.
parameter integer C_RATIO_LOG = 1
// Log2 of Up-Sizing ratio for data.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_valid,
input wire cmd_fix,
input wire cmd_modified,
input wire cmd_complete_wrap,
input wire cmd_packed_wrap,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_first_word,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_next_word,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_last_word,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_offset,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_mask,
input wire [C_S_AXI_BYTES_LOG:0] cmd_step,
input wire [8-1:0] cmd_length,
output wire cmd_ready,
// Slave Interface Write Data Ports
input wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Master Interface Write Data Ports
output wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for SI-side word lanes on MI-side.
genvar word_cnt;
// Generate variable for intra SI-word byte control (on MI-side) for always pack.
genvar byte_cnt;
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam integer C_NEVER_PACK = 0;
localparam integer C_DEFAULT_PACK = 1;
localparam integer C_ALWAYS_PACK = 2;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Sub-word handling.
wire sel_first_word;
wire first_word;
wire [C_M_AXI_BYTES_LOG-1:0] current_word_1;
wire [C_M_AXI_BYTES_LOG-1:0] current_word;
wire [C_M_AXI_BYTES_LOG-1:0] current_word_adjusted;
wire [C_RATIO-1:0] current_word_idx;
wire last_beat;
wire last_word;
wire last_word_extra_carry;
wire [C_M_AXI_BYTES_LOG-1:0] cmd_step_i;
// Sub-word handling for the next cycle.
wire [C_M_AXI_BYTES_LOG-1:0] pre_next_word_i;
wire [C_M_AXI_BYTES_LOG-1:0] pre_next_word;
wire [C_M_AXI_BYTES_LOG-1:0] pre_next_word_1;
wire [C_M_AXI_BYTES_LOG-1:0] next_word_i;
wire [C_M_AXI_BYTES_LOG-1:0] next_word;
// Burst length handling.
wire first_mi_word;
wire [8-1:0] length_counter_1;
reg [8-1:0] length_counter;
wire [8-1:0] next_length_counter;
// Handle wrap buffering.
wire store_in_wrap_buffer_enabled;
wire store_in_wrap_buffer;
wire ARESET_or_store_in_wrap_buffer;
wire use_wrap_buffer;
reg wrap_buffer_available;
// Detect start of MI word.
wire first_si_in_mi;
// Throttling help signals.
wire word_complete_next_wrap;
wire word_complete_next_wrap_qual;
wire word_complete_next_wrap_valid;
wire word_complete_next_wrap_pop;
wire word_complete_next_wrap_last;
wire word_complete_next_wrap_stall;
wire word_complete_last_word;
wire word_complete_rest;
wire word_complete_rest_qual;
wire word_complete_rest_valid;
wire word_complete_rest_pop;
wire word_complete_rest_last;
wire word_complete_rest_stall;
wire word_completed;
wire word_completed_qualified;
wire cmd_ready_i;
wire pop_si_data;
wire pop_mi_data_i;
wire pop_mi_data;
wire mi_stalling;
// Internal SI side control signals.
wire S_AXI_WREADY_I;
// Internal packed write data.
wire use_expander_data;
wire [C_M_AXI_DATA_WIDTH/8-1:0] wdata_qualifier; // For FPGA only
wire [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_qualifier; // For FPGA only
wire [C_M_AXI_DATA_WIDTH/8-1:0] wrap_qualifier; // For FPGA only
wire [C_M_AXI_DATA_WIDTH-1:0] wdata_buffer_i; // For FPGA only
wire [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_buffer_i; // For FPGA only
reg [C_M_AXI_DATA_WIDTH-1:0] wdata_buffer_q; // For RTL only
reg [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_buffer_q; // For RTL only
wire [C_M_AXI_DATA_WIDTH-1:0] wdata_buffer;
wire [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_buffer;
reg [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER_II;
reg [C_M_AXI_DATA_WIDTH-1:0] wdata_last_word_mux;
reg [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_last_word_mux;
reg [C_M_AXI_DATA_WIDTH-1:0] wdata_wrap_buffer_cmb; // For FPGA only
reg [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_wrap_buffer_cmb; // For FPGA only
reg [C_M_AXI_DATA_WIDTH-1:0] wdata_wrap_buffer_q; // For RTL only
reg [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_wrap_buffer_q; // For RTL only
wire [C_M_AXI_DATA_WIDTH-1:0] wdata_wrap_buffer;
wire [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_wrap_buffer;
// Internal signals for MI-side.
wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA_cmb; // For FPGA only
wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA_q; // For FPGA only
reg [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA_I;
wire [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB_cmb; // For FPGA only
wire [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB_q; // For FPGA only
reg [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB_I;
wire M_AXI_WLAST_I;
reg [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER_I;
wire M_AXI_WVALID_I;
wire M_AXI_WREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// Data on the MI-side is available when data a complete word has been
// assembled from the data on SI-side (and potentially from any remainder in
// the wrap buffer).
// No data is produced on the MI-side when a unaligned packed wrap is
// encountered, instead it stored in the wrap buffer to be used when the
// last SI-side data beat is received.
//
// The command is popped from the command queue once the last beat on the
// SI-side has been ackowledged.
//
// The packing process is stalled when a new MI-side is completed but not
// yet acknowledged (by ready).
//
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_RATIO_LOG > 1 ) begin : USE_LARGE_UPSIZING
assign cmd_step_i = {{C_RATIO_LOG-1{1'b0}}, cmd_step};
end else begin : NO_LARGE_UPSIZING
assign cmd_step_i = cmd_step;
end
endgenerate
generate
if ( C_FAMILY == "rtl" || ( C_SUPPORT_BURSTS == 0 ) ||
( C_PACKING_LEVEL == C_NEVER_PACK ) ) begin : USE_RTL_WORD_COMPLETED
// Detect when MI-side word is completely assembled.
assign word_completed = ( cmd_fix ) |
( ~cmd_fix & ~cmd_complete_wrap & next_word == {C_M_AXI_BYTES_LOG{1'b0}} ) |
( ~cmd_fix & last_word ) |
( ~cmd_modified ) |
( C_PACKING_LEVEL == C_NEVER_PACK ) |
( C_SUPPORT_BURSTS == 0 );
assign word_completed_qualified = word_completed & cmd_valid & ~store_in_wrap_buffer_enabled;
// RTL equivalent of optimized partial extressions (address wrap for next word).
assign word_complete_next_wrap = ( ~cmd_fix & ~cmd_complete_wrap &
next_word == {C_M_AXI_BYTES_LOG{1'b0}} ) |
( C_PACKING_LEVEL == C_NEVER_PACK ) |
( C_SUPPORT_BURSTS == 0 );
assign word_complete_next_wrap_qual = word_complete_next_wrap & cmd_valid & ~store_in_wrap_buffer_enabled;
assign word_complete_next_wrap_valid = word_complete_next_wrap_qual & S_AXI_WVALID;
assign word_complete_next_wrap_pop = word_complete_next_wrap_valid & M_AXI_WREADY_I;
assign word_complete_next_wrap_last = word_complete_next_wrap_pop & M_AXI_WLAST_I;
assign word_complete_next_wrap_stall = word_complete_next_wrap_valid & ~M_AXI_WREADY_I;
// RTL equivalent of optimized partial extressions (last word and the remaining).
assign word_complete_last_word = last_word & ~cmd_fix;
assign word_complete_rest = word_complete_last_word | cmd_fix | ~cmd_modified;
assign word_complete_rest_qual = word_complete_rest & cmd_valid & ~store_in_wrap_buffer_enabled;
assign word_complete_rest_valid = word_complete_rest_qual & S_AXI_WVALID;
assign word_complete_rest_pop = word_complete_rest_valid & M_AXI_WREADY_I;
assign word_complete_rest_last = word_complete_rest_pop & M_AXI_WLAST_I;
assign word_complete_rest_stall = word_complete_rest_valid & ~M_AXI_WREADY_I;
end else begin : USE_FPGA_WORD_COMPLETED
wire next_word_wrap;
wire sel_word_complete_next_wrap;
wire sel_word_complete_next_wrap_qual;
wire sel_word_complete_next_wrap_stall;
wire sel_last_word;
wire sel_word_complete_rest;
wire sel_word_complete_rest_qual;
wire sel_word_complete_rest_stall;
// Optimize next word address wrap branch of expression.
//
mig_7series_v4_0_ddr_comparator_sel_static #
(
.C_FAMILY(C_FAMILY),
.C_VALUE({C_M_AXI_BYTES_LOG{1'b0}}),
.C_DATA_WIDTH(C_M_AXI_BYTES_LOG)
) next_word_wrap_inst
(
.CIN(1'b1),
.S(sel_first_word),
.A(pre_next_word_1),
.B(cmd_next_word),
.COUT(next_word_wrap)
);
assign sel_word_complete_next_wrap = ~cmd_fix & ~cmd_complete_wrap;
mig_7series_v4_0_ddr_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_inst
(
.CIN(next_word_wrap),
.S(sel_word_complete_next_wrap),
.COUT(word_complete_next_wrap)
);
assign sel_word_complete_next_wrap_qual = cmd_valid & ~store_in_wrap_buffer_enabled;
mig_7series_v4_0_ddr_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_valid_inst
(
.CIN(word_complete_next_wrap),
.S(sel_word_complete_next_wrap_qual),
.COUT(word_complete_next_wrap_qual)
);
mig_7series_v4_0_ddr_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_qual_inst
(
.CIN(word_complete_next_wrap_qual),
.S(S_AXI_WVALID),
.COUT(word_complete_next_wrap_valid)
);
mig_7series_v4_0_ddr_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_pop_inst
(
.CIN(word_complete_next_wrap_valid),
.S(M_AXI_WREADY_I),
.COUT(word_complete_next_wrap_pop)
);
assign sel_word_complete_next_wrap_stall = ~M_AXI_WREADY_I;
mig_7series_v4_0_ddr_carry_latch_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_stall_inst
(
.CIN(word_complete_next_wrap_valid),
.I(sel_word_complete_next_wrap_stall),
.O(word_complete_next_wrap_stall)
);
mig_7series_v4_0_ddr_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_last_inst
(
.CIN(word_complete_next_wrap_pop),
.S(M_AXI_WLAST_I),
.COUT(word_complete_next_wrap_last)
);
// Optimize last word and "rest" branch of expression.
//
assign sel_last_word = ~cmd_fix;
mig_7series_v4_0_ddr_carry_and #
(
.C_FAMILY(C_FAMILY)
) last_word_inst_2
(
.CIN(last_word_extra_carry),
.S(sel_last_word),
.COUT(word_complete_last_word)
);
assign sel_word_complete_rest = cmd_fix | ~cmd_modified;
mig_7series_v4_0_ddr_carry_or #
(
.C_FAMILY(C_FAMILY)
) pop_si_data_inst
(
.CIN(word_complete_last_word),
.S(sel_word_complete_rest),
.COUT(word_complete_rest)
);
assign sel_word_complete_rest_qual = cmd_valid & ~store_in_wrap_buffer_enabled;
mig_7series_v4_0_ddr_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_rest_valid_inst
(
.CIN(word_complete_rest),
.S(sel_word_complete_rest_qual),
.COUT(word_complete_rest_qual)
);
mig_7series_v4_0_ddr_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_rest_qual_inst
(
.CIN(word_complete_rest_qual),
.S(S_AXI_WVALID),
.COUT(word_complete_rest_valid)
);
mig_7series_v4_0_ddr_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_rest_pop_inst
(
.CIN(word_complete_rest_valid),
.S(M_AXI_WREADY_I),
.COUT(word_complete_rest_pop)
);
assign sel_word_complete_rest_stall = ~M_AXI_WREADY_I;
mig_7series_v4_0_ddr_carry_latch_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_rest_stall_inst
(
.CIN(word_complete_rest_valid),
.I(sel_word_complete_rest_stall),
.O(word_complete_rest_stall)
);
mig_7series_v4_0_ddr_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_rest_last_inst
(
.CIN(word_complete_rest_pop),
.S(M_AXI_WLAST_I),
.COUT(word_complete_rest_last)
);
// Combine the two branches to generate the full signal.
assign word_completed = word_complete_next_wrap | word_complete_rest;
assign word_completed_qualified = word_complete_next_wrap_qual | word_complete_rest_qual;
end
endgenerate
// Pop word from SI-side.
assign S_AXI_WREADY_I = ~mi_stalling & cmd_valid;
assign S_AXI_WREADY = S_AXI_WREADY_I;
// Indicate when there is data available @ MI-side.
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_M_WVALID
assign M_AXI_WVALID_I = S_AXI_WVALID & word_completed_qualified;
end else begin : USE_FPGA_M_WVALID
assign M_AXI_WVALID_I = ( word_complete_next_wrap_valid | word_complete_rest_valid);
end
endgenerate
// Get SI-side data.
generate
if ( C_M_AXI_REGISTER ) begin : USE_REGISTER_SI_POP
assign pop_si_data = S_AXI_WVALID & ~mi_stalling & cmd_valid;
end else begin : NO_REGISTER_SI_POP
if ( C_FAMILY == "rtl" ) begin : USE_RTL_POP_SI
assign pop_si_data = S_AXI_WVALID & S_AXI_WREADY_I;
end else begin : USE_FPGA_POP_SI
assign pop_si_data = ~( word_complete_next_wrap_stall | word_complete_rest_stall ) &
cmd_valid & S_AXI_WVALID;
end
end
endgenerate
// Signal that the command is done (so that it can be poped from command queue).
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_CMD_READY
assign cmd_ready_i = cmd_valid & M_AXI_WLAST_I & pop_mi_data_i;
end else begin : USE_FPGA_CMD_READY
assign cmd_ready_i = ( word_complete_next_wrap_last | word_complete_rest_last);
end
endgenerate
assign cmd_ready = cmd_ready_i;
// Set last upsized word.
assign M_AXI_WLAST_I = S_AXI_WLAST;
/////////////////////////////////////////////////////////////////////////////
// Keep track of data extraction:
//
// Current address is taken form the command buffer for the first data beat
// to handle unaligned Write transactions. After this is the extraction
// address usually calculated from this point.
// FIX transactions uses the same word address for all data beats.
//
// Next word address is generated as current word plus the current step
// size, with masking to facilitate sub-sized wraping. The Mask is all ones
// for normal wraping, and less when sub-sized wraping is used.
//
// The calculated word addresses (current and next) is offseted by the
// current Offset. For sub-sized transaction the Offest points to the least
// significant address of the included data beats. (The least significant
// word is not necessarily the first data to be packed, consider WRAP).
// Offset is only used for sub-sized WRAP transcation that are Complete.
//
// First word is active during the first SI-side data beat.
//
// First MI is set while the entire first MI-side word is processed.
//
// The transaction length is taken from the command buffer combinatorialy
// during the First MI cycle. For each generated MI word it is decreased
// until Last beat is reached.
//
/////////////////////////////////////////////////////////////////////////////
// Select if the offset comes from command queue directly or
// from a counter while when extracting multiple SI words per MI word
assign sel_first_word = first_word | cmd_fix;
assign current_word = sel_first_word ? cmd_first_word :
current_word_1;
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_NEXT_WORD
// Calculate next word.
assign pre_next_word_i = ( next_word_i + cmd_step_i );
// Calculate next word.
assign next_word_i = sel_first_word ? cmd_next_word :
pre_next_word_1;
end else begin : USE_FPGA_NEXT_WORD
wire [C_M_AXI_BYTES_LOG-1:0] next_sel;
wire [C_M_AXI_BYTES_LOG:0] next_carry_local;
// Assign input to local vectors.
assign next_carry_local[0] = 1'b0;
// Instantiate one carry and per level.
for (bit_cnt = 0; bit_cnt < C_M_AXI_BYTES_LOG ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
LUT6_2 # (
.INIT(64'h5A5A_5A66_F0F0_F0CC)
) LUT6_2_inst (
.O6(next_sel[bit_cnt]), // 6/5-LUT output (1-bit)
.O5(next_word_i[bit_cnt]), // 5-LUT output (1-bit)
.I0(cmd_step_i[bit_cnt]), // LUT input (1-bit)
.I1(pre_next_word_1[bit_cnt]), // LUT input (1-bit)
.I2(cmd_next_word[bit_cnt]), // LUT input (1-bit)
.I3(first_word), // LUT input (1-bit)
.I4(cmd_fix), // LUT input (1-bit)
.I5(1'b1) // LUT input (1-bit)
);
MUXCY next_carry_inst
(
.O (next_carry_local[bit_cnt+1]),
.CI (next_carry_local[bit_cnt]),
.DI (cmd_step_i[bit_cnt]),
.S (next_sel[bit_cnt])
);
XORCY next_xorcy_inst
(
.O(pre_next_word_i[bit_cnt]),
.CI(next_carry_local[bit_cnt]),
.LI(next_sel[bit_cnt])
);
end // end for bit_cnt
end
endgenerate
// Calculate next word.
assign next_word = next_word_i & cmd_mask;
assign pre_next_word = pre_next_word_i & cmd_mask;
// Calculate the word address with offset.
assign current_word_adjusted = sel_first_word ? ( cmd_first_word | cmd_offset ) :
( current_word_1 | cmd_offset );
// Prepare next word address.
generate
if ( C_FAMILY == "rtl" || C_M_AXI_REGISTER ) begin : USE_RTL_CURR_WORD
reg [C_M_AXI_BYTES_LOG-1:0] current_word_q;
reg first_word_q;
reg [C_M_AXI_BYTES_LOG-1:0] pre_next_word_q;
always @ (posedge ACLK) begin
if (ARESET) begin
first_word_q <= 1'b1;
current_word_q <= {C_M_AXI_BYTES_LOG{1'b0}};
pre_next_word_q <= {C_M_AXI_BYTES_LOG{1'b0}};
end else begin
if ( pop_si_data ) begin
if ( S_AXI_WLAST ) begin
// Prepare for next access.
first_word_q <= 1'b1;
end else begin
first_word_q <= 1'b0;
end
current_word_q <= next_word;
pre_next_word_q <= pre_next_word;
end
end
end
assign first_word = first_word_q;
assign current_word_1 = current_word_q;
assign pre_next_word_1 = pre_next_word_q;
end else begin : USE_FPGA_CURR_WORD
reg first_word_cmb;
wire first_word_i;
wire [C_M_AXI_BYTES_LOG-1:0] current_word_i;
wire [C_M_AXI_BYTES_LOG-1:0] local_pre_next_word_i;
always @ *
begin
if ( S_AXI_WLAST ) begin
// Prepare for next access.
first_word_cmb = 1'b1;
end else begin
first_word_cmb = 1'b0;
end
end
for (bit_cnt = 0; bit_cnt < C_M_AXI_BYTES_LOG ; bit_cnt = bit_cnt + 1) begin : BIT_LANE
LUT6 # (
.INIT(64'hCCCA_CCCC_CCCC_CCCC)
) LUT6_current_inst (
.O(current_word_i[bit_cnt]), // 6-LUT output (1-bit)
.I0(next_word[bit_cnt]), // LUT input (1-bit)
.I1(current_word_1[bit_cnt]), // LUT input (1-bit)
.I2(word_complete_rest_stall), // LUT input (1-bit)
.I3(word_complete_next_wrap_stall), // LUT input (1-bit)
.I4(cmd_valid), // LUT input (1-bit)
.I5(S_AXI_WVALID) // LUT input (1-bit)
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_current_inst (
.Q(current_word_1[bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(current_word_i[bit_cnt]) // Data input
);
LUT6 # (
.INIT(64'hCCCA_CCCC_CCCC_CCCC)
) LUT6_next_inst (
.O(local_pre_next_word_i[bit_cnt]), // 6-LUT output (1-bit)
.I0(pre_next_word[bit_cnt]), // LUT input (1-bit)
.I1(pre_next_word_1[bit_cnt]), // LUT input (1-bit)
.I2(word_complete_rest_stall), // LUT input (1-bit)
.I3(word_complete_next_wrap_stall), // LUT input (1-bit)
.I4(cmd_valid), // LUT input (1-bit)
.I5(S_AXI_WVALID) // LUT input (1-bit)
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_next_inst (
.Q(pre_next_word_1[bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(local_pre_next_word_i[bit_cnt]) // Data input
);
end // end for bit_cnt
LUT6 # (
.INIT(64'hCCCA_CCCC_CCCC_CCCC)
) LUT6_first_inst (
.O(first_word_i), // 6-LUT output (1-bit)
.I0(first_word_cmb), // LUT input (1-bit)
.I1(first_word), // LUT input (1-bit)
.I2(word_complete_rest_stall), // LUT input (1-bit)
.I3(word_complete_next_wrap_stall), // LUT input (1-bit)
.I4(cmd_valid), // LUT input (1-bit)
.I5(S_AXI_WVALID) // LUT input (1-bit)
);
FDSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) FDSE_first_inst (
.Q(first_word), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.S(ARESET), // Synchronous reset input
.D(first_word_i) // Data input
);
end
endgenerate
// Select command length or counted length.
always @ *
begin
if ( first_mi_word )
length_counter = cmd_length;
else
length_counter = length_counter_1;
end
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_LENGTH
reg [8-1:0] length_counter_q;
reg first_mi_word_q;
// Calculate next length counter value.
assign next_length_counter = length_counter - 1'b1;
// Keep track of burst length.
always @ (posedge ACLK) begin
if (ARESET) begin
first_mi_word_q <= 1'b1;
length_counter_q <= 8'b0;
end else begin
if ( pop_mi_data_i ) begin
if ( M_AXI_WLAST_I ) begin
first_mi_word_q <= 1'b1;
end else begin
first_mi_word_q <= 1'b0;
end
length_counter_q <= next_length_counter;
end
end
end
assign first_mi_word = first_mi_word_q;
assign length_counter_1 = length_counter_q;
end else begin : USE_FPGA_LENGTH
wire [8-1:0] length_counter_i;
wire [8-1:0] length_counter_ii;
wire [8-1:0] length_sel;
wire [8-1:0] length_di;
wire [8:0] length_local_carry;
// Assign input to local vectors.
assign length_local_carry[0] = 1'b0;
for (bit_cnt = 0; bit_cnt < 8 ; bit_cnt = bit_cnt + 1) begin : BIT_LANE
LUT6_2 # (
.INIT(64'h333C_555A_FFF0_FFF0)
) LUT6_length_inst (
.O6(length_sel[bit_cnt]), // 6/5-LUT output (1-bit)
.O5(length_di[bit_cnt]), // 5-LUT output (1-bit)
.I0(length_counter_1[bit_cnt]), // LUT input (1-bit)
.I1(cmd_length[bit_cnt]), // LUT input (1-bit)
.I2(1'b1), // LUT input (1-bit)
.I3(1'b1), // LUT input (1-bit)
.I4(first_mi_word), // LUT input (1-bit)
.I5(1'b1) // LUT input (1-bit)
);
MUXCY carry_inst
(
.O (length_local_carry[bit_cnt+1]),
.CI (length_local_carry[bit_cnt]),
.DI (length_di[bit_cnt]),
.S (length_sel[bit_cnt])
);
XORCY xorcy_inst
(
.O(length_counter_ii[bit_cnt]),
.CI(length_local_carry[bit_cnt]),
.LI(length_sel[bit_cnt])
);
LUT4 # (
.INIT(16'hCCCA)
) LUT4_inst (
.O(length_counter_i[bit_cnt]), // 5-LUT output (1-bit)
.I0(length_counter_1[bit_cnt]), // LUT input (1-bit)
.I1(length_counter_ii[bit_cnt]), // LUT input (1-bit)
.I2(word_complete_rest_pop), // LUT input (1-bit)
.I3(word_complete_next_wrap_pop) // LUT input (1-bit)
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_length_inst (
.Q(length_counter_1[bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(length_counter_i[bit_cnt]) // Data input
);
end // end for bit_cnt
wire first_mi_word_i;
LUT6 # (
.INIT(64'hAAAC_AAAC_AAAC_AAAC)
) LUT6_first_mi_inst (
.O(first_mi_word_i), // 6-LUT output (1-bit)
.I0(M_AXI_WLAST_I), // LUT input (1-bit)
.I1(first_mi_word), // LUT input (1-bit)
.I2(word_complete_rest_pop), // LUT input (1-bit)
.I3(word_complete_next_wrap_pop), // LUT input (1-bit)
.I4(1'b1), // LUT input (1-bit)
.I5(1'b1) // LUT input (1-bit)
);
FDSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) FDSE_inst (
.Q(first_mi_word), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.S(ARESET), // Synchronous reset input
.D(first_mi_word_i) // Data input
);
end
endgenerate
generate
if ( C_FAMILY == "rtl" || C_SUPPORT_BURSTS == 0 ) begin : USE_RTL_LAST_WORD
// Detect last beat in a burst.
assign last_beat = ( length_counter == 8'b0 );
// Determine if this last word that shall be assembled into this MI-side word.
assign last_word = ( cmd_modified & last_beat & ( current_word == cmd_last_word ) ) |
( C_SUPPORT_BURSTS == 0 );
end else begin : USE_FPGA_LAST_WORD
wire last_beat_curr_word;
mig_7series_v4_0_ddr_comparator_sel_static #
(
.C_FAMILY(C_FAMILY),
.C_VALUE(8'b0),
.C_DATA_WIDTH(8)
) last_beat_inst
(
.CIN(1'b1),
.S(first_mi_word),
.A(length_counter_1),
.B(cmd_length),
.COUT(last_beat)
);
mig_7series_v4_0_ddr_comparator_sel #
(
.C_FAMILY(C_FAMILY),
.C_DATA_WIDTH(C_M_AXI_BYTES_LOG)
) last_beat_curr_word_inst
(
.CIN(last_beat),
.S(sel_first_word),
.A(current_word_1),
.B(cmd_first_word),
.V(cmd_last_word),
.COUT(last_beat_curr_word)
);
mig_7series_v4_0_ddr_carry_and #
(
.C_FAMILY(C_FAMILY)
) last_word_inst
(
.CIN(last_beat_curr_word),
.S(cmd_modified),
.COUT(last_word)
);
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Handle wrap buffer:
//
// The wrap buffer is used to move data around in an unaligned WRAP
// transaction. SI-side data word(s) for an unaligned accesses are delay
// to be packed with with the tail of the transaction to make it a WRAP
// transaction that is aligned to native MI-side data with.
// For example: an 32bit to 64bit write upsizing @ 0x4 will delay the first
// word until the 0x0 data arrives in the last data beat. This will make the
// Upsized transaction be WRAP at 0x8 on the MI-side
// (was WRAP @ 0x4 on SI-side).
//
/////////////////////////////////////////////////////////////////////////////
// The unaligned SI-side words are pushed into the wrap buffer.
assign store_in_wrap_buffer_enabled = cmd_packed_wrap & ~wrap_buffer_available & cmd_valid;
assign store_in_wrap_buffer = store_in_wrap_buffer_enabled & S_AXI_WVALID;
assign ARESET_or_store_in_wrap_buffer = store_in_wrap_buffer | ARESET;
// The wrap buffer is used to complete last word.
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_USE_WRAP
assign use_wrap_buffer = wrap_buffer_available & last_word;
end else begin : USE_FPGA_USE_WRAP
wire last_word_carry;
mig_7series_v4_0_ddr_carry_and #
(
.C_FAMILY(C_FAMILY)
) last_word_inst2
(
.CIN(last_word),
.S(1'b1),
.COUT(last_word_carry)
);
mig_7series_v4_0_ddr_carry_and #
(
.C_FAMILY(C_FAMILY)
) last_word_inst3
(
.CIN(last_word_carry),
.S(1'b1),
.COUT(last_word_extra_carry)
);
mig_7series_v4_0_ddr_carry_latch_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_stall_inst
(
.CIN(last_word_carry),
.I(wrap_buffer_available),
.O(use_wrap_buffer)
);
end
endgenerate
// Wrap buffer becomes available when the unaligned wrap words has been taken care of.
always @ (posedge ACLK) begin
if (ARESET) begin
wrap_buffer_available <= 1'b0;
end else begin
if ( store_in_wrap_buffer & word_completed ) begin
wrap_buffer_available <= 1'b1;
end else if ( cmd_ready_i ) begin
wrap_buffer_available <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Handle USER bits:
//
// The USER bits are always propagated from the least significant SI-side
// beat to the Up-Sized MI-side data beat. That means:
// * FIX transactions propagate all USER data (1:1 SI- vs MI-side beat ratio).
// * INCR transactions uses the first SI-side beat that goes into a MI-side
// data word.
// * WRAP always propagates the USER bits from the most zero aligned SI-side
// data word, regardless if the data is packed or not. For unpacked data
// this would be a 1:1 ratio.
/////////////////////////////////////////////////////////////////////////////
// Detect first SI-side word per MI-side word.
assign first_si_in_mi = cmd_fix |
first_word |
~cmd_modified |
(cmd_modified & current_word == {C_M_AXI_BYTES_LOG{1'b0}}) |
( C_SUPPORT_BURSTS == 0 );
// Select USER bits combinatorially when expanding or fix.
always @ *
begin
if ( C_AXI_SUPPORTS_USER_SIGNALS ) begin
if ( first_si_in_mi ) begin
M_AXI_WUSER_I = S_AXI_WUSER;
end else begin
M_AXI_WUSER_I = M_AXI_WUSER_II;
end
end else begin
M_AXI_WUSER_I = {C_AXI_WUSER_WIDTH{1'b0}};
end
end
// Capture user bits.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_WUSER_II <= {C_AXI_WUSER_WIDTH{1'b0}};
end else begin
if ( first_si_in_mi & pop_si_data ) begin
M_AXI_WUSER_II <= S_AXI_WUSER;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pack multiple data SI-side words into fewer MI-side data word.
// Data is only packed when modify is set. Granularity is SI-side word for
// the combinatorial data mux.
//
// Expander:
// WDATA is expanded to all SI-word lane on the MI-side.
// WSTRB is activted to the correct SI-word lane on the MI-side.
//
// Packer:
// The WDATA and WSTRB registers are always cleared before a new word is
// assembled.
// WDATA is (SI-side word granularity)
// * Combinatorial WDATA is used for current word line or when expanding.
// * All other is taken from registers.
// WSTRB is
// * Combinatorial for single data to matching word lane
// * Zero for single data to mismatched word lane
// * Register data when multiple data
//
// To support sub-sized packing during Always Pack is the combinatorial
// information packed with "or" instead of multiplexing.
//
/////////////////////////////////////////////////////////////////////////////
// Determine if expander data should be used.
assign use_expander_data = ~cmd_modified & cmd_valid;
// Registers and combinatorial data word mux.
generate
for (word_cnt = 0; word_cnt < C_RATIO ; word_cnt = word_cnt + 1) begin : WORD_LANE
// Generate select signal per SI-side word.
if ( C_RATIO == 1 ) begin : SINGLE_WORD
assign current_word_idx[word_cnt] = 1'b1;
end else begin : MULTIPLE_WORD
assign current_word_idx[word_cnt] = current_word_adjusted[C_M_AXI_BYTES_LOG-C_RATIO_LOG +: C_RATIO_LOG] == word_cnt;
end
if ( ( C_PACKING_LEVEL == C_NEVER_PACK ) | ( C_SUPPORT_BURSTS == 0 ) ) begin : USE_EXPANDER
// Expander only functionality.
if ( C_M_AXI_REGISTER ) begin : USE_REGISTER
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH +: C_S_AXI_DATA_WIDTH] = {C_S_AXI_DATA_WIDTH{1'b0}};
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8 +: C_S_AXI_DATA_WIDTH/8] = {C_S_AXI_DATA_WIDTH/8{1'b0}};
end else begin
if ( pop_si_data ) begin
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH +: C_S_AXI_DATA_WIDTH] = S_AXI_WDATA;
// Multiplex write strobe.
if ( current_word_idx[word_cnt] ) begin
// Combinatorial for last word to MI-side (only word for single).
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8 +: C_S_AXI_DATA_WIDTH/8] = S_AXI_WSTRB;
end else begin
// Use registered strobes. Registers are zero until valid data is written.
// I.e. zero when used for mismatched lanes while expanding.
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8 +: C_S_AXI_DATA_WIDTH/8] = {C_S_AXI_DATA_WIDTH/8{1'b0}};
end
end
end
end
end else begin : NO_REGISTER
always @ *
begin
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH +: C_S_AXI_DATA_WIDTH] = S_AXI_WDATA;
// Multiplex write strobe.
if ( current_word_idx[word_cnt] ) begin
// Combinatorial for last word to MI-side (only word for single).
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8 +: C_S_AXI_DATA_WIDTH/8] = S_AXI_WSTRB;
end else begin
// Use registered strobes. Registers are zero until valid data is written.
// I.e. zero when used for mismatched lanes while expanding.
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8 +: C_S_AXI_DATA_WIDTH/8] = {C_S_AXI_DATA_WIDTH/8{1'b0}};
end
end
end // end if C_M_AXI_REGISTER
end else begin : USE_ALWAYS_PACKER
// Packer functionality
for (byte_cnt = 0; byte_cnt < C_S_AXI_DATA_WIDTH / 8 ; byte_cnt = byte_cnt + 1) begin : BYTE_LANE
if ( C_FAMILY == "rtl" ) begin : USE_RTL_DATA
// Generate extended write data and strobe in wrap buffer.
always @ (posedge ACLK) begin
if (ARESET) begin
wdata_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0;
wstrb_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0;
end else begin
if ( cmd_ready_i ) begin
wdata_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0;
wstrb_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0;
end else if ( current_word_idx[word_cnt] & store_in_wrap_buffer & S_AXI_WSTRB[byte_cnt] ) begin
wdata_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= S_AXI_WDATA[byte_cnt*8 +: 8];
wstrb_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= S_AXI_WSTRB[byte_cnt];
end
end
end
assign wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] =
wdata_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8];
assign wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] =
wstrb_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1];
if ( C_M_AXI_REGISTER ) begin : USE_REGISTER
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0;
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0;
end else begin
if ( ( current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] | use_expander_data ) & pop_si_data & ~store_in_wrap_buffer ) begin
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= S_AXI_WDATA[byte_cnt*8 +: 8];
end else if ( use_wrap_buffer & pop_si_data &
wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] ) begin
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8];
end else if ( pop_mi_data ) begin
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0;
end
if ( current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] & pop_si_data & ~store_in_wrap_buffer ) begin
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= S_AXI_WSTRB[byte_cnt];
end else if ( use_wrap_buffer & pop_si_data &
wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] ) begin
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b1;
end else if ( pop_mi_data ) begin
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0;
end
end
end
end else begin : NO_REGISTER
// Generate extended write data and strobe.
always @ (posedge ACLK) begin
if (ARESET) begin
wdata_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0;
wstrb_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0;
end else begin
if ( pop_mi_data | store_in_wrap_buffer_enabled ) begin
wdata_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0;
wstrb_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0;
end else if ( current_word_idx[word_cnt] & pop_si_data & S_AXI_WSTRB[byte_cnt] ) begin
wdata_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= S_AXI_WDATA[byte_cnt*8 +: 8];
wstrb_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= S_AXI_WSTRB[byte_cnt];
end
end
end
assign wdata_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] =
wdata_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8];
assign wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] =
wstrb_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1];
// Select packed or extended data.
always @ *
begin
// Multiplex data.
if ( ( current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] ) | use_expander_data ) begin
wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = S_AXI_WDATA[byte_cnt*8 +: 8];
end else begin
wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = 8'b0;
end
// Multiplex write strobe.
if ( current_word_idx[word_cnt] ) begin
// Combinatorial for last word to MI-side (only word for single).
wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = S_AXI_WSTRB[byte_cnt];
end else begin
// Use registered strobes. Registers are zero until valid data is written.
// I.e. zero when used for mismatched lanes while expanding.
wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = 1'b0;
end
end
// Merge previous with current data.
always @ *
begin
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] =
( wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] ) |
( wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] ) |
( wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] & use_wrap_buffer );
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] =
( wdata_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] ) |
( wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] ) |
( wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] & {8{use_wrap_buffer}} );
end
end // end if C_M_AXI_REGISTER
end else begin : USE_FPGA_DATA
always @ *
begin
if ( cmd_ready_i ) begin
wdata_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = 8'b0;
wstrb_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = 1'b0;
end else if ( current_word_idx[word_cnt] & store_in_wrap_buffer & S_AXI_WSTRB[byte_cnt] ) begin
wdata_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = S_AXI_WDATA[byte_cnt*8 +: 8];
wstrb_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = 1'b1;
end else begin
wdata_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] =
wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8];
wstrb_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] =
wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1];
end
end
for (bit_cnt = 0; bit_cnt < 8 ; bit_cnt = bit_cnt + 1) begin : BIT_LANE
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_wdata_inst (
.Q(wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(wdata_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]) // Data input
);
end // end for bit_cnt
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_wstrb_inst (
.Q(wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(wstrb_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]) // Data input
);
if ( C_M_AXI_REGISTER ) begin : USE_REGISTER
assign wdata_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] = ( current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] | use_expander_data ) & pop_si_data & ~store_in_wrap_buffer_enabled;
assign wstrb_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] = current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] & pop_si_data & ~store_in_wrap_buffer_enabled;
assign wrap_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] = use_wrap_buffer & pop_si_data &
wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1];
for (bit_cnt = 0; bit_cnt < 8 ; bit_cnt = bit_cnt + 1) begin : BIT_LANE
LUT6 # (
.INIT(64'hF0F0_F0F0_CCCC_00AA)
) LUT6_data_inst (
.O(M_AXI_WDATA_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // 6-LUT output (1-bit)
.I0(M_AXI_WDATA_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // LUT input (1-bit)
.I1(wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // LUT input (1-bit)
.I2(S_AXI_WDATA[byte_cnt*8+bit_cnt]), // LUT input (1-bit)
.I3(pop_mi_data), // LUT input (1-bit)
.I4(wrap_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)
.I5(wdata_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]) // LUT input (1-bit)
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_wdata_inst (
.Q(M_AXI_WDATA_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(M_AXI_WDATA_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]) // Data input
);
end // end for bit_cnt
LUT6 # (
.INIT(64'hF0F0_F0F0_CCCC_00AA)
) LUT6_strb_inst (
.O(M_AXI_WSTRB_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // 6-LUT output (1-bit)
.I0(M_AXI_WSTRB_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)
.I1(wrap_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)
.I2(S_AXI_WSTRB[byte_cnt]), // LUT input (1-bit)
.I3(pop_mi_data), // LUT input (1-bit)
.I4(wrap_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)
.I5(wstrb_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]) // LUT input (1-bit)
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_wstrb_inst (
.Q(M_AXI_WSTRB_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(M_AXI_WSTRB_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]) // Data input
);
always @ *
begin
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = M_AXI_WDATA_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8];
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = M_AXI_WSTRB_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1];
end
end else begin : NO_REGISTER
assign wdata_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] = current_word_idx[word_cnt] & cmd_valid & S_AXI_WSTRB[byte_cnt];
assign wstrb_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] = current_word_idx[word_cnt] &
S_AXI_WSTRB[byte_cnt] &
cmd_valid & S_AXI_WVALID;
for (bit_cnt = 0; bit_cnt < 8 ; bit_cnt = bit_cnt + 1) begin : BIT_LANE
LUT6 # (
.INIT(64'hCCCA_CCCC_CCCC_CCCC)
) LUT6_data_inst (
.O(wdata_buffer_i[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // 6-LUT output (1-bit)
.I0(S_AXI_WDATA[byte_cnt*8+bit_cnt]), // LUT input (1-bit)
.I1(wdata_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // LUT input (1-bit)
.I2(word_complete_rest_stall), // LUT input (1-bit)
.I3(word_complete_next_wrap_stall), // LUT input (1-bit)
.I4(wdata_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)
.I5(S_AXI_WVALID) // LUT input (1-bit)
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_wdata_inst (
.Q(wdata_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(wdata_buffer_i[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]) // Data input
);
end // end for bit_cnt
LUT6 # (
.INIT(64'h0000_0000_0000_AAAE)
) LUT6_strb_inst (
.O(wstrb_buffer_i[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // 6-LUT output (1-bit)
.I0(wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)
.I1(wstrb_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)
.I2(word_complete_rest_stall), // LUT input (1-bit)
.I3(word_complete_next_wrap_stall), // LUT input (1-bit)
.I4(word_complete_rest_pop), // LUT input (1-bit)
.I5(word_complete_next_wrap_pop) // LUT input (1-bit)
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_wstrb_inst (
.Q(wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET_or_store_in_wrap_buffer), // Synchronous reset input
.D(wstrb_buffer_i[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]) // Data input
);
// Select packed or extended data.
always @ *
begin
// Multiplex data.
if ( ( current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] ) | use_expander_data ) begin
wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = S_AXI_WDATA[byte_cnt*8 +: 8];
end else begin
wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] =
( wdata_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] & {8{wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]}} ) |
( wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] & {8{use_wrap_buffer}} );
end
// Multiplex write strobe.
if ( current_word_idx[word_cnt] ) begin
// Combinatorial for last word to MI-side (only word for single).
wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = S_AXI_WSTRB[byte_cnt] |
( wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] ) |
( wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] & use_wrap_buffer );
end else begin
// Use registered strobes. Registers are zero until valid data is written.
// I.e. zero when used for mismatched lanes while expanding.
wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] =
( wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] ) |
( wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] & use_wrap_buffer );
end
end
// Merge previous with current data.
always @ *
begin
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] =
( wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] );
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] =
( wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] );
end
end // end if C_M_AXI_REGISTER
end // end if C_FAMILY
end // end for byte_cnt
end // end if USE_ALWAYS_PACKER
end // end for word_cnt
endgenerate
/////////////////////////////////////////////////////////////////////////////
// MI-side output handling
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_M_AXI_REGISTER ) begin : USE_REGISTER
reg M_AXI_WLAST_q;
reg [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER_q;
reg M_AXI_WVALID_q;
// Register MI-side Data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_WLAST_q <= 1'b0;
M_AXI_WUSER_q <= {C_AXI_WUSER_WIDTH{1'b0}};
M_AXI_WVALID_q <= 1'b0;
end else begin
if ( M_AXI_WREADY_I ) begin
M_AXI_WLAST_q <= M_AXI_WLAST_I;
M_AXI_WUSER_q <= M_AXI_WUSER_I;
M_AXI_WVALID_q <= M_AXI_WVALID_I;
end
end
end
assign M_AXI_WDATA = M_AXI_WDATA_I;
assign M_AXI_WSTRB = M_AXI_WSTRB_I;
assign M_AXI_WLAST = M_AXI_WLAST_q;
assign M_AXI_WUSER = M_AXI_WUSER_q;
assign M_AXI_WVALID = M_AXI_WVALID_q;
assign M_AXI_WREADY_I = ( M_AXI_WVALID_q & M_AXI_WREADY) | ~M_AXI_WVALID_q;
// Get MI-side data.
assign pop_mi_data_i = M_AXI_WVALID_I & M_AXI_WREADY_I;
assign pop_mi_data = M_AXI_WVALID_q & M_AXI_WREADY_I;
// Detect when MI-side is stalling.
assign mi_stalling = ( M_AXI_WVALID_q & ~M_AXI_WREADY_I ) & ~store_in_wrap_buffer_enabled;
end else begin : NO_REGISTER
// Combinatorial MI-side Data.
assign M_AXI_WDATA = M_AXI_WDATA_I;
assign M_AXI_WSTRB = M_AXI_WSTRB_I;
assign M_AXI_WLAST = M_AXI_WLAST_I;
assign M_AXI_WUSER = M_AXI_WUSER_I;
assign M_AXI_WVALID = M_AXI_WVALID_I;
assign M_AXI_WREADY_I = M_AXI_WREADY;
// Get MI-side data.
if ( C_FAMILY == "rtl" ) begin : USE_RTL_POP_MI
assign pop_mi_data_i = M_AXI_WVALID_I & M_AXI_WREADY_I;
end else begin : USE_FPGA_POP_MI
assign pop_mi_data_i = ( word_complete_next_wrap_pop | word_complete_rest_pop);
end
assign pop_mi_data = pop_mi_data_i;
// Detect when MI-side is stalling.
assign mi_stalling = word_completed_qualified & ~M_AXI_WREADY_I;
end
endgenerate
endmodule
|
////////////////////////////////////////////////////////////////////////////////
//
// Filename: speechfifo.v
// {{{
// Project: wbuart32, a full featured UART with simulator
//
// Purpose: To test/demonstrate/prove the wishbone access to the FIFO'd
// UART via sending more information than the FIFO can hold,
// and then verifying that this was the value received.
//
// To do this, we "borrow" a copy of Abraham Lincolns Gettysburg address,
// make that the FIFO isn't large enough to hold it, and then try
// to send this address every couple of minutes.
//
// With some minor modifications (discussed below), this RTL should be
// able to be run as a top-level testing file, requiring only that the
// clock and the transmit UART pins be working.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
// }}}
// Copyright (C) 2015-2021, Gisselquist Technology, LLC
// {{{
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
// One issue with the design is how to set the values of the setup register.
// (*This is a comment, not a verilator attribute ... ) Verilator needs to
// know/set those values in order to work. However, this design can also be
// used as a stand-alone top level configuration file. In this latter case,
// the setup register needs to be set internal to the file. Here, we use
// OPT_STANDALONE to distinguish between the two. If set, the file runs under
// (* Another comment still ...) Verilator and we need to get i_setup from the
// external environment. If not, it must be set internally.
//
`ifndef VERILATOR
`define OPT_STANDALONE
`endif
// }}}
module speechfifo #(
// {{{
// Here we set i_setup to something appropriate to create a
// 115200 Baud UART system from a 100MHz clock. This also sets
// us to an 8-bit data word, 1-stop bit, and no parity (for the
// non-LITE UART). This will be overwritten by i_setup (if
// present), but at least it gives us something to start
// with/from.
parameter INITIAL_UART_SETUP = 31'd868,
// Let's set our message length, in case we ever wish to change
// it in the future
localparam MSGLEN=2203
// }}}
) (
// {{{
input wire i_clk,
`ifndef OPT_STANDALONE
input wire [30:0] i_setup,
`endif
output wire o_uart_tx
// }}}
);
// Signal declarations
// {{{
reg restart;
reg wb_stb;
reg [1:0] wb_addr;
reg [31:0] wb_data;
wire uart_stall;
// We aren't using the receive interrupts, or the received data, or the
// ready to send line, so we'll just mark them all here as ignored.
/* verilator lint_off UNUSED */
wire uart_ack, tx_int;
wire [31:0] uart_data;
wire ignored_rx_int, ignored_rxfifo_int;
wire rts_n_ignored;
/* verilator lint_on UNUSED */
reg pwr_reset;
reg [7:0] message [0:4095];
reg [30:0] restart_counter;
reg [11:0] msg_index;
reg end_of_message;
wire cts_n;
wire txfifo_int;
// }}}
// i_setup
// {{{
// The i_setup wires are input when run under Verilator, but need to
// be set internally if this is going to run as a standalone top level
// test configuration.
`ifdef OPT_STANDALONE
wire [30:0] i_setup;
assign i_setup = INITIAL_UART_SETUP;
`endif
// }}}
// pwr_reset
// {{{
// The next four lines create a strobe signal that is true on the first
// clock, but never after. This makes for a decent power-on reset
// signal.
initial pwr_reset = 1'b1;
always @(posedge i_clk)
pwr_reset <= 1'b0;
// }}}
// initializing the memory
// {{{
// The message we wish to transmit is kept in "message". It needs to be
// set initially. Do so here.
//
// Since the message has fewer than 2048 elements in it, we preset every
// element to a space so that if (for some reason) we broadcast past the
// end of our message, we'll at least be sending something useful.
integer i;
initial begin
// xx Verilator needs this file to be in the directory the file
// is run from. For that reason, the project builds, makes,
// and keeps speech.hex in bench/cpp.
//
// Vivado, however, wants speech.hex to be in a project file
// directory, such as bench/verilog. For that reason, the
// build function in bench/cpp also copies speech.hex to the
// bench/verilog directory. You may need to make certain the
// file is both built, and copied into a directory where your
// synthesis tool can find it.
//
$readmemh("speech.hex", message);
for(i=MSGLEN; i<4095; i=i+1)
message[i] = 8'h20;
//
// The problem with the above approach is Xilinx's ISE program.
// It's broken. It can't handle HEX files well (at all?) and
// has more problems with HEX's defining ROM's. For that
// reason, the mkspeech program can be tuned to create an
// include file, speech.inc. We include that program here.
// It is rather ugly, though, and not a very elegant solution,
// since it walks through every value in our speech, byte by
// byte, with an initial line for each byte declaring what it
// is to be.
//
// If you (need to) use this route, comment out both the
// readmemh, the for loop, and the message[i] = 8'h20 lines
// above and uncomment the include line below.
//
// `include "speech.inc"
end
// }}}
// restart_counter
// {{{
// Let's keep track of time, and send our message over and over again.
// To do this, we'll keep track of a restart counter. When this counter
// rolls over, we restart our message.
//
// Since we want to start our message just a couple clocks after power
// up, we'll set the reset counter just a couple clocks shy of a roll
// over.
initial restart_counter = -31'd16;
always @(posedge i_clk)
restart_counter <= restart_counter+1'b1;
// }}}
// restart
// {{{
// Ok, now that we have a counter that tells us when to start over,
// let's build a set of signals that we can use to get things started
// again. This will be the restart signal. On this signal, we just
// restart everything.
initial restart = 0;
always @(posedge i_clk)
restart <= (restart_counter == 0);
// }}}
// msg_index
// {{{
// Our message index. This is the address of the character we wish to
// transmit next. Note, there's a clock delay between setting this
// index and when the wb_data is valid. Hence, we set the index on
// restart[0] to zero.
initial msg_index = 12'h000 - 12'h8;
always @(posedge i_clk)
if (restart)
msg_index <= 0;
else if ((wb_stb)&&(!uart_stall))
// We only advance the index if a port operation on the
// wbuart has taken place. That's what the
// (wb_stb)&&(!uart_stall) is about. (wb_stb) is the
// request for a transaction on the bus, uart_stall
// tells us to wait 'cause the peripheral isn't ready.
// In our case, it's always ready, uart_stall == 0, but
// we keep/maintain this logic for good form.
//
// Note also, we only advance when restart[0] is zero.
// This keeps us from advancing prior to the setup
// word.
msg_index <= msg_index + 1'b1;
// }}}
// wb_data -- What data will we be sending to the port?
// {{{
always @(posedge i_clk)
if (restart)
// The first thing we do is set the baud rate, and
// serial port configuration parameters. Ideally,
// we'd only set this once. But rather than complicate
// the logic, we set it everytime we start over.
wb_data <= { 1'b0, i_setup };
else if ((wb_stb)&&(!uart_stall))
// Then, if the last thing was received over the bus,
// we move to the next data item.
wb_data <= { 24'h00, message[msg_index] };
// }}}
// wb_addr
// {{{
// We send our first value to the SETUP address (all zeros), all other
// values we send to the transmitters address. We should really be
// double checking that stall remains low, but its not required here.
always @(posedge i_clk)
if (restart)
wb_addr <= 2'b00;
else // if (!uart_stall)??
wb_addr <= 2'b11;
// }}}
// end_of_message
// {{{
// Knowing when to stop sending the speech is important, but depends
// upon an 11 bit comparison. Since FPGA logic is best measured by the
// number of inputs to an always block, we pull those 11-bits out of
// the always block for wb_stb, and place them here on the clock prior.
// If end_of_message is true, then we need to stop transmitting, and
// wait for the next (restart) to get us started again. We set that
// flag hee.
initial end_of_message = 1'b1;
always @(posedge i_clk)
if (restart)
end_of_message <= 1'b0;
else
end_of_message <= (msg_index >= MSGLEN);
// }}}
// wb_stb
// {{{
// The wb_stb signal indicates that we wish to write, using the wishbone
// to our peripheral. We have two separate types of writes. First,
// we wish to write our setup. Then we want to drop STB and write
// our data. Once we've filled half of the FIFO, we wait for the FIFO
// to empty before issuing a STB again and then fill up half the FIFO
// again.
initial wb_stb = 1'b0;
always @(posedge i_clk)
if (restart)
// Start sending to the UART on a reset. The first
// thing we'll send will be the configuration, but
// that's done elsewhere. This just starts up the
// writes to the peripheral wbuart.
wb_stb <= 1'b1;
else if (end_of_message)
// Stop transmitting when we get to the end of our
// message.
wb_stb <= 1'b0;
else if (txfifo_int)
// If the FIFO is less than half full, then write to
// it.
wb_stb <= 1'b1;
else
// But once the FIFO gets to half full, stop.
wb_stb <= 1'b0;
// }}}
// cts_n
// {{{
// The WBUART can handle hardware flow control signals. This test,
// however, cannot. The reason? Simply just to keep things simple.
// If you want to add hardware flow control to your design, simply
// make rts an input to this module.
//
// Since this is an output only module demonstrator, what would be the
// cts output is unused.
assign cts_n = 1'b0;
// }}}
// Finally--the unit under test--now that we've set up all the wires
// to run/test it.
wbuart #(INITIAL_UART_SETUP)
wbuarti(i_clk, pwr_reset,
wb_stb, wb_stb, 1'b1, wb_addr, wb_data, 4'hf,
uart_stall, uart_ack, uart_data,
1'b1, o_uart_tx, cts_n, rts_n_ignored,
ignored_rx_int, tx_int,
ignored_rxfifo_int, txfifo_int);
endmodule
|
/*
* Copyright (C) 2017 Systems Group, ETHZ
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
* http://www.apache.org/licenses/LICENSE-2.0
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`include "framework_defines.vh"
module pipeline_agent
(
input wire clk,
input wire rst_n,
// Pipelining request
input wire find_pipeline_schedule,
input wire direct_pipeline_schedule,
input wire [0:`NUMBER_OF_FTHREADS-1] fthreads_state,
input wire [0:`NUMBER_OF_FTHREADS-1] src_job_fthread_mapping,
input wire [0:`NUMBER_OF_FTHREADS-1] dst_job_fthread_mapping,
// Pipeline Schedule decision
output reg [0:`NUMBER_OF_FTHREADS-1] src_fthread_select,
output reg [0:`NUMBER_OF_FTHREADS-1] dst_fthread_select,
output reg dst_fthread_reserve,
output reg pipeline_schedule_valid
);
wire [0:`NUMBER_OF_FTHREADS-1] dst_job_mapping_shifted;
wire [0:`NUMBER_OF_FTHREADS-1] pipeline_src_job_mapping;
wire [0:`NUMBER_OF_FTHREADS-1] valid_pipeline_mapping_src;
wire [0:`NUMBER_OF_FTHREADS-1] src_job_mapping_shifted;
wire [0:`NUMBER_OF_FTHREADS-1] pipeline_dst_job_mapping;
wire [0:`NUMBER_OF_FTHREADS-1] valid_pipeline_mapping_dst;
wire [0:`NUMBER_OF_FTHREADS-1] valid_pipeline_mapping_both;
wire [0:`NUMBER_OF_FTHREADS-1] src_fthread_select_b;
wire [0:`NUMBER_OF_FTHREADS-1] dst_fthread_select_b;
wire [0:`NUMBER_OF_FTHREADS-1] src_fthread_select_s;
wire [0:`NUMBER_OF_FTHREADS-1] dst_fthread_select_s;
wire [0:`NUMBER_OF_FTHREADS-1] src_fthread_select_a;
wire [0:`NUMBER_OF_FTHREADS-1] dst_fthread_select_a;
wire [0:`NUMBER_OF_FTHREADS-1] dst_fthread_select_r;
wire [0:`NUMBER_OF_FTHREADS-1] valid_mapping_src;
wire [0:`NUMBER_OF_FTHREADS-1] valid_mapping_dst;
genvar k;
///////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// ///////////////////////////////
/////////////////////////////// Memory Pipeline Schedule Decision /////////////////////////////
////////////////////////////////// ///////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
generate if(`NUMBER_OF_FTHREADS > 1) begin
// any valid mapping
assign valid_mapping_src = src_job_fthread_mapping & ~fthreads_state;
assign valid_mapping_dst = dst_job_fthread_mapping & ~fthreads_state;
// src schedule decision
//generate
for ( k = `NUMBER_OF_FTHREADS-1; k >1 ; k = k-1) begin: ft_selected_src_a
assign src_fthread_select_a[k] = valid_mapping_src[k] & ~(|(valid_mapping_src[0:k-1]));
end
//endgenerate
assign src_fthread_select_a[1] = valid_mapping_src[1] & ~valid_mapping_src[0];
assign src_fthread_select_a[0] = valid_mapping_src[0];
// dst schedule decision
//generate
for ( k = `NUMBER_OF_FTHREADS-1; k >1 ; k = k-1) begin: ft_selected_dst_a
assign dst_fthread_select_a[k] = valid_mapping_dst[k] & ~(|(valid_mapping_dst[0:k-1]));
end
//endgenerate
assign dst_fthread_select_a[1] = valid_mapping_dst[1] & ~valid_mapping_dst[0];
assign dst_fthread_select_a[0] = valid_mapping_dst[0];
// dst schedule reserve
//generate
for ( k = `NUMBER_OF_FTHREADS-1; k >1 ; k = k-1) begin: ft_selected_dst_r
assign dst_fthread_select_r[k] = dst_job_fthread_mapping[k] & ~(|(dst_job_fthread_mapping[0:k-1]));
end
//endgenerate
assign dst_fthread_select_r[1] = dst_job_fthread_mapping[1] & ~dst_job_fthread_mapping[0];
assign dst_fthread_select_r[0] = dst_job_fthread_mapping[0];
///////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// ///////////////////////////////
/////////////////////////////// Direct Pipeline Schedule Decision /////////////////////////////
////////////////////////////////// ///////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
// Check if at least the src can be mapped
assign dst_job_mapping_shifted = {dst_job_fthread_mapping[1:`NUMBER_OF_FTHREADS-1], 1'b0};
assign pipeline_src_job_mapping = dst_job_mapping_shifted & src_job_fthread_mapping;
assign valid_pipeline_mapping_src = pipeline_src_job_mapping & ~fthreads_state;
// check if at least dst can be mapped
assign src_job_mapping_shifted = {1'b0, src_job_fthread_mapping[0:`NUMBER_OF_FTHREADS-2]};
assign pipeline_dst_job_mapping = src_job_mapping_shifted & dst_job_fthread_mapping;
assign valid_pipeline_mapping_dst = pipeline_dst_job_mapping & ~fthreads_state;
// Check if both src and dst can be mapped
assign valid_pipeline_mapping_both = {valid_pipeline_mapping_dst[1:`NUMBER_OF_FTHREADS-1], 1'b0} &
valid_pipeline_mapping_src;
//---------------------------------------------------------------------------------------------------//
// src schedule decision based on valid mapping for both src & dst
//generate
for ( k = `NUMBER_OF_FTHREADS-1; k >1 ; k = k-1) begin: ft_selected_src_b
assign src_fthread_select_b[k] = valid_pipeline_mapping_both[k] & ~(|(valid_pipeline_mapping_both[0:k-1]));
end
//endgenerate
assign src_fthread_select_b[1] = valid_pipeline_mapping_both[1] & ~valid_pipeline_mapping_both[0];
assign src_fthread_select_b[0] = valid_pipeline_mapping_both[0];
//---------------------------------------------------------------------------------------------------//
// dst schedule decision based on valid mapping for both src & dst
assign dst_fthread_select_b = {1'b0, src_fthread_select_b[0:`NUMBER_OF_FTHREADS-2]};
//---------------------------------------------------------------------------------------------------//
// src schedule decision based on valid mapping at least for src
//generate
for ( k = `NUMBER_OF_FTHREADS-1; k >1 ; k = k-1) begin: ft_selected_src_s
assign src_fthread_select_s[k] = valid_pipeline_mapping_src[k] & ~(|(valid_pipeline_mapping_src[0:k-1]));
end
//endgenerate
assign src_fthread_select_s[1] = valid_pipeline_mapping_src[1] & ~valid_pipeline_mapping_src[0];
assign src_fthread_select_s[0] = valid_pipeline_mapping_src[0];
//---------------------------------------------------------------------------------------------------//
// dst reserved
assign dst_fthread_select_s = {1'b0, src_fthread_select_s[0:`NUMBER_OF_FTHREADS-2]};
//---------------------------------------------------------------------------------------------------//
always @(posedge clk) begin
if (~rst_n) begin
src_fthread_select <= 0;
dst_fthread_select <= 0;
dst_fthread_reserve <= 0;
pipeline_schedule_valid <= 0;
end
else begin
if(direct_pipeline_schedule) begin
if (|src_fthread_select_b) begin
src_fthread_select <= src_fthread_select_b;
dst_fthread_select <= dst_fthread_select_b;
dst_fthread_reserve <= 1'b0;
end
else begin
src_fthread_select <= src_fthread_select_s;
dst_fthread_select <= dst_fthread_select_s;
dst_fthread_reserve <= 1'b1;
end
end
else begin
src_fthread_select <= src_fthread_select_a;
dst_fthread_select <= 0;
dst_fthread_reserve <= 1'b0;
if(|src_fthread_select_a) begin
if(|dst_fthread_select_a) begin
dst_fthread_select <= dst_fthread_select_a;
end
else begin
dst_fthread_select <= dst_fthread_select_r;
dst_fthread_reserve <= 1'b1;
end
end
end
pipeline_schedule_valid <= find_pipeline_schedule;
end
end
end
else begin
always @(posedge clk) begin
src_fthread_select <= 0;
dst_fthread_select <= 0;
dst_fthread_reserve <= 0;
pipeline_schedule_valid <= 0;
end
end
endgenerate
endmodule |
module Nerf_Sentry_sm3(clock, uart, recieved, reset, pos, fire);
input clock;
input [7:0] uart;
input recieved;
input reset;
output reg [7:0] pos;
output reg fire;
reg [4:0] state;
reg [7:0] fireReg;
reg [7:0] x100, x010, x001;
parameter IDLE = 5'b00000,
X100 = 5'b00001,
X010 = 5'b00010,
X001 = 5'b00011,
Y100 = 5'b00100,
Y010 = 5'b00101,
Y001 = 5'b00110,
FIRE = 5'b00111,
FIRESEL = 5'b01000,
SCANSEL = 5'b01001,
//Buffer States
BIDLE = 5'b01011,
BX100 = 5'b01100,
BX010 = 5'b01101,
BX001 = 5'b01110,
BY100 = 5'b01111,
BY010 = 5'b10000,
BY001 = 5'b10001,
BFIRE = 5'b10010,
BFIRESEL = 5'b10011,
BSCANSEL = 5'b10100;
//State Control Function
always @ (posedge clock)
begin
case(state)
BIDLE:
begin
if (recieved == 1)
state <= BIDLE;
else
state <= IDLE;
end
IDLE: //Check to see if the trigger char is sent 'a'
begin
if (recieved == 1)
begin
if (uart[7:0] == 8'b01100001)
state <= BX100;
else
state <= IDLE;
end
end
BX100:
begin
if (recieved == 1)
state <= BX100;
else
state <= X100;
end
X100: ///
begin
if (recieved == 1)
state <= BX010;
else
state <= X100;
end
BX010:
begin
if (recieved == 1)
state <= BX010;
else
state <= X010;
end
X010:
begin
if (recieved == 1)
state <= BX001;
else
state <= X010;
end
BX001:
begin
if (recieved == 1)
state <= BX001;
else
state <= X001;
end
X001:
begin
if (recieved == 1)
state <= BY100;
else
state <= X001;
end
BY100:
begin
if (recieved == 1)
state <= BY100;
else
state <= Y100;
end
Y100:
begin
if (recieved == 1)
state <= BY010;
else
state <= Y100;
end
BY010:
begin
if (recieved == 1)
state <= BY010;
else
state <= Y010;
end
Y010:
begin
if (recieved == 1)
state <= BY001;
else
state <= Y010;
end
BY001:
begin
if (recieved == 1)
state <= BY001;
else
state <= Y001;
end
Y001:
begin
if (recieved == 1)
state <= BFIRE;
else
state <= Y001;
end
BFIRE:
begin
if (recieved == 1)
state <= BFIRE;
else
state <= FIRE;
end
FIRE:
begin
if (recieved == 1)
state <= BFIRESEL;
else
state <= FIRE;
end
BFIRESEL:
begin
if (recieved == 1)
state <= BFIRESEL;
else
state <= FIRESEL;
end
FIRESEL:
begin
if (recieved == 1)
state <= BSCANSEL;
else
state <= FIRESEL;
end
BSCANSEL:
begin
if (recieved == 1)
state <= BSCANSEL;
else
state <= SCANSEL;
end
SCANSEL:
begin
if (recieved == 1)
state <= BIDLE;
else
state <= SCANSEL;
end
default: ;//state <= IDLE;
endcase
end
//State Output Function
always @ (posedge clock)
begin
case(state)
IDLE:
begin
pos[7:0] <= ((x100 - 8'b00110000) * 8'b01100100) + ((x010 - 8'b00110000) * 8'b00001010) + (x001 - 8'b00110000);
fire <= fireReg[0];
end
X100: x100[7:0] <= uart[7:0];
X010: x010[7:0] <= uart[7:0];
X001: x001[7:0] <= uart[7:0];
FIRE: fireReg[7:0] <= uart[7:0];
default: ;
endcase
end
endmodule |
(* This program is free software; you can redistribute it and/or *)
(* modify it under the terms of the GNU Lesser General Public License *)
(* as published by the Free Software Foundation; either version 2.1 *)
(* of the License, or (at your option) any later version. *)
(* *)
(* This program is distributed in the hope that it will be useful, *)
(* but WITHOUT ANY WARRANTY; without even the implied warranty of *)
(* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *)
(* GNU General Public License for more details. *)
(* *)
(* You should have received a copy of the GNU Lesser General Public *)
(* License along with this program; if not, write to the Free *)
(* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA *)
(* 02110-1301 USA *)
(** This file includes random facts about Integers (and natural numbers) which are not found in the standard library. Some of the lemma here are not used in the QArith developement but are rather useful.
*)
Require Export ZArith.
Require Export ZArithRing.
Tactic Notation "ElimCompare" constr(c) constr(d) := elim_compare c d.
Ltac Flip :=
apply Zgt_lt || apply Zlt_gt || apply Zle_ge || apply Zge_le; assumption.
Ltac Falsum :=
try intro; apply False_ind;
repeat
match goal with
| id1:(~ ?X1) |- ?X2 =>
(apply id1; assumption || reflexivity) || clear id1
end.
Ltac Step_l a :=
match goal with
| |- (?X1 < ?X2)%Z => replace X1 with a; [ idtac | try ring ]
end.
Ltac Step_r a :=
match goal with
| |- (?X1 < ?X2)%Z => replace X2 with a; [ idtac | try ring ]
end.
Ltac CaseEq formula :=
generalize (refl_equal formula); pattern formula at -1 in |- *;
case formula.
Lemma pair_1 : forall (A B : Set) (H : A * B), H = pair (fst H) (snd H).
Proof.
intros.
case H.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma pair_2 :
forall (A B : Set) (H1 H2 : A * B),
fst H1 = fst H2 -> snd H1 = snd H2 -> H1 = H2.
Proof.
intros A B H1 H2.
case H1.
case H2.
simpl in |- *.
intros.
rewrite H.
rewrite H0.
reflexivity.
Qed.
Section projection.
Variable A : Set.
Variable P : A -> Prop.
Definition projP1 (H : sig P) := let (x, h) := H in x.
Definition projP2 (H : sig P) :=
let (x, h) as H return (P (projP1 H)) := H in h.
End projection.
(*###########################################################################*)
(* Declaring some realtions on natural numbers for stepl and stepr tactics. *)
(*###########################################################################*)
Lemma le_stepl: forall x y z, le x y -> x=z -> le z y.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma le_stepr: forall x y z, le x y -> y=z -> le x z.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma lt_stepl: forall x y z, lt x y -> x=z -> lt z y.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma lt_stepr: forall x y z, lt x y -> y=z -> lt x z.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma neq_stepl:forall (x y z:nat), x<>y -> x=z -> z<>y.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Lemma neq_stepr:forall (x y z:nat), x<>y -> y=z -> x<>z.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Declare Left Step le_stepl.
Declare Right Step le_stepr.
Declare Left Step lt_stepl.
Declare Right Step lt_stepr.
Declare Left Step neq_stepl.
Declare Right Step neq_stepr.
(*###########################################################################*)
(** Some random facts about natural numbers, positive numbers and integers *)
(*###########################################################################*)
Lemma not_O_S : forall n : nat, n <> 0 -> {p : nat | n = S p}.
Proof.
intros [| np] Hn; [ exists 0; apply False_ind; apply Hn | exists np ];
reflexivity.
Qed.
Lemma lt_minus_neq : forall m n : nat, m < n -> n - m <> 0.
Proof.
intros.
omega.
Qed.
Lemma lt_minus_eq_0 : forall m n : nat, m < n -> m - n = 0.
Proof.
intros.
omega.
Qed.
Lemma le_plus_Sn_1_SSn : forall n : nat, S n + 1 <= S (S n).
Proof.
intros.
omega.
Qed.
Lemma le_plus_O_l : forall p q : nat, p + q <= 0 -> p = 0.
Proof.
intros; omega.
Qed.
Lemma le_plus_O_r : forall p q : nat, p + q <= 0 -> q = 0.
Proof.
intros; omega.
Qed.
Lemma minus_pred : forall m n : nat, 0 < n -> pred m - pred n = m - n.
Proof.
intros.
omega.
Qed.
(*###########################################################################*)
(* Declaring some realtions on integers for stepl and stepr tactics. *)
(*###########################################################################*)
Lemma Zle_stepl: forall x y z, (x<=y)%Z -> x=z -> (z<=y)%Z.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma Zle_stepr: forall x y z, (x<=y)%Z -> y=z -> (x<=z)%Z.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma Zlt_stepl: forall x y z, (x<y)%Z -> x=z -> (z<y)%Z.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma Zlt_stepr: forall x y z, (x<y)%Z -> y=z -> (x<z)%Z.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma Zneq_stepl:forall (x y z:Z), (x<>y)%Z -> x=z -> (z<>y)%Z.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Lemma Zneq_stepr:forall (x y z:Z), (x<>y)%Z -> y=z -> (x<>z)%Z.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Declare Left Step Zle_stepl.
Declare Right Step Zle_stepr.
Declare Left Step Zlt_stepl.
Declare Right Step Zlt_stepr.
Declare Left Step Zneq_stepl.
Declare Right Step Zneq_stepr.
(*###########################################################################*)
(** Informative case analysis *)
(*###########################################################################*)
Lemma Zlt_cotrans :
forall x y : Z, (x < y)%Z -> forall z : Z, {(x < z)%Z} + {(z < y)%Z}.
Proof.
intros.
case (Z_lt_ge_dec x z).
intro.
left.
assumption.
intro.
right.
apply Zle_lt_trans with (m := x).
apply Zge_le.
assumption.
assumption.
Qed.
Lemma Zlt_cotrans_pos :
forall x y : Z, (0 < x + y)%Z -> {(0 < x)%Z} + {(0 < y)%Z}.
Proof.
intros.
case (Zlt_cotrans 0 (x + y) H x).
intro.
left.
assumption.
intro.
right.
apply Zplus_lt_reg_l with (p := x).
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zlt_cotrans_neg :
forall x y : Z, (x + y < 0)%Z -> {(x < 0)%Z} + {(y < 0)%Z}.
Proof.
intros x y H; case (Zlt_cotrans (x + y) 0 H x); intro Hxy;
[ right; apply Zplus_lt_reg_l with (p := x); rewrite Zplus_0_r | left ];
assumption.
Qed.
Lemma not_Zeq_inf : forall x y : Z, x <> y -> {(x < y)%Z} + {(y < x)%Z}.
Proof.
intros.
case Z_lt_ge_dec with x y.
intro.
left.
assumption.
intro H0.
generalize (Zge_le _ _ H0).
intro.
case (Z_le_lt_eq_dec _ _ H1).
intro.
right.
assumption.
intro.
apply False_rec.
apply H.
symmetry in |- *.
assumption.
Qed.
Lemma Z_dec : forall x y : Z, {(x < y)%Z} + {(x > y)%Z} + {x = y}.
Proof.
intros.
case (Z_lt_ge_dec x y).
intro H.
left.
left.
assumption.
intro H.
generalize (Zge_le _ _ H).
intro H0.
case (Z_le_lt_eq_dec y x H0).
intro H1.
left.
right.
apply Zlt_gt.
assumption.
intro.
right.
symmetry in |- *.
assumption.
Qed.
Lemma Z_dec' : forall x y : Z, {(x < y)%Z} + {(y < x)%Z} + {x = y}.
Proof.
intros x y.
case (Z_eq_dec x y); intro H;
[ right; assumption | left; apply (not_Zeq_inf _ _ H) ].
Qed.
Lemma Z_lt_le_dec : forall x y : Z, {(x < y)%Z} + {(y <= x)%Z}.
Proof.
intros.
case (Z_lt_ge_dec x y).
intro.
left.
assumption.
intro.
right.
apply Zge_le.
assumption.
Qed.
Lemma Z_le_lt_dec : forall x y : Z, {(x <= y)%Z} + {(y < x)%Z}.
Proof.
intros; case (Z_lt_le_dec y x); [ right | left ]; assumption.
Qed.
Lemma Z_lt_lt_S_eq_dec :
forall x y : Z, (x < y)%Z -> {(x + 1 < y)%Z} + {(x + 1)%Z = y}.
Proof.
intros.
generalize (Zlt_le_succ _ _ H).
unfold Zsucc in |- *.
apply Z_le_lt_eq_dec.
Qed.
Lemma quadro_leq_inf :
forall a b c d : Z,
{(c <= a)%Z /\ (d <= b)%Z} + {~ ((c <= a)%Z /\ (d <= b)%Z)}.
Proof.
intros.
case (Z_lt_le_dec a c).
intro z.
right.
intro.
elim H.
intros.
generalize z.
apply Zle_not_lt.
assumption.
intro.
case (Z_lt_le_dec b d).
intro z0.
right.
intro.
elim H.
intros.
generalize z0.
apply Zle_not_lt.
assumption.
intro.
left.
split.
assumption.
assumption.
Qed.
(*###########################################################################*)
(** General auxiliary lemmata *)
(*###########################################################################*)
Lemma Zminus_eq : forall x y : Z, (x - y)%Z = 0%Z -> x = y.
Proof.
intros.
apply Zplus_reg_l with (- y)%Z.
rewrite Zplus_opp_l.
unfold Zminus in H.
rewrite Zplus_comm.
assumption.
Qed.
Lemma Zlt_minus : forall a b : Z, (b < a)%Z -> (0 < a - b)%Z.
Proof.
intros a b.
intros.
apply Zplus_lt_reg_l with b.
unfold Zminus in |- *.
rewrite (Zplus_comm a).
rewrite (Zplus_assoc b (- b)).
rewrite Zplus_opp_r.
simpl in |- *.
rewrite <- Zplus_0_r_reverse.
assumption.
Qed.
Lemma Zle_minus : forall a b : Z, (b <= a)%Z -> (0 <= a - b)%Z.
Proof.
intros a b.
intros.
apply Zplus_le_reg_l with b.
unfold Zminus in |- *.
rewrite (Zplus_comm a).
rewrite (Zplus_assoc b (- b)).
rewrite Zplus_opp_r.
simpl in |- *.
rewrite <- Zplus_0_r_reverse.
assumption.
Qed.
Lemma Zlt_plus_plus :
forall m n p q : Z, (m < n)%Z -> (p < q)%Z -> (m + p < n + q)%Z.
Proof.
intros.
apply Zlt_trans with (m := (n + p)%Z).
rewrite Zplus_comm.
rewrite Zplus_comm with (n := n).
apply Zplus_lt_compat_l.
assumption.
apply Zplus_lt_compat_l.
assumption.
Qed.
Lemma Zgt_plus_plus :
forall m n p q : Z, (m > n)%Z -> (p > q)%Z -> (m + p > n + q)%Z.
intros.
apply Zgt_trans with (m := (n + p)%Z).
rewrite Zplus_comm.
rewrite Zplus_comm with (n := n).
apply Zplus_gt_compat_l.
assumption.
apply Zplus_gt_compat_l.
assumption.
Qed.
Lemma Zle_lt_plus_plus :
forall m n p q : Z, (m <= n)%Z -> (p < q)%Z -> (m + p < n + q)%Z.
Proof.
intros.
case (Zle_lt_or_eq m n).
assumption.
intro.
apply Zlt_plus_plus.
assumption.
assumption.
intro.
rewrite H1.
apply Zplus_lt_compat_l.
assumption.
Qed.
Lemma Zge_gt_plus_plus :
forall m n p q : Z, (m >= n)%Z -> (p > q)%Z -> (m + p > n + q)%Z.
Proof.
intros.
case (Zle_lt_or_eq n m).
apply Zge_le.
assumption.
intro.
apply Zgt_plus_plus.
apply Zlt_gt.
assumption.
assumption.
intro.
rewrite H1.
apply Zplus_gt_compat_l.
assumption.
Qed.
Lemma Zgt_ge_plus_plus :
forall m n p q : Z, (m > n)%Z -> (p >= q)%Z -> (m + p > n + q)%Z.
Proof.
intros.
rewrite Zplus_comm.
replace (n + q)%Z with (q + n)%Z.
apply Zge_gt_plus_plus.
assumption.
assumption.
apply Zplus_comm.
Qed.
Lemma Zlt_resp_pos : forall x y : Z, (0 < x)%Z -> (0 < y)%Z -> (0 < x + y)%Z.
Proof.
intros.
rewrite <- Zplus_0_r with 0%Z.
apply Zlt_plus_plus; assumption.
Qed.
Lemma Zle_resp_neg :
forall x y : Z, (x <= 0)%Z -> (y <= 0)%Z -> (x + y <= 0)%Z.
Proof.
intros.
rewrite <- Zplus_0_r with 0%Z.
apply Zplus_le_compat; assumption.
Qed.
Lemma Zlt_pos_opp : forall x : Z, (0 < x)%Z -> (- x < 0)%Z.
Proof.
intros.
apply Zplus_lt_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zlt_neg_opp : forall x : Z, (x < 0)%Z -> (0 < - x)%Z.
Proof.
intros.
apply Zplus_lt_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zle_neg_opp : forall x : Z, (x <= 0)%Z -> (0 <= - x)%Z.
Proof.
intros.
apply Zplus_le_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zle_pos_opp : forall x : Z, (0 <= x)%Z -> (- x <= 0)%Z.
Proof.
intros.
apply Zplus_le_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zge_opp : forall x y : Z, (x <= y)%Z -> (- x >= - y)%Z.
Proof.
intros.
apply Zle_ge.
apply Zplus_le_reg_l with (p := (x + y)%Z).
ring_simplify (x + y + - y)%Z (x + y + - x)%Z.
assumption.
Qed.
(* Omega can't solve this *)
Lemma Zmult_pos_pos : forall x y : Z, (0 < x)%Z -> (0 < y)%Z -> (0 < x * y)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Lemma Zmult_neg_neg : forall x y : Z, (x < 0)%Z -> (y < 0)%Z -> (0 < x * y)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Lemma Zmult_neg_pos : forall x y : Z, (x < 0)%Z -> (0 < y)%Z -> (x * y < 0)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Lemma Zmult_pos_neg : forall x y : Z, (0 < x)%Z -> (y < 0)%Z -> (x * y < 0)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Hint Resolve Zmult_pos_pos Zmult_neg_neg Zmult_neg_pos Zmult_pos_neg: zarith.
Lemma Zle_reg_mult_l :
forall x y a : Z, (0 < a)%Z -> (x <= y)%Z -> (a * x <= a * y)%Z.
Proof.
intros.
apply Zplus_le_reg_l with (p := (- a * x)%Z).
ring_simplify (- a * x + a * x)%Z.
replace (- a * x + a * y)%Z with ((y - x) * a)%Z.
apply Zmult_gt_0_le_0_compat.
apply Zlt_gt.
assumption.
unfold Zminus in |- *.
apply Zle_left.
assumption.
ring.
Qed.
Lemma Zsimpl_plus_l_dep :
forall x y m n : Z, (x + m)%Z = (y + n)%Z -> x = y -> m = n.
Proof.
intros.
apply Zplus_reg_l with x.
rewrite <- H0 in H.
assumption.
Qed.
Lemma Zsimpl_plus_r_dep :
forall x y m n : Z, (m + x)%Z = (n + y)%Z -> x = y -> m = n.
Proof.
intros.
apply Zplus_reg_l with x.
rewrite Zplus_comm.
rewrite Zplus_comm with x n.
rewrite <- H0 in H.
assumption.
Qed.
Lemma Zmult_simpl :
forall n m p q : Z, n = m -> p = q -> (n * p)%Z = (m * q)%Z.
Proof.
intros.
rewrite H.
rewrite H0.
reflexivity.
Qed.
Lemma Zsimpl_mult_l :
forall n m p : Z, n <> 0%Z -> (n * m)%Z = (n * p)%Z -> m = p.
Proof.
intros.
apply Zplus_reg_l with (n := (- p)%Z).
replace (- p + p)%Z with 0%Z.
apply Zmult_integral_l with (n := n).
assumption.
replace ((- p + m) * n)%Z with (n * m + - (n * p))%Z.
apply Zegal_left.
assumption.
ring.
ring.
Qed.
Lemma Zlt_reg_mult_l :
forall x y z : Z, (x > 0)%Z -> (y < z)%Z -> (x * y < x * z)%Z. (*QA*)
Proof.
intros.
case (Zcompare_Gt_spec x 0).
unfold Zgt in H.
assumption.
intros.
cut (x = Zpos x0).
intro.
rewrite H2.
unfold Zlt in H0.
unfold Zlt in |- *.
cut ((Zpos x0 * y ?= Zpos x0 * z)%Z = (y ?= z)%Z).
intro.
exact (trans_eq H3 H0).
apply Zcompare_mult_compat.
cut (x = (x + - (0))%Z).
intro.
exact (trans_eq H2 H1).
simpl in |- *.
apply (sym_eq (A:=Z)).
exact (Zplus_0_r x).
Qed.
Lemma Zlt_opp : forall x y : Z, (x < y)%Z -> (- x > - y)%Z. (*QA*)
Proof.
intros.
red in |- *.
apply sym_eq.
cut (Datatypes.Gt = (y ?= x)%Z).
intro.
cut ((y ?= x)%Z = (- x ?= - y)%Z).
intro.
exact (trans_eq H0 H1).
exact (Zcompare_opp y x).
apply sym_eq.
exact (Zlt_gt x y H).
Qed.
Lemma Zlt_conv_mult_l :
forall x y z : Z, (x < 0)%Z -> (y < z)%Z -> (x * y > x * z)%Z. (*QA*)
Proof.
intros.
cut (- x > 0)%Z.
intro.
cut (- x * y < - x * z)%Z.
intro.
cut (- (- x * y) > - (- x * z))%Z.
intro.
cut (- - (x * y) > - - (x * z))%Z.
intro.
cut ((- - (x * y))%Z = (x * y)%Z).
intro.
rewrite H5 in H4.
cut ((- - (x * z))%Z = (x * z)%Z).
intro.
rewrite H6 in H4.
assumption.
exact (Zopp_involutive (x * z)).
exact (Zopp_involutive (x * y)).
cut ((- (- x * y))%Z = (- - (x * y))%Z).
intro.
rewrite H4 in H3.
cut ((- (- x * z))%Z = (- - (x * z))%Z).
intro.
rewrite H5 in H3.
assumption.
cut ((- x * z)%Z = (- (x * z))%Z).
intro.
exact (f_equal Zopp H5).
exact (Zopp_mult_distr_l_reverse x z).
cut ((- x * y)%Z = (- (x * y))%Z).
intro.
exact (f_equal Zopp H4).
exact (Zopp_mult_distr_l_reverse x y).
exact (Zlt_opp (- x * y) (- x * z) H2).
exact (Zlt_reg_mult_l (- x) y z H1 H0).
exact (Zlt_opp x 0 H).
Qed.
Lemma Zgt_not_eq : forall x y : Z, (x > y)%Z -> x <> y. (*QA*)
Proof.
intros.
cut (y < x)%Z.
intro.
cut (y <> x).
intro.
red in |- *.
intros.
cut (y = x).
intros.
apply H1.
assumption.
exact (sym_eq H2).
exact (Zorder.Zlt_not_eq y x H0).
exact (Zgt_lt x y H).
Qed.
Lemma Zmult_resp_nonzero :
forall x y : Z, x <> 0%Z -> y <> 0%Z -> (x * y)%Z <> 0%Z.
Proof.
intros x y Hx Hy Hxy.
apply Hx.
apply Zmult_integral_l with y; assumption.
Qed.
Lemma Zopp_app : forall y : Z, y <> 0%Z -> (- y)%Z <> 0%Z.
Proof.
intros.
intro.
apply H.
apply Zplus_reg_l with (- y)%Z.
rewrite Zplus_opp_l.
rewrite H0.
simpl in |- *.
reflexivity.
Qed.
Lemma Zle_neq_Zlt : forall a b : Z, (a <= b)%Z -> b <> a -> (a < b)%Z.
Proof.
intros a b H H0.
case (Z_le_lt_eq_dec _ _ H); trivial.
intro; apply False_ind; apply H0; symmetry in |- *; assumption.
Qed.
Lemma not_Zle_lt : forall x y : Z, ~ (y <= x)%Z -> (x < y)%Z.
Proof.
intros; apply Zgt_lt; apply Znot_le_gt; assumption.
Qed.
Lemma not_Zlt : forall x y : Z, ~ (y < x)%Z -> (x <= y)%Z.
Proof.
intros x y H1 H2; apply H1; apply Zgt_lt; assumption.
Qed.
Lemma Zmult_absorb :
forall x y z : Z, x <> 0%Z -> (x * y)%Z = (x * z)%Z -> y = z. (*QA*)
Proof.
intros.
case (dec_eq y z).
intro.
assumption.
intro.
case (not_Zeq y z).
assumption.
intro.
case (not_Zeq x 0).
assumption.
intro.
apply False_ind.
cut (x * y > x * z)%Z.
intro.
cut ((x * y)%Z <> (x * z)%Z).
intro.
apply H5.
assumption.
exact (Zgt_not_eq (x * y) (x * z) H4).
exact (Zlt_conv_mult_l x y z H3 H2).
intro.
apply False_ind.
cut (x * y < x * z)%Z.
intro.
cut ((x * y)%Z <> (x * z)%Z).
intro.
apply H5.
assumption.
exact (Zorder.Zlt_not_eq (x * y) (x * z) H4).
cut (x > 0)%Z.
intro.
exact (Zlt_reg_mult_l x y z H4 H2).
exact (Zlt_gt 0 x H3).
intro.
apply False_ind.
cut (x * z < x * y)%Z.
intro.
cut ((x * z)%Z <> (x * y)%Z).
intro.
apply H4.
apply (sym_eq (A:=Z)).
assumption.
exact (Zorder.Zlt_not_eq (x * z) (x * y) H3).
apply False_ind.
case (not_Zeq x 0).
assumption.
intro.
cut (x * z > x * y)%Z.
intro.
cut ((x * z)%Z <> (x * y)%Z).
intro.
apply H5.
apply (sym_eq (A:=Z)).
assumption.
exact (Zgt_not_eq (x * z) (x * y) H4).
exact (Zlt_conv_mult_l x z y H3 H2).
intro.
cut (x * z < x * y)%Z.
intro.
cut ((x * z)%Z <> (x * y)%Z).
intro.
apply H5.
apply (sym_eq (A:=Z)).
assumption.
exact (Zorder.Zlt_not_eq (x * z) (x * y) H4).
cut (x > 0)%Z.
intro.
exact (Zlt_reg_mult_l x z y H4 H2).
exact (Zlt_gt 0 x H3).
Qed.
Lemma Zlt_mult_mult :
forall a b c d : Z,
(0 < a)%Z -> (0 < d)%Z -> (a < b)%Z -> (c < d)%Z -> (a * c < b * d)%Z.
Proof.
intros.
apply Zlt_trans with (a * d)%Z.
apply Zlt_reg_mult_l.
Flip.
assumption.
rewrite Zmult_comm.
rewrite Zmult_comm with b d.
apply Zlt_reg_mult_l.
Flip.
assumption.
Qed.
Lemma Zgt_mult_conv_absorb_l :
forall a x y : Z, (a < 0)%Z -> (a * x > a * y)%Z -> (x < y)%Z. (*QC*)
Proof.
intros.
case (dec_eq x y).
intro.
apply False_ind.
rewrite H1 in H0.
cut ((a * y)%Z = (a * y)%Z).
change ((a * y)%Z <> (a * y)%Z) in |- *.
apply Zgt_not_eq.
assumption.
trivial.
intro.
case (not_Zeq x y H1).
trivial.
intro.
apply False_ind.
cut (a * y > a * x)%Z.
apply Zgt_asym with (m := (a * y)%Z) (n := (a * x)%Z).
assumption.
apply Zlt_conv_mult_l.
assumption.
assumption.
Qed.
Lemma Zgt_mult_reg_absorb_l :
forall a x y : Z, (a > 0)%Z -> (a * x > a * y)%Z -> (x > y)%Z. (*QC*)
Proof.
intros.
cut (- - a > - - (0))%Z.
intro.
cut (- a < - (0))%Z.
simpl in |- *.
intro.
replace x with (- - x)%Z.
replace y with (- - y)%Z.
apply Zlt_opp.
apply Zgt_mult_conv_absorb_l with (a := (- a)%Z) (x := (- x)%Z).
assumption.
rewrite Zmult_opp_opp.
rewrite Zmult_opp_opp.
assumption.
apply Zopp_involutive.
apply Zopp_involutive.
apply Zgt_lt.
apply Zlt_opp.
apply Zgt_lt.
assumption.
simpl in |- *.
rewrite Zopp_involutive.
assumption.
Qed.
Lemma Zopp_Zlt : forall x y : Z, (y < x)%Z -> (- x < - y)%Z.
Proof.
intros x y Hyx.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
replace (-1 * - y)%Z with y.
replace (-1 * - x)%Z with x.
Flip.
ring.
ring.
Qed.
Lemma Zmin_cancel_Zlt : forall x y : Z, (- x < - y)%Z -> (y < x)%Z.
Proof.
intros.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
replace (-1 * y)%Z with (- y)%Z.
replace (-1 * x)%Z with (- x)%Z.
apply Zlt_gt.
assumption.
ring.
ring.
Qed.
Lemma Zmult_cancel_Zle :
forall a x y : Z, (a < 0)%Z -> (a * x <= a * y)%Z -> (y <= x)%Z.
Proof.
intros.
case (Z_le_gt_dec y x).
trivial.
intro.
apply False_ind.
apply (Zlt_irrefl (a * x)).
apply Zle_lt_trans with (m := (a * y)%Z).
assumption.
apply Zgt_lt.
apply Zlt_conv_mult_l.
assumption.
apply Zgt_lt.
assumption.
Qed.
Lemma Zlt_mult_cancel_l :
forall x y z : Z, (0 < x)%Z -> (x * y < x * z)%Z -> (y < z)%Z.
Proof.
intros.
apply Zgt_lt.
apply Zgt_mult_reg_absorb_l with x.
apply Zlt_gt.
assumption.
apply Zlt_gt.
assumption.
Qed.
Lemma Zmin_cancel_Zle : forall x y : Z, (- x <= - y)%Z -> (y <= x)%Z.
Proof.
intros.
apply Zmult_cancel_Zle with (a := (-1)%Z).
constructor.
replace (-1 * y)%Z with (- y)%Z.
replace (-1 * x)%Z with (- x)%Z.
assumption.
ring.
ring.
Qed.
Lemma Zmult_resp_Zle :
forall a x y : Z, (0 < a)%Z -> (a * y <= a * x)%Z -> (y <= x)%Z.
Proof.
intros.
case (Z_le_gt_dec y x).
trivial.
intro.
apply False_ind.
apply (Zlt_irrefl (a * y)).
apply Zle_lt_trans with (m := (a * x)%Z).
assumption.
apply Zlt_reg_mult_l.
apply Zlt_gt.
assumption.
apply Zgt_lt.
assumption.
Qed.
Lemma Zopp_Zle : forall x y : Z, (y <= x)%Z -> (- x <= - y)%Z.
Proof.
intros.
apply Zmult_cancel_Zle with (a := (-1)%Z).
constructor.
replace (-1 * - y)%Z with y.
replace (-1 * - x)%Z with x.
assumption.
clear y H; ring.
clear x H; ring.
Qed.
Lemma Zle_lt_eq_S : forall x y : Z, (x <= y)%Z -> (y < x + 1)%Z -> y = x.
Proof.
intros.
case (Z_le_lt_eq_dec x y H).
intro H1.
apply False_ind.
generalize (Zlt_le_succ x y H1).
intro.
apply (Zlt_not_le y (x + 1) H0).
replace (x + 1)%Z with (Zsucc x).
assumption.
reflexivity.
intro H1.
symmetry in |- *.
assumption.
Qed.
Lemma Zlt_le_eq_S :
forall x y : Z, (x < y)%Z -> (y <= x + 1)%Z -> y = (x + 1)%Z.
Proof.
intros.
case (Z_le_lt_eq_dec y (x + 1) H0).
intro H1.
apply False_ind.
generalize (Zlt_le_succ x y H).
intro.
apply (Zlt_not_le y (x + 1) H1).
replace (x + 1)%Z with (Zsucc x).
assumption.
reflexivity.
trivial.
Qed.
Lemma double_not_equal_zero :
forall c d : Z, ~ (c = 0%Z /\ d = 0%Z) -> c <> d \/ c <> 0%Z.
Proof.
intros.
case (Z_zerop c).
intro.
rewrite e.
left.
apply sym_not_eq.
intro.
apply H; repeat split; assumption.
intro; right; assumption.
Qed.
Lemma triple_not_equal_zero :
forall a b c : Z,
~ (a = 0%Z /\ b = 0%Z /\ c = 0%Z) -> a <> 0%Z \/ b <> 0%Z \/ c <> 0%Z.
Proof.
intros a b c H; case (Z_zerop a); intro Ha;
[ case (Z_zerop b); intro Hb;
[ case (Z_zerop c); intro Hc;
[ apply False_ind; apply H; repeat split | right; right ]
| right; left ]
| left ]; assumption.
Qed.
Lemma mediant_1 :
forall m n m' n' : Z, (m' * n < m * n')%Z -> ((m + m') * n < m * (n + n'))%Z.
Proof.
intros.
rewrite Zmult_plus_distr_r.
rewrite Zmult_plus_distr_l.
apply Zplus_lt_compat_l.
assumption.
Qed.
Lemma mediant_2 :
forall m n m' n' : Z,
(m' * n < m * n')%Z -> (m' * (n + n') < (m + m') * n')%Z.
Proof.
intros.
rewrite Zmult_plus_distr_l.
rewrite Zmult_plus_distr_r.
apply Zplus_lt_compat_r.
assumption.
Qed.
Lemma mediant_3 :
forall a b m n m' n' : Z,
(0 <= a * m + b * n)%Z ->
(0 <= a * m' + b * n')%Z -> (0 <= a * (m + m') + b * (n + n'))%Z.
Proof.
intros.
replace (a * (m + m') + b * (n + n'))%Z with
(a * m + b * n + (a * m' + b * n'))%Z.
apply Zplus_le_0_compat.
assumption.
assumption.
ring.
Qed.
Lemma fraction_lt_trans :
forall a b c d e f : Z,
(0 < b)%Z ->
(0 < d)%Z ->
(0 < f)%Z -> (a * d < c * b)%Z -> (c * f < e * d)%Z -> (a * f < e * b)%Z.
Proof.
intros.
apply Zgt_lt.
apply Zgt_mult_reg_absorb_l with d.
Flip.
apply Zgt_trans with (c * b * f)%Z.
replace (d * (e * b))%Z with (b * (e * d))%Z.
replace (c * b * f)%Z with (b * (c * f))%Z.
apply Zlt_gt.
apply Zlt_reg_mult_l.
Flip.
assumption.
ring.
ring.
replace (c * b * f)%Z with (f * (c * b))%Z.
replace (d * (a * f))%Z with (f * (a * d))%Z.
apply Zlt_gt.
apply Zlt_reg_mult_l.
Flip.
assumption.
ring.
ring.
Qed.
Lemma square_pos : forall a : Z, a <> 0%Z -> (0 < a * a)%Z.
Proof.
intros [| p| p]; intros; [ Falsum | constructor | constructor ].
Qed.
Hint Resolve square_pos: zarith.
(*###########################################################################*)
(** Properties of positive numbers, mapping between Z and nat *)
(*###########################################################################*)
Definition Z2positive (z : Z) :=
match z with
| Zpos p => p
| Zneg p => p
| Z0 => 1%positive
end.
Lemma ZL9 : forall p : positive, Z_of_nat (nat_of_P p) = Zpos p. (*QF*)
Proof.
intro.
cut (exists h : nat, nat_of_P p = S h).
intro.
case H.
intros.
unfold Z_of_nat in |- *.
rewrite H0.
apply f_equal with (A := positive) (B := Z) (f := Zpos).
cut (P_of_succ_nat (nat_of_P p) = P_of_succ_nat (S x)).
intro.
rewrite P_of_succ_nat_o_nat_of_P_eq_succ in H1.
cut (Ppred (Psucc p) = Ppred (P_of_succ_nat (S x))).
intro.
rewrite Ppred_succ in H2.
simpl in H2.
rewrite Ppred_succ in H2.
apply sym_eq.
assumption.
apply f_equal with (A := positive) (B := positive) (f := Ppred).
assumption.
apply f_equal with (f := P_of_succ_nat).
assumption.
apply ZL4.
Qed.
Coercion Z_of_nat : nat >-> Z.
Lemma ZERO_lt_POS : forall p : positive, (0 < Zpos p)%Z.
Proof.
intros.
constructor.
Qed.
Lemma POS_neq_ZERO : forall p : positive, Zpos p <> 0%Z.
Proof.
intros.
apply sym_not_eq.
apply Zorder.Zlt_not_eq.
apply ZERO_lt_POS.
Qed.
Lemma NEG_neq_ZERO : forall p : positive, Zneg p <> 0%Z.
Proof.
intros.
apply Zorder.Zlt_not_eq.
unfold Zlt in |- *.
constructor.
Qed.
Lemma POS_resp_eq : forall p0 p1 : positive, Zpos p0 = Zpos p1 -> p0 = p1.
Proof.
intros.
injection H.
trivial.
Qed.
Lemma nat_nat_pos : forall m n : nat, ((m + 1) * (n + 1) > 0)%Z. (*QF*)
Proof.
intros.
apply Zlt_gt.
cut (Z_of_nat m + 1 > 0)%Z.
intro.
cut (0 < Z_of_nat n + 1)%Z.
intro.
cut ((Z_of_nat m + 1) * 0 < (Z_of_nat m + 1) * (Z_of_nat n + 1))%Z.
rewrite Zmult_0_r.
intro.
assumption.
apply Zlt_reg_mult_l.
assumption.
assumption.
change (0 < Zsucc (Z_of_nat n))%Z in |- *.
apply Zle_lt_succ.
change (Z_of_nat 0 <= Z_of_nat n)%Z in |- *.
apply Znat.inj_le.
apply le_O_n.
apply Zlt_gt.
change (0 < Zsucc (Z_of_nat m))%Z in |- *.
apply Zle_lt_succ.
change (Z_of_nat 0 <= Z_of_nat m)%Z in |- *.
apply Znat.inj_le.
apply le_O_n.
Qed.
Theorem S_predn : forall m : nat, m <> 0 -> S (pred m) = m. (*QF*)
Proof.
intros.
case (O_or_S m).
intro.
case s.
intros.
rewrite <- e.
rewrite <- pred_Sn with (n := x).
trivial.
intro.
apply False_ind.
apply H.
apply sym_eq.
assumption.
Qed.
Lemma absolu_1 : forall x : Z, Zabs_nat x = 0 -> x = 0%Z. (*QF*)
Proof.
intros.
case (dec_eq x 0).
intro.
assumption.
intro.
apply False_ind.
cut ((x < 0)%Z \/ (x > 0)%Z).
intro.
ElimCompare x 0%Z.
intro.
cut (x = 0%Z).
assumption.
cut ((x ?= 0)%Z = Datatypes.Eq -> x = 0%Z).
intro.
apply H3.
assumption.
apply proj1 with (B := x = 0%Z -> (x ?= 0)%Z = Datatypes.Eq).
change ((x ?= 0)%Z = Datatypes.Eq <-> x = 0%Z) in |- *.
apply Zcompare_Eq_iff_eq.
(***)
intro.
cut (exists h : nat, Zabs_nat x = S h).
intro.
case H3.
rewrite H.
exact O_S.
change (x < 0)%Z in H2.
cut (0 > x)%Z.
intro.
cut (exists p : positive, (0 + - x)%Z = Zpos p).
simpl in |- *.
intro.
case H4.
intros.
cut (exists q : positive, x = Zneg q).
intro.
case H6.
intros.
rewrite H7.
unfold Zabs_nat in |- *.
generalize x1.
exact ZL4.
cut (x = (- Zpos x0)%Z).
simpl in |- *.
intro.
exists x0.
assumption.
cut ((- - x)%Z = x).
intro.
rewrite <- H6.
exact (f_equal Zopp H5).
apply Zopp_involutive.
apply Zcompare_Gt_spec.
assumption.
apply Zlt_gt.
assumption.
(***)
intro.
cut (exists h : nat, Zabs_nat x = S h).
intro.
case H3.
rewrite H.
exact O_S.
cut (exists p : positive, (x + - (0))%Z = Zpos p).
simpl in |- *.
rewrite Zplus_0_r.
intro.
case H3.
intros.
rewrite H4.
unfold Zabs_nat in |- *.
generalize x0.
exact ZL4.
apply Zcompare_Gt_spec.
assumption.
(***)
cut ((x < 0)%Z \/ (0 < x)%Z).
intro.
apply
or_ind with (A := (x < 0)%Z) (B := (0 < x)%Z) (P := (x < 0)%Z \/ (x > 0)%Z).
intro.
left.
assumption.
intro.
right.
apply Zlt_gt.
assumption.
assumption.
apply not_Zeq.
assumption.
Qed.
Lemma absolu_2 : forall x : Z, x <> 0%Z -> Zabs_nat x <> 0. (*QF*)
Proof.
intros.
intro.
apply H.
apply absolu_1.
assumption.
Qed.
Lemma absolu_inject_nat : forall n : nat, Zabs_nat (Z_of_nat n) = n.
Proof.
simple induction n; simpl in |- *.
reflexivity.
intros.
apply nat_of_P_o_P_of_succ_nat_eq_succ.
Qed.
Lemma eq_inj : forall m n : nat, m = n :>Z -> m = n.
Proof.
intros.
generalize (f_equal Zabs_nat H).
intro.
rewrite (absolu_inject_nat m) in H0.
rewrite (absolu_inject_nat n) in H0.
assumption.
Qed.
Lemma lt_inj : forall m n : nat, (m < n)%Z -> m < n.
Proof.
intros.
omega.
Qed.
Lemma le_inj : forall m n : nat, (m <= n)%Z -> m <= n.
Proof.
intros.
omega.
Qed.
Lemma inject_nat_S_inf : forall x : Z, (0 < x)%Z -> {n : nat | x = S n}.
Proof.
intros [| p| p] Hp; try discriminate Hp.
exists (pred (nat_of_P p)).
rewrite S_predn.
symmetry in |- *; apply ZL9.
clear Hp;
apply sym_not_equal; apply lt_O_neq; apply lt_O_nat_of_P.
Qed.
Lemma le_absolu :
forall x y : Z,
(0 <= x)%Z -> (0 <= y)%Z -> (x <= y)%Z -> Zabs_nat x <= Zabs_nat y.
Proof.
intros [| x| x] [| y| y] Hx Hy Hxy;
apply le_O_n ||
(try
match goal with
| id1:(0 <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= 0)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
end).
simpl in |- *.
apply le_inj.
do 2 rewrite ZL9.
assumption.
Qed.
Lemma lt_absolu :
forall x y : Z,
(0 <= x)%Z -> (0 <= y)%Z -> (x < y)%Z -> Zabs_nat x < Zabs_nat y.
Proof.
intros [| x| x] [| y| y] Hx Hy Hxy; inversion Hxy;
try
match goal with
| id1:(0 <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= 0)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
end; simpl in |- *; apply lt_inj; repeat rewrite ZL9;
assumption.
Qed.
Lemma absolu_plus :
forall x y : Z,
(0 <= x)%Z -> (0 <= y)%Z -> Zabs_nat (x + y) = Zabs_nat x + Zabs_nat y.
Proof.
intros [| x| x] [| y| y] Hx Hy; trivial;
try
match goal with
| id1:(0 <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= 0)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
end.
rewrite <- BinInt.Zpos_plus_distr.
unfold Zabs_nat in |- *.
apply nat_of_P_plus_morphism.
Qed.
Lemma pred_absolu :
forall x : Z, (0 < x)%Z -> pred (Zabs_nat x) = Zabs_nat (x - 1).
Proof.
intros x Hx.
generalize (Z_lt_lt_S_eq_dec 0 x Hx); simpl in |- *; intros [H1| H1];
[ replace (Zabs_nat x) with (Zabs_nat (x - 1 + 1));
[ idtac | apply f_equal with Z; auto with zarith ];
rewrite absolu_plus;
[ unfold Zabs_nat at 2, nat_of_P, Piter_op in |- *; omega
| auto with zarith
| intro; discriminate ]
| rewrite <- H1; reflexivity ].
Qed.
Definition pred_nat : forall (x : Z) (Hx : (0 < x)%Z), nat.
intros [| px| px] Hx; try abstract (discriminate Hx).
exact (pred (nat_of_P px)).
Defined.
Lemma pred_nat_equal :
forall (x : Z) (Hx1 Hx2 : (0 < x)%Z), pred_nat x Hx1 = pred_nat x Hx2.
Proof.
intros [| px| px] Hx1 Hx2; try (discriminate Hx1); trivial.
Qed.
Let pred_nat_unfolded_subproof px :
Pos.to_nat px <> 0.
Proof.
apply sym_not_equal; apply lt_O_neq; apply lt_O_nat_of_P.
Qed.
Lemma pred_nat_unfolded :
forall (x : Z) (Hx : (0 < x)%Z), x = S (pred_nat x Hx).
Proof.
intros [| px| px] Hx; try discriminate Hx.
unfold pred_nat in |- *.
rewrite S_predn.
symmetry in |- *; apply ZL9.
clear Hx; apply pred_nat_unfolded_subproof.
Qed.
Lemma absolu_pred_nat :
forall (m : Z) (Hm : (0 < m)%Z), S (pred_nat m Hm) = Zabs_nat m.
Proof.
intros [| px| px] Hx; try discriminate Hx.
unfold pred_nat in |- *.
rewrite S_predn.
reflexivity.
apply pred_nat_unfolded_subproof.
Qed.
Lemma pred_nat_absolu :
forall (m : Z) (Hm : (0 < m)%Z), pred_nat m Hm = Zabs_nat (m - 1).
Proof.
intros [| px| px] Hx; try discriminate Hx.
unfold pred_nat in |- *.
rewrite <- pred_absolu; reflexivity || assumption.
Qed.
Lemma minus_pred_nat :
forall (n m : Z) (Hn : (0 < n)%Z) (Hm : (0 < m)%Z) (Hnm : (0 < n - m)%Z),
S (pred_nat n Hn) - S (pred_nat m Hm) = S (pred_nat (n - m) Hnm).
Proof.
intros.
simpl in |- *.
destruct n; try discriminate Hn.
destruct m; try discriminate Hm.
unfold pred_nat at 1 2 in |- *.
rewrite minus_pred; try apply lt_O_nat_of_P.
apply eq_inj.
rewrite <- pred_nat_unfolded.
rewrite Znat.inj_minus1.
repeat rewrite ZL9.
reflexivity.
apply le_inj.
apply Zlt_le_weak.
repeat rewrite ZL9.
apply Zlt_O_minus_lt.
assumption.
Qed.
(*###########################################################################*)
(** Properties of Zsgn *)
(*###########################################################################*)
Lemma Zsgn_1 :
forall x : Z, {Zsgn x = 0%Z} + {Zsgn x = 1%Z} + {Zsgn x = (-1)%Z}. (*QF*)
Proof.
intros.
case x.
left.
left.
unfold Zsgn in |- *.
reflexivity.
intro.
simpl in |- *.
left.
right.
reflexivity.
intro.
right.
simpl in |- *.
reflexivity.
Qed.
Lemma Zsgn_2 : forall x : Z, Zsgn x = 0%Z -> x = 0%Z. (*QF*)
Proof.
intros [| p1| p1]; simpl in |- *; intro H; constructor || discriminate H.
Qed.
Lemma Zsgn_3 : forall x : Z, x <> 0%Z -> Zsgn x <> 0%Z. (*QF*)
Proof.
intro.
case x.
intros.
apply False_ind.
apply H.
reflexivity.
intros.
simpl in |- *.
discriminate.
intros.
simpl in |- *.
discriminate.
Qed.
Theorem Zsgn_4 : forall a : Z, a = (Zsgn a * Zabs_nat a)%Z. (*QF*)
Proof.
intro.
case a.
simpl in |- *.
reflexivity.
intro.
unfold Zsgn in |- *.
unfold Zabs_nat in |- *.
rewrite Zmult_1_l.
symmetry in |- *.
apply ZL9.
intros.
unfold Zsgn in |- *.
unfold Zabs_nat in |- *.
rewrite ZL9.
constructor.
Qed.
Theorem Zsgn_5 :
forall a b x y : Z,
x <> 0%Z ->
y <> 0%Z ->
(Zsgn a * x)%Z = (Zsgn b * y)%Z -> (Zsgn a * y)%Z = (Zsgn b * x)%Z. (*QF*)
Proof.
intros a b x y H H0.
case a.
case b.
simpl in |- *.
trivial.
intro.
unfold Zsgn in |- *.
intro.
rewrite Zmult_1_l in H1.
simpl in H1.
apply False_ind.
apply H0.
symmetry in |- *.
assumption.
intro.
unfold Zsgn in |- *.
intro.
apply False_ind.
apply H0.
apply Zopp_inj.
simpl in |- *.
transitivity (-1 * y)%Z.
constructor.
transitivity (0 * x)%Z.
symmetry in |- *.
assumption.
simpl in |- *.
reflexivity.
intro.
unfold Zsgn at 1 in |- *.
unfold Zsgn at 2 in |- *.
intro.
transitivity y.
rewrite Zmult_1_l.
reflexivity.
transitivity (Zsgn b * (Zsgn b * y))%Z.
case (Zsgn_1 b).
intro.
case s.
intro.
apply False_ind.
apply H.
rewrite e in H1.
change ((1 * x)%Z = 0%Z) in H1.
rewrite Zmult_1_l in H1.
assumption.
intro.
rewrite e.
rewrite Zmult_1_l.
rewrite Zmult_1_l.
reflexivity.
intro.
rewrite e.
ring.
rewrite Zmult_1_l in H1.
rewrite H1.
reflexivity.
intro.
unfold Zsgn at 1 in |- *.
unfold Zsgn at 2 in |- *.
intro.
transitivity (Zsgn b * (-1 * (Zsgn b * y)))%Z.
case (Zsgn_1 b).
intros.
case s.
intro.
apply False_ind.
apply H.
apply Zopp_inj.
transitivity (-1 * x)%Z.
ring.
unfold Zopp in |- *.
rewrite e in H1.
transitivity (0 * y)%Z.
assumption.
simpl in |- *.
reflexivity.
intro.
rewrite e.
ring.
intro.
rewrite e.
ring.
rewrite <- H1.
ring.
Qed.
Lemma Zsgn_6 : forall x : Z, x = 0%Z -> Zsgn x = 0%Z.
Proof.
intros.
rewrite H.
simpl in |- *.
reflexivity.
Qed.
Lemma Zsgn_7 : forall x : Z, (x > 0)%Z -> Zsgn x = 1%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
apply (Zlt_irrefl 0).
Flip.
intros.
simpl in |- *.
reflexivity.
intros.
apply False_ind.
apply (Zlt_irrefl (Zneg p)).
apply Zlt_trans with 0%Z.
constructor.
Flip.
Qed.
Lemma Zsgn_7' : forall x : Z, (0 < x)%Z -> Zsgn x = 1%Z.
Proof.
intros; apply Zsgn_7; Flip.
Qed.
Lemma Zsgn_8 : forall x : Z, (x < 0)%Z -> Zsgn x = (-1)%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
apply (Zlt_irrefl 0).
assumption.
intros.
apply False_ind.
apply (Zlt_irrefl 0).
apply Zlt_trans with (Zpos p).
constructor.
assumption.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma Zsgn_9 : forall x : Z, Zsgn x = 1%Z -> (0 < x)%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
simpl in H.
discriminate.
intros.
constructor.
intros.
apply False_ind.
discriminate.
Qed.
Lemma Zsgn_10 : forall x : Z, Zsgn x = (-1)%Z -> (x < 0)%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
discriminate.
intros.
apply False_ind.
discriminate.
intros.
constructor.
Qed.
Lemma Zsgn_11 : forall x : Z, (Zsgn x < 0)%Z -> (x < 0)%Z.
Proof.
intros.
apply Zsgn_10.
case (Zsgn_1 x).
intro.
apply False_ind.
case s.
intro.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
apply (H0 e).
intro.
rewrite e in H.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
discriminate.
trivial.
Qed.
Lemma Zsgn_12 : forall x : Z, (0 < Zsgn x)%Z -> (0 < x)%Z.
Proof.
intros.
apply Zsgn_9.
case (Zsgn_1 x).
intro.
case s.
intro.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
generalize (sym_eq e).
intro.
apply False_ind.
apply (H0 H1).
trivial.
intro.
rewrite e in H.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
apply False_ind.
discriminate.
Qed.
Lemma Zsgn_13 : forall x : Z, (0 <= Zsgn x)%Z -> (0 <= x)%Z.
Proof.
intros.
case (Z_le_lt_eq_dec 0 (Zsgn x) H).
intro.
apply Zlt_le_weak.
apply Zsgn_12.
assumption.
intro.
assert (x = 0%Z).
apply Zsgn_2.
symmetry in |- *.
assumption.
rewrite H0.
apply Zle_refl.
Qed.
Lemma Zsgn_14 : forall x : Z, (Zsgn x <= 0)%Z -> (x <= 0)%Z.
Proof.
intros.
case (Z_le_lt_eq_dec (Zsgn x) 0 H).
intro.
apply Zlt_le_weak.
apply Zsgn_11.
assumption.
intro.
assert (x = 0%Z).
apply Zsgn_2.
assumption.
rewrite H0.
apply Zle_refl.
Qed.
Lemma Zsgn_15 : forall x y : Z, Zsgn (x * y) = (Zsgn x * Zsgn y)%Z.
Proof.
intros [|p1|p1]; [intros y|intros [|p2|p2] ..]; simpl in |- *; constructor.
Qed.
Lemma Zsgn_16 :
forall x y : Z,
Zsgn (x * y) = 1%Z -> {(0 < x)%Z /\ (0 < y)%Z} + {(x < 0)%Z /\ (y < 0)%Z}.
Proof.
intros [|p1|p1]; [intros y|intros [|p2|p2] ..]; simpl in |- *; intro H;
try discriminate H; [ left | right ]; repeat split.
Qed.
Lemma Zsgn_17 :
forall x y : Z,
Zsgn (x * y) = (-1)%Z -> {(0 < x)%Z /\ (y < 0)%Z} + {(x < 0)%Z /\ (0 < y)%Z}.
Proof.
intros [|p1|p1]; [intros y|intros [|p2|p2] ..]; simpl in |- *; intro H;
try discriminate H; [ left | right ]; repeat split.
Qed.
Lemma Zsgn_18 : forall x y : Z, Zsgn (x * y) = 0%Z -> {x = 0%Z} + {y = 0%Z}.
Proof.
intros [|p1|p1]; [intros y|intros [|p2|p2] ..]; simpl in |- *; intro H;
try discriminate H; [ left | right | right ]; constructor.
Qed.
Lemma Zsgn_19 : forall x y : Z, (0 < Zsgn x + Zsgn y)%Z -> (0 < x + y)%Z.
Proof.
Proof.
intros [|p1|p1]; [intros y|intros [|p2|p2] ..]; simpl in |- *; intro H;
discriminate H || (constructor || apply Zsgn_12; assumption).
Qed.
Lemma Zsgn_20 : forall x y : Z, (Zsgn x + Zsgn y < 0)%Z -> (x + y < 0)%Z.
Proof.
Proof.
intros [|p1|p1]; [intros y|intros [|p2|p2] ..]; simpl in |- *; intro H;
discriminate H || (constructor || apply Zsgn_11; assumption).
Qed.
Lemma Zsgn_21 : forall x y : Z, (0 < Zsgn x + Zsgn y)%Z -> (0 <= x)%Z.
Proof.
intros [|p1|p1]; [intros y|intros [|p2|p2] ..]; simpl in |- *; intros H H0;
discriminate H || discriminate H0.
Qed.
Lemma Zsgn_22 : forall x y : Z, (Zsgn x + Zsgn y < 0)%Z -> (x <= 0)%Z.
Proof.
Proof.
intros [|p1|p1]; [intros y|intros [|p2|p2] ..]; simpl in |- *; intros H H0;
discriminate H || discriminate H0.
Qed.
Lemma Zsgn_23 : forall x y : Z, (0 < Zsgn x + Zsgn y)%Z -> (0 <= y)%Z.
Proof.
intros [|p1|p1] [|p2|p2]; simpl in |- *;
intros H H0; discriminate H || discriminate H0.
Qed.
Lemma Zsgn_24 : forall x y : Z, (Zsgn x + Zsgn y < 0)%Z -> (y <= 0)%Z.
Proof.
intros [|p1|p1] [|p2|p2]; simpl in |- *;
intros H H0; discriminate H || discriminate H0.
Qed.
Lemma Zsgn_25 : forall x : Z, Zsgn (- x) = (- Zsgn x)%Z.
Proof.
intros [| p1| p1]; simpl in |- *; reflexivity.
Qed.
Lemma Zsgn_26 : forall x : Z, (0 < x)%Z -> (0 < Zsgn x)%Z.
Proof.
intros [| p| p] Hp; trivial.
Qed.
Lemma Zsgn_27 : forall x : Z, (x < 0)%Z -> (Zsgn x < 0)%Z.
Proof.
intros [| p| p] Hp; trivial.
Qed.
Hint Resolve Zsgn_1 Zsgn_2 Zsgn_3 Zsgn_4 Zsgn_5 Zsgn_6 Zsgn_7 Zsgn_7' Zsgn_8
Zsgn_9 Zsgn_10 Zsgn_11 Zsgn_12 Zsgn_13 Zsgn_14 Zsgn_15 Zsgn_16 Zsgn_17
Zsgn_18 Zsgn_19 Zsgn_20 Zsgn_21 Zsgn_22 Zsgn_23 Zsgn_24 Zsgn_25 Zsgn_26
Zsgn_27: zarith.
(*###########################################################################*)
(** Properties of Zabs *)
(*###########################################################################*)
Lemma Zabs_1 : forall z p : Z, (Zabs z < p)%Z -> (z < p)%Z /\ (- p < z)%Z.
Proof.
intros z p.
case z.
intros.
simpl in H.
split.
assumption.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
replace (-1)%Z with (Zpred 0).
apply Zlt_pred.
simpl; trivial.
ring_simplify (-1 * - p)%Z (-1 * 0)%Z.
apply Zlt_gt.
assumption.
intros.
simpl in H.
split.
assumption.
apply Zlt_trans with (m := 0%Z).
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
replace (-1)%Z with (Zpred 0).
apply Zlt_pred.
simpl; trivial.
ring_simplify (-1 * - p)%Z (-1 * 0)%Z.
apply Zlt_gt.
apply Zlt_trans with (m := Zpos p0).
constructor.
assumption.
constructor.
intros.
simpl in H.
split.
apply Zlt_trans with (m := Zpos p0).
constructor.
assumption.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
replace (-1)%Z with (Zpred 0).
apply Zlt_pred.
simpl;trivial.
ring_simplify (-1 * - p)%Z.
replace (-1 * Zneg p0)%Z with (- Zneg p0)%Z.
replace (- Zneg p0)%Z with (Zpos p0).
apply Zlt_gt.
assumption.
symmetry in |- *.
apply Zopp_neg.
rewrite Zopp_mult_distr_l_reverse with (n := 1%Z).
simpl in |- *.
constructor.
Qed.
Lemma Zabs_2 : forall z p : Z, (Zabs z > p)%Z -> (z > p)%Z \/ (- p > z)%Z.
Proof.
intros z p.
case z.
intros.
simpl in H.
left.
assumption.
intros.
simpl in H.
left.
assumption.
intros.
simpl in H.
right.
apply Zlt_gt.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
ring_simplify (-1 * - p)%Z.
replace (-1 * Zneg p0)%Z with (Zpos p0).
assumption.
reflexivity.
Qed.
Lemma Zabs_3 : forall z p : Z, (z < p)%Z /\ (- p < z)%Z -> (Zabs z < p)%Z.
Proof.
intros z p.
case z.
intro.
simpl in |- *.
elim H.
intros.
assumption.
intros.
elim H.
intros.
simpl in |- *.
assumption.
intros.
elim H.
intros.
simpl in |- *.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
replace (-1 * Zpos p0)%Z with (Zneg p0).
replace (-1 * p)%Z with (- p)%Z.
apply Zlt_gt.
assumption.
ring.
simpl in |- *.
reflexivity.
Qed.
Lemma Zabs_4 : forall z p : Z, (Zabs z < p)%Z -> (- p < z < p)%Z.
Proof.
intros.
split.
apply proj2 with (A := (z < p)%Z).
apply Zabs_1.
assumption.
apply proj1 with (B := (- p < z)%Z).
apply Zabs_1.
assumption.
Qed.
Lemma Zabs_5 : forall z p : Z, (Zabs z <= p)%Z -> (- p <= z <= p)%Z.
Proof.
intros.
split.
replace (- p)%Z with (Zsucc (- Zsucc p)).
apply Zlt_le_succ.
apply proj2 with (A := (z < Zsucc p)%Z).
apply Zabs_1.
apply Zle_lt_succ.
assumption.
unfold Zsucc in |- *.
ring.
apply Zlt_succ_le.
apply proj1 with (B := (- Zsucc p < z)%Z).
apply Zabs_1.
apply Zle_lt_succ.
assumption.
Qed.
Lemma Zabs_6 : forall z p : Z, (Zabs z <= p)%Z -> (z <= p)%Z.
Proof.
intros.
apply proj2 with (A := (- p <= z)%Z).
apply Zabs_5.
assumption.
Qed.
Lemma Zabs_7 : forall z p : Z, (Zabs z <= p)%Z -> (- p <= z)%Z.
Proof.
intros.
apply proj1 with (B := (z <= p)%Z).
apply Zabs_5.
assumption.
Qed.
Lemma Zabs_8 : forall z p : Z, (- p <= z <= p)%Z -> (Zabs z <= p)%Z.
Proof.
intros.
apply Zlt_succ_le.
apply Zabs_3.
elim H.
intros.
split.
apply Zle_lt_succ.
assumption.
apply Zlt_le_trans with (m := (- p)%Z).
apply Zgt_lt.
apply Zlt_opp.
apply Zlt_succ.
assumption.
Qed.
Lemma Zabs_min : forall z : Z, Zabs z = Zabs (- z).
Proof.
intro.
case z.
simpl in |- *.
reflexivity.
intro.
simpl in |- *.
reflexivity.
intro.
simpl in |- *.
reflexivity.
Qed.
Lemma Zabs_9 :
forall z p : Z, (0 <= p)%Z -> (p < z)%Z \/ (z < - p)%Z -> (p < Zabs z)%Z.
Proof.
intros.
case H0.
intro.
replace (Zabs z) with z.
assumption.
symmetry in |- *.
apply Zabs_eq.
apply Zlt_le_weak.
apply Zle_lt_trans with (m := p).
assumption.
assumption.
intro.
cut (Zabs z = (- z)%Z).
intro.
rewrite H2.
apply Zmin_cancel_Zlt.
ring_simplify (- - z)%Z.
assumption.
rewrite Zabs_min.
apply Zabs_eq.
apply Zlt_le_weak.
apply Zle_lt_trans with (m := p).
assumption.
apply Zmin_cancel_Zlt.
ring_simplify (- - z)%Z.
assumption.
Qed.
Lemma Zabs_10 : forall z : Z, (0 <= Zabs z)%Z.
Proof.
intro.
case (Z_zerop z).
intro.
rewrite e.
simpl in |- *.
apply Zle_refl.
intro.
case (not_Zeq z 0 n).
intro.
apply Zlt_le_weak.
apply Zabs_9.
apply Zle_refl.
simpl in |- *.
right.
assumption.
intro.
apply Zlt_le_weak.
apply Zabs_9.
apply Zle_refl.
simpl in |- *.
left.
assumption.
Qed.
Lemma Zabs_11 : forall z : Z, z <> 0%Z -> (0 < Zabs z)%Z.
Proof.
intros.
apply Zabs_9.
apply Zle_refl.
simpl in |- *.
apply not_Zeq.
intro.
apply H.
symmetry in |- *.
assumption.
Qed.
Lemma Zabs_12 : forall z m : Z, (m < Zabs z)%Z -> {(m < z)%Z} + {(z < - m)%Z}.
Proof.
intros [| p| p] m; simpl in |- *; intros H;
[ left | left | right; apply Zmin_cancel_Zlt; rewrite Zopp_involutive ];
assumption.
Qed.
Lemma Zabs_mult : forall z p : Z, Zabs (z * p) = (Zabs z * Zabs p)%Z.
Proof.
intros.
case z.
simpl in |- *.
reflexivity.
case p.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
case p.
intro.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma Zabs_plus : forall z p : Z, (Zabs (z + p) <= Zabs z + Zabs p)%Z.
Proof.
intros.
case z.
simpl in |- *.
apply Zle_refl.
case p.
intro.
simpl in |- *.
apply Zle_refl.
intros.
simpl in |- *.
apply Zle_refl.
intros.
unfold Zabs at 2 in |- *.
unfold Zabs at 2 in |- *.
apply Zabs_8.
split.
apply Zplus_le_reg_l with (Zpos p1 - Zneg p0)%Z.
replace (Zpos p1 - Zneg p0 + - (Zpos p1 + Zpos p0))%Z with
(- (Zpos p0 + Zneg p0))%Z.
replace (Zpos p1 - Zneg p0 + (Zpos p1 + Zneg p0))%Z with (2 * Zpos p1)%Z.
replace (- (Zpos p0 + Zneg p0))%Z with 0%Z.
apply Zmult_gt_0_le_0_compat.
constructor.
apply Zlt_le_weak.
constructor.
rewrite <- Zopp_neg with p0.
ring.
ring.
ring.
apply Zplus_le_compat.
apply Zle_refl.
apply Zlt_le_weak.
constructor.
case p.
simpl in |- *.
intro.
apply Zle_refl.
intros.
unfold Zabs at 2 in |- *.
unfold Zabs at 2 in |- *.
apply Zabs_8.
split.
apply Zplus_le_reg_l with (Zpos p1 + Zneg p0)%Z.
replace (Zpos p1 + Zneg p0 + - (Zpos p1 + Zpos p0))%Z with
(Zneg p0 - Zpos p0)%Z.
replace (Zpos p1 + Zneg p0 + (Zneg p1 + Zpos p0))%Z with 0%Z.
apply Zplus_le_reg_l with (Zpos p0).
replace (Zpos p0 + (Zneg p0 - Zpos p0))%Z with (Zneg p0).
simpl in |- *.
apply Zlt_le_weak.
constructor.
ring.
replace (Zpos p1 + Zneg p0 + (Zneg p1 + Zpos p0))%Z with
(Zpos p1 + Zneg p1 + (Zpos p0 + Zneg p0))%Z.
replace 0%Z with (0 + 0)%Z.
apply Zplus_eq_compat.
rewrite <- Zopp_neg with p1.
ring.
rewrite <- Zopp_neg with p0.
ring.
simpl in |- *.
constructor.
ring.
ring.
apply Zplus_le_compat.
apply Zlt_le_weak.
constructor.
apply Zle_refl.
intros.
simpl in |- *.
apply Zle_refl.
Qed.
Lemma Zabs_neg : forall z : Z, (z <= 0)%Z -> Zabs z = (- z)%Z.
Proof.
intro.
case z.
simpl in |- *.
intro.
reflexivity.
intros.
apply False_ind.
apply H.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma Zle_Zabs: forall z, (z <= Zabs z)%Z.
Proof.
intros [|z|z]; simpl; auto with zarith; apply Zle_neg_pos.
Qed.
Hint Resolve Zabs_1 Zabs_2 Zabs_3 Zabs_4 Zabs_5 Zabs_6 Zabs_7 Zabs_8 Zabs_9
Zabs_10 Zabs_11 Zabs_12 Zabs_min Zabs_neg Zabs_mult Zabs_plus Zle_Zabs: zarith.
(*###########################################################################*)
(** Induction on Z *)
(*###########################################################################*)
Lemma Zind :
forall (P : Z -> Prop) (p : Z),
P p ->
(forall q : Z, (p <= q)%Z -> P q -> P (q + 1)%Z) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros P p.
intro.
intro.
cut (forall q : Z, (p <= q)%Z -> exists k : nat, q = (p + k)%Z).
intro.
cut (forall k : nat, P (p + k)%Z).
intro.
intros.
cut (exists k : nat, q = (p + Z_of_nat k)%Z).
intro.
case H4.
intros.
rewrite H5.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
ring_simplify (p + 0)%Z.
assumption.
replace (p + Z_of_nat (S k))%Z with (p + k + 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (Z_of_nat 0).
ring_simplify (- p + (p + Z_of_nat k))%Z.
apply Znat.inj_le.
apply le_O_n.
ring_simplify; auto with arith.
assumption.
rewrite (Znat.inj_S k).
unfold Zsucc in |- *.
ring.
intros.
cut (exists k : nat, (q - p)%Z = Z_of_nat k).
intro.
case H2.
intro k.
intros.
exists k.
apply Zplus_reg_l with (n := (- p)%Z).
replace (- p + q)%Z with (q - p)%Z.
rewrite H3.
ring.
ring.
apply Z_of_nat_complete.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zrec :
forall (P : Z -> Set) (p : Z),
P p ->
(forall q : Z, (p <= q)%Z -> P q -> P (q + 1)%Z) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros F p.
intro.
intro.
cut (forall q : Z, (p <= q)%Z -> {k : nat | q = (p + k)%Z}).
intro.
cut (forall k : nat, F (p + k)%Z).
intro.
intros.
cut {k : nat | q = (p + Z_of_nat k)%Z}.
intro.
case H4.
intros.
rewrite e.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
rewrite Zplus_0_r.
assumption.
replace (p + Z_of_nat (S k))%Z with (p + k + 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (Z_of_nat 0).
replace (- p + (p + Z_of_nat k))%Z with (Z_of_nat k).
apply Znat.inj_le.
apply le_O_n.
rewrite Zplus_assoc; rewrite Zplus_opp_l; reflexivity.
rewrite Zplus_opp_l; reflexivity.
assumption.
rewrite (Znat.inj_S k).
unfold Zsucc in |- *.
apply Zplus_assoc_reverse.
intros.
cut {k : nat | (q - p)%Z = Z_of_nat k}.
intro H2.
case H2.
intro k.
intros.
exists k.
apply Zplus_reg_l with (n := (- p)%Z).
replace (- p + q)%Z with (q - p)%Z.
rewrite e.
rewrite Zplus_assoc; rewrite Zplus_opp_l; reflexivity.
unfold Zminus in |- *.
apply Zplus_comm.
apply Z_of_nat_complete_inf.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zrec_down :
forall (P : Z -> Set) (p : Z),
P p ->
(forall q : Z, (q <= p)%Z -> P q -> P (q - 1)%Z) ->
forall q : Z, (q <= p)%Z -> P q.
Proof.
intros F p.
intro.
intro.
cut (forall q : Z, (q <= p)%Z -> {k : nat | q = (p - k)%Z}).
intro.
cut (forall k : nat, F (p - k)%Z).
intro.
intros.
cut {k : nat | q = (p - Z_of_nat k)%Z}.
intro.
case H4.
intros.
rewrite e.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
replace (p - 0)%Z with p.
assumption.
unfold Zminus in |- *.
unfold Zopp in |- *.
rewrite Zplus_0_r; reflexivity.
replace (p - Z_of_nat (S k))%Z with (p - k - 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (- Z_of_nat 0)%Z.
replace (- p + (p - Z_of_nat k))%Z with (- Z_of_nat k)%Z.
apply Zge_le.
apply Zge_opp.
apply Znat.inj_le.
apply le_O_n.
unfold Zminus in |- *; rewrite Zplus_assoc; rewrite Zplus_opp_l; reflexivity.
rewrite Zplus_opp_l; reflexivity.
assumption.
rewrite (Znat.inj_S k).
unfold Zsucc in |- *.
unfold Zminus at 1 2 in |- *.
rewrite Zplus_assoc_reverse.
rewrite <- Zopp_plus_distr.
reflexivity.
intros.
cut {k : nat | (p - q)%Z = Z_of_nat k}.
intro.
case H2.
intro k.
intros.
exists k.
apply Zopp_inj.
apply Zplus_reg_l with (n := p).
replace (p + - (p - Z_of_nat k))%Z with (Z_of_nat k).
rewrite <- e.
reflexivity.
unfold Zminus in |- *.
rewrite Zopp_plus_distr.
rewrite Zplus_assoc.
rewrite Zplus_opp_r.
rewrite Zopp_involutive.
reflexivity.
apply Z_of_nat_complete_inf.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zind_down :
forall (P : Z -> Prop) (p : Z),
P p ->
(forall q : Z, (q <= p)%Z -> P q -> P (q - 1)%Z) ->
forall q : Z, (q <= p)%Z -> P q.
Proof.
intros F p.
intro.
intro.
cut (forall q : Z, (q <= p)%Z -> exists k : nat, q = (p - k)%Z).
intro.
cut (forall k : nat, F (p - k)%Z).
intro.
intros.
cut (exists k : nat, q = (p - Z_of_nat k)%Z).
intro.
case H4.
intros x e.
rewrite e.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
replace (p - 0)%Z with p.
assumption.
ring.
replace (p - Z_of_nat (S k))%Z with (p - k - 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (- Z_of_nat 0)%Z.
replace (- p + (p - Z_of_nat k))%Z with (- Z_of_nat k)%Z.
apply Zge_le.
apply Zge_opp.
apply Znat.inj_le.
apply le_O_n.
ring.
ring_simplify; auto with arith.
assumption.
rewrite (Znat.inj_S k).
unfold Zsucc in |- *.
ring.
intros.
cut (exists k : nat, (p - q)%Z = Z_of_nat k).
intro.
case H2.
intro k.
intros.
exists k.
apply Zopp_inj.
apply Zplus_reg_l with (n := p).
replace (p + - (p - Z_of_nat k))%Z with (Z_of_nat k).
rewrite <- H3.
ring.
ring.
apply Z_of_nat_complete.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zrec_wf :
forall (P : Z -> Set) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros P p WF_ind_step q Hq.
cut (forall x : Z, (p <= x)%Z -> forall y : Z, (p <= y < x)%Z -> P y).
intro.
apply (H (Zsucc q)).
apply Zle_le_succ.
assumption.
split; [ assumption | exact (Zlt_succ q) ].
intros x0 Hx0; generalize Hx0; pattern x0 in |- *.
apply Zrec with (p := p).
intros.
absurd (p <= p)%Z.
apply Zgt_not_le.
apply Zgt_le_trans with (m := y).
apply Zlt_gt.
elim H.
intros.
assumption.
elim H.
intros.
assumption.
apply Zle_refl.
intros.
apply WF_ind_step.
intros.
apply (H0 H).
split.
elim H2.
intros.
assumption.
apply Zlt_le_trans with y.
elim H2.
intros.
assumption.
apply Zgt_succ_le.
apply Zlt_gt.
elim H1.
intros.
unfold Zsucc in |- *.
assumption.
assumption.
Qed.
Lemma Zrec_wf2 :
forall (q : Z) (P : Z -> Set) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
(p <= q)%Z -> P q.
Proof.
intros.
apply Zrec_wf with (p := p).
assumption.
assumption.
Qed.
Lemma Zrec_wf_double :
forall (P : Z -> Z -> Set) (p0 q0 : Z),
(forall n m : Z,
(forall p q : Z, (q0 <= q)%Z -> (p0 <= p < n)%Z -> P p q) ->
(forall p : Z, (q0 <= p < m)%Z -> P n p) -> P n m) ->
forall p q : Z, (q0 <= q)%Z -> (p0 <= p)%Z -> P p q.
Proof.
intros P p0 q0 Hrec p.
intros.
generalize q H.
pattern p in |- *.
apply Zrec_wf with (p := p0).
intros p1 H1.
intros.
pattern q1 in |- *.
apply Zrec_wf with (p := q0).
intros q2 H3.
apply Hrec.
intros.
apply H1.
assumption.
assumption.
intros.
apply H3.
assumption.
assumption.
assumption.
Qed.
Lemma Zind_wf :
forall (P : Z -> Prop) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros P p WF_ind_step q Hq.
cut (forall x : Z, (p <= x)%Z -> forall y : Z, (p <= y < x)%Z -> P y).
intro.
apply (H (Zsucc q)).
apply Zle_le_succ.
assumption.
split; [ assumption | exact (Zlt_succ q) ].
intros x0 Hx0; generalize Hx0; pattern x0 in |- *.
apply Zind with (p := p).
intros.
absurd (p <= p)%Z.
apply Zgt_not_le.
apply Zgt_le_trans with (m := y).
apply Zlt_gt.
elim H.
intros.
assumption.
elim H.
intros.
assumption.
apply Zle_refl.
intros.
apply WF_ind_step.
intros.
apply (H0 H).
split.
elim H2.
intros.
assumption.
apply Zlt_le_trans with y.
elim H2.
intros.
assumption.
apply Zgt_succ_le.
apply Zlt_gt.
elim H1.
intros.
unfold Zsucc in |- *.
assumption.
assumption.
Qed.
Lemma Zind_wf2 :
forall (q : Z) (P : Z -> Prop) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
(p <= q)%Z -> P q.
Proof.
intros.
apply Zind_wf with (p := p).
assumption.
assumption.
Qed.
Lemma Zind_wf_double :
forall (P : Z -> Z -> Prop) (p0 q0 : Z),
(forall n m : Z,
(forall p q : Z, (q0 <= q)%Z -> (p0 <= p < n)%Z -> P p q) ->
(forall p : Z, (q0 <= p < m)%Z -> P n p) -> P n m) ->
forall p q : Z, (q0 <= q)%Z -> (p0 <= p)%Z -> P p q.
Proof.
intros P p0 q0 Hrec p.
intros.
generalize q H.
pattern p in |- *.
apply Zind_wf with (p := p0).
intros p1 H1.
intros.
pattern q1 in |- *.
apply Zind_wf with (p := q0).
intros q2 H3.
apply Hrec.
intros.
apply H1.
assumption.
assumption.
intros.
apply H3.
assumption.
assumption.
assumption.
Qed.
(*###########################################################################*)
(** Properties of Zmax *)
(*###########################################################################*)
Definition Zmax (n m : Z) := (n + m - Zmin n m)%Z.
Lemma ZmaxSS : forall n m : Z, (Zmax n m + 1)%Z = Zmax (n + 1) (m + 1).
Proof.
intros.
unfold Zmax in |- *.
replace (Zmin (n + 1) (m + 1)) with (Zmin n m + 1)%Z.
ring.
symmetry in |- *.
change (Zmin (Zsucc n) (Zsucc m) = Zsucc (Zmin n m)) in |- *.
symmetry in |- *.
apply Zmin_SS.
Qed.
Lemma Zle_max_l : forall n m : Z, (n <= Zmax n m)%Z.
Proof.
intros.
unfold Zmax in |- *.
apply Zplus_le_reg_l with (p := (- n + Zmin n m)%Z).
ring_simplify (- n + Zmin n m + n)%Z.
ring_simplify (- n + Zmin n m + (n + m - Zmin n m))%Z.
apply Zle_min_r.
Qed.
Lemma Zle_max_r : forall n m : Z, (m <= Zmax n m)%Z.
Proof.
intros.
unfold Zmax in |- *.
apply Zplus_le_reg_l with (p := (- m + Zmin n m)%Z).
ring_simplify (- m + Zmin n m + m)%Z.
ring_simplify (- m + Zmin n m + (n + m - Zmin n m))%Z.
apply Zle_min_l.
Qed.
Lemma Zmin_or_informative : forall n m : Z, {Zmin n m = n} + {Zmin n m = m}.
Proof.
intros.
case (Z_lt_ge_dec n m).
unfold Zmin in |- *.
unfold Zlt in |- *.
intro z.
rewrite z.
left.
reflexivity.
intro.
cut ({(n > m)%Z} + {n = m :>Z}).
intro.
case H.
intros z0.
unfold Zmin in |- *.
unfold Zgt in z0.
rewrite z0.
right.
reflexivity.
intro.
rewrite e.
right.
apply Zmin_n_n.
cut ({(m < n)%Z} + {m = n :>Z}).
intro.
elim H.
intro.
left.
apply Zlt_gt.
assumption.
intro.
right.
symmetry in |- *.
assumption.
apply Z_le_lt_eq_dec.
apply Zge_le.
assumption.
Qed.
Lemma Zmax_case : forall (n m : Z) (P : Z -> Set), P n -> P m -> P (Zmax n m).
Proof.
intros.
unfold Zmax in |- *.
case Zmin_or_informative with (n := n) (m := m).
intro.
rewrite e.
cut ((n + m - n)%Z = m).
intro.
rewrite H1.
assumption.
ring.
intro.
rewrite e.
cut ((n + m - m)%Z = n).
intro.
rewrite H1.
assumption.
ring.
Qed.
Lemma Zmax_or_informative : forall n m : Z, {Zmax n m = n} + {Zmax n m = m}.
Proof.
intros.
unfold Zmax in |- *.
case Zmin_or_informative with (n := n) (m := m).
intro.
rewrite e.
right.
ring.
intro.
rewrite e.
left.
ring.
Qed.
Lemma Zmax_n_n : forall n : Z, Zmax n n = n.
Proof.
intros.
unfold Zmax in |- *.
rewrite (Zmin_n_n n).
ring.
Qed.
Hint Resolve ZmaxSS Zle_max_r Zle_max_l Zmax_n_n: zarith.
(*###########################################################################*)
(** Properties of Arity *)
(*###########################################################################*)
Lemma Zeven_S : forall x : Z, Zeven.Zodd x -> Zeven.Zeven (x + 1).
Proof.
exact Zeven.Zeven_Sn.
Qed.
Lemma Zeven_pred : forall x : Z, Zeven.Zodd x -> Zeven.Zeven (x - 1).
Proof.
exact Zeven.Zeven_pred.
Qed.
(* This lemma used to be useful since it was mentioned with an unnecessary premise
`x>=0` as Z_modulo_2 in ZArith, but the ZArith version has been fixed. *)
Definition Z_modulo_2_always :
forall x : Z, {y : Z | x = (2 * y)%Z} + {y : Z | x = (2 * y + 1)%Z} :=
Zeven.Z_modulo_2.
(*###########################################################################*)
(** Properties of Zdiv *)
(*###########################################################################*)
Lemma Z_div_mod_eq_2 :
forall a b : Z, (0 < b)%Z -> (b * (a / b))%Z = (a - a mod b)%Z.
Proof.
intros.
apply Zplus_minus_eq.
rewrite Zplus_comm.
apply Z_div_mod_eq.
Flip.
Qed.
Lemma Z_div_le :
forall a b c : Z, (0 < c)%Z -> (b <= a)%Z -> (b / c <= a / c)%Z.
Proof.
intros.
apply Zge_le.
apply Z_div_ge; Flip; assumption.
Qed.
Lemma Z_div_nonneg :
forall a b : Z, (0 < b)%Z -> (0 <= a)%Z -> (0 <= a / b)%Z.
Proof.
intros.
apply Zge_le.
apply Z_div_ge0; Flip; assumption.
Qed.
Lemma Z_div_neg : forall a b : Z, (0 < b)%Z -> (a < 0)%Z -> (a / b < 0)%Z.
Proof.
intros.
rewrite (Z_div_mod_eq a b) in H0.
elim (Z_mod_lt a b).
intros H1 _.
apply Znot_ge_lt.
intro.
apply (Zlt_not_le (b * (a / b) + a mod b) 0 H0).
apply Zplus_le_0_compat.
apply Zmult_le_0_compat.
apply Zlt_le_weak; assumption.
Flip.
assumption.
Flip.
Flip.
Qed.
Hint Resolve Z_div_mod_eq_2 Z_div_le Z_div_nonneg Z_div_neg: zarith.
(*###########################################################################*)
(** Properties of Zpower *)
(*###########################################################################*)
Lemma Zpower_1 : forall a : Z, (a ^ 1)%Z = a.
Proof.
intros; unfold Zpower in |- *; unfold Zpower_pos in |- *; simpl in |- *;
auto with zarith.
Qed.
Lemma Zpower_2 : forall a : Z, (a ^ 2)%Z = (a * a)%Z.
Proof.
intros; unfold Zpower in |- *; unfold Zpower_pos in |- *; simpl in |- *;
ring.
Qed.
Hint Resolve Zpower_1 Zpower_2: zarith.
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2022 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Outputs
out,
// Inputs
clk_0, clk_1, clk_2, clk_3, clk_4, clk_5, clk_6, clk_7, clk_8, clk_9, clk_10,
clk_11, clk_12, clk_13, clk_14, clk_15, clk_16, clk_17, clk_18, clk_19,
rstn_0, rstn_1, rstn_2, rstn_3, rstn_4, rstn_5, rstn_6, rstn_7, rstn_8,
rstn_9, rstn_10, rstn_11, rstn_12, rstn_13, rstn_14, rstn_15, rstn_16,
rstn_17, rstn_18, rstn_19
);
input clk_0;
input clk_1;
input clk_2;
input clk_3;
input clk_4;
input clk_5;
input clk_6;
input clk_7;
input clk_8;
input clk_9;
input clk_10;
input clk_11;
input clk_12;
input clk_13;
input clk_14;
input clk_15;
input clk_16;
input clk_17;
input clk_18;
input clk_19;
input rstn_0;
input rstn_1;
input rstn_2;
input rstn_3;
input rstn_4;
input rstn_5;
input rstn_6;
input rstn_7;
input rstn_8;
input rstn_9;
input rstn_10;
input rstn_11;
input rstn_12;
input rstn_13;
input rstn_14;
input rstn_15;
input rstn_16;
input rstn_17;
input rstn_18;
input rstn_19;
// verilator lint_off MULTIDRIVEN
output reg out [0:29-1];
always_ff @(posedge clk_0, negedge rstn_0) if ((rstn_0 == 0)) out[0] <= 0;
always_ff @(posedge clk_1, negedge rstn_1) if ((rstn_1 == 0)) out[1] <= 0;
always_ff @(posedge clk_2, negedge rstn_2) if ((rstn_2 == 0)) out[2] <= 0;
always_ff @(posedge clk_3, negedge rstn_3) if ((rstn_3 == 0)) out[3] <= 0;
always_ff @(posedge clk_4, negedge rstn_4) if ((rstn_4 == 0)) out[4] <= 0;
always_ff @(posedge clk_5, negedge rstn_5) if ((rstn_5 == 0)) out[5] <= 0;
always_ff @(posedge clk_6, negedge rstn_6) if ((rstn_6 == 0)) out[6] <= 0;
always_ff @(posedge clk_7, negedge rstn_7) if ((rstn_7 == 0)) out[7] <= 0;
always_ff @(posedge clk_8, negedge rstn_8) if ((rstn_8 == 0)) out[8] <= 0;
always_ff @(posedge clk_9, negedge rstn_9) if ((rstn_9 == 0)) out[9] <= 0;
always_ff @(posedge clk_10, negedge rstn_10) if ((rstn_10 == 0)) out[10] <= 0;
always_ff @(posedge clk_11, negedge rstn_11) if ((rstn_11 == 0)) out[11] <= 0;
always_ff @(posedge clk_12, negedge rstn_12) if ((rstn_12 == 0)) out[12] <= 0;
always_ff @(posedge clk_13, negedge rstn_13) if ((rstn_13 == 0)) out[13] <= 0;
always_ff @(posedge clk_14, negedge rstn_14) if ((rstn_14 == 0)) out[14] <= 0;
always_ff @(posedge clk_15, negedge rstn_15) if ((rstn_15 == 0)) out[15] <= 0;
always_ff @(posedge clk_16, negedge rstn_16) if ((rstn_16 == 0)) out[16] <= 0;
always_ff @(posedge clk_17, negedge rstn_17) if ((rstn_17 == 0)) out[17] <= 0;
always_ff @(posedge clk_18, negedge rstn_18) if ((rstn_18 == 0)) out[18] <= 0;
always_ff @(posedge clk_19, negedge rstn_19) if ((rstn_19 == 0)) out[19] <= 0;
endmodule
|
/*
`gcd16.v'
Balsa Verilog netlist file
Created: Fri Jan 10 11:55:03 JST 2014
By: xaos@kikurage (Linux)
With net-verilog (balsa-netlist) version: 4.0
Using technology: aclass/four_b_rb
Command line : (balsa-netlist -Xaclass gcd16.breeze)
Using `propagate-globals'
The design contains the following global nets
global-signal: initialise input 1
*/
module ao22 (
q,
i0,
i1,
i2,
i3
);
output q;
input i0;
input i1;
input i2;
input i3;
wire [1:0] int_0n;
OR2 I0 (q, int_0n[0], int_0n[1]);
AN2 I1 (int_0n[1], i2, i3);
AN2 I2 (int_0n[0], i0, i1);
endmodule
module mux2 (
out,
in0,
in1,
sel
);
output out;
input in0;
input in1;
input sel;
wire nsel_0n;
ao22 I0 (out, in0, nsel_0n, in1, sel);
IV I1 (nsel_0n, sel);
endmodule
module aoi22 (
q,
i0,
i1,
i2,
i3
);
output q;
input i0;
input i1;
input i2;
input i3;
wire [1:0] int_0n;
NR2 I0 (q, int_0n[0], int_0n[1]);
AN2 I1 (int_0n[1], i2, i3);
AN2 I2 (int_0n[0], i0, i1);
endmodule
module nmux2 (
out,
in0,
in1,
sel
);
output out;
input in0;
input in1;
input sel;
wire nsel_0n;
aoi22 I0 (out, in0, nsel_0n, in1, sel);
IV I1 (nsel_0n, sel);
endmodule
module balsa_fa (
nStart,
A,
B,
nCVi,
Ci,
nCVo,
Co,
sum
);
input nStart;
input A;
input B;
input nCVi;
input Ci;
output nCVo;
output Co;
output sum;
wire start;
wire ha;
wire cv;
IV I0 (start, nStart);
NR2 I1 (cv, nStart, nCVi);
nmux2 I2 (nCVo, start, cv, ha);
mux2 I3 (Co, A, Ci, ha);
EO I4 (ha, A, B);
EO I5 (sum, ha, Ci);
endmodule
module buf1 (
z,
a
);
output z;
input a;
wire na_0n;
IV I0 (z, na_0n);
IV I1 (na_0n, a);
endmodule
module BrzBinaryFunc_1_16_16_s11_GreaterThan_s5_f_m13m (
out_0r, out_0a, out_0d,
inpA_0r, inpA_0a, inpA_0d,
inpB_0r, inpB_0a, inpB_0d
);
input out_0r;
output out_0a;
output out_0d;
output inpA_0r;
input inpA_0a;
input [15:0] inpA_0d;
output inpB_0r;
input inpB_0a;
input [15:0] inpB_0d;
wire [7:0] internal_0n;
wire start_0n;
wire nStart_0n;
wire [16:0] nCv_0n;
wire [16:0] c_0n;
wire [15:0] eq_0n;
wire [15:0] addOut_0n;
wire [15:0] w_0n;
wire [15:0] n_0n;
wire v_0n;
wire z_0n;
wire nz_0n;
wire nxv_0n;
wire done_0n;
wire vcc;
VCC vcc_cell_instance (vcc);
NR2 I0 (out_0d, z_0n, nxv_0n);
EO I1 (nxv_0n, v_0n, addOut_0n[15]);
NR4 I2 (internal_0n[0], addOut_0n[0], addOut_0n[1], addOut_0n[2], addOut_0n[3]);
NR4 I3 (internal_0n[1], addOut_0n[4], addOut_0n[5], addOut_0n[6], addOut_0n[7]);
NR4 I4 (internal_0n[2], addOut_0n[8], addOut_0n[9], addOut_0n[10], addOut_0n[11]);
NR4 I5 (internal_0n[3], addOut_0n[12], addOut_0n[13], addOut_0n[14], addOut_0n[15]);
AN4 I6 (z_0n, internal_0n[0], internal_0n[1], internal_0n[2], internal_0n[3]);
NR4 I7 (internal_0n[4], nCv_0n[1], nCv_0n[2], nCv_0n[3], nCv_0n[4]);
NR4 I8 (internal_0n[5], nCv_0n[5], nCv_0n[6], nCv_0n[7], nCv_0n[8]);
NR4 I9 (internal_0n[6], nCv_0n[9], nCv_0n[10], nCv_0n[11], nCv_0n[12]);
NR4 I10 (internal_0n[7], nCv_0n[13], nCv_0n[14], nCv_0n[15], nCv_0n[16]);
AN4 I11 (done_0n, internal_0n[4], internal_0n[5], internal_0n[6], internal_0n[7]);
EO I12 (v_0n, c_0n[15], c_0n[16]);
balsa_fa I13 (nStart_0n, n_0n[0], w_0n[0], nCv_0n[0], c_0n[0], nCv_0n[1], c_0n[1], addOut_0n[0]);
balsa_fa I14 (nStart_0n, n_0n[1], w_0n[1], nCv_0n[1], c_0n[1], nCv_0n[2], c_0n[2], addOut_0n[1]);
balsa_fa I15 (nStart_0n, n_0n[2], w_0n[2], nCv_0n[2], c_0n[2], nCv_0n[3], c_0n[3], addOut_0n[2]);
balsa_fa I16 (nStart_0n, n_0n[3], w_0n[3], nCv_0n[3], c_0n[3], nCv_0n[4], c_0n[4], addOut_0n[3]);
balsa_fa I17 (nStart_0n, n_0n[4], w_0n[4], nCv_0n[4], c_0n[4], nCv_0n[5], c_0n[5], addOut_0n[4]);
balsa_fa I18 (nStart_0n, n_0n[5], w_0n[5], nCv_0n[5], c_0n[5], nCv_0n[6], c_0n[6], addOut_0n[5]);
balsa_fa I19 (nStart_0n, n_0n[6], w_0n[6], nCv_0n[6], c_0n[6], nCv_0n[7], c_0n[7], addOut_0n[6]);
balsa_fa I20 (nStart_0n, n_0n[7], w_0n[7], nCv_0n[7], c_0n[7], nCv_0n[8], c_0n[8], addOut_0n[7]);
balsa_fa I21 (nStart_0n, n_0n[8], w_0n[8], nCv_0n[8], c_0n[8], nCv_0n[9], c_0n[9], addOut_0n[8]);
balsa_fa I22 (nStart_0n, n_0n[9], w_0n[9], nCv_0n[9], c_0n[9], nCv_0n[10], c_0n[10], addOut_0n[9]);
balsa_fa I23 (nStart_0n, n_0n[10], w_0n[10], nCv_0n[10], c_0n[10], nCv_0n[11], c_0n[11], addOut_0n[10]);
balsa_fa I24 (nStart_0n, n_0n[11], w_0n[11], nCv_0n[11], c_0n[11], nCv_0n[12], c_0n[12], addOut_0n[11]);
balsa_fa I25 (nStart_0n, n_0n[12], w_0n[12], nCv_0n[12], c_0n[12], nCv_0n[13], c_0n[13], addOut_0n[12]);
balsa_fa I26 (nStart_0n, n_0n[13], w_0n[13], nCv_0n[13], c_0n[13], nCv_0n[14], c_0n[14], addOut_0n[13]);
balsa_fa I27 (nStart_0n, n_0n[14], w_0n[14], nCv_0n[14], c_0n[14], nCv_0n[15], c_0n[15], addOut_0n[14]);
balsa_fa I28 (nStart_0n, n_0n[15], w_0n[15], nCv_0n[15], c_0n[15], nCv_0n[16], c_0n[16], addOut_0n[15]);
assign nCv_0n[0] = nStart_0n;
assign c_0n[0] = vcc;
IV I31 (nStart_0n, start_0n);
IV I32 (n_0n[0], inpB_0d[0]);
IV I33 (n_0n[1], inpB_0d[1]);
IV I34 (n_0n[2], inpB_0d[2]);
IV I35 (n_0n[3], inpB_0d[3]);
IV I36 (n_0n[4], inpB_0d[4]);
IV I37 (n_0n[5], inpB_0d[5]);
IV I38 (n_0n[6], inpB_0d[6]);
IV I39 (n_0n[7], inpB_0d[7]);
IV I40 (n_0n[8], inpB_0d[8]);
IV I41 (n_0n[9], inpB_0d[9]);
IV I42 (n_0n[10], inpB_0d[10]);
IV I43 (n_0n[11], inpB_0d[11]);
IV I44 (n_0n[12], inpB_0d[12]);
IV I45 (n_0n[13], inpB_0d[13]);
IV I46 (n_0n[14], inpB_0d[14]);
IV I47 (n_0n[15], inpB_0d[15]);
assign w_0n[0] = inpA_0d[0];
assign w_0n[1] = inpA_0d[1];
assign w_0n[2] = inpA_0d[2];
assign w_0n[3] = inpA_0d[3];
assign w_0n[4] = inpA_0d[4];
assign w_0n[5] = inpA_0d[5];
assign w_0n[6] = inpA_0d[6];
assign w_0n[7] = inpA_0d[7];
assign w_0n[8] = inpA_0d[8];
assign w_0n[9] = inpA_0d[9];
assign w_0n[10] = inpA_0d[10];
assign w_0n[11] = inpA_0d[11];
assign w_0n[12] = inpA_0d[12];
assign w_0n[13] = inpA_0d[13];
assign w_0n[14] = inpA_0d[14];
assign w_0n[15] = inpA_0d[15];
assign out_0a = done_0n;
C2 I65 (start_0n, inpA_0a, inpB_0a);
assign inpA_0r = out_0r;
assign inpB_0r = out_0r;
endmodule
module BrzBinaryFunc_1_16_16_s9_NotEquals_s5_fals_m14m (
out_0r, out_0a, out_0d,
inpA_0r, inpA_0a, inpA_0d,
inpB_0r, inpB_0a, inpB_0d
);
input out_0r;
output out_0a;
output out_0d;
output inpA_0r;
input inpA_0a;
input [15:0] inpA_0d;
output inpB_0r;
input inpB_0a;
input [15:0] inpB_0d;
wire [3:0] internal_0n;
wire start_0n;
wire nStart_0n;
wire [16:0] nCv_0n;
wire [16:0] c_0n;
wire [15:0] eq_0n;
wire [15:0] addOut_0n;
wire [15:0] w_0n;
wire [15:0] n_0n;
wire v_0n;
wire z_0n;
wire nz_0n;
wire nxv_0n;
wire done_0n;
NR4 I0 (internal_0n[0], eq_0n[0], eq_0n[1], eq_0n[2], eq_0n[3]);
NR4 I1 (internal_0n[1], eq_0n[4], eq_0n[5], eq_0n[6], eq_0n[7]);
NR4 I2 (internal_0n[2], eq_0n[8], eq_0n[9], eq_0n[10], eq_0n[11]);
NR4 I3 (internal_0n[3], eq_0n[12], eq_0n[13], eq_0n[14], eq_0n[15]);
ND4 I4 (out_0d, internal_0n[0], internal_0n[1], internal_0n[2], internal_0n[3]);
EO I5 (eq_0n[0], w_0n[0], n_0n[0]);
EO I6 (eq_0n[1], w_0n[1], n_0n[1]);
EO I7 (eq_0n[2], w_0n[2], n_0n[2]);
EO I8 (eq_0n[3], w_0n[3], n_0n[3]);
EO I9 (eq_0n[4], w_0n[4], n_0n[4]);
EO I10 (eq_0n[5], w_0n[5], n_0n[5]);
EO I11 (eq_0n[6], w_0n[6], n_0n[6]);
EO I12 (eq_0n[7], w_0n[7], n_0n[7]);
EO I13 (eq_0n[8], w_0n[8], n_0n[8]);
EO I14 (eq_0n[9], w_0n[9], n_0n[9]);
EO I15 (eq_0n[10], w_0n[10], n_0n[10]);
EO I16 (eq_0n[11], w_0n[11], n_0n[11]);
EO I17 (eq_0n[12], w_0n[12], n_0n[12]);
EO I18 (eq_0n[13], w_0n[13], n_0n[13]);
EO I19 (eq_0n[14], w_0n[14], n_0n[14]);
EO I20 (eq_0n[15], w_0n[15], n_0n[15]);
assign done_0n = start_0n;
assign n_0n[0] = inpB_0d[0];
assign n_0n[1] = inpB_0d[1];
assign n_0n[2] = inpB_0d[2];
assign n_0n[3] = inpB_0d[3];
assign n_0n[4] = inpB_0d[4];
assign n_0n[5] = inpB_0d[5];
assign n_0n[6] = inpB_0d[6];
assign n_0n[7] = inpB_0d[7];
assign n_0n[8] = inpB_0d[8];
assign n_0n[9] = inpB_0d[9];
assign n_0n[10] = inpB_0d[10];
assign n_0n[11] = inpB_0d[11];
assign n_0n[12] = inpB_0d[12];
assign n_0n[13] = inpB_0d[13];
assign n_0n[14] = inpB_0d[14];
assign n_0n[15] = inpB_0d[15];
assign w_0n[0] = inpA_0d[0];
assign w_0n[1] = inpA_0d[1];
assign w_0n[2] = inpA_0d[2];
assign w_0n[3] = inpA_0d[3];
assign w_0n[4] = inpA_0d[4];
assign w_0n[5] = inpA_0d[5];
assign w_0n[6] = inpA_0d[6];
assign w_0n[7] = inpA_0d[7];
assign w_0n[8] = inpA_0d[8];
assign w_0n[9] = inpA_0d[9];
assign w_0n[10] = inpA_0d[10];
assign w_0n[11] = inpA_0d[11];
assign w_0n[12] = inpA_0d[12];
assign w_0n[13] = inpA_0d[13];
assign w_0n[14] = inpA_0d[14];
assign w_0n[15] = inpA_0d[15];
assign out_0a = done_0n;
C2 I55 (start_0n, inpA_0a, inpB_0a);
assign inpA_0r = out_0r;
assign inpB_0r = out_0r;
endmodule
module BrzBinaryFunc_16_16_16_s8_Subtract_s5_fals_m15m (
out_0r, out_0a, out_0d,
inpA_0r, inpA_0a, inpA_0d,
inpB_0r, inpB_0a, inpB_0d
);
input out_0r;
output out_0a;
output [15:0] out_0d;
output inpA_0r;
input inpA_0a;
input [15:0] inpA_0d;
output inpB_0r;
input inpB_0a;
input [15:0] inpB_0d;
wire [3:0] internal_0n;
wire start_0n;
wire nStart_0n;
wire [16:0] nCv_0n;
wire [16:0] c_0n;
wire [15:0] eq_0n;
wire [15:0] addOut_0n;
wire [15:0] w_0n;
wire [15:0] n_0n;
wire v_0n;
wire z_0n;
wire nz_0n;
wire nxv_0n;
wire done_0n;
wire vcc;
VCC vcc_cell_instance (vcc);
NR4 I0 (internal_0n[0], nCv_0n[1], nCv_0n[2], nCv_0n[3], nCv_0n[4]);
NR4 I1 (internal_0n[1], nCv_0n[5], nCv_0n[6], nCv_0n[7], nCv_0n[8]);
NR4 I2 (internal_0n[2], nCv_0n[9], nCv_0n[10], nCv_0n[11], nCv_0n[12]);
NR4 I3 (internal_0n[3], nCv_0n[13], nCv_0n[14], nCv_0n[15], nCv_0n[16]);
AN4 I4 (done_0n, internal_0n[0], internal_0n[1], internal_0n[2], internal_0n[3]);
assign out_0d[0] = addOut_0n[0];
assign out_0d[1] = addOut_0n[1];
assign out_0d[2] = addOut_0n[2];
assign out_0d[3] = addOut_0n[3];
assign out_0d[4] = addOut_0n[4];
assign out_0d[5] = addOut_0n[5];
assign out_0d[6] = addOut_0n[6];
assign out_0d[7] = addOut_0n[7];
assign out_0d[8] = addOut_0n[8];
assign out_0d[9] = addOut_0n[9];
assign out_0d[10] = addOut_0n[10];
assign out_0d[11] = addOut_0n[11];
assign out_0d[12] = addOut_0n[12];
assign out_0d[13] = addOut_0n[13];
assign out_0d[14] = addOut_0n[14];
assign out_0d[15] = addOut_0n[15];
balsa_fa I21 (nStart_0n, n_0n[0], w_0n[0], nCv_0n[0], c_0n[0], nCv_0n[1], c_0n[1], addOut_0n[0]);
balsa_fa I22 (nStart_0n, n_0n[1], w_0n[1], nCv_0n[1], c_0n[1], nCv_0n[2], c_0n[2], addOut_0n[1]);
balsa_fa I23 (nStart_0n, n_0n[2], w_0n[2], nCv_0n[2], c_0n[2], nCv_0n[3], c_0n[3], addOut_0n[2]);
balsa_fa I24 (nStart_0n, n_0n[3], w_0n[3], nCv_0n[3], c_0n[3], nCv_0n[4], c_0n[4], addOut_0n[3]);
balsa_fa I25 (nStart_0n, n_0n[4], w_0n[4], nCv_0n[4], c_0n[4], nCv_0n[5], c_0n[5], addOut_0n[4]);
balsa_fa I26 (nStart_0n, n_0n[5], w_0n[5], nCv_0n[5], c_0n[5], nCv_0n[6], c_0n[6], addOut_0n[5]);
balsa_fa I27 (nStart_0n, n_0n[6], w_0n[6], nCv_0n[6], c_0n[6], nCv_0n[7], c_0n[7], addOut_0n[6]);
balsa_fa I28 (nStart_0n, n_0n[7], w_0n[7], nCv_0n[7], c_0n[7], nCv_0n[8], c_0n[8], addOut_0n[7]);
balsa_fa I29 (nStart_0n, n_0n[8], w_0n[8], nCv_0n[8], c_0n[8], nCv_0n[9], c_0n[9], addOut_0n[8]);
balsa_fa I30 (nStart_0n, n_0n[9], w_0n[9], nCv_0n[9], c_0n[9], nCv_0n[10], c_0n[10], addOut_0n[9]);
balsa_fa I31 (nStart_0n, n_0n[10], w_0n[10], nCv_0n[10], c_0n[10], nCv_0n[11], c_0n[11], addOut_0n[10]);
balsa_fa I32 (nStart_0n, n_0n[11], w_0n[11], nCv_0n[11], c_0n[11], nCv_0n[12], c_0n[12], addOut_0n[11]);
balsa_fa I33 (nStart_0n, n_0n[12], w_0n[12], nCv_0n[12], c_0n[12], nCv_0n[13], c_0n[13], addOut_0n[12]);
balsa_fa I34 (nStart_0n, n_0n[13], w_0n[13], nCv_0n[13], c_0n[13], nCv_0n[14], c_0n[14], addOut_0n[13]);
balsa_fa I35 (nStart_0n, n_0n[14], w_0n[14], nCv_0n[14], c_0n[14], nCv_0n[15], c_0n[15], addOut_0n[14]);
balsa_fa I36 (nStart_0n, n_0n[15], w_0n[15], nCv_0n[15], c_0n[15], nCv_0n[16], c_0n[16], addOut_0n[15]);
assign nCv_0n[0] = nStart_0n;
assign c_0n[0] = vcc;
IV I39 (nStart_0n, start_0n);
IV I40 (n_0n[0], inpB_0d[0]);
IV I41 (n_0n[1], inpB_0d[1]);
IV I42 (n_0n[2], inpB_0d[2]);
IV I43 (n_0n[3], inpB_0d[3]);
IV I44 (n_0n[4], inpB_0d[4]);
IV I45 (n_0n[5], inpB_0d[5]);
IV I46 (n_0n[6], inpB_0d[6]);
IV I47 (n_0n[7], inpB_0d[7]);
IV I48 (n_0n[8], inpB_0d[8]);
IV I49 (n_0n[9], inpB_0d[9]);
IV I50 (n_0n[10], inpB_0d[10]);
IV I51 (n_0n[11], inpB_0d[11]);
IV I52 (n_0n[12], inpB_0d[12]);
IV I53 (n_0n[13], inpB_0d[13]);
IV I54 (n_0n[14], inpB_0d[14]);
IV I55 (n_0n[15], inpB_0d[15]);
assign w_0n[0] = inpA_0d[0];
assign w_0n[1] = inpA_0d[1];
assign w_0n[2] = inpA_0d[2];
assign w_0n[3] = inpA_0d[3];
assign w_0n[4] = inpA_0d[4];
assign w_0n[5] = inpA_0d[5];
assign w_0n[6] = inpA_0d[6];
assign w_0n[7] = inpA_0d[7];
assign w_0n[8] = inpA_0d[8];
assign w_0n[9] = inpA_0d[9];
assign w_0n[10] = inpA_0d[10];
assign w_0n[11] = inpA_0d[11];
assign w_0n[12] = inpA_0d[12];
assign w_0n[13] = inpA_0d[13];
assign w_0n[14] = inpA_0d[14];
assign w_0n[15] = inpA_0d[15];
assign out_0a = done_0n;
C2 I73 (start_0n, inpA_0a, inpB_0a);
assign inpA_0r = out_0r;
assign inpB_0r = out_0r;
endmodule
module BrzCallMux_16_2 (
inp_0r, inp_0a, inp_0d,
inp_1r, inp_1a, inp_1d,
out_0r, out_0a, out_0d
);
input inp_0r;
output inp_0a;
input [15:0] inp_0d;
input inp_1r;
output inp_1a;
input [15:0] inp_1d;
output out_0r;
input out_0a;
output [15:0] out_0d;
wire [15:0] muxOut_0n;
wire select_0n;
wire nselect_0n;
wire [1:0] nwaySelect_0n;
wire [15:0] nwayMuxOut_0n;
wire [15:0] nwayMuxOut_1n;
mux2 I0 (out_0d[0], inp_0d[0], inp_1d[0], select_0n);
mux2 I1 (out_0d[1], inp_0d[1], inp_1d[1], select_0n);
mux2 I2 (out_0d[2], inp_0d[2], inp_1d[2], select_0n);
mux2 I3 (out_0d[3], inp_0d[3], inp_1d[3], select_0n);
mux2 I4 (out_0d[4], inp_0d[4], inp_1d[4], select_0n);
mux2 I5 (out_0d[5], inp_0d[5], inp_1d[5], select_0n);
mux2 I6 (out_0d[6], inp_0d[6], inp_1d[6], select_0n);
mux2 I7 (out_0d[7], inp_0d[7], inp_1d[7], select_0n);
mux2 I8 (out_0d[8], inp_0d[8], inp_1d[8], select_0n);
mux2 I9 (out_0d[9], inp_0d[9], inp_1d[9], select_0n);
mux2 I10 (out_0d[10], inp_0d[10], inp_1d[10], select_0n);
mux2 I11 (out_0d[11], inp_0d[11], inp_1d[11], select_0n);
mux2 I12 (out_0d[12], inp_0d[12], inp_1d[12], select_0n);
mux2 I13 (out_0d[13], inp_0d[13], inp_1d[13], select_0n);
mux2 I14 (out_0d[14], inp_0d[14], inp_1d[14], select_0n);
mux2 I15 (out_0d[15], inp_0d[15], inp_1d[15], select_0n);
mux2 I16 (out_0r, inp_0r, inp_1r, select_0n);
AN2 I17 (inp_0a, nselect_0n, out_0a);
AN2 I18 (inp_1a, select_0n, out_0a);
SRFF I19 (inp_1r, inp_0r, select_0n, nselect_0n);
endmodule
module demux2 (
i,
o0,
o1,
s
);
input i;
output o0;
output o1;
input s;
wire ns_0n;
AN2 I0 (o1, i, s);
AN2 I1 (o0, i, ns_0n);
IV I2 (ns_0n, s);
endmodule
module BrzCase_1_2_s5_0_3b1 (
inp_0r, inp_0a, inp_0d,
activateOut_0r, activateOut_0a,
activateOut_1r, activateOut_1a
);
input inp_0r;
output inp_0a;
input inp_0d;
output activateOut_0r;
input activateOut_0a;
output activateOut_1r;
input activateOut_1a;
wire t_0n;
wire c_0n;
wire elseAck_0n;
wire [1:0] int0_0n;
OR2 I0 (inp_0a, activateOut_0a, activateOut_1a);
assign int0_0n[0] = c_0n;
assign int0_0n[1] = t_0n;
assign activateOut_1r = int0_0n[1];
assign activateOut_0r = int0_0n[0];
demux2 I5 (inp_0r, c_0n, t_0n, inp_0d);
endmodule
module telem (
Ar,
Aa,
Br,
Ba
);
input Ar;
output Aa;
output Br;
input Ba;
wire s_0n;
ACU0D1 I0 (Aa, Ba, Ar);
IV I1 (s_0n, Aa);
AN2 I2 (Br, Ar, s_0n);
endmodule
module BrzConcur_2 (
activate_0r, activate_0a,
activateOut_0r, activateOut_0a,
activateOut_1r, activateOut_1a
);
input activate_0r;
output activate_0a;
output activateOut_0r;
input activateOut_0a;
output activateOut_1r;
input activateOut_1a;
wire [1:0] acks_0n;
C2 I0 (activate_0a, acks_0n[0], acks_0n[1]);
telem I1 (activate_0r, acks_0n[0], activateOut_0r, activateOut_0a);
telem I2 (activate_0r, acks_0n[1], activateOut_1r, activateOut_1a);
endmodule
module BrzFetch_1_s5_false (
activate_0r, activate_0a,
inp_0r, inp_0a, inp_0d,
out_0r, out_0a, out_0d
);
input activate_0r;
output activate_0a;
output inp_0r;
input inp_0a;
input inp_0d;
output out_0r;
input out_0a;
output out_0d;
assign activate_0a = out_0a;
assign out_0r = inp_0a;
assign inp_0r = activate_0r;
assign out_0d = inp_0d;
endmodule
module BrzFetch_16_s5_false (
activate_0r, activate_0a,
inp_0r, inp_0a, inp_0d,
out_0r, out_0a, out_0d
);
input activate_0r;
output activate_0a;
output inp_0r;
input inp_0a;
input [15:0] inp_0d;
output out_0r;
input out_0a;
output [15:0] out_0d;
assign activate_0a = out_0a;
assign out_0r = inp_0a;
assign inp_0r = activate_0r;
assign out_0d[0] = inp_0d[0];
assign out_0d[1] = inp_0d[1];
assign out_0d[2] = inp_0d[2];
assign out_0d[3] = inp_0d[3];
assign out_0d[4] = inp_0d[4];
assign out_0d[5] = inp_0d[5];
assign out_0d[6] = inp_0d[6];
assign out_0d[7] = inp_0d[7];
assign out_0d[8] = inp_0d[8];
assign out_0d[9] = inp_0d[9];
assign out_0d[10] = inp_0d[10];
assign out_0d[11] = inp_0d[11];
assign out_0d[12] = inp_0d[12];
assign out_0d[13] = inp_0d[13];
assign out_0d[14] = inp_0d[14];
assign out_0d[15] = inp_0d[15];
endmodule
module BrzLoop (
activate_0r, activate_0a,
activateOut_0r, activateOut_0a
);
input activate_0r;
output activate_0a;
output activateOut_0r;
input activateOut_0a;
wire nReq_0n;
wire gnd;
GND gnd_cell_instance (gnd);
IV I0 (nReq_0n, activate_0r);
NR2 I1 (activateOut_0r, nReq_0n, activateOut_0a);
assign activate_0a = gnd;
endmodule
module selem (
Ar,
Aa,
Br,
Ba
);
input Ar;
output Aa;
output Br;
input Ba;
wire s_0n;
NC2P I0 (s_0n, Ar, Ba);
NR2 I1 (Aa, Ba, s_0n);
AN2 I2 (Br, Ar, s_0n);
endmodule
module BrzSequence_2_s1_S (
activate_0r, activate_0a,
activateOut_0r, activateOut_0a,
activateOut_1r, activateOut_1a
);
input activate_0r;
output activate_0a;
output activateOut_0r;
input activateOut_0a;
output activateOut_1r;
input activateOut_1a;
wire [1:0] sreq_0n;
assign activate_0a = activateOut_1a;
assign activateOut_1r = sreq_0n[1];
assign sreq_0n[0] = activate_0r;
selem I3 (sreq_0n[0], sreq_0n[1], activateOut_0r, activateOut_0a);
endmodule
module telemr (
Ar,
Aa,
Br,
Ba,
initialise
);
input Ar;
output Aa;
output Br;
input Ba;
input initialise;
wire s;
AN2 I0 (Br, Ar, s);
IV I1 (s, Aa);
C2R I2 (Aa, Ba, Ar, initialise);
endmodule
module BrzSequence_3_s2_ST (
activate_0r, activate_0a,
activateOut_0r, activateOut_0a,
activateOut_1r, activateOut_1a,
activateOut_2r, activateOut_2a,
initialise
);
input activate_0r;
output activate_0a;
output activateOut_0r;
input activateOut_0a;
output activateOut_1r;
input activateOut_1a;
output activateOut_2r;
input activateOut_2a;
input initialise;
wire [2:0] sreq_0n;
assign activate_0a = activateOut_2a;
assign activateOut_2r = sreq_0n[2];
assign sreq_0n[0] = activate_0r;
telemr I3 (sreq_0n[1], sreq_0n[2], activateOut_1r, activateOut_1a, initialise);
selem I4 (sreq_0n[0], sreq_0n[1], activateOut_0r, activateOut_0a);
endmodule
module BrzVariable_1_1_s0_ (
write_0r, write_0a, write_0d,
read_0r, read_0a, read_0d
);
input write_0r;
output write_0a;
input write_0d;
input read_0r;
output read_0a;
output read_0d;
wire data_0n;
wire nWriteReq_0n;
wire bWriteReq_0n;
wire nbWriteReq_0n;
assign read_0a = read_0r;
assign read_0d = data_0n;
LD1 I2 (write_0d, bWriteReq_0n, data_0n);
IV I3 (write_0a, nbWriteReq_0n);
IV I4 (nbWriteReq_0n, bWriteReq_0n);
IV I5 (bWriteReq_0n, nWriteReq_0n);
IV I6 (nWriteReq_0n, write_0r);
endmodule
module BrzVariable_16_1_s0_ (
write_0r, write_0a, write_0d,
read_0r, read_0a, read_0d
);
input write_0r;
output write_0a;
input [15:0] write_0d;
input read_0r;
output read_0a;
output [15:0] read_0d;
wire [15:0] data_0n;
wire nWriteReq_0n;
wire bWriteReq_0n;
wire nbWriteReq_0n;
assign read_0a = read_0r;
assign read_0d[0] = data_0n[0];
assign read_0d[1] = data_0n[1];
assign read_0d[2] = data_0n[2];
assign read_0d[3] = data_0n[3];
assign read_0d[4] = data_0n[4];
assign read_0d[5] = data_0n[5];
assign read_0d[6] = data_0n[6];
assign read_0d[7] = data_0n[7];
assign read_0d[8] = data_0n[8];
assign read_0d[9] = data_0n[9];
assign read_0d[10] = data_0n[10];
assign read_0d[11] = data_0n[11];
assign read_0d[12] = data_0n[12];
assign read_0d[13] = data_0n[13];
assign read_0d[14] = data_0n[14];
assign read_0d[15] = data_0n[15];
LD1 I17 (write_0d[0], bWriteReq_0n, data_0n[0]);
LD1 I18 (write_0d[1], bWriteReq_0n, data_0n[1]);
LD1 I19 (write_0d[2], bWriteReq_0n, data_0n[2]);
LD1 I20 (write_0d[3], bWriteReq_0n, data_0n[3]);
LD1 I21 (write_0d[4], bWriteReq_0n, data_0n[4]);
LD1 I22 (write_0d[5], bWriteReq_0n, data_0n[5]);
LD1 I23 (write_0d[6], bWriteReq_0n, data_0n[6]);
LD1 I24 (write_0d[7], bWriteReq_0n, data_0n[7]);
LD1 I25 (write_0d[8], bWriteReq_0n, data_0n[8]);
LD1 I26 (write_0d[9], bWriteReq_0n, data_0n[9]);
LD1 I27 (write_0d[10], bWriteReq_0n, data_0n[10]);
LD1 I28 (write_0d[11], bWriteReq_0n, data_0n[11]);
LD1 I29 (write_0d[12], bWriteReq_0n, data_0n[12]);
LD1 I30 (write_0d[13], bWriteReq_0n, data_0n[13]);
LD1 I31 (write_0d[14], bWriteReq_0n, data_0n[14]);
LD1 I32 (write_0d[15], bWriteReq_0n, data_0n[15]);
IV I33 (write_0a, nbWriteReq_0n);
IV I34 (nbWriteReq_0n, bWriteReq_0n);
IV I35 (bWriteReq_0n, nWriteReq_0n);
IV I36 (nWriteReq_0n, write_0r);
endmodule
module BrzVariable_16_4_s0_ (
write_0r, write_0a, write_0d,
read_0r, read_0a, read_0d,
read_1r, read_1a, read_1d,
read_2r, read_2a, read_2d,
read_3r, read_3a, read_3d
);
input write_0r;
output write_0a;
input [15:0] write_0d;
input read_0r;
output read_0a;
output [15:0] read_0d;
input read_1r;
output read_1a;
output [15:0] read_1d;
input read_2r;
output read_2a;
output [15:0] read_2d;
input read_3r;
output read_3a;
output [15:0] read_3d;
wire [15:0] data_0n;
wire nWriteReq_0n;
wire bWriteReq_0n;
wire nbWriteReq_0n;
assign read_0a = read_0r;
assign read_1a = read_1r;
assign read_2a = read_2r;
assign read_3a = read_3r;
assign read_3d[0] = data_0n[0];
assign read_3d[1] = data_0n[1];
assign read_3d[2] = data_0n[2];
assign read_3d[3] = data_0n[3];
assign read_3d[4] = data_0n[4];
assign read_3d[5] = data_0n[5];
assign read_3d[6] = data_0n[6];
assign read_3d[7] = data_0n[7];
assign read_3d[8] = data_0n[8];
assign read_3d[9] = data_0n[9];
assign read_3d[10] = data_0n[10];
assign read_3d[11] = data_0n[11];
assign read_3d[12] = data_0n[12];
assign read_3d[13] = data_0n[13];
assign read_3d[14] = data_0n[14];
assign read_3d[15] = data_0n[15];
assign read_2d[0] = data_0n[0];
assign read_2d[1] = data_0n[1];
assign read_2d[2] = data_0n[2];
assign read_2d[3] = data_0n[3];
assign read_2d[4] = data_0n[4];
assign read_2d[5] = data_0n[5];
assign read_2d[6] = data_0n[6];
assign read_2d[7] = data_0n[7];
assign read_2d[8] = data_0n[8];
assign read_2d[9] = data_0n[9];
assign read_2d[10] = data_0n[10];
assign read_2d[11] = data_0n[11];
assign read_2d[12] = data_0n[12];
assign read_2d[13] = data_0n[13];
assign read_2d[14] = data_0n[14];
assign read_2d[15] = data_0n[15];
assign read_1d[0] = data_0n[0];
assign read_1d[1] = data_0n[1];
assign read_1d[2] = data_0n[2];
assign read_1d[3] = data_0n[3];
assign read_1d[4] = data_0n[4];
assign read_1d[5] = data_0n[5];
assign read_1d[6] = data_0n[6];
assign read_1d[7] = data_0n[7];
assign read_1d[8] = data_0n[8];
assign read_1d[9] = data_0n[9];
assign read_1d[10] = data_0n[10];
assign read_1d[11] = data_0n[11];
assign read_1d[12] = data_0n[12];
assign read_1d[13] = data_0n[13];
assign read_1d[14] = data_0n[14];
assign read_1d[15] = data_0n[15];
assign read_0d[0] = data_0n[0];
assign read_0d[1] = data_0n[1];
assign read_0d[2] = data_0n[2];
assign read_0d[3] = data_0n[3];
assign read_0d[4] = data_0n[4];
assign read_0d[5] = data_0n[5];
assign read_0d[6] = data_0n[6];
assign read_0d[7] = data_0n[7];
assign read_0d[8] = data_0n[8];
assign read_0d[9] = data_0n[9];
assign read_0d[10] = data_0n[10];
assign read_0d[11] = data_0n[11];
assign read_0d[12] = data_0n[12];
assign read_0d[13] = data_0n[13];
assign read_0d[14] = data_0n[14];
assign read_0d[15] = data_0n[15];
LD1 I68 (write_0d[0], bWriteReq_0n, data_0n[0]);
LD1 I69 (write_0d[1], bWriteReq_0n, data_0n[1]);
LD1 I70 (write_0d[2], bWriteReq_0n, data_0n[2]);
LD1 I71 (write_0d[3], bWriteReq_0n, data_0n[3]);
LD1 I72 (write_0d[4], bWriteReq_0n, data_0n[4]);
LD1 I73 (write_0d[5], bWriteReq_0n, data_0n[5]);
LD1 I74 (write_0d[6], bWriteReq_0n, data_0n[6]);
LD1 I75 (write_0d[7], bWriteReq_0n, data_0n[7]);
LD1 I76 (write_0d[8], bWriteReq_0n, data_0n[8]);
LD1 I77 (write_0d[9], bWriteReq_0n, data_0n[9]);
LD1 I78 (write_0d[10], bWriteReq_0n, data_0n[10]);
LD1 I79 (write_0d[11], bWriteReq_0n, data_0n[11]);
LD1 I80 (write_0d[12], bWriteReq_0n, data_0n[12]);
LD1 I81 (write_0d[13], bWriteReq_0n, data_0n[13]);
LD1 I82 (write_0d[14], bWriteReq_0n, data_0n[14]);
LD1 I83 (write_0d[15], bWriteReq_0n, data_0n[15]);
IV I84 (write_0a, nbWriteReq_0n);
IV I85 (nbWriteReq_0n, bWriteReq_0n);
IV I86 (bWriteReq_0n, nWriteReq_0n);
IV I87 (nWriteReq_0n, write_0r);
endmodule
module BrzVariable_16_5_s0_ (
write_0r, write_0a, write_0d,
read_0r, read_0a, read_0d,
read_1r, read_1a, read_1d,
read_2r, read_2a, read_2d,
read_3r, read_3a, read_3d,
read_4r, read_4a, read_4d
);
input write_0r;
output write_0a;
input [15:0] write_0d;
input read_0r;
output read_0a;
output [15:0] read_0d;
input read_1r;
output read_1a;
output [15:0] read_1d;
input read_2r;
output read_2a;
output [15:0] read_2d;
input read_3r;
output read_3a;
output [15:0] read_3d;
input read_4r;
output read_4a;
output [15:0] read_4d;
wire [15:0] data_0n;
wire nWriteReq_0n;
wire bWriteReq_0n;
wire nbWriteReq_0n;
assign read_0a = read_0r;
assign read_1a = read_1r;
assign read_2a = read_2r;
assign read_3a = read_3r;
assign read_4a = read_4r;
assign read_4d[0] = data_0n[0];
assign read_4d[1] = data_0n[1];
assign read_4d[2] = data_0n[2];
assign read_4d[3] = data_0n[3];
assign read_4d[4] = data_0n[4];
assign read_4d[5] = data_0n[5];
assign read_4d[6] = data_0n[6];
assign read_4d[7] = data_0n[7];
assign read_4d[8] = data_0n[8];
assign read_4d[9] = data_0n[9];
assign read_4d[10] = data_0n[10];
assign read_4d[11] = data_0n[11];
assign read_4d[12] = data_0n[12];
assign read_4d[13] = data_0n[13];
assign read_4d[14] = data_0n[14];
assign read_4d[15] = data_0n[15];
assign read_3d[0] = data_0n[0];
assign read_3d[1] = data_0n[1];
assign read_3d[2] = data_0n[2];
assign read_3d[3] = data_0n[3];
assign read_3d[4] = data_0n[4];
assign read_3d[5] = data_0n[5];
assign read_3d[6] = data_0n[6];
assign read_3d[7] = data_0n[7];
assign read_3d[8] = data_0n[8];
assign read_3d[9] = data_0n[9];
assign read_3d[10] = data_0n[10];
assign read_3d[11] = data_0n[11];
assign read_3d[12] = data_0n[12];
assign read_3d[13] = data_0n[13];
assign read_3d[14] = data_0n[14];
assign read_3d[15] = data_0n[15];
assign read_2d[0] = data_0n[0];
assign read_2d[1] = data_0n[1];
assign read_2d[2] = data_0n[2];
assign read_2d[3] = data_0n[3];
assign read_2d[4] = data_0n[4];
assign read_2d[5] = data_0n[5];
assign read_2d[6] = data_0n[6];
assign read_2d[7] = data_0n[7];
assign read_2d[8] = data_0n[8];
assign read_2d[9] = data_0n[9];
assign read_2d[10] = data_0n[10];
assign read_2d[11] = data_0n[11];
assign read_2d[12] = data_0n[12];
assign read_2d[13] = data_0n[13];
assign read_2d[14] = data_0n[14];
assign read_2d[15] = data_0n[15];
assign read_1d[0] = data_0n[0];
assign read_1d[1] = data_0n[1];
assign read_1d[2] = data_0n[2];
assign read_1d[3] = data_0n[3];
assign read_1d[4] = data_0n[4];
assign read_1d[5] = data_0n[5];
assign read_1d[6] = data_0n[6];
assign read_1d[7] = data_0n[7];
assign read_1d[8] = data_0n[8];
assign read_1d[9] = data_0n[9];
assign read_1d[10] = data_0n[10];
assign read_1d[11] = data_0n[11];
assign read_1d[12] = data_0n[12];
assign read_1d[13] = data_0n[13];
assign read_1d[14] = data_0n[14];
assign read_1d[15] = data_0n[15];
assign read_0d[0] = data_0n[0];
assign read_0d[1] = data_0n[1];
assign read_0d[2] = data_0n[2];
assign read_0d[3] = data_0n[3];
assign read_0d[4] = data_0n[4];
assign read_0d[5] = data_0n[5];
assign read_0d[6] = data_0n[6];
assign read_0d[7] = data_0n[7];
assign read_0d[8] = data_0n[8];
assign read_0d[9] = data_0n[9];
assign read_0d[10] = data_0n[10];
assign read_0d[11] = data_0n[11];
assign read_0d[12] = data_0n[12];
assign read_0d[13] = data_0n[13];
assign read_0d[14] = data_0n[14];
assign read_0d[15] = data_0n[15];
LD1 I85 (write_0d[0], bWriteReq_0n, data_0n[0]);
LD1 I86 (write_0d[1], bWriteReq_0n, data_0n[1]);
LD1 I87 (write_0d[2], bWriteReq_0n, data_0n[2]);
LD1 I88 (write_0d[3], bWriteReq_0n, data_0n[3]);
LD1 I89 (write_0d[4], bWriteReq_0n, data_0n[4]);
LD1 I90 (write_0d[5], bWriteReq_0n, data_0n[5]);
LD1 I91 (write_0d[6], bWriteReq_0n, data_0n[6]);
LD1 I92 (write_0d[7], bWriteReq_0n, data_0n[7]);
LD1 I93 (write_0d[8], bWriteReq_0n, data_0n[8]);
LD1 I94 (write_0d[9], bWriteReq_0n, data_0n[9]);
LD1 I95 (write_0d[10], bWriteReq_0n, data_0n[10]);
LD1 I96 (write_0d[11], bWriteReq_0n, data_0n[11]);
LD1 I97 (write_0d[12], bWriteReq_0n, data_0n[12]);
LD1 I98 (write_0d[13], bWriteReq_0n, data_0n[13]);
LD1 I99 (write_0d[14], bWriteReq_0n, data_0n[14]);
LD1 I100 (write_0d[15], bWriteReq_0n, data_0n[15]);
IV I101 (write_0a, nbWriteReq_0n);
IV I102 (nbWriteReq_0n, bWriteReq_0n);
IV I103 (bWriteReq_0n, nWriteReq_0n);
IV I104 (nWriteReq_0n, write_0r);
endmodule
module BrzWhile (
activate_0r, activate_0a,
guard_0r, guard_0a, guard_0d,
activateOut_0r, activateOut_0a
);
input activate_0r;
output activate_0a;
output guard_0r;
input guard_0a;
input guard_0d;
output activateOut_0r;
input activateOut_0a;
wire guardReq_0n;
wire guardAck_0n;
wire nReq_0n;
demux2 I0 (guard_0a, activate_0a, guardAck_0n, guard_0d);
selem I1 (guardReq_0n, activateOut_0r, guard_0r, guardAck_0n);
IV I2 (nReq_0n, activate_0r);
NR2 I3 (guardReq_0n, nReq_0n, activateOut_0a);
endmodule
module Balsa_gcd16 (
activate_0r, activate_0a,
x_0r, x_0a, x_0d,
y_0r, y_0a, y_0d,
z_0r, z_0a, z_0d,
initialise
);
input activate_0r;
output activate_0a;
output x_0r;
input x_0a;
input [15:0] x_0d;
output y_0r;
input y_0a;
input [15:0] y_0d;
output z_0r;
input z_0a;
output [15:0] z_0d;
input initialise;
wire c45_r;
wire c45_a;
wire [15:0] c45_d;
wire c44_r;
wire c44_a;
wire [15:0] c44_d;
wire c43_r;
wire c43_a;
wire c42_r;
wire c42_a;
wire c41_r;
wire c41_a;
wire c40_r;
wire c40_a;
wire [15:0] c40_d;
wire c39_r;
wire c39_a;
wire c38_r;
wire c38_a;
wire [15:0] c38_d;
wire c37_r;
wire c37_a;
wire c36_r;
wire c36_a;
wire c36_d;
wire c35_r;
wire c35_a;
wire [15:0] c35_d;
wire c34_r;
wire c34_a;
wire [15:0] c34_d;
wire c33_r;
wire c33_a;
wire c33_d;
wire c32_r;
wire c32_a;
wire c32_d;
wire c31_r;
wire c31_a;
wire c30_r;
wire c30_a;
wire c29_r;
wire c29_a;
wire c29_d;
wire c28_r;
wire c28_a;
wire c27_r;
wire c27_a;
wire c27_d;
wire c26_r;
wire c26_a;
wire [15:0] c26_d;
wire c25_r;
wire c25_a;
wire [15:0] c25_d;
wire c24_r;
wire c24_a;
wire [15:0] c24_d;
wire c23_r;
wire c23_a;
wire [15:0] c23_d;
wire c22_r;
wire c22_a;
wire c21_r;
wire c21_a;
wire c20_r;
wire c20_a;
wire c19_r;
wire c19_a;
wire [15:0] c19_d;
wire c18_r;
wire c18_a;
wire [15:0] c18_d;
wire c17_r;
wire c17_a;
wire [15:0] c17_d;
wire c16_r;
wire c16_a;
wire [15:0] c16_d;
wire c15_r;
wire c15_a;
wire [15:0] c15_d;
wire c14_r;
wire c14_a;
wire [15:0] c14_d;
wire c13_r;
wire c13_a;
wire c12_r;
wire c12_a;
wire c11_r;
wire c11_a;
wire c10_r;
wire c10_a;
wire [15:0] c10_d;
wire c9_r;
wire c9_a;
wire [15:0] c9_d;
wire c8_r;
wire c8_a;
wire [15:0] c8_d;
wire c7_r;
wire c7_a;
wire [15:0] c7_d;
wire c6_r;
wire c6_a;
wire c5_r;
wire c5_a;
wire [15:0] c5_d;
BrzVariable_16_5_s0_ I0 (c45_r, c45_a, c45_d, c35_r, c35_a, c35_d, c17_r, c17_a, c17_d, c7_r, c7_a, c7_d, c26_r, c26_a, c26_d, c5_r, c5_a, c5_d);
BrzCallMux_16_2 I1 (c19_r, c19_a, c19_d, c40_r, c40_a, c40_d, c45_r, c45_a, c45_d);
BrzVariable_16_4_s0_ I2 (c44_r, c44_a, c44_d, c34_r, c34_a, c34_d, c16_r, c16_a, c16_d, c8_r, c8_a, c8_d, c25_r, c25_a, c25_d);
BrzCallMux_16_2 I3 (c10_r, c10_a, c10_d, c38_r, c38_a, c38_d, c44_r, c44_a, c44_d);
BrzLoop I4 (activate_0r, activate_0a, c43_r, c43_a);
BrzSequence_3_s2_ST I5 (c43_r, c43_a, c42_r, c42_a, c37_r, c37_a, c6_r, c6_a, initialise);
BrzConcur_2 I6 (c42_r, c42_a, c41_r, c41_a, c39_r, c39_a);
BrzFetch_16_s5_false I7 (c41_r, c41_a, x_0r, x_0a, x_0d, c40_r, c40_a, c40_d);
BrzFetch_16_s5_false I8 (c39_r, c39_a, y_0r, y_0a, y_0d, c38_r, c38_a, c38_d);
BrzWhile I9 (c37_r, c37_a, c36_r, c36_a, c36_d, c28_r, c28_a);
BrzBinaryFunc_1_16_16_s9_NotEquals_s5_fals_m14m I10 (c36_r, c36_a, c36_d, c35_r, c35_a, c35_d, c34_r, c34_a, c34_d);
BrzCase_1_2_s5_0_3b1 I11 (c29_r, c29_a, c29_d, c11_r, c11_a, c20_r, c20_a);
BrzSequence_2_s1_S I12 (c28_r, c28_a, c30_r, c30_a, c31_r, c31_a);
BrzFetch_1_s5_false I13 (c30_r, c30_a, c27_r, c27_a, c27_d, c32_r, c32_a, c32_d);
BrzFetch_1_s5_false I14 (c31_r, c31_a, c33_r, c33_a, c33_d, c29_r, c29_a, c29_d);
BrzVariable_1_1_s0_ I15 (c32_r, c32_a, c32_d, c33_r, c33_a, c33_d);
BrzBinaryFunc_1_16_16_s11_GreaterThan_s5_f_m13m I16 (c27_r, c27_a, c27_d, c26_r, c26_a, c26_d, c25_r, c25_a, c25_d);
BrzSequence_2_s1_S I17 (c20_r, c20_a, c21_r, c21_a, c22_r, c22_a);
BrzFetch_16_s5_false I18 (c21_r, c21_a, c18_r, c18_a, c18_d, c23_r, c23_a, c23_d);
BrzFetch_16_s5_false I19 (c22_r, c22_a, c24_r, c24_a, c24_d, c19_r, c19_a, c19_d);
BrzVariable_16_1_s0_ I20 (c23_r, c23_a, c23_d, c24_r, c24_a, c24_d);
BrzBinaryFunc_16_16_16_s8_Subtract_s5_fals_m15m I21 (c18_r, c18_a, c18_d, c17_r, c17_a, c17_d, c16_r, c16_a, c16_d);
BrzSequence_2_s1_S I22 (c11_r, c11_a, c12_r, c12_a, c13_r, c13_a);
BrzFetch_16_s5_false I23 (c12_r, c12_a, c9_r, c9_a, c9_d, c14_r, c14_a, c14_d);
BrzFetch_16_s5_false I24 (c13_r, c13_a, c15_r, c15_a, c15_d, c10_r, c10_a, c10_d);
BrzVariable_16_1_s0_ I25 (c14_r, c14_a, c14_d, c15_r, c15_a, c15_d);
BrzBinaryFunc_16_16_16_s8_Subtract_s5_fals_m15m I26 (c9_r, c9_a, c9_d, c8_r, c8_a, c8_d, c7_r, c7_a, c7_d);
BrzFetch_16_s5_false I27 (c6_r, c6_a, c5_r, c5_a, c5_d, z_0r, z_0a, z_0d);
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module uart #(
//parameter csr_addr = 4'h0,
parameter clk_freq = 100000000,
parameter baud = 115200
) (
//cpu_read_write
//wb_input
input [31:0] dat_i,
input [31:0] adr_i,
input we_i,
input stb_i,
//wb_output
output reg [31:0] dat_o,
output ack_o,
input sys_clk,
input sys_rst,
output rx_irq,
output tx_irq,
input uart_rx,
output uart_tx,
input rx_iack
);
reg [15:0] divisor;
wire [7:0] rx_data;
wire [7:0] tx_data;
wire tx_wr;
wire rx_done, tx_done;
wire tx_busy;
wire full_rx, full_tx, empty_rx, empty_tx;
reg thru = 0;
wire uart_tx_transceiver;
wire [7:0] rx_data_out;
reg fifo_rx_wr = 0;
reg tmpflag = 0;
wire fifo_rx_rd;
reg fifo_rd_once = 0;
wire [7:0] tx_data_out;
wire fifo_tx_rd;
reg tran_tx_wr = 0;
reg fifo_tx_rd_once = 0;
reg fifo_busy;
wire uart_wr;
uart_transceiver transceiver(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.uart_rx(uart_rx),
.uart_tx(uart_tx_transceiver),
.divisor(divisor),
.rx_data(rx_data),
.rx_done(rx_done),
.tx_data(tx_data_out),
.tx_wr(tran_tx_wr & fifo_tx_rd_once),
.tx_done(tx_done),
.tx_busy(tx_busy),
.rx_busy(rx_busy)
);
// always @(posedge sys_clk) begin
// if(rx_done & ~fifo_rx_wr) fifo_rx_wr = 1;
// else if(~rx_done & fifo_rx_wr & ~tmpflag) begin
// fifo_rx_wr = 1;
// tmpflag = 1;
// end
// else if(tmpflag) begin
// fifo_rx_wr = 0;
// tmpflag = 0;
// end
// end
always @(posedge sys_clk) begin
if(rx_done) fifo_rx_wr = 1;
else fifo_rx_wr = 0;
end
assign fifo_rx_rd = rx_wr & ~fifo_rd_once;
always @(posedge sys_clk) begin
if(rx_wr) fifo_rd_once = 1;
else fifo_rd_once = 0;
end
assign rx_irq = full_rx & ~rx_iack;
uart_fifo fifo_rx (
.clk(sys_clk), // input clk
.rst(sys_rst), // input rst
.din(rx_data), // input [7 : 0] din
.wr_en(fifo_rx_wr), // input wr_en
.rd_en(fifo_rx_rd), // input rd_en
.dout(rx_data_out), // output [7 : 0] dout
.full(full_rx), // output full
.empty(empty_rx), // output empty
.data_count() // output [7 : 0] data_count
);
always @(posedge sys_clk) begin
if(tran_tx_wr) fifo_tx_rd_once = 1;
else fifo_tx_rd_once = 0;
end
assign fifo_tx_rd = ~tx_busy & ~empty_tx;
always @(posedge sys_clk) begin
tran_tx_wr = fifo_tx_rd;
end
always @(posedge sys_clk) begin
if(tx_wr) fifo_busy = 1;
else fifo_busy = 0;
end
//assign tx_irq = full_tx;
uart_fifo fifo_tx (
.clk(sys_clk), // input clk
.rst(sys_rst), // input rst
.din(tx_data), // input [7 : 0] din
.wr_en(tx_wr & ~fifo_busy), // input wr_en
.rd_en(tran_tx_wr & fifo_tx_rd_once/*fifo_tx_rd*/), // input rd_en
.dout(tx_data_out), // output [7 : 0] dout
.full(full_tx), // output full
.empty(empty_tx), // output empty
.data_count() // output [7 : 0] data_count
);
assign uart_tx = thru ? uart_rx : uart_tx_transceiver;
/* CSR interface */
//wire csr_selected = csr_a[13:10] == csr_addr;
assign tx_data = dat_i[7:0];
//assign tx_wr = csr_selected & csr_we & (csr_a[1:0] == 2'b00);
assign tx_wr = stb_i & ack_o & we_i & (adr_i[1:0] == 2'b00);
assign rx_wr = stb_i & ack_o & ~we_i & (adr_i[1:0] == 2'b00) & ~empty_rx;
parameter default_divisor = clk_freq/baud/16;
assign ack_o = stb_i & (we_i?~full_tx:1) ;//& ((we_i&~full_tx) | (~we_i&~empty_rx));
assign uart_wr = stb_i && ack_o;
always @(posedge sys_clk or posedge sys_rst) begin
if(sys_rst) begin
divisor <= default_divisor;
dat_o <= 32'd0;
end else if(uart_wr) begin
dat_o <= 32'd0;
case(adr_i[1:0])
2'b00: if(rx_wr) begin dat_o <= {23'h0, 1'b1, rx_data_out}; end
2'b01: dat_o <= divisor;
2'b10: dat_o <= thru;
endcase
if(we_i/*csr_we*/) begin
case(adr_i[1:0])
2'b00:; /* handled by transceiver */
2'b01: divisor <= dat_i[15:0];
2'b10: thru <= dat_i[0];
endcase
end
end
end
//always @(posedge sys_clk) begin
// if(sys_rst) begin
// divisor <= default_divisor;
// dat_o <= 32'd0;
// end else begin
// dat_o <= 32'd0;
// if(stb_i && ack_o/*csr_selected*/) begin
// case(adr_i[1:0])
// 2'b00: dat_o <= rx_data;
// 2'b01: dat_o <= divisor;
// 2'b10: dat_o <= thru;
// endcase
// if(we_i/*csr_we*/) begin
// case(adr_i[1:0])
// 2'b00:; /* handled by transceiver */
// 2'b01: divisor <= dat_i[15:0];
// 2'b10: thru <= dat_i[0];
// endcase
// end
// end
// end
//end
endmodule
|
module check (input unsigned [103:0] a, b, c);
wire [103:0] int_AB;
assign int_AB = ~(a | b);
always @(a, b, int_AB, c) begin
#1;
if (int_AB !== c) begin
$display("ERROR");
$finish;
end
end
endmodule
module stimulus (output reg unsigned [103:0] A, B);
parameter S = 2000;
int unsigned i;
initial begin
A = 0; B= 0;
// values with 0, 1
for (i=0; i<S; i=i+1) begin
#1 A[103:8] = {$random, $random, $random};
A[7:0] = $random % 256;
B[103:8] = {$random, $random, $random};
B[7:0] = $random % 256;
end
// values with x, z
for (i=0; i<S; i=i+1) begin
#1;
A[103:8] = {$random, $random, $random};
A[7:0] = $random % 256;
B[103:8] = {$random, $random, $random};
B[7:0] = $random % 256;
A[103:72] = xz_inject (A[103:72]);
A[71:40] = xz_inject (A[71:40]);
B[71:40] = xz_inject (B[71:40]);
B[39:8] = xz_inject (B[39:8]);
end
end
// injects some x, z values on 32 bits arguments
function [31:0] xz_inject (input unsigned [31:0] value);
integer i, temp;
begin
temp = {$random};
for (i=0; i<32; i=i+1)
begin
if (temp[i] == 1'b1)
begin
temp = $random;
if (temp <= 0)
value[i] = 1'bx; // 'x noise
else
value[i] = 1'bz; // 'z noise
end
end
xz_inject = value;
end
endfunction
endmodule
module test;
wire unsigned [103:0] a, b;
wire unsigned [103:0] r;
stimulus stim (.A(a), .B(b));
nor104 duv (.a_i(a), .b_i(b), .c_o(r) );
check check (.a(a), .b(b), .c(r) );
initial begin
#120000;
$display("PASSED");
$finish;
end
endmodule
|
/*
* Copyright 2013, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* round constant */
module rconst(i, rc);
input [23:0] i;
output reg [63:0] rc;
always @ (i)
begin
rc = 0;
rc[0] = i[0] | i[4] | i[5] | i[6] | i[7] | i[10] | i[12] | i[13] | i[14] | i[15] | i[20] | i[22];
rc[1] = i[1] | i[2] | i[4] | i[8] | i[11] | i[12] | i[13] | i[15] | i[16] | i[18] | i[19];
rc[3] = i[2] | i[4] | i[7] | i[8] | i[9] | i[10] | i[11] | i[12] | i[13] | i[14] | i[18] | i[19] | i[23];
rc[7] = i[1] | i[2] | i[4] | i[6] | i[8] | i[9] | i[12] | i[13] | i[14] | i[17] | i[20] | i[21];
rc[15] = i[1] | i[2] | i[3] | i[4] | i[6] | i[7] | i[10] | i[12] | i[14] | i[15] | i[16] | i[18] | i[20] | i[21] | i[23];
rc[31] = i[3] | i[5] | i[6] | i[10] | i[11] | i[12] | i[19] | i[20] | i[22] | i[23];
rc[63] = i[2] | i[3] | i[6] | i[7] | i[13] | i[14] | i[15] | i[16] | i[17] | i[19] | i[20] | i[21] | i[23];
end
endmodule
|
/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact: [email protected]
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
* Module name: openhmc_8x_rf
*
*
*/
module openhmc_8x_rf (
input wire clk,
input wire res_n,
input wire[6:3] address,
output reg invalid_address,
output reg access_complete,
input wire read_en,
output reg[63:0] read_data,
input wire write_en,
input wire[63:0] write_data,
input wire status_general_link_up_next,
input wire status_general_link_training_next,
input wire status_general_sleep_mode_next,
input wire status_general_lanes_reversed_next,
input wire status_general_phy_ready_next,
input wire[9:0] status_general_hmc_tokens_remaining_next,
input wire[9:0] status_general_rx_tokens_remaining_next,
input wire[7:0] status_general_lane_polarity_reversed_next,
input wire[7:0] status_init_lane_descramblers_locked_next,
input wire[7:0] status_init_descrambler_part_aligned_next,
input wire[7:0] status_init_descrambler_aligned_next,
input wire status_init_all_descramblers_aligned_next,
input wire[1:0] status_init_tx_init_status_next,
input wire status_init_hmc_init_TS1_next,
output reg control_p_rst_n,
output reg control_hmc_init_cont_set,
output reg control_set_hmc_sleep,
output reg control_scrambler_disable,
output reg control_run_length_enable,
output reg[2:0] control_first_cube_ID,
output reg control_debug_dont_send_tret,
output reg control_debug_halt_on_error_abort,
output reg control_debug_halt_on_tx_retry,
output reg[9:0] control_rx_token_count,
output reg[4:0] control_irtry_received_threshold,
output reg[4:0] control_irtry_to_send,
output reg[5:0] control_bit_slip_time,
input wire[63:0] sent_p_cnt_next,
input wire[63:0] sent_np_cnt_next,
input wire[63:0] sent_r_cnt_next,
input wire[63:0] poisoned_packets_cnt_next,
input wire[63:0] rcvd_rsp_cnt_next,
input wire tx_link_retries_count_countup,
input wire errors_on_rx_count_countup,
input wire run_length_bit_flip_count_countup,
input wire error_abort_not_cleared_count_countup
);
reg status_general_link_up;
reg status_general_link_training;
reg status_general_sleep_mode;
reg status_general_lanes_reversed;
reg status_general_phy_ready;
reg[9:0] status_general_hmc_tokens_remaining;
reg[9:0] status_general_rx_tokens_remaining;
reg[7:0] status_general_lane_polarity_reversed;
reg[7:0] status_init_lane_descramblers_locked;
reg[7:0] status_init_descrambler_part_aligned;
reg[7:0] status_init_descrambler_aligned;
reg status_init_all_descramblers_aligned;
reg[1:0] status_init_tx_init_status;
reg status_init_hmc_init_TS1;
reg[63:0] sent_p_cnt;
reg[63:0] sent_np_cnt;
reg[63:0] sent_r_cnt;
reg[63:0] poisoned_packets_cnt;
reg[63:0] rcvd_rsp_cnt;
reg rreinit;
wire[31:0] tx_link_retries_count;
wire[31:0] errors_on_rx_count;
wire[31:0] run_length_bit_flip_count;
wire[31:0] error_abort_not_cleared_count;
counter48 #(
.DATASIZE(32)
) tx_link_retries_count_I (
.clk(clk),
.res_n(res_n),
.increment(tx_link_retries_count_countup),
.load(32'b0),
.load_enable(rreinit),
.value(tx_link_retries_count)
);
counter48 #(
.DATASIZE(32)
) errors_on_rx_count_I (
.clk(clk),
.res_n(res_n),
.increment(errors_on_rx_count_countup),
.load(32'b0),
.load_enable(rreinit),
.value(errors_on_rx_count)
);
counter48 #(
.DATASIZE(32)
) run_length_bit_flip_count_I (
.clk(clk),
.res_n(res_n),
.increment(run_length_bit_flip_count_countup),
.load(32'b0),
.load_enable(rreinit),
.value(run_length_bit_flip_count)
);
counter48 #(
.DATASIZE(32)
) error_abort_not_cleared_count_I (
.clk(clk),
.res_n(res_n),
.increment(error_abort_not_cleared_count_countup),
.load(32'b0),
.load_enable(rreinit),
.value(error_abort_not_cleared_count)
);
//Register: status_general
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) `else
always @(posedge clk) `endif
begin
if(!res_n)
begin
status_general_link_up <= 1'h0;
status_general_link_training <= 1'h0;
status_general_sleep_mode <= 1'h0;
status_general_lanes_reversed <= 1'h0;
status_general_phy_ready <= 1'h0;
status_general_hmc_tokens_remaining <= 10'h0;
status_general_rx_tokens_remaining <= 10'h0;
status_general_lane_polarity_reversed <= 0;
end
else
begin
status_general_link_up <= status_general_link_up_next;
status_general_link_training <= status_general_link_training_next;
status_general_sleep_mode <= status_general_sleep_mode_next;
status_general_lanes_reversed <= status_general_lanes_reversed_next;
status_general_phy_ready <= status_general_phy_ready_next;
status_general_hmc_tokens_remaining <= status_general_hmc_tokens_remaining_next;
status_general_rx_tokens_remaining <= status_general_rx_tokens_remaining_next;
status_general_lane_polarity_reversed <= status_general_lane_polarity_reversed_next;
end
end
//Register: status_init
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) `else
always @(posedge clk) `endif
begin
if(!res_n)
begin
status_init_lane_descramblers_locked <= 0;
status_init_descrambler_part_aligned <= 0;
status_init_descrambler_aligned <= 0;
status_init_all_descramblers_aligned <= 1'h0;
status_init_tx_init_status <= 2'h0;
status_init_hmc_init_TS1 <= 1'h0;
end
else
begin
status_init_lane_descramblers_locked <= status_init_lane_descramblers_locked_next;
status_init_descrambler_part_aligned <= status_init_descrambler_part_aligned_next;
status_init_descrambler_aligned <= status_init_descrambler_aligned_next;
status_init_all_descramblers_aligned <= status_init_all_descramblers_aligned_next;
status_init_tx_init_status <= status_init_tx_init_status_next;
status_init_hmc_init_TS1 <= status_init_hmc_init_TS1_next;
end
end
//Register: control
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) `else
always @(posedge clk) `endif
begin
if(!res_n)
begin
control_p_rst_n <= 1'h0;
control_hmc_init_cont_set <= 1'b0;
control_set_hmc_sleep <= 1'h0;
control_scrambler_disable <= 1'h0;
control_run_length_enable <= 1'h0;
control_first_cube_ID <= 3'h0;
control_debug_dont_send_tret <= 1'h0;
control_debug_halt_on_error_abort <= 1'h0;
control_debug_halt_on_tx_retry <= 1'h0;
control_rx_token_count <= 100;
control_irtry_received_threshold <= 5'h10;
control_irtry_to_send <= 5'h16;
control_bit_slip_time <= 6'h28;
end
else
begin
if((address[6:3] == 2) && write_en)
begin
control_p_rst_n <= write_data[0:0];
end
if((address[6:3] == 2) && write_en)
begin
control_hmc_init_cont_set <= write_data[1:1];
end
if((address[6:3] == 2) && write_en)
begin
control_set_hmc_sleep <= write_data[2:2];
end
if((address[6:3] == 2) && write_en)
begin
control_scrambler_disable <= write_data[3:3];
end
if((address[6:3] == 2) && write_en)
begin
control_run_length_enable <= write_data[4:4];
end
if((address[6:3] == 2) && write_en)
begin
control_first_cube_ID <= write_data[7:5];
end
if((address[6:3] == 2) && write_en)
begin
control_debug_dont_send_tret <= write_data[8:8];
end
if((address[6:3] == 2) && write_en)
begin
control_debug_halt_on_error_abort <= write_data[9:9];
end
if((address[6:3] == 2) && write_en)
begin
control_debug_halt_on_tx_retry <= write_data[10:10];
end
if((address[6:3] == 2) && write_en)
begin
control_rx_token_count <= write_data[25:16];
end
if((address[6:3] == 2) && write_en)
begin
control_irtry_received_threshold <= write_data[36:32];
end
if((address[6:3] == 2) && write_en)
begin
control_irtry_to_send <= write_data[44:40];
end
if((address[6:3] == 2) && write_en)
begin
control_bit_slip_time <= write_data[53:48];
end
end
end
//Register: sent_p
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) `else
always @(posedge clk) `endif
begin
if(!res_n)
begin
sent_p_cnt <= 64'h0;
end
else
begin
sent_p_cnt <= sent_p_cnt_next;
end
end
//Register: sent_np
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) `else
always @(posedge clk) `endif
begin
if(!res_n)
begin
sent_np_cnt <= 64'h0;
end
else
begin
sent_np_cnt <= sent_np_cnt_next;
end
end
//Register: sent_r
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) `else
always @(posedge clk) `endif
begin
if(!res_n)
begin
sent_r_cnt <= 64'h0;
end
else
begin
sent_r_cnt <= sent_r_cnt_next;
end
end
//Register: poisoned_packets
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) `else
always @(posedge clk) `endif
begin
if(!res_n)
begin
poisoned_packets_cnt <= 64'h0;
end
else
begin
poisoned_packets_cnt <= poisoned_packets_cnt_next;
end
end
//Register: rcvd_rsp
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) `else
always @(posedge clk) `endif
begin
if(!res_n)
begin
rcvd_rsp_cnt <= 64'h0;
end
else
begin
rcvd_rsp_cnt <= rcvd_rsp_cnt_next;
end
end
//Register: counter_reset
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) `else
always @(posedge clk) `endif
begin
if(!res_n)
begin
rreinit <= 1'b0;
end
else
begin
if((address[6:3] == 8) && write_en)
begin
rreinit <= 1'b1;
end
else
begin
rreinit <= 1'b0;
end
end
end
//Address Decoder Software Read:
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) `else
always @(posedge clk) `endif
begin
if(!res_n)
begin
invalid_address <= 1'b0;
access_complete <= 1'b0;
read_data <= 64'b0;
end
else
begin
casex(address[6:3])
4'h0:
begin
read_data[0:0] <= status_general_link_up;
read_data[1:1] <= status_general_link_training;
read_data[2:2] <= status_general_sleep_mode;
read_data[3:3] <= status_general_lanes_reversed;
read_data[8:8] <= status_general_phy_ready;
read_data[25:16] <= status_general_hmc_tokens_remaining;
read_data[41:32] <= status_general_rx_tokens_remaining;
read_data[55:48] <= status_general_lane_polarity_reversed;
read_data[63:56] <= 8'b0;
invalid_address <= write_en;
access_complete <= read_en || write_en;
end
4'h1:
begin
read_data[7:0] <= status_init_lane_descramblers_locked;
read_data[23:16] <= status_init_descrambler_part_aligned;
read_data[39:32] <= status_init_descrambler_aligned;
read_data[48:48] <= status_init_all_descramblers_aligned;
read_data[50:49] <= status_init_tx_init_status;
read_data[51:51] <= status_init_hmc_init_TS1;
read_data[63:52] <= 12'b0;
invalid_address <= write_en;
access_complete <= read_en || write_en;
end
4'h2:
begin
read_data[0:0] <= control_p_rst_n;
read_data[1:1] <= control_hmc_init_cont_set;
read_data[2:2] <= control_set_hmc_sleep;
read_data[3:3] <= control_scrambler_disable;
read_data[4:4] <= control_run_length_enable;
read_data[7:5] <= control_first_cube_ID;
read_data[8:8] <= control_debug_dont_send_tret;
read_data[9:9] <= control_debug_halt_on_error_abort;
read_data[10:10] <= control_debug_halt_on_tx_retry;
read_data[25:16] <= control_rx_token_count;
read_data[36:32] <= control_irtry_received_threshold;
read_data[44:40] <= control_irtry_to_send;
read_data[53:48] <= control_bit_slip_time;
read_data[63:54] <= 10'b0;
invalid_address <= 1'b0;
access_complete <= read_en || write_en;
end
4'h3:
begin
read_data[63:0] <= sent_p_cnt;
invalid_address <= write_en;
access_complete <= read_en || write_en;
end
4'h4:
begin
read_data[63:0] <= sent_np_cnt;
invalid_address <= write_en;
access_complete <= read_en || write_en;
end
4'h5:
begin
read_data[63:0] <= sent_r_cnt;
invalid_address <= write_en;
access_complete <= read_en || write_en;
end
4'h6:
begin
read_data[63:0] <= poisoned_packets_cnt;
invalid_address <= write_en;
access_complete <= read_en || write_en;
end
4'h7:
begin
read_data[63:0] <= rcvd_rsp_cnt;
invalid_address <= write_en;
access_complete <= read_en || write_en;
end
4'h8:
begin
read_data[63:0] <= 64'b0;
invalid_address <= read_en;
access_complete <= read_en || write_en;
end
4'h9:
begin
read_data[31:0] <= tx_link_retries_count;
read_data[63:32] <= 32'b0;
invalid_address <= write_en;
access_complete <= read_en || write_en;
end
4'ha:
begin
read_data[31:0] <= errors_on_rx_count;
read_data[63:32] <= 32'b0;
invalid_address <= write_en;
access_complete <= read_en || write_en;
end
4'hb:
begin
read_data[31:0] <= run_length_bit_flip_count;
read_data[63:32] <= 32'b0;
invalid_address <= write_en;
access_complete <= read_en || write_en;
end
4'hc:
begin
read_data[31:0] <= error_abort_not_cleared_count;
read_data[63:32] <= 32'b0;
invalid_address <= write_en;
access_complete <= read_en || write_en;
end
default:
begin
invalid_address <= read_en || write_en;
access_complete <= read_en || write_en;
end
endcase
end
end
endmodule |
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`include "../../../../usrp/firmware/include/fpga_regs_common.v"
`include "../../../../usrp/firmware/include/fpga_regs_standard.v"
module sounder_tx(clk_i,rst_i,ena_i,strobe_i,ampl_i,mask_i,tx_i_o,tx_q_o);
input clk_i;
input rst_i;
input ena_i;
input strobe_i;
input [13:0] ampl_i;
input [15:0] mask_i;
output [13:0] tx_i_o;
output [13:0] tx_q_o;
wire pn;
wire [13:0] min_value = (~ampl_i)+14'b1;
lfsr pn_code
( .clk_i(clk_i),.rst_i(rst_i),.ena_i(ena_i),.strobe_i(strobe_i),.mask_i(mask_i),.pn_o(pn) );
assign tx_i_o = ena_i ? (pn ? ampl_i : min_value) : 14'b0; // Bipolar
assign tx_q_o = 14'b0;
endmodule // sounder_tx
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFXBP_PP_SYMBOL_V
`define SKY130_FD_SC_LP__SDFXBP_PP_SYMBOL_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFXBP_PP_SYMBOL_V
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule
module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule
module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule
module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule
module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule
module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule
|
module autoconstant_gooch
(/*AUTOARG*/
// Outputs
out1, out2, out3,
// Inputs
in1, in2, in3
);
input [3:0] in1;
input [3:0] in2;
input [3:0] in3;
output [3:0] out1;
reg [3:0] out1;
output [3:0] out2;
reg [3:0] out2;
output [3:0] out3;
reg [3:0] out3;
always @(/*AUTOSENSE*/in1 or in2 or in3)
begin
case (in1)
4'b0001 : begin
out1 = in2;
end
4'b0010 : begin
out1 = in2 + in3;
end
4'b0100 : begin
out1 = in2 - in3;
end
4'b1000 : begin
out1 = in2;
end
default : begin
out1 = {4{1'b0}};
end
endcase
end
always @(/*AUTOSENSE*/in1 or in2 or in3)
begin
case (in1)
4'b0001 : begin
out2 = in2;
end
4'b0010 : begin
out2 = in2 + in3;
end
4'b0100 : begin
out2 = in2 - in3;
end
4'b1000 : begin
out2 = in2;
end
default : begin
out2 = {4{1'b0}};
end
endcase
end
always @(/*AUTOSENSE*/in1 or in2 or in3)
begin
/* AUTO_CONSTANT( temp )*/
/* AxxxUTO_CONSTANT temp */
out3 = in1 + in2;
temp2 = temp;
// ERROR here - above constant definition is not
// correct - no braces - and so parser keeps looking
// for the first variable it finds between a pair of
// braces - in this case, in2. This in2 is now a
// "constant" and is removed from all sensitivity lists.
// ( in2 )
case (in1)
4'b0001 : begin
out3 = in2;
end
4'b0010 : begin
out3 = in2 + in3;
end
4'b0100 : begin
out3 = in2 - in3;
end
4'b1000 : begin
out3 = in2;
end
default : begin
out3 = {4{1'b0}};
end
endcase
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// $Id: small_fifo.v 1998 2007-07-21 01:22:57Z grg $
//
// Module: fallthrough_small_fifo.v
// Project: utils
// Description: small fifo with fallthrough i.e. data valid when rd is high
//
// Change history:
// 7/20/07 -- Set nearly full to 2^MAX_DEPTH_BITS - 1 by default so that it
// goes high a clock cycle early.
// 2/11/09 -- jnaous: Rewrote to make much more efficient.
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module fallthrough_small_fifo
#(parameter WIDTH = 72,
parameter MAX_DEPTH_BITS = 3,
parameter PROG_FULL_THRESHOLD = 2**MAX_DEPTH_BITS - 1)
(
input [WIDTH-1:0] din, // Data in
input wr_en, // Write enable
input rd_en, // Read the next word
output [WIDTH-1:0] dout, // Data out
output full,
output nearly_full,
output prog_full,
output reg empty,
output [MAX_DEPTH_BITS:0] data_count,
input reset,
input clk
);
reg fifo_rd_en, empty_nxt;
small_fifo
#(.WIDTH (WIDTH),
.MAX_DEPTH_BITS (MAX_DEPTH_BITS),
.PROG_FULL_THRESHOLD (PROG_FULL_THRESHOLD))
fifo
(.din (din),
.wr_en (wr_en),
.rd_en (fifo_rd_en),
.dout (dout),
.full (full),
.nearly_full (nearly_full),
.prog_full (prog_full),
.empty (fifo_empty),
.data_count (data_count),
.reset (reset),
.clk (clk)
);
always @(*) begin
empty_nxt = empty;
fifo_rd_en = 0;
case (empty)
1'b1: begin
if(!fifo_empty) begin
fifo_rd_en = 1;
empty_nxt = 0;
end
end
1'b0: begin
if(rd_en) begin
if(fifo_empty) begin
empty_nxt = 1;
end
else begin
fifo_rd_en = 1;
end
end
end
endcase // case(empty)
end // always @ (*)
always @(posedge clk) begin
if(reset) begin
empty <= 1'b1;
end
else begin
empty <= empty_nxt;
end
end
// synthesis translate_off
always @(posedge clk)
begin
if (wr_en && full) begin
$display("%t ERROR: Attempt to write to full FIFO: %m", $time);
end
if (rd_en && empty) begin
$display("%t ERROR: Attempt to read an empty FIFO: %m", $time);
end
end // always @ (posedge clk)
// synthesis translate_on
endmodule // fallthrough_small_fifo_v2
// synthesis translate_off
module fallthrough_small_fifo_tester();
reg [31:0] din = 0;
reg wr_en = 0;
reg rd_en = 0;
wire [31:0] dout;
wire full;
wire nearly_full;
wire prog_full;
wire empty;
reg clk = 0;
reg reset = 0;
integer count = 0;
always #8 clk = ~clk;
fallthrough_small_fifo
#(.WIDTH (32),
.MAX_DEPTH_BITS (3),
.PROG_FULL_THRESHOLD (4))
fifo
(.din (din),
.wr_en (wr_en),
.rd_en (rd_en),
.dout (dout),
.full (full),
.nearly_full (nearly_full),
.prog_full (prog_full),
.empty (empty),
.reset (reset),
.clk (clk)
);
always @(posedge clk) begin
count <= count + 1;
reset <= 0;
wr_en <= 0;
rd_en <= 0;
if(count < 2) begin
reset <= 1'b1;
end
else if(count < 2 + 9) begin
wr_en <= 1;
din <= din + 1'b1;
end
else if(count < 2 + 8 + 4) begin
rd_en <= 1;
end
else if(count < 2 + 8 + 4 + 2) begin
din <= din + 1'b1;
wr_en <= 1'b1;
end
else if(count < 2 + 8 + 4 + 2 + 8) begin
din <= din + 1'b1;
wr_en <= 1'b1;
rd_en <= 1'b1;
end
else if(count < 2 + 8 + 4 + 2 + 8 + 4) begin
rd_en <= 1'b1;
end
else if(count < 2 + 8 + 4 + 2 + 8 + 4 + 8) begin
din <= din + 1'b1;
wr_en <= 1'b1;
rd_en <= 1'b1;
end
end // always @ (posedge clk)
endmodule // fallthrough_small_fifo_tester
// synthesis translate_on
/* vim:set shiftwidth=3 softtabstop=3 expandtab: */
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
`include "trellis.vh"
`include "riffa.vh"
`timescale 1ns/1ns
module riffa
#(parameter C_PCI_DATA_WIDTH = 128,
parameter C_NUM_CHNL = 12,
parameter C_MAX_READ_REQ_BYTES = 512, // Max size of read requests (in bytes)
parameter C_TAG_WIDTH = 5, // Number of outstanding requests
parameter C_VENDOR = "ALTERA",
parameter C_FPGA_NAME = "FPGA", // TODO: Give each channel a unique name
parameter C_FPGA_ID = 0,// A value from 0 to 255 uniquely identifying this RIFFA design
parameter C_DEPTH_PACKETS = 10)
(input CLK,
input RST_BUS,
output RST_OUT,
input DONE_TXC_RST,
input DONE_TXR_RST,
// Interface: RXC Engine
input [C_PCI_DATA_WIDTH-1:0] RXC_DATA,
input RXC_DATA_VALID,
input [(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_WORD_ENABLE,
input RXC_DATA_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_START_OFFSET,
input RXC_DATA_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_END_OFFSET,
input [`SIG_LBE_W-1:0] RXC_META_LDWBE,
input [`SIG_FBE_W-1:0] RXC_META_FDWBE,
input [`SIG_TAG_W-1:0] RXC_META_TAG,
input [`SIG_LOWADDR_W-1:0] RXC_META_ADDR,
input [`SIG_TYPE_W-1:0] RXC_META_TYPE,
input [`SIG_LEN_W-1:0] RXC_META_LENGTH,
input [`SIG_BYTECNT_W-1:0] RXC_META_BYTES_REMAINING,
input [`SIG_CPLID_W-1:0] RXC_META_COMPLETER_ID,
input RXC_META_EP,
// Interface: RXR Engine
input [C_PCI_DATA_WIDTH-1:0] RXR_DATA,
input RXR_DATA_VALID,
input [(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_WORD_ENABLE,
input RXR_DATA_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_START_OFFSET,
input RXR_DATA_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_END_OFFSET,
input [`SIG_FBE_W-1:0] RXR_META_FDWBE,
input [`SIG_LBE_W-1:0] RXR_META_LDWBE,
input [`SIG_TC_W-1:0] RXR_META_TC,
input [`SIG_ATTR_W-1:0] RXR_META_ATTR,
input [`SIG_TAG_W-1:0] RXR_META_TAG,
input [`SIG_TYPE_W-1:0] RXR_META_TYPE,
input [`SIG_ADDR_W-1:0] RXR_META_ADDR,
input [`SIG_BARDECODE_W-1:0] RXR_META_BAR_DECODED,
input [`SIG_REQID_W-1:0] RXR_META_REQUESTER_ID,
input [`SIG_LEN_W-1:0] RXR_META_LENGTH,
input RXR_META_EP,
// Interface: TXC Engine
output [C_PCI_DATA_WIDTH-1:0] TXC_DATA,
output TXC_DATA_VALID,
output TXC_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_START_OFFSET,
output TXC_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_END_OFFSET,
input TXC_DATA_READY,
output TXC_META_VALID,
output [`SIG_FBE_W-1:0] TXC_META_FDWBE,
output [`SIG_LBE_W-1:0] TXC_META_LDWBE,
output [`SIG_LOWADDR_W-1:0] TXC_META_ADDR,
output [`SIG_TYPE_W-1:0] TXC_META_TYPE,
output [`SIG_LEN_W-1:0] TXC_META_LENGTH,
output [`SIG_BYTECNT_W-1:0] TXC_META_BYTE_COUNT,
output [`SIG_TAG_W-1:0] TXC_META_TAG,
output [`SIG_REQID_W-1:0] TXC_META_REQUESTER_ID,
output [`SIG_TC_W-1:0] TXC_META_TC,
output [`SIG_ATTR_W-1:0] TXC_META_ATTR,
output TXC_META_EP,
input TXC_META_READY,
input TXC_SENT,
// Interface: TXR Engine
output TXR_DATA_VALID,
output [C_PCI_DATA_WIDTH-1:0] TXR_DATA,
output TXR_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET,
output TXR_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET,
input TXR_DATA_READY,
output TXR_META_VALID,
output [`SIG_FBE_W-1:0] TXR_META_FDWBE,
output [`SIG_LBE_W-1:0] TXR_META_LDWBE,
output [`SIG_ADDR_W-1:0] TXR_META_ADDR,
output [`SIG_LEN_W-1:0] TXR_META_LENGTH,
output [`SIG_TAG_W-1:0] TXR_META_TAG,
output [`SIG_TC_W-1:0] TXR_META_TC,
output [`SIG_ATTR_W-1:0] TXR_META_ATTR,
output [`SIG_TYPE_W-1:0] TXR_META_TYPE,
output TXR_META_EP,
input TXR_META_READY,
input TXR_SENT,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
input CONFIG_BUS_MASTER_ENABLE,
input [`SIG_LINKWIDTH_W-1:0] CONFIG_LINK_WIDTH,
input [`SIG_LINKRATE_W-1:0] CONFIG_LINK_RATE,
input [`SIG_MAXREAD_W-1:0] CONFIG_MAX_READ_REQUEST_SIZE,
input [`SIG_MAXPAYLOAD_W-1:0] CONFIG_MAX_PAYLOAD_SIZE,
input [`SIG_FC_CPLD_W-1:0] CONFIG_MAX_CPL_DATA, // Receive credit limit for data
input [`SIG_FC_CPLH_W-1:0] CONFIG_MAX_CPL_HDR, // Receive credit limit for headers
input CONFIG_INTERRUPT_MSIENABLE,
input CONFIG_CPL_BOUNDARY_SEL,
// Interrupt Request
input INTR_MSI_RDY, // High when interrupt is able to be sent
output INTR_MSI_REQUEST, // High to request interrupt, when both INTR_MSI_RDY and INTR_MSI_RE
input [C_NUM_CHNL-1:0] CHNL_RX_CLK,
output [C_NUM_CHNL-1:0] CHNL_RX,
input [C_NUM_CHNL-1:0] CHNL_RX_ACK,
output [C_NUM_CHNL-1:0] CHNL_RX_LAST,
output [(C_NUM_CHNL*32)-1:0] CHNL_RX_LEN,
output [(C_NUM_CHNL*31)-1:0] CHNL_RX_OFF,
output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_RX_DATA,
output [C_NUM_CHNL-1:0] CHNL_RX_DATA_VALID,
input [C_NUM_CHNL-1:0] CHNL_RX_DATA_REN,
input [C_NUM_CHNL-1:0] CHNL_TX_CLK,
input [C_NUM_CHNL-1:0] CHNL_TX,
output [C_NUM_CHNL-1:0] CHNL_TX_ACK,
input [C_NUM_CHNL-1:0] CHNL_TX_LAST,
input [(C_NUM_CHNL*32)-1:0] CHNL_TX_LEN,
input [(C_NUM_CHNL*31)-1:0] CHNL_TX_OFF,
input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_TX_DATA,
input [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID,
output [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN
);
localparam C_MAX_READ_REQ = clog2s(C_MAX_READ_REQ_BYTES)-7; // Max read: 000=128B; 001=256B; 010=512B; 011=1024B; 100=2048B; 101=4096B
localparam C_NUM_CHNL_WIDTH = clog2s(C_NUM_CHNL);
localparam C_PCI_DATA_WORD_WIDTH = clog2s((C_PCI_DATA_WIDTH/32)+1);
localparam C_NUM_VECTORS = 2;
localparam C_VECTOR_WIDTH = 32;
// Interface: Reorder Buffer Output
wire [(C_NUM_CHNL*C_PCI_DATA_WORD_WIDTH)-1:0] wRxEngMainDataEn; // Start offset and end offset
wire [C_PCI_DATA_WIDTH-1:0] wRxEngData;
wire [C_NUM_CHNL-1:0] wRxEngMainDone;
wire [C_NUM_CHNL-1:0] wRxEngMainErr;
// Interface: Reorder Buffer to SG RX engines
wire [(C_NUM_CHNL*C_PCI_DATA_WORD_WIDTH)-1:0] wRxEngSgRxDataEn;
wire [C_NUM_CHNL-1:0] wRxEngSgRxDone;
wire [C_NUM_CHNL-1:0] wRxEngSgRxErr;
// Interface: Reorder Buffer to SG TX engines
wire [(C_NUM_CHNL*C_PCI_DATA_WORD_WIDTH)-1:0] wRxEngSgTxDataEn;
wire [C_NUM_CHNL-1:0] wRxEngSgTxDone;
wire [C_NUM_CHNL-1:0] wRxEngSgTxErr;
// Interface: Channel TX Write
wire [C_NUM_CHNL-1:0] wTxEngWrReq;
wire [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] wTxEngWrAddr;
wire [(C_NUM_CHNL*`SIG_LEN_W)-1:0] wTxEngWrLen;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] wTxEngWrData;
wire [C_NUM_CHNL-1:0] wTxEngWrDataRen;
wire [C_NUM_CHNL-1:0] wTxEngWrAck;
wire [C_NUM_CHNL-1:0] wTxEngWrSent;
// Interface: Channel TX Read
wire [C_NUM_CHNL-1:0] wTxEngRdReq;
wire [(C_NUM_CHNL*2)-1:0] wTxEngRdSgChnl;
wire [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] wTxEngRdAddr;
wire [(C_NUM_CHNL*`SIG_LEN_W)-1:0] wTxEngRdLen;
wire [C_NUM_CHNL-1:0] wTxEngRdAck;
// Interface: Channel Interrupts
wire [C_NUM_CHNL-1:0] wChnlSgRxBufRecvd;
wire [C_NUM_CHNL-1:0] wChnlRxDone;
wire [C_NUM_CHNL-1:0] wChnlTxRequest;
wire [C_NUM_CHNL-1:0] wChnlTxDone;
wire [C_NUM_CHNL-1:0] wChnlSgTxBufRecvd;
wire wInternalTagValid;
wire [5:0] wInternalTag;
wire wExternalTagValid;
wire [C_TAG_WIDTH-1:0] wExternalTag;
// Interface: Channel - PIO Read
wire [C_NUM_CHNL-1:0] wChnlTxLenReady;
wire [(`SIG_TXRLEN_W*C_NUM_CHNL)-1:0] wChnlTxReqLen;
wire [C_NUM_CHNL-1:0] wChnlTxOfflastReady;
wire [(`SIG_OFFLAST_W*C_NUM_CHNL)-1:0] wChnlTxOfflast;
wire wCoreSettingsReady;
wire [`SIG_CORESETTINGS_W-1:0] wCoreSettings;
wire [C_NUM_VECTORS-1:0] wIntrVectorReady;
wire [C_NUM_VECTORS*C_VECTOR_WIDTH-1:0] wIntrVector;
wire [C_NUM_CHNL-1:0] wChnlTxDoneReady;
wire [(`SIG_TXDONELEN_W*C_NUM_CHNL)-1:0] wChnlTxDoneLen;
wire [C_NUM_CHNL-1:0] wChnlRxDoneReady;
wire [(`SIG_RXDONELEN_W*C_NUM_CHNL)-1:0] wChnlRxDoneLen;
wire wChnlNameReady;
// Interface: Channel - PIO Write
wire [31:0] wChnlReqData;
wire [C_NUM_CHNL-1:0] wChnlSgRxLenValid;
wire [C_NUM_CHNL-1:0] wChnlSgRxAddrLoValid;
wire [C_NUM_CHNL-1:0] wChnlSgRxAddrHiValid;
wire [C_NUM_CHNL-1:0] wChnlSgTxLenValid;
wire [C_NUM_CHNL-1:0] wChnlSgTxAddrLoValid;
wire [C_NUM_CHNL-1:0] wChnlSgTxAddrHiValid;
wire [C_NUM_CHNL-1:0] wChnlRxLenValid;
wire [C_NUM_CHNL-1:0] wChnlRxOfflastValid;
// Interface: TXC Engine
wire [C_PCI_DATA_WIDTH-1:0] _wTxcData, wTxcData;
wire _wTxcDataValid, wTxcDataValid;
wire _wTxcDataStartFlag, wTxcDataStartFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] _wTxcDataStartOffset, wTxcDataStartOffset;
wire _wTxcDataEndFlag, wTxcDataEndFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] _wTxcDataEndOffset, wTxcDataEndOffset;
wire _wTxcDataReady, wTxcDataReady;
wire _wTxcMetaValid, wTxcMetaValid;
wire [`SIG_FBE_W-1:0] _wTxcMetaFdwbe, wTxcMetaFdwbe;
wire [`SIG_LBE_W-1:0] _wTxcMetaLdwbe, wTxcMetaLdwbe;
wire [`SIG_LOWADDR_W-1:0] _wTxcMetaAddr, wTxcMetaAddr;
wire [`SIG_TYPE_W-1:0] _wTxcMetaType, wTxcMetaType;
wire [`SIG_LEN_W-1:0] _wTxcMetaLength, wTxcMetaLength;
wire [`SIG_BYTECNT_W-1:0] _wTxcMetaByteCount, wTxcMetaByteCount;
wire [`SIG_TAG_W-1:0] _wTxcMetaTag, wTxcMetaTag;
wire [`SIG_REQID_W-1:0] _wTxcMetaRequesterId, wTxcMetaRequesterId;
wire [`SIG_TC_W-1:0] _wTxcMetaTc, wTxcMetaTc;
wire [`SIG_ATTR_W-1:0] _wTxcMetaAttr, wTxcMetaAttr;
wire _wTxcMetaEp, wTxcMetaEp;
wire _wTxcMetaReady, wTxcMetaReady;
wire wRxBufSpaceAvail;
wire wTxEngRdReqSent;
wire wRxEngRdComplete;
wire [31:0] wCPciDataWidth;
reg [31:0] wCFpgaId;
reg [4:0] rWideRst;
reg rRst;
genvar i;
assign wRxEngRdComplete = RXC_DATA_END_FLAG & RXC_DATA_VALID &
(RXC_META_LENGTH >= RXC_META_BYTES_REMAINING[`SIG_BYTECNT_W-1:2]);// TODO: Retime (if possible)
assign wCoreSettings = {1'd0, wCFpgaId, wCPciDataWidth[8:5],
CONFIG_MAX_PAYLOAD_SIZE, CONFIG_MAX_READ_REQUEST_SIZE,
CONFIG_LINK_RATE[1:0], CONFIG_LINK_WIDTH, CONFIG_BUS_MASTER_ENABLE,
C_NUM_CHNL[3:0]};
// Interface: TXC Engine
assign TXC_DATA = wTxcData;
assign TXC_DATA_START_FLAG = wTxcDataStartFlag;
assign TXC_DATA_START_OFFSET = wTxcDataStartOffset;
assign TXC_DATA_END_FLAG = wTxcDataEndFlag;
assign TXC_DATA_END_OFFSET = wTxcDataEndOffset;
assign TXC_DATA_VALID = wTxcDataValid & ~wPendingRst & DONE_TXC_RST;
assign wTxcDataReady = TXC_DATA_READY & ~wPendingRst & DONE_TXC_RST;
assign TXC_META_FDWBE = wTxcMetaFdwbe;
assign TXC_META_LDWBE = wTxcMetaLdwbe;
assign TXC_META_ADDR = wTxcMetaAddr;
assign TXC_META_TYPE = wTxcMetaType;
assign TXC_META_LENGTH = wTxcMetaLength;
assign TXC_META_BYTE_COUNT = wTxcMetaByteCount;
assign TXC_META_TAG = wTxcMetaTag;
assign TXC_META_REQUESTER_ID = wTxcMetaRequesterId;
assign TXC_META_TC = wTxcMetaTc;
assign TXC_META_ATTR = wTxcMetaAttr;
assign TXC_META_EP = wTxcMetaEp;
assign TXC_META_VALID = wTxcMetaValid & ~wPendingRst & DONE_TXC_RST;
assign wTxcMetaReady = TXC_META_READY & ~wPendingRst & DONE_TXC_RST;
/* Workaround for a bug reported by the NetFPGA group, where the parameter
C_PCI_DATA_WIDTH cannot be directly assigned to a wire. */
generate
if(C_PCI_DATA_WIDTH == 32) begin
assign wCPciDataWidth = 32;
end else if (C_PCI_DATA_WIDTH == 64) begin
assign wCPciDataWidth = 64;
end else if (C_PCI_DATA_WIDTH == 128) begin
assign wCPciDataWidth = 128;
end else if (C_PCI_DATA_WIDTH == 256) begin
assign wCPciDataWidth = 256;
end
always @(*) begin
wCFpgaId = 0;
if((C_FPGA_ID & 128) != 0) begin
wCFpgaId[7] = 1;
end else if ((C_FPGA_ID & 64) != 1) begin
wCFpgaId[6] = 1;
end else if ((C_FPGA_ID & 32) != 1) begin
wCFpgaId[5] = 1;
end else if ((C_FPGA_ID & 16) != 1) begin
wCFpgaId[4] = 1;
end else if ((C_FPGA_ID & 8) != 1) begin
wCFpgaId[3] = 1;
end else if ((C_FPGA_ID & 4) != 1) begin
wCFpgaId[2] = 1;
end else if ((C_FPGA_ID & 2) != 1) begin
wCFpgaId[1] = 1;
end else if ((C_FPGA_ID & 1) != 1) begin
wCFpgaId[0] = 1;
end
end
endgenerate
/* The purpose of these two hold modules is to safely reset the TX path and
still respond to the core status request (which causes a RIFFA reset). We
could wait until after the completion has been transmitted, but we have no
guarantee that the TX path is operating correctly until after we reset */
pipeline
#(// Parameters
.C_DEPTH (1),
.C_WIDTH (2 * `SIG_FBE_W + `SIG_LOWADDR_W +
`SIG_TYPE_W + `SIG_LEN_W +
`SIG_BYTECNT_W + `SIG_TAG_W +
`SIG_REQID_W + `SIG_TC_W +
`SIG_ATTR_W + 1),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
txc_meta_hold
(// Outputs
.WR_DATA_READY (_wTxcMetaReady), // NC
.RD_DATA ({wTxcMetaFdwbe, wTxcMetaLdwbe,
wTxcMetaAddr, wTxcMetaType,
wTxcMetaLength,
wTxcMetaByteCount, wTxcMetaTag,
wTxcMetaRequesterId, wTxcMetaTc,
wTxcMetaAttr, wTxcMetaEp}),
.RD_DATA_VALID (wTxcMetaValid),
// Inputs
.WR_DATA ({_wTxcMetaFdwbe, _wTxcMetaLdwbe,
_wTxcMetaAddr, _wTxcMetaType,
_wTxcMetaLength,
_wTxcMetaByteCount, _wTxcMetaTag,
_wTxcMetaRequesterId, _wTxcMetaTc,
_wTxcMetaAttr, _wTxcMetaEp}),
.WR_DATA_VALID (_wTxcMetaValid),
.RD_DATA_READY (wTxcMetaReady),
.RST_IN (RST_BUS),
/*AUTOINST*/
// Inputs
.CLK (CLK));
pipeline
#(// Parameters
.C_DEPTH (1),
.C_WIDTH (C_PCI_DATA_WIDTH +
2 * (clog2s(C_PCI_DATA_WIDTH/32) + 1)),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
txc_data_hold
(// Outputs
.WR_DATA_READY (_wTxcDataReady), // NC
.RD_DATA ({wTxcData, wTxcDataStartFlag,
wTxcDataStartOffset, wTxcDataEndFlag,
wTxcDataEndOffset}),
.RD_DATA_VALID (wTxcDataValid),
// Inputs
.WR_DATA ({_wTxcData, _wTxcDataStartFlag,
_wTxcDataStartOffset, _wTxcDataEndFlag,
_wTxcDataEndOffset}),
.WR_DATA_VALID (_wTxcDataValid),
.RD_DATA_READY (wTxcDataReady),
.RST_IN (RST_BUS),
/*AUTOINST*/
// Inputs
.CLK (CLK));
reset_extender
#(.C_RST_COUNT (8)
/*AUTOINSTPARAM*/)
reset_extender_inst
(// Outputs
.PENDING_RST (wPendingRst),
// Inputs
.RST_LOGIC (wCoreSettingsReady),
/*AUTOINST*/
// Outputs
.RST_OUT (RST_OUT),
// Inputs
.CLK (CLK),
.RST_BUS (RST_BUS));
reorder_queue
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),
.C_NUM_CHNL(C_NUM_CHNL),
.C_MAX_READ_REQ_BYTES(C_MAX_READ_REQ_BYTES),
.C_TAG_WIDTH(C_TAG_WIDTH))
reorderQueue
(.RST (RST_OUT),
.VALID (RXC_DATA_VALID),
.DATA_START_FLAG (RXC_DATA_START_FLAG),
.DATA_START_OFFSET (RXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.DATA_END_FLAG (RXC_DATA_END_FLAG),
.DATA_END_OFFSET (RXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.DATA (RXC_DATA),
.DATA_EN (RXC_DATA_WORD_ENABLE),
.DONE (wRxEngRdComplete),
.ERR (RXC_META_EP),
.TAG (RXC_META_TAG[C_TAG_WIDTH-1:0]),
.INT_TAG (wInternalTag),
.INT_TAG_VALID (wInternalTagValid),
.EXT_TAG (wExternalTag),
.EXT_TAG_VALID (wExternalTagValid),
.ENG_DATA (wRxEngData),
.MAIN_DATA_EN (wRxEngMainDataEn),
.MAIN_DONE (wRxEngMainDone),
.MAIN_ERR (wRxEngMainErr),
.SG_RX_DATA_EN (wRxEngSgRxDataEn),
.SG_RX_DONE (wRxEngSgRxDone),
.SG_RX_ERR (wRxEngSgRxErr),
.SG_TX_DATA_EN (wRxEngSgTxDataEn),
.SG_TX_DONE (wRxEngSgTxDone),
.SG_TX_ERR (wRxEngSgTxErr),
/*AUTOINST*/
// Inputs
.CLK (CLK));
registers
#(// Parameters
.C_PIPELINE_OUTPUT (1),
.C_PIPELINE_INPUT (1),
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_NUM_CHNL (C_NUM_CHNL),
.C_MAX_READ_REQ_BYTES (C_MAX_READ_REQ_BYTES),
.C_VENDOR (C_VENDOR),
.C_NUM_VECTORS (C_NUM_VECTORS),
.C_VECTOR_WIDTH (C_VECTOR_WIDTH),
.C_FPGA_NAME (C_FPGA_NAME))
reg_inst
(// Outputs
// Write Interfaces
.CHNL_REQ_DATA (wChnlReqData[31:0]),
.CHNL_SGRX_LEN_VALID (wChnlSgRxLenValid),
.CHNL_SGRX_ADDRLO_VALID (wChnlSgRxAddrLoValid),
.CHNL_SGRX_ADDRHI_VALID (wChnlSgRxAddrHiValid),
.CHNL_SGTX_LEN_VALID (wChnlSgTxLenValid),
.CHNL_SGTX_ADDRLO_VALID (wChnlSgTxAddrLoValid),
.CHNL_SGTX_ADDRHI_VALID (wChnlSgTxAddrHiValid),
.CHNL_RX_LEN_VALID (wChnlRxLenValid),
.CHNL_RX_OFFLAST_VALID (wChnlRxOfflastValid),
// Read Interfaces
.CHNL_TX_LEN_READY (wChnlTxLenReady),
.CHNL_TX_OFFLAST_READY (wChnlTxOfflastReady),
.CORE_SETTINGS_READY (wCoreSettingsReady),
.INTR_VECTOR_READY (wIntrVectorReady),
.CHNL_TX_DONE_READY (wChnlTxDoneReady),
.CHNL_RX_DONE_READY (wChnlRxDoneReady),
.CHNL_NAME_READY (wChnlNameReady), // TODO: Could do this on a per-channel basis
// TXC Engine Interface
.TXC_DATA_VALID (_wTxcDataValid),
.TXC_DATA (_wTxcData[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_START_FLAG (_wTxcDataStartFlag),
.TXC_DATA_START_OFFSET (_wTxcDataStartOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (_wTxcDataEndFlag),
.TXC_DATA_END_OFFSET (_wTxcDataEndOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (_wTxcMetaValid),
.TXC_META_FDWBE (_wTxcMetaFdwbe[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (_wTxcMetaLdwbe[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (_wTxcMetaAddr[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (_wTxcMetaType[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (_wTxcMetaLength[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (_wTxcMetaByteCount[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (_wTxcMetaTag[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (_wTxcMetaRequesterId[`SIG_REQID_W-1:0]),
.TXC_META_TC (_wTxcMetaTc[`SIG_TC_W-1:0]),
.TXC_META_ATTR (_wTxcMetaAttr[`SIG_ATTR_W-1:0]),
.TXC_META_EP (_wTxcMetaEp),
// Inputs
// Read Data
.CORE_SETTINGS (wCoreSettings),
.CHNL_TX_REQLEN (wChnlTxReqLen),
.CHNL_TX_OFFLAST (wChnlTxOfflast),
.CHNL_TX_DONELEN (wChnlTxDoneLen),
.CHNL_RX_DONELEN (wChnlRxDoneLen),
.INTR_VECTOR (wIntrVector),
.RST_IN (RST_OUT),
.TXC_DATA_READY (_wTxcDataReady),
.TXC_META_READY (_wTxcMetaReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RXR_DATA (RXR_DATA[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_VALID (RXR_DATA_VALID),
.RXR_DATA_START_FLAG (RXR_DATA_START_FLAG),
.RXR_DATA_START_OFFSET (RXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (RXR_META_FDWBE[`SIG_FBE_W-1:0]),
.RXR_DATA_END_FLAG (RXR_DATA_END_FLAG),
.RXR_DATA_END_OFFSET (RXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_LDWBE (RXR_META_LDWBE[`SIG_LBE_W-1:0]),
.RXR_META_TC (RXR_META_TC[`SIG_TC_W-1:0]),
.RXR_META_ATTR (RXR_META_ATTR[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (RXR_META_TAG[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (RXR_META_TYPE[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (RXR_META_ADDR[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (RXR_META_BAR_DECODED[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (RXR_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (RXR_META_LENGTH[`SIG_LEN_W-1:0]));
// Track receive buffer flow control credits (header & Data)
recv_credit_flow_ctrl rc_fc
(// Outputs
.RXBUF_SPACE_AVAIL (wRxBufSpaceAvail),
// Inputs
.RX_ENG_RD_DONE (wRxEngRdComplete),
.TX_ENG_RD_REQ_SENT (wTxEngRdReqSent),
.RST (RST_OUT),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.CONFIG_MAX_READ_REQUEST_SIZE (CONFIG_MAX_READ_REQUEST_SIZE[2:0]),
.CONFIG_MAX_CPL_DATA (CONFIG_MAX_CPL_DATA[11:0]),
.CONFIG_MAX_CPL_HDR (CONFIG_MAX_CPL_HDR[7:0]),
.CONFIG_CPL_BOUNDARY_SEL (CONFIG_CPL_BOUNDARY_SEL));
// Connect the interrupt vector and controller.
interrupt
#(.C_NUM_CHNL (C_NUM_CHNL))
intr
(// Inputs
.RST (RST_OUT),
.RX_SG_BUF_RECVD (wChnlSgRxBufRecvd),
.RX_TXN_DONE (wChnlRxDone),
.TX_TXN (wChnlTxRequest),
.TX_SG_BUF_RECVD (wChnlSgTxBufRecvd),
.TX_TXN_DONE (wChnlTxDone),
.VECT_0_RST (wIntrVectorReady[0]),
.VECT_1_RST (wIntrVectorReady[1]),
.VECT_RST (_wTxcData[31:0]),
.VECT_0 (wIntrVector[31:0]),
.VECT_1 (wIntrVector[63:32]),
.INTR_LEGACY_CLR (1'd0),
/*AUTOINST*/
// Outputs
.INTR_MSI_REQUEST (INTR_MSI_REQUEST),
// Inputs
.CLK (CLK),
.CONFIG_INTERRUPT_MSIENABLE (CONFIG_INTERRUPT_MSIENABLE),
.INTR_MSI_RDY (INTR_MSI_RDY));
tx_multiplexer
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_NUM_CHNL (C_NUM_CHNL),
.C_TAG_WIDTH (C_TAG_WIDTH),
.C_VENDOR (C_VENDOR),
.C_DEPTH_PACKETS (C_DEPTH_PACKETS))
tx_mux_inst
(
// Outputs
.WR_DATA_REN (wTxEngWrDataRen[C_NUM_CHNL-1:0]),
.WR_ACK (wTxEngWrAck[C_NUM_CHNL-1:0]),
.RD_ACK (wTxEngRdAck[C_NUM_CHNL-1:0]),
.INT_TAG (wInternalTag[5:0]),
.INT_TAG_VALID (wInternalTagValid),
.TX_ENG_RD_REQ_SENT (wTxEngRdReqSent),
// Inputs
.RST_IN (RST_OUT),
.WR_REQ (wTxEngWrReq[C_NUM_CHNL-1:0]),
.WR_ADDR (wTxEngWrAddr[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
.WR_LEN (wTxEngWrLen[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
.WR_DATA (wTxEngWrData[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.WR_SENT (wTxEngWrSent[C_NUM_CHNL-1:0]),
.RD_REQ (wTxEngRdReq[C_NUM_CHNL-1:0]),
.RD_SG_CHNL (wTxEngRdSgChnl[(C_NUM_CHNL*2)-1:0]),
.RD_ADDR (wTxEngRdAddr[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
.RD_LEN (wTxEngRdLen[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
.EXT_TAG (wExternalTag[C_TAG_WIDTH-1:0]),
.EXT_TAG_VALID (wExternalTagValid),
.RXBUF_SPACE_AVAIL (wRxBufSpaceAvail),
/*AUTOINST*/
// Outputs
.TXR_DATA_VALID (TXR_DATA_VALID),
.TXR_DATA (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (TXR_DATA_START_FLAG),
.TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (TXR_DATA_END_FLAG),
.TXR_DATA_END_OFFSET (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (TXR_META_VALID),
.TXR_META_FDWBE (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
.TXR_META_TAG (TXR_META_TAG[`SIG_TAG_W-1:0]),
.TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]),
.TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
.TXR_META_EP (TXR_META_EP),
// Inputs
.CLK (CLK),
.TXR_DATA_READY (TXR_DATA_READY),
.TXR_META_READY (TXR_META_READY),
.TXR_SENT (TXR_SENT));
// Generate and link up the channels.
generate
for (i = 0; i < C_NUM_CHNL; i = i + 1) begin : channels
channel
#(
.C_DATA_WIDTH(C_PCI_DATA_WIDTH),
.C_MAX_READ_REQ(C_MAX_READ_REQ)
)
channel
(
.RST(RST_OUT),
.CLK(CLK),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.PIO_DATA(wChnlReqData),
.ENG_DATA(wRxEngData),
.SG_RX_BUF_RECVD(wChnlSgRxBufRecvd[i]),
.SG_TX_BUF_RECVD(wChnlSgTxBufRecvd[i]),
.TXN_TX(wChnlTxRequest[i]),
.TXN_TX_DONE(wChnlTxDone[i]),
.TXN_RX_DONE(wChnlRxDone[i]),
.SG_RX_BUF_LEN_VALID(wChnlSgRxLenValid[i]),
.SG_RX_BUF_ADDR_HI_VALID(wChnlSgRxAddrHiValid[i]),
.SG_RX_BUF_ADDR_LO_VALID(wChnlSgRxAddrLoValid[i]),
.SG_TX_BUF_LEN_VALID(wChnlSgTxLenValid[i]),
.SG_TX_BUF_ADDR_HI_VALID(wChnlSgTxAddrHiValid[i]),
.SG_TX_BUF_ADDR_LO_VALID(wChnlSgTxAddrLoValid[i]),
.TXN_RX_LEN_VALID(wChnlRxLenValid[i]),
.TXN_RX_OFF_LAST_VALID(wChnlRxOfflastValid[i]),
.TXN_RX_DONE_LEN(wChnlRxDoneLen[(`SIG_RXDONELEN_W*i) +: `SIG_RXDONELEN_W]),
.TXN_RX_DONE_ACK(wChnlRxDoneReady[i]),
.TXN_TX_ACK(wChnlTxLenReady[i]), // ACK'd on length read
.TXN_TX_LEN(wChnlTxReqLen[(`SIG_TXRLEN_W*i) +: `SIG_TXRLEN_W]),
.TXN_TX_OFF_LAST(wChnlTxOfflast[(`SIG_OFFLAST_W*i) +: `SIG_OFFLAST_W]),
.TXN_TX_DONE_LEN(wChnlTxDoneLen[(`SIG_TXDONELEN_W*i) +:`SIG_TXDONELEN_W]),
.TXN_TX_DONE_ACK(wChnlTxDoneReady[i]),
.RX_REQ(wTxEngRdReq[i]),
.RX_REQ_ACK(wTxEngRdAck[i]),
.RX_REQ_TAG(wTxEngRdSgChnl[(2*i) +:2]),// TODO: `SIG_INTERNALTAG_W
.RX_REQ_ADDR(wTxEngRdAddr[(`SIG_ADDR_W*i) +:`SIG_ADDR_W]),
.RX_REQ_LEN(wTxEngRdLen[(`SIG_LEN_W*i) +:`SIG_LEN_W]),
.TX_REQ(wTxEngWrReq[i]),
.TX_REQ_ACK(wTxEngWrAck[i]),
.TX_ADDR(wTxEngWrAddr[(`SIG_ADDR_W*i) +: `SIG_ADDR_W]),
.TX_LEN(wTxEngWrLen[(`SIG_LEN_W*i) +: `SIG_LEN_W]),
.TX_DATA(wTxEngWrData[(C_PCI_DATA_WIDTH*i) +:C_PCI_DATA_WIDTH]),
.TX_DATA_REN(wTxEngWrDataRen[i]),
.TX_SENT(wTxEngWrSent[i]),
.MAIN_DATA_EN(wRxEngMainDataEn[(C_PCI_DATA_WORD_WIDTH*i) +:C_PCI_DATA_WORD_WIDTH]),
.MAIN_DONE(wRxEngMainDone[i]),
.MAIN_ERR(wRxEngMainErr[i]),
.SG_RX_DATA_EN(wRxEngSgRxDataEn[(C_PCI_DATA_WORD_WIDTH*i) +:C_PCI_DATA_WORD_WIDTH]),
.SG_RX_DONE(wRxEngSgRxDone[i]),
.SG_RX_ERR(wRxEngSgRxErr[i]),
.SG_TX_DATA_EN(wRxEngSgTxDataEn[(C_PCI_DATA_WORD_WIDTH*i) +:C_PCI_DATA_WORD_WIDTH]),
.SG_TX_DONE(wRxEngSgTxDone[i]),
.SG_TX_ERR(wRxEngSgTxErr[i]),
.CHNL_RX_CLK(CHNL_RX_CLK[i]),
.CHNL_RX(CHNL_RX[i]),
.CHNL_RX_ACK(CHNL_RX_ACK[i]),
.CHNL_RX_LAST(CHNL_RX_LAST[i]),
.CHNL_RX_LEN(CHNL_RX_LEN[(32*i) +:32]),
.CHNL_RX_OFF(CHNL_RX_OFF[(31*i) +:31]),
.CHNL_RX_DATA(CHNL_RX_DATA[(C_PCI_DATA_WIDTH*i) +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID[i]),
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN[i]),
.CHNL_TX_CLK(CHNL_TX_CLK[i]),
.CHNL_TX(CHNL_TX[i]),
.CHNL_TX_ACK(CHNL_TX_ACK[i]),
.CHNL_TX_LAST(CHNL_TX_LAST[i]),
.CHNL_TX_LEN(CHNL_TX_LEN[(32*i) +:32]),
.CHNL_TX_OFF(CHNL_TX_OFF[(31*i) +:31]),
.CHNL_TX_DATA(CHNL_TX_DATA[(C_PCI_DATA_WIDTH*i) +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID[i]),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN[i])
);
end
endgenerate
endmodule
// Local Variables:
// verilog-library-directories:("." "registers/" "import")
// End:
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 100MHz LVDS
*/
input wire clk_100mhz_p,
input wire clk_100mhz_n,
/*
* GPIO
*/
output wire [1:0] sfp_1_led,
output wire [1:0] sfp_2_led,
output wire [1:0] sma_led,
/*
* Ethernet: SFP+
*/
input wire sfp_1_rx_p,
input wire sfp_1_rx_n,
output wire sfp_1_tx_p,
output wire sfp_1_tx_n,
input wire sfp_2_rx_p,
input wire sfp_2_rx_n,
output wire sfp_2_tx_p,
output wire sfp_2_tx_n,
input wire sfp_mgt_refclk_p,
input wire sfp_mgt_refclk_n,
output wire sfp_1_tx_disable,
output wire sfp_2_tx_disable,
input wire sfp_1_npres,
input wire sfp_2_npres,
input wire sfp_1_los,
input wire sfp_2_los,
output wire sfp_1_rs,
output wire sfp_2_rs
);
// Clock and reset
wire clk_100mhz_ibufg;
// Internal 125 MHz clock
wire clk_125mhz_mmcm_out;
wire clk_125mhz_int;
wire rst_125mhz_int;
// Internal 156.25 MHz clock
wire clk_156mhz_int;
wire rst_156mhz_int;
wire mmcm_rst = 1'b0;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFGDS #(
.DIFF_TERM("FALSE"),
.IBUF_LOW_PWR("FALSE")
)
clk_100mhz_ibufg_inst (
.O (clk_100mhz_ibufg),
.I (clk_100mhz_p),
.IB (clk_100mhz_n)
);
// MMCM instance
// 100 MHz in, 125 MHz out
// PFD range: 10 MHz to 500 MHz
// VCO range: 600 MHz to 1440 MHz
// M = 10, D = 1 sets Fvco = 1000 MHz (in range)
// Divide by 8 to get output frequency of 125 MHz
MMCME3_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(8),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(10),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(10.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_100mhz_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_125mhz_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_125mhz_bufg_inst (
.I(clk_125mhz_mmcm_out),
.O(clk_125mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.out(rst_125mhz_int)
);
// GPIO
wire [1:0] sfp_1_led_int;
wire [1:0] sfp_2_led_int;
wire [1:0] sma_led_int;
// XGMII 10G PHY
assign sfp_1_tx_disable = 1'b0;
assign sfp_2_tx_disable = 1'b0;
assign sfp_1_rs = 1'b1;
assign sfp_2_rs = 1'b1;
wire sfp_1_tx_clk_int;
wire sfp_1_tx_rst_int;
wire [63:0] sfp_1_txd_int;
wire [7:0] sfp_1_txc_int;
wire sfp_1_rx_clk_int;
wire sfp_1_rx_rst_int;
wire [63:0] sfp_1_rxd_int;
wire [7:0] sfp_1_rxc_int;
wire sfp_2_tx_clk_int;
wire sfp_2_tx_rst_int;
wire [63:0] sfp_2_txd_int;
wire [7:0] sfp_2_txc_int;
wire sfp_2_rx_clk_int;
wire sfp_2_rx_rst_int;
wire [63:0] sfp_2_rxd_int;
wire [7:0] sfp_2_rxc_int;
wire sfp_1_rx_block_lock;
wire sfp_2_rx_block_lock;
wire sfp_mgt_refclk;
wire [1:0] gt_txclkout;
wire gt_txusrclk;
wire gt_txusrclk2;
wire [1:0] gt_rxclkout;
wire [1:0] gt_rxusrclk;
wire [1:0] gt_rxusrclk2;
wire gt_reset_tx_done;
wire gt_reset_rx_done;
wire [1:0] gt_txprgdivresetdone;
wire [1:0] gt_txpmaresetdone;
wire [1:0] gt_rxprgdivresetdone;
wire [1:0] gt_rxpmaresetdone;
wire gt_tx_reset = ~((>_txprgdivresetdone) & (>_txpmaresetdone));
wire gt_rx_reset = ~>_rxpmaresetdone;
reg gt_userclk_tx_active = 1'b0;
reg [1:0] gt_userclk_rx_active = 1'b0;
IBUFDS_GTE3 ibufds_gte3_sfp_mgt_refclk_inst (
.I (sfp_mgt_refclk_p),
.IB (sfp_mgt_refclk_n),
.CEB (1'b0),
.O (sfp_mgt_refclk),
.ODIV2 ()
);
BUFG_GT bufg_gt_tx_usrclk_inst (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (gt_tx_reset),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (gt_txclkout[0]),
.O (gt_txusrclk)
);
BUFG_GT bufg_gt_tx_usrclk2_inst (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (gt_tx_reset),
.CLRMASK (1'b0),
.DIV (3'd1),
.I (gt_txclkout[0]),
.O (gt_txusrclk2)
);
assign clk_156mhz_int = gt_txusrclk2;
always @(posedge gt_txusrclk, posedge gt_tx_reset) begin
if (gt_tx_reset) begin
gt_userclk_tx_active <= 1'b0;
end else begin
gt_userclk_tx_active <= 1'b1;
end
end
genvar n;
generate
for (n = 0 ; n < 2; n = n + 1) begin
BUFG_GT bufg_gt_rx_usrclk_0_inst (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (gt_rx_reset),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (gt_rxclkout[n]),
.O (gt_rxusrclk[n])
);
BUFG_GT bufg_gt_rx_usrclk2_0_inst (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (gt_rx_reset),
.CLRMASK (1'b0),
.DIV (3'd1),
.I (gt_rxclkout[n]),
.O (gt_rxusrclk2[n])
);
always @(posedge gt_rxusrclk[n], posedge gt_rx_reset) begin
if (gt_rx_reset) begin
gt_userclk_rx_active[n] <= 1'b0;
end else begin
gt_userclk_rx_active[n] <= 1'b1;
end
end
end
endgenerate
sync_reset #(
.N(4)
)
sync_reset_156mhz_inst (
.clk(clk_156mhz_int),
.rst(~gt_reset_tx_done),
.out(rst_156mhz_int)
);
wire [5:0] sfp_1_gt_txheader;
wire [63:0] sfp_1_gt_txdata;
wire sfp_1_gt_rxgearboxslip;
wire [5:0] sfp_1_gt_rxheader;
wire [1:0] sfp_1_gt_rxheadervalid;
wire [63:0] sfp_1_gt_rxdata;
wire [1:0] sfp_1_gt_rxdatavalid;
wire [5:0] sfp_2_gt_txheader;
wire [63:0] sfp_2_gt_txdata;
wire sfp_2_gt_rxgearboxslip;
wire [5:0] sfp_2_gt_rxheader;
wire [1:0] sfp_2_gt_rxheadervalid;
wire [63:0] sfp_2_gt_rxdata;
wire [1:0] sfp_2_gt_rxdatavalid;
gtwizard_ultrascale_0
sfp_gth_inst (
.gtwiz_userclk_tx_active_in(>_userclk_tx_active),
.gtwiz_userclk_rx_active_in(>_userclk_rx_active),
.gtwiz_reset_clk_freerun_in(clk_125mhz_int),
.gtwiz_reset_all_in(rst_125mhz_int),
.gtwiz_reset_tx_pll_and_datapath_in(1'b0),
.gtwiz_reset_tx_datapath_in(1'b0),
.gtwiz_reset_rx_pll_and_datapath_in(1'b0),
.gtwiz_reset_rx_datapath_in(1'b0),
.gtwiz_reset_rx_cdr_stable_out(),
.gtwiz_reset_tx_done_out(gt_reset_tx_done),
.gtwiz_reset_rx_done_out(gt_reset_rx_done),
.gtrefclk00_in(sfp_mgt_refclk),
.qpll0outclk_out(),
.qpll0outrefclk_out(),
.gthrxn_in({sfp_2_rx_n, sfp_1_rx_n}),
.gthrxp_in({sfp_2_rx_p, sfp_1_rx_p}),
.rxusrclk_in(gt_rxusrclk),
.rxusrclk2_in(gt_rxusrclk2),
.gtwiz_userdata_tx_in({sfp_2_gt_txdata, sfp_1_gt_txdata}),
.txheader_in({sfp_2_gt_txheader, sfp_1_gt_txheader}),
.txsequence_in({2{7'b0}}),
.txusrclk_in({2{gt_txusrclk}}),
.txusrclk2_in({2{gt_txusrclk2}}),
.gtpowergood_out(),
.gthtxn_out({sfp_2_tx_n, sfp_1_tx_n}),
.gthtxp_out({sfp_2_tx_p, sfp_1_tx_p}),
.txpolarity_in(2'b11),
.rxpolarity_in(2'b00),
.rxgearboxslip_in({sfp_2_gt_rxgearboxslip, sfp_1_gt_rxgearboxslip}),
.gtwiz_userdata_rx_out({sfp_2_gt_rxdata, sfp_1_gt_rxdata}),
.rxdatavalid_out({sfp_2_gt_rxdatavalid, sfp_1_gt_rxdatavalid}),
.rxheader_out({sfp_2_gt_rxheader, sfp_1_gt_rxheader}),
.rxheadervalid_out({sfp_2_gt_rxheadervalid, sfp_1_gt_rxheadervalid}),
.rxoutclk_out(gt_rxclkout),
.rxpmaresetdone_out(gt_rxpmaresetdone),
.rxprgdivresetdone_out(gt_rxprgdivresetdone),
.rxstartofseq_out(),
.txoutclk_out(gt_txclkout),
.txpmaresetdone_out(gt_txpmaresetdone),
.txprgdivresetdone_out(gt_txprgdivresetdone)
);
assign sfp_1_tx_clk_int = clk_156mhz_int;
assign sfp_1_tx_rst_int = rst_156mhz_int;
assign sfp_1_rx_clk_int = gt_rxusrclk2[0];
sync_reset #(
.N(4)
)
sfp_1_rx_rst_reset_sync_inst (
.clk(sfp_1_rx_clk_int),
.rst(~gt_reset_rx_done),
.out(sfp_1_rx_rst_int)
);
eth_phy_10g #(
.BIT_REVERSE(1)
)
sfp_1_phy_inst (
.tx_clk(sfp_1_tx_clk_int),
.tx_rst(sfp_1_tx_rst_int),
.rx_clk(sfp_1_rx_clk_int),
.rx_rst(sfp_1_rx_rst_int),
.xgmii_txd(sfp_1_txd_int),
.xgmii_txc(sfp_1_txc_int),
.xgmii_rxd(sfp_1_rxd_int),
.xgmii_rxc(sfp_1_rxc_int),
.serdes_tx_data(sfp_1_gt_txdata),
.serdes_tx_hdr(sfp_1_gt_txheader),
.serdes_rx_data(sfp_1_gt_rxdata),
.serdes_rx_hdr(sfp_1_gt_rxheader),
.serdes_rx_bitslip(sfp_1_gt_rxgearboxslip),
.rx_block_lock(sfp_1_rx_block_lock),
.rx_high_ber()
);
assign sfp_2_tx_clk_int = clk_156mhz_int;
assign sfp_2_tx_rst_int = rst_156mhz_int;
assign sfp_2_rx_clk_int = gt_rxusrclk2[1];
sync_reset #(
.N(4)
)
sfp_2_rx_rst_reset_sync_inst (
.clk(sfp_2_rx_clk_int),
.rst(~gt_reset_rx_done),
.out(sfp_2_rx_rst_int)
);
eth_phy_10g #(
.BIT_REVERSE(1)
)
sfp_2_phy_inst (
.tx_clk(sfp_2_tx_clk_int),
.tx_rst(sfp_2_tx_rst_int),
.rx_clk(sfp_2_rx_clk_int),
.rx_rst(sfp_2_rx_rst_int),
.xgmii_txd(sfp_2_txd_int),
.xgmii_txc(sfp_2_txc_int),
.xgmii_rxd(sfp_2_rxd_int),
.xgmii_rxc(sfp_2_rxc_int),
.serdes_tx_data(sfp_2_gt_txdata),
.serdes_tx_hdr(sfp_2_gt_txheader),
.serdes_rx_data(sfp_2_gt_rxdata),
.serdes_rx_hdr(sfp_2_gt_rxheader),
.serdes_rx_bitslip(sfp_2_gt_rxgearboxslip),
.rx_block_lock(sfp_2_rx_block_lock),
.rx_high_ber()
);
assign sfp_1_led[0] = sfp_1_rx_block_lock;
assign sfp_1_led[1] = 1'b0;
assign sfp_2_led[0] = sfp_2_rx_block_lock;
assign sfp_2_led[1] = 1'b0;
assign sma_led = sma_led_int;
fpga_core
core_inst (
/*
* Clock: 156.25 MHz
* Synchronous reset
*/
.clk(clk_156mhz_int),
.rst(rst_156mhz_int),
/*
* GPIO
*/
.sfp_1_led(sfp_1_led_int),
.sfp_2_led(sfp_2_led_int),
.sma_led(sma_led_int),
/*
* Ethernet: SFP+
*/
.sfp_1_tx_clk(sfp_1_tx_clk_int),
.sfp_1_tx_rst(sfp_1_tx_rst_int),
.sfp_1_txd(sfp_1_txd_int),
.sfp_1_txc(sfp_1_txc_int),
.sfp_1_rx_clk(sfp_1_rx_clk_int),
.sfp_1_rx_rst(sfp_1_rx_rst_int),
.sfp_1_rxd(sfp_1_rxd_int),
.sfp_1_rxc(sfp_1_rxc_int),
.sfp_2_tx_clk(sfp_2_tx_clk_int),
.sfp_2_tx_rst(sfp_2_tx_rst_int),
.sfp_2_txd(sfp_2_txd_int),
.sfp_2_txc(sfp_2_txc_int),
.sfp_2_rx_clk(sfp_2_rx_clk_int),
.sfp_2_rx_rst(sfp_2_rx_rst_int),
.sfp_2_rxd(sfp_2_rxd_int),
.sfp_2_rxc(sfp_2_rxc_int)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFSTP_PP_SYMBOL_V
`define SKY130_FD_SC_HD__DFSTP_PP_SYMBOL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfstp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFSTP_PP_SYMBOL_V
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerperipheralhdladi_pcore_dut.v
// Created: 2014-09-08 14:12:15
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerperipheralhdladi_pcore_dut
// Source Path: controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore_dut
// Hierarchy Level: 1
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerperipheralhdladi_pcore_dut
(
CLK_IN,
reset,
dut_enable,
adc_current1,
adc_current2,
encoder_a,
encoder_b,
encoder_index,
axi_controller_mode,
axi_command,
axi_velocity_p_gain,
axi_velocity_i_gain,
axi_current_p_gain,
axi_current_i_gain,
axi_open_loop_bias,
axi_open_loop_scalar,
axi_encoder_zero_offset,
ce_out_0,
ce_out_1,
pwm_a,
pwm_b,
pwm_c,
mon_phase_voltage_a,
mon_phase_voltage_b,
mon_phase_current_a,
mon_phase_current_b,
mon_rotor_position,
mon_electrical_position,
mon_rotor_velocity,
mon_d_current,
mon_q_current,
axi_electrical_pos_err
);
input CLK_IN;
input reset;
input dut_enable; // ufix1
input signed [17:0] adc_current1; // sfix18_En17
input signed [17:0] adc_current2; // sfix18_En17
input encoder_a; // ufix1
input encoder_b; // ufix1
input encoder_index; // ufix1
input [1:0] axi_controller_mode; // ufix2
input signed [17:0] axi_command; // sfix18_En8
input signed [17:0] axi_velocity_p_gain; // sfix18_En16
input signed [17:0] axi_velocity_i_gain; // sfix18_En15
input signed [17:0] axi_current_p_gain; // sfix18_En10
input signed [17:0] axi_current_i_gain; // sfix18_En2
input signed [17:0] axi_open_loop_bias; // sfix18_En14
input signed [17:0] axi_open_loop_scalar; // sfix18_En16
input signed [17:0] axi_encoder_zero_offset; // sfix18_En14
output ce_out_0; // ufix1
output ce_out_1; // ufix1
output pwm_a; // ufix1
output pwm_b; // ufix1
output pwm_c; // ufix1
output signed [31:0] mon_phase_voltage_a; // sfix32
output signed [31:0] mon_phase_voltage_b; // sfix32
output signed [31:0] mon_phase_current_a; // sfix32
output signed [31:0] mon_phase_current_b; // sfix32
output signed [31:0] mon_rotor_position; // sfix32
output signed [31:0] mon_electrical_position; // sfix32
output signed [31:0] mon_rotor_velocity; // sfix32
output signed [31:0] mon_d_current; // sfix32
output signed [31:0] mon_q_current; // sfix32
output signed [18:0] axi_electrical_pos_err; // sfix19_En14
wire enb;
wire ce_out_0_sig; // ufix1
wire ce_out_1_sig; // ufix1
wire pwm_a_sig; // ufix1
wire pwm_b_sig; // ufix1
wire pwm_c_sig; // ufix1
wire signed [31:0] mon_phase_voltage_a_sig; // sfix32
wire signed [31:0] mon_phase_voltage_b_sig; // sfix32
wire signed [31:0] mon_phase_current_a_sig; // sfix32
wire signed [31:0] mon_phase_current_b_sig; // sfix32
wire signed [31:0] mon_rotor_position_sig; // sfix32
wire signed [31:0] mon_electrical_position_sig; // sfix32
wire signed [31:0] mon_rotor_velocity_sig; // sfix32
wire signed [31:0] mon_d_current_sig; // sfix32
wire signed [31:0] mon_q_current_sig; // sfix32
wire signed [18:0] axi_electrical_pos_err_sig; // sfix19_En14
assign enb = dut_enable;
controllerPeripheralHdlAdi u_controllerPeripheralHdlAdi (.CLK_IN(CLK_IN),
.clk_enable(enb),
.reset(reset),
.adc_current1(adc_current1), // sfix18_En17
.adc_current2(adc_current2), // sfix18_En17
.encoder_a(encoder_a), // ufix1
.encoder_b(encoder_b), // ufix1
.encoder_index(encoder_index), // ufix1
.axi_controller_mode(axi_controller_mode), // ufix2
.axi_command(axi_command), // sfix18_En8
.axi_velocity_p_gain(axi_velocity_p_gain), // sfix18_En16
.axi_velocity_i_gain(axi_velocity_i_gain), // sfix18_En15
.axi_current_p_gain(axi_current_p_gain), // sfix18_En10
.axi_current_i_gain(axi_current_i_gain), // sfix18_En2
.axi_open_loop_bias(axi_open_loop_bias), // sfix18_En14
.axi_open_loop_scalar(axi_open_loop_scalar), // sfix18_En16
.axi_encoder_zero_offset(axi_encoder_zero_offset), // sfix18_En14
.ce_out_0(ce_out_0_sig), // ufix1
.ce_out_1(ce_out_1_sig), // ufix1
.pwm_a(pwm_a_sig), // ufix1
.pwm_b(pwm_b_sig), // ufix1
.pwm_c(pwm_c_sig), // ufix1
.mon_phase_voltage_a(mon_phase_voltage_a_sig), // sfix32
.mon_phase_voltage_b(mon_phase_voltage_b_sig), // sfix32
.mon_phase_current_a(mon_phase_current_a_sig), // sfix32
.mon_phase_current_b(mon_phase_current_b_sig), // sfix32
.mon_rotor_position(mon_rotor_position_sig), // sfix32
.mon_electrical_position(mon_electrical_position_sig), // sfix32
.mon_rotor_velocity(mon_rotor_velocity_sig), // sfix32
.mon_d_current(mon_d_current_sig), // sfix32
.mon_q_current(mon_q_current_sig), // sfix32
.axi_electrical_pos_err(axi_electrical_pos_err_sig) // sfix19_En14
);
assign ce_out_0 = ce_out_0_sig;
assign ce_out_1 = ce_out_1_sig;
assign pwm_a = pwm_a_sig;
assign pwm_b = pwm_b_sig;
assign pwm_c = pwm_c_sig;
assign mon_phase_voltage_a = mon_phase_voltage_a_sig;
assign mon_phase_voltage_b = mon_phase_voltage_b_sig;
assign mon_phase_current_a = mon_phase_current_a_sig;
assign mon_phase_current_b = mon_phase_current_b_sig;
assign mon_rotor_position = mon_rotor_position_sig;
assign mon_electrical_position = mon_electrical_position_sig;
assign mon_rotor_velocity = mon_rotor_velocity_sig;
assign mon_d_current = mon_d_current_sig;
assign mon_q_current = mon_q_current_sig;
assign axi_electrical_pos_err = axi_electrical_pos_err_sig;
endmodule // controllerperipheralhdladi_pcore_dut
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t_inst(/*AUTOARG*/
// Outputs
passed,
// Inputs
clk, fastclk
);
input clk;
input fastclk;
output passed; reg passed; initial passed = 0;
genvar unused;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire o_com; // From b of t_inst_b.v
wire o_seq_d1r; // From b of t_inst_b.v
// End of automatics
integer _mode; // initial _mode=0
reg na,nb,nc,nd,ne;
wire ma,mb,mc,md,me;
wire da,db,dc,dd,de;
reg [7:0] wa,wb,wc,wd,we;
wire [7:0] qa,qb,qc,qd,qe;
wire [5:0] ra;
wire [4:0] rb;
wire [29:0] rc;
wire [63:0] rd;
reg [5:0] sa;
reg [4:0] sb;
reg [29:0] sc;
reg [63:0] sd;
reg _guard1; initial _guard1=0;
wire [104:0] r_wide = {ra,rb,rc,rd};
reg _guard2; initial _guard2=0;
wire [98:0] r_wide0 = {rb,rc,rd};
reg _guard3; initial _guard3=0;
wire [93:0] r_wide1 = {rc,rd};
reg _guard4; initial _guard4=0;
wire [63:0] r_wide2 = {rd};
reg _guard5; initial _guard5=0;
wire [168:0] r_wide3 = {ra,rb,rc,rd,rd};
reg [127:0] _guard6; initial _guard6=0;
t_inst_a a (
.clk (clk),
// Outputs
.o_w5 ({ma,mb,mc,md,me}),
.o_w5_d1r ({da,db,dc,dd,de}),
.o_w40 ({qa,qb,qc,qd,qe}),
.o_w104 ({ra,rb,rc,rd}),
// Inputs
.i_w5 ({na,nb,nc,nd,ne}),
.i_w40 ({wa,wb,wc,wd,we}),
.i_w104 ({sa,sb,sc,sd})
);
reg i_seq;
reg i_com;
wire [15:14] o2_comhigh;
t_inst_b b (
.o2_com (o2_comhigh),
.i2_com ({i_com,~i_com}),
.wide_for_trace (128'h1234_5678_aaaa_bbbb_cccc_dddd),
.wide_for_trace_2 (_guard6 + 128'h1234_5678_aaaa_bbbb_cccc_dddd),
/*AUTOINST*/
// Outputs
.o_seq_d1r (o_seq_d1r),
.o_com (o_com),
// Inputs
.clk (clk),
.i_seq (i_seq),
.i_com (i_com));
// surefire lint_off STMINI
initial _mode = 0;
always @ (posedge fastclk) begin
if (_mode==1) begin
if (o_com !== ~i_com) $stop;
if (o2_comhigh !== {~i_com,i_com}) $stop;
end
end
always @ (posedge clk) begin
//$write("[%0t] t_inst: MODE = %0x NA=%x MA=%x DA=%x\n", $time, _mode,
// {na,nb,nc,nd,ne}, {ma,mb,mc,md,me}, {da,db,dc,dd,de});
$write("[%0t] t_inst: MODE = %0x IS=%x OS=%x\n", $time, _mode, i_seq, o_seq_d1r);
if (_mode==0) begin
$write("[%0t] t_inst: Running\n", $time);
_mode<=1;
{na,nb,nc,nd,ne} <= 5'b10110;
{wa,wb,wc,wd,we} <= {8'ha, 8'hb, 8'hc, 8'hd, 8'he};
{sa,sb,sc,sd} <= {6'hf, 5'h3, 30'h12345, 32'h0abc_abcd, 32'h7654_3210};
//
i_seq <= 1'b1;
i_com <= 1'b1;
end
else if (_mode==1) begin
_mode<=2;
if ({ma,mb,mc,md,me} !== 5'b10110) $stop;
if ({qa,qb,qc,qd,qe} !== {8'ha,8'hb,8'hc,8'hd,8'he}) $stop;
if ({sa,sb,sc,sd} !== {6'hf, 5'h3, 30'h12345, 32'h0abc_abcd, 32'h7654_3210}) $stop;
end
else if (_mode==2) begin
_mode<=3;
if ({da,db,dc,dd,de} !== 5'b10110) $stop;
if (o_seq_d1r !== ~i_seq) $stop;
//
$write("[%0t] t_inst: Passed\n", $time);
passed <= 1'b1;
end
if (|{_guard1,_guard2,_guard3,_guard4,_guard5,_guard6}) begin
$write("Guard error %x %x %x %x %x\n",_guard1,_guard2,_guard3,_guard4,_guard5);
$stop;
end
end
// surefire lint_off UDDSDN
wire _unused_ok = |{1'b1, r_wide0, r_wide1,r_wide2,r_wide3,r_wide};
endmodule
|
(** * ImpCEvalFun: Evaluation Function for Imp *)
(* $Date: 2013-07-01 18:48:47 -0400 (Mon, 01 Jul 2013) $ *)
(* #################################### *)
(** * Evaluation Function *)
Require Import Imp.
(** Here's a first try at an evaluation function for commands,
omitting [WHILE]. *)
Fixpoint ceval_step1 (st : state) (c : com) : state :=
match c with
| SKIP =>
st
| l ::= a1 =>
update st l (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_step1 st c1 in
ceval_step1 st' c2
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step1 st c1
else ceval_step1 st c2
| WHILE b1 DO c1 END =>
st (* bogus *)
end.
(** In a traditional functional programming language like ML or
Haskell we could write the WHILE case as follows:
<<
| WHILE b1 DO c1 END =>
if (beval st b1)
then ceval_step1 st (c1;; WHILE b1 DO c1 END)
else st
>>
Coq doesn't accept such a definition ([Error: Cannot guess
decreasing argument of fix]) because the function we want to
define is not guaranteed to terminate. Indeed, the changed
[ceval_step1] function applied to the [loop] program from [Imp.v] would
never terminate. Since Coq is not just a functional programming
language, but also a consistent logic, any potentially
non-terminating function needs to be rejected. Here is an
invalid(!) Coq program showing what would go wrong if Coq allowed
non-terminating recursive functions:
<<
Fixpoint loop_false (n : nat) : False := loop_false n.
>>
That is, propositions like [False] would become
provable (e.g. [loop_false 0] would be a proof of [False]), which
would be a disaster for Coq's logical consistency.
Thus, because it doesn't terminate on all inputs, the full version
of [ceval_step1] cannot be written in Coq -- at least not
without one additional trick... *)
(** Second try, using an extra numeric argument as a "step index" to
ensure that evaluation always terminates. *)
Fixpoint ceval_step2 (st : state) (c : com) (i : nat) : state :=
match i with
| O => empty_state
| S i' =>
match c with
| SKIP =>
st
| l ::= a1 =>
update st l (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_step2 st c1 i' in
ceval_step2 st' c2 i'
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step2 st c1 i'
else ceval_step2 st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then let st' := ceval_step2 st c1 i' in
ceval_step2 st' c i'
else st
end
end.
(** _Note_: It is tempting to think that the index [i] here is
counting the "number of steps of evaluation." But if you look
closely you'll see that this is not the case: for example, in the
rule for sequencing, the same [i] is passed to both recursive
calls. Understanding the exact way that [i] is treated will be
important in the proof of [ceval__ceval_step], which is given as
an exercise below. *)
(** Third try, returning an [option state] instead of just a [state]
so that we can distinguish between normal and abnormal
termination. *)
Fixpoint ceval_step3 (st : state) (c : com) (i : nat)
: option state :=
match i with
| O => None
| S i' =>
match c with
| SKIP =>
Some st
| l ::= a1 =>
Some (update st l (aeval st a1))
| c1 ;; c2 =>
match (ceval_step3 st c1 i') with
| Some st' => ceval_step3 st' c2 i'
| None => None
end
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step3 st c1 i'
else ceval_step3 st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then match (ceval_step3 st c1 i') with
| Some st' => ceval_step3 st' c i'
| None => None
end
else Some st
end
end.
(** We can improve the readability of this definition by introducing a
bit of auxiliary notation to hide the "plumbing" involved in
repeatedly matching against optional states. *)
Notation "'LETOPT' x <== e1 'IN' e2"
:= (match e1 with
| Some x => e2
| None => None
end)
(right associativity, at level 60).
Fixpoint ceval_step (st : state) (c : com) (i : nat)
: option state :=
match i with
| O => None
| S i' =>
match c with
| SKIP =>
Some st
| l ::= a1 =>
Some (update st l (aeval st a1))
| c1 ;; c2 =>
LETOPT st' <== ceval_step st c1 i' IN
ceval_step st' c2 i'
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step st c1 i'
else ceval_step st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then LETOPT st' <== ceval_step st c1 i' IN
ceval_step st' c i'
else Some st
end
end.
Definition test_ceval (st:state) (c:com) :=
match ceval_step st c 500 with
| None => None
| Some st => Some (st X, st Y, st Z)
end.
(* Eval compute in
(test_ceval empty_state
(X ::= ANum 2;;
IFB BLe (AId X) (ANum 1)
THEN Y ::= ANum 3
ELSE Z ::= ANum 4
FI)).
====>
Some (2, 0, 4) *)
(** **** Exercise: 2 stars (pup_to_n) *)
(** Write an Imp program that sums the numbers from [1] to
[X] (inclusive: [1 + 2 + ... + X]) in the variable [Y]. Make sure
your solution satisfies the test that follows. *)
Definition pup_to_n : com :=
(* FILL IN HERE *) admit.
(*
Example pup_to_n_1 :
test_ceval (update empty_state X 5) pup_to_n
= Some (0, 15, 0).
Proof. reflexivity. Qed.
*)
(** [] *)
(** **** Exercise: 2 stars, optional (peven) *)
(** Write a [While] program that sets [Z] to [0] if [X] is even and
sets [Z] to [1] otherwise. Use [ceval_test] to test your
program. *)
(* FILL IN HERE *)
(** [] *)
(* ################################################################ *)
(** * Equivalence of Relational and Step-Indexed Evaluation *)
(** As with arithmetic and boolean expressions, we'd hope that
the two alternative definitions of evaluation actually boil down
to the same thing. This section shows that this is the case.
Make sure you understand the statements of the theorems and can
follow the structure of the proofs. *)
Theorem ceval_step__ceval: forall c st st',
(exists i, ceval_step st c i = Some st') ->
c / st || st'.
Proof.
intros c st st' H.
inversion H as [i E].
clear H.
generalize dependent st'.
generalize dependent st.
generalize dependent c.
induction i as [| i' ].
Case "i = 0 -- contradictory".
intros c st st' H. inversion H.
Case "i = S i'".
intros c st st' H.
com_cases (destruct c) SCase;
simpl in H; inversion H; subst; clear H.
SCase "SKIP". apply E_Skip.
SCase "::=". apply E_Ass. reflexivity.
SCase ";;".
destruct (ceval_step st c1 i') eqn:Heqr1.
SSCase "Evaluation of r1 terminates normally".
apply E_Seq with s.
apply IHi'. rewrite Heqr1. reflexivity.
apply IHi'. simpl in H1. assumption.
SSCase "Otherwise -- contradiction".
inversion H1.
SCase "IFB".
destruct (beval st b) eqn:Heqr.
SSCase "r = true".
apply E_IfTrue. rewrite Heqr. reflexivity.
apply IHi'. assumption.
SSCase "r = false".
apply E_IfFalse. rewrite Heqr. reflexivity.
apply IHi'. assumption.
SCase "WHILE". destruct (beval st b) eqn :Heqr.
SSCase "r = true".
destruct (ceval_step st c i') eqn:Heqr1.
SSSCase "r1 = Some s".
apply E_WhileLoop with s. rewrite Heqr. reflexivity.
apply IHi'. rewrite Heqr1. reflexivity.
apply IHi'. simpl in H1. assumption.
SSSCase "r1 = None".
inversion H1.
SSCase "r = false".
inversion H1.
apply E_WhileEnd.
rewrite <- Heqr. subst. reflexivity. Qed.
(** **** Exercise: 4 stars (ceval_step__ceval_inf) *)
(** Write an informal proof of [ceval_step__ceval], following the
usual template. (The template for case analysis on an inductively
defined value should look the same as for induction, except that
there is no induction hypothesis.) Make your proof communicate
the main ideas to a human reader; do not simply transcribe the
steps of the formal proof.
(* FILL IN HERE *)
[]
*)
Theorem ceval_step_more: forall i1 i2 st st' c,
i1 <= i2 ->
ceval_step st c i1 = Some st' ->
ceval_step st c i2 = Some st'.
Proof.
induction i1 as [|i1']; intros i2 st st' c Hle Hceval.
Case "i1 = 0".
simpl in Hceval. inversion Hceval.
Case "i1 = S i1'".
destruct i2 as [|i2']. inversion Hle.
assert (Hle': i1' <= i2') by omega.
com_cases (destruct c) SCase.
SCase "SKIP".
simpl in Hceval. inversion Hceval.
reflexivity.
SCase "::=".
simpl in Hceval. inversion Hceval.
reflexivity.
SCase ";;".
simpl in Hceval. simpl.
destruct (ceval_step st c1 i1') eqn:Heqst1'o.
SSCase "st1'o = Some".
apply (IHi1' i2') in Heqst1'o; try assumption.
rewrite Heqst1'o. simpl. simpl in Hceval.
apply (IHi1' i2') in Hceval; try assumption.
SSCase "st1'o = None".
inversion Hceval.
SCase "IFB".
simpl in Hceval. simpl.
destruct (beval st b); apply (IHi1' i2') in Hceval; assumption.
SCase "WHILE".
simpl in Hceval. simpl.
destruct (beval st b); try assumption.
destruct (ceval_step st c i1') eqn: Heqst1'o.
SSCase "st1'o = Some".
apply (IHi1' i2') in Heqst1'o; try assumption.
rewrite -> Heqst1'o. simpl. simpl in Hceval.
apply (IHi1' i2') in Hceval; try assumption.
SSCase "i1'o = None".
simpl in Hceval. inversion Hceval. Qed.
(** **** Exercise: 3 stars (ceval__ceval_step) *)
(** Finish the following proof. You'll need [ceval_step_more] in a
few places, as well as some basic facts about [<=] and [plus]. *)
Theorem ceval__ceval_step: forall c st st',
c / st || st' ->
exists i, ceval_step st c i = Some st'.
Proof.
intros c st st' Hce.
ceval_cases (induction Hce) Case.
(* FILL IN HERE *) Admitted.
(** [] *)
Theorem ceval_and_ceval_step_coincide: forall c st st',
c / st || st'
<-> exists i, ceval_step st c i = Some st'.
Proof.
intros c st st'.
split. apply ceval__ceval_step. apply ceval_step__ceval.
Qed.
(* ####################################################### *)
(** * Determinism of Evaluation (Simpler Proof) *)
(** Here's a slicker proof showing that the evaluation relation is
deterministic, using the fact that the relational and step-indexed
definition of evaluation are the same. *)
Theorem ceval_deterministic' : forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 He1 He2.
apply ceval__ceval_step in He1.
apply ceval__ceval_step in He2.
inversion He1 as [i1 E1].
inversion He2 as [i2 E2].
apply ceval_step_more with (i2 := i1 + i2) in E1.
apply ceval_step_more with (i2 := i1 + i2) in E2.
rewrite E1 in E2. inversion E2. reflexivity.
omega. omega. Qed.
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYMETAL6S6S_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DLYMETAL6S6S_FUNCTIONAL_PP_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__dlymetal6s6s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYMETAL6S6S_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21AI_SYMBOL_V
`define SKY130_FD_SC_HDLL__O21AI_SYMBOL_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o21ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21AI_SYMBOL_V
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// ********************************************************************************************************************************
// File name: acv_hard_memphy.v
// This file instantiates all the main components of the PHY.
// ********************************************************************************************************************************
`timescale 1 ps / 1 ps
module hps_sdram_p0_acv_hard_memphy (
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,
afi_reset_n,
pll_locked,
oct_ctl_rs_value,
oct_ctl_rt_value,
afi_addr,
afi_ba,
afi_cke,
afi_cs_n,
afi_ras_n,
afi_we_n,
afi_cas_n,
afi_rst_n,
afi_odt,
afi_mem_clk_disable,
afi_dqs_burst,
afi_wdata_valid,
afi_wdata,
afi_dm,
afi_rdata,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata_valid,
afi_wlat,
afi_rlat,
afi_cal_success,
afi_cal_fail,
avl_read,
avl_write,
avl_address,
avl_writedata,
avl_waitrequest,
avl_readdata,
cfg_addlat,
cfg_bankaddrwidth,
cfg_caswrlat,
cfg_coladdrwidth,
cfg_csaddrwidth,
cfg_devicewidth,
cfg_dramconfig,
cfg_interfacewidth,
cfg_rowaddrwidth,
cfg_tcl,
cfg_tmrd,
cfg_trefi,
cfg_trfc,
cfg_twr,
io_intaddrdout,
io_intbadout,
io_intcasndout,
io_intckdout,
io_intckedout,
io_intckndout,
io_intcsndout,
io_intdmdout,
io_intdqdin,
io_intdqdout,
io_intdqoe,
io_intdqsbdout,
io_intdqsboe,
io_intdqsdout,
io_intdqslogicdqsena,
io_intdqslogicfiforeset,
io_intdqslogicincrdataen,
io_intdqslogicincwrptr,
io_intdqslogicoct,
io_intdqslogicrdatavalid,
io_intdqslogicreadlatency,
io_intdqsoe,
io_intodtdout,
io_intrasndout,
io_intresetndout,
io_intwendout,
io_intafirlat,
io_intafiwlat,
io_intaficalfail,
io_intaficalsuccess,
mem_a,
mem_ba,
mem_cs_n,
mem_cke,
mem_odt,
mem_we_n,
mem_ras_n,
mem_cas_n,
mem_reset_n,
mem_dq,
mem_dm,
mem_ck,
mem_ck_n,
mem_dqs,
mem_dqs_n,
reset_n_scc_clk,
reset_n_avl_clk,
scc_data,
scc_dqs_ena,
scc_dqs_io_ena,
scc_dq_ena,
scc_dm_ena,
scc_upd,
capture_strobe_tracking,
phy_clk,
ctl_clk,
phy_reset_n,
pll_afi_clk,
pll_afi_half_clk,
pll_addr_cmd_clk,
pll_mem_clk,
pll_mem_phy_clk,
pll_afi_phy_clk,
pll_avl_phy_clk,
pll_write_clk,
pll_write_clk_pre_phy_clk,
pll_dqs_ena_clk,
seq_clk,
pll_avl_clk,
pll_config_clk,
dll_clk,
dll_pll_locked,
dll_phy_delayctrl
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver
parameter DEVICE_FAMILY = "";
parameter IS_HHP_HPS = "false";
// On-chip termination
parameter OCT_SERIES_TERM_CONTROL_WIDTH = "";
parameter OCT_PARALLEL_TERM_CONTROL_WIDTH = "";
// PHY-Memory Interface
// Memory device specific parameters, they are set according to the memory spec
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_IF_CS_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_DQS_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
// PHY-Controller (AFI) Interface
// The AFI interface widths are derived from the memory interface widths based on full/half rate operations
// The calculations are done on higher level wrapper
// DLL Interface
// The DLL delay output control is always 6 bits for current existing devices
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter MR1_ODS = "";
parameter MR1_RTT = "";
parameter MR2_RTT_WR = "";
parameter TB_PROTOCOL = "";
parameter TB_MEM_CLK_FREQ = "";
parameter TB_RATE = "";
parameter TB_MEM_DQ_WIDTH = "";
parameter TB_MEM_DQS_WIDTH = "";
parameter TB_PLL_DLL_MASTER = "";
parameter FAST_SIM_MODEL = "";
parameter FAST_SIM_CALIBRATION = "";
// Width of the calibration status register used to control calibration skipping.
parameter CALIB_REG_WIDTH = "";
parameter AC_ROM_INIT_FILE_NAME = "";
parameter INST_ROM_INIT_FILE_NAME = "";
// The number of AFI Resets to generate
localparam NUM_AFI_RESET = 4;
// Addr/cmd clock phase
localparam ADC_PHASE_SETTING = 0;
localparam ADC_INVERT_PHASE = "true";
// END PARAMETER SECTION
// ********************************************************************************************************************************
// ********************************************************************************************************************************
// BEGIN PORT SECTION
// Reset Interface
input global_reset_n; // Resets (active-low) the whole system (all PHY logic + PLL)
input soft_reset_n; // Resets (active-low) PHY logic only, PLL is NOT reset
input pll_locked; // Indicates that PLL is locked
output ctl_reset_n; // Asynchronously asserted and synchronously de-asserted on ctl_clk domain
output ctl_reset_export_n; // Asynchronously asserted and synchronously de-asserted on ctl_clk domain
output afi_reset_n; // Asynchronously asserted and synchronously de-asserted on afi_clk domain
input [OCT_SERIES_TERM_CONTROL_WIDTH-1:0] oct_ctl_rs_value;
input [OCT_PARALLEL_TERM_CONTROL_WIDTH-1:0] oct_ctl_rt_value;
// PHY-Controller Interface, AFI 2.0
// Control Interface
input [19:0] afi_addr;
input [2:0] afi_ba;
input [1:0] afi_cke;
input [1:0] afi_cs_n;
input [0:0] afi_cas_n;
input [1:0] afi_odt;
input [0:0] afi_ras_n;
input [0:0] afi_we_n;
input [0:0] afi_rst_n;
input [0:0] afi_mem_clk_disable;
input [4:0] afi_dqs_burst;
output [3:0] afi_wlat;
output [4:0] afi_rlat;
// Write data interface
input [79:0] afi_wdata; // write data
input [4:0] afi_wdata_valid; // write data valid, used to maintain write latency required by protocol spec
input [9:0] afi_dm; // write data mask
// Read data interface
output [79:0] afi_rdata; // read data
input [4:0] afi_rdata_en; // read enable, used to maintain the read latency calibrated by PHY
input [4:0] afi_rdata_en_full; // read enable full burst, used to create DQS enable
output [0:0] afi_rdata_valid; // read data valid
// Status interface
output afi_cal_success; // calibration success
output afi_cal_fail; // calibration failure
// Avalon interface to the sequencer
input [15:0] avl_address; //MarkW TODO: the sequencer only uses 13 bits
input avl_read;
output [31:0] avl_readdata;
output avl_waitrequest;
input avl_write;
input [31:0] avl_writedata;
// Configuration interface to the memory controller
input [7:0] cfg_addlat;
input [7:0] cfg_bankaddrwidth;
input [7:0] cfg_caswrlat;
input [7:0] cfg_coladdrwidth;
input [7:0] cfg_csaddrwidth;
input [7:0] cfg_devicewidth;
input [23:0] cfg_dramconfig;
input [7:0] cfg_interfacewidth;
input [7:0] cfg_rowaddrwidth;
input [7:0] cfg_tcl;
input [7:0] cfg_tmrd;
input [15:0] cfg_trefi;
input [7:0] cfg_trfc;
input [7:0] cfg_twr;
// IO/bypass interface to the core (or soft controller)
input [63:0] io_intaddrdout;
input [11:0] io_intbadout;
input [3:0] io_intcasndout;
input [3:0] io_intckdout;
input [7:0] io_intckedout;
input [3:0] io_intckndout;
input [7:0] io_intcsndout;
input [19:0] io_intdmdout;
output [179:0] io_intdqdin;
input [179:0] io_intdqdout;
input [89:0] io_intdqoe;
input [19:0] io_intdqsbdout;
input [9:0] io_intdqsboe;
input [19:0] io_intdqsdout;
input [9:0] io_intdqslogicdqsena;
input [4:0] io_intdqslogicfiforeset;
input [9:0] io_intdqslogicincrdataen;
input [9:0] io_intdqslogicincwrptr;
input [9:0] io_intdqslogicoct;
output [4:0] io_intdqslogicrdatavalid;
input [24:0] io_intdqslogicreadlatency;
input [9:0] io_intdqsoe;
input [7:0] io_intodtdout;
input [3:0] io_intrasndout;
input [3:0] io_intresetndout;
input [3:0] io_intwendout;
output [4:0] io_intafirlat;
output [3:0] io_intafiwlat;
output io_intaficalfail;
output io_intaficalsuccess;
// PHY-Memory Interface
output [MEM_ADDRESS_WIDTH-1:0] mem_a;
output [MEM_BANK_WIDTH-1:0] mem_ba;
output [MEM_IF_CS_WIDTH-1:0] mem_cs_n;
output [MEM_CLK_EN_WIDTH-1:0] mem_cke;
output [MEM_ODT_WIDTH-1:0] mem_odt;
output [MEM_CONTROL_WIDTH-1:0] mem_we_n;
output [MEM_CONTROL_WIDTH-1:0] mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] mem_cas_n;
output mem_reset_n;
inout [MEM_DQ_WIDTH-1:0] mem_dq;
output [MEM_DM_WIDTH-1:0] mem_dm;
output [MEM_CK_WIDTH-1:0] mem_ck;
output [MEM_CK_WIDTH-1:0] mem_ck_n;
inout [MEM_DQS_WIDTH-1:0] mem_dqs;
inout [MEM_DQS_WIDTH-1:0] mem_dqs_n;
output reset_n_scc_clk;
output reset_n_avl_clk;
// Scan chain configuration manager interface
input scc_data;
input [MEM_READ_DQS_WIDTH-1:0] scc_dqs_ena;
input [MEM_READ_DQS_WIDTH-1:0] scc_dqs_io_ena;
input [MEM_DQ_WIDTH-1:0] scc_dq_ena;
input [MEM_DM_WIDTH-1:0] scc_dm_ena;
input [0:0] scc_upd;
output [MEM_READ_DQS_WIDTH-1:0] capture_strobe_tracking;
output phy_clk;
output ctl_clk;
output phy_reset_n;
// PLL Interface
input pll_afi_clk; // clocks AFI interface logic
input pll_afi_half_clk; //
input pll_addr_cmd_clk; // clocks address/command DDIO
input pll_mem_clk; // output clock to memory
input pll_write_clk; // clocks write data DDIO
input pll_write_clk_pre_phy_clk;
input pll_dqs_ena_clk;
input seq_clk;
input pll_avl_clk;
input pll_config_clk;
input pll_mem_phy_clk;
input pll_afi_phy_clk;
input pll_avl_phy_clk;
// DLL Interface
output dll_clk;
output dll_pll_locked;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl; // dll output used to control the input DQS phase shift
// END PARAMETER SECTION
// ********************************************************************************************************************************
wire [179:0] ddio_phy_dqdin;
wire [4:0] ddio_phy_dqslogic_rdatavalid;
wire [63:0] phy_ddio_address;
wire [11:0] phy_ddio_bank;
wire [3:0] phy_ddio_cas_n;
wire [3:0] phy_ddio_ck;
wire [7:0] phy_ddio_cke;
wire [3:0] phy_ddio_ck_n;
wire [7:0] phy_ddio_cs_n;
wire [19:0] phy_ddio_dmdout;
wire [179:0] phy_ddio_dqdout;
wire [89:0] phy_ddio_dqoe;
wire [9:0] phy_ddio_dqsb_oe;
wire [9:0] phy_ddio_dqslogic_dqsena;
wire [4:0] phy_ddio_dqslogic_fiforeset;
wire [4:0] phy_ddio_dqslogic_aclr_pstamble;
wire [4:0] phy_ddio_dqslogic_aclr_fifoctrl;
wire [9:0] phy_ddio_dqslogic_incrdataen;
wire [9:0] phy_ddio_dqslogic_incwrptr;
wire [9:0] phy_ddio_dqslogic_oct;
wire [24:0] phy_ddio_dqslogic_readlatency;
wire [9:0] phy_ddio_dqs_oe;
wire [19:0] phy_ddio_dqs_dout;
wire [7:0] phy_ddio_odt;
wire [3:0] phy_ddio_ras_n;
wire [3:0] phy_ddio_reset_n;
wire [3:0] phy_ddio_we_n;
wire read_capture_clk;
wire [NUM_AFI_RESET-1:0] reset_n_afi_clk;
wire reset_n_addr_cmd_clk;
wire reset_n_seq_clk;
wire reset_n_scc_clk;
wire reset_n_avl_clk;
wire reset_n_resync_clk;
localparam SKIP_CALIBRATION_STEPS = 7'b1111111;
localparam CALIBRATION_STEPS = SKIP_CALIBRATION_STEPS;
localparam SKIP_MEM_INIT = 1'b1;
localparam SEQ_CALIB_INIT = {CALIBRATION_STEPS, SKIP_MEM_INIT};
generate
if (IS_HHP_HPS != "true") begin
reg [CALIB_REG_WIDTH-1:0] seq_calib_init_reg /* synthesis syn_noprune syn_preserve = 1 */;
// Initialization of the sequencer status register. This register
// is preserved in the netlist so that it can be forced during simulation
always @(posedge pll_afi_clk)
`ifdef SYNTH_FOR_SIM
`else
//synthesis translate_off
`endif
seq_calib_init_reg <= SEQ_CALIB_INIT;
`ifdef SYNTH_FOR_SIM
`else
//synthesis translate_on
//synthesis read_comments_as_HDL on
`endif
// seq_calib_init_reg <= {CALIB_REG_WIDTH{1'b0}};
`ifdef SYNTH_FOR_SIM
`else
// synthesis read_comments_as_HDL off
`endif
end
endgenerate
// ********************************************************************************************************************************
// The reset scheme used in the UNIPHY is asynchronous assert and synchronous de-assert
// The reset block has 2 main functionalities:
// 1. Keep all the PHY logic in reset state until after the PLL is locked
// 2. Synchronize the reset to each clock domain
// ********************************************************************************************************************************
generate
if (IS_HHP_HPS != "true") begin
hps_sdram_p0_reset ureset(
.pll_afi_clk (pll_afi_clk),
.pll_addr_cmd_clk (pll_addr_cmd_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.seq_clk (seq_clk),
.pll_avl_clk (pll_avl_clk),
.scc_clk (pll_config_clk),
.reset_n_scc_clk (reset_n_scc_clk),
.reset_n_avl_clk (reset_n_avl_clk),
.read_capture_clk (read_capture_clk),
.pll_locked (pll_locked),
.global_reset_n (global_reset_n),
.soft_reset_n (soft_reset_n),
.ctl_reset_export_n (ctl_reset_export_n),
.reset_n_afi_clk (reset_n_afi_clk),
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_seq_clk (reset_n_seq_clk),
.reset_n_resync_clk (reset_n_resync_clk)
);
defparam ureset.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam ureset.NUM_AFI_RESET = NUM_AFI_RESET;
end else begin
// synthesis translate_off
hps_sdram_p0_reset ureset(
.pll_afi_clk (pll_afi_clk),
.pll_addr_cmd_clk (pll_addr_cmd_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.seq_clk (seq_clk),
.pll_avl_clk (pll_avl_clk),
.scc_clk (pll_config_clk),
.reset_n_scc_clk (reset_n_scc_clk),
.reset_n_avl_clk (reset_n_avl_clk),
.read_capture_clk (read_capture_clk),
.pll_locked (pll_locked),
.global_reset_n (global_reset_n),
.soft_reset_n (soft_reset_n),
.ctl_reset_export_n (ctl_reset_export_n),
.reset_n_afi_clk (reset_n_afi_clk),
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_seq_clk (reset_n_seq_clk),
.reset_n_resync_clk (reset_n_resync_clk)
);
defparam ureset.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam ureset.NUM_AFI_RESET = NUM_AFI_RESET;
// synthesis translate_on
// synthesis read_comments_as_HDL on
// assign reset_n_afi_clk = {NUM_AFI_RESET{global_reset_n}};
// assign reset_n_addr_cmd_clk = global_reset_n;
// assign reset_n_avl_clk = global_reset_n;
// assign reset_n_scc_clk = global_reset_n;
// synthesis read_comments_as_HDL off
end
endgenerate
assign phy_clk = seq_clk;
assign phy_reset_n = reset_n_seq_clk;
assign dll_clk = pll_write_clk_pre_phy_clk;
assign dll_pll_locked = pll_locked;
// PHY clock and LDC
wire afi_clk;
wire avl_clk;
wire adc_clk;
wire adc_clk_cps;
hps_sdram_p0_acv_ldc # (
.DLL_DELAY_CTRL_WIDTH (DLL_DELAY_CTRL_WIDTH),
.ADC_PHASE_SETTING (ADC_PHASE_SETTING),
.ADC_INVERT_PHASE (ADC_INVERT_PHASE),
.IS_HHP_HPS (IS_HHP_HPS)
) memphy_ldc (
.pll_hr_clk (pll_avl_phy_clk),
.pll_dq_clk (pll_write_clk),
.pll_dqs_clk (pll_mem_phy_clk),
.dll_phy_delayctrl (dll_phy_delayctrl),
.afi_clk (afi_clk),
.avl_clk (avl_clk),
.adc_clk (adc_clk),
.adc_clk_cps (adc_clk_cps)
);
assign ctl_clk = afi_clk;
assign afi_reset_n = reset_n_afi_clk;
// ********************************************************************************************************************************
// This is the hard PHY instance
// ********************************************************************************************************************************
cyclonev_mem_phy hphy_inst (
.pllaficlk (afi_clk),
.pllavlclk (avl_clk),
.plllocked (pll_locked),
.plladdrcmdclk (adc_clk),
.globalresetn (global_reset_n),
.softresetn (soft_reset_n),
.phyresetn (phy_reset_n),
.ctlresetn (ctl_reset_n),
.iointaddrdout (io_intaddrdout),
.iointbadout (io_intbadout),
.iointcasndout (io_intcasndout),
.iointckdout (io_intckdout),
.iointckedout (io_intckedout),
.iointckndout (io_intckndout),
.iointcsndout (io_intcsndout),
.iointdmdout (io_intdmdout),
.iointdqdin (io_intdqdin),
.iointdqdout (io_intdqdout),
.iointdqoe (io_intdqoe),
.iointdqsbdout (io_intdqsbdout),
.iointdqsboe (io_intdqsboe),
.iointdqsdout (io_intdqsdout),
.iointdqslogicdqsena (io_intdqslogicdqsena),
.iointdqslogicfiforeset (io_intdqslogicfiforeset),
.iointdqslogicincrdataen (io_intdqslogicincrdataen),
.iointdqslogicincwrptr (io_intdqslogicincwrptr),
.iointdqslogicoct (io_intdqslogicoct),
.iointdqslogicrdatavalid (io_intdqslogicrdatavalid),
.iointdqslogicreadlatency (io_intdqslogicreadlatency),
.iointdqsoe (io_intdqsoe),
.iointodtdout (io_intodtdout),
.iointrasndout (io_intrasndout),
.iointresetndout (io_intresetndout),
.iointwendout (io_intwendout),
.iointafirlat (io_intafirlat),
.iointafiwlat (io_intafiwlat),
.iointaficalfail (io_intaficalfail),
.iointaficalsuccess (io_intaficalsuccess),
.ddiophydqdin (ddio_phy_dqdin),
.ddiophydqslogicrdatavalid (ddio_phy_dqslogic_rdatavalid),
.phyddioaddrdout (phy_ddio_address),
.phyddiobadout (phy_ddio_bank),
.phyddiocasndout (phy_ddio_cas_n),
.phyddiockdout (phy_ddio_ck),
.phyddiockedout (phy_ddio_cke),
.phyddiockndout (),
.phyddiocsndout (phy_ddio_cs_n),
.phyddiodmdout (phy_ddio_dmdout),
.phyddiodqdout (phy_ddio_dqdout),
.phyddiodqoe (phy_ddio_dqoe),
.phyddiodqsbdout (),
.phyddiodqsboe (phy_ddio_dqsb_oe),
.phyddiodqslogicdqsena (phy_ddio_dqslogic_dqsena),
.phyddiodqslogicfiforeset (phy_ddio_dqslogic_fiforeset),
.phyddiodqslogicaclrpstamble (phy_ddio_dqslogic_aclr_pstamble),
.phyddiodqslogicaclrfifoctrl (phy_ddio_dqslogic_aclr_fifoctrl),
.phyddiodqslogicincrdataen (phy_ddio_dqslogic_incrdataen),
.phyddiodqslogicincwrptr (phy_ddio_dqslogic_incwrptr),
.phyddiodqslogicoct (phy_ddio_dqslogic_oct),
.phyddiodqslogicreadlatency (phy_ddio_dqslogic_readlatency),
.phyddiodqsoe (phy_ddio_dqs_oe),
.phyddiodqsdout (phy_ddio_dqs_dout),
.phyddioodtdout (phy_ddio_odt),
.phyddiorasndout (phy_ddio_ras_n),
.phyddioresetndout (phy_ddio_reset_n),
.phyddiowendout (phy_ddio_we_n),
.afiaddr (afi_addr),
.afiba (afi_ba),
.aficalfail (afi_cal_fail),
.aficalsuccess (afi_cal_success),
.aficasn (afi_cas_n),
.aficke (afi_cke),
.aficsn (afi_cs_n),
.afidm (afi_dm),
.afidqsburst (afi_dqs_burst),
.afimemclkdisable (afi_mem_clk_disable),
.afiodt (afi_odt),
.afirasn (afi_ras_n),
.afirdata (afi_rdata),
.afirdataen (afi_rdata_en),
.afirdataenfull (afi_rdata_en_full),
.afirdatavalid (afi_rdata_valid),
.afirlat (afi_rlat),
.afirstn (afi_rst_n),
.afiwdata (afi_wdata),
.afiwdatavalid (afi_wdata_valid),
.afiwen (afi_we_n),
.afiwlat (afi_wlat),
.avladdress (avl_address),
.avlread (avl_read),
.avlreaddata (avl_readdata),
.avlresetn (reset_n_avl_clk),
.avlwaitrequest (avl_waitrequest),
.avlwrite (avl_write),
.avlwritedata (avl_writedata),
.cfgaddlat (cfg_addlat),
.cfgbankaddrwidth (cfg_bankaddrwidth),
.cfgcaswrlat (cfg_caswrlat),
.cfgcoladdrwidth (cfg_coladdrwidth),
.cfgcsaddrwidth (cfg_csaddrwidth),
.cfgdevicewidth (cfg_devicewidth),
.cfgdramconfig (cfg_dramconfig),
.cfginterfacewidth (cfg_interfacewidth),
.cfgrowaddrwidth (cfg_rowaddrwidth),
.cfgtcl (cfg_tcl),
.cfgtmrd (cfg_tmrd),
.cfgtrefi (cfg_trefi),
.cfgtrfc (cfg_trfc),
.cfgtwr (cfg_twr),
.scanen ()
);
defparam hphy_inst.hphy_ac_ddr_disable = "true";
defparam hphy_inst.hphy_datapath_delay = "one_cycle";
defparam hphy_inst.hphy_datapath_ac_delay = "one_and_half_cycles";
defparam hphy_inst.hphy_reset_delay_en = "false";
defparam hphy_inst.m_hphy_ac_rom_init_file = AC_ROM_INIT_FILE_NAME;
defparam hphy_inst.m_hphy_inst_rom_init_file = INST_ROM_INIT_FILE_NAME;
defparam hphy_inst.hphy_wrap_back_en = "false";
defparam hphy_inst.hphy_atpg_en = "false";
defparam hphy_inst.hphy_use_hphy = "true";
defparam hphy_inst.hphy_csr_pipelineglobalenable = "true";
defparam hphy_inst.hphy_hhp_hps = IS_HHP_HPS;
// ********************************************************************************************************************************
// The I/O block is responsible for instantiating all the built-in I/O logic in the FPGA
// ********************************************************************************************************************************
hps_sdram_p0_acv_hard_io_pads #(
.DEVICE_FAMILY(DEVICE_FAMILY),
.FAST_SIM_MODEL(FAST_SIM_MODEL),
.OCT_SERIES_TERM_CONTROL_WIDTH(OCT_SERIES_TERM_CONTROL_WIDTH),
.OCT_PARALLEL_TERM_CONTROL_WIDTH(OCT_PARALLEL_TERM_CONTROL_WIDTH),
.MEM_ADDRESS_WIDTH(MEM_ADDRESS_WIDTH),
.MEM_BANK_WIDTH(MEM_BANK_WIDTH),
.MEM_CHIP_SELECT_WIDTH(MEM_IF_CS_WIDTH),
.MEM_CLK_EN_WIDTH(MEM_CLK_EN_WIDTH),
.MEM_CK_WIDTH(MEM_CK_WIDTH),
.MEM_ODT_WIDTH(MEM_ODT_WIDTH),
.MEM_DQS_WIDTH(MEM_DQS_WIDTH),
.MEM_DM_WIDTH(MEM_DM_WIDTH),
.MEM_CONTROL_WIDTH(MEM_CONTROL_WIDTH),
.MEM_DQ_WIDTH(MEM_DQ_WIDTH),
.MEM_READ_DQS_WIDTH(MEM_READ_DQS_WIDTH),
.MEM_WRITE_DQS_WIDTH(MEM_WRITE_DQS_WIDTH),
.DLL_DELAY_CTRL_WIDTH(DLL_DELAY_CTRL_WIDTH),
.ADC_PHASE_SETTING(ADC_PHASE_SETTING),
.ADC_INVERT_PHASE(ADC_INVERT_PHASE),
.IS_HHP_HPS(IS_HHP_HPS)
) uio_pads (
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_afi_clk (reset_n_afi_clk[1]),
.oct_ctl_rs_value (oct_ctl_rs_value),
.oct_ctl_rt_value (oct_ctl_rt_value),
.phy_ddio_address (phy_ddio_address),
.phy_ddio_bank (phy_ddio_bank),
.phy_ddio_cs_n (phy_ddio_cs_n),
.phy_ddio_cke (phy_ddio_cke),
.phy_ddio_odt (phy_ddio_odt),
.phy_ddio_we_n (phy_ddio_we_n),
.phy_ddio_ras_n (phy_ddio_ras_n),
.phy_ddio_cas_n (phy_ddio_cas_n),
.phy_ddio_ck (phy_ddio_ck),
.phy_ddio_reset_n (phy_ddio_reset_n),
.phy_mem_address (mem_a),
.phy_mem_bank (mem_ba),
.phy_mem_cs_n (mem_cs_n),
.phy_mem_cke (mem_cke),
.phy_mem_odt (mem_odt),
.phy_mem_we_n (mem_we_n),
.phy_mem_ras_n (mem_ras_n),
.phy_mem_cas_n (mem_cas_n),
.phy_mem_reset_n (mem_reset_n),
.pll_afi_clk (pll_afi_clk),
.pll_mem_clk (pll_mem_clk),
.pll_afi_phy_clk (pll_afi_phy_clk),
.pll_avl_phy_clk (pll_avl_phy_clk),
.pll_avl_clk (pll_avl_clk),
.avl_clk (avl_clk),
.pll_mem_phy_clk (pll_mem_phy_clk),
.pll_write_clk (pll_write_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.pll_addr_cmd_clk (adc_clk_cps),
.phy_mem_dq (mem_dq),
.phy_mem_dm (mem_dm),
.phy_mem_ck (mem_ck),
.phy_mem_ck_n (mem_ck_n),
.mem_dqs (mem_dqs),
.mem_dqs_n (mem_dqs_n),
.dll_phy_delayctrl (dll_phy_delayctrl),
.scc_clk (pll_config_clk),
.scc_data (scc_data),
.scc_dqs_ena (scc_dqs_ena),
.scc_dqs_io_ena (scc_dqs_io_ena),
.scc_dq_ena (scc_dq_ena),
.scc_dm_ena (scc_dm_ena),
.scc_upd (scc_upd[0]),
.phy_ddio_dmdout (phy_ddio_dmdout),
.phy_ddio_dqdout (phy_ddio_dqdout),
.phy_ddio_dqs_oe (phy_ddio_dqs_oe),
.phy_ddio_dqsdout (phy_ddio_dqs_dout),
.phy_ddio_dqsb_oe (phy_ddio_dqsb_oe),
.phy_ddio_dqslogic_oct (phy_ddio_dqslogic_oct),
.phy_ddio_dqslogic_fiforeset (phy_ddio_dqslogic_fiforeset),
.phy_ddio_dqslogic_aclr_pstamble (phy_ddio_dqslogic_aclr_pstamble),
.phy_ddio_dqslogic_aclr_fifoctrl (phy_ddio_dqslogic_aclr_fifoctrl),
.phy_ddio_dqslogic_incwrptr (phy_ddio_dqslogic_incwrptr),
.phy_ddio_dqslogic_readlatency (phy_ddio_dqslogic_readlatency),
.ddio_phy_dqslogic_rdatavalid (ddio_phy_dqslogic_rdatavalid),
.ddio_phy_dqdin (ddio_phy_dqdin),
.phy_ddio_dqslogic_incrdataen (phy_ddio_dqslogic_incrdataen),
.phy_ddio_dqslogic_dqsena (phy_ddio_dqslogic_dqsena),
.phy_ddio_dqoe (phy_ddio_dqoe),
.capture_strobe_tracking (capture_strobe_tracking)
);
generate
if (IS_HHP_HPS != "true") begin
reg afi_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_afi_clk)
afi_clk_reg <= ~afi_clk_reg;
reg afi_half_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_afi_half_clk)
afi_half_clk_reg <= ~afi_half_clk_reg;
reg avl_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_avl_clk)
avl_clk_reg <= ~avl_clk_reg;
reg config_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_config_clk)
config_clk_reg <= ~config_clk_reg;
end
endgenerate
// Calculate the ceiling of log_2 of the input value
function integer ceil_log2;
input integer value;
begin
value = value - 1;
for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1)
value = value >> 1;
end
endfunction
endmodule
|
`timescale 1ns / 100ps
`define EIC_DIRECT_CHANNELS 20
`define EIC_SENSE_CHANNELS 20
`include "mfp_eic_core.vh"
module test_eic;
`include "ahb_lite.vh"
reg [ `EIC_CHANNELS -1 : 0 ] signal;
wire [ 17 : 1 ] EIC_Offset;
wire [ 3 : 0 ] EIC_ShadowSet;
wire [ 7 : 0 ] EIC_Interrupt;
wire [ 5 : 0 ] EIC_Vector;
wire EIC_Present;
reg [ `EIC_ADDR_WIDTH - 1 : 0 ] read_addr;
wire [ 31 : 0 ] read_data;
reg [ `EIC_ADDR_WIDTH - 1 : 0 ] write_addr;
reg [ 31 : 0 ] write_data;
reg write_enable;
task eicRead;
input [ `EIC_ADDR_WIDTH - 1 : 0 ] _read_addr;
begin
read_addr = _read_addr;
@(posedge HCLK);
$display("%t READEN ADDR=%h DATA=%h",
$time, _read_addr, read_data);
end
endtask
task eicWrite;
input [ `EIC_ADDR_WIDTH - 1 : 0 ] _write_addr;
input [ 31 : 0 ] _write_data;
begin
write_addr = _write_addr;
write_data = _write_data;
write_enable = 1'b1;
@(posedge HCLK);
write_enable = 1'b0;
$display("%t WRITEN ADDR=%h DATA=%h",
$time, _write_addr, _write_data);
end
endtask
task delay;
begin
@(posedge HCLK);
@(posedge HCLK);
@(posedge HCLK);
end
endtask
mfp_eic_core eic
(
.CLK ( HCLK ),
.RESETn ( HRESETn ),
.signal ( signal ),
.read_addr ( read_addr ),
.read_data ( read_data ),
.write_addr ( write_addr ),
.write_data ( write_data ),
.write_enable ( write_enable ),
.EIC_Offset ( EIC_Offset ),
.EIC_ShadowSet ( EIC_ShadowSet ),
.EIC_Interrupt ( EIC_Interrupt ),
.EIC_Vector ( EIC_Vector ),
.EIC_Present ( EIC_Present )
);
parameter Tclk = 20;
always #(Tclk/2) HCLK = ~HCLK;
initial begin
begin
/*
`define EIC_REG_EICR +
`define EIC_REG_EIMSK_0 +
`define EIC_REG_EIMSK_1 +
`define EIC_REG_EIFR_0 +
`define EIC_REG_EIFR_1
`define EIC_REG_EIFRS_0 +
`define EIC_REG_EIFRS_1
`define EIC_REG_EIFRC_0
`define EIC_REG_EIFRC_1 +
`define EIC_REG_EISMSK_0 +
`define EIC_REG_EISMSK_1
`define EIC_REG_EIIPR_0 +
`define EIC_REG_EIIPR_1 +
*/
signal = 16'b0;
HRESETn = 0;
@(posedge HCLK);
@(posedge HCLK);
HRESETn = 1;
@(posedge HCLK);
@(posedge HCLK);
eicWrite(`EIC_REG_EICR, 32'h01); //enable eic
eicWrite(`EIC_REG_EISMSK_0, 32'h05); //any logical change for irq 1, 2 (pins 0, 1)
eicWrite(`EIC_REG_EIMSK_0, 32'h03); //enable irq 1, 2 (pins 0, 1)
eicWrite(`EIC_REG_EIMSK_1, 32'h01); //enable irq 33 (pin 32)
eicRead(`EIC_REG_EIMSK_0);
eicRead(`EIC_REG_EIMSK_1);
@(posedge HCLK); signal[0] = 1'b1;
@(posedge HCLK); signal[1] = 1'b1;
delay();
@(posedge HCLK); signal[32] = 1'b1;
@(posedge HCLK); signal[32] = 1'b0;
delay();
eicRead(`EIC_REG_EIFR_1);
eicWrite(`EIC_REG_EIFRC_1, 32'h01); //clear irq 33 (pin 32)
eicRead(`EIC_REG_EIFR_0);
delay();
eicWrite(`EIC_REG_EIFR_0, 32'h01); //set EIFR word0
eicRead(`EIC_REG_EIFR_0);
delay();
eicWrite(`EIC_REG_EIFRS_0, 32'h04); //set EIFR bit3
eicRead(`EIC_REG_EIFR_0);
delay();
end
$stop;
$finish;
end
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_acv_hard_io_pads(
reset_n_addr_cmd_clk,
reset_n_afi_clk,
oct_ctl_rs_value,
oct_ctl_rt_value,
phy_ddio_address,
phy_ddio_bank,
phy_ddio_cs_n,
phy_ddio_cke,
phy_ddio_odt,
phy_ddio_we_n,
phy_ddio_ras_n,
phy_ddio_cas_n,
phy_ddio_ck,
phy_ddio_reset_n,
phy_mem_address,
phy_mem_bank,
phy_mem_cs_n,
phy_mem_cke,
phy_mem_odt,
phy_mem_we_n,
phy_mem_ras_n,
phy_mem_cas_n,
phy_mem_reset_n,
pll_afi_clk,
pll_afi_phy_clk,
pll_avl_phy_clk,
pll_avl_clk,
avl_clk,
pll_mem_clk,
pll_mem_phy_clk,
pll_write_clk,
pll_dqs_ena_clk,
pll_addr_cmd_clk,
phy_mem_dq,
phy_mem_dm,
phy_mem_ck,
phy_mem_ck_n,
mem_dqs,
mem_dqs_n,
dll_phy_delayctrl,
scc_clk,
scc_data,
scc_dqs_ena,
scc_dqs_io_ena,
scc_dq_ena,
scc_dm_ena,
scc_upd,
seq_read_latency_counter,
seq_read_increment_vfifo_fr,
seq_read_increment_vfifo_hr,
phy_ddio_dmdout,
phy_ddio_dqdout,
phy_ddio_dqs_oe,
phy_ddio_dqsdout,
phy_ddio_dqsb_oe,
phy_ddio_dqslogic_oct,
phy_ddio_dqslogic_fiforeset,
phy_ddio_dqslogic_aclr_pstamble,
phy_ddio_dqslogic_aclr_fifoctrl,
phy_ddio_dqslogic_incwrptr,
phy_ddio_dqslogic_readlatency,
ddio_phy_dqslogic_rdatavalid,
ddio_phy_dqdin,
phy_ddio_dqslogic_incrdataen,
phy_ddio_dqslogic_dqsena,
phy_ddio_dqoe,
capture_strobe_tracking
);
parameter DEVICE_FAMILY = "";
parameter FAST_SIM_MODEL = 0;
parameter OCT_SERIES_TERM_CONTROL_WIDTH = "";
parameter OCT_PARALLEL_TERM_CONTROL_WIDTH = "";
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_CHIP_SELECT_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_DQS_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter ADC_PHASE_SETTING = "";
parameter ADC_INVERT_PHASE = "";
parameter IS_HHP_HPS = "";
localparam AFI_ADDRESS_WIDTH = 64;
localparam AFI_BANK_WIDTH = 12;
localparam AFI_CHIP_SELECT_WIDTH = 8;
localparam AFI_CLK_EN_WIDTH = 8;
localparam AFI_ODT_WIDTH = 8;
localparam AFI_DATA_MASK_WIDTH = 20;
localparam AFI_CONTROL_WIDTH = 4;
input reset_n_afi_clk;
input reset_n_addr_cmd_clk;
input [OCT_SERIES_TERM_CONTROL_WIDTH-1:0] oct_ctl_rs_value;
input [OCT_PARALLEL_TERM_CONTROL_WIDTH-1:0] oct_ctl_rt_value;
input [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
input [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
input [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
input [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ck;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_reset_n;
output [MEM_ADDRESS_WIDTH-1:0] phy_mem_address;
output [MEM_BANK_WIDTH-1:0] phy_mem_bank;
output [MEM_CHIP_SELECT_WIDTH-1:0] phy_mem_cs_n;
output [MEM_CLK_EN_WIDTH-1:0] phy_mem_cke;
output [MEM_ODT_WIDTH-1:0] phy_mem_odt;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_we_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_cas_n;
output phy_mem_reset_n;
input pll_afi_clk;
input pll_afi_phy_clk;
input pll_avl_phy_clk;
input pll_avl_clk;
input avl_clk;
input pll_mem_clk;
input pll_mem_phy_clk;
input pll_write_clk;
input pll_dqs_ena_clk;
input pll_addr_cmd_clk;
inout [MEM_DQ_WIDTH-1:0] phy_mem_dq;
output [MEM_DM_WIDTH-1:0] phy_mem_dm;
output [MEM_CK_WIDTH-1:0] phy_mem_ck;
output [MEM_CK_WIDTH-1:0] phy_mem_ck_n;
inout [MEM_DQS_WIDTH-1:0] mem_dqs;
inout [MEM_DQS_WIDTH-1:0] mem_dqs_n;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl;
input scc_clk;
input scc_data;
input [MEM_READ_DQS_WIDTH - 1:0] scc_dqs_ena;
input [MEM_READ_DQS_WIDTH - 1:0] scc_dqs_io_ena;
input [MEM_DQ_WIDTH - 1:0] scc_dq_ena;
input [MEM_DM_WIDTH - 1:0] scc_dm_ena;
input [4:0] seq_read_latency_counter;
input [MEM_READ_DQS_WIDTH-1:0] seq_read_increment_vfifo_fr;
input [MEM_READ_DQS_WIDTH-1:0] seq_read_increment_vfifo_hr;
input scc_upd;
output [MEM_READ_DQS_WIDTH - 1:0] capture_strobe_tracking;
input [24 : 0] phy_ddio_dmdout;
input [179 : 0] phy_ddio_dqdout;
input [9 : 0] phy_ddio_dqs_oe;
input [19 : 0] phy_ddio_dqsdout;
input [9 : 0] phy_ddio_dqsb_oe;
input [9 : 0] phy_ddio_dqslogic_oct;
input [4 : 0] phy_ddio_dqslogic_fiforeset;
input [4 : 0] phy_ddio_dqslogic_aclr_pstamble;
input [4 : 0] phy_ddio_dqslogic_aclr_fifoctrl;
input [9 : 0] phy_ddio_dqslogic_incwrptr;
input [24 : 0] phy_ddio_dqslogic_readlatency;
output [4 : 0] ddio_phy_dqslogic_rdatavalid;
output [179 : 0] ddio_phy_dqdin;
input [9 : 0] phy_ddio_dqslogic_incrdataen;
input [9 : 0] phy_ddio_dqslogic_dqsena;
input [89 : 0] phy_ddio_dqoe;
wire [MEM_DQ_WIDTH-1:0] mem_phy_dq;
wire [DLL_DELAY_CTRL_WIDTH-1:0] read_bidir_dll_phy_delayctrl;
wire [MEM_READ_DQS_WIDTH-1:0] bidir_read_dqs_bus_out;
wire [MEM_DQ_WIDTH-1:0] bidir_read_dq_input_data_out_high;
wire [MEM_DQ_WIDTH-1:0] bidir_read_dq_input_data_out_low;
wire dqs_busout;
wire hr_clk = pll_avl_clk;
wire core_clk = pll_afi_clk;
wire reset_n_core_clk = reset_n_afi_clk;
hps_sdram_p0_acv_hard_addr_cmd_pads uaddr_cmd_pads(
/*
.config_data_in(config_data_in),
.config_clock_in(config_clock_in),
.config_io_ena(config_io_ena),
.config_update(config_update),
*/
.reset_n (reset_n_addr_cmd_clk),
.reset_n_afi_clk (reset_n_afi_clk),
.pll_afi_clk (pll_afi_phy_clk),
.pll_mem_clk (pll_mem_phy_clk),
.pll_hr_clk (hr_clk),
.pll_avl_phy_clk (pll_avl_phy_clk),
.pll_write_clk (pll_write_clk),
.dll_delayctrl_in (dll_phy_delayctrl),
.phy_ddio_address (phy_ddio_address),
.phy_ddio_bank (phy_ddio_bank),
.phy_ddio_cs_n (phy_ddio_cs_n),
.phy_ddio_cke (phy_ddio_cke),
.phy_ddio_odt (phy_ddio_odt),
.phy_ddio_we_n (phy_ddio_we_n),
.phy_ddio_ras_n (phy_ddio_ras_n),
.phy_ddio_cas_n (phy_ddio_cas_n),
.phy_ddio_ck (phy_ddio_ck),
.phy_ddio_reset_n (phy_ddio_reset_n),
.phy_mem_address (phy_mem_address),
.phy_mem_bank (phy_mem_bank),
.phy_mem_cs_n (phy_mem_cs_n),
.phy_mem_cke (phy_mem_cke),
.phy_mem_odt (phy_mem_odt),
.phy_mem_we_n (phy_mem_we_n),
.phy_mem_ras_n (phy_mem_ras_n),
.phy_mem_cas_n (phy_mem_cas_n),
.phy_mem_reset_n (phy_mem_reset_n),
.phy_mem_ck (phy_mem_ck),
.phy_mem_ck_n (phy_mem_ck_n)
);
defparam uaddr_cmd_pads.DEVICE_FAMILY = DEVICE_FAMILY;
defparam uaddr_cmd_pads.MEM_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH;
defparam uaddr_cmd_pads.MEM_BANK_WIDTH = MEM_BANK_WIDTH;
defparam uaddr_cmd_pads.MEM_CHIP_SELECT_WIDTH = MEM_CHIP_SELECT_WIDTH;
defparam uaddr_cmd_pads.MEM_CLK_EN_WIDTH = MEM_CLK_EN_WIDTH;
defparam uaddr_cmd_pads.MEM_CK_WIDTH = MEM_CK_WIDTH;
defparam uaddr_cmd_pads.MEM_ODT_WIDTH = MEM_ODT_WIDTH;
defparam uaddr_cmd_pads.MEM_CONTROL_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_pads.AFI_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH * 4;
defparam uaddr_cmd_pads.AFI_BANK_WIDTH = MEM_BANK_WIDTH * 4;
defparam uaddr_cmd_pads.AFI_CHIP_SELECT_WIDTH = MEM_CHIP_SELECT_WIDTH * 4;
defparam uaddr_cmd_pads.AFI_CLK_EN_WIDTH = MEM_CLK_EN_WIDTH * 4;
defparam uaddr_cmd_pads.AFI_ODT_WIDTH = MEM_ODT_WIDTH * 4;
defparam uaddr_cmd_pads.AFI_CONTROL_WIDTH = MEM_CONTROL_WIDTH * 4;
defparam uaddr_cmd_pads.DLL_WIDTH = DLL_DELAY_CTRL_WIDTH;
defparam uaddr_cmd_pads.ADC_PHASE_SETTING = ADC_PHASE_SETTING;
defparam uaddr_cmd_pads.ADC_INVERT_PHASE = ADC_INVERT_PHASE;
defparam uaddr_cmd_pads.IS_HHP_HPS = IS_HHP_HPS;
localparam NUM_OF_DQDQS = MEM_WRITE_DQS_WIDTH;
localparam DQDQS_DATA_WIDTH = MEM_DQ_WIDTH / NUM_OF_DQDQS;
localparam NATIVE_GROUP_SIZE =
(DQDQS_DATA_WIDTH == 8) ? 9 : DQDQS_DATA_WIDTH;
localparam DQDQS_DM_WIDTH = MEM_DM_WIDTH / MEM_WRITE_DQS_WIDTH;
localparam NUM_OF_DQDQS_WITH_DM = MEM_WRITE_DQS_WIDTH;
generate
genvar i;
for (i=0; i<NUM_OF_DQDQS; i=i+1)
begin: dq_ddio
hps_sdram_p0_altdqdqs ubidir_dq_dqs (
.write_strobe_clock_in (pll_mem_phy_clk),
.reset_n_core_clock_in (reset_n_core_clk),
.core_clock_in (core_clk),
.fr_clock_in (pll_write_clk),
.hr_clock_in (pll_avl_phy_clk),
.parallelterminationcontrol_in(oct_ctl_rt_value),
.seriesterminationcontrol_in(oct_ctl_rs_value),
.strobe_ena_hr_clock_in (hr_clk),
.capture_strobe_tracking (capture_strobe_tracking[i]),
.read_write_data_io (phy_mem_dq[(DQDQS_DATA_WIDTH*(i+1)-1) : DQDQS_DATA_WIDTH*i]),
.read_data_out (ddio_phy_dqdin[((NATIVE_GROUP_SIZE*i+DQDQS_DATA_WIDTH)*4-1) : (NATIVE_GROUP_SIZE*i*4)]),
.capture_strobe_out(dqs_busout),
.extra_write_data_in (phy_ddio_dmdout[(i + 1) * 4 - 1 : (i * 4)]),
.write_data_in (phy_ddio_dqdout[((NATIVE_GROUP_SIZE*i+DQDQS_DATA_WIDTH)*4-1) : (NATIVE_GROUP_SIZE*i*4)]),
.write_oe_in (phy_ddio_dqoe[((NATIVE_GROUP_SIZE*i+DQDQS_DATA_WIDTH)*2-1) : (NATIVE_GROUP_SIZE*i*2)]),
.strobe_io (mem_dqs[i]),
.strobe_n_io (mem_dqs_n[i]),
.output_strobe_ena(phy_ddio_dqs_oe[(i + 1) * 2 - 1 : (i * 2)]),
.write_strobe(phy_ddio_dqsdout[(i + 1) * 4 - 1 : (i * 4)]),
.oct_ena_in(phy_ddio_dqslogic_oct[(i + 1) * 2 - 1 : (i * 2)]),
.extra_write_data_out (phy_mem_dm[i]),
.config_data_in (scc_data),
.config_dqs_ena (scc_dqs_ena[i]),
.config_io_ena (scc_dq_ena[(DQDQS_DATA_WIDTH*(i+1)-1) : DQDQS_DATA_WIDTH*i]),
.config_dqs_io_ena (scc_dqs_io_ena[i]),
.config_update (scc_upd),
.config_clock_in (scc_clk),
.config_extra_io_ena (scc_dm_ena[i]),
.lfifo_rdata_en(phy_ddio_dqslogic_incrdataen[(i + 1) * 2 - 1 : (i * 2)]),
.lfifo_rdata_en_full(phy_ddio_dqslogic_dqsena[(i + 1) * 2 - 1 : (i * 2)]),
.lfifo_rd_latency(phy_ddio_dqslogic_readlatency[(i + 1) * 5 - 1 : (i * 5)]),
.lfifo_reset_n (phy_ddio_dqslogic_aclr_fifoctrl[i]),
.lfifo_rdata_valid(ddio_phy_dqslogic_rdatavalid[i]),
.vfifo_qvld(phy_ddio_dqslogic_dqsena[(i + 1) * 2 - 1 : (i * 2)]),
.vfifo_inc_wr_ptr(phy_ddio_dqslogic_incwrptr[(i + 1) * 2 - 1 : (i * 2)]),
.vfifo_reset_n (phy_ddio_dqslogic_aclr_pstamble[i]),
.dll_delayctrl_in (dll_phy_delayctrl),
.rfifo_reset_n(phy_ddio_dqslogic_fiforeset[i])
);
end
endgenerate
generate
genvar j;
for (j = NUM_OF_DQDQS; j < 5; j=j+1)
begin: to_vcc
assign ddio_phy_dqslogic_rdatavalid[j] = 1'b1;
end
endgenerate
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_9_b2s_cmd_translator.v
//
// Description:
// INCR and WRAP burst modes are decoded in parallel and then the output is
// chosen based on the AxBURST value. FIXED burst mode is not supported and
// is mapped to the INCR command instead.
//
// Specifications:
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_9_b2s_cmd_translator #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axaddr ,
input wire [7:0] s_axlen ,
input wire [2:0] s_axsize ,
input wire [1:0] s_axburst ,
input wire s_axhandshake ,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axaddr ,
output wire incr_burst ,
// Connections to/from fsm module
// signal to increment to the next mc transaction
input wire next ,
// signal to the fsm there is another transaction required
output wire next_pending
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// AXBURST decodes
localparam P_AXBURST_FIXED = 2'b00;
localparam P_AXBURST_INCR = 2'b01;
localparam P_AXBURST_WRAP = 2'b10;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire [C_AXI_ADDR_WIDTH-1:0] incr_cmd_byte_addr;
wire incr_next_pending;
wire [C_AXI_ADDR_WIDTH-1:0] wrap_cmd_byte_addr;
wire wrap_next_pending;
reg sel_first;
reg s_axburst_eq1;
reg s_axburst_eq0;
reg sel_first_i;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// INCR and WRAP translations are calcuated in independently, select the one
// for our transactions
// right shift by the UI width to the DRAM width ratio
assign m_axaddr = (s_axburst == P_AXBURST_FIXED) ? s_axaddr :
(s_axburst == P_AXBURST_INCR) ? incr_cmd_byte_addr :
wrap_cmd_byte_addr;
assign incr_burst = (s_axburst[1]) ? 1'b0 : 1'b1;
// Indicates if we are on the first transaction of a mc translation with more
// than 1 transaction.
always @(posedge clk) begin
if (reset | s_axhandshake) begin
sel_first <= 1'b1;
end else if (next) begin
sel_first <= 1'b0;
end
end
always @( * ) begin
if (reset | s_axhandshake) begin
sel_first_i = 1'b1;
end else if (next) begin
sel_first_i = 1'b0;
end else begin
sel_first_i = sel_first;
end
end
assign next_pending = s_axburst[1] ? s_axburst_eq1 : s_axburst_eq0;
always @(posedge clk) begin
if (sel_first_i || s_axburst[1]) begin
s_axburst_eq1 <= wrap_next_pending;
end else begin
s_axburst_eq1 <= incr_next_pending;
end
if (sel_first_i || !s_axburst[1]) begin
s_axburst_eq0 <= incr_next_pending;
end else begin
s_axburst_eq0 <= wrap_next_pending;
end
end
axi_protocol_converter_v2_1_9_b2s_incr_cmd #(
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH)
)
incr_cmd_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axaddr ( s_axaddr ) ,
.axlen ( s_axlen ) ,
.axsize ( s_axsize ) ,
.axhandshake ( s_axhandshake ) ,
.cmd_byte_addr ( incr_cmd_byte_addr ) ,
.next ( next ) ,
.next_pending ( incr_next_pending )
);
axi_protocol_converter_v2_1_9_b2s_wrap_cmd #(
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH)
)
wrap_cmd_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axaddr ( s_axaddr ) ,
.axlen ( s_axlen ) ,
.axsize ( s_axsize ) ,
.axhandshake ( s_axhandshake ) ,
.cmd_byte_addr ( wrap_cmd_byte_addr ) ,
.next ( next ) ,
.next_pending ( wrap_next_pending )
);
endmodule
`default_nettype wire
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_cntrl.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Structural block instantiating the three sub blocks that make up
// a bank machine.
`timescale 1ps/1ps
module mig_7series_v2_3_bank_cntrl #
(
parameter TCQ = 100,
parameter ADDR_CMD_MODE = "1T",
parameter BANK_WIDTH = 3,
parameter BM_CNT_WIDTH = 2,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter CWL = 5,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter ECC = "OFF",
parameter ID = 4,
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nOP_WAIT = 0,
parameter nRAS_CLKS = 10,
parameter nRCD = 5,
parameter nRTP = 4,
parameter nRP = 10,
parameter nWTP_CLKS = 5,
parameter ORDERING = "NORM",
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter RAS_TIMER_WIDTH = 5,
parameter ROW_WIDTH = 16,
parameter STARVE_LIMIT = 2
)
(/*AUTOARG*/
// Outputs
wr_this_rank_r, start_rcd, start_pre_wait, rts_row, rts_col, rts_pre, rtc,
row_cmd_wr, row_addr, req_size_r, req_row_r, req_ras,
req_periodic_rd_r, req_cas, req_bank_r, rd_this_rank_r,
rb_hit_busy_ns, ras_timer_ns, rank_busy_r, ordered_r,
ordered_issued, op_exit_req, end_rtp, demand_priority,
demand_act_priority, col_rdy_wr, col_addr, act_this_rank_r, idle_ns,
req_wr_r, rd_wr_r, bm_end, idle_r, head_r, req_rank_r,
rb_hit_busy_r, passing_open_bank, maint_hit, req_data_buf_addr_r,
// Inputs
was_wr, was_priority, use_addr, start_rcd_in,
size, sent_row, sent_col, sending_row, sending_pre, sending_col, rst, row,
req_rank_r_in, rd_rmw, rd_data_addr, rb_hit_busy_ns_in,
rb_hit_busy_cnt, ras_timer_ns_in, rank, periodic_rd_rank_r,
periodic_rd_insert, periodic_rd_ack_r, passing_open_bank_in,
order_cnt, op_exit_grant, maint_zq_r, maint_sre_r, maint_req_r, maint_rank_r,
maint_idle, low_idle_cnt_r, rnk_config_valid_r, inhbt_rd, inhbt_wr,
rnk_config_strobe, rnk_config, inhbt_act_faw_r, idle_cnt, hi_priority,
dq_busy_data, phy_rddata_valid, demand_priority_in, demand_act_priority_in,
data_buf_addr, col, cmd, clk, bm_end_in, bank, adv_order_q,
accept_req, accept_internal_r, rnk_config_kill_rts_col, phy_mc_ctl_full,
phy_mc_cmd_full, phy_mc_data_full
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input accept_internal_r; // To bank_queue0 of bank_queue.v
input accept_req; // To bank_queue0 of bank_queue.v
input adv_order_q; // To bank_queue0 of bank_queue.v
input [BANK_WIDTH-1:0] bank; // To bank_compare0 of bank_compare.v
input [(nBANK_MACHS*2)-1:0] bm_end_in; // To bank_queue0 of bank_queue.v
input clk; // To bank_compare0 of bank_compare.v, ...
input [2:0] cmd; // To bank_compare0 of bank_compare.v
input [COL_WIDTH-1:0] col; // To bank_compare0 of bank_compare.v
input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr;// To bank_compare0 of bank_compare.v
input [(nBANK_MACHS*2)-1:0] demand_act_priority_in;// To bank_state0 of bank_state.v
input [(nBANK_MACHS*2)-1:0] demand_priority_in;// To bank_state0 of bank_state.v
input phy_rddata_valid; // To bank_state0 of bank_state.v
input dq_busy_data; // To bank_state0 of bank_state.v
input hi_priority; // To bank_compare0 of bank_compare.v
input [BM_CNT_WIDTH-1:0] idle_cnt; // To bank_queue0 of bank_queue.v
input [RANKS-1:0] inhbt_act_faw_r; // To bank_state0 of bank_state.v
input [RANKS-1:0] inhbt_rd; // To bank_state0 of bank_state.v
input [RANKS-1:0] inhbt_wr; // To bank_state0 of bank_state.v
input [RANK_WIDTH-1:0]rnk_config; // To bank_state0 of bank_state.v
input rnk_config_strobe; // To bank_state0 of bank_state.v
input rnk_config_kill_rts_col;// To bank_state0 of bank_state.v
input rnk_config_valid_r; // To bank_state0 of bank_state.v
input low_idle_cnt_r; // To bank_state0 of bank_state.v
input maint_idle; // To bank_queue0 of bank_queue.v
input [RANK_WIDTH-1:0] maint_rank_r; // To bank_compare0 of bank_compare.v
input maint_req_r; // To bank_queue0 of bank_queue.v
input maint_zq_r; // To bank_compare0 of bank_compare.v
input maint_sre_r; // To bank_compare0 of bank_compare.v
input op_exit_grant; // To bank_state0 of bank_state.v
input [BM_CNT_WIDTH-1:0] order_cnt; // To bank_queue0 of bank_queue.v
input [(nBANK_MACHS*2)-1:0] passing_open_bank_in;// To bank_queue0 of bank_queue.v
input periodic_rd_ack_r; // To bank_queue0 of bank_queue.v
input periodic_rd_insert; // To bank_compare0 of bank_compare.v
input [RANK_WIDTH-1:0] periodic_rd_rank_r; // To bank_compare0 of bank_compare.v
input phy_mc_ctl_full;
input phy_mc_cmd_full;
input phy_mc_data_full;
input [RANK_WIDTH-1:0] rank; // To bank_compare0 of bank_compare.v
input [(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0] ras_timer_ns_in;// To bank_state0 of bank_state.v
input [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt; // To bank_queue0 of bank_queue.v
input [(nBANK_MACHS*2)-1:0] rb_hit_busy_ns_in;// To bank_queue0 of bank_queue.v
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; // To bank_state0 of bank_state.v
input rd_rmw; // To bank_state0 of bank_state.v
input [(RANK_WIDTH*nBANK_MACHS*2)-1:0] req_rank_r_in;// To bank_state0 of bank_state.v
input [ROW_WIDTH-1:0] row; // To bank_compare0 of bank_compare.v
input rst; // To bank_state0 of bank_state.v, ...
input sending_col; // To bank_compare0 of bank_compare.v, ...
input sending_row; // To bank_state0 of bank_state.v
input sending_pre;
input sent_col; // To bank_state0 of bank_state.v
input sent_row; // To bank_state0 of bank_state.v
input size; // To bank_compare0 of bank_compare.v
input [(nBANK_MACHS*2)-1:0] start_rcd_in; // To bank_state0 of bank_state.v
input use_addr; // To bank_queue0 of bank_queue.v
input was_priority; // To bank_queue0 of bank_queue.v
input was_wr; // To bank_queue0 of bank_queue.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [RANKS-1:0] act_this_rank_r; // From bank_state0 of bank_state.v
output [ROW_WIDTH-1:0] col_addr; // From bank_compare0 of bank_compare.v
output col_rdy_wr; // From bank_state0 of bank_state.v
output demand_act_priority; // From bank_state0 of bank_state.v
output demand_priority; // From bank_state0 of bank_state.v
output end_rtp; // From bank_state0 of bank_state.v
output op_exit_req; // From bank_state0 of bank_state.v
output ordered_issued; // From bank_queue0 of bank_queue.v
output ordered_r; // From bank_queue0 of bank_queue.v
output [RANKS-1:0] rank_busy_r; // From bank_compare0 of bank_compare.v
output [RAS_TIMER_WIDTH-1:0] ras_timer_ns; // From bank_state0 of bank_state.v
output rb_hit_busy_ns; // From bank_compare0 of bank_compare.v
output [RANKS-1:0] rd_this_rank_r; // From bank_state0 of bank_state.v
output [BANK_WIDTH-1:0] req_bank_r; // From bank_compare0 of bank_compare.v
output req_cas; // From bank_compare0 of bank_compare.v
output req_periodic_rd_r; // From bank_compare0 of bank_compare.v
output req_ras; // From bank_compare0 of bank_compare.v
output [ROW_WIDTH-1:0] req_row_r; // From bank_compare0 of bank_compare.v
output req_size_r; // From bank_compare0 of bank_compare.v
output [ROW_WIDTH-1:0] row_addr; // From bank_compare0 of bank_compare.v
output row_cmd_wr; // From bank_compare0 of bank_compare.v
output rtc; // From bank_state0 of bank_state.v
output rts_col; // From bank_state0 of bank_state.v
output rts_row; // From bank_state0 of bank_state.v
output rts_pre;
output start_pre_wait; // From bank_state0 of bank_state.v
output start_rcd; // From bank_state0 of bank_state.v
output [RANKS-1:0] wr_this_rank_r; // From bank_state0 of bank_state.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire act_wait_r; // From bank_state0 of bank_state.v
wire allow_auto_pre; // From bank_state0 of bank_state.v
wire auto_pre_r; // From bank_queue0 of bank_queue.v
wire bank_wait_in_progress; // From bank_state0 of bank_state.v
wire order_q_zero; // From bank_queue0 of bank_queue.v
wire pass_open_bank_ns; // From bank_queue0 of bank_queue.v
wire pass_open_bank_r; // From bank_queue0 of bank_queue.v
wire pre_wait_r; // From bank_state0 of bank_state.v
wire precharge_bm_end; // From bank_state0 of bank_state.v
wire q_has_priority; // From bank_queue0 of bank_queue.v
wire q_has_rd; // From bank_queue0 of bank_queue.v
wire [nBANK_MACHS*2-1:0] rb_hit_busies_r; // From bank_queue0 of bank_queue.v
wire rcv_open_bank; // From bank_queue0 of bank_queue.v
wire rd_half_rmw; // From bank_state0 of bank_state.v
wire req_priority_r; // From bank_compare0 of bank_compare.v
wire row_hit_r; // From bank_compare0 of bank_compare.v
wire tail_r; // From bank_queue0 of bank_queue.v
wire wait_for_maint_r; // From bank_queue0 of bank_queue.v
// End of automatics
output idle_ns;
output req_wr_r;
output rd_wr_r;
output bm_end;
output idle_r;
output head_r;
output [RANK_WIDTH-1:0] req_rank_r;
output rb_hit_busy_r;
output passing_open_bank;
output maint_hit;
output [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r;
mig_7series_v2_3_bank_compare #
(/*AUTOINSTPARAM*/
// Parameters
.BANK_WIDTH (BANK_WIDTH),
.TCQ (TCQ),
.BURST_MODE (BURST_MODE),
.COL_WIDTH (COL_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.ECC (ECC),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ROW_WIDTH (ROW_WIDTH))
bank_compare0
(/*AUTOINST*/
// Outputs
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_WIDTH-1:0]),
.req_periodic_rd_r (req_periodic_rd_r),
.req_size_r (req_size_r),
.rd_wr_r (rd_wr_r),
.req_rank_r (req_rank_r[RANK_WIDTH-1:0]),
.req_bank_r (req_bank_r[BANK_WIDTH-1:0]),
.req_row_r (req_row_r[ROW_WIDTH-1:0]),
.req_wr_r (req_wr_r),
.req_priority_r (req_priority_r),
.rb_hit_busy_r (rb_hit_busy_r),
.rb_hit_busy_ns (rb_hit_busy_ns),
.row_hit_r (row_hit_r),
.maint_hit (maint_hit),
.col_addr (col_addr[ROW_WIDTH-1:0]),
.req_ras (req_ras),
.req_cas (req_cas),
.row_cmd_wr (row_cmd_wr),
.row_addr (row_addr[ROW_WIDTH-1:0]),
.rank_busy_r (rank_busy_r[RANKS-1:0]),
// Inputs
.clk (clk),
.idle_ns (idle_ns),
.idle_r (idle_r),
.data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.periodic_rd_insert (periodic_rd_insert),
.size (size),
.cmd (cmd[2:0]),
.sending_col (sending_col),
.rank (rank[RANK_WIDTH-1:0]),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
.bank (bank[BANK_WIDTH-1:0]),
.row (row[ROW_WIDTH-1:0]),
.col (col[COL_WIDTH-1:0]),
.hi_priority (hi_priority),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.auto_pre_r (auto_pre_r),
.rd_half_rmw (rd_half_rmw),
.act_wait_r (act_wait_r));
mig_7series_v2_3_bank_state #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.CWL (CWL),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.ECC (ECC),
.ID (ID),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nOP_WAIT (nOP_WAIT),
.nRAS_CLKS (nRAS_CLKS),
.nRP (nRP),
.nRTP (nRTP),
.nRCD (nRCD),
.nWTP_CLKS (nWTP_CLKS),
.ORDERING (ORDERING),
.RANKS (RANKS),
.RANK_WIDTH (RANK_WIDTH),
.RAS_TIMER_WIDTH (RAS_TIMER_WIDTH),
.STARVE_LIMIT (STARVE_LIMIT))
bank_state0
(/*AUTOINST*/
// Outputs
.start_rcd (start_rcd),
.act_wait_r (act_wait_r),
.rd_half_rmw (rd_half_rmw),
.ras_timer_ns (ras_timer_ns[RAS_TIMER_WIDTH-1:0]),
.end_rtp (end_rtp),
.bank_wait_in_progress (bank_wait_in_progress),
.start_pre_wait (start_pre_wait),
.op_exit_req (op_exit_req),
.pre_wait_r (pre_wait_r),
.allow_auto_pre (allow_auto_pre),
.precharge_bm_end (precharge_bm_end),
.demand_act_priority (demand_act_priority),
.rts_row (rts_row),
.rts_pre (rts_pre),
.act_this_rank_r (act_this_rank_r[RANKS-1:0]),
.demand_priority (demand_priority),
.col_rdy_wr (col_rdy_wr),
.rts_col (rts_col),
.wr_this_rank_r (wr_this_rank_r[RANKS-1:0]),
.rd_this_rank_r (rd_this_rank_r[RANKS-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.bm_end (bm_end),
.pass_open_bank_r (pass_open_bank_r),
.sending_row (sending_row),
.sending_pre (sending_pre),
.rcv_open_bank (rcv_open_bank),
.sending_col (sending_col),
.rd_wr_r (rd_wr_r),
.req_wr_r (req_wr_r),
.rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_WIDTH-1:0]),
.phy_rddata_valid (phy_rddata_valid),
.rd_rmw (rd_rmw),
.ras_timer_ns_in (ras_timer_ns_in[(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0]),
.rb_hit_busies_r (rb_hit_busies_r[(nBANK_MACHS*2)-1:0]),
.idle_r (idle_r),
.passing_open_bank (passing_open_bank),
.low_idle_cnt_r (low_idle_cnt_r),
.op_exit_grant (op_exit_grant),
.tail_r (tail_r),
.auto_pre_r (auto_pre_r),
.pass_open_bank_ns (pass_open_bank_ns),
.phy_mc_cmd_full (phy_mc_cmd_full),
.phy_mc_ctl_full (phy_mc_ctl_full),
.phy_mc_data_full (phy_mc_data_full),
.rnk_config (rnk_config[RANK_WIDTH-1:0]),
.rnk_config_strobe (rnk_config_strobe),
.rnk_config_kill_rts_col (rnk_config_kill_rts_col),
.rnk_config_valid_r (rnk_config_valid_r),
.rtc (rtc),
.req_rank_r (req_rank_r[RANK_WIDTH-1:0]),
.req_rank_r_in (req_rank_r_in[(RANK_WIDTH*nBANK_MACHS*2)-1:0]),
.start_rcd_in (start_rcd_in[(nBANK_MACHS*2)-1:0]),
.inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]),
.wait_for_maint_r (wait_for_maint_r),
.head_r (head_r),
.sent_row (sent_row),
.demand_act_priority_in (demand_act_priority_in[(nBANK_MACHS*2)-1:0]),
.order_q_zero (order_q_zero),
.sent_col (sent_col),
.q_has_rd (q_has_rd),
.q_has_priority (q_has_priority),
.req_priority_r (req_priority_r),
.idle_ns (idle_ns),
.demand_priority_in (demand_priority_in[(nBANK_MACHS*2)-1:0]),
.inhbt_rd (inhbt_rd[RANKS-1:0]),
.inhbt_wr (inhbt_wr[RANKS-1:0]),
.dq_busy_data (dq_busy_data));
mig_7series_v2_3_bank_queue #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.nBANK_MACHS (nBANK_MACHS),
.ORDERING (ORDERING),
.ID (ID))
bank_queue0
(/*AUTOINST*/
// Outputs
.head_r (head_r),
.tail_r (tail_r),
.idle_ns (idle_ns),
.idle_r (idle_r),
.pass_open_bank_ns (pass_open_bank_ns),
.pass_open_bank_r (pass_open_bank_r),
.auto_pre_r (auto_pre_r),
.bm_end (bm_end),
.passing_open_bank (passing_open_bank),
.ordered_issued (ordered_issued),
.ordered_r (ordered_r),
.order_q_zero (order_q_zero),
.rcv_open_bank (rcv_open_bank),
.rb_hit_busies_r (rb_hit_busies_r[nBANK_MACHS*2-1:0]),
.q_has_rd (q_has_rd),
.q_has_priority (q_has_priority),
.wait_for_maint_r (wait_for_maint_r),
// Inputs
.clk (clk),
.rst (rst),
.accept_internal_r (accept_internal_r),
.use_addr (use_addr),
.periodic_rd_ack_r (periodic_rd_ack_r),
.bm_end_in (bm_end_in[(nBANK_MACHS*2)-1:0]),
.idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]),
.rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]),
.accept_req (accept_req),
.rb_hit_busy_r (rb_hit_busy_r),
.maint_idle (maint_idle),
.maint_hit (maint_hit),
.row_hit_r (row_hit_r),
.pre_wait_r (pre_wait_r),
.allow_auto_pre (allow_auto_pre),
.sending_col (sending_col),
.req_wr_r (req_wr_r),
.rd_wr_r (rd_wr_r),
.bank_wait_in_progress (bank_wait_in_progress),
.precharge_bm_end (precharge_bm_end),
.adv_order_q (adv_order_q),
.order_cnt (order_cnt[BM_CNT_WIDTH-1:0]),
.rb_hit_busy_ns_in (rb_hit_busy_ns_in[(nBANK_MACHS*2)-1:0]),
.passing_open_bank_in (passing_open_bank_in[(nBANK_MACHS*2)-1:0]),
.was_wr (was_wr),
.maint_req_r (maint_req_r),
.was_priority (was_priority));
endmodule // bank_cntrl
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module converts incoming ascii characters into their pixel *
* representation, which is suitable for output on a display, such as a *
* VGA-compatible monitor or LCD. *
* *
******************************************************************************/
module Computer_System_VGA_Subsystem_Char_Buf_Subsystem_ASCII_to_Image (
// Global Signals
clk,
reset,
// ASCII Character Stream (input stream)
ascii_in_channel,
ascii_in_data,
ascii_in_startofpacket,
ascii_in_endofpacket,
ascii_in_valid,
ascii_in_ready,
// Image Stream (output stream)
image_out_ready,
image_out_data,
image_out_startofpacket,
image_out_endofpacket,
image_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IDW = 7;
parameter ODW = 0;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Global Signals
input clk;
input reset;
// ASCII Character Stream (avalon stream - sink)
input [ 5: 0] ascii_in_channel;
input [IDW:0] ascii_in_data;
input ascii_in_startofpacket;
input ascii_in_endofpacket;
input ascii_in_valid;
output ascii_in_ready;
// Image Stream (avalon stream - source)
input image_out_ready;
output reg [ODW:0] image_out_data;
output reg image_out_startofpacket;
output reg image_out_endofpacket;
output reg image_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire rom_data;
// Internal Registers
reg internal_startofpacket;
reg internal_endofpacket;
reg internal_valid;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
image_out_data <= 'h0;
image_out_startofpacket <= 1'b0;
image_out_endofpacket <= 1'b0;
image_out_valid <= 1'b0;
end
else if (image_out_ready | ~image_out_valid)
begin
image_out_data <= rom_data;
image_out_startofpacket <= internal_startofpacket;
image_out_endofpacket <= internal_endofpacket;
image_out_valid <= internal_valid;
end
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
begin
internal_startofpacket <= 1'b0;
internal_endofpacket <= 1'b0;
internal_valid <= 1'b0;
end
else if (ascii_in_ready)
begin
internal_startofpacket <= ascii_in_startofpacket;
internal_endofpacket <= ascii_in_endofpacket;
internal_valid <= ascii_in_valid;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign ascii_in_ready = ~ascii_in_valid | image_out_ready | ~image_out_valid;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_video_ascii_rom_128 ASCII_Character_Rom (
// Global Signals
.clk (clk),
.clk_en (ascii_in_ready),
// Inputs
.character (ascii_in_data[ 6: 0]),
.x_coordinate (ascii_in_channel[ 2: 0]),
.y_coordinate (ascii_in_channel[ 5: 3]),
// Outputs
.character_data (rom_data)
);
endmodule
|
`timescale 1ns / 1ps
module AXI_DDR2(
// Common
input CLK, // system clock
input CLK_200MHZ, // 200MHZ
input RST, // active high system reset
// AXI-4 SLAVE Interface
input axi_awvalid,
output axi_awready,
input [32-1:0] axi_awaddr,
input [3-1:0] axi_awprot,
input axi_wvalid,
output axi_wready,
input [32-1:0] axi_wdata,
input [4-1:0] axi_wstrb,
output axi_bvalid,
input axi_bready,
input axi_arvalid,
output axi_arready,
input [32-1:0] axi_araddr,
input [3-1:0] axi_arprot,
output axi_rvalid,
input axi_rready,
output [32-1:0] axi_rdata,
// DDR2 interface
output [12:0] ddr2_addr,
output [2:0] ddr2_ba,
output ddr2_ras_n,
output ddr2_cas_n,
output ddr2_we_n,
output [0:0] ddr2_ck_p,
output [0:0] ddr2_ck_n,
output [0:0] ddr2_cke,
output [0:0] ddr2_cs_n,
output [1:0] ddr2_dm,
output [0:0] ddr2_odt,
inout [15:0] ddr2_dq,
inout [1:0] ddr2_dqs_p,
inout [1:0] ddr2_dqs_n
);
wire mem_init_calib_complete;
wire mem_ui_clk;
wire axi_wready_int;
wire axi_awready_int;
wire axi_rvalid_int;
wire axi_bvalid_int;
wire axi_arready_int;
assign axi_wready = mem_ui_rst?1'b0:(mem_init_calib_complete? axi_wready_int : 1'b0 );
assign axi_awready = mem_ui_rst?1'b0:(mem_init_calib_complete? axi_awready_int : 1'b0);
assign axi_rvalid = mem_ui_rst?1'b0:(mem_init_calib_complete? axi_rvalid_int : 1'b0);
assign axi_bvalid = mem_ui_rst?1'b0:(mem_init_calib_complete? axi_bvalid_int : 1'b0);
assign axi_arready = mem_ui_rst?1'b0:(mem_init_calib_complete? axi_arready_int : 1'b0);
ddr_axi Inst_DDR_AXI (
.ddr2_dq (ddr2_dq),
.ddr2_dqs_p (ddr2_dqs_p),
.ddr2_dqs_n (ddr2_dqs_n),
.ddr2_addr (ddr2_addr),
.ddr2_ba (ddr2_ba),
.ddr2_ras_n (ddr2_ras_n),
.ddr2_cas_n (ddr2_cas_n),
.ddr2_we_n (ddr2_we_n),
.ddr2_ck_p (ddr2_ck_p),
.ddr2_ck_n (ddr2_ck_n),
.ddr2_cke (ddr2_cke),
.ddr2_cs_n (ddr2_cs_n),
.ddr2_dm (ddr2_dm),
.ddr2_odt (ddr2_odt),
//-- Inputs
.sys_clk_i (CLK_200MHZ),
.sys_rst (RST),
//-- user interface signals
/*.app_addr (mem_addr),
.app_cmd (mem_cmd),
.app_en (mem_en),
.app_wdf_data (mem_wdf_data),
.app_wdf_end (mem_wdf_end),
.app_wdf_mask (mem_wdf_mask),
.app_wdf_wren (mem_wdf_wren),
.app_rd_data (mem_rd_data),
.app_rd_data_end (mem_rd_data_end),
.app_rd_data_valid (mem_rd_data_valid),
.app_rdy (mem_rdy),
.app_wdf_rdy (mem_wdf_rdy),*/
.app_sr_req (1'b0),
//.app_sr_active (open),
.app_ref_req (1'b0),
// .app_ref_ack (open),
.app_zq_req (1'b0),
// .app_zq_ack (open),
.ui_clk (mem_ui_clk),
.ui_clk_sync_rst (mem_ui_rst),
.device_temp_i (12'b000000000000),
.init_calib_complete (mem_init_calib_complete),
// .user .interface .signals
//.mmcm_locked, // IDK
.aresetn(RST),
// .Slave .Interface .Write .Address .Ports
.s_axi_awid(0),
.s_axi_awaddr(axi_awaddr),
.s_axi_awlen(0),
.s_axi_awsize(2),
.s_axi_awburst(0),
.s_axi_awlock(0),
.s_axi_awcache(0),
.s_axi_awprot(axi_awprot),
.s_axi_awqos(0),
.s_axi_awvalid(axi_awvalid),
.s_axi_awready(axi_awready_int),
// .Slave .Interface .Write .Data .Ports
.s_axi_wdata(axi_wdata),
.s_axi_wstrb(axi_wstrb),
.s_axi_wlast(1),
.s_axi_wvalid(axi_wvalid),
.s_axi_wready(axi_wready_int),
// .Slave .Interface .Write .Response .Ports
.s_axi_bready(axi_bready),
//.s_axi_bid(0),
//.s_axi_bresp(0),
.s_axi_bvalid(axi_bvalid_int),
// .Slave .Interface .Read .Address .Ports
.s_axi_arid(0),
.s_axi_araddr(axi_araddr),
.s_axi_arlen(0),
.s_axi_arsize(2),
.s_axi_arburst(0),
.s_axi_arlock(0),
.s_axi_arcache(0),
.s_axi_arprot(axi_arprot),
.s_axi_arqos(0),
.s_axi_arvalid(axi_arvalid),
.s_axi_arready(axi_arready_int),
// .Slave .Interface .Read .Data .Ports
.s_axi_rready(axi_rready),
//.s_axi_rid(0),
.s_axi_rdata(axi_rdata),
//.s_axi_rresp(0),
//.s_axi_rlast(1),
.s_axi_rvalid(axi_rvalid_int));
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2015 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: ogfx_ram_arbiter.v
//
// *Module Description:
// RAM arbiter for LUT and VIDEO memories
// LUT-RAM arbitration:
//
// - Software interface: fixed highest priority
// - Refresh interface: fixed lowest priority
//
// Video-RAM arbitration:
//
// - Software interface: fixed highest priority
// - Refresh interface: round-robin with GPIO if
// - GPU interface: round-robin with Refresh if
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`ifdef OGFX_NO_INCLUDE
`else
`include "openGFX430_defines.v"
`endif
module ogfx_ram_arbiter (
mclk, // Main system clock
puc_rst, // Main system reset
//------------------------------------------------------------
// SW interface, fixed highest priority
lut_ram_sw_addr_i, // LUT-RAM Software address
lut_ram_sw_din_i, // LUT-RAM Software data
lut_ram_sw_wen_i, // LUT-RAM Software write strobe (active low)
lut_ram_sw_cen_i, // LUT-RAM Software chip enable (active low)
lut_ram_sw_dout_o, // LUT-RAM Software data input
// Refresh-backend, fixed lowest priority
lut_ram_refr_addr_i, // LUT-RAM Refresh address
lut_ram_refr_din_i, // LUT-RAM Refresh data
lut_ram_refr_wen_i, // LUT-RAM Refresh write strobe (active low)
lut_ram_refr_cen_i, // LUT-RAM Refresh enable (active low)
lut_ram_refr_dout_o, // LUT-RAM Refresh data output
lut_ram_refr_dout_rdy_nxt_o, // LUT-RAM Refresh data output ready during next cycle
// LUT Memory interface
lut_ram_addr_o, // LUT-RAM address
lut_ram_din_o, // LUT-RAM data
lut_ram_wen_o, // LUT-RAM write strobe (active low)
lut_ram_cen_o, // LUT-RAM chip enable (active low)
lut_ram_dout_i, // LUT-RAM data input
//------------------------------------------------------------
// SW interface, fixed highest priority
vid_ram_sw_addr_i, // Video-RAM Software address
vid_ram_sw_din_i, // Video-RAM Software data
vid_ram_sw_wen_i, // Video-RAM Software write strobe (active low)
vid_ram_sw_cen_i, // Video-RAM Software chip enable (active low)
vid_ram_sw_dout_o, // Video-RAM Software data input
// GPU interface (round-robin with refresh-backend)
vid_ram_gpu_addr_i, // Video-RAM GPU address
vid_ram_gpu_din_i, // Video-RAM GPU data
vid_ram_gpu_wen_i, // Video-RAM GPU write strobe (active low)
vid_ram_gpu_cen_i, // Video-RAM GPU chip enable (active low)
vid_ram_gpu_dout_o, // Video-RAM GPU data input
vid_ram_gpu_dout_rdy_nxt_o, // Video-RAM GPU data output ready during next cycle
// Refresh-backend (round-robin with GPU interface)
vid_ram_refr_addr_i, // Video-RAM Refresh address
vid_ram_refr_din_i, // Video-RAM Refresh data
vid_ram_refr_wen_i, // Video-RAM Refresh write strobe (active low)
vid_ram_refr_cen_i, // Video-RAM Refresh enable (active low)
vid_ram_refr_dout_o, // Video-RAM Refresh data output
vid_ram_refr_dout_rdy_nxt_o, // Video-RAM Refresh data output ready during next cycle
// Video Memory interface
vid_ram_addr_o, // Video-RAM address
vid_ram_din_o, // Video-RAM data
vid_ram_wen_o, // Video-RAM write strobe (active low)
vid_ram_cen_o, // Video-RAM chip enable (active low)
vid_ram_dout_i // Video-RAM data input
//------------------------------------------------------------
);
// CLOCK/RESET
//=============
input mclk; // Main system clock
input puc_rst; // Main system reset
// LUT MEMORY
//=============
// SW interface, fixed highest priority
input [`LRAM_MSB:0] lut_ram_sw_addr_i; // LUT-RAM Software address
input [15:0] lut_ram_sw_din_i; // LUT-RAM Software data
input lut_ram_sw_wen_i; // LUT-RAM Software write strobe (active low)
input lut_ram_sw_cen_i; // LUT-RAM Software chip enable (active low)
output [15:0] lut_ram_sw_dout_o; // LUT-RAM Software data input
// Refresh-backend, fixed lowest priority
input [`LRAM_MSB:0] lut_ram_refr_addr_i; // LUT-RAM Refresh address
input [15:0] lut_ram_refr_din_i; // LUT-RAM Refresh data
input lut_ram_refr_wen_i; // LUT-RAM Refresh write strobe (active low)
input lut_ram_refr_cen_i; // LUT-RAM Refresh enable (active low)
output [15:0] lut_ram_refr_dout_o; // LUT-RAM Refresh data output
output lut_ram_refr_dout_rdy_nxt_o; // LUT-RAM Refresh data output ready during next cycle
// LUT Memory interface
output [`LRAM_MSB:0] lut_ram_addr_o; // LUT-RAM address
output [15:0] lut_ram_din_o; // LUT-RAM data
output lut_ram_wen_o; // LUT-RAM write strobe (active low)
output lut_ram_cen_o; // LUT-RAM chip enable (active low)
input [15:0] lut_ram_dout_i; // LUT-RAM data input
// VIDEO MEMORY
//==============
// SW interface, fixed highest priority
input [`VRAM_MSB:0] vid_ram_sw_addr_i; // Video-RAM Software address
input [15:0] vid_ram_sw_din_i; // Video-RAM Software data
input vid_ram_sw_wen_i; // Video-RAM Software write strobe (active low)
input vid_ram_sw_cen_i; // Video-RAM Software chip enable (active low)
output [15:0] vid_ram_sw_dout_o; // Video-RAM Software data input
// GPU interface (round-robin with refresh-backend)
input [`VRAM_MSB:0] vid_ram_gpu_addr_i; // Video-RAM GPU address
input [15:0] vid_ram_gpu_din_i; // Video-RAM GPU data
input vid_ram_gpu_wen_i; // Video-RAM GPU write strobe (active low)
input vid_ram_gpu_cen_i; // Video-RAM GPU chip enable (active low)
output [15:0] vid_ram_gpu_dout_o; // Video-RAM GPU data input
output vid_ram_gpu_dout_rdy_nxt_o; // Video-RAM GPU data output ready during next cycle
// Refresh-backend (round-robin with GPU interface)
input [`VRAM_MSB:0] vid_ram_refr_addr_i; // Video-RAM Refresh address
input [15:0] vid_ram_refr_din_i; // Video-RAM Refresh data
input vid_ram_refr_wen_i; // Video-RAM Refresh write strobe (active low)
input vid_ram_refr_cen_i; // Video-RAM Refresh enable (active low)
output [15:0] vid_ram_refr_dout_o; // Video-RAM Refresh data output
output vid_ram_refr_dout_rdy_nxt_o; // Video-RAM Refresh data output ready during next cycle
// Video Memory interface
output [`VRAM_MSB:0] vid_ram_addr_o; // Video-RAM address
output [15:0] vid_ram_din_o; // Video-RAM data
output vid_ram_wen_o; // Video-RAM write strobe (active low)
output vid_ram_cen_o; // Video-RAM chip enable (active low)
input [15:0] vid_ram_dout_i; // Video-RAM data input
//=============================================================================
// 1) WIRE, REGISTERS AND PARAMETER DECLARATION
//=============================================================================
reg gpu_is_last_owner;
//=============================================================================
// 2) LUT MEMORY ARBITER
//=============================================================================
// Arbitration signals
wire sw_lram_access_granted = ~lut_ram_sw_cen_i;
wire refr_lram_access_granted = ~sw_lram_access_granted & ~lut_ram_refr_cen_i;
// LUT RAM signal muxing
assign lut_ram_sw_dout_o = lut_ram_dout_i;
assign lut_ram_refr_dout_o = lut_ram_dout_i;
assign lut_ram_refr_dout_rdy_nxt_o = refr_lram_access_granted;
assign lut_ram_addr_o = ({`LRAM_AWIDTH{ sw_lram_access_granted }} & lut_ram_sw_addr_i ) |
({`LRAM_AWIDTH{ refr_lram_access_granted}} & lut_ram_refr_addr_i) ;
assign lut_ram_din_o = ({ 16{ sw_lram_access_granted }} & lut_ram_sw_din_i ) |
({ 16{ refr_lram_access_granted}} & lut_ram_refr_din_i ) ;
assign lut_ram_wen_o = ( ~sw_lram_access_granted | lut_ram_sw_wen_i ) &
( ~refr_lram_access_granted | lut_ram_refr_wen_i ) ;
assign lut_ram_cen_o = lut_ram_sw_cen_i & lut_ram_refr_cen_i;
//=============================================================================
// 3) VIDEO MEMORY ARBITER
//=============================================================================
// Arbitration signals
wire sw_vram_access_granted = ~vid_ram_sw_cen_i;
wire gpu_vram_access_granted = ~sw_vram_access_granted & // No SW access
((~vid_ram_gpu_cen_i & vid_ram_refr_cen_i) | // GPU requests alone
(~vid_ram_gpu_cen_i & ~vid_ram_refr_cen_i & ~gpu_is_last_owner)) ; // GPU & REFR both requests (arbitration required)
wire refr_vram_access_granted = ~sw_vram_access_granted & // No SW access
(( vid_ram_gpu_cen_i & ~vid_ram_refr_cen_i) | // GPU requests alone
(~vid_ram_gpu_cen_i & ~vid_ram_refr_cen_i & gpu_is_last_owner)) ; // GPU & REFR both requests (arbitration required)
// Detect who was the last to own the RAM between the GPU and Refresh interface
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) gpu_is_last_owner <= 1'b0;
else if (gpu_vram_access_granted ) gpu_is_last_owner <= 1'b1;
else if (refr_vram_access_granted) gpu_is_last_owner <= 1'b0;
// Video RAM signal muxing
assign vid_ram_sw_dout_o = vid_ram_dout_i;
assign vid_ram_gpu_dout_o = vid_ram_dout_i;
assign vid_ram_gpu_dout_rdy_nxt_o = gpu_vram_access_granted;
assign vid_ram_refr_dout_o = vid_ram_dout_i;
assign vid_ram_refr_dout_rdy_nxt_o = refr_vram_access_granted;
assign vid_ram_addr_o = ({`VRAM_AWIDTH{ sw_vram_access_granted }} & vid_ram_sw_addr_i ) |
({`VRAM_AWIDTH{ gpu_vram_access_granted }} & vid_ram_gpu_addr_i ) |
({`VRAM_AWIDTH{ refr_vram_access_granted}} & vid_ram_refr_addr_i) ;
assign vid_ram_din_o = ({ 16{ sw_vram_access_granted }} & vid_ram_sw_din_i ) |
({ 16{ gpu_vram_access_granted }} & vid_ram_gpu_din_i ) |
({ 16{ refr_vram_access_granted}} & vid_ram_refr_din_i ) ;
assign vid_ram_wen_o = ( ~sw_vram_access_granted | vid_ram_sw_wen_i ) &
( ~gpu_vram_access_granted | vid_ram_gpu_wen_i ) &
( ~refr_vram_access_granted | vid_ram_refr_wen_i ) ;
assign vid_ram_cen_o = vid_ram_sw_cen_i & vid_ram_gpu_cen_i & vid_ram_refr_cen_i;
endmodule // ogfx_ram_arbiter
`ifdef OGFX_NO_INCLUDE
`else
`include "openGFX430_undefines.v"
`endif
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_read_datapath(
ck,
reset_n,
check_do,
check_dm,
check_do_lfsr,
check_dm_lfsr,
check_pattern_push,
clear_error,
read_data,
read_data_valid,
error_word
);
parameter DATA_WIDTH = "";
parameter AFI_RATIO = "";
localparam NUMBER_OF_WORDS = 2 * AFI_RATIO;
localparam DATA_BUS_SIZE = DATA_WIDTH * NUMBER_OF_WORDS;
input ck;
input reset_n;
input [3:0] check_do;
input [2:0] check_dm;
input check_do_lfsr;
input check_dm_lfsr;
input check_pattern_push;
input clear_error;
input [DATA_BUS_SIZE - 1 : 0] read_data;
input read_data_valid;
output [DATA_WIDTH - 1 : 0] error_word;
reg [4:0] pattern_radd;
reg [4:0] pattern_wadd;
wire [4:0] pattern_radd_next;
wire [8:0] check_word_write = { check_do, check_dm, check_do_lfsr, check_dm_lfsr };
wire [8:0] check_word_read;
wire [3:0] check_do_read = check_word_read[8:5];
wire [2:0] check_dm_read = check_word_read[4:2];
wire check_do_lfsr_read = check_word_read[1];
wire check_dm_lfsr_read = check_word_read[0];
wire [DATA_BUS_SIZE - 1 : 0] do_data;
wire [NUMBER_OF_WORDS - 1 : 0] dm_data;
wire do_lfsr_step = check_do_lfsr_read & read_data_valid;
wire dm_lfsr_step = check_dm_lfsr_read & read_data_valid;
rw_manager_bitcheck bitcheck_i(
.ck(ck),
.reset_n(reset_n),
.clear(clear_error),
.enable(read_data_valid),
.read_data(read_data),
.reference_data(do_data),
.mask(dm_data),
.error_word(error_word)
);
defparam bitcheck_i.DATA_WIDTH = DATA_WIDTH;
defparam bitcheck_i.AFI_RATIO = AFI_RATIO;
rw_manager_write_decoder write_decoder_i(
.ck(ck),
.reset_n(reset_n),
.do_lfsr(check_do_lfsr_read),
.dm_lfsr(check_dm_lfsr_read),
.do_lfsr_step(do_lfsr_step),
.dm_lfsr_step(dm_lfsr_step),
.do_code(check_do_read),
.dm_code(check_dm_read),
.do_data(do_data),
.dm_data(dm_data)
);
defparam write_decoder_i.DATA_WIDTH = DATA_WIDTH;
defparam write_decoder_i.AFI_RATIO = AFI_RATIO;
rw_manager_pattern_fifo pattern_fifo_i(
.clock(ck),
.data(check_word_write),
.rdaddress(pattern_radd_next),
.wraddress(pattern_wadd),
.wren(check_pattern_push),
.q(check_word_read)
);
assign pattern_radd_next = pattern_radd + (read_data_valid ? 1'b1 : 1'b0);
always @(posedge ck or negedge reset_n) begin
if(~reset_n) begin
pattern_radd <= 5'b00000;
pattern_wadd <= 5'b00000;
end
else begin
if (clear_error) begin
pattern_radd <= 5'b00000;
pattern_wadd <= 5'b00000;
end else begin
if(read_data_valid) begin
pattern_radd <= pattern_radd + 1'b1;
end
if(check_pattern_push) begin
pattern_wadd <= pattern_wadd + 1'b1;
end
end
end
end
endmodule
|
// megafunction wizard: %ALTFP_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTFP_MULT
// ============================================================
// File Name: acl_fp_mul_fast_double.v
// Megafunction Name(s):
// ALTFP_MULT
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altfp_mult CBX_AUTO_BLACKBOX="ALL" DEDICATED_MULTIPLIER_CIRCUITRY="YES" DENORMAL_SUPPORT="NO" DEVICE_FAMILY="Stratix IV" EXCEPTION_HANDLING="NO" PIPELINE=10 REDUCED_FUNCTIONALITY="NO" ROUNDING="TO_NEAREST" WIDTH_EXP=11 WIDTH_MAN=52 clk_en clock dataa datab result
//VERSION_BEGIN 11.0 cbx_alt_ded_mult_y 2011:04:27:21:05:53:SJ cbx_altbarrel_shift 2011:04:27:21:05:53:SJ cbx_altera_mult_add 2011:04:27:21:05:53:SJ cbx_altfp_mult 2011:04:27:21:05:53:SJ cbx_altmult_add 2011:04:27:21:05:53:SJ cbx_cycloneii 2011:04:27:21:05:53:SJ cbx_lpm_add_sub 2011:04:27:21:05:53:SJ cbx_lpm_compare 2011:04:27:21:05:53:SJ cbx_lpm_counter 2011:04:27:21:05:53:SJ cbx_lpm_decode 2011:04:27:21:05:53:SJ cbx_lpm_mult 2011:04:27:21:05:53:SJ cbx_mgl 2011:04:27:21:20:02:SJ cbx_padd 2011:04:27:21:05:53:SJ cbx_parallel_add 2011:04:27:21:05:53:SJ cbx_stratix 2011:04:27:21:05:53:SJ cbx_stratixii 2011:04:27:21:05:53:SJ cbx_stratixiii 2011:04:27:21:05:53:SJ cbx_stratixv 2011:04:27:21:05:53:SJ cbx_util_mgl 2011:04:27:21:05:53:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = lpm_add_sub 4 lpm_mult 1 reg 426
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_mul_fast_double_altfp_mult_ufo
(
clk_en,
clock,
dataa,
datab,
result) ;
input clk_en;
input clock;
input [63:0] dataa;
input [63:0] datab;
output [63:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg dataa_exp_all_one_ff_p1;
reg dataa_exp_not_zero_ff_p1;
reg dataa_man_not_zero_ff_p1;
reg dataa_man_not_zero_ff_p2;
reg datab_exp_all_one_ff_p1;
reg datab_exp_not_zero_ff_p1;
reg datab_man_not_zero_ff_p1;
reg datab_man_not_zero_ff_p2;
reg [12:0] delay_exp2_bias;
reg [12:0] delay_exp3_bias;
reg [12:0] delay_exp_bias;
reg delay_man_product_msb;
reg delay_man_product_msb2;
reg delay_man_product_msb_p0;
reg [52:0] delay_round;
reg [11:0] exp_add_p1;
reg [12:0] exp_adj_p1;
reg [12:0] exp_adj_p2;
reg [11:0] exp_bias_p1;
reg [11:0] exp_bias_p2;
reg [10:0] exp_result_ff;
reg input_is_infinity_dffe_0;
reg input_is_infinity_dffe_1;
reg input_is_infinity_dffe_2;
reg input_is_infinity_dffe_3;
reg input_is_infinity_ff1;
reg input_is_infinity_ff2;
reg input_is_infinity_ff3;
reg input_is_infinity_ff4;
reg input_is_nan_dffe_0;
reg input_is_nan_dffe_1;
reg input_is_nan_dffe_2;
reg input_is_nan_dffe_3;
reg input_is_nan_ff1;
reg input_is_nan_ff2;
reg input_is_nan_ff3;
reg input_is_nan_ff4;
reg input_not_zero_dffe_0;
reg input_not_zero_dffe_1;
reg input_not_zero_dffe_2;
reg input_not_zero_dffe_3;
reg input_not_zero_ff1;
reg input_not_zero_ff2;
reg input_not_zero_ff3;
reg input_not_zero_ff4;
reg lsb_dffe;
reg [51:0] man_result_ff;
reg man_round_carry_p0;
reg [52:0] man_round_p;
reg [52:0] man_round_p0;
reg [53:0] man_round_p2;
reg round_dffe;
reg [0:0] sign_node_ff0;
reg [0:0] sign_node_ff1;
reg [0:0] sign_node_ff2;
reg [0:0] sign_node_ff3;
reg [0:0] sign_node_ff4;
reg [0:0] sign_node_ff5;
reg [0:0] sign_node_ff6;
reg [0:0] sign_node_ff7;
reg [0:0] sign_node_ff8;
reg [0:0] sign_node_ff9;
reg sticky_dffe;
wire [11:0] wire_exp_add_adder_result;
wire [12:0] wire_exp_adj_adder_result;
wire [12:0] wire_exp_bias_subtr_result;
wire [53:0] wire_man_round_adder_result;
wire [105:0] wire_man_product2_mult_result;
wire aclr;
wire [12:0] bias;
wire [10:0] dataa_exp_all_one;
wire [10:0] dataa_exp_not_zero;
wire [51:0] dataa_man_not_zero;
wire [10:0] datab_exp_all_one;
wire [10:0] datab_exp_not_zero;
wire [51:0] datab_man_not_zero;
wire exp_is_inf;
wire exp_is_zero;
wire [12:0] expmod;
wire [10:0] inf_num;
wire lsb_bit;
wire [53:0] man_shift_full;
wire [10:0] result_exp_all_one;
wire [11:0] result_exp_not_zero;
wire round_bit;
wire round_carry;
wire [51:0] sticky_bit;
// synopsys translate_off
initial
dataa_exp_all_one_ff_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dataa_exp_all_one_ff_p1 <= 1'b0;
else if (clk_en == 1'b1) dataa_exp_all_one_ff_p1 <= dataa_exp_all_one[10];
// synopsys translate_off
initial
dataa_exp_not_zero_ff_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dataa_exp_not_zero_ff_p1 <= 1'b0;
else if (clk_en == 1'b1) dataa_exp_not_zero_ff_p1 <= dataa_exp_not_zero[10];
// synopsys translate_off
initial
dataa_man_not_zero_ff_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dataa_man_not_zero_ff_p1 <= 1'b0;
else if (clk_en == 1'b1) dataa_man_not_zero_ff_p1 <= dataa_man_not_zero[25];
// synopsys translate_off
initial
dataa_man_not_zero_ff_p2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dataa_man_not_zero_ff_p2 <= 1'b0;
else if (clk_en == 1'b1) dataa_man_not_zero_ff_p2 <= dataa_man_not_zero[51];
// synopsys translate_off
initial
datab_exp_all_one_ff_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) datab_exp_all_one_ff_p1 <= 1'b0;
else if (clk_en == 1'b1) datab_exp_all_one_ff_p1 <= datab_exp_all_one[10];
// synopsys translate_off
initial
datab_exp_not_zero_ff_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) datab_exp_not_zero_ff_p1 <= 1'b0;
else if (clk_en == 1'b1) datab_exp_not_zero_ff_p1 <= datab_exp_not_zero[10];
// synopsys translate_off
initial
datab_man_not_zero_ff_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) datab_man_not_zero_ff_p1 <= 1'b0;
else if (clk_en == 1'b1) datab_man_not_zero_ff_p1 <= datab_man_not_zero[25];
// synopsys translate_off
initial
datab_man_not_zero_ff_p2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) datab_man_not_zero_ff_p2 <= 1'b0;
else if (clk_en == 1'b1) datab_man_not_zero_ff_p2 <= datab_man_not_zero[51];
// synopsys translate_off
initial
delay_exp2_bias = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) delay_exp2_bias <= 13'b0;
else if (clk_en == 1'b1) delay_exp2_bias <= delay_exp_bias;
// synopsys translate_off
initial
delay_exp3_bias = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) delay_exp3_bias <= 13'b0;
else if (clk_en == 1'b1) delay_exp3_bias <= delay_exp2_bias;
// synopsys translate_off
initial
delay_exp_bias = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) delay_exp_bias <= 13'b0;
else if (clk_en == 1'b1) delay_exp_bias <= wire_exp_bias_subtr_result;
// synopsys translate_off
initial
delay_man_product_msb = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) delay_man_product_msb <= 1'b0;
else if (clk_en == 1'b1) delay_man_product_msb <= delay_man_product_msb_p0;
// synopsys translate_off
initial
delay_man_product_msb2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) delay_man_product_msb2 <= 1'b0;
else if (clk_en == 1'b1) delay_man_product_msb2 <= delay_man_product_msb;
// synopsys translate_off
initial
delay_man_product_msb_p0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) delay_man_product_msb_p0 <= 1'b0;
else if (clk_en == 1'b1) delay_man_product_msb_p0 <= wire_man_product2_mult_result[105];
// synopsys translate_off
initial
delay_round = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) delay_round <= 53'b0;
else if (clk_en == 1'b1) delay_round <= ((man_round_p2[52:0] & {53{(~ man_round_p2[53])}}) | (man_round_p2[53:1] & {53{man_round_p2[53]}}));
// synopsys translate_off
initial
exp_add_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_add_p1 <= 12'b0;
else if (clk_en == 1'b1) exp_add_p1 <= wire_exp_add_adder_result;
// synopsys translate_off
initial
exp_adj_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_adj_p1 <= 13'b0;
else if (clk_en == 1'b1) exp_adj_p1 <= delay_exp3_bias;
// synopsys translate_off
initial
exp_adj_p2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_adj_p2 <= 13'b0;
else if (clk_en == 1'b1) exp_adj_p2 <= wire_exp_adj_adder_result;
// synopsys translate_off
initial
exp_bias_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_bias_p1 <= 12'b0;
else if (clk_en == 1'b1) exp_bias_p1 <= exp_add_p1[11:0];
// synopsys translate_off
initial
exp_bias_p2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_bias_p2 <= 12'b0;
else if (clk_en == 1'b1) exp_bias_p2 <= exp_bias_p1;
// synopsys translate_off
initial
exp_result_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_ff <= 11'b0;
else if (clk_en == 1'b1) exp_result_ff <= ((inf_num & {11{((exp_is_inf | input_is_infinity_ff4) | input_is_nan_ff4)}}) | ((exp_adj_p2[10:0] & {11{(~ exp_is_zero)}}) & {11{input_not_zero_ff4}}));
// synopsys translate_off
initial
input_is_infinity_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_dffe_0 <= ((dataa_exp_all_one_ff_p1 & (~ (dataa_man_not_zero_ff_p1 | dataa_man_not_zero_ff_p2))) | (datab_exp_all_one_ff_p1 & (~ (datab_man_not_zero_ff_p1 | datab_man_not_zero_ff_p2))));
// synopsys translate_off
initial
input_is_infinity_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_dffe_1 <= input_is_infinity_dffe_0;
// synopsys translate_off
initial
input_is_infinity_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_dffe_2 <= input_is_infinity_dffe_1;
// synopsys translate_off
initial
input_is_infinity_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_dffe_3 <= input_is_infinity_dffe_2;
// synopsys translate_off
initial
input_is_infinity_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_ff1 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_ff1 <= input_is_infinity_dffe_3;
// synopsys translate_off
initial
input_is_infinity_ff2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_ff2 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_ff2 <= input_is_infinity_ff1;
// synopsys translate_off
initial
input_is_infinity_ff3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_ff3 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_ff3 <= input_is_infinity_ff2;
// synopsys translate_off
initial
input_is_infinity_ff4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_ff4 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_ff4 <= input_is_infinity_ff3;
// synopsys translate_off
initial
input_is_nan_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe_0 <= ((dataa_exp_all_one_ff_p1 & (dataa_man_not_zero_ff_p1 | dataa_man_not_zero_ff_p2)) | (datab_exp_all_one_ff_p1 & (datab_man_not_zero_ff_p1 | datab_man_not_zero_ff_p2)));
// synopsys translate_off
initial
input_is_nan_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe_1 <= input_is_nan_dffe_0;
// synopsys translate_off
initial
input_is_nan_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe_2 <= input_is_nan_dffe_1;
// synopsys translate_off
initial
input_is_nan_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe_3 <= input_is_nan_dffe_2;
// synopsys translate_off
initial
input_is_nan_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_ff1 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_ff1 <= input_is_nan_dffe_3;
// synopsys translate_off
initial
input_is_nan_ff2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_ff2 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_ff2 <= input_is_nan_ff1;
// synopsys translate_off
initial
input_is_nan_ff3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_ff3 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_ff3 <= input_is_nan_ff2;
// synopsys translate_off
initial
input_is_nan_ff4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_ff4 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_ff4 <= input_is_nan_ff3;
// synopsys translate_off
initial
input_not_zero_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_not_zero_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) input_not_zero_dffe_0 <= (dataa_exp_not_zero_ff_p1 & datab_exp_not_zero_ff_p1);
// synopsys translate_off
initial
input_not_zero_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_not_zero_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) input_not_zero_dffe_1 <= input_not_zero_dffe_0;
// synopsys translate_off
initial
input_not_zero_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_not_zero_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) input_not_zero_dffe_2 <= input_not_zero_dffe_1;
// synopsys translate_off
initial
input_not_zero_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_not_zero_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) input_not_zero_dffe_3 <= input_not_zero_dffe_2;
// synopsys translate_off
initial
input_not_zero_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_not_zero_ff1 <= 1'b0;
else if (clk_en == 1'b1) input_not_zero_ff1 <= input_not_zero_dffe_3;
// synopsys translate_off
initial
input_not_zero_ff2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_not_zero_ff2 <= 1'b0;
else if (clk_en == 1'b1) input_not_zero_ff2 <= input_not_zero_ff1;
// synopsys translate_off
initial
input_not_zero_ff3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_not_zero_ff3 <= 1'b0;
else if (clk_en == 1'b1) input_not_zero_ff3 <= input_not_zero_ff2;
// synopsys translate_off
initial
input_not_zero_ff4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_not_zero_ff4 <= 1'b0;
else if (clk_en == 1'b1) input_not_zero_ff4 <= input_not_zero_ff3;
// synopsys translate_off
initial
lsb_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lsb_dffe <= 1'b0;
else if (clk_en == 1'b1) lsb_dffe <= lsb_bit;
// synopsys translate_off
initial
man_result_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_result_ff <= 52'b0;
else if (clk_en == 1'b1) man_result_ff <= {((((((delay_round[51] & input_not_zero_ff4) & (~ input_is_infinity_ff4)) & (~ exp_is_inf)) & (~ exp_is_zero)) | (input_is_infinity_ff4 & (~ input_not_zero_ff4))) | input_is_nan_ff4), (((((delay_round[50:0] & {51{input_not_zero_ff4}}) & {51{(~ input_is_infinity_ff4)}}) & {51{(~ exp_is_inf)}}) & {51{(~ exp_is_zero)}}) & {51{(~ input_is_nan_ff4)}})};
// synopsys translate_off
initial
man_round_carry_p0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_round_carry_p0 <= 1'b0;
else if (clk_en == 1'b1) man_round_carry_p0 <= round_carry;
// synopsys translate_off
initial
man_round_p = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_round_p <= 53'b0;
else if (clk_en == 1'b1) man_round_p <= man_shift_full[53:1];
// synopsys translate_off
initial
man_round_p0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_round_p0 <= 53'b0;
else if (clk_en == 1'b1) man_round_p0 <= man_round_p;
// synopsys translate_off
initial
man_round_p2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_round_p2 <= 54'b0;
else if (clk_en == 1'b1) man_round_p2 <= wire_man_round_adder_result;
// synopsys translate_off
initial
round_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) round_dffe <= 1'b0;
else if (clk_en == 1'b1) round_dffe <= round_bit;
// synopsys translate_off
initial
sign_node_ff0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff0 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff0 <= (dataa[63] ^ datab[63]);
// synopsys translate_off
initial
sign_node_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff1 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff1 <= sign_node_ff0[0:0];
// synopsys translate_off
initial
sign_node_ff2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff2 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff2 <= sign_node_ff1[0:0];
// synopsys translate_off
initial
sign_node_ff3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff3 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff3 <= sign_node_ff2[0:0];
// synopsys translate_off
initial
sign_node_ff4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff4 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff4 <= sign_node_ff3[0:0];
// synopsys translate_off
initial
sign_node_ff5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff5 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff5 <= sign_node_ff4[0:0];
// synopsys translate_off
initial
sign_node_ff6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff6 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff6 <= sign_node_ff5[0:0];
// synopsys translate_off
initial
sign_node_ff7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff7 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff7 <= sign_node_ff6[0:0];
// synopsys translate_off
initial
sign_node_ff8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff8 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff8 <= sign_node_ff7[0:0];
// synopsys translate_off
initial
sign_node_ff9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff9 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff9 <= sign_node_ff8[0:0];
// synopsys translate_off
initial
sticky_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sticky_dffe <= 1'b0;
else if (clk_en == 1'b1) sticky_dffe <= sticky_bit[51];
lpm_add_sub exp_add_adder
(
.aclr(aclr),
.cin(1'b0),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa({1'b0, dataa[62:52]}),
.datab({1'b0, datab[62:52]}),
.overflow(),
.result(wire_exp_add_adder_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
exp_add_adder.lpm_pipeline = 1,
exp_add_adder.lpm_width = 12,
exp_add_adder.lpm_type = "lpm_add_sub";
lpm_add_sub exp_adj_adder
(
.cin(1'b0),
.cout(),
.dataa(exp_adj_p1),
.datab({expmod[12:0]}),
.overflow(),
.result(wire_exp_adj_adder_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
exp_adj_adder.lpm_pipeline = 0,
exp_adj_adder.lpm_width = 13,
exp_adj_adder.lpm_type = "lpm_add_sub";
lpm_add_sub exp_bias_subtr
(
.cout(),
.dataa({1'b0, exp_bias_p2}),
.datab({bias[12:0]}),
.overflow(),
.result(wire_exp_bias_subtr_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
exp_bias_subtr.lpm_direction = "SUB",
exp_bias_subtr.lpm_pipeline = 0,
exp_bias_subtr.lpm_representation = "UNSIGNED",
exp_bias_subtr.lpm_width = 13,
exp_bias_subtr.lpm_type = "lpm_add_sub";
lpm_add_sub man_round_adder
(
.cout(),
.dataa({1'b0, man_round_p0}),
.datab({{53{1'b0}}, man_round_carry_p0}),
.overflow(),
.result(wire_man_round_adder_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
man_round_adder.lpm_pipeline = 0,
man_round_adder.lpm_width = 54,
man_round_adder.lpm_type = "lpm_add_sub";
lpm_mult man_product2_mult
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa({1'b1, dataa[51:0]}),
.datab({1'b1, datab[51:0]}),
.result(wire_man_product2_mult_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
man_product2_mult.lpm_pipeline = 5,
man_product2_mult.lpm_representation = "UNSIGNED",
man_product2_mult.lpm_widtha = 53,
man_product2_mult.lpm_widthb = 53,
man_product2_mult.lpm_widthp = 106,
man_product2_mult.lpm_widths = 1,
man_product2_mult.lpm_type = "lpm_mult",
man_product2_mult.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
assign
aclr = 1'b0,
bias = {{3{1'b0}}, {10{1'b1}}},
dataa_exp_all_one = {(dataa[62] & dataa_exp_all_one[9]), (dataa[61] & dataa_exp_all_one[8]), (dataa[60] & dataa_exp_all_one[7]), (dataa[59] & dataa_exp_all_one[6]), (dataa[58] & dataa_exp_all_one[5]), (dataa[57] & dataa_exp_all_one[4]), (dataa[56] & dataa_exp_all_one[3]), (dataa[55] & dataa_exp_all_one[2]), (dataa[54] & dataa_exp_all_one[1]), (dataa[53] & dataa_exp_all_one[0]), dataa[52]},
dataa_exp_not_zero = {(dataa[62] | dataa_exp_not_zero[9]), (dataa[61] | dataa_exp_not_zero[8]), (dataa[60] | dataa_exp_not_zero[7]), (dataa[59] | dataa_exp_not_zero[6]), (dataa[58] | dataa_exp_not_zero[5]), (dataa[57] | dataa_exp_not_zero[4]), (dataa[56] | dataa_exp_not_zero[3]), (dataa[55] | dataa_exp_not_zero[2]), (dataa[54] | dataa_exp_not_zero[1]), (dataa[53] | dataa_exp_not_zero[0]), dataa[52]},
dataa_man_not_zero = {(dataa[51] | dataa_man_not_zero[50]), (dataa[50] | dataa_man_not_zero[49]), (dataa[49] | dataa_man_not_zero[48]), (dataa[48] | dataa_man_not_zero[47]), (dataa[47] | dataa_man_not_zero[46]), (dataa[46] | dataa_man_not_zero[45]), (dataa[45] | dataa_man_not_zero[44]), (dataa[44] | dataa_man_not_zero[43]), (dataa[43] | dataa_man_not_zero[42]), (dataa[42] | dataa_man_not_zero[41]), (dataa[41] | dataa_man_not_zero[40]), (dataa[40] | dataa_man_not_zero[39]), (dataa[39] | dataa_man_not_zero[38]), (dataa[38] | dataa_man_not_zero[37]), (dataa[37] | dataa_man_not_zero[36]), (dataa[36] | dataa_man_not_zero[35]), (dataa[35] | dataa_man_not_zero[34]), (dataa[34] | dataa_man_not_zero[33]), (dataa[33] | dataa_man_not_zero[32]), (dataa[32] | dataa_man_not_zero[31]), (dataa[31] | dataa_man_not_zero[30]), (dataa[30] | dataa_man_not_zero[29]), (dataa[29] | dataa_man_not_zero[28]), (dataa[28] | dataa_man_not_zero[27]), (dataa[27] | dataa_man_not_zero[26]), dataa[26], (dataa[25] | dataa_man_not_zero[24]), (dataa[24] | dataa_man_not_zero[23]), (dataa[23] | dataa_man_not_zero[22]), (dataa[22] | dataa_man_not_zero[21]), (dataa[21] | dataa_man_not_zero[20]), (dataa[20] | dataa_man_not_zero[19]), (dataa[19] | dataa_man_not_zero[18]), (dataa[18] | dataa_man_not_zero[17]), (dataa[17] | dataa_man_not_zero[16]), (dataa[16] | dataa_man_not_zero[15]), (dataa[15] | dataa_man_not_zero[14]), (dataa[14] | dataa_man_not_zero[13]), (dataa[13] | dataa_man_not_zero[12]), (dataa[12] | dataa_man_not_zero[11]), (dataa[11] | dataa_man_not_zero[10]), (dataa[10] | dataa_man_not_zero[9]), (dataa[9] | dataa_man_not_zero[8]), (dataa[8] | dataa_man_not_zero[7]), (dataa[7] | dataa_man_not_zero[6]), (dataa[6] | dataa_man_not_zero[5]), (dataa[5] | dataa_man_not_zero[4]), (dataa[4] | dataa_man_not_zero[3]), (dataa[3] | dataa_man_not_zero[2]), (dataa[2] | dataa_man_not_zero[1]), (dataa[1] | dataa_man_not_zero[0]), dataa[0]},
datab_exp_all_one = {(datab[62] & datab_exp_all_one[9]), (datab[61] & datab_exp_all_one[8]), (datab[60] & datab_exp_all_one[7]), (datab[59] & datab_exp_all_one[6]), (datab[58] & datab_exp_all_one[5]), (datab[57] & datab_exp_all_one[4]), (datab[56] & datab_exp_all_one[3]), (datab[55] & datab_exp_all_one[2]), (datab[54] & datab_exp_all_one[1]), (datab[53] & datab_exp_all_one[0]), datab[52]},
datab_exp_not_zero = {(datab[62] | datab_exp_not_zero[9]), (datab[61] | datab_exp_not_zero[8]), (datab[60] | datab_exp_not_zero[7]), (datab[59] | datab_exp_not_zero[6]), (datab[58] | datab_exp_not_zero[5]), (datab[57] | datab_exp_not_zero[4]), (datab[56] | datab_exp_not_zero[3]), (datab[55] | datab_exp_not_zero[2]), (datab[54] | datab_exp_not_zero[1]), (datab[53] | datab_exp_not_zero[0]), datab[52]},
datab_man_not_zero = {(datab[51] | datab_man_not_zero[50]), (datab[50] | datab_man_not_zero[49]), (datab[49] | datab_man_not_zero[48]), (datab[48] | datab_man_not_zero[47]), (datab[47] | datab_man_not_zero[46]), (datab[46] | datab_man_not_zero[45]), (datab[45] | datab_man_not_zero[44]), (datab[44] | datab_man_not_zero[43]), (datab[43] | datab_man_not_zero[42]), (datab[42] | datab_man_not_zero[41]), (datab[41] | datab_man_not_zero[40]), (datab[40] | datab_man_not_zero[39]), (datab[39] | datab_man_not_zero[38]), (datab[38] | datab_man_not_zero[37]), (datab[37] | datab_man_not_zero[36]), (datab[36] | datab_man_not_zero[35]), (datab[35] | datab_man_not_zero[34]), (datab[34] | datab_man_not_zero[33]), (datab[33] | datab_man_not_zero[32]), (datab[32] | datab_man_not_zero[31]), (datab[31] | datab_man_not_zero[30]), (datab[30] | datab_man_not_zero[29]), (datab[29] | datab_man_not_zero[28]), (datab[28] | datab_man_not_zero[27]), (datab[27] | datab_man_not_zero[26]), datab[26], (datab[25] | datab_man_not_zero[24]), (datab[24] | datab_man_not_zero[23]), (datab[23] | datab_man_not_zero[22]), (datab[22] | datab_man_not_zero[21]), (datab[21] | datab_man_not_zero[20]), (datab[20] | datab_man_not_zero[19]), (datab[19] | datab_man_not_zero[18]), (datab[18] | datab_man_not_zero[17]), (datab[17] | datab_man_not_zero[16]), (datab[16] | datab_man_not_zero[15]), (datab[15] | datab_man_not_zero[14]), (datab[14] | datab_man_not_zero[13]), (datab[13] | datab_man_not_zero[12]), (datab[12] | datab_man_not_zero[11]), (datab[11] | datab_man_not_zero[10]), (datab[10] | datab_man_not_zero[9]), (datab[9] | datab_man_not_zero[8]), (datab[8] | datab_man_not_zero[7]), (datab[7] | datab_man_not_zero[6]), (datab[6] | datab_man_not_zero[5]), (datab[5] | datab_man_not_zero[4]), (datab[4] | datab_man_not_zero[3]), (datab[3] | datab_man_not_zero[2]), (datab[2] | datab_man_not_zero[1]), (datab[1] | datab_man_not_zero[0]), datab[0]},
exp_is_inf = (((~ exp_adj_p2[12]) & exp_adj_p2[11]) | ((~ exp_adj_p2[11]) & result_exp_all_one[10])),
exp_is_zero = (exp_adj_p2[12] | (~ result_exp_not_zero[11])),
expmod = {{11{1'b0}}, (delay_man_product_msb2 & man_round_p2[53]), (delay_man_product_msb2 ^ man_round_p2[53])},
inf_num = {11{1'b1}},
lsb_bit = man_shift_full[1],
man_shift_full = ((wire_man_product2_mult_result[104:51] & {54{(~ wire_man_product2_mult_result[105])}}) | (wire_man_product2_mult_result[105:52] & {54{wire_man_product2_mult_result[105]}})),
result = {sign_node_ff9[0:0], exp_result_ff[10:0], man_result_ff[51:0]},
result_exp_all_one = {(result_exp_all_one[9] & exp_adj_p2[10]), (result_exp_all_one[8] & exp_adj_p2[9]), (result_exp_all_one[7] & exp_adj_p2[8]), (result_exp_all_one[6] & exp_adj_p2[7]), (result_exp_all_one[5] & exp_adj_p2[6]), (result_exp_all_one[4] & exp_adj_p2[5]), (result_exp_all_one[3] & exp_adj_p2[4]), (result_exp_all_one[2] & exp_adj_p2[3]), (result_exp_all_one[1] & exp_adj_p2[2]), (result_exp_all_one[0] & exp_adj_p2[1]), exp_adj_p2[0]},
result_exp_not_zero = {(result_exp_not_zero[10] | exp_adj_p2[11]), (result_exp_not_zero[9] | exp_adj_p2[10]), (result_exp_not_zero[8] | exp_adj_p2[9]), (result_exp_not_zero[7] | exp_adj_p2[8]), (result_exp_not_zero[6] | exp_adj_p2[7]), (result_exp_not_zero[5] | exp_adj_p2[6]), (result_exp_not_zero[4] | exp_adj_p2[5]), (result_exp_not_zero[3] | exp_adj_p2[4]), (result_exp_not_zero[2] | exp_adj_p2[3]), (result_exp_not_zero[1] | exp_adj_p2[2]), (result_exp_not_zero[0] | exp_adj_p2[1]), exp_adj_p2[0]},
round_bit = man_shift_full[0],
round_carry = (round_dffe & (lsb_dffe | sticky_dffe)),
sticky_bit = {(sticky_bit[50] | (wire_man_product2_mult_result[105] & wire_man_product2_mult_result[51])), (sticky_bit[49] | wire_man_product2_mult_result[50]), (sticky_bit[48] | wire_man_product2_mult_result[49]), (sticky_bit[47] | wire_man_product2_mult_result[48]), (sticky_bit[46] | wire_man_product2_mult_result[47]), (sticky_bit[45] | wire_man_product2_mult_result[46]), (sticky_bit[44] | wire_man_product2_mult_result[45]), (sticky_bit[43] | wire_man_product2_mult_result[44]), (sticky_bit[42] | wire_man_product2_mult_result[43]), (sticky_bit[41] | wire_man_product2_mult_result[42]), (sticky_bit[40] | wire_man_product2_mult_result[41]), (sticky_bit[39] | wire_man_product2_mult_result[40]), (sticky_bit[38] | wire_man_product2_mult_result[39]), (sticky_bit[37] | wire_man_product2_mult_result[38]), (sticky_bit[36] | wire_man_product2_mult_result[37]), (sticky_bit[35] | wire_man_product2_mult_result[36]), (sticky_bit[34] | wire_man_product2_mult_result[35]), (sticky_bit[33] | wire_man_product2_mult_result[34]), (sticky_bit[32] | wire_man_product2_mult_result[33]), (sticky_bit[31] | wire_man_product2_mult_result[32]), (sticky_bit[30] | wire_man_product2_mult_result[31]), (sticky_bit[29] | wire_man_product2_mult_result[30]), (sticky_bit[28] | wire_man_product2_mult_result[29]), (sticky_bit[27] | wire_man_product2_mult_result[28]), (sticky_bit[26] | wire_man_product2_mult_result[27]), (sticky_bit[25] | wire_man_product2_mult_result[26]), (sticky_bit[24] | wire_man_product2_mult_result[25]), (sticky_bit[23] | wire_man_product2_mult_result[24]), (sticky_bit[22] | wire_man_product2_mult_result[23]), (sticky_bit[21] | wire_man_product2_mult_result[22]), (sticky_bit[20] | wire_man_product2_mult_result[21]), (sticky_bit[19] | wire_man_product2_mult_result[20]), (sticky_bit[18] | wire_man_product2_mult_result[19]), (sticky_bit[17] | wire_man_product2_mult_result[18]), (sticky_bit[16] | wire_man_product2_mult_result[17]), (sticky_bit[15] | wire_man_product2_mult_result[16]), (sticky_bit[14] | wire_man_product2_mult_result[15]
), (sticky_bit[13] | wire_man_product2_mult_result[14]), (sticky_bit[12] | wire_man_product2_mult_result[13]), (sticky_bit[11] | wire_man_product2_mult_result[12]), (sticky_bit[10] | wire_man_product2_mult_result[11]), (sticky_bit[9] | wire_man_product2_mult_result[10]), (sticky_bit[8] | wire_man_product2_mult_result[9]), (sticky_bit[7] | wire_man_product2_mult_result[8]), (sticky_bit[6] | wire_man_product2_mult_result[7]), (sticky_bit[5] | wire_man_product2_mult_result[6]), (sticky_bit[4] | wire_man_product2_mult_result[5]), (sticky_bit[3] | wire_man_product2_mult_result[4]), (sticky_bit[2] | wire_man_product2_mult_result[3]), (sticky_bit[1] | wire_man_product2_mult_result[2]), (sticky_bit[0] | wire_man_product2_mult_result[1]), wire_man_product2_mult_result[0]};
endmodule //acl_fp_mul_fast_double_altfp_mult_ufo
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_mul_fast_double (
enable,
clock,
dataa,
datab,
result);
input enable;
input clock;
input [63:0] dataa;
input [63:0] datab;
output [63:0] result;
wire [63:0] sub_wire0;
wire [63:0] result = sub_wire0[63:0];
acl_fp_mul_fast_double_altfp_mult_ufo acl_fp_mul_fast_double_altfp_mult_ufo_component (
.clk_en (enable),
.clock (clock),
.datab (datab),
.dataa (dataa),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: FPM_FORMAT STRING "Double"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "YES"
// Retrieval info: CONSTANT: DENORMAL_SUPPORT STRING "NO"
// Retrieval info: CONSTANT: EXCEPTION_HANDLING STRING "NO"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altfp_mult"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "10"
// Retrieval info: CONSTANT: REDUCED_FUNCTIONALITY STRING "NO"
// Retrieval info: CONSTANT: ROUNDING STRING "TO_NEAREST"
// Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "52"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: USED_PORT: dataa 0 0 64 0 INPUT NODEFVAL "dataa[63..0]"
// Retrieval info: CONNECT: @dataa 0 0 64 0 dataa 0 0 64 0
// Retrieval info: USED_PORT: datab 0 0 64 0 INPUT NODEFVAL "datab[63..0]"
// Retrieval info: CONNECT: @datab 0 0 64 0 datab 0 0 64 0
// Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT NODEFVAL "result[63..0]"
// Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_mul_fast_double.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_mul_fast_double.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_mul_fast_double.bsf FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_mul_fast_double_inst.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_mul_fast_double_bb.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_mul_fast_double.inc FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_mul_fast_double.cmp FALSE TRUE
// Retrieval info: LIB_FILE: lpm
|
/*
* PS2 Mouse Interface
* Copyright (C) 2010 Donna Polehn <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module ps2_mouse (
input clk, // Clock Input
input reset, // Reset Input
inout ps2_clk, // PS2 Clock, Bidirectional
inout ps2_dat, // PS2 Data, Bidirectional
input [7:0] the_command, // Command to send to mouse
input send_command, // Signal to send
output command_was_sent, // Signal command finished sending
output error_communication_timed_out,
output [7:0] received_data, // Received data
output received_data_en, // If 1 - new data has been received
output start_receiving_data,
output wait_for_incoming_data
);
// --------------------------------------------------------------------
// Internal wires and registers Declarations
// --------------------------------------------------------------------
wire ps2_clk_posedge; // Internal Wires
wire ps2_clk_negedge;
reg [7:0] idle_counter; // Internal Registers
reg ps2_clk_reg;
reg ps2_data_reg;
reg last_ps2_clk;
reg [2:0] ns_ps2_transceiver; // State Machine Registers
reg [2:0] s_ps2_transceiver;
// --------------------------------------------------------------------
// Constant Declarations
// --------------------------------------------------------------------
localparam PS2_STATE_0_IDLE = 3'h0, // states
PS2_STATE_1_DATA_IN = 3'h1,
PS2_STATE_2_COMMAND_OUT = 3'h2,
PS2_STATE_3_END_TRANSFER = 3'h3,
PS2_STATE_4_END_DELAYED = 3'h4;
// --------------------------------------------------------------------
// Finite State Machine(s)
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) s_ps2_transceiver <= PS2_STATE_0_IDLE;
else s_ps2_transceiver <= ns_ps2_transceiver;
end
always @(*) begin
ns_ps2_transceiver = PS2_STATE_0_IDLE; // Defaults
case (s_ps2_transceiver)
PS2_STATE_0_IDLE:
begin
if((idle_counter == 8'hFF) && (send_command == 1'b1))
ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
else ns_ps2_transceiver = PS2_STATE_0_IDLE;
end
PS2_STATE_1_DATA_IN:
begin
// if((received_data_en == 1'b1) && (ps2_clk_posedge == 1'b1))
if((received_data_en == 1'b1)) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
end
PS2_STATE_2_COMMAND_OUT:
begin
if((command_was_sent == 1'b1) || (error_communication_timed_out == 1'b1))
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
else ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
end
PS2_STATE_3_END_TRANSFER:
begin
if(send_command == 1'b0) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else if((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
else ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
PS2_STATE_4_END_DELAYED:
begin
if(received_data_en == 1'b1) begin
if(send_command == 1'b0) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
else ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
end
default:
ns_ps2_transceiver = PS2_STATE_0_IDLE;
endcase
end
// --------------------------------------------------------------------
// Sequential logic
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) begin
last_ps2_clk <= 1'b1;
ps2_clk_reg <= 1'b1;
ps2_data_reg <= 1'b1;
end
else begin
last_ps2_clk <= ps2_clk_reg;
ps2_clk_reg <= ps2_clk;
ps2_data_reg <= ps2_dat;
end
end
always @(posedge clk) begin
if(reset == 1'b1) idle_counter <= 6'h00;
else if((s_ps2_transceiver == PS2_STATE_0_IDLE) && (idle_counter != 8'hFF))
idle_counter <= idle_counter + 6'h01;
else if (s_ps2_transceiver != PS2_STATE_0_IDLE)
idle_counter <= 6'h00;
end
// --------------------------------------------------------------------
// Combinational logic
// --------------------------------------------------------------------
assign ps2_clk_posedge = ((ps2_clk_reg == 1'b1) && (last_ps2_clk == 1'b0)) ? 1'b1 : 1'b0;
assign ps2_clk_negedge = ((ps2_clk_reg == 1'b0) && (last_ps2_clk == 1'b1)) ? 1'b1 : 1'b0;
assign start_receiving_data = (s_ps2_transceiver == PS2_STATE_1_DATA_IN);
assign wait_for_incoming_data = (s_ps2_transceiver == PS2_STATE_3_END_TRANSFER);
// --------------------------------------------------------------------
// Internal Modules
// --------------------------------------------------------------------
ps2_mouse_cmdout mouse_cmdout (
.clk (clk), // Inputs
.reset (reset),
.the_command (the_command),
.send_command (send_command),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
.ps2_clk (ps2_clk), // Bidirectionals
.ps2_dat (ps2_dat),
.command_was_sent (command_was_sent), // Outputs
.error_communication_timed_out (error_communication_timed_out)
);
ps2_mouse_datain mouse_datain (
.clk (clk), // Inputs
.reset (reset),
.wait_for_incoming_data (wait_for_incoming_data),
.start_receiving_data (start_receiving_data),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
.ps2_data (ps2_data_reg),
.received_data (received_data), // Outputs
.received_data_en (received_data_en)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jorge Sequeira
//
// Create Date: 09/01/2016 06:29:42 PM
// Design Name:
// Module Name: KOA_FPGA
// Project Name: Recursive Karatsuba Offman Multiplication
// Target Devices:
// Tool Versions:
// Description: RKOA optimization for DSP
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module KOA_FPGA
//#(parameter SW = 24)
#(parameter SW = 54)
(
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] sgf_result_o
);
wire [SW/2+1:0] result_A_adder;
wire [SW/2+1:0] result_B_adder;
wire [2*(SW/2)-1:0] Q_left;
wire [2*(SW/2+1)-1:0] Q_right;
wire [2*(SW/2+2)-1:0] Q_middle;
wire [2*(SW/2+2)-1:0] S_A;
wire [2*(SW/2+2)-1:0] S_B;
wire [4*(SW/2)+2:0] Result;
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 =2'b00;
assign zero2 =4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
wire [4*(SW/2)-1:0] sgf_r;
assign rightside1 = (SW/2) *1'b0;
assign rightside2 = (SW/2+1)*1'b0;
assign leftside1 = (SW/2-2) *1'b0; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = (SW/2-3)*1'b0;
localparam half = SW/2;
//localparam level1=4;
//localparam level2=5;
////////////////////////////////////
generate
if (SW<=18) begin : K1
multiplier_C #(.W(SW)/*,.level(level1)*/) main(
.Data_A_i(Data_A_i),
.Data_B_i(Data_B_i),
.Data_S_o(sgf_result_o)
);
end else begin : K2
case (SW%2)
0:begin : K3
//////////////////////////////////even//////////////////////////////////
//Multiplier for left side and right side
KOA_FPGA #(.SW(SW/2)/*,.level(level1)*/) left(
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.sgf_result_o(/*result_left_mult*/Q_left)
);
KOA_FPGA #(.SW(SW/2)/*,.level(level1)*/) right(
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.sgf_result_o(/*result_right_mult[2*(SW/2)-1:0]*/Q_right[2*(SW/2)-1:0])
);
//Adders for middle
adder #(.W(SW/2)) A_operation (
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder[SW/2:0])
);
adder #(.W(SW/2)) B_operation (
.Data_A_i(Data_B_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder[SW/2:0])
);
//segmentation registers for 64 bits
/*RegisterAdd #(.W(SW/2+1)) preAreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_A_adder[SW/2:0]),
.Q(Q_result_A_adder[SW/2:0])
);//
RegisterAdd #(.W(SW/2+1)) preBreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_B_adder[SW/2:0]),
.Q(Q_result_B_adder[SW/2:0])
);//*/
//multiplication for middle
KOA_FPGA #(.SW(SW/2+1)/*,.level(level1)*/) middle (
.Data_A_i(/*Q_result_A_adder[SW/2:0]*/result_A_adder[SW/2:0]),
.Data_B_i(/*Q_result_B_adder[SW/2:0]*/result_B_adder[SW/2:0]),
.sgf_result_o(/*result_middle_mult[2*(SW/2)+1:0]*/Q_middle[2*(SW/2)+1:0])
);
///Subtractors for middle
substractor #(.W(SW+2)) Subtr_1 (
.Data_A_i(/*result_middle_mult//*/Q_middle[2*(SW/2)+1:0]),
.Data_B_i({zero1, /*result_left_mult//*/Q_left}),
.Data_S_o(S_A[2*(SW/2)+1:0])
);
substractor #(.W(SW+2)) Subtr_2 (
.Data_A_i(S_A[2*(SW/2)+1:0]),
.Data_B_i({zero1, /*result_right_mult//*/Q_right[2*(SW/2)-1:0]}),
.Data_S_o(S_B[2*(SW/2)+1:0])
);
//Final adder
adder #(.W(4*(SW/2))) Final(
.Data_A_i({/*result_left_mult,result_right_mult*/Q_left,Q_right[2*(SW/2)-1:0]}),
.Data_B_i({leftside1,S_B[2*(SW/2)+1:0],rightside1}),
.Data_S_o(Result[4*(SW/2):0])
);
//Final assignation
assign sgf_result_o = Result[2*SW-1:0];
end
1:begin : K4
//////////////////////////////////odd//////////////////////////////////
//Multiplier for left side and right side
KOA_FPGA #(.SW(SW/2)/*,.level(level2)*/) left_high(
.Data_A_i(Data_A_i[SW-1:SW/2+1]),
.Data_B_i(Data_B_i[SW-1:SW/2+1]),
.sgf_result_o(/*result_left_mult*/Q_left)
);
KOA_FPGA #(.SW((SW/2)+1)/*,.level(level2)*/) right_lower(
/// Modificacion: Tamaño de puerto cambia de SW/2+1 a SW/2+2. El compilador lo pide por alguna razon.
.Data_A_i(Data_A_i[SW/2:0]),
.Data_B_i(Data_B_i[SW/2:0]),
.sgf_result_o(/*result_right_mult*/Q_right)
);
//Adders for middle
adder #(.W(SW/2+1)) A_operation (
.Data_A_i({1'b0,Data_A_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder)
);
adder #(.W(SW/2+1)) B_operation (
.Data_A_i({1'b0,Data_B_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder)
);
//segmentation registers for 64 bits
/*RegisterAdd #(.W(SW/2+2)) preAreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_A_adder),
.Q(Q_result_A_adder)
);//
RegisterAdd #(.W(SW/2+2)) preBreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_B_adder),
.Q(Q_result_B_adder)
);//*/
//multiplication for middle
KOA_FPGA #(.SW(SW/2+2)/*,.level(level2)*/) middle (
.Data_A_i(/*Q_result_A_adder*/result_A_adder),
.Data_B_i(/*Q_result_B_adder*/result_B_adder),
.sgf_result_o(/*result_middle_mult*/Q_middle)
);
//segmentation registers array
///Subtractors for middle
substractor #(.W(2*(SW/2+2))) Subtr_1 (
.Data_A_i(/*result_middle_mult//*/Q_middle),
.Data_B_i({zero2, /*result_left_mult//*/Q_left}),
.Data_S_o(S_A)
);
substractor #(.W(2*(SW/2+2))) Subtr_2 (
.Data_A_i(S_A),
.Data_B_i({zero1, /*result_right_mult//*/Q_right}),
.Data_S_o(S_B)
);
//Final adder
adder #(.W(4*(SW/2)+2)) Final(
.Data_A_i({/*result_left_mult,result_right_mult*/Q_left,Q_right}),
.Data_B_i({leftside2,S_B,rightside2}),
.Data_S_o(Result[4*(SW/2)+2:0])
);
//Final assignation
assign sgf_result_o = Result[2*SW-1:0];
end
endcase
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/26/2016 07:00:53 AM
// Design Name:
// Module Name: Adder_Round
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Adder_Round
#(parameter SW=26) (
input wire clk,
input wire rst,
input wire load_i,//Reg load input
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
/////////////////////////////////////////////////////////////
output wire [SW-1:0] Data_Result_o,
output wire FSM_C_o
);
wire [SW:0] result_A_adder;
adder #(.W(SW)) A_operation (
.Data_A_i(Data_A_i),
.Data_B_i(Data_B_i),
.Data_S_o(result_A_adder)
);
RegisterAdd #(.W(SW)) Add_Subt_Result(
.clk (clk),
.rst (rst),
.load (load_i),
.D (result_A_adder[SW-1:0]),
.Q (Data_Result_o)
);
RegisterAdd #(.W(1)) Add_overflow_Result(
.clk (clk),
.rst (rst),
.load (load_i),
.D (result_A_adder[SW]),
.Q (FSM_C_o)
);
endmodule
|
//#############################################################################
//# Function: Carry Save Adder (4:2) #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_csa42 #( parameter DW = 1 // data width
)
( input [DW-1:0] in0, //input
input [DW-1:0] in1,//input
input [DW-1:0] in2,//input
input [DW-1:0] in3,//input
input [DW-1:0] cin,//carry in
output [DW-1:0] s, //sum
output [DW-1:0] c, //carry
output [DW-1:0] cout //carry out
);
localparam ASIC = `CFG_ASIC; // use asic library
generate
if(ASIC)
begin
asic_csa42 i_csa42[DW-1:0] (.s(s[DW-1:0]),
.cout(cout[DW-1:0]),
.c(c[DW-1:0]),
.cin(cin[DW-1:0]),
.in3(in3[DW-1:0]),
.in2(in2[DW-1:0]),
.in1(in1[DW-1:0]),
.in0(in0[DW-1:0]));
end
else
begin
wire [DW-1:0] s_int;
assign s[DW-1:0] = in0[DW-1:0] ^
in1[DW-1:0] ^
in2[DW-1:0] ^
in3[DW-1:0] ^
cin[DW-1:0];
assign s_int[DW-1:0] = in1[DW-1:0] ^
in2[DW-1:0] ^
in3[DW-1:0];
assign c[DW-1:0] = (in0[DW-1:0] & s_int[DW-1:0]) |
(in0[DW-1:0] & cin[DW-1:0]) |
(s_int[DW-1:0] & cin[DW-1:0]);
assign cout[DW-1:0] = (in1[DW-1:0] & in2[DW-1:0]) |
(in1[DW-1:0] & in3[DW-1:0]) |
(in2[DW-1:0] & in3[DW-1:0]);
end // else: !if(ASIC)
endgenerate
endmodule // oh_csa42
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_mac_pcs_pma_gige.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_mac_pcs_pma_gige.v,v $
//
// $Revision: #1 $
// $Date: 2010/04/12 $
// Check in by : $Author: max $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet
//
// Description :
//
// Top level MAC + PCS + PMA module for Triple Speed Ethernet MAC + PCS + PMA
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
module altera_tse_mac_pcs_pma_gige /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */(
// inputs:
address,
clk,
ff_rx_clk,
ff_rx_rdy,
ff_tx_clk,
ff_tx_crc_fwd,
ff_tx_data,
ff_tx_mod,
ff_tx_eop,
ff_tx_err,
ff_tx_sop,
ff_tx_wren,
gxb_cal_blk_clk,
gxb_pwrdn_in,
magic_sleep_n,
mdio_in,
read,
reconfig_clk,
reconfig_togxb,
ref_clk,
reset,
rxp,
write,
writedata,
xoff_gen,
xon_gen,
// outputs:
ff_rx_a_empty,
ff_rx_a_full,
ff_rx_data,
ff_rx_mod,
ff_rx_dsav,
ff_rx_dval,
ff_rx_eop,
ff_rx_sop,
ff_tx_a_empty,
ff_tx_a_full,
ff_tx_rdy,
ff_tx_septy,
led_an,
led_char_err,
led_col,
led_crs,
led_disp_err,
led_link,
magic_wakeup,
mdc,
mdio_oen,
mdio_out,
pcs_pwrdn_out,
readdata,
reconfig_fromgxb,
rx_err,
rx_err_stat,
rx_frm_type,
tx_ff_uflow,
txp,
waitrequest
);
// Parameters to configure the core for different variations
// ---------------------------------------------------------
parameter ENABLE_ENA = 8; // Enable n-Bit Local Interface
parameter ENABLE_GMII_LOOPBACK = 1; // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
parameter ENABLE_HD_LOGIC = 1; // HD_LOGIC_ENA : Enable Half Duplex Logic
parameter USE_SYNC_RESET = 1; // Use Synchronized Reset Inputs
parameter ENABLE_SUP_ADDR = 1; // SUP_ADDR_ENA : Enable Supplemental Addresses
parameter ENA_HASH = 1; // ENA_HASH Enable Hask Table
parameter STAT_CNT_ENA = 1; // STAT_CNT_ENA Enable Statistic Counters
parameter ENABLE_EXTENDED_STAT_REG = 0; // Enable a few extended statistic registers
parameter EG_FIFO = 256 ; // Egress FIFO Depth
parameter EG_ADDR = 8 ; // Egress FIFO Depth
parameter ING_FIFO = 256 ; // Ingress FIFO Depth
parameter ING_ADDR = 8 ; // Egress FIFO Depth
parameter RESET_LEVEL = 1'b 1 ; // Reset Active Level
parameter MDIO_CLK_DIV = 40 ; // Host Clock Division - MDC Generation
parameter CORE_VERSION = 16'h3; // MorethanIP Core Version
parameter CUST_VERSION = 1 ; // Customer Core Version
parameter REDUCED_INTERFACE_ENA = 1; // Enable the RGMII / MII Interface
parameter ENABLE_MDIO = 1; // Enable the MDIO Interface
parameter ENABLE_MAGIC_DETECT = 1; // Enable magic packet detection
parameter ENABLE_MACLITE = 0; // Enable MAC LITE operation
parameter MACLITE_GIGE = 0; // Enable/Disable Gigabit MAC operation for MAC LITE.
parameter CRC32DWIDTH = 4'b 1000; // input data width (informal, not for change)
parameter CRC32GENDELAY = 3'b 110; // when the data from the generator is valid
parameter CRC32CHECK16BIT = 1'b 0; // 1 compare two times 16 bit of the CRC (adds one pipeline step)
parameter CRC32S1L2_EXTERN = 1'b0; // false: merge enable
parameter ENABLE_SHIFT16 = 0; // Enable byte stuffing at packet header
parameter RAM_TYPE = "AUTO"; // Specify the RAM type
parameter INSERT_TA = 0; // Option to insert timing adapter for SOPC systems
parameter PHY_IDENTIFIER = 32'h 00000000;// PHY Identifier
parameter DEV_VERSION = 16'h 0001 ; // Customer Phy's Core Version
parameter ENABLE_SGMII = 1; // Enable SGMII logic for synthesis
parameter ENABLE_MAC_FLOW_CTRL = 1'b1; // Option to enable flow control
parameter ENABLE_MAC_TXADDR_SET = 1'b1; // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
parameter ENABLE_MAC_RX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC RX data path
parameter ENABLE_MAC_TX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC TX data path
parameter EXPORT_PWRDN = 1'b0; // Option to export the Alt2gxb powerdown signal
parameter DEVICE_FAMILY = "ARRIAGX"; // The device family the the core is targetted for.
parameter TRANSCEIVER_OPTION = 1'b0; // Option to select transceiver block for MAC PCS PMA Instantiation. Valid Values are 0 and 1: 0 - GXB (GIGE Mode) 1 - LVDS I/O
parameter ENABLE_ALT_RECONFIG = 0; // Option to have the Alt_Reconfig ports exposed
parameter STARTING_CHANNEL_NUMBER = 0; // Starting Channel Number for Reconfig block
parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
output ff_rx_a_empty;
output ff_rx_a_full;
output [ENABLE_ENA-1:0] ff_rx_data;
output [1:0] ff_rx_mod;
output ff_rx_dsav;
output ff_rx_dval;
output ff_rx_eop;
output ff_rx_sop;
output ff_tx_a_empty;
output ff_tx_a_full;
output ff_tx_rdy;
output ff_tx_septy;
output led_an;
output led_char_err;
output led_col;
output led_crs;
output led_disp_err;
output led_link;
output magic_wakeup;
output mdc;
output mdio_oen;
output mdio_out;
output pcs_pwrdn_out;
output [31: 0] readdata;
output [16:0] reconfig_fromgxb;
output [5: 0] rx_err;
output [17: 0] rx_err_stat;
output [3: 0] rx_frm_type;
output tx_ff_uflow;
output txp;
output waitrequest;
input [7: 0] address;
input clk;
input ff_rx_clk;
input ff_rx_rdy;
input ff_tx_clk;
input ff_tx_crc_fwd;
input [ENABLE_ENA-1:0] ff_tx_data;
input [1:0] ff_tx_mod;
input ff_tx_eop;
input ff_tx_err;
input ff_tx_sop;
input ff_tx_wren;
input gxb_cal_blk_clk;
input gxb_pwrdn_in;
input magic_sleep_n;
input mdio_in;
input read;
input reconfig_clk;
input [3:0] reconfig_togxb;
input ref_clk;
input reset;
input rxp;
input write;
input [31:0] writedata;
input xoff_gen;
input xon_gen;
wire MAC_PCS_reset;
wire ff_rx_a_empty;
wire ff_rx_a_full;
wire [ENABLE_ENA-1:0] ff_rx_data;
wire [1:0] ff_rx_mod;
wire ff_rx_dsav;
wire ff_rx_dval;
wire ff_rx_eop;
wire ff_rx_sop;
wire ff_tx_a_empty;
wire ff_tx_a_full;
wire ff_tx_rdy;
wire ff_tx_septy;
wire gige_pma_reset;
wire led_an;
wire led_char_err;
wire led_char_err_gx;
wire led_col;
wire led_crs;
wire led_disp_err;
wire led_link;
wire link_status;
wire magic_wakeup;
wire mdc;
wire mdio_oen;
wire mdio_out;
wire pcs_clk;
wire [7:0] pcs_rx_frame;
wire pcs_rx_kchar;
wire pcs_pwrdn_out_sig;
wire gxb_pwrdn_in_sig;
wire gxb_cal_blk_clk_sig;
wire [31:0] readdata;
wire rx_char_err_gx;
wire rx_disp_err;
wire [5:0] rx_err;
wire [17:0] rx_err_stat;
wire [3:0] rx_frm_type;
wire [7:0] rx_frame;
wire rx_syncstatus;
wire rx_kchar;
wire sd_loopback;
wire tx_ff_uflow;
wire [7:0] tx_frame;
wire tx_kchar;
wire txp;
wire waitrequest;
wire rx_runlengthviolation;
wire rx_patterndetect;
wire rx_runningdisp;
wire rx_rmfifodatadeleted;
wire rx_rmfifodatainserted;
wire pcs_rx_carrierdetected;
wire pcs_rx_rmfifodatadeleted;
wire pcs_rx_rmfifodatainserted;
reg pma_digital_rst0;
reg pma_digital_rst1;
reg pma_digital_rst2;
wire [16:0] reconfig_fromgxb;
// Reset logic used to reset the PMA blocks
// ----------------------------------------
always @(posedge clk or posedge reset)
begin
if (reset == 1)
begin
pma_digital_rst0 <= reset;
pma_digital_rst1 <= reset;
pma_digital_rst2 <= reset;
end
else
begin
pma_digital_rst0 <= reset;
pma_digital_rst1 <= pma_digital_rst0;
pma_digital_rst2 <= pma_digital_rst1;
end
end
// Assign the digital reset of the PMA to the MAC_PCS logic
// --------------------------------------------------------
assign MAC_PCS_reset = pma_digital_rst2;
// Assign the character error and link status to top level leds
// ------------------------------------------------------------
assign led_char_err = led_char_err_gx;
assign led_link = link_status;
// Instantiation of the MAC_PCS core that connects to a PMA
// --------------------------------------------------------
altera_tse_mac_pcs_pma_strx_gx_ena altera_tse_mac_pcs_pma_strx_gx_ena_inst
(
.rx_carrierdetected(pcs_rx_carrierdetected),
.rx_rmfifodatadeleted(pcs_rx_rmfifodatadeleted),
.rx_rmfifodatainserted(pcs_rx_rmfifodatainserted),
.address (address),
.clk (clk),
.ff_rx_a_empty (ff_rx_a_empty),
.ff_rx_a_full (ff_rx_a_full),
.ff_rx_clk (ff_rx_clk),
.ff_rx_data (ff_rx_data),
.ff_rx_mod (ff_rx_mod),
.ff_rx_dsav (ff_rx_dsav),
.ff_rx_dval (ff_rx_dval),
.ff_rx_eop (ff_rx_eop),
.ff_rx_rdy (ff_rx_rdy),
.ff_rx_sop (ff_rx_sop),
.ff_tx_a_empty (ff_tx_a_empty),
.ff_tx_a_full (ff_tx_a_full),
.ff_tx_clk (ff_tx_clk),
.ff_tx_crc_fwd (ff_tx_crc_fwd),
.ff_tx_data (ff_tx_data),
.ff_tx_mod (ff_tx_mod),
.ff_tx_eop (ff_tx_eop),
.ff_tx_err (ff_tx_err),
.ff_tx_rdy (ff_tx_rdy),
.ff_tx_septy (ff_tx_septy),
.ff_tx_sop (ff_tx_sop),
.ff_tx_wren (ff_tx_wren),
.led_an (led_an),
.led_char_err (led_char_err_gx),
.led_col (led_col),
.led_crs (led_crs),
.led_link (link_status),
.magic_sleep_n (magic_sleep_n),
.magic_wakeup (magic_wakeup),
.mdc (mdc),
.mdio_in (mdio_in),
.mdio_oen (mdio_oen),
.mdio_out (mdio_out),
.powerdown (pcs_pwrdn_out_sig),
.read (read),
.readdata (readdata),
.reset (MAC_PCS_reset),
.rx_clkout (pcs_clk),
.rx_err (rx_err),
.rx_err_stat (rx_err_stat),
.rx_frame (pcs_rx_frame),
.rx_frm_type (rx_frm_type),
.rx_kchar (pcs_rx_kchar),
.sd_loopback (sd_loopback),
.tx_clkout (pcs_clk),
.tx_ff_uflow (tx_ff_uflow),
.tx_frame (tx_frame),
.tx_kchar (tx_kchar),
.waitrequest (waitrequest),
.write (write),
.writedata (writedata),
.xoff_gen (xoff_gen),
.xon_gen (xon_gen)
);
defparam
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_ENA = ENABLE_ENA,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.USE_SYNC_RESET = USE_SYNC_RESET,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENA_HASH = ENA_HASH,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.STAT_CNT_ENA = STAT_CNT_ENA,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.EG_FIFO = EG_FIFO,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.EG_ADDR = EG_ADDR,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ING_FIFO = ING_FIFO,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ING_ADDR = ING_ADDR,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.RESET_LEVEL = RESET_LEVEL,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.MDIO_CLK_DIV = MDIO_CLK_DIV,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CORE_VERSION = CORE_VERSION,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CUST_VERSION = CUST_VERSION,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MDIO = ENABLE_MDIO,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MACLITE = ENABLE_MACLITE,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.MACLITE_GIGE = MACLITE_GIGE,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CRC32DWIDTH = CRC32DWIDTH,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CRC32CHECK16BIT = CRC32CHECK16BIT,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CRC32GENDELAY = CRC32GENDELAY,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_SHIFT16 = ENABLE_SHIFT16,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.INSERT_TA = INSERT_TA,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.RAM_TYPE = RAM_TYPE,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.PHY_IDENTIFIER = PHY_IDENTIFIER,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.DEV_VERSION = DEV_VERSION,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_SGMII = ENABLE_SGMII,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.SYNCHRONIZER_DEPTH = SYNCHRONIZER_DEPTH,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN;
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1)
begin
assign gxb_pwrdn_in_sig = gxb_pwrdn_in;
assign pcs_pwrdn_out = pcs_pwrdn_out_sig;
end
else
begin
assign gxb_pwrdn_in_sig = pcs_pwrdn_out_sig;
assign pcs_pwrdn_out = 1'b0;
end
endgenerate
// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX and ArriaGX devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync
(
.clk(pcs_clk),
.reset(MAC_PCS_reset),
//input (from alt2gxb)
.alt_dataout(rx_frame),
.alt_sync(rx_syncstatus),
.alt_disperr(rx_disp_err),
.alt_ctrldetect(rx_kchar),
.alt_errdetect(rx_char_err_gx),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted),
.alt_rmfifodatainserted(rx_rmfifodatainserted),
.alt_runlengthviolation(rx_runlengthviolation),
.alt_patterndetect(rx_patterndetect),
.alt_runningdisp(rx_runningdisp),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame),
.altpcs_sync(link_status),
.altpcs_disperr(led_disp_err),
.altpcs_ctrldetect(pcs_rx_kchar),
.altpcs_errdetect(led_char_err_gx),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted),
.altpcs_carrierdetect(pcs_rx_carrierdetected)
) ;
defparam
the_altera_tse_gxb_aligned_rxsync.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig),
.pll_inclk (ref_clk),
.reconfig_clk(reconfig_clk),
.reconfig_togxb(reconfig_togxb),
.reconfig_fromgxb(reconfig_fromgxb),
.rx_analogreset (reset),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar),
.rx_datain (rxp),
.rx_dataout (rx_frame),
.rx_digitalreset (pma_digital_rst2),
.rx_disperr (rx_disp_err),
.rx_errdetect (rx_char_err_gx),
.rx_patterndetect (rx_patterndetect),
.rx_rlv (rx_runlengthviolation),
.rx_seriallpbken (sd_loopback),
.rx_syncstatus (rx_syncstatus),
.tx_clkout (pcs_clk),
.tx_ctrlenable (tx_kchar),
.tx_datain (tx_frame),
.tx_dataout (txp),
.tx_digitalreset (pma_digital_rst2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted),
.rx_rmfifodatainserted(rx_rmfifodatainserted),
.rx_runningdisp(rx_runningdisp)
);
defparam
the_altera_tse_gxb_gige_inst.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER,
the_altera_tse_gxb_gige_inst.DEVICE_FAMILY = DEVICE_FAMILY;
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : mig_7series_v2_3_ddr_phy_tempmon.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Dec 20 2013
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Monitors chip temperature via the XADC and adjusts the
// stage 2 tap values as appropriate.
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v2_3_ddr_phy_tempmon #
(
parameter TCQ = 100, // Register delay (simulation only)
// Temperature bands must be in order. To disable bands, set to extreme.
parameter TEMP_INCDEC = 1465, // Degrees C * 100 (14.65 * 100)
parameter TEMP_HYST = 1,
parameter TEMP_MIN_LIMIT = 12'h8ac,
parameter TEMP_MAX_LIMIT = 12'hca4
)
(
input clk, // Fabric clock
input rst, // System reset
input calib_complete, // Calibration complete
input tempmon_sample_en, // Signal to enable sampling
input [11:0] device_temp, // Current device temperature
output tempmon_pi_f_inc, // Increment PHASER_IN taps
output tempmon_pi_f_dec, // Decrement PHASER_IN taps
output tempmon_sel_pi_incdec // Assume control of PHASER_IN taps
);
// translate hysteresis into XADC units
localparam HYST_OFFSET = (TEMP_HYST * 4096) / 504;
localparam TEMP_INCDEC_OFFSET = ((TEMP_INCDEC * 4096) / 50400) ;
// Temperature sampler FSM encoding
localparam IDLE = 11'b000_0000_0001;
localparam INIT = 11'b000_0000_0010;
localparam FOUR_INC = 11'b000_0000_0100;
localparam THREE_INC = 11'b000_0000_1000;
localparam TWO_INC = 11'b000_0001_0000;
localparam ONE_INC = 11'b000_0010_0000;
localparam NEUTRAL = 11'b000_0100_0000;
localparam ONE_DEC = 11'b000_1000_0000;
localparam TWO_DEC = 11'b001_0000_0000;
localparam THREE_DEC = 11'b010_0000_0000;
localparam FOUR_DEC = 11'b100_0000_0000;
//===========================================================================
// Reg declarations
//===========================================================================
// Output port flops. Inc and dec are mutex.
reg pi_f_dec; // Flop output
reg pi_f_inc; // Flop output
reg pi_f_dec_nxt; // FSM output
reg pi_f_inc_nxt; // FSM output
// FSM state
reg [10:0] tempmon_state;
reg [10:0] tempmon_state_nxt;
// FSM output used to capture the initial device termperature
reg tempmon_state_init;
// Flag to indicate the initial device temperature is captured and normal operation can begin
reg tempmon_init_complete;
// Temperature band/state boundaries
reg [11:0] four_inc_max_limit;
reg [11:0] three_inc_max_limit;
reg [11:0] two_inc_max_limit;
reg [11:0] one_inc_max_limit;
reg [11:0] neutral_max_limit;
reg [11:0] one_dec_max_limit;
reg [11:0] two_dec_max_limit;
reg [11:0] three_dec_max_limit;
reg [11:0] three_inc_min_limit;
reg [11:0] two_inc_min_limit;
reg [11:0] one_inc_min_limit;
reg [11:0] neutral_min_limit;
reg [11:0] one_dec_min_limit;
reg [11:0] two_dec_min_limit;
reg [11:0] three_dec_min_limit;
reg [11:0] four_dec_min_limit;
reg [11:0] device_temp_init;
// Flops for capturing and storing the current device temperature
reg tempmon_sample_en_101;
reg tempmon_sample_en_102;
reg [11:0] device_temp_101;
reg [11:0] device_temp_capture_102;
reg update_temp_102;
// Flops for comparing temperature to max limits
reg temp_cmp_four_inc_max_102;
reg temp_cmp_three_inc_max_102;
reg temp_cmp_two_inc_max_102;
reg temp_cmp_one_inc_max_102;
reg temp_cmp_neutral_max_102;
reg temp_cmp_one_dec_max_102;
reg temp_cmp_two_dec_max_102;
reg temp_cmp_three_dec_max_102;
// Flops for comparing temperature to min limits
reg temp_cmp_three_inc_min_102;
reg temp_cmp_two_inc_min_102;
reg temp_cmp_one_inc_min_102;
reg temp_cmp_neutral_min_102;
reg temp_cmp_one_dec_min_102;
reg temp_cmp_two_dec_min_102;
reg temp_cmp_three_dec_min_102;
reg temp_cmp_four_dec_min_102;
//===========================================================================
// Overview and temperature band limits
//===========================================================================
// The main feature of the tempmon block is an FSM that tracks the temerature provided by the ADC and decides if the phaser needs to be adjusted. The FSM
// has nine temperature bands or states, centered around an initial device temperature. The name of each state is the net number of phaser increments or
// decrements that have been issued in getting to the state. There are two temperature boundaries or limits between adjacent states. These two boundaries are
// offset by a small amount to provide hysteresis. The max limits are the boundaries that are used to determine when to move to the next higher temperature state
// and decrement the phaser. The min limits determine when to move to the next lower temperature state and increment the phaser. The limits are calculated when
// the initial device temperature is taken, and will always be at fixed offsets from the initial device temperature. States with limits below 0C or above
// 125C will never be entered.
// Temperature lowest highest
// <------------------------------------------------------------------------------------------------------------------------------------------------>
//
// Temp four three two one neutral one two three four
// band/state inc inc inc inc dec dec dec dec
//
// Max limits |<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|
// Min limits |<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->| |
// | | | | | | |
// | | | | | | |
// three_inc_min_limit | HYST_OFFSET--->| |<-- | four_dec_min_limit |
// | device_temp_init |
// four_inc_max_limit three_dec_max_limit
// Boundaries for moving from lower temp bands to higher temp bands.
// Note that only three_dec_max_limit can roll over, assuming device_temp_init is between 0C and 125C and TEMP_INCDEC_OFFSET is 14.65C,
// and none of the min or max limits can roll under. So three_dec_max_limit has a check for being out of the 0x0 to 0xFFF range.
wire [11:0] four_inc_max_limit_nxt = device_temp_init - 7*TEMP_INCDEC_OFFSET; // upper boundary of lowest temp band
wire [11:0] three_inc_max_limit_nxt = device_temp_init - 5*TEMP_INCDEC_OFFSET;
wire [11:0] two_inc_max_limit_nxt = device_temp_init - 3*TEMP_INCDEC_OFFSET;
wire [11:0] one_inc_max_limit_nxt = device_temp_init - TEMP_INCDEC_OFFSET;
wire [11:0] neutral_max_limit_nxt = device_temp_init + TEMP_INCDEC_OFFSET; // upper boundary of init temp band
wire [11:0] one_dec_max_limit_nxt = device_temp_init + 3*TEMP_INCDEC_OFFSET;
wire [11:0] two_dec_max_limit_nxt = device_temp_init + 5*TEMP_INCDEC_OFFSET;
wire [12:0] three_dec_max_limit_tmp = device_temp_init + 7*TEMP_INCDEC_OFFSET; // upper boundary of 2nd highest temp band
wire [11:0] three_dec_max_limit_nxt = three_dec_max_limit_tmp[12] ? 12'hFFF : three_dec_max_limit_tmp[11:0];
// Boundaries for moving from higher temp bands to lower temp bands
wire [11:0] three_inc_min_limit_nxt = four_inc_max_limit - HYST_OFFSET; // lower boundary of 2nd lowest temp band
wire [11:0] two_inc_min_limit_nxt = three_inc_max_limit - HYST_OFFSET;
wire [11:0] one_inc_min_limit_nxt = two_inc_max_limit - HYST_OFFSET;
wire [11:0] neutral_min_limit_nxt = one_inc_max_limit - HYST_OFFSET; // lower boundary of init temp band
wire [11:0] one_dec_min_limit_nxt = neutral_max_limit - HYST_OFFSET;
wire [11:0] two_dec_min_limit_nxt = one_dec_max_limit - HYST_OFFSET;
wire [11:0] three_dec_min_limit_nxt = two_dec_max_limit - HYST_OFFSET;
wire [11:0] four_dec_min_limit_nxt = three_dec_max_limit - HYST_OFFSET; // lower boundary of highest temp band
//===========================================================================
// Capture device temperature
//===========================================================================
// There is a three stage pipeline used to capture temperature, calculate the next state
// of the FSM, and update the tempmon outputs.
//
// Stage 100 Inputs device_temp and tempmon_sample_en become valid and are flopped.
// Input device_temp is compared to ADC codes for 0C and 125C and limited
// at the flop input if needed.
//
// Stage 101 The flopped version of device_temp is compared to the FSM temperature band boundaries
// to determine if a state change is needed. State changes are only enabled on the
// rising edge of the flopped tempmon_sample_en signal. If there is a state change a phaser
// increment or decrement signal is generated and flopped.
//
// Stage 102 The flopped versions of the phaser inc/dec signals drive the module outputs.
// Limit device_temp to 0C to 125C and assign it to flop input device_temp_100
// temp C = ( ( ADC CODE * 503.975 ) / 4096 ) - 273.15
wire device_temp_high = device_temp > TEMP_MAX_LIMIT;
wire device_temp_low = device_temp < TEMP_MIN_LIMIT;
wire [11:0] device_temp_100 = ( { 12 { device_temp_high } } & TEMP_MAX_LIMIT )
| ( { 12 { device_temp_low } } & TEMP_MIN_LIMIT )
| ( { 12 { ~device_temp_high & ~device_temp_low } } & device_temp );
// Capture/hold the initial temperature used in setting temperature bands and set init complete flag
// to enable normal sample operation.
wire [11:0] device_temp_init_nxt = tempmon_state_init ? device_temp_101 : device_temp_init;
wire tempmon_init_complete_nxt = tempmon_state_init ? 1'b1 : tempmon_init_complete;
// Capture/hold the current temperature on the sample enable signal rising edge after init is complete.
// The captured current temp is not used functionaly. It is just useful for debug and waveform review.
wire update_temp_101 = tempmon_init_complete & ~tempmon_sample_en_102 & tempmon_sample_en_101;
wire [11:0] device_temp_capture_101 = update_temp_101 ? device_temp_101 : device_temp_capture_102;
//===========================================================================
// Generate FSM arc signals
//===========================================================================
// Temperature comparisons for increasing temperature.
wire temp_cmp_four_inc_max_101 = device_temp_101 >= four_inc_max_limit ;
wire temp_cmp_three_inc_max_101 = device_temp_101 >= three_inc_max_limit ;
wire temp_cmp_two_inc_max_101 = device_temp_101 >= two_inc_max_limit ;
wire temp_cmp_one_inc_max_101 = device_temp_101 >= one_inc_max_limit ;
wire temp_cmp_neutral_max_101 = device_temp_101 >= neutral_max_limit ;
wire temp_cmp_one_dec_max_101 = device_temp_101 >= one_dec_max_limit ;
wire temp_cmp_two_dec_max_101 = device_temp_101 >= two_dec_max_limit ;
wire temp_cmp_three_dec_max_101 = device_temp_101 >= three_dec_max_limit ;
// Temperature comparisons for decreasing temperature.
wire temp_cmp_three_inc_min_101 = device_temp_101 < three_inc_min_limit ;
wire temp_cmp_two_inc_min_101 = device_temp_101 < two_inc_min_limit ;
wire temp_cmp_one_inc_min_101 = device_temp_101 < one_inc_min_limit ;
wire temp_cmp_neutral_min_101 = device_temp_101 < neutral_min_limit ;
wire temp_cmp_one_dec_min_101 = device_temp_101 < one_dec_min_limit ;
wire temp_cmp_two_dec_min_101 = device_temp_101 < two_dec_min_limit ;
wire temp_cmp_three_dec_min_101 = device_temp_101 < three_dec_min_limit ;
wire temp_cmp_four_dec_min_101 = device_temp_101 < four_dec_min_limit ;
// FSM arcs for increasing temperature.
wire temp_gte_four_inc_max = update_temp_102 & temp_cmp_four_inc_max_102;
wire temp_gte_three_inc_max = update_temp_102 & temp_cmp_three_inc_max_102;
wire temp_gte_two_inc_max = update_temp_102 & temp_cmp_two_inc_max_102;
wire temp_gte_one_inc_max = update_temp_102 & temp_cmp_one_inc_max_102;
wire temp_gte_neutral_max = update_temp_102 & temp_cmp_neutral_max_102;
wire temp_gte_one_dec_max = update_temp_102 & temp_cmp_one_dec_max_102;
wire temp_gte_two_dec_max = update_temp_102 & temp_cmp_two_dec_max_102;
wire temp_gte_three_dec_max = update_temp_102 & temp_cmp_three_dec_max_102;
// FSM arcs for decreasing temperature.
wire temp_lte_three_inc_min = update_temp_102 & temp_cmp_three_inc_min_102;
wire temp_lte_two_inc_min = update_temp_102 & temp_cmp_two_inc_min_102;
wire temp_lte_one_inc_min = update_temp_102 & temp_cmp_one_inc_min_102;
wire temp_lte_neutral_min = update_temp_102 & temp_cmp_neutral_min_102;
wire temp_lte_one_dec_min = update_temp_102 & temp_cmp_one_dec_min_102;
wire temp_lte_two_dec_min = update_temp_102 & temp_cmp_two_dec_min_102;
wire temp_lte_three_dec_min = update_temp_102 & temp_cmp_three_dec_min_102;
wire temp_lte_four_dec_min = update_temp_102 & temp_cmp_four_dec_min_102;
//===========================================================================
// Implement FSM
//===========================================================================
// In addition to the nine temperature states, there are also IDLE and INIT states.
// The INIT state triggers the calculation of the temperature boundaries between the
// other states. After INIT, the FSM will always go to the NEUTRAL state. There is
// no timing restriction required between calib_complete and tempmon_sample_en.
always @(*) begin
tempmon_state_nxt = tempmon_state;
tempmon_state_init = 1'b0;
pi_f_inc_nxt = 1'b0;
pi_f_dec_nxt = 1'b0;
casez (tempmon_state)
IDLE: begin
if (calib_complete) tempmon_state_nxt = INIT;
end
INIT: begin
tempmon_state_nxt = NEUTRAL;
tempmon_state_init = 1'b1;
end
FOUR_INC: begin
if (temp_gte_four_inc_max) begin
tempmon_state_nxt = THREE_INC;
pi_f_dec_nxt = 1'b1;
end
end
THREE_INC: begin
if (temp_gte_three_inc_max) begin
tempmon_state_nxt = TWO_INC;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_three_inc_min) begin
tempmon_state_nxt = FOUR_INC;
pi_f_inc_nxt = 1'b1;
end
end
TWO_INC: begin
if (temp_gte_two_inc_max) begin
tempmon_state_nxt = ONE_INC;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_two_inc_min) begin
tempmon_state_nxt = THREE_INC;
pi_f_inc_nxt = 1'b1;
end
end
ONE_INC: begin
if (temp_gte_one_inc_max) begin
tempmon_state_nxt = NEUTRAL;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_one_inc_min) begin
tempmon_state_nxt = TWO_INC;
pi_f_inc_nxt = 1'b1;
end
end
NEUTRAL: begin
if (temp_gte_neutral_max) begin
tempmon_state_nxt = ONE_DEC;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_neutral_min) begin
tempmon_state_nxt = ONE_INC;
pi_f_inc_nxt = 1'b1;
end
end
ONE_DEC: begin
if (temp_gte_one_dec_max) begin
tempmon_state_nxt = TWO_DEC;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_one_dec_min) begin
tempmon_state_nxt = NEUTRAL;
pi_f_inc_nxt = 1'b1;
end
end
TWO_DEC: begin
if (temp_gte_two_dec_max) begin
tempmon_state_nxt = THREE_DEC;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_two_dec_min) begin
tempmon_state_nxt = ONE_DEC;
pi_f_inc_nxt = 1'b1;
end
end
THREE_DEC: begin
if (temp_gte_three_dec_max) begin
tempmon_state_nxt = FOUR_DEC;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_three_dec_min) begin
tempmon_state_nxt = TWO_DEC;
pi_f_inc_nxt = 1'b1;
end
end
FOUR_DEC: begin
if (temp_lte_four_dec_min) begin
tempmon_state_nxt = THREE_DEC;
pi_f_inc_nxt = 1'b1;
end
end
default: begin
tempmon_state_nxt = IDLE;
end
endcase
end //always
//synopsys translate_off
reg [71:0] tempmon_state_name;
always @(*) casez (tempmon_state)
IDLE : tempmon_state_name = "IDLE";
INIT : tempmon_state_name = "INIT";
FOUR_INC : tempmon_state_name = "FOUR_INC";
THREE_INC : tempmon_state_name = "THREE_INC";
TWO_INC : tempmon_state_name = "TWO_INC";
ONE_INC : tempmon_state_name = "ONE_INC";
NEUTRAL : tempmon_state_name = "NEUTRAL";
ONE_DEC : tempmon_state_name = "ONE_DEC";
TWO_DEC : tempmon_state_name = "TWO_DEC";
THREE_DEC : tempmon_state_name = "THREE_DEC";
FOUR_DEC : tempmon_state_name = "FOUR_DEC";
default : tempmon_state_name = "BAD_STATE";
endcase
//synopsys translate_on
//===========================================================================
// Generate final output and implement flops
//===========================================================================
// Generate output
assign tempmon_pi_f_inc = pi_f_inc;
assign tempmon_pi_f_dec = pi_f_dec;
assign tempmon_sel_pi_incdec = pi_f_inc | pi_f_dec;
// Implement reset flops
always @(posedge clk) begin
if(rst) begin
tempmon_state <= #TCQ 11'b000_0000_0001;
pi_f_inc <= #TCQ 1'b0;
pi_f_dec <= #TCQ 1'b0;
four_inc_max_limit <= #TCQ 12'b0;
three_inc_max_limit <= #TCQ 12'b0;
two_inc_max_limit <= #TCQ 12'b0;
one_inc_max_limit <= #TCQ 12'b0;
neutral_max_limit <= #TCQ 12'b0;
one_dec_max_limit <= #TCQ 12'b0;
two_dec_max_limit <= #TCQ 12'b0;
three_dec_max_limit <= #TCQ 12'b0;
three_inc_min_limit <= #TCQ 12'b0;
two_inc_min_limit <= #TCQ 12'b0;
one_inc_min_limit <= #TCQ 12'b0;
neutral_min_limit <= #TCQ 12'b0;
one_dec_min_limit <= #TCQ 12'b0;
two_dec_min_limit <= #TCQ 12'b0;
three_dec_min_limit <= #TCQ 12'b0;
four_dec_min_limit <= #TCQ 12'b0;
device_temp_init <= #TCQ 12'b0;
tempmon_init_complete <= #TCQ 1'b0;
tempmon_sample_en_101 <= #TCQ 1'b0;
tempmon_sample_en_102 <= #TCQ 1'b0;
device_temp_101 <= #TCQ 12'b0;
device_temp_capture_102 <= #TCQ 12'b0;
end
else begin
tempmon_state <= #TCQ tempmon_state_nxt;
pi_f_inc <= #TCQ pi_f_inc_nxt;
pi_f_dec <= #TCQ pi_f_dec_nxt;
four_inc_max_limit <= #TCQ four_inc_max_limit_nxt;
three_inc_max_limit <= #TCQ three_inc_max_limit_nxt;
two_inc_max_limit <= #TCQ two_inc_max_limit_nxt;
one_inc_max_limit <= #TCQ one_inc_max_limit_nxt;
neutral_max_limit <= #TCQ neutral_max_limit_nxt;
one_dec_max_limit <= #TCQ one_dec_max_limit_nxt;
two_dec_max_limit <= #TCQ two_dec_max_limit_nxt;
three_dec_max_limit <= #TCQ three_dec_max_limit_nxt;
three_inc_min_limit <= #TCQ three_inc_min_limit_nxt;
two_inc_min_limit <= #TCQ two_inc_min_limit_nxt;
one_inc_min_limit <= #TCQ one_inc_min_limit_nxt;
neutral_min_limit <= #TCQ neutral_min_limit_nxt;
one_dec_min_limit <= #TCQ one_dec_min_limit_nxt;
two_dec_min_limit <= #TCQ two_dec_min_limit_nxt;
three_dec_min_limit <= #TCQ three_dec_min_limit_nxt;
four_dec_min_limit <= #TCQ four_dec_min_limit_nxt;
device_temp_init <= #TCQ device_temp_init_nxt;
tempmon_init_complete <= #TCQ tempmon_init_complete_nxt;
tempmon_sample_en_101 <= #TCQ tempmon_sample_en;
tempmon_sample_en_102 <= #TCQ tempmon_sample_en_101;
device_temp_101 <= #TCQ device_temp_100;
device_temp_capture_102 <= #TCQ device_temp_capture_101;
end
end
// Implement non-reset flops
always @(posedge clk) begin
temp_cmp_four_inc_max_102 <= #TCQ temp_cmp_four_inc_max_101;
temp_cmp_three_inc_max_102 <= #TCQ temp_cmp_three_inc_max_101;
temp_cmp_two_inc_max_102 <= #TCQ temp_cmp_two_inc_max_101;
temp_cmp_one_inc_max_102 <= #TCQ temp_cmp_one_inc_max_101;
temp_cmp_neutral_max_102 <= #TCQ temp_cmp_neutral_max_101;
temp_cmp_one_dec_max_102 <= #TCQ temp_cmp_one_dec_max_101;
temp_cmp_two_dec_max_102 <= #TCQ temp_cmp_two_dec_max_101;
temp_cmp_three_dec_max_102 <= #TCQ temp_cmp_three_dec_max_101;
temp_cmp_three_inc_min_102 <= #TCQ temp_cmp_three_inc_min_101;
temp_cmp_two_inc_min_102 <= #TCQ temp_cmp_two_inc_min_101;
temp_cmp_one_inc_min_102 <= #TCQ temp_cmp_one_inc_min_101;
temp_cmp_neutral_min_102 <= #TCQ temp_cmp_neutral_min_101;
temp_cmp_one_dec_min_102 <= #TCQ temp_cmp_one_dec_min_101;
temp_cmp_two_dec_min_102 <= #TCQ temp_cmp_two_dec_min_101;
temp_cmp_three_dec_min_102 <= #TCQ temp_cmp_three_dec_min_101;
temp_cmp_four_dec_min_102 <= #TCQ temp_cmp_four_dec_min_101;
update_temp_102 <= #TCQ update_temp_101;
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_sq_arb # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [8:0] sq_rst_n,
input [8:0] sq_valid,
input [7:0] admin_sq_size,
input [7:0] io_sq1_size,
input [7:0] io_sq2_size,
input [7:0] io_sq3_size,
input [7:0] io_sq4_size,
input [7:0] io_sq5_size,
input [7:0] io_sq6_size,
input [7:0] io_sq7_size,
input [7:0] io_sq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] admin_sq_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
input [7:0] admin_sq_tail_ptr,
input [7:0] io_sq1_tail_ptr,
input [7:0] io_sq2_tail_ptr,
input [7:0] io_sq3_tail_ptr,
input [7:0] io_sq4_tail_ptr,
input [7:0] io_sq5_tail_ptr,
input [7:0] io_sq6_tail_ptr,
input [7:0] io_sq7_tail_ptr,
input [7:0] io_sq8_tail_ptr,
output arb_sq_rdy,
output [3:0] sq_qid,
output [C_PCIE_ADDR_WIDTH-1:2] hcmd_pcie_addr,
input sq_hcmd_ack
);
localparam S_ARB_HCMD = 5'b00001;
localparam S_LOAD_HEAD_PTR = 5'b00010;
localparam S_CALC_ADDR = 5'b00100;
localparam S_GNT_HCMD = 5'b01000;
localparam S_UPDATE_HEAD_PTR = 5'b10000;
reg [4:0] cur_state;
reg [4:0] next_state;
reg [7:0] r_admin_sq_head_ptr;
reg [7:0] r_io_sq1_head_ptr;
reg [7:0] r_io_sq2_head_ptr;
reg [7:0] r_io_sq3_head_ptr;
reg [7:0] r_io_sq4_head_ptr;
reg [7:0] r_io_sq5_head_ptr;
reg [7:0] r_io_sq6_head_ptr;
reg [7:0] r_io_sq7_head_ptr;
reg [7:0] r_io_sq8_head_ptr;
reg r_arb_sq_rdy;
reg [3:0] r_sq_qid;
reg [7:0] r_sq_head_ptr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_hcmd_pcie_addr;
wire [8:0] w_sq_entry_valid;
wire w_sq_entry_valid_ok;
reg [8:0] r_sq_entry_valid;
wire [8:0] w_sq_valid_mask;
reg [8:0] r_sq_update_entry;
wire [8:0] w_sq_rst_n;
assign arb_sq_rdy = r_arb_sq_rdy;
assign sq_qid = r_sq_qid;
assign hcmd_pcie_addr = r_hcmd_pcie_addr;
assign w_sq_entry_valid[0] = (r_admin_sq_head_ptr != admin_sq_tail_ptr) & sq_valid[0];
assign w_sq_entry_valid[1] = (r_io_sq1_head_ptr != io_sq1_tail_ptr) & sq_valid[1];
assign w_sq_entry_valid[2] = (r_io_sq2_head_ptr != io_sq2_tail_ptr) & sq_valid[2];
assign w_sq_entry_valid[3] = (r_io_sq3_head_ptr != io_sq3_tail_ptr) & sq_valid[3];
assign w_sq_entry_valid[4] = (r_io_sq4_head_ptr != io_sq4_tail_ptr) & sq_valid[4];
assign w_sq_entry_valid[5] = (r_io_sq5_head_ptr != io_sq5_tail_ptr) & sq_valid[5];
assign w_sq_entry_valid[6] = (r_io_sq6_head_ptr != io_sq6_tail_ptr) & sq_valid[6];
assign w_sq_entry_valid[7] = (r_io_sq7_head_ptr != io_sq7_tail_ptr) & sq_valid[7];
assign w_sq_entry_valid[8] = (r_io_sq8_head_ptr != io_sq8_tail_ptr) & sq_valid[8];
assign w_sq_valid_mask = {r_sq_entry_valid[7:0], r_sq_entry_valid[8]};
assign w_sq_entry_valid_ok = ((w_sq_entry_valid[8:1] & w_sq_valid_mask[8:1]) != 0) | w_sq_entry_valid[0];
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_ARB_HCMD;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_ARB_HCMD: begin
if(w_sq_entry_valid_ok == 1)
next_state <= S_LOAD_HEAD_PTR;
else
next_state <= S_ARB_HCMD;
end
S_LOAD_HEAD_PTR: begin
next_state <= S_CALC_ADDR;
end
S_CALC_ADDR: begin
next_state <= S_GNT_HCMD;
end
S_GNT_HCMD: begin
if(sq_hcmd_ack == 1)
next_state <= S_UPDATE_HEAD_PTR;
else
next_state <= S_GNT_HCMD;
end
S_UPDATE_HEAD_PTR: begin
next_state <= S_ARB_HCMD;
end
default: begin
next_state <= S_ARB_HCMD;
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_sq_entry_valid <= 1;
end
else begin
case(cur_state)
S_ARB_HCMD: begin
if(w_sq_entry_valid[0] == 1)
r_sq_entry_valid <= 1;
else
r_sq_entry_valid <= w_sq_valid_mask;
end
S_LOAD_HEAD_PTR: begin
end
S_CALC_ADDR: begin
end
S_GNT_HCMD: begin
end
S_UPDATE_HEAD_PTR: begin
end
default: begin
end
endcase
end
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_ARB_HCMD: begin
end
S_LOAD_HEAD_PTR: begin
case(r_sq_entry_valid) // synthesis parallel_case full_case
9'b000000001: begin
r_hcmd_pcie_addr <= admin_sq_bs_addr;
r_sq_head_ptr <= r_admin_sq_head_ptr;
end
9'b000000010: begin
r_hcmd_pcie_addr <= io_sq1_bs_addr;
r_sq_head_ptr <= r_io_sq1_head_ptr;
end
9'b000000100: begin
r_hcmd_pcie_addr <= io_sq2_bs_addr;
r_sq_head_ptr <= r_io_sq2_head_ptr;
end
9'b000001000: begin
r_hcmd_pcie_addr <= io_sq3_bs_addr;
r_sq_head_ptr <= r_io_sq3_head_ptr;
end
9'b000010000: begin
r_hcmd_pcie_addr <= io_sq4_bs_addr;
r_sq_head_ptr <= r_io_sq4_head_ptr;
end
9'b000100000: begin
r_hcmd_pcie_addr <= io_sq5_bs_addr;
r_sq_head_ptr <= r_io_sq5_head_ptr;
end
9'b001000000: begin
r_hcmd_pcie_addr <= io_sq6_bs_addr;
r_sq_head_ptr <= r_io_sq6_head_ptr;
end
9'b010000000: begin
r_hcmd_pcie_addr <= io_sq7_bs_addr;
r_sq_head_ptr <= r_io_sq7_head_ptr;
end
9'b100000000: begin
r_hcmd_pcie_addr <= io_sq8_bs_addr;
r_sq_head_ptr <= r_io_sq8_head_ptr;
end
endcase
end
S_CALC_ADDR: begin
r_hcmd_pcie_addr <= r_hcmd_pcie_addr + {r_sq_head_ptr, 4'b0};
r_sq_head_ptr <= r_sq_head_ptr + 1;
end
S_GNT_HCMD: begin
end
S_UPDATE_HEAD_PTR: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_ARB_HCMD: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= 0;
end
S_LOAD_HEAD_PTR: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= 0;
end
S_CALC_ADDR: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= 0;
end
S_GNT_HCMD: begin
r_arb_sq_rdy <= 1;
r_sq_update_entry <= 0;
end
S_UPDATE_HEAD_PTR: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= r_sq_entry_valid;
end
default: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= 0;
end
endcase
end
always @ (*)
begin
case(r_sq_entry_valid) // synthesis parallel_case full_case
9'b000000001: r_sq_qid <= 4'h0;
9'b000000010: r_sq_qid <= 4'h1;
9'b000000100: r_sq_qid <= 4'h2;
9'b000001000: r_sq_qid <= 4'h3;
9'b000010000: r_sq_qid <= 4'h4;
9'b000100000: r_sq_qid <= 4'h5;
9'b001000000: r_sq_qid <= 4'h6;
9'b010000000: r_sq_qid <= 4'h7;
9'b100000000: r_sq_qid <= 4'h8;
endcase
end
assign w_sq_rst_n[0] = pcie_user_rst_n & sq_rst_n[0];
assign w_sq_rst_n[1] = pcie_user_rst_n & sq_rst_n[1];
assign w_sq_rst_n[2] = pcie_user_rst_n & sq_rst_n[2];
assign w_sq_rst_n[3] = pcie_user_rst_n & sq_rst_n[3];
assign w_sq_rst_n[4] = pcie_user_rst_n & sq_rst_n[4];
assign w_sq_rst_n[5] = pcie_user_rst_n & sq_rst_n[5];
assign w_sq_rst_n[6] = pcie_user_rst_n & sq_rst_n[6];
assign w_sq_rst_n[7] = pcie_user_rst_n & sq_rst_n[7];
assign w_sq_rst_n[8] = pcie_user_rst_n & sq_rst_n[8];
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[0])
begin
if(w_sq_rst_n[0] == 0) begin
r_admin_sq_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[0] == 1) begin
if(r_admin_sq_head_ptr == admin_sq_size) begin
r_admin_sq_head_ptr <= 0;
end
else begin
r_admin_sq_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[1])
begin
if(w_sq_rst_n[1] == 0) begin
r_io_sq1_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[1] == 1) begin
if(r_io_sq1_head_ptr == io_sq1_size) begin
r_io_sq1_head_ptr <= 0;
end
else begin
r_io_sq1_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[2])
begin
if(w_sq_rst_n[2] == 0) begin
r_io_sq2_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[2] == 1) begin
if(r_io_sq2_head_ptr == io_sq2_size) begin
r_io_sq2_head_ptr <= 0;
end
else begin
r_io_sq2_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[3])
begin
if(w_sq_rst_n[3] == 0) begin
r_io_sq3_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[3] == 1) begin
if(r_io_sq3_head_ptr == io_sq3_size) begin
r_io_sq3_head_ptr <= 0;
end
else begin
r_io_sq3_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[4])
begin
if(w_sq_rst_n[4] == 0) begin
r_io_sq4_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[4] == 1) begin
if(r_io_sq4_head_ptr == io_sq4_size) begin
r_io_sq4_head_ptr <= 0;
end
else begin
r_io_sq4_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[5])
begin
if(w_sq_rst_n[5] == 0) begin
r_io_sq5_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[5] == 1) begin
if(r_io_sq5_head_ptr == io_sq5_size) begin
r_io_sq5_head_ptr <= 0;
end
else begin
r_io_sq5_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[6])
begin
if(w_sq_rst_n[6] == 0) begin
r_io_sq6_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[6] == 1) begin
if(r_io_sq6_head_ptr == io_sq6_size) begin
r_io_sq6_head_ptr <= 0;
end
else begin
r_io_sq6_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[7])
begin
if(w_sq_rst_n[7] == 0) begin
r_io_sq7_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[7] == 1) begin
if(r_io_sq7_head_ptr == io_sq7_size) begin
r_io_sq7_head_ptr <= 0;
end
else begin
r_io_sq7_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[8])
begin
if(w_sq_rst_n[8] == 0) begin
r_io_sq8_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[8] == 1) begin
if(r_io_sq8_head_ptr == io_sq8_size) begin
r_io_sq8_head_ptr <= 0;
end
else begin
r_io_sq8_head_ptr <= r_sq_head_ptr;
end
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DLATCH_P_PP_SN_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DLATCH_P_PP_SN_SYMBOL_V
/**
* udp_dlatch$P_pp$sN: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dlatch$P_pp$sN (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input SLEEP_B ,
input NOTIFIER
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DLATCH_P_PP_SN_SYMBOL_V
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: ram_controller_phy_alt_mem_phy_pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.0.0 Build 211 04/27/2016 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram_controller_phy_alt_mem_phy_pll (
areset,
inclk0,
phasecounterselect,
phasestep,
phaseupdown,
scanclk,
c0,
c1,
c2,
c3,
c4,
locked,
phasedone);
input areset;
input inclk0;
input [2:0] phasecounterselect;
input phasestep;
input phaseupdown;
input scanclk;
output c0;
output c1;
output c2;
output c3;
output c4;
output locked;
output phasedone;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [2:0] phasecounterselect;
tri0 phasestep;
tri0 phaseupdown;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] sub_wire0;
wire sub_wire6;
wire sub_wire7;
wire [0:0] sub_wire10 = 1'h0;
wire [4:4] sub_wire5 = sub_wire0[4:4];
wire [3:3] sub_wire4 = sub_wire0[3:3];
wire [2:2] sub_wire3 = sub_wire0[2:2];
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire c2 = sub_wire3;
wire c3 = sub_wire4;
wire c4 = sub_wire5;
wire locked = sub_wire6;
wire phasedone = sub_wire7;
wire sub_wire8 = inclk0;
wire [1:0] sub_wire9 = {sub_wire10, sub_wire8};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire9),
.phasecounterselect (phasecounterselect),
.phasestep (phasestep),
.phaseupdown (phaseupdown),
.scanclk (scanclk),
.clk (sub_wire0),
.locked (sub_wire6),
.phasedone (sub_wire7),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 100,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 133,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 50,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 133,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 50,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 133,
altpll_component.clk2_phase_shift = "-1880",
altpll_component.clk3_divide_by = 50,
altpll_component.clk3_duty_cycle = 50,
altpll_component.clk3_multiply_by = 133,
altpll_component.clk3_phase_shift = "0",
altpll_component.clk4_divide_by = 50,
altpll_component.clk4_duty_cycle = 50,
altpll_component.clk4_multiply_by = 133,
altpll_component.clk4_phase_shift = "0",
altpll_component.compensate_clock = "CLK1",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_USED",
altpll_component.port_phasedone = "PORT_USED",
altpll_component.port_phasestep = "PORT_USED",
altpll_component.port_phaseupdown = "PORT_USED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_USED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_USED",
altpll_component.port_clk4 = "PORT_USED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.vco_frequency_control = "MANUAL_PHASE",
altpll_component.vco_phase_shift_step = 117,
altpll_component.width_clock = 5,
altpll_component.width_phasecounterselect = 3;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c1"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "66.500000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "133.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "133.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "133.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "133.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "deg"
// Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_EDIT STRING "117.00000000"
// Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_UNIT STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2"
// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
// Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "2"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "66.50000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "133.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "133.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "133.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "133.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "1"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-90.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "1"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "alt_mem_phy_pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
// Retrieval info: PRIVATE: USE_CLK4 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "100"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "133"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "133"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "133"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-1880"
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "50"
// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "133"
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "50"
// Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "133"
// Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK1"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: VCO_FREQUENCY_CONTROL STRING "MANUAL_PHASE"
// Retrieval info: CONSTANT: VCO_PHASE_SHIFT_STEP NUMERIC "117"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: CONSTANT: WIDTH_PHASECOUNTERSELECT NUMERIC "3"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
// Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: USED_PORT: phasecounterselect 0 0 3 0 INPUT GND "phasecounterselect[2..0]"
// Retrieval info: USED_PORT: phasedone 0 0 0 0 OUTPUT GND "phasedone"
// Retrieval info: USED_PORT: phasestep 0 0 0 0 INPUT GND "phasestep"
// Retrieval info: USED_PORT: phaseupdown 0 0 0 0 INPUT GND "phaseupdown"
// Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: @phasecounterselect 0 0 3 0 phasecounterselect 0 0 3 0
// Retrieval info: CONNECT: @phasestep 0 0 0 0 phasestep 0 0 0 0
// Retrieval info: CONNECT: @phaseupdown 0 0 0 0 phaseupdown 0 0 0 0
// Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
// Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: CONNECT: phasedone 0 0 0 0 @phasedone 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_phy_pll_wave*.jpg FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_controller_phy_alt_mem_phy_pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_controller_phy_alt_mem_phy_pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_controller_phy_alt_mem_phy_pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_controller_phy_alt_mem_phy_pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_controller_phy_alt_mem_phy_pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_controller_phy_alt_mem_phy_pll_bb.v TRUE
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: AXI Splitter
// Each transfer received on the AXI handshake slave port is replicated onto
// each of the master ports, and is completed back to the slave (S_READY)
// once all master ports have completed.
//
// M_VALID is asserted combinatorially from S_VALID assertion.
// Each M_VALID is masked off beginning the cycle after each M_READY is
// received (if S_READY remains low) until the cycle after both S_VALID
// and S_READY are asserted.
// S_READY is asserted combinatorially when the last (or all) of the M_READY
// inputs have been received.
// If all M_READYs are asserted when S_VALID is asserted, back-to-back
// handshakes can occur without bubble cycles.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// splitter
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_splitter #
(
parameter integer C_NUM_M = 2 // Number of master ports = [2:16]
)
(
// Global Signals
input wire ACLK,
input wire ARESET,
// Slave Port
input wire S_VALID,
output wire S_READY,
// Master Ports
output wire [C_NUM_M-1:0] M_VALID,
input wire [C_NUM_M-1:0] M_READY
);
reg [C_NUM_M-1:0] m_ready_d;
wire s_ready_i;
wire [C_NUM_M-1:0] m_valid_i;
always @(posedge ACLK) begin
if (ARESET | s_ready_i) m_ready_d <= {C_NUM_M{1'b0}};
else m_ready_d <= m_ready_d | (m_valid_i & M_READY);
end
assign s_ready_i = &(m_ready_d | M_READY);
assign m_valid_i = {C_NUM_M{S_VALID}} & ~m_ready_d;
assign M_VALID = m_valid_i;
assign S_READY = s_ready_i;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [127:0] i;
wire [127:0] q1;
wire [127:0] q32;
wire [127:0] q64;
wire [63:0] q64_low;
assign q1 = {
i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4],
i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4],
i[8*4], i[9*4], i[10*4], i[11*4], i[12*4], i[13*4], i[14*4], i[15*4],
i[0*4], i[1*4], i[2*4], i[3*4], i[4*4], i[5*4], i[6*4], i[7*4],
i[24*4+1], i[25*4+1], i[26*4+1], i[27*4+1], i[28*4+1], i[29*4+1], i[30*4+1], i[31*4+1],
i[16*4+1], i[17*4+1], i[18*4+1], i[19*4+1], i[20*4+1], i[21*4+1], i[22*4+1], i[23*4+1],
i[8*4+1], i[9*4+1], i[10*4+1], i[11*4+1], i[12*4+1], i[13*4+1], i[14*4+1], i[15*4+1],
i[0*4+1], i[1*4+1], i[2*4+1], i[3*4+1], i[4*4+1], i[5*4+1], i[6*4+1], i[7*4+1],
i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2],
i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2],
i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2],
i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2],
i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3],
i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3],
i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3],
i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]};
assign q64[127:64] = {
i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4],
i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4],
i[8*4], i[9*4], i[10*4], i[11*4], i[12*4], i[13*4], i[14*4], i[15*4],
i[0*4], i[1*4], i[2*4], i[3*4], i[4*4], i[5*4], i[6*4], i[7*4],
i[24*4+1], i[25*4+1], i[26*4+1], i[27*4+1], i[28*4+1], i[29*4+1], i[30*4+1], i[31*4+1],
i[16*4+1], i[17*4+1], i[18*4+1], i[19*4+1], i[20*4+1], i[21*4+1], i[22*4+1], i[23*4+1],
i[8*4+1], i[9*4+1], i[10*4+1], i[11*4+1], i[12*4+1], i[13*4+1], i[14*4+1], i[15*4+1],
i[0*4+1], i[1*4+1], i[2*4+1], i[3*4+1], i[4*4+1], i[5*4+1], i[6*4+1], i[7*4+1]};
assign q64[63:0] = {
i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2],
i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2],
i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2],
i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2],
i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3],
i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3],
i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3],
i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]};
assign q64_low = {
i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2],
i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2],
i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2],
i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2],
i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3],
i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3],
i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3],
i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]};
assign q32[127:96] = {
i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4],
i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4],
i[8*4], i[9*4], i[10*4], i[11*4], i[12*4], i[13*4], i[14*4], i[15*4],
i[0*4], i[1*4], i[2*4], i[3*4], i[4*4], i[5*4], i[6*4], i[7*4]};
assign q32[95:64] = {
i[24*4+1], i[25*4+1], i[26*4+1], i[27*4+1], i[28*4+1], i[29*4+1], i[30*4+1], i[31*4+1],
i[16*4+1], i[17*4+1], i[18*4+1], i[19*4+1], i[20*4+1], i[21*4+1], i[22*4+1], i[23*4+1],
i[8*4+1], i[9*4+1], i[10*4+1], i[11*4+1], i[12*4+1], i[13*4+1], i[14*4+1], i[15*4+1],
i[0*4+1], i[1*4+1], i[2*4+1], i[3*4+1], i[4*4+1], i[5*4+1], i[6*4+1], i[7*4+1]};
assign q32[63:32] = {
i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2],
i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2],
i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2],
i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2]};
assign q32[31:0] = {
i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3],
i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3],
i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3],
i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]};
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("%x %x\n", q1, i);
`endif
if (cyc==1) begin
i <= 128'hed388e646c843d35de489bab2413d770;
end
if (cyc==2) begin
i <= 128'h0e17c88f3d5fe51a982646c8e2bd68c3;
if (q1 != 128'h06f0b17c6551e269e3ab07723b26fb10) $stop;
if (q1 != q32) $stop;
if (q1 != q64) $stop;
if (q1[63:0] != q64_low) $stop;
end
if (cyc==3) begin
i <= 128'he236ddfddddbdad20a48e039c9f395b8;
if (q1 != 128'h8c6f018c8a992c979a3e7859f29ac36d) $stop;
if (q1 != q32) $stop;
if (q1 != q64) $stop;
if (q1[63:0] != q64_low) $stop;
end
if (cyc==4) begin
i <= 128'h45e0eb7642b148537491f3da147e7f26;
if (q1 != 128'hf45fc07e4fa8524cf9571425f17f9ad7) $stop;
if (q1 != q32) $stop;
if (q1 != q64) $stop;
if (q1[63:0] != q64_low) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.1
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="nfa_accept_samples_generic_hw,hls_ip_2014_1,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc5vlx50tff1136-3,HLS_INPUT_CLOCK=7.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=5.200000,HLS_SYN_LAT=53290010,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=0,HLS_SYN_LUT=0}" *)
module nfa_accept_samples_generic_hw (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
nfa_initials_buckets_req_din,
nfa_initials_buckets_req_full_n,
nfa_initials_buckets_req_write,
nfa_initials_buckets_rsp_empty_n,
nfa_initials_buckets_rsp_read,
nfa_initials_buckets_address,
nfa_initials_buckets_datain,
nfa_initials_buckets_dataout,
nfa_initials_buckets_size,
nfa_finals_buckets_req_din,
nfa_finals_buckets_req_full_n,
nfa_finals_buckets_req_write,
nfa_finals_buckets_rsp_empty_n,
nfa_finals_buckets_rsp_read,
nfa_finals_buckets_address,
nfa_finals_buckets_datain,
nfa_finals_buckets_dataout,
nfa_finals_buckets_size,
nfa_forward_buckets_req_din,
nfa_forward_buckets_req_full_n,
nfa_forward_buckets_req_write,
nfa_forward_buckets_rsp_empty_n,
nfa_forward_buckets_rsp_read,
nfa_forward_buckets_address,
nfa_forward_buckets_datain,
nfa_forward_buckets_dataout,
nfa_forward_buckets_size,
nfa_symbols,
sample_buffer_req_din,
sample_buffer_req_full_n,
sample_buffer_req_write,
sample_buffer_rsp_empty_n,
sample_buffer_rsp_read,
sample_buffer_address,
sample_buffer_datain,
sample_buffer_dataout,
sample_buffer_size,
sample_buffer_length,
sample_length,
indices_req_din,
indices_req_full_n,
indices_req_write,
indices_rsp_empty_n,
indices_rsp_read,
indices_address,
indices_datain,
indices_dataout,
indices_size,
i_size,
begin_index,
begin_sample,
end_index,
end_sample,
stop_on_first,
accept,
ap_return
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 6'b000000;
parameter ap_ST_st2_fsm_1 = 6'b1;
parameter ap_ST_st3_fsm_2 = 6'b10;
parameter ap_ST_st4_fsm_3 = 6'b11;
parameter ap_ST_st5_fsm_4 = 6'b100;
parameter ap_ST_st6_fsm_5 = 6'b101;
parameter ap_ST_st7_fsm_6 = 6'b110;
parameter ap_ST_st8_fsm_7 = 6'b111;
parameter ap_ST_st9_fsm_8 = 6'b1000;
parameter ap_ST_st10_fsm_9 = 6'b1001;
parameter ap_ST_st11_fsm_10 = 6'b1010;
parameter ap_ST_st12_fsm_11 = 6'b1011;
parameter ap_ST_st13_fsm_12 = 6'b1100;
parameter ap_ST_st14_fsm_13 = 6'b1101;
parameter ap_ST_st15_fsm_14 = 6'b1110;
parameter ap_ST_st16_fsm_15 = 6'b1111;
parameter ap_ST_st17_fsm_16 = 6'b10000;
parameter ap_ST_st18_fsm_17 = 6'b10001;
parameter ap_ST_st19_fsm_18 = 6'b10010;
parameter ap_ST_st20_fsm_19 = 6'b10011;
parameter ap_ST_st21_fsm_20 = 6'b10100;
parameter ap_ST_st22_fsm_21 = 6'b10101;
parameter ap_ST_st23_fsm_22 = 6'b10110;
parameter ap_ST_st24_fsm_23 = 6'b10111;
parameter ap_ST_st25_fsm_24 = 6'b11000;
parameter ap_ST_st26_fsm_25 = 6'b11001;
parameter ap_ST_st27_fsm_26 = 6'b11010;
parameter ap_ST_st28_fsm_27 = 6'b11011;
parameter ap_ST_st29_fsm_28 = 6'b11100;
parameter ap_ST_st30_fsm_29 = 6'b11101;
parameter ap_ST_st31_fsm_30 = 6'b11110;
parameter ap_ST_st32_fsm_31 = 6'b11111;
parameter ap_ST_st33_fsm_32 = 6'b100000;
parameter ap_ST_st34_fsm_33 = 6'b100001;
parameter ap_ST_st35_fsm_34 = 6'b100010;
parameter ap_ST_st36_fsm_35 = 6'b100011;
parameter ap_ST_st37_fsm_36 = 6'b100100;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv16_0 = 16'b0000000000000000;
parameter ap_const_lv64_0 = 64'b0000000000000000000000000000000000000000000000000000000000000000;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv2_2 = 2'b10;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv64_1 = 64'b1;
parameter ap_const_lv16_1 = 16'b1;
parameter ap_const_lv5_0 = 5'b00000;
parameter ap_const_lv8_0 = 8'b00000000;
parameter ap_true = 1'b1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
output nfa_initials_buckets_req_din;
input nfa_initials_buckets_req_full_n;
output nfa_initials_buckets_req_write;
input nfa_initials_buckets_rsp_empty_n;
output nfa_initials_buckets_rsp_read;
output [31:0] nfa_initials_buckets_address;
input [31:0] nfa_initials_buckets_datain;
output [31:0] nfa_initials_buckets_dataout;
output [31:0] nfa_initials_buckets_size;
output nfa_finals_buckets_req_din;
input nfa_finals_buckets_req_full_n;
output nfa_finals_buckets_req_write;
input nfa_finals_buckets_rsp_empty_n;
output nfa_finals_buckets_rsp_read;
output [31:0] nfa_finals_buckets_address;
input [31:0] nfa_finals_buckets_datain;
output [31:0] nfa_finals_buckets_dataout;
output [31:0] nfa_finals_buckets_size;
output nfa_forward_buckets_req_din;
input nfa_forward_buckets_req_full_n;
output nfa_forward_buckets_req_write;
input nfa_forward_buckets_rsp_empty_n;
output nfa_forward_buckets_rsp_read;
output [31:0] nfa_forward_buckets_address;
input [31:0] nfa_forward_buckets_datain;
output [31:0] nfa_forward_buckets_dataout;
output [31:0] nfa_forward_buckets_size;
input [7:0] nfa_symbols;
output sample_buffer_req_din;
input sample_buffer_req_full_n;
output sample_buffer_req_write;
input sample_buffer_rsp_empty_n;
output sample_buffer_rsp_read;
output [31:0] sample_buffer_address;
input [7:0] sample_buffer_datain;
output [7:0] sample_buffer_dataout;
output [31:0] sample_buffer_size;
input [31:0] sample_buffer_length;
input [15:0] sample_length;
output indices_req_din;
input indices_req_full_n;
output indices_req_write;
input indices_rsp_empty_n;
output indices_rsp_read;
output [31:0] indices_address;
input [55:0] indices_datain;
output [55:0] indices_dataout;
output [31:0] indices_size;
input [15:0] i_size;
input [15:0] begin_index;
input [15:0] begin_sample;
input [15:0] end_index;
input [15:0] end_sample;
input [0:0] stop_on_first;
input [0:0] accept;
output [31:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg nfa_forward_buckets_req_write;
reg nfa_forward_buckets_rsp_read;
reg[31:0] nfa_forward_buckets_address;
reg sample_buffer_req_write;
reg sample_buffer_rsp_read;
reg indices_req_din;
reg indices_req_write;
reg indices_rsp_read;
reg[31:0] indices_address;
reg[55:0] indices_dataout;
reg[31:0] indices_size;
reg [5:0] ap_CS_fsm = 6'b000000;
reg [31:0] reg_512;
wire [0:0] stop_on_first_read_read_fu_150_p2;
reg [31:0] c_load_reg_813;
reg [31:0] current_buckets_0_reg_822;
reg [31:0] current_buckets_1_reg_827;
wire [63:0] tmp_2_fu_548_p1;
reg [63:0] tmp_2_reg_832;
reg [31:0] sample_buffer_addr_reg_837;
wire [15:0] i_fu_568_p2;
reg [15:0] i_reg_846;
wire [63:0] p_rec_i_fu_574_p2;
reg [63:0] p_rec_i_reg_851;
wire [0:0] tmp_3_fu_563_p2;
reg [7:0] sym_reg_856;
wire [0:0] tmp_2_i_fu_580_p2;
reg [0:0] tmp_2_i_reg_861;
wire [0:0] tmp_2_1_i_fu_586_p2;
reg [0:0] tmp_2_1_i_reg_865;
wire [4:0] r_bit_p_bsf32_hw_fu_506_ap_return;
reg [4:0] r_bit_reg_869;
wire [7:0] j_bucket_index1_ph_cast_fu_597_p1;
wire [7:0] j_bit1_ph_cast_fu_601_p1;
wire [13:0] tmp_10_i_cast_fu_605_p1;
reg [13:0] tmp_10_i_cast_reg_884;
wire [0:0] j_end_phi_fu_417_p4;
wire [13:0] tmp_11_i_fu_644_p2;
reg [13:0] tmp_11_i_reg_899;
reg [7:0] j_bit_reg_911;
reg [7:0] j_bucket_index_reg_916;
reg [31:0] j_bucket_reg_921;
reg [0:0] p_s_reg_926;
wire [31:0] next_buckets_0_1_fu_701_p2;
reg [31:0] next_buckets_0_1_reg_937;
wire [31:0] next_buckets_1_1_fu_707_p2;
reg [31:0] tmp_buckets_0_reg_947;
reg [31:0] tmp_buckets_1_reg_952;
wire [0:0] tmp_5_fu_737_p2;
wire grp_bitset_next_fu_460_ap_start;
wire grp_bitset_next_fu_460_ap_done;
wire grp_bitset_next_fu_460_ap_idle;
wire grp_bitset_next_fu_460_ap_ready;
wire grp_bitset_next_fu_460_ap_ce;
wire [31:0] grp_bitset_next_fu_460_p_read;
wire [7:0] grp_bitset_next_fu_460_r_bit;
wire [7:0] grp_bitset_next_fu_460_r_bucket_index;
wire [31:0] grp_bitset_next_fu_460_r_bucket;
wire [7:0] grp_bitset_next_fu_460_ap_return_0;
wire [7:0] grp_bitset_next_fu_460_ap_return_1;
wire [31:0] grp_bitset_next_fu_460_ap_return_2;
wire [0:0] grp_bitset_next_fu_460_ap_return_3;
wire grp_sample_iterator_next_fu_472_ap_start;
wire grp_sample_iterator_next_fu_472_ap_done;
wire grp_sample_iterator_next_fu_472_ap_idle;
wire grp_sample_iterator_next_fu_472_ap_ready;
wire grp_sample_iterator_next_fu_472_indices_req_din;
wire grp_sample_iterator_next_fu_472_indices_req_full_n;
wire grp_sample_iterator_next_fu_472_indices_req_write;
wire grp_sample_iterator_next_fu_472_indices_rsp_empty_n;
wire grp_sample_iterator_next_fu_472_indices_rsp_read;
wire [31:0] grp_sample_iterator_next_fu_472_indices_address;
wire [55:0] grp_sample_iterator_next_fu_472_indices_datain;
wire [55:0] grp_sample_iterator_next_fu_472_indices_dataout;
wire [31:0] grp_sample_iterator_next_fu_472_indices_size;
wire grp_sample_iterator_next_fu_472_ap_ce;
wire [15:0] grp_sample_iterator_next_fu_472_i_index;
wire [15:0] grp_sample_iterator_next_fu_472_i_sample;
wire [15:0] grp_sample_iterator_next_fu_472_ap_return_0;
wire [15:0] grp_sample_iterator_next_fu_472_ap_return_1;
wire grp_sample_iterator_get_offset_fu_482_ap_start;
wire grp_sample_iterator_get_offset_fu_482_ap_done;
wire grp_sample_iterator_get_offset_fu_482_ap_idle;
wire grp_sample_iterator_get_offset_fu_482_ap_ready;
wire grp_sample_iterator_get_offset_fu_482_indices_req_din;
wire grp_sample_iterator_get_offset_fu_482_indices_req_full_n;
wire grp_sample_iterator_get_offset_fu_482_indices_req_write;
wire grp_sample_iterator_get_offset_fu_482_indices_rsp_empty_n;
wire grp_sample_iterator_get_offset_fu_482_indices_rsp_read;
wire [31:0] grp_sample_iterator_get_offset_fu_482_indices_address;
wire [55:0] grp_sample_iterator_get_offset_fu_482_indices_datain;
wire [55:0] grp_sample_iterator_get_offset_fu_482_indices_dataout;
wire [31:0] grp_sample_iterator_get_offset_fu_482_indices_size;
wire grp_sample_iterator_get_offset_fu_482_ap_ce;
wire [15:0] grp_sample_iterator_get_offset_fu_482_i_index;
wire [15:0] grp_sample_iterator_get_offset_fu_482_i_sample;
wire [31:0] grp_sample_iterator_get_offset_fu_482_sample_buffer_size;
wire [15:0] grp_sample_iterator_get_offset_fu_482_sample_length;
wire [31:0] grp_sample_iterator_get_offset_fu_482_ap_return;
wire grp_nfa_get_initials_fu_494_ap_start;
wire grp_nfa_get_initials_fu_494_ap_done;
wire grp_nfa_get_initials_fu_494_ap_idle;
wire grp_nfa_get_initials_fu_494_ap_ready;
wire grp_nfa_get_initials_fu_494_ap_ce;
wire grp_nfa_get_initials_fu_494_nfa_initials_buckets_req_din;
wire grp_nfa_get_initials_fu_494_nfa_initials_buckets_req_full_n;
wire grp_nfa_get_initials_fu_494_nfa_initials_buckets_req_write;
wire grp_nfa_get_initials_fu_494_nfa_initials_buckets_rsp_empty_n;
wire grp_nfa_get_initials_fu_494_nfa_initials_buckets_rsp_read;
wire [31:0] grp_nfa_get_initials_fu_494_nfa_initials_buckets_address;
wire [31:0] grp_nfa_get_initials_fu_494_nfa_initials_buckets_datain;
wire [31:0] grp_nfa_get_initials_fu_494_nfa_initials_buckets_dataout;
wire [31:0] grp_nfa_get_initials_fu_494_nfa_initials_buckets_size;
wire [31:0] grp_nfa_get_initials_fu_494_ap_return_0;
wire [31:0] grp_nfa_get_initials_fu_494_ap_return_1;
wire grp_nfa_get_finals_fu_500_ap_start;
wire grp_nfa_get_finals_fu_500_ap_done;
wire grp_nfa_get_finals_fu_500_ap_idle;
wire grp_nfa_get_finals_fu_500_ap_ready;
wire grp_nfa_get_finals_fu_500_ap_ce;
wire grp_nfa_get_finals_fu_500_nfa_finals_buckets_req_din;
wire grp_nfa_get_finals_fu_500_nfa_finals_buckets_req_full_n;
wire grp_nfa_get_finals_fu_500_nfa_finals_buckets_req_write;
wire grp_nfa_get_finals_fu_500_nfa_finals_buckets_rsp_empty_n;
wire grp_nfa_get_finals_fu_500_nfa_finals_buckets_rsp_read;
wire [31:0] grp_nfa_get_finals_fu_500_nfa_finals_buckets_address;
wire [31:0] grp_nfa_get_finals_fu_500_nfa_finals_buckets_datain;
wire [31:0] grp_nfa_get_finals_fu_500_nfa_finals_buckets_dataout;
wire [31:0] grp_nfa_get_finals_fu_500_nfa_finals_buckets_size;
wire [31:0] grp_nfa_get_finals_fu_500_ap_return_0;
wire [31:0] grp_nfa_get_finals_fu_500_ap_return_1;
wire [31:0] r_bit_p_bsf32_hw_fu_506_bus_r;
reg [15:0] i_index_reg_222;
reg [15:0] i_sample_reg_232;
reg [31:0] next_buckets_1_reg_242;
wire [0:0] any_0_i_phi_fu_429_p4;
reg [31:0] next_buckets_0_reg_252;
reg [15:0] i_0_i_reg_262;
reg [63:0] p_01_rec_i_reg_273;
reg [31:0] bus_assign_reg_284;
reg [0:0] agg_result_bucket_index_0_lcssa4_i_reg_296;
reg [31:0] j_bucket1_ph_phi_fu_313_p4;
reg [31:0] j_bucket1_ph_reg_309;
reg [1:0] j_bucket_index1_ph_phi_fu_326_p4;
reg [1:0] j_bucket_index1_ph_reg_322;
wire [1:0] agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_592_p1;
reg [4:0] j_bit1_ph_phi_fu_337_p4;
reg [4:0] j_bit1_ph_reg_333;
reg [0:0] j_end_ph_phi_fu_348_p4;
reg [0:0] j_end_ph_reg_344;
reg [31:0] tmp_buckets_1_3_reg_357;
reg [31:0] tmp_buckets_0_3_reg_370;
reg [31:0] j_bucket1_reg_383;
reg [7:0] j_bucket_index1_reg_394;
reg [7:0] j_bit1_reg_404;
reg [0:0] j_end_reg_414;
reg [0:0] any_0_i_reg_424;
reg [0:0] r_reg_437;
reg [31:0] p_0_reg_448;
wire [0:0] tmp_i_13_fu_534_p2;
wire [0:0] or_cond_fu_743_p2;
reg grp_bitset_next_fu_460_ap_start_ap_start_reg = 1'b0;
reg [5:0] ap_NS_fsm;
reg grp_sample_iterator_next_fu_472_ap_start_ap_start_reg = 1'b0;
reg grp_sample_iterator_get_offset_fu_482_ap_start_ap_start_reg = 1'b0;
reg grp_nfa_get_initials_fu_494_ap_start_ap_start_reg = 1'b0;
reg grp_nfa_get_finals_fu_500_ap_start_ap_start_reg = 1'b0;
wire [63:0] sum_fu_552_p2;
wire [63:0] tmp_12_i_cast_fu_656_p1;
wire [63:0] tmp_13_i_cast_fu_690_p1;
reg [31:0] c_fu_140;
wire [31:0] c_1_fu_748_p2;
wire [0:0] tmp_i_fu_524_p2;
wire [0:0] tmp_i_12_fu_529_p2;
wire [0:0] tmp_6_fu_608_p1;
wire [5:0] tmp_i1_fu_612_p3;
wire [5:0] tmp_8_fu_620_p1;
wire [5:0] state_fu_624_p2;
wire [7:0] grp_fu_638_p0;
wire [5:0] grp_fu_638_p1;
wire [13:0] grp_fu_638_p2;
wire [14:0] tmp_12_i_fu_649_p3;
wire [14:0] tmp_13_i_fu_683_p3;
wire [31:0] current_buckets_1_1_fu_726_p2;
wire [31:0] current_buckets_0_1_fu_721_p2;
wire [31:0] tmp_1_fu_731_p2;
wire grp_fu_638_ce;
wire [13:0] grp_fu_638_p00;
wire [13:0] grp_fu_638_p10;
reg ap_sig_bdd_370;
reg ap_sig_bdd_187;
bitset_next grp_bitset_next_fu_460(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.ap_start( grp_bitset_next_fu_460_ap_start ),
.ap_done( grp_bitset_next_fu_460_ap_done ),
.ap_idle( grp_bitset_next_fu_460_ap_idle ),
.ap_ready( grp_bitset_next_fu_460_ap_ready ),
.ap_ce( grp_bitset_next_fu_460_ap_ce ),
.p_read( grp_bitset_next_fu_460_p_read ),
.r_bit( grp_bitset_next_fu_460_r_bit ),
.r_bucket_index( grp_bitset_next_fu_460_r_bucket_index ),
.r_bucket( grp_bitset_next_fu_460_r_bucket ),
.ap_return_0( grp_bitset_next_fu_460_ap_return_0 ),
.ap_return_1( grp_bitset_next_fu_460_ap_return_1 ),
.ap_return_2( grp_bitset_next_fu_460_ap_return_2 ),
.ap_return_3( grp_bitset_next_fu_460_ap_return_3 )
);
sample_iterator_next grp_sample_iterator_next_fu_472(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.ap_start( grp_sample_iterator_next_fu_472_ap_start ),
.ap_done( grp_sample_iterator_next_fu_472_ap_done ),
.ap_idle( grp_sample_iterator_next_fu_472_ap_idle ),
.ap_ready( grp_sample_iterator_next_fu_472_ap_ready ),
.indices_req_din( grp_sample_iterator_next_fu_472_indices_req_din ),
.indices_req_full_n( grp_sample_iterator_next_fu_472_indices_req_full_n ),
.indices_req_write( grp_sample_iterator_next_fu_472_indices_req_write ),
.indices_rsp_empty_n( grp_sample_iterator_next_fu_472_indices_rsp_empty_n ),
.indices_rsp_read( grp_sample_iterator_next_fu_472_indices_rsp_read ),
.indices_address( grp_sample_iterator_next_fu_472_indices_address ),
.indices_datain( grp_sample_iterator_next_fu_472_indices_datain ),
.indices_dataout( grp_sample_iterator_next_fu_472_indices_dataout ),
.indices_size( grp_sample_iterator_next_fu_472_indices_size ),
.ap_ce( grp_sample_iterator_next_fu_472_ap_ce ),
.i_index( grp_sample_iterator_next_fu_472_i_index ),
.i_sample( grp_sample_iterator_next_fu_472_i_sample ),
.ap_return_0( grp_sample_iterator_next_fu_472_ap_return_0 ),
.ap_return_1( grp_sample_iterator_next_fu_472_ap_return_1 )
);
sample_iterator_get_offset grp_sample_iterator_get_offset_fu_482(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.ap_start( grp_sample_iterator_get_offset_fu_482_ap_start ),
.ap_done( grp_sample_iterator_get_offset_fu_482_ap_done ),
.ap_idle( grp_sample_iterator_get_offset_fu_482_ap_idle ),
.ap_ready( grp_sample_iterator_get_offset_fu_482_ap_ready ),
.indices_req_din( grp_sample_iterator_get_offset_fu_482_indices_req_din ),
.indices_req_full_n( grp_sample_iterator_get_offset_fu_482_indices_req_full_n ),
.indices_req_write( grp_sample_iterator_get_offset_fu_482_indices_req_write ),
.indices_rsp_empty_n( grp_sample_iterator_get_offset_fu_482_indices_rsp_empty_n ),
.indices_rsp_read( grp_sample_iterator_get_offset_fu_482_indices_rsp_read ),
.indices_address( grp_sample_iterator_get_offset_fu_482_indices_address ),
.indices_datain( grp_sample_iterator_get_offset_fu_482_indices_datain ),
.indices_dataout( grp_sample_iterator_get_offset_fu_482_indices_dataout ),
.indices_size( grp_sample_iterator_get_offset_fu_482_indices_size ),
.ap_ce( grp_sample_iterator_get_offset_fu_482_ap_ce ),
.i_index( grp_sample_iterator_get_offset_fu_482_i_index ),
.i_sample( grp_sample_iterator_get_offset_fu_482_i_sample ),
.sample_buffer_size( grp_sample_iterator_get_offset_fu_482_sample_buffer_size ),
.sample_length( grp_sample_iterator_get_offset_fu_482_sample_length ),
.ap_return( grp_sample_iterator_get_offset_fu_482_ap_return )
);
nfa_get_initials grp_nfa_get_initials_fu_494(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.ap_start( grp_nfa_get_initials_fu_494_ap_start ),
.ap_done( grp_nfa_get_initials_fu_494_ap_done ),
.ap_idle( grp_nfa_get_initials_fu_494_ap_idle ),
.ap_ready( grp_nfa_get_initials_fu_494_ap_ready ),
.ap_ce( grp_nfa_get_initials_fu_494_ap_ce ),
.nfa_initials_buckets_req_din( grp_nfa_get_initials_fu_494_nfa_initials_buckets_req_din ),
.nfa_initials_buckets_req_full_n( grp_nfa_get_initials_fu_494_nfa_initials_buckets_req_full_n ),
.nfa_initials_buckets_req_write( grp_nfa_get_initials_fu_494_nfa_initials_buckets_req_write ),
.nfa_initials_buckets_rsp_empty_n( grp_nfa_get_initials_fu_494_nfa_initials_buckets_rsp_empty_n ),
.nfa_initials_buckets_rsp_read( grp_nfa_get_initials_fu_494_nfa_initials_buckets_rsp_read ),
.nfa_initials_buckets_address( grp_nfa_get_initials_fu_494_nfa_initials_buckets_address ),
.nfa_initials_buckets_datain( grp_nfa_get_initials_fu_494_nfa_initials_buckets_datain ),
.nfa_initials_buckets_dataout( grp_nfa_get_initials_fu_494_nfa_initials_buckets_dataout ),
.nfa_initials_buckets_size( grp_nfa_get_initials_fu_494_nfa_initials_buckets_size ),
.ap_return_0( grp_nfa_get_initials_fu_494_ap_return_0 ),
.ap_return_1( grp_nfa_get_initials_fu_494_ap_return_1 )
);
nfa_get_finals grp_nfa_get_finals_fu_500(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.ap_start( grp_nfa_get_finals_fu_500_ap_start ),
.ap_done( grp_nfa_get_finals_fu_500_ap_done ),
.ap_idle( grp_nfa_get_finals_fu_500_ap_idle ),
.ap_ready( grp_nfa_get_finals_fu_500_ap_ready ),
.ap_ce( grp_nfa_get_finals_fu_500_ap_ce ),
.nfa_finals_buckets_req_din( grp_nfa_get_finals_fu_500_nfa_finals_buckets_req_din ),
.nfa_finals_buckets_req_full_n( grp_nfa_get_finals_fu_500_nfa_finals_buckets_req_full_n ),
.nfa_finals_buckets_req_write( grp_nfa_get_finals_fu_500_nfa_finals_buckets_req_write ),
.nfa_finals_buckets_rsp_empty_n( grp_nfa_get_finals_fu_500_nfa_finals_buckets_rsp_empty_n ),
.nfa_finals_buckets_rsp_read( grp_nfa_get_finals_fu_500_nfa_finals_buckets_rsp_read ),
.nfa_finals_buckets_address( grp_nfa_get_finals_fu_500_nfa_finals_buckets_address ),
.nfa_finals_buckets_datain( grp_nfa_get_finals_fu_500_nfa_finals_buckets_datain ),
.nfa_finals_buckets_dataout( grp_nfa_get_finals_fu_500_nfa_finals_buckets_dataout ),
.nfa_finals_buckets_size( grp_nfa_get_finals_fu_500_nfa_finals_buckets_size ),
.ap_return_0( grp_nfa_get_finals_fu_500_ap_return_0 ),
.ap_return_1( grp_nfa_get_finals_fu_500_ap_return_1 )
);
p_bsf32_hw r_bit_p_bsf32_hw_fu_506(
.bus_r( r_bit_p_bsf32_hw_fu_506_bus_r ),
.ap_return( r_bit_p_bsf32_hw_fu_506_ap_return )
);
nfa_accept_samples_generic_hw_mul_8ns_6ns_14_2 #(
.ID( 16 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 8 ),
.din1_WIDTH( 6 ),
.dout_WIDTH( 14 ))
nfa_accept_samples_generic_hw_mul_8ns_6ns_14_2_U16(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_638_p0 ),
.din1( grp_fu_638_p1 ),
.ce( grp_fu_638_ce ),
.dout( grp_fu_638_p2 )
);
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// grp_bitset_next_fu_460_ap_start_ap_start_reg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_grp_bitset_next_fu_460_ap_start_ap_start_reg
if (ap_rst == 1'b1) begin
grp_bitset_next_fu_460_ap_start_ap_start_reg <= ap_const_logic_0;
end else begin
if (((ap_ST_st16_fsm_15 == ap_CS_fsm) & (ap_ST_st17_fsm_16 == ap_NS_fsm))) begin
grp_bitset_next_fu_460_ap_start_ap_start_reg <= ap_const_logic_1;
end else if ((ap_const_logic_1 == grp_bitset_next_fu_460_ap_ready)) begin
grp_bitset_next_fu_460_ap_start_ap_start_reg <= ap_const_logic_0;
end
end
end
/// grp_nfa_get_finals_fu_500_ap_start_ap_start_reg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_grp_nfa_get_finals_fu_500_ap_start_ap_start_reg
if (ap_rst == 1'b1) begin
grp_nfa_get_finals_fu_500_ap_start_ap_start_reg <= ap_const_logic_0;
end else begin
if (((ap_ST_st10_fsm_9 == ap_CS_fsm) & (ap_ST_st25_fsm_24 == ap_NS_fsm))) begin
grp_nfa_get_finals_fu_500_ap_start_ap_start_reg <= ap_const_logic_1;
end else if ((ap_const_logic_1 == grp_nfa_get_finals_fu_500_ap_ready)) begin
grp_nfa_get_finals_fu_500_ap_start_ap_start_reg <= ap_const_logic_0;
end
end
end
/// grp_nfa_get_initials_fu_494_ap_start_ap_start_reg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_grp_nfa_get_initials_fu_494_ap_start_ap_start_reg
if (ap_rst == 1'b1) begin
grp_nfa_get_initials_fu_494_ap_start_ap_start_reg <= ap_const_logic_0;
end else begin
if (((ap_ST_st2_fsm_1 == ap_CS_fsm) & (ap_ST_st3_fsm_2 == ap_NS_fsm))) begin
grp_nfa_get_initials_fu_494_ap_start_ap_start_reg <= ap_const_logic_1;
end else if ((ap_const_logic_1 == grp_nfa_get_initials_fu_494_ap_ready)) begin
grp_nfa_get_initials_fu_494_ap_start_ap_start_reg <= ap_const_logic_0;
end
end
end
/// grp_sample_iterator_get_offset_fu_482_ap_start_ap_start_reg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_grp_sample_iterator_get_offset_fu_482_ap_start_ap_start_reg
if (ap_rst == 1'b1) begin
grp_sample_iterator_get_offset_fu_482_ap_start_ap_start_reg <= ap_const_logic_0;
end else begin
if (((ap_ST_st5_fsm_4 == ap_NS_fsm) & (ap_ST_st4_fsm_3 == ap_CS_fsm))) begin
grp_sample_iterator_get_offset_fu_482_ap_start_ap_start_reg <= ap_const_logic_1;
end else if ((ap_const_logic_1 == grp_sample_iterator_get_offset_fu_482_ap_ready)) begin
grp_sample_iterator_get_offset_fu_482_ap_start_ap_start_reg <= ap_const_logic_0;
end
end
end
/// grp_sample_iterator_next_fu_472_ap_start_ap_start_reg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_grp_sample_iterator_next_fu_472_ap_start_ap_start_reg
if (ap_rst == 1'b1) begin
grp_sample_iterator_next_fu_472_ap_start_ap_start_reg <= ap_const_logic_0;
end else begin
if (((ap_ST_st32_fsm_31 == ap_CS_fsm) & (ap_ST_st33_fsm_32 == ap_NS_fsm))) begin
grp_sample_iterator_next_fu_472_ap_start_ap_start_reg <= ap_const_logic_1;
end else if ((ap_const_logic_1 == grp_sample_iterator_next_fu_472_ap_ready)) begin
grp_sample_iterator_next_fu_472_ap_start_ap_start_reg <= ap_const_logic_0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (ap_sig_bdd_187) begin
if (ap_sig_bdd_370) begin
agg_result_bucket_index_0_lcssa4_i_reg_296 <= ap_const_lv1_1;
end else if ((ap_const_lv1_0 == tmp_2_i_fu_580_p2)) begin
agg_result_bucket_index_0_lcssa4_i_reg_296 <= ap_const_lv1_0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st15_fsm_14 == ap_CS_fsm)) begin
any_0_i_reg_424 <= ap_const_lv1_0;
end else if ((ap_ST_st24_fsm_23 == ap_CS_fsm)) begin
any_0_i_reg_424 <= ap_const_lv1_1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (ap_sig_bdd_187) begin
if (ap_sig_bdd_370) begin
bus_assign_reg_284 <= next_buckets_1_reg_242;
end else if ((ap_const_lv1_0 == tmp_2_i_fu_580_p2)) begin
bus_assign_reg_284 <= next_buckets_0_reg_252;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st32_fsm_31 == ap_CS_fsm) & (stop_on_first_read_read_fu_150_p2 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_fu_743_p2))) begin
c_fu_140 <= c_1_fu_748_p2;
end else if (((ap_ST_st1_fsm_0 == ap_CS_fsm) & ~(ap_start == ap_const_logic_0))) begin
c_fu_140 <= ap_const_lv32_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st16_fsm_15 == ap_CS_fsm) & ~(ap_const_lv1_0 == j_end_phi_fu_417_p4) & ~(ap_const_lv1_0 == any_0_i_phi_fu_429_p4))) begin
i_0_i_reg_262 <= i_reg_846;
end else if ((ap_ST_st9_fsm_8 == ap_CS_fsm)) begin
i_0_i_reg_262 <= ap_const_lv16_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st36_fsm_35 == ap_CS_fsm)) begin
i_index_reg_222 <= grp_sample_iterator_next_fu_472_ap_return_0;
end else if (((ap_ST_st1_fsm_0 == ap_CS_fsm) & ~(ap_start == ap_const_logic_0))) begin
i_index_reg_222 <= begin_index;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st36_fsm_35 == ap_CS_fsm)) begin
i_sample_reg_232 <= grp_sample_iterator_next_fu_472_ap_return_1;
end else if (((ap_ST_st1_fsm_0 == ap_CS_fsm) & ~(ap_start == ap_const_logic_0))) begin
i_sample_reg_232 <= begin_sample;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st15_fsm_14 == ap_CS_fsm)) begin
j_bit1_reg_404 <= j_bit1_ph_cast_fu_601_p1;
end else if ((ap_ST_st24_fsm_23 == ap_CS_fsm)) begin
j_bit1_reg_404 <= j_bit_reg_911;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st15_fsm_14 == ap_CS_fsm) & ((ap_const_lv1_0 == tmp_2_i_reg_861) | (ap_const_lv1_0 == tmp_2_1_i_reg_865)))) begin
j_bucket1_ph_reg_309 <= bus_assign_reg_284;
end else if (((ap_ST_st13_fsm_12 == ap_CS_fsm) & ~(sample_buffer_rsp_empty_n == ap_const_logic_0) & ~(ap_const_lv1_0 == tmp_2_i_fu_580_p2) & ~(ap_const_lv1_0 == tmp_2_1_i_fu_586_p2))) begin
j_bucket1_ph_reg_309 <= ap_const_lv32_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st15_fsm_14 == ap_CS_fsm)) begin
j_bucket1_reg_383 <= j_bucket1_ph_phi_fu_313_p4;
end else if ((ap_ST_st24_fsm_23 == ap_CS_fsm)) begin
j_bucket1_reg_383 <= j_bucket_reg_921;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st15_fsm_14 == ap_CS_fsm) & ((ap_const_lv1_0 == tmp_2_i_reg_861) | (ap_const_lv1_0 == tmp_2_1_i_reg_865)))) begin
j_bucket_index1_ph_reg_322 <= agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_592_p1;
end else if (((ap_ST_st13_fsm_12 == ap_CS_fsm) & ~(sample_buffer_rsp_empty_n == ap_const_logic_0) & ~(ap_const_lv1_0 == tmp_2_i_fu_580_p2) & ~(ap_const_lv1_0 == tmp_2_1_i_fu_586_p2))) begin
j_bucket_index1_ph_reg_322 <= ap_const_lv2_2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st15_fsm_14 == ap_CS_fsm)) begin
j_bucket_index1_reg_394 <= j_bucket_index1_ph_cast_fu_597_p1;
end else if ((ap_ST_st24_fsm_23 == ap_CS_fsm)) begin
j_bucket_index1_reg_394 <= j_bucket_index_reg_916;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st15_fsm_14 == ap_CS_fsm) & ((ap_const_lv1_0 == tmp_2_i_reg_861) | (ap_const_lv1_0 == tmp_2_1_i_reg_865)))) begin
j_end_ph_reg_344 <= ap_const_lv1_0;
end else if (((ap_ST_st13_fsm_12 == ap_CS_fsm) & ~(sample_buffer_rsp_empty_n == ap_const_logic_0) & ~(ap_const_lv1_0 == tmp_2_i_fu_580_p2) & ~(ap_const_lv1_0 == tmp_2_1_i_fu_586_p2))) begin
j_end_ph_reg_344 <= ap_const_lv1_1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st15_fsm_14 == ap_CS_fsm)) begin
j_end_reg_414 <= j_end_ph_phi_fu_348_p4;
end else if ((ap_ST_st24_fsm_23 == ap_CS_fsm)) begin
j_end_reg_414 <= p_s_reg_926;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st16_fsm_15 == ap_CS_fsm) & ~(ap_const_lv1_0 == j_end_phi_fu_417_p4) & ~(ap_const_lv1_0 == any_0_i_phi_fu_429_p4))) begin
next_buckets_0_reg_252 <= tmp_buckets_0_3_reg_370;
end else if ((ap_ST_st9_fsm_8 == ap_CS_fsm)) begin
next_buckets_0_reg_252 <= current_buckets_0_reg_822;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st16_fsm_15 == ap_CS_fsm) & ~(ap_const_lv1_0 == j_end_phi_fu_417_p4) & ~(ap_const_lv1_0 == any_0_i_phi_fu_429_p4))) begin
next_buckets_1_reg_242 <= tmp_buckets_1_3_reg_357;
end else if ((ap_ST_st9_fsm_8 == ap_CS_fsm)) begin
next_buckets_1_reg_242 <= current_buckets_1_reg_827;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st16_fsm_15 == ap_CS_fsm) & ~(ap_const_lv1_0 == j_end_phi_fu_417_p4) & ~(ap_const_lv1_0 == any_0_i_phi_fu_429_p4))) begin
p_01_rec_i_reg_273 <= p_rec_i_reg_851;
end else if ((ap_ST_st9_fsm_8 == ap_CS_fsm)) begin
p_01_rec_i_reg_273 <= ap_const_lv64_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st32_fsm_31 == ap_CS_fsm) & ~(stop_on_first_read_read_fu_150_p2 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_fu_743_p2))) begin
p_0_reg_448 <= ap_const_lv32_1;
end else if (((ap_ST_st2_fsm_1 == ap_CS_fsm) & ~(ap_const_lv1_0 == tmp_i_13_fu_534_p2))) begin
p_0_reg_448 <= c_fu_140;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st16_fsm_15 == ap_CS_fsm) & ~(ap_const_lv1_0 == j_end_phi_fu_417_p4) & (ap_const_lv1_0 == any_0_i_phi_fu_429_p4))) begin
r_reg_437 <= ap_const_lv1_0;
end else if ((ap_ST_st31_fsm_30 == ap_CS_fsm)) begin
r_reg_437 <= tmp_5_fu_737_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st15_fsm_14 == ap_CS_fsm)) begin
tmp_buckets_0_3_reg_370 <= ap_const_lv32_0;
end else if ((ap_ST_st24_fsm_23 == ap_CS_fsm)) begin
tmp_buckets_0_3_reg_370 <= next_buckets_0_1_reg_937;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st15_fsm_14 == ap_CS_fsm)) begin
tmp_buckets_1_3_reg_357 <= ap_const_lv32_0;
end else if ((ap_ST_st24_fsm_23 == ap_CS_fsm)) begin
tmp_buckets_1_3_reg_357 <= next_buckets_1_1_fu_707_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st2_fsm_1 == ap_CS_fsm)) begin
c_load_reg_813 <= c_fu_140;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st8_fsm_7 == ap_CS_fsm)) begin
current_buckets_0_reg_822 <= grp_nfa_get_initials_fu_494_ap_return_0;
current_buckets_1_reg_827 <= grp_nfa_get_initials_fu_494_ap_return_1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st10_fsm_9 == ap_CS_fsm)) begin
i_reg_846 <= i_fu_568_p2;
sample_buffer_addr_reg_837 <= sum_fu_552_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st15_fsm_14 == ap_CS_fsm) & ((ap_const_lv1_0 == tmp_2_i_reg_861) | (ap_const_lv1_0 == tmp_2_1_i_reg_865)))) begin
j_bit1_ph_reg_333 <= r_bit_reg_869;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st19_fsm_18 == ap_CS_fsm)) begin
j_bit_reg_911 <= grp_bitset_next_fu_460_ap_return_0;
j_bucket_index_reg_916 <= grp_bitset_next_fu_460_ap_return_1;
j_bucket_reg_921 <= grp_bitset_next_fu_460_ap_return_2;
p_s_reg_926 <= grp_bitset_next_fu_460_ap_return_3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st21_fsm_20 == ap_CS_fsm)) begin
next_buckets_0_1_reg_937 <= next_buckets_0_1_fu_701_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st10_fsm_9 == ap_CS_fsm) & ~(tmp_3_fu_563_p2 == ap_const_lv1_0))) begin
p_rec_i_reg_851 <= p_rec_i_fu_574_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st14_fsm_13 == ap_CS_fsm)) begin
r_bit_reg_869 <= r_bit_p_bsf32_hw_fu_506_ap_return;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((((ap_ST_st20_fsm_19 == ap_CS_fsm) & ~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0)) | (~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0) & (ap_ST_st23_fsm_22 == ap_CS_fsm)))) begin
reg_512 <= nfa_forward_buckets_datain;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st13_fsm_12 == ap_CS_fsm) & ~(sample_buffer_rsp_empty_n == ap_const_logic_0))) begin
sym_reg_856 <= sample_buffer_datain;
tmp_2_i_reg_861 <= tmp_2_i_fu_580_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st15_fsm_14 == ap_CS_fsm)) begin
tmp_10_i_cast_reg_884[0] <= tmp_10_i_cast_fu_605_p1[0];
tmp_10_i_cast_reg_884[1] <= tmp_10_i_cast_fu_605_p1[1];
tmp_10_i_cast_reg_884[2] <= tmp_10_i_cast_fu_605_p1[2];
tmp_10_i_cast_reg_884[3] <= tmp_10_i_cast_fu_605_p1[3];
tmp_10_i_cast_reg_884[4] <= tmp_10_i_cast_fu_605_p1[4];
tmp_10_i_cast_reg_884[5] <= tmp_10_i_cast_fu_605_p1[5];
tmp_10_i_cast_reg_884[6] <= tmp_10_i_cast_fu_605_p1[6];
tmp_10_i_cast_reg_884[7] <= tmp_10_i_cast_fu_605_p1[7];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st17_fsm_16 == ap_CS_fsm)) begin
tmp_11_i_reg_899 <= tmp_11_i_fu_644_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st13_fsm_12 == ap_CS_fsm) & ~(sample_buffer_rsp_empty_n == ap_const_logic_0) & ~(ap_const_lv1_0 == tmp_2_i_fu_580_p2))) begin
tmp_2_1_i_reg_865 <= tmp_2_1_i_fu_586_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st9_fsm_8 == ap_CS_fsm)) begin
tmp_2_reg_832[0] <= tmp_2_fu_548_p1[0];
tmp_2_reg_832[1] <= tmp_2_fu_548_p1[1];
tmp_2_reg_832[2] <= tmp_2_fu_548_p1[2];
tmp_2_reg_832[3] <= tmp_2_fu_548_p1[3];
tmp_2_reg_832[4] <= tmp_2_fu_548_p1[4];
tmp_2_reg_832[5] <= tmp_2_fu_548_p1[5];
tmp_2_reg_832[6] <= tmp_2_fu_548_p1[6];
tmp_2_reg_832[7] <= tmp_2_fu_548_p1[7];
tmp_2_reg_832[8] <= tmp_2_fu_548_p1[8];
tmp_2_reg_832[9] <= tmp_2_fu_548_p1[9];
tmp_2_reg_832[10] <= tmp_2_fu_548_p1[10];
tmp_2_reg_832[11] <= tmp_2_fu_548_p1[11];
tmp_2_reg_832[12] <= tmp_2_fu_548_p1[12];
tmp_2_reg_832[13] <= tmp_2_fu_548_p1[13];
tmp_2_reg_832[14] <= tmp_2_fu_548_p1[14];
tmp_2_reg_832[15] <= tmp_2_fu_548_p1[15];
tmp_2_reg_832[16] <= tmp_2_fu_548_p1[16];
tmp_2_reg_832[17] <= tmp_2_fu_548_p1[17];
tmp_2_reg_832[18] <= tmp_2_fu_548_p1[18];
tmp_2_reg_832[19] <= tmp_2_fu_548_p1[19];
tmp_2_reg_832[20] <= tmp_2_fu_548_p1[20];
tmp_2_reg_832[21] <= tmp_2_fu_548_p1[21];
tmp_2_reg_832[22] <= tmp_2_fu_548_p1[22];
tmp_2_reg_832[23] <= tmp_2_fu_548_p1[23];
tmp_2_reg_832[24] <= tmp_2_fu_548_p1[24];
tmp_2_reg_832[25] <= tmp_2_fu_548_p1[25];
tmp_2_reg_832[26] <= tmp_2_fu_548_p1[26];
tmp_2_reg_832[27] <= tmp_2_fu_548_p1[27];
tmp_2_reg_832[28] <= tmp_2_fu_548_p1[28];
tmp_2_reg_832[29] <= tmp_2_fu_548_p1[29];
tmp_2_reg_832[30] <= tmp_2_fu_548_p1[30];
tmp_2_reg_832[31] <= tmp_2_fu_548_p1[31];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st30_fsm_29 == ap_CS_fsm)) begin
tmp_buckets_0_reg_947 <= grp_nfa_get_finals_fu_500_ap_return_0;
tmp_buckets_1_reg_952 <= grp_nfa_get_finals_fu_500_ap_return_1;
end
end
/// ap_done assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st37_fsm_36 == ap_CS_fsm)) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_CS_fsm)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_ST_st1_fsm_0 == ap_CS_fsm))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st37_fsm_36 == ap_CS_fsm)) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// indices_address assign process. ///
always @ (ap_CS_fsm or grp_sample_iterator_next_fu_472_indices_address or grp_sample_iterator_get_offset_fu_482_indices_address)
begin
if (((ap_ST_st8_fsm_7 == ap_CS_fsm) | (ap_ST_st9_fsm_8 == ap_CS_fsm) | (ap_ST_st5_fsm_4 == ap_CS_fsm) | (ap_ST_st6_fsm_5 == ap_CS_fsm) | (ap_ST_st7_fsm_6 == ap_CS_fsm))) begin
indices_address = grp_sample_iterator_get_offset_fu_482_indices_address;
end else if (((ap_ST_st36_fsm_35 == ap_CS_fsm) | (ap_ST_st33_fsm_32 == ap_CS_fsm) | (ap_ST_st34_fsm_33 == ap_CS_fsm) | (ap_ST_st35_fsm_34 == ap_CS_fsm))) begin
indices_address = grp_sample_iterator_next_fu_472_indices_address;
end else begin
indices_address = 'bx;
end
end
/// indices_dataout assign process. ///
always @ (ap_CS_fsm or grp_sample_iterator_next_fu_472_indices_dataout or grp_sample_iterator_get_offset_fu_482_indices_dataout)
begin
if (((ap_ST_st8_fsm_7 == ap_CS_fsm) | (ap_ST_st9_fsm_8 == ap_CS_fsm) | (ap_ST_st5_fsm_4 == ap_CS_fsm) | (ap_ST_st6_fsm_5 == ap_CS_fsm) | (ap_ST_st7_fsm_6 == ap_CS_fsm))) begin
indices_dataout = grp_sample_iterator_get_offset_fu_482_indices_dataout;
end else if (((ap_ST_st36_fsm_35 == ap_CS_fsm) | (ap_ST_st33_fsm_32 == ap_CS_fsm) | (ap_ST_st34_fsm_33 == ap_CS_fsm) | (ap_ST_st35_fsm_34 == ap_CS_fsm))) begin
indices_dataout = grp_sample_iterator_next_fu_472_indices_dataout;
end else begin
indices_dataout = 'bx;
end
end
/// indices_req_din assign process. ///
always @ (ap_CS_fsm or grp_sample_iterator_next_fu_472_indices_req_din or grp_sample_iterator_get_offset_fu_482_indices_req_din)
begin
if (((ap_ST_st8_fsm_7 == ap_CS_fsm) | (ap_ST_st9_fsm_8 == ap_CS_fsm) | (ap_ST_st5_fsm_4 == ap_CS_fsm) | (ap_ST_st6_fsm_5 == ap_CS_fsm) | (ap_ST_st7_fsm_6 == ap_CS_fsm))) begin
indices_req_din = grp_sample_iterator_get_offset_fu_482_indices_req_din;
end else if (((ap_ST_st36_fsm_35 == ap_CS_fsm) | (ap_ST_st33_fsm_32 == ap_CS_fsm) | (ap_ST_st34_fsm_33 == ap_CS_fsm) | (ap_ST_st35_fsm_34 == ap_CS_fsm))) begin
indices_req_din = grp_sample_iterator_next_fu_472_indices_req_din;
end else begin
indices_req_din = 'bx;
end
end
/// indices_req_write assign process. ///
always @ (ap_CS_fsm or grp_sample_iterator_next_fu_472_indices_req_write or grp_sample_iterator_get_offset_fu_482_indices_req_write)
begin
if (((ap_ST_st8_fsm_7 == ap_CS_fsm) | (ap_ST_st9_fsm_8 == ap_CS_fsm) | (ap_ST_st5_fsm_4 == ap_CS_fsm) | (ap_ST_st6_fsm_5 == ap_CS_fsm) | (ap_ST_st7_fsm_6 == ap_CS_fsm))) begin
indices_req_write = grp_sample_iterator_get_offset_fu_482_indices_req_write;
end else if (((ap_ST_st36_fsm_35 == ap_CS_fsm) | (ap_ST_st33_fsm_32 == ap_CS_fsm) | (ap_ST_st34_fsm_33 == ap_CS_fsm) | (ap_ST_st35_fsm_34 == ap_CS_fsm))) begin
indices_req_write = grp_sample_iterator_next_fu_472_indices_req_write;
end else begin
indices_req_write = 'bx;
end
end
/// indices_rsp_read assign process. ///
always @ (ap_CS_fsm or grp_sample_iterator_next_fu_472_indices_rsp_read or grp_sample_iterator_get_offset_fu_482_indices_rsp_read)
begin
if (((ap_ST_st8_fsm_7 == ap_CS_fsm) | (ap_ST_st9_fsm_8 == ap_CS_fsm) | (ap_ST_st5_fsm_4 == ap_CS_fsm) | (ap_ST_st6_fsm_5 == ap_CS_fsm) | (ap_ST_st7_fsm_6 == ap_CS_fsm))) begin
indices_rsp_read = grp_sample_iterator_get_offset_fu_482_indices_rsp_read;
end else if (((ap_ST_st36_fsm_35 == ap_CS_fsm) | (ap_ST_st33_fsm_32 == ap_CS_fsm) | (ap_ST_st34_fsm_33 == ap_CS_fsm) | (ap_ST_st35_fsm_34 == ap_CS_fsm))) begin
indices_rsp_read = grp_sample_iterator_next_fu_472_indices_rsp_read;
end else begin
indices_rsp_read = 'bx;
end
end
/// indices_size assign process. ///
always @ (ap_CS_fsm or grp_sample_iterator_next_fu_472_indices_size or grp_sample_iterator_get_offset_fu_482_indices_size)
begin
if (((ap_ST_st8_fsm_7 == ap_CS_fsm) | (ap_ST_st9_fsm_8 == ap_CS_fsm) | (ap_ST_st5_fsm_4 == ap_CS_fsm) | (ap_ST_st6_fsm_5 == ap_CS_fsm) | (ap_ST_st7_fsm_6 == ap_CS_fsm))) begin
indices_size = grp_sample_iterator_get_offset_fu_482_indices_size;
end else if (((ap_ST_st36_fsm_35 == ap_CS_fsm) | (ap_ST_st33_fsm_32 == ap_CS_fsm) | (ap_ST_st34_fsm_33 == ap_CS_fsm) | (ap_ST_st35_fsm_34 == ap_CS_fsm))) begin
indices_size = grp_sample_iterator_next_fu_472_indices_size;
end else begin
indices_size = 'bx;
end
end
/// j_bit1_ph_phi_fu_337_p4 assign process. ///
always @ (ap_CS_fsm or tmp_2_i_reg_861 or tmp_2_1_i_reg_865 or r_bit_reg_869 or j_bit1_ph_reg_333)
begin
if (((ap_ST_st15_fsm_14 == ap_CS_fsm) & ((ap_const_lv1_0 == tmp_2_i_reg_861) | (ap_const_lv1_0 == tmp_2_1_i_reg_865)))) begin
j_bit1_ph_phi_fu_337_p4 = r_bit_reg_869;
end else begin
j_bit1_ph_phi_fu_337_p4 = j_bit1_ph_reg_333;
end
end
/// j_bucket1_ph_phi_fu_313_p4 assign process. ///
always @ (ap_CS_fsm or tmp_2_i_reg_861 or tmp_2_1_i_reg_865 or bus_assign_reg_284 or j_bucket1_ph_reg_309)
begin
if (((ap_ST_st15_fsm_14 == ap_CS_fsm) & ((ap_const_lv1_0 == tmp_2_i_reg_861) | (ap_const_lv1_0 == tmp_2_1_i_reg_865)))) begin
j_bucket1_ph_phi_fu_313_p4 = bus_assign_reg_284;
end else begin
j_bucket1_ph_phi_fu_313_p4 = j_bucket1_ph_reg_309;
end
end
/// j_bucket_index1_ph_phi_fu_326_p4 assign process. ///
always @ (ap_CS_fsm or tmp_2_i_reg_861 or tmp_2_1_i_reg_865 or j_bucket_index1_ph_reg_322 or agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_592_p1)
begin
if (((ap_ST_st15_fsm_14 == ap_CS_fsm) & ((ap_const_lv1_0 == tmp_2_i_reg_861) | (ap_const_lv1_0 == tmp_2_1_i_reg_865)))) begin
j_bucket_index1_ph_phi_fu_326_p4 = agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_592_p1;
end else begin
j_bucket_index1_ph_phi_fu_326_p4 = j_bucket_index1_ph_reg_322;
end
end
/// j_end_ph_phi_fu_348_p4 assign process. ///
always @ (ap_CS_fsm or tmp_2_i_reg_861 or tmp_2_1_i_reg_865 or j_end_ph_reg_344)
begin
if (((ap_ST_st15_fsm_14 == ap_CS_fsm) & ((ap_const_lv1_0 == tmp_2_i_reg_861) | (ap_const_lv1_0 == tmp_2_1_i_reg_865)))) begin
j_end_ph_phi_fu_348_p4 = ap_const_lv1_0;
end else begin
j_end_ph_phi_fu_348_p4 = j_end_ph_reg_344;
end
end
/// nfa_forward_buckets_address assign process. ///
always @ (ap_CS_fsm or tmp_12_i_cast_fu_656_p1 or tmp_13_i_cast_fu_690_p1)
begin
if ((ap_ST_st21_fsm_20 == ap_CS_fsm)) begin
nfa_forward_buckets_address = tmp_13_i_cast_fu_690_p1;
end else if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
nfa_forward_buckets_address = tmp_12_i_cast_fu_656_p1;
end else begin
nfa_forward_buckets_address = 'bx;
end
end
/// nfa_forward_buckets_req_write assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st18_fsm_17 == ap_CS_fsm) | (ap_ST_st21_fsm_20 == ap_CS_fsm))) begin
nfa_forward_buckets_req_write = ap_const_logic_1;
end else begin
nfa_forward_buckets_req_write = ap_const_logic_0;
end
end
/// nfa_forward_buckets_rsp_read assign process. ///
always @ (ap_CS_fsm or nfa_forward_buckets_rsp_empty_n)
begin
if ((((ap_ST_st20_fsm_19 == ap_CS_fsm) & ~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0)) | (~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0) & (ap_ST_st23_fsm_22 == ap_CS_fsm)))) begin
nfa_forward_buckets_rsp_read = ap_const_logic_1;
end else begin
nfa_forward_buckets_rsp_read = ap_const_logic_0;
end
end
/// sample_buffer_req_write assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st11_fsm_10 == ap_CS_fsm)) begin
sample_buffer_req_write = ap_const_logic_1;
end else begin
sample_buffer_req_write = ap_const_logic_0;
end
end
/// sample_buffer_rsp_read assign process. ///
always @ (ap_CS_fsm or sample_buffer_rsp_empty_n)
begin
if (((ap_ST_st13_fsm_12 == ap_CS_fsm) & ~(sample_buffer_rsp_empty_n == ap_const_logic_0))) begin
sample_buffer_rsp_read = ap_const_logic_1;
end else begin
sample_buffer_rsp_read = ap_const_logic_0;
end
end
always @ (ap_start or ap_CS_fsm or nfa_forward_buckets_rsp_empty_n or sample_buffer_rsp_empty_n or stop_on_first_read_read_fu_150_p2 or tmp_3_fu_563_p2 or tmp_2_i_fu_580_p2 or tmp_2_1_i_fu_586_p2 or j_end_phi_fu_417_p4 or any_0_i_phi_fu_429_p4 or tmp_i_13_fu_534_p2 or or_cond_fu_743_p2)
begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 :
if (~(ap_start == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
ap_ST_st2_fsm_1 :
if (~(ap_const_lv1_0 == tmp_i_13_fu_534_p2)) begin
ap_NS_fsm = ap_ST_st37_fsm_36;
end else begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end
ap_ST_st3_fsm_2 :
ap_NS_fsm = ap_ST_st4_fsm_3;
ap_ST_st4_fsm_3 :
ap_NS_fsm = ap_ST_st5_fsm_4;
ap_ST_st5_fsm_4 :
ap_NS_fsm = ap_ST_st6_fsm_5;
ap_ST_st6_fsm_5 :
ap_NS_fsm = ap_ST_st7_fsm_6;
ap_ST_st7_fsm_6 :
ap_NS_fsm = ap_ST_st8_fsm_7;
ap_ST_st8_fsm_7 :
ap_NS_fsm = ap_ST_st9_fsm_8;
ap_ST_st9_fsm_8 :
ap_NS_fsm = ap_ST_st10_fsm_9;
ap_ST_st10_fsm_9 :
if ((tmp_3_fu_563_p2 == ap_const_lv1_0)) begin
ap_NS_fsm = ap_ST_st25_fsm_24;
end else begin
ap_NS_fsm = ap_ST_st11_fsm_10;
end
ap_ST_st11_fsm_10 :
ap_NS_fsm = ap_ST_st12_fsm_11;
ap_ST_st12_fsm_11 :
ap_NS_fsm = ap_ST_st13_fsm_12;
ap_ST_st13_fsm_12 :
if ((~(sample_buffer_rsp_empty_n == ap_const_logic_0) & ~(ap_const_lv1_0 == tmp_2_i_fu_580_p2) & ~(ap_const_lv1_0 == tmp_2_1_i_fu_586_p2))) begin
ap_NS_fsm = ap_ST_st15_fsm_14;
end else if ((~(sample_buffer_rsp_empty_n == ap_const_logic_0) & ((ap_const_lv1_0 == tmp_2_i_fu_580_p2) | (ap_const_lv1_0 == tmp_2_1_i_fu_586_p2)))) begin
ap_NS_fsm = ap_ST_st14_fsm_13;
end else begin
ap_NS_fsm = ap_ST_st13_fsm_12;
end
ap_ST_st14_fsm_13 :
ap_NS_fsm = ap_ST_st15_fsm_14;
ap_ST_st15_fsm_14 :
ap_NS_fsm = ap_ST_st16_fsm_15;
ap_ST_st16_fsm_15 :
if ((~(ap_const_lv1_0 == j_end_phi_fu_417_p4) & ~(ap_const_lv1_0 == any_0_i_phi_fu_429_p4))) begin
ap_NS_fsm = ap_ST_st10_fsm_9;
end else if ((~(ap_const_lv1_0 == j_end_phi_fu_417_p4) & (ap_const_lv1_0 == any_0_i_phi_fu_429_p4))) begin
ap_NS_fsm = ap_ST_st32_fsm_31;
end else begin
ap_NS_fsm = ap_ST_st17_fsm_16;
end
ap_ST_st17_fsm_16 :
ap_NS_fsm = ap_ST_st18_fsm_17;
ap_ST_st18_fsm_17 :
ap_NS_fsm = ap_ST_st19_fsm_18;
ap_ST_st19_fsm_18 :
ap_NS_fsm = ap_ST_st20_fsm_19;
ap_ST_st20_fsm_19 :
if (~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st21_fsm_20;
end else begin
ap_NS_fsm = ap_ST_st20_fsm_19;
end
ap_ST_st21_fsm_20 :
ap_NS_fsm = ap_ST_st22_fsm_21;
ap_ST_st22_fsm_21 :
ap_NS_fsm = ap_ST_st23_fsm_22;
ap_ST_st23_fsm_22 :
if (~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st24_fsm_23;
end else begin
ap_NS_fsm = ap_ST_st23_fsm_22;
end
ap_ST_st24_fsm_23 :
ap_NS_fsm = ap_ST_st16_fsm_15;
ap_ST_st25_fsm_24 :
ap_NS_fsm = ap_ST_st26_fsm_25;
ap_ST_st26_fsm_25 :
ap_NS_fsm = ap_ST_st27_fsm_26;
ap_ST_st27_fsm_26 :
ap_NS_fsm = ap_ST_st28_fsm_27;
ap_ST_st28_fsm_27 :
ap_NS_fsm = ap_ST_st29_fsm_28;
ap_ST_st29_fsm_28 :
ap_NS_fsm = ap_ST_st30_fsm_29;
ap_ST_st30_fsm_29 :
ap_NS_fsm = ap_ST_st31_fsm_30;
ap_ST_st31_fsm_30 :
ap_NS_fsm = ap_ST_st32_fsm_31;
ap_ST_st32_fsm_31 :
if ((~(stop_on_first_read_read_fu_150_p2 == ap_const_lv1_0) & (ap_const_lv1_0 == or_cond_fu_743_p2))) begin
ap_NS_fsm = ap_ST_st37_fsm_36;
end else begin
ap_NS_fsm = ap_ST_st33_fsm_32;
end
ap_ST_st33_fsm_32 :
ap_NS_fsm = ap_ST_st34_fsm_33;
ap_ST_st34_fsm_33 :
ap_NS_fsm = ap_ST_st35_fsm_34;
ap_ST_st35_fsm_34 :
ap_NS_fsm = ap_ST_st36_fsm_35;
ap_ST_st36_fsm_35 :
ap_NS_fsm = ap_ST_st2_fsm_1;
ap_ST_st37_fsm_36 :
ap_NS_fsm = ap_ST_st1_fsm_0;
default :
ap_NS_fsm = 'bx;
endcase
end
assign agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_592_p1 = $unsigned(agg_result_bucket_index_0_lcssa4_i_reg_296);
assign any_0_i_phi_fu_429_p4 = any_0_i_reg_424;
assign ap_return = p_0_reg_448;
/// ap_sig_bdd_187 assign process. ///
always @ (ap_CS_fsm or sample_buffer_rsp_empty_n)
begin
ap_sig_bdd_187 = ((ap_ST_st13_fsm_12 == ap_CS_fsm) & ~(sample_buffer_rsp_empty_n == ap_const_logic_0));
end
/// ap_sig_bdd_370 assign process. ///
always @ (tmp_2_i_fu_580_p2 or tmp_2_1_i_fu_586_p2)
begin
ap_sig_bdd_370 = (~(ap_const_lv1_0 == tmp_2_i_fu_580_p2) & (ap_const_lv1_0 == tmp_2_1_i_fu_586_p2));
end
assign c_1_fu_748_p2 = (c_load_reg_813 + ap_const_lv32_1);
assign current_buckets_0_1_fu_721_p2 = (next_buckets_0_reg_252 & tmp_buckets_0_reg_947);
assign current_buckets_1_1_fu_726_p2 = (next_buckets_1_reg_242 & tmp_buckets_1_reg_952);
assign grp_bitset_next_fu_460_ap_ce = ap_const_logic_1;
assign grp_bitset_next_fu_460_ap_start = grp_bitset_next_fu_460_ap_start_ap_start_reg;
assign grp_bitset_next_fu_460_p_read = next_buckets_1_reg_242;
assign grp_bitset_next_fu_460_r_bit = j_bit1_reg_404;
assign grp_bitset_next_fu_460_r_bucket = j_bucket1_reg_383;
assign grp_bitset_next_fu_460_r_bucket_index = j_bucket_index1_reg_394;
assign grp_fu_638_ce = ap_const_logic_1;
assign grp_fu_638_p0 = grp_fu_638_p00;
assign grp_fu_638_p00 = $unsigned(nfa_symbols);
assign grp_fu_638_p1 = grp_fu_638_p10;
assign grp_fu_638_p10 = $unsigned(state_fu_624_p2);
assign grp_nfa_get_finals_fu_500_ap_ce = ap_const_logic_1;
assign grp_nfa_get_finals_fu_500_ap_start = grp_nfa_get_finals_fu_500_ap_start_ap_start_reg;
assign grp_nfa_get_finals_fu_500_nfa_finals_buckets_datain = nfa_finals_buckets_datain;
assign grp_nfa_get_finals_fu_500_nfa_finals_buckets_req_full_n = nfa_finals_buckets_req_full_n;
assign grp_nfa_get_finals_fu_500_nfa_finals_buckets_rsp_empty_n = nfa_finals_buckets_rsp_empty_n;
assign grp_nfa_get_initials_fu_494_ap_ce = ap_const_logic_1;
assign grp_nfa_get_initials_fu_494_ap_start = grp_nfa_get_initials_fu_494_ap_start_ap_start_reg;
assign grp_nfa_get_initials_fu_494_nfa_initials_buckets_datain = nfa_initials_buckets_datain;
assign grp_nfa_get_initials_fu_494_nfa_initials_buckets_req_full_n = nfa_initials_buckets_req_full_n;
assign grp_nfa_get_initials_fu_494_nfa_initials_buckets_rsp_empty_n = nfa_initials_buckets_rsp_empty_n;
assign grp_sample_iterator_get_offset_fu_482_ap_ce = ap_const_logic_1;
assign grp_sample_iterator_get_offset_fu_482_ap_start = grp_sample_iterator_get_offset_fu_482_ap_start_ap_start_reg;
assign grp_sample_iterator_get_offset_fu_482_i_index = i_index_reg_222;
assign grp_sample_iterator_get_offset_fu_482_i_sample = i_sample_reg_232;
assign grp_sample_iterator_get_offset_fu_482_indices_datain = indices_datain;
assign grp_sample_iterator_get_offset_fu_482_indices_req_full_n = indices_req_full_n;
assign grp_sample_iterator_get_offset_fu_482_indices_rsp_empty_n = indices_rsp_empty_n;
assign grp_sample_iterator_get_offset_fu_482_sample_buffer_size = sample_buffer_length;
assign grp_sample_iterator_get_offset_fu_482_sample_length = sample_length;
assign grp_sample_iterator_next_fu_472_ap_ce = ap_const_logic_1;
assign grp_sample_iterator_next_fu_472_ap_start = grp_sample_iterator_next_fu_472_ap_start_ap_start_reg;
assign grp_sample_iterator_next_fu_472_i_index = i_index_reg_222;
assign grp_sample_iterator_next_fu_472_i_sample = i_sample_reg_232;
assign grp_sample_iterator_next_fu_472_indices_datain = indices_datain;
assign grp_sample_iterator_next_fu_472_indices_req_full_n = indices_req_full_n;
assign grp_sample_iterator_next_fu_472_indices_rsp_empty_n = indices_rsp_empty_n;
assign i_fu_568_p2 = (i_0_i_reg_262 + ap_const_lv16_1);
assign j_bit1_ph_cast_fu_601_p1 = $unsigned(j_bit1_ph_phi_fu_337_p4);
assign j_bucket_index1_ph_cast_fu_597_p1 = $unsigned(j_bucket_index1_ph_phi_fu_326_p4);
assign j_end_phi_fu_417_p4 = j_end_reg_414;
assign next_buckets_0_1_fu_701_p2 = (reg_512 | tmp_buckets_0_3_reg_370);
assign next_buckets_1_1_fu_707_p2 = (reg_512 | tmp_buckets_1_3_reg_357);
assign nfa_finals_buckets_address = grp_nfa_get_finals_fu_500_nfa_finals_buckets_address;
assign nfa_finals_buckets_dataout = grp_nfa_get_finals_fu_500_nfa_finals_buckets_dataout;
assign nfa_finals_buckets_req_din = grp_nfa_get_finals_fu_500_nfa_finals_buckets_req_din;
assign nfa_finals_buckets_req_write = grp_nfa_get_finals_fu_500_nfa_finals_buckets_req_write;
assign nfa_finals_buckets_rsp_read = grp_nfa_get_finals_fu_500_nfa_finals_buckets_rsp_read;
assign nfa_finals_buckets_size = grp_nfa_get_finals_fu_500_nfa_finals_buckets_size;
assign nfa_forward_buckets_dataout = ap_const_lv32_0;
assign nfa_forward_buckets_req_din = ap_const_logic_0;
assign nfa_forward_buckets_size = ap_const_lv32_1;
assign nfa_initials_buckets_address = grp_nfa_get_initials_fu_494_nfa_initials_buckets_address;
assign nfa_initials_buckets_dataout = grp_nfa_get_initials_fu_494_nfa_initials_buckets_dataout;
assign nfa_initials_buckets_req_din = grp_nfa_get_initials_fu_494_nfa_initials_buckets_req_din;
assign nfa_initials_buckets_req_write = grp_nfa_get_initials_fu_494_nfa_initials_buckets_req_write;
assign nfa_initials_buckets_rsp_read = grp_nfa_get_initials_fu_494_nfa_initials_buckets_rsp_read;
assign nfa_initials_buckets_size = grp_nfa_get_initials_fu_494_nfa_initials_buckets_size;
assign or_cond_fu_743_p2 = (r_reg_437 ^ accept);
assign p_rec_i_fu_574_p2 = (p_01_rec_i_reg_273 + ap_const_lv64_1);
assign r_bit_p_bsf32_hw_fu_506_bus_r = bus_assign_reg_284;
assign sample_buffer_address = sample_buffer_addr_reg_837;
assign sample_buffer_dataout = ap_const_lv8_0;
assign sample_buffer_req_din = ap_const_logic_0;
assign sample_buffer_size = ap_const_lv32_1;
assign state_fu_624_p2 = (tmp_i1_fu_612_p3 + tmp_8_fu_620_p1);
assign stop_on_first_read_read_fu_150_p2 = stop_on_first;
assign sum_fu_552_p2 = (p_01_rec_i_reg_273 + tmp_2_reg_832);
assign tmp_10_i_cast_fu_605_p1 = $unsigned(sym_reg_856);
assign tmp_11_i_fu_644_p2 = (grp_fu_638_p2 + tmp_10_i_cast_reg_884);
assign tmp_12_i_cast_fu_656_p1 = $unsigned(tmp_12_i_fu_649_p3);
assign tmp_12_i_fu_649_p3 = {{tmp_11_i_reg_899}, {ap_const_lv1_0}};
assign tmp_13_i_cast_fu_690_p1 = $unsigned(tmp_13_i_fu_683_p3);
assign tmp_13_i_fu_683_p3 = {{tmp_11_i_reg_899}, {ap_const_lv1_1}};
assign tmp_1_fu_731_p2 = (current_buckets_1_1_fu_726_p2 | current_buckets_0_1_fu_721_p2);
assign tmp_2_1_i_fu_586_p2 = (next_buckets_1_reg_242 == ap_const_lv32_0? 1'b1: 1'b0);
assign tmp_2_fu_548_p1 = $unsigned(grp_sample_iterator_get_offset_fu_482_ap_return);
assign tmp_2_i_fu_580_p2 = (next_buckets_0_reg_252 == ap_const_lv32_0? 1'b1: 1'b0);
assign tmp_3_fu_563_p2 = (i_0_i_reg_262 < sample_length? 1'b1: 1'b0);
assign tmp_5_fu_737_p2 = (tmp_1_fu_731_p2 != ap_const_lv32_0? 1'b1: 1'b0);
assign tmp_6_fu_608_p1 = j_bucket_index1_reg_394[0:0];
assign tmp_8_fu_620_p1 = j_bit1_reg_404[5:0];
assign tmp_i1_fu_612_p3 = {{tmp_6_fu_608_p1}, {ap_const_lv5_0}};
assign tmp_i_12_fu_529_p2 = (i_index_reg_222 == end_index? 1'b1: 1'b0);
assign tmp_i_13_fu_534_p2 = (tmp_i_fu_524_p2 & tmp_i_12_fu_529_p2);
assign tmp_i_fu_524_p2 = (i_sample_reg_232 == end_sample? 1'b1: 1'b0);
always @ (posedge ap_clk)
begin
tmp_2_reg_832[63:32] <= 32'b00000000000000000000000000000000;
tmp_10_i_cast_reg_884[13:8] <= 6'b000000;
end
endmodule //nfa_accept_samples_generic_hw
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: sg_list_reader_128.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Reads data from the scatter gather list buffer.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_SGR128_RD_0 1'b1
`define S_SGR128_RD_WAIT 1'b0
`define S_SGR128_CAP_0 1'b0
`define S_SGR128_CAP_RDY 1'b1
`timescale 1ns/1ns
module sg_list_reader_128 #(
parameter C_DATA_WIDTH = 9'd128
)
(
input CLK,
input RST,
input [C_DATA_WIDTH-1:0] BUF_DATA, // Scatter gather buffer data
input BUF_DATA_EMPTY, // Scatter gather buffer data empty
output BUF_DATA_REN, // Scatter gather buffer data read enable
output VALID, // Scatter gather element data is valid
output EMPTY, // Scatter gather elements empty
input REN, // Scatter gather element data read enable
output [63:0] ADDR, // Scatter gather element address
output [31:0] LEN // Scatter gather element length (in words)
);
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg rRdState=`S_SGR128_RD_0, _rRdState=`S_SGR128_RD_0;
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg rCapState=`S_SGR128_CAP_0, _rCapState=`S_SGR128_CAP_0;
reg [C_DATA_WIDTH-1:0] rData={C_DATA_WIDTH{1'd0}}, _rData={C_DATA_WIDTH{1'd0}};
reg [63:0] rAddr=64'd0, _rAddr=64'd0;
reg [31:0] rLen=0, _rLen=0;
reg rFifoValid=0, _rFifoValid=0;
reg rDataValid=0, _rDataValid=0;
assign BUF_DATA_REN = rRdState; // Not S_SGR128_RD_WAIT
assign VALID = rCapState; // S_SGR128_CAP_RDY
assign EMPTY = (BUF_DATA_EMPTY & rRdState); // Not S_SGR128_RD_WAIT
assign ADDR = rAddr;
assign LEN = rLen;
// Capture address and length as it comes out of the FIFO
always @ (posedge CLK) begin
rRdState <= #1 (RST ? `S_SGR128_RD_0 : _rRdState);
rCapState <= #1 (RST ? `S_SGR128_CAP_0 : _rCapState);
rData <= #1 _rData;
rFifoValid <= #1 (RST ? 1'd0 : _rFifoValid);
rDataValid <= #1 (RST ? 1'd0 : _rDataValid);
rAddr <= #1 _rAddr;
rLen <= #1 _rLen;
end
always @ (*) begin
_rRdState = rRdState;
_rCapState = rCapState;
_rAddr = rAddr;
_rLen = rLen;
_rData = BUF_DATA;
_rFifoValid = (BUF_DATA_REN & !BUF_DATA_EMPTY);
_rDataValid = rFifoValid;
case (rCapState)
`S_SGR128_CAP_0: begin
if (rDataValid) begin
_rAddr = rData[63:0];
_rLen = rData[95:64];
_rCapState = `S_SGR128_CAP_RDY;
end
end
`S_SGR128_CAP_RDY: begin
if (REN)
_rCapState = `S_SGR128_CAP_0;
end
endcase
case (rRdState)
`S_SGR128_RD_0: begin // Read from the sg data FIFO
if (!BUF_DATA_EMPTY)
_rRdState = `S_SGR128_RD_WAIT;
end
`S_SGR128_RD_WAIT: begin // Wait for the data to be consumed
if (REN)
_rRdState = `S_SGR128_RD_0;
end
endcase
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Wed Oct 25 12:44:01 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ srio_gen2_0_stub.v
// Design : srio_gen2_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "srio_gen2_v4_0_5,Vivado 2015.1.0" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(sys_clkp, sys_clkn, sys_rst, log_clk_out,
phy_clk_out, gt_clk_out, gt_pcs_clk_out, drpclk_out, refclk_out, clk_lock_out, cfg_rst_out,
log_rst_out, buf_rst_out, phy_rst_out, gt_pcs_rst_out, gt0_qpll_clk_out,
gt0_qpll_out_refclk_out, srio_rxn0, srio_rxp0, srio_rxn1, srio_rxp1, srio_rxn2, srio_rxp2,
srio_rxn3, srio_rxp3, srio_txn0, srio_txp0, srio_txn1, srio_txp1, srio_txn2, srio_txp2,
srio_txn3, srio_txp3, s_axis_iotx_tvalid, s_axis_iotx_tready, s_axis_iotx_tlast,
s_axis_iotx_tdata, s_axis_iotx_tkeep, s_axis_iotx_tuser, m_axis_iorx_tvalid,
m_axis_iorx_tready, m_axis_iorx_tlast, m_axis_iorx_tdata, m_axis_iorx_tkeep,
m_axis_iorx_tuser, s_axi_maintr_rst, s_axi_maintr_awvalid, s_axi_maintr_awready,
s_axi_maintr_awaddr, s_axi_maintr_wvalid, s_axi_maintr_wready, s_axi_maintr_wdata,
s_axi_maintr_bvalid, s_axi_maintr_bready, s_axi_maintr_bresp, s_axi_maintr_arvalid,
s_axi_maintr_arready, s_axi_maintr_araddr, s_axi_maintr_rvalid, s_axi_maintr_rready,
s_axi_maintr_rdata, s_axi_maintr_rresp, sim_train_en, force_reinit, phy_mce,
phy_link_reset, phy_rcvd_mce, phy_rcvd_link_reset, phy_debug, gtrx_disperr_or,
gtrx_notintable_or, port_error, port_timeout, srio_host, port_decode_error, deviceid,
idle2_selected, phy_lcl_master_enable_out, buf_lcl_response_only_out,
buf_lcl_tx_flow_control_out, buf_lcl_phy_buf_stat_out, phy_lcl_phy_next_fm_out,
phy_lcl_phy_last_ack_out, phy_lcl_phy_rewind_out, phy_lcl_phy_rcvd_buf_stat_out,
phy_lcl_maint_only_out, port_initialized, link_initialized, idle_selected, mode_1x)
/* synthesis syn_black_box black_box_pad_pin="sys_clkp,sys_clkn,sys_rst,log_clk_out,phy_clk_out,gt_clk_out,gt_pcs_clk_out,drpclk_out,refclk_out,clk_lock_out,cfg_rst_out,log_rst_out,buf_rst_out,phy_rst_out,gt_pcs_rst_out,gt0_qpll_clk_out,gt0_qpll_out_refclk_out,srio_rxn0,srio_rxp0,srio_rxn1,srio_rxp1,srio_rxn2,srio_rxp2,srio_rxn3,srio_rxp3,srio_txn0,srio_txp0,srio_txn1,srio_txp1,srio_txn2,srio_txp2,srio_txn3,srio_txp3,s_axis_iotx_tvalid,s_axis_iotx_tready,s_axis_iotx_tlast,s_axis_iotx_tdata[63:0],s_axis_iotx_tkeep[7:0],s_axis_iotx_tuser[31:0],m_axis_iorx_tvalid,m_axis_iorx_tready,m_axis_iorx_tlast,m_axis_iorx_tdata[63:0],m_axis_iorx_tkeep[7:0],m_axis_iorx_tuser[31:0],s_axi_maintr_rst,s_axi_maintr_awvalid,s_axi_maintr_awready,s_axi_maintr_awaddr[31:0],s_axi_maintr_wvalid,s_axi_maintr_wready,s_axi_maintr_wdata[31:0],s_axi_maintr_bvalid,s_axi_maintr_bready,s_axi_maintr_bresp[1:0],s_axi_maintr_arvalid,s_axi_maintr_arready,s_axi_maintr_araddr[31:0],s_axi_maintr_rvalid,s_axi_maintr_rready,s_axi_maintr_rdata[31:0],s_axi_maintr_rresp[1:0],sim_train_en,force_reinit,phy_mce,phy_link_reset,phy_rcvd_mce,phy_rcvd_link_reset,phy_debug[223:0],gtrx_disperr_or,gtrx_notintable_or,port_error,port_timeout[23:0],srio_host,port_decode_error,deviceid[15:0],idle2_selected,phy_lcl_master_enable_out,buf_lcl_response_only_out,buf_lcl_tx_flow_control_out,buf_lcl_phy_buf_stat_out[5:0],phy_lcl_phy_next_fm_out[5:0],phy_lcl_phy_last_ack_out[5:0],phy_lcl_phy_rewind_out,phy_lcl_phy_rcvd_buf_stat_out[5:0],phy_lcl_maint_only_out,port_initialized,link_initialized,idle_selected,mode_1x" */;
input sys_clkp;
input sys_clkn;
input sys_rst;
output log_clk_out;
output phy_clk_out;
output gt_clk_out;
output gt_pcs_clk_out;
output drpclk_out;
output refclk_out;
output clk_lock_out;
output cfg_rst_out;
output log_rst_out;
output buf_rst_out;
output phy_rst_out;
output gt_pcs_rst_out;
output gt0_qpll_clk_out;
output gt0_qpll_out_refclk_out;
input srio_rxn0;
input srio_rxp0;
input srio_rxn1;
input srio_rxp1;
input srio_rxn2;
input srio_rxp2;
input srio_rxn3;
input srio_rxp3;
output srio_txn0;
output srio_txp0;
output srio_txn1;
output srio_txp1;
output srio_txn2;
output srio_txp2;
output srio_txn3;
output srio_txp3;
input s_axis_iotx_tvalid;
output s_axis_iotx_tready;
input s_axis_iotx_tlast;
input [63:0]s_axis_iotx_tdata;
input [7:0]s_axis_iotx_tkeep;
input [31:0]s_axis_iotx_tuser;
output m_axis_iorx_tvalid;
input m_axis_iorx_tready;
output m_axis_iorx_tlast;
output [63:0]m_axis_iorx_tdata;
output [7:0]m_axis_iorx_tkeep;
output [31:0]m_axis_iorx_tuser;
input s_axi_maintr_rst;
input s_axi_maintr_awvalid;
output s_axi_maintr_awready;
input [31:0]s_axi_maintr_awaddr;
input s_axi_maintr_wvalid;
output s_axi_maintr_wready;
input [31:0]s_axi_maintr_wdata;
output s_axi_maintr_bvalid;
input s_axi_maintr_bready;
output [1:0]s_axi_maintr_bresp;
input s_axi_maintr_arvalid;
output s_axi_maintr_arready;
input [31:0]s_axi_maintr_araddr;
output s_axi_maintr_rvalid;
input s_axi_maintr_rready;
output [31:0]s_axi_maintr_rdata;
output [1:0]s_axi_maintr_rresp;
input sim_train_en;
input force_reinit;
input phy_mce;
input phy_link_reset;
output phy_rcvd_mce;
output phy_rcvd_link_reset;
output [223:0]phy_debug;
output gtrx_disperr_or;
output gtrx_notintable_or;
output port_error;
output [23:0]port_timeout;
output srio_host;
output port_decode_error;
output [15:0]deviceid;
output idle2_selected;
output phy_lcl_master_enable_out;
output buf_lcl_response_only_out;
output buf_lcl_tx_flow_control_out;
output [5:0]buf_lcl_phy_buf_stat_out;
output [5:0]phy_lcl_phy_next_fm_out;
output [5:0]phy_lcl_phy_last_ack_out;
output phy_lcl_phy_rewind_out;
output [5:0]phy_lcl_phy_rcvd_buf_stat_out;
output phy_lcl_maint_only_out;
output port_initialized;
output link_initialized;
output idle_selected;
output mode_1x;
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module TimeHoldOver_Qsys_uart_0_tx (
// inputs:
baud_divisor,
begintransfer,
clk,
clk_en,
do_force_break,
reset_n,
status_wr_strobe,
tx_data,
tx_wr_strobe,
// outputs:
tx_overrun,
tx_ready,
tx_shift_empty,
txd
)
;
output tx_overrun;
output tx_ready;
output tx_shift_empty;
output txd;
input [ 9: 0] baud_divisor;
input begintransfer;
input clk;
input clk_en;
input do_force_break;
input reset_n;
input status_wr_strobe;
input [ 7: 0] tx_data;
input tx_wr_strobe;
reg baud_clk_en;
reg [ 9: 0] baud_rate_counter;
wire baud_rate_counter_is_zero;
reg do_load_shifter;
wire do_shift;
reg pre_txd;
wire shift_done;
wire [ 9: 0] tx_load_val;
reg tx_overrun;
reg tx_ready;
reg tx_shift_empty;
wire tx_shift_reg_out;
wire [ 9: 0] tx_shift_register_contents;
wire tx_wr_strobe_onset;
reg txd;
wire [ 9: 0] unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in;
reg [ 9: 0] unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out;
assign tx_wr_strobe_onset = tx_wr_strobe && begintransfer;
assign tx_load_val = {{1 {1'b1}},
tx_data,
1'b0};
assign shift_done = ~(|tx_shift_register_contents);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
do_load_shifter <= 0;
else if (clk_en)
do_load_shifter <= (~tx_ready) && shift_done;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tx_ready <= 1'b1;
else if (clk_en)
if (tx_wr_strobe_onset)
tx_ready <= 0;
else if (do_load_shifter)
tx_ready <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tx_overrun <= 0;
else if (clk_en)
if (status_wr_strobe)
tx_overrun <= 0;
else if (~tx_ready && tx_wr_strobe_onset)
tx_overrun <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tx_shift_empty <= 1'b1;
else if (clk_en)
tx_shift_empty <= tx_ready && shift_done;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
baud_rate_counter <= 0;
else if (clk_en)
if (baud_rate_counter_is_zero || do_load_shifter)
baud_rate_counter <= baud_divisor;
else
baud_rate_counter <= baud_rate_counter - 1;
end
assign baud_rate_counter_is_zero = baud_rate_counter == 0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
baud_clk_en <= 0;
else if (clk_en)
baud_clk_en <= baud_rate_counter_is_zero;
end
assign do_shift = baud_clk_en &&
(~shift_done) &&
(~do_load_shifter);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
pre_txd <= 1;
else if (~shift_done)
pre_txd <= tx_shift_reg_out;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
txd <= 1;
else if (clk_en)
txd <= pre_txd & ~do_force_break;
end
//_reg, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out <= 0;
else if (clk_en)
unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out <= unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in;
end
assign unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in = (do_load_shifter)? tx_load_val :
(do_shift)? {1'b0,
unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9 : 1]} :
unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out;
assign tx_shift_register_contents = unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out;
assign tx_shift_reg_out = unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0];
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module TimeHoldOver_Qsys_uart_0_rx_stimulus_source (
// inputs:
baud_divisor,
clk,
clk_en,
reset_n,
rx_char_ready,
rxd,
// outputs:
source_rxd
)
;
output source_rxd;
input [ 9: 0] baud_divisor;
input clk;
input clk_en;
input reset_n;
input rx_char_ready;
input rxd;
reg [ 7: 0] d1_stim_data;
reg delayed_unxrx_char_readyxx0;
wire do_send_stim_data;
wire pickup_pulse;
wire source_rxd;
wire [ 7: 0] stim_data;
wire unused_empty;
wire unused_overrun;
wire unused_ready;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//stimulus_transmitter, which is an e_instance
TimeHoldOver_Qsys_uart_0_tx stimulus_transmitter
(
.baud_divisor (baud_divisor),
.begintransfer (do_send_stim_data),
.clk (clk),
.clk_en (clk_en),
.do_force_break (1'b0),
.reset_n (reset_n),
.status_wr_strobe (1'b0),
.tx_data (d1_stim_data),
.tx_overrun (unused_overrun),
.tx_ready (unused_ready),
.tx_shift_empty (unused_empty),
.tx_wr_strobe (1'b1),
.txd (source_rxd)
);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_stim_data <= 0;
else if (do_send_stim_data)
d1_stim_data <= stim_data;
end
assign stim_data = 8'b0;
//delayed_unxrx_char_readyxx0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxrx_char_readyxx0 <= 0;
else if (clk_en)
delayed_unxrx_char_readyxx0 <= rx_char_ready;
end
assign pickup_pulse = ~(rx_char_ready) & (delayed_unxrx_char_readyxx0);
assign do_send_stim_data = (pickup_pulse || 1'b0) && 1'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign source_rxd = rxd;
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module TimeHoldOver_Qsys_uart_0_rx (
// inputs:
baud_divisor,
begintransfer,
clk,
clk_en,
reset_n,
rx_rd_strobe,
rxd,
status_wr_strobe,
// outputs:
break_detect,
framing_error,
parity_error,
rx_char_ready,
rx_data,
rx_overrun
)
;
output break_detect;
output framing_error;
output parity_error;
output rx_char_ready;
output [ 7: 0] rx_data;
output rx_overrun;
input [ 9: 0] baud_divisor;
input begintransfer;
input clk;
input clk_en;
input reset_n;
input rx_rd_strobe;
input rxd;
input status_wr_strobe;
reg baud_clk_en;
wire [ 9: 0] baud_load_value;
reg [ 9: 0] baud_rate_counter;
wire baud_rate_counter_is_zero;
reg break_detect;
reg delayed_unxrx_in_processxx3;
reg delayed_unxsync_rxdxx1;
reg delayed_unxsync_rxdxx2;
reg do_start_rx;
reg framing_error;
wire got_new_char;
wire [ 8: 0] half_bit_cell_divisor;
wire is_break;
wire is_framing_error;
wire parity_error;
wire [ 7: 0] raw_data_in;
reg rx_char_ready;
reg [ 7: 0] rx_data;
wire rx_in_process;
reg rx_overrun;
wire rx_rd_strobe_onset;
wire rxd_edge;
wire rxd_falling;
wire [ 9: 0] rxd_shift_reg;
wire sample_enable;
wire shift_reg_start_bit_n;
wire source_rxd;
wire stop_bit;
wire sync_rxd;
wire unused_start_bit;
wire [ 9: 0] unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_in;
reg [ 9: 0] unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out;
TimeHoldOver_Qsys_uart_0_rx_stimulus_source the_TimeHoldOver_Qsys_uart_0_rx_stimulus_source
(
.baud_divisor (baud_divisor),
.clk (clk),
.clk_en (clk_en),
.reset_n (reset_n),
.rx_char_ready (rx_char_ready),
.rxd (rxd),
.source_rxd (source_rxd)
);
altera_std_synchronizer the_altera_std_synchronizer
(
.clk (clk),
.din (source_rxd),
.dout (sync_rxd),
.reset_n (reset_n)
);
defparam the_altera_std_synchronizer.depth = 2;
//delayed_unxsync_rxdxx1, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxsync_rxdxx1 <= 0;
else if (clk_en)
delayed_unxsync_rxdxx1 <= sync_rxd;
end
assign rxd_falling = ~(sync_rxd) & (delayed_unxsync_rxdxx1);
//delayed_unxsync_rxdxx2, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxsync_rxdxx2 <= 0;
else if (clk_en)
delayed_unxsync_rxdxx2 <= sync_rxd;
end
assign rxd_edge = (sync_rxd) ^ (delayed_unxsync_rxdxx2);
assign rx_rd_strobe_onset = rx_rd_strobe && begintransfer;
assign half_bit_cell_divisor = baud_divisor[9 : 1];
assign baud_load_value = (rxd_edge)? half_bit_cell_divisor :
baud_divisor;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
baud_rate_counter <= 0;
else if (clk_en)
if (baud_rate_counter_is_zero || rxd_edge)
baud_rate_counter <= baud_load_value;
else
baud_rate_counter <= baud_rate_counter - 1;
end
assign baud_rate_counter_is_zero = baud_rate_counter == 0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
baud_clk_en <= 0;
else if (clk_en)
if (rxd_edge)
baud_clk_en <= 0;
else
baud_clk_en <= baud_rate_counter_is_zero;
end
assign sample_enable = baud_clk_en && rx_in_process;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
do_start_rx <= 0;
else if (clk_en)
if (~rx_in_process && rxd_falling)
do_start_rx <= 1;
else
do_start_rx <= 0;
end
assign rx_in_process = shift_reg_start_bit_n;
assign {stop_bit,
raw_data_in,
unused_start_bit} = rxd_shift_reg;
assign is_break = ~(|rxd_shift_reg);
assign is_framing_error = ~stop_bit && ~is_break;
//delayed_unxrx_in_processxx3, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxrx_in_processxx3 <= 0;
else if (clk_en)
delayed_unxrx_in_processxx3 <= rx_in_process;
end
assign got_new_char = ~(rx_in_process) & (delayed_unxrx_in_processxx3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rx_data <= 0;
else if (got_new_char)
rx_data <= raw_data_in;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
framing_error <= 0;
else if (clk_en)
if (status_wr_strobe)
framing_error <= 0;
else if (got_new_char && is_framing_error)
framing_error <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
break_detect <= 0;
else if (clk_en)
if (status_wr_strobe)
break_detect <= 0;
else if (got_new_char && is_break)
break_detect <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rx_overrun <= 0;
else if (clk_en)
if (status_wr_strobe)
rx_overrun <= 0;
else if (got_new_char && rx_char_ready)
rx_overrun <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rx_char_ready <= 0;
else if (clk_en)
if (rx_rd_strobe_onset)
rx_char_ready <= 0;
else if (got_new_char)
rx_char_ready <= -1;
end
assign parity_error = 0;
//_reg, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out <= 0;
else if (clk_en)
unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out <= unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_in;
end
assign unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_in = (do_start_rx)? {10{1'b1}} :
(sample_enable)? {sync_rxd,
unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9 : 1]} :
unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out;
assign rxd_shift_reg = unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out;
assign shift_reg_start_bit_n = unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0];
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module TimeHoldOver_Qsys_uart_0_regs (
// inputs:
address,
break_detect,
chipselect,
clk,
clk_en,
framing_error,
parity_error,
read_n,
reset_n,
rx_char_ready,
rx_data,
rx_overrun,
tx_overrun,
tx_ready,
tx_shift_empty,
write_n,
writedata,
// outputs:
baud_divisor,
dataavailable,
do_force_break,
irq,
readdata,
readyfordata,
rx_rd_strobe,
status_wr_strobe,
tx_data,
tx_wr_strobe
)
;
output [ 9: 0] baud_divisor;
output dataavailable;
output do_force_break;
output irq;
output [ 15: 0] readdata;
output readyfordata;
output rx_rd_strobe;
output status_wr_strobe;
output [ 7: 0] tx_data;
output tx_wr_strobe;
input [ 2: 0] address;
input break_detect;
input chipselect;
input clk;
input clk_en;
input framing_error;
input parity_error;
input read_n;
input reset_n;
input rx_char_ready;
input [ 7: 0] rx_data;
input rx_overrun;
input tx_overrun;
input tx_ready;
input tx_shift_empty;
input write_n;
input [ 15: 0] writedata;
wire any_error;
wire [ 9: 0] baud_divisor;
reg [ 9: 0] control_reg;
wire control_wr_strobe;
wire cts_status_bit;
reg d1_rx_char_ready;
reg d1_tx_ready;
wire dataavailable;
wire dcts_status_bit;
reg delayed_unxtx_readyxx4;
wire [ 9: 0] divisor_constant;
wire do_force_break;
wire do_write_char;
wire eop_status_bit;
wire ie_any_error;
wire ie_break_detect;
wire ie_framing_error;
wire ie_parity_error;
wire ie_rx_char_ready;
wire ie_rx_overrun;
wire ie_tx_overrun;
wire ie_tx_ready;
wire ie_tx_shift_empty;
reg irq;
wire qualified_irq;
reg [ 15: 0] readdata;
wire readyfordata;
wire rx_rd_strobe;
wire [ 15: 0] selected_read_data;
wire [ 12: 0] status_reg;
wire status_wr_strobe;
reg [ 7: 0] tx_data;
wire tx_wr_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= selected_read_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq <= 0;
else if (clk_en)
irq <= qualified_irq;
end
assign rx_rd_strobe = chipselect && ~read_n && (address == 3'd0);
assign tx_wr_strobe = chipselect && ~write_n && (address == 3'd1);
assign status_wr_strobe = chipselect && ~write_n && (address == 3'd2);
assign control_wr_strobe = chipselect && ~write_n && (address == 3'd3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tx_data <= 0;
else if (tx_wr_strobe)
tx_data <= writedata[7 : 0];
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_reg <= 0;
else if (control_wr_strobe)
control_reg <= writedata[9 : 0];
end
assign baud_divisor = divisor_constant;
assign cts_status_bit = 0;
assign dcts_status_bit = 0;
assign {do_force_break,
ie_any_error,
ie_rx_char_ready,
ie_tx_ready,
ie_tx_shift_empty,
ie_tx_overrun,
ie_rx_overrun,
ie_break_detect,
ie_framing_error,
ie_parity_error} = control_reg;
assign any_error = tx_overrun ||
rx_overrun ||
parity_error ||
framing_error ||
break_detect;
assign status_reg = {eop_status_bit,
cts_status_bit,
dcts_status_bit,
1'b0,
any_error,
rx_char_ready,
tx_ready,
tx_shift_empty,
tx_overrun,
rx_overrun,
break_detect,
framing_error,
parity_error};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_rx_char_ready <= 0;
else if (clk_en)
d1_rx_char_ready <= rx_char_ready;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_tx_ready <= 0;
else if (clk_en)
d1_tx_ready <= tx_ready;
end
assign dataavailable = d1_rx_char_ready;
assign readyfordata = d1_tx_ready;
assign eop_status_bit = 1'b0;
assign selected_read_data = ({16 {(address == 3'd0)}} & rx_data) |
({16 {(address == 3'd1)}} & tx_data) |
({16 {(address == 3'd2)}} & status_reg) |
({16 {(address == 3'd3)}} & control_reg);
assign qualified_irq = (ie_any_error && any_error ) ||
(ie_tx_shift_empty && tx_shift_empty ) ||
(ie_tx_overrun && tx_overrun ) ||
(ie_rx_overrun && rx_overrun ) ||
(ie_break_detect && break_detect ) ||
(ie_framing_error && framing_error ) ||
(ie_parity_error && parity_error ) ||
(ie_rx_char_ready && rx_char_ready ) ||
(ie_tx_ready && tx_ready );
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//delayed_unxtx_readyxx4, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxtx_readyxx4 <= 0;
else if (clk_en)
delayed_unxtx_readyxx4 <= tx_ready;
end
assign do_write_char = (tx_ready) & ~(delayed_unxtx_readyxx4);
always @(posedge clk)
begin
if (do_write_char)
$write("%c", tx_data);
end
assign divisor_constant = 4;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign divisor_constant = 868;
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module TimeHoldOver_Qsys_uart_0 (
// inputs:
address,
begintransfer,
chipselect,
clk,
read_n,
reset_n,
rxd,
write_n,
writedata,
// outputs:
dataavailable,
irq,
readdata,
readyfordata,
txd
)
/* synthesis altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION OFF" */ ;
output dataavailable;
output irq;
output [ 15: 0] readdata;
output readyfordata;
output txd;
input [ 2: 0] address;
input begintransfer;
input chipselect;
input clk;
input read_n;
input reset_n;
input rxd;
input write_n;
input [ 15: 0] writedata;
wire [ 9: 0] baud_divisor;
wire break_detect;
wire clk_en;
wire dataavailable;
wire do_force_break;
wire framing_error;
wire irq;
wire parity_error;
wire [ 15: 0] readdata;
wire readyfordata;
wire rx_char_ready;
wire [ 7: 0] rx_data;
wire rx_overrun;
wire rx_rd_strobe;
wire status_wr_strobe;
wire [ 7: 0] tx_data;
wire tx_overrun;
wire tx_ready;
wire tx_shift_empty;
wire tx_wr_strobe;
wire txd;
assign clk_en = 1;
TimeHoldOver_Qsys_uart_0_tx the_TimeHoldOver_Qsys_uart_0_tx
(
.baud_divisor (baud_divisor),
.begintransfer (begintransfer),
.clk (clk),
.clk_en (clk_en),
.do_force_break (do_force_break),
.reset_n (reset_n),
.status_wr_strobe (status_wr_strobe),
.tx_data (tx_data),
.tx_overrun (tx_overrun),
.tx_ready (tx_ready),
.tx_shift_empty (tx_shift_empty),
.tx_wr_strobe (tx_wr_strobe),
.txd (txd)
);
TimeHoldOver_Qsys_uart_0_rx the_TimeHoldOver_Qsys_uart_0_rx
(
.baud_divisor (baud_divisor),
.begintransfer (begintransfer),
.break_detect (break_detect),
.clk (clk),
.clk_en (clk_en),
.framing_error (framing_error),
.parity_error (parity_error),
.reset_n (reset_n),
.rx_char_ready (rx_char_ready),
.rx_data (rx_data),
.rx_overrun (rx_overrun),
.rx_rd_strobe (rx_rd_strobe),
.rxd (rxd),
.status_wr_strobe (status_wr_strobe)
);
TimeHoldOver_Qsys_uart_0_regs the_TimeHoldOver_Qsys_uart_0_regs
(
.address (address),
.baud_divisor (baud_divisor),
.break_detect (break_detect),
.chipselect (chipselect),
.clk (clk),
.clk_en (clk_en),
.dataavailable (dataavailable),
.do_force_break (do_force_break),
.framing_error (framing_error),
.irq (irq),
.parity_error (parity_error),
.read_n (read_n),
.readdata (readdata),
.readyfordata (readyfordata),
.reset_n (reset_n),
.rx_char_ready (rx_char_ready),
.rx_data (rx_data),
.rx_overrun (rx_overrun),
.rx_rd_strobe (rx_rd_strobe),
.status_wr_strobe (status_wr_strobe),
.tx_data (tx_data),
.tx_overrun (tx_overrun),
.tx_ready (tx_ready),
.tx_shift_empty (tx_shift_empty),
.tx_wr_strobe (tx_wr_strobe),
.write_n (write_n),
.writedata (writedata)
);
//s1, which is an e_avalon_slave
endmodule
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007, 2008 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.4
// \ \ Application: MIG
// / / Filename: ddr2_phy_io.v
// /___/ /\ Date Last Modified: $Date: 2009/11/03 04:43:18 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// This module instantiates calibration logic, data, data strobe and the
// data mask iobs.
//Reference:
//Revision History:
// Rev 1.1 - DM_IOB instance made based on USE_DM_PORT value . PK. 25/6/08
// Rev 1.2 - Parameter HIGH_PERFORMANCE_MODE added. PK. 7/10/08
// Rev 1.3 - Parameter IODELAY_GRP added. PK. 11/27/08
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_phy_io #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module mig_v3_4 module. Please refer to
// the mig_v3_4 module for actual values.
parameter CLK_WIDTH = 1,
parameter USE_DM_PORT = 1,
parameter DM_WIDTH = 9,
parameter DQ_WIDTH = 72,
parameter DQ_BITS = 7,
parameter DQ_PER_DQS = 8,
parameter DQS_BITS = 4,
parameter DQS_WIDTH = 9,
parameter HIGH_PERFORMANCE_MODE = "TRUE",
parameter IODELAY_GRP = "IODELAY_MIG",
parameter ODT_WIDTH = 1,
parameter ADDITIVE_LAT = 0,
parameter CAS_LAT = 5,
parameter REG_ENABLE = 1,
parameter CLK_PERIOD = 3000,
parameter DDR_TYPE = 1,
parameter SIM_ONLY = 0,
parameter DEBUG_EN = 0,
parameter FPGA_SPEED_GRADE = 2
)
(
input clk0,
input clk90,
input clkdiv0,
input rst0,
input rst90,
input rstdiv0,
input dm_ce,
input [1:0] dq_oe_n,
input dqs_oe_n,
input dqs_rst_n,
input [3:0] calib_start,
input ctrl_rden,
input phy_init_rden,
input calib_ref_done,
output [3:0] calib_done,
output calib_ref_req,
output [DQS_WIDTH-1:0] calib_rden,
output [DQS_WIDTH-1:0] calib_rden_sel,
input [DQ_WIDTH-1:0] wr_data_rise,
input [DQ_WIDTH-1:0] wr_data_fall,
input [(DQ_WIDTH/8)-1:0] mask_data_rise,
input [(DQ_WIDTH/8)-1:0] mask_data_fall,
output [(DQ_WIDTH)-1:0] rd_data_rise,
output [(DQ_WIDTH)-1:0] rd_data_fall,
output [CLK_WIDTH-1:0] ddr_ck,
output [CLK_WIDTH-1:0] ddr_ck_n,
output [DM_WIDTH-1:0] ddr_dm,
inout [DQS_WIDTH-1:0] ddr_dqs,
inout [DQS_WIDTH-1:0] ddr_dqs_n,
inout [DQ_WIDTH-1:0] ddr_dq,
// Debug signals (optional use)
input dbg_idel_up_all,
input dbg_idel_down_all,
input dbg_idel_up_dq,
input dbg_idel_down_dq,
input dbg_idel_up_dqs,
input dbg_idel_down_dqs,
input dbg_idel_up_gate,
input dbg_idel_down_gate,
input [DQ_BITS-1:0] dbg_sel_idel_dq,
input dbg_sel_all_idel_dq,
input [DQS_BITS:0] dbg_sel_idel_dqs,
input dbg_sel_all_idel_dqs,
input [DQS_BITS:0] dbg_sel_idel_gate,
input dbg_sel_all_idel_gate,
output [3:0] dbg_calib_done,
output [3:0] dbg_calib_err,
output [(6*DQ_WIDTH)-1:0] dbg_calib_dq_tap_cnt,
output [(6*DQS_WIDTH)-1:0] dbg_calib_dqs_tap_cnt,
output [(6*DQS_WIDTH)-1:0] dbg_calib_gate_tap_cnt,
output [DQS_WIDTH-1:0] dbg_calib_rd_data_sel,
output [(5*DQS_WIDTH)-1:0] dbg_calib_rden_dly,
output [(5*DQS_WIDTH)-1:0] dbg_calib_gate_dly
);
// ratio of # of physical DM outputs to bytes in data bus
// may be different - e.g. if using x4 components
localparam DM_TO_BYTE_RATIO = DM_WIDTH / (DQ_WIDTH/8);
wire [CLK_WIDTH-1:0] ddr_ck_q;
wire [DQS_WIDTH-1:0] delayed_dqs;
wire [DQ_WIDTH-1:0] dlyce_dq;
wire [DQS_WIDTH-1:0] dlyce_dqs;
wire [DQS_WIDTH-1:0] dlyce_gate;
wire [DQ_WIDTH-1:0] dlyinc_dq;
wire [DQS_WIDTH-1:0] dlyinc_dqs;
wire [DQS_WIDTH-1:0] dlyinc_gate;
wire dlyrst_dq;
wire dlyrst_dqs;
wire [DQS_WIDTH-1:0] dlyrst_gate;
wire [DQS_WIDTH-1:0] dq_ce;
(* KEEP = "TRUE" *) wire [DQS_WIDTH-1:0] en_dqs /* synthesis syn_keep = 1 */;
wire [DQS_WIDTH-1:0] rd_data_sel;
//***************************************************************************
ddr2_phy_calib #
(
.DQ_WIDTH (DQ_WIDTH),
.DQ_BITS (DQ_BITS),
.DQ_PER_DQS (DQ_PER_DQS),
.DQS_BITS (DQS_BITS),
.DQS_WIDTH (DQS_WIDTH),
.ADDITIVE_LAT (ADDITIVE_LAT),
.CAS_LAT (CAS_LAT),
.REG_ENABLE (REG_ENABLE),
.CLK_PERIOD (CLK_PERIOD),
.SIM_ONLY (SIM_ONLY),
.DEBUG_EN (DEBUG_EN)
)
u_phy_calib
(
.clk (clk0),
.clkdiv (clkdiv0),
.rstdiv (rstdiv0),
.calib_start (calib_start),
.ctrl_rden (ctrl_rden),
.phy_init_rden (phy_init_rden),
.rd_data_rise (rd_data_rise),
.rd_data_fall (rd_data_fall),
.calib_ref_done (calib_ref_done),
.calib_done (calib_done),
.calib_ref_req (calib_ref_req),
.calib_rden (calib_rden),
.calib_rden_sel (calib_rden_sel),
.dlyrst_dq (dlyrst_dq),
.dlyce_dq (dlyce_dq),
.dlyinc_dq (dlyinc_dq),
.dlyrst_dqs (dlyrst_dqs),
.dlyce_dqs (dlyce_dqs),
.dlyinc_dqs (dlyinc_dqs),
.dlyrst_gate (dlyrst_gate),
.dlyce_gate (dlyce_gate),
.dlyinc_gate (dlyinc_gate),
.en_dqs (en_dqs),
.rd_data_sel (rd_data_sel),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_dq (dbg_idel_up_dq),
.dbg_idel_down_dq (dbg_idel_down_dq),
.dbg_idel_up_dqs (dbg_idel_up_dqs),
.dbg_idel_down_dqs (dbg_idel_down_dqs),
.dbg_idel_up_gate (dbg_idel_up_gate),
.dbg_idel_down_gate (dbg_idel_down_gate),
.dbg_sel_idel_dq (dbg_sel_idel_dq),
.dbg_sel_all_idel_dq (dbg_sel_all_idel_dq),
.dbg_sel_idel_dqs (dbg_sel_idel_dqs),
.dbg_sel_all_idel_dqs (dbg_sel_all_idel_dqs),
.dbg_sel_idel_gate (dbg_sel_idel_gate),
.dbg_sel_all_idel_gate (dbg_sel_all_idel_gate),
.dbg_calib_done (dbg_calib_done),
.dbg_calib_err (dbg_calib_err),
.dbg_calib_dq_tap_cnt (dbg_calib_dq_tap_cnt),
.dbg_calib_dqs_tap_cnt (dbg_calib_dqs_tap_cnt),
.dbg_calib_gate_tap_cnt (dbg_calib_gate_tap_cnt),
.dbg_calib_rd_data_sel (dbg_calib_rd_data_sel),
.dbg_calib_rden_dly (dbg_calib_rden_dly),
.dbg_calib_gate_dly (dbg_calib_gate_dly)
);
//***************************************************************************
// Memory clock generation
//***************************************************************************
genvar ck_i;
generate
for(ck_i = 0; ck_i < CLK_WIDTH; ck_i = ck_i+1) begin: gen_ck
ODDR #
(
.SRTYPE ("SYNC"),
.DDR_CLK_EDGE ("OPPOSITE_EDGE")
)
u_oddr_ck_i
(
.Q (ddr_ck_q[ck_i]),
.C (clk0),
.CE (1'b1),
.D1 (1'b0),
.D2 (1'b1),
.R (1'b0),
.S (1'b0)
);
// Can insert ODELAY here if required
OBUFDS u_obuf_ck_i
(
.I (ddr_ck_q[ck_i]),
.O (ddr_ck[ck_i]),
.OB (ddr_ck_n[ck_i])
);
end
endgenerate
//***************************************************************************
// DQS instances
//***************************************************************************
genvar dqs_i;
generate
for(dqs_i = 0; dqs_i < DQS_WIDTH; dqs_i = dqs_i+1) begin: gen_dqs
ddr2_phy_dqs_iob #
(
.DDR_TYPE (DDR_TYPE),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.IODELAY_GRP (IODELAY_GRP)
)
u_iob_dqs
(
.clk0 (clk0),
.clkdiv0 (clkdiv0),
.rst0 (rst0),
.dlyinc_dqs (dlyinc_dqs[dqs_i]),
.dlyce_dqs (dlyce_dqs[dqs_i]),
.dlyrst_dqs (dlyrst_dqs),
.dlyinc_gate (dlyinc_gate[dqs_i]),
.dlyce_gate (dlyce_gate[dqs_i]),
.dlyrst_gate (dlyrst_gate[dqs_i]),
.dqs_oe_n (dqs_oe_n),
.dqs_rst_n (dqs_rst_n),
.en_dqs (en_dqs[dqs_i]),
.ddr_dqs (ddr_dqs[dqs_i]),
.ddr_dqs_n (ddr_dqs_n[dqs_i]),
.dq_ce (dq_ce[dqs_i]),
.delayed_dqs (delayed_dqs[dqs_i])
);
end
endgenerate
//***************************************************************************
// DM instances
//***************************************************************************
genvar dm_i;
generate
if (USE_DM_PORT) begin: gen_dm_inst
for(dm_i = 0; dm_i < DM_WIDTH; dm_i = dm_i+1) begin: gen_dm
ddr2_phy_dm_iob u_iob_dm
(
.clk90 (clk90),
.dm_ce (dm_ce),
.mask_data_rise (mask_data_rise[dm_i/DM_TO_BYTE_RATIO]),
.mask_data_fall (mask_data_fall[dm_i/DM_TO_BYTE_RATIO]),
.ddr_dm (ddr_dm[dm_i])
);
end
end
endgenerate
//***************************************************************************
// DQ IOB instances
//***************************************************************************
genvar dq_i;
generate
for(dq_i = 0; dq_i < DQ_WIDTH; dq_i = dq_i+1) begin: gen_dq
ddr2_phy_dq_iob #
(
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE)
)
u_iob_dq
(
.clk0 (clk0),
.clk90 (clk90),
.clkdiv0 (clkdiv0),
.rst90 (rst90),
.dlyinc (dlyinc_dq[dq_i]),
.dlyce (dlyce_dq[dq_i]),
.dlyrst (dlyrst_dq),
.dq_oe_n (dq_oe_n),
.dqs (delayed_dqs[dq_i/DQ_PER_DQS]),
.ce (dq_ce[dq_i/DQ_PER_DQS]),
.rd_data_sel (rd_data_sel[dq_i/DQ_PER_DQS]),
.wr_data_rise (wr_data_rise[dq_i]),
.wr_data_fall (wr_data_fall[dq_i]),
.rd_data_rise (rd_data_rise[dq_i]),
.rd_data_fall (rd_data_fall[dq_i]),
.ddr_dq (ddr_dq[dq_i])
);
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND4_BLACKBOX_V
`define SKY130_FD_SC_HDLL__AND4_BLACKBOX_V
/**
* and4: 4-input AND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__and4 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND4_BLACKBOX_V
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
// IP Revision: 8
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_auto_us_0 (
s_axi_aclk,
s_axi_aresetn,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_dwidth_converter_v2_1_8_top #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(0),
.C_S_AXI_ID_WIDTH(1),
.C_SUPPORTS_ID(0),
.C_AXI_ADDR_WIDTH(32),
.C_S_AXI_DATA_WIDTH(32),
.C_M_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_WRITE(0),
.C_AXI_SUPPORTS_READ(1),
.C_FIFO_MODE(0),
.C_S_AXI_ACLK_RATIO(1),
.C_M_AXI_ACLK_RATIO(2),
.C_AXI_IS_ACLK_ASYNC(0),
.C_MAX_SPLIT_BEATS(16),
.C_PACKING_LEVEL(1),
.C_SYNCHRONIZER_STAGE(3)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(32'H00000000),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H1),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(3'H0),
.s_axi_awregion(4'H0),
.s_axi_awqos(4'H0),
.s_axi_awvalid(1'H0),
.s_axi_awready(),
.s_axi_wdata(32'H00000000),
.s_axi_wstrb(4'HF),
.s_axi_wlast(1'H1),
.s_axi_wvalid(1'H0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'H0),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_aclk(1'H0),
.m_axi_aresetn(1'H0),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awvalid(),
.m_axi_awready(1'H0),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wvalid(),
.m_axi_wready(1'H0),
.m_axi_bresp(2'H0),
.m_axi_bvalid(1'H0),
.m_axi_bready(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
`timescale 1ns/1ps
//Reads from accumulate buffer and writes directly to indexed location in DRAM
module data_loader #(
parameter DRAM_BASE_ADDR=31'h40000000,
parameter ADDRESS_WIDTH=31,
parameter DATA_WIDTH=32,
parameter BLOCK_SIZE=64
) (
clk,
reset,
//Accumulator port for external writes
accumulate_fifo_read_slave_readdata,
accumulate_fifo_read_slave_waitrequest,
accumulate_fifo_read_slave_read,
//Accumulator for internal writes
accumulator_local_readdata,
accumulator_local_read,
accumulator_local_waitrequest,
//Write interface to write into DDR memory
control_fixed_location,
control_write_base,
control_write_length,
control_go,
control_done,
//user logic
user_write_buffer,
user_buffer_input_data,
user_buffer_full
);
localparam NUM_STATES=6;
localparam STATE_IDLE=0;
localparam STATE_WAIT_READ=1;
localparam STATE_READ_KEY_VAL=2;
localparam STATE_COMPUTE_ADDRESS=3;
localparam STATE_WRITE_DRAM=4;
localparam STATE_WAIT_DONE=5;
////////////Ports///////////////////
input clk;
input reset;
//Read interface to read from accumulator FIFO
input [63: 0] accumulate_fifo_read_slave_readdata;
input accumulate_fifo_read_slave_waitrequest;
output reg accumulate_fifo_read_slave_read;
//Accumulator for local writes
//Signals for local accumulation
input [63:0] accumulator_local_readdata;
input accumulator_local_waitrequest;
output reg accumulator_local_read;
// control inputs and outputs
output wire control_fixed_location;
output reg [ADDRESS_WIDTH-1:0] control_write_base;
output reg [ADDRESS_WIDTH-1:0] control_write_length;
output reg control_go;
input wire control_done;
// user logic inputs and outputs
output reg user_write_buffer;
output reg [DATA_WIDTH-1:0] user_buffer_input_data;
input wire user_buffer_full;
///////////Registers/////////////////////
reg avalonmm_read_slave_read_next;
reg [ADDRESS_WIDTH-1:0] control_write_base_next;
reg [ADDRESS_WIDTH-1:0] control_write_length_next;
reg control_go_next;
reg user_write_buffer_next;
reg [DATA_WIDTH-1:0] user_buffer_input_data_next;
reg [NUM_STATES-1:0] state, state_next;
reg [DATA_WIDTH-1:0] key, val, key_next, val_next;
reg accumulate_fifo_read_slave_read_next;
reg accum_type, accum_type_next;
reg accumulator_local_read_next;
localparam LOCAL=0; //local update
localparam EXT=1; //external update
assign control_fixed_location=1'b0;
always@(*)
begin
accumulate_fifo_read_slave_read_next = 1'b0;
key_next = key;
val_next = val;
control_write_length_next = control_write_length;
control_write_base_next = control_write_base;
control_go_next = 1'b0;
user_buffer_input_data_next = user_buffer_input_data;
user_write_buffer_next = 1'b0;
state_next = state;
accum_type_next = accum_type;
accumulator_local_read_next = 1'b0;
case(state)
STATE_IDLE: begin
if(!accumulate_fifo_read_slave_waitrequest) begin //if fifo is not empty, start reading first key
state_next = STATE_WAIT_READ;
accumulate_fifo_read_slave_read_next = 1'b1;
accum_type_next = EXT;
end
else if(!accumulator_local_waitrequest) begin
state_next = STATE_WAIT_READ;
accumulator_local_read_next = 1'b1;
accum_type_next = LOCAL;
end
else begin
state_next = STATE_IDLE;
end
end
STATE_WAIT_READ: begin
//Issue a sucessive read to get value (The FIFO must have (key,value) pairs
accumulate_fifo_read_slave_read_next = 1'b0;
accumulator_local_read_next = 1'b0;
state_next = STATE_READ_KEY_VAL;
end
STATE_READ_KEY_VAL: begin
if(accum_type==EXT) begin
key_next = accumulate_fifo_read_slave_readdata[63:32];
val_next = accumulate_fifo_read_slave_readdata[31:0];
end
else begin
key_next = accumulator_local_readdata[63:32];
val_next = accumulator_local_readdata[31:0];
end
state_next = STATE_COMPUTE_ADDRESS;
end
STATE_COMPUTE_ADDRESS: begin
control_write_base_next = (DRAM_BASE_ADDR+(key<<BLOCK_SIZE)); //convert key to an addressable location in DDDR2 DRAM [loc=key*64]
control_write_length_next = 4; //write a 32 bit key
control_go_next = 1'b1;
state_next = STATE_WRITE_DRAM;
end
STATE_WRITE_DRAM: begin
if(!user_buffer_full) begin
user_buffer_input_data_next = val;
user_write_buffer_next = 1'b1;
state_next = STATE_WAIT_DONE;
end
end
STATE_WAIT_DONE: begin
if(control_done)
state_next = STATE_IDLE;
end
endcase
end
always@(posedge clk)
begin
if(reset) begin
state <= STATE_IDLE;
accumulate_fifo_read_slave_read <= 1'b0;
key <= 0;
val <= 0;
control_write_length <= 0;
control_write_base <= 0;
control_go <= 0;
user_buffer_input_data <= 0;
user_write_buffer <= 1'b0;
accum_type <= 0;
accumulator_local_read <= 0;
end
else begin
state <= state_next;
accumulate_fifo_read_slave_read <= accumulate_fifo_read_slave_read_next;
key <= key_next;
val <= val_next;
control_write_length <= control_write_length_next;
control_write_base <= control_write_base_next;
control_go <= control_go_next;
user_buffer_input_data <= user_buffer_input_data_next;
user_write_buffer <= user_write_buffer_next;
accum_type <= accum_type_next;
accumulator_local_read <= accumulator_local_read_next;
end
end
endmodule
|
// parallel to bsg_counter_clear_up
// set occurs before down, and both events can take place in the same cycle.
// we do not output an overflow flag because there is no == that we would
// want to amortize the cost of
`include "bsg_defines.v"
module bsg_counter_set_down #(parameter `BSG_INV_PARAM(width_p), parameter init_val_p='0, parameter set_and_down_exclusive_p=0)
(input clk_i
, input reset_i
, input set_i
, input [width_p-1:0] val_i
, input down_i
, output [width_p-1:0] count_r_o
);
logic [width_p-1:0] ctr_r, ctr_n;
always_ff @(posedge clk_i)
if (reset_i)
ctr_r <= width_p ' (init_val_p);
else
ctr_r <= ctr_n;
if (set_and_down_exclusive_p)
begin: excl
always_comb
begin
ctr_n = ctr_r;
if (set_i)
ctr_n = val_i;
else
if (down_i)
ctr_n = ctr_n - 1;
end
end
else
begin : non_excl
always_comb
begin
ctr_n = ctr_r;
if (set_i)
ctr_n = val_i;
if (down_i)
ctr_n = ctr_n - 1;
end
end
assign count_r_o = ctr_r;
`ifndef SYNTHESIS
always_ff @(negedge clk_i)
begin
if (!reset_i && down_i && (ctr_n == '1))
$display("%m error: counter underflow at time %t", $time);
if (~reset_i & set_and_down_exclusive_p & set_i & down_i)
$display("%m error: set and down non-exclusive at time %t", $time);
end
`endif
endmodule
`BSG_ABSTRACT_MODULE(bsg_counter_set_down)
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: clk_doubler.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.2 Build 156 11/29/2004 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module clk_doubler (
inclk0,
c0);
input inclk0;
output c0;
wire [5:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0)
// synopsys translate_off
,
.activeclock (),
.areset (),
.clkbad (),
.clkena (),
.clkloss (),
.clkswitch (),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena (),
.fbin (),
.locked (),
.pfdena (),
.pllena (),
.scanaclr (),
.scanclk (),
.scandata (),
.scandataout (),
.scandone (),
.scanread (),
.scanwrite (),
.sclkout0 (),
.sclkout1 ()
// synopsys translate_on
);
defparam
altpll_component.clk0_duty_cycle = 50,
altpll_component.lpm_type = "altpll",
altpll_component.clk0_multiply_by = 2,
altpll_component.inclk0_input_frequency = 15625,
altpll_component.clk0_divide_by = 1,
altpll_component.pll_type = "AUTO",
altpll_component.intended_device_family = "Cyclone",
altpll_component.operation_mode = "NORMAL",
altpll_component.compensate_clock = "CLK0",
altpll_component.clk0_phase_shift = "0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_bb.v TRUE FALSE
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_0_core_top_pcie_pipe_lane.v
// Version : 3.0
//
// Description: PIPE per lane module for 7-Series PCIe Block
//
//
//
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module pcie_7x_0_core_top_pcie_pipe_lane #
(
parameter PIPE_PIPELINE_STAGES = 0, // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
parameter TCQ = 1 // synthesis warning solved : parameter declaration becomes local
)
(
output wire [ 1:0] pipe_rx_char_is_k_o , // Pipelined PIPE Rx Char Is K
output wire [15:0] pipe_rx_data_o , // Pipelined PIPE Rx Data
output wire pipe_rx_valid_o , // Pipelined PIPE Rx Data Valid
output wire pipe_rx_chanisaligned_o , // Pipelined PIPE Rx Chan Is Aligned
output wire [ 2:0] pipe_rx_status_o , // Pipelined PIPE Rx Status
output wire pipe_rx_phy_status_o , // Pipelined PIPE Rx Phy Status
output wire pipe_rx_elec_idle_o , // Pipelined PIPE Rx Electrical Idle
input wire pipe_rx_polarity_i , // PIPE Rx Polarity
input wire pipe_tx_compliance_i , // PIPE Tx Compliance
input wire [ 1:0] pipe_tx_char_is_k_i , // PIPE Tx Char Is K
input wire [15:0] pipe_tx_data_i , // PIPE Tx Data
input wire pipe_tx_elec_idle_i , // PIPE Tx Electrical Idle
input wire [ 1:0] pipe_tx_powerdown_i , // PIPE Tx Powerdown
input wire [ 1:0] pipe_rx_char_is_k_i , // PIPE Rx Char Is K
input wire [15:0] pipe_rx_data_i , // PIPE Rx Data
input wire pipe_rx_valid_i , // PIPE Rx Data Valid
input wire pipe_rx_chanisaligned_i , // PIPE Rx Chan Is Aligned
input wire [ 2:0] pipe_rx_status_i , // PIPE Rx Status
input wire pipe_rx_phy_status_i , // PIPE Rx Phy Status
input wire pipe_rx_elec_idle_i , // PIPE Rx Electrical Idle
output wire pipe_rx_polarity_o , // Pipelined PIPE Rx Polarity
output wire pipe_tx_compliance_o , // Pipelined PIPE Tx Compliance
output wire [ 1:0] pipe_tx_char_is_k_o , // Pipelined PIPE Tx Char Is K
output wire [15:0] pipe_tx_data_o , // Pipelined PIPE Tx Data
output wire pipe_tx_elec_idle_o , // Pipelined PIPE Tx Electrical Idle
output wire [ 1:0] pipe_tx_powerdown_o , // Pipelined PIPE Tx Powerdown
input wire pipe_clk , // PIPE Clock
input wire rst_n // Reset
);
//******************************************************************//
// Reality check. //
//******************************************************************//
// parameter TCQ = 1; // clock to out delay model
generate
if (PIPE_PIPELINE_STAGES == 0) begin : pipe_stages_0
assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_i;
assign pipe_rx_data_o = pipe_rx_data_i;
assign pipe_rx_valid_o = pipe_rx_valid_i;
assign pipe_rx_chanisaligned_o = pipe_rx_chanisaligned_i;
assign pipe_rx_status_o = pipe_rx_status_i;
assign pipe_rx_phy_status_o = pipe_rx_phy_status_i;
assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_i;
assign pipe_rx_polarity_o = pipe_rx_polarity_i;
assign pipe_tx_compliance_o = pipe_tx_compliance_i;
assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_i;
assign pipe_tx_data_o = pipe_tx_data_i;
assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_i;
assign pipe_tx_powerdown_o = pipe_tx_powerdown_i;
end // if (PIPE_PIPELINE_STAGES == 0)
else if (PIPE_PIPELINE_STAGES == 1) begin : pipe_stages_1
reg [ 1:0] pipe_rx_char_is_k_q ;
reg [15:0] pipe_rx_data_q ;
reg pipe_rx_valid_q ;
reg pipe_rx_chanisaligned_q ;
reg [ 2:0] pipe_rx_status_q ;
reg pipe_rx_phy_status_q ;
reg pipe_rx_elec_idle_q ;
reg pipe_rx_polarity_q ;
reg pipe_tx_compliance_q ;
reg [ 1:0] pipe_tx_char_is_k_q ;
reg [15:0] pipe_tx_data_q ;
reg pipe_tx_elec_idle_q ;
reg [ 1:0] pipe_tx_powerdown_q ;
always @(posedge pipe_clk) begin
if (rst_n)
begin
pipe_rx_char_is_k_q <= #TCQ 0;
pipe_rx_data_q <= #TCQ 0;
pipe_rx_valid_q <= #TCQ 0;
pipe_rx_chanisaligned_q <= #TCQ 0;
pipe_rx_status_q <= #TCQ 0;
pipe_rx_phy_status_q <= #TCQ 0;
pipe_rx_elec_idle_q <= #TCQ 0;
pipe_rx_polarity_q <= #TCQ 0;
pipe_tx_compliance_q <= #TCQ 0;
pipe_tx_char_is_k_q <= #TCQ 0;
pipe_tx_data_q <= #TCQ 0;
pipe_tx_elec_idle_q <= #TCQ 1'b1;
pipe_tx_powerdown_q <= #TCQ 2'b10;
end
else
begin
pipe_rx_char_is_k_q <= #TCQ pipe_rx_char_is_k_i;
pipe_rx_data_q <= #TCQ pipe_rx_data_i;
pipe_rx_valid_q <= #TCQ pipe_rx_valid_i;
pipe_rx_chanisaligned_q <= #TCQ pipe_rx_chanisaligned_i;
pipe_rx_status_q <= #TCQ pipe_rx_status_i;
pipe_rx_phy_status_q <= #TCQ pipe_rx_phy_status_i;
pipe_rx_elec_idle_q <= #TCQ pipe_rx_elec_idle_i;
pipe_rx_polarity_q <= #TCQ pipe_rx_polarity_i;
pipe_tx_compliance_q <= #TCQ pipe_tx_compliance_i;
pipe_tx_char_is_k_q <= #TCQ pipe_tx_char_is_k_i;
pipe_tx_data_q <= #TCQ pipe_tx_data_i;
pipe_tx_elec_idle_q <= #TCQ pipe_tx_elec_idle_i;
pipe_tx_powerdown_q <= #TCQ pipe_tx_powerdown_i;
end
end
assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_q;
assign pipe_rx_data_o = pipe_rx_data_q;
assign pipe_rx_valid_o = pipe_rx_valid_q;
assign pipe_rx_chanisaligned_o = pipe_rx_chanisaligned_q;
assign pipe_rx_status_o = pipe_rx_status_q;
assign pipe_rx_phy_status_o = pipe_rx_phy_status_q;
assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_q;
assign pipe_rx_polarity_o = pipe_rx_polarity_q;
assign pipe_tx_compliance_o = pipe_tx_compliance_q;
assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_q;
assign pipe_tx_data_o = pipe_tx_data_q;
assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_q;
assign pipe_tx_powerdown_o = pipe_tx_powerdown_q;
end // if (PIPE_PIPELINE_STAGES == 1)
else if (PIPE_PIPELINE_STAGES == 2) begin : pipe_stages_2
reg [ 1:0] pipe_rx_char_is_k_q ;
reg [15:0] pipe_rx_data_q ;
reg pipe_rx_valid_q ;
reg pipe_rx_chanisaligned_q ;
reg [ 2:0] pipe_rx_status_q ;
reg pipe_rx_phy_status_q ;
reg pipe_rx_elec_idle_q ;
reg pipe_rx_polarity_q ;
reg pipe_tx_compliance_q ;
reg [ 1:0] pipe_tx_char_is_k_q ;
reg [15:0] pipe_tx_data_q ;
reg pipe_tx_elec_idle_q ;
reg [ 1:0] pipe_tx_powerdown_q ;
reg [ 1:0] pipe_rx_char_is_k_qq ;
reg [15:0] pipe_rx_data_qq ;
reg pipe_rx_valid_qq ;
reg pipe_rx_chanisaligned_qq;
reg [ 2:0] pipe_rx_status_qq ;
reg pipe_rx_phy_status_qq ;
reg pipe_rx_elec_idle_qq ;
reg pipe_rx_polarity_qq ;
reg pipe_tx_compliance_qq ;
reg [ 1:0] pipe_tx_char_is_k_qq ;
reg [15:0] pipe_tx_data_qq ;
reg pipe_tx_elec_idle_qq ;
reg [ 1:0] pipe_tx_powerdown_qq ;
always @(posedge pipe_clk) begin
if (rst_n)
begin
pipe_rx_char_is_k_q <= #TCQ 0;
pipe_rx_data_q <= #TCQ 0;
pipe_rx_valid_q <= #TCQ 0;
pipe_rx_chanisaligned_q <= #TCQ 0;
pipe_rx_status_q <= #TCQ 0;
pipe_rx_phy_status_q <= #TCQ 0;
pipe_rx_elec_idle_q <= #TCQ 0;
pipe_rx_polarity_q <= #TCQ 0;
pipe_tx_compliance_q <= #TCQ 0;
pipe_tx_char_is_k_q <= #TCQ 0;
pipe_tx_data_q <= #TCQ 0;
pipe_tx_elec_idle_q <= #TCQ 1'b1;
pipe_tx_powerdown_q <= #TCQ 2'b10;
pipe_rx_char_is_k_qq <= #TCQ 0;
pipe_rx_data_qq <= #TCQ 0;
pipe_rx_valid_qq <= #TCQ 0;
pipe_rx_chanisaligned_qq <= #TCQ 0;
pipe_rx_status_qq <= #TCQ 0;
pipe_rx_phy_status_qq <= #TCQ 0;
pipe_rx_elec_idle_qq <= #TCQ 0;
pipe_rx_polarity_qq <= #TCQ 0;
pipe_tx_compliance_qq <= #TCQ 0;
pipe_tx_char_is_k_qq <= #TCQ 0;
pipe_tx_data_qq <= #TCQ 0;
pipe_tx_elec_idle_qq <= #TCQ 1'b1;
pipe_tx_powerdown_qq <= #TCQ 2'b10;
end
else
begin
pipe_rx_char_is_k_q <= #TCQ pipe_rx_char_is_k_i;
pipe_rx_data_q <= #TCQ pipe_rx_data_i;
pipe_rx_valid_q <= #TCQ pipe_rx_valid_i;
pipe_rx_chanisaligned_q <= #TCQ pipe_rx_chanisaligned_i;
pipe_rx_status_q <= #TCQ pipe_rx_status_i;
pipe_rx_phy_status_q <= #TCQ pipe_rx_phy_status_i;
pipe_rx_elec_idle_q <= #TCQ pipe_rx_elec_idle_i;
pipe_rx_polarity_q <= #TCQ pipe_rx_polarity_i;
pipe_tx_compliance_q <= #TCQ pipe_tx_compliance_i;
pipe_tx_char_is_k_q <= #TCQ pipe_tx_char_is_k_i;
pipe_tx_data_q <= #TCQ pipe_tx_data_i;
pipe_tx_elec_idle_q <= #TCQ pipe_tx_elec_idle_i;
pipe_tx_powerdown_q <= #TCQ pipe_tx_powerdown_i;
pipe_rx_char_is_k_qq <= #TCQ pipe_rx_char_is_k_q;
pipe_rx_data_qq <= #TCQ pipe_rx_data_q;
pipe_rx_valid_qq <= #TCQ pipe_rx_valid_q;
pipe_rx_chanisaligned_qq <= #TCQ pipe_rx_chanisaligned_q;
pipe_rx_status_qq <= #TCQ pipe_rx_status_q;
pipe_rx_phy_status_qq <= #TCQ pipe_rx_phy_status_q;
pipe_rx_elec_idle_qq <= #TCQ pipe_rx_elec_idle_q;
pipe_rx_polarity_qq <= #TCQ pipe_rx_polarity_q;
pipe_tx_compliance_qq <= #TCQ pipe_tx_compliance_q;
pipe_tx_char_is_k_qq <= #TCQ pipe_tx_char_is_k_q;
pipe_tx_data_qq <= #TCQ pipe_tx_data_q;
pipe_tx_elec_idle_qq <= #TCQ pipe_tx_elec_idle_q;
pipe_tx_powerdown_qq <= #TCQ pipe_tx_powerdown_q;
end
end
assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_qq;
assign pipe_rx_data_o = pipe_rx_data_qq;
assign pipe_rx_valid_o = pipe_rx_valid_qq;
assign pipe_rx_chanisaligned_o = pipe_rx_chanisaligned_qq;
assign pipe_rx_status_o = pipe_rx_status_qq;
assign pipe_rx_phy_status_o = pipe_rx_phy_status_qq;
assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_qq;
assign pipe_rx_polarity_o = pipe_rx_polarity_qq;
assign pipe_tx_compliance_o = pipe_tx_compliance_qq;
assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_qq;
assign pipe_tx_data_o = pipe_tx_data_qq;
assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_qq;
assign pipe_tx_powerdown_o = pipe_tx_powerdown_qq;
end // if (PIPE_PIPELINE_STAGES == 2)
endgenerate
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// SCFIFO_128x64_withCount for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: Single clock FIFO (128 width, 64 depth) wrapper
// Module Name: SCFIFO_128x64_withCount
// File Name: SCFIFO_128x64_withCount.v
//
// Version: v1.0.0
//
// Description: Standard FIFO, 1 cycle data out latency
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module SCFIFO_128x64_withCount
(
input iClock ,
input iReset ,
input [127:0] iPushData ,
input iPushEnable ,
output oIsFull ,
output [127:0] oPopData ,
input iPopEnable ,
output oIsEmpty ,
output [5:0] oDataCount
);
DPBSCFIFO128x64WC
Inst_DPBSCFIFO128x64WC
(
.clk (iClock ),
.srst (iReset ),
.din (iPushData ),
.wr_en (iPushEnable ),
.full (oIsFull ),
.dout (oPopData ),
.rd_en (iPopEnable ),
.empty (oIsEmpty ),
.data_count (oDataCount )
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MAJ3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__MAJ3_FUNCTIONAL_PP_V
/**
* maj3: 3-input majority vote.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__maj3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire or1_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , B, A );
and and0 (and0_out , or0_out, C );
and and1 (and1_out , A, B );
or or1 (or1_out_X , and1_out, and0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__MAJ3_FUNCTIONAL_PP_V |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2016 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file RAM_B.v when simulating
// the core, RAM_B. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module RAM_B(
clka,
wea,
addra,
dina,
douta
);
input clka;
input [0 : 0] wea;
input [9 : 0] addra;
input [31 : 0] dina;
output [31 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("kintex7"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("RAM_B.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(1024),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("kintex7")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: trellis.vh
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The reset_controller module will safely reset a single stage
// pipeline without using an asychronous reset (bleh). It is intended for use in
// the TX engines, where it will control the output stage of the engine, and
// provide a gracefull end-of-packet reset
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`define S_RC_IDLE 3'b001
`define S_RC_WAIT 3'b010
`define S_RC_ACTIVE 3'b100
`include "trellis.vh"
module reset_controller
#(parameter C_RST_COUNT = 10)
(
input CLK,
input RST_IN,
output DONE_RST,
output WAITING_RESET,
output RST_OUT,
input SIGNAL_RST,
input WAIT_RST,
input NEXT_CYC_RST);
localparam C_CLOG2_RST_COUNT = clog2s(C_RST_COUNT);
localparam C_CEIL2_RST_COUNT = 1 << C_CLOG2_RST_COUNT;
reg [2:0] _rState,rState;
wire [C_CLOG2_RST_COUNT:0] wRstCount;
assign DONE_RST = rState[0];
assign WAITING_RESET = rState[1] & NEXT_CYC_RST;
assign RST_OUT = rState[2];
counter
#(// Parameters
.C_MAX_VALUE (C_CEIL2_RST_COUNT),
.C_SAT_VALUE (C_CEIL2_RST_COUNT),
.C_RST_VALUE (C_CEIL2_RST_COUNT - C_RST_COUNT)
/*AUTOINSTPARAM*/)
rst_counter
(// Outputs
.VALUE (wRstCount),
// Inputs
.ENABLE (1'b1),
.RST_IN (~rState[2] | RST_IN),
/*AUTOINST*/
// Inputs
.CLK (CLK));
always @(posedge CLK) begin
if(RST_IN) begin
rState <= `S_RC_ACTIVE;
end else begin
rState <= _rState;
end
end
always @(*) begin
_rState = rState;
case(rState)
`S_RC_IDLE:begin
if(SIGNAL_RST & WAIT_RST) begin
_rState = `S_RC_WAIT;
end else if(SIGNAL_RST) begin
_rState = `S_RC_ACTIVE;
end
end
`S_RC_WAIT:begin
if(NEXT_CYC_RST) begin
_rState = `S_RC_ACTIVE;
end
end
`S_RC_ACTIVE:begin
if(wRstCount[C_CLOG2_RST_COUNT] & ~SIGNAL_RST) begin
_rState = `S_RC_IDLE;
end
end
default: _rState = rState;
endcase
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_dma_cmd_gen # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
output pcie_cmd_rd_en,
input [33:0] pcie_cmd_rd_data,
input pcie_cmd_empty_n,
output prp_fifo_rd_en,
input [C_PCIE_DATA_WIDTH-1:0] prp_fifo_rd_data,
output prp_fifo_free_en,
output [5:4] prp_fifo_free_len,
input prp_fifo_empty_n,
output pcie_rx_cmd_wr_en,
output [33:0] pcie_rx_cmd_wr_data,
input pcie_rx_cmd_full_n,
output pcie_tx_cmd_wr_en,
output [33:0] pcie_tx_cmd_wr_data,
input pcie_tx_cmd_full_n
);
localparam S_IDLE = 15'b000000000000001;
localparam S_CMD0 = 15'b000000000000010;
localparam S_CMD1 = 15'b000000000000100;
localparam S_CMD2 = 15'b000000000001000;
localparam S_CMD3 = 15'b000000000010000;
localparam S_CHECK_PRP_FIFO = 15'b000000000100000;
localparam S_RD_PRP0 = 15'b000000001000000;
localparam S_RD_PRP1 = 15'b000000010000000;
localparam S_PCIE_PRP = 15'b000000100000000;
localparam S_CHECK_PCIE_CMD_FIFO0 = 15'b000001000000000;
localparam S_PCIE_CMD0 = 15'b000010000000000;
localparam S_PCIE_CMD1 = 15'b000100000000000;
localparam S_CHECK_PCIE_CMD_FIFO1 = 15'b001000000000000;
localparam S_PCIE_CMD2 = 15'b010000000000000;
localparam S_PCIE_CMD3 = 15'b100000000000000;
reg [14:0] cur_state;
reg [14:0] next_state;
reg r_dma_cmd_type;
reg r_dma_cmd_dir;
reg r_2st_valid;
reg r_1st_mrd_need;
reg r_2st_mrd_need;
reg [6:0] r_hcmd_slot_tag;
reg r_pcie_rcb_cross;
reg [12:2] r_1st_4b_len;
reg [12:2] r_2st_4b_len;
reg [C_PCIE_ADDR_WIDTH-1:2] r_hcmd_prp_1;
reg [C_PCIE_ADDR_WIDTH-1:2] r_hcmd_prp_2;
reg [63:2] r_prp_1;
reg [63:2] r_prp_2;
reg r_pcie_cmd_rd_en;
reg r_prp_fifo_rd_en;
reg r_prp_fifo_free_en;
reg r_pcie_rx_cmd_wr_en;
reg r_pcie_tx_cmd_wr_en;
reg [3:0] r_pcie_cmd_wr_data_sel;
reg [33:0] r_pcie_cmd_wr_data;
wire w_pcie_cmd_full_n;
assign pcie_cmd_rd_en = r_pcie_cmd_rd_en;
assign prp_fifo_rd_en = r_prp_fifo_rd_en;
assign prp_fifo_free_en = r_prp_fifo_free_en;
assign prp_fifo_free_len = (r_pcie_rcb_cross == 0) ? 2'b01 : 2'b10;
assign pcie_rx_cmd_wr_en = r_pcie_rx_cmd_wr_en;
assign pcie_rx_cmd_wr_data = r_pcie_cmd_wr_data;
assign pcie_tx_cmd_wr_en = r_pcie_tx_cmd_wr_en;
assign pcie_tx_cmd_wr_data = r_pcie_cmd_wr_data;
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
assign w_pcie_cmd_full_n = (r_dma_cmd_dir == 1'b1) ? pcie_tx_cmd_full_n : pcie_rx_cmd_full_n;
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(pcie_cmd_empty_n == 1'b1)
next_state <= S_CMD0;
else
next_state <= S_IDLE;
end
S_CMD0: begin
next_state <= S_CMD1;
end
S_CMD1: begin
next_state <= S_CMD2;
end
S_CMD2: begin
next_state <= S_CMD3;
end
S_CMD3: begin
if((r_1st_mrd_need | (r_2st_valid & r_2st_mrd_need)) == 1'b1)
next_state <= S_CHECK_PRP_FIFO;
else
next_state <= S_CHECK_PCIE_CMD_FIFO0;
end
S_CHECK_PRP_FIFO: begin
if(prp_fifo_empty_n == 1)
next_state <= S_RD_PRP0;
else
next_state <= S_CHECK_PRP_FIFO;
end
S_RD_PRP0: begin
if(r_pcie_rcb_cross == 1)
next_state <= S_RD_PRP1;
else
next_state <= S_PCIE_PRP;
end
S_RD_PRP1: begin
next_state <= S_PCIE_PRP;
end
S_PCIE_PRP: begin
next_state <= S_CHECK_PCIE_CMD_FIFO0;
end
S_CHECK_PCIE_CMD_FIFO0: begin
if(w_pcie_cmd_full_n == 1'b1)
next_state <= S_PCIE_CMD0;
else
next_state <= S_CHECK_PCIE_CMD_FIFO0;
end
S_PCIE_CMD0: begin
next_state <= S_PCIE_CMD1;
end
S_PCIE_CMD1: begin
if(r_2st_valid == 1'b1)
next_state <= S_CHECK_PCIE_CMD_FIFO1;
else
next_state <= S_IDLE;
end
S_CHECK_PCIE_CMD_FIFO1: begin
if(w_pcie_cmd_full_n == 1'b1)
next_state <= S_PCIE_CMD2;
else
next_state <= S_CHECK_PCIE_CMD_FIFO1;
end
S_PCIE_CMD2: begin
next_state <= S_PCIE_CMD3;
end
S_PCIE_CMD3: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
end
S_CMD0: begin
r_dma_cmd_type <= pcie_cmd_rd_data[11];
r_dma_cmd_dir <= pcie_cmd_rd_data[10];
r_2st_valid <= pcie_cmd_rd_data[9];
r_1st_mrd_need <= pcie_cmd_rd_data[8];
r_2st_mrd_need <= pcie_cmd_rd_data[7];
r_hcmd_slot_tag <= pcie_cmd_rd_data[6:0];
end
S_CMD1: begin
r_pcie_rcb_cross <= pcie_cmd_rd_data[22];
r_1st_4b_len <= pcie_cmd_rd_data[21:11];
r_2st_4b_len <= pcie_cmd_rd_data[10:0];
end
S_CMD2: begin
r_hcmd_prp_1 <= pcie_cmd_rd_data[33:0];
end
S_CMD3: begin
r_hcmd_prp_2 <= {pcie_cmd_rd_data[33:10], 10'b0};
end
S_CHECK_PRP_FIFO: begin
end
S_RD_PRP0: begin
r_prp_1 <= prp_fifo_rd_data[63:2];
r_prp_2 <= prp_fifo_rd_data[127:66];
end
S_RD_PRP1: begin
r_prp_2 <= prp_fifo_rd_data[63:2];
end
S_PCIE_PRP: begin
if(r_1st_mrd_need == 1) begin
r_hcmd_prp_1[C_PCIE_ADDR_WIDTH-1:12] <= r_prp_1[C_PCIE_ADDR_WIDTH-1:12];
r_hcmd_prp_2[C_PCIE_ADDR_WIDTH-1:12] <= r_prp_2[C_PCIE_ADDR_WIDTH-1:12];
end
else begin
r_hcmd_prp_2[C_PCIE_ADDR_WIDTH-1:12] <= r_prp_1[C_PCIE_ADDR_WIDTH-1:12];
end
end
S_CHECK_PCIE_CMD_FIFO0: begin
end
S_PCIE_CMD0: begin
end
S_PCIE_CMD1: begin
end
S_CHECK_PCIE_CMD_FIFO1: begin
end
S_PCIE_CMD2: begin
end
S_PCIE_CMD3: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(r_pcie_cmd_wr_data_sel) // synthesis parallel_case full_case
4'b0001: r_pcie_cmd_wr_data <= {14'b0, r_dma_cmd_type, ~r_2st_valid, r_hcmd_slot_tag, r_1st_4b_len};
4'b0010: r_pcie_cmd_wr_data <= r_hcmd_prp_1;
4'b0100: r_pcie_cmd_wr_data <= {14'b0, r_dma_cmd_type, 1'b1, r_hcmd_slot_tag, r_2st_4b_len};
4'b1000: r_pcie_cmd_wr_data <= {r_hcmd_prp_2[C_PCIE_ADDR_WIDTH-1:12], 10'b0};
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
S_CMD0: begin
r_pcie_cmd_rd_en <= 1;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
S_CMD1: begin
r_pcie_cmd_rd_en <= 1;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
S_CMD2: begin
r_pcie_cmd_rd_en <= 1;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
S_CMD3: begin
r_pcie_cmd_rd_en <= 1;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
S_CHECK_PRP_FIFO: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
S_RD_PRP0: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 1;
r_prp_fifo_free_en <= 1;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
S_RD_PRP1: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 1;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
S_PCIE_PRP: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
S_CHECK_PCIE_CMD_FIFO0: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
S_PCIE_CMD0: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= ~r_dma_cmd_dir;
r_pcie_tx_cmd_wr_en <= r_dma_cmd_dir;
r_pcie_cmd_wr_data_sel <= 4'b0001;
end
S_PCIE_CMD1: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= ~r_dma_cmd_dir;
r_pcie_tx_cmd_wr_en <= r_dma_cmd_dir;
r_pcie_cmd_wr_data_sel <= 4'b0010;
end
S_CHECK_PCIE_CMD_FIFO1: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
S_PCIE_CMD2: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= ~r_dma_cmd_dir;
r_pcie_tx_cmd_wr_en <= r_dma_cmd_dir;
r_pcie_cmd_wr_data_sel <= 4'b0100;
end
S_PCIE_CMD3: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= ~r_dma_cmd_dir;
r_pcie_tx_cmd_wr_en <= r_dma_cmd_dir;
r_pcie_cmd_wr_data_sel <= 4'b1000;
end
default: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
endcase
end
endmodule |
/****************************************************************************
ISA definition file
- The MIPS I ISA has a 6 bit opcode in the upper 6 bits.
- The opcode can also specify a "class". There are two classes:
1. SPECIAL - look in lowest 6 bits to find operation
2. REGIMM - look in [20:16] to find type of branch
****************************************************************************/
/****** OPCODES - bits 31...26 *******/
`define VAL 31
`define WIDTH 32
`define NUMREGS 32
`define LOG2NUMREGS 5
`define PC_WIDTH 30
`define I_DATAWIDTH 32
`define I_ADDRESSWIDTH 14
`define I_SIZE 16384
`define D_ADDRESSWIDTH 32
`define DM_DATAWIDTH 32
`define DM_BYTEENAWIDTH 4
`define DM_ADDRESSWIDTH 16
`define DM_SIZE 16384
`define OP_SPECIAL 6'b000000
`define OP_REGIMM 6'b000001
`define OP_J 6'b000010
`define OP_JAL 6'b000011
`define OP_BEQ 6'b000100
`define OP_BNE 6'b000101
`define OP_BLEZ 6'b000110
`define OP_BGTZ 6'b000111
`define OP_ADDI 6'b001000
`define OP_ADDIU 6'b001001
`define OP_SLTI 6'b001010
`define OP_SLTIU 6'b001011
`define OP_ANDI 6'b001100
`define OP_ORI 6'b001101
`define OP_XORI 6'b001110
`define OP_LUI 6'b001111
`define OP_LB 6'b100000
`define OP_LH 6'b100001
`define OP_LWL 6'b100010
`define OP_LW 6'b100011
`define OP_LBU 6'b100100
`define OP_LHU 6'b100101
`define OP_LWR 6'b100110
`define OP_SB 6'b101100
`define OP_SH 6'b101101
`define OP_SWL 6'b101010
`define OP_SW 6'b101111
`define OP_SWR 6'b101110
/****** FUNCTION CLASS - bits 5...0 *******/
`define FUNC_SLL 6'b000000
`define FUNC_SRL 6'b000010
`define FUNC_SRA 6'b000011
`define FUNC_SLLV 6'b000100
`define FUNC_SRLV 6'b000110
`define FUNC_SRAV 6'b000111
`define FUNC_JR 6'b001110
`define FUNC_JALR 6'b001111
`define FUNC_MFHI 6'b110100
`define FUNC_MTHI 6'b110101
`define FUNC_MFLO 6'b110110
`define FUNC_MTLO 6'b110111
`define FUNC_MULT 6'b111100
`define FUNC_MULTU 6'b111101
`define FUNC_DIV 6'b111110
`define FUNC_DIVU 6'b111111
`define FUNC_ADD 6'b100000
`define FUNC_ADDU 6'b100001
`define FUNC_SUB 6'b100010
`define FUNC_SUBU 6'b100011
`define FUNC_AND 6'b100100
`define FUNC_OR 6'b100101
`define FUNC_XOR 6'b100110
`define FUNC_NOR 6'b100111
`define FUNC_SLT 6'b101010
`define FUNC_SLTU 6'b101011
/****** REGIMM Class - bits 20...16 *******/
`define FUNC_BLTZ 1'b0
`define FUNC_BGEZ 1'b1
`define OP_COP2 6'b010010
`define COP2_FUNC_CFC2 6'b111000
`define COP2_FUNC_CTC2 6'b111010
`define COP2_FUNC_MTC2 6'b111011
//`define FUNC_BLTZAL 5'b10000
//`define FUNC_BGEZAL 5'b10001
/******
* Original REGIMM class, compressed above to save decode logic
`define FUNC_BLTZ 5'b00000
`define FUNC_BGEZ 5'b00001
`define FUNC_BLTZAL 5'b10000
`define FUNC_BGEZAL 5'b10001
*/
module system (
clk,
resetn,
boot_iaddr,
boot_idata,
boot_iwe,
boot_daddr,
boot_ddata,
boot_dwe,
nop7_q
);
/************************* IO Declarations *********************/
input clk;
input resetn;
input [31:0] boot_iaddr;
input [31:0] boot_idata;
input boot_iwe;
input [31:0] boot_daddr;
input [31:0] boot_ddata;
input boot_dwe;
output [31:0] nop7_q;
/*********************** Signal Declarations *******************/
wire branch_mispred;
wire stall_2nd_delayslot;
wire has_delayslot;
wire haz_zeroer0_q_pipereg5_q;
wire haz_zeroer_q_pipereg5_q;
// Datapath signals declarations
wire addersub_result_slt;
wire [ 31 : 0 ] addersub_result;
wire [ 31 : 0 ] reg_file_b_readdataout;
wire [ 31 : 0 ] reg_file_a_readdataout;
wire [ 31 : 0 ] mul_shift_result;
wire [ 31 : 0 ] mul_lo;
wire [ 31 : 0 ] mul_hi;
wire ctrl_mul_stalled;
wire [ 31 : 0 ] ifetch_pc_out;
wire [ 31 : 0 ] ifetch_instr;
wire [ 5 : 0 ] ifetch_opcode;
wire [ 5 : 0 ] ifetch_func;
wire [4 : 0 ] ifetch_rs;
wire [ 4 : 0 ] ifetch_rt;
wire [ 4 : 0 ] ifetch_rd;
wire [ 25 : 0 ] ifetch_instr_index;
wire [ 15 : 0 ] ifetch_offset;
wire [ 4 : 0 ] ifetch_sa;
wire [ 31 : 0 ] ifetch_next_pc;
wire [ 31 : 0 ] data_mem_d_loadresult;
wire ctrl_data_mem_stalled;
wire [ 31 : 0 ] logic_unit_result;
wire [ 31 : 0 ] pcadder_result;
wire [ 31 : 0 ] signext16_out;
wire [ 31 : 0 ] merge26lo_out;
wire [ 31 : 0 ] hi_reg_q;
wire branchresolve_eqz;
wire branchresolve_gez;
wire branchresolve_gtz;
wire branchresolve_lez;
wire branchresolve_ltz;
wire branchresolve_ne;
wire branchresolve_eq;
wire [ 31 : 0 ] lo_reg_q;
wire [ 31 : 0 ] const8_out;
wire [ 31 : 0 ] const9_out;
wire [ 31 : 0 ] const_out;
wire [ 31 : 0 ] pipereg_q;
wire [ 25 : 0 ] pipereg1_q;
wire [ 4 : 0 ] pipereg2_q;
wire [ 31 : 0 ] pipereg5_q;
wire [ 31 : 0 ] pipereg14_q;
wire [ 31 : 0 ] pipereg3_q;
wire [ 31 : 0 ] nop7_q;
wire [ 31 : 0 ] nop_q;
wire [ 31 : 0 ] nop10_q;
wire [ 31 : 0 ] nop6_q;
wire [ 31 : 0 ] zeroer_q;
wire [ 31 : 0 ] zeroer0_q;
wire [ 31 : 0 ] zeroer4_q;
wire [ 31 : 0 ] fakedelay_q;
wire [ 31 : 0 ] mux3to1_ifetch_load_data_out;
wire [ 31 : 0 ] mux2to1_mul_opA_out;
wire mux6to1_ifetch_load_out;
wire [ 4 : 0 ] mux3to1_mul_sa_out;
wire [ 31 : 0 ] mux2to1_addersub_opA_out;
wire [ 31 : 0 ] mux7to1_nop10_d_out;
wire [ 31 : 0 ] mux2to1_pipereg_d_out;
wire [ 31 : 0 ] mux3to1_nop6_d_out;
wire [ 31 : 0 ] mux3to1_zeroer4_d_out;
wire [ 5 : 0 ] pipereg11_q;
wire [ 31 : 0 ] mux2to1_nop_d_out;
wire pipereg16_q;
wire pipereg15_q;
wire [ 31 : 0 ] mux2to1_nop7_d_out;
wire [ 5 : 0 ] pipereg12_q;
wire [ 4 : 0 ] pipereg13_q;
/***************** Control Signals ***************/
//Decoded Opcode signal declarations
reg ctrl_mux2to1_pipereg_d_sel;
reg [ 2 : 0 ] ctrl_mux7to1_nop10_d_sel;
reg ctrl_mux2to1_addersub_opA_sel;
reg [ 2 : 0 ] ctrl_mux6to1_ifetch_load_sel;
reg [ 1 : 0 ] ctrl_mux3to1_nop6_d_sel;
reg ctrl_mux2to1_mul_opA_sel;
reg [ 1 : 0 ] ctrl_mux3to1_mul_sa_sel;
reg [ 1 : 0 ] ctrl_mux3to1_ifetch_load_data_sel;
reg [ 1 : 0 ] ctrl_mux3to1_zeroer4_d_sel;
reg ctrl_zeroer4_en;
reg ctrl_zeroer0_en;
reg ctrl_zeroer_en;
reg [ 3 : 0 ] ctrl_data_mem_op;
reg [ 2 : 0 ] ctrl_addersub_op;
reg ctrl_ifetch_op;
reg [ 2 : 0 ] ctrl_mul_op;
reg [ 1 : 0 ] ctrl_logic_unit_op;
//Enable signal declarations
reg ctrl_hi_reg_en;
reg ctrl_lo_reg_en;
reg ctrl_branchresolve_en;
reg ctrl_reg_file_c_we;
reg ctrl_reg_file_b_en;
reg ctrl_reg_file_a_en;
reg ctrl_data_mem_en;
reg ctrl_ifetch_we;
reg ctrl_ifetch_en;
reg ctrl_mul_start;
//Other Signals
wire squash_stage2;
wire stall_out_stage2;
wire squash_stage1;
wire stall_out_stage1;
wire ctrl_pipereg16_squashn;
wire ctrl_pipereg15_squashn;
wire ctrl_pipereg14_squashn;
wire ctrl_pipereg_squashn;
wire ctrl_pipereg5_squashn;
wire ctrl_pipereg2_squashn;
wire ctrl_pipereg3_squashn;
wire ctrl_pipereg1_squashn;
wire ctrl_pipereg11_squashn;
wire ctrl_pipereg12_squashn;
wire ctrl_pipereg13_squashn;
wire ctrl_pipereg16_resetn;
wire ctrl_pipereg15_resetn;
wire ctrl_pipereg14_resetn;
wire ctrl_pipereg_resetn;
wire ctrl_pipereg5_resetn;
wire ctrl_pipereg2_resetn;
wire ctrl_pipereg3_resetn;
wire ctrl_pipereg1_resetn;
wire ctrl_pipereg11_resetn;
wire ctrl_pipereg12_resetn;
wire ctrl_pipereg13_resetn;
wire ctrl_pipereg16_en;
wire ctrl_pipereg15_en;
wire ctrl_pipereg14_en;
wire ctrl_pipereg_en;
wire ctrl_pipereg5_en;
wire ctrl_pipereg2_en;
wire ctrl_pipereg3_en;
wire ctrl_pipereg1_en;
wire ctrl_pipereg11_en;
wire ctrl_pipereg12_en;
wire ctrl_pipereg13_en;
wire crtl_ifetch_squashn;
/****************************** Control **************************/
//Decode Logic for Opcode and Multiplex Select signals
always@(posedge clk)
begin
// Initialize control opcodes to zero
case (ifetch_opcode)
`OP_ADDI:
begin
ctrl_mux2to1_pipereg_d_sel <= 1'b1;
ctrl_mux3to1_zeroer4_d_sel <= 2'b10;
ctrl_zeroer4_en <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`OP_ADDIU:
begin
ctrl_mux2to1_pipereg_d_sel <= 1'b1;
ctrl_mux3to1_zeroer4_d_sel <= 2'b10;
ctrl_zeroer4_en <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`OP_ANDI:
begin
ctrl_mux2to1_pipereg_d_sel <= 1'b1;
ctrl_mux3to1_zeroer4_d_sel <= 2'b10;
ctrl_zeroer4_en <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`OP_BEQ:
begin
ctrl_mux2to1_pipereg_d_sel <= 1'b1;
ctrl_zeroer0_en <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`OP_BGTZ:
begin
ctrl_mux2to1_pipereg_d_sel <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`OP_BLEZ:
begin
ctrl_mux2to1_pipereg_d_sel <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`OP_BNE:
begin
ctrl_mux2to1_pipereg_d_sel <= 1'b1;
ctrl_zeroer0_en <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`OP_JAL:
begin
ctrl_mux3to1_zeroer4_d_sel <= 2'b10;
ctrl_zeroer4_en <= 1'b1;
end
`OP_LB:
begin
ctrl_mux2to1_pipereg_d_sel <= 1'b1;
ctrl_mux3to1_zeroer4_d_sel <= 2'b10;
ctrl_zeroer4_en <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`OP_LBU:
begin
ctrl_mux2to1_pipereg_d_sel <= 1'b1;
ctrl_mux3to1_zeroer4_d_sel <= 2'b10;
ctrl_zeroer4_en <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`OP_LH:
begin
ctrl_mux2to1_pipereg_d_sel <= 1'b1;
ctrl_mux3to1_zeroer4_d_sel <= 2'b10;
ctrl_zeroer4_en <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`OP_LHU:
begin
ctrl_mux2to1_pipereg_d_sel <= 1'b1;
ctrl_mux3to1_zeroer4_d_sel <= 2'b10;
ctrl_zeroer4_en <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`OP_LUI:
begin
ctrl_mux2to1_pipereg_d_sel <= 1'b1;
ctrl_mux3to1_zeroer4_d_sel <= 2'b10;
ctrl_zeroer4_en <= 1'b1;
end
`OP_LW:
begin
ctrl_mux2to1_pipereg_d_sel <= 1'b1;
ctrl_mux3to1_zeroer4_d_sel <= 2'b10;
ctrl_zeroer4_en <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`OP_ORI:
begin
ctrl_mux2to1_pipereg_d_sel <= 1'b1;
ctrl_mux3to1_zeroer4_d_sel <= 2'b10;
ctrl_zeroer4_en <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`OP_REGIMM:
case (ifetch_rt[0])
`FUNC_BGEZ:
begin
ctrl_mux2to1_pipereg_d_sel <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`FUNC_BLTZ:
begin
ctrl_mux2to1_pipereg_d_sel <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
endcase
`OP_SB:
begin
ctrl_mux2to1_pipereg_d_sel <= 1'b1;
ctrl_zeroer0_en <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`OP_SH:
begin
ctrl_mux2to1_pipereg_d_sel <= 1'b1;
ctrl_zeroer0_en <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`OP_SLTI:
begin
ctrl_mux2to1_pipereg_d_sel <= 1'b1;
ctrl_mux3to1_zeroer4_d_sel <= 2'b10;
ctrl_zeroer4_en <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`OP_SLTIU:
begin
ctrl_mux2to1_pipereg_d_sel <= 1'b1;
ctrl_mux3to1_zeroer4_d_sel <= 2'b10;
ctrl_zeroer4_en <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`OP_SPECIAL:
case (ifetch_func)
`FUNC_ADD:
begin
ctrl_mux3to1_zeroer4_d_sel <= 2'b01;
ctrl_zeroer4_en <= 1'b1;
ctrl_zeroer0_en <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`FUNC_ADDU:
begin
ctrl_mux3to1_zeroer4_d_sel <= 2'b01;
ctrl_zeroer4_en <= 1'b1;
ctrl_zeroer0_en <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`FUNC_AND:
begin
ctrl_mux3to1_zeroer4_d_sel <= 2'b01;
ctrl_zeroer4_en <= 1'b1;
ctrl_zeroer0_en <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`FUNC_JALR:
begin
ctrl_mux3to1_zeroer4_d_sel <= 2'b01;
ctrl_zeroer4_en <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`FUNC_JR:
ctrl_zeroer_en <= 1'b1;
`FUNC_MFHI:
begin
ctrl_mux3to1_zeroer4_d_sel <= 2'b01;
ctrl_zeroer4_en <= 1'b1;
end
`FUNC_MFLO:
begin
ctrl_mux3to1_zeroer4_d_sel <= 2'b01;
ctrl_zeroer4_en <= 1'b1;
end
`FUNC_MULT:
begin
ctrl_zeroer0_en <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`FUNC_MULTU:
begin
ctrl_zeroer0_en <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`FUNC_NOR:
begin
ctrl_mux3to1_zeroer4_d_sel <= 2'b01;
ctrl_zeroer4_en <= 1'b1;
ctrl_zeroer0_en <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`FUNC_OR:
begin
ctrl_mux3to1_zeroer4_d_sel <= 2'b01;
ctrl_zeroer4_en <= 1'b1;
ctrl_zeroer0_en <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`FUNC_SLL:
begin
ctrl_mux3to1_zeroer4_d_sel <= 2'b01;
ctrl_zeroer4_en <= 1'b1;
ctrl_zeroer0_en <= 1'b1;
end
`FUNC_SLLV:
begin
ctrl_mux3to1_zeroer4_d_sel <= 2'b01;
ctrl_zeroer4_en <= 1'b1;
ctrl_zeroer0_en <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`FUNC_SLT:
begin
ctrl_mux3to1_zeroer4_d_sel <= 2'b01;
ctrl_zeroer4_en <= 1'b1;
ctrl_zeroer0_en <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`FUNC_SLTU:
begin
ctrl_mux3to1_zeroer4_d_sel <= 2'b01;
ctrl_zeroer4_en <= 1'b1;
ctrl_zeroer0_en <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`FUNC_SRA:
begin
ctrl_mux3to1_zeroer4_d_sel <= 2'b01;
ctrl_zeroer4_en <= 1'b1;
ctrl_zeroer0_en <= 1'b1;
end
`FUNC_SRAV:
begin
ctrl_mux3to1_zeroer4_d_sel <= 2'b01;
ctrl_zeroer4_en <= 1'b1;
ctrl_zeroer0_en <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`FUNC_SRL:
begin
ctrl_mux3to1_zeroer4_d_sel <= 2'b01;
ctrl_zeroer4_en <= 1'b1;
ctrl_zeroer0_en <= 1'b1;
end
`FUNC_SRLV:
begin
ctrl_mux3to1_zeroer4_d_sel <= 2'b01;
ctrl_zeroer4_en <= 1'b1;
ctrl_zeroer0_en <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`FUNC_SUB:
begin
ctrl_mux3to1_zeroer4_d_sel <= 2'b01;
ctrl_zeroer4_en <= 1'b1;
ctrl_zeroer0_en <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`FUNC_SUBU:
begin
ctrl_mux3to1_zeroer4_d_sel <= 2'b01;
ctrl_zeroer4_en <= 1'b1;
ctrl_zeroer0_en <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`FUNC_XOR:
begin
ctrl_mux3to1_zeroer4_d_sel <= 2'b01;
ctrl_zeroer4_en <= 1'b1;
ctrl_zeroer0_en <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
endcase
`OP_SW:
begin
ctrl_mux2to1_pipereg_d_sel <= 1'b1;
ctrl_zeroer0_en <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
`OP_XORI:
begin
ctrl_mux2to1_pipereg_d_sel <= 1'b1;
ctrl_mux3to1_zeroer4_d_sel <= 2'b10;
ctrl_zeroer4_en <= 1'b1;
ctrl_zeroer_en <= 1'b1;
end
endcase
//Logic for enable signals in Pipe Stage 1
ctrl_reg_file_b_en <= ~stall_out_stage2;
ctrl_reg_file_a_en <= ~stall_out_stage2;
ctrl_ifetch_en <= ~stall_out_stage2;
//Decode Logic for Opcode and Multiplex Select signals
// Initialize control opcodes to zero
case (pipereg11_q)
`OP_ADDI:
begin
ctrl_mux7to1_nop10_d_sel <= 3'b110;
ctrl_mux2to1_addersub_opA_sel <= 1'b0;
ctrl_mux3to1_nop6_d_sel <= 2'b10;
ctrl_addersub_op <= 3'b011;
end
`OP_ADDIU:
begin
ctrl_mux7to1_nop10_d_sel <= 3'b110;
ctrl_mux2to1_addersub_opA_sel <= 1'b0;
ctrl_mux3to1_nop6_d_sel <= 2'b10;
ctrl_addersub_op <= 3'b001;
end
`OP_ANDI:
begin
ctrl_mux7to1_nop10_d_sel <= 3'b100;
ctrl_mux3to1_nop6_d_sel <= 2'b10;
ctrl_logic_unit_op <= 2'b00;
end
`OP_BEQ:
begin
ctrl_mux6to1_ifetch_load_sel <= 3'b101;
ctrl_mux3to1_ifetch_load_data_sel<= 2'b10;
ctrl_ifetch_op <= 1'b0;
end
`OP_BGTZ:
begin
ctrl_mux6to1_ifetch_load_sel <= 3'b000;
ctrl_mux3to1_ifetch_load_data_sel<= 2'b10;
ctrl_ifetch_op <= 1'b0;
end
`OP_BLEZ:
begin
ctrl_mux6to1_ifetch_load_sel <= 3'b011;
ctrl_mux3to1_ifetch_load_data_sel<= 2'b10;
ctrl_ifetch_op <= 1'b0;
end
`OP_BNE:
begin
ctrl_mux6to1_ifetch_load_sel <= 3'b100;
ctrl_mux3to1_ifetch_load_data_sel<= 2'b10;
ctrl_ifetch_op <= 1'b0;
end
`OP_J:
begin
ctrl_mux3to1_ifetch_load_data_sel<= 2'b01;
ctrl_ifetch_op <= 1'b1;
end
`OP_JAL:
begin
ctrl_mux7to1_nop10_d_sel <= 3'b110;
ctrl_mux2to1_addersub_opA_sel <= 1'b1;
ctrl_mux3to1_ifetch_load_data_sel<= 2'b01;
ctrl_addersub_op <= 3'b001;
ctrl_ifetch_op <= 1'b1;
end
`OP_LB:
begin
ctrl_mux7to1_nop10_d_sel <= 3'b010;
ctrl_mux2to1_addersub_opA_sel <= 1'b0;
ctrl_mux3to1_nop6_d_sel <= 2'b10;
ctrl_data_mem_op <= 4'b0111;
ctrl_addersub_op <= 3'b011;
end
`OP_LBU:
begin
ctrl_mux7to1_nop10_d_sel <= 3'b010;
ctrl_mux2to1_addersub_opA_sel <= 1'b0;
ctrl_mux3to1_nop6_d_sel <= 2'b10;
ctrl_data_mem_op <= 4'b0011;
ctrl_addersub_op <= 3'b011;
end
`OP_LH:
begin
ctrl_mux7to1_nop10_d_sel <= 3'b010;
ctrl_mux2to1_addersub_opA_sel <= 1'b0;
ctrl_mux3to1_nop6_d_sel <= 2'b10;
ctrl_data_mem_op <= 4'b0101;
ctrl_addersub_op <= 3'b011;
end
`OP_LHU:
begin
ctrl_mux7to1_nop10_d_sel <= 3'b010;
ctrl_mux2to1_addersub_opA_sel <= 1'b0;
ctrl_mux3to1_nop6_d_sel <= 2'b10;
ctrl_data_mem_op <= 4'b0001;
ctrl_addersub_op <= 3'b011;
end
`OP_LUI:
begin
ctrl_mux7to1_nop10_d_sel <= 3'b011;
ctrl_mux3to1_nop6_d_sel <= 2'b10;
ctrl_mux2to1_mul_opA_sel <= 1'b0;
ctrl_mux3to1_mul_sa_sel <= 2'b01;
ctrl_mul_op <= 3'b000;
end
`OP_LW:
begin
ctrl_mux7to1_nop10_d_sel <= 3'b010;
ctrl_mux2to1_addersub_opA_sel <= 1'b0;
ctrl_mux3to1_nop6_d_sel <= 2'b10;
ctrl_data_mem_op <= 4'b0000;
ctrl_addersub_op <= 3'b011;
end
`OP_ORI:
begin
ctrl_mux7to1_nop10_d_sel <= 3'b100;
ctrl_mux3to1_nop6_d_sel <= 2'b10;
ctrl_logic_unit_op <= 2'b01;
end
`OP_REGIMM:
case (pipereg13_q[0])
`FUNC_BGEZ:
begin
ctrl_mux6to1_ifetch_load_sel <= 3'b001;
ctrl_mux3to1_ifetch_load_data_sel<= 2'b10;
ctrl_ifetch_op <= 1'b0;
end
`FUNC_BLTZ:
begin
ctrl_mux6to1_ifetch_load_sel <= 3'b010;
ctrl_mux3to1_ifetch_load_data_sel<= 2'b10;
ctrl_ifetch_op <= 1'b0;
end
endcase
`OP_SB:
begin
ctrl_mux2to1_addersub_opA_sel <= 1'b0;
ctrl_mux3to1_nop6_d_sel <= 2'b10;
ctrl_data_mem_op <= 4'b0011;
ctrl_addersub_op <= 3'b011;
end
`OP_SH:
begin
ctrl_mux2to1_addersub_opA_sel <= 1'b0;
ctrl_mux3to1_nop6_d_sel <= 2'b10;
ctrl_data_mem_op <= 4'b1001;
ctrl_addersub_op <= 3'b011;
end
`OP_SLTI:
begin
ctrl_mux7to1_nop10_d_sel <= 3'b101;
ctrl_mux2to1_addersub_opA_sel <= 1'b0;
ctrl_mux3to1_nop6_d_sel <= 2'b10;
ctrl_addersub_op <= 3'b101;
end
`OP_SLTIU:
begin
ctrl_mux7to1_nop10_d_sel <= 3'b101;
ctrl_mux2to1_addersub_opA_sel <= 1'b0;
ctrl_mux3to1_nop6_d_sel <= 2'b10;
ctrl_addersub_op <= 3'b100;
end
`OP_SPECIAL:
case (pipereg12_q)
`FUNC_ADD:
begin
ctrl_mux7to1_nop10_d_sel <= 3'b110;
ctrl_mux2to1_addersub_opA_sel <= 1'b0;
ctrl_mux3to1_nop6_d_sel <= 2'b01;
ctrl_addersub_op <= 3'b011;
end
`FUNC_ADDU:
begin
ctrl_mux7to1_nop10_d_sel <= 3'b110;
ctrl_mux2to1_addersub_opA_sel <= 1'b0;
ctrl_mux3to1_nop6_d_sel <= 2'b01;
ctrl_addersub_op <= 3'b001;
end
`FUNC_AND:
begin
ctrl_mux7to1_nop10_d_sel <= 3'b100;
ctrl_mux3to1_nop6_d_sel <= 2'b01;
ctrl_logic_unit_op <= 2'b00;
end
`FUNC_JALR:
begin
ctrl_mux7to1_nop10_d_sel <= 3'b110;
ctrl_mux2to1_addersub_opA_sel <= 1'b1;
ctrl_mux3to1_ifetch_load_data_sel<= 2'b00;
ctrl_addersub_op <= 3'b001;
ctrl_ifetch_op <= 1'b1;
end
`FUNC_JR:
begin
ctrl_mux3to1_ifetch_load_data_sel<= 2'b00;
ctrl_ifetch_op <= 1'b1;
end
`FUNC_MFHI:
ctrl_mux7to1_nop10_d_sel <= 3'b001;
`FUNC_MFLO:
ctrl_mux7to1_nop10_d_sel <= 3'b000;
`FUNC_MULT:
begin
ctrl_mux2to1_mul_opA_sel <= 1'b1;
ctrl_mul_op <= 3'b110;
end
`FUNC_MULTU:
begin
ctrl_mux2to1_mul_opA_sel <= 1'b1;
ctrl_mul_op <= 3'b100;
end
`FUNC_NOR:
begin
ctrl_mux7to1_nop10_d_sel <= 3'b100;
ctrl_mux3to1_nop6_d_sel <= 2'b01;
ctrl_logic_unit_op <= 2'b11;
end
`FUNC_OR:
begin
ctrl_mux7to1_nop10_d_sel <= 3'b100;
ctrl_mux3to1_nop6_d_sel <= 2'b01;
ctrl_logic_unit_op <= 2'b01;
end
`FUNC_SLL:
begin
ctrl_mux7to1_nop10_d_sel <= 3'b011;
ctrl_mux3to1_nop6_d_sel <= 2'b01;
ctrl_mux2to1_mul_opA_sel <= 1'b0;
ctrl_mux3to1_mul_sa_sel <= 2'b00;
ctrl_mul_op <= 3'b000;
end
`FUNC_SLLV:
begin
ctrl_mux7to1_nop10_d_sel <= 3'b011;
ctrl_mux3to1_nop6_d_sel <= 2'b01;
ctrl_mux2to1_mul_opA_sel <= 1'b0;
ctrl_mux3to1_mul_sa_sel <= 2'b10;
ctrl_mul_op <= 3'b000;
end
`FUNC_SLT:
begin
ctrl_mux7to1_nop10_d_sel <= 3'b101;
ctrl_mux2to1_addersub_opA_sel <= 1'b0;
ctrl_mux3to1_nop6_d_sel <= 2'b01;
ctrl_addersub_op <= 3'b110;
end
`FUNC_SLTU:
begin
ctrl_mux7to1_nop10_d_sel <= 3'b101;
ctrl_mux2to1_addersub_opA_sel <= 1'b0;
ctrl_mux3to1_nop6_d_sel <= 2'b01;
ctrl_addersub_op <= 3'b100;
end
`FUNC_SRA:
begin
ctrl_mux7to1_nop10_d_sel <= 3'b011;
ctrl_mux3to1_nop6_d_sel <= 2'b01;
ctrl_mux2to1_mul_opA_sel <= 1'b0;
ctrl_mux3to1_mul_sa_sel <= 2'b00;
ctrl_mul_op <= 3'b011;
end
`FUNC_SRAV:
begin
ctrl_mux7to1_nop10_d_sel <= 3'b011;
ctrl_mux3to1_nop6_d_sel <= 2'b01;
ctrl_mux2to1_mul_opA_sel <= 1'b0;
ctrl_mux3to1_mul_sa_sel <= 2'b10;
ctrl_mul_op <= 3'b011;
end
`FUNC_SRL:
begin
ctrl_mux7to1_nop10_d_sel <= 3'b011;
ctrl_mux3to1_nop6_d_sel <= 2'b01;
ctrl_mux2to1_mul_opA_sel <= 1'b0;
ctrl_mux3to1_mul_sa_sel <= 2'b00;
ctrl_mul_op <= 3'b001;
end
`FUNC_SRLV:
begin
ctrl_mux7to1_nop10_d_sel <= 3'b011;
ctrl_mux3to1_nop6_d_sel <= 2'b01;
ctrl_mux2to1_mul_opA_sel <= 1'b0;
ctrl_mux3to1_mul_sa_sel <= 2'b10;
ctrl_mul_op <= 3'b001;
end
`FUNC_SUB:
begin
ctrl_mux7to1_nop10_d_sel <= 3'b110;
ctrl_mux2to1_addersub_opA_sel <= 1'b0;
ctrl_mux3to1_nop6_d_sel <= 2'b01;
ctrl_addersub_op <= 3'b000;
end
`FUNC_SUBU:
begin
ctrl_mux7to1_nop10_d_sel <= 3'b110;
ctrl_mux2to1_addersub_opA_sel <= 1'b0;
ctrl_mux3to1_nop6_d_sel <= 2'b01;
ctrl_addersub_op <= 3'b010;
end
`FUNC_XOR:
begin
ctrl_mux7to1_nop10_d_sel <= 3'b100;
ctrl_mux3to1_nop6_d_sel <= 2'b01;
ctrl_logic_unit_op <= 2'b10;
end
endcase
`OP_SW:
begin
ctrl_mux2to1_addersub_opA_sel <= 1'b0;
ctrl_mux3to1_nop6_d_sel <= 2'b10;
ctrl_data_mem_op <= 4'b1000;
ctrl_addersub_op <= 3'b011;
end
`OP_XORI:
begin
ctrl_mux7to1_nop10_d_sel <= 3'b100;
ctrl_mux3to1_nop6_d_sel <= 2'b10;
ctrl_logic_unit_op <= 2'b10;
end
endcase
//Logic for enable signals in Pipe Stage 2
case (pipereg11_q)
`OP_ADDI:
ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
`OP_ADDIU:
ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
`OP_ANDI:
ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
`OP_BEQ:
begin
ctrl_branchresolve_en <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
ctrl_ifetch_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
end
`OP_BGTZ:
begin
ctrl_branchresolve_en <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
ctrl_ifetch_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
end
`OP_BLEZ:
begin
ctrl_branchresolve_en <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
ctrl_ifetch_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
end
`OP_BNE:
begin
ctrl_branchresolve_en <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
ctrl_ifetch_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
end
`OP_J:
ctrl_ifetch_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
`OP_JAL:
begin
ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
ctrl_ifetch_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
end
`OP_LB:
begin
ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
ctrl_data_mem_en <=1'b1;
end
`OP_LBU:
begin
ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
ctrl_data_mem_en <=1'b1;
end
`OP_LH:
begin
ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
ctrl_data_mem_en <=1'b1;
end
`OP_LHU:
begin
ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
ctrl_data_mem_en <=1'b1;
end
`OP_LUI:
begin
ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
ctrl_mul_start <=1'b1;
end
`OP_LW:
begin
ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
ctrl_data_mem_en <=1'b1;
end
`OP_ORI:
ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
`OP_REGIMM:
case (pipereg13_q[0])
`FUNC_BGEZ:
begin
ctrl_branchresolve_en <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
ctrl_ifetch_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
end
`FUNC_BLTZ:
begin
ctrl_branchresolve_en <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
ctrl_ifetch_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
end
endcase
`OP_SB:
ctrl_data_mem_en <=1'b1;
`OP_SH:
ctrl_data_mem_en <=1'b1;
`OP_SLTI:
ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
`OP_SLTIU:
ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
`OP_SPECIAL:
case (pipereg12_q)
`FUNC_ADD:
ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
`FUNC_ADDU:
ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
`FUNC_AND:
ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
`FUNC_JALR:
begin
ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
ctrl_ifetch_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
end
`FUNC_JR:
ctrl_ifetch_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
`FUNC_MFHI:
ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
`FUNC_MFLO:
ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
`FUNC_MULT:
begin
ctrl_hi_reg_en <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
ctrl_lo_reg_en <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
ctrl_mul_start <=1'b1;
end
`FUNC_MULTU:
begin
ctrl_hi_reg_en <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
ctrl_lo_reg_en <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
ctrl_mul_start <=1'b1;
end
`FUNC_NOR:
ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
`FUNC_OR:
ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
`FUNC_SLL:
begin
ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
ctrl_mul_start <=1'b1;
end
`FUNC_SLLV:
begin
ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
ctrl_mul_start <=1'b1;
end
`FUNC_SLT:
ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
`FUNC_SLTU:
ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
`FUNC_SRA:
begin
ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
ctrl_mul_start <=1'b1;
end
`FUNC_SRAV:
begin
ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
ctrl_mul_start <=1'b1;
end
`FUNC_SRL:
begin
ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
ctrl_mul_start <=1'b1;
end
`FUNC_SRLV:
begin
ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
ctrl_mul_start <=1'b1;
end
`FUNC_SUB:
ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
`FUNC_SUBU:
ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
`FUNC_XOR:
ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
endcase
`OP_SW:
ctrl_data_mem_en <=1'b1;
`OP_XORI:
ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled;
endcase
end
/********* Stall Network & PipeReg Control ********/
assign stall_out_stage1 = stall_out_stage2;
assign ctrl_pipereg13_en = ~stall_out_stage1;
assign ctrl_pipereg12_en = ~stall_out_stage1;
assign ctrl_pipereg11_en = ~stall_out_stage1;
assign ctrl_pipereg1_en = ~stall_out_stage1;
assign ctrl_pipereg3_en = ~stall_out_stage1;
assign ctrl_pipereg2_en = ~stall_out_stage1;
assign ctrl_pipereg5_en = ~stall_out_stage1;
assign ctrl_pipereg_en = ~stall_out_stage1;
assign ctrl_pipereg14_en = ~stall_out_stage1;
assign ctrl_pipereg15_en = ~stall_out_stage1;
assign ctrl_pipereg16_en = ~stall_out_stage1;
assign stall_out_stage2 = ctrl_data_mem_stalled|ctrl_mul_stalled;
assign branch_mispred = (((ctrl_ifetch_op==1) || (ctrl_ifetch_op==0 && mux6to1_ifetch_load_out)) & ctrl_ifetch_we);
assign stall_2nd_delayslot = &has_delayslot;
assign has_delayslot = 0;
assign squash_stage1 = ((stall_out_stage1&~stall_out_stage2))|~resetn;
assign ctrl_pipereg13_resetn = ~squash_stage1;
assign ctrl_pipereg12_resetn = ~squash_stage1;
assign ctrl_pipereg11_resetn = ~squash_stage1;
assign ctrl_pipereg1_resetn = ~squash_stage1;
assign ctrl_pipereg3_resetn = ~squash_stage1;
assign ctrl_pipereg2_resetn = ~squash_stage1;
assign ctrl_pipereg5_resetn = ~squash_stage1;
assign ctrl_pipereg_resetn = ~squash_stage1;
assign ctrl_pipereg14_resetn = ~squash_stage1;
assign ctrl_pipereg15_resetn = ~squash_stage1;
assign ctrl_pipereg16_resetn = ~squash_stage1;
assign ctrl_pipereg16_squashn = 1'b1;
assign ctrl_pipereg15_squashn = 1'b1;
assign ctrl_pipereg14_squashn = 1'b1;
assign ctrl_pipereg_squashn = 1'b1;
assign ctrl_pipereg5_squashn = 1'b1;
assign ctrl_pipereg2_squashn = 1'b1;
assign ctrl_pipereg3_squashn = 1'b1;
assign ctrl_pipereg1_squashn = 1'b1;
assign ctrl_pipereg11_squashn = 1'b1;
assign ctrl_pipereg12_squashn = 1'b1;
assign ctrl_pipereg13_squashn = 1'b1;
assign ctrl_ifetch_squashn = 1'b1;
wire ctrl_ifetch_squashn;
assign squash_stage2 = ((stall_out_stage2))|~resetn;
/****************************** Datapath **************************/
/******************** Hazard Detection Logic ***********************/
assign haz_zeroer0_q_pipereg5_q = (zeroer0_q==pipereg5_q) && (|zeroer0_q);
assign haz_zeroer_q_pipereg5_q = (zeroer_q==pipereg5_q) && (|zeroer_q);
assign const8_out = 32'b00000000000000000000000000000000;
assign const9_out = 32'b00000000000000000000000000010000;
assign const_out = 32'b00000000000000000000000000011111;
/*************** DATAPATH COMPONENTS **************/
addersub addersub (
.opB(nop6_q),
.opA(mux2to1_addersub_opA_out),
.op(ctrl_addersub_op),
.result_slt(addersub_result_slt),
.result(addersub_result));
// defparam
// addersub.WIDTH=32;
reg_file reg_file (
.clk(clk),
.resetn(resetn),
.c_writedatain(nop10_q),
.c_reg(pipereg5_q),
.b_reg(zeroer0_q),
.a_reg(zeroer_q),
.c_we(ctrl_reg_file_c_we),
.b_en(ctrl_reg_file_b_en),
.a_en(ctrl_reg_file_a_en),
.b_readdataout(reg_file_b_readdataout),
.a_readdataout(reg_file_a_readdataout));
mul mul (
.clk(clk),
.resetn(resetn),
.sa(mux3to1_mul_sa_out),
.dst(pipereg5_q),
.opB(nop7_q),
.opA(mux2to1_mul_opA_out),
.op(ctrl_mul_op),
.start(ctrl_mul_start),
.stalled(ctrl_mul_stalled),
.shift_result(mul_shift_result),
.lo(mul_lo),
.hi(mul_hi));
// defparam
// mul.WIDTH=32;
ifetch ifetch (
.clk(clk),
.resetn(resetn),
.boot_iaddr(boot_iaddr),
.boot_idata(boot_idata),
.boot_iwe(boot_iwe),
.load(mux6to1_ifetch_load_out),
.load_data(mux3to1_ifetch_load_data_out),
.op(ctrl_ifetch_op),
.we(ctrl_ifetch_we),
.squashn(ctrl_ifetch_squashn),
.en(ctrl_ifetch_en),
.pc_out(ifetch_pc_out),
.instr(ifetch_instr),
.opcode(ifetch_opcode),
.func(ifetch_func),
.rs(ifetch_rs),
.rt(ifetch_rt),
.rd(ifetch_rd),
.instr_index(ifetch_instr_index),
.offset(ifetch_offset),
.sa(ifetch_sa),
.next_pc(ifetch_next_pc));
data_mem data_mem (
.clk(clk),
.resetn(resetn),
.stalled(ctrl_data_mem_stalled),
.d_writedata(nop7_q),
.d_address(addersub_result),
.boot_daddr(boot_daddr),
.boot_ddata(boot_ddata),
.boot_dwe(boot_dwe),
.op(ctrl_data_mem_op),
.d_loadresult(data_mem_d_loadresult));
logic_unit logic_unit (
.opB(nop6_q),
.opA(nop_q),
.op(ctrl_logic_unit_op),
.result(logic_unit_result));
// defparam
// logic_unit.WIDTH=32;
pcadder pcadder (
.offset(pipereg_q),
.pc(pipereg3_q),
.result(pcadder_result));
signext16 signext16 (
.in(ifetch_offset),
.out(signext16_out));
merge26lo merge26lo (
.in2(pipereg1_q),
.in1(pipereg3_q),
.out(merge26lo_out));
hi_reg hi_reg (
.clk(clk),
.resetn(resetn),
.d(mul_hi),
.en(ctrl_hi_reg_en),
.q(hi_reg_q));
// defparam
// hi_reg.WIDTH=32;
branchresolve branchresolve (
.rt(nop7_q),
.rs(nop_q),
.en(ctrl_branchresolve_en),
.eqz(branchresolve_eqz),
.gez(branchresolve_gez),
.gtz(branchresolve_gtz),
.lez(branchresolve_lez),
.ltz(branchresolve_ltz),
.ne(branchresolve_ne),
.eq(branchresolve_eq));
// defparam
// branchresolve.WIDTH=32;
lo_reg lo_reg (
.clk(clk),
.resetn(resetn),
.d(mul_lo),
.en(ctrl_lo_reg_en),
.q(lo_reg_q));
// defparam
// lo_reg.WIDTH=32;
/*
const const8 (
.out(const8_out));
// defparam
// const8.WIDTH=32,
//const8.VAL=0;
const const9 (
.out(const9_out));
// defparam
// const9.WIDTH=32,
//const9.VAL=16;
const const (
.out(const_out));
// defparam
// const.WIDTH=32,
//const.VAL=31;
*/
pipereg_w32 pipereg (
.clk(clk),
.resetn(ctrl_pipereg_resetn),
.d(mux2to1_pipereg_d_out),
.squashn(ctrl_pipereg_squashn),
.en(ctrl_pipereg_en),
.q(pipereg_q));
// defparam
// pipereg.WIDTH=32;
pipereg_w26 pipereg1 (
.clk(clk),
.resetn(ctrl_pipereg1_resetn),
.d(ifetch_instr_index),
.squashn(ctrl_pipereg1_squashn),
.en(ctrl_pipereg1_en),
.q(pipereg1_q));
// defparam
// pipereg1.WIDTH=26;
pipereg_w5 pipereg2 (
.clk(clk),
.resetn(ctrl_pipereg2_resetn),
.d(ifetch_sa),
.squashn(ctrl_pipereg2_squashn),
.en(ctrl_pipereg2_en),
.q(pipereg2_q));
// defparam
// pipereg2.WIDTH=5;
pipereg_w5 pipereg5 (
.clk(clk),
.resetn(ctrl_pipereg5_resetn),
.d(zeroer4_q),
.squashn(ctrl_pipereg5_squashn),
.en(ctrl_pipereg5_en),
.q(pipereg5_q));
//defparam
//pipereg5.WIDTH=5;
pipereg_w32 pipereg14 (
.clk(clk),
.resetn(ctrl_pipereg14_resetn),
.d(nop10_q),
.squashn(ctrl_pipereg14_squashn),
.en(ctrl_pipereg14_en),
.q(pipereg14_q));
//defparam
// pipereg14.WIDTH=32;
pipereg_w32 pipereg3 (
.clk(clk),
.resetn(ctrl_pipereg3_resetn),
.d(ifetch_pc_out),
.squashn(ctrl_pipereg3_squashn),
.en(ctrl_pipereg3_en),
.q(pipereg3_q));
// defparam
// pipereg3.WIDTH=32;
nop nop7 (
.d(mux2to1_nop7_d_out),
.q(nop7_q));
//defparam
// nop7.WIDTH=32;
nop nop (
.d(mux2to1_nop_d_out),
.q(nop_q));
//defparam
// nop.WIDTH=32;
nop nop10 (
.d(mux7to1_nop10_d_out),
.q(nop10_q));
//defparam
// nop10.WIDTH=32;
nop nop6 (
.d(mux3to1_nop6_d_out),
.q(nop6_q));
//defparam
// nop6.WIDTH=32;
zeroer zeroer (
.d(ifetch_rs),
.en(ctrl_zeroer_en),
.q(zeroer_q));
//defparam
// zeroer.WIDTH=5;
zeroer zeroer0 (
.d(ifetch_rt),
.en(ctrl_zeroer0_en),
.q(zeroer0_q));
//defparam
// zeroer0.WIDTH=5;
zeroer zeroer4 (
.d(mux3to1_zeroer4_d_out),
.en(ctrl_zeroer4_en),
.q(zeroer4_q));
//defparam
// zeroer4.WIDTH=5;
fakedelay fakedelay (
.clk(clk),
.d(ifetch_pc_out),
.q(fakedelay_q));
//defparam
// fakedelay.WIDTH=32;
// Multiplexor mux3to1_ifetch_load_data instantiation
assign mux3to1_ifetch_load_data_out =
(ctrl_mux3to1_ifetch_load_data_sel==2) ? pcadder_result :
(ctrl_mux3to1_ifetch_load_data_sel==1) ? merge26lo_out :
nop_q;
// Multiplexor mux2to1_mul_opA instantiation
assign mux2to1_mul_opA_out =
(ctrl_mux2to1_mul_opA_sel==1) ? nop_q :
nop6_q;
// Multiplexor mux6to1_ifetch_load instantiation
assign mux6to1_ifetch_load_out =
(ctrl_mux6to1_ifetch_load_sel==3'd5) ? branchresolve_eq :
(ctrl_mux6to1_ifetch_load_sel==3'd4) ? branchresolve_ne :
(ctrl_mux6to1_ifetch_load_sel==3'd3) ? branchresolve_lez :
(ctrl_mux6to1_ifetch_load_sel==3'd2) ? branchresolve_ltz :
(ctrl_mux6to1_ifetch_load_sel==3'd1) ? branchresolve_gez :
branchresolve_gtz;
// Multiplexor mux3to1_mul_sa instantiation
assign mux3to1_mul_sa_out =
(ctrl_mux3to1_mul_sa_sel==2) ? nop_q :
(ctrl_mux3to1_mul_sa_sel==1) ? const9_out :
pipereg2_q;
// Multiplexor mux2to1_addersub_opA instantiation
assign mux2to1_addersub_opA_out =
(ctrl_mux2to1_addersub_opA_sel==1) ? fakedelay_q :
nop_q;
// Multiplexor mux7to1_nop10_d instantiation
assign mux7to1_nop10_d_out =
(ctrl_mux7to1_nop10_d_sel==3'd6) ? addersub_result :
(ctrl_mux7to1_nop10_d_sel==3'd5) ? addersub_result_slt :
(ctrl_mux7to1_nop10_d_sel==3'd4) ? logic_unit_result :
(ctrl_mux7to1_nop10_d_sel==3'd3) ? mul_shift_result :
(ctrl_mux7to1_nop10_d_sel==3'd2) ? data_mem_d_loadresult :
(ctrl_mux7to1_nop10_d_sel==3'd1) ? hi_reg_q :
lo_reg_q;
// Multiplexor mux2to1_pipereg_d instantiation
assign mux2to1_pipereg_d_out =
(ctrl_mux2to1_pipereg_d_sel==1) ? ifetch_offset :
signext16_out;
// Multiplexor mux3to1_nop6_d instantiation
assign mux3to1_nop6_d_out =
(ctrl_mux3to1_nop6_d_sel==2) ? pipereg_q :
(ctrl_mux3to1_nop6_d_sel==1) ? nop7_q :
const8_out;
// Multiplexor mux3to1_zeroer4_d instantiation
assign mux3to1_zeroer4_d_out =
(ctrl_mux3to1_zeroer4_d_sel==2) ? ifetch_rt :
(ctrl_mux3to1_zeroer4_d_sel==1) ? ifetch_rd :
const_out;
pipereg_w6 pipereg11 (
.clk(clk),
.resetn(ctrl_pipereg11_resetn),
.d(ifetch_opcode),
.squashn(ctrl_pipereg11_squashn),
.en(ctrl_pipereg11_en),
.q(pipereg11_q));
//defparam
// pipereg11.WIDTH=6;
// Multiplexor mux2to1_nop_d instantiation
assign mux2to1_nop_d_out =
(pipereg15_q==1) ? pipereg14_q :
reg_file_a_readdataout;
pipereg_w1 pipereg16 (
.clk(clk),
.resetn(ctrl_pipereg16_resetn),
.d(haz_zeroer0_q_pipereg5_q),
.squashn(ctrl_pipereg16_squashn),
.en(ctrl_pipereg16_en),
.q(pipereg16_q));
//defparam
// pipereg16.WIDTH=1;
pipereg_w1 pipereg15 (
.clk(clk),
.resetn(ctrl_pipereg15_resetn),
.d(haz_zeroer_q_pipereg5_q),
.squashn(ctrl_pipereg15_squashn),
.en(ctrl_pipereg15_en),
.q(pipereg15_q));
//defparam
// pipereg15.WIDTH=1;
// Multiplexor mux2to1_nop7_d instantiation
assign mux2to1_nop7_d_out =
(pipereg16_q==1) ? pipereg14_q :
reg_file_b_readdataout;
pipereg_w6 pipereg12 (
.clk(clk),
.resetn(ctrl_pipereg12_resetn),
.d(ifetch_func),
.squashn(ctrl_pipereg12_squashn),
.en(ctrl_pipereg12_en),
.q(pipereg12_q));
//defparam
// pipereg12.WIDTH=6;
pipereg_w5 pipereg13 (
.clk(clk),
.resetn(ctrl_pipereg13_resetn),
.d(ifetch_rt),
.squashn(ctrl_pipereg13_squashn),
.en(ctrl_pipereg13_en),
.q(pipereg13_q));
//defparam
// pipereg13.WIDTH=5;
endmodule
/****************************************************************************
AddSub unit
- Should perform ADD, ADDU, SUBU, SUB, SLT, SLTU
is_slt signext addsub
op[2] op[1] op[0] | Operation
0 0 0 0 SUBU
2 0 1 0 SUB
1 0 0 1 ADDU
3 0 1 1 ADD
4 1 0 0 SLTU
6 1 1 0 SLT
****************************************************************************/
module addersub (
opB, opA,
op,
result_slt,
result );
//parameter WIDTH=32;
//`DEFINE WIDTH 32
input [31:0] opA;
input [31:0] opB;
//input carry_in;
input [2:0] op;
output result_slt;
output [31:0] result;
wire [32:0] sum;
wire addsub;
wire useless;
assign useless = op[1] & op[2];
assign addsub=op[0];
wire not_addsub;
assign not_addsub = ~addsub;
assign result=sum[31:0];
assign result_slt=sum[32];
dummy_add_sub adder32bit (opA,opB,not_addsub,sum);
// This is an LPM from Altera, replacing with a dummy one for now
/*
lpm_add_sub adder_inst(
.dataa({signext&opA[WIDTH-1],opA}),
.datab({signext&opB[WIDTH-1],opB}),
.cin(~addsub),
.add_sub(addsub),
.result(sum)
// synopsys translate_off
,
.cout (),
.clken (),
.clock (),
.overflow (),
.aclr ()
// synopsys translate_on
);
//defparam
// adder_inst.lpm_width=WIDTH+1,
// adder_inst.lpm_representation="SIGNED";
*/
endmodule
module dummy_add_sub (dataa,datab,cin,result);
//this is goign to be UUUUGGGGGGLLLYYYYY
//probably going to do some serious timing violations
// but i'm sure it will be interesting for the packing problem
input [31:0] dataa;
input [31:0] datab;
input cin;
output [32:0] result;
//
wire [31:0] carry_from;
wire [31:0] sum;
full_adder bit0 (cin,dataa[0],datab[0],sum[0],carry_from [0]);
full_adder bit1 (carry_from [0],dataa[1],datab[1],sum[1],carry_from [1]);
full_adder bit2 (carry_from [1],dataa[2],datab[2],sum[2],carry_from [2]);
full_adder bit3 (carry_from [2],dataa[3],datab[3],sum[3],carry_from [3]);
full_adder bit4 (carry_from [3],dataa[4],datab[4],sum[4],carry_from [4]);
full_adder bit5 (carry_from [4],dataa[5],datab[5],sum[5],carry_from [5]);
full_adder bit6 (carry_from [5],dataa[6],datab[6],sum[6],carry_from [6]);
full_adder bit7 (carry_from [6],dataa[7],datab[7],sum[7],carry_from [7]);
full_adder bit8 (carry_from [7],dataa[8],datab[8],sum[8],carry_from [8]);
full_adder bit9 (carry_from [8],dataa[9],datab[9],sum[9],carry_from [9]);
full_adder bit10 (carry_from [9],dataa[10],datab[10],sum[10],carry_from [10]);
full_adder bit11 (carry_from [10],dataa[11],datab[11],sum[11],carry_from [11]);
full_adder bit12 (carry_from [11],dataa[12],datab[12],sum[12],carry_from [12]);
full_adder bit13 (carry_from [12],dataa[13],datab[13],sum[13],carry_from [13]);
full_adder bit14 (carry_from [13],dataa[14],datab[14],sum[14],carry_from [14]);
full_adder bit15 (carry_from [14],dataa[15],datab[15],sum[15],carry_from [15]);
full_adder bit16 (carry_from [15],dataa[16],datab[16],sum[16],carry_from [16]);
full_adder bit17 (carry_from [16],dataa[17],datab[17],sum[17],carry_from [17]);
full_adder bit18 (carry_from [17],dataa[18],datab[18],sum[18],carry_from [18]);
full_adder bit19 (carry_from [18],dataa[19],datab[19],sum[19],carry_from [19]);
full_adder bit20 (carry_from [19],dataa[20],datab[20],sum[20],carry_from [20]);
full_adder bit21 (carry_from [20],dataa[21],datab[21],sum[21],carry_from [21]);
full_adder bit22 (carry_from [21],dataa[22],datab[22],sum[22],carry_from [22]);
full_adder bit23 (carry_from [22],dataa[23],datab[23],sum[23],carry_from [23]);
full_adder bit24 (carry_from [23],dataa[24],datab[24],sum[24],carry_from [24]);
full_adder bit25 (carry_from [24],dataa[25],datab[25],sum[25],carry_from [25]);
full_adder bit26 (carry_from [25],dataa[26],datab[26],sum[26],carry_from [26]);
full_adder bit27 (carry_from [26],dataa[27],datab[27],sum[27],carry_from [27]);
full_adder bit28 (carry_from [27],dataa[28],datab[28],sum[28],carry_from [28]);
full_adder bit29 (carry_from [28],dataa[29],datab[29],sum[29],carry_from [29]);
full_adder bit30 (carry_from [29],dataa[30],datab[30],sum[30],carry_from [30]);
full_adder bit31 (carry_from [30],dataa[31],datab[31],sum[31],carry_from [31]);
assign result [31:0] = sum;
assign result [32] = carry_from [31];
endmodule
module full_adder (cin,x,y,s,cout);
input cin;
input x;
input y;
output s;
output cout;
assign s = x^y^cin;
assign cout = (x&y) | (x & cin) | (y&cin);
endmodule
/****************************************************************************
Register File
- Has two read ports (a and b) and one write port (c)
- sel chooses the register to be read/written
****************************************************************************/
module reg_file(clk,resetn, c_writedatain,
c_reg,b_reg,a_reg,c_we, b_en, a_en,
b_readdataout, a_readdataout);
//parameter WIDTH=32;
//parameter NUMREGS=32;
//parameter LOG2NUMREGS=5;
input clk;
input resetn;
input a_en;
input b_en;
input [31:0] c_writedatain;
input c_we;
input [31:0] a_reg;
input [31:0] b_reg;
input [31:0] c_reg;
output [31:0] a_readdataout;
output [31:0] b_readdataout;
reg [31:0] a_readdataout;
reg [31:0] b_readdataout;
wire [31:0] a_readdataout_temp;
wire [31:0] b_readdataout_temp;
assign b_readdataout = b_readdataout_temp;
assign a_readdataout = a_readdataout_temp;
/*
altsyncram reg_file1(
.wren_a (c_we&(|c_reg)),
.clock0 (clk),
.clock1 (clk),
.clocken1 (a_en),
.address_a (c_reg[LOG2NUMREGS-1:0]),
.address_b (a_reg[LOG2NUMREGS-1:0]),
.data_a (c_writedatain),
.q_b (a_readdataout)
// synopsys translate_off
,
.aclr0 (1'b0),
.aclr1 (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.data_b (32'b11111111),
.wren_b (1'b0),
.rden_b(1'b1),
.q_a (),
.clocken0 (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0)
// synopsys translate_on
);
defparam
reg_file1.operation_mode = "DUAL_PORT",
reg_file1.width_a = WIDTH,
reg_file1.widthad_a = LOG2NUMREGS,
reg_file1.numwords_a = NUMREGS,
reg_file1.width_b = WIDTH,
reg_file1.widthad_b = LOG2NUMREGS,
reg_file1.numwords_b = NUMREGS,
reg_file1.lpm_type = "altsyncram",
reg_file1.width_byteena_a = 1,
reg_file1.outdata_reg_b = "UNREGISTERED",
reg_file1.indata_aclr_a = "NONE",
reg_file1.wrcontrol_aclr_a = "NONE",
reg_file1.address_aclr_a = "NONE",
reg_file1.rdcontrol_reg_b = "CLOCK1",
reg_file1.address_reg_b = "CLOCK1",
reg_file1.address_aclr_b = "NONE",
reg_file1.outdata_aclr_b = "NONE",
reg_file1.read_during_write_mode_mixed_ports = "OLD_DATA",
reg_file1.ram_block_type = "AUTO",
reg_file1.intended_device_family = "Stratix";
//Reg file duplicated to avoid contention between 2 read
//and 1 write
*/
wire [31:0] dummy_out;
wire [31:0] constone;
assign constone = 32'b11111111111111111111111111111111;
wire wren1;
assign wren1 = (c_we & (|c_reg));
dual_port_ram regfile1_replace (
.clk (clk),
.we1(wren1),
.we2(1'b0),
.data1(c_writedatain),
.data2(constone),
.out1(a_readdataout_temp),
.out2(dummy_out),
.addr1(c_reg),
.addr2(a_reg));
//MORE MEMORY
/*
altsyncram reg_file2(
.wren_a (c_we&(|c_reg)),
.clock0 (clk),
.clock1 (clk),
.clocken1 (b_en),
.address_a (c_reg[LOG2NUMREGS-1:0]),
.address_b (b_reg[LOG2NUMREGS-1:0]),
.data_a (c_writedatain),
.q_b (b_readdataout)
// synopsys translate_off
,
.aclr0 (1'b0),
.aclr1 (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.data_b (32'b11111111),
.rden_b(1'b1),
.wren_b (1'b0),
.q_a (),
.clocken0 (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0)
// synopsys translate_on
);
defparam
reg_file2.operation_mode = "DUAL_PORT",
reg_file2.width_a = WIDTH,
reg_file2.widthad_a = LOG2NUMREGS,
reg_file2.numwords_a = NUMREGS,
reg_file2.width_b = WIDTH,
reg_file2.widthad_b = LOG2NUMREGS,
reg_file2.numwords_b = NUMREGS,
reg_file2.lpm_type = "altsyncram",
reg_file2.width_byteena_a = 1,
reg_file2.outdata_reg_b = "UNREGISTERED",
reg_file2.indata_aclr_a = "NONE",
reg_file2.wrcontrol_aclr_a = "NONE",
reg_file2.address_aclr_a = "NONE",
reg_file2.rdcontrol_reg_b = "CLOCK1",
reg_file2.address_reg_b = "CLOCK1",
reg_file2.address_aclr_b = "NONE",
reg_file2.outdata_aclr_b = "NONE",
reg_file2.read_during_write_mode_mixed_ports = "OLD_DATA",
reg_file2.ram_block_type = "AUTO",
reg_file2.intended_device_family = "Stratix";
*/
wire [31:0] dummywire;
dual_port_ram regfile2_replace(
.clk (clk),
.we1(wren1),
.we2(1'b0),
.data1(c_writedatain),
.data2(constone),
.out1(b_readdataout_temp),
.out2(dummywire),
.addr1(c_reg),
.addr2(b_reg));
wire useless_inputs;
assign useless_inputs = resetn & b_en & a_en;
endmodule
/****************************************************************************
MUL/DIV unit
Operation table
op sign dir
4 1 0 x | MULTU
6 1 1 x | MULT
0 0 0 0 | ShiftLeft
1 0 0 1 | ShiftRightLogic
3 0 1 1 | ShiftRightArith
****************************************************************************/
module mul(clk, resetn, sa, dst, opB,opA,
op, start, stalled,
shift_result,
lo,hi);
//parameter 32=32;
input clk;
input resetn;
input start;
output stalled;
input [4:0] dst;
input [31:0] opA;
input [31:0] opB;
input [4:0] sa;
input [2:0] op;
output [31:0] shift_result;
output [31:0] hi;
output [31:0] lo;
/********* Control Signals *********/
wire is_signed;
wire dir;
wire is_mul;
assign is_mul=op[2]; // selects between opB and the computed shift amount
assign is_signed=op[1];
assign dir=op[0]; // selects between 2^sa and 2^(32-sa) for right shift
/********* Circuit Body *********/
wire dum;
wire dum2;
wire dum3;
wire [32:0] opB_mux_out;
wire [4:0] left_sa; // Amount of left shift required for both left/right
reg [32:0] decoded_sa;
wire [31:0] result;
//assign opB_mux_out= (is_mul) ? {is_signed&opB[31],opB} : decoded_sa;
assign opB_mux_out = opB;
dummy_mult fake_mult_one (opA,opB_mux_out, clk, resetn, result);
assign hi = result [15:8];
assign lo = result [7:0];
// Cannot support this now
/*
lpm_mult lpm_mult_component (
.dataa ({is_signed&opA[31],opA}),
.datab (opB_mux_out),
.sum(),
.clock(clk),
.clken(),
.aclr(~resetn),
.result ({dum2,dum,hi,lo}));
defparam
lpm_mult_component.lpm_32a = 32+1,
lpm_mult_component.lpm_32b = 32+1,
lpm_mult_component.lpm_32p = 2*32+2,
lpm_mult_component.lpm_32s = 1,
lpm_mult_component.lpm_pipeline = 1,
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_representation = "SIGNED",
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=6";
*/
assign shift_result= (dir & |sa) ? hi : lo;
// 1 cycle stall state machine
wire or_dst;
wire start_and_ismul;
wire request;
assign or_dst = |dst;
assign start_and_ismul = start & is_mul;
assign request = (or_dst & start & ~is_mul) | (start_and_ismul);
onecyclestall staller(request,clk,resetn,stalled);
endmodule
module dummy_mult (opA,opB_mux_out, clk, resetn, result);
input [31:0] opA;
input [31:0] opB_mux_out;
input clk;
input resetn;
output[31:0] result;
reg [31:0] result;
always @ (posedge clk)
begin
if (resetn)
result <= 32'b00000000000000000000000000000000;
else
//multiplier by star symbol
//though this is probably supposed to be signed
result <= opA * opB_mux_out;
end
endmodule
/****************************************************************************
Fetch Unit
op
0 Conditional PC write
1 UnConditional PC write
****************************************************************************/
module ifetch(clk,resetn,
boot_iaddr,
boot_idata,
boot_iwe,
load,
load_data,
op,
we,
squashn,
en,
pc_out,
instr,
opcode,
func,
rs,
rt,
rd,
instr_index,
offset,
sa,
next_pc);
//parameter PC_WIDTH=30;
//parameter I_DATAWIDTH=32;
//parameter I_ADDRESSWIDTH=14;
//parameter I_SIZE=16384;
input [31:0] boot_iaddr;
input [31:0] boot_idata;
input boot_iwe;
input clk;
input resetn;
input en; // PC increment enable
input we; // PC write enable
input squashn;// squash fetch
input op; // determines if conditional or unconditional branch
input load;
input [`I_DATAWIDTH-1:0] load_data;
output [`I_DATAWIDTH-1:0] pc_out; // output pc + 1 shifted left 2 bits
output [`PC_WIDTH-1:0] next_pc;
output [31:26] opcode;
output [25:21] rs;
output [20:16] rt;
output [15:11] rd;
output [10:6] sa;
output [15:0] offset;
output [25:0] instr_index;
output [5:0] func;
output [`I_DATAWIDTH-1:0] instr;
wire [`PC_WIDTH-1:0] pc_plus_1;
wire [`PC_WIDTH-1:0] pc;
assign pc_plus_1 = pc;
wire ctrl_load;
wire out_of_sync;
assign ctrl_load=(load&~op|op);
wire notresetn;
assign notresetn = ~resetn;
wire count_en;
assign count_en = (~ctrl_load)&~out_of_sync;
wire counter_en;
assign counter_en = en | we;
wire [32:2] reg_load_data;
assign reg_load_data = load_data [31:2];
wire reg_d;
wire reg_en;
assign reg_d = (we&(~en)&(squashn));
assign reg_en = en|we;
register_1bit sync_pcs_up( reg_d, clk, resetn,reg_en, out_of_sync);
wire wren1;
assign wren1 = 1'b0;
wire [31:0] next_pc_wire;
assign next_pc_wire = next_pc [13:0];
dual_port_ram imem_replace(
.clk (clk),
.we1(wren1),
.we2(boot_iwe),
.data1(load_data),
.data2(boot_idata),
.out1(instr),
.out2(dummyout2),
.addr1(next_pc_wire),
.addr2(boot_iaddr));
wire [31:0]dummyout2;
wire [31:0] dummyin1;
assign dummyin1 = 32'b00000000000000000000000000000000;
wire dummy;
dummy_counter pc_reg ((reg_load_data),(clk),(counter_en),(count_en),(notresetn),(ctrl_load),(pc));
//assign {dummy,pc_plus_1} = pc + {1'b0,~out_of_sync};
//assign pc_out={pc_plus_1,2'b0};
assign pc_out [31:2] = pc_plus_1;
assign pc_out [1:0] = 2'b00;
assign next_pc = ctrl_load ? load_data[31:2] : pc_plus_1;
//assign next_pc = pc_plus_1;
assign opcode=instr[31:26];
assign rs=instr[25:21];
assign rt=instr[20:16];
assign rd=instr[15:11];
assign sa=instr[10:6];
assign offset=instr[15:0];
assign instr_index=instr[25:0];
assign func=instr[5:0];
endmodule
module dummy_counter (data,clock,clk_en,cnt_en,aset,sload,q);
input [31:2] data;
input clock;
input clk_en;
input cnt_en;
input aset;
input sload;
output [`PC_WIDTH-1:0] q;
reg [`PC_WIDTH-1:0] q;
wire [2:0] sload_cnten_aset;
assign sload_cnten_aset [0] = sload;
assign sload_cnten_aset [1] = cnt_en;
assign sload_cnten_aset [2] = aset;
always @ (posedge clock)
//if (cnt_en == 1)
//q <= q+1;
begin
case (sload_cnten_aset)
3'b000:
q <= q;
3'b011:
q <= q;
3'b110:
q <= q;
3'b111:
q <= q;
3'b101:
q <= q;
3'b100:
q <= data;
3'b010:
begin
if (clk_en)
q <= q+1;
else
q <= q;
end
3'b001:
q <= 29'b00000000000000000000000000000;
default:
q <= q;
endcase
end
/*case (sload)
1'b1:
begin
q = data;
end
default:
begin
case (cnt_en)
1'b1:
begin
q = q+1;
end
default:
begin
case (aset)
1'b1:
begin
q = 0;
end
default:
begin
q = q;
end
endcase
end
endcase
end
endcase
*/
endmodule
module data_mem( clk, resetn, stalled,
d_writedata,
d_address,
boot_daddr, boot_ddata, boot_dwe,
op,
d_loadresult);
input clk;
input resetn;
output stalled;
input [31:0] boot_daddr;
input [31:0] boot_ddata;
input boot_dwe;
input [`D_ADDRESSWIDTH-1:0] d_address;
input [3:0] op;
input [31:0] d_writedata;
output [`DM_DATAWIDTH-1:0] d_loadresult;
wire [`DM_BYTEENAWIDTH-1:0] d_byteena;
wire [`DM_DATAWIDTH-1:0] d_readdatain;
wire [`DM_DATAWIDTH-1:0] d_writedatamem;
wire d_write;
wire [1:0] d_address_latched;
assign d_write=op[3];
wire [1:0] d_small_adr;
assign d_small_adr = d_address[1:0];
wire one;
assign one = 1'b1;
wire [1:0] d_adr_one_zero;
assign d_adr_one_zero = d_address [1:0];
wire [1:0] opsize;
assign opsize = op[1:0];
wire opext;
assign opext = op[2];
store_data_translator sdtrans_inst(
.write_data(d_writedata),
.d_address(d_adr_one_zero),
.store_size(op[1:0]),
.d_byteena(d_byteena),
.d_writedataout(d_writedatamem));
load_data_translator ldtrans_inst(
.d_readdatain(d_readdatain),
.d_loadresult(d_loadresult));
wire dnot_address;
assign dnot_address = ~d_address[31];
wire will_be_wren1;
assign will_be_wren1 = d_write&(dnot_address);
wire [31:0] dont_care;
wire [31:0] memaddr_wrd;
assign memaddr_wrd = d_address[`DM_ADDRESSWIDTH:2];
dual_port_ram dmem_replace(
.clk (clk),
.we1(will_be_wren1),
.we2(boot_dwe),
.data1(d_writedatamem),
.data2(boot_ddata),
.out1(d_readdatain),
.out2 (dont_care),
.addr1(memaddr_wrd),
.addr2(boot_daddr));
// 1 cycle stall state machine
wire en_and_not_d_write;
assign en_and_not_d_write = ~d_write;
onecyclestall staller(en_and_not_d_write,clk,resetn,stalled);
wire useless_inputs;
assign useless_inputs = |d_address;
endmodule
//temp in here
/****************************************************************************
Store data translator
- moves store data to appropriate byte/halfword
- interfaces with altera blockrams
****************************************************************************/
module store_data_translator(
write_data, // data in least significant position
d_address,
store_size,
d_byteena,
d_writedataout); // shifted data to coincide with address
//parameter WIDTH=32;
input [31:0] write_data;
input [1:0] d_address;
input [1:0] store_size;
output [3:0] d_byteena;
output [31:0] d_writedataout;
reg [3:0] d_byteena;
reg [31:0] d_writedataout;
always @(write_data or d_address or store_size)
begin
case (store_size)
2'b11:
case(d_address[1:0])
2'b00:
begin
d_byteena=4'b1000;
d_writedataout={write_data[7:0],24'b0};
end
2'b01:
begin
d_byteena=4'b0100;
d_writedataout={8'b0,write_data[7:0],16'b0};
end
2'b10:
begin
d_byteena=4'b0010;
d_writedataout={16'b0,write_data[7:0],8'b0};
end
default:
begin
d_byteena=4'b0001;
d_writedataout={24'b0,write_data[7:0]};
end
endcase
2'b01:
case(d_address[1])
1'b0:
begin
d_byteena=4'b1100;
d_writedataout={write_data[15:0],16'b0};
end
default:
begin
d_byteena=4'b0011;
d_writedataout={16'b0,write_data[15:0]};
end
endcase
default:
begin
d_byteena=4'b1111;
d_writedataout=write_data;
end
endcase
end
endmodule
/****************************************************************************
Load data translator
- moves read data to appropriate byte/halfword and zero/sign extends
****************************************************************************/
module load_data_translator(
d_readdatain,
d_loadresult);
//parameter WIDTH=32;
input [31:0] d_readdatain;
output [31:0] d_loadresult;
wire d_adr_one;
assign d_adr_one = d_address [1];
reg [31:0] d_loadresult;
reg sign;
wire [1:0] d_address;
assign d_address [1:0] =d_readdatain [25:24];
//assume always full-word-access
always @(d_readdatain or d_address )
begin
d_loadresult[31:0]=d_readdatain[31:0];
end
/*
Odin II REFUSES TO ACKNOWLEDGE THAT SIGN EXTENDING IS NOT A COMBINATIONAL LOOP
always @(d_readdatain or d_address or load_size or load_sign_ext)
begin
case (load_size)
2'b11:
begin
case (d_address)
2'b00:
begin
d_loadresult[7:0]=d_readdatain[31:24];
sign = d_readdatain[31];
end
2'b01:
begin
d_loadresult[7:0]=d_readdatain[23:16];
sign = d_readdatain[23];
end
2'b10:
begin
d_loadresult[7:0]=d_readdatain[15:8];
sign = d_readdatain[15];
end
default:
begin
d_loadresult[7:0]=d_readdatain[7:0];
sign = d_readdatain[7];
end
endcase
// peter milankov note: do this by hand
// odin II does not support multiple concatenation
//d_loadresult[31:8]={24{load_sign_ext&d_loadresult[7]}};
d_loadresult[31]= load_sign_ext&sign;
d_loadresult[30]= load_sign_ext&sign;
d_loadresult[29]= load_sign_ext&sign;
d_loadresult[28]= load_sign_ext&sign;
d_loadresult[27]= load_sign_ext&sign;
d_loadresult[26]= load_sign_ext&sign;
d_loadresult[25]= load_sign_ext&sign;
d_loadresult[24]= load_sign_ext&sign;
d_loadresult[23]= load_sign_ext&sign;
d_loadresult[22]= load_sign_ext&sign;
d_loadresult[21]= load_sign_ext&sign;
d_loadresult[20]= load_sign_ext&sign;
d_loadresult[19]= load_sign_ext&sign;
d_loadresult[18]= load_sign_ext&sign;
d_loadresult[17]= load_sign_ext&sign;
d_loadresult[16]= load_sign_ext&sign;
d_loadresult[15]= load_sign_ext&sign;
d_loadresult[14]= load_sign_ext&sign;
d_loadresult[13]= load_sign_ext&sign;
d_loadresult[12]= load_sign_ext&sign;
d_loadresult[11]= load_sign_ext&sign;
d_loadresult[10]= load_sign_ext&sign;
d_loadresult[9]= load_sign_ext&sign;
d_loadresult[8]= load_sign_ext&sign;
end
2'b01:
begin
case (d_adr_one)
1'b0:
begin
d_loadresult[15:0]=d_readdatain[31:16];
sign = d_readdatain[31];
end
default:
begin
d_loadresult[15:0]=d_readdatain[15:0];
sign = d_readdatain[15];
end
endcase
// peter milankov note sign extend is concat, do by hand
//d_loadresult[31:16]={16{load_sign_ext&d_loadresult[15]}};
d_loadresult[31]= load_sign_ext&sign;
d_loadresult[30]= load_sign_ext&sign;
d_loadresult[29]= load_sign_ext&sign;
d_loadresult[28]= load_sign_ext&sign;
d_loadresult[27]= load_sign_ext&sign;
d_loadresult[26]= load_sign_ext&sign;
d_loadresult[25]= load_sign_ext&sign;
d_loadresult[24]= load_sign_ext&sign;
d_loadresult[23]= load_sign_ext&sign;
d_loadresult[22]= load_sign_ext&sign;
d_loadresult[21]= load_sign_ext&sign;
d_loadresult[20]= load_sign_ext&sign;
d_loadresult[19]= load_sign_ext&sign;
d_loadresult[18]= load_sign_ext&sign;
d_loadresult[17]= load_sign_ext&sign;
d_loadresult[16]= load_sign_ext&sign;
end
default:
d_loadresult[31:0]=d_readdatain[31:0];
endcase
end
*/
endmodule
/****************************************************************************
logic unit
- note ALU must be able to increment PC for JAL type instructions
Operation Table
op
0 AND
1 OR
2 XOR
3 NOR
****************************************************************************/
module logic_unit (
opB, opA,
op,
result);
//parameter WIDTH=32;
input [31:0] opA;
input [31:0] opB;
input [1:0] op;
output [31:0] result;
reg [31:0] logic_result;
always@(opA or opB or op )
case(op)
2'b00:
logic_result=opA&opB;
2'b01:
logic_result=opA|opB;
2'b10:
logic_result=opA^opB;
2'b11:
logic_result=~(opA|opB);
endcase
assign result=logic_result;
endmodule
module pcadder(offset,pc, result);
//parameter PC_WIDTH=32;
input [31:0] pc;
input [31:0] offset;
output [31:0] result;
wire dum;
wire useless_inputs;
assign useless_inputs = |offset;
assign {dum,result} = pc + {offset[31:0],2'b0};
endmodule
module signext16 ( in, out);
input [15:0] in;
output [31:0] out;
assign out [30]= in[15];
assign out [31]= in[15];
assign out [29]= in[15];
assign out [28]= in[15];
assign out [27]= in[15];
assign out [26]= in[15];
assign out [25]= in[15];
assign out [24]= in[15];
assign out [23]= in[15];
assign out [22]= in[15];
assign out [21]= in[15];
assign out [20]= in[15];
assign out [19]= in[15];
assign out [18]= in[15];
assign out [17]= in[15];
assign out [16]= in[15];
assign out [15:0] = in [15:0];
endmodule
module merge26lo(in2, in1, out);
input [31:0] in1;
input [25:0] in2;
output [31:0] out;
//assign out[31:0]={in1[31:28],in2[25:0],2'b0};
assign out [31:28] = in1 [31:28];
assign out [27:2] = in2 [25:0];
assign out [1:0] = 2'b00;
wire useless_inputs;
assign useless_inputs = |in1 & |in2;
endmodule
/****************************************************************************
Generic Register
****************************************************************************/
module lo_reg(clk,resetn,d,en,q);
//parameter WIDTH=32;
input clk;
input resetn;
input en;
input [31:0] d;
output [31:0] q;
reg [31:0] q;
always @(posedge clk )
begin
if (resetn==0)
q<=0;
else if (en==1)
q<=d;
end
endmodule
/****************************************************************************
Generic Register
****************************************************************************/
module hi_reg(clk,resetn,d,en,q);
//parameter WIDTH=32;
input clk;
input resetn;
input en;
input [31:0] d;
output [31:0] q;
reg [31:0] q;
always @(posedge clk ) //used to be asynchronous reset
begin
if (resetn==0)
q<=0;
else if (en==1)
q<=d;
end
endmodule
/****************************************************************************
Generic Register
****************************************************************************/
//`define WIDTH 32
/*
module register(d,clk,resetn,en,q);
//parameter WIDTH=32;
input clk;
input resetn;
input en;
input [31:0] d;
output [31:0] q;
reg [31:0] q;
always @(posedge clk )
begin
if (resetn==0)
q<=0;
else if (en==1)
q<=d;
end
endmodule
*/
module register_1bit(d,clk,resetn,en,q);
//parameter WIDTH=32;
input clk;
input resetn;
input en;
input d;
output q;
reg q;
always @(posedge clk )
begin
if (resetn==0)
q<=0;
else if (en==1)
q<=d;
end
endmodule
/****************************************************************************
Generic Register - synchronous reset
****************************************************************************/
/*
module register_sync(d,clk,resetn,en,q);
//parameter WIDTH=32;
input clk;
input resetn;
input en;
input [31:0] d;
output [31:0] q;
reg [31:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn==0)
q<=0;
else if (en==1)
q<=d;
end
endmodule
*/
/****************************************************************************
Generic Pipelined Register
- Special component, components starting with "pipereg" have
their enables treated independently of instructrions that use them.
- They are enabled whenever the stage is active and not stalled
****************************************************************************/
/*
module pipereg(clk,resetn,d,squashn,en,q);
//parameter WIDTH=32;
//`define WIDTH 32
input clk;
input resetn;
input en;
input squashn;
input [31:0] d;
output [31:0] q;
reg [31:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn==0 || squashn==0)
q<=0;
else if (en==1)
q<=d;
end
endmodule
*/
module pipereg_w32(clk,resetn,d,squashn,en,q);
//parameter WIDTH=32;
//`define WIDTH 32
input clk;
input resetn;
input en;
input squashn;
input [31:0] d;
output [31:0] q;
reg [31:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn==0 || squashn==0)
q<=0;
else if (en==1)
q<=d;
end
endmodule
module pipereg_w26(clk,resetn,d,squashn,en,q);
//parameter WIDTH=32;
//`define WIDTH 32
input clk;
input resetn;
input en;
input squashn;
input [25:0] d;
output [25:0] q;
reg [25:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn==0 || squashn==0)
q<=0;
else if (en==1)
q<=d;
end
endmodule
module pipereg_w6(clk,resetn,d,squashn,en,q);
//parameter WIDTH=32;
//`define WIDTH 32
input clk;
input resetn;
input en;
input squashn;
input [31:0] d;
output [31:0] q;
reg [31:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn==0 || squashn==0)
q<=0;
else if (en==1)
begin
q[5:0]<=d;
q[31:6] <= 0;
end
end
endmodule
module pipereg_w5(clk,resetn,d,squashn,en,q);
//parameter WIDTH=32;
//`define WIDTH 32
input clk;
input resetn;
input en;
input squashn;
input [31:0] d;
output [31:0] q;
reg [31:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn==0 || squashn==0)
q<=0;
else if (en==1)
begin
q[4:0]<=d;
q[31:5] <= 0;
end
end
endmodule
module pipereg_w1(clk,resetn,d,squashn,en,q);
//parameter WIDTH=32;
//`define WIDTH 32
input clk;
input resetn;
input en;
input squashn;
input d;
output q;
reg q;
always @(posedge clk) //synchronous reset
begin
if (resetn==0 || squashn==0)
q<=0;
else if (en==1)
q<=d;
end
endmodule
/****************************************************************************
Generic Pipelined Register 2 -OLD: If not enabled, queues squash
- This piperegister stalls the reset signal as well
*/
/*
module pipereg_full(d,clk,resetn,squashn,en,q);
//parameter WIDTH=32;
input clk;
input resetn;
input en;
input squashn;
input [31:0] d;
output [31:0] q;
reg [31:0] q;
reg squash_save;
always @(posedge clk) //synchronous reset
begin
if (resetn==0 || (squashn==0 && en==1) || (squash_save&en))
q<=0;
else if (en==1)
q<=d;
end
always @(posedge clk)
begin
if (resetn==1 && squashn==0 && en==0)
squash_save<=1;
else
squash_save<=0;
end
endmodule
*/
/****************************************************************************/
/****************************************************************************
One cycle Stall circuit
****************************************************************************/
module onecyclestall(request,clk,resetn,stalled);
input request;
input clk;
input resetn;
output stalled;
reg T,Tnext;
// State machine for Stalling 1 cycle
always@(request or T)
begin
case(T)
1'b0: Tnext=request;
1'b1: Tnext=0;
endcase
end
always@(posedge clk)
if (~resetn)
T<=0;
else
T<=Tnext;
assign stalled=(request&~T);
endmodule
/****************************************************************************
Multi cycle Stall circuit - with wait signal
- One FF plus one 2:1 mux to stall 1st cycle on request, then wait
- this makes wait don't care for the first cycle
****************************************************************************/
/*
module multicyclestall(request, devwait,clk,resetn,stalled);
input request;
input devwait;
input clk;
input resetn;
output stalled;
reg T;
always@(posedge clk)
if (~resetn)
T<=0;
else
T<=stalled;
assign stalled=(T) ? devwait : request;
endmodule
*/
/****************************************************************************
One cycle - Pipeline delay register
****************************************************************************/
/*
module pipedelayreg(d,en,clk,resetn,squashn,dst,stalled,q);
//`define WIDTH 32
//parameter WIDTH=32;
input [31:0] d;
input [4:0] dst;
input en;
input clk;
input resetn;
input squashn;
output stalled;
output [31:0] q;
reg [31:0] q;
reg T,Tnext;
// State machine for Stalling 1 cycle
always@(en or T or dst)
begin
case(T)
0: Tnext=en&(|dst);
1: Tnext=0;
endcase
end
always@(posedge clk)
if (~resetn)
T<=0;
else
T<=Tnext;
always @(posedge clk) //synchronous reset
begin
if (resetn==0 || squashn==0)
q<=0;
else if (en==1)
q<=d;
end
assign stalled=(en&~T&(|dst));
endmodule
*/
/****************************************************************************
Fake Delay
****************************************************************************/
module fakedelay(clk,d,q);
//`define WIDTH 32
//parameter WIDTH=32;
input [31:0] d;
input clk;
output [31:0] q;
wire unused;
assign unused = clk;
assign q=d;
endmodule
/****************************************************************************
Zeroer
****************************************************************************/
module zeroer(d,en,q);
//parameter WIDTH=32;
//`define WIDTH 32
input en;
input [4:0] d;
output [31:0] q;
assign q[4:0]= (en) ? d : 0;
assign q [31:05] = 0;
endmodule
/****************************************************************************
NOP - used to hack position of multiplexors
****************************************************************************/
module nop(d,q);
//parameter WIDTH=32;
//`define WIDTH 32
input [31:0] d;
output [31:0] q;
assign q=d;
endmodule
/****************************************************************************
Const
****************************************************************************/
/****************************************************************************
Branch detector
****************************************************************************/
/*
module branch_detector(opcode, func, is_branch);
input [5:0] opcode;
input [5:0] func;
output is_branch;
wire is_special;
assign is_special=!(|opcode);
assign is_branch=((!(|opcode[5:3])) && !is_special) ||
((is_special)&&(func[5:3]==3'b001));
endmodule
*/
//`define WIDTH 32
module branchresolve ( rt, rs,en, eqz,gez,gtz,lez,ltz,ne, eq);
//parameter WIDTH=32;
input en;
input [31:0] rs;
input [31:0] rt;
output eq;
output ne;
output ltz;
output lez;
output gtz;
output gez;
output eqz;
assign eq=(en)&(rs==rt);
assign ne=(en)&~eq;
assign eqz=(en)&~(|rs);
assign ltz=(en)&rs[31];
assign lez=(en)&rs[31] | eqz;
assign gtz=(en)&(~rs[31]) & ~eqz;
assign gez=(en)&(~rs[31]);
endmodule
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ps / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
// megafunction wizard: %DDR3 SDRAM High Performance Controller v10.0%
//GENERATION: XML
//Generated by DDR3 SDRAM High Performance Controller 10.0
//IPFS_FILES:
//RELATED_FILES:
//<< MEGAWIZARD PARSE FILE DDR310.0
//.
//<< START MEGAWIZARD INSERT MODULE
module ddr3_int_example_top (
// inputs:
clock_source,
global_reset_n,
// outputs:
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_clk,
mem_clk_n,
mem_cs_n,
mem_dm,
mem_dq,
mem_dqs,
mem_dqsn,
mem_odt,
mem_ras_n,
mem_reset_n,
mem_we_n,
pnf,
pnf_per_byte,
test_complete,
test_status
)
;
output [ 12: 0] mem_addr;
output [ 2: 0] mem_ba;
output mem_cas_n;
output [ 0: 0] mem_cke;
inout [ 0: 0] mem_clk;
inout [ 0: 0] mem_clk_n;
output [ 0: 0] mem_cs_n;
output [ 3: 0] mem_dm;
inout [ 31: 0] mem_dq;
inout [ 3: 0] mem_dqs;
inout [ 3: 0] mem_dqsn;
output [ 0: 0] mem_odt;
output mem_ras_n;
output mem_reset_n;
output mem_we_n;
output pnf;
output [ 15: 0] pnf_per_byte;
output test_complete;
output [ 7: 0] test_status;
input clock_source;
input global_reset_n;
wire [ 0: 0] cs_n;
wire dll_reference_clk_sig;
wire [ 5: 0] dqs_delay_ctrl_export_sig;
wire local_burstbegin_sig;
wire [ 12: 0] mem_addr;
wire mem_aux_full_rate_clk;
wire mem_aux_half_rate_clk;
wire [ 2: 0] mem_ba;
wire mem_cas_n;
wire [ 0: 0] mem_cke;
wire [ 0: 0] mem_clk;
wire [ 0: 0] mem_clk_n;
wire [ 0: 0] mem_cs_n;
wire [ 3: 0] mem_dm;
wire [ 31: 0] mem_dq;
wire [ 3: 0] mem_dqs;
wire [ 3: 0] mem_dqsn;
wire [ 23: 0] mem_local_addr;
wire [ 15: 0] mem_local_be;
wire [ 9: 0] mem_local_col_addr;
wire mem_local_cs_addr;
wire [127: 0] mem_local_rdata;
wire mem_local_rdata_valid;
wire mem_local_read_req;
wire mem_local_ready;
wire [ 5: 0] mem_local_size;
wire [127: 0] mem_local_wdata;
wire mem_local_write_req;
wire [ 0: 0] mem_odt;
wire mem_ras_n;
wire mem_reset_n;
wire mem_we_n;
wire phy_clk;
wire pnf;
wire [ 15: 0] pnf_per_byte;
wire reset_phy_clk_n;
wire test_complete;
wire [ 7: 0] test_status;
wire tie_high;
wire tie_low;
//
//
assign mem_cs_n = cs_n;
//<< END MEGAWIZARD INSERT MODULE
assign tie_high = 1'b1;
assign tie_low = 1'b0;
//<< START MEGAWIZARD INSERT WRAPPER_NAME
ddr3_int ddr3_int_inst
(
.aux_full_rate_clk (mem_aux_full_rate_clk),
.aux_half_rate_clk (mem_aux_half_rate_clk),
.dll_reference_clk (dll_reference_clk_sig),
.dqs_delay_ctrl_export (dqs_delay_ctrl_export_sig),
.global_reset_n (global_reset_n),
.local_address (mem_local_addr),
.local_be (mem_local_be),
.local_burstbegin (local_burstbegin_sig),
.local_init_done (),
.local_rdata (mem_local_rdata),
.local_rdata_valid (mem_local_rdata_valid),
.local_read_req (mem_local_read_req),
.local_ready (mem_local_ready),
.local_refresh_ack (),
.local_size (mem_local_size),
.local_wdata (mem_local_wdata),
.local_wdata_req (),
.local_write_req (mem_local_write_req),
.mem_addr (mem_addr[12 : 0]),
.mem_ba (mem_ba),
.mem_cas_n (mem_cas_n),
.mem_cke (mem_cke),
.mem_clk (mem_clk),
.mem_clk_n (mem_clk_n),
.mem_cs_n (cs_n),
.mem_dm (mem_dm[3 : 0]),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs[3 : 0]),
.mem_dqsn (mem_dqsn[3 : 0]),
.mem_odt (mem_odt),
.mem_ras_n (mem_ras_n),
.mem_reset_n (mem_reset_n),
.mem_we_n (mem_we_n),
.phy_clk (phy_clk),
.pll_ref_clk (clock_source),
.reset_phy_clk_n (reset_phy_clk_n),
.reset_request_n (),
.soft_reset_n (tie_high)
);
//<< END MEGAWIZARD INSERT WRAPPER_NAME
//<< START MEGAWIZARD INSERT CS_ADDR_MAP
//connect up the column address bits, dropping 2 bits from example driver output because of 4:1 data rate
assign mem_local_addr[7 : 0] = mem_local_col_addr[9 : 2];
//<< END MEGAWIZARD INSERT CS_ADDR_MAP
//<< START MEGAWIZARD INSERT EXAMPLE_DRIVER
//Self-test, synthesisable code to exercise the DDR SDRAM Controller
ddr3_int_example_driver driver
(
.clk (phy_clk),
.local_bank_addr (mem_local_addr[23 : 21]),
.local_be (mem_local_be),
.local_burstbegin (local_burstbegin_sig),
.local_col_addr (mem_local_col_addr),
.local_cs_addr (mem_local_cs_addr),
.local_rdata (mem_local_rdata),
.local_rdata_valid (mem_local_rdata_valid),
.local_read_req (mem_local_read_req),
.local_ready (mem_local_ready),
.local_row_addr (mem_local_addr[20 : 8]),
.local_size (mem_local_size),
.local_wdata (mem_local_wdata),
.local_write_req (mem_local_write_req),
.pnf_per_byte (pnf_per_byte[15 : 0]),
.pnf_persist (pnf),
.reset_n (reset_phy_clk_n),
.test_complete (test_complete),
.test_status (test_status)
);
//<< END MEGAWIZARD INSERT EXAMPLE_DRIVER
//<< START MEGAWIZARD INSERT DLL
//<< END MEGAWIZARD INSERT DLL
//<< START MEGAWIZARD INSERT BANK_INFORMATION_EXAMPLE
//<< END MEGAWIZARD INSERT BANK_INFORMATION_EXAMPLE
//<< start europa
endmodule
|
/* Copyright (C) 2015-2016 by John Cronin
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
// Timer MMIO interface
module timer(clk, rst_, data, addr, cs_, oe_, we_, interrupt);
input clk;
input rst_;
inout [7:0] data;
input [7:0] addr;
input cs_;
input oe_;
input we_;
output interrupt;
reg [7:0] r[0:7];
// Provide read support of memory
assign data = (~cs_ & ~oe_) ? r[addr] : 8'bzzzzzzzz;
`ifndef USE_RST_LOGIC
initial begin
{ r[3], r[2], r[1], r[0] } = 32'd0;
{ r[7], r[6], r[5], r[4] } = 32'd0;
end
`endif
always @(posedge clk)
`ifdef USE_RST_LOGIC
if(~rst_) begin
{ r[3], r[2], r[1], r[0] } = 32'd0;
{ r[7], r[6], r[5], r[4] } = 32'd0;
end
else
`endif
if(~cs_ & ~we_)
r[addr] <= data;
else
{ r[3], r[2], r[1], r[0] } <= { r[3], r[2], r[1], r[0] } + 32'd1;
assign interrupt = ( { r[7], r[6], r[5], r[4] } == 32'd0 ) ? 1'b0 :
(( { r[3], r[2], r[1], r[0] } >= { r[7], r[6], r[5], r[4] } ) ? 1'b1 : 1'b0);
endmodule
|
(** * Stlc: The Simply Typed Lambda-Calculus *)
Require Export Types.
(* ###################################################################### *)
(** * The Simply Typed Lambda-Calculus *)
(** The simply typed lambda-calculus (STLC) is a tiny core calculus
embodying the key concept of _functional abstraction_, which shows
up in pretty much every real-world programming language in some
form (functions, procedures, methods, etc.).
We will follow exactly the same pattern as in the previous
chapter when formalizing this calculus (syntax, small-step
semantics, typing rules) and its main properties (progress and
preservation). The new technical challenges (which will take some
work to deal with) all arise from the mechanisms of _variable
binding_ and _substitution_. *)
(* ###################################################################### *)
(** ** Overview *)
(** The STLC is built on some collection of _base types_ -- booleans,
numbers, strings, etc. The exact choice of base types doesn't
matter -- the construction of the language and its theoretical
properties work out pretty much the same -- so for the sake of
brevity let's take just [Bool] for the moment. At the end of the
chapter we'll see how to add more base types, and in later
chapters we'll enrich the pure STLC with other useful constructs
like pairs, records, subtyping, and mutable state.
Starting from the booleans, we add three things:
- variables
- function abstractions
- application
This gives us the following collection of abstract syntax
constructors (written out here in informal BNF notation -- we'll
formalize it below).
*)
(** Informal concrete syntax:
t ::= x variable
| \x:T1.t2 abstraction
| t1 t2 application
| true constant true
| false constant false
| if t1 then t2 else t3 conditional
*)
(** The [\] symbol (backslash, in ascii) in a function abstraction
[\x:T1.t2] is generally written as a greek letter "lambda" (hence
the name of the calculus). The variable [x] is called the
_parameter_ to the function; the term [t2] is its _body_. The
annotation [:T] specifies the type of arguments that the function
can be applied to. *)
(** Some examples:
- [\x:Bool. x]
The identity function for booleans.
- [(\x:Bool. x) true]
The identity function for booleans, applied to the boolean [true].
- [\x:Bool. if x then false else true]
The boolean "not" function.
- [\x:Bool. true]
The constant function that takes every (boolean) argument to
[true]. *)
(**
- [\x:Bool. \y:Bool. x]
A two-argument function that takes two booleans and returns
the first one. (Note that, as in Coq, a two-argument function
is really a one-argument function whose body is also a
one-argument function.)
- [(\x:Bool. \y:Bool. x) false true]
A two-argument function that takes two booleans and returns
the first one, applied to the booleans [false] and [true].
Note that, as in Coq, application associates to the left --
i.e., this expression is parsed as [((\x:Bool. \y:Bool. x)
false) true].
- [\f:Bool->Bool. f (f true)]
A higher-order function that takes a _function_ [f] (from
booleans to booleans) as an argument, applies [f] to [true],
and applies [f] again to the result.
- [(\f:Bool->Bool. f (f true)) (\x:Bool. false)]
The same higher-order function, applied to the constantly
[false] function. *)
(** As the last several examples show, the STLC is a language of
_higher-order_ functions: we can write down functions that take
other functions as arguments and/or return other functions as
results.
Another point to note is that the STLC doesn't provide any
primitive syntax for defining _named_ functions -- all functions
are "anonymous." We'll see in chapter [MoreStlc] that it is easy
to add named functions to what we've got -- indeed, the
fundamental naming and binding mechanisms are exactly the same.
The _types_ of the STLC include [Bool], which classifies the
boolean constants [true] and [false] as well as more complex
computations that yield booleans, plus _arrow types_ that classify
functions. *)
(**
T ::= Bool
| T1 -> T2
For example:
- [\x:Bool. false] has type [Bool->Bool]
- [\x:Bool. x] has type [Bool->Bool]
- [(\x:Bool. x) true] has type [Bool]
- [\x:Bool. \y:Bool. x] has type [Bool->Bool->Bool] (i.e. [Bool -> (Bool->Bool)])
- [(\x:Bool. \y:Bool. x) false] has type [Bool->Bool]
- [(\x:Bool. \y:Bool. x) false true] has type [Bool]
*)
(* ###################################################################### *)
(** ** Syntax *)
Module STLC.
(* ################################### *)
(** *** Types *)
Inductive ty : Type :=
| TBool : ty
| TArrow : ty -> ty -> ty.
(* ################################### *)
(** *** Terms *)
Inductive tm : Type :=
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Tactic Notation "t_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "tvar" | Case_aux c "tapp"
| Case_aux c "tabs" | Case_aux c "ttrue"
| Case_aux c "tfalse" | Case_aux c "tif" ].
(** Note that an abstraction [\x:T.t] (formally, [tabs x T t]) is
always annotated with the type [T] of its parameter, in contrast
to Coq (and other functional languages like ML, Haskell, etc.),
which use _type inference_ to fill in missing annotations. We're
not considering type inference here, to keep things simple. *)
(** Some examples... *)
Definition x := (Id 0).
Definition y := (Id 1).
Definition z := (Id 2).
Hint Unfold x.
Hint Unfold y.
Hint Unfold z.
(** [idB = \x:Bool. x] *)
Notation idB :=
(tabs x TBool (tvar x)).
(** [idBB = \x:Bool->Bool. x] *)
Notation idBB :=
(tabs x (TArrow TBool TBool) (tvar x)).
(** [idBBBB = \x:(Bool->Bool) -> (Bool->Bool). x] *)
Notation idBBBB :=
(tabs x (TArrow (TArrow TBool TBool)
(TArrow TBool TBool))
(tvar x)).
(** [k = \x:Bool. \y:Bool. x] *)
Notation k := (tabs x TBool (tabs y TBool (tvar x))).
(** [notB = \x:Bool. if x then false else true] *)
Notation notB := (tabs x TBool (tif (tvar x) tfalse ttrue)).
(** (We write these as [Notation]s rather than [Definition]s to make
things easier for [auto].) *)
(* ###################################################################### *)
(** ** Operational Semantics *)
(** To define the small-step semantics of STLC terms, we begin -- as
always -- by defining the set of values. Next, we define the
critical notions of _free variables_ and _substitution_, which are
used in the reduction rule for application expressions. And
finally we give the small-step relation itself. *)
(* ################################### *)
(** *** Values *)
(** To define the values of the STLC, we have a few cases to consider.
First, for the boolean part of the language, the situation is
clear: [true] and [false] are the only values. An [if]
expression is never a value. *)
(** Second, an application is clearly not a value: It represents a
function being invoked on some argument, which clearly still has
work left to do. *)
(** Third, for abstractions, we have a choice:
- We can say that [\x:T.t1] is a value only when [t1] is a
value -- i.e., only if the function's body has been
reduced (as much as it can be without knowing what argument it
is going to be applied to).
- Or we can say that [\x:T.t1] is always a value, no matter
whether [t1] is one or not -- in other words, we can say that
reduction stops at abstractions.
Coq, in its built-in functional programming langauge, makes the
first choice -- for example,
Eval simpl in (fun x:bool => 3 + 4)
yields [fun x:bool => 7].
Most real-world functional programming languages make the second
choice -- reduction of a function's body only begins when the
function is actually applied to an argument. We also make the
second choice here. *)
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tabs x T t)
| v_true :
value ttrue
| v_false :
value tfalse.
Hint Constructors value.
(** Finally, we must consider what constitutes a _complete_ program.
Intuitively, a "complete" program must not refer to any undefined
variables. We'll see shortly how to define the "free" variables
in a STLC term. A program is "closed", that is, it contains no
free variables.
*)
(** Having made the choice not to reduce under abstractions,
we don't need to worry about whether variables are values, since
we'll always be reducing programs "from the outside in," and that
means the [step] relation will always be working with closed
terms (ones with no free variables). *)
(* ###################################################################### *)
(** *** Substitution *)
(** Now we come to the heart of the STLC: the operation of
substituting one term for a variable in another term.
This operation will be used below to define the operational
semantics of function application, where we will need to
substitute the argument term for the function parameter in the
function's body. For example, we reduce
(\x:Bool. if x then true else x) false
to
if false then true else false
]]
by substituting [false] for the parameter [x] in the body of the
function.
In general, we need to be able to substitute some given
term [s] for occurrences of some variable [x] in another term [t].
In informal discussions, this is usually written [ [x:=s]t ] and
pronounced "substitute [x] with [s] in [t]." *)
(** Here are some examples:
- [[x:=true] (if x then x else false)] yields [if true then true else false]
- [[x:=true] x] yields [true]
- [[x:=true] (if x then x else y)] yields [if true then true else y]
- [[x:=true] y] yields [y]
- [[x:=true] false] yields [false] (vacuous substitution)
- [[x:=true] (\y:Bool. if y then x else false)] yields [\y:Bool. if y then true else false]
- [[x:=true] (\y:Bool. x)] yields [\y:Bool. true]
- [[x:=true] (\y:Bool. y)] yields [\y:Bool. y]
- [[x:=true] (\x:Bool. x)] yields [\x:Bool. x]
The last example is very important: substituting [x] with [true] in
[\x:Bool. x] does _not_ yield [\x:Bool. true]! The reason for
this is that the [x] in the body of [\x:Bool. x] is _bound_ by the
abstraction: it is a new, local name that just happens to be
spelled the same as some global name [x]. *)
(** Here is the definition, informally...
[x:=s]x = s
[x:=s]y = y if x <> y
[x:=s](\x:T11.t12) = \x:T11. t12
[x:=s](\y:T11.t12) = \y:T11. [x:=s]t12 if x <> y
[x:=s](t1 t2) = ([x:=s]t1) ([x:=s]t2)
[x:=s]true = true
[x:=s]false = false
[x:=s](if t1 then t2 else t3) =
if [x:=s]t1 then [x:=s]t2 else [x:=s]t3
]]
*)
(** ... and formally: *)
Reserved Notation "'[' x ':=' s ']' t" (at level 20).
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar x' =>
if eq_id_dec x x' then s else t
| tabs x' T t1 =>
tabs x' T (if eq_id_dec x x' then t1 else ([x:=s] t1))
| tapp t1 t2 =>
tapp ([x:=s] t1) ([x:=s] t2)
| ttrue =>
ttrue
| tfalse =>
tfalse
| tif t1 t2 t3 =>
tif ([x:=s] t1) ([x:=s] t2) ([x:=s] t3)
end
where "'[' x ':=' s ']' t" := (subst x s t).
(** _Technical note_: Substitution becomes trickier to define if we
consider the case where [s], the term being substituted for a
variable in some other term, may itself contain free variables.
Since we are only interested here in defining the [step] relation
on closed terms (i.e., terms like [\x:Bool. x], that do not mention
variables are not bound by some enclosing lambda), we can skip
this extra complexity here, but it must be dealt with when
formalizing richer languages. *)
(** *** *)
(** **** Exercise: 3 stars (substi) *)
(** The definition that we gave above uses Coq's [Fixpoint] facility
to define substitution as a _function_. Suppose, instead, we
wanted to define substitution as an inductive _relation_ [substi].
We've begun the definition by providing the [Inductive] header and
one of the constructors; your job is to fill in the rest of the
constructors. *)
Inductive substi (s:tm) (x:id) : tm -> tm -> Prop :=
| s_var1 :
substi s x (tvar x) s
| s_var2 :
forall y,
x <> y ->
substi s x (tvar y) (tvar y)
| s_abs1 :
forall T t1,
substi s x (tabs x T t1) (tabs x T t1)
| s_abs2 :
forall y T t1,
x <> y ->
substi s x (tabs y T t1) (tabs y T ([x:=s] t1))
| s_app :
forall t1 t2,
substi s x (tapp t1 t2) (tapp ([x:=s] t1) ([x:=s] t2))
| s_true :
substi s x ttrue ttrue
| s_false :
substi s x tfalse tfalse
| s_if :
forall t1 t2 t3,
substi s x (tif t1 t2 t3) (tif ([x:=s] t1) ([x:=s] t2) ([x:=s] t3)).
Hint Constructors substi.
Theorem substi_correct : forall s x t t',
[x:=s]t = t' <-> substi s x t t'.
Proof.
split; intros.
Case "->".
destruct t.
simpl in H.
destruct (eq_id_dec x0 i).
rewrite e. rewrite H. apply s_var1.
rewrite <- H. apply s_var2. assumption.
rewrite <- H. simpl. apply s_app.
simpl in H.
destruct (eq_id_dec x0 i).
rewrite <- H. rewrite <- e. apply s_abs1.
rewrite <- H. apply s_abs2. assumption.
rewrite <- H. simpl. apply s_true.
rewrite <- H. simpl. apply s_false.
rewrite <- H. simpl. apply s_if.
Case "<-".
inversion H.
simpl. rewrite eq_id. reflexivity.
simpl. apply neq_id. assumption.
simpl. rewrite eq_id. reflexivity.
simpl. rewrite neq_id. reflexivity. assumption.
reflexivity.
reflexivity.
reflexivity.
simpl. reflexivity.
Qed.
(** [] *)
(* ################################### *)
(** *** Reduction *)
(** The small-step reduction relation for STLC now follows the same
pattern as the ones we have seen before. Intuitively, to reduce a
function application, we first reduce its left-hand side until it
becomes a literal function; then we reduce its right-hand
side (the argument) until it is also a value; and finally we
substitute the argument for the bound variable in the body of the
function. This last rule, written informally as
(\x:T.t12) v2 ==> [x:=v2]t12
is traditionally called "beta-reduction". *)
(**
value v2
---------------------------- (ST_AppAbs)
(\x:T.t12) v2 ==> [x:=v2]t12
t1 ==> t1'
---------------- (ST_App1)
t1 t2 ==> t1' t2
value v1
t2 ==> t2'
---------------- (ST_App2)
v1 t2 ==> v1 t2'
*)
(** ... plus the usual rules for booleans:
-------------------------------- (ST_IfTrue)
(if true then t1 else t2) ==> t1
--------------------------------- (ST_IfFalse)
(if false then t1 else t2) ==> t2
t1 ==> t1'
---------------------------------------------------- (ST_If)
(if t1 then t2 else t3) ==> (if t1' then t2 else t3)
*)
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T t12 v2,
value v2 ->
(tapp (tabs x T t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
tapp t1 t2 ==> tapp t1' t2
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
tapp v1 t2 ==> tapp v1 t2'
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif t1 t2 t3) ==> (tif t1' t2 t3)
where "t1 '==>' t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_AppAbs" | Case_aux c "ST_App1"
| Case_aux c "ST_App2" | Case_aux c "ST_IfTrue"
| Case_aux c "ST_IfFalse" | Case_aux c "ST_If" ].
Hint Constructors step.
Notation multistep := (multi step).
Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40).
(* ##################################### *)
(* ##################################### *)
(** *** Examples *)
(** Example:
((\x:Bool->Bool. x) (\x:Bool. x)) ==>* (\x:Bool. x)
i.e.
(idBB idB) ==>* idB
*)
Lemma step_example1 :
(tapp idBB idB) ==>* idB.
Proof.
eapply multi_step.
apply ST_AppAbs.
apply v_abs.
simpl.
apply multi_refl. Qed.
(** Example:
((\x:Bool->Bool. x) ((\x:Bool->Bool. x) (\x:Bool. x)))
==>* (\x:Bool. x)
i.e.
(idBB (idBB idB)) ==>* idB.
*)
Lemma step_example2 :
(tapp idBB (tapp idBB idB)) ==>* idB.
Proof.
eapply multi_step.
apply ST_App2. auto.
apply ST_AppAbs. auto.
eapply multi_step.
apply ST_AppAbs. simpl. auto.
simpl. apply multi_refl. Qed.
(** Example:
((\x:Bool->Bool. x) (\x:Bool. if x then false
else true)) true)
==>* false
i.e.
((idBB notB) ttrue) ==>* tfalse.
*)
Lemma step_example3 :
tapp (tapp idBB notB) ttrue ==>* tfalse.
Proof.
eapply multi_step.
apply ST_App1. apply ST_AppAbs. auto. simpl.
eapply multi_step.
apply ST_AppAbs. auto. simpl.
eapply multi_step.
apply ST_IfTrue. apply multi_refl. Qed.
(** Example:
((\x:Bool -> Bool. x) ((\x:Bool. if x then false
else true) true))
==>* false
i.e.
(idBB (notB ttrue)) ==>* tfalse.
*)
Lemma step_example4 :
tapp idBB (tapp notB ttrue) ==>* tfalse.
Proof.
eapply multi_step.
apply ST_App2. auto.
apply ST_AppAbs. auto. simpl.
eapply multi_step.
apply ST_App2. auto.
apply ST_IfTrue.
eapply multi_step.
apply ST_AppAbs. auto. simpl.
apply multi_refl. Qed.
(** A more automatic proof *)
Lemma step_example1' :
(tapp idBB idB) ==>* idB.
Proof. normalize. Qed.
(** Again, we can use the [normalize] tactic from above to simplify
the proof. *)
Lemma step_example2' :
(tapp idBB (tapp idBB idB)) ==>* idB.
Proof.
normalize.
Qed.
Lemma step_example3' :
tapp (tapp idBB notB) ttrue ==>* tfalse.
Proof. normalize. Qed.
Lemma step_example4' :
tapp idBB (tapp notB ttrue) ==>* tfalse.
Proof. normalize. Qed.
(** **** Exercise: 2 stars (step_example3) *)
(** Try to do this one both with and without [normalize]. *)
Lemma step_example5 :
(tapp (tapp idBBBB idBB) idB)
==>* idB.
Proof.
(* normalize. *)
eapply multi_step.
apply ST_App1.
apply ST_AppAbs. auto.
simpl.
eapply multi_step.
apply ST_AppAbs. auto.
simpl. apply multi_refl.
Qed.
(* FILL IN HERE *)
(** [] *)
(* ###################################################################### *)
(** ** Typing *)
(* ################################### *)
(** *** Contexts *)
(** _Question_: What is the type of the term "[x y]"?
_Answer_: It depends on the types of [x] and [y]!
I.e., in order to assign a type to a term, we need to know
what assumptions we should make about the types of its free
variables.
This leads us to a three-place "typing judgment", informally
written [Gamma |- t \in T], where [Gamma] is a
"typing context" -- a mapping from variables to their types. *)
(** We hide the definition of partial maps in a module since it is
actually defined in [SfLib]. *)
Module PartialMap.
Definition partial_map (A:Type) := id -> option A.
Definition empty {A:Type} : partial_map A := (fun _ => None).
(** Informally, we'll write [Gamma, x:T] for "extend the partial
function [Gamma] to also map [x] to [T]." Formally, we use the
function [extend] to add a binding to a partial map. *)
Definition extend {A:Type} (Gamma : partial_map A) (x:id) (T : A) :=
fun x' => if eq_id_dec x x' then Some T else Gamma x'.
Lemma extend_eq : forall A (ctxt: partial_map A) x T,
(extend ctxt x T) x = Some T.
Proof.
intros. unfold extend. rewrite eq_id. auto.
Qed.
Lemma extend_neq : forall A (ctxt: partial_map A) x1 T x2,
x2 <> x1 ->
(extend ctxt x2 T) x1 = ctxt x1.
Proof.
intros. unfold extend. rewrite neq_id; auto.
Qed.
End PartialMap.
Definition context := partial_map ty.
(* ################################### *)
(** *** Typing Relation *)
(**
Gamma x = T
-------------- (T_Var)
Gamma |- x \in T
Gamma , x:T11 |- t12 \in T12
---------------------------- (T_Abs)
Gamma |- \x:T11.t12 \in T11->T12
Gamma |- t1 \in T11->T12
Gamma |- t2 \in T11
---------------------- (T_App)
Gamma |- t1 t2 \in T12
-------------------- (T_True)
Gamma |- true \in Bool
--------------------- (T_False)
Gamma |- false \in Bool
Gamma |- t1 \in Bool Gamma |- t2 \in T Gamma |- t3 \in T
-------------------------------------------------------- (T_If)
Gamma |- if t1 then t2 else t3 \in T
We can read the three-place relation [Gamma |- t \in T] as:
"to the term [t] we can assign the type [T] using as types for
the free variables of [t] the ones specified in the context
[Gamma]." *)
Reserved Notation "Gamma '|-' t '\in' T" (at level 40).
Inductive has_type : context -> tm -> ty -> Prop :=
| T_Var : forall Gamma x T,
Gamma x = Some T ->
Gamma |- tvar x \in T
| T_Abs : forall Gamma x T11 T12 t12,
extend Gamma x T11 |- t12 \in T12 ->
Gamma |- tabs x T11 t12 \in TArrow T11 T12
| T_App : forall T11 T12 Gamma t1 t2,
Gamma |- t1 \in TArrow T11 T12 ->
Gamma |- t2 \in T11 ->
Gamma |- tapp t1 t2 \in T12
| T_True : forall Gamma,
Gamma |- ttrue \in TBool
| T_False : forall Gamma,
Gamma |- tfalse \in TBool
| T_If : forall t1 t2 t3 T Gamma,
Gamma |- t1 \in TBool ->
Gamma |- t2 \in T ->
Gamma |- t3 \in T ->
Gamma |- tif t1 t2 t3 \in T
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_Var" | Case_aux c "T_Abs"
| Case_aux c "T_App" | Case_aux c "T_True"
| Case_aux c "T_False" | Case_aux c "T_If" ].
Hint Constructors has_type.
(* ################################### *)
(** *** Examples *)
Example typing_example_1 :
empty |- tabs x TBool (tvar x) \in TArrow TBool TBool.
Proof.
apply T_Abs. apply T_Var. reflexivity. Qed.
(** Note that since we added the [has_type] constructors to the hints
database, auto can actually solve this one immediately. *)
Example typing_example_1' :
empty |- tabs x TBool (tvar x) \in TArrow TBool TBool.
Proof. auto. Qed.
(** Another example:
empty |- \x:A. \y:A->A. y (y x))
\in A -> (A->A) -> A.
*)
Example typing_example_2 :
empty |-
(tabs x TBool
(tabs y (TArrow TBool TBool)
(tapp (tvar y) (tapp (tvar y) (tvar x))))) \in
(TArrow TBool (TArrow (TArrow TBool TBool) TBool)).
Proof with auto using extend_eq.
apply T_Abs.
apply T_Abs.
eapply T_App. apply T_Var...
eapply T_App. apply T_Var...
apply T_Var...
Qed.
(** **** Exercise: 2 stars, optional (typing_example_2_full) *)
(** Prove the same result without using [auto], [eauto], or
[eapply]. *)
Example typing_example_2_full :
empty |-
(tabs x TBool
(tabs y (TArrow TBool TBool)
(tapp (tvar y) (tapp (tvar y) (tvar x))))) \in
(TArrow TBool (TArrow (TArrow TBool TBool) TBool)).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (typing_example_3) *)
(** Formally prove the following typing derivation holds: *)
(**
empty |- \x:Bool->B. \y:Bool->Bool. \z:Bool.
y (x z)
\in T.
*)
Example typing_example_3 :
exists T,
empty |-
(tabs x (TArrow TBool TBool)
(tabs y (TArrow TBool TBool)
(tabs z TBool
(tapp (tvar y) (tapp (tvar x) (tvar z)))))) \in
T.
Proof with auto.
exists (TArrow (TArrow TBool TBool)
(TArrow (TArrow TBool TBool)
(TArrow TBool TBool))).
apply T_Abs.
apply T_Abs.
apply T_Abs.
apply T_App with (T11 := TBool).
apply T_Var. reflexivity.
apply T_App with (T11 := TBool).
apply T_Var. reflexivity.
apply T_Var. reflexivity.
Qed.
(** [] *)
(** We can also show that terms are _not_ typable. For example, let's
formally check that there is no typing derivation assigning a type
to the term [\x:Bool. \y:Bool, x y] -- i.e.,
~ exists T,
empty |- \x:Bool. \y:Bool, x y : T.
*)
Example typing_nonexample_1 :
~ exists T,
empty |-
(tabs x TBool
(tabs y TBool
(tapp (tvar x) (tvar y)))) \in
T.
Proof.
intros Hc. inversion Hc.
(* The [clear] tactic is useful here for tidying away bits of
the context that we're not going to need again. *)
inversion H. subst. clear H.
inversion H5. subst. clear H5.
inversion H4. subst. clear H4.
inversion H2. subst. clear H2.
inversion H5. subst. clear H5.
(* rewrite extend_neq in H1. rewrite extend_eq in H1. *)
inversion H1. Qed.
(** **** Exercise: 3 stars, optional (typing_nonexample_3) *)
(** Another nonexample:
~ (exists S, exists T,
empty |- \x:S. x x : T).
*)
Example typing_nonexample_3 :
~ (exists S, exists T,
empty |-
(tabs x S
(tapp (tvar x) (tvar x))) \in
T).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End STLC.
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 19:08:25 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire Shift_reg_FLAGS_7_6, intAS, SIGN_FLAG_EXP, OP_FLAG_EXP, ZERO_FLAG_EXP,
SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1, left_right_SHT2,
SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2,
ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG,
ZERO_FLAG_SFG, inst_FSM_INPUT_ENABLE_state_next_1_, n544, n545, n546,
n547, n548, n549, n550, n551, n552, n553, n554, n555, n556, n557,
n558, n559, n560, n561, n562, n563, n564, n565, n566, n567, n568,
n569, n570, n571, n572, n573, n574, n575, n576, n577, n578, n579,
n580, n581, n582, n583, n584, n585, n586, n587, n588, n589, n590,
n591, n592, n593, n594, n595, n596, n597, n598, n599, n600, n601,
n602, n603, n604, n605, n606, n607, n608, n609, n610, n611, n612,
n613, n614, n615, n616, n617, n618, n619, n620, n621, n622, n623,
n624, n625, n626, n627, n628, n629, n630, n631, n632, n633, n634,
n635, n636, n637, n638, n639, n640, n641, n642, n643, n644, n645,
n646, n647, n648, n649, n650, n651, n652, n653, n654, n655, n656,
n657, n658, n659, n660, n661, n662, n663, n664, n665, n666, n667,
n668, n669, n670, n671, n672, n673, n674, n675, n676, n677, n678,
n679, n680, n681, n682, n683, n684, n685, n686, n687, n688, n689,
n690, n691, n692, n693, n694, n695, n696, n697, n698, n699, n700,
n701, n702, n703, n704, n705, n706, n707, n708, n709, n710, n711,
n712, n713, n714, n715, n716, n717, n718, n719, n720, n721, n722,
n723, n724, n725, n726, n727, n728, n729, n730, n731, n732, n733,
n734, n735, n736, n737, n738, n739, n740, n741, n742, n743, n744,
n745, n746, n747, n748, n749, n750, n751, n752, n753, n754, n755,
n756, n757, n758, n759, n760, n761, n762, n763, n764, n765, n766,
n767, n768, n769, n770, n771, n772, n773, n774, n775, n776, n777,
n778, n779, n780, n781, n782, n783, n784, n785, n786, n787, n788,
n789, n790, n791, n792, n793, n794, n795, n796, n797, n798, n799,
n800, n801, n802, n803, n804, n805, n806, n807, n808, n809, n810,
n811, n812, n813, n814, n815, n816, n817, n818, n819, n820, n821,
n822, n823, n824, n825, n826, n827, n828, n829, n830, n831, n832,
n833, n834, n835, n836, n837, n838, n839, n840, n841, n842, n843,
n844, n845, n846, n847, n848, n850, n851, n852, n853, n854, n855,
n856, n857, n858, n859, n860, n861, n862, n863, n864, n865, n866,
n867, n868, n869, n870, n871, n872, n873, n874, n875, n876, n877,
n878, n879, n880, n881, n882, n883, n884, n885, n886, n887, n888,
n889, n890, n891, n892, n893, n894, n895, n896, n897, n898, n899,
n900, n901, n902, n903, n904, n905, n906, n907, n908, n909, n910,
n911, n912, n913, n914, n915, n916, n917, n918, n919, n920, n921,
n922, n923, n924, n925, n926, n927, n928, n929, n930, n931, n932,
n933, n934, n935, n936, n937, n938, n939, n940, n941, n942, n943,
n944, n945, n946, n947, n948, n949, n950, n951, n952,
DP_OP_15J11_123_2691_n8, DP_OP_15J11_123_2691_n7,
DP_OP_15J11_123_2691_n6, DP_OP_15J11_123_2691_n5,
DP_OP_15J11_123_2691_n4, intadd_5_B_9_, intadd_5_B_8_, intadd_5_B_7_,
intadd_5_B_6_, intadd_5_B_5_, intadd_5_B_4_, intadd_5_B_3_,
intadd_5_B_2_, intadd_5_B_1_, intadd_5_B_0_, intadd_5_CI,
intadd_5_SUM_9_, intadd_5_SUM_8_, intadd_5_SUM_7_, intadd_5_SUM_6_,
intadd_5_SUM_5_, intadd_5_SUM_4_, intadd_5_SUM_3_, intadd_5_SUM_2_,
intadd_5_SUM_1_, intadd_5_SUM_0_, intadd_5_n10, intadd_5_n9,
intadd_5_n8, intadd_5_n7, intadd_5_n6, intadd_5_n5, intadd_5_n4,
intadd_5_n3, intadd_5_n2, intadd_5_n1, n953, n954, n955, n956, n957,
n958, n959, n960, n961, n962, n963, n964, n965, n966, n967, n968,
n969, n970, n971, n972, n973, n974, n975, n976, n977, n978, n979,
n980, n981, n982, n983, n984, n985, n986, n987, n988, n989, n990,
n991, n992, n993, n994, n995, n996, n997, n998, n999, n1000, n1001,
n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009, n1010, n1011,
n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020, n1021,
n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030, n1031,
n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040, n1041,
n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050, n1051,
n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060, n1061,
n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070, n1071,
n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080, n1081,
n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090, n1091,
n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100, n1101,
n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110, n1111,
n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120, n1121,
n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130, n1131,
n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140, n1141,
n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150, n1151,
n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160, n1161,
n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170, n1171,
n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180, n1181,
n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190, n1191,
n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201,
n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211,
n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221,
n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231,
n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241,
n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251,
n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261,
n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271,
n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281,
n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291,
n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301,
n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311,
n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321,
n1322, n1323, n1324, n1325, n1326, n1327, n1329, n1330, n1331, n1332,
n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342,
n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352,
n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362,
n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372,
n1373, n1374, n1375, n1376, n1377, n1379, n1380, n1381, n1382, n1383,
n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393,
n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403,
n1404, n1405, n1406, n1408, n1409, n1410, n1411, n1412, n1413, n1414,
n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424,
n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434,
n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444,
n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454,
n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464,
n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474,
n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484,
n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494,
n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504,
n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514,
n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524,
n1525, n1526, n1527, n1528, n1530, n1531, n1532, n1533, n1534, n1535,
n1536, n1537, n1538, n1539, n1541, n1542, n1543, n1544, n1545, n1546,
n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556,
n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566,
n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576,
n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586,
n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596,
n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606,
n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616,
n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626,
n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636,
n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646,
n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656,
n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666,
n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676,
n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686,
n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696,
n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706,
n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716,
n1717, n1718, n1719, n1721, n1722, n1723, n1724, n1725, n1726, n1727,
n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1738,
n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748,
n1750, n1751, n1752;
wire [1:0] Shift_reg_FLAGS_7;
wire [31:0] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:1] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [25:1] Raw_mant_NRM_SWR;
wire [23:0] Data_array_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [4:0] LZD_output_NRM2_EW;
wire [4:1] exp_rslt_NRM2_EW1;
wire [30:0] DMP_SFG;
wire [25:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(n947), .CK(clk), .RN(n1721), .QN(
n970) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n941), .CK(clk), .RN(n1730),
.QN(n963) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n933), .CK(clk), .RN(n1723),
.QN(n964) );
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n911), .CK(clk), .RN(n1722), .Q(
intAS) );
DFFRXLTS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n910), .CK(clk), .RN(n1721), .Q(
left_right_SHT2) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n1727),
.Q(ready) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n873), .CK(clk), .RN(n1728), .QN(
n958) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n869), .CK(clk), .RN(n1725), .QN(
n967) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n855), .CK(clk), .RN(n1745), .Q(
Data_array_SWR[3]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n854), .CK(clk), .RN(n1726), .Q(
Data_array_SWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n846), .CK(clk), .RN(n1729),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n845), .CK(clk), .RN(n1728),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n844), .CK(clk), .RN(n1725),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n843), .CK(clk), .RN(n1729),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n842), .CK(clk), .RN(n1743), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n841), .CK(clk), .RN(n1747), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n840), .CK(clk), .RN(n1747), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n839), .CK(clk), .RN(n1747), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n838), .CK(clk), .RN(n1747), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n837), .CK(clk), .RN(n1747), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n836), .CK(clk), .RN(n1747), .Q(
final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n835), .CK(clk), .RN(n1747), .Q(
final_result_ieee[30]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n834), .CK(clk), .RN(n1744), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n833), .CK(clk), .RN(n1726), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n832), .CK(clk), .RN(n1726), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n831), .CK(clk), .RN(n1728), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n830), .CK(clk), .RN(n1725), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n829), .CK(clk), .RN(n1745), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n828), .CK(clk), .RN(n1732), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n827), .CK(clk), .RN(n1726), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n826), .CK(clk), .RN(n1738), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n825), .CK(clk), .RN(n1730), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n824), .CK(clk), .RN(n1723), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n823), .CK(clk), .RN(n1724), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n822), .CK(clk), .RN(n1722), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n821), .CK(clk), .RN(n1721), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n820), .CK(clk), .RN(n1727), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n819), .CK(clk), .RN(n1730), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n818), .CK(clk), .RN(n1723), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n817), .CK(clk), .RN(n1734), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n816), .CK(clk), .RN(n1721), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n815), .CK(clk), .RN(n1724), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n814), .CK(clk), .RN(n1727), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n813), .CK(clk), .RN(n1731), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n812), .CK(clk), .RN(n1731), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(n807), .CK(clk), .RN(n1731), .QN(n971)
);
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n806), .CK(clk), .RN(n1731), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n805), .CK(clk), .RN(n1731), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n804), .CK(clk), .RN(n1731), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n803), .CK(clk), .RN(n1731), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n802), .CK(clk), .RN(n1731), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n801), .CK(clk), .RN(n1722), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n800), .CK(clk), .RN(n1722), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n799), .CK(clk), .RN(n1723), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n797), .CK(clk), .RN(n956), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n796), .CK(clk), .RN(n956), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n794), .CK(clk), .RN(n956), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n793), .CK(clk), .RN(n956), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n791), .CK(clk), .RN(n956), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n790), .CK(clk), .RN(n1005), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n788), .CK(clk), .RN(n956), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n787), .CK(clk), .RN(n1732), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n785), .CK(clk), .RN(n1732), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n784), .CK(clk), .RN(n956), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n782), .CK(clk), .RN(n1733), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n781), .CK(clk), .RN(n1736), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n779), .CK(clk), .RN(n1736), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n778), .CK(clk), .RN(n1005), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n776), .CK(clk), .RN(n1733), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n775), .CK(clk), .RN(n1733), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n773), .CK(clk), .RN(n1005), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n772), .CK(clk), .RN(n956), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n770), .CK(clk), .RN(n1733), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n769), .CK(clk), .RN(n1743), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n767), .CK(clk), .RN(n1005), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n766), .CK(clk), .RN(n1743), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n764), .CK(clk), .RN(n1722), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n763), .CK(clk), .RN(n1734), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n761), .CK(clk), .RN(n1722), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n760), .CK(clk), .RN(n1734), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_13_ ( .D(n759), .CK(clk), .RN(n1722), .Q(
DMP_SFG[13]), .QN(n1668) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n758), .CK(clk), .RN(n1734), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n757), .CK(clk), .RN(n1722), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_14_ ( .D(n756), .CK(clk), .RN(n1734), .Q(
DMP_SFG[14]), .QN(n1671) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n755), .CK(clk), .RN(n1734), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n754), .CK(clk), .RN(n1722), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_15_ ( .D(n753), .CK(clk), .RN(n1746), .Q(
DMP_SFG[15]), .QN(n1690) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n752), .CK(clk), .RN(n1735), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n751), .CK(clk), .RN(n1746), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_16_ ( .D(n750), .CK(clk), .RN(n1735), .Q(
DMP_SFG[16]), .QN(n1689) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n749), .CK(clk), .RN(n1746), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n748), .CK(clk), .RN(n1735), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_17_ ( .D(n747), .CK(clk), .RN(n1746), .Q(
DMP_SFG[17]), .QN(n1703) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n746), .CK(clk), .RN(n1735), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n745), .CK(clk), .RN(n1746), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_18_ ( .D(n744), .CK(clk), .RN(n1735), .Q(
DMP_SFG[18]), .QN(n1702) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n743), .CK(clk), .RN(n1746), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n742), .CK(clk), .RN(n1735), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_19_ ( .D(n741), .CK(clk), .RN(n1005), .Q(
DMP_SFG[19]), .QN(n1709) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n740), .CK(clk), .RN(n1736), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n739), .CK(clk), .RN(n1736), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_20_ ( .D(n738), .CK(clk), .RN(n1733), .Q(
DMP_SFG[20]), .QN(n1708) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n737), .CK(clk), .RN(n1732), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n736), .CK(clk), .RN(n1743), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_21_ ( .D(n735), .CK(clk), .RN(n956), .Q(
DMP_SFG[21]), .QN(n1718) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n734), .CK(clk), .RN(n1733), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n733), .CK(clk), .RN(n1733), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_22_ ( .D(n732), .CK(clk), .RN(n1736), .Q(
DMP_SFG[22]), .QN(n1717) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n731), .CK(clk), .RN(n1005), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n730), .CK(clk), .RN(n1732), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(n729), .CK(clk), .RN(n956), .Q(
DMP_SFG[23]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n728), .CK(clk), .RN(n1743), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n726), .CK(clk), .RN(n1733), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n725), .CK(clk), .RN(n1743), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(n724), .CK(clk), .RN(n1005), .Q(
DMP_SFG[24]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n723), .CK(clk), .RN(n1736), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n721), .CK(clk), .RN(n1736), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n720), .CK(clk), .RN(n1732), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(n719), .CK(clk), .RN(n1743), .Q(
DMP_SFG[25]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n718), .CK(clk), .RN(n1736), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n716), .CK(clk), .RN(n1732), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n715), .CK(clk), .RN(n956), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(n714), .CK(clk), .RN(n1738), .Q(
DMP_SFG[26]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n713), .CK(clk), .RN(n1738), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n711), .CK(clk), .RN(n1738), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n710), .CK(clk), .RN(n1738), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(n709), .CK(clk), .RN(n1738), .Q(
DMP_SFG[27]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n708), .CK(clk), .RN(n1738), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n706), .CK(clk), .RN(n1738), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n705), .CK(clk), .RN(n1738), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(n704), .CK(clk), .RN(n1738), .Q(
DMP_SFG[28]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n703), .CK(clk), .RN(n1738), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n701), .CK(clk), .RN(n1738), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n700), .CK(clk), .RN(n1738), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(n699), .CK(clk), .RN(n1739), .Q(
DMP_SFG[29]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n698), .CK(clk), .RN(n1739), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n696), .CK(clk), .RN(n1739), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n695), .CK(clk), .RN(n1739), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(n694), .CK(clk), .RN(n1739), .Q(
DMP_SFG[30]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n693), .CK(clk), .RN(n1739), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n691), .CK(clk), .RN(n1739), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n690), .CK(clk), .RN(n1739), .QN(
n972) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n689), .CK(clk), .RN(n1739), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n687), .CK(clk), .RN(n1739), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n685), .CK(clk), .RN(n1740), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n683), .CK(clk), .RN(n1740), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n682), .CK(clk), .RN(n1740), .QN(
n975) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n681), .CK(clk), .RN(n1740), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n680), .CK(clk), .RN(n1740), .QN(
n973) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n679), .CK(clk), .RN(n1740), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n677), .CK(clk), .RN(n1740), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n675), .CK(clk), .RN(n1740), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n673), .CK(clk), .RN(n1739), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n672), .CK(clk), .RN(n1743), .QN(
n959) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n671), .CK(clk), .RN(n1731), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n669), .CK(clk), .RN(n1736), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n668), .CK(clk), .RN(n1740),
.QN(n974) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n667), .CK(clk), .RN(n1733), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n665), .CK(clk), .RN(n1736), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n664), .CK(clk), .RN(n1729),
.QN(n960) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n663), .CK(clk), .RN(n1727), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n661), .CK(clk), .RN(n1745), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n660), .CK(clk), .RN(n1738),
.QN(n968) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n659), .CK(clk), .RN(n1745), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n657), .CK(clk), .RN(n1744), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n655), .CK(clk), .RN(n1729), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n653), .CK(clk), .RN(n1741), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n652), .CK(clk), .RN(n1739),
.QN(n969) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n651), .CK(clk), .RN(n1731), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n649), .CK(clk), .RN(n1741), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n647), .CK(clk), .RN(n1741), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_23_ ( .D(n645), .CK(clk), .RN(n1741), .Q(
DmP_EXP_EWSW[23]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n640), .CK(clk), .RN(n1741), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n639), .CK(clk), .RN(n1747), .Q(
overflow_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n638), .CK(clk), .RN(n1741), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n637), .CK(clk), .RN(n1741), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n636), .CK(clk), .RN(n1742), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n635), .CK(clk), .RN(n1742), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n634), .CK(clk), .RN(n1742), .Q(
ZERO_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n633), .CK(clk), .RN(n1742), .Q(
zero_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n632), .CK(clk), .RN(n1742), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n631), .CK(clk), .RN(n1742), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n629), .CK(clk), .RN(n1742), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n628), .CK(clk), .RN(n1742), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n627), .CK(clk), .RN(n1742), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n626), .CK(clk), .RN(n1742), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n625), .CK(clk), .RN(n1742), .Q(
SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n624), .CK(clk), .RN(n1747), .Q(
final_result_ieee[31]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n612), .CK(clk), .RN(n1733), .Q(
DmP_mant_SFG_SWR[14]), .QN(n996) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n610), .CK(clk), .RN(n1736), .Q(
LZD_output_NRM2_EW[4]), .QN(n1672) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n609), .CK(clk), .RN(n1729), .Q(
DmP_mant_SFG_SWR[1]), .QN(n997) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n607), .CK(clk), .RN(n1732), .Q(
LZD_output_NRM2_EW[2]), .QN(n1669) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n604), .CK(clk), .RN(n1736), .Q(
LZD_output_NRM2_EW[1]), .QN(n1663) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n603), .CK(clk), .RN(n1746), .Q(
DmP_mant_SFG_SWR[0]), .QN(n999) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n602), .CK(clk), .RN(n1721), .QN(
n965) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n598), .CK(clk), .RN(n1733), .Q(
LZD_output_NRM2_EW[3]), .QN(n1673) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n595), .CK(clk), .RN(n1730), .Q(
DmP_mant_SFG_SWR[6]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n593), .CK(clk), .RN(n1743), .Q(
LZD_output_NRM2_EW[0]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n592), .CK(clk), .RN(n1743), .Q(
DmP_mant_SFG_SWR[4]), .QN(n1001) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n590), .CK(clk), .RN(n1747), .Q(
DmP_mant_SFG_SWR[5]), .QN(n1000) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n588), .CK(clk), .RN(n1745), .Q(
DmP_mant_SFG_SWR[7]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n586), .CK(clk), .RN(n1743), .Q(
DmP_mant_SFG_SWR[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n583), .CK(clk), .RN(n1735), .Q(
final_result_ieee[10]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n580), .CK(clk), .RN(n1744), .Q(
DmP_mant_SFG_SWR[11]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n578), .CK(clk), .RN(n1744), .Q(
DmP_mant_SFG_SWR[10]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n577), .CK(clk), .RN(n1744), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n576), .CK(clk), .RN(n1744), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n574), .CK(clk), .RN(n1744), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n573), .CK(clk), .RN(n1744), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n572), .CK(clk), .RN(n1744), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n571), .CK(clk), .RN(n1744), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n570), .CK(clk), .RN(n1745), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n569), .CK(clk), .RN(n1729), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n568), .CK(clk), .RN(n1745), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n567), .CK(clk), .RN(n1729), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n566), .CK(clk), .RN(n1745), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n565), .CK(clk), .RN(n1729), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n564), .CK(clk), .RN(n1745), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n563), .CK(clk), .RN(n1729), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n562), .CK(clk), .RN(n1745), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n561), .CK(clk), .RN(n1729), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n560), .CK(clk), .RN(n1745), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n559), .CK(clk), .RN(n1729), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n558), .CK(clk), .RN(n1746), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n557), .CK(clk), .RN(n1735), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n556), .CK(clk), .RN(n1746), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n555), .CK(clk), .RN(n1735), .Q(
final_result_ieee[22]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n554), .CK(clk), .RN(n1746), .Q(
DmP_mant_SFG_SWR[15]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n553), .CK(clk), .RN(n1735), .Q(
DmP_mant_SFG_SWR[16]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n552), .CK(clk), .RN(n1735), .Q(
DmP_mant_SFG_SWR[17]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n551), .CK(clk), .RN(n1746), .Q(
DmP_mant_SFG_SWR[18]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n550), .CK(clk), .RN(n1746), .Q(
DmP_mant_SFG_SWR[19]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n549), .CK(clk), .RN(n1735), .Q(
DmP_mant_SFG_SWR[20]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n548), .CK(clk), .RN(n1735), .Q(
DmP_mant_SFG_SWR[21]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n545), .CK(clk), .RN(n1747), .Q(
DmP_mant_SFG_SWR[24]), .QN(n993) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n544), .CK(clk), .RN(n1747), .Q(
DmP_mant_SFG_SWR[25]), .QN(n994) );
CMPR32X2TS intadd_5_U11 ( .A(n1668), .B(intadd_5_B_0_), .C(intadd_5_CI),
.CO(intadd_5_n10), .S(intadd_5_SUM_0_) );
CMPR32X2TS intadd_5_U10 ( .A(n1671), .B(intadd_5_B_1_), .C(intadd_5_n10),
.CO(intadd_5_n9), .S(intadd_5_SUM_1_) );
CMPR32X2TS intadd_5_U9 ( .A(n1690), .B(intadd_5_B_2_), .C(intadd_5_n9), .CO(
intadd_5_n8), .S(intadd_5_SUM_2_) );
CMPR32X2TS intadd_5_U8 ( .A(n1689), .B(intadd_5_B_3_), .C(intadd_5_n8), .CO(
intadd_5_n7), .S(intadd_5_SUM_3_) );
CMPR32X2TS intadd_5_U7 ( .A(n1703), .B(intadd_5_B_4_), .C(intadd_5_n7), .CO(
intadd_5_n6), .S(intadd_5_SUM_4_) );
CMPR32X2TS intadd_5_U6 ( .A(n1702), .B(intadd_5_B_5_), .C(intadd_5_n6), .CO(
intadd_5_n5), .S(intadd_5_SUM_5_) );
CMPR32X2TS intadd_5_U5 ( .A(n1709), .B(intadd_5_B_6_), .C(intadd_5_n5), .CO(
intadd_5_n4), .S(intadd_5_SUM_6_) );
CMPR32X2TS intadd_5_U4 ( .A(n1708), .B(intadd_5_B_7_), .C(intadd_5_n4), .CO(
intadd_5_n3), .S(intadd_5_SUM_7_) );
CMPR32X2TS intadd_5_U3 ( .A(n1718), .B(intadd_5_B_8_), .C(intadd_5_n3), .CO(
intadd_5_n2), .S(intadd_5_SUM_8_) );
CMPR32X2TS intadd_5_U2 ( .A(n1717), .B(intadd_5_B_9_), .C(intadd_5_n2), .CO(
intadd_5_n1), .S(intadd_5_SUM_9_) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n872), .CK(clk), .RN(n1726), .Q(
Data_array_SWR[19]), .QN(n1715) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n643), .CK(clk), .RN(n1741), .Q(
DmP_EXP_EWSW[25]), .QN(n1714) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n808), .CK(clk), .RN(n1731), .Q(
DMP_EXP_EWSW[26]), .QN(n1713) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n919), .CK(clk), .RN(n1734),
.Q(intDX_EWSW[24]), .QN(n1712) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n864), .CK(clk), .RN(n1728), .Q(
Data_array_SWR[12]), .QN(n1711) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n642), .CK(clk), .RN(n1741), .Q(
DmP_EXP_EWSW[26]), .QN(n1710) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n692), .CK(clk), .RN(n1747), .Q(
DMP_exp_NRM2_EW[7]), .QN(n1707) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n809), .CK(clk), .RN(n1731), .Q(
DMP_EXP_EWSW[25]), .QN(n1706) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n863), .CK(clk), .RN(n1726), .Q(
Data_array_SWR[11]), .QN(n1705) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n862), .CK(clk), .RN(n1733), .Q(
Data_array_SWR[10]), .QN(n1704) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n871), .CK(clk), .RN(n1729), .Q(
Data_array_SWR[18]), .QN(n1701) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n599), .CK(clk), .RN(n1005), .Q(
Raw_mant_NRM_SWR[3]), .QN(n1700) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n891), .CK(clk), .RN(n1726),
.Q(intDY_EWSW[18]), .QN(n1699) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n915), .CK(clk), .RN(n1727),
.Q(intDX_EWSW[28]), .QN(n1698) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n870), .CK(clk), .RN(n1730), .Q(
Data_array_SWR[17]), .QN(n1697) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n901), .CK(clk), .RN(n1726), .Q(
intDY_EWSW[8]), .QN(n1696) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n908), .CK(clk), .RN(n1721), .Q(
intDY_EWSW[1]), .QN(n1695) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n892), .CK(clk), .RN(n1744),
.Q(intDY_EWSW[17]), .QN(n1694) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n909), .CK(clk), .RN(n1722), .Q(
intDY_EWSW[0]), .QN(n1693) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n884), .CK(clk), .RN(n1728),
.Q(intDY_EWSW[25]), .QN(n1692) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n883), .CK(clk), .RN(n1725),
.Q(intDY_EWSW[26]), .QN(n1691) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n702), .CK(clk), .RN(n1732), .Q(
DMP_exp_NRM2_EW[5]), .QN(n1688) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n697), .CK(clk), .RN(n1746), .Q(
DMP_exp_NRM2_EW[6]), .QN(n1687) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n886), .CK(clk), .RN(n1729),
.Q(intDY_EWSW[23]), .QN(n1686) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n914), .CK(clk), .RN(n1721),
.Q(intDX_EWSW[29]), .QN(n1685) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n902), .CK(clk), .RN(n1728), .Q(
intDY_EWSW[7]), .QN(n1684) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n882), .CK(clk), .RN(n1723),
.Q(intDY_EWSW[27]), .QN(n1683) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n895), .CK(clk), .RN(n1729),
.Q(intDY_EWSW[14]), .QN(n1681) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n897), .CK(clk), .RN(n1731),
.Q(intDY_EWSW[12]), .QN(n1680) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n905), .CK(clk), .RN(n1745), .Q(
intDY_EWSW[4]), .QN(n1679) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n907), .CK(clk), .RN(n1730), .Q(
intDY_EWSW[2]), .QN(n1678) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n896), .CK(clk), .RN(n1728),
.Q(intDY_EWSW[13]), .QN(n1676) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n900), .CK(clk), .RN(n1738), .Q(
intDY_EWSW[9]), .QN(n1675) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n903), .CK(clk), .RN(n1726), .Q(
intDY_EWSW[6]), .QN(n1674) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n951), .CK(clk), .RN(
n1724), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n1670) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n879), .CK(clk), .RN(n1730),
.Q(intDY_EWSW[30]), .QN(n1667) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n927), .CK(clk), .RN(n1723),
.Q(intDX_EWSW[16]), .QN(n1665) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n587), .CK(clk), .RN(n1740), .Q(
Raw_mant_NRM_SWR[9]), .QN(n1664) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n727), .CK(clk), .RN(n1006), .Q(
DMP_exp_NRM2_EW[0]), .QN(n1662) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n937), .CK(clk), .RN(n1730), .Q(
intDX_EWSW[6]), .QN(n1660) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n594), .CK(clk), .RN(n1743), .Q(
Raw_mant_NRM_SWR[6]), .QN(n1659) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n938), .CK(clk), .RN(n1724), .Q(
intDX_EWSW[5]), .QN(n1658) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n600), .CK(clk), .RN(n1740), .Q(
Raw_mant_NRM_SWR[2]), .QN(n1657) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n585), .CK(clk), .RN(n1723), .Q(
Raw_mant_NRM_SWR[10]), .QN(n1656) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n848), .CK(clk), .RN(n1721), .Q(
shift_value_SHT2_EWR[4]), .QN(n1655) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n589), .CK(clk), .RN(n1741), .Q(
Raw_mant_NRM_SWR[7]), .QN(n1654) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n579), .CK(clk), .RN(n1744), .Q(
Raw_mant_NRM_SWR[12]), .QN(n1653) );
DFFRX2TS inst_ShiftRegister_Q_reg_5_ ( .D(n949), .CK(clk), .RN(n1730), .Q(
n1632), .QN(n1716) );
DFFRX1TS inst_ShiftRegister_Q_reg_4_ ( .D(n948), .CK(clk), .RN(n1721), .QN(
n1719) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n917), .CK(clk), .RN(n1724),
.Q(intDX_EWSW[26]), .QN(n1652) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n918), .CK(clk), .RN(n1730),
.Q(intDX_EWSW[25]), .QN(n1651) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n867), .CK(clk), .RN(n1735), .Q(
Data_array_SWR[15]), .QN(n1650) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n866), .CK(clk), .RN(n1745), .Q(
Data_array_SWR[14]), .QN(n1649) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n810), .CK(clk), .RN(n1731), .Q(
DMP_EXP_EWSW[24]), .QN(n1648) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n644), .CK(clk), .RN(n1741), .Q(
DmP_EXP_EWSW[24]), .QN(n1647) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n875), .CK(clk), .RN(n1725), .Q(
Data_array_SWR[21]), .QN(n1646) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n890), .CK(clk), .RN(n1726),
.Q(intDY_EWSW[19]), .QN(n1645) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n913), .CK(clk), .RN(n1727),
.Q(intDX_EWSW[30]), .QN(n1644) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n887), .CK(clk), .RN(n1726),
.Q(intDY_EWSW[22]), .QN(n1643) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n893), .CK(clk), .RN(n1725),
.Q(intDY_EWSW[16]), .QN(n1642) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n904), .CK(clk), .RN(n1725), .Q(
intDY_EWSW[5]), .QN(n1641) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n1723), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n1640) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n880), .CK(clk), .RN(n1734),
.Q(intDY_EWSW[29]), .QN(n1638) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n936), .CK(clk), .RN(n1723), .Q(
intDX_EWSW[7]), .QN(n1637) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n939), .CK(clk), .RN(n1734), .Q(
intDX_EWSW[4]), .QN(n1636) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n596), .CK(clk), .RN(n1733), .Q(
Raw_mant_NRM_SWR[4]), .QN(n1635) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n575), .CK(clk), .RN(n1744), .Q(
Raw_mant_NRM_SWR[11]), .QN(n1634) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n611), .CK(clk), .RN(n1736), .Q(
Raw_mant_NRM_SWR[14]), .QN(n1633) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n622), .CK(clk), .RN(n1735), .Q(
Raw_mant_NRM_SWR[16]), .QN(n1631) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n874), .CK(clk), .RN(n1727), .Q(
Data_array_SWR[20]), .QN(n1630) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n885), .CK(clk), .RN(n1728),
.Q(intDY_EWSW[24]), .QN(n1629) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n621), .CK(clk), .RN(n956), .Q(
Raw_mant_NRM_SWR[17]), .QN(n1628) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n617), .CK(clk), .RN(n956), .Q(
Raw_mant_NRM_SWR[21]), .QN(n1627) );
DFFRX2TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n630), .CK(clk), .RN(n1745), .Q(n1002), .QN(n1639) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n613), .CK(clk), .RN(n1743), .Q(
Raw_mant_NRM_SWR[25]), .QN(n1626) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n616), .CK(clk), .RN(n956), .Q(
Raw_mant_NRM_SWR[22]), .QN(n1625) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n920), .CK(clk), .RN(n1724),
.Q(intDX_EWSW[23]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n930), .CK(clk), .RN(n1721),
.Q(intDX_EWSW[13]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n940), .CK(clk), .RN(n1727), .Q(
intDX_EWSW[3]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n928), .CK(clk), .RN(n1727),
.Q(intDX_EWSW[15]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n922), .CK(clk), .RN(n1721),
.Q(intDX_EWSW[21]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n876), .CK(clk), .RN(n1722), .Q(
Data_array_SWR[22]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n618), .CK(clk), .RN(n1006), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n926), .CK(clk), .RN(n1722),
.Q(intDX_EWSW[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n877), .CK(clk), .RN(n1726), .Q(
Data_array_SWR[23]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n932), .CK(clk), .RN(n1722),
.Q(intDX_EWSW[11]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n934), .CK(clk), .RN(n1730), .Q(
intDX_EWSW[9]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n935), .CK(clk), .RN(n1723), .Q(
intDX_EWSW[8]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n916), .CK(clk), .RN(n1722),
.Q(intDX_EWSW[27]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n865), .CK(clk), .RN(n1725), .Q(
Data_array_SWR[13]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n619), .CK(clk), .RN(n956), .Q(
Raw_mant_NRM_SWR[19]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n943), .CK(clk), .RN(n1727), .Q(
intDX_EWSW[0]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n925), .CK(clk), .RN(n1730),
.Q(intDX_EWSW[18]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n581), .CK(clk), .RN(n1744), .Q(
Raw_mant_NRM_SWR[13]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n605), .CK(clk), .RN(n956), .Q(
Raw_mant_NRM_SWR[8]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n623), .CK(clk), .RN(n956), .Q(
Raw_mant_NRM_SWR[15]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n608), .CK(clk), .RN(n1741), .Q(
Raw_mant_NRM_SWR[1]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n591), .CK(clk), .RN(n1733), .Q(
Raw_mant_NRM_SWR[5]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n952), .CK(clk), .RN(
n1724), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n860), .CK(clk), .RN(n1735), .Q(
Data_array_SWR[8]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n868), .CK(clk), .RN(n1726), .Q(
Data_array_SWR[16]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n620), .CK(clk), .RN(n956), .Q(
Raw_mant_NRM_SWR[18]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n856), .CK(clk), .RN(n1729), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n857), .CK(clk), .RN(n1728), .Q(
Data_array_SWR[5]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n615), .CK(clk), .RN(n956), .Q(
Raw_mant_NRM_SWR[23]), .QN(n961) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n858), .CK(clk), .RN(n1725), .Q(
Data_array_SWR[6]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n859), .CK(clk), .RN(n1746), .Q(
Data_array_SWR[7]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_2_ ( .D(n792), .CK(clk), .RN(n1005), .Q(
DMP_SFG[2]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_12_ ( .D(n762), .CK(clk), .RN(n1734), .Q(
DMP_SFG[12]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n912), .CK(clk), .RN(n1723),
.Q(intDX_EWSW[31]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n850), .CK(clk), .RN(n1730), .Q(
shift_value_SHT2_EWR[3]), .QN(n1666) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_8_ ( .D(n774), .CK(clk), .RN(n1006), .Q(
DMP_SFG[8]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n795), .CK(clk), .RN(n956), .Q(
DMP_SFG[1]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n614), .CK(clk), .RN(n1005), .Q(
Raw_mant_NRM_SWR[24]), .QN(n995) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n646), .CK(clk), .RN(n1741), .Q(
DmP_mant_SHT1_SW[22]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n658), .CK(clk), .RN(n1740), .Q(
DmP_mant_SHT1_SW[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n656), .CK(clk), .RN(n1723), .Q(
DmP_mant_SHT1_SW[17]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n676), .CK(clk), .RN(n1740), .Q(
DmP_mant_SHT1_SW[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n684), .CK(clk), .RN(n1740), .Q(
DmP_mant_SHT1_SW[3]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n654), .CK(clk), .RN(n1724), .Q(
DmP_mant_SHT1_SW[18]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n666), .CK(clk), .RN(n1723), .Q(
DmP_mant_SHT1_SW[12]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n670), .CK(clk), .RN(n1724), .Q(
DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n674), .CK(clk), .RN(n1740), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n899), .CK(clk), .RN(n1726),
.Q(intDY_EWSW[10]), .QN(n957) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n650), .CK(clk), .RN(n1730), .Q(
DmP_mant_SHT1_SW[20]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n662), .CK(clk), .RN(n1730), .Q(
DmP_mant_SHT1_SW[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n648), .CK(clk), .RN(n1741), .Q(
DmP_mant_SHT1_SW[21]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n678), .CK(clk), .RN(n1740), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n686), .CK(clk), .RN(n1739), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n688), .CK(clk), .RN(n1739), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n777), .CK(clk), .RN(n1006), .Q(
DMP_SFG[7]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_11_ ( .D(n765), .CK(clk), .RN(n1722), .Q(
DMP_SFG[11]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_4_ ( .D(n786), .CK(clk), .RN(n1730), .Q(
DMP_SFG[4]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_3_ ( .D(n789), .CK(clk), .RN(n1724), .Q(
DMP_SFG[3]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n582), .CK(clk), .RN(n1744), .Q(
DmP_mant_SFG_SWR[13]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n584), .CK(clk), .RN(n1747), .Q(
DmP_mant_SFG_SWR[12]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n597), .CK(clk), .RN(n1005), .Q(
DmP_mant_SFG_SWR[3]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n601), .CK(clk), .RN(n956), .Q(
DmP_mant_SFG_SWR[2]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_10_ ( .D(n768), .CK(clk), .RN(n1732), .Q(
DMP_SFG[10]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_6_ ( .D(n780), .CK(clk), .RN(n1743), .Q(
DMP_SFG[6]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n798), .CK(clk), .RN(n956), .Q(
DMP_SFG[0]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n771), .CK(clk), .RN(n1722), .Q(
DMP_SFG[9]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n546), .CK(clk), .RN(n1747), .Q(
DmP_mant_SFG_SWR[23]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n547), .CK(clk), .RN(n1746), .Q(
DmP_mant_SFG_SWR[22]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n847), .CK(clk), .RN(n1738),
.Q(Shift_amount_SHT1_EWR[0]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n783), .CK(clk), .RN(n1736), .Q(
DMP_SFG[5]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n894), .CK(clk), .RN(n1745),
.Q(intDY_EWSW[15]), .QN(n1752) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n889), .CK(clk), .RN(n1728),
.Q(intDY_EWSW[20]), .QN(n1682) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n888), .CK(clk), .RN(n1739),
.Q(intDY_EWSW[21]), .QN(n1677) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n811), .CK(clk), .RN(n1731), .Q(
DMP_EXP_EWSW[23]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n712), .CK(clk), .RN(n1733), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n717), .CK(clk), .RN(n1006), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n722), .CK(clk), .RN(n1006), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n878), .CK(clk), .RN(n1724),
.Q(intDY_EWSW[31]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n931), .CK(clk), .RN(n1724),
.Q(intDX_EWSW[12]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n923), .CK(clk), .RN(n1723),
.Q(intDX_EWSW[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n929), .CK(clk), .RN(n1724),
.Q(intDX_EWSW[14]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n921), .CK(clk), .RN(n1727),
.Q(intDX_EWSW[22]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n942), .CK(clk), .RN(n1727), .Q(
intDX_EWSW[1]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n906), .CK(clk), .RN(n1725), .Q(
intDY_EWSW[3]), .QN(n1750) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n881), .CK(clk), .RN(n1723),
.Q(intDY_EWSW[28]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n898), .CK(clk), .RN(n1746),
.Q(intDY_EWSW[11]), .QN(n1751) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n924), .CK(clk), .RN(n1727),
.Q(intDX_EWSW[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n861), .CK(clk), .RN(n1747), .Q(
Data_array_SWR[9]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n851), .CK(clk), .RN(n1723), .Q(
shift_value_SHT2_EWR[2]), .QN(n1661) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n852), .CK(clk), .RN(n1724), .Q(
Data_array_SWR[0]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n707), .CK(clk), .RN(n1732), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n853), .CK(clk), .RN(n1724), .Q(
Data_array_SWR[1]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n641), .CK(clk), .RN(n1741), .Q(
DmP_EXP_EWSW[27]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n606), .CK(clk), .RN(n1733), .Q(
DmP_mant_SFG_SWR[8]), .QN(n998) );
ADDFX1TS DP_OP_15J11_123_2691_U8 ( .A(n1663), .B(DMP_exp_NRM2_EW[1]), .CI(
DP_OP_15J11_123_2691_n8), .CO(DP_OP_15J11_123_2691_n7), .S(
exp_rslt_NRM2_EW1[1]) );
ADDFX1TS DP_OP_15J11_123_2691_U7 ( .A(n1669), .B(DMP_exp_NRM2_EW[2]), .CI(
DP_OP_15J11_123_2691_n7), .CO(DP_OP_15J11_123_2691_n6), .S(
exp_rslt_NRM2_EW1[2]) );
ADDFX1TS DP_OP_15J11_123_2691_U6 ( .A(n1673), .B(DMP_exp_NRM2_EW[3]), .CI(
DP_OP_15J11_123_2691_n6), .CO(DP_OP_15J11_123_2691_n5), .S(
exp_rslt_NRM2_EW1[3]) );
ADDFX1TS DP_OP_15J11_123_2691_U5 ( .A(n1672), .B(DMP_exp_NRM2_EW[4]), .CI(
DP_OP_15J11_123_2691_n5), .CO(DP_OP_15J11_123_2691_n4), .S(
exp_rslt_NRM2_EW1[4]) );
DFFRX4TS inst_ShiftRegister_Q_reg_1_ ( .D(n945), .CK(clk), .RN(n1724), .Q(
Shift_reg_FLAGS_7[1]), .QN(n954) );
DFFRX4TS inst_ShiftRegister_Q_reg_6_ ( .D(n950), .CK(clk), .RN(n1734), .Q(
Shift_reg_FLAGS_7_6), .QN(n1003) );
DFFRX4TS inst_ShiftRegister_Q_reg_0_ ( .D(n944), .CK(clk), .RN(n1727), .Q(
Shift_reg_FLAGS_7[0]) );
DFFRX4TS inst_ShiftRegister_Q_reg_2_ ( .D(n946), .CK(clk), .RN(n1727), .Q(
n953), .QN(n1748) );
CLKINVX6TS U964 ( .A(rst), .Y(n1005) );
AOI211X1TS U965 ( .A0(n1456), .A1(Data_array_SWR[3]), .B0(n1455), .C0(n1454),
.Y(n1590) );
AOI211X1TS U966 ( .A0(n1456), .A1(Data_array_SWR[2]), .B0(n1451), .C0(n1450),
.Y(n1593) );
CMPR32X2TS U967 ( .A(DMP_SFG[1]), .B(n1020), .C(n1461), .CO(n1474), .S(n1007) );
AOI222X4TS U968 ( .A0(n989), .A1(n1471), .B0(n990), .B1(n1470), .C0(
Data_array_SWR[23]), .C1(n1445), .Y(n1436) );
INVX6TS U969 ( .A(n1354), .Y(n955) );
CLKINVX6TS U970 ( .A(n1373), .Y(n1221) );
AOI31XLTS U971 ( .A0(n1205), .A1(Raw_mant_NRM_SWR[8]), .A2(n1664), .B0(n1330), .Y(n1206) );
AND2X4TS U972 ( .A(Shift_reg_FLAGS_7_6), .B(n1085), .Y(n1095) );
CLKINVX3TS U973 ( .A(n1344), .Y(n1347) );
CLKINVX3TS U974 ( .A(n1349), .Y(n1348) );
BUFX6TS U975 ( .A(n1403), .Y(n1617) );
INVX6TS U976 ( .A(n1379), .Y(n1210) );
CLKINVX3TS U977 ( .A(n1544), .Y(n1420) );
NOR2X6TS U978 ( .A(shift_value_SHT2_EWR[4]), .B(n1453), .Y(n1421) );
INVX6TS U979 ( .A(Shift_reg_FLAGS_7_6), .Y(n1086) );
CLKINVX3TS U980 ( .A(n1543), .Y(n1429) );
BUFX6TS U981 ( .A(n1639), .Y(n1505) );
BUFX6TS U982 ( .A(n1005), .Y(n956) );
NAND2BXLTS U983 ( .AN(n992), .B(intDY_EWSW[2]), .Y(n1034) );
NAND2BXLTS U984 ( .AN(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n1068) );
NAND2BXLTS U985 ( .AN(intDX_EWSW[27]), .B(intDY_EWSW[27]), .Y(n1022) );
NAND2BXLTS U986 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n1047) );
OAI2BB2XLTS U987 ( .B0(intDY_EWSW[14]), .B1(n1053), .A0N(intDX_EWSW[15]),
.A1N(n1752), .Y(n1054) );
NAND2BXLTS U988 ( .AN(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n1043) );
NAND2BXLTS U989 ( .AN(intDX_EWSW[21]), .B(intDY_EWSW[21]), .Y(n1062) );
AO22XLTS U990 ( .A0(DmP_mant_SFG_SWR[4]), .A1(n1506), .B0(n1505), .B1(n1001),
.Y(n966) );
AOI222X4TS U991 ( .A0(n989), .A1(n1420), .B0(n990), .B1(n1421), .C0(
Data_array_SWR[23]), .C1(n1429), .Y(n1519) );
NAND2BXLTS U992 ( .AN(n1333), .B(n1014), .Y(n1017) );
AOI222X1TS U993 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n955), .B0(n1363), .B1(
DmP_mant_SHT1_SW[7]), .C0(n1362), .C1(DmP_mant_SHT1_SW[8]), .Y(n1260)
);
AOI222X1TS U994 ( .A0(DMP_SFG[12]), .A1(n976), .B0(DMP_SFG[12]), .B1(n1311),
.C0(n976), .C1(n1311), .Y(intadd_5_B_0_) );
AOI211X1TS U995 ( .A0(DmP_mant_SHT1_SW[22]), .A1(n954), .B0(n1362), .C0(
n1351), .Y(n1356) );
AOI222X1TS U996 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n955), .B0(n1363), .B1(n982), .C0(n1362), .C1(DmP_mant_SHT1_SW[14]), .Y(n1253) );
AOI31X1TS U997 ( .A0(n977), .A1(DMP_SFG[2]), .A2(n1463), .B0(n1473), .Y(
n1483) );
AOI222X1TS U998 ( .A0(Raw_mant_NRM_SWR[14]), .A1(n955), .B0(n1363), .B1(n984), .C0(n1362), .C1(DmP_mant_SHT1_SW[10]), .Y(n1269) );
AOI222X1TS U999 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n955), .B0(n1363), .B1(n983), .C0(n1362), .C1(DmP_mant_SHT1_SW[12]), .Y(n1266) );
AOI222X1TS U1000 ( .A0(n1570), .A1(n1621), .B0(Data_array_SWR[9]), .B1(n1588), .C0(n1569), .C1(n1586), .Y(n1602) );
AOI222X1TS U1001 ( .A0(n1570), .A1(n1592), .B0(n1622), .B1(Data_array_SWR[9]), .C0(n1569), .C1(n1503), .Y(n1568) );
INVX4TS U1002 ( .A(n1618), .Y(n1613) );
BUFX4TS U1003 ( .A(n1719), .Y(n1404) );
AOI222X1TS U1004 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n955), .B0(n1363), .B1(
DmP_mant_SHT1_SW[2]), .C0(n1362), .C1(DmP_mant_SHT1_SW[3]), .Y(n1280)
);
AOI222X1TS U1005 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n955), .B0(n1363), .B1(
DmP_mant_SHT1_SW[3]), .C0(n1362), .C1(n979), .Y(n1276) );
AOI222X1TS U1006 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n955), .B0(n1363), .B1(n981), .C0(n1362), .C1(DmP_mant_SHT1_SW[16]), .Y(n1250) );
AOI222X1TS U1007 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n955), .B0(
DmP_mant_SHT1_SW[20]), .B1(n1362), .C0(n1363), .C1(n980), .Y(n1261) );
AO22XLTS U1008 ( .A0(n1521), .A1(DMP_SHT2_EWSW[5]), .B0(n1618), .B1(
DMP_SFG[5]), .Y(n783) );
AO22XLTS U1009 ( .A0(n1616), .A1(DMP_SHT2_EWSW[9]), .B0(n1617), .B1(
DMP_SFG[9]), .Y(n771) );
AO22XLTS U1010 ( .A0(n1521), .A1(DMP_SHT2_EWSW[0]), .B0(n1618), .B1(
DMP_SFG[0]), .Y(n798) );
AO22XLTS U1011 ( .A0(n1616), .A1(DMP_SHT2_EWSW[6]), .B0(n1618), .B1(
DMP_SFG[6]), .Y(n780) );
AO22XLTS U1012 ( .A0(n1521), .A1(DMP_SHT2_EWSW[10]), .B0(n1520), .B1(
DMP_SFG[10]), .Y(n768) );
AO22XLTS U1013 ( .A0(n1521), .A1(n1584), .B0(n1520), .B1(DmP_mant_SFG_SWR[2]), .Y(n601) );
AO22XLTS U1014 ( .A0(n1521), .A1(n1583), .B0(n1520), .B1(DmP_mant_SFG_SWR[3]), .Y(n597) );
AO22XLTS U1015 ( .A0(n1521), .A1(n1516), .B0(n1520), .B1(
DmP_mant_SFG_SWR[12]), .Y(n584) );
AO22XLTS U1016 ( .A0(n1521), .A1(n1567), .B0(n1520), .B1(
DmP_mant_SFG_SWR[13]), .Y(n582) );
AO22XLTS U1017 ( .A0(n1616), .A1(DMP_SHT2_EWSW[3]), .B0(n1618), .B1(
DMP_SFG[3]), .Y(n789) );
AO22XLTS U1018 ( .A0(n1616), .A1(DMP_SHT2_EWSW[4]), .B0(n1618), .B1(
DMP_SFG[4]), .Y(n786) );
AO22XLTS U1019 ( .A0(n1616), .A1(DMP_SHT2_EWSW[11]), .B0(n1403), .B1(
DMP_SFG[11]), .Y(n765) );
AO22XLTS U1020 ( .A0(n1411), .A1(DmP_EXP_EWSW[1]), .B0(n1405), .B1(
DmP_mant_SHT1_SW[1]), .Y(n688) );
AO22XLTS U1021 ( .A0(n1411), .A1(DmP_EXP_EWSW[2]), .B0(n1415), .B1(
DmP_mant_SHT1_SW[2]), .Y(n686) );
AO22XLTS U1022 ( .A0(n1411), .A1(DmP_EXP_EWSW[6]), .B0(n1413), .B1(
DmP_mant_SHT1_SW[6]), .Y(n678) );
AO22XLTS U1023 ( .A0(n1411), .A1(DmP_EXP_EWSW[21]), .B0(n1405), .B1(
DmP_mant_SHT1_SW[21]), .Y(n648) );
AO22XLTS U1024 ( .A0(n1416), .A1(DmP_EXP_EWSW[20]), .B0(n1413), .B1(
DmP_mant_SHT1_SW[20]), .Y(n650) );
AO22XLTS U1025 ( .A0(n1411), .A1(DmP_EXP_EWSW[8]), .B0(n1415), .B1(
DmP_mant_SHT1_SW[8]), .Y(n674) );
AO22XLTS U1026 ( .A0(n1411), .A1(DmP_EXP_EWSW[10]), .B0(n1413), .B1(
DmP_mant_SHT1_SW[10]), .Y(n670) );
AO22XLTS U1027 ( .A0(n1411), .A1(DmP_EXP_EWSW[12]), .B0(n1405), .B1(
DmP_mant_SHT1_SW[12]), .Y(n666) );
AO22XLTS U1028 ( .A0(n1411), .A1(DmP_EXP_EWSW[18]), .B0(n1415), .B1(
DmP_mant_SHT1_SW[18]), .Y(n654) );
AO22XLTS U1029 ( .A0(n1411), .A1(DmP_EXP_EWSW[3]), .B0(n1716), .B1(
DmP_mant_SHT1_SW[3]), .Y(n684) );
AO22XLTS U1030 ( .A0(n1411), .A1(DmP_EXP_EWSW[7]), .B0(n1413), .B1(
DmP_mant_SHT1_SW[7]), .Y(n676) );
AO22XLTS U1031 ( .A0(n1416), .A1(DmP_EXP_EWSW[17]), .B0(n1413), .B1(
DmP_mant_SHT1_SW[17]), .Y(n656) );
AO22XLTS U1032 ( .A0(n1616), .A1(DMP_SHT2_EWSW[1]), .B0(n1618), .B1(
DMP_SFG[1]), .Y(n795) );
AO22XLTS U1033 ( .A0(n1521), .A1(DMP_SHT2_EWSW[8]), .B0(n1617), .B1(
DMP_SFG[8]), .Y(n774) );
AO22XLTS U1034 ( .A0(n1340), .A1(n1564), .B0(n1341), .B1(n978), .Y(n946) );
AO22XLTS U1035 ( .A0(n1345), .A1(Data_X[31]), .B0(n1343), .B1(intDX_EWSW[31]), .Y(n912) );
AO22XLTS U1036 ( .A0(n1521), .A1(DMP_SHT2_EWSW[12]), .B0(n1618), .B1(
DMP_SFG[12]), .Y(n762) );
AO22XLTS U1037 ( .A0(n1616), .A1(DMP_SHT2_EWSW[2]), .B0(n1618), .B1(
DMP_SFG[2]), .Y(n792) );
NAND2BXLTS U1038 ( .AN(n1525), .B(n1524), .Y(n1526) );
AO22XLTS U1039 ( .A0(n1416), .A1(DmP_EXP_EWSW[15]), .B0(n1405), .B1(n981),
.Y(n660) );
AO22XLTS U1040 ( .A0(n1416), .A1(DmP_EXP_EWSW[13]), .B0(n1415), .B1(n982),
.Y(n664) );
AO22XLTS U1041 ( .A0(n1411), .A1(DmP_EXP_EWSW[11]), .B0(n1716), .B1(n983),
.Y(n668) );
AO22XLTS U1042 ( .A0(n1411), .A1(DmP_EXP_EWSW[9]), .B0(n1413), .B1(n984),
.Y(n672) );
AO22XLTS U1043 ( .A0(n1411), .A1(DmP_EXP_EWSW[5]), .B0(n1413), .B1(n985),
.Y(n680) );
AO22XLTS U1044 ( .A0(n1411), .A1(DmP_EXP_EWSW[4]), .B0(n1415), .B1(n979),
.Y(n682) );
AO22XLTS U1045 ( .A0(n1411), .A1(DmP_EXP_EWSW[0]), .B0(n1413), .B1(n986),
.Y(n690) );
AO22XLTS U1046 ( .A0(n1341), .A1(busy), .B0(n1340), .B1(n978), .Y(n947) );
OA22X1TS U1047 ( .A0(n1505), .A1(DmP_mant_SFG_SWR[14]), .B0(n1002), .B1(n996), .Y(n962) );
BUFX3TS U1048 ( .A(n1005), .Y(n1732) );
NOR2BX2TS U1049 ( .AN(n1325), .B(n1324), .Y(n1200) );
NAND4XLTS U1050 ( .A(n1626), .B(n995), .C(n961), .D(n1625), .Y(n1324) );
AOI222X1TS U1051 ( .A0(n1589), .A1(n1592), .B0(n1622), .B1(Data_array_SWR[8]), .C0(n1587), .C1(n1503), .Y(n1585) );
CLKINVX3TS U1052 ( .A(n1591), .Y(n1622) );
AOI222X1TS U1053 ( .A0(n1589), .A1(n1621), .B0(Data_array_SWR[8]), .B1(n1588), .C0(n1587), .C1(n1586), .Y(n1604) );
CLKINVX3TS U1054 ( .A(n1548), .Y(n1588) );
BUFX4TS U1055 ( .A(n1743), .Y(n1738) );
BUFX4TS U1056 ( .A(n1745), .Y(n1747) );
BUFX4TS U1057 ( .A(n1744), .Y(n1735) );
BUFX4TS U1058 ( .A(n1741), .Y(n1746) );
BUFX4TS U1059 ( .A(n1736), .Y(n1745) );
BUFX4TS U1060 ( .A(n1736), .Y(n1729) );
BUFX4TS U1061 ( .A(n956), .Y(n1740) );
BUFX4TS U1062 ( .A(n1005), .Y(n1731) );
BUFX4TS U1063 ( .A(n956), .Y(n1739) );
NOR2X4TS U1064 ( .A(shift_value_SHT2_EWR[4]), .B(n1621), .Y(n1586) );
BUFX4TS U1065 ( .A(n1005), .Y(n1744) );
BUFX4TS U1066 ( .A(n1005), .Y(n1741) );
NOR2X4TS U1067 ( .A(shift_value_SHT2_EWR[4]), .B(n1592), .Y(n1503) );
BUFX6TS U1068 ( .A(n1403), .Y(n1618) );
CLKINVX6TS U1069 ( .A(n1405), .Y(n1414) );
BUFX6TS U1070 ( .A(n1716), .Y(n1413) );
BUFX4TS U1071 ( .A(n1728), .Y(n1724) );
BUFX4TS U1072 ( .A(n1005), .Y(n1733) );
BUFX4TS U1073 ( .A(n1005), .Y(n1736) );
BUFX4TS U1074 ( .A(n1005), .Y(n1743) );
NOR2X2TS U1075 ( .A(shift_value_SHT2_EWR[2]), .B(n1666), .Y(n1445) );
OAI22X2TS U1076 ( .A0(n1630), .A1(n1453), .B0(n1697), .B1(n1452), .Y(n1572)
);
OAI22X2TS U1077 ( .A0(n1646), .A1(n1453), .B0(n1701), .B1(n1452), .Y(n1581)
);
BUFX6TS U1078 ( .A(n1004), .Y(n1345) );
BUFX4TS U1079 ( .A(n1004), .Y(n1349) );
BUFX4TS U1080 ( .A(n1004), .Y(n1344) );
BUFX4TS U1081 ( .A(n1725), .Y(n1723) );
BUFX4TS U1082 ( .A(n1729), .Y(n1730) );
BUFX4TS U1083 ( .A(n1739), .Y(n1722) );
BUFX4TS U1084 ( .A(n1726), .Y(n1727) );
INVX2TS U1085 ( .A(n962), .Y(n976) );
INVX2TS U1086 ( .A(n966), .Y(n977) );
OR2X1TS U1087 ( .A(n954), .B(n1226), .Y(n1354) );
OAI211X2TS U1088 ( .A0(n1659), .A1(n1208), .B0(n1207), .C0(n1206), .Y(n1226)
);
NOR2X4TS U1089 ( .A(n1452), .B(shift_value_SHT2_EWR[4]), .Y(n1456) );
INVX2TS U1090 ( .A(n970), .Y(n978) );
INVX2TS U1091 ( .A(n975), .Y(n979) );
INVX2TS U1092 ( .A(n969), .Y(n980) );
INVX2TS U1093 ( .A(n968), .Y(n981) );
INVX2TS U1094 ( .A(n960), .Y(n982) );
INVX2TS U1095 ( .A(n974), .Y(n983) );
INVX2TS U1096 ( .A(n959), .Y(n984) );
INVX2TS U1097 ( .A(n973), .Y(n985) );
INVX2TS U1098 ( .A(n972), .Y(n986) );
INVX2TS U1099 ( .A(n971), .Y(n987) );
CLKINVX3TS U1100 ( .A(n1287), .Y(n1265) );
CLKINVX6TS U1101 ( .A(n1621), .Y(n1592) );
BUFX6TS U1102 ( .A(left_right_SHT2), .Y(n1621) );
INVX3TS U1103 ( .A(n1293), .Y(n1371) );
BUFX6TS U1104 ( .A(n1223), .Y(n1369) );
BUFX6TS U1105 ( .A(n1237), .Y(n1362) );
BUFX6TS U1106 ( .A(n1209), .Y(n1363) );
CLKINVX6TS U1107 ( .A(n1345), .Y(n1343) );
CLKINVX3TS U1108 ( .A(n1618), .Y(n1624) );
INVX2TS U1109 ( .A(n965), .Y(n988) );
INVX2TS U1110 ( .A(n958), .Y(n989) );
INVX2TS U1111 ( .A(n967), .Y(n990) );
AOI32X1TS U1112 ( .A0(n1699), .A1(n1068), .A2(intDX_EWSW[18]), .B0(
intDX_EWSW[19]), .B1(n1645), .Y(n1069) );
AOI221X1TS U1113 ( .A0(n1699), .A1(intDX_EWSW[18]), .B0(intDX_EWSW[19]),
.B1(n1645), .C0(n1148), .Y(n1153) );
AOI221X1TS U1114 ( .A0(n957), .A1(n991), .B0(intDX_EWSW[11]), .B1(n1751),
.C0(n1156), .Y(n1161) );
AOI221X1TS U1115 ( .A0(n1683), .A1(intDX_EWSW[27]), .B0(intDY_EWSW[28]),
.B1(n1698), .C0(n1141), .Y(n1145) );
INVX2TS U1116 ( .A(n964), .Y(n991) );
AOI221X1TS U1117 ( .A0(n1678), .A1(n992), .B0(intDX_EWSW[3]), .B1(n1750),
.C0(n1164), .Y(n1169) );
INVX2TS U1118 ( .A(n963), .Y(n992) );
AOI221X1TS U1119 ( .A0(n1695), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[17]), .B1(
n1694), .C0(n1147), .Y(n1154) );
AOI221X1TS U1120 ( .A0(n1643), .A1(intDX_EWSW[22]), .B0(intDX_EWSW[23]),
.B1(n1686), .C0(n1150), .Y(n1151) );
AOI221X1TS U1121 ( .A0(n1681), .A1(intDX_EWSW[14]), .B0(intDX_EWSW[15]),
.B1(n1752), .C0(n1158), .Y(n1159) );
OAI211X2TS U1122 ( .A0(intDX_EWSW[20]), .A1(n1682), .B0(n1076), .C0(n1062),
.Y(n1071) );
AOI221X1TS U1123 ( .A0(n1682), .A1(intDX_EWSW[20]), .B0(intDX_EWSW[21]),
.B1(n1677), .C0(n1149), .Y(n1152) );
OAI211X2TS U1124 ( .A0(intDX_EWSW[12]), .A1(n1680), .B0(n1057), .C0(n1043),
.Y(n1059) );
AOI221X1TS U1125 ( .A0(n1680), .A1(intDX_EWSW[12]), .B0(intDX_EWSW[13]),
.B1(n1676), .C0(n1157), .Y(n1160) );
AOI211X1TS U1126 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1202), .B0(n1218), .C0(
n1193), .Y(n1195) );
OAI31XLTS U1127 ( .A0(n1402), .A1(n1178), .A2(n1408), .B0(n1177), .Y(n801)
);
NOR2X2TS U1128 ( .A(n1243), .B(n954), .Y(n1332) );
NOR4BBX2TS U1129 ( .AN(n1220), .BN(n1219), .C(n1218), .D(n1217), .Y(n1243)
);
NOR2X2TS U1130 ( .A(n1382), .B(DMP_EXP_EWSW[23]), .Y(n1387) );
BUFX4TS U1131 ( .A(n1743), .Y(n1726) );
XNOR2X2TS U1132 ( .A(DMP_exp_NRM2_EW[6]), .B(n1015), .Y(n1333) );
XNOR2X2TS U1133 ( .A(DMP_exp_NRM2_EW[0]), .B(n1312), .Y(n1298) );
XNOR2X2TS U1134 ( .A(DMP_exp_NRM2_EW[5]), .B(DP_OP_15J11_123_2691_n4), .Y(
n1300) );
CLKINVX6TS U1135 ( .A(n1505), .Y(n1506) );
NOR2X2TS U1136 ( .A(n1460), .B(DMP_SFG[3]), .Y(n1472) );
NOR2X2TS U1137 ( .A(n1437), .B(DMP_SFG[4]), .Y(n1484) );
NOR2X2TS U1138 ( .A(n1310), .B(DMP_SFG[11]), .Y(n1525) );
NOR2X2TS U1139 ( .A(n1495), .B(DMP_SFG[7]), .Y(n1554) );
AOI222X1TS U1140 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n955), .B0(n1363), .B1(
DmP_mant_SHT1_SW[6]), .C0(n1237), .C1(DmP_mant_SHT1_SW[7]), .Y(n1294)
);
AOI222X1TS U1141 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n955), .B0(n1363), .B1(
DmP_mant_SHT1_SW[17]), .C0(n1362), .C1(DmP_mant_SHT1_SW[18]), .Y(n1264) );
AOI222X4TS U1142 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n955), .B0(n1363), .B1(
DmP_mant_SHT1_SW[16]), .C0(n1362), .C1(DmP_mant_SHT1_SW[17]), .Y(n1288) );
AOI222X1TS U1143 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n955), .B0(n1363), .B1(
DmP_mant_SHT1_SW[21]), .C0(n1362), .C1(DmP_mant_SHT1_SW[22]), .Y(n1270) );
AOI211X1TS U1144 ( .A0(n1216), .A1(n1215), .B0(Raw_mant_NRM_SWR[24]), .C0(
Raw_mant_NRM_SWR[25]), .Y(n1217) );
OAI211XLTS U1145 ( .A0(n977), .A1(DMP_SFG[2]), .B0(n1461), .C0(DMP_SFG[1]),
.Y(n1464) );
NOR2X4TS U1146 ( .A(n1515), .B(n1514), .Y(n1595) );
OAI2BB1X2TS U1147 ( .A0N(n1306), .A1N(n1305), .B0(Shift_reg_FLAGS_7[0]), .Y(
n1514) );
NAND3X2TS U1148 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.C(n1655), .Y(n1543) );
NAND2X4TS U1149 ( .A(n954), .B(n1404), .Y(n1379) );
BUFX4TS U1150 ( .A(n1748), .Y(n1562) );
XOR2XLTS U1151 ( .A(DMP_SFG[12]), .B(n976), .Y(n1427) );
AOI222X1TS U1152 ( .A0(n1573), .A1(n1592), .B0(n1622), .B1(Data_array_SWR[7]), .C0(n1572), .C1(n1503), .Y(n1571) );
AOI222X1TS U1153 ( .A0(n1573), .A1(n1621), .B0(Data_array_SWR[7]), .B1(n1588), .C0(n1572), .C1(n1586), .Y(n1606) );
AOI222X1TS U1154 ( .A0(n1582), .A1(n1592), .B0(n1622), .B1(Data_array_SWR[6]), .C0(n1581), .C1(n1503), .Y(n1580) );
AOI222X1TS U1155 ( .A0(n1582), .A1(n1621), .B0(Data_array_SWR[6]), .B1(n1588), .C0(n1581), .C1(n1586), .Y(n1608) );
INVX4TS U1156 ( .A(n1095), .Y(n1406) );
AOI222X1TS U1157 ( .A0(n1576), .A1(n1592), .B0(n1622), .B1(Data_array_SWR[5]), .C0(n1575), .C1(n1503), .Y(n1574) );
AOI222X1TS U1158 ( .A0(n1576), .A1(n1621), .B0(Data_array_SWR[5]), .B1(n1588), .C0(n1575), .C1(n1586), .Y(n1610) );
AOI222X1TS U1159 ( .A0(n1579), .A1(n1592), .B0(n1622), .B1(Data_array_SWR[4]), .C0(n1578), .C1(n1503), .Y(n1577) );
AOI222X1TS U1160 ( .A0(n1579), .A1(n1621), .B0(Data_array_SWR[4]), .B1(n1588), .C0(n1578), .C1(n1586), .Y(n1612) );
INVX3TS U1161 ( .A(n1409), .Y(n1597) );
CLKINVX6TS U1162 ( .A(n1404), .Y(n1417) );
AOI222X4TS U1163 ( .A0(Data_array_SWR[19]), .A1(n1420), .B0(
Data_array_SWR[22]), .B1(n1429), .C0(Data_array_SWR[16]), .C1(n1421),
.Y(n1518) );
AOI222X4TS U1164 ( .A0(Data_array_SWR[19]), .A1(n1471), .B0(
Data_array_SWR[22]), .B1(n1445), .C0(Data_array_SWR[16]), .C1(n1470),
.Y(n1502) );
NOR2X2TS U1165 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1670), .Y(n1338) );
NOR3X2TS U1166 ( .A(Raw_mant_NRM_SWR[6]), .B(Raw_mant_NRM_SWR[5]), .C(n1208),
.Y(n1202) );
AOI32X1TS U1167 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1214), .A2(n1213), .B0(
Raw_mant_NRM_SWR[19]), .B1(n1214), .Y(n1215) );
NOR2X2TS U1168 ( .A(Raw_mant_NRM_SWR[13]), .B(n1187), .Y(n1212) );
OAI21X2TS U1169 ( .A0(intDX_EWSW[18]), .A1(n1699), .B0(n1068), .Y(n1148) );
NOR3X1TS U1170 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[19]), .C(
Raw_mant_NRM_SWR[20]), .Y(n1325) );
AOI221X1TS U1171 ( .A0(n1696), .A1(intDX_EWSW[8]), .B0(intDX_EWSW[6]), .B1(
n1674), .C0(n1166), .Y(n1167) );
AND2X2TS U1172 ( .A(beg_OP), .B(n1342), .Y(n1004) );
NOR2XLTS U1173 ( .A(n1751), .B(intDX_EWSW[11]), .Y(n1045) );
OAI21XLTS U1174 ( .A0(intDX_EWSW[15]), .A1(n1752), .B0(intDX_EWSW[14]), .Y(
n1053) );
NOR2XLTS U1175 ( .A(n1066), .B(intDY_EWSW[16]), .Y(n1067) );
OAI21XLTS U1176 ( .A0(intDX_EWSW[21]), .A1(n1677), .B0(intDX_EWSW[20]), .Y(
n1065) );
NOR2XLTS U1177 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[16]), .Y(
n1213) );
OAI21XLTS U1178 ( .A0(n1554), .A1(n1509), .B0(n1552), .Y(n1510) );
NOR2XLTS U1179 ( .A(n1473), .B(n1472), .Y(n1476) );
OAI21XLTS U1180 ( .A0(n1178), .A1(n1086), .B0(n1175), .Y(n1176) );
AOI31XLTS U1181 ( .A0(n1417), .A1(Shift_amount_SHT1_EWR[4]), .A2(n954), .B0(
n1314), .Y(n1196) );
OAI21XLTS U1182 ( .A0(n1379), .A1(n1655), .B0(n1196), .Y(n848) );
OAI211XLTS U1183 ( .A0(n1269), .A1(n1369), .B0(n1268), .C0(n1267), .Y(n863)
);
OAI21XLTS U1184 ( .A0(n1683), .A1(n1408), .B0(n1088), .Y(n807) );
OAI21XLTS U1185 ( .A0(n957), .A1(n1182), .B0(n1134), .Y(n824) );
OAI211XLTS U1186 ( .A0(n1276), .A1(n1221), .B0(n1228), .C0(n1227), .Y(n855)
);
CLKBUFX2TS U1187 ( .A(n1005), .Y(n1006) );
BUFX3TS U1188 ( .A(n1731), .Y(n1734) );
BUFX3TS U1189 ( .A(n1736), .Y(n1742) );
BUFX3TS U1190 ( .A(n956), .Y(n1728) );
BUFX3TS U1191 ( .A(n1743), .Y(n1725) );
BUFX3TS U1192 ( .A(n1726), .Y(n1721) );
AO22XLTS U1193 ( .A0(Shift_reg_FLAGS_7[1]), .A1(ZERO_FLAG_NRM), .B0(n954),
.B1(ZERO_FLAG_SHT1SHT2), .Y(n634) );
AO22XLTS U1194 ( .A0(Shift_reg_FLAGS_7[1]), .A1(SIGN_FLAG_NRM), .B0(n954),
.B1(SIGN_FLAG_SHT1SHT2), .Y(n625) );
INVX4TS U1195 ( .A(n1748), .Y(n1477) );
AOI2BB2X1TS U1196 ( .B0(DmP_mant_SFG_SWR[2]), .B1(n1002), .A0N(n1002), .A1N(
DmP_mant_SFG_SWR[2]), .Y(n1018) );
CLKAND2X2TS U1197 ( .A(n1018), .B(DMP_SFG[0]), .Y(n1020) );
AOI2BB2X1TS U1198 ( .B0(DmP_mant_SFG_SWR[3]), .B1(n1002), .A0N(n1002), .A1N(
DmP_mant_SFG_SWR[3]), .Y(n1461) );
AO22XLTS U1199 ( .A0(n1562), .A1(Raw_mant_NRM_SWR[3]), .B0(n1477), .B1(n1007), .Y(n599) );
AO22XLTS U1200 ( .A0(n1748), .A1(Raw_mant_NRM_SWR[4]), .B0(n1477), .B1(n1008), .Y(n596) );
INVX2TS U1201 ( .A(DP_OP_15J11_123_2691_n4), .Y(n1009) );
NAND2X1TS U1202 ( .A(n1688), .B(n1009), .Y(n1015) );
INVX1TS U1203 ( .A(LZD_output_NRM2_EW[0]), .Y(n1312) );
NOR2XLTS U1204 ( .A(n1298), .B(exp_rslt_NRM2_EW1[1]), .Y(n1012) );
INVX2TS U1205 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n1011) );
INVX2TS U1206 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n1010) );
NAND4BXLTS U1207 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n1012), .C(n1011), .D(n1010), .Y(n1013) );
NOR2XLTS U1208 ( .A(n1013), .B(n1300), .Y(n1014) );
INVX2TS U1209 ( .A(n1015), .Y(n1016) );
NAND2X1TS U1210 ( .A(n1687), .B(n1016), .Y(n1303) );
XNOR2X1TS U1211 ( .A(DMP_exp_NRM2_EW[7]), .B(n1303), .Y(n1297) );
OR2X1TS U1212 ( .A(n1017), .B(n1297), .Y(n1308) );
CLKBUFX2TS U1213 ( .A(Shift_reg_FLAGS_7[0]), .Y(n1409) );
NAND2X2TS U1214 ( .A(n1308), .B(n1409), .Y(n1334) );
OA22X1TS U1215 ( .A0(n1334), .A1(exp_rslt_NRM2_EW1[3]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[26]), .Y(n839) );
OA22X1TS U1216 ( .A0(n1334), .A1(n1298), .B0(final_result_ieee[23]), .B1(
Shift_reg_FLAGS_7[0]), .Y(n842) );
OA22X1TS U1217 ( .A0(n1334), .A1(exp_rslt_NRM2_EW1[2]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[25]), .Y(n840) );
OA22X1TS U1218 ( .A0(n1334), .A1(n1300), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[28]), .Y(n837) );
OA22X1TS U1219 ( .A0(n1334), .A1(exp_rslt_NRM2_EW1[1]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[24]), .Y(n841) );
OA22X1TS U1220 ( .A0(n1334), .A1(exp_rslt_NRM2_EW1[4]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[27]), .Y(n838) );
INVX4TS U1221 ( .A(n1404), .Y(busy) );
OAI21XLTS U1222 ( .A0(n1417), .A1(n1592), .B0(n954), .Y(n910) );
NOR2XLTS U1223 ( .A(n1018), .B(DMP_SFG[0]), .Y(n1019) );
INVX4TS U1224 ( .A(n1748), .Y(n1564) );
OAI32X1TS U1225 ( .A0(n1748), .A1(n1020), .A2(n1019), .B0(n1564), .B1(n1657),
.Y(n600) );
NOR2X1TS U1226 ( .A(n1692), .B(intDX_EWSW[25]), .Y(n1079) );
NOR2XLTS U1227 ( .A(n1079), .B(intDY_EWSW[24]), .Y(n1021) );
AOI22X1TS U1228 ( .A0(intDX_EWSW[25]), .A1(n1692), .B0(intDX_EWSW[24]), .B1(
n1021), .Y(n1025) );
OAI21X1TS U1229 ( .A0(intDX_EWSW[26]), .A1(n1691), .B0(n1022), .Y(n1080) );
NAND3XLTS U1230 ( .A(n1691), .B(n1022), .C(intDX_EWSW[26]), .Y(n1024) );
NAND2BXLTS U1231 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n1023) );
OAI211XLTS U1232 ( .A0(n1025), .A1(n1080), .B0(n1024), .C0(n1023), .Y(n1030)
);
NOR2X1TS U1233 ( .A(n1667), .B(intDX_EWSW[30]), .Y(n1028) );
NOR2X1TS U1234 ( .A(n1638), .B(intDX_EWSW[29]), .Y(n1026) );
AOI211X1TS U1235 ( .A0(intDY_EWSW[28]), .A1(n1698), .B0(n1028), .C0(n1026),
.Y(n1078) );
NOR3X1TS U1236 ( .A(n1698), .B(n1026), .C(intDY_EWSW[28]), .Y(n1027) );
AOI221X1TS U1237 ( .A0(intDX_EWSW[30]), .A1(n1667), .B0(intDX_EWSW[29]),
.B1(n1638), .C0(n1027), .Y(n1029) );
AOI2BB2X1TS U1238 ( .B0(n1030), .B1(n1078), .A0N(n1029), .A1N(n1028), .Y(
n1084) );
NOR2X1TS U1239 ( .A(n1694), .B(intDX_EWSW[17]), .Y(n1066) );
OAI22X1TS U1240 ( .A0(n957), .A1(n991), .B0(n1751), .B1(intDX_EWSW[11]), .Y(
n1156) );
INVX2TS U1241 ( .A(n1156), .Y(n1050) );
OAI211XLTS U1242 ( .A0(intDX_EWSW[8]), .A1(n1696), .B0(n1047), .C0(n1050),
.Y(n1061) );
OAI2BB1X1TS U1243 ( .A0N(n1658), .A1N(intDY_EWSW[5]), .B0(intDX_EWSW[4]),
.Y(n1031) );
OAI22X1TS U1244 ( .A0(intDY_EWSW[4]), .A1(n1031), .B0(n1658), .B1(
intDY_EWSW[5]), .Y(n1042) );
OAI2BB1X1TS U1245 ( .A0N(n1637), .A1N(intDY_EWSW[7]), .B0(intDX_EWSW[6]),
.Y(n1032) );
OAI22X1TS U1246 ( .A0(intDY_EWSW[6]), .A1(n1032), .B0(n1637), .B1(
intDY_EWSW[7]), .Y(n1041) );
OAI21XLTS U1247 ( .A0(intDX_EWSW[1]), .A1(n1695), .B0(intDX_EWSW[0]), .Y(
n1033) );
OAI2BB2XLTS U1248 ( .B0(intDY_EWSW[0]), .B1(n1033), .A0N(intDX_EWSW[1]),
.A1N(n1695), .Y(n1035) );
OAI211XLTS U1249 ( .A0(n1750), .A1(intDX_EWSW[3]), .B0(n1035), .C0(n1034),
.Y(n1038) );
OAI21XLTS U1250 ( .A0(intDX_EWSW[3]), .A1(n1750), .B0(n992), .Y(n1036) );
AOI2BB2XLTS U1251 ( .B0(intDX_EWSW[3]), .B1(n1750), .A0N(intDY_EWSW[2]),
.A1N(n1036), .Y(n1037) );
AOI222X1TS U1252 ( .A0(intDY_EWSW[4]), .A1(n1636), .B0(n1038), .B1(n1037),
.C0(intDY_EWSW[5]), .C1(n1658), .Y(n1040) );
AOI22X1TS U1253 ( .A0(intDY_EWSW[7]), .A1(n1637), .B0(intDY_EWSW[6]), .B1(
n1660), .Y(n1039) );
OAI32X1TS U1254 ( .A0(n1042), .A1(n1041), .A2(n1040), .B0(n1039), .B1(n1041),
.Y(n1060) );
OA22X1TS U1255 ( .A0(n1681), .A1(intDX_EWSW[14]), .B0(n1752), .B1(
intDX_EWSW[15]), .Y(n1057) );
OAI21XLTS U1256 ( .A0(intDX_EWSW[13]), .A1(n1676), .B0(intDX_EWSW[12]), .Y(
n1044) );
OAI2BB2XLTS U1257 ( .B0(intDY_EWSW[12]), .B1(n1044), .A0N(intDX_EWSW[13]),
.A1N(n1676), .Y(n1056) );
NOR2XLTS U1258 ( .A(n1045), .B(intDY_EWSW[10]), .Y(n1046) );
AOI22X1TS U1259 ( .A0(intDX_EWSW[11]), .A1(n1751), .B0(n991), .B1(n1046),
.Y(n1052) );
NAND2BXLTS U1260 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n1049) );
NAND3XLTS U1261 ( .A(n1696), .B(n1047), .C(intDX_EWSW[8]), .Y(n1048) );
AOI21X1TS U1262 ( .A0(n1049), .A1(n1048), .B0(n1059), .Y(n1051) );
OAI2BB2XLTS U1263 ( .B0(n1052), .B1(n1059), .A0N(n1051), .A1N(n1050), .Y(
n1055) );
AOI211X1TS U1264 ( .A0(n1057), .A1(n1056), .B0(n1055), .C0(n1054), .Y(n1058)
);
OAI31X1TS U1265 ( .A0(n1061), .A1(n1060), .A2(n1059), .B0(n1058), .Y(n1064)
);
OA22X1TS U1266 ( .A0(n1643), .A1(intDX_EWSW[22]), .B0(n1686), .B1(
intDX_EWSW[23]), .Y(n1076) );
AOI211XLTS U1267 ( .A0(intDY_EWSW[16]), .A1(n1665), .B0(n1071), .C0(n1148),
.Y(n1063) );
NAND3BXLTS U1268 ( .AN(n1066), .B(n1064), .C(n1063), .Y(n1083) );
OAI2BB2XLTS U1269 ( .B0(intDY_EWSW[20]), .B1(n1065), .A0N(intDX_EWSW[21]),
.A1N(n1677), .Y(n1075) );
AOI22X1TS U1270 ( .A0(intDX_EWSW[17]), .A1(n1694), .B0(intDX_EWSW[16]), .B1(
n1067), .Y(n1070) );
OAI32X1TS U1271 ( .A0(n1148), .A1(n1071), .A2(n1070), .B0(n1069), .B1(n1071),
.Y(n1074) );
OAI21XLTS U1272 ( .A0(intDX_EWSW[23]), .A1(n1686), .B0(intDX_EWSW[22]), .Y(
n1072) );
OAI2BB2XLTS U1273 ( .B0(intDY_EWSW[22]), .B1(n1072), .A0N(intDX_EWSW[23]),
.A1N(n1686), .Y(n1073) );
AOI211X1TS U1274 ( .A0(n1076), .A1(n1075), .B0(n1074), .C0(n1073), .Y(n1082)
);
NAND2BXLTS U1275 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n1077) );
NAND4BBX1TS U1276 ( .AN(n1080), .BN(n1079), .C(n1078), .D(n1077), .Y(n1081)
);
AOI32X1TS U1277 ( .A0(n1084), .A1(n1083), .A2(n1082), .B0(n1081), .B1(n1084),
.Y(n1085) );
NOR2X1TS U1278 ( .A(n1085), .B(n1003), .Y(n1096) );
INVX4TS U1279 ( .A(n1096), .Y(n1408) );
BUFX4TS U1280 ( .A(n1086), .Y(n1183) );
AOI22X1TS U1281 ( .A0(intDX_EWSW[22]), .A1(n1095), .B0(DMP_EXP_EWSW[22]),
.B1(n1183), .Y(n1087) );
OAI21XLTS U1282 ( .A0(n1643), .A1(n1408), .B0(n1087), .Y(n812) );
BUFX4TS U1283 ( .A(n1086), .Y(n1339) );
AOI22X1TS U1284 ( .A0(n987), .A1(n1339), .B0(intDX_EWSW[27]), .B1(n1095),
.Y(n1088) );
AOI22X1TS U1285 ( .A0(intDX_EWSW[20]), .A1(n1095), .B0(DMP_EXP_EWSW[20]),
.B1(n1183), .Y(n1089) );
OAI21XLTS U1286 ( .A0(n1682), .A1(n1408), .B0(n1089), .Y(n814) );
INVX4TS U1287 ( .A(n1135), .Y(n1182) );
AOI22X1TS U1288 ( .A0(DMP_EXP_EWSW[23]), .A1(n1339), .B0(intDX_EWSW[23]),
.B1(n1095), .Y(n1090) );
OAI21XLTS U1289 ( .A0(n1686), .A1(n1182), .B0(n1090), .Y(n811) );
AOI22X1TS U1290 ( .A0(intDX_EWSW[4]), .A1(n1095), .B0(DMP_EXP_EWSW[4]), .B1(
n1086), .Y(n1091) );
OAI21XLTS U1291 ( .A0(n1679), .A1(n1408), .B0(n1091), .Y(n830) );
AOI22X1TS U1292 ( .A0(intDX_EWSW[7]), .A1(n1095), .B0(DMP_EXP_EWSW[7]), .B1(
n1086), .Y(n1092) );
OAI21XLTS U1293 ( .A0(n1684), .A1(n1182), .B0(n1092), .Y(n827) );
AOI22X1TS U1294 ( .A0(intDX_EWSW[5]), .A1(n1095), .B0(DMP_EXP_EWSW[5]), .B1(
n1086), .Y(n1093) );
OAI21XLTS U1295 ( .A0(n1641), .A1(n1182), .B0(n1093), .Y(n829) );
AOI22X1TS U1296 ( .A0(intDX_EWSW[6]), .A1(n1095), .B0(DMP_EXP_EWSW[6]), .B1(
n1086), .Y(n1094) );
OAI21XLTS U1297 ( .A0(n1674), .A1(n1182), .B0(n1094), .Y(n828) );
BUFX3TS U1298 ( .A(n1096), .Y(n1135) );
BUFX4TS U1299 ( .A(n1135), .Y(n1123) );
AOI22X1TS U1300 ( .A0(intDX_EWSW[18]), .A1(n1123), .B0(DmP_EXP_EWSW[18]),
.B1(n1339), .Y(n1097) );
OAI21XLTS U1301 ( .A0(n1699), .A1(n1406), .B0(n1097), .Y(n655) );
AOI22X1TS U1302 ( .A0(intDY_EWSW[28]), .A1(n1123), .B0(DMP_EXP_EWSW[28]),
.B1(n1183), .Y(n1098) );
OAI21XLTS U1303 ( .A0(n1698), .A1(n1175), .B0(n1098), .Y(n806) );
AOI22X1TS U1304 ( .A0(intDX_EWSW[22]), .A1(n1123), .B0(DmP_EXP_EWSW[22]),
.B1(n1339), .Y(n1099) );
OAI21XLTS U1305 ( .A0(n1643), .A1(n1406), .B0(n1099), .Y(n647) );
AOI22X1TS U1306 ( .A0(intDX_EWSW[19]), .A1(n1123), .B0(DmP_EXP_EWSW[19]),
.B1(n1339), .Y(n1100) );
OAI21XLTS U1307 ( .A0(n1645), .A1(n1406), .B0(n1100), .Y(n653) );
AOI22X1TS U1308 ( .A0(intDX_EWSW[17]), .A1(n1123), .B0(DmP_EXP_EWSW[17]),
.B1(n1339), .Y(n1101) );
OAI21XLTS U1309 ( .A0(n1694), .A1(n1175), .B0(n1101), .Y(n657) );
AOI22X1TS U1310 ( .A0(intDX_EWSW[20]), .A1(n1123), .B0(DmP_EXP_EWSW[20]),
.B1(n1339), .Y(n1102) );
OAI21XLTS U1311 ( .A0(n1682), .A1(n1175), .B0(n1102), .Y(n651) );
INVX4TS U1312 ( .A(n1095), .Y(n1175) );
AOI22X1TS U1313 ( .A0(intDX_EWSW[3]), .A1(n1135), .B0(DmP_EXP_EWSW[3]), .B1(
n1183), .Y(n1103) );
OAI21XLTS U1314 ( .A0(n1750), .A1(n1406), .B0(n1103), .Y(n685) );
AOI22X1TS U1315 ( .A0(intDY_EWSW[29]), .A1(n1135), .B0(DMP_EXP_EWSW[29]),
.B1(n1183), .Y(n1104) );
OAI21XLTS U1316 ( .A0(n1685), .A1(n1175), .B0(n1104), .Y(n805) );
AOI22X1TS U1317 ( .A0(intDX_EWSW[12]), .A1(n1123), .B0(DmP_EXP_EWSW[12]),
.B1(n1086), .Y(n1105) );
OAI21XLTS U1318 ( .A0(n1680), .A1(n1175), .B0(n1105), .Y(n667) );
AOI22X1TS U1319 ( .A0(n992), .A1(n1135), .B0(DmP_EXP_EWSW[2]), .B1(n1339),
.Y(n1106) );
OAI21XLTS U1320 ( .A0(n1678), .A1(n1406), .B0(n1106), .Y(n687) );
AOI22X1TS U1321 ( .A0(DmP_EXP_EWSW[27]), .A1(n1339), .B0(intDX_EWSW[27]),
.B1(n1135), .Y(n1107) );
OAI21XLTS U1322 ( .A0(n1683), .A1(n1175), .B0(n1107), .Y(n641) );
AOI22X1TS U1323 ( .A0(intDX_EWSW[9]), .A1(n1123), .B0(DmP_EXP_EWSW[9]), .B1(
n1183), .Y(n1108) );
OAI21XLTS U1324 ( .A0(n1675), .A1(n1406), .B0(n1108), .Y(n673) );
AOI22X1TS U1325 ( .A0(intDX_EWSW[8]), .A1(n1123), .B0(DmP_EXP_EWSW[8]), .B1(
n1086), .Y(n1109) );
OAI21XLTS U1326 ( .A0(n1696), .A1(n1175), .B0(n1109), .Y(n675) );
AOI22X1TS U1327 ( .A0(intDY_EWSW[30]), .A1(n1135), .B0(DMP_EXP_EWSW[30]),
.B1(n1183), .Y(n1110) );
OAI21XLTS U1328 ( .A0(n1644), .A1(n1406), .B0(n1110), .Y(n804) );
AOI22X1TS U1329 ( .A0(intDX_EWSW[16]), .A1(n1123), .B0(DmP_EXP_EWSW[16]),
.B1(n1339), .Y(n1111) );
OAI21XLTS U1330 ( .A0(n1642), .A1(n1175), .B0(n1111), .Y(n659) );
AOI22X1TS U1331 ( .A0(intDX_EWSW[15]), .A1(n1123), .B0(DmP_EXP_EWSW[15]),
.B1(n1339), .Y(n1112) );
OAI21XLTS U1332 ( .A0(n1752), .A1(n1406), .B0(n1112), .Y(n661) );
AOI22X1TS U1333 ( .A0(intDX_EWSW[14]), .A1(n1123), .B0(DmP_EXP_EWSW[14]),
.B1(n1183), .Y(n1113) );
OAI21XLTS U1334 ( .A0(n1681), .A1(n1406), .B0(n1113), .Y(n663) );
AOI22X1TS U1335 ( .A0(intDX_EWSW[13]), .A1(n1123), .B0(DmP_EXP_EWSW[13]),
.B1(n1339), .Y(n1114) );
OAI21XLTS U1336 ( .A0(n1676), .A1(n1175), .B0(n1114), .Y(n665) );
AOI22X1TS U1337 ( .A0(intDX_EWSW[4]), .A1(n1135), .B0(DmP_EXP_EWSW[4]), .B1(
n1086), .Y(n1115) );
OAI21XLTS U1338 ( .A0(n1679), .A1(n1406), .B0(n1115), .Y(n683) );
AOI22X1TS U1339 ( .A0(intDX_EWSW[1]), .A1(n1135), .B0(DmP_EXP_EWSW[1]), .B1(
n1339), .Y(n1116) );
OAI21XLTS U1340 ( .A0(n1695), .A1(n1175), .B0(n1116), .Y(n689) );
AOI22X1TS U1341 ( .A0(intDX_EWSW[0]), .A1(n1135), .B0(DmP_EXP_EWSW[0]), .B1(
n1183), .Y(n1117) );
OAI21XLTS U1342 ( .A0(n1693), .A1(n1406), .B0(n1117), .Y(n691) );
AOI22X1TS U1343 ( .A0(intDX_EWSW[5]), .A1(n1123), .B0(DmP_EXP_EWSW[5]), .B1(
n1183), .Y(n1118) );
OAI21XLTS U1344 ( .A0(n1641), .A1(n1175), .B0(n1118), .Y(n681) );
AOI22X1TS U1345 ( .A0(intDX_EWSW[7]), .A1(n1135), .B0(DmP_EXP_EWSW[7]), .B1(
n1183), .Y(n1119) );
OAI21XLTS U1346 ( .A0(n1684), .A1(n1406), .B0(n1119), .Y(n677) );
AOI22X1TS U1347 ( .A0(intDX_EWSW[6]), .A1(n1123), .B0(DmP_EXP_EWSW[6]), .B1(
n1339), .Y(n1120) );
OAI21XLTS U1348 ( .A0(n1674), .A1(n1175), .B0(n1120), .Y(n679) );
AOI22X1TS U1349 ( .A0(n991), .A1(n1123), .B0(DmP_EXP_EWSW[10]), .B1(n1183),
.Y(n1121) );
OAI21XLTS U1350 ( .A0(n957), .A1(n1175), .B0(n1121), .Y(n671) );
AOI22X1TS U1351 ( .A0(intDX_EWSW[11]), .A1(n1123), .B0(DmP_EXP_EWSW[11]),
.B1(n1339), .Y(n1122) );
OAI21XLTS U1352 ( .A0(n1751), .A1(n1406), .B0(n1122), .Y(n669) );
AOI22X1TS U1353 ( .A0(intDX_EWSW[21]), .A1(n1123), .B0(DmP_EXP_EWSW[21]),
.B1(n1339), .Y(n1124) );
OAI21XLTS U1354 ( .A0(n1677), .A1(n1406), .B0(n1124), .Y(n649) );
AOI22X1TS U1355 ( .A0(intDX_EWSW[0]), .A1(n1095), .B0(DMP_EXP_EWSW[0]), .B1(
n1086), .Y(n1125) );
OAI21XLTS U1356 ( .A0(n1693), .A1(n1408), .B0(n1125), .Y(n834) );
AOI22X1TS U1357 ( .A0(intDX_EWSW[9]), .A1(n1095), .B0(DMP_EXP_EWSW[9]), .B1(
n1086), .Y(n1126) );
OAI21XLTS U1358 ( .A0(n1675), .A1(n1182), .B0(n1126), .Y(n825) );
AOI22X1TS U1359 ( .A0(n992), .A1(n1095), .B0(DMP_EXP_EWSW[2]), .B1(n1086),
.Y(n1127) );
OAI21XLTS U1360 ( .A0(n1678), .A1(n1182), .B0(n1127), .Y(n832) );
AOI22X1TS U1361 ( .A0(intDX_EWSW[1]), .A1(n1095), .B0(DMP_EXP_EWSW[1]), .B1(
n1183), .Y(n1128) );
OAI21XLTS U1362 ( .A0(n1695), .A1(n1182), .B0(n1128), .Y(n833) );
AOI22X1TS U1363 ( .A0(intDX_EWSW[8]), .A1(n1095), .B0(DMP_EXP_EWSW[8]), .B1(
n1086), .Y(n1129) );
OAI21XLTS U1364 ( .A0(n1696), .A1(n1182), .B0(n1129), .Y(n826) );
AOI22X1TS U1365 ( .A0(intDX_EWSW[3]), .A1(n1095), .B0(DMP_EXP_EWSW[3]), .B1(
n1086), .Y(n1130) );
OAI21XLTS U1366 ( .A0(n1750), .A1(n1408), .B0(n1130), .Y(n831) );
BUFX3TS U1367 ( .A(n1095), .Y(n1184) );
AOI22X1TS U1368 ( .A0(intDX_EWSW[16]), .A1(n1184), .B0(DMP_EXP_EWSW[16]),
.B1(n1183), .Y(n1131) );
OAI21XLTS U1369 ( .A0(n1642), .A1(n1182), .B0(n1131), .Y(n818) );
AOI22X1TS U1370 ( .A0(intDX_EWSW[19]), .A1(n1184), .B0(DMP_EXP_EWSW[19]),
.B1(n1183), .Y(n1132) );
OAI21XLTS U1371 ( .A0(n1645), .A1(n1408), .B0(n1132), .Y(n815) );
AOI22X1TS U1372 ( .A0(intDX_EWSW[18]), .A1(n1184), .B0(DMP_EXP_EWSW[18]),
.B1(n1183), .Y(n1133) );
OAI21XLTS U1373 ( .A0(n1699), .A1(n1182), .B0(n1133), .Y(n816) );
AOI22X1TS U1374 ( .A0(n991), .A1(n1184), .B0(DMP_EXP_EWSW[10]), .B1(n1086),
.Y(n1134) );
AOI222X1TS U1375 ( .A0(n1135), .A1(intDX_EWSW[23]), .B0(DmP_EXP_EWSW[23]),
.B1(n1086), .C0(intDY_EWSW[23]), .C1(n1184), .Y(n1136) );
INVX2TS U1376 ( .A(n1136), .Y(n645) );
AOI22X1TS U1377 ( .A0(intDX_EWSW[14]), .A1(n1184), .B0(DMP_EXP_EWSW[14]),
.B1(n1086), .Y(n1137) );
OAI21XLTS U1378 ( .A0(n1681), .A1(n1182), .B0(n1137), .Y(n820) );
AOI22X1TS U1379 ( .A0(intDX_EWSW[17]), .A1(n1184), .B0(DMP_EXP_EWSW[17]),
.B1(n1183), .Y(n1138) );
OAI21XLTS U1380 ( .A0(n1694), .A1(n1182), .B0(n1138), .Y(n817) );
AOI22X1TS U1381 ( .A0(intDX_EWSW[12]), .A1(n1184), .B0(DMP_EXP_EWSW[12]),
.B1(n1086), .Y(n1139) );
OAI21XLTS U1382 ( .A0(n1680), .A1(n1182), .B0(n1139), .Y(n822) );
OAI22X1TS U1383 ( .A0(n1692), .A1(intDX_EWSW[25]), .B0(n1691), .B1(
intDX_EWSW[26]), .Y(n1140) );
AOI221X1TS U1384 ( .A0(n1692), .A1(intDX_EWSW[25]), .B0(intDX_EWSW[26]),
.B1(n1691), .C0(n1140), .Y(n1146) );
OAI22X1TS U1385 ( .A0(n1683), .A1(intDX_EWSW[27]), .B0(n1698), .B1(
intDY_EWSW[28]), .Y(n1141) );
OAI22X1TS U1386 ( .A0(n1685), .A1(intDY_EWSW[29]), .B0(n1644), .B1(
intDY_EWSW[30]), .Y(n1142) );
AOI221X1TS U1387 ( .A0(n1685), .A1(intDY_EWSW[29]), .B0(intDY_EWSW[30]),
.B1(n1644), .C0(n1142), .Y(n1144) );
AOI2BB2XLTS U1388 ( .B0(intDX_EWSW[7]), .B1(n1684), .A0N(n1684), .A1N(
intDX_EWSW[7]), .Y(n1143) );
NAND4XLTS U1389 ( .A(n1146), .B(n1145), .C(n1144), .D(n1143), .Y(n1174) );
OAI22X1TS U1390 ( .A0(n1695), .A1(intDX_EWSW[1]), .B0(n1694), .B1(
intDX_EWSW[17]), .Y(n1147) );
OAI22X1TS U1391 ( .A0(n1682), .A1(intDX_EWSW[20]), .B0(n1677), .B1(
intDX_EWSW[21]), .Y(n1149) );
OAI22X1TS U1392 ( .A0(n1643), .A1(intDX_EWSW[22]), .B0(n1686), .B1(
intDX_EWSW[23]), .Y(n1150) );
NAND4XLTS U1393 ( .A(n1154), .B(n1153), .C(n1152), .D(n1151), .Y(n1173) );
OAI22X1TS U1394 ( .A0(n1629), .A1(intDX_EWSW[24]), .B0(n1675), .B1(
intDX_EWSW[9]), .Y(n1155) );
AOI221X1TS U1395 ( .A0(n1629), .A1(intDX_EWSW[24]), .B0(intDX_EWSW[9]), .B1(
n1675), .C0(n1155), .Y(n1162) );
OAI22X1TS U1396 ( .A0(n1680), .A1(intDX_EWSW[12]), .B0(n1676), .B1(
intDX_EWSW[13]), .Y(n1157) );
OAI22X1TS U1397 ( .A0(n1681), .A1(intDX_EWSW[14]), .B0(n1752), .B1(
intDX_EWSW[15]), .Y(n1158) );
NAND4XLTS U1398 ( .A(n1162), .B(n1161), .C(n1160), .D(n1159), .Y(n1172) );
OAI22X1TS U1399 ( .A0(n1642), .A1(intDX_EWSW[16]), .B0(n1693), .B1(
intDX_EWSW[0]), .Y(n1163) );
AOI221X1TS U1400 ( .A0(n1642), .A1(intDX_EWSW[16]), .B0(intDX_EWSW[0]), .B1(
n1693), .C0(n1163), .Y(n1170) );
OAI22X1TS U1401 ( .A0(n1678), .A1(n992), .B0(n1750), .B1(intDX_EWSW[3]), .Y(
n1164) );
OAI22X1TS U1402 ( .A0(n1679), .A1(intDX_EWSW[4]), .B0(n1641), .B1(
intDX_EWSW[5]), .Y(n1165) );
AOI221X1TS U1403 ( .A0(n1679), .A1(intDX_EWSW[4]), .B0(intDX_EWSW[5]), .B1(
n1641), .C0(n1165), .Y(n1168) );
OAI22X1TS U1404 ( .A0(n1696), .A1(intDX_EWSW[8]), .B0(n1674), .B1(
intDX_EWSW[6]), .Y(n1166) );
NAND4XLTS U1405 ( .A(n1170), .B(n1169), .C(n1168), .D(n1167), .Y(n1171) );
NOR4X1TS U1406 ( .A(n1174), .B(n1173), .C(n1172), .D(n1171), .Y(n1402) );
CLKXOR2X2TS U1407 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n1400) );
INVX2TS U1408 ( .A(n1400), .Y(n1178) );
AOI22X1TS U1409 ( .A0(intDX_EWSW[31]), .A1(n1176), .B0(SIGN_FLAG_EXP), .B1(
n1339), .Y(n1177) );
AOI22X1TS U1410 ( .A0(intDX_EWSW[11]), .A1(n1184), .B0(DMP_EXP_EWSW[11]),
.B1(n1183), .Y(n1179) );
OAI21XLTS U1411 ( .A0(n1751), .A1(n1182), .B0(n1179), .Y(n823) );
AOI22X1TS U1412 ( .A0(intDX_EWSW[13]), .A1(n1184), .B0(DMP_EXP_EWSW[13]),
.B1(n1086), .Y(n1180) );
OAI21XLTS U1413 ( .A0(n1676), .A1(n1182), .B0(n1180), .Y(n821) );
AOI22X1TS U1414 ( .A0(intDX_EWSW[15]), .A1(n1184), .B0(DMP_EXP_EWSW[15]),
.B1(n1086), .Y(n1181) );
OAI21XLTS U1415 ( .A0(n1752), .A1(n1182), .B0(n1181), .Y(n819) );
AOI22X1TS U1416 ( .A0(intDX_EWSW[21]), .A1(n1184), .B0(DMP_EXP_EWSW[21]),
.B1(n1183), .Y(n1185) );
OAI21XLTS U1417 ( .A0(n1677), .A1(n1408), .B0(n1185), .Y(n813) );
AOI2BB2XLTS U1418 ( .B0(beg_OP), .B1(n1640), .A0N(n1640), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n1186) );
NAND3XLTS U1419 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1640), .C(
n1670), .Y(n1335) );
OAI21XLTS U1420 ( .A0(n1338), .A1(n1186), .B0(n1335), .Y(n951) );
NOR2BX1TS U1421 ( .AN(n1200), .B(Raw_mant_NRM_SWR[18]), .Y(n1316) );
NOR3X1TS U1422 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[15]), .C(
Raw_mant_NRM_SWR[16]), .Y(n1317) );
CLKAND2X2TS U1423 ( .A(n1316), .B(n1317), .Y(n1315) );
NAND2X1TS U1424 ( .A(n1315), .B(n1633), .Y(n1187) );
NAND2X1TS U1425 ( .A(n1212), .B(n1634), .Y(n1199) );
NOR2X1TS U1426 ( .A(Raw_mant_NRM_SWR[10]), .B(n1199), .Y(n1205) );
NAND2X1TS U1427 ( .A(n1205), .B(n1653), .Y(n1191) );
NOR3X1TS U1428 ( .A(Raw_mant_NRM_SWR[9]), .B(Raw_mant_NRM_SWR[8]), .C(n1191),
.Y(n1188) );
NAND2X1TS U1429 ( .A(n1188), .B(n1654), .Y(n1208) );
NOR2XLTS U1430 ( .A(Raw_mant_NRM_SWR[3]), .B(Raw_mant_NRM_SWR[2]), .Y(n1190)
);
NAND2X1TS U1431 ( .A(n1202), .B(n1635), .Y(n1326) );
OAI21XLTS U1432 ( .A0(Raw_mant_NRM_SWR[7]), .A1(Raw_mant_NRM_SWR[6]), .B0(
n1188), .Y(n1189) );
OAI21X1TS U1433 ( .A0(n1190), .A1(n1326), .B0(n1189), .Y(n1218) );
NOR2XLTS U1434 ( .A(Raw_mant_NRM_SWR[9]), .B(Raw_mant_NRM_SWR[8]), .Y(n1192)
);
NAND2BXLTS U1435 ( .AN(n1208), .B(Raw_mant_NRM_SWR[5]), .Y(n1327) );
OAI21XLTS U1436 ( .A0(n1192), .A1(n1191), .B0(n1327), .Y(n1193) );
NOR3X1TS U1437 ( .A(Raw_mant_NRM_SWR[3]), .B(Raw_mant_NRM_SWR[2]), .C(n1326),
.Y(n1194) );
NAND2X1TS U1438 ( .A(n1194), .B(n988), .Y(n1204) );
NAND2X1TS U1439 ( .A(Raw_mant_NRM_SWR[1]), .B(n1194), .Y(n1319) );
AOI31X1TS U1440 ( .A0(n1195), .A1(n1204), .A2(n1319), .B0(n954), .Y(n1314)
);
NAND2X1TS U1441 ( .A(Raw_mant_NRM_SWR[14]), .B(n1315), .Y(n1220) );
AOI32X1TS U1442 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n961), .A2(n1627), .B0(
Raw_mant_NRM_SWR[22]), .B1(n961), .Y(n1197) );
AOI32X1TS U1443 ( .A0(n995), .A1(n1220), .A2(n1197), .B0(
Raw_mant_NRM_SWR[25]), .B1(n1220), .Y(n1198) );
AOI31XLTS U1444 ( .A0(n1200), .A1(Raw_mant_NRM_SWR[16]), .A2(n1628), .B0(
n1198), .Y(n1207) );
OAI21XLTS U1445 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n1657), .B0(n1635), .Y(n1201) );
NOR3X1TS U1446 ( .A(Raw_mant_NRM_SWR[12]), .B(n1656), .C(n1199), .Y(n1322)
);
AO21XLTS U1447 ( .A0(n1200), .A1(Raw_mant_NRM_SWR[18]), .B0(n1322), .Y(n1211) );
AOI21X1TS U1448 ( .A0(n1202), .A1(n1201), .B0(n1211), .Y(n1203) );
NAND2X1TS U1449 ( .A(Raw_mant_NRM_SWR[12]), .B(n1212), .Y(n1320) );
OAI211X1TS U1450 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n1204), .B0(n1203), .C0(
n1320), .Y(n1330) );
NOR2XLTS U1451 ( .A(Shift_reg_FLAGS_7[1]), .B(Shift_amount_SHT1_EWR[0]), .Y(
n1209) );
NOR2BX1TS U1452 ( .AN(Shift_amount_SHT1_EWR[0]), .B(Shift_reg_FLAGS_7[1]),
.Y(n1237) );
AOI31XLTS U1453 ( .A0(n1653), .A1(Raw_mant_NRM_SWR[11]), .A2(n1212), .B0(
n1211), .Y(n1219) );
NOR2XLTS U1454 ( .A(Raw_mant_NRM_SWR[23]), .B(Raw_mant_NRM_SWR[22]), .Y(
n1216) );
NOR2X1TS U1455 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[20]), .Y(
n1214) );
AOI21X1TS U1456 ( .A0(Shift_amount_SHT1_EWR[1]), .A1(n954), .B0(n1332), .Y(
n1222) );
NOR2X2TS U1457 ( .A(n1210), .B(n1222), .Y(n1373) );
NAND2X1TS U1458 ( .A(n1222), .B(n1379), .Y(n1223) );
INVX2TS U1459 ( .A(n1369), .Y(n1240) );
NAND2X2TS U1460 ( .A(n1226), .B(Shift_reg_FLAGS_7[1]), .Y(n1365) );
INVX2TS U1461 ( .A(n1365), .Y(n1352) );
AOI22X1TS U1462 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1352), .B0(n1362), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1225) );
AOI22X1TS U1463 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n955), .B0(n1363), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1224) );
NAND2X1TS U1464 ( .A(n1225), .B(n1224), .Y(n1254) );
AOI22X1TS U1465 ( .A0(n1210), .A1(Data_array_SWR[3]), .B0(n1240), .B1(n1254),
.Y(n1228) );
NAND2X1TS U1466 ( .A(n1332), .B(n1226), .Y(n1287) );
NAND2X1TS U1467 ( .A(Raw_mant_NRM_SWR[19]), .B(n1265), .Y(n1227) );
AOI22X1TS U1468 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n1352), .B0(n1362), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1230) );
AOI22X1TS U1469 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n955), .B0(n1363), .B1(n986), .Y(n1229) );
NAND2X1TS U1470 ( .A(n1230), .B(n1229), .Y(n1372) );
AOI22X1TS U1471 ( .A0(n1210), .A1(Data_array_SWR[2]), .B0(n1240), .B1(n1372),
.Y(n1232) );
NAND2X1TS U1472 ( .A(Raw_mant_NRM_SWR[20]), .B(n1265), .Y(n1231) );
OAI211XLTS U1473 ( .A0(n1280), .A1(n1221), .B0(n1232), .C0(n1231), .Y(n854)
);
AOI22X1TS U1474 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1352), .B0(n1362), .B1(
DmP_mant_SHT1_SW[6]), .Y(n1234) );
AOI22X1TS U1475 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n955), .B0(n1363), .B1(n985), .Y(n1233) );
NAND2X1TS U1476 ( .A(n1234), .B(n1233), .Y(n1273) );
AOI22X1TS U1477 ( .A0(n1210), .A1(Data_array_SWR[7]), .B0(n1240), .B1(n1273),
.Y(n1236) );
NAND2X1TS U1478 ( .A(Raw_mant_NRM_SWR[15]), .B(n1265), .Y(n1235) );
OAI211XLTS U1479 ( .A0(n1260), .A1(n1221), .B0(n1236), .C0(n1235), .Y(n859)
);
AOI22X1TS U1480 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1352), .B0(n1362), .B1(
n985), .Y(n1239) );
AOI22X1TS U1481 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n955), .B0(n1363), .B1(n979), .Y(n1238) );
NAND2X1TS U1482 ( .A(n1239), .B(n1238), .Y(n1277) );
AOI22X1TS U1483 ( .A0(n1210), .A1(Data_array_SWR[6]), .B0(n1240), .B1(n1277),
.Y(n1242) );
NAND2X1TS U1484 ( .A(Raw_mant_NRM_SWR[16]), .B(n1265), .Y(n1241) );
OAI211XLTS U1485 ( .A0(n1294), .A1(n1221), .B0(n1242), .C0(n1241), .Y(n858)
);
AOI22X1TS U1486 ( .A0(n1210), .A1(Data_array_SWR[13]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n1265), .Y(n1245) );
NAND2X1TS U1487 ( .A(n1243), .B(n1352), .Y(n1293) );
AOI2BB2XLTS U1488 ( .B0(Raw_mant_NRM_SWR[11]), .B1(n1371), .A0N(n1253),
.A1N(n1221), .Y(n1244) );
OAI211XLTS U1489 ( .A0(n1266), .A1(n1369), .B0(n1245), .C0(n1244), .Y(n865)
);
AOI22X1TS U1490 ( .A0(n1210), .A1(n989), .B0(Raw_mant_NRM_SWR[1]), .B1(n1265), .Y(n1247) );
AOI2BB2XLTS U1491 ( .B0(Raw_mant_NRM_SWR[3]), .B1(n1371), .A0N(n1270), .A1N(
n1221), .Y(n1246) );
OAI211XLTS U1492 ( .A0(n1261), .A1(n1369), .B0(n1247), .C0(n1246), .Y(n873)
);
AOI22X1TS U1493 ( .A0(n1210), .A1(n990), .B0(Raw_mant_NRM_SWR[5]), .B1(n1265), .Y(n1249) );
AOI2BB2XLTS U1494 ( .B0(Raw_mant_NRM_SWR[7]), .B1(n1371), .A0N(n1264), .A1N(
n1221), .Y(n1248) );
OAI211XLTS U1495 ( .A0(n1250), .A1(n1369), .B0(n1249), .C0(n1248), .Y(n869)
);
AOI22X1TS U1496 ( .A0(n1210), .A1(Data_array_SWR[15]), .B0(
Raw_mant_NRM_SWR[7]), .B1(n1265), .Y(n1252) );
AOI2BB2XLTS U1497 ( .B0(Raw_mant_NRM_SWR[9]), .B1(n1371), .A0N(n1250), .A1N(
n1221), .Y(n1251) );
OAI211XLTS U1498 ( .A0(n1253), .A1(n1369), .B0(n1252), .C0(n1251), .Y(n867)
);
AOI22X1TS U1499 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n955), .B0(n1362), .B1(n986), .Y(n1257) );
AOI22X1TS U1500 ( .A0(n1210), .A1(Data_array_SWR[1]), .B0(
Raw_mant_NRM_SWR[23]), .B1(n1371), .Y(n1256) );
NAND2X1TS U1501 ( .A(n1373), .B(n1254), .Y(n1255) );
OAI211XLTS U1502 ( .A0(n1257), .A1(n1369), .B0(n1256), .C0(n1255), .Y(n853)
);
AOI22X1TS U1503 ( .A0(n1210), .A1(Data_array_SWR[9]), .B0(
Raw_mant_NRM_SWR[13]), .B1(n1265), .Y(n1259) );
AOI2BB2XLTS U1504 ( .B0(Raw_mant_NRM_SWR[15]), .B1(n1371), .A0N(n1269),
.A1N(n1221), .Y(n1258) );
OAI211XLTS U1505 ( .A0(n1260), .A1(n1369), .B0(n1259), .C0(n1258), .Y(n861)
);
AOI22X1TS U1506 ( .A0(n1210), .A1(Data_array_SWR[18]), .B0(
Raw_mant_NRM_SWR[3]), .B1(n1265), .Y(n1263) );
AOI2BB2XLTS U1507 ( .B0(Raw_mant_NRM_SWR[5]), .B1(n1371), .A0N(n1261), .A1N(
n1221), .Y(n1262) );
OAI211XLTS U1508 ( .A0(n1264), .A1(n1369), .B0(n1263), .C0(n1262), .Y(n871)
);
AOI22X1TS U1509 ( .A0(n1210), .A1(Data_array_SWR[11]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n1265), .Y(n1268) );
AOI2BB2XLTS U1510 ( .B0(Raw_mant_NRM_SWR[13]), .B1(n1371), .A0N(n1266),
.A1N(n1221), .Y(n1267) );
AOI21X1TS U1511 ( .A0(n955), .A1(n988), .B0(n1363), .Y(n1350) );
OAI22X1TS U1512 ( .A0(n1270), .A1(n1369), .B0(n1379), .B1(n1646), .Y(n1271)
);
AOI21X1TS U1513 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n1371), .B0(n1271), .Y(n1272) );
OAI21XLTS U1514 ( .A0(n1350), .A1(n1221), .B0(n1272), .Y(n875) );
AOI22X1TS U1515 ( .A0(n1210), .A1(Data_array_SWR[5]), .B0(n1373), .B1(n1273),
.Y(n1275) );
NAND2X1TS U1516 ( .A(Raw_mant_NRM_SWR[19]), .B(n1371), .Y(n1274) );
OAI211XLTS U1517 ( .A0(n1276), .A1(n1369), .B0(n1275), .C0(n1274), .Y(n857)
);
AOI22X1TS U1518 ( .A0(n1210), .A1(Data_array_SWR[4]), .B0(n1373), .B1(n1277),
.Y(n1279) );
NAND2X1TS U1519 ( .A(Raw_mant_NRM_SWR[20]), .B(n1371), .Y(n1278) );
OAI211XLTS U1520 ( .A0(n1280), .A1(n1369), .B0(n1279), .C0(n1278), .Y(n856)
);
AOI22X1TS U1521 ( .A0(n1363), .A1(DmP_mant_SHT1_SW[18]), .B0(n1362), .B1(
n980), .Y(n1281) );
OAI21XLTS U1522 ( .A0(n1635), .A1(n1365), .B0(n1281), .Y(n1282) );
AOI21X1TS U1523 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n955), .B0(n1282), .Y(n1357)
);
OAI22X1TS U1524 ( .A0(n1288), .A1(n1369), .B0(n1659), .B1(n1293), .Y(n1283)
);
AOI21X1TS U1525 ( .A0(n1210), .A1(Data_array_SWR[17]), .B0(n1283), .Y(n1284)
);
OAI21XLTS U1526 ( .A0(n1357), .A1(n1221), .B0(n1284), .Y(n870) );
AOI22X1TS U1527 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1352), .B0(n1362), .B1(n981), .Y(n1285) );
OAI21XLTS U1528 ( .A0(n1664), .A1(n1354), .B0(n1285), .Y(n1286) );
AOI21X1TS U1529 ( .A0(n1363), .A1(DmP_mant_SHT1_SW[14]), .B0(n1286), .Y(
n1361) );
OAI22X1TS U1530 ( .A0(n1288), .A1(n1221), .B0(n1659), .B1(n1287), .Y(n1289)
);
AOI21X1TS U1531 ( .A0(n1210), .A1(Data_array_SWR[16]), .B0(n1289), .Y(n1290)
);
OAI21XLTS U1532 ( .A0(n1361), .A1(n1369), .B0(n1290), .Y(n868) );
AOI22X1TS U1533 ( .A0(n1363), .A1(DmP_mant_SHT1_SW[8]), .B0(n1362), .B1(n984), .Y(n1291) );
OAI21XLTS U1534 ( .A0(n1633), .A1(n1365), .B0(n1291), .Y(n1292) );
AOI21X1TS U1535 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n955), .B0(n1292), .Y(n1368) );
OAI22X1TS U1536 ( .A0(n1294), .A1(n1369), .B0(n1631), .B1(n1293), .Y(n1295)
);
AOI21X1TS U1537 ( .A0(n1210), .A1(Data_array_SWR[8]), .B0(n1295), .Y(n1296)
);
OAI21XLTS U1538 ( .A0(n1368), .A1(n1221), .B0(n1296), .Y(n860) );
INVX2TS U1539 ( .A(n1297), .Y(n1307) );
AND4X1TS U1540 ( .A(exp_rslt_NRM2_EW1[3]), .B(n1298), .C(
exp_rslt_NRM2_EW1[2]), .D(exp_rslt_NRM2_EW1[1]), .Y(n1299) );
NAND3XLTS U1541 ( .A(n1300), .B(exp_rslt_NRM2_EW1[4]), .C(n1299), .Y(n1301)
);
NAND2BXLTS U1542 ( .AN(n1301), .B(n1333), .Y(n1302) );
NOR2XLTS U1543 ( .A(n1307), .B(n1302), .Y(n1306) );
INVX2TS U1544 ( .A(n1303), .Y(n1304) );
CLKAND2X2TS U1545 ( .A(n1707), .B(n1304), .Y(n1305) );
OAI2BB2XLTS U1546 ( .B0(n1514), .B1(n1307), .A0N(final_result_ieee[30]),
.A1N(n1597), .Y(n835) );
INVX2TS U1547 ( .A(n1308), .Y(n1515) );
NOR2XLTS U1548 ( .A(n1515), .B(SIGN_FLAG_SHT1SHT2), .Y(n1309) );
OAI2BB2XLTS U1549 ( .B0(n1309), .B1(n1514), .A0N(n1597), .A1N(
final_result_ieee[31]), .Y(n624) );
AOI2BB2X1TS U1550 ( .B0(DmP_mant_SFG_SWR[13]), .B1(n1002), .A0N(n1002),
.A1N(DmP_mant_SFG_SWR[13]), .Y(n1310) );
AOI2BB2X1TS U1551 ( .B0(DmP_mant_SFG_SWR[12]), .B1(n1505), .A0N(n1505),
.A1N(DmP_mant_SFG_SWR[12]), .Y(n1424) );
NAND2BX1TS U1552 ( .AN(n1424), .B(DMP_SFG[10]), .Y(n1537) );
NAND2X1TS U1553 ( .A(n1310), .B(DMP_SFG[11]), .Y(n1524) );
OAI21X1TS U1554 ( .A0(n1525), .A1(n1537), .B0(n1524), .Y(n1311) );
INVX2TS U1555 ( .A(n1312), .Y(n1313) );
NAND2X1TS U1556 ( .A(n1662), .B(n1313), .Y(DP_OP_15J11_123_2691_n8) );
MX2X1TS U1557 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n692) );
MX2X1TS U1558 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n697) );
MX2X1TS U1559 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n702) );
MX2X1TS U1560 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n707) );
MX2X1TS U1561 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n712) );
MX2X1TS U1562 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n717) );
MX2X1TS U1563 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n722) );
MX2X1TS U1564 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n727) );
AO21XLTS U1565 ( .A0(LZD_output_NRM2_EW[4]), .A1(n954), .B0(n1314), .Y(n610)
);
OAI211X1TS U1566 ( .A0(Raw_mant_NRM_SWR[11]), .A1(Raw_mant_NRM_SWR[13]),
.B0(n1315), .C0(n1633), .Y(n1323) );
OAI2BB1X1TS U1567 ( .A0N(n1317), .A1N(n1633), .B0(n1316), .Y(n1318) );
NAND4XLTS U1568 ( .A(n1320), .B(n1323), .C(n1319), .D(n1318), .Y(n1321) );
OAI21X1TS U1569 ( .A0(n1322), .A1(n1321), .B0(Shift_reg_FLAGS_7[1]), .Y(
n1380) );
OAI2BB1X1TS U1570 ( .A0N(LZD_output_NRM2_EW[3]), .A1N(n954), .B0(n1380), .Y(
n598) );
OAI21XLTS U1571 ( .A0(n1325), .A1(n1324), .B0(n1323), .Y(n1331) );
OAI22X1TS U1572 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1327), .B0(n1326), .B1(
n1700), .Y(n1329) );
OAI31X1TS U1573 ( .A0(n1331), .A1(n1330), .A2(n1329), .B0(
Shift_reg_FLAGS_7[1]), .Y(n1376) );
OAI2BB1X1TS U1574 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n954), .B0(n1376), .Y(
n607) );
AO21XLTS U1575 ( .A0(LZD_output_NRM2_EW[1]), .A1(n954), .B0(n1332), .Y(n604)
);
OAI2BB1X1TS U1576 ( .A0N(LZD_output_NRM2_EW[0]), .A1N(n954), .B0(n1365), .Y(
n593) );
OA22X1TS U1577 ( .A0(n1334), .A1(n1333), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[29]), .Y(n836) );
OA21XLTS U1578 ( .A0(Shift_reg_FLAGS_7[0]), .A1(overflow_flag), .B0(n1514),
.Y(n639) );
INVX2TS U1579 ( .A(n1338), .Y(n1336) );
AOI22X1TS U1580 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n1336), .B1(n1640), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U1581 ( .A(n1336), .B(n1335), .Y(n952) );
NOR2XLTS U1582 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n1337) );
AOI32X4TS U1583 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n1337), .B1(n1670), .Y(n1341)
);
INVX2TS U1584 ( .A(n1341), .Y(n1340) );
AOI22X1TS U1585 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n1338), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n1640), .Y(n1342) );
AO22XLTS U1586 ( .A0(n1340), .A1(Shift_reg_FLAGS_7_6), .B0(n1341), .B1(n1342), .Y(n950) );
AOI22X1TS U1587 ( .A0(n1341), .A1(n1339), .B0(n1415), .B1(n1340), .Y(n949)
);
AOI22X1TS U1588 ( .A0(n1341), .A1(n1413), .B0(n1404), .B1(n1340), .Y(n948)
);
AOI22X1TS U1589 ( .A0(n1341), .A1(n1748), .B0(n954), .B1(n1340), .Y(n945) );
AOI22X1TS U1590 ( .A0(n1341), .A1(n954), .B0(n1597), .B1(n1340), .Y(n944) );
AO22XLTS U1591 ( .A0(n1345), .A1(Data_X[0]), .B0(n1347), .B1(intDX_EWSW[0]),
.Y(n943) );
AO22XLTS U1592 ( .A0(n1344), .A1(Data_X[1]), .B0(n1343), .B1(intDX_EWSW[1]),
.Y(n942) );
AO22XLTS U1593 ( .A0(n1344), .A1(Data_X[2]), .B0(n1343), .B1(n992), .Y(n941)
);
AO22XLTS U1594 ( .A0(n1349), .A1(Data_X[3]), .B0(n1343), .B1(intDX_EWSW[3]),
.Y(n940) );
AO22XLTS U1595 ( .A0(n1349), .A1(Data_X[4]), .B0(n1347), .B1(intDX_EWSW[4]),
.Y(n939) );
AO22XLTS U1596 ( .A0(n1344), .A1(Data_X[5]), .B0(n1343), .B1(intDX_EWSW[5]),
.Y(n938) );
AO22XLTS U1597 ( .A0(n1345), .A1(Data_X[6]), .B0(n1343), .B1(intDX_EWSW[6]),
.Y(n937) );
AO22XLTS U1598 ( .A0(n1345), .A1(Data_X[7]), .B0(n1343), .B1(intDX_EWSW[7]),
.Y(n936) );
AO22XLTS U1599 ( .A0(n1349), .A1(Data_X[8]), .B0(n1347), .B1(intDX_EWSW[8]),
.Y(n935) );
AO22XLTS U1600 ( .A0(n1344), .A1(Data_X[9]), .B0(n1343), .B1(intDX_EWSW[9]),
.Y(n934) );
AO22XLTS U1601 ( .A0(n1345), .A1(Data_X[10]), .B0(n1347), .B1(n991), .Y(n933) );
AO22XLTS U1602 ( .A0(n1344), .A1(Data_X[11]), .B0(n1347), .B1(intDX_EWSW[11]), .Y(n932) );
AO22XLTS U1603 ( .A0(n1345), .A1(Data_X[12]), .B0(n1348), .B1(intDX_EWSW[12]), .Y(n931) );
AO22XLTS U1604 ( .A0(n1344), .A1(Data_X[13]), .B0(n1348), .B1(intDX_EWSW[13]), .Y(n930) );
AO22XLTS U1605 ( .A0(n1344), .A1(Data_X[14]), .B0(n1348), .B1(intDX_EWSW[14]), .Y(n929) );
AO22XLTS U1606 ( .A0(n1349), .A1(Data_X[15]), .B0(n1348), .B1(intDX_EWSW[15]), .Y(n928) );
AO22XLTS U1607 ( .A0(n1344), .A1(Data_X[16]), .B0(n1348), .B1(intDX_EWSW[16]), .Y(n927) );
AO22XLTS U1608 ( .A0(n1345), .A1(Data_X[17]), .B0(n1348), .B1(intDX_EWSW[17]), .Y(n926) );
AO22XLTS U1609 ( .A0(n1345), .A1(Data_X[18]), .B0(n1348), .B1(intDX_EWSW[18]), .Y(n925) );
AO22XLTS U1610 ( .A0(n1345), .A1(Data_X[19]), .B0(n1348), .B1(intDX_EWSW[19]), .Y(n924) );
AO22XLTS U1611 ( .A0(n1345), .A1(Data_X[20]), .B0(n1348), .B1(intDX_EWSW[20]), .Y(n923) );
AO22XLTS U1612 ( .A0(n1349), .A1(Data_X[21]), .B0(n1348), .B1(intDX_EWSW[21]), .Y(n922) );
AO22XLTS U1613 ( .A0(n1349), .A1(Data_X[22]), .B0(n1348), .B1(intDX_EWSW[22]), .Y(n921) );
AO22XLTS U1614 ( .A0(n1345), .A1(Data_X[23]), .B0(n1348), .B1(intDX_EWSW[23]), .Y(n920) );
AO22XLTS U1615 ( .A0(n1343), .A1(intDX_EWSW[24]), .B0(n1004), .B1(Data_X[24]), .Y(n919) );
AO22XLTS U1616 ( .A0(n1343), .A1(intDX_EWSW[25]), .B0(n1345), .B1(Data_X[25]), .Y(n918) );
AO22XLTS U1617 ( .A0(n1347), .A1(intDX_EWSW[26]), .B0(n1349), .B1(Data_X[26]), .Y(n917) );
AO22XLTS U1618 ( .A0(n1349), .A1(Data_X[27]), .B0(n1343), .B1(intDX_EWSW[27]), .Y(n916) );
AO22XLTS U1619 ( .A0(n1343), .A1(intDX_EWSW[28]), .B0(n1349), .B1(Data_X[28]), .Y(n915) );
AO22XLTS U1620 ( .A0(n1343), .A1(intDX_EWSW[29]), .B0(n1349), .B1(Data_X[29]), .Y(n914) );
AO22XLTS U1621 ( .A0(n1347), .A1(intDX_EWSW[30]), .B0(n1344), .B1(Data_X[30]), .Y(n913) );
AO22XLTS U1622 ( .A0(n1349), .A1(add_subt), .B0(n1347), .B1(intAS), .Y(n911)
);
AO22XLTS U1623 ( .A0(n1343), .A1(intDY_EWSW[0]), .B0(n1345), .B1(Data_Y[0]),
.Y(n909) );
AO22XLTS U1624 ( .A0(n1343), .A1(intDY_EWSW[1]), .B0(n1344), .B1(Data_Y[1]),
.Y(n908) );
AO22XLTS U1625 ( .A0(n1343), .A1(intDY_EWSW[2]), .B0(n1345), .B1(Data_Y[2]),
.Y(n907) );
AO22XLTS U1626 ( .A0(n1347), .A1(intDY_EWSW[3]), .B0(n1345), .B1(Data_Y[3]),
.Y(n906) );
INVX4TS U1627 ( .A(n1004), .Y(n1346) );
AO22XLTS U1628 ( .A0(n1346), .A1(intDY_EWSW[4]), .B0(n1349), .B1(Data_Y[4]),
.Y(n905) );
AO22XLTS U1629 ( .A0(n1346), .A1(intDY_EWSW[5]), .B0(n1344), .B1(Data_Y[5]),
.Y(n904) );
AO22XLTS U1630 ( .A0(n1347), .A1(intDY_EWSW[6]), .B0(n1345), .B1(Data_Y[6]),
.Y(n903) );
AO22XLTS U1631 ( .A0(n1343), .A1(intDY_EWSW[7]), .B0(n1004), .B1(Data_Y[7]),
.Y(n902) );
AO22XLTS U1632 ( .A0(n1346), .A1(intDY_EWSW[8]), .B0(n1344), .B1(Data_Y[8]),
.Y(n901) );
AO22XLTS U1633 ( .A0(n1343), .A1(intDY_EWSW[9]), .B0(n1344), .B1(Data_Y[9]),
.Y(n900) );
AO22XLTS U1634 ( .A0(n1347), .A1(intDY_EWSW[10]), .B0(n1004), .B1(Data_Y[10]), .Y(n899) );
AO22XLTS U1635 ( .A0(n1343), .A1(intDY_EWSW[11]), .B0(n1344), .B1(Data_Y[11]), .Y(n898) );
AO22XLTS U1636 ( .A0(n1346), .A1(intDY_EWSW[12]), .B0(n1345), .B1(Data_Y[12]), .Y(n897) );
AO22XLTS U1637 ( .A0(n1346), .A1(intDY_EWSW[13]), .B0(n1344), .B1(Data_Y[13]), .Y(n896) );
AO22XLTS U1638 ( .A0(n1346), .A1(intDY_EWSW[14]), .B0(n1349), .B1(Data_Y[14]), .Y(n895) );
AO22XLTS U1639 ( .A0(n1343), .A1(intDY_EWSW[15]), .B0(n1345), .B1(Data_Y[15]), .Y(n894) );
AO22XLTS U1640 ( .A0(n1346), .A1(intDY_EWSW[16]), .B0(n1004), .B1(Data_Y[16]), .Y(n893) );
AO22XLTS U1641 ( .A0(n1346), .A1(intDY_EWSW[17]), .B0(n1345), .B1(Data_Y[17]), .Y(n892) );
AO22XLTS U1642 ( .A0(n1346), .A1(intDY_EWSW[18]), .B0(n1349), .B1(Data_Y[18]), .Y(n891) );
AO22XLTS U1643 ( .A0(n1346), .A1(intDY_EWSW[19]), .B0(n1004), .B1(Data_Y[19]), .Y(n890) );
AO22XLTS U1644 ( .A0(n1346), .A1(intDY_EWSW[20]), .B0(n1345), .B1(Data_Y[20]), .Y(n889) );
AO22XLTS U1645 ( .A0(n1346), .A1(intDY_EWSW[21]), .B0(n1349), .B1(Data_Y[21]), .Y(n888) );
AO22XLTS U1646 ( .A0(n1346), .A1(intDY_EWSW[22]), .B0(n1344), .B1(Data_Y[22]), .Y(n887) );
AO22XLTS U1647 ( .A0(n1346), .A1(intDY_EWSW[23]), .B0(n1345), .B1(Data_Y[23]), .Y(n886) );
AO22XLTS U1648 ( .A0(n1346), .A1(intDY_EWSW[24]), .B0(n1349), .B1(Data_Y[24]), .Y(n885) );
AO22XLTS U1649 ( .A0(n1346), .A1(intDY_EWSW[25]), .B0(n1349), .B1(Data_Y[25]), .Y(n884) );
AO22XLTS U1650 ( .A0(n1346), .A1(intDY_EWSW[26]), .B0(n1344), .B1(Data_Y[26]), .Y(n883) );
AO22XLTS U1651 ( .A0(n1346), .A1(intDY_EWSW[27]), .B0(n1345), .B1(Data_Y[27]), .Y(n882) );
AO22XLTS U1652 ( .A0(n1345), .A1(Data_Y[28]), .B0(n1343), .B1(intDY_EWSW[28]), .Y(n881) );
AO22XLTS U1653 ( .A0(n1345), .A1(Data_Y[29]), .B0(n1343), .B1(intDY_EWSW[29]), .Y(n880) );
AO22XLTS U1654 ( .A0(n1344), .A1(Data_Y[30]), .B0(n1343), .B1(intDY_EWSW[30]), .Y(n879) );
AO22XLTS U1655 ( .A0(n1349), .A1(Data_Y[31]), .B0(n1347), .B1(intDY_EWSW[31]), .Y(n878) );
OAI2BB2XLTS U1656 ( .B0(n1350), .B1(n1369), .A0N(n1210), .A1N(
Data_array_SWR[23]), .Y(n877) );
AO22XLTS U1657 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n955), .B0(n988), .B1(n1352),
.Y(n1351) );
OAI2BB2XLTS U1658 ( .B0(n1356), .B1(n1369), .A0N(n1210), .A1N(
Data_array_SWR[22]), .Y(n876) );
AOI22X1TS U1659 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n1352), .B0(
DmP_mant_SHT1_SW[21]), .B1(n1362), .Y(n1353) );
OAI21XLTS U1660 ( .A0(n1700), .A1(n1354), .B0(n1353), .Y(n1355) );
AOI21X1TS U1661 ( .A0(DmP_mant_SHT1_SW[20]), .A1(n1363), .B0(n1355), .Y(
n1358) );
OAI222X1TS U1662 ( .A0(n1379), .A1(n1630), .B0(n1221), .B1(n1356), .C0(n1369), .C1(n1358), .Y(n874) );
OAI222X1TS U1663 ( .A0(n1715), .A1(n1379), .B0(n1221), .B1(n1358), .C0(n1369), .C1(n1357), .Y(n872) );
AOI22X1TS U1664 ( .A0(n1363), .A1(DmP_mant_SHT1_SW[12]), .B0(n1362), .B1(
n982), .Y(n1359) );
OAI21XLTS U1665 ( .A0(n1656), .A1(n1365), .B0(n1359), .Y(n1360) );
AOI21X1TS U1666 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n955), .B0(n1360), .Y(n1367) );
OAI222X1TS U1667 ( .A0(n1649), .A1(n1379), .B0(n1221), .B1(n1361), .C0(n1369), .C1(n1367), .Y(n866) );
AOI22X1TS U1668 ( .A0(n1363), .A1(DmP_mant_SHT1_SW[10]), .B0(n1362), .B1(
n983), .Y(n1364) );
OAI21XLTS U1669 ( .A0(n1653), .A1(n1365), .B0(n1364), .Y(n1366) );
AOI21X1TS U1670 ( .A0(Raw_mant_NRM_SWR[13]), .A1(n955), .B0(n1366), .Y(n1370) );
OAI222X1TS U1671 ( .A0(n1711), .A1(n1379), .B0(n1221), .B1(n1367), .C0(n1369), .C1(n1370), .Y(n864) );
OAI222X1TS U1672 ( .A0(n1704), .A1(n1379), .B0(n1221), .B1(n1370), .C0(n1369), .C1(n1368), .Y(n862) );
AOI22X1TS U1673 ( .A0(n1210), .A1(Data_array_SWR[0]), .B0(
Raw_mant_NRM_SWR[24]), .B1(n1371), .Y(n1375) );
AOI22X1TS U1674 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n955), .B0(n1373), .B1(
n1372), .Y(n1374) );
NAND2X1TS U1675 ( .A(n1375), .B(n1374), .Y(n852) );
AOI32X1TS U1676 ( .A0(Shift_amount_SHT1_EWR[2]), .A1(n1379), .A2(n954), .B0(
shift_value_SHT2_EWR[2]), .B1(n1210), .Y(n1377) );
NAND2X1TS U1677 ( .A(n1377), .B(n1376), .Y(n851) );
AOI32X1TS U1678 ( .A0(Shift_amount_SHT1_EWR[3]), .A1(n1379), .A2(n954), .B0(
shift_value_SHT2_EWR[3]), .B1(n1210), .Y(n1381) );
NAND2X1TS U1679 ( .A(n1381), .B(n1380), .Y(n850) );
INVX4TS U1680 ( .A(n1405), .Y(n1411) );
CLKINVX1TS U1681 ( .A(DmP_EXP_EWSW[23]), .Y(n1382) );
AOI21X1TS U1682 ( .A0(DMP_EXP_EWSW[23]), .A1(n1382), .B0(n1387), .Y(n1383)
);
AOI2BB2XLTS U1683 ( .B0(n1411), .B1(n1383), .A0N(Shift_amount_SHT1_EWR[0]),
.A1N(n1632), .Y(n847) );
NOR2X1TS U1684 ( .A(n1647), .B(DMP_EXP_EWSW[24]), .Y(n1386) );
AOI21X1TS U1685 ( .A0(DMP_EXP_EWSW[24]), .A1(n1647), .B0(n1386), .Y(n1384)
);
XNOR2X1TS U1686 ( .A(n1387), .B(n1384), .Y(n1385) );
AO22XLTS U1687 ( .A0(n1632), .A1(n1385), .B0(n1413), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n846) );
OAI22X1TS U1688 ( .A0(n1387), .A1(n1386), .B0(DmP_EXP_EWSW[24]), .B1(n1648),
.Y(n1390) );
NAND2X1TS U1689 ( .A(DmP_EXP_EWSW[25]), .B(n1706), .Y(n1391) );
OAI21XLTS U1690 ( .A0(DmP_EXP_EWSW[25]), .A1(n1706), .B0(n1391), .Y(n1388)
);
XNOR2X1TS U1691 ( .A(n1390), .B(n1388), .Y(n1389) );
AO22XLTS U1692 ( .A0(n1632), .A1(n1389), .B0(n1415), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n845) );
AOI22X1TS U1693 ( .A0(DMP_EXP_EWSW[25]), .A1(n1714), .B0(n1391), .B1(n1390),
.Y(n1394) );
NOR2X1TS U1694 ( .A(n1710), .B(DMP_EXP_EWSW[26]), .Y(n1395) );
AOI21X1TS U1695 ( .A0(DMP_EXP_EWSW[26]), .A1(n1710), .B0(n1395), .Y(n1392)
);
XNOR2X1TS U1696 ( .A(n1394), .B(n1392), .Y(n1393) );
AO22XLTS U1697 ( .A0(n1632), .A1(n1393), .B0(n1405), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n844) );
OAI22X1TS U1698 ( .A0(n1395), .A1(n1394), .B0(DmP_EXP_EWSW[26]), .B1(n1713),
.Y(n1397) );
XNOR2X1TS U1699 ( .A(DmP_EXP_EWSW[27]), .B(n987), .Y(n1396) );
XOR2XLTS U1700 ( .A(n1397), .B(n1396), .Y(n1398) );
AO22XLTS U1701 ( .A0(n1632), .A1(n1398), .B0(n1415), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n843) );
OAI222X1TS U1702 ( .A0(n1175), .A1(n1712), .B0(n1648), .B1(
Shift_reg_FLAGS_7_6), .C0(n1629), .C1(n1408), .Y(n810) );
OAI222X1TS U1703 ( .A0(n1406), .A1(n1651), .B0(n1706), .B1(
Shift_reg_FLAGS_7_6), .C0(n1692), .C1(n1408), .Y(n809) );
OAI222X1TS U1704 ( .A0(n1175), .A1(n1652), .B0(n1713), .B1(
Shift_reg_FLAGS_7_6), .C0(n1691), .C1(n1408), .Y(n808) );
OAI21XLTS U1705 ( .A0(n1400), .A1(intDX_EWSW[31]), .B0(Shift_reg_FLAGS_7_6),
.Y(n1399) );
AOI21X1TS U1706 ( .A0(n1400), .A1(intDX_EWSW[31]), .B0(n1399), .Y(n1401) );
AO21XLTS U1707 ( .A0(OP_FLAG_EXP), .A1(n1086), .B0(n1401), .Y(n803) );
AO22XLTS U1708 ( .A0(n1402), .A1(n1401), .B0(ZERO_FLAG_EXP), .B1(n1086), .Y(
n802) );
AO22XLTS U1709 ( .A0(n1632), .A1(DMP_EXP_EWSW[0]), .B0(n1415), .B1(
DMP_SHT1_EWSW[0]), .Y(n800) );
AO22XLTS U1710 ( .A0(busy), .A1(DMP_SHT1_EWSW[0]), .B0(n1404), .B1(
DMP_SHT2_EWSW[0]), .Y(n799) );
NAND2X1TS U1711 ( .A(n978), .B(n1597), .Y(n1403) );
INVX4TS U1712 ( .A(n1617), .Y(n1521) );
AO22XLTS U1713 ( .A0(n1632), .A1(DMP_EXP_EWSW[1]), .B0(n1413), .B1(
DMP_SHT1_EWSW[1]), .Y(n797) );
AO22XLTS U1714 ( .A0(busy), .A1(DMP_SHT1_EWSW[1]), .B0(n1404), .B1(
DMP_SHT2_EWSW[1]), .Y(n796) );
INVX4TS U1715 ( .A(n1617), .Y(n1616) );
AO22XLTS U1716 ( .A0(n1632), .A1(DMP_EXP_EWSW[2]), .B0(n1405), .B1(
DMP_SHT1_EWSW[2]), .Y(n794) );
AO22XLTS U1717 ( .A0(busy), .A1(DMP_SHT1_EWSW[2]), .B0(n1404), .B1(
DMP_SHT2_EWSW[2]), .Y(n793) );
AO22XLTS U1718 ( .A0(n1414), .A1(DMP_EXP_EWSW[3]), .B0(n1413), .B1(
DMP_SHT1_EWSW[3]), .Y(n791) );
AO22XLTS U1719 ( .A0(busy), .A1(DMP_SHT1_EWSW[3]), .B0(n1404), .B1(
DMP_SHT2_EWSW[3]), .Y(n790) );
AO22XLTS U1720 ( .A0(n1414), .A1(DMP_EXP_EWSW[4]), .B0(n1415), .B1(
DMP_SHT1_EWSW[4]), .Y(n788) );
AO22XLTS U1721 ( .A0(busy), .A1(DMP_SHT1_EWSW[4]), .B0(n1404), .B1(
DMP_SHT2_EWSW[4]), .Y(n787) );
AO22XLTS U1722 ( .A0(n1414), .A1(DMP_EXP_EWSW[5]), .B0(n1413), .B1(
DMP_SHT1_EWSW[5]), .Y(n785) );
AO22XLTS U1723 ( .A0(busy), .A1(DMP_SHT1_EWSW[5]), .B0(n1404), .B1(
DMP_SHT2_EWSW[5]), .Y(n784) );
AO22XLTS U1724 ( .A0(n1414), .A1(DMP_EXP_EWSW[6]), .B0(n1405), .B1(
DMP_SHT1_EWSW[6]), .Y(n782) );
AO22XLTS U1725 ( .A0(busy), .A1(DMP_SHT1_EWSW[6]), .B0(n1404), .B1(
DMP_SHT2_EWSW[6]), .Y(n781) );
AO22XLTS U1726 ( .A0(n1414), .A1(DMP_EXP_EWSW[7]), .B0(n1415), .B1(
DMP_SHT1_EWSW[7]), .Y(n779) );
AO22XLTS U1727 ( .A0(busy), .A1(DMP_SHT1_EWSW[7]), .B0(n1404), .B1(
DMP_SHT2_EWSW[7]), .Y(n778) );
AO22XLTS U1728 ( .A0(n1624), .A1(DMP_SHT2_EWSW[7]), .B0(n1618), .B1(
DMP_SFG[7]), .Y(n777) );
AO22XLTS U1729 ( .A0(n1414), .A1(DMP_EXP_EWSW[8]), .B0(n1413), .B1(
DMP_SHT1_EWSW[8]), .Y(n776) );
AO22XLTS U1730 ( .A0(busy), .A1(DMP_SHT1_EWSW[8]), .B0(n1404), .B1(
DMP_SHT2_EWSW[8]), .Y(n775) );
AO22XLTS U1731 ( .A0(n1414), .A1(DMP_EXP_EWSW[9]), .B0(n1413), .B1(
DMP_SHT1_EWSW[9]), .Y(n773) );
AO22XLTS U1732 ( .A0(n1417), .A1(DMP_SHT1_EWSW[9]), .B0(n1404), .B1(
DMP_SHT2_EWSW[9]), .Y(n772) );
AO22XLTS U1733 ( .A0(n1414), .A1(DMP_EXP_EWSW[10]), .B0(n1415), .B1(
DMP_SHT1_EWSW[10]), .Y(n770) );
BUFX4TS U1734 ( .A(n1404), .Y(n1412) );
AO22XLTS U1735 ( .A0(n1417), .A1(DMP_SHT1_EWSW[10]), .B0(n1412), .B1(
DMP_SHT2_EWSW[10]), .Y(n769) );
BUFX4TS U1736 ( .A(n1716), .Y(n1415) );
AO22XLTS U1737 ( .A0(n1414), .A1(DMP_EXP_EWSW[11]), .B0(n1716), .B1(
DMP_SHT1_EWSW[11]), .Y(n767) );
AO22XLTS U1738 ( .A0(n1417), .A1(DMP_SHT1_EWSW[11]), .B0(n1412), .B1(
DMP_SHT2_EWSW[11]), .Y(n766) );
AO22XLTS U1739 ( .A0(n1414), .A1(DMP_EXP_EWSW[12]), .B0(n1413), .B1(
DMP_SHT1_EWSW[12]), .Y(n764) );
AO22XLTS U1740 ( .A0(n1417), .A1(DMP_SHT1_EWSW[12]), .B0(n1412), .B1(
DMP_SHT2_EWSW[12]), .Y(n763) );
AO22XLTS U1741 ( .A0(n1414), .A1(DMP_EXP_EWSW[13]), .B0(n1415), .B1(
DMP_SHT1_EWSW[13]), .Y(n761) );
AO22XLTS U1742 ( .A0(n1417), .A1(DMP_SHT1_EWSW[13]), .B0(n1412), .B1(
DMP_SHT2_EWSW[13]), .Y(n760) );
AO22XLTS U1743 ( .A0(n1617), .A1(DMP_SFG[13]), .B0(n1616), .B1(
DMP_SHT2_EWSW[13]), .Y(n759) );
AO22XLTS U1744 ( .A0(n1414), .A1(DMP_EXP_EWSW[14]), .B0(n1413), .B1(
DMP_SHT1_EWSW[14]), .Y(n758) );
AO22XLTS U1745 ( .A0(n1417), .A1(DMP_SHT1_EWSW[14]), .B0(n1412), .B1(
DMP_SHT2_EWSW[14]), .Y(n757) );
AO22XLTS U1746 ( .A0(n1617), .A1(DMP_SFG[14]), .B0(n1616), .B1(
DMP_SHT2_EWSW[14]), .Y(n756) );
AO22XLTS U1747 ( .A0(n1414), .A1(DMP_EXP_EWSW[15]), .B0(n1716), .B1(
DMP_SHT1_EWSW[15]), .Y(n755) );
AO22XLTS U1748 ( .A0(n1417), .A1(DMP_SHT1_EWSW[15]), .B0(n1412), .B1(
DMP_SHT2_EWSW[15]), .Y(n754) );
AO22XLTS U1749 ( .A0(n1617), .A1(DMP_SFG[15]), .B0(n1616), .B1(
DMP_SHT2_EWSW[15]), .Y(n753) );
AO22XLTS U1750 ( .A0(n1414), .A1(DMP_EXP_EWSW[16]), .B0(n1413), .B1(
DMP_SHT1_EWSW[16]), .Y(n752) );
AO22XLTS U1751 ( .A0(n1417), .A1(DMP_SHT1_EWSW[16]), .B0(n1412), .B1(
DMP_SHT2_EWSW[16]), .Y(n751) );
AO22XLTS U1752 ( .A0(n1617), .A1(DMP_SFG[16]), .B0(n1521), .B1(
DMP_SHT2_EWSW[16]), .Y(n750) );
INVX4TS U1753 ( .A(n1405), .Y(n1416) );
AO22XLTS U1754 ( .A0(n1416), .A1(DMP_EXP_EWSW[17]), .B0(n1415), .B1(
DMP_SHT1_EWSW[17]), .Y(n749) );
AO22XLTS U1755 ( .A0(n1417), .A1(DMP_SHT1_EWSW[17]), .B0(n1412), .B1(
DMP_SHT2_EWSW[17]), .Y(n748) );
AO22XLTS U1756 ( .A0(n1617), .A1(DMP_SFG[17]), .B0(n1616), .B1(
DMP_SHT2_EWSW[17]), .Y(n747) );
AO22XLTS U1757 ( .A0(n1416), .A1(DMP_EXP_EWSW[18]), .B0(n1413), .B1(
DMP_SHT1_EWSW[18]), .Y(n746) );
AO22XLTS U1758 ( .A0(busy), .A1(DMP_SHT1_EWSW[18]), .B0(n1412), .B1(
DMP_SHT2_EWSW[18]), .Y(n745) );
AO22XLTS U1759 ( .A0(n1617), .A1(DMP_SFG[18]), .B0(n1521), .B1(
DMP_SHT2_EWSW[18]), .Y(n744) );
BUFX4TS U1760 ( .A(n1716), .Y(n1405) );
AO22XLTS U1761 ( .A0(n1416), .A1(DMP_EXP_EWSW[19]), .B0(n1415), .B1(
DMP_SHT1_EWSW[19]), .Y(n743) );
AO22XLTS U1762 ( .A0(busy), .A1(DMP_SHT1_EWSW[19]), .B0(n1412), .B1(
DMP_SHT2_EWSW[19]), .Y(n742) );
AO22XLTS U1763 ( .A0(n1617), .A1(DMP_SFG[19]), .B0(n1521), .B1(
DMP_SHT2_EWSW[19]), .Y(n741) );
AO22XLTS U1764 ( .A0(n1416), .A1(DMP_EXP_EWSW[20]), .B0(n1405), .B1(
DMP_SHT1_EWSW[20]), .Y(n740) );
AO22XLTS U1765 ( .A0(busy), .A1(DMP_SHT1_EWSW[20]), .B0(n1412), .B1(
DMP_SHT2_EWSW[20]), .Y(n739) );
AO22XLTS U1766 ( .A0(n1617), .A1(DMP_SFG[20]), .B0(n1616), .B1(
DMP_SHT2_EWSW[20]), .Y(n738) );
AO22XLTS U1767 ( .A0(n1416), .A1(DMP_EXP_EWSW[21]), .B0(n1415), .B1(
DMP_SHT1_EWSW[21]), .Y(n737) );
AO22XLTS U1768 ( .A0(busy), .A1(DMP_SHT1_EWSW[21]), .B0(n1412), .B1(
DMP_SHT2_EWSW[21]), .Y(n736) );
AO22XLTS U1769 ( .A0(n1617), .A1(DMP_SFG[21]), .B0(n1616), .B1(
DMP_SHT2_EWSW[21]), .Y(n735) );
AO22XLTS U1770 ( .A0(n1416), .A1(DMP_EXP_EWSW[22]), .B0(n1415), .B1(
DMP_SHT1_EWSW[22]), .Y(n734) );
AO22XLTS U1771 ( .A0(n1417), .A1(DMP_SHT1_EWSW[22]), .B0(n1719), .B1(
DMP_SHT2_EWSW[22]), .Y(n733) );
AO22XLTS U1772 ( .A0(n1617), .A1(DMP_SFG[22]), .B0(n1521), .B1(
DMP_SHT2_EWSW[22]), .Y(n732) );
AO22XLTS U1773 ( .A0(n1416), .A1(DMP_EXP_EWSW[23]), .B0(n1413), .B1(
DMP_SHT1_EWSW[23]), .Y(n731) );
AO22XLTS U1774 ( .A0(n1417), .A1(DMP_SHT1_EWSW[23]), .B0(n1404), .B1(
DMP_SHT2_EWSW[23]), .Y(n730) );
BUFX3TS U1775 ( .A(n1617), .Y(n1520) );
AO22XLTS U1776 ( .A0(n1624), .A1(DMP_SHT2_EWSW[23]), .B0(n1520), .B1(
DMP_SFG[23]), .Y(n729) );
AO22XLTS U1777 ( .A0(n1477), .A1(DMP_SFG[23]), .B0(n1562), .B1(
DMP_exp_NRM_EW[0]), .Y(n728) );
AO22XLTS U1778 ( .A0(n1416), .A1(DMP_EXP_EWSW[24]), .B0(n1405), .B1(
DMP_SHT1_EWSW[24]), .Y(n726) );
AO22XLTS U1779 ( .A0(n1417), .A1(DMP_SHT1_EWSW[24]), .B0(n1412), .B1(
DMP_SHT2_EWSW[24]), .Y(n725) );
AO22XLTS U1780 ( .A0(n1521), .A1(DMP_SHT2_EWSW[24]), .B0(n1617), .B1(
DMP_SFG[24]), .Y(n724) );
AO22XLTS U1781 ( .A0(n1477), .A1(DMP_SFG[24]), .B0(n1562), .B1(
DMP_exp_NRM_EW[1]), .Y(n723) );
AO22XLTS U1782 ( .A0(n1416), .A1(DMP_EXP_EWSW[25]), .B0(n1413), .B1(
DMP_SHT1_EWSW[25]), .Y(n721) );
AO22XLTS U1783 ( .A0(n1417), .A1(DMP_SHT1_EWSW[25]), .B0(n1412), .B1(
DMP_SHT2_EWSW[25]), .Y(n720) );
AO22XLTS U1784 ( .A0(n1624), .A1(DMP_SHT2_EWSW[25]), .B0(n1617), .B1(
DMP_SFG[25]), .Y(n719) );
AO22XLTS U1785 ( .A0(n1477), .A1(DMP_SFG[25]), .B0(n1562), .B1(
DMP_exp_NRM_EW[2]), .Y(n718) );
AO22XLTS U1786 ( .A0(n1416), .A1(DMP_EXP_EWSW[26]), .B0(n1415), .B1(
DMP_SHT1_EWSW[26]), .Y(n716) );
AO22XLTS U1787 ( .A0(n1417), .A1(DMP_SHT1_EWSW[26]), .B0(n1412), .B1(
DMP_SHT2_EWSW[26]), .Y(n715) );
AO22XLTS U1788 ( .A0(n1521), .A1(DMP_SHT2_EWSW[26]), .B0(n1520), .B1(
DMP_SFG[26]), .Y(n714) );
AO22XLTS U1789 ( .A0(n1477), .A1(DMP_SFG[26]), .B0(n1562), .B1(
DMP_exp_NRM_EW[3]), .Y(n713) );
AO22XLTS U1790 ( .A0(n1416), .A1(n987), .B0(n1413), .B1(DMP_SHT1_EWSW[27]),
.Y(n711) );
AO22XLTS U1791 ( .A0(n1417), .A1(DMP_SHT1_EWSW[27]), .B0(n1412), .B1(
DMP_SHT2_EWSW[27]), .Y(n710) );
AO22XLTS U1792 ( .A0(n1624), .A1(DMP_SHT2_EWSW[27]), .B0(n1520), .B1(
DMP_SFG[27]), .Y(n709) );
AO22XLTS U1793 ( .A0(n1477), .A1(DMP_SFG[27]), .B0(n1562), .B1(
DMP_exp_NRM_EW[4]), .Y(n708) );
AO22XLTS U1794 ( .A0(n1416), .A1(DMP_EXP_EWSW[28]), .B0(n1716), .B1(
DMP_SHT1_EWSW[28]), .Y(n706) );
AO22XLTS U1795 ( .A0(n1417), .A1(DMP_SHT1_EWSW[28]), .B0(n1412), .B1(
DMP_SHT2_EWSW[28]), .Y(n705) );
AO22XLTS U1796 ( .A0(n1521), .A1(DMP_SHT2_EWSW[28]), .B0(n1617), .B1(
DMP_SFG[28]), .Y(n704) );
AO22XLTS U1797 ( .A0(n1477), .A1(DMP_SFG[28]), .B0(n1562), .B1(
DMP_exp_NRM_EW[5]), .Y(n703) );
AO22XLTS U1798 ( .A0(n1416), .A1(DMP_EXP_EWSW[29]), .B0(n1415), .B1(
DMP_SHT1_EWSW[29]), .Y(n701) );
AO22XLTS U1799 ( .A0(n1417), .A1(DMP_SHT1_EWSW[29]), .B0(n1412), .B1(
DMP_SHT2_EWSW[29]), .Y(n700) );
AO22XLTS U1800 ( .A0(n1521), .A1(DMP_SHT2_EWSW[29]), .B0(n1520), .B1(
DMP_SFG[29]), .Y(n699) );
AO22XLTS U1801 ( .A0(n1477), .A1(DMP_SFG[29]), .B0(n1748), .B1(
DMP_exp_NRM_EW[6]), .Y(n698) );
AO22XLTS U1802 ( .A0(n1411), .A1(DMP_EXP_EWSW[30]), .B0(n1413), .B1(
DMP_SHT1_EWSW[30]), .Y(n696) );
AO22XLTS U1803 ( .A0(n1417), .A1(DMP_SHT1_EWSW[30]), .B0(n1412), .B1(
DMP_SHT2_EWSW[30]), .Y(n695) );
AO22XLTS U1804 ( .A0(n1624), .A1(DMP_SHT2_EWSW[30]), .B0(n1520), .B1(
DMP_SFG[30]), .Y(n694) );
AO22XLTS U1805 ( .A0(n953), .A1(DMP_SFG[30]), .B0(n1748), .B1(
DMP_exp_NRM_EW[7]), .Y(n693) );
AO22XLTS U1806 ( .A0(n1414), .A1(DmP_EXP_EWSW[14]), .B0(n1405), .B1(
DmP_mant_SHT1_SW[14]), .Y(n662) );
AO22XLTS U1807 ( .A0(n1414), .A1(DmP_EXP_EWSW[16]), .B0(n1405), .B1(
DmP_mant_SHT1_SW[16]), .Y(n658) );
AO22XLTS U1808 ( .A0(n1414), .A1(DmP_EXP_EWSW[19]), .B0(n1716), .B1(n980),
.Y(n652) );
AO22XLTS U1809 ( .A0(n1414), .A1(DmP_EXP_EWSW[22]), .B0(n1415), .B1(
DmP_mant_SHT1_SW[22]), .Y(n646) );
OAI222X1TS U1810 ( .A0(n1408), .A1(n1712), .B0(n1647), .B1(
Shift_reg_FLAGS_7_6), .C0(n1629), .C1(n1406), .Y(n644) );
OAI222X1TS U1811 ( .A0(n1408), .A1(n1651), .B0(n1714), .B1(
Shift_reg_FLAGS_7_6), .C0(n1692), .C1(n1175), .Y(n643) );
OAI222X1TS U1812 ( .A0(n1408), .A1(n1652), .B0(n1710), .B1(
Shift_reg_FLAGS_7_6), .C0(n1691), .C1(n1406), .Y(n642) );
INVX4TS U1813 ( .A(n1409), .Y(n1594) );
NAND2X1TS U1814 ( .A(n1515), .B(Shift_reg_FLAGS_7[0]), .Y(n1410) );
OAI2BB1X1TS U1815 ( .A0N(underflow_flag), .A1N(n1594), .B0(n1410), .Y(n640)
);
AO22XLTS U1816 ( .A0(n1411), .A1(ZERO_FLAG_EXP), .B0(n1405), .B1(
ZERO_FLAG_SHT1), .Y(n638) );
AO22XLTS U1817 ( .A0(n1417), .A1(ZERO_FLAG_SHT1), .B0(n1412), .B1(
ZERO_FLAG_SHT2), .Y(n637) );
AO22XLTS U1818 ( .A0(n1624), .A1(ZERO_FLAG_SHT2), .B0(n1520), .B1(
ZERO_FLAG_SFG), .Y(n636) );
AO22XLTS U1819 ( .A0(n1477), .A1(ZERO_FLAG_SFG), .B0(n1748), .B1(
ZERO_FLAG_NRM), .Y(n635) );
AO22XLTS U1820 ( .A0(Shift_reg_FLAGS_7[0]), .A1(ZERO_FLAG_SHT1SHT2), .B0(
n1594), .B1(zero_flag), .Y(n633) );
AO22XLTS U1821 ( .A0(n1414), .A1(OP_FLAG_EXP), .B0(n1413), .B1(OP_FLAG_SHT1),
.Y(n632) );
AO22XLTS U1822 ( .A0(n1417), .A1(OP_FLAG_SHT1), .B0(n1719), .B1(OP_FLAG_SHT2), .Y(n631) );
AO22XLTS U1823 ( .A0(n1617), .A1(n1506), .B0(n1616), .B1(OP_FLAG_SHT2), .Y(
n630) );
AO22XLTS U1824 ( .A0(n1416), .A1(SIGN_FLAG_EXP), .B0(n1413), .B1(
SIGN_FLAG_SHT1), .Y(n629) );
AO22XLTS U1825 ( .A0(n1417), .A1(SIGN_FLAG_SHT1), .B0(n1719), .B1(
SIGN_FLAG_SHT2), .Y(n628) );
AO22XLTS U1826 ( .A0(n1521), .A1(SIGN_FLAG_SHT2), .B0(n1520), .B1(
SIGN_FLAG_SFG), .Y(n627) );
AO22XLTS U1827 ( .A0(n953), .A1(SIGN_FLAG_SFG), .B0(n1562), .B1(
SIGN_FLAG_NRM), .Y(n626) );
INVX1TS U1828 ( .A(DmP_mant_SFG_SWR[15]), .Y(n1599) );
AOI22X1TS U1829 ( .A0(n1506), .A1(n1599), .B0(DmP_mant_SFG_SWR[15]), .B1(
n1639), .Y(intadd_5_CI) );
AOI2BB2XLTS U1830 ( .B0(n953), .B1(intadd_5_SUM_0_), .A0N(
Raw_mant_NRM_SWR[15]), .A1N(n1477), .Y(n623) );
INVX1TS U1831 ( .A(DmP_mant_SFG_SWR[16]), .Y(n1601) );
AOI22X1TS U1832 ( .A0(n1506), .A1(n1601), .B0(DmP_mant_SFG_SWR[16]), .B1(
n1639), .Y(intadd_5_B_1_) );
AOI22X1TS U1833 ( .A0(n1564), .A1(intadd_5_SUM_1_), .B0(n1631), .B1(n1562),
.Y(n622) );
INVX1TS U1834 ( .A(DmP_mant_SFG_SWR[17]), .Y(n1603) );
AOI22X1TS U1835 ( .A0(n1506), .A1(n1603), .B0(DmP_mant_SFG_SWR[17]), .B1(
n1505), .Y(intadd_5_B_2_) );
AOI22X1TS U1836 ( .A0(n1564), .A1(intadd_5_SUM_2_), .B0(n1628), .B1(n1562),
.Y(n621) );
INVX1TS U1837 ( .A(DmP_mant_SFG_SWR[18]), .Y(n1605) );
AOI22X1TS U1838 ( .A0(n1506), .A1(n1605), .B0(DmP_mant_SFG_SWR[18]), .B1(
n1505), .Y(intadd_5_B_3_) );
AOI2BB2XLTS U1839 ( .B0(n953), .B1(intadd_5_SUM_3_), .A0N(
Raw_mant_NRM_SWR[18]), .A1N(n1477), .Y(n620) );
INVX1TS U1840 ( .A(DmP_mant_SFG_SWR[19]), .Y(n1607) );
AOI22X1TS U1841 ( .A0(n1506), .A1(n1607), .B0(DmP_mant_SFG_SWR[19]), .B1(
n1505), .Y(intadd_5_B_4_) );
AOI2BB2XLTS U1842 ( .B0(n953), .B1(intadd_5_SUM_4_), .A0N(
Raw_mant_NRM_SWR[19]), .A1N(n1477), .Y(n619) );
INVX1TS U1843 ( .A(DmP_mant_SFG_SWR[20]), .Y(n1609) );
AOI22X1TS U1844 ( .A0(DmP_mant_SFG_SWR[20]), .A1(n1505), .B0(n1506), .B1(
n1609), .Y(intadd_5_B_5_) );
AOI2BB2XLTS U1845 ( .B0(n953), .B1(intadd_5_SUM_5_), .A0N(
Raw_mant_NRM_SWR[20]), .A1N(n1477), .Y(n618) );
INVX1TS U1846 ( .A(DmP_mant_SFG_SWR[21]), .Y(n1611) );
AOI22X1TS U1847 ( .A0(DmP_mant_SFG_SWR[21]), .A1(n1505), .B0(n1506), .B1(
n1611), .Y(intadd_5_B_6_) );
AOI22X1TS U1848 ( .A0(n953), .A1(intadd_5_SUM_6_), .B0(n1627), .B1(n1562),
.Y(n617) );
AOI2BB2XLTS U1849 ( .B0(DmP_mant_SFG_SWR[22]), .B1(n1505), .A0N(n1505),
.A1N(DmP_mant_SFG_SWR[22]), .Y(intadd_5_B_7_) );
AOI22X1TS U1850 ( .A0(n953), .A1(intadd_5_SUM_7_), .B0(n1625), .B1(n1562),
.Y(n616) );
AOI2BB2XLTS U1851 ( .B0(DmP_mant_SFG_SWR[23]), .B1(n1505), .A0N(n1505),
.A1N(DmP_mant_SFG_SWR[23]), .Y(intadd_5_B_8_) );
AOI22X1TS U1852 ( .A0(n1564), .A1(intadd_5_SUM_8_), .B0(n961), .B1(n1562),
.Y(n615) );
AOI22X1TS U1853 ( .A0(DmP_mant_SFG_SWR[24]), .A1(n1505), .B0(n1002), .B1(
n993), .Y(intadd_5_B_9_) );
AOI22X1TS U1854 ( .A0(n1564), .A1(intadd_5_SUM_9_), .B0(n995), .B1(n1562),
.Y(n614) );
AOI22X1TS U1855 ( .A0(DmP_mant_SFG_SWR[25]), .A1(n1506), .B0(n1505), .B1(
n994), .Y(n1418) );
XNOR2X1TS U1856 ( .A(intadd_5_n1), .B(n1418), .Y(n1419) );
AOI22X1TS U1857 ( .A0(n1564), .A1(n1419), .B0(n1626), .B1(n1562), .Y(n613)
);
NAND2X2TS U1858 ( .A(n1655), .B(n1445), .Y(n1544) );
NOR2X2TS U1859 ( .A(shift_value_SHT2_EWR[3]), .B(n1661), .Y(n1471) );
INVX2TS U1860 ( .A(n1471), .Y(n1453) );
AOI22X1TS U1861 ( .A0(Data_array_SWR[18]), .A1(n1420), .B0(
Data_array_SWR[15]), .B1(n1421), .Y(n1422) );
OAI21X1TS U1862 ( .A0(n1646), .A1(n1543), .B0(n1422), .Y(n1531) );
INVX2TS U1863 ( .A(n1421), .Y(n1542) );
OAI22X1TS U1864 ( .A0(n1630), .A1(n1544), .B0(n1697), .B1(n1542), .Y(n1532)
);
NOR2X2TS U1865 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n1470) );
INVX2TS U1866 ( .A(n1470), .Y(n1452) );
NAND2X2TS U1867 ( .A(n1592), .B(n1456), .Y(n1591) );
NAND2X2TS U1868 ( .A(n1621), .B(n1456), .Y(n1548) );
OAI22X1TS U1869 ( .A0(n1649), .A1(n1591), .B0(n1705), .B1(n1548), .Y(n1423)
);
AOI221X1TS U1870 ( .A0(n1621), .A1(n1531), .B0(n1592), .B1(n1532), .C0(n1423), .Y(n1566) );
AOI22X1TS U1871 ( .A0(n1613), .A1(n1566), .B0(n1617), .B1(n996), .Y(n612) );
INVX1TS U1872 ( .A(DmP_mant_SFG_SWR[11]), .Y(n1533) );
AOI22X1TS U1873 ( .A0(n1506), .A1(DmP_mant_SFG_SWR[11]), .B0(n1533), .B1(
n1639), .Y(n1522) );
CLKAND2X2TS U1874 ( .A(DMP_SFG[9]), .B(n1522), .Y(n1559) );
NAND2BX1TS U1875 ( .AN(DMP_SFG[10]), .B(n1424), .Y(n1536) );
OAI2BB1X1TS U1876 ( .A0N(n1559), .A1N(n1536), .B0(n1537), .Y(n1523) );
INVX2TS U1877 ( .A(n1523), .Y(n1425) );
OAI21XLTS U1878 ( .A0(n1425), .A1(n1525), .B0(n1524), .Y(n1426) );
XNOR2X1TS U1879 ( .A(n1427), .B(n1426), .Y(n1428) );
AOI22X1TS U1880 ( .A0(n1564), .A1(n1428), .B0(n1633), .B1(n1562), .Y(n611)
);
AOI22X1TS U1881 ( .A0(Data_array_SWR[13]), .A1(n1429), .B0(Data_array_SWR[9]), .B1(n1420), .Y(n1431) );
AOI22X1TS U1882 ( .A0(Data_array_SWR[5]), .A1(n1421), .B0(Data_array_SWR[1]),
.B1(n1456), .Y(n1430) );
OAI211X1TS U1883 ( .A0(n1436), .A1(n1655), .B0(n1431), .C0(n1430), .Y(n1596)
);
AOI22X1TS U1884 ( .A0(Data_array_SWR[22]), .A1(n1588), .B0(n1592), .B1(n1596), .Y(n1432) );
AOI22X1TS U1885 ( .A0(n1613), .A1(n1432), .B0(n1520), .B1(n997), .Y(n609) );
AOI22X1TS U1886 ( .A0(DmP_mant_SFG_SWR[1]), .A1(n1505), .B0(n1002), .B1(n997), .Y(n1433) );
AOI2BB2XLTS U1887 ( .B0(n953), .B1(n1433), .A0N(Raw_mant_NRM_SWR[1]), .A1N(
n953), .Y(n608) );
AOI22X1TS U1888 ( .A0(Data_array_SWR[12]), .A1(n1421), .B0(
Data_array_SWR[16]), .B1(n1420), .Y(n1435) );
NOR2X2TS U1889 ( .A(n1655), .B(n1452), .Y(n1499) );
AOI22X1TS U1890 ( .A0(Data_array_SWR[19]), .A1(n1429), .B0(
Data_array_SWR[22]), .B1(n1499), .Y(n1434) );
NAND2X1TS U1891 ( .A(n1435), .B(n1434), .Y(n1589) );
INVX2TS U1892 ( .A(n1436), .Y(n1587) );
AOI22X1TS U1893 ( .A0(n1613), .A1(n1585), .B0(n998), .B1(n1520), .Y(n606) );
INVX1TS U1894 ( .A(DmP_mant_SFG_SWR[7]), .Y(n1490) );
AOI22X1TS U1895 ( .A0(n1506), .A1(n1490), .B0(DmP_mant_SFG_SWR[7]), .B1(
n1505), .Y(n1438) );
NAND2BX1TS U1896 ( .AN(DMP_SFG[5]), .B(n1438), .Y(n1493) );
INVX1TS U1897 ( .A(DmP_mant_SFG_SWR[6]), .Y(n1459) );
AOI22X1TS U1898 ( .A0(n1506), .A1(DmP_mant_SFG_SWR[6]), .B0(n1459), .B1(
n1639), .Y(n1437) );
AOI22X1TS U1899 ( .A0(DmP_mant_SFG_SWR[5]), .A1(n1506), .B0(n1639), .B1(
n1000), .Y(n1460) );
NAND2X1TS U1900 ( .A(n1460), .B(DMP_SFG[3]), .Y(n1462) );
NAND2X1TS U1901 ( .A(n1437), .B(DMP_SFG[4]), .Y(n1482) );
OAI21XLTS U1902 ( .A0(n1484), .A1(n1462), .B0(n1482), .Y(n1440) );
INVX2TS U1903 ( .A(n1438), .Y(n1439) );
CLKAND2X2TS U1904 ( .A(DMP_SFG[5]), .B(n1439), .Y(n1491) );
AOI21X1TS U1905 ( .A0(n1493), .A1(n1440), .B0(n1491), .Y(n1443) );
OAI22X1TS U1906 ( .A0(n1505), .A1(n998), .B0(DmP_mant_SFG_SWR[8]), .B1(n1506), .Y(n1441) );
NAND2BX1TS U1907 ( .AN(n1441), .B(DMP_SFG[6]), .Y(n1553) );
NAND2BX1TS U1908 ( .AN(DMP_SFG[6]), .B(n1441), .Y(n1492) );
NAND2X1TS U1909 ( .A(n1553), .B(n1492), .Y(n1442) );
XNOR2X1TS U1910 ( .A(n1443), .B(n1442), .Y(n1444) );
AOI2BB2XLTS U1911 ( .B0(n953), .B1(n1444), .A0N(Raw_mant_NRM_SWR[8]), .A1N(
n1564), .Y(n605) );
AOI22X1TS U1912 ( .A0(Data_array_SWR[12]), .A1(n1429), .B0(Data_array_SWR[8]), .B1(n1420), .Y(n1447) );
AOI22X1TS U1913 ( .A0(Data_array_SWR[4]), .A1(n1421), .B0(Data_array_SWR[0]),
.B1(n1456), .Y(n1446) );
OAI211X1TS U1914 ( .A0(n1502), .A1(n1655), .B0(n1447), .C0(n1446), .Y(n1620)
);
AOI22X1TS U1915 ( .A0(Data_array_SWR[23]), .A1(n1588), .B0(n1592), .B1(n1620), .Y(n1448) );
AOI22X1TS U1916 ( .A0(n1624), .A1(n1448), .B0(n1618), .B1(n999), .Y(n603) );
AOI22X1TS U1917 ( .A0(DmP_mant_SFG_SWR[0]), .A1(n1505), .B0(n1506), .B1(n999), .Y(n1449) );
AOI2BB2XLTS U1918 ( .B0(n953), .B1(n1449), .A0N(n988), .A1N(n1477), .Y(n602)
);
OAI22X1TS U1919 ( .A0(n1649), .A1(n1543), .B0(n1704), .B1(n1544), .Y(n1451)
);
AO22XLTS U1920 ( .A0(n1572), .A1(shift_value_SHT2_EWR[4]), .B0(
Data_array_SWR[6]), .B1(n1421), .Y(n1450) );
OAI22X1TS U1921 ( .A0(n1621), .A1(n1593), .B0(n1646), .B1(n1548), .Y(n1584)
);
OAI22X1TS U1922 ( .A0(n1650), .A1(n1543), .B0(n1705), .B1(n1544), .Y(n1455)
);
AO22XLTS U1923 ( .A0(n1581), .A1(shift_value_SHT2_EWR[4]), .B0(
Data_array_SWR[7]), .B1(n1421), .Y(n1454) );
OAI22X1TS U1924 ( .A0(n1621), .A1(n1590), .B0(n1630), .B1(n1548), .Y(n1583)
);
AOI22X1TS U1925 ( .A0(Data_array_SWR[14]), .A1(n1420), .B0(
Data_array_SWR[10]), .B1(n1421), .Y(n1458) );
AOI22X1TS U1926 ( .A0(Data_array_SWR[20]), .A1(n1499), .B0(
Data_array_SWR[17]), .B1(n1429), .Y(n1457) );
NAND2X1TS U1927 ( .A(n1458), .B(n1457), .Y(n1582) );
AOI22X1TS U1928 ( .A0(n1613), .A1(n1580), .B0(n1459), .B1(n1617), .Y(n595)
);
INVX2TS U1929 ( .A(n1482), .Y(n1494) );
NOR2XLTS U1930 ( .A(n1494), .B(n1484), .Y(n1466) );
INVX2TS U1931 ( .A(n1472), .Y(n1463) );
INVX2TS U1932 ( .A(n1462), .Y(n1473) );
OAI21XLTS U1933 ( .A0(n1472), .A1(n1464), .B0(n1483), .Y(n1465) );
XNOR2X1TS U1934 ( .A(n1466), .B(n1465), .Y(n1467) );
AOI22X1TS U1935 ( .A0(n1564), .A1(n1467), .B0(n1659), .B1(n1748), .Y(n594)
);
AOI22X1TS U1936 ( .A0(Data_array_SWR[19]), .A1(n1470), .B0(
Data_array_SWR[22]), .B1(n1471), .Y(n1481) );
AOI22X1TS U1937 ( .A0(Data_array_SWR[12]), .A1(n1420), .B0(Data_array_SWR[8]), .B1(n1421), .Y(n1469) );
NAND2X1TS U1938 ( .A(Data_array_SWR[16]), .B(n1429), .Y(n1468) );
OAI211X1TS U1939 ( .A0(n1481), .A1(n1655), .B0(n1469), .C0(n1468), .Y(n1579)
);
AO22X1TS U1940 ( .A0(Data_array_SWR[23]), .A1(n1471), .B0(n989), .B1(n1470),
.Y(n1578) );
AOI22X1TS U1941 ( .A0(n1613), .A1(n1577), .B0(n1617), .B1(n1001), .Y(n592)
);
CMPR32X2TS U1942 ( .A(DMP_SFG[2]), .B(n977), .C(n1474), .CO(n1475), .S(n1008) );
XNOR2X1TS U1943 ( .A(n1476), .B(n1475), .Y(n1478) );
AOI2BB2XLTS U1944 ( .B0(n953), .B1(n1478), .A0N(Raw_mant_NRM_SWR[5]), .A1N(
n1477), .Y(n591) );
AOI22X1TS U1945 ( .A0(Data_array_SWR[13]), .A1(n1420), .B0(Data_array_SWR[9]), .B1(n1421), .Y(n1480) );
AOI22X1TS U1946 ( .A0(n990), .A1(n1429), .B0(shift_value_SHT2_EWR[4]), .B1(
n1578), .Y(n1479) );
NAND2X1TS U1947 ( .A(n1480), .B(n1479), .Y(n1576) );
INVX2TS U1948 ( .A(n1481), .Y(n1575) );
AOI22X1TS U1949 ( .A0(n1624), .A1(n1574), .B0(n1618), .B1(n1000), .Y(n590)
);
NOR2BX1TS U1950 ( .AN(n1493), .B(n1491), .Y(n1486) );
OAI21XLTS U1951 ( .A0(n1484), .A1(n1483), .B0(n1482), .Y(n1485) );
XNOR2X1TS U1952 ( .A(n1486), .B(n1485), .Y(n1487) );
AOI22X1TS U1953 ( .A0(n1564), .A1(n1487), .B0(n1654), .B1(n1748), .Y(n589)
);
AOI22X1TS U1954 ( .A0(Data_array_SWR[15]), .A1(n1420), .B0(
Data_array_SWR[11]), .B1(n1421), .Y(n1489) );
AOI22X1TS U1955 ( .A0(Data_array_SWR[21]), .A1(n1499), .B0(
Data_array_SWR[18]), .B1(n1429), .Y(n1488) );
NAND2X1TS U1956 ( .A(n1489), .B(n1488), .Y(n1573) );
AOI22X1TS U1957 ( .A0(n1613), .A1(n1571), .B0(n1490), .B1(n1618), .Y(n588)
);
OAI2BB1X1TS U1958 ( .A0N(n1491), .A1N(n1492), .B0(n1553), .Y(n1508) );
AOI31XLTS U1959 ( .A0(n1494), .A1(n1493), .A2(n1492), .B0(n1508), .Y(n1497)
);
INVX1TS U1960 ( .A(DmP_mant_SFG_SWR[9]), .Y(n1504) );
AOI22X1TS U1961 ( .A0(n1506), .A1(DmP_mant_SFG_SWR[9]), .B0(n1504), .B1(
n1505), .Y(n1495) );
NAND2X1TS U1962 ( .A(n1495), .B(DMP_SFG[7]), .Y(n1552) );
NOR2BX1TS U1963 ( .AN(n1552), .B(n1554), .Y(n1496) );
XOR2X1TS U1964 ( .A(n1497), .B(n1496), .Y(n1498) );
AOI22X1TS U1965 ( .A0(n1564), .A1(n1498), .B0(n1664), .B1(n1748), .Y(n587)
);
AOI22X1TS U1966 ( .A0(n990), .A1(n1420), .B0(Data_array_SWR[13]), .B1(n1421),
.Y(n1501) );
AOI22X1TS U1967 ( .A0(n989), .A1(n1429), .B0(Data_array_SWR[23]), .B1(n1499),
.Y(n1500) );
NAND2X1TS U1968 ( .A(n1501), .B(n1500), .Y(n1570) );
INVX2TS U1969 ( .A(n1502), .Y(n1569) );
AOI22X1TS U1970 ( .A0(n1624), .A1(n1568), .B0(n1504), .B1(n1618), .Y(n586)
);
INVX1TS U1971 ( .A(DmP_mant_SFG_SWR[10]), .Y(n1546) );
AOI22X1TS U1972 ( .A0(n1506), .A1(DmP_mant_SFG_SWR[10]), .B0(n1546), .B1(
n1505), .Y(n1507) );
NAND2X1TS U1973 ( .A(n1507), .B(DMP_SFG[8]), .Y(n1534) );
INVX2TS U1974 ( .A(n1534), .Y(n1557) );
NOR2X2TS U1975 ( .A(n1507), .B(DMP_SFG[8]), .Y(n1555) );
NOR2XLTS U1976 ( .A(n1557), .B(n1555), .Y(n1511) );
INVX2TS U1977 ( .A(n1508), .Y(n1509) );
XNOR2X1TS U1978 ( .A(n1511), .B(n1510), .Y(n1512) );
AOI22X1TS U1979 ( .A0(n1564), .A1(n1512), .B0(n1656), .B1(n1748), .Y(n585)
);
AOI22X1TS U1980 ( .A0(Data_array_SWR[12]), .A1(n1622), .B0(
Data_array_SWR[13]), .B1(n1588), .Y(n1513) );
OAI221X1TS U1981 ( .A0(n1621), .A1(n1518), .B0(n1592), .B1(n1519), .C0(n1513), .Y(n1516) );
AO22XLTS U1982 ( .A0(n1595), .A1(n1516), .B0(final_result_ieee[10]), .B1(
n1594), .Y(n583) );
AOI22X1TS U1983 ( .A0(Data_array_SWR[12]), .A1(n1588), .B0(
Data_array_SWR[13]), .B1(n1622), .Y(n1517) );
OAI221X1TS U1984 ( .A0(n1621), .A1(n1519), .B0(n1592), .B1(n1518), .C0(n1517), .Y(n1567) );
OR2X1TS U1985 ( .A(DMP_SFG[9]), .B(n1522), .Y(n1558) );
AOI31XLTS U1986 ( .A0(n1557), .A1(n1536), .A2(n1558), .B0(n1523), .Y(n1527)
);
XNOR2X1TS U1987 ( .A(n1527), .B(n1526), .Y(n1528) );
AOI2BB2XLTS U1988 ( .B0(n953), .B1(n1528), .A0N(Raw_mant_NRM_SWR[13]), .A1N(
n953), .Y(n581) );
OAI22X1TS U1989 ( .A0(n1649), .A1(n1548), .B0(n1705), .B1(n1591), .Y(n1530)
);
AOI221X1TS U1990 ( .A0(n1621), .A1(n1532), .B0(n1592), .B1(n1531), .C0(n1530), .Y(n1565) );
AOI22X1TS U1991 ( .A0(n1624), .A1(n1565), .B0(n1533), .B1(n1618), .Y(n580)
);
OAI21XLTS U1992 ( .A0(n1555), .A1(n1552), .B0(n1534), .Y(n1535) );
AOI21X1TS U1993 ( .A0(n1558), .A1(n1535), .B0(n1559), .Y(n1539) );
NAND2X1TS U1994 ( .A(n1537), .B(n1536), .Y(n1538) );
XNOR2X1TS U1995 ( .A(n1539), .B(n1538), .Y(n1541) );
AOI22X1TS U1996 ( .A0(n1564), .A1(n1541), .B0(n1653), .B1(n1748), .Y(n579)
);
OAI22X1TS U1997 ( .A0(n1646), .A1(n1544), .B0(n1701), .B1(n1542), .Y(n1550)
);
OAI222X1TS U1998 ( .A0(n1544), .A1(n1697), .B0(n1543), .B1(n1630), .C0(n1542), .C1(n1649), .Y(n1551) );
OAI22X1TS U1999 ( .A0(n1704), .A1(n1591), .B0(n1650), .B1(n1548), .Y(n1545)
);
AOI221X1TS U2000 ( .A0(n1621), .A1(n1550), .B0(n1592), .B1(n1551), .C0(n1545), .Y(n1547) );
AOI22X1TS U2001 ( .A0(n1624), .A1(n1547), .B0(n1546), .B1(n1618), .Y(n578)
);
INVX4TS U2002 ( .A(n1595), .Y(n1598) );
OAI2BB2XLTS U2003 ( .B0(n1547), .B1(n1598), .A0N(final_result_ieee[8]),
.A1N(n1594), .Y(n577) );
OAI22X1TS U2004 ( .A0(n1704), .A1(n1548), .B0(n1650), .B1(n1591), .Y(n1549)
);
AOI221X1TS U2005 ( .A0(n1621), .A1(n1551), .B0(n1592), .B1(n1550), .C0(n1549), .Y(n1600) );
OAI2BB2XLTS U2006 ( .B0(n1600), .B1(n1598), .A0N(final_result_ieee[13]),
.A1N(n1594), .Y(n576) );
OAI32X1TS U2007 ( .A0(n1555), .A1(n1554), .A2(n1553), .B0(n1552), .B1(n1555),
.Y(n1556) );
NOR2XLTS U2008 ( .A(n1557), .B(n1556), .Y(n1561) );
NAND2BXLTS U2009 ( .AN(n1559), .B(n1558), .Y(n1560) );
XNOR2X1TS U2010 ( .A(n1561), .B(n1560), .Y(n1563) );
AOI22X1TS U2011 ( .A0(n1564), .A1(n1563), .B0(n1634), .B1(n1562), .Y(n575)
);
OAI2BB2XLTS U2012 ( .B0(n1565), .B1(n1598), .A0N(final_result_ieee[9]),
.A1N(n1594), .Y(n574) );
OAI2BB2XLTS U2013 ( .B0(n1566), .B1(n1598), .A0N(final_result_ieee[12]),
.A1N(n1594), .Y(n573) );
AO22XLTS U2014 ( .A0(n1595), .A1(n1567), .B0(final_result_ieee[11]), .B1(
n1594), .Y(n572) );
OAI2BB2XLTS U2015 ( .B0(n1568), .B1(n1598), .A0N(final_result_ieee[7]),
.A1N(n1594), .Y(n571) );
OAI2BB2XLTS U2016 ( .B0(n1602), .B1(n1598), .A0N(final_result_ieee[14]),
.A1N(n1594), .Y(n570) );
OAI2BB2XLTS U2017 ( .B0(n1571), .B1(n1598), .A0N(final_result_ieee[5]),
.A1N(n1597), .Y(n569) );
OAI2BB2XLTS U2018 ( .B0(n1606), .B1(n1598), .A0N(final_result_ieee[16]),
.A1N(n1597), .Y(n568) );
OAI2BB2XLTS U2019 ( .B0(n1574), .B1(n1598), .A0N(final_result_ieee[3]),
.A1N(n1597), .Y(n567) );
OAI2BB2XLTS U2020 ( .B0(n1610), .B1(n1598), .A0N(final_result_ieee[18]),
.A1N(n1597), .Y(n566) );
OAI2BB2XLTS U2021 ( .B0(n1577), .B1(n1598), .A0N(final_result_ieee[2]),
.A1N(n1597), .Y(n565) );
OAI2BB2XLTS U2022 ( .B0(n1612), .B1(n1598), .A0N(final_result_ieee[19]),
.A1N(n1597), .Y(n564) );
OAI2BB2XLTS U2023 ( .B0(n1580), .B1(n1598), .A0N(final_result_ieee[4]),
.A1N(n1597), .Y(n563) );
OAI2BB2XLTS U2024 ( .B0(n1608), .B1(n1598), .A0N(final_result_ieee[17]),
.A1N(n1597), .Y(n562) );
AO22XLTS U2025 ( .A0(n1595), .A1(n1583), .B0(final_result_ieee[1]), .B1(
n1594), .Y(n561) );
AO22XLTS U2026 ( .A0(n1595), .A1(n1584), .B0(final_result_ieee[0]), .B1(
n1594), .Y(n560) );
OAI2BB2XLTS U2027 ( .B0(n1585), .B1(n1598), .A0N(final_result_ieee[6]),
.A1N(n1597), .Y(n559) );
OAI2BB2XLTS U2028 ( .B0(n1604), .B1(n1598), .A0N(final_result_ieee[15]),
.A1N(n1594), .Y(n558) );
OAI22X1TS U2029 ( .A0(n1590), .A1(n1592), .B0(n1630), .B1(n1591), .Y(n1614)
);
AO22XLTS U2030 ( .A0(n1595), .A1(n1614), .B0(final_result_ieee[20]), .B1(
n1594), .Y(n557) );
OAI22X1TS U2031 ( .A0(n1593), .A1(n1592), .B0(n1646), .B1(n1591), .Y(n1615)
);
AO22XLTS U2032 ( .A0(n1595), .A1(n1615), .B0(final_result_ieee[21]), .B1(
n1594), .Y(n556) );
AOI22X1TS U2033 ( .A0(Data_array_SWR[22]), .A1(n1622), .B0(n1621), .B1(n1596), .Y(n1619) );
OAI2BB2XLTS U2034 ( .B0(n1619), .B1(n1598), .A0N(final_result_ieee[22]),
.A1N(n1597), .Y(n555) );
AOI22X1TS U2035 ( .A0(n1613), .A1(n1600), .B0(n1599), .B1(n1618), .Y(n554)
);
AOI22X1TS U2036 ( .A0(n1613), .A1(n1602), .B0(n1601), .B1(n1618), .Y(n553)
);
AOI22X1TS U2037 ( .A0(n1613), .A1(n1604), .B0(n1603), .B1(n1618), .Y(n552)
);
AOI22X1TS U2038 ( .A0(n1613), .A1(n1606), .B0(n1605), .B1(n1618), .Y(n551)
);
AOI22X1TS U2039 ( .A0(n1613), .A1(n1608), .B0(n1607), .B1(n1618), .Y(n550)
);
AOI22X1TS U2040 ( .A0(n1613), .A1(n1610), .B0(n1609), .B1(n1618), .Y(n549)
);
AOI22X1TS U2041 ( .A0(n1613), .A1(n1612), .B0(n1611), .B1(n1618), .Y(n548)
);
AO22XLTS U2042 ( .A0(n1617), .A1(DmP_mant_SFG_SWR[22]), .B0(n1616), .B1(
n1614), .Y(n547) );
AO22XLTS U2043 ( .A0(n1617), .A1(DmP_mant_SFG_SWR[23]), .B0(n1616), .B1(
n1615), .Y(n546) );
AOI22X1TS U2044 ( .A0(n1613), .A1(n1619), .B0(n1618), .B1(n993), .Y(n545) );
AOI22X1TS U2045 ( .A0(Data_array_SWR[23]), .A1(n1622), .B0(n1621), .B1(n1620), .Y(n1623) );
AOI22X1TS U2046 ( .A0(n1613), .A1(n1623), .B0(n1617), .B1(n994), .Y(n544) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk40.tcl_ACAIN16Q4_syn.sdf");
endmodule
|
module test ( n0 , n1 , n2 , n3 , n4 , n5 , n6 , n7 , n8 , n9 , n10 ,
n11 , n12 , n13 , n14 , n15 , n16 , n17 , n18 , n19 , n20 ,
n21 , n22 , n23 , n24 , n25 , n26 , n27 , n28 , n29 , n30 ,
n31 , n32 , n33 , n34 , n35 , n36 , n37 , n38 , n39 , n40 ,
n41 , n42 , n43 , n44 , n45 , n46 , n47 , n48 , n49 , n50 ,
n51 , n52 , n53 , n54 , n55 , n56 , n57 , n58 , n59 , n60 ,
n61 , n62 , n63 , n64 , n65 , n66 , n67 , n68 , n69 , n70 ,
n71 , n72 , n73 , n74 , n75 , n76 , n77 , n78 , n79 , n80 ,
n81 , n82 , n83 , n84 , n85 , n86 , n87 , n88 , n89 , n90 ,
n91 , n92 , n93 , n94 , n95 , n96 , n97 , n98 , n99 , n100 ,
n101 , n102 , n103 , n104 , n105 , n106 , n107 , n108 , n109 , n110 ,
n111 , n112 , n113 , n114 , n115 , n116 , n117 , n118 , n119 , n120 ,
n121 , n122 , n123 , n124 , n125 , n126 , n127 , n128 , n129 , n130 ,
n131 , n132 , n133 , n134 , n135 , n136 , n137 , n138 , n139 , n140 ,
n141 , n142 , n143 , n144 , n145 , n146 , n147 , n148 , n149 , n150 ,
n151 , n152 , n153 , n154 , n155 , n156 , n157 , n158 , n159 , n160 ,
n161 , n162 , n163 , n164 , n165 , n166 , n167 , n168 , n169 , n170 ,
n171 , n172 , n173 , n174 , n175 , n176 , n177 , n178 , n179 , n180 ,
n181 , n182 , n183 , n184 );
input n0 , n1 , n2 , n3 , n4 , n5 , n6 , n7 , n8 , n9 , n10 ,
n11 , n12 , n13 , n14 , n15 , n16 , n17 , n18 , n19 , n20 ,
n21 , n22 , n23 , n24 , n25 , n26 , n27 , n28 , n29 , n30 ,
n31 , n32 , n33 , n34 , n35 , n36 , n37 , n38 , n39 , n40 ,
n41 , n42 , n43 , n44 , n45 , n46 , n47 , n48 , n49 , n50 ,
n51 , n52 , n53 , n54 , n55 ;
output n56 , n57 , n58 , n59 , n60 , n61 , n62 , n63 , n64 , n65 , n66 ,
n67 , n68 , n69 , n70 , n71 , n72 , n73 , n74 , n75 , n76 ,
n77 , n78 , n79 , n80 , n81 , n82 , n83 , n84 , n85 , n86 ,
n87 , n88 , n89 , n90 , n91 , n92 , n93 , n94 , n95 , n96 ,
n97 , n98 , n99 , n100 , n101 , n102 , n103 , n104 , n105 , n106 ,
n107 , n108 , n109 , n110 , n111 , n112 , n113 , n114 , n115 , n116 ,
n117 , n118 , n119 , n120 , n121 , n122 , n123 , n124 , n125 , n126 ,
n127 , n128 , n129 , n130 , n131 , n132 , n133 , n134 , n135 , n136 ,
n137 , n138 , n139 , n140 , n141 , n142 , n143 , n144 , n145 , n146 ,
n147 , n148 , n149 , n150 , n151 , n152 , n153 , n154 , n155 , n156 ,
n157 , n158 , n159 , n160 , n161 , n162 , n163 , n164 , n165 , n166 ,
n167 , n168 , n169 , n170 , n171 , n172 , n173 , n174 , n175 , n176 ,
n177 , n178 , n179 , n180 , n181 , n182 , n183 , n184 ;
wire n370 , n371 , n372 , n373 , n374 , n375 , n376 , n377 , n378 , n379 , n380 ,
n381 , n382 , n383 , n384 , n385 , n386 , n387 , n388 , n389 , n390 ,
n391 , n392 , n393 , n394 , n395 , n396 , n397 , n398 , n399 , n400 ,
n401 , n402 , n403 , n404 , n405 , n406 , n407 , n408 , n409 , n410 ,
n411 , n412 , n413 , n414 , n415 , n416 , n417 , n418 , n419 , n420 ,
n421 , n422 , n423 , n424 , n425 , n426 , n427 , n428 , n429 , n430 ,
n431 , n432 , n433 , n434 , n435 , n436 , n437 , n438 , n439 , n440 ,
n441 , n442 , n443 , n444 , n445 , n446 , n447 , n448 , n449 , n450 ,
n451 , n452 , n453 , n454 , n455 , n456 , n457 , n458 , n459 , n460 ,
n461 , n462 , n463 , n464 , n465 , n466 , n467 , n468 , n469 , n470 ,
n471 , n472 , n473 , n474 , n475 , n476 , n477 , n478 , n479 , n480 ,
n481 , n482 , n483 , n484 , n485 , n486 , n487 , n488 , n489 , n490 ,
n491 , n492 , n493 , n494 , n495 , n496 , n497 , n498 , n499 , n500 ,
n501 , n502 , n503 , n504 , n505 , n506 , n507 , n508 , n509 , n510 ,
n511 , n512 , n513 , n514 , n515 , n516 , n517 , n518 , n519 , n520 ,
n521 , n522 , n523 , n524 , n525 , n526 , n527 , n528 , n529 , n530 ,
n531 , n532 , n533 , n534 , n535 , n536 , n537 , n538 , n539 , n540 ,
n541 , n542 , n543 , n544 , n545 , n546 , n547 , n548 , n549 , n550 ,
n551 , n552 , n553 , n554 , n555 , n556 , n557 , n558 , n559 , n560 ,
n561 , n562 , n563 , n564 , n565 , n566 , n567 , n568 , n569 , n570 ,
n571 , n572 , n573 , n574 , n575 , n576 , n577 , n578 , n579 , n580 ,
n581 , n582 , n583 , n584 , n585 , n586 , n587 , n588 , n589 , n590 ,
n591 , n592 , n593 , n594 , n595 , n596 , n597 , n598 , n599 , n600 ,
n601 , n602 , n603 , n604 , n605 , n606 , n607 , n608 , n609 , n610 ,
n611 , n612 , n613 , n614 , n615 , n616 , n617 , n618 , n619 , n620 ,
n621 , n622 , n623 , n624 , n625 , n626 , n627 , n628 , n629 , n630 ,
n631 , n632 , n633 , n634 , n635 , n636 , n637 , n638 , n639 , n640 ,
n641 , n642 , n643 , n644 , n645 , n646 , n647 , n648 , n649 , n650 ,
n651 , n652 , n653 , n654 , n655 , n656 , n657 , n658 , n659 , n660 ,
n661 , n662 , n663 , n664 , n665 , n666 , n667 , n668 , n669 , n670 ,
n671 , n672 , n673 , n674 , n675 , n676 , n677 , n678 , n679 , n680 ,
n681 , n682 , n683 , n684 , n685 , n686 , n687 , n688 , n689 , n690 ,
n691 , n692 , n693 , n694 , n695 , n696 , n697 , n698 , n699 , n700 ,
n701 , n702 , n703 , n704 , n705 , n706 , n707 , n708 , n709 , n710 ,
n711 , n712 , n713 , n714 , n715 , n716 , n717 , n718 , n719 , n720 ,
n721 , n722 , n723 , n724 , n725 , n726 , n727 , n728 , n729 , n730 ,
n731 , n732 , n733 , n734 , n735 , n736 , n737 , n738 , n739 , n740 ,
n741 , n742 , n743 , n744 , n745 , n746 , n747 , n748 , n749 , n750 ,
n751 , n752 , n753 , n754 , n755 , n756 , n757 , n758 , n759 , n760 ,
n761 , n762 , n763 , n764 , n765 , n766 , n767 , n768 , n769 , n770 ,
n771 , n772 , n773 , n774 , n775 , n776 , n777 , n778 , n779 , n780 ,
n781 , n782 , n783 , n784 , n785 , n786 , n787 , n788 , n789 , n790 ,
n791 , n792 , n793 , n794 , n795 , n796 , n797 , n798 , n799 , n800 ,
n801 , n802 , n803 , n804 , n805 , n806 , n807 , n808 , n809 , n810 ,
n811 , n812 , n813 , n814 , n815 , n816 , n817 , n818 , n819 , n820 ,
n821 , n822 , n823 , n824 , n825 , n826 , n827 , n828 , n829 , n830 ,
n831 , n832 , n833 , n834 , n835 , n836 , n837 , n838 , n839 , n840 ,
n841 , n842 , n843 , n844 , n845 , n846 , n847 , n848 , n849 , n850 ,
n851 , n852 , n853 , n854 , n855 , n856 , n857 , n858 , n859 , n860 ,
n861 , n862 , n863 , n864 , n865 , n866 , n867 , n868 , n869 , n870 ,
n871 , n872 , n873 , n874 , n875 , n876 , n877 , n878 , n879 , n880 ,
n881 , n882 , n883 , n884 , n885 , n886 , n887 , n888 , n889 , n890 ,
n891 , n892 , n893 , n894 , n895 , n896 , n897 , n898 , n899 , n900 ,
n901 , n902 , n903 , n904 , n905 , n906 , n907 , n908 , n909 , n910 ,
n911 , n912 , n913 , n914 , n915 , n916 , n917 , n918 , n919 , n920 ,
n921 , n922 , n923 , n924 , n925 , n926 , n927 , n928 , n929 , n930 ,
n931 , n932 , n933 , n934 , n935 , n936 , n937 , n938 , n939 , n940 ,
n941 , n942 , n943 , n944 , n945 , n946 , n947 , n948 , n949 , n950 ,
n951 , n952 , n953 , n954 , n955 , n956 , n957 , n958 , n959 , n960 ,
n961 , n962 , n963 , n964 , n965 , n966 , n967 , n968 , n969 , n970 ,
n971 , n972 , n973 , n974 , n975 , n976 , n977 , n978 , n979 , n980 ,
n981 , n982 , n983 , n984 , n985 , n986 , n987 , n988 , n989 , n990 ,
n991 , n992 , n993 , n994 , n995 , n996 , n997 , n998 , n999 , n1000 ,
n1001 , n1002 , n1003 , n1004 , n1005 , n1006 , n1007 , n1008 , n1009 , n1010 ,
n1011 , n1012 , n1013 , n1014 , n1015 , n1016 , n1017 , n1018 , n1019 , n1020 ,
n1021 , n1022 , n1023 , n1024 , n1025 , n1026 , n1027 , n1028 , n1029 , n1030 ,
n1031 , n1032 , n1033 , n1034 , n1035 , n1036 , n1037 , n1038 , n1039 , n1040 ,
n1041 , n1042 , n1043 , n1044 , n1045 , n1046 , n1047 , n1048 , n1049 , n1050 ,
n1051 , n1052 , n1053 , n1054 , n1055 , n1056 , n1057 , n1058 , n1059 , n1060 ,
n1061 , n1062 , n1063 , n1064 , n1065 , n1066 , n1067 , n1068 , n1069 , n1070 ,
n1071 , n1072 , n1073 , n1074 , n1075 , n1076 , n1077 , n1078 , n1079 , n1080 ,
n1081 , n1082 , n1083 , n1084 , n1085 , n1086 , n1087 , n1088 , n1089 , n1090 ,
n1091 , n1092 , n1093 , n1094 , n1095 , n1096 , n1097 , n1098 , n1099 , n1100 ,
n1101 , n1102 , n1103 , n1104 , n1105 , n1106 , n1107 , n1108 , n1109 , n1110 ,
n1111 , n1112 , n1113 , n1114 , n1115 , n1116 , n1117 , n1118 , n1119 , n1120 ,
n1121 , n1122 , n1123 , n1124 , n1125 , n1126 , n1127 , n1128 , n1129 , n1130 ,
n1131 , n1132 , n1133 , n1134 , n1135 , n1136 , n1137 , n1138 , n1139 , n1140 ,
n1141 , n1142 , n1143 , n1144 , n1145 , n1146 , n1147 , n1148 , n1149 , n1150 ,
n1151 , n1152 , n1153 , n1154 , n1155 , n1156 , n1157 , n1158 , n1159 , n1160 ,
n1161 , n1162 , n1163 , n1164 , n1165 , n1166 , n1167 , n1168 , n1169 , n1170 ,
n1171 , n1172 , n1173 , n1174 , n1175 , n1176 , n1177 , n1178 , n1179 , n1180 ,
n1181 , n1182 , n1183 , n1184 , n1185 , n1186 , n1187 , n1188 , n1189 , n1190 ,
n1191 , n1192 , n1193 , n1194 , n1195 , n1196 , n1197 , n1198 , n1199 , n1200 ,
n1201 , n1202 , n1203 , n1204 , n1205 , n1206 , n1207 , n1208 , n1209 , n1210 ,
n1211 , n1212 , n1213 , n1214 , n1215 , n1216 , n1217 , n1218 , n1219 , n1220 ,
n1221 , n1222 , n1223 , n1224 , n1225 , n1226 , n1227 , n1228 , n1229 , n1230 ,
n1231 , n1232 , n1233 , n1234 , n1235 , n1236 , n1237 , n1238 , n1239 , n1240 ,
n1241 , n1242 , n1243 , n1244 , n1245 , n1246 , n1247 , n1248 , n1249 , n1250 ,
n1251 , n1252 , n1253 , n1254 , n1255 , n1256 , n1257 , n1258 , n1259 , n1260 ,
n1261 , n1262 , n1263 , n1264 , n1265 , n1266 , n1267 , n1268 , n1269 , n1270 ,
n1271 , n1272 , n1273 , n1274 , n1275 , n1276 , n1277 , n1278 , n1279 , n1280 ,
n1281 , n1282 , n1283 , n1284 , n1285 , n1286 , n1287 , n1288 , n1289 , n1290 ,
n1291 , n1292 , n1293 , n1294 , n1295 , n1296 , n1297 , n1298 , n1299 , n1300 ,
n1301 , n1302 , n1303 , n1304 , n1305 , n1306 , n1307 , n1308 , n1309 , n1310 ,
n1311 , n1312 , n1313 , n1314 , n1315 , n1316 , n1317 , n1318 , n1319 , n1320 ,
n1321 , n1322 , n1323 , n1324 , n1325 , n1326 , n1327 , n1328 , n1329 , n1330 ,
n1331 , n1332 , n1333 , n1334 , n1335 , n1336 , n1337 , n1338 , n1339 , n1340 ,
n1341 , n1342 , n1343 , n1344 , n1345 , n1346 , n1347 , n1348 , n1349 , n1350 ,
n1351 , n1352 , n1353 , n1354 , n1355 , n1356 , n1357 , n1358 , n1359 , n1360 ,
n1361 , n1362 , n1363 , n1364 , n1365 , n1366 , n1367 , n1368 , n1369 , n1370 ,
n1371 , n1372 , n1373 , n1374 , n1375 , n1376 , n1377 , n1378 , n1379 , n1380 ,
n1381 , n1382 , n1383 , n1384 , n1385 , n1386 , n1387 , n1388 , n1389 , n1390 ,
n1391 , n1392 , n1393 , n1394 , n1395 , n1396 , n1397 , n1398 , n1399 , n1400 ,
n1401 , n1402 , n1403 , n1404 , n1405 , n1406 , n1407 , n1408 , n1409 , n1410 ,
n1411 , n1412 , n1413 , n1414 , n1415 , n1416 , n1417 , n1418 , n1419 , n1420 ,
n1421 , n1422 , n1423 , n1424 , n1425 , n1426 , n1427 , n1428 , n1429 , n1430 ,
n1431 , n1432 , n1433 , n1434 , n1435 , n1436 , n1437 , n1438 , n1439 , n1440 ,
n1441 , n1442 , n1443 , n1444 , n1445 , n1446 , n1447 , n1448 , n1449 , n1450 ,
n1451 , n1452 , n1453 , n1454 , n1455 , n1456 , n1457 , n1458 , n1459 , n1460 ,
n1461 , n1462 , n1463 , n1464 , n1465 , n1466 , n1467 , n1468 , n1469 , n1470 ,
n1471 , n1472 , n1473 , n1474 , n1475 , n1476 , n1477 , n1478 , n1479 , n1480 ,
n1481 , n1482 , n1483 , n1484 , n1485 , n1486 , n1487 , n1488 , n1489 , n1490 ,
n1491 , n1492 , n1493 , n1494 , n1495 , n1496 , n1497 , n1498 , n1499 , n1500 ,
n1501 , n1502 , n1503 , n1504 , n1505 , n1506 , n1507 , n1508 , n1509 , n1510 ,
n1511 , n1512 , n1513 , n1514 , n1515 , n1516 , n1517 , n1518 , n1519 , n1520 ,
n1521 , n1522 , n1523 , n1524 , n1525 , n1526 , n1527 , n1528 , n1529 , n1530 ,
n1531 , n1532 , n1533 , n1534 , n1535 , n1536 , n1537 , n1538 , n1539 , n1540 ,
n1541 , n1542 , n1543 , n1544 , n1545 , n1546 , n1547 , n1548 , n1549 , n1550 ,
n1551 , n1552 , n1553 , n1554 , n1555 , n1556 , n1557 , n1558 , n1559 , n1560 ,
n1561 , n1562 , n1563 , n1564 , n1565 , n1566 , n1567 , n1568 , n1569 , n1570 ,
n1571 , n1572 , n1573 , n1574 , n1575 , n1576 , n1577 , n1578 , n1579 , n1580 ,
n1581 , n1582 , n1583 , n1584 , n1585 , n1586 , n1587 , n1588 , n1589 , n1590 ,
n1591 , n1592 , n1593 , n1594 , n1595 , n1596 , n1597 , n1598 , n1599 , n1600 ,
n1601 , n1602 , n1603 , n1604 , n1605 , n1606 , n1607 , n1608 , n1609 , n1610 ,
n1611 , n1612 , n1613 , n1614 , n1615 , n1616 , n1617 , n1618 , n1619 , n1620 ,
n1621 , n1622 , n1623 , n1624 , n1625 , n1626 , n1627 , n1628 , n1629 , n1630 ,
n1631 , n1632 , n1633 , n1634 , n1635 , n1636 , n1637 , n1638 , n1639 , n1640 ,
n1641 , n1642 , n1643 , n1644 , n1645 , n1646 , n1647 , n1648 , n1649 , n1650 ,
n1651 , n1652 , n1653 , n1654 , n1655 , n1656 , n1657 , n1658 , n1659 , n1660 ,
n1661 , n1662 , n1663 , n1664 , n1665 , n1666 , n1667 , n1668 , n1669 , n1670 ,
n1671 , n1672 , n1673 , n1674 , n1675 , n1676 , n1677 , n1678 , n1679 , n1680 ,
n1681 , n1682 , n1683 , n1684 , n1685 , n1686 , n1687 , n1688 , n1689 , n1690 ,
n1691 , n1692 , n1693 , n1694 , n1695 , n1696 , n1697 , n1698 , n1699 , n1700 ,
n1701 , n1702 , n1703 , n1704 , n1705 , n1706 , n1707 , n1708 , n1709 , n1710 ,
n1711 , n1712 , n1713 , n1714 , n1715 , n1716 , n1717 , n1718 , n1719 , n1720 ,
n1721 , n1722 , n1723 , n1724 , n1725 , n1726 , n1727 , n1728 , n1729 , n1730 ,
n1731 , n1732 , n1733 , n1734 , n1735 , n1736 , n1737 , n1738 , n1739 , n1740 ,
n1741 , n1742 , n1743 , n1744 , n1745 , n1746 , n1747 , n1748 , n1749 , n1750 ,
n1751 , n1752 , n1753 , n1754 , n1755 , n1756 , n1757 , n1758 , n1759 , n1760 ,
n1761 , n1762 , n1763 , n1764 , n1765 , n1766 , n1767 , n1768 , n1769 , n1770 ,
n1771 , n1772 , n1773 , n1774 , n1775 , n1776 , n1777 , n1778 , n1779 , n1780 ,
n1781 , n1782 , n1783 , n1784 , n1785 , n1786 , n1787 , n1788 , n1789 , n1790 ,
n1791 , n1792 , n1793 , n1794 , n1795 , n1796 , n1797 , n1798 , n1799 , n1800 ,
n1801 , n1802 , n1803 , n1804 , n1805 , n1806 , n1807 , n1808 , n1809 , n1810 ,
n1811 , n1812 , n1813 , n1814 , n1815 , n1816 , n1817 , n1818 , n1819 , n1820 ,
n1821 , n1822 , n1823 , n1824 , n1825 , n1826 , n1827 , n1828 , n1829 , n1830 ,
n1831 , n1832 , n1833 , n1834 , n1835 , n1836 , n1837 , n1838 , n1839 , n1840 ,
n1841 , n1842 , n1843 , n1844 , n1845 , n1846 , n1847 , n1848 , n1849 , n1850 ,
n1851 , n1852 , n1853 , n1854 , n1855 , n1856 , n1857 , n1858 , n1859 , n1860 ,
n1861 , n1862 , n1863 , n1864 , n1865 , n1866 , n1867 , n1868 , n1869 , n1870 ,
n1871 , n1872 , n1873 , n1874 , n1875 , n1876 , n1877 , n1878 , n1879 , n1880 ,
n1881 , n1882 , n1883 , n1884 , n1885 , n1886 , n1887 , n1888 , n1889 , n1890 ,
n1891 , n1892 , n1893 , n1894 , n1895 , n1896 , n1897 , n1898 , n1899 , n1900 ,
n1901 , n1902 , n1903 , n1904 , n1905 , n1906 , n1907 , n1908 , n1909 , n1910 ,
n1911 , n1912 , n1913 , n1914 , n1915 , n1916 , n1917 , n1918 , n1919 , n1920 ,
n1921 , n1922 , n1923 , n1924 , n1925 , n1926 , n1927 , n1928 , n1929 , n1930 ,
n1931 , n1932 , n1933 , n1934 , n1935 , n1936 , n1937 , n1938 , n1939 , n1940 ,
n1941 , n1942 , n1943 , n1944 , n1945 , n1946 , n1947 , n1948 , n1949 , n1950 ,
n1951 , n1952 , n1953 , n1954 , n1955 , n1956 , n1957 , n1958 , n1959 , n1960 ,
n1961 , n1962 , n1963 , n1964 , n1965 , n1966 , n1967 , n1968 , n1969 , n1970 ,
n1971 , n1972 , n1973 , n1974 , n1975 , n1976 , n1977 , n1978 , n1979 , n1980 ,
n1981 , n1982 , n1983 , n1984 , n1985 , n1986 , n1987 , n1988 , n1989 , n1990 ,
n1991 , n1992 , n1993 , n1994 , n1995 , n1996 , n1997 , n1998 , n1999 , n2000 ,
n2001 , n2002 , n2003 , n2004 , n2005 , n2006 , n2007 , n2008 , n2009 , n2010 ,
n2011 , n2012 , n2013 , n2014 , n2015 , n2016 , n2017 , n2018 , n2019 , n2020 ,
n2021 , n2022 , n2023 , n2024 , n2025 , n2026 , n2027 , n2028 , n2029 , n2030 ,
n2031 , n2032 , n2033 , n2034 , n2035 , n2036 , n2037 , n2038 , n2039 , n2040 ,
n2041 , n2042 , n2043 , n2044 , n2045 , n2046 , n2047 , n2048 , n2049 , n2050 ,
n2051 , n2052 , n2053 , n2054 , n2055 , n2056 , n2057 , n2058 , n2059 , n2060 ,
n2061 , n2062 , n2063 , n2064 , n2065 , n2066 , n2067 , n2068 , n2069 , n2070 ,
n2071 , n2072 , n2073 , n2074 , n2075 , n2076 , n2077 , n2078 , n2079 , n2080 ,
n2081 , n2082 , n2083 , n2084 , n2085 , n2086 , n2087 , n2088 , n2089 , n2090 ,
n2091 , n2092 , n2093 , n2094 , n2095 , n2096 , n2097 , n2098 , n2099 , n2100 ,
n2101 , n2102 , n2103 , n2104 , n2105 , n2106 , n2107 , n2108 , n2109 , n2110 ,
n2111 , n2112 , n2113 , n2114 , n2115 , n2116 , n2117 , n2118 , n2119 , n2120 ,
n2121 , n2122 , n2123 , n2124 , n2125 , n2126 , n2127 , n2128 , n2129 , n2130 ,
n2131 , n2132 , n2133 , n2134 , n2135 , n2136 , n2137 , n2138 , n2139 , n2140 ,
n2141 , n2142 , n2143 , n2144 , n2145 , n2146 , n2147 , n2148 , n2149 , n2150 ,
n2151 , n2152 , n2153 , n2154 , n2155 , n2156 , n2157 , n2158 , n2159 , n2160 ,
n2161 , n2162 , n2163 , n2164 , n2165 , n2166 , n2167 , n2168 , n2169 , n2170 ,
n2171 , n2172 , n2173 , n2174 , n2175 , n2176 , n2177 , n2178 , n2179 , n2180 ,
n2181 , n2182 , n2183 , n2184 , n2185 , n2186 , n2187 , n2188 , n2189 , n2190 ,
n2191 , n2192 , n2193 , n2194 , n2195 , n2196 , n2197 , n2198 , n2199 , n2200 ,
n2201 , n2202 , n2203 , n2204 , n2205 , n2206 , n2207 , n2208 , n2209 , n2210 ,
n2211 , n2212 , n2213 , n2214 , n2215 , n2216 , n2217 , n2218 , n2219 , n2220 ,
n2221 , n2222 , n2223 , n2224 , n2225 , n2226 , n2227 , n2228 , n2229 , n2230 ,
n2231 , n2232 , n2233 , n2234 , n2235 , n2236 , n2237 , n2238 , n2239 , n2240 ,
n2241 , n2242 , n2243 , n2244 , n2245 , n2246 , n2247 , n2248 , n2249 , n2250 ,
n2251 , n2252 , n2253 , n2254 , n2255 , n2256 , n2257 , n2258 , n2259 , n2260 ,
n2261 , n2262 , n2263 , n2264 , n2265 , n2266 , n2267 , n2268 , n2269 , n2270 ,
n2271 , n2272 , n2273 , n2274 , n2275 , n2276 , n2277 , n2278 , n2279 , n2280 ,
n2281 , n2282 , n2283 , n2284 , n2285 , n2286 , n2287 , n2288 , n2289 , n2290 ,
n2291 , n2292 , n2293 , n2294 , n2295 , n2296 , n2297 , n2298 , n2299 , n2300 ,
n2301 , n2302 , n2303 , n2304 , n2305 , n2306 , n2307 , n2308 , n2309 , n2310 ,
n2311 , n2312 , n2313 , n2314 , n2315 , n2316 , n2317 , n2318 , n2319 , n2320 ,
n2321 , n2322 , n2323 , n2324 , n2325 , n2326 , n2327 , n2328 , n2329 , n2330 ,
n2331 , n2332 , n2333 , n2334 , n2335 , n2336 , n2337 , n2338 , n2339 , n2340 ,
n2341 , n2342 , n2343 , n2344 , n2345 , n2346 , n2347 , n2348 , n2349 , n2350 ,
n2351 , n2352 , n2353 , n2354 , n2355 , n2356 , n2357 , n2358 , n2359 , n2360 ,
n2361 , n2362 , n2363 , n2364 , n2365 , n2366 , n2367 , n2368 , n2369 , n2370 ,
n2371 , n2372 , n2373 , n2374 , n2375 , n2376 , n2377 , n2378 , n2379 , n2380 ,
n2381 , n2382 , n2383 , n2384 , n2385 , n2386 , n2387 , n2388 , n2389 , n2390 ,
n2391 , n2392 , n2393 , n2394 , n2395 , n2396 , n2397 , n2398 , n2399 , n2400 ,
n2401 , n2402 , n2403 , n2404 , n2405 , n2406 , n2407 , n2408 , n2409 , n2410 ,
n2411 , n2412 , n2413 , n2414 , n2415 , n2416 , n2417 , n2418 , n2419 , n2420 ,
n2421 , n2422 , n2423 , n2424 , n2425 , n2426 , n2427 , n2428 , n2429 , n2430 ,
n2431 , n2432 , n2433 , n2434 , n2435 , n2436 , n2437 , n2438 , n2439 , n2440 ,
n2441 , n2442 , n2443 , n2444 , n2445 , n2446 , n2447 , n2448 , n2449 , n2450 ,
n2451 , n2452 , n2453 , n2454 , n2455 , n2456 , n2457 , n2458 , n2459 , n2460 ,
n2461 , n2462 , n2463 , n2464 , n2465 , n2466 , n2467 , n2468 , n2469 , n2470 ,
n2471 , n2472 , n2473 , n2474 , n2475 , n2476 , n2477 , n2478 , n2479 , n2480 ,
n2481 , n2482 , n2483 , n2484 , n2485 , n2486 , n2487 , n2488 , n2489 , n2490 ,
n2491 , n2492 , n2493 , n2494 , n2495 , n2496 , n2497 , n2498 , n2499 , n2500 ,
n2501 , n2502 , n2503 , n2504 , n2505 , n2506 , n2507 , n2508 , n2509 , n2510 ,
n2511 , n2512 , n2513 , n2514 , n2515 , n2516 , n2517 , n2518 , n2519 , n2520 ,
n2521 , n2522 , n2523 , n2524 , n2525 , n2526 , n2527 , n2528 , n2529 , n2530 ,
n2531 , n2532 , n2533 , n2534 , n2535 , n2536 , n2537 , n2538 , n2539 , n2540 ,
n2541 , n2542 , n2543 , n2544 , n2545 , n2546 , n2547 , n2548 , n2549 , n2550 ,
n2551 , n2552 , n2553 , n2554 , n2555 , n2556 , n2557 , n2558 , n2559 , n2560 ,
n2561 , n2562 , n2563 , n2564 , n2565 , n2566 , n2567 , n2568 , n2569 , n2570 ,
n2571 , n2572 , n2573 , n2574 , n2575 , n2576 , n2577 , n2578 , n2579 , n2580 ,
n2581 , n2582 , n2583 , n2584 , n2585 , n2586 , n2587 , n2588 , n2589 , n2590 ,
n2591 , n2592 , n2593 , n2594 , n2595 , n2596 , n2597 , n2598 , n2599 , n2600 ,
n2601 , n2602 , n2603 , n2604 , n2605 , n2606 , n2607 , n2608 , n2609 , n2610 ,
n2611 , n2612 , n2613 , n2614 , n2615 , n2616 , n2617 , n2618 , n2619 , n2620 ,
n2621 , n2622 , n2623 , n2624 , n2625 , n2626 , n2627 , n2628 , n2629 , n2630 ,
n2631 , n2632 , n2633 , n2634 , n2635 , n2636 , n2637 , n2638 , n2639 , n2640 ,
n2641 , n2642 , n2643 , n2644 , n2645 , n2646 , n2647 , n2648 , n2649 , n2650 ,
n2651 , n2652 , n2653 , n2654 , n2655 , n2656 , n2657 , n2658 , n2659 , n2660 ,
n2661 , n2662 , n2663 , n2664 , n2665 , n2666 , n2667 , n2668 , n2669 , n2670 ,
n2671 , n2672 , n2673 , n2674 , n2675 , n2676 , n2677 , n2678 , n2679 , n2680 ,
n2681 , n2682 , n2683 , n2684 , n2685 , n2686 , n2687 , n2688 , n2689 , n2690 ,
n2691 , n2692 , n2693 , n2694 , n2695 , n2696 , n2697 , n2698 , n2699 , n2700 ,
n2701 , n2702 , n2703 , n2704 , n2705 , n2706 , n2707 , n2708 , n2709 , n2710 ,
n2711 , n2712 , n2713 , n2714 , n2715 , n2716 , n2717 , n2718 , n2719 , n2720 ,
n2721 , n2722 , n2723 , n2724 , n2725 , n2726 , n2727 , n2728 , n2729 , n2730 ,
n2731 , n2732 , n2733 , n2734 , n2735 , n2736 , n2737 , n2738 , n2739 , n2740 ,
n2741 , n2742 , n2743 , n2744 , n2745 , n2746 , n2747 , n2748 , n2749 , n2750 ,
n2751 , n2752 , n2753 , n2754 , n2755 , n2756 , n2757 , n2758 , n2759 , n2760 ,
n2761 , n2762 , n2763 , n2764 , n2765 , n2766 , n2767 , n2768 , n2769 , n2770 ,
n2771 , n2772 , n2773 , n2774 , n2775 , n2776 , n2777 , n2778 , n2779 , n2780 ,
n2781 , n2782 , n2783 , n2784 , n2785 , n2786 , n2787 , n2788 , n2789 , n2790 ,
n2791 , n2792 , n2793 , n2794 , n2795 , n2796 , n2797 , n2798 , n2799 , n2800 ,
n2801 , n2802 , n2803 , n2804 , n2805 , n2806 , n2807 , n2808 , n2809 , n2810 ,
n2811 , n2812 , n2813 , n2814 , n2815 , n2816 , n2817 , n2818 , n2819 , n2820 ,
n2821 , n2822 , n2823 , n2824 , n2825 , n2826 , n2827 , n2828 , n2829 , n2830 ,
n2831 , n2832 , n2833 , n2834 , n2835 , n2836 , n2837 , n2838 , n2839 , n2840 ,
n2841 , n2842 , n2843 , n2844 , n2845 , n2846 , n2847 , n2848 , n2849 , n2850 ,
n2851 , n2852 , n2853 , n2854 , n2855 , n2856 , n2857 , n2858 , n2859 , n2860 ,
n2861 , n2862 , n2863 , n2864 , n2865 , n2866 , n2867 , n2868 , n2869 , n2870 ,
n2871 , n2872 , n2873 , n2874 , n2875 , n2876 , n2877 , n2878 , n2879 , n2880 ,
n2881 , n2882 , n2883 , n2884 , n2885 , n2886 , n2887 , n2888 , n2889 , n2890 ,
n2891 , n2892 , n2893 , n2894 , n2895 , n2896 , n2897 , n2898 , n2899 , n2900 ,
n2901 , n2902 , n2903 , n2904 , n2905 , n2906 , n2907 , n2908 , n2909 , n2910 ,
n2911 , n2912 , n2913 , n2914 , n2915 , n2916 , n2917 , n2918 , n2919 , n2920 ,
n2921 , n2922 , n2923 , n2924 , n2925 , n2926 , n2927 , n2928 , n2929 , n2930 ,
n2931 , n2932 , n2933 , n2934 , n2935 , n2936 , n2937 , n2938 , n2939 , n2940 ,
n2941 , n2942 , n2943 , n2944 , n2945 , n2946 , n2947 , n2948 , n2949 , n2950 ,
n2951 , n2952 , n2953 , n2954 , n2955 , n2956 , n2957 , n2958 , n2959 , n2960 ,
n2961 , n2962 , n2963 , n2964 , n2965 , n2966 , n2967 , n2968 , n2969 , n2970 ,
n2971 , n2972 , n2973 , n2974 , n2975 , n2976 , n2977 , n2978 , n2979 , n2980 ,
n2981 , n2982 , n2983 , n2984 , n2985 , n2986 , n2987 , n2988 , n2989 , n2990 ,
n2991 , n2992 , n2993 , n2994 , n2995 , n2996 , n2997 , n2998 , n2999 , n3000 ,
n3001 , n3002 , n3003 , n3004 , n3005 , n3006 , n3007 , n3008 , n3009 , n3010 ,
n3011 , n3012 , n3013 , n3014 , n3015 , n3016 , n3017 , n3018 , n3019 , n3020 ,
n3021 , n3022 , n3023 , n3024 , n3025 , n3026 , n3027 , n3028 , n3029 , n3030 ,
n3031 , n3032 , n3033 , n3034 , n3035 , n3036 , n3037 , n3038 , n3039 , n3040 ,
n3041 , n3042 , n3043 , n3044 , n3045 , n3046 , n3047 , n3048 , n3049 , n3050 ,
n3051 , n3052 , n3053 , n3054 , n3055 , n3056 , n3057 , n3058 , n3059 , n3060 ,
n3061 , n3062 , n3063 , n3064 , n3065 , n3066 , n3067 , n3068 , n3069 , n3070 ,
n3071 , n3072 , n3073 , n3074 , n3075 , n3076 , n3077 , n3078 , n3079 , n3080 ,
n3081 , n3082 , n3083 , n3084 , n3085 , n3086 , n3087 , n3088 , n3089 , n3090 ,
n3091 , n3092 , n3093 , n3094 , n3095 , n3096 , n3097 , n3098 , n3099 , n3100 ,
n3101 , n3102 , n3103 , n3104 , n3105 , n3106 , n3107 , n3108 , n3109 , n3110 ,
n3111 , n3112 , n3113 , n3114 , n3115 , n3116 , n3117 , n3118 , n3119 , n3120 ,
n3121 , n3122 , n3123 , n3124 , n3125 , n3126 , n3127 , n3128 , n3129 , n3130 ,
n3131 , n3132 , n3133 , n3134 , n3135 , n3136 , n3137 , n3138 , n3139 , n3140 ,
n3141 , n3142 , n3143 , n3144 , n3145 , n3146 , n3147 , n3148 , n3149 , n3150 ,
n3151 , n3152 , n3153 , n3154 , n3155 , n3156 , n3157 , n3158 , n3159 , n3160 ,
n3161 , n3162 , n3163 , n3164 , n3165 , n3166 , n3167 , n3168 , n3169 , n3170 ,
n3171 , n3172 , n3173 , n3174 , n3175 , n3176 , n3177 , n3178 , n3179 , n3180 ,
n3181 , n3182 , n3183 , n3184 , n3185 , n3186 , n3187 , n3188 , n3189 , n3190 ,
n3191 , n3192 , n3193 , n3194 , n3195 , n3196 , n3197 , n3198 , n3199 , n3200 ,
n3201 , n3202 , n3203 , n3204 , n3205 , n3206 , n3207 , n3208 , n3209 , n3210 ,
n3211 , n3212 , n3213 , n3214 , n3215 , n3216 , n3217 , n3218 , n3219 , n3220 ,
n3221 , n3222 , n3223 , n3224 , n3225 , n3226 , n3227 , n3228 , n3229 , n3230 ,
n3231 , n3232 , n3233 , n3234 , n3235 , n3236 , n3237 , n3238 , n3239 , n3240 ,
n3241 , n3242 , n3243 , n3244 , n3245 , n3246 , n3247 , n3248 , n3249 , n3250 ,
n3251 , n3252 , n3253 , n3254 , n3255 , n3256 , n3257 , n3258 , n3259 , n3260 ,
n3261 , n3262 , n3263 , n3264 , n3265 , n3266 , n3267 , n3268 , n3269 , n3270 ,
n3271 , n3272 , n3273 , n3274 , n3275 , n3276 , n3277 , n3278 , n3279 , n3280 ,
n3281 , n3282 , n3283 , n3284 , n3285 , n3286 , n3287 , n3288 , n3289 , n3290 ,
n3291 , n3292 , n3293 , n3294 , n3295 , n3296 , n3297 , n3298 , n3299 , n3300 ,
n3301 , n3302 , n3303 , n3304 , n3305 , n3306 , n3307 , n3308 , n3309 , n3310 ,
n3311 , n3312 , n3313 , n3314 , n3315 , n3316 , n3317 , n3318 , n3319 , n3320 ,
n3321 , n3322 , n3323 , n3324 , n3325 , n3326 , n3327 , n3328 , n3329 , n3330 ,
n3331 , n3332 , n3333 , n3334 , n3335 , n3336 , n3337 , n3338 , n3339 , n3340 ,
n3341 , n3342 , n3343 , n3344 , n3345 , n3346 , n3347 , n3348 , n3349 , n3350 ,
n3351 , n3352 , n3353 , n3354 , n3355 , n3356 , n3357 , n3358 , n3359 , n3360 ,
n3361 , n3362 , n3363 , n3364 , n3365 , n3366 , n3367 , n3368 , n3369 , n3370 ,
n3371 , n3372 , n3373 , n3374 , n3375 , n3376 , n3377 , n3378 , n3379 , n3380 ,
n3381 , n3382 , n3383 , n3384 , n3385 , n3386 , n3387 , n3388 , n3389 , n3390 ,
n3391 , n3392 , n3393 , n3394 , n3395 , n3396 , n3397 , n3398 , n3399 , n3400 ,
n3401 , n3402 , n3403 , n3404 , n3405 , n3406 , n3407 , n3408 , n3409 , n3410 ,
n3411 , n3412 , n3413 , n3414 , n3415 , n3416 , n3417 , n3418 , n3419 , n3420 ,
n3421 , n3422 , n3423 , n3424 , n3425 , n3426 , n3427 , n3428 , n3429 , n3430 ,
n3431 , n3432 , n3433 , n3434 , n3435 , n3436 , n3437 , n3438 , n3439 , n3440 ,
n3441 , n3442 , n3443 , n3444 , n3445 , n3446 , n3447 , n3448 , n3449 , n3450 ,
n3451 , n3452 , n3453 , n3454 , n3455 , n3456 , n3457 , n3458 , n3459 , n3460 ,
n3461 , n3462 , n3463 , n3464 , n3465 , n3466 , n3467 , n3468 , n3469 , n3470 ,
n3471 , n3472 , n3473 , n3474 , n3475 , n3476 , n3477 , n3478 , n3479 , n3480 ,
n3481 , n3482 , n3483 , n3484 , n3485 , n3486 , n3487 , n3488 , n3489 , n3490 ,
n3491 , n3492 , n3493 , n3494 , n3495 , n3496 , n3497 , n3498 , n3499 , n3500 ,
n3501 , n3502 , n3503 , n3504 , n3505 , n3506 , n3507 , n3508 , n3509 , n3510 ,
n3511 , n3512 , n3513 , n3514 , n3515 , n3516 , n3517 , n3518 , n3519 , n3520 ,
n3521 , n3522 , n3523 , n3524 , n3525 , n3526 , n3527 , n3528 , n3529 , n3530 ,
n3531 , n3532 , n3533 , n3534 , n3535 , n3536 , n3537 , n3538 , n3539 , n3540 ,
n3541 , n3542 , n3543 , n3544 , n3545 , n3546 , n3547 , n3548 , n3549 , n3550 ,
n3551 , n3552 , n3553 , n3554 , n3555 , n3556 , n3557 , n3558 , n3559 , n3560 ,
n3561 , n3562 , n3563 , n3564 , n3565 , n3566 , n3567 , n3568 , n3569 , n3570 ,
n3571 , n3572 , n3573 , n3574 , n3575 , n3576 , n3577 , n3578 , n3579 , n3580 ,
n3581 , n3582 , n3583 , n3584 , n3585 , n3586 , n3587 , n3588 , n3589 , n3590 ,
n3591 , n3592 , n3593 , n3594 , n3595 , n3596 , n3597 , n3598 , n3599 , n3600 ,
n3601 , n3602 , n3603 , n3604 , n3605 , n3606 , n3607 , n3608 , n3609 , n3610 ,
n3611 , n3612 , n3613 , n3614 , n3615 , n3616 , n3617 , n3618 , n3619 , n3620 ,
n3621 , n3622 , n3623 , n3624 , n3625 , n3626 , n3627 , n3628 , n3629 , n3630 ,
n3631 , n3632 , n3633 , n3634 , n3635 , n3636 , n3637 , n3638 , n3639 , n3640 ,
n3641 , n3642 , n3643 , n3644 , n3645 , n3646 , n3647 , n3648 , n3649 , n3650 ,
n3651 , n3652 , n3653 , n3654 , n3655 , n3656 , n3657 , n3658 , n3659 , n3660 ,
n3661 , n3662 , n3663 , n3664 , n3665 , n3666 , n3667 , n3668 , n3669 , n3670 ,
n3671 , n3672 , n3673 , n3674 , n3675 , n3676 , n3677 , n3678 , n3679 , n3680 ,
n3681 , n3682 , n3683 , n3684 , n3685 , n3686 , n3687 , n3688 , n3689 , n3690 ,
n3691 , n3692 , n3693 , n3694 , n3695 , n3696 , n3697 , n3698 , n3699 , n3700 ,
n3701 , n3702 , n3703 , n3704 , n3705 , n3706 , n3707 , n3708 , n3709 , n3710 ,
n3711 , n3712 , n3713 , n3714 , n3715 , n3716 , n3717 , n3718 , n3719 , n3720 ,
n3721 , n3722 , n3723 , n3724 , n3725 , n3726 , n3727 , n3728 , n3729 , n3730 ,
n3731 , n3732 , n3733 , n3734 , n3735 , n3736 , n3737 , n3738 , n3739 , n3740 ,
n3741 , n3742 , n3743 , n3744 , n3745 , n3746 , n3747 , n3748 , n3749 , n3750 ,
n3751 , n3752 , n3753 , n3754 , n3755 , n3756 , n3757 , n3758 , n3759 , n3760 ,
n3761 , n3762 , n3763 , n3764 , n3765 , n3766 , n3767 , n3768 , n3769 , n3770 ,
n3771 , n3772 , n3773 , n3774 , n3775 , n3776 , n3777 , n3778 , n3779 , n3780 ,
n3781 , n3782 , n3783 , n3784 , n3785 , n3786 , n3787 , n3788 , n3789 , n3790 ,
n3791 , n3792 , n3793 , n3794 , n3795 , n3796 , n3797 , n3798 , n3799 , n3800 ,
n3801 , n3802 , n3803 , n3804 , n3805 , n3806 , n3807 , n3808 , n3809 , n3810 ,
n3811 , n3812 , n3813 , n3814 , n3815 , n3816 , n3817 , n3818 , n3819 , n3820 ,
n3821 , n3822 , n3823 , n3824 , n3825 , n3826 , n3827 , n3828 , n3829 , n3830 ,
n3831 , n3832 , n3833 , n3834 , n3835 , n3836 , n3837 , n3838 , n3839 , n3840 ,
n3841 , n3842 , n3843 , n3844 , n3845 , n3846 , n3847 , n3848 , n3849 , n3850 ,
n3851 , n3852 , n3853 , n3854 , n3855 , n3856 , n3857 , n3858 , n3859 , n3860 ,
n3861 , n3862 , n3863 , n3864 , n3865 , n3866 , n3867 , n3868 , n3869 , n3870 ,
n3871 , n3872 , n3873 , n3874 , n3875 , n3876 , n3877 , n3878 , n3879 , n3880 ,
n3881 , n3882 , n3883 , n3884 , n3885 , n3886 , n3887 , n3888 , n3889 , n3890 ,
n3891 , n3892 , n3893 , n3894 , n3895 , n3896 , n3897 , n3898 , n3899 , n3900 ,
n3901 , n3902 , n3903 , n3904 , n3905 , n3906 , n3907 , n3908 , n3909 , n3910 ,
n3911 , n3912 , n3913 , n3914 , n3915 , n3916 , n3917 , n3918 , n3919 , n3920 ,
n3921 , n3922 , n3923 , n3924 , n3925 , n3926 , n3927 , n3928 , n3929 , n3930 ,
n3931 , n3932 , n3933 , n3934 , n3935 , n3936 , n3937 , n3938 , n3939 , n3940 ,
n3941 , n3942 , n3943 , n3944 , n3945 , n3946 , n3947 , n3948 , n3949 , n3950 ,
n3951 , n3952 , n3953 , n3954 , n3955 , n3956 , n3957 , n3958 , n3959 , n3960 ,
n3961 , n3962 , n3963 , n3964 , n3965 , n3966 , n3967 , n3968 , n3969 , n3970 ,
n3971 , n3972 , n3973 , n3974 , n3975 , n3976 , n3977 , n3978 , n3979 , n3980 ,
n3981 , n3982 , n3983 , n3984 , n3985 , n3986 , n3987 , n3988 , n3989 , n3990 ,
n3991 , n3992 , n3993 , n3994 , n3995 , n3996 , n3997 , n3998 , n3999 , n4000 ,
n4001 , n4002 , n4003 , n4004 , n4005 , n4006 , n4007 , n4008 , n4009 , n4010 ,
n4011 , n4012 , n4013 , n4014 , n4015 , n4016 , n4017 , n4018 , n4019 , n4020 ,
n4021 , n4022 , n4023 , n4024 , n4025 , n4026 , n4027 , n4028 , n4029 , n4030 ,
n4031 , n4032 , n4033 , n4034 , n4035 , n4036 , n4037 , n4038 , n4039 , n4040 ,
n4041 , n4042 , n4043 , n4044 , n4045 , n4046 , n4047 , n4048 , n4049 , n4050 ,
n4051 , n4052 , n4053 , n4054 , n4055 , n4056 , n4057 , n4058 , n4059 , n4060 ,
n4061 , n4062 , n4063 , n4064 , n4065 , n4066 , n4067 , n4068 , n4069 , n4070 ,
n4071 , n4072 , n4073 , n4074 , n4075 , n4076 , n4077 , n4078 , n4079 , n4080 ,
n4081 , n4082 , n4083 , n4084 , n4085 , n4086 , n4087 , n4088 , n4089 , n4090 ,
n4091 , n4092 , n4093 , n4094 , n4095 , n4096 , n4097 , n4098 , n4099 , n4100 ,
n4101 , n4102 , n4103 , n4104 , n4105 , n4106 , n4107 , n4108 , n4109 , n4110 ,
n4111 , n4112 , n4113 , n4114 , n4115 , n4116 , n4117 , n4118 , n4119 , n4120 ,
n4121 , n4122 , n4123 , n4124 , n4125 , n4126 , n4127 , n4128 , n4129 , n4130 ,
n4131 , n4132 , n4133 , n4134 , n4135 , n4136 , n4137 , n4138 , n4139 , n4140 ,
n4141 , n4142 , n4143 , n4144 , n4145 , n4146 , n4147 , n4148 , n4149 , n4150 ,
n4151 , n4152 , n4153 , n4154 , n4155 , n4156 , n4157 , n4158 , n4159 , n4160 ,
n4161 , n4162 , n4163 , n4164 , n4165 , n4166 , n4167 , n4168 , n4169 , n4170 ,
n4171 , n4172 , n4173 , n4174 , n4175 , n4176 , n4177 , n4178 , n4179 , n4180 ,
n4181 , n4182 , n4183 , n4184 , n4185 , n4186 , n4187 , n4188 , n4189 , n4190 ,
n4191 , n4192 , n4193 , n4194 , n4195 , n4196 , n4197 , n4198 , n4199 , n4200 ,
n4201 , n4202 , n4203 , n4204 , n4205 , n4206 , n4207 , n4208 , n4209 , n4210 ,
n4211 , n4212 , n4213 , n4214 , n4215 , n4216 , n4217 , n4218 , n4219 , n4220 ,
n4221 , n4222 , n4223 , n4224 , n4225 , n4226 , n4227 , n4228 , n4229 , n4230 ,
n4231 , n4232 , n4233 , n4234 , n4235 , n4236 , n4237 , n4238 , n4239 , n4240 ,
n4241 , n4242 , n4243 , n4244 , n4245 , n4246 , n4247 , n4248 , n4249 , n4250 ,
n4251 , n4252 , n4253 , n4254 , n4255 , n4256 , n4257 , n4258 , n4259 , n4260 ,
n4261 , n4262 , n4263 , n4264 , n4265 , n4266 , n4267 , n4268 , n4269 , n4270 ,
n4271 , n4272 , n4273 , n4274 , n4275 , n4276 , n4277 , n4278 , n4279 , n4280 ,
n4281 , n4282 , n4283 , n4284 , n4285 , n4286 , n4287 , n4288 , n4289 , n4290 ,
n4291 , n4292 , n4293 , n4294 , n4295 , n4296 , n4297 , n4298 , n4299 , n4300 ,
n4301 , n4302 , n4303 , n4304 , n4305 , n4306 , n4307 , n4308 , n4309 , n4310 ,
n4311 , n4312 , n4313 , n4314 , n4315 , n4316 , n4317 , n4318 , n4319 , n4320 ,
n4321 , n4322 , n4323 , n4324 , n4325 , n4326 , n4327 , n4328 , n4329 , n4330 ,
n4331 , n4332 , n4333 , n4334 , n4335 , n4336 , n4337 , n4338 , n4339 , n4340 ,
n4341 , n4342 , n4343 , n4344 , n4345 , n4346 , n4347 , n4348 , n4349 , n4350 ,
n4351 , n4352 , n4353 , n4354 , n4355 , n4356 , n4357 , n4358 , n4359 , n4360 ,
n4361 , n4362 , n4363 , n4364 , n4365 , n4366 , n4367 , n4368 , n4369 , n4370 ,
n4371 , n4372 , n4373 , n4374 , n4375 , n4376 , n4377 , n4378 , n4379 , n4380 ,
n4381 , n4382 , n4383 , n4384 , n4385 , n4386 , n4387 , n4388 , n4389 , n4390 ,
n4391 , n4392 , n4393 , n4394 , n4395 , n4396 , n4397 , n4398 , n4399 , n4400 ,
n4401 , n4402 , n4403 , n4404 , n4405 , n4406 , n4407 , n4408 , n4409 , n4410 ,
n4411 , n4412 , n4413 , n4414 , n4415 , n4416 , n4417 , n4418 , n4419 , n4420 ,
n4421 , n4422 , n4423 , n4424 , n4425 , n4426 , n4427 , n4428 , n4429 , n4430 ,
n4431 , n4432 , n4433 , n4434 , n4435 , n4436 , n4437 , n4438 , n4439 , n4440 ,
n4441 , n4442 , n4443 , n4444 , n4445 , n4446 , n4447 , n4448 , n4449 , n4450 ,
n4451 , n4452 , n4453 , n4454 , n4455 , n4456 , n4457 , n4458 , n4459 , n4460 ,
n4461 , n4462 , n4463 , n4464 , n4465 , n4466 , n4467 , n4468 , n4469 , n4470 ,
n4471 , n4472 , n4473 , n4474 , n4475 , n4476 , n4477 , n4478 , n4479 , n4480 ,
n4481 , n4482 , n4483 , n4484 , n4485 , n4486 , n4487 , n4488 , n4489 , n4490 ,
n4491 , n4492 , n4493 , n4494 , n4495 , n4496 , n4497 , n4498 , n4499 , n4500 ,
n4501 , n4502 , n4503 , n4504 , n4505 , n4506 , n4507 , n4508 , n4509 , n4510 ,
n4511 , n4512 , n4513 , n4514 , n4515 , n4516 , n4517 , n4518 , n4519 , n4520 ,
n4521 , n4522 , n4523 , n4524 , n4525 , n4526 , n4527 , n4528 , n4529 , n4530 ,
n4531 , n4532 , n4533 , n4534 , n4535 , n4536 , n4537 , n4538 , n4539 , n4540 ,
n4541 , n4542 , n4543 , n4544 , n4545 , n4546 , n4547 , n4548 , n4549 , n4550 ,
n4551 , n4552 , n4553 , n4554 , n4555 , n4556 , n4557 , n4558 , n4559 , n4560 ,
n4561 , n4562 , n4563 , n4564 , n4565 , n4566 , n4567 , n4568 , n4569 , n4570 ,
n4571 , n4572 , n4573 , n4574 , n4575 , n4576 , n4577 , n4578 , n4579 , n4580 ,
n4581 , n4582 , n4583 , n4584 , n4585 , n4586 , n4587 , n4588 , n4589 , n4590 ,
n4591 , n4592 , n4593 , n4594 , n4595 , n4596 , n4597 , n4598 , n4599 , n4600 ,
n4601 , n4602 , n4603 , n4604 , n4605 , n4606 , n4607 , n4608 , n4609 , n4610 ,
n4611 , n4612 , n4613 , n4614 , n4615 , n4616 , n4617 , n4618 , n4619 , n4620 ,
n4621 , n4622 , n4623 , n4624 , n4625 , n4626 , n4627 , n4628 , n4629 , n4630 ,
n4631 , n4632 , n4633 , n4634 , n4635 , n4636 , n4637 , n4638 , n4639 , n4640 ,
n4641 , n4642 , n4643 , n4644 , n4645 , n4646 , n4647 , n4648 , n4649 , n4650 ,
n4651 , n4652 , n4653 , n4654 , n4655 , n4656 , n4657 , n4658 , n4659 , n4660 ,
n4661 , n4662 , n4663 , n4664 , n4665 , n4666 , n4667 , n4668 , n4669 , n4670 ,
n4671 , n4672 , n4673 , n4674 , n4675 , n4676 , n4677 , n4678 , n4679 , n4680 ,
n4681 , n4682 , n4683 , n4684 , n4685 , n4686 , n4687 , n4688 , n4689 , n4690 ,
n4691 , n4692 , n4693 , n4694 , n4695 , n4696 , n4697 , n4698 , n4699 , n4700 ,
n4701 , n4702 , n4703 , n4704 , n4705 , n4706 , n4707 , n4708 , n4709 , n4710 ,
n4711 , n4712 , n4713 , n4714 , n4715 , n4716 , n4717 , n4718 , n4719 , n4720 ,
n4721 , n4722 , n4723 , n4724 , n4725 , n4726 , n4727 , n4728 , n4729 , n4730 ,
n4731 , n4732 , n4733 , n4734 , n4735 , n4736 , n4737 , n4738 , n4739 , n4740 ,
n4741 , n4742 , n4743 , n4744 , n4745 , n4746 , n4747 , n4748 , n4749 , n4750 ,
n4751 , n4752 , n4753 , n4754 , n4755 , n4756 , n4757 , n4758 , n4759 , n4760 ,
n4761 , n4762 , n4763 , n4764 , n4765 , n4766 , n4767 , n4768 , n4769 , n4770 ,
n4771 , n4772 , n4773 , n4774 , n4775 , n4776 , n4777 , n4778 , n4779 , n4780 ,
n4781 , n4782 , n4783 , n4784 , n4785 , n4786 , n4787 , n4788 , n4789 , n4790 ,
n4791 , n4792 , n4793 , n4794 , n4795 , n4796 , n4797 , n4798 , n4799 , n4800 ,
n4801 , n4802 , n4803 , n4804 , n4805 , n4806 , n4807 , n4808 , n4809 , n4810 ,
n4811 , n4812 , n4813 , n4814 , n4815 , n4816 , n4817 , n4818 , n4819 , n4820 ,
n4821 , n4822 , n4823 , n4824 , n4825 , n4826 , n4827 , n4828 , n4829 , n4830 ,
n4831 , n4832 , n4833 , n4834 , n4835 , n4836 , n4837 , n4838 , n4839 , n4840 ,
n4841 , n4842 , n4843 , n4844 , n4845 , n4846 , n4847 , n4848 , n4849 , n4850 ,
n4851 , n4852 , n4853 , n4854 , n4855 , n4856 , n4857 , n4858 , n4859 , n4860 ,
n4861 , n4862 , n4863 , n4864 , n4865 , n4866 , n4867 , n4868 , n4869 , n4870 ,
n4871 , n4872 , n4873 , n4874 , n4875 , n4876 , n4877 , n4878 , n4879 , n4880 ,
n4881 , n4882 , n4883 , n4884 , n4885 , n4886 , n4887 , n4888 , n4889 , n4890 ,
n4891 , n4892 , n4893 , n4894 , n4895 , n4896 , n4897 , n4898 , n4899 , n4900 ,
n4901 , n4902 , n4903 , n4904 , n4905 , n4906 , n4907 , n4908 , n4909 , n4910 ,
n4911 , n4912 , n4913 , n4914 , n4915 , n4916 , n4917 , n4918 , n4919 , n4920 ,
n4921 , n4922 , n4923 , n4924 , n4925 , n4926 , n4927 , n4928 , n4929 , n4930 ,
n4931 , n4932 , n4933 , n4934 , n4935 , n4936 , n4937 , n4938 , n4939 , n4940 ,
n4941 , n4942 , n4943 , n4944 , n4945 , n4946 , n4947 , n4948 , n4949 , n4950 ,
n4951 , n4952 , n4953 , n4954 , n4955 , n4956 , n4957 , n4958 , n4959 , n4960 ,
n4961 , n4962 , n4963 , n4964 , n4965 , n4966 , n4967 , n4968 , n4969 , n4970 ,
n4971 , n4972 , n4973 , n4974 , n4975 , n4976 , n4977 , n4978 , n4979 , n4980 ,
n4981 , n4982 , n4983 , n4984 , n4985 , n4986 , n4987 , n4988 , n4989 , n4990 ,
n4991 , n4992 , n4993 , n4994 , n4995 , n4996 , n4997 , n4998 , n4999 , n5000 ,
n5001 , n5002 , n5003 , n5004 , n5005 , n5006 , n5007 , n5008 , n5009 , n5010 ,
n5011 , n5012 , n5013 , n5014 , n5015 , n5016 , n5017 , n5018 , n5019 , n5020 ,
n5021 , n5022 , n5023 , n5024 , n5025 , n5026 , n5027 , n5028 , n5029 , n5030 ,
n5031 , n5032 , n5033 , n5034 , n5035 , n5036 , n5037 , n5038 , n5039 , n5040 ,
n5041 , n5042 , n5043 , n5044 , n5045 , n5046 , n5047 , n5048 , n5049 , n5050 ,
n5051 , n5052 , n5053 , n5054 , n5055 , n5056 , n5057 , n5058 , n5059 , n5060 ,
n5061 , n5062 , n5063 , n5064 , n5065 , n5066 , n5067 , n5068 , n5069 , n5070 ,
n5071 , n5072 , n5073 , n5074 , n5075 , n5076 , n5077 , n5078 , n5079 , n5080 ,
n5081 , n5082 , n5083 , n5084 , n5085 , n5086 , n5087 , n5088 , n5089 , n5090 ,
n5091 , n5092 , n5093 , n5094 , n5095 , n5096 , n5097 , n5098 , n5099 , n5100 ,
n5101 , n5102 , n5103 , n5104 , n5105 , n5106 , n5107 , n5108 , n5109 , n5110 ,
n5111 , n5112 , n5113 , n5114 , n5115 , n5116 , n5117 , n5118 , n5119 , n5120 ,
n5121 , n5122 , n5123 , n5124 , n5125 , n5126 , n5127 , n5128 , n5129 , n5130 ,
n5131 , n5132 , n5133 , n5134 , n5135 , n5136 , n5137 , n5138 , n5139 , n5140 ,
n5141 , n5142 , n5143 , n5144 , n5145 , n5146 , n5147 , n5148 , n5149 , n5150 ,
n5151 , n5152 , n5153 , n5154 , n5155 , n5156 , n5157 , n5158 , n5159 , n5160 ,
n5161 , n5162 , n5163 , n5164 , n5165 , n5166 , n5167 , n5168 , n5169 , n5170 ,
n5171 , n5172 , n5173 , n5174 , n5175 , n5176 , n5177 , n5178 , n5179 , n5180 ,
n5181 , n5182 , n5183 , n5184 , n5185 , n5186 , n5187 , n5188 , n5189 , n5190 ,
n5191 , n5192 , n5193 , n5194 , n5195 , n5196 , n5197 , n5198 , n5199 , n5200 ,
n5201 , n5202 , n5203 , n5204 , n5205 , n5206 , n5207 , n5208 , n5209 , n5210 ,
n5211 , n5212 , n5213 , n5214 , n5215 , n5216 , n5217 , n5218 , n5219 , n5220 ,
n5221 , n5222 , n5223 , n5224 , n5225 , n5226 , n5227 , n5228 , n5229 , n5230 ,
n5231 , n5232 , n5233 , n5234 , n5235 , n5236 , n5237 , n5238 , n5239 , n5240 ,
n5241 , n5242 , n5243 , n5244 , n5245 , n5246 , n5247 , n5248 , n5249 , n5250 ,
n5251 , n5252 , n5253 , n5254 , n5255 , n5256 , n5257 , n5258 , n5259 , n5260 ,
n5261 , n5262 , n5263 , n5264 , n5265 , n5266 , n5267 , n5268 , n5269 , n5270 ,
n5271 , n5272 , n5273 , n5274 , n5275 , n5276 , n5277 , n5278 , n5279 , n5280 ,
n5281 , n5282 , n5283 , n5284 , n5285 , n5286 , n5287 , n5288 , n5289 , n5290 ,
n5291 , n5292 , n5293 , n5294 , n5295 , n5296 , n5297 , n5298 , n5299 , n5300 ,
n5301 , n5302 , n5303 , n5304 , n5305 , n5306 , n5307 , n5308 , n5309 , n5310 ,
n5311 , n5312 , n5313 , n5314 , n5315 , n5316 , n5317 , n5318 , n5319 , n5320 ,
n5321 , n5322 , n5323 , n5324 , n5325 , n5326 , n5327 , n5328 , n5329 , n5330 ,
n5331 , n5332 , n5333 , n5334 , n5335 , n5336 , n5337 , n5338 , n5339 , n5340 ,
n5341 , n5342 , n5343 , n5344 , n5345 , n5346 , n5347 , n5348 , n5349 , n5350 ,
n5351 , n5352 , n5353 , n5354 , n5355 , n5356 , n5357 , n5358 , n5359 , n5360 ,
n5361 , n5362 , n5363 , n5364 , n5365 , n5366 , n5367 , n5368 , n5369 , n5370 ,
n5371 , n5372 , n5373 , n5374 , n5375 , n5376 , n5377 , n5378 , n5379 , n5380 ,
n5381 , n5382 , n5383 , n5384 , n5385 , n5386 , n5387 , n5388 , n5389 , n5390 ,
n5391 , n5392 , n5393 , n5394 , n5395 , n5396 , n5397 , n5398 , n5399 , n5400 ,
n5401 , n5402 , n5403 , n5404 , n5405 , n5406 , n5407 , n5408 , n5409 , n5410 ,
n5411 , n5412 , n5413 , n5414 , n5415 , n5416 , n5417 , n5418 , n5419 , n5420 ,
n5421 , n5422 , n5423 , n5424 , n5425 , n5426 , n5427 , n5428 , n5429 , n5430 ,
n5431 , n5432 , n5433 , n5434 , n5435 , n5436 , n5437 , n5438 , n5439 , n5440 ,
n5441 , n5442 , n5443 , n5444 , n5445 , n5446 , n5447 , n5448 , n5449 , n5450 ,
n5451 , n5452 , n5453 , n5454 , n5455 , n5456 , n5457 , n5458 , n5459 , n5460 ,
n5461 , n5462 , n5463 , n5464 , n5465 , n5466 , n5467 , n5468 , n5469 , n5470 ,
n5471 , n5472 , n5473 , n5474 , n5475 , n5476 , n5477 , n5478 , n5479 , n5480 ,
n5481 , n5482 , n5483 , n5484 , n5485 , n5486 , n5487 , n5488 , n5489 , n5490 ,
n5491 , n5492 , n5493 , n5494 , n5495 , n5496 , n5497 , n5498 , n5499 , n5500 ,
n5501 , n5502 , n5503 , n5504 , n5505 , n5506 , n5507 , n5508 , n5509 , n5510 ,
n5511 , n5512 , n5513 , n5514 , n5515 , n5516 , n5517 , n5518 , n5519 , n5520 ,
n5521 , n5522 , n5523 , n5524 , n5525 , n5526 , n5527 , n5528 , n5529 , n5530 ,
n5531 , n5532 , n5533 , n5534 , n5535 , n5536 , n5537 , n5538 , n5539 , n5540 ,
n5541 , n5542 , n5543 , n5544 , n5545 , n5546 , n5547 , n5548 , n5549 , n5550 ,
n5551 , n5552 , n5553 , n5554 , n5555 , n5556 , n5557 , n5558 , n5559 , n5560 ,
n5561 , n5562 , n5563 , n5564 , n5565 , n5566 , n5567 , n5568 , n5569 , n5570 ,
n5571 , n5572 , n5573 , n5574 , n5575 , n5576 , n5577 , n5578 , n5579 , n5580 ,
n5581 , n5582 , n5583 , n5584 , n5585 , n5586 , n5587 , n5588 , n5589 , n5590 ,
n5591 , n5592 , n5593 , n5594 , n5595 , n5596 , n5597 , n5598 , n5599 , n5600 ,
n5601 , n5602 , n5603 , n5604 , n5605 , n5606 , n5607 , n5608 , n5609 , n5610 ,
n5611 , n5612 , n5613 , n5614 , n5615 , n5616 , n5617 , n5618 , n5619 , n5620 ,
n5621 , n5622 , n5623 , n5624 , n5625 , n5626 , n5627 , n5628 , n5629 , n5630 ,
n5631 , n5632 , n5633 , n5634 , n5635 , n5636 , n5637 , n5638 , n5639 , n5640 ,
n5641 , n5642 , n5643 , n5644 , n5645 , n5646 , n5647 , n5648 , n5649 , n5650 ,
n5651 , n5652 , n5653 , n5654 , n5655 , n5656 , n5657 , n5658 , n5659 , n5660 ,
n5661 , n5662 , n5663 , n5664 , n5665 , n5666 , n5667 , n5668 , n5669 , n5670 ,
n5671 , n5672 , n5673 , n5674 , n5675 , n5676 , n5677 , n5678 , n5679 , n5680 ,
n5681 , n5682 , n5683 , n5684 , n5685 , n5686 , n5687 , n5688 , n5689 , n5690 ,
n5691 , n5692 , n5693 , n5694 , n5695 , n5696 , n5697 , n5698 , n5699 , n5700 ,
n5701 , n5702 , n5703 , n5704 , n5705 , n5706 , n5707 , n5708 , n5709 , n5710 ,
n5711 , n5712 , n5713 , n5714 , n5715 , n5716 , n5717 , n5718 , n5719 , n5720 ,
n5721 , n5722 , n5723 , n5724 , n5725 , n5726 , n5727 , n5728 , n5729 , n5730 ,
n5731 , n5732 , n5733 , n5734 , n5735 , n5736 , n5737 , n5738 , n5739 , n5740 ,
n5741 , n5742 , n5743 , n5744 , n5745 , n5746 , n5747 , n5748 , n5749 , n5750 ,
n5751 , n5752 , n5753 , n5754 , n5755 , n5756 , n5757 , n5758 , n5759 , n5760 ,
n5761 , n5762 , n5763 , n5764 , n5765 , n5766 , n5767 , n5768 , n5769 , n5770 ,
n5771 , n5772 , n5773 , n5774 , n5775 , n5776 , n5777 , n5778 , n5779 , n5780 ,
n5781 , n5782 , n5783 , n5784 , n5785 , n5786 , n5787 , n5788 , n5789 , n5790 ,
n5791 , n5792 , n5793 , n5794 , n5795 , n5796 , n5797 , n5798 , n5799 , n5800 ,
n5801 , n5802 , n5803 , n5804 , n5805 , n5806 , n5807 , n5808 , n5809 , n5810 ,
n5811 , n5812 , n5813 , n5814 , n5815 , n5816 , n5817 , n5818 , n5819 , n5820 ,
n5821 , n5822 , n5823 , n5824 , n5825 , n5826 , n5827 , n5828 , n5829 , n5830 ,
n5831 , n5832 , n5833 , n5834 , n5835 , n5836 , n5837 , n5838 , n5839 , n5840 ,
n5841 , n5842 , n5843 , n5844 , n5845 , n5846 , n5847 , n5848 , n5849 , n5850 ,
n5851 , n5852 , n5853 , n5854 , n5855 , n5856 , n5857 , n5858 , n5859 , n5860 ,
n5861 , n5862 , n5863 , n5864 , n5865 , n5866 , n5867 , n5868 , n5869 , n5870 ,
n5871 , n5872 , n5873 , n5874 , n5875 , n5876 , n5877 , n5878 , n5879 , n5880 ,
n5881 , n5882 , n5883 , n5884 , n5885 , n5886 , n5887 , n5888 , n5889 , n5890 ,
n5891 , n5892 , n5893 , n5894 , n5895 , n5896 , n5897 , n5898 , n5899 , n5900 ,
n5901 , n5902 , n5903 , n5904 , n5905 , n5906 , n5907 , n5908 , n5909 , n5910 ,
n5911 , n5912 , n5913 , n5914 , n5915 , n5916 , n5917 , n5918 , n5919 , n5920 ,
n5921 , n5922 , n5923 , n5924 , n5925 , n5926 , n5927 , n5928 , n5929 , n5930 ,
n5931 , n5932 , n5933 , n5934 , n5935 , n5936 , n5937 , n5938 , n5939 , n5940 ,
n5941 , n5942 , n5943 , n5944 , n5945 , n5946 , n5947 , n5948 , n5949 , n5950 ,
n5951 , n5952 , n5953 , n5954 , n5955 , n5956 , n5957 , n5958 , n5959 , n5960 ,
n5961 , n5962 , n5963 , n5964 , n5965 , n5966 , n5967 , n5968 , n5969 , n5970 ,
n5971 , n5972 , n5973 , n5974 , n5975 , n5976 , n5977 , n5978 , n5979 , n5980 ,
n5981 , n5982 , n5983 , n5984 , n5985 , n5986 , n5987 , n5988 , n5989 , n5990 ,
n5991 , n5992 , n5993 , n5994 , n5995 , n5996 , n5997 , n5998 , n5999 , n6000 ,
n6001 , n6002 , n6003 , n6004 , n6005 , n6006 , n6007 , n6008 , n6009 , n6010 ,
n6011 , n6012 , n6013 , n6014 , n6015 , n6016 , n6017 , n6018 , n6019 , n6020 ,
n6021 , n6022 , n6023 , n6024 , n6025 , n6026 , n6027 , n6028 , n6029 , n6030 ,
n6031 , n6032 , n6033 , n6034 , n6035 , n6036 , n6037 , n6038 , n6039 , n6040 ,
n6041 , n6042 , n6043 , n6044 , n6045 , n6046 , n6047 , n6048 , n6049 , n6050 ,
n6051 , n6052 , n6053 , n6054 , n6055 , n6056 , n6057 , n6058 , n6059 , n6060 ,
n6061 , n6062 , n6063 , n6064 , n6065 , n6066 , n6067 , n6068 , n6069 , n6070 ,
n6071 , n6072 , n6073 , n6074 , n6075 , n6076 , n6077 , n6078 , n6079 , n6080 ,
n6081 , n6082 , n6083 , n6084 , n6085 , n6086 , n6087 , n6088 , n6089 , n6090 ,
n6091 , n6092 , n6093 , n6094 , n6095 , n6096 , n6097 , n6098 , n6099 , n6100 ,
n6101 , n6102 , n6103 , n6104 , n6105 , n6106 , n6107 , n6108 , n6109 , n6110 ,
n6111 , n6112 , n6113 , n6114 , n6115 , n6116 , n6117 , n6118 , n6119 , n6120 ,
n6121 , n6122 , n6123 , n6124 , n6125 , n6126 , n6127 , n6128 , n6129 , n6130 ,
n6131 , n6132 , n6133 , n6134 , n6135 , n6136 , n6137 , n6138 , n6139 , n6140 ,
n6141 , n6142 , n6143 , n6144 , n6145 , n6146 , n6147 , n6148 , n6149 , n6150 ,
n6151 , n6152 , n6153 , n6154 , n6155 , n6156 , n6157 , n6158 , n6159 , n6160 ,
n6161 , n6162 , n6163 , n6164 , n6165 , n6166 , n6167 , n6168 , n6169 , n6170 ,
n6171 , n6172 , n6173 , n6174 , n6175 , n6176 , n6177 , n6178 , n6179 , n6180 ,
n6181 , n6182 , n6183 , n6184 , n6185 , n6186 , n6187 , n6188 , n6189 , n6190 ,
n6191 , n6192 , n6193 , n6194 , n6195 , n6196 , n6197 , n6198 , n6199 , n6200 ,
n6201 , n6202 , n6203 , n6204 , n6205 , n6206 , n6207 , n6208 , n6209 , n6210 ,
n6211 , n6212 , n6213 , n6214 , n6215 , n6216 , n6217 , n6218 , n6219 , n6220 ,
n6221 , n6222 , n6223 , n6224 , n6225 , n6226 , n6227 , n6228 , n6229 , n6230 ,
n6231 , n6232 , n6233 , n6234 , n6235 , n6236 , n6237 , n6238 , n6239 , n6240 ,
n6241 , n6242 , n6243 , n6244 , n6245 , n6246 , n6247 , n6248 , n6249 , n6250 ,
n6251 , n6252 , n6253 , n6254 , n6255 , n6256 , n6257 , n6258 , n6259 , n6260 ,
n6261 , n6262 , n6263 , n6264 , n6265 , n6266 , n6267 , n6268 , n6269 , n6270 ,
n6271 , n6272 , n6273 , n6274 , n6275 , n6276 , n6277 , n6278 , n6279 , n6280 ,
n6281 , n6282 , n6283 , n6284 , n6285 , n6286 , n6287 , n6288 , n6289 , n6290 ,
n6291 , n6292 , n6293 , n6294 , n6295 , n6296 , n6297 , n6298 , n6299 , n6300 ,
n6301 , n6302 , n6303 , n6304 , n6305 , n6306 , n6307 , n6308 , n6309 , n6310 ,
n6311 , n6312 , n6313 , n6314 , n6315 , n6316 , n6317 , n6318 , n6319 , n6320 ,
n6321 , n6322 , n6323 , n6324 , n6325 , n6326 , n6327 , n6328 , n6329 , n6330 ,
n6331 , n6332 , n6333 , n6334 , n6335 , n6336 , n6337 , n6338 , n6339 , n6340 ,
n6341 , n6342 , n6343 , n6344 , n6345 , n6346 , n6347 , n6348 , n6349 , n6350 ,
n6351 , n6352 , n6353 , n6354 , n6355 , n6356 , n6357 , n6358 , n6359 , n6360 ,
n6361 , n6362 , n6363 , n6364 , n6365 , n6366 , n6367 , n6368 , n6369 , n6370 ,
n6371 , n6372 , n6373 , n6374 , n6375 , n6376 , n6377 , n6378 , n6379 , n6380 ,
n6381 , n6382 , n6383 , n6384 , n6385 , n6386 , n6387 , n6388 , n6389 , n6390 ,
n6391 , n6392 , n6393 , n6394 , n6395 , n6396 , n6397 , n6398 , n6399 , n6400 ,
n6401 , n6402 , n6403 , n6404 , n6405 , n6406 , n6407 , n6408 , n6409 , n6410 ,
n6411 , n6412 , n6413 , n6414 , n6415 , n6416 , n6417 , n6418 , n6419 , n6420 ,
n6421 , n6422 , n6423 , n6424 , n6425 , n6426 , n6427 , n6428 , n6429 , n6430 ,
n6431 , n6432 , n6433 , n6434 , n6435 , n6436 , n6437 , n6438 , n6439 , n6440 ,
n6441 , n6442 , n6443 , n6444 , n6445 , n6446 , n6447 , n6448 , n6449 , n6450 ,
n6451 , n6452 , n6453 , n6454 , n6455 , n6456 , n6457 , n6458 , n6459 , n6460 ,
n6461 , n6462 , n6463 , n6464 , n6465 , n6466 , n6467 , n6468 , n6469 , n6470 ,
n6471 , n6472 , n6473 , n6474 , n6475 , n6476 , n6477 , n6478 , n6479 , n6480 ,
n6481 , n6482 , n6483 , n6484 , n6485 , n6486 , n6487 , n6488 , n6489 , n6490 ,
n6491 , n6492 , n6493 , n6494 , n6495 , n6496 , n6497 , n6498 , n6499 , n6500 ,
n6501 , n6502 , n6503 , n6504 , n6505 , n6506 , n6507 , n6508 , n6509 , n6510 ,
n6511 , n6512 , n6513 , n6514 , n6515 , n6516 , n6517 , n6518 , n6519 , n6520 ,
n6521 , n6522 , n6523 , n6524 , n6525 , n6526 , n6527 , n6528 , n6529 , n6530 ,
n6531 , n6532 , n6533 , n6534 , n6535 , n6536 , n6537 , n6538 , n6539 , n6540 ,
n6541 , n6542 , n6543 , n6544 , n6545 , n6546 , n6547 , n6548 , n6549 , n6550 ,
n6551 , n6552 , n6553 , n6554 , n6555 , n6556 , n6557 , n6558 , n6559 , n6560 ,
n6561 , n6562 , n6563 , n6564 , n6565 , n6566 , n6567 , n6568 , n6569 , n6570 ,
n6571 , n6572 , n6573 , n6574 , n6575 , n6576 , n6577 , n6578 , n6579 , n6580 ,
n6581 , n6582 , n6583 , n6584 , n6585 , n6586 , n6587 , n6588 , n6589 , n6590 ,
n6591 , n6592 , n6593 , n6594 , n6595 , n6596 , n6597 , n6598 , n6599 , n6600 ,
n6601 , n6602 , n6603 , n6604 , n6605 , n6606 , n6607 , n6608 , n6609 , n6610 ,
n6611 , n6612 , n6613 , n6614 , n6615 , n6616 , n6617 , n6618 , n6619 , n6620 ,
n6621 , n6622 , n6623 , n6624 , n6625 , n6626 , n6627 , n6628 , n6629 , n6630 ,
n6631 , n6632 , n6633 , n6634 , n6635 , n6636 , n6637 , n6638 , n6639 , n6640 ,
n6641 , n6642 , n6643 , n6644 , n6645 , n6646 , n6647 , n6648 , n6649 , n6650 ,
n6651 , n6652 , n6653 , n6654 , n6655 , n6656 , n6657 , n6658 , n6659 , n6660 ,
n6661 , n6662 , n6663 , n6664 , n6665 , n6666 , n6667 , n6668 , n6669 , n6670 ,
n6671 , n6672 , n6673 , n6674 , n6675 , n6676 , n6677 , n6678 , n6679 , n6680 ,
n6681 , n6682 , n6683 , n6684 , n6685 , n6686 , n6687 , n6688 , n6689 , n6690 ,
n6691 , n6692 , n6693 , n6694 , n6695 , n6696 , n6697 , n6698 , n6699 , n6700 ,
n6701 , n6702 , n6703 , n6704 , n6705 , n6706 , n6707 , n6708 , n6709 , n6710 ,
n6711 , n6712 , n6713 , n6714 , n6715 , n6716 , n6717 , n6718 , n6719 , n6720 ,
n6721 , n6722 , n6723 , n6724 , n6725 , n6726 , n6727 , n6728 , n6729 , n6730 ,
n6731 , n6732 , n6733 , n6734 , n6735 , n6736 , n6737 , n6738 , n6739 , n6740 ,
n6741 , n6742 , n6743 , n6744 , n6745 , n6746 , n6747 , n6748 , n6749 , n6750 ,
n6751 , n6752 , n6753 , n6754 , n6755 , n6756 , n6757 , n6758 , n6759 , n6760 ,
n6761 , n6762 , n6763 , n6764 , n6765 , n6766 , n6767 , n6768 , n6769 , n6770 ,
n6771 , n6772 , n6773 , n6774 , n6775 , n6776 , n6777 , n6778 , n6779 , n6780 ,
n6781 , n6782 , n6783 , n6784 , n6785 , n6786 , n6787 , n6788 , n6789 , n6790 ,
n6791 , n6792 , n6793 , n6794 , n6795 , n6796 , n6797 , n6798 , n6799 , n6800 ,
n6801 , n6802 , n6803 , n6804 , n6805 , n6806 , n6807 , n6808 , n6809 , n6810 ,
n6811 , n6812 , n6813 , n6814 , n6815 , n6816 , n6817 , n6818 , n6819 , n6820 ,
n6821 , n6822 , n6823 , n6824 , n6825 , n6826 , n6827 , n6828 , n6829 , n6830 ,
n6831 , n6832 , n6833 , n6834 , n6835 , n6836 , n6837 , n6838 , n6839 , n6840 ,
n6841 , n6842 , n6843 , n6844 , n6845 , n6846 , n6847 , n6848 , n6849 , n6850 ,
n6851 , n6852 , n6853 , n6854 , n6855 , n6856 , n6857 , n6858 , n6859 , n6860 ,
n6861 , n6862 , n6863 , n6864 , n6865 , n6866 , n6867 , n6868 , n6869 , n6870 ,
n6871 , n6872 , n6873 , n6874 , n6875 , n6876 , n6877 , n6878 , n6879 , n6880 ,
n6881 , n6882 , n6883 , n6884 , n6885 , n6886 , n6887 , n6888 , n6889 , n6890 ,
n6891 , n6892 , n6893 , n6894 , n6895 , n6896 , n6897 , n6898 , n6899 , n6900 ,
n6901 , n6902 , n6903 , n6904 , n6905 , n6906 , n6907 , n6908 , n6909 , n6910 ,
n6911 , n6912 , n6913 , n6914 , n6915 , n6916 , n6917 , n6918 , n6919 , n6920 ,
n6921 , n6922 , n6923 , n6924 , n6925 , n6926 , n6927 , n6928 , n6929 , n6930 ,
n6931 , n6932 , n6933 , n6934 , n6935 , n6936 , n6937 , n6938 , n6939 , n6940 ,
n6941 , n6942 , n6943 , n6944 , n6945 , n6946 , n6947 , n6948 , n6949 , n6950 ,
n6951 , n6952 , n6953 , n6954 , n6955 , n6956 , n6957 , n6958 , n6959 , n6960 ,
n6961 , n6962 , n6963 , n6964 , n6965 , n6966 , n6967 , n6968 , n6969 , n6970 ,
n6971 , n6972 , n6973 , n6974 , n6975 , n6976 , n6977 , n6978 , n6979 , n6980 ,
n6981 , n6982 , n6983 , n6984 , n6985 , n6986 , n6987 , n6988 , n6989 , n6990 ,
n6991 , n6992 , n6993 , n6994 , n6995 , n6996 , n6997 , n6998 , n6999 , n7000 ,
n7001 , n7002 , n7003 , n7004 , n7005 , n7006 , n7007 , n7008 , n7009 , n7010 ,
n7011 , n7012 , n7013 , n7014 , n7015 , n7016 , n7017 , n7018 , n7019 , n7020 ,
n7021 , n7022 , n7023 , n7024 , n7025 , n7026 , n7027 , n7028 , n7029 , n7030 ,
n7031 , n7032 , n7033 , n7034 , n7035 , n7036 , n7037 , n7038 , n7039 , n7040 ,
n7041 , n7042 , n7043 , n7044 , n7045 , n7046 , n7047 , n7048 , n7049 , n7050 ,
n7051 , n7052 , n7053 , n7054 , n7055 , n7056 , n7057 , n7058 , n7059 , n7060 ,
n7061 , n7062 , n7063 , n7064 , n7065 , n7066 , n7067 , n7068 , n7069 , n7070 ,
n7071 , n7072 , n7073 , n7074 , n7075 , n7076 , n7077 , n7078 , n7079 , n7080 ,
n7081 , n7082 , n7083 , n7084 , n7085 , n7086 , n7087 , n7088 , n7089 , n7090 ,
n7091 , n7092 , n7093 , n7094 , n7095 , n7096 , n7097 , n7098 , n7099 , n7100 ,
n7101 , n7102 , n7103 , n7104 , n7105 , n7106 , n7107 , n7108 , n7109 , n7110 ,
n7111 , n7112 , n7113 , n7114 , n7115 , n7116 , n7117 , n7118 , n7119 , n7120 ,
n7121 , n7122 , n7123 , n7124 , n7125 , n7126 , n7127 , n7128 , n7129 , n7130 ,
n7131 , n7132 , n7133 , n7134 , n7135 , n7136 , n7137 , n7138 , n7139 , n7140 ,
n7141 , n7142 , n7143 , n7144 , n7145 , n7146 , n7147 , n7148 , n7149 , n7150 ,
n7151 , n7152 , n7153 , n7154 , n7155 , n7156 , n7157 , n7158 , n7159 , n7160 ,
n7161 , n7162 , n7163 , n7164 , n7165 , n7166 , n7167 , n7168 , n7169 , n7170 ,
n7171 , n7172 , n7173 , n7174 , n7175 , n7176 , n7177 , n7178 , n7179 , n7180 ,
n7181 , n7182 , n7183 , n7184 , n7185 , n7186 , n7187 , n7188 , n7189 , n7190 ,
n7191 , n7192 , n7193 , n7194 , n7195 , n7196 , n7197 , n7198 , n7199 , n7200 ,
n7201 , n7202 , n7203 , n7204 , n7205 , n7206 , n7207 , n7208 , n7209 , n7210 ,
n7211 , n7212 , n7213 , n7214 , n7215 , n7216 , n7217 , n7218 , n7219 , n7220 ,
n7221 , n7222 , n7223 , n7224 , n7225 , n7226 , n7227 , n7228 , n7229 , n7230 ,
n7231 , n7232 , n7233 , n7234 , n7235 , n7236 , n7237 , n7238 , n7239 , n7240 ,
n7241 , n7242 , n7243 , n7244 , n7245 , n7246 , n7247 , n7248 , n7249 , n7250 ,
n7251 , n7252 , n7253 , n7254 , n7255 , n7256 , n7257 , n7258 , n7259 , n7260 ,
n7261 , n7262 , n7263 , n7264 , n7265 , n7266 , n7267 , n7268 , n7269 , n7270 ,
n7271 , n7272 , n7273 , n7274 , n7275 , n7276 , n7277 , n7278 , n7279 , n7280 ,
n7281 , n7282 , n7283 , n7284 , n7285 , n7286 , n7287 , n7288 , n7289 , n7290 ,
n7291 , n7292 , n7293 , n7294 , n7295 , n7296 , n7297 , n7298 , n7299 , n7300 ,
n7301 , n7302 , n7303 , n7304 , n7305 , n7306 , n7307 , n7308 , n7309 , n7310 ,
n7311 , n7312 , n7313 , n7314 , n7315 , n7316 , n7317 , n7318 , n7319 , n7320 ,
n7321 , n7322 , n7323 , n7324 , n7325 , n7326 , n7327 , n7328 , n7329 , n7330 ,
n7331 , n7332 , n7333 , n7334 , n7335 , n7336 , n7337 , n7338 , n7339 , n7340 ,
n7341 , n7342 , n7343 , n7344 , n7345 , n7346 , n7347 , n7348 , n7349 , n7350 ,
n7351 , n7352 , n7353 , n7354 , n7355 , n7356 , n7357 , n7358 , n7359 , n7360 ,
n7361 , n7362 , n7363 , n7364 , n7365 , n7366 , n7367 , n7368 , n7369 , n7370 ,
n7371 , n7372 , n7373 , n7374 , n7375 , n7376 , n7377 , n7378 , n7379 , n7380 ,
n7381 , n7382 , n7383 , n7384 , n7385 , n7386 , n7387 , n7388 , n7389 , n7390 ,
n7391 , n7392 , n7393 , n7394 , n7395 , n7396 , n7397 , n7398 , n7399 , n7400 ,
n7401 , n7402 , n7403 , n7404 , n7405 , n7406 , n7407 , n7408 , n7409 , n7410 ,
n7411 , n7412 , n7413 , n7414 , n7415 , n7416 , n7417 , n7418 , n7419 , n7420 ,
n7421 , n7422 , n7423 , n7424 , n7425 , n7426 , n7427 , n7428 , n7429 , n7430 ,
n7431 , n7432 , n7433 , n7434 , n7435 , n7436 , n7437 , n7438 , n7439 , n7440 ,
n7441 , n7442 , n7443 , n7444 , n7445 , n7446 , n7447 , n7448 , n7449 , n7450 ,
n7451 , n7452 , n7453 , n7454 , n7455 , n7456 , n7457 , n7458 , n7459 , n7460 ,
n7461 , n7462 , n7463 , n7464 , n7465 , n7466 , n7467 , n7468 , n7469 , n7470 ,
n7471 , n7472 , n7473 , n7474 , n7475 , n7476 , n7477 , n7478 , n7479 , n7480 ,
n7481 , n7482 , n7483 , n7484 , n7485 , n7486 , n7487 , n7488 , n7489 , n7490 ,
n7491 , n7492 , n7493 , n7494 , n7495 , n7496 , n7497 , n7498 , n7499 , n7500 ,
n7501 , n7502 , n7503 , n7504 , n7505 , n7506 , n7507 , n7508 , n7509 , n7510 ,
n7511 , n7512 , n7513 , n7514 , n7515 , n7516 , n7517 , n7518 , n7519 , n7520 ,
n7521 , n7522 , n7523 , n7524 , n7525 , n7526 , n7527 , n7528 , n7529 , n7530 ,
n7531 , n7532 , n7533 , n7534 , n7535 , n7536 , n7537 , n7538 , n7539 , n7540 ,
n7541 , n7542 , n7543 , n7544 , n7545 , n7546 , n7547 , n7548 , n7549 , n7550 ,
n7551 , n7552 , n7553 , n7554 , n7555 , n7556 , n7557 , n7558 , n7559 , n7560 ,
n7561 , n7562 , n7563 , n7564 , n7565 , n7566 , n7567 , n7568 , n7569 , n7570 ,
n7571 , n7572 , n7573 , n7574 , n7575 , n7576 , n7577 , n7578 , n7579 , n7580 ,
n7581 , n7582 , n7583 , n7584 , n7585 , n7586 , n7587 , n7588 , n7589 , n7590 ,
n7591 , n7592 , n7593 , n7594 , n7595 , n7596 , n7597 , n7598 , n7599 , n7600 ,
n7601 , n7602 , n7603 , n7604 , n7605 , n7606 , n7607 , n7608 , n7609 , n7610 ,
n7611 , n7612 , n7613 , n7614 , n7615 , n7616 , n7617 , n7618 , n7619 , n7620 ,
n7621 , n7622 , n7623 , n7624 , n7625 , n7626 , n7627 , n7628 , n7629 , n7630 ,
n7631 , n7632 , n7633 , n7634 , n7635 , n7636 , n7637 , n7638 , n7639 , n7640 ,
n7641 , n7642 , n7643 , n7644 , n7645 , n7646 , n7647 , n7648 , n7649 , n7650 ,
n7651 , n7652 , n7653 , n7654 , n7655 , n7656 , n7657 , n7658 , n7659 , n7660 ,
n7661 , n7662 , n7663 , n7664 , n7665 , n7666 , n7667 , n7668 , n7669 , n7670 ,
n7671 , n7672 , n7673 , n7674 , n7675 , n7676 , n7677 , n7678 , n7679 , n7680 ,
n7681 , n7682 , n7683 , n7684 , n7685 , n7686 , n7687 , n7688 , n7689 , n7690 ,
n7691 , n7692 , n7693 , n7694 , n7695 , n7696 , n7697 , n7698 , n7699 , n7700 ,
n7701 , n7702 , n7703 , n7704 , n7705 , n7706 , n7707 , n7708 , n7709 , n7710 ,
n7711 , n7712 , n7713 , n7714 , n7715 , n7716 , n7717 , n7718 , n7719 , n7720 ,
n7721 , n7722 , n7723 , n7724 , n7725 , n7726 , n7727 , n7728 , n7729 , n7730 ,
n7731 , n7732 , n7733 , n7734 , n7735 , n7736 , n7737 , n7738 , n7739 , n7740 ,
n7741 , n7742 , n7743 , n7744 , n7745 , n7746 , n7747 , n7748 , n7749 , n7750 ,
n7751 , n7752 , n7753 , n7754 , n7755 , n7756 , n7757 , n7758 , n7759 , n7760 ,
n7761 , n7762 , n7763 , n7764 , n7765 , n7766 , n7767 , n7768 , n7769 , n7770 ,
n7771 , n7772 , n7773 , n7774 , n7775 , n7776 , n7777 , n7778 , n7779 , n7780 ,
n7781 , n7782 , n7783 , n7784 , n7785 , n7786 , n7787 , n7788 , n7789 , n7790 ,
n7791 , n7792 , n7793 , n7794 , n7795 , n7796 , n7797 , n7798 , n7799 , n7800 ,
n7801 , n7802 , n7803 , n7804 , n7805 , n7806 , n7807 , n7808 , n7809 , n7810 ,
n7811 , n7812 , n7813 , n7814 , n7815 , n7816 , n7817 , n7818 , n7819 , n7820 ,
n7821 , n7822 , n7823 , n7824 , n7825 , n7826 , n7827 , n7828 , n7829 , n7830 ,
n7831 , n7832 , n7833 , n7834 , n7835 , n7836 , n7837 , n7838 , n7839 , n7840 ,
n7841 , n7842 , n7843 , n7844 , n7845 , n7846 , n7847 , n7848 , n7849 , n7850 ,
n7851 , n7852 , n7853 , n7854 , n7855 , n7856 , n7857 , n7858 , n7859 , n7860 ,
n7861 , n7862 , n7863 , n7864 , n7865 , n7866 , n7867 , n7868 , n7869 , n7870 ,
n7871 , n7872 , n7873 , n7874 , n7875 , n7876 , n7877 , n7878 , n7879 , n7880 ,
n7881 , n7882 , n7883 , n7884 , n7885 , n7886 , n7887 , n7888 , n7889 , n7890 ,
n7891 , n7892 , n7893 , n7894 , n7895 , n7896 , n7897 , n7898 , n7899 , n7900 ,
n7901 , n7902 , n7903 , n7904 , n7905 , n7906 , n7907 , n7908 , n7909 , n7910 ,
n7911 , n7912 , n7913 , n7914 , n7915 , n7916 , n7917 , n7918 , n7919 , n7920 ,
n7921 , n7922 , n7923 , n7924 , n7925 , n7926 , n7927 , n7928 , n7929 , n7930 ,
n7931 , n7932 , n7933 , n7934 , n7935 , n7936 , n7937 , n7938 , n7939 , n7940 ,
n7941 , n7942 , n7943 , n7944 , n7945 , n7946 , n7947 , n7948 , n7949 , n7950 ,
n7951 , n7952 , n7953 , n7954 , n7955 , n7956 , n7957 , n7958 , n7959 , n7960 ,
n7961 , n7962 , n7963 , n7964 , n7965 , n7966 , n7967 , n7968 , n7969 , n7970 ,
n7971 , n7972 , n7973 , n7974 , n7975 , n7976 , n7977 , n7978 , n7979 , n7980 ,
n7981 , n7982 , n7983 , n7984 , n7985 , n7986 , n7987 , n7988 , n7989 , n7990 ,
n7991 , n7992 , n7993 , n7994 , n7995 , n7996 , n7997 , n7998 , n7999 , n8000 ,
n8001 , n8002 , n8003 , n8004 , n8005 , n8006 , n8007 , n8008 , n8009 , n8010 ,
n8011 , n8012 , n8013 , n8014 , n8015 , n8016 , n8017 , n8018 , n8019 , n8020 ,
n8021 , n8022 , n8023 , n8024 , n8025 , n8026 , n8027 , n8028 , n8029 , n8030 ,
n8031 , n8032 , n8033 , n8034 , n8035 , n8036 , n8037 , n8038 , n8039 , n8040 ,
n8041 , n8042 , n8043 , n8044 , n8045 , n8046 , n8047 , n8048 , n8049 , n8050 ,
n8051 , n8052 , n8053 , n8054 , n8055 , n8056 , n8057 , n8058 , n8059 , n8060 ,
n8061 , n8062 , n8063 , n8064 , n8065 , n8066 , n8067 , n8068 , n8069 , n8070 ,
n8071 , n8072 , n8073 , n8074 , n8075 , n8076 , n8077 , n8078 , n8079 , n8080 ,
n8081 , n8082 , n8083 , n8084 , n8085 , n8086 , n8087 , n8088 , n8089 , n8090 ,
n8091 , n8092 , n8093 , n8094 , n8095 , n8096 , n8097 , n8098 , n8099 , n8100 ,
n8101 , n8102 , n8103 , n8104 , n8105 , n8106 , n8107 , n8108 , n8109 , n8110 ,
n8111 , n8112 , n8113 , n8114 , n8115 , n8116 , n8117 , n8118 , n8119 , n8120 ,
n8121 , n8122 , n8123 , n8124 , n8125 , n8126 , n8127 , n8128 , n8129 , n8130 ,
n8131 , n8132 , n8133 , n8134 , n8135 , n8136 , n8137 , n8138 , n8139 , n8140 ,
n8141 , n8142 , n8143 , n8144 , n8145 , n8146 , n8147 , n8148 , n8149 , n8150 ,
n8151 , n8152 , n8153 , n8154 , n8155 , n8156 , n8157 , n8158 , n8159 , n8160 ,
n8161 , n8162 , n8163 , n8164 , n8165 , n8166 , n8167 , n8168 , n8169 , n8170 ,
n8171 , n8172 , n8173 , n8174 , n8175 , n8176 , n8177 , n8178 , n8179 , n8180 ,
n8181 , n8182 , n8183 , n8184 , n8185 , n8186 , n8187 , n8188 , n8189 , n8190 ,
n8191 , n8192 , n8193 , n8194 , n8195 , n8196 , n8197 , n8198 , n8199 , n8200 ,
n8201 , n8202 , n8203 , n8204 , n8205 , n8206 , n8207 , n8208 , n8209 , n8210 ,
n8211 , n8212 , n8213 , n8214 , n8215 , n8216 , n8217 , n8218 , n8219 , n8220 ,
n8221 , n8222 , n8223 , n8224 , n8225 , n8226 , n8227 , n8228 , n8229 , n8230 ,
n8231 , n8232 , n8233 , n8234 , n8235 , n8236 , n8237 , n8238 , n8239 , n8240 ,
n8241 , n8242 , n8243 , n8244 , n8245 , n8246 , n8247 , n8248 , n8249 , n8250 ,
n8251 , n8252 , n8253 , n8254 , n8255 , n8256 , n8257 , n8258 , n8259 , n8260 ,
n8261 , n8262 , n8263 , n8264 , n8265 , n8266 , n8267 , n8268 , n8269 , n8270 ,
n8271 , n8272 , n8273 , n8274 , n8275 , n8276 , n8277 , n8278 , n8279 , n8280 ,
n8281 , n8282 , n8283 , n8284 , n8285 , n8286 , n8287 , n8288 , n8289 , n8290 ,
n8291 , n8292 , n8293 , n8294 , n8295 , n8296 , n8297 , n8298 , n8299 , n8300 ,
n8301 , n8302 , n8303 , n8304 , n8305 , n8306 , n8307 , n8308 , n8309 , n8310 ,
n8311 , n8312 , n8313 , n8314 , n8315 , n8316 , n8317 , n8318 , n8319 , n8320 ,
n8321 , n8322 , n8323 , n8324 , n8325 , n8326 , n8327 , n8328 , n8329 , n8330 ,
n8331 , n8332 , n8333 , n8334 , n8335 , n8336 , n8337 , n8338 , n8339 , n8340 ,
n8341 , n8342 , n8343 , n8344 , n8345 , n8346 , n8347 , n8348 , n8349 , n8350 ,
n8351 , n8352 , n8353 , n8354 , n8355 , n8356 , n8357 , n8358 , n8359 , n8360 ,
n8361 , n8362 , n8363 , n8364 , n8365 , n8366 , n8367 , n8368 , n8369 , n8370 ,
n8371 , n8372 , n8373 , n8374 , n8375 , n8376 , n8377 , n8378 , n8379 , n8380 ,
n8381 , n8382 , n8383 , n8384 , n8385 , n8386 , n8387 , n8388 , n8389 , n8390 ,
n8391 , n8392 , n8393 , n8394 , n8395 , n8396 , n8397 , n8398 , n8399 , n8400 ,
n8401 , n8402 , n8403 , n8404 , n8405 , n8406 , n8407 , n8408 , n8409 , n8410 ,
n8411 , n8412 , n8413 , n8414 , n8415 , n8416 , n8417 , n8418 , n8419 , n8420 ,
n8421 , n8422 , n8423 , n8424 , n8425 , n8426 , n8427 , n8428 , n8429 , n8430 ,
n8431 , n8432 , n8433 , n8434 , n8435 , n8436 , n8437 , n8438 , n8439 , n8440 ,
n8441 , n8442 , n8443 , n8444 , n8445 , n8446 , n8447 , n8448 , n8449 , n8450 ,
n8451 , n8452 , n8453 , n8454 , n8455 , n8456 , n8457 , n8458 , n8459 , n8460 ,
n8461 , n8462 , n8463 , n8464 , n8465 , n8466 , n8467 , n8468 , n8469 , n8470 ,
n8471 , n8472 , n8473 , n8474 , n8475 , n8476 , n8477 , n8478 , n8479 , n8480 ,
n8481 , n8482 , n8483 , n8484 , n8485 , n8486 , n8487 , n8488 , n8489 , n8490 ,
n8491 , n8492 , n8493 , n8494 , n8495 , n8496 , n8497 , n8498 , n8499 , n8500 ,
n8501 , n8502 , n8503 , n8504 , n8505 , n8506 , n8507 , n8508 , n8509 , n8510 ,
n8511 , n8512 , n8513 , n8514 , n8515 , n8516 , n8517 , n8518 , n8519 , n8520 ,
n8521 , n8522 , n8523 , n8524 , n8525 , n8526 , n8527 , n8528 , n8529 , n8530 ,
n8531 , n8532 , n8533 , n8534 , n8535 , n8536 , n8537 , n8538 , n8539 , n8540 ,
n8541 , n8542 , n8543 , n8544 , n8545 , n8546 , n8547 , n8548 , n8549 , n8550 ,
n8551 , n8552 , n8553 , n8554 , n8555 , n8556 , n8557 , n8558 , n8559 , n8560 ,
n8561 , n8562 , n8563 , n8564 , n8565 , n8566 , n8567 , n8568 , n8569 , n8570 ,
n8571 , n8572 , n8573 , n8574 , n8575 , n8576 , n8577 , n8578 , n8579 , n8580 ,
n8581 , n8582 , n8583 , n8584 , n8585 , n8586 , n8587 , n8588 , n8589 , n8590 ,
n8591 , n8592 , n8593 , n8594 , n8595 , n8596 , n8597 , n8598 , n8599 , n8600 ,
n8601 , n8602 , n8603 , n8604 , n8605 , n8606 , n8607 , n8608 , n8609 , n8610 ,
n8611 , n8612 , n8613 , n8614 , n8615 , n8616 , n8617 , n8618 , n8619 , n8620 ,
n8621 , n8622 , n8623 , n8624 , n8625 , n8626 , n8627 , n8628 , n8629 , n8630 ,
n8631 , n8632 , n8633 , n8634 , n8635 , n8636 , n8637 , n8638 , n8639 , n8640 ,
n8641 , n8642 , n8643 , n8644 , n8645 , n8646 , n8647 , n8648 , n8649 , n8650 ,
n8651 , n8652 , n8653 , n8654 , n8655 , n8656 , n8657 , n8658 , n8659 , n8660 ,
n8661 , n8662 , n8663 , n8664 , n8665 , n8666 , n8667 , n8668 , n8669 , n8670 ,
n8671 , n8672 , n8673 , n8674 , n8675 , n8676 , n8677 , n8678 , n8679 , n8680 ,
n8681 , n8682 , n8683 , n8684 , n8685 , n8686 , n8687 , n8688 , n8689 , n8690 ,
n8691 , n8692 , n8693 , n8694 , n8695 , n8696 , n8697 , n8698 , n8699 , n8700 ,
n8701 , n8702 , n8703 , n8704 , n8705 , n8706 , n8707 , n8708 , n8709 , n8710 ,
n8711 , n8712 , n8713 , n8714 , n8715 , n8716 , n8717 , n8718 , n8719 , n8720 ,
n8721 , n8722 , n8723 , n8724 , n8725 , n8726 , n8727 , n8728 , n8729 , n8730 ,
n8731 , n8732 , n8733 , n8734 , n8735 , n8736 , n8737 , n8738 , n8739 , n8740 ,
n8741 , n8742 , n8743 , n8744 , n8745 , n8746 , n8747 , n8748 , n8749 , n8750 ,
n8751 , n8752 , n8753 , n8754 , n8755 , n8756 , n8757 , n8758 , n8759 , n8760 ,
n8761 , n8762 , n8763 , n8764 , n8765 , n8766 , n8767 , n8768 , n8769 , n8770 ,
n8771 , n8772 , n8773 , n8774 , n8775 , n8776 , n8777 , n8778 , n8779 , n8780 ,
n8781 , n8782 , n8783 , n8784 , n8785 , n8786 , n8787 , n8788 , n8789 , n8790 ,
n8791 , n8792 , n8793 , n8794 , n8795 , n8796 , n8797 , n8798 , n8799 , n8800 ,
n8801 , n8802 , n8803 , n8804 , n8805 , n8806 , n8807 , n8808 , n8809 , n8810 ,
n8811 , n8812 , n8813 , n8814 , n8815 , n8816 , n8817 , n8818 , n8819 , n8820 ,
n8821 , n8822 , n8823 , n8824 , n8825 , n8826 , n8827 , n8828 , n8829 , n8830 ,
n8831 , n8832 , n8833 , n8834 , n8835 , n8836 , n8837 , n8838 , n8839 , n8840 ,
n8841 , n8842 , n8843 , n8844 , n8845 , n8846 , n8847 , n8848 , n8849 , n8850 ,
n8851 , n8852 , n8853 , n8854 , n8855 , n8856 , n8857 , n8858 , n8859 , n8860 ,
n8861 , n8862 , n8863 , n8864 , n8865 , n8866 , n8867 , n8868 , n8869 , n8870 ,
n8871 , n8872 , n8873 , n8874 , n8875 , n8876 , n8877 , n8878 , n8879 , n8880 ,
n8881 , n8882 , n8883 , n8884 , n8885 , n8886 , n8887 , n8888 , n8889 , n8890 ,
n8891 , n8892 , n8893 , n8894 , n8895 , n8896 , n8897 , n8898 , n8899 , n8900 ,
n8901 , n8902 , n8903 , n8904 , n8905 , n8906 , n8907 , n8908 , n8909 , n8910 ,
n8911 , n8912 , n8913 , n8914 , n8915 , n8916 , n8917 , n8918 , n8919 , n8920 ,
n8921 , n8922 , n8923 , n8924 , n8925 , n8926 , n8927 , n8928 , n8929 , n8930 ,
n8931 , n8932 , n8933 , n8934 , n8935 , n8936 , n8937 , n8938 , n8939 , n8940 ,
n8941 , n8942 , n8943 , n8944 , n8945 , n8946 , n8947 , n8948 , n8949 , n8950 ,
n8951 , n8952 , n8953 , n8954 , n8955 , n8956 , n8957 , n8958 , n8959 , n8960 ,
n8961 , n8962 , n8963 , n8964 , n8965 , n8966 , n8967 , n8968 , n8969 , n8970 ,
n8971 , n8972 , n8973 , n8974 , n8975 , n8976 , n8977 , n8978 , n8979 , n8980 ,
n8981 , n8982 , n8983 , n8984 , n8985 , n8986 , n8987 , n8988 , n8989 , n8990 ,
n8991 , n8992 , n8993 , n8994 , n8995 , n8996 , n8997 , n8998 , n8999 , n9000 ,
n9001 , n9002 , n9003 , n9004 , n9005 , n9006 , n9007 , n9008 , n9009 , n9010 ,
n9011 , n9012 , n9013 , n9014 , n9015 , n9016 , n9017 , n9018 , n9019 , n9020 ,
n9021 , n9022 , n9023 , n9024 , n9025 , n9026 , n9027 , n9028 , n9029 , n9030 ,
n9031 , n9032 , n9033 , n9034 , n9035 , n9036 , n9037 , n9038 , n9039 , n9040 ,
n9041 , n9042 , n9043 , n9044 , n9045 , n9046 , n9047 , n9048 , n9049 , n9050 ,
n9051 , n9052 , n9053 , n9054 , n9055 , n9056 , n9057 , n9058 , n9059 , n9060 ,
n9061 , n9062 , n9063 , n9064 , n9065 , n9066 , n9067 , n9068 , n9069 , n9070 ,
n9071 , n9072 , n9073 , n9074 , n9075 , n9076 , n9077 , n9078 , n9079 , n9080 ,
n9081 , n9082 , n9083 , n9084 , n9085 , n9086 , n9087 , n9088 , n9089 , n9090 ,
n9091 , n9092 , n9093 , n9094 , n9095 , n9096 , n9097 , n9098 , n9099 , n9100 ,
n9101 , n9102 , n9103 , n9104 , n9105 , n9106 , n9107 , n9108 , n9109 , n9110 ,
n9111 , n9112 , n9113 , n9114 , n9115 , n9116 , n9117 , n9118 , n9119 , n9120 ,
n9121 , n9122 , n9123 , n9124 , n9125 , n9126 , n9127 , n9128 , n9129 , n9130 ,
n9131 , n9132 , n9133 , n9134 , n9135 , n9136 , n9137 , n9138 , n9139 , n9140 ,
n9141 , n9142 , n9143 , n9144 , n9145 , n9146 , n9147 , n9148 , n9149 , n9150 ,
n9151 , n9152 , n9153 , n9154 , n9155 , n9156 , n9157 , n9158 , n9159 , n9160 ,
n9161 , n9162 , n9163 , n9164 , n9165 , n9166 , n9167 , n9168 , n9169 , n9170 ,
n9171 , n9172 , n9173 , n9174 , n9175 , n9176 , n9177 , n9178 , n9179 , n9180 ,
n9181 , n9182 , n9183 , n9184 , n9185 , n9186 , n9187 , n9188 , n9189 , n9190 ,
n9191 , n9192 , n9193 , n9194 , n9195 , n9196 , n9197 , n9198 , n9199 , n9200 ,
n9201 , n9202 , n9203 , n9204 , n9205 , n9206 , n9207 , n9208 , n9209 , n9210 ,
n9211 , n9212 , n9213 , n9214 , n9215 , n9216 , n9217 , n9218 , n9219 , n9220 ,
n9221 , n9222 , n9223 , n9224 , n9225 , n9226 , n9227 , n9228 , n9229 , n9230 ,
n9231 , n9232 , n9233 , n9234 , n9235 , n9236 , n9237 , n9238 , n9239 , n9240 ,
n9241 , n9242 , n9243 , n9244 , n9245 , n9246 , n9247 , n9248 , n9249 , n9250 ,
n9251 , n9252 , n9253 , n9254 , n9255 , n9256 , n9257 , n9258 , n9259 , n9260 ,
n9261 , n9262 , n9263 , n9264 , n9265 , n9266 , n9267 , n9268 , n9269 , n9270 ,
n9271 , n9272 , n9273 , n9274 , n9275 , n9276 , n9277 , n9278 , n9279 , n9280 ,
n9281 , n9282 , n9283 , n9284 , n9285 , n9286 , n9287 , n9288 , n9289 , n9290 ,
n9291 , n9292 , n9293 , n9294 , n9295 , n9296 , n9297 , n9298 , n9299 , n9300 ,
n9301 , n9302 , n9303 , n9304 , n9305 , n9306 , n9307 , n9308 , n9309 , n9310 ,
n9311 , n9312 , n9313 , n9314 , n9315 , n9316 , n9317 , n9318 , n9319 , n9320 ,
n9321 , n9322 , n9323 , n9324 , n9325 , n9326 , n9327 , n9328 , n9329 , n9330 ,
n9331 , n9332 , n9333 , n9334 , n9335 , n9336 , n9337 , n9338 , n9339 , n9340 ,
n9341 , n9342 , n9343 , n9344 , n9345 , n9346 , n9347 , n9348 , n9349 , n9350 ,
n9351 , n9352 , n9353 , n9354 , n9355 , n9356 , n9357 , n9358 , n9359 , n9360 ,
n9361 , n9362 , n9363 , n9364 , n9365 , n9366 , n9367 , n9368 , n9369 , n9370 ,
n9371 , n9372 , n9373 , n9374 , n9375 , n9376 , n9377 , n9378 , n9379 , n9380 ,
n9381 , n9382 , n9383 , n9384 , n9385 , n9386 , n9387 , n9388 , n9389 , n9390 ,
n9391 , n9392 , n9393 , n9394 , n9395 , n9396 , n9397 , n9398 , n9399 , n9400 ,
n9401 , n9402 , n9403 , n9404 , n9405 , n9406 , n9407 , n9408 , n9409 , n9410 ,
n9411 , n9412 , n9413 , n9414 , n9415 , n9416 , n9417 , n9418 , n9419 , n9420 ,
n9421 , n9422 , n9423 , n9424 , n9425 , n9426 , n9427 , n9428 , n9429 , n9430 ,
n9431 , n9432 , n9433 , n9434 , n9435 , n9436 , n9437 , n9438 , n9439 , n9440 ,
n9441 , n9442 , n9443 , n9444 , n9445 , n9446 , n9447 , n9448 , n9449 , n9450 ,
n9451 , n9452 , n9453 , n9454 , n9455 , n9456 , n9457 , n9458 , n9459 , n9460 ,
n9461 , n9462 , n9463 , n9464 , n9465 , n9466 , n9467 , n9468 , n9469 , n9470 ,
n9471 , n9472 , n9473 , n9474 , n9475 , n9476 , n9477 , n9478 , n9479 , n9480 ,
n9481 , n9482 , n9483 , n9484 , n9485 , n9486 , n9487 , n9488 , n9489 , n9490 ,
n9491 , n9492 , n9493 , n9494 , n9495 , n9496 , n9497 , n9498 , n9499 , n9500 ,
n9501 , n9502 , n9503 , n9504 , n9505 , n9506 , n9507 , n9508 , n9509 , n9510 ,
n9511 , n9512 , n9513 , n9514 , n9515 , n9516 , n9517 , n9518 , n9519 , n9520 ,
n9521 , n9522 , n9523 , n9524 , n9525 , n9526 , n9527 , n9528 , n9529 , n9530 ,
n9531 , n9532 , n9533 , n9534 , n9535 , n9536 , n9537 , n9538 , n9539 , n9540 ,
n9541 , n9542 , n9543 , n9544 , n9545 , n9546 , n9547 , n9548 , n9549 , n9550 ,
n9551 , n9552 , n9553 , n9554 , n9555 , n9556 , n9557 , n9558 , n9559 , n9560 ,
n9561 , n9562 , n9563 , n9564 , n9565 , n9566 , n9567 , n9568 , n9569 , n9570 ,
n9571 , n9572 , n9573 , n9574 , n9575 , n9576 , n9577 , n9578 , n9579 , n9580 ,
n9581 , n9582 , n9583 , n9584 , n9585 , n9586 , n9587 , n9588 , n9589 , n9590 ,
n9591 , n9592 , n9593 , n9594 , n9595 , n9596 , n9597 , n9598 , n9599 , n9600 ,
n9601 , n9602 , n9603 , n9604 , n9605 , n9606 , n9607 , n9608 , n9609 , n9610 ,
n9611 , n9612 , n9613 , n9614 , n9615 , n9616 , n9617 , n9618 , n9619 , n9620 ,
n9621 , n9622 , n9623 , n9624 , n9625 , n9626 , n9627 , n9628 , n9629 , n9630 ,
n9631 , n9632 , n9633 , n9634 , n9635 , n9636 , n9637 , n9638 , n9639 , n9640 ,
n9641 , n9642 , n9643 , n9644 , n9645 , n9646 , n9647 , n9648 , n9649 , n9650 ,
n9651 , n9652 , n9653 , n9654 , n9655 , n9656 , n9657 , n9658 , n9659 , n9660 ,
n9661 , n9662 , n9663 , n9664 , n9665 , n9666 , n9667 , n9668 , n9669 , n9670 ,
n9671 , n9672 , n9673 , n9674 , n9675 , n9676 , n9677 , n9678 , n9679 , n9680 ,
n9681 , n9682 , n9683 , n9684 , n9685 , n9686 , n9687 , n9688 , n9689 , n9690 ,
n9691 , n9692 , n9693 , n9694 , n9695 , n9696 , n9697 , n9698 , n9699 , n9700 ,
n9701 , n9702 , n9703 , n9704 , n9705 , n9706 , n9707 , n9708 , n9709 , n9710 ,
n9711 , n9712 , n9713 , n9714 , n9715 , n9716 , n9717 , n9718 , n9719 , n9720 ,
n9721 , n9722 , n9723 , n9724 , n9725 , n9726 , n9727 , n9728 , n9729 , n9730 ,
n9731 , n9732 , n9733 , n9734 , n9735 , n9736 , n9737 , n9738 , n9739 , n9740 ,
n9741 , n9742 , n9743 , n9744 , n9745 , n9746 , n9747 , n9748 , n9749 , n9750 ,
n9751 , n9752 , n9753 , n9754 , n9755 , n9756 , n9757 , n9758 , n9759 , n9760 ,
n9761 , n9762 , n9763 , n9764 , n9765 , n9766 , n9767 , n9768 , n9769 , n9770 ,
n9771 , n9772 , n9773 , n9774 , n9775 , n9776 , n9777 , n9778 , n9779 , n9780 ,
n9781 , n9782 , n9783 , n9784 , n9785 , n9786 , n9787 , n9788 , n9789 , n9790 ,
n9791 , n9792 , n9793 , n9794 , n9795 , n9796 , n9797 , n9798 , n9799 , n9800 ,
n9801 , n9802 , n9803 , n9804 , n9805 , n9806 , n9807 , n9808 , n9809 , n9810 ,
n9811 , n9812 , n9813 , n9814 , n9815 , n9816 , n9817 , n9818 , n9819 , n9820 ,
n9821 , n9822 , n9823 , n9824 , n9825 , n9826 , n9827 , n9828 , n9829 , n9830 ,
n9831 , n9832 , n9833 , n9834 , n9835 , n9836 , n9837 , n9838 , n9839 , n9840 ,
n9841 , n9842 , n9843 , n9844 , n9845 , n9846 , n9847 , n9848 , n9849 , n9850 ,
n9851 , n9852 , n9853 , n9854 , n9855 , n9856 , n9857 , n9858 , n9859 , n9860 ,
n9861 , n9862 , n9863 , n9864 , n9865 , n9866 , n9867 , n9868 , n9869 , n9870 ,
n9871 , n9872 , n9873 , n9874 , n9875 , n9876 , n9877 , n9878 , n9879 , n9880 ,
n9881 , n9882 , n9883 , n9884 , n9885 , n9886 , n9887 , n9888 , n9889 , n9890 ,
n9891 , n9892 , n9893 , n9894 , n9895 , n9896 , n9897 , n9898 , n9899 , n9900 ,
n9901 , n9902 , n9903 , n9904 , n9905 , n9906 , n9907 , n9908 , n9909 , n9910 ,
n9911 , n9912 , n9913 , n9914 , n9915 , n9916 , n9917 , n9918 , n9919 , n9920 ,
n9921 , n9922 , n9923 , n9924 , n9925 , n9926 , n9927 , n9928 , n9929 , n9930 ,
n9931 , n9932 , n9933 , n9934 , n9935 , n9936 , n9937 , n9938 , n9939 , n9940 ,
n9941 , n9942 , n9943 , n9944 , n9945 , n9946 , n9947 , n9948 , n9949 , n9950 ,
n9951 , n9952 , n9953 , n9954 , n9955 , n9956 , n9957 , n9958 , n9959 , n9960 ,
n9961 , n9962 , n9963 , n9964 , n9965 , n9966 , n9967 , n9968 , n9969 , n9970 ,
n9971 , n9972 , n9973 , n9974 , n9975 , n9976 , n9977 , n9978 , n9979 , n9980 ,
n9981 , n9982 , n9983 , n9984 , n9985 , n9986 , n9987 , n9988 , n9989 , n9990 ,
n9991 , n9992 , n9993 , n9994 , n9995 , n9996 , n9997 , n9998 , n9999 , n10000 ,
n10001 , n10002 , n10003 , n10004 , n10005 , n10006 , n10007 , n10008 , n10009 , n10010 ,
n10011 , n10012 , n10013 , n10014 , n10015 , n10016 , n10017 , n10018 , n10019 , n10020 ,
n10021 , n10022 , n10023 , n10024 , n10025 , n10026 , n10027 , n10028 , n10029 , n10030 ,
n10031 , n10032 , n10033 , n10034 , n10035 , n10036 , n10037 , n10038 , n10039 , n10040 ,
n10041 , n10042 , n10043 , n10044 , n10045 , n10046 , n10047 , n10048 , n10049 , n10050 ,
n10051 , n10052 , n10053 , n10054 , n10055 , n10056 , n10057 , n10058 , n10059 , n10060 ,
n10061 , n10062 , n10063 , n10064 , n10065 , n10066 , n10067 , n10068 , n10069 , n10070 ,
n10071 , n10072 , n10073 , n10074 , n10075 , n10076 , n10077 , n10078 , n10079 , n10080 ,
n10081 , n10082 , n10083 , n10084 , n10085 , n10086 , n10087 , n10088 , n10089 , n10090 ,
n10091 , n10092 , n10093 , n10094 , n10095 , n10096 , n10097 , n10098 , n10099 , n10100 ,
n10101 , n10102 , n10103 , n10104 , n10105 , n10106 , n10107 , n10108 , n10109 , n10110 ,
n10111 , n10112 , n10113 , n10114 , n10115 , n10116 , n10117 , n10118 , n10119 , n10120 ,
n10121 , n10122 , n10123 , n10124 , n10125 , n10126 , n10127 , n10128 , n10129 , n10130 ,
n10131 , n10132 , n10133 , n10134 , n10135 , n10136 , n10137 , n10138 , n10139 , n10140 ,
n10141 , n10142 , n10143 , n10144 , n10145 , n10146 , n10147 , n10148 , n10149 , n10150 ,
n10151 , n10152 , n10153 , n10154 , n10155 , n10156 , n10157 , n10158 , n10159 , n10160 ,
n10161 , n10162 , n10163 , n10164 , n10165 , n10166 , n10167 , n10168 , n10169 , n10170 ,
n10171 , n10172 , n10173 , n10174 , n10175 , n10176 , n10177 , n10178 , n10179 , n10180 ,
n10181 , n10182 , n10183 , n10184 , n10185 , n10186 , n10187 , n10188 , n10189 , n10190 ,
n10191 , n10192 , n10193 , n10194 , n10195 , n10196 , n10197 , n10198 , n10199 , n10200 ,
n10201 , n10202 , n10203 , n10204 , n10205 , n10206 , n10207 , n10208 , n10209 , n10210 ,
n10211 , n10212 , n10213 , n10214 , n10215 , n10216 , n10217 , n10218 , n10219 , n10220 ,
n10221 , n10222 , n10223 , n10224 , n10225 , n10226 , n10227 , n10228 , n10229 , n10230 ,
n10231 , n10232 , n10233 , n10234 , n10235 , n10236 , n10237 , n10238 , n10239 , n10240 ,
n10241 , n10242 , n10243 , n10244 , n10245 , n10246 , n10247 , n10248 , n10249 , n10250 ,
n10251 , n10252 , n10253 , n10254 , n10255 , n10256 , n10257 , n10258 , n10259 , n10260 ,
n10261 , n10262 , n10263 , n10264 , n10265 , n10266 , n10267 , n10268 , n10269 , n10270 ,
n10271 , n10272 , n10273 , n10274 , n10275 , n10276 , n10277 , n10278 , n10279 , n10280 ,
n10281 , n10282 , n10283 , n10284 , n10285 , n10286 , n10287 , n10288 , n10289 , n10290 ,
n10291 , n10292 , n10293 , n10294 , n10295 , n10296 , n10297 , n10298 , n10299 , n10300 ,
n10301 , n10302 , n10303 , n10304 , n10305 , n10306 , n10307 , n10308 , n10309 , n10310 ,
n10311 , n10312 , n10313 , n10314 , n10315 , n10316 , n10317 , n10318 , n10319 , n10320 ,
n10321 , n10322 , n10323 , n10324 , n10325 , n10326 , n10327 , n10328 , n10329 , n10330 ,
n10331 , n10332 , n10333 , n10334 , n10335 , n10336 , n10337 , n10338 , n10339 , n10340 ,
n10341 , n10342 , n10343 , n10344 , n10345 , n10346 , n10347 , n10348 , n10349 , n10350 ,
n10351 , n10352 , n10353 , n10354 , n10355 , n10356 , n10357 , n10358 , n10359 , n10360 ,
n10361 , n10362 , n10363 , n10364 , n10365 , n10366 , n10367 , n10368 , n10369 , n10370 ,
n10371 , n10372 , n10373 , n10374 , n10375 , n10376 , n10377 , n10378 , n10379 , n10380 ,
n10381 , n10382 , n10383 , n10384 , n10385 , n10386 , n10387 , n10388 , n10389 , n10390 ,
n10391 , n10392 , n10393 , n10394 , n10395 , n10396 , n10397 , n10398 , n10399 , n10400 ,
n10401 , n10402 , n10403 , n10404 , n10405 , n10406 , n10407 , n10408 , n10409 , n10410 ,
n10411 , n10412 , n10413 , n10414 , n10415 , n10416 , n10417 , n10418 , n10419 , n10420 ,
n10421 , n10422 , n10423 , n10424 , n10425 , n10426 , n10427 , n10428 , n10429 , n10430 ,
n10431 , n10432 , n10433 , n10434 , n10435 , n10436 , n10437 , n10438 , n10439 , n10440 ,
n10441 , n10442 , n10443 , n10444 , n10445 , n10446 , n10447 , n10448 , n10449 , n10450 ,
n10451 , n10452 , n10453 , n10454 , n10455 , n10456 , n10457 , n10458 , n10459 , n10460 ,
n10461 , n10462 , n10463 , n10464 , n10465 , n10466 , n10467 , n10468 , n10469 , n10470 ,
n10471 , n10472 , n10473 , n10474 , n10475 , n10476 , n10477 , n10478 , n10479 , n10480 ,
n10481 , n10482 , n10483 , n10484 , n10485 , n10486 , n10487 , n10488 , n10489 , n10490 ,
n10491 , n10492 , n10493 , n10494 , n10495 , n10496 , n10497 , n10498 , n10499 , n10500 ,
n10501 , n10502 , n10503 , n10504 , n10505 , n10506 , n10507 , n10508 , n10509 , n10510 ,
n10511 , n10512 , n10513 , n10514 , n10515 , n10516 , n10517 , n10518 , n10519 , n10520 ,
n10521 , n10522 , n10523 , n10524 , n10525 , n10526 , n10527 , n10528 , n10529 , n10530 ,
n10531 , n10532 , n10533 , n10534 , n10535 , n10536 , n10537 , n10538 , n10539 , n10540 ,
n10541 , n10542 , n10543 , n10544 , n10545 , n10546 , n10547 , n10548 , n10549 , n10550 ,
n10551 , n10552 , n10553 , n10554 , n10555 , n10556 , n10557 , n10558 , n10559 , n10560 ,
n10561 , n10562 , n10563 , n10564 , n10565 , n10566 , n10567 , n10568 , n10569 , n10570 ,
n10571 , n10572 , n10573 , n10574 , n10575 , n10576 , n10577 , n10578 , n10579 , n10580 ,
n10581 , n10582 , n10583 , n10584 , n10585 , n10586 , n10587 , n10588 , n10589 , n10590 ,
n10591 , n10592 , n10593 , n10594 , n10595 , n10596 , n10597 , n10598 , n10599 , n10600 ,
n10601 , n10602 , n10603 , n10604 , n10605 , n10606 , n10607 , n10608 , n10609 , n10610 ,
n10611 , n10612 , n10613 , n10614 , n10615 , n10616 , n10617 , n10618 , n10619 , n10620 ,
n10621 , n10622 , n10623 , n10624 , n10625 , n10626 , n10627 , n10628 , n10629 , n10630 ,
n10631 , n10632 , n10633 , n10634 , n10635 , n10636 , n10637 , n10638 , n10639 , n10640 ,
n10641 , n10642 , n10643 , n10644 , n10645 , n10646 , n10647 , n10648 , n10649 , n10650 ,
n10651 , n10652 , n10653 , n10654 , n10655 , n10656 , n10657 , n10658 , n10659 , n10660 ,
n10661 , n10662 , n10663 , n10664 , n10665 , n10666 , n10667 , n10668 , n10669 , n10670 ,
n10671 , n10672 , n10673 , n10674 , n10675 , n10676 , n10677 , n10678 , n10679 , n10680 ,
n10681 , n10682 , n10683 , n10684 , n10685 , n10686 , n10687 , n10688 , n10689 , n10690 ,
n10691 , n10692 , n10693 , n10694 , n10695 , n10696 , n10697 , n10698 , n10699 , n10700 ,
n10701 , n10702 , n10703 , n10704 , n10705 , n10706 , n10707 , n10708 , n10709 , n10710 ,
n10711 , n10712 , n10713 , n10714 , n10715 , n10716 , n10717 , n10718 , n10719 , n10720 ,
n10721 , n10722 , n10723 , n10724 , n10725 , n10726 , n10727 , n10728 , n10729 , n10730 ,
n10731 , n10732 , n10733 , n10734 , n10735 , n10736 , n10737 , n10738 , n10739 , n10740 ,
n10741 , n10742 , n10743 , n10744 , n10745 , n10746 , n10747 , n10748 , n10749 , n10750 ,
n10751 , n10752 , n10753 , n10754 , n10755 , n10756 , n10757 , n10758 , n10759 , n10760 ,
n10761 , n10762 , n10763 , n10764 , n10765 , n10766 , n10767 , n10768 , n10769 , n10770 ,
n10771 , n10772 , n10773 , n10774 , n10775 , n10776 , n10777 , n10778 , n10779 , n10780 ,
n10781 , n10782 , n10783 , n10784 , n10785 , n10786 , n10787 , n10788 , n10789 , n10790 ,
n10791 , n10792 , n10793 , n10794 , n10795 , n10796 , n10797 , n10798 , n10799 , n10800 ,
n10801 , n10802 , n10803 , n10804 , n10805 , n10806 , n10807 , n10808 , n10809 , n10810 ,
n10811 , n10812 , n10813 , n10814 , n10815 , n10816 , n10817 , n10818 , n10819 , n10820 ,
n10821 , n10822 , n10823 , n10824 , n10825 , n10826 , n10827 , n10828 , n10829 , n10830 ,
n10831 , n10832 , n10833 , n10834 , n10835 , n10836 , n10837 , n10838 , n10839 , n10840 ,
n10841 , n10842 , n10843 , n10844 , n10845 , n10846 , n10847 , n10848 , n10849 , n10850 ,
n10851 , n10852 , n10853 , n10854 , n10855 , n10856 , n10857 , n10858 , n10859 , n10860 ,
n10861 , n10862 , n10863 , n10864 , n10865 , n10866 , n10867 , n10868 , n10869 , n10870 ,
n10871 , n10872 , n10873 , n10874 , n10875 , n10876 , n10877 , n10878 , n10879 , n10880 ,
n10881 , n10882 , n10883 , n10884 , n10885 , n10886 , n10887 , n10888 , n10889 , n10890 ,
n10891 , n10892 , n10893 , n10894 , n10895 , n10896 , n10897 , n10898 , n10899 , n10900 ,
n10901 , n10902 , n10903 , n10904 , n10905 , n10906 , n10907 , n10908 , n10909 , n10910 ,
n10911 , n10912 , n10913 , n10914 , n10915 , n10916 , n10917 , n10918 , n10919 , n10920 ,
n10921 , n10922 , n10923 , n10924 , n10925 , n10926 , n10927 , n10928 , n10929 , n10930 ,
n10931 , n10932 , n10933 , n10934 , n10935 , n10936 , n10937 , n10938 , n10939 , n10940 ,
n10941 , n10942 , n10943 , n10944 , n10945 , n10946 , n10947 , n10948 , n10949 , n10950 ,
n10951 , n10952 , n10953 , n10954 , n10955 , n10956 , n10957 , n10958 , n10959 , n10960 ,
n10961 , n10962 , n10963 , n10964 , n10965 , n10966 , n10967 , n10968 , n10969 , n10970 ,
n10971 , n10972 , n10973 , n10974 , n10975 , n10976 , n10977 , n10978 , n10979 , n10980 ,
n10981 , n10982 , n10983 , n10984 , n10985 , n10986 , n10987 , n10988 , n10989 , n10990 ,
n10991 , n10992 , n10993 , n10994 , n10995 , n10996 , n10997 , n10998 , n10999 , n11000 ,
n11001 , n11002 , n11003 , n11004 , n11005 , n11006 , n11007 , n11008 , n11009 , n11010 ,
n11011 , n11012 , n11013 , n11014 , n11015 , n11016 , n11017 , n11018 , n11019 , n11020 ,
n11021 , n11022 , n11023 , n11024 , n11025 , n11026 , n11027 , n11028 , n11029 , n11030 ,
n11031 , n11032 , n11033 , n11034 , n11035 , n11036 , n11037 , n11038 , n11039 , n11040 ,
n11041 , n11042 , n11043 , n11044 , n11045 , n11046 , n11047 , n11048 , n11049 , n11050 ,
n11051 , n11052 , n11053 , n11054 , n11055 , n11056 , n11057 , n11058 , n11059 , n11060 ,
n11061 , n11062 , n11063 , n11064 , n11065 , n11066 , n11067 , n11068 , n11069 , n11070 ,
n11071 , n11072 , n11073 , n11074 , n11075 , n11076 , n11077 , n11078 , n11079 , n11080 ,
n11081 , n11082 , n11083 , n11084 , n11085 , n11086 , n11087 , n11088 , n11089 , n11090 ,
n11091 , n11092 , n11093 , n11094 , n11095 , n11096 , n11097 , n11098 , n11099 , n11100 ,
n11101 , n11102 , n11103 , n11104 , n11105 , n11106 , n11107 , n11108 , n11109 , n11110 ,
n11111 , n11112 , n11113 , n11114 , n11115 , n11116 , n11117 , n11118 , n11119 , n11120 ,
n11121 , n11122 , n11123 , n11124 , n11125 , n11126 , n11127 , n11128 , n11129 , n11130 ,
n11131 , n11132 , n11133 , n11134 , n11135 , n11136 , n11137 , n11138 , n11139 , n11140 ,
n11141 , n11142 , n11143 , n11144 , n11145 , n11146 , n11147 , n11148 , n11149 , n11150 ,
n11151 , n11152 , n11153 , n11154 , n11155 , n11156 , n11157 , n11158 , n11159 , n11160 ,
n11161 , n11162 , n11163 , n11164 , n11165 , n11166 , n11167 , n11168 , n11169 , n11170 ,
n11171 , n11172 , n11173 , n11174 , n11175 , n11176 , n11177 , n11178 , n11179 , n11180 ,
n11181 , n11182 , n11183 , n11184 , n11185 , n11186 , n11187 , n11188 , n11189 , n11190 ,
n11191 , n11192 , n11193 , n11194 , n11195 , n11196 , n11197 , n11198 , n11199 , n11200 ,
n11201 , n11202 , n11203 , n11204 , n11205 , n11206 , n11207 , n11208 , n11209 , n11210 ,
n11211 , n11212 , n11213 , n11214 , n11215 , n11216 , n11217 , n11218 , n11219 , n11220 ,
n11221 , n11222 , n11223 , n11224 , n11225 , n11226 , n11227 , n11228 , n11229 , n11230 ,
n11231 , n11232 , n11233 , n11234 , n11235 , n11236 , n11237 , n11238 , n11239 , n11240 ,
n11241 , n11242 , n11243 , n11244 , n11245 , n11246 , n11247 , n11248 , n11249 , n11250 ,
n11251 , n11252 , n11253 , n11254 , n11255 , n11256 , n11257 , n11258 , n11259 , n11260 ,
n11261 , n11262 , n11263 , n11264 , n11265 , n11266 , n11267 , n11268 , n11269 , n11270 ,
n11271 , n11272 , n11273 , n11274 , n11275 , n11276 , n11277 , n11278 , n11279 , n11280 ,
n11281 , n11282 , n11283 , n11284 , n11285 , n11286 , n11287 , n11288 , n11289 , n11290 ,
n11291 , n11292 , n11293 , n11294 , n11295 , n11296 , n11297 , n11298 , n11299 , n11300 ,
n11301 , n11302 , n11303 , n11304 , n11305 , n11306 , n11307 , n11308 , n11309 , n11310 ,
n11311 , n11312 , n11313 , n11314 , n11315 , n11316 , n11317 , n11318 , n11319 , n11320 ,
n11321 , n11322 , n11323 , n11324 , n11325 , n11326 , n11327 , n11328 , n11329 , n11330 ,
n11331 , n11332 , n11333 , n11334 , n11335 , n11336 , n11337 , n11338 , n11339 , n11340 ,
n11341 , n11342 , n11343 , n11344 , n11345 , n11346 , n11347 , n11348 , n11349 , n11350 ,
n11351 , n11352 , n11353 , n11354 , n11355 , n11356 , n11357 , n11358 , n11359 , n11360 ,
n11361 , n11362 , n11363 , n11364 , n11365 , n11366 , n11367 , n11368 , n11369 , n11370 ,
n11371 , n11372 , n11373 , n11374 , n11375 , n11376 , n11377 , n11378 , n11379 , n11380 ,
n11381 , n11382 , n11383 , n11384 , n11385 , n11386 , n11387 , n11388 , n11389 , n11390 ,
n11391 , n11392 , n11393 , n11394 , n11395 , n11396 , n11397 , n11398 , n11399 , n11400 ,
n11401 , n11402 , n11403 , n11404 , n11405 , n11406 , n11407 , n11408 , n11409 , n11410 ,
n11411 , n11412 , n11413 , n11414 , n11415 , n11416 , n11417 , n11418 , n11419 , n11420 ,
n11421 , n11422 , n11423 , n11424 , n11425 , n11426 , n11427 , n11428 , n11429 , n11430 ,
n11431 , n11432 , n11433 , n11434 , n11435 , n11436 , n11437 , n11438 , n11439 , n11440 ,
n11441 , n11442 , n11443 , n11444 , n11445 , n11446 , n11447 , n11448 , n11449 , n11450 ,
n11451 , n11452 , n11453 , n11454 , n11455 , n11456 , n11457 , n11458 , n11459 , n11460 ,
n11461 , n11462 , n11463 , n11464 , n11465 , n11466 , n11467 , n11468 , n11469 , n11470 ,
n11471 , n11472 , n11473 , n11474 , n11475 , n11476 , n11477 , n11478 , n11479 , n11480 ,
n11481 , n11482 , n11483 , n11484 , n11485 , n11486 , n11487 , n11488 , n11489 , n11490 ,
n11491 , n11492 , n11493 , n11494 , n11495 , n11496 , n11497 , n11498 , n11499 , n11500 ,
n11501 , n11502 , n11503 , n11504 , n11505 , n11506 , n11507 , n11508 , n11509 , n11510 ,
n11511 , n11512 , n11513 , n11514 , n11515 , n11516 , n11517 , n11518 , n11519 , n11520 ,
n11521 , n11522 , n11523 , n11524 , n11525 , n11526 , n11527 , n11528 , n11529 , n11530 ,
n11531 , n11532 , n11533 , n11534 , n11535 , n11536 , n11537 , n11538 , n11539 , n11540 ,
n11541 , n11542 , n11543 , n11544 , n11545 , n11546 , n11547 , n11548 , n11549 , n11550 ,
n11551 , n11552 , n11553 , n11554 , n11555 , n11556 , n11557 , n11558 , n11559 , n11560 ,
n11561 , n11562 , n11563 , n11564 , n11565 , n11566 , n11567 , n11568 , n11569 , n11570 ,
n11571 , n11572 , n11573 , n11574 , n11575 , n11576 , n11577 , n11578 , n11579 , n11580 ,
n11581 , n11582 , n11583 , n11584 , n11585 , n11586 , n11587 , n11588 , n11589 , n11590 ,
n11591 , n11592 , n11593 , n11594 , n11595 , n11596 , n11597 , n11598 , n11599 , n11600 ,
n11601 , n11602 , n11603 , n11604 , n11605 , n11606 , n11607 , n11608 , n11609 , n11610 ,
n11611 , n11612 , n11613 , n11614 , n11615 , n11616 , n11617 , n11618 , n11619 , n11620 ,
n11621 , n11622 , n11623 , n11624 , n11625 , n11626 , n11627 , n11628 , n11629 , n11630 ,
n11631 , n11632 , n11633 , n11634 , n11635 , n11636 , n11637 , n11638 , n11639 , n11640 ,
n11641 , n11642 , n11643 , n11644 , n11645 , n11646 , n11647 , n11648 , n11649 , n11650 ,
n11651 , n11652 , n11653 , n11654 , n11655 , n11656 , n11657 , n11658 , n11659 , n11660 ,
n11661 , n11662 , n11663 , n11664 , n11665 , n11666 , n11667 , n11668 , n11669 , n11670 ,
n11671 , n11672 , n11673 , n11674 , n11675 , n11676 , n11677 , n11678 , n11679 , n11680 ,
n11681 , n11682 , n11683 , n11684 , n11685 , n11686 , n11687 , n11688 , n11689 , n11690 ,
n11691 , n11692 , n11693 , n11694 , n11695 , n11696 , n11697 , n11698 , n11699 , n11700 ,
n11701 , n11702 , n11703 , n11704 , n11705 , n11706 , n11707 , n11708 , n11709 , n11710 ,
n11711 , n11712 , n11713 , n11714 , n11715 , n11716 , n11717 , n11718 , n11719 , n11720 ,
n11721 , n11722 , n11723 , n11724 , n11725 , n11726 , n11727 , n11728 , n11729 , n11730 ,
n11731 , n11732 , n11733 , n11734 , n11735 , n11736 , n11737 , n11738 , n11739 , n11740 ,
n11741 , n11742 , n11743 , n11744 , n11745 , n11746 , n11747 , n11748 , n11749 , n11750 ,
n11751 , n11752 , n11753 , n11754 , n11755 , n11756 , n11757 , n11758 , n11759 , n11760 ,
n11761 , n11762 , n11763 , n11764 , n11765 , n11766 , n11767 , n11768 , n11769 , n11770 ,
n11771 , n11772 , n11773 , n11774 , n11775 , n11776 , n11777 , n11778 , n11779 , n11780 ,
n11781 , n11782 , n11783 , n11784 , n11785 , n11786 , n11787 , n11788 , n11789 , n11790 ,
n11791 , n11792 , n11793 , n11794 , n11795 , n11796 , n11797 , n11798 , n11799 , n11800 ,
n11801 , n11802 , n11803 , n11804 , n11805 , n11806 , n11807 , n11808 , n11809 , n11810 ,
n11811 , n11812 , n11813 , n11814 , n11815 , n11816 , n11817 , n11818 , n11819 , n11820 ,
n11821 , n11822 , n11823 , n11824 , n11825 , n11826 , n11827 , n11828 , n11829 , n11830 ,
n11831 , n11832 , n11833 , n11834 , n11835 , n11836 , n11837 , n11838 , n11839 , n11840 ,
n11841 , n11842 , n11843 , n11844 , n11845 , n11846 , n11847 , n11848 , n11849 , n11850 ,
n11851 , n11852 , n11853 , n11854 , n11855 , n11856 , n11857 , n11858 , n11859 , n11860 ,
n11861 , n11862 , n11863 , n11864 , n11865 , n11866 , n11867 , n11868 , n11869 , n11870 ,
n11871 , n11872 , n11873 , n11874 , n11875 , n11876 , n11877 , n11878 , n11879 , n11880 ,
n11881 , n11882 , n11883 , n11884 , n11885 , n11886 , n11887 , n11888 , n11889 , n11890 ,
n11891 , n11892 , n11893 , n11894 , n11895 , n11896 , n11897 , n11898 , n11899 , n11900 ,
n11901 , n11902 , n11903 , n11904 , n11905 , n11906 , n11907 , n11908 , n11909 , n11910 ,
n11911 , n11912 , n11913 , n11914 , n11915 , n11916 , n11917 , n11918 , n11919 , n11920 ,
n11921 , n11922 , n11923 , n11924 , n11925 , n11926 , n11927 , n11928 , n11929 , n11930 ,
n11931 , n11932 , n11933 , n11934 , n11935 , n11936 , n11937 , n11938 , n11939 , n11940 ,
n11941 , n11942 , n11943 , n11944 , n11945 , n11946 , n11947 , n11948 , n11949 , n11950 ,
n11951 , n11952 , n11953 , n11954 , n11955 , n11956 , n11957 , n11958 , n11959 , n11960 ,
n11961 , n11962 , n11963 , n11964 , n11965 , n11966 , n11967 , n11968 , n11969 , n11970 ,
n11971 , n11972 , n11973 , n11974 , n11975 , n11976 , n11977 , n11978 , n11979 , n11980 ,
n11981 , n11982 , n11983 , n11984 , n11985 , n11986 , n11987 , n11988 , n11989 , n11990 ,
n11991 , n11992 , n11993 , n11994 , n11995 , n11996 , n11997 , n11998 , n11999 , n12000 ,
n12001 , n12002 , n12003 , n12004 , n12005 , n12006 , n12007 , n12008 , n12009 , n12010 ,
n12011 , n12012 , n12013 , n12014 , n12015 , n12016 , n12017 , n12018 , n12019 , n12020 ,
n12021 , n12022 , n12023 , n12024 , n12025 , n12026 , n12027 , n12028 , n12029 , n12030 ,
n12031 , n12032 , n12033 , n12034 , n12035 , n12036 , n12037 , n12038 , n12039 , n12040 ,
n12041 , n12042 , n12043 , n12044 , n12045 , n12046 , n12047 , n12048 , n12049 , n12050 ,
n12051 , n12052 , n12053 , n12054 , n12055 , n12056 , n12057 , n12058 , n12059 , n12060 ,
n12061 , n12062 , n12063 , n12064 , n12065 , n12066 , n12067 , n12068 , n12069 , n12070 ,
n12071 , n12072 , n12073 , n12074 , n12075 , n12076 , n12077 , n12078 , n12079 , n12080 ,
n12081 , n12082 , n12083 , n12084 , n12085 , n12086 , n12087 , n12088 , n12089 , n12090 ,
n12091 , n12092 , n12093 , n12094 , n12095 , n12096 , n12097 , n12098 , n12099 , n12100 ,
n12101 , n12102 , n12103 , n12104 , n12105 , n12106 , n12107 , n12108 , n12109 , n12110 ,
n12111 , n12112 , n12113 , n12114 , n12115 , n12116 , n12117 , n12118 , n12119 , n12120 ,
n12121 , n12122 , n12123 , n12124 , n12125 , n12126 , n12127 , n12128 , n12129 , n12130 ,
n12131 , n12132 , n12133 , n12134 , n12135 , n12136 , n12137 , n12138 , n12139 , n12140 ,
n12141 , n12142 , n12143 , n12144 , n12145 , n12146 , n12147 , n12148 , n12149 , n12150 ,
n12151 , n12152 , n12153 , n12154 , n12155 , n12156 , n12157 , n12158 , n12159 , n12160 ,
n12161 , n12162 , n12163 , n12164 , n12165 , n12166 , n12167 , n12168 , n12169 , n12170 ,
n12171 , n12172 , n12173 , n12174 , n12175 , n12176 , n12177 , n12178 , n12179 , n12180 ,
n12181 , n12182 , n12183 , n12184 , n12185 , n12186 , n12187 , n12188 , n12189 , n12190 ,
n12191 , n12192 , n12193 , n12194 , n12195 , n12196 , n12197 , n12198 , n12199 , n12200 ,
n12201 , n12202 , n12203 , n12204 , n12205 , n12206 , n12207 , n12208 , n12209 , n12210 ,
n12211 , n12212 , n12213 , n12214 , n12215 , n12216 , n12217 , n12218 , n12219 , n12220 ,
n12221 , n12222 , n12223 , n12224 , n12225 , n12226 , n12227 , n12228 , n12229 , n12230 ,
n12231 , n12232 , n12233 , n12234 , n12235 , n12236 , n12237 , n12238 , n12239 , n12240 ,
n12241 , n12242 , n12243 , n12244 , n12245 , n12246 , n12247 , n12248 , n12249 , n12250 ,
n12251 , n12252 , n12253 , n12254 , n12255 , n12256 , n12257 , n12258 , n12259 , n12260 ,
n12261 , n12262 , n12263 , n12264 , n12265 , n12266 , n12267 , n12268 , n12269 , n12270 ,
n12271 , n12272 , n12273 , n12274 , n12275 , n12276 , n12277 , n12278 , n12279 , n12280 ,
n12281 , n12282 , n12283 , n12284 , n12285 , n12286 , n12287 , n12288 , n12289 , n12290 ,
n12291 , n12292 , n12293 , n12294 , n12295 , n12296 , n12297 , n12298 , n12299 , n12300 ,
n12301 , n12302 , n12303 , n12304 , n12305 , n12306 , n12307 , n12308 , n12309 , n12310 ,
n12311 , n12312 , n12313 , n12314 , n12315 , n12316 , n12317 , n12318 , n12319 , n12320 ,
n12321 , n12322 , n12323 , n12324 , n12325 , n12326 , n12327 , n12328 , n12329 , n12330 ,
n12331 , n12332 , n12333 , n12334 , n12335 , n12336 , n12337 , n12338 , n12339 , n12340 ,
n12341 , n12342 , n12343 , n12344 , n12345 , n12346 , n12347 , n12348 , n12349 , n12350 ,
n12351 , n12352 , n12353 , n12354 , n12355 , n12356 , n12357 , n12358 , n12359 , n12360 ,
n12361 , n12362 , n12363 , n12364 , n12365 , n12366 , n12367 , n12368 , n12369 , n12370 ,
n12371 , n12372 , n12373 , n12374 , n12375 , n12376 , n12377 , n12378 , n12379 , n12380 ,
n12381 , n12382 , n12383 , n12384 , n12385 , n12386 , n12387 , n12388 , n12389 , n12390 ,
n12391 , n12392 , n12393 , n12394 , n12395 , n12396 , n12397 , n12398 , n12399 , n12400 ,
n12401 , n12402 , n12403 , n12404 , n12405 , n12406 , n12407 , n12408 , n12409 , n12410 ,
n12411 , n12412 , n12413 , n12414 , n12415 , n12416 , n12417 , n12418 , n12419 , n12420 ,
n12421 , n12422 , n12423 , n12424 , n12425 , n12426 , n12427 , n12428 , n12429 , n12430 ,
n12431 , n12432 , n12433 , n12434 , n12435 , n12436 , n12437 , n12438 , n12439 , n12440 ,
n12441 , n12442 , n12443 , n12444 , n12445 , n12446 , n12447 , n12448 , n12449 , n12450 ,
n12451 , n12452 , n12453 , n12454 , n12455 , n12456 , n12457 , n12458 , n12459 , n12460 ,
n12461 , n12462 , n12463 , n12464 , n12465 , n12466 , n12467 , n12468 , n12469 , n12470 ,
n12471 , n12472 , n12473 , n12474 , n12475 , n12476 , n12477 , n12478 , n12479 , n12480 ,
n12481 , n12482 , n12483 , n12484 , n12485 , n12486 , n12487 , n12488 , n12489 , n12490 ,
n12491 , n12492 , n12493 , n12494 , n12495 , n12496 , n12497 , n12498 , n12499 , n12500 ,
n12501 , n12502 , n12503 , n12504 , n12505 , n12506 , n12507 , n12508 , n12509 , n12510 ,
n12511 , n12512 , n12513 , n12514 , n12515 , n12516 , n12517 , n12518 , n12519 , n12520 ,
n12521 , n12522 , n12523 , n12524 , n12525 , n12526 , n12527 , n12528 , n12529 , n12530 ,
n12531 , n12532 , n12533 , n12534 , n12535 , n12536 , n12537 , n12538 , n12539 , n12540 ,
n12541 , n12542 , n12543 , n12544 , n12545 , n12546 , n12547 , n12548 , n12549 , n12550 ,
n12551 , n12552 , n12553 , n12554 , n12555 , n12556 , n12557 , n12558 , n12559 , n12560 ,
n12561 , n12562 , n12563 , n12564 , n12565 , n12566 , n12567 , n12568 , n12569 , n12570 ,
n12571 , n12572 , n12573 , n12574 , n12575 , n12576 , n12577 , n12578 , n12579 , n12580 ,
n12581 , n12582 , n12583 , n12584 , n12585 , n12586 , n12587 , n12588 , n12589 , n12590 ,
n12591 , n12592 , n12593 , n12594 , n12595 , n12596 , n12597 , n12598 , n12599 , n12600 ,
n12601 , n12602 , n12603 , n12604 , n12605 , n12606 , n12607 , n12608 , n12609 , n12610 ,
n12611 , n12612 , n12613 , n12614 , n12615 , n12616 , n12617 , n12618 , n12619 , n12620 ,
n12621 , n12622 , n12623 , n12624 , n12625 , n12626 , n12627 , n12628 , n12629 , n12630 ,
n12631 , n12632 , n12633 , n12634 , n12635 , n12636 , n12637 , n12638 , n12639 , n12640 ,
n12641 , n12642 , n12643 , n12644 , n12645 , n12646 , n12647 , n12648 , n12649 , n12650 ,
n12651 , n12652 , n12653 , n12654 , n12655 , n12656 , n12657 , n12658 , n12659 , n12660 ,
n12661 , n12662 , n12663 , n12664 , n12665 , n12666 , n12667 , n12668 , n12669 , n12670 ,
n12671 , n12672 , n12673 , n12674 , n12675 , n12676 , n12677 , n12678 , n12679 , n12680 ,
n12681 , n12682 , n12683 , n12684 , n12685 , n12686 , n12687 , n12688 , n12689 , n12690 ,
n12691 , n12692 , n12693 , n12694 , n12695 , n12696 , n12697 , n12698 , n12699 , n12700 ,
n12701 , n12702 , n12703 , n12704 , n12705 , n12706 , n12707 , n12708 , n12709 , n12710 ,
n12711 , n12712 , n12713 , n12714 , n12715 , n12716 , n12717 , n12718 , n12719 , n12720 ,
n12721 , n12722 , n12723 , n12724 , n12725 , n12726 , n12727 , n12728 , n12729 , n12730 ,
n12731 , n12732 , n12733 , n12734 , n12735 , n12736 , n12737 , n12738 , n12739 , n12740 ,
n12741 , n12742 , n12743 , n12744 , n12745 , n12746 , n12747 , n12748 , n12749 , n12750 ,
n12751 , n12752 , n12753 , n12754 , n12755 , n12756 , n12757 , n12758 , n12759 , n12760 ,
n12761 , n12762 , n12763 , n12764 , n12765 , n12766 , n12767 , n12768 , n12769 , n12770 ,
n12771 , n12772 , n12773 , n12774 , n12775 , n12776 , n12777 , n12778 , n12779 , n12780 ,
n12781 , n12782 , n12783 , n12784 , n12785 , n12786 , n12787 , n12788 , n12789 , n12790 ,
n12791 , n12792 , n12793 , n12794 , n12795 , n12796 , n12797 , n12798 , n12799 , n12800 ,
n12801 , n12802 , n12803 , n12804 , n12805 , n12806 , n12807 , n12808 , n12809 , n12810 ,
n12811 , n12812 , n12813 , n12814 , n12815 , n12816 , n12817 , n12818 , n12819 , n12820 ,
n12821 , n12822 , n12823 , n12824 , n12825 , n12826 , n12827 , n12828 , n12829 , n12830 ,
n12831 , n12832 , n12833 , n12834 , n12835 , n12836 , n12837 , n12838 , n12839 , n12840 ,
n12841 , n12842 , n12843 , n12844 , n12845 , n12846 , n12847 , n12848 , n12849 , n12850 ,
n12851 , n12852 , n12853 , n12854 , n12855 , n12856 , n12857 , n12858 , n12859 , n12860 ,
n12861 , n12862 , n12863 , n12864 , n12865 , n12866 , n12867 , n12868 , n12869 , n12870 ,
n12871 , n12872 , n12873 , n12874 , n12875 , n12876 , n12877 , n12878 , n12879 , n12880 ,
n12881 , n12882 , n12883 , n12884 , n12885 , n12886 , n12887 , n12888 , n12889 , n12890 ,
n12891 , n12892 , n12893 , n12894 , n12895 , n12896 , n12897 , n12898 , n12899 , n12900 ,
n12901 , n12902 , n12903 , n12904 , n12905 , n12906 , n12907 , n12908 , n12909 , n12910 ,
n12911 , n12912 , n12913 , n12914 , n12915 , n12916 , n12917 , n12918 , n12919 , n12920 ,
n12921 , n12922 , n12923 , n12924 , n12925 , n12926 , n12927 , n12928 , n12929 , n12930 ,
n12931 , n12932 , n12933 , n12934 , n12935 , n12936 , n12937 , n12938 , n12939 , n12940 ,
n12941 , n12942 , n12943 , n12944 , n12945 , n12946 , n12947 , n12948 , n12949 , n12950 ,
n12951 , n12952 , n12953 , n12954 , n12955 , n12956 , n12957 , n12958 , n12959 , n12960 ,
n12961 , n12962 , n12963 , n12964 , n12965 , n12966 , n12967 , n12968 , n12969 , n12970 ,
n12971 , n12972 , n12973 , n12974 , n12975 , n12976 , n12977 , n12978 , n12979 , n12980 ,
n12981 , n12982 , n12983 , n12984 , n12985 , n12986 , n12987 , n12988 , n12989 , n12990 ,
n12991 , n12992 , n12993 , n12994 , n12995 , n12996 , n12997 , n12998 , n12999 , n13000 ,
n13001 , n13002 , n13003 , n13004 , n13005 , n13006 , n13007 , n13008 , n13009 , n13010 ,
n13011 , n13012 , n13013 , n13014 , n13015 , n13016 , n13017 , n13018 , n13019 , n13020 ,
n13021 , n13022 , n13023 , n13024 , n13025 , n13026 , n13027 , n13028 , n13029 , n13030 ,
n13031 , n13032 , n13033 , n13034 , n13035 , n13036 , n13037 , n13038 , n13039 , n13040 ,
n13041 , n13042 , n13043 , n13044 , n13045 , n13046 , n13047 , n13048 , n13049 , n13050 ,
n13051 , n13052 , n13053 , n13054 , n13055 , n13056 , n13057 , n13058 , n13059 , n13060 ,
n13061 , n13062 , n13063 , n13064 , n13065 , n13066 , n13067 , n13068 , n13069 , n13070 ,
n13071 , n13072 , n13073 , n13074 , n13075 , n13076 , n13077 , n13078 , n13079 , n13080 ,
n13081 , n13082 , n13083 , n13084 , n13085 , n13086 , n13087 , n13088 , n13089 , n13090 ,
n13091 , n13092 , n13093 , n13094 , n13095 , n13096 , n13097 , n13098 , n13099 , n13100 ,
n13101 , n13102 , n13103 , n13104 , n13105 , n13106 , n13107 , n13108 , n13109 , n13110 ,
n13111 , n13112 , n13113 , n13114 , n13115 , n13116 , n13117 , n13118 , n13119 , n13120 ,
n13121 , n13122 , n13123 , n13124 , n13125 , n13126 , n13127 , n13128 , n13129 , n13130 ,
n13131 , n13132 , n13133 , n13134 , n13135 , n13136 , n13137 , n13138 , n13139 , n13140 ,
n13141 , n13142 , n13143 , n13144 , n13145 , n13146 , n13147 , n13148 , n13149 , n13150 ,
n13151 , n13152 , n13153 , n13154 , n13155 , n13156 , n13157 , n13158 , n13159 , n13160 ,
n13161 , n13162 , n13163 , n13164 , n13165 , n13166 , n13167 , n13168 , n13169 , n13170 ,
n13171 , n13172 , n13173 , n13174 , n13175 , n13176 , n13177 , n13178 , n13179 , n13180 ,
n13181 , n13182 , n13183 , n13184 , n13185 , n13186 , n13187 , n13188 , n13189 , n13190 ,
n13191 , n13192 , n13193 , n13194 , n13195 , n13196 , n13197 , n13198 , n13199 , n13200 ,
n13201 , n13202 , n13203 , n13204 , n13205 , n13206 , n13207 , n13208 , n13209 , n13210 ,
n13211 , n13212 , n13213 , n13214 , n13215 , n13216 , n13217 , n13218 , n13219 , n13220 ,
n13221 , n13222 , n13223 , n13224 , n13225 , n13226 , n13227 , n13228 , n13229 , n13230 ,
n13231 , n13232 , n13233 , n13234 , n13235 , n13236 , n13237 , n13238 , n13239 , n13240 ,
n13241 , n13242 , n13243 , n13244 , n13245 , n13246 , n13247 , n13248 , n13249 , n13250 ,
n13251 , n13252 , n13253 , n13254 , n13255 , n13256 , n13257 , n13258 , n13259 , n13260 ,
n13261 , n13262 , n13263 , n13264 , n13265 , n13266 , n13267 , n13268 , n13269 , n13270 ,
n13271 , n13272 , n13273 , n13274 , n13275 , n13276 , n13277 , n13278 , n13279 , n13280 ,
n13281 , n13282 , n13283 , n13284 , n13285 , n13286 , n13287 , n13288 , n13289 , n13290 ,
n13291 , n13292 , n13293 , n13294 , n13295 , n13296 , n13297 , n13298 , n13299 , n13300 ,
n13301 , n13302 , n13303 , n13304 , n13305 , n13306 , n13307 , n13308 , n13309 , n13310 ,
n13311 , n13312 , n13313 , n13314 , n13315 , n13316 , n13317 , n13318 , n13319 , n13320 ,
n13321 , n13322 , n13323 , n13324 , n13325 , n13326 , n13327 , n13328 , n13329 , n13330 ,
n13331 , n13332 , n13333 , n13334 , n13335 , n13336 , n13337 , n13338 , n13339 , n13340 ,
n13341 , n13342 , n13343 , n13344 , n13345 , n13346 , n13347 , n13348 , n13349 , n13350 ,
n13351 , n13352 , n13353 , n13354 , n13355 , n13356 , n13357 , n13358 , n13359 , n13360 ,
n13361 , n13362 , n13363 , n13364 , n13365 , n13366 , n13367 , n13368 , n13369 , n13370 ,
n13371 , n13372 , n13373 , n13374 , n13375 , n13376 , n13377 , n13378 , n13379 , n13380 ,
n13381 , n13382 , n13383 , n13384 , n13385 , n13386 , n13387 , n13388 , n13389 , n13390 ,
n13391 , n13392 , n13393 , n13394 , n13395 , n13396 , n13397 , n13398 , n13399 , n13400 ,
n13401 , n13402 , n13403 , n13404 , n13405 , n13406 , n13407 , n13408 , n13409 , n13410 ,
n13411 , n13412 , n13413 , n13414 , n13415 , n13416 , n13417 , n13418 , n13419 , n13420 ,
n13421 , n13422 , n13423 , n13424 , n13425 , n13426 , n13427 , n13428 , n13429 , n13430 ,
n13431 , n13432 , n13433 , n13434 , n13435 , n13436 , n13437 , n13438 , n13439 , n13440 ,
n13441 , n13442 , n13443 , n13444 , n13445 , n13446 , n13447 , n13448 , n13449 , n13450 ,
n13451 , n13452 , n13453 , n13454 , n13455 , n13456 , n13457 , n13458 , n13459 , n13460 ,
n13461 , n13462 , n13463 , n13464 , n13465 , n13466 , n13467 , n13468 , n13469 , n13470 ,
n13471 , n13472 , n13473 , n13474 , n13475 , n13476 , n13477 , n13478 , n13479 , n13480 ,
n13481 , n13482 , n13483 , n13484 , n13485 , n13486 , n13487 , n13488 , n13489 , n13490 ,
n13491 , n13492 , n13493 , n13494 , n13495 , n13496 , n13497 , n13498 , n13499 , n13500 ,
n13501 , n13502 , n13503 , n13504 , n13505 , n13506 , n13507 , n13508 , n13509 , n13510 ,
n13511 , n13512 , n13513 , n13514 , n13515 , n13516 , n13517 , n13518 , n13519 , n13520 ,
n13521 , n13522 , n13523 , n13524 , n13525 , n13526 , n13527 , n13528 , n13529 , n13530 ,
n13531 , n13532 , n13533 , n13534 , n13535 , n13536 , n13537 , n13538 , n13539 , n13540 ,
n13541 , n13542 , n13543 , n13544 , n13545 , n13546 , n13547 , n13548 , n13549 , n13550 ,
n13551 , n13552 , n13553 , n13554 , n13555 , n13556 , n13557 , n13558 , n13559 , n13560 ,
n13561 , n13562 , n13563 , n13564 , n13565 , n13566 , n13567 , n13568 , n13569 , n13570 ,
n13571 , n13572 , n13573 , n13574 , n13575 , n13576 , n13577 , n13578 , n13579 , n13580 ,
n13581 , n13582 , n13583 , n13584 , n13585 , n13586 , n13587 , n13588 , n13589 , n13590 ,
n13591 , n13592 , n13593 , n13594 , n13595 , n13596 , n13597 , n13598 , n13599 , n13600 ,
n13601 , n13602 , n13603 , n13604 , n13605 , n13606 , n13607 , n13608 , n13609 , n13610 ,
n13611 , n13612 , n13613 , n13614 , n13615 , n13616 , n13617 , n13618 , n13619 , n13620 ,
n13621 , n13622 , n13623 , n13624 , n13625 , n13626 , n13627 , n13628 , n13629 , n13630 ,
n13631 , n13632 , n13633 , n13634 , n13635 , n13636 , n13637 , n13638 , n13639 , n13640 ,
n13641 , n13642 , n13643 , n13644 , n13645 , n13646 , n13647 , n13648 , n13649 , n13650 ,
n13651 , n13652 , n13653 , n13654 , n13655 , n13656 , n13657 , n13658 , n13659 , n13660 ,
n13661 , n13662 , n13663 , n13664 , n13665 , n13666 , n13667 , n13668 , n13669 , n13670 ,
n13671 , n13672 , n13673 , n13674 , n13675 , n13676 , n13677 , n13678 , n13679 , n13680 ,
n13681 , n13682 , n13683 , n13684 , n13685 , n13686 , n13687 , n13688 , n13689 , n13690 ,
n13691 , n13692 , n13693 , n13694 , n13695 , n13696 , n13697 , n13698 , n13699 , n13700 ,
n13701 , n13702 , n13703 , n13704 , n13705 , n13706 , n13707 , n13708 , n13709 , n13710 ,
n13711 , n13712 , n13713 , n13714 , n13715 , n13716 , n13717 , n13718 , n13719 , n13720 ,
n13721 , n13722 , n13723 , n13724 , n13725 , n13726 , n13727 , n13728 , n13729 , n13730 ,
n13731 , n13732 , n13733 , n13734 , n13735 , n13736 , n13737 , n13738 , n13739 , n13740 ,
n13741 , n13742 , n13743 , n13744 , n13745 , n13746 , n13747 , n13748 , n13749 , n13750 ,
n13751 , n13752 , n13753 , n13754 , n13755 , n13756 , n13757 , n13758 , n13759 , n13760 ,
n13761 , n13762 , n13763 , n13764 , n13765 , n13766 , n13767 , n13768 , n13769 , n13770 ,
n13771 , n13772 , n13773 , n13774 , n13775 , n13776 , n13777 , n13778 , n13779 , n13780 ,
n13781 , n13782 , n13783 , n13784 , n13785 , n13786 , n13787 , n13788 , n13789 , n13790 ,
n13791 , n13792 , n13793 , n13794 , n13795 , n13796 , n13797 , n13798 , n13799 , n13800 ,
n13801 , n13802 , n13803 , n13804 , n13805 , n13806 , n13807 , n13808 , n13809 , n13810 ,
n13811 , n13812 , n13813 , n13814 , n13815 , n13816 , n13817 , n13818 , n13819 , n13820 ,
n13821 , n13822 , n13823 , n13824 , n13825 , n13826 , n13827 , n13828 , n13829 , n13830 ,
n13831 , n13832 , n13833 , n13834 , n13835 , n13836 , n13837 , n13838 , n13839 , n13840 ,
n13841 , n13842 , n13843 , n13844 , n13845 , n13846 , n13847 , n13848 , n13849 , n13850 ,
n13851 , n13852 , n13853 , n13854 , n13855 , n13856 , n13857 , n13858 , n13859 , n13860 ,
n13861 , n13862 , n13863 , n13864 , n13865 , n13866 , n13867 , n13868 , n13869 , n13870 ,
n13871 , n13872 , n13873 , n13874 , n13875 , n13876 , n13877 , n13878 , n13879 , n13880 ,
n13881 , n13882 , n13883 , n13884 , n13885 , n13886 , n13887 , n13888 , n13889 , n13890 ,
n13891 , n13892 , n13893 , n13894 , n13895 , n13896 , n13897 , n13898 , n13899 , n13900 ,
n13901 , n13902 , n13903 , n13904 , n13905 , n13906 , n13907 , n13908 , n13909 , n13910 ,
n13911 , n13912 , n13913 , n13914 , n13915 , n13916 , n13917 , n13918 , n13919 , n13920 ,
n13921 , n13922 , n13923 , n13924 , n13925 , n13926 , n13927 , n13928 , n13929 , n13930 ,
n13931 , n13932 , n13933 , n13934 , n13935 , n13936 , n13937 , n13938 , n13939 , n13940 ,
n13941 , n13942 , n13943 , n13944 , n13945 , n13946 , n13947 , n13948 , n13949 , n13950 ,
n13951 , n13952 , n13953 , n13954 , n13955 , n13956 , n13957 , n13958 , n13959 , n13960 ,
n13961 , n13962 , n13963 , n13964 , n13965 , n13966 , n13967 , n13968 , n13969 , n13970 ,
n13971 , n13972 , n13973 , n13974 , n13975 , n13976 , n13977 , n13978 , n13979 , n13980 ,
n13981 , n13982 , n13983 , n13984 , n13985 , n13986 , n13987 , n13988 , n13989 , n13990 ,
n13991 , n13992 , n13993 , n13994 , n13995 , n13996 , n13997 , n13998 , n13999 , n14000 ,
n14001 , n14002 , n14003 , n14004 , n14005 , n14006 , n14007 , n14008 , n14009 , n14010 ,
n14011 , n14012 , n14013 , n14014 , n14015 , n14016 , n14017 , n14018 , n14019 , n14020 ,
n14021 , n14022 , n14023 , n14024 , n14025 , n14026 , n14027 , n14028 , n14029 , n14030 ,
n14031 , n14032 , n14033 , n14034 , n14035 , n14036 , n14037 , n14038 , n14039 , n14040 ,
n14041 , n14042 , n14043 , n14044 , n14045 , n14046 , n14047 , n14048 , n14049 , n14050 ,
n14051 , n14052 , n14053 , n14054 , n14055 , n14056 , n14057 , n14058 , n14059 , n14060 ,
n14061 , n14062 , n14063 , n14064 , n14065 , n14066 , n14067 , n14068 , n14069 , n14070 ,
n14071 , n14072 , n14073 , n14074 , n14075 , n14076 , n14077 , n14078 , n14079 , n14080 ,
n14081 , n14082 , n14083 , n14084 , n14085 , n14086 , n14087 , n14088 , n14089 , n14090 ,
n14091 , n14092 , n14093 , n14094 , n14095 , n14096 , n14097 , n14098 , n14099 , n14100 ,
n14101 , n14102 , n14103 , n14104 , n14105 , n14106 , n14107 , n14108 , n14109 , n14110 ,
n14111 , n14112 , n14113 , n14114 , n14115 , n14116 , n14117 , n14118 , n14119 , n14120 ,
n14121 , n14122 , n14123 , n14124 , n14125 , n14126 , n14127 , n14128 , n14129 , n14130 ,
n14131 , n14132 , n14133 , n14134 , n14135 , n14136 , n14137 , n14138 , n14139 , n14140 ,
n14141 , n14142 , n14143 , n14144 , n14145 , n14146 , n14147 , n14148 , n14149 , n14150 ,
n14151 , n14152 , n14153 , n14154 , n14155 , n14156 , n14157 , n14158 , n14159 , n14160 ,
n14161 , n14162 , n14163 , n14164 , n14165 , n14166 , n14167 , n14168 , n14169 , n14170 ,
n14171 , n14172 , n14173 , n14174 , n14175 , n14176 , n14177 , n14178 , n14179 , n14180 ,
n14181 , n14182 , n14183 , n14184 , n14185 , n14186 , n14187 , n14188 , n14189 , n14190 ,
n14191 , n14192 , n14193 , n14194 , n14195 , n14196 , n14197 , n14198 , n14199 , n14200 ,
n14201 , n14202 , n14203 , n14204 , n14205 , n14206 , n14207 , n14208 , n14209 , n14210 ,
n14211 , n14212 , n14213 , n14214 , n14215 , n14216 , n14217 , n14218 , n14219 , n14220 ,
n14221 , n14222 , n14223 , n14224 , n14225 , n14226 , n14227 , n14228 , n14229 , n14230 ,
n14231 , n14232 , n14233 , n14234 , n14235 , n14236 , n14237 , n14238 , n14239 , n14240 ,
n14241 , n14242 , n14243 , n14244 , n14245 , n14246 , n14247 , n14248 , n14249 , n14250 ,
n14251 , n14252 , n14253 , n14254 , n14255 , n14256 , n14257 , n14258 , n14259 , n14260 ,
n14261 , n14262 , n14263 , n14264 , n14265 , n14266 , n14267 , n14268 , n14269 , n14270 ,
n14271 , n14272 , n14273 , n14274 , n14275 , n14276 , n14277 , n14278 , n14279 , n14280 ,
n14281 , n14282 , n14283 , n14284 , n14285 , n14286 , n14287 , n14288 , n14289 , n14290 ,
n14291 , n14292 , n14293 , n14294 , n14295 , n14296 , n14297 , n14298 , n14299 , n14300 ,
n14301 , n14302 , n14303 , n14304 , n14305 , n14306 , n14307 , n14308 , n14309 , n14310 ,
n14311 , n14312 , n14313 , n14314 , n14315 , n14316 , n14317 , n14318 , n14319 , n14320 ,
n14321 , n14322 , n14323 , n14324 , n14325 , n14326 , n14327 , n14328 , n14329 , n14330 ,
n14331 , n14332 , n14333 , n14334 , n14335 , n14336 , n14337 , n14338 , n14339 , n14340 ,
n14341 , n14342 , n14343 , n14344 , n14345 , n14346 , n14347 , n14348 , n14349 , n14350 ,
n14351 , n14352 , n14353 , n14354 , n14355 , n14356 , n14357 , n14358 , n14359 , n14360 ,
n14361 , n14362 , n14363 , n14364 , n14365 , n14366 , n14367 , n14368 , n14369 , n14370 ,
n14371 , n14372 , n14373 , n14374 , n14375 , n14376 , n14377 , n14378 , n14379 , n14380 ,
n14381 , n14382 , n14383 , n14384 , n14385 , n14386 , n14387 , n14388 , n14389 , n14390 ,
n14391 , n14392 , n14393 , n14394 , n14395 , n14396 , n14397 , n14398 , n14399 , n14400 ,
n14401 , n14402 , n14403 , n14404 , n14405 , n14406 , n14407 , n14408 , n14409 , n14410 ,
n14411 , n14412 , n14413 , n14414 , n14415 , n14416 , n14417 , n14418 , n14419 , n14420 ,
n14421 , n14422 , n14423 , n14424 , n14425 , n14426 , n14427 , n14428 , n14429 , n14430 ,
n14431 , n14432 , n14433 , n14434 , n14435 , n14436 , n14437 , n14438 , n14439 , n14440 ,
n14441 , n14442 , n14443 , n14444 , n14445 , n14446 , n14447 , n14448 , n14449 , n14450 ,
n14451 , n14452 , n14453 , n14454 , n14455 , n14456 , n14457 , n14458 , n14459 , n14460 ,
n14461 , n14462 , n14463 , n14464 , n14465 , n14466 , n14467 , n14468 , n14469 , n14470 ,
n14471 , n14472 , n14473 , n14474 , n14475 , n14476 , n14477 , n14478 , n14479 , n14480 ,
n14481 , n14482 , n14483 , n14484 , n14485 , n14486 , n14487 , n14488 , n14489 , n14490 ,
n14491 , n14492 , n14493 , n14494 , n14495 , n14496 , n14497 , n14498 , n14499 , n14500 ,
n14501 , n14502 , n14503 , n14504 , n14505 , n14506 , n14507 , n14508 , n14509 , n14510 ,
n14511 , n14512 , n14513 , n14514 , n14515 , n14516 , n14517 , n14518 , n14519 , n14520 ,
n14521 , n14522 , n14523 , n14524 , n14525 , n14526 , n14527 , n14528 , n14529 , n14530 ,
n14531 , n14532 , n14533 , n14534 , n14535 , n14536 , n14537 , n14538 , n14539 , n14540 ,
n14541 , n14542 , n14543 , n14544 , n14545 , n14546 , n14547 , n14548 , n14549 , n14550 ,
n14551 , n14552 , n14553 , n14554 , n14555 , n14556 , n14557 , n14558 , n14559 , n14560 ,
n14561 , n14562 , n14563 , n14564 , n14565 , n14566 , n14567 , n14568 , n14569 , n14570 ,
n14571 , n14572 , n14573 , n14574 , n14575 , n14576 , n14577 , n14578 , n14579 , n14580 ,
n14581 , n14582 , n14583 , n14584 , n14585 , n14586 , n14587 , n14588 , n14589 , n14590 ,
n14591 , n14592 , n14593 , n14594 , n14595 , n14596 , n14597 , n14598 , n14599 , n14600 ,
n14601 , n14602 , n14603 , n14604 , n14605 , n14606 , n14607 , n14608 , n14609 , n14610 ,
n14611 , n14612 , n14613 , n14614 , n14615 , n14616 , n14617 , n14618 , n14619 , n14620 ,
n14621 , n14622 , n14623 , n14624 , n14625 , n14626 , n14627 , n14628 , n14629 , n14630 ,
n14631 , n14632 , n14633 , n14634 , n14635 , n14636 , n14637 , n14638 , n14639 , n14640 ,
n14641 , n14642 , n14643 , n14644 , n14645 , C0n , C0 , C1n , C1 ;
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buf ( n457 , C0 );
buf ( n458 , C0 );
buf ( n459 , C0 );
buf ( n460 , C0 );
buf ( n461 , C0 );
buf ( n462 , C0 );
buf ( n463 , C0 );
buf ( n464 , C0 );
buf ( n465 , C0 );
buf ( n466 , C0 );
buf ( n467 , C0 );
buf ( n468 , C0 );
buf ( n469 , C0 );
buf ( n470 , C0 );
buf ( n471 , C0 );
buf ( n472 , C0 );
buf ( n473 , C0 );
buf ( n474 , C0 );
buf ( n475 , C0 );
buf ( n476 , C0 );
buf ( n477 , C0 );
buf ( n478 , C0 );
buf ( n479 , C0 );
buf ( n480 , C0 );
buf ( n481 , C0 );
buf ( n482 , C0 );
buf ( n483 , C0 );
buf ( n484 , C0 );
buf ( n485 , C0 );
buf ( n486 , C0 );
buf ( n487 , C0 );
buf ( n488 , C0 );
buf ( n489 , C0 );
buf ( n490 , n14587 );
buf ( n491 , n14555 );
buf ( n492 , n14566 );
buf ( n493 , n14512 );
buf ( n494 , n14640 );
buf ( n495 , n14498 );
buf ( n496 , n14078 );
buf ( n497 , n14614 );
buf ( n498 , n14600 );
buf ( n499 , n14641 );
buf ( n500 , n14641 );
buf ( n501 , n14641 );
buf ( n502 , n14641 );
buf ( n503 , n14641 );
buf ( n504 , n14641 );
buf ( n505 , n14641 );
buf ( n506 , n14562 );
buf ( n507 , n14562 );
buf ( n508 , n14562 );
buf ( n509 , n14562 );
buf ( n510 , n14562 );
buf ( n511 , n14562 );
buf ( n512 , n14562 );
buf ( n513 , n14562 );
buf ( n514 , n14562 );
buf ( n515 , n14562 );
buf ( n516 , n14562 );
buf ( n517 , n14562 );
buf ( n518 , n14563 );
buf ( n519 , n14563 );
buf ( n520 , n14563 );
buf ( n521 , n14563 );
buf ( n522 , n14563 );
buf ( n523 , n14563 );
buf ( n524 , n14563 );
buf ( n525 , n14563 );
buf ( n526 , n14563 );
buf ( n527 , n14563 );
buf ( n528 , n14563 );
buf ( n529 , n14563 );
buf ( n530 , n13586 );
buf ( n531 , n14579 );
buf ( n532 , n14620 );
buf ( n533 , n13635 );
buf ( n534 , n13650 );
buf ( n535 , n14099 );
buf ( n536 , n14136 );
buf ( n537 , n14551 );
buf ( n538 , n14121 );
buf ( n539 , n14199 );
buf ( n540 , n14645 );
buf ( n541 , n14179 );
buf ( n542 , n14606 );
buf ( n543 , n14591 );
buf ( n544 , n14226 );
buf ( n545 , n14250 );
buf ( n546 , n14261 );
buf ( n547 , n14489 );
buf ( n548 , n14435 );
buf ( n549 , n14473 );
buf ( n550 , n14477 );
buf ( n551 , n14537 );
buf ( n552 , n14466 );
buf ( n553 , n14469 );
buf ( n554 , n14630 );
not ( n555 , n370 );
nand ( n556 , n370 , n374 );
not ( n557 , n556 );
nand ( n558 , n371 , n373 );
not ( n559 , n558 );
or ( n560 , n557 , n559 );
and ( n561 , n370 , n375 );
xor ( n562 , n372 , n561 );
and ( n563 , n372 , n373 );
and ( n564 , n562 , n563 );
and ( n565 , n372 , n561 );
or ( n566 , n564 , n565 );
nand ( n567 , n560 , n566 );
nand ( n568 , n370 , n373 );
nand ( n569 , n371 , n372 );
xor ( n570 , n568 , n569 );
not ( n571 , n371 );
xor ( n572 , n570 , n571 );
not ( n573 , n556 );
not ( n574 , n558 );
nand ( n575 , n573 , n574 );
nand ( n576 , n567 , n572 , n575 );
nand ( n577 , n568 , n569 );
nand ( n578 , n568 , n571 );
nand ( n579 , n569 , n571 );
nand ( n580 , n577 , n578 , n579 );
nand ( n581 , n370 , n372 );
nand ( n582 , n580 , n581 );
nand ( n583 , n576 , n582 );
nor ( n584 , n555 , n583 );
not ( n585 , n584 );
nand ( n586 , n371 , n374 );
not ( n587 , n586 );
xor ( n588 , n372 , n561 );
xor ( n589 , n588 , n563 );
not ( n590 , n589 );
not ( n591 , n590 );
or ( n592 , n587 , n591 );
nand ( n593 , n370 , n376 );
not ( n594 , n593 );
not ( n595 , n594 );
nand ( n596 , n371 , n375 );
not ( n597 , n596 );
not ( n598 , n597 );
or ( n599 , n595 , n598 );
not ( n600 , n596 );
not ( n601 , n593 );
or ( n602 , n600 , n601 );
and ( n603 , n372 , n374 );
nand ( n604 , n602 , n603 );
nand ( n605 , n599 , n604 );
nand ( n606 , n592 , n605 );
not ( n607 , n586 );
nand ( n608 , n589 , n607 );
and ( n609 , n606 , n608 );
not ( n610 , n574 );
not ( n611 , n556 );
and ( n612 , n610 , n611 );
and ( n613 , n556 , n574 );
nor ( n614 , n612 , n613 );
xor ( n615 , n566 , n614 );
nand ( n616 , n609 , n615 );
not ( n617 , n616 );
nand ( n618 , n373 , n374 );
not ( n619 , n618 );
not ( n620 , n370 );
not ( n621 , n377 );
or ( n622 , n620 , n621 );
nand ( n623 , n371 , n376 );
nand ( n624 , n622 , n623 );
not ( n625 , n624 );
and ( n626 , n372 , n375 );
not ( n627 , n626 );
or ( n628 , n625 , n627 );
nand ( n629 , n371 , n376 , n370 , n377 );
nand ( n630 , n628 , n629 );
nor ( n631 , n619 , n630 );
nand ( n632 , n372 , n374 );
nand ( n633 , n371 , n375 );
nand ( n634 , n370 , n376 );
and ( n635 , n633 , n634 );
not ( n636 , n633 );
and ( n637 , n636 , n594 );
nor ( n638 , n635 , n637 );
xor ( n639 , n632 , n638 );
or ( n640 , n631 , n639 );
not ( n641 , n618 );
nand ( n642 , n641 , n630 );
nand ( n643 , n640 , n642 );
not ( n644 , n643 );
not ( n645 , n644 );
xor ( n646 , n607 , n605 );
xnor ( n647 , n646 , n589 );
not ( n648 , n647 );
or ( n649 , n645 , n648 );
nand ( n650 , n373 , n375 , n372 , n376 );
not ( n651 , n650 );
nand ( n652 , n618 , n373 );
not ( n653 , n652 );
and ( n654 , n651 , n653 );
nand ( n655 , n372 , n375 );
nand ( n656 , n371 , n376 );
and ( n657 , n655 , n656 );
not ( n658 , n655 );
not ( n659 , n623 );
and ( n660 , n658 , n659 );
nor ( n661 , n657 , n660 );
and ( n662 , n370 , n377 );
xor ( n663 , n661 , n662 );
nand ( n664 , n652 , n650 );
and ( n665 , n663 , n664 );
nor ( n666 , n654 , n665 );
xor ( n667 , n618 , n630 );
xnor ( n668 , n667 , n639 );
nand ( n669 , n666 , n668 );
nand ( n670 , n649 , n669 );
not ( n671 , n670 );
not ( n672 , n671 );
not ( n673 , n663 );
not ( n674 , n650 );
not ( n675 , n374 );
not ( n676 , n373 );
or ( n677 , n675 , n676 );
nand ( n678 , n677 , n373 );
not ( n679 , n678 );
or ( n680 , n674 , n679 );
or ( n681 , n678 , n650 );
nand ( n682 , n680 , n681 );
not ( n683 , n682 );
and ( n684 , n673 , n683 );
and ( n685 , n682 , n663 );
nor ( n686 , n684 , n685 );
nand ( n687 , n374 , n375 );
nand ( n688 , n371 , n377 );
xor ( n689 , n687 , n688 );
nand ( n690 , n373 , n375 );
nand ( n691 , n376 , n372 );
xnor ( n692 , n690 , n691 );
and ( n693 , n689 , n692 );
and ( n694 , n687 , n688 );
or ( n695 , n693 , n694 );
nand ( n696 , n686 , n695 );
not ( n697 , n696 );
xor ( n698 , n687 , n688 );
xor ( n699 , n698 , n692 );
nand ( n700 , n372 , n377 );
not ( n701 , n700 );
nand ( n702 , n373 , n376 );
not ( n703 , n702 );
and ( n704 , n701 , n703 );
nand ( n705 , n700 , n702 );
not ( n706 , n375 );
and ( n707 , n706 , n374 );
and ( n708 , n705 , n707 );
nor ( n709 , n704 , n708 );
nand ( n710 , n699 , n709 );
not ( n711 , n710 );
nand ( n712 , n377 , n374 , n375 );
not ( n713 , n712 );
nand ( n714 , n375 , n377 );
nand ( n715 , n377 , n376 );
nor ( n716 , n714 , n715 );
nand ( n717 , n713 , n716 );
nand ( n718 , n374 , n376 );
not ( n719 , n718 );
nand ( n720 , n373 , n377 );
not ( n721 , n720 );
or ( n722 , n719 , n721 );
nand ( n723 , n374 , n376 );
nand ( n724 , n373 , n377 );
or ( n725 , n723 , n724 );
nand ( n726 , n722 , n725 );
nand ( n727 , n726 , n712 );
and ( n728 , n374 , n377 );
nand ( n729 , n375 , n376 );
nor ( n730 , n728 , n729 );
and ( n731 , n727 , n730 );
nor ( n732 , n712 , n726 );
nor ( n733 , n731 , n732 );
nand ( n734 , n717 , n733 );
not ( n735 , n734 );
or ( n736 , n700 , n702 );
not ( n737 , n373 );
not ( n738 , n376 );
or ( n739 , n737 , n738 );
nand ( n740 , n372 , n377 );
nand ( n741 , n739 , n740 );
nand ( n742 , n736 , n741 );
not ( n743 , n742 );
not ( n744 , n707 );
and ( n745 , n743 , n744 );
and ( n746 , n707 , n742 );
nor ( n747 , n745 , n746 );
not ( n748 , n618 );
and ( n749 , n377 , n376 );
nand ( n750 , n748 , n749 );
nand ( n751 , n747 , n750 );
not ( n752 , n751 );
or ( n753 , n735 , n752 );
not ( n754 , n747 );
not ( n755 , n750 );
nand ( n756 , n754 , n755 );
nand ( n757 , n753 , n756 );
not ( n758 , n757 );
or ( n759 , n711 , n758 );
or ( n760 , n699 , n709 );
nand ( n761 , n759 , n760 );
not ( n762 , n761 );
or ( n763 , n697 , n762 );
not ( n764 , n686 );
not ( n765 , n695 );
nand ( n766 , n764 , n765 );
nand ( n767 , n763 , n766 );
not ( n768 , n767 );
or ( n769 , n672 , n768 );
not ( n770 , n647 );
not ( n771 , n644 );
and ( n772 , n770 , n771 );
nand ( n773 , n647 , n644 );
nor ( n774 , n666 , n668 );
and ( n775 , n773 , n774 );
nor ( n776 , n772 , n775 );
nand ( n777 , n769 , n776 );
not ( n778 , n777 );
or ( n779 , n617 , n778 );
nor ( n780 , n615 , n609 );
not ( n781 , n780 );
nand ( n782 , n779 , n781 );
not ( n783 , n782 );
or ( n784 , n585 , n783 );
not ( n785 , n575 );
not ( n786 , n567 );
or ( n787 , n785 , n786 );
not ( n788 , n572 );
nand ( n789 , n787 , n788 );
not ( n790 , n582 );
or ( n791 , n789 , n790 );
or ( n792 , n580 , n581 );
nand ( n793 , n791 , n792 );
or ( n794 , n793 , n371 );
nand ( n795 , n794 , n370 );
nand ( n796 , n784 , n795 );
buf ( n797 , n796 );
and ( n798 , n715 , n376 );
buf ( n799 , n798 );
and ( n800 , n797 , n799 );
buf ( n801 , n800 );
buf ( n802 , n801 );
buf ( n803 , n767 );
buf ( n804 , n803 );
not ( n805 , n774 );
buf ( n806 , n669 );
nand ( n807 , n805 , n806 );
not ( n808 , n807 );
and ( n809 , n804 , n808 );
not ( n810 , n804 );
and ( n811 , n810 , n807 );
nor ( n812 , n809 , n811 );
buf ( n813 , n812 );
buf ( n814 , n813 );
buf ( n815 , n814 );
buf ( n816 , n815 );
and ( n817 , n802 , n816 );
not ( n818 , n802 );
buf ( n819 , n815 );
not ( n820 , n819 );
buf ( n821 , n820 );
buf ( n822 , n821 );
and ( n823 , n818 , n822 );
nor ( n824 , n817 , n823 );
buf ( n825 , n824 );
not ( n826 , n790 );
nand ( n827 , n826 , n792 );
not ( n828 , n827 );
not ( n829 , n616 );
not ( n830 , n576 );
nor ( n831 , n829 , n830 );
not ( n832 , n831 );
buf ( n833 , n777 );
not ( n834 , n833 );
or ( n835 , n832 , n834 );
and ( n836 , n780 , n576 );
not ( n837 , n789 );
nor ( n838 , n836 , n837 );
nand ( n839 , n835 , n838 );
not ( n840 , n839 );
or ( n841 , n828 , n840 );
or ( n842 , n827 , n839 );
nand ( n843 , n841 , n842 );
buf ( n844 , n843 );
not ( n845 , n844 );
buf ( n846 , n845 );
buf ( n847 , n846 );
not ( n848 , n847 );
buf ( n849 , n848 );
and ( n850 , n714 , n749 );
not ( n851 , n714 );
and ( n852 , n851 , n715 );
or ( n853 , n850 , n852 );
nand ( n854 , n849 , n853 );
buf ( n855 , n854 );
nand ( n856 , n571 , n370 );
not ( n857 , n856 );
not ( n858 , n857 );
nor ( n859 , n829 , n583 );
not ( n860 , n859 );
not ( n861 , n777 );
or ( n862 , n860 , n861 );
not ( n863 , n781 );
not ( n864 , n583 );
and ( n865 , n863 , n864 );
nor ( n866 , n865 , n793 );
nand ( n867 , n862 , n866 );
not ( n868 , n867 );
not ( n869 , n868 );
or ( n870 , n858 , n869 );
nand ( n871 , n867 , n856 );
nand ( n872 , n870 , n871 );
buf ( n873 , n872 );
not ( n874 , n873 );
buf ( n875 , n874 );
buf ( n876 , n875 );
not ( n877 , n876 );
buf ( n878 , n877 );
buf ( n879 , n878 );
buf ( n880 , n798 );
and ( n881 , n879 , n880 );
xor ( n882 , n699 , n709 );
xor ( n883 , n882 , n757 );
nand ( n884 , n812 , n883 );
buf ( n885 , n884 );
not ( n886 , n885 );
buf ( n887 , n886 );
buf ( n888 , n887 );
nor ( n889 , n881 , n888 );
buf ( n890 , n889 );
buf ( n891 , n890 );
or ( n892 , n855 , n891 );
buf ( n893 , n878 );
buf ( n894 , n887 );
buf ( n895 , n798 );
nand ( n896 , n893 , n894 , n895 );
buf ( n897 , n896 );
buf ( n898 , n897 );
nand ( n899 , n892 , n898 );
buf ( n900 , n899 );
buf ( n901 , n900 );
not ( n902 , n901 );
buf ( n903 , n902 );
xor ( n904 , n825 , n903 );
not ( n905 , n830 );
nand ( n906 , n905 , n789 );
xnor ( n907 , n782 , n906 );
buf ( n908 , n907 );
not ( n909 , n730 );
nand ( n910 , n374 , n377 );
xor ( n911 , n910 , n375 );
nand ( n912 , n911 , n729 );
nand ( n913 , n909 , n912 );
and ( n914 , n913 , n716 );
not ( n915 , n913 );
not ( n916 , n716 );
and ( n917 , n915 , n916 );
or ( n918 , n914 , n917 );
nand ( n919 , n908 , n918 );
buf ( n920 , n919 );
not ( n921 , n920 );
not ( n922 , n829 );
nand ( n923 , n922 , n781 );
not ( n924 , n923 );
not ( n925 , n924 );
not ( n926 , n833 );
not ( n927 , n926 );
or ( n928 , n925 , n927 );
nand ( n929 , n833 , n923 );
nand ( n930 , n928 , n929 );
buf ( n931 , n930 );
not ( n932 , n931 );
buf ( n933 , n932 );
buf ( n934 , n933 );
not ( n935 , n934 );
buf ( n936 , n935 );
not ( n937 , n912 );
not ( n938 , n716 );
or ( n939 , n937 , n938 );
nand ( n940 , n939 , n909 );
not ( n941 , n940 );
not ( n942 , n941 );
not ( n943 , n732 );
nand ( n944 , n943 , n727 );
not ( n945 , n944 );
not ( n946 , n945 );
or ( n947 , n942 , n946 );
nand ( n948 , n944 , n940 );
nand ( n949 , n947 , n948 );
nand ( n950 , n936 , n949 );
buf ( n951 , n950 );
not ( n952 , n951 );
or ( n953 , n921 , n952 );
not ( n954 , n806 );
not ( n955 , n803 );
or ( n956 , n954 , n955 );
not ( n957 , n774 );
nand ( n958 , n956 , n957 );
not ( n959 , n958 );
and ( n960 , n647 , n643 );
not ( n961 , n647 );
and ( n962 , n961 , n644 );
nor ( n963 , n960 , n962 );
not ( n964 , n963 );
and ( n965 , n959 , n964 );
and ( n966 , n958 , n963 );
nor ( n967 , n965 , n966 );
not ( n968 , n967 );
nand ( n969 , n756 , n751 );
xnor ( n970 , n734 , n969 );
buf ( n971 , n970 );
buf ( n972 , n971 );
buf ( n973 , n972 );
nand ( n974 , n968 , n973 );
buf ( n975 , n974 );
not ( n976 , n975 );
buf ( n977 , n976 );
buf ( n978 , n977 );
nand ( n979 , n953 , n978 );
buf ( n980 , n979 );
buf ( n981 , n980 );
not ( n982 , n919 );
not ( n983 , n950 );
nand ( n984 , n982 , n983 );
buf ( n985 , n984 );
nand ( n986 , n981 , n985 );
buf ( n987 , n986 );
xnor ( n988 , n904 , n987 );
buf ( n989 , n988 );
not ( n990 , n919 );
and ( n991 , n974 , n990 );
not ( n992 , n974 );
and ( n993 , n992 , n919 );
nor ( n994 , n991 , n993 );
xor ( n995 , n983 , n994 );
buf ( n996 , n995 );
not ( n997 , n996 );
nand ( n998 , n878 , n798 );
xor ( n999 , n884 , n998 );
xnor ( n1000 , n999 , n854 );
not ( n1001 , n1000 );
buf ( n1002 , n1001 );
not ( n1003 , n1002 );
or ( n1004 , n997 , n1003 );
buf ( n1005 , n796 );
buf ( n1006 , n1005 );
buf ( n1007 , n1006 );
buf ( n1008 , n1007 );
buf ( n1009 , n377 );
nand ( n1010 , n1008 , n1009 );
buf ( n1011 , n1010 );
and ( n1012 , n764 , n765 );
not ( n1013 , n764 );
and ( n1014 , n1013 , n695 );
nor ( n1015 , n1012 , n1014 );
not ( n1016 , n1015 );
buf ( n1017 , n761 );
not ( n1018 , n1017 );
not ( n1019 , n1018 );
or ( n1020 , n1016 , n1019 );
not ( n1021 , n1015 );
nand ( n1022 , n1021 , n1017 );
nand ( n1023 , n1020 , n1022 );
buf ( n1024 , n1023 );
buf ( n1025 , n1024 );
buf ( n1026 , n1025 );
and ( n1027 , n1011 , n1026 );
not ( n1028 , n1011 );
buf ( n1029 , n1026 );
not ( n1030 , n1029 );
buf ( n1031 , n1030 );
and ( n1032 , n1028 , n1031 );
nor ( n1033 , n1027 , n1032 );
and ( n1034 , n1023 , n973 );
not ( n1035 , n857 );
not ( n1036 , n868 );
or ( n1037 , n1035 , n1036 );
nand ( n1038 , n1037 , n871 );
buf ( n1039 , n1038 );
nand ( n1040 , n1034 , n377 , n1039 );
nand ( n1041 , n1033 , n1040 );
not ( n1042 , n1041 );
buf ( n1043 , n968 );
not ( n1044 , n1043 );
buf ( n1045 , n918 );
not ( n1046 , n1045 );
buf ( n1047 , n1046 );
buf ( n1048 , n1047 );
nor ( n1049 , n1044 , n1048 );
buf ( n1050 , n1049 );
buf ( n1051 , n1050 );
buf ( n1052 , n936 );
buf ( n1053 , n853 );
and ( n1054 , n1052 , n1053 );
buf ( n1055 , n1054 );
buf ( n1056 , n1055 );
buf ( n1057 , n908 );
buf ( n1058 , n798 );
and ( n1059 , n1057 , n1058 );
buf ( n1060 , n1059 );
buf ( n1061 , n1060 );
and ( n1062 , n1051 , n1056 );
or ( n1063 , C0 , n1062 );
buf ( n1064 , n1063 );
not ( n1065 , n1064 );
or ( n1066 , n1042 , n1065 );
not ( n1067 , n1033 );
not ( n1068 , n1040 );
nand ( n1069 , n1067 , n1068 );
nand ( n1070 , n1066 , n1069 );
buf ( n1071 , n1070 );
nand ( n1072 , n1004 , n1071 );
buf ( n1073 , n1072 );
buf ( n1074 , n1073 );
not ( n1075 , n995 );
nand ( n1076 , n1075 , n1000 );
buf ( n1077 , n1076 );
nand ( n1078 , n1074 , n1077 );
buf ( n1079 , n1078 );
buf ( n1080 , n1079 );
buf ( n1081 , n812 );
not ( n1082 , n1015 );
not ( n1083 , n1018 );
or ( n1084 , n1082 , n1083 );
nand ( n1085 , n1084 , n1022 );
buf ( n1086 , n1085 );
nand ( n1087 , n1081 , n1086 );
buf ( n1088 , n1087 );
and ( n1089 , n968 , n883 );
xor ( n1090 , n1088 , n1089 );
buf ( n1091 , n949 );
buf ( n1092 , n908 );
nand ( n1093 , n1091 , n1092 );
buf ( n1094 , n1093 );
xnor ( n1095 , n1090 , n1094 );
not ( n1096 , n1095 );
buf ( n1097 , n843 );
buf ( n1098 , n918 );
and ( n1099 , n1097 , n1098 );
buf ( n1100 , n1099 );
buf ( n1101 , n933 );
not ( n1102 , n1101 );
buf ( n1103 , n1102 );
buf ( n1104 , n1103 );
buf ( n1105 , n970 );
and ( n1106 , n1104 , n1105 );
buf ( n1107 , n1106 );
xor ( n1108 , n1100 , n1107 );
buf ( n1109 , n1038 );
buf ( n1110 , n853 );
and ( n1111 , n1109 , n1110 );
buf ( n1112 , n1111 );
xor ( n1113 , n1108 , n1112 );
not ( n1114 , n1113 );
or ( n1115 , n1096 , n1114 );
or ( n1116 , n1113 , n1095 );
nand ( n1117 , n1115 , n1116 );
buf ( n1118 , n1085 );
buf ( n1119 , n883 );
nand ( n1120 , n1118 , n1119 );
buf ( n1121 , n1120 );
buf ( n1122 , n1121 );
not ( n1123 , n1122 );
buf ( n1124 , n968 );
buf ( n1125 , n949 );
nand ( n1126 , n1124 , n1125 );
buf ( n1127 , n1126 );
buf ( n1128 , n1127 );
not ( n1129 , n1128 );
or ( n1130 , n1123 , n1129 );
buf ( n1131 , n812 );
buf ( n1132 , n973 );
and ( n1133 , n1131 , n1132 );
buf ( n1134 , n1133 );
buf ( n1135 , n1134 );
nand ( n1136 , n1130 , n1135 );
buf ( n1137 , n1136 );
buf ( n1138 , n1137 );
buf ( n1139 , n1127 );
not ( n1140 , n1139 );
buf ( n1141 , n1121 );
not ( n1142 , n1141 );
buf ( n1143 , n1142 );
buf ( n1144 , n1143 );
nand ( n1145 , n1140 , n1144 );
buf ( n1146 , n1145 );
buf ( n1147 , n1146 );
nand ( n1148 , n1138 , n1147 );
buf ( n1149 , n1148 );
buf ( n1150 , n1149 );
buf ( n1151 , n1007 );
buf ( n1152 , n1026 );
buf ( n1153 , n377 );
and ( n1154 , n1151 , n1152 , n1153 );
buf ( n1155 , n1154 );
buf ( n1156 , n1155 );
xor ( n1157 , n1150 , n1156 );
buf ( n1158 , n908 );
buf ( n1159 , n853 );
nand ( n1160 , n1158 , n1159 );
buf ( n1161 , n1160 );
buf ( n1162 , n1161 );
not ( n1163 , n1162 );
buf ( n1164 , n1163 );
buf ( n1165 , n1164 );
not ( n1166 , n1165 );
buf ( n1167 , n936 );
buf ( n1168 , n918 );
and ( n1169 , n1167 , n1168 );
buf ( n1170 , n1169 );
buf ( n1171 , n1170 );
not ( n1172 , n1171 );
or ( n1173 , n1166 , n1172 );
buf ( n1174 , n798 );
not ( n1175 , n1174 );
buf ( n1176 , n1175 );
buf ( n1177 , C1 );
buf ( n1178 , n1177 );
nand ( n1179 , n1173 , n1178 );
buf ( n1180 , n1179 );
buf ( n1181 , n1180 );
and ( n1182 , n1157 , n1181 );
and ( n1183 , n1150 , n1156 );
or ( n1184 , n1182 , n1183 );
buf ( n1185 , n1184 );
xor ( n1186 , n1117 , n1185 );
buf ( n1187 , n1186 );
xor ( n1188 , n989 , n1080 );
xor ( n1189 , n1188 , n1187 );
buf ( n1190 , n1189 );
xor ( n1191 , n989 , n1080 );
and ( n1192 , n1191 , n1187 );
and ( n1193 , n989 , n1080 );
or ( n1194 , n1192 , n1193 );
buf ( n1195 , n1194 );
and ( n1196 , n815 , n1007 , n798 );
not ( n1197 , n1088 );
nand ( n1198 , n1197 , n1089 );
not ( n1199 , n1198 );
not ( n1200 , n1094 );
or ( n1201 , n1199 , n1200 );
not ( n1202 , n1089 );
nand ( n1203 , n1202 , n1088 );
nand ( n1204 , n1201 , n1203 );
xor ( n1205 , n1196 , n1204 );
xor ( n1206 , n1100 , n1107 );
and ( n1207 , n1206 , n1112 );
and ( n1208 , n1100 , n1107 );
or ( n1209 , n1207 , n1208 );
xnor ( n1210 , n1205 , n1209 );
buf ( n1211 , n1210 );
not ( n1212 , n1113 );
nand ( n1213 , n1212 , n1095 );
buf ( n1214 , n1213 );
not ( n1215 , n1214 );
buf ( n1216 , n1185 );
not ( n1217 , n1216 );
or ( n1218 , n1215 , n1217 );
not ( n1219 , n1095 );
nand ( n1220 , n1219 , n1113 );
buf ( n1221 , n1220 );
nand ( n1222 , n1218 , n1221 );
buf ( n1223 , n1222 );
buf ( n1224 , n1223 );
not ( n1225 , n825 );
nand ( n1226 , n1225 , n903 );
not ( n1227 , n1226 );
not ( n1228 , n987 );
or ( n1229 , n1227 , n1228 );
not ( n1230 , n903 );
nand ( n1231 , n1230 , n825 );
nand ( n1232 , n1229 , n1231 );
buf ( n1233 , n1103 );
buf ( n1234 , n883 );
and ( n1235 , n1233 , n1234 );
buf ( n1236 , n1235 );
buf ( n1237 , n872 );
buf ( n1238 , n918 );
and ( n1239 , n1237 , n1238 );
buf ( n1240 , n1239 );
xor ( n1241 , n1236 , n1240 );
buf ( n1242 , n843 );
buf ( n1243 , n949 );
and ( n1244 , n1242 , n1243 );
buf ( n1245 , n1244 );
xor ( n1246 , n1241 , n1245 );
buf ( n1247 , n1246 );
buf ( n1248 , n968 );
buf ( n1249 , n1085 );
and ( n1250 , n1248 , n1249 );
buf ( n1251 , n1250 );
buf ( n1252 , n1251 );
not ( n1253 , n795 );
nand ( n1254 , n782 , n584 );
not ( n1255 , n1254 );
or ( n1256 , n1253 , n1255 );
nand ( n1257 , n1256 , n853 );
not ( n1258 , n1257 );
buf ( n1259 , n1258 );
xor ( n1260 , n1252 , n1259 );
buf ( n1261 , n908 );
buf ( n1262 , n973 );
and ( n1263 , n1261 , n1262 );
buf ( n1264 , n1263 );
buf ( n1265 , n1264 );
xor ( n1266 , n1260 , n1265 );
buf ( n1267 , n1266 );
buf ( n1268 , n1267 );
not ( n1269 , n1268 );
buf ( n1270 , n1269 );
buf ( n1271 , n1270 );
and ( n1272 , n1247 , n1271 );
not ( n1273 , n1247 );
buf ( n1274 , n1267 );
and ( n1275 , n1273 , n1274 );
nor ( n1276 , n1272 , n1275 );
buf ( n1277 , n1276 );
xnor ( n1278 , n1232 , n1277 );
buf ( n1279 , n1278 );
xor ( n1280 , n1211 , n1224 );
xor ( n1281 , n1280 , n1279 );
buf ( n1282 , n1281 );
xor ( n1283 , n1211 , n1224 );
and ( n1284 , n1283 , n1279 );
and ( n1285 , n1211 , n1224 );
or ( n1286 , n1284 , n1285 );
buf ( n1287 , n1286 );
not ( n1288 , n1070 );
and ( n1289 , n995 , n1001 );
not ( n1290 , n995 );
and ( n1291 , n1290 , n1000 );
nor ( n1292 , n1289 , n1291 );
xor ( n1293 , n1288 , n1292 );
not ( n1294 , n1293 );
xor ( n1295 , n1150 , n1156 );
xor ( n1296 , n1295 , n1181 );
buf ( n1297 , n1296 );
buf ( n1298 , n1297 );
not ( n1299 , n1298 );
buf ( n1300 , n1299 );
not ( n1301 , n1300 );
and ( n1302 , n1294 , n1301 );
buf ( n1303 , n1293 );
buf ( n1304 , n1300 );
nand ( n1305 , n1303 , n1304 );
buf ( n1306 , n1305 );
buf ( n1307 , n1143 );
buf ( n1308 , n1127 );
xor ( n1309 , n1307 , n1308 );
buf ( n1310 , n1134 );
xor ( n1311 , n1309 , n1310 );
buf ( n1312 , n1311 );
buf ( n1313 , n1312 );
not ( n1314 , n1313 );
buf ( n1315 , n1170 );
buf ( n1316 , n1164 );
and ( n1317 , n1315 , n1316 );
not ( n1318 , n1315 );
buf ( n1319 , n1161 );
and ( n1320 , n1318 , n1319 );
nor ( n1321 , n1317 , n1320 );
buf ( n1322 , n1321 );
buf ( n1323 , n849 );
buf ( n1324 , n798 );
and ( n1325 , n1323 , n1324 );
buf ( n1326 , n1325 );
xnor ( n1327 , n1322 , n1326 );
buf ( n1328 , n1327 );
not ( n1329 , n1328 );
buf ( n1330 , n1329 );
buf ( n1331 , n1330 );
nand ( n1332 , n1314 , n1331 );
buf ( n1333 , n1332 );
buf ( n1334 , n1333 );
buf ( n1335 , n1312 );
not ( n1336 , n1335 );
buf ( n1337 , n1327 );
not ( n1338 , n1337 );
or ( n1339 , n1336 , n1338 );
buf ( n1340 , n812 );
buf ( n1341 , n1340 );
buf ( n1342 , n1341 );
buf ( n1343 , n1342 );
buf ( n1344 , n949 );
and ( n1345 , n1343 , n1344 );
buf ( n1346 , n1345 );
buf ( n1347 , n1346 );
buf ( n1348 , n843 );
buf ( n1349 , n1348 );
buf ( n1350 , n1349 );
buf ( n1351 , n1350 );
not ( n1352 , n1351 );
buf ( n1353 , n883 );
buf ( n1354 , n1353 );
buf ( n1355 , n1354 );
buf ( n1356 , n1355 );
buf ( n1357 , n377 );
nand ( n1358 , n1356 , n1357 );
buf ( n1359 , n1358 );
buf ( n1360 , n1359 );
nor ( n1361 , n1352 , n1360 );
buf ( n1362 , n1361 );
buf ( n1363 , n1362 );
xor ( n1364 , n1347 , n1363 );
nand ( n1365 , n377 , n1038 );
xnor ( n1366 , n1365 , n1034 );
buf ( n1367 , n1366 );
and ( n1368 , n1364 , n1367 );
and ( n1369 , n1347 , n1363 );
or ( n1370 , n1368 , n1369 );
buf ( n1371 , n1370 );
buf ( n1372 , n1371 );
nand ( n1373 , n1339 , n1372 );
buf ( n1374 , n1373 );
buf ( n1375 , n1374 );
nand ( n1376 , n1334 , n1375 );
buf ( n1377 , n1376 );
and ( n1378 , n1306 , n1377 );
nor ( n1379 , n1302 , n1378 );
buf ( n1380 , n1379 );
not ( n1381 , n1380 );
buf ( n1382 , n1381 );
xor ( n1383 , n1051 , n1056 );
xor ( n1384 , n1383 , n1061 );
buf ( n1385 , n1384 );
buf ( n1386 , n1385 );
buf ( n1387 , n883 );
buf ( n1388 , n970 );
and ( n1389 , n1387 , n1388 );
buf ( n1390 , n1389 );
buf ( n1391 , n1390 );
buf ( n1392 , n968 );
buf ( n1393 , n853 );
and ( n1394 , n1392 , n1393 );
buf ( n1395 , n1394 );
buf ( n1396 , n1395 );
xor ( n1397 , n1391 , n1396 );
buf ( n1398 , n1103 );
buf ( n1399 , n798 );
and ( n1400 , n1398 , n1399 );
buf ( n1401 , n1400 );
buf ( n1402 , n1401 );
and ( n1403 , n1397 , n1402 );
and ( n1404 , n1391 , n1396 );
or ( n1405 , n1403 , n1404 );
buf ( n1406 , n1405 );
buf ( n1407 , n1406 );
xor ( n1408 , n1386 , n1407 );
buf ( n1409 , n1085 );
buf ( n1410 , n949 );
and ( n1411 , n1409 , n1410 );
buf ( n1412 , n1411 );
buf ( n1413 , n1412 );
buf ( n1414 , n1342 );
not ( n1415 , n1414 );
buf ( n1416 , n1047 );
nor ( n1417 , n1415 , n1416 );
buf ( n1418 , n1417 );
buf ( n1419 , n1418 );
xor ( n1420 , n1413 , n1419 );
buf ( n1421 , n908 );
buf ( n1422 , n1421 );
buf ( n1423 , n377 );
nand ( n1424 , n1422 , n1423 );
buf ( n1425 , n1424 );
buf ( n1426 , n1425 );
buf ( n1427 , n883 );
buf ( n1428 , n949 );
nand ( n1429 , n1427 , n1428 );
buf ( n1430 , n1429 );
buf ( n1431 , n1430 );
nor ( n1432 , n1426 , n1431 );
buf ( n1433 , n1432 );
buf ( n1434 , n1433 );
and ( n1435 , n1420 , n1434 );
and ( n1436 , n1413 , n1419 );
or ( n1437 , n1435 , n1436 );
buf ( n1438 , n1437 );
buf ( n1439 , n1438 );
and ( n1440 , n1408 , n1439 );
and ( n1441 , n1386 , n1407 );
or ( n1442 , n1440 , n1441 );
buf ( n1443 , n1442 );
buf ( n1444 , n1443 );
buf ( n1445 , n1068 );
not ( n1446 , n1445 );
buf ( n1447 , n1033 );
not ( n1448 , n1447 );
or ( n1449 , n1446 , n1448 );
buf ( n1450 , n1068 );
buf ( n1451 , n1033 );
or ( n1452 , n1450 , n1451 );
nand ( n1453 , n1449 , n1452 );
buf ( n1454 , n1453 );
xor ( n1455 , n1064 , n1454 );
buf ( n1456 , n1455 );
buf ( n1457 , n1312 );
buf ( n1458 , n1330 );
xor ( n1459 , n1457 , n1458 );
buf ( n1460 , n1371 );
xnor ( n1461 , n1459 , n1460 );
buf ( n1462 , n1461 );
buf ( n1463 , n1462 );
xor ( n1464 , n1444 , n1456 );
xor ( n1465 , n1464 , n1463 );
buf ( n1466 , n1465 );
xor ( n1467 , n1444 , n1456 );
and ( n1468 , n1467 , n1463 );
and ( n1469 , n1444 , n1456 );
or ( n1470 , n1468 , n1469 );
buf ( n1471 , n1470 );
buf ( n1472 , n1293 );
buf ( n1473 , n1293 );
not ( n1474 , n1473 );
buf ( n1475 , n1474 );
buf ( n1476 , n1475 );
buf ( n1477 , n1377 );
buf ( n1478 , n1297 );
and ( n1479 , n1477 , n1478 );
not ( n1480 , n1477 );
buf ( n1481 , n1300 );
and ( n1482 , n1480 , n1481 );
nor ( n1483 , n1479 , n1482 );
buf ( n1484 , n1483 );
buf ( n1485 , n1484 );
and ( n1486 , n1485 , n1476 );
not ( n1487 , n1485 );
and ( n1488 , n1487 , n1472 );
nor ( n1489 , n1486 , n1488 );
buf ( n1490 , n1489 );
buf ( n1491 , n1421 );
buf ( n1492 , n1007 );
buf ( n1493 , n1026 );
nand ( n1494 , n1492 , n1493 );
buf ( n1495 , n1494 );
buf ( n1496 , n1495 );
xor ( n1497 , n1491 , n1496 );
buf ( n1498 , n936 );
buf ( n1499 , n1498 );
buf ( n1500 , n1499 );
buf ( n1501 , n1500 );
buf ( n1502 , n1421 );
and ( n1503 , n1501 , n1502 );
buf ( n1504 , n1503 );
buf ( n1505 , n1504 );
xnor ( n1506 , n1497 , n1505 );
buf ( n1507 , n1506 );
buf ( n1508 , n1507 );
buf ( n1509 , n1039 );
buf ( n1510 , n815 );
and ( n1511 , n1509 , n1510 );
buf ( n1512 , n1511 );
buf ( n1513 , n1512 );
buf ( n1514 , n849 );
buf ( n1515 , n967 );
not ( n1516 , n1515 );
buf ( n1517 , n1516 );
and ( n1518 , n1514 , n1517 );
buf ( n1519 , n1518 );
buf ( n1520 , n1519 );
xor ( n1521 , n1513 , n1520 );
buf ( n1522 , n1007 );
buf ( n1523 , n1355 );
nand ( n1524 , n1522 , n1523 );
buf ( n1525 , n1524 );
buf ( n1526 , n1525 );
not ( n1527 , n1526 );
buf ( n1528 , n908 );
buf ( n1529 , n1516 );
nand ( n1530 , n1528 , n1529 );
buf ( n1531 , n1530 );
buf ( n1532 , n1531 );
not ( n1533 , n1532 );
or ( n1534 , n1527 , n1533 );
buf ( n1535 , n1039 );
not ( n1536 , n1535 );
buf ( n1537 , n1031 );
nor ( n1538 , n1536 , n1537 );
buf ( n1539 , n1538 );
buf ( n1540 , n1539 );
nand ( n1541 , n1534 , n1540 );
buf ( n1542 , n1541 );
buf ( n1543 , n1542 );
or ( n1544 , n1525 , n1531 );
buf ( n1545 , n1544 );
nand ( n1546 , n1543 , n1545 );
buf ( n1547 , n1546 );
buf ( n1548 , n1547 );
xor ( n1549 , n1521 , n1548 );
buf ( n1550 , n1549 );
buf ( n1551 , n1550 );
buf ( n1552 , n849 );
buf ( n1553 , n1026 );
and ( n1554 , n1552 , n1553 );
buf ( n1555 , n1554 );
not ( n1556 , n1555 );
buf ( n1557 , n878 );
buf ( n1558 , n883 );
nand ( n1559 , n1557 , n1558 );
buf ( n1560 , n1559 );
buf ( n1561 , n1560 );
buf ( n1562 , n936 );
buf ( n1563 , n968 );
and ( n1564 , n1562 , n1563 );
buf ( n1565 , n1564 );
buf ( n1566 , n1565 );
not ( n1567 , n1566 );
buf ( n1568 , n1567 );
buf ( n1569 , n1568 );
nand ( n1570 , n1561 , n1569 );
buf ( n1571 , n1570 );
not ( n1572 , n1571 );
or ( n1573 , n1556 , n1572 );
buf ( n1574 , n1039 );
buf ( n1575 , n1355 );
nand ( n1576 , n1574 , n1575 );
buf ( n1577 , n1576 );
not ( n1578 , n1577 );
nand ( n1579 , n1578 , n1565 );
nand ( n1580 , n1573 , n1579 );
not ( n1581 , n1580 );
buf ( n1582 , n849 );
not ( n1583 , n1582 );
buf ( n1584 , n821 );
nor ( n1585 , n1583 , n1584 );
buf ( n1586 , n1585 );
not ( n1587 , n1586 );
or ( n1588 , n1581 , n1587 );
buf ( n1589 , n1586 );
not ( n1590 , n1589 );
buf ( n1591 , n1590 );
not ( n1592 , n1591 );
buf ( n1593 , n1580 );
not ( n1594 , n1593 );
buf ( n1595 , n1594 );
not ( n1596 , n1595 );
or ( n1597 , n1592 , n1596 );
buf ( n1598 , n1500 );
not ( n1599 , n1598 );
buf ( n1600 , n812 );
not ( n1601 , n1600 );
buf ( n1602 , n1601 );
buf ( n1603 , n1602 );
not ( n1604 , n1603 );
buf ( n1605 , n908 );
nand ( n1606 , n1604 , n1605 );
buf ( n1607 , n1606 );
buf ( n1608 , n1607 );
not ( n1609 , n1608 );
buf ( n1610 , n1609 );
buf ( n1611 , n1610 );
not ( n1612 , n1611 );
or ( n1613 , n1599 , n1612 );
buf ( n1614 , n1607 );
not ( n1615 , n1614 );
buf ( n1616 , n936 );
not ( n1617 , n1616 );
buf ( n1618 , n1617 );
buf ( n1619 , n1618 );
not ( n1620 , n1619 );
or ( n1621 , n1615 , n1620 );
buf ( n1622 , n796 );
buf ( n1623 , n973 );
and ( n1624 , n1622 , n1623 );
buf ( n1625 , n1624 );
buf ( n1626 , n1625 );
nand ( n1627 , n1621 , n1626 );
buf ( n1628 , n1627 );
buf ( n1629 , n1628 );
nand ( n1630 , n1613 , n1629 );
buf ( n1631 , n1630 );
nand ( n1632 , n1597 , n1631 );
nand ( n1633 , n1588 , n1632 );
buf ( n1634 , n1633 );
xor ( n1635 , n1508 , n1551 );
xor ( n1636 , n1635 , n1634 );
buf ( n1637 , n1636 );
xor ( n1638 , n1508 , n1551 );
and ( n1639 , n1638 , n1634 );
and ( n1640 , n1508 , n1551 );
or ( n1641 , n1639 , n1640 );
buf ( n1642 , n1641 );
xor ( n1643 , n1413 , n1419 );
xor ( n1644 , n1643 , n1434 );
buf ( n1645 , n1644 );
buf ( n1646 , n1645 );
buf ( n1647 , n970 );
buf ( n1648 , n949 );
and ( n1649 , n1647 , n1648 );
buf ( n1650 , n1649 );
buf ( n1651 , n1650 );
buf ( n1652 , n1023 );
not ( n1653 , n1652 );
buf ( n1654 , n853 );
not ( n1655 , n1654 );
buf ( n1656 , n1655 );
buf ( n1657 , n1656 );
nor ( n1658 , n1653 , n1657 );
buf ( n1659 , n1658 );
buf ( n1660 , n1659 );
xor ( n1661 , n1651 , n1660 );
buf ( n1662 , n1342 );
not ( n1663 , n1662 );
buf ( n1664 , n1176 );
nor ( n1665 , n1663 , n1664 );
buf ( n1666 , n1665 );
buf ( n1667 , n1666 );
and ( n1668 , n1661 , n1667 );
and ( n1669 , n1651 , n1660 );
or ( n1670 , n1668 , n1669 );
buf ( n1671 , n1670 );
buf ( n1672 , n1671 );
xor ( n1673 , n1430 , n1425 );
buf ( n1674 , n1673 );
xor ( n1675 , n1672 , n1674 );
buf ( n1676 , n973 );
buf ( n1677 , n377 );
not ( n1678 , n1677 );
buf ( n1679 , n1618 );
nor ( n1680 , n1678 , n1679 );
buf ( n1681 , n1680 );
buf ( n1682 , n1681 );
and ( n1683 , n1676 , n1682 );
buf ( n1684 , n1683 );
buf ( n1685 , n1684 );
and ( n1686 , n1675 , n1685 );
and ( n1687 , n1672 , n1674 );
or ( n1688 , n1686 , n1687 );
buf ( n1689 , n1688 );
buf ( n1690 , n1689 );
buf ( n1691 , n1023 );
buf ( n1692 , n918 );
nand ( n1693 , n1691 , n1692 );
buf ( n1694 , n1693 );
buf ( n1695 , n1694 );
not ( n1696 , n1695 );
buf ( n1697 , n968 );
buf ( n1698 , n798 );
nand ( n1699 , n1697 , n1698 );
buf ( n1700 , n1699 );
buf ( n1701 , n1700 );
not ( n1702 , n1701 );
or ( n1703 , n1696 , n1702 );
buf ( n1704 , n1342 );
buf ( n1705 , n853 );
and ( n1706 , n1704 , n1705 );
buf ( n1707 , n1706 );
buf ( n1708 , n1707 );
nand ( n1709 , n1703 , n1708 );
buf ( n1710 , n1709 );
buf ( n1711 , n1710 );
buf ( n1712 , n1694 );
not ( n1713 , n1712 );
buf ( n1714 , n1713 );
buf ( n1715 , C1 );
buf ( n1716 , n1715 );
nand ( n1717 , n1711 , n1716 );
buf ( n1718 , n1717 );
buf ( n1719 , n1718 );
xor ( n1720 , n1391 , n1396 );
xor ( n1721 , n1720 , n1402 );
buf ( n1722 , n1721 );
buf ( n1723 , n1722 );
xor ( n1724 , n1719 , n1723 );
buf ( n1725 , n1350 );
buf ( n1726 , n377 );
nand ( n1727 , n1725 , n1726 );
buf ( n1728 , n1727 );
xnor ( n1729 , n1355 , n1728 );
buf ( n1730 , n1729 );
xor ( n1731 , n1724 , n1730 );
buf ( n1732 , n1731 );
buf ( n1733 , n1732 );
xor ( n1734 , n1646 , n1690 );
xor ( n1735 , n1734 , n1733 );
buf ( n1736 , n1735 );
xor ( n1737 , n1646 , n1690 );
and ( n1738 , n1737 , n1733 );
and ( n1739 , n1646 , n1690 );
or ( n1740 , n1738 , n1739 );
buf ( n1741 , n1740 );
xnor ( n1742 , n1707 , n1714 );
buf ( n1743 , n1742 );
buf ( n1744 , n1700 );
and ( n1745 , n1743 , n1744 );
nor ( n1746 , n1745 , C0 );
buf ( n1747 , n1746 );
buf ( n1748 , n1747 );
buf ( n1749 , n1355 );
buf ( n1750 , n918 );
and ( n1751 , n1749 , n1750 );
buf ( n1752 , n1751 );
buf ( n1753 , n1752 );
nand ( n1754 , n1516 , n377 );
buf ( n1755 , n1754 );
buf ( n1756 , n973 );
buf ( n1757 , n918 );
nand ( n1758 , n1756 , n1757 );
buf ( n1759 , n1758 );
buf ( n1760 , n1759 );
nor ( n1761 , n1755 , n1760 );
buf ( n1762 , n1761 );
buf ( n1763 , n1762 );
xor ( n1764 , n1753 , n1763 );
xor ( n1765 , n1676 , n1682 );
buf ( n1766 , n1765 );
buf ( n1767 , n1766 );
and ( n1768 , n1764 , n1767 );
and ( n1769 , n1753 , n1763 );
or ( n1770 , n1768 , n1769 );
buf ( n1771 , n1770 );
buf ( n1772 , n1771 );
xor ( n1773 , n1672 , n1674 );
xor ( n1774 , n1773 , n1685 );
buf ( n1775 , n1774 );
buf ( n1776 , n1775 );
xor ( n1777 , n1748 , n1772 );
xor ( n1778 , n1777 , n1776 );
buf ( n1779 , n1778 );
xor ( n1780 , n1748 , n1772 );
and ( n1781 , n1780 , n1776 );
and ( n1782 , n1748 , n1772 );
or ( n1783 , n1781 , n1782 );
buf ( n1784 , n1783 );
xor ( n1785 , n1386 , n1407 );
xor ( n1786 , n1785 , n1439 );
buf ( n1787 , n1786 );
buf ( n1788 , n1516 );
buf ( n1789 , n815 );
and ( n1790 , n1788 , n1789 );
buf ( n1791 , n1790 );
buf ( n1792 , n1791 );
xor ( n1793 , n1236 , n1240 );
and ( n1794 , n1793 , n1245 );
and ( n1795 , n1236 , n1240 );
or ( n1796 , n1794 , n1795 );
buf ( n1797 , n1796 );
xor ( n1798 , n1252 , n1259 );
and ( n1799 , n1798 , n1265 );
and ( n1800 , n1252 , n1259 );
or ( n1801 , n1799 , n1800 );
buf ( n1802 , n1801 );
buf ( n1803 , n1802 );
xor ( n1804 , n1792 , n1797 );
xor ( n1805 , n1804 , n1803 );
buf ( n1806 , n1805 );
xor ( n1807 , n1792 , n1797 );
and ( n1808 , n1807 , n1803 );
and ( n1809 , n1792 , n1797 );
or ( n1810 , n1808 , n1809 );
buf ( n1811 , n1810 );
xor ( n1812 , n1651 , n1660 );
xor ( n1813 , n1812 , n1667 );
buf ( n1814 , n1813 );
buf ( n1815 , n1814 );
buf ( n1816 , n1355 );
buf ( n1817 , n853 );
and ( n1818 , n1816 , n1817 );
buf ( n1819 , n1818 );
buf ( n1820 , n1819 );
buf ( n1821 , n1026 );
buf ( n1822 , n798 );
and ( n1823 , n1821 , n1822 );
buf ( n1824 , n1823 );
buf ( n1825 , n1824 );
xor ( n1826 , n1820 , n1825 );
buf ( n1827 , n815 );
buf ( n1828 , n377 );
nand ( n1829 , n1827 , n1828 );
buf ( n1830 , n1829 );
buf ( n1831 , n1830 );
buf ( n1832 , n949 );
not ( n1833 , n1832 );
buf ( n1834 , n1833 );
buf ( n1835 , n1834 );
nor ( n1836 , n1831 , n1835 );
buf ( n1837 , n1836 );
buf ( n1838 , n1837 );
and ( n1839 , n1826 , n1838 );
or ( n1840 , n1839 , C0 );
buf ( n1841 , n1840 );
buf ( n1842 , n1841 );
xor ( n1843 , n1753 , n1763 );
xor ( n1844 , n1843 , n1767 );
buf ( n1845 , n1844 );
buf ( n1846 , n1845 );
xor ( n1847 , n1815 , n1842 );
xor ( n1848 , n1847 , n1846 );
buf ( n1849 , n1848 );
xor ( n1850 , n1815 , n1842 );
and ( n1851 , n1850 , n1846 );
and ( n1852 , n1815 , n1842 );
or ( n1853 , n1851 , n1852 );
buf ( n1854 , n1853 );
buf ( n1855 , n849 );
not ( n1856 , n1855 );
buf ( n1857 , n1856 );
buf ( n1858 , n1857 );
not ( n1859 , n1421 );
buf ( n1860 , n1859 );
nor ( n1861 , n1858 , n1860 );
buf ( n1862 , n1861 );
buf ( n1863 , n1862 );
buf ( n1864 , n1007 );
buf ( n1865 , n815 );
and ( n1866 , n1864 , n1865 );
buf ( n1867 , n1866 );
buf ( n1868 , n1867 );
buf ( n1869 , n849 );
not ( n1870 , n1869 );
buf ( n1871 , n1618 );
nor ( n1872 , n1870 , n1871 );
buf ( n1873 , n1872 );
buf ( n1874 , n1873 );
xor ( n1875 , n1868 , n1874 );
buf ( n1876 , n1039 );
buf ( n1877 , n1516 );
and ( n1878 , n1876 , n1877 );
buf ( n1879 , n1878 );
buf ( n1880 , n1879 );
and ( n1881 , n1875 , n1880 );
and ( n1882 , n1868 , n1874 );
or ( n1883 , n1881 , n1882 );
buf ( n1884 , n1883 );
buf ( n1885 , n1884 );
buf ( n1886 , n1007 );
buf ( n1887 , n1516 );
and ( n1888 , n1886 , n1887 );
buf ( n1889 , n1888 );
buf ( n1890 , n1889 );
buf ( n1891 , n1857 );
not ( n1892 , n1891 );
buf ( n1893 , n1892 );
buf ( n1894 , n1893 );
xor ( n1895 , n1890 , n1894 );
buf ( n1896 , n1039 );
buf ( n1897 , n1500 );
and ( n1898 , n1896 , n1897 );
buf ( n1899 , n1898 );
buf ( n1900 , n1899 );
xor ( n1901 , n1895 , n1900 );
buf ( n1902 , n1901 );
buf ( n1903 , n1902 );
xor ( n1904 , n1863 , n1885 );
xor ( n1905 , n1904 , n1903 );
buf ( n1906 , n1905 );
xor ( n1907 , n1863 , n1885 );
and ( n1908 , n1907 , n1903 );
and ( n1909 , n1863 , n1885 );
or ( n1910 , n1908 , n1909 );
buf ( n1911 , n1910 );
buf ( n1912 , n1421 );
not ( n1913 , n1912 );
buf ( n1914 , n1495 );
not ( n1915 , n1914 );
buf ( n1916 , n1915 );
buf ( n1917 , n1916 );
not ( n1918 , n1917 );
or ( n1919 , n1913 , n1918 );
buf ( n1920 , n1504 );
not ( n1921 , n1920 );
buf ( n1922 , n1921 );
buf ( n1923 , n1922 );
nand ( n1924 , n1919 , n1923 );
buf ( n1925 , n1924 );
buf ( n1926 , n1925 );
xor ( n1927 , n1868 , n1874 );
xor ( n1928 , n1927 , n1880 );
buf ( n1929 , n1928 );
buf ( n1930 , n1929 );
xor ( n1931 , n1513 , n1520 );
and ( n1932 , n1931 , n1548 );
and ( n1933 , n1513 , n1520 );
or ( n1934 , n1932 , n1933 );
buf ( n1935 , n1934 );
buf ( n1936 , n1935 );
xor ( n1937 , n1926 , n1930 );
xor ( n1938 , n1937 , n1936 );
buf ( n1939 , n1938 );
xor ( n1940 , n1926 , n1930 );
and ( n1941 , n1940 , n1936 );
and ( n1942 , n1926 , n1930 );
or ( n1943 , n1941 , n1942 );
buf ( n1944 , n1943 );
buf ( n1945 , n1246 );
not ( n1946 , n1945 );
buf ( n1947 , n1270 );
nand ( n1948 , n1946 , n1947 );
buf ( n1949 , n1948 );
buf ( n1950 , n1949 );
buf ( n1951 , n1232 );
nand ( n1952 , n1267 , n1246 );
buf ( n1953 , n1952 );
not ( n1954 , n1950 );
not ( n1955 , n1951 );
or ( n1956 , n1954 , n1955 );
nand ( n1957 , n1956 , n1953 );
buf ( n1958 , n1957 );
xor ( n1959 , n1719 , n1723 );
and ( n1960 , n1959 , n1730 );
and ( n1961 , n1719 , n1723 );
or ( n1962 , n1960 , n1961 );
buf ( n1963 , n1962 );
buf ( n1964 , n1355 );
buf ( n1965 , n798 );
nand ( n1966 , n1964 , n1965 );
buf ( n1967 , n1966 );
buf ( n1968 , n1967 );
buf ( n1969 , n973 );
buf ( n1970 , n853 );
nand ( n1971 , n1969 , n1970 );
buf ( n1972 , n1971 );
buf ( n1973 , n1972 );
nand ( n1974 , n1968 , n1973 );
buf ( n1975 , n1974 );
not ( n1976 , n1975 );
buf ( n1977 , n949 );
buf ( n1978 , n918 );
and ( n1979 , n1977 , n1978 );
buf ( n1980 , n1979 );
not ( n1981 , n1980 );
or ( n1982 , n1976 , n1981 );
nand ( n1983 , n1982 , C1 );
buf ( n1984 , n1983 );
xor ( n1985 , n1759 , n1754 );
buf ( n1986 , n1985 );
xor ( n1987 , n1820 , n1825 );
xor ( n1988 , n1987 , n1838 );
buf ( n1989 , n1988 );
buf ( n1990 , n1989 );
xor ( n1991 , n1984 , n1986 );
xor ( n1992 , n1991 , n1990 );
buf ( n1993 , n1992 );
xor ( n1994 , n1984 , n1986 );
and ( n1995 , n1994 , n1990 );
and ( n1996 , n1984 , n1986 );
or ( n1997 , n1995 , n1996 );
buf ( n1998 , n1997 );
xor ( n1999 , n1531 , n1525 );
xor ( n2000 , n1999 , n1539 );
buf ( n2001 , n2000 );
and ( n2002 , n1631 , n1586 );
not ( n2003 , n1631 );
or ( n2004 , n1857 , n821 );
and ( n2005 , n2003 , n2004 );
nor ( n2006 , n2002 , n2005 );
buf ( n2007 , n2006 );
not ( n2008 , n2007 );
buf ( n2009 , n1595 );
not ( n2010 , n2009 );
and ( n2011 , n2008 , n2010 );
buf ( n2012 , n1595 );
buf ( n2013 , n2006 );
and ( n2014 , n2012 , n2013 );
nor ( n2015 , n2011 , n2014 );
buf ( n2016 , n2015 );
buf ( n2017 , n2016 );
nand ( n2018 , n2001 , n2017 );
buf ( n2019 , n2018 );
buf ( n2020 , n1967 );
not ( n2021 , n2020 );
buf ( n2022 , n1980 );
not ( n2023 , n2022 );
buf ( n2024 , n1972 );
not ( n2025 , n2024 );
or ( n2026 , n2023 , n2025 );
buf ( n2027 , n1972 );
buf ( n2028 , n1980 );
or ( n2029 , n2027 , n2028 );
nand ( n2030 , n2026 , n2029 );
buf ( n2031 , n2030 );
buf ( n2032 , n2031 );
not ( n2033 , n2032 );
or ( n2034 , n2021 , n2033 );
buf ( n2035 , n2031 );
buf ( n2036 , n1967 );
or ( n2037 , n2035 , n2036 );
nand ( n2038 , n2034 , n2037 );
buf ( n2039 , n2038 );
buf ( n2040 , n2039 );
buf ( n2041 , n949 );
buf ( n2042 , n853 );
and ( n2043 , n2041 , n2042 );
buf ( n2044 , n2043 );
buf ( n2045 , n2044 );
buf ( n2046 , n1026 );
buf ( n2047 , n377 );
and ( n2048 , n2046 , n2047 );
buf ( n2049 , n2048 );
buf ( n2050 , n2049 );
and ( n2051 , n2045 , n2050 );
buf ( n2052 , n2051 );
buf ( n2053 , n2052 );
buf ( n2054 , n1830 );
buf ( n2055 , n1834 );
and ( n2056 , n2054 , n2055 );
not ( n2057 , n2054 );
buf ( n2058 , n949 );
and ( n2059 , n2057 , n2058 );
nor ( n2060 , n2056 , n2059 );
buf ( n2061 , n2060 );
buf ( n2062 , n2061 );
xor ( n2063 , n2040 , n2053 );
xor ( n2064 , n2063 , n2062 );
buf ( n2065 , n2064 );
xor ( n2066 , n2040 , n2053 );
and ( n2067 , n2066 , n2062 );
and ( n2068 , n2040 , n2053 );
or ( n2069 , n2067 , n2068 );
buf ( n2070 , n2069 );
buf ( n2071 , n402 );
buf ( n2072 , n970 );
buf ( n2073 , n377 );
and ( n2074 , n2072 , n2073 );
buf ( n2075 , n2074 );
buf ( n2076 , n2075 );
and ( n2077 , n2071 , n2076 );
buf ( n2078 , n2077 );
buf ( n2079 , n2078 );
buf ( n2080 , n949 );
buf ( n2081 , n798 );
and ( n2082 , n2080 , n2081 );
buf ( n2083 , n2082 );
buf ( n2084 , n2083 );
buf ( n2085 , n918 );
buf ( n2086 , n918 );
buf ( n2087 , n853 );
nand ( n2088 , n2086 , n2087 );
buf ( n2089 , n2088 );
buf ( n2090 , n2089 );
xor ( n2091 , n2085 , n2090 );
buf ( n2092 , n1359 );
xor ( n2093 , n2091 , n2092 );
buf ( n2094 , n2093 );
buf ( n2095 , n2094 );
xor ( n2096 , n2079 , n2084 );
xor ( n2097 , n2096 , n2095 );
buf ( n2098 , n2097 );
xor ( n2099 , n2079 , n2084 );
and ( n2100 , n2099 , n2095 );
or ( n2101 , n2100 , C0 );
buf ( n2102 , n2101 );
buf ( n2103 , n973 );
buf ( n2104 , n798 );
and ( n2105 , n2103 , n2104 );
buf ( n2106 , n2105 );
buf ( n2107 , n2106 );
buf ( n2108 , n1359 );
not ( n2109 , n2108 );
buf ( n2110 , n918 );
nand ( n2111 , n2109 , n2110 );
buf ( n2112 , n2111 );
buf ( n2113 , n2112 );
buf ( n2114 , n2089 );
nand ( n2115 , n2113 , n2114 );
buf ( n2116 , n2115 );
buf ( n2117 , n2116 );
xor ( n2118 , n2045 , n2050 );
buf ( n2119 , n2118 );
buf ( n2120 , n2119 );
xor ( n2121 , n2107 , n2117 );
xor ( n2122 , n2121 , n2120 );
buf ( n2123 , n2122 );
xor ( n2124 , n2107 , n2117 );
and ( n2125 , n2124 , n2120 );
or ( n2126 , n2125 , C0 );
buf ( n2127 , n2126 );
buf ( n2128 , n1039 );
buf ( n2129 , n1421 );
and ( n2130 , n2128 , n2129 );
buf ( n2131 , n2130 );
buf ( n2132 , n2131 );
buf ( n2133 , n1500 );
buf ( n2134 , n1007 );
and ( n2135 , n2133 , n2134 );
buf ( n2136 , n2135 );
buf ( n2137 , n2136 );
xor ( n2138 , n1890 , n1894 );
and ( n2139 , n2138 , n1900 );
and ( n2140 , n1890 , n1894 );
or ( n2141 , n2139 , n2140 );
buf ( n2142 , n2141 );
buf ( n2143 , n2142 );
xor ( n2144 , n2132 , n2137 );
xor ( n2145 , n2144 , n2143 );
buf ( n2146 , n2145 );
xor ( n2147 , n2132 , n2137 );
and ( n2148 , n2147 , n2143 );
and ( n2149 , n2132 , n2137 );
or ( n2150 , n2148 , n2149 );
buf ( n2151 , n2150 );
xor ( n2152 , n1347 , n1363 );
xor ( n2153 , n2152 , n1367 );
buf ( n2154 , n2153 );
buf ( n2155 , n796 );
buf ( n2156 , n949 );
and ( n2157 , n2155 , n2156 );
buf ( n2158 , n2157 );
buf ( n2159 , n2158 );
buf ( n2160 , n936 );
buf ( n2161 , n1342 );
and ( n2162 , n2160 , n2161 );
buf ( n2163 , n2162 );
buf ( n2164 , n2163 );
xor ( n2165 , n2159 , n2164 );
buf ( n2166 , n908 );
buf ( n2167 , n1023 );
and ( n2168 , n2166 , n2167 );
buf ( n2169 , n2168 );
buf ( n2170 , n2169 );
xor ( n2171 , n2165 , n2170 );
buf ( n2172 , n2171 );
buf ( n2173 , n2172 );
not ( n2174 , n2173 );
buf ( n2175 , n2174 );
buf ( n2176 , n2175 );
buf ( n2177 , n1516 );
buf ( n2178 , n796 );
buf ( n2179 , n918 );
and ( n2180 , n2178 , n2179 );
buf ( n2181 , n2180 );
buf ( n2182 , n2181 );
xor ( n2183 , n2177 , n2182 );
buf ( n2184 , n908 );
buf ( n2185 , n883 );
and ( n2186 , n2184 , n2185 );
buf ( n2187 , n2186 );
buf ( n2188 , n2187 );
and ( n2189 , n2183 , n2188 );
and ( n2190 , n2177 , n2182 );
or ( n2191 , n2189 , n2190 );
buf ( n2192 , n2191 );
buf ( n2193 , n2192 );
buf ( n2194 , n2175 );
buf ( n2195 , n2192 );
not ( n2196 , n2176 );
not ( n2197 , n2193 );
and ( n2198 , n2196 , n2197 );
and ( n2199 , n2194 , n2195 );
nor ( n2200 , n2198 , n2199 );
buf ( n2201 , n2200 );
buf ( n2202 , n2000 );
not ( n2203 , n2202 );
buf ( n2204 , n2203 );
and ( n2205 , n1103 , n1085 );
buf ( n2206 , n2205 );
buf ( n2207 , n872 );
buf ( n2208 , n949 );
and ( n2209 , n2207 , n2208 );
buf ( n2210 , n2209 );
buf ( n2211 , n2210 );
buf ( n2212 , n849 );
buf ( n2213 , n973 );
and ( n2214 , n2212 , n2213 );
buf ( n2215 , n2214 );
buf ( n2216 , n2215 );
xor ( n2217 , n2206 , n2211 );
xor ( n2218 , n2217 , n2216 );
buf ( n2219 , n2218 );
xor ( n2220 , n2206 , n2211 );
and ( n2221 , n2220 , n2216 );
and ( n2222 , n2206 , n2211 );
or ( n2223 , n2221 , n2222 );
buf ( n2224 , n2223 );
buf ( n2225 , n2175 );
buf ( n2226 , n2192 );
not ( n2227 , n2226 );
buf ( n2228 , n2227 );
buf ( n2229 , n2228 );
nand ( n2230 , n2225 , n2229 );
buf ( n2231 , n2230 );
xor ( n2232 , n2159 , n2164 );
and ( n2233 , n2232 , n2170 );
and ( n2234 , n2159 , n2164 );
or ( n2235 , n2233 , n2234 );
buf ( n2236 , n2235 );
buf ( n2237 , n1039 );
buf ( n2238 , n1859 );
not ( n2239 , n2238 );
buf ( n2240 , n1007 );
nand ( n2241 , n2239 , n2240 );
buf ( n2242 , n2241 );
buf ( n2243 , n2242 );
not ( n2244 , n2243 );
buf ( n2245 , n2244 );
buf ( n2246 , n2245 );
buf ( n2247 , n1893 );
buf ( n2248 , n1039 );
nand ( n2249 , n2247 , n2248 );
buf ( n2250 , n2249 );
buf ( n2251 , n2250 );
not ( n2252 , n2237 );
not ( n2253 , n2246 );
or ( n2254 , n2252 , n2253 );
nand ( n2255 , n2254 , n2251 );
buf ( n2256 , n2255 );
xor ( n2257 , n2071 , n2076 );
buf ( n2258 , n2257 );
buf ( n2259 , n404 );
buf ( n2260 , n918 );
buf ( n2261 , n377 );
and ( n2262 , n2260 , n2261 );
buf ( n2263 , n2262 );
buf ( n2264 , n2263 );
xor ( n2265 , n2259 , n2264 );
buf ( n2266 , n2265 );
and ( n2267 , n2259 , n2264 );
buf ( n2268 , n2267 );
buf ( n2269 , n405 );
buf ( n2270 , n798 );
xor ( n2271 , n2269 , n2270 );
buf ( n2272 , n2271 );
and ( n2273 , n2269 , n2270 );
buf ( n2274 , n2273 );
buf ( n2275 , n403 );
buf ( n2276 , n853 );
xor ( n2277 , n2275 , n2276 );
buf ( n2278 , n2277 );
and ( n2279 , n2275 , n2276 );
buf ( n2280 , n2279 );
buf ( n2281 , n1565 );
buf ( n2282 , n1560 );
buf ( n2283 , n1577 );
buf ( n2284 , n1565 );
not ( n2285 , n2281 );
not ( n2286 , n2282 );
or ( n2287 , n2285 , n2286 );
or ( n2288 , n2283 , n2284 );
nand ( n2289 , n2287 , n2288 );
buf ( n2290 , n2289 );
buf ( n2291 , n1893 );
buf ( n2292 , n1007 );
and ( n2293 , n2291 , n2292 );
buf ( n2294 , n2293 );
buf ( n2295 , n949 );
buf ( n2296 , n377 );
and ( n2297 , n2295 , n2296 );
buf ( n2298 , n2297 );
buf ( n2299 , n1039 );
buf ( n2300 , n973 );
and ( n2301 , n2299 , n2300 );
buf ( n2302 , n2301 );
buf ( n2303 , n1893 );
buf ( n2304 , n1355 );
and ( n2305 , n2303 , n2304 );
buf ( n2306 , n2305 );
buf ( n2307 , n2175 );
buf ( n2308 , n2228 );
or ( n2309 , n2307 , n2308 );
buf ( n2310 , n2309 );
buf ( n2311 , n1500 );
buf ( n2312 , n1625 );
buf ( n2313 , n1610 );
xor ( n2314 , n2311 , n2312 );
xor ( n2315 , n2314 , n2313 );
buf ( n2316 , n2315 );
buf ( n2317 , n377 );
buf ( n2318 , n1656 );
not ( n2319 , n2317 );
nor ( n2320 , n2319 , n2318 );
buf ( n2321 , n2320 );
not ( n2322 , n2302 );
xor ( n2323 , n2322 , n2306 );
xnor ( n2324 , n2323 , n2224 );
not ( n2325 , n1196 );
nand ( n2326 , n2325 , n1204 );
not ( n2327 , n2326 );
not ( n2328 , n1209 );
or ( n2329 , n2327 , n2328 );
not ( n2330 , n1204 );
nand ( n2331 , n2330 , n1196 );
nand ( n2332 , n2329 , n2331 );
not ( n2333 , n2332 );
xor ( n2334 , n2177 , n2182 );
xor ( n2335 , n2334 , n2188 );
buf ( n2336 , n2335 );
not ( n2337 , n2336 );
not ( n2338 , n2219 );
nand ( n2339 , n2337 , n2338 );
not ( n2340 , n2339 );
or ( n2341 , n2333 , n2340 );
not ( n2342 , n2338 );
nand ( n2343 , n2342 , n2336 );
nand ( n2344 , n2341 , n2343 );
xor ( n2345 , n2324 , n2344 );
not ( n2346 , n2201 );
not ( n2347 , n2346 );
not ( n2348 , n1811 );
not ( n2349 , n2348 );
or ( n2350 , n2347 , n2349 );
nand ( n2351 , n1811 , n2201 );
nand ( n2352 , n2350 , n2351 );
xor ( n2353 , n2345 , n2352 );
buf ( n2354 , n2353 );
not ( n2355 , n1958 );
not ( n2356 , n1806 );
nand ( n2357 , n2355 , n2356 );
not ( n2358 , n2357 );
xor ( n2359 , n2337 , n2342 );
xnor ( n2360 , n2359 , n2332 );
not ( n2361 , n2360 );
or ( n2362 , n2358 , n2361 );
nand ( n2363 , n1958 , n1806 );
nand ( n2364 , n2362 , n2363 );
buf ( n2365 , n2364 );
nor ( n2366 , n2354 , n2365 );
buf ( n2367 , n2366 );
buf ( n2368 , n2367 );
not ( n2369 , n2368 );
not ( n2370 , n2204 );
not ( n2371 , n2016 );
not ( n2372 , n2371 );
or ( n2373 , n2370 , n2372 );
nand ( n2374 , n2373 , n2019 );
xor ( n2375 , n2236 , n2316 );
xor ( n2376 , n2290 , n1555 );
and ( n2377 , n2375 , n2376 );
and ( n2378 , n2236 , n2316 );
or ( n2379 , n2377 , n2378 );
xor ( n2380 , n2374 , n2379 );
not ( n2381 , n2302 );
not ( n2382 , n2306 );
or ( n2383 , n2381 , n2382 );
not ( n2384 , n2322 );
not ( n2385 , n2306 );
not ( n2386 , n2385 );
or ( n2387 , n2384 , n2386 );
nand ( n2388 , n2387 , n2224 );
nand ( n2389 , n2383 , n2388 );
xor ( n2390 , n2236 , n2316 );
xor ( n2391 , n2390 , n2376 );
xor ( n2392 , n2389 , n2391 );
not ( n2393 , n2231 );
not ( n2394 , n1811 );
or ( n2395 , n2393 , n2394 );
nand ( n2396 , n2395 , n2310 );
and ( n2397 , n2392 , n2396 );
and ( n2398 , n2389 , n2391 );
or ( n2399 , n2397 , n2398 );
nor ( n2400 , n2380 , n2399 );
buf ( n2401 , n2400 );
not ( n2402 , n2401 );
not ( n2403 , n1287 );
not ( n2404 , n1806 );
not ( n2405 , n2355 );
or ( n2406 , n2404 , n2405 );
nand ( n2407 , n1958 , n2356 );
nand ( n2408 , n2406 , n2407 );
and ( n2409 , n2408 , n2360 );
not ( n2410 , n2408 );
not ( n2411 , n2360 );
and ( n2412 , n2410 , n2411 );
nor ( n2413 , n2409 , n2412 );
not ( n2414 , n2413 );
nand ( n2415 , n2403 , n2414 );
buf ( n2416 , n2415 );
xor ( n2417 , n2389 , n2391 );
xor ( n2418 , n2417 , n2396 );
buf ( n2419 , n2418 );
not ( n2420 , n2419 );
buf ( n2421 , n2324 );
or ( n2422 , n2352 , n2421 );
buf ( n2423 , n2344 );
and ( n2424 , n2422 , n2423 );
and ( n2425 , n2352 , n2421 );
nor ( n2426 , n2424 , n2425 );
buf ( n2427 , n2426 );
nand ( n2428 , n2420 , n2427 );
buf ( n2429 , n2428 );
buf ( n2430 , n2429 );
nand ( n2431 , n2369 , n2402 , n2416 , n2430 );
buf ( n2432 , n2431 );
buf ( n2433 , n2432 );
buf ( n2434 , n1642 );
not ( n2435 , n2434 );
buf ( n2436 , n2435 );
buf ( n2437 , n2436 );
buf ( n2438 , n1939 );
not ( n2439 , n2438 );
buf ( n2440 , n2439 );
buf ( n2441 , n2440 );
or ( n2442 , n2437 , n2441 );
buf ( n2443 , n2442 );
not ( n2444 , n2443 );
not ( n2445 , n2371 );
not ( n2446 , n2000 );
or ( n2447 , n2445 , n2446 );
not ( n2448 , n2204 );
not ( n2449 , n2016 );
or ( n2450 , n2448 , n2449 );
nand ( n2451 , n2450 , n2379 );
nand ( n2452 , n2447 , n2451 );
buf ( n2453 , n2452 );
buf ( n2454 , n1637 );
nand ( n2455 , n2453 , n2454 );
buf ( n2456 , n2455 );
buf ( n2457 , n2456 );
not ( n2458 , n2457 );
buf ( n2459 , n2436 );
buf ( n2460 , n2440 );
nand ( n2461 , n2459 , n2460 );
buf ( n2462 , n2461 );
buf ( n2463 , n2462 );
nand ( n2464 , n2458 , n2463 );
buf ( n2465 , n2464 );
not ( n2466 , n2465 );
or ( n2467 , n2444 , n2466 );
or ( n2468 , n2146 , n1911 );
not ( n2469 , n1906 );
not ( n2470 , n1944 );
nand ( n2471 , n2469 , n2470 );
nand ( n2472 , n2468 , n2471 );
not ( n2473 , n2472 );
nand ( n2474 , n2467 , n2473 );
buf ( n2475 , n2474 );
nand ( n2476 , n1944 , n1906 );
not ( n2477 , n2468 );
or ( n2478 , n2476 , n2477 );
nand ( n2479 , n2146 , n1911 );
nand ( n2480 , n2478 , n2479 );
buf ( n2481 , n2480 );
xor ( n2482 , n2250 , n1039 );
xor ( n2483 , n2482 , n2242 );
nand ( n2484 , n2151 , n2483 );
buf ( n2485 , n2484 );
buf ( n2486 , n2256 );
buf ( n2487 , n2294 );
nor ( n2488 , n2486 , n2487 );
buf ( n2489 , n2488 );
buf ( n2490 , n2489 );
or ( n2491 , n2485 , n2490 );
buf ( n2492 , n2256 );
buf ( n2493 , n2294 );
nand ( n2494 , n2492 , n2493 );
buf ( n2495 , n2494 );
buf ( n2496 , n2495 );
nand ( n2497 , n2491 , n2496 );
buf ( n2498 , n2497 );
buf ( n2499 , n2498 );
nor ( n2500 , n2481 , n2499 );
buf ( n2501 , n2500 );
buf ( n2502 , n2501 );
nand ( n2503 , n2433 , n2475 , n2502 );
buf ( n2504 , n2503 );
buf ( n2505 , n2504 );
buf ( n2506 , n1195 );
not ( n2507 , n2506 );
buf ( n2508 , n1282 );
not ( n2509 , n2508 );
and ( n2510 , n2507 , n2509 );
buf ( n2511 , n1190 );
not ( n2512 , n2511 );
buf ( n2513 , n2512 );
buf ( n2514 , n2513 );
buf ( n2515 , n1382 );
not ( n2516 , n2515 );
buf ( n2517 , n2516 );
buf ( n2518 , n2517 );
and ( n2519 , n2514 , n2518 );
nor ( n2520 , n2510 , n2519 );
buf ( n2521 , n2520 );
buf ( n2522 , n1490 );
buf ( n2523 , n1471 );
nor ( n2524 , n2522 , n2523 );
buf ( n2525 , n2524 );
buf ( n2526 , n2525 );
buf ( n2527 , n1466 );
xor ( n2528 , n2154 , n1963 );
and ( n2529 , n2528 , n1787 );
and ( n2530 , n2154 , n1963 );
or ( n2531 , n2529 , n2530 );
buf ( n2532 , n2531 );
nor ( n2533 , n2527 , n2532 );
buf ( n2534 , n2533 );
buf ( n2535 , n2534 );
nor ( n2536 , n2526 , n2535 );
buf ( n2537 , n2536 );
nand ( n2538 , n2521 , n2537 );
nand ( n2539 , n2538 , n2474 , n2501 );
buf ( n2540 , n2539 );
buf ( n2541 , n2498 );
not ( n2542 , n2541 );
buf ( n2543 , n2489 );
not ( n2544 , n2543 );
buf ( n2545 , n2151 );
buf ( n2546 , n2483 );
or ( n2547 , n2545 , n2546 );
buf ( n2548 , n2547 );
buf ( n2549 , n2548 );
nand ( n2550 , n2544 , n2549 );
buf ( n2551 , n2550 );
buf ( n2552 , n2551 );
nand ( n2553 , n2542 , n2552 );
buf ( n2554 , n2553 );
buf ( n2555 , n2554 );
and ( n2556 , n2505 , n2540 , n2555 );
buf ( n2557 , n2556 );
buf ( n2558 , n2557 );
not ( n2559 , n1741 );
xor ( n2560 , n2154 , n1963 );
xor ( n2561 , n2560 , n1787 );
not ( n2562 , n2561 );
and ( n2563 , n2559 , n2562 );
nor ( n2564 , n1736 , n1784 );
nor ( n2565 , n2563 , n2564 );
not ( n2566 , n2565 );
buf ( n2567 , n1779 );
buf ( n2568 , n1854 );
nor ( n2569 , n2567 , n2568 );
buf ( n2570 , n2569 );
buf ( n2571 , n1849 );
buf ( n2572 , n1998 );
nand ( n2573 , n2571 , n2572 );
buf ( n2574 , n2573 );
or ( n2575 , n2570 , n2574 );
buf ( n2576 , n1779 );
buf ( n2577 , n1854 );
nand ( n2578 , n2576 , n2577 );
buf ( n2579 , n2578 );
nand ( n2580 , n2575 , n2579 );
not ( n2581 , n2580 );
or ( n2582 , n2566 , n2581 );
not ( n2583 , n2561 );
not ( n2584 , n1741 );
nand ( n2585 , n2583 , n2584 );
and ( n2586 , n1736 , n1784 );
and ( n2587 , n2585 , n2586 );
buf ( n2588 , n2561 );
buf ( n2589 , n1741 );
and ( n2590 , n2588 , n2589 );
buf ( n2591 , n2590 );
nor ( n2592 , n2587 , n2591 );
nand ( n2593 , n2582 , n2592 );
buf ( n2594 , n2593 );
buf ( n2595 , n2501 );
not ( n2596 , n2595 );
buf ( n2597 , n2596 );
buf ( n2598 , n2597 );
nor ( n2599 , n2594 , n2598 );
buf ( n2600 , n2599 );
buf ( n2601 , n2600 );
not ( n2602 , n2570 );
not ( n2603 , n2602 );
buf ( n2604 , n1849 );
buf ( n2605 , n1998 );
nor ( n2606 , n2604 , n2605 );
buf ( n2607 , n2606 );
buf ( n2608 , n2607 );
nor ( n2609 , n2603 , n2608 );
buf ( n2610 , n2123 );
buf ( n2611 , n2102 );
nor ( n2612 , n2610 , n2611 );
buf ( n2613 , n2612 );
buf ( n2614 , n2613 );
buf ( n2615 , n2098 );
and ( n2616 , n2280 , n2258 );
buf ( n2617 , n2616 );
nand ( n2618 , n2615 , n2617 );
buf ( n2619 , n2618 );
buf ( n2620 , n2619 );
or ( n2621 , n2614 , n2620 );
buf ( n2622 , n2123 );
buf ( n2623 , n2102 );
nand ( n2624 , n2622 , n2623 );
buf ( n2625 , n2624 );
buf ( n2626 , n2625 );
nand ( n2627 , n2621 , n2626 );
buf ( n2628 , n2627 );
not ( n2629 , n2628 );
buf ( n2630 , n1993 );
buf ( n2631 , n2070 );
nor ( n2632 , n2630 , n2631 );
buf ( n2633 , n2632 );
buf ( n2634 , n2633 );
buf ( n2635 , n2065 );
buf ( n2636 , n2127 );
nor ( n2637 , n2635 , n2636 );
buf ( n2638 , n2637 );
buf ( n2639 , n2638 );
nor ( n2640 , n2634 , n2639 );
buf ( n2641 , n2640 );
not ( n2642 , n2641 );
or ( n2643 , n2629 , n2642 );
buf ( n2644 , n2633 );
not ( n2645 , n2644 );
buf ( n2646 , n2645 );
buf ( n2647 , n2646 );
buf ( n2648 , n2127 );
buf ( n2649 , n2065 );
and ( n2650 , n2648 , n2649 );
buf ( n2651 , n2650 );
buf ( n2652 , n2651 );
and ( n2653 , n2647 , n2652 );
buf ( n2654 , n1993 );
buf ( n2655 , n2070 );
and ( n2656 , n2654 , n2655 );
nor ( n2657 , n2653 , n2656 );
buf ( n2658 , n2657 );
nand ( n2659 , n2643 , n2658 );
nand ( n2660 , n2565 , n2609 , n2659 );
buf ( n2661 , n2660 );
buf ( n2662 , n2474 );
nor ( n2663 , n2570 , n2608 );
not ( n2664 , n2638 );
or ( n2665 , n2098 , n2616 );
or ( n2666 , n2123 , n2102 );
xor ( n2667 , n2278 , n2298 );
buf ( n2668 , n2667 );
not ( n2669 , n2668 );
buf ( n2670 , n2268 );
not ( n2671 , n2670 );
and ( n2672 , n2669 , n2671 );
xor ( n2673 , n2280 , n2258 );
buf ( n2674 , n2673 );
and ( n2675 , n2278 , n2298 );
buf ( n2676 , n2675 );
nor ( n2677 , n2674 , n2676 );
buf ( n2678 , n2677 );
buf ( n2679 , n2678 );
nor ( n2680 , n2672 , n2679 );
buf ( n2681 , n2680 );
buf ( n2682 , n2681 );
buf ( n2683 , n2266 );
buf ( n2684 , n2274 );
nor ( n2685 , n2683 , n2684 );
buf ( n2686 , n2685 );
buf ( n2687 , n2686 );
buf ( n2688 , n406 );
not ( n2689 , n2688 );
and ( n2690 , C1 , n2689 );
buf ( n2691 , n407 );
buf ( n2692 , n408 );
buf ( n2693 , n377 );
buf ( n2694 , n409 );
nand ( n2695 , n2691 , n2692 , n2693 , n2694 );
buf ( n2696 , n2695 );
buf ( n2697 , n2696 );
nor ( n2698 , n2690 , n2697 );
buf ( n2699 , n2698 );
buf ( n2700 , n2699 );
nor ( n2701 , C0 , n2700 );
buf ( n2702 , n2701 );
buf ( n2703 , n2702 );
buf ( n2704 , n2321 );
buf ( n2705 , n2272 );
nor ( n2706 , n2704 , n2705 );
buf ( n2707 , n2706 );
buf ( n2708 , n2707 );
nor ( n2709 , n2687 , n2703 , n2708 );
buf ( n2710 , n2709 );
buf ( n2711 , n2710 );
nand ( n2712 , n2682 , n2711 );
buf ( n2713 , n2712 );
buf ( n2714 , n2713 );
buf ( n2715 , n2686 );
not ( n2716 , n2715 );
buf ( n2717 , n2716 );
buf ( n2718 , n2717 );
buf ( n2719 , n2321 );
buf ( n2720 , n2272 );
and ( n2721 , n2718 , n2719 , n2720 );
buf ( n2722 , n2266 );
buf ( n2723 , n2274 );
and ( n2724 , n2722 , n2723 );
nor ( n2725 , n2721 , n2724 );
buf ( n2726 , n2725 );
buf ( n2727 , n2726 );
not ( n2728 , n2727 );
buf ( n2729 , n2681 );
nand ( n2730 , n2728 , n2729 );
buf ( n2731 , n2730 );
buf ( n2732 , n2731 );
buf ( n2733 , n2678 );
not ( n2734 , n2733 );
buf ( n2735 , n2734 );
buf ( n2736 , n2735 );
buf ( n2737 , n2667 );
buf ( n2738 , n2268 );
and ( n2739 , n2736 , n2737 , n2738 );
buf ( n2740 , n2673 );
buf ( n2741 , n2675 );
and ( n2742 , n2740 , n2741 );
nor ( n2743 , n2739 , n2742 );
buf ( n2744 , n2743 );
buf ( n2745 , n2744 );
nand ( n2746 , n2714 , n2732 , n2745 );
buf ( n2747 , n2746 );
nand ( n2748 , n2665 , n2666 , n2747 );
nor ( n2749 , n2748 , n2633 );
nand ( n2750 , n2664 , n2749 );
nor ( n2751 , n2564 , n2750 );
nand ( n2752 , n2663 , n2751 , n2585 );
buf ( n2753 , n2752 );
nand ( n2754 , n2601 , n2661 , n2662 , n2753 );
buf ( n2755 , n2754 );
buf ( n2756 , n2755 );
buf ( n2757 , n2474 );
buf ( n2758 , n2452 );
buf ( n2759 , n1637 );
or ( n2760 , n2758 , n2759 );
buf ( n2761 , n2760 );
buf ( n2762 , n2761 );
buf ( n2763 , n2462 );
nand ( n2764 , n2762 , n2763 );
buf ( n2765 , n2764 );
buf ( n2766 , n2765 );
buf ( n2767 , n2472 );
nor ( n2768 , n2766 , n2767 );
buf ( n2769 , n2768 );
buf ( n2770 , n2769 );
buf ( n2771 , n2597 );
nor ( n2772 , n2770 , n2771 );
buf ( n2773 , n2772 );
buf ( n2774 , n2773 );
nand ( n2775 , n2757 , n2774 );
buf ( n2776 , n2775 );
buf ( n2777 , n2776 );
and ( n2778 , n2756 , n2777 );
buf ( n2779 , n2778 );
buf ( n2780 , n2779 );
nand ( n2781 , n2558 , n2780 );
buf ( n2782 , n2781 );
not ( n2783 , n2593 );
and ( n2784 , n2609 , n2751 , n2585 );
not ( n2785 , n2480 );
nand ( n2786 , n2785 , n2484 );
nor ( n2787 , n2784 , n2786 );
nand ( n2788 , n2474 , n2783 , n2660 , n2787 );
buf ( n2789 , n2788 );
buf ( n2790 , n2465 );
not ( n2791 , n2790 );
buf ( n2792 , n2791 );
buf ( n2793 , n2792 );
not ( n2794 , n2793 );
buf ( n2795 , n2479 );
buf ( n2796 , n2484 );
and ( n2797 , n2795 , n2796 );
buf ( n2798 , n2797 );
buf ( n2799 , n2798 );
buf ( n2800 , n2443 );
buf ( n2801 , n2476 );
nand ( n2802 , n2799 , n2800 , n2801 );
buf ( n2803 , n2802 );
buf ( n2804 , n2803 );
not ( n2805 , n2804 );
and ( n2806 , n2794 , n2805 );
buf ( n2807 , n2472 );
buf ( n2808 , n2798 );
and ( n2809 , n2807 , n2808 );
nor ( n2810 , n2806 , n2809 );
buf ( n2811 , n2810 );
buf ( n2812 , n2811 );
not ( n2813 , n2812 );
buf ( n2814 , n2769 );
not ( n2815 , n2814 );
and ( n2816 , n2813 , n2815 );
buf ( n2817 , n2367 );
not ( n2818 , n2817 );
buf ( n2819 , n2400 );
not ( n2820 , n2819 );
buf ( n2821 , n2415 );
buf ( n2822 , n2429 );
nand ( n2823 , n2818 , n2820 , n2821 , n2822 );
buf ( n2824 , n2823 );
buf ( n2825 , n2824 );
buf ( n2826 , n2811 );
not ( n2827 , n2826 );
buf ( n2828 , n2827 );
buf ( n2829 , n2828 );
and ( n2830 , n2825 , n2829 );
nor ( n2831 , n2816 , n2830 );
buf ( n2832 , n2831 );
buf ( n2833 , n2832 );
and ( n2834 , n2828 , n2538 );
buf ( n2835 , n2548 );
not ( n2836 , n2835 );
buf ( n2837 , n2836 );
nor ( n2838 , n2834 , n2837 );
buf ( n2839 , n2838 );
nand ( n2840 , n2789 , n2833 , n2839 );
buf ( n2841 , n2840 );
buf ( n2842 , n2761 );
buf ( n2843 , n2432 );
not ( n2844 , n2843 );
buf ( n2845 , n2844 );
not ( n2846 , n2845 );
buf ( n2847 , n1490 );
buf ( n2848 , n1471 );
nand ( n2849 , n2847 , n2848 );
buf ( n2850 , n2849 );
nand ( n2851 , n1466 , n2531 );
and ( n2852 , n2850 , n2851 );
nor ( n2853 , n2852 , n2525 );
buf ( n2854 , n2853 );
not ( n2855 , n2854 );
buf ( n2856 , n2521 );
not ( n2857 , n2856 );
or ( n2858 , n2855 , n2857 );
buf ( n2859 , n1195 );
not ( n2860 , n2859 );
buf ( n2861 , n1282 );
not ( n2862 , n2861 );
buf ( n2863 , n2862 );
buf ( n2864 , n2863 );
nand ( n2865 , n2860 , n2864 );
buf ( n2866 , n2865 );
buf ( n2867 , n2866 );
buf ( n2868 , n1190 );
buf ( n2869 , n1382 );
and ( n2870 , n2868 , n2869 );
buf ( n2871 , n2870 );
buf ( n2872 , n2871 );
and ( n2873 , n2867 , n2872 );
buf ( n2874 , n2863 );
not ( n2875 , n2874 );
buf ( n2876 , n2875 );
buf ( n2877 , n2876 );
buf ( n2878 , n1195 );
and ( n2879 , n2877 , n2878 );
nor ( n2880 , n2873 , n2879 );
buf ( n2881 , n2880 );
buf ( n2882 , n2881 );
nand ( n2883 , n2858 , n2882 );
buf ( n2884 , n2883 );
not ( n2885 , n2884 );
or ( n2886 , n2846 , n2885 );
buf ( n2887 , n2400 );
not ( n2888 , n2887 );
buf ( n2889 , n2888 );
nand ( n2890 , n2889 , n2429 );
not ( n2891 , n2890 );
not ( n2892 , n2367 );
buf ( n2893 , n1287 );
not ( n2894 , n2893 );
buf ( n2895 , n2413 );
not ( n2896 , n2895 );
or ( n2897 , n2894 , n2896 );
buf ( n2898 , n2353 );
buf ( n2899 , n2364 );
nand ( n2900 , n2898 , n2899 );
buf ( n2901 , n2900 );
buf ( n2902 , n2901 );
nand ( n2903 , n2897 , n2902 );
buf ( n2904 , n2903 );
nand ( n2905 , n2892 , n2904 );
not ( n2906 , n2905 );
and ( n2907 , n2891 , n2906 );
not ( n2908 , n2400 );
not ( n2909 , n2908 );
and ( n2910 , n2422 , n2423 );
nor ( n2911 , n2910 , n2425 );
not ( n2912 , n2418 );
nor ( n2913 , n2911 , n2912 );
not ( n2914 , n2913 );
or ( n2915 , n2909 , n2914 );
nand ( n2916 , n2380 , n2399 );
nand ( n2917 , n2915 , n2916 );
nor ( n2918 , n2907 , n2917 );
nand ( n2919 , n2886 , n2918 );
buf ( n2920 , n2919 );
nand ( n2921 , n2842 , n2920 );
buf ( n2922 , n2921 );
buf ( n2923 , n2922 );
nand ( n2924 , n2783 , n2752 , n2660 );
buf ( n2925 , n2924 );
buf ( n2926 , n2925 );
buf ( n2927 , n2521 );
not ( n2928 , n2927 );
buf ( n2929 , n2525 );
buf ( n2930 , n2534 );
or ( n2931 , n2929 , n2930 );
buf ( n2932 , n2931 );
buf ( n2933 , n2932 );
nor ( n2934 , n2928 , n2933 );
buf ( n2935 , n2934 );
and ( n2936 , n2845 , n2935 );
buf ( n2937 , n2936 );
buf ( n2938 , n2761 );
nand ( n2939 , n2926 , n2937 , n2938 );
buf ( n2940 , n2939 );
buf ( n2941 , n2940 );
buf ( n2942 , n2456 );
nand ( n2943 , n2923 , n2941 , n2942 );
buf ( n2944 , n2943 );
buf ( n2945 , n2925 );
not ( n2946 , n2415 );
buf ( n2947 , n2367 );
nor ( n2948 , n2946 , n2947 );
not ( n2949 , n2948 );
nor ( n2950 , n2949 , n2538 );
buf ( n2951 , n2950 );
nand ( n2952 , n2945 , n2951 );
buf ( n2953 , n2952 );
buf ( n2954 , C1 );
buf ( n2955 , n2769 );
not ( n2956 , n2955 );
buf ( n2957 , n2956 );
buf ( n2958 , n2957 );
buf ( n2959 , n2551 );
not ( n2960 , n2959 );
buf ( n2961 , n1007 );
nand ( n2962 , n2960 , n2961 );
buf ( n2963 , n2962 );
buf ( n2964 , n2963 );
nor ( n2965 , n2958 , n2964 );
buf ( n2966 , n2965 );
buf ( n2967 , C1 );
buf ( n2968 , n2919 );
not ( n2969 , n2765 );
buf ( n2970 , n2969 );
nand ( n2971 , n2968 , n2970 );
buf ( n2972 , n2971 );
buf ( n2973 , n2919 );
buf ( n2974 , n2769 );
nand ( n2975 , n2973 , n2974 );
buf ( n2976 , n2975 );
not ( n2977 , n2845 );
not ( n2978 , n2884 );
or ( n2979 , n2977 , n2978 );
nand ( n2980 , n2979 , n2918 );
buf ( n2981 , n2980 );
buf ( n2982 , n2966 );
nand ( n2983 , n2981 , n2982 );
buf ( n2984 , n2983 );
buf ( n2985 , n2919 );
not ( n2986 , n2985 );
buf ( n2987 , n2986 );
not ( n2988 , n2947 );
not ( n2989 , n2415 );
not ( n2990 , n2429 );
nor ( n2991 , n2989 , n2990 );
nand ( n2992 , n2988 , n2991 );
not ( n2993 , n2992 );
buf ( n2994 , n2993 );
buf ( n2995 , n2884 );
or ( n2996 , n2990 , n2905 );
not ( n2997 , n2913 );
nand ( n2998 , n2996 , n2997 );
buf ( n2999 , n2998 );
and ( n3000 , n2994 , n2995 );
nor ( n3001 , n3000 , n2999 );
buf ( n3002 , n3001 );
buf ( n3003 , n2480 );
not ( n3004 , n3003 );
buf ( n3005 , n2474 );
nand ( n3006 , n3004 , n3005 );
buf ( n3007 , n3006 );
buf ( n3008 , n3007 );
buf ( n3009 , n2963 );
not ( n3010 , n3009 );
buf ( n3011 , n3010 );
buf ( n3012 , n3011 );
buf ( n3013 , n1007 );
not ( n3014 , n3013 );
buf ( n3015 , n2498 );
not ( n3016 , n3015 );
or ( n3017 , n3014 , n3016 );
nand ( n3018 , n1039 , n1007 );
buf ( n3019 , n3018 );
nand ( n3020 , n3017 , n3019 );
buf ( n3021 , n3020 );
buf ( n3022 , n3021 );
and ( n3023 , n3008 , n3012 );
nor ( n3024 , n3023 , n3022 );
buf ( n3025 , n3024 );
buf ( n3026 , n2957 );
buf ( n3027 , n2551 );
nor ( n3028 , n3026 , n3027 );
buf ( n3029 , n3028 );
buf ( n3030 , n2957 );
buf ( n3031 , n2837 );
nor ( n3032 , n3030 , n3031 );
buf ( n3033 , n3032 );
not ( n3034 , n2990 );
nand ( n3035 , n3034 , n2997 );
buf ( n3036 , n3035 );
not ( n3037 , n3036 );
buf ( n3038 , n3037 );
buf ( n3039 , n2462 );
buf ( n3040 , n2443 );
nand ( n3041 , n3039 , n3040 );
buf ( n3042 , n3041 );
buf ( n3043 , n2944 );
buf ( n3044 , n3042 );
xnor ( n3045 , n3043 , n3044 );
buf ( n3046 , n3045 );
buf ( n3047 , n409 );
buf ( n3048 , n415 );
and ( n3049 , n3047 , n3048 );
buf ( n3050 , n3049 );
buf ( n3051 , n3050 );
buf ( n3052 , n407 );
buf ( n3053 , n417 );
and ( n3054 , n3052 , n3053 );
buf ( n3055 , n3054 );
buf ( n3056 , n3055 );
buf ( n3057 , n408 );
buf ( n3058 , n416 );
and ( n3059 , n3057 , n3058 );
buf ( n3060 , n3059 );
buf ( n3061 , n3060 );
xor ( n3062 , n3051 , n3056 );
xor ( n3063 , n3062 , n3061 );
buf ( n3064 , n3063 );
xor ( n3065 , n3051 , n3056 );
and ( n3066 , n3065 , n3061 );
and ( n3067 , n3051 , n3056 );
or ( n3068 , n3066 , n3067 );
buf ( n3069 , n3068 );
buf ( n3070 , n391 );
buf ( n3071 , n393 );
and ( n3072 , n3070 , n3071 );
buf ( n3073 , n3072 );
buf ( n3074 , n3073 );
buf ( n3075 , n392 );
buf ( n3076 , n393 );
nand ( n3077 , n3075 , n3076 );
buf ( n3078 , n3077 );
buf ( n3079 , n3078 );
buf ( n3080 , n409 );
buf ( n3081 , n416 );
nand ( n3082 , n3080 , n3081 );
buf ( n3083 , n3082 );
buf ( n3084 , n3083 );
nor ( n3085 , n3079 , n3084 );
buf ( n3086 , n3085 );
buf ( n3087 , n3086 );
buf ( n3088 , C0 );
xor ( n3089 , n3074 , n3087 );
xor ( n3090 , n3089 , n3088 );
buf ( n3091 , n3090 );
and ( n3092 , n3074 , n3087 );
or ( n3093 , C0 , n3092 );
buf ( n3094 , n3093 );
buf ( n3095 , n408 );
buf ( n3096 , n415 );
and ( n3097 , n3095 , n3096 );
buf ( n3098 , n3097 );
buf ( n3099 , n3098 );
buf ( n3100 , n407 );
buf ( n3101 , n416 );
and ( n3102 , n3100 , n3101 );
buf ( n3103 , n3102 );
buf ( n3104 , n3103 );
buf ( n3105 , n406 );
buf ( n3106 , n417 );
and ( n3107 , n3105 , n3106 );
buf ( n3108 , n3107 );
buf ( n3109 , n3108 );
xor ( n3110 , n3099 , n3104 );
xor ( n3111 , n3110 , n3109 );
buf ( n3112 , n3111 );
xor ( n3113 , n3099 , n3104 );
and ( n3114 , n3113 , n3109 );
and ( n3115 , n3099 , n3104 );
or ( n3116 , n3114 , n3115 );
buf ( n3117 , n3116 );
not ( n3118 , n392 );
nand ( n3119 , n3118 , n391 , n393 );
not ( n3120 , n391 );
nand ( n3121 , n3120 , n392 , n393 );
nand ( n3122 , n3119 , n3121 );
buf ( n3123 , n3122 );
buf ( n3124 , n409 );
buf ( n3125 , n414 );
nand ( n3126 , n3124 , n3125 );
buf ( n3127 , n3126 );
buf ( n3128 , n390 );
buf ( n3129 , n393 );
nand ( n3130 , n3128 , n3129 );
buf ( n3131 , n3130 );
xor ( n3132 , n3127 , n3131 );
buf ( n3133 , n3132 );
not ( n3134 , n392 );
nor ( n3135 , n3134 , n393 );
buf ( n3136 , n3135 );
xor ( n3137 , n3123 , n3133 );
xor ( n3138 , n3137 , n3136 );
buf ( n3139 , n3138 );
xor ( n3140 , n3123 , n3133 );
and ( n3141 , n3140 , n3136 );
and ( n3142 , n3123 , n3133 );
or ( n3143 , n3141 , n3142 );
buf ( n3144 , n3143 );
buf ( n3145 , n3069 );
buf ( n3146 , n3112 );
buf ( n3147 , n3094 );
xor ( n3148 , n3145 , n3146 );
xor ( n3149 , n3148 , n3147 );
buf ( n3150 , n3149 );
xor ( n3151 , n3145 , n3146 );
and ( n3152 , n3151 , n3147 );
and ( n3153 , n3145 , n3146 );
or ( n3154 , n3152 , n3153 );
buf ( n3155 , n3154 );
buf ( n3156 , n407 );
buf ( n3157 , n415 );
and ( n3158 , n3156 , n3157 );
buf ( n3159 , n3158 );
buf ( n3160 , n3159 );
buf ( n3161 , n409 );
buf ( n3162 , n413 );
and ( n3163 , n3161 , n3162 );
buf ( n3164 , n3163 );
buf ( n3165 , n3164 );
buf ( n3166 , n406 );
buf ( n3167 , n416 );
and ( n3168 , n3166 , n3167 );
buf ( n3169 , n3168 );
buf ( n3170 , n3169 );
xor ( n3171 , n3160 , n3165 );
xor ( n3172 , n3171 , n3170 );
buf ( n3173 , n3172 );
xor ( n3174 , n3160 , n3165 );
and ( n3175 , n3174 , n3170 );
and ( n3176 , n3160 , n3165 );
or ( n3177 , n3175 , n3176 );
buf ( n3178 , n3177 );
buf ( n3179 , n405 );
buf ( n3180 , n417 );
and ( n3181 , n3179 , n3180 );
buf ( n3182 , n3181 );
buf ( n3183 , n3182 );
buf ( n3184 , n408 );
buf ( n3185 , n414 );
and ( n3186 , n3184 , n3185 );
buf ( n3187 , n3186 );
buf ( n3188 , n3187 );
buf ( n3189 , n389 );
buf ( n3190 , n393 );
and ( n3191 , n3189 , n3190 );
buf ( n3192 , n3191 );
buf ( n3193 , n3192 );
xor ( n3194 , n3188 , n3193 );
buf ( n3195 , n3194 );
buf ( n3196 , n3195 );
buf ( n3197 , n3135 );
buf ( n3198 , n391 );
and ( n3199 , n3197 , n3198 );
buf ( n3200 , n3199 );
buf ( n3201 , n3200 );
xor ( n3202 , n3183 , n3196 );
xor ( n3203 , n3202 , n3201 );
buf ( n3204 , n3203 );
xor ( n3205 , n3183 , n3196 );
and ( n3206 , n3205 , n3201 );
and ( n3207 , n3183 , n3196 );
or ( n3208 , n3206 , n3207 );
buf ( n3209 , n3208 );
buf ( n3210 , n3131 );
buf ( n3211 , n3127 );
nor ( n3212 , n3210 , n3211 );
buf ( n3213 , n3212 );
buf ( n3214 , n3213 );
buf ( n3215 , n3122 );
buf ( n3216 , n392 );
and ( n3217 , n3215 , n3216 );
buf ( n3218 , n3217 );
buf ( n3219 , n3218 );
buf ( n3220 , n3117 );
xor ( n3221 , n3214 , n3219 );
xor ( n3222 , n3221 , n3220 );
buf ( n3223 , n3222 );
xor ( n3224 , n3214 , n3219 );
and ( n3225 , n3224 , n3220 );
and ( n3226 , n3214 , n3219 );
or ( n3227 , n3225 , n3226 );
buf ( n3228 , n3227 );
buf ( n3229 , n3173 );
buf ( n3230 , n3144 );
buf ( n3231 , n3204 );
xor ( n3232 , n3229 , n3230 );
xor ( n3233 , n3232 , n3231 );
buf ( n3234 , n3233 );
xor ( n3235 , n3229 , n3230 );
and ( n3236 , n3235 , n3231 );
and ( n3237 , n3229 , n3230 );
or ( n3238 , n3236 , n3237 );
buf ( n3239 , n3238 );
nand ( n3240 , n392 , n391 );
not ( n3241 , n3240 );
nand ( n3242 , n390 , n393 );
and ( n3243 , n3242 , n3120 );
not ( n3244 , n3242 );
and ( n3245 , n3244 , n391 );
or ( n3246 , n3243 , n3245 );
not ( n3247 , n3246 );
or ( n3248 , n3241 , n3247 );
and ( n3249 , n391 , n392 );
nand ( n3250 , n3249 , n3242 );
nand ( n3251 , n3248 , n3250 );
nand ( n3252 , n392 , n393 , n391 );
and ( n3253 , n3251 , n3252 );
not ( n3254 , n3251 );
not ( n3255 , n3252 );
and ( n3256 , n3254 , n3255 );
nor ( n3257 , n3253 , n3256 );
buf ( n3258 , n3257 );
buf ( n3259 , n3258 );
buf ( n3260 , n393 );
and ( n3261 , n3259 , n3260 );
buf ( n3262 , n3261 );
buf ( n3263 , n3262 );
buf ( n3264 , n3223 );
buf ( n3265 , n3155 );
xor ( n3266 , n3263 , n3264 );
xor ( n3267 , n3266 , n3265 );
buf ( n3268 , n3267 );
xor ( n3269 , n3263 , n3264 );
and ( n3270 , n3269 , n3265 );
and ( n3271 , n3263 , n3264 );
or ( n3272 , n3270 , n3271 );
buf ( n3273 , n3272 );
buf ( n3274 , n407 );
buf ( n3275 , n414 );
and ( n3276 , n3274 , n3275 );
buf ( n3277 , n3276 );
buf ( n3278 , n3277 );
buf ( n3279 , n408 );
buf ( n3280 , n413 );
and ( n3281 , n3279 , n3280 );
buf ( n3282 , n3281 );
buf ( n3283 , n3282 );
buf ( n3284 , n409 );
buf ( n3285 , n412 );
and ( n3286 , n3284 , n3285 );
buf ( n3287 , n3286 );
buf ( n3288 , n3287 );
xor ( n3289 , n3278 , n3283 );
xor ( n3290 , n3289 , n3288 );
buf ( n3291 , n3290 );
xor ( n3292 , n3278 , n3283 );
and ( n3293 , n3292 , n3288 );
and ( n3294 , n3278 , n3283 );
or ( n3295 , n3293 , n3294 );
buf ( n3296 , n3295 );
buf ( n3297 , n388 );
buf ( n3298 , n393 );
and ( n3299 , n3297 , n3298 );
buf ( n3300 , n3299 );
buf ( n3301 , n3300 );
buf ( n3302 , n404 );
buf ( n3303 , n417 );
and ( n3304 , n3302 , n3303 );
buf ( n3305 , n3304 );
buf ( n3306 , n3305 );
buf ( n3307 , n3135 );
buf ( n3308 , n390 );
and ( n3309 , n3307 , n3308 );
buf ( n3310 , n3309 );
buf ( n3311 , n3310 );
xor ( n3312 , n3301 , n3306 );
xor ( n3313 , n3312 , n3311 );
buf ( n3314 , n3313 );
xor ( n3315 , n3301 , n3306 );
and ( n3316 , n3315 , n3311 );
and ( n3317 , n3301 , n3306 );
or ( n3318 , n3316 , n3317 );
buf ( n3319 , n3318 );
buf ( n3320 , n405 );
buf ( n3321 , n416 );
and ( n3322 , n3320 , n3321 );
buf ( n3323 , n3322 );
buf ( n3324 , n3323 );
buf ( n3325 , n406 );
buf ( n3326 , n415 );
and ( n3327 , n3325 , n3326 );
buf ( n3328 , n3327 );
buf ( n3329 , n3328 );
xor ( n3330 , n3324 , n3329 );
buf ( n3331 , n3330 );
buf ( n3332 , n3331 );
buf ( n3333 , n3122 );
buf ( n3334 , n391 );
and ( n3335 , n3333 , n3334 );
buf ( n3336 , n3335 );
buf ( n3337 , n3336 );
and ( n3338 , n3188 , n3193 );
buf ( n3339 , n3338 );
buf ( n3340 , n3339 );
xor ( n3341 , n3332 , n3337 );
xor ( n3342 , n3341 , n3340 );
buf ( n3343 , n3342 );
xor ( n3344 , n3332 , n3337 );
and ( n3345 , n3344 , n3340 );
and ( n3346 , n3332 , n3337 );
or ( n3347 , n3345 , n3346 );
buf ( n3348 , n3347 );
buf ( n3349 , n3178 );
buf ( n3350 , n3291 );
buf ( n3351 , n3314 );
xor ( n3352 , n3349 , n3350 );
xor ( n3353 , n3352 , n3351 );
buf ( n3354 , n3353 );
xor ( n3355 , n3349 , n3350 );
and ( n3356 , n3355 , n3351 );
and ( n3357 , n3349 , n3350 );
or ( n3358 , n3356 , n3357 );
buf ( n3359 , n3358 );
buf ( n3360 , n3209 );
buf ( n3361 , n3228 );
buf ( n3362 , n3343 );
xor ( n3363 , n3360 , n3361 );
xor ( n3364 , n3363 , n3362 );
buf ( n3365 , n3364 );
xor ( n3366 , n3360 , n3361 );
and ( n3367 , n3366 , n3362 );
and ( n3368 , n3360 , n3361 );
or ( n3369 , n3367 , n3368 );
buf ( n3370 , n3369 );
buf ( n3371 , n3258 );
buf ( n3372 , n392 );
and ( n3373 , n3371 , n3372 );
buf ( n3374 , n3373 );
buf ( n3375 , n3374 );
nand ( n3376 , n392 , n390 );
nand ( n3377 , n393 , n389 );
or ( n3378 , n3376 , n3377 );
not ( n3379 , n393 );
not ( n3380 , n389 );
or ( n3381 , n3379 , n3380 );
nand ( n3382 , n392 , n390 );
nand ( n3383 , n3381 , n3382 );
nand ( n3384 , n3378 , n3383 );
buf ( n3385 , n3384 );
nand ( n3386 , n393 , n390 , n391 );
or ( n3387 , n3385 , n3386 );
nand ( n3388 , n3384 , n3386 );
buf ( n3389 , n3388 );
nand ( n3390 , n3387 , n3389 );
nand ( n3391 , n393 , n392 , n391 );
nand ( n3392 , n3391 , n3250 );
not ( n3393 , n3392 );
and ( n3394 , n3390 , n3393 );
not ( n3395 , n3390 );
and ( n3396 , n3395 , n3392 );
nor ( n3397 , n3394 , n3396 );
buf ( n3398 , n3397 );
buf ( n3399 , n393 );
and ( n3400 , n3398 , n3399 );
buf ( n3401 , n3400 );
buf ( n3402 , n3401 );
buf ( n3403 , n3354 );
xor ( n3404 , n3375 , n3402 );
xor ( n3405 , n3404 , n3403 );
buf ( n3406 , n3405 );
xor ( n3407 , n3375 , n3402 );
and ( n3408 , n3407 , n3403 );
and ( n3409 , n3375 , n3402 );
or ( n3410 , n3408 , n3409 );
buf ( n3411 , n3410 );
buf ( n3412 , n3239 );
buf ( n3413 , n3365 );
buf ( n3414 , n3406 );
xor ( n3415 , n3412 , n3413 );
xor ( n3416 , n3415 , n3414 );
buf ( n3417 , n3416 );
xor ( n3418 , n3412 , n3413 );
and ( n3419 , n3418 , n3414 );
and ( n3420 , n3412 , n3413 );
or ( n3421 , n3419 , n3420 );
buf ( n3422 , n3421 );
buf ( n3423 , n409 );
buf ( n3424 , n411 );
and ( n3425 , n3423 , n3424 );
buf ( n3426 , n3425 );
buf ( n3427 , n3426 );
buf ( n3428 , n387 );
buf ( n3429 , n393 );
and ( n3430 , n3428 , n3429 );
buf ( n3431 , n3430 );
buf ( n3432 , n3431 );
buf ( n3433 , n405 );
buf ( n3434 , n415 );
and ( n3435 , n3433 , n3434 );
buf ( n3436 , n3435 );
buf ( n3437 , n3436 );
xor ( n3438 , n3427 , n3432 );
xor ( n3439 , n3438 , n3437 );
buf ( n3440 , n3439 );
xor ( n3441 , n3427 , n3432 );
and ( n3442 , n3441 , n3437 );
and ( n3443 , n3427 , n3432 );
or ( n3444 , n3442 , n3443 );
buf ( n3445 , n3444 );
buf ( n3446 , n407 );
buf ( n3447 , n413 );
and ( n3448 , n3446 , n3447 );
buf ( n3449 , n3448 );
buf ( n3450 , n3449 );
buf ( n3451 , n408 );
buf ( n3452 , n412 );
and ( n3453 , n3451 , n3452 );
buf ( n3454 , n3453 );
buf ( n3455 , n3454 );
buf ( n3456 , n406 );
buf ( n3457 , n414 );
and ( n3458 , n3456 , n3457 );
buf ( n3459 , n3458 );
buf ( n3460 , n3459 );
xor ( n3461 , n3450 , n3455 );
xor ( n3462 , n3461 , n3460 );
buf ( n3463 , n3462 );
xor ( n3464 , n3450 , n3455 );
and ( n3465 , n3464 , n3460 );
and ( n3466 , n3450 , n3455 );
or ( n3467 , n3465 , n3466 );
buf ( n3468 , n3467 );
buf ( n3469 , n3122 );
buf ( n3470 , n390 );
and ( n3471 , n3469 , n3470 );
buf ( n3472 , n3471 );
buf ( n3473 , n3472 );
buf ( n3474 , n403 );
buf ( n3475 , n417 );
and ( n3476 , n3474 , n3475 );
buf ( n3477 , n3476 );
buf ( n3478 , n3477 );
buf ( n3479 , n404 );
buf ( n3480 , n416 );
and ( n3481 , n3479 , n3480 );
buf ( n3482 , n3481 );
buf ( n3483 , n3482 );
xor ( n3484 , n3478 , n3483 );
buf ( n3485 , n3484 );
buf ( n3486 , n3485 );
buf ( n3487 , n3135 );
buf ( n3488 , n389 );
and ( n3489 , n3487 , n3488 );
buf ( n3490 , n3489 );
buf ( n3491 , n3490 );
xor ( n3492 , n3473 , n3486 );
xor ( n3493 , n3492 , n3491 );
buf ( n3494 , n3493 );
xor ( n3495 , n3473 , n3486 );
and ( n3496 , n3495 , n3491 );
and ( n3497 , n3473 , n3486 );
or ( n3498 , n3496 , n3497 );
buf ( n3499 , n3498 );
and ( n3500 , n3324 , n3329 );
buf ( n3501 , n3500 );
buf ( n3502 , n3501 );
buf ( n3503 , n3296 );
buf ( n3504 , n3440 );
xor ( n3505 , n3502 , n3503 );
xor ( n3506 , n3505 , n3504 );
buf ( n3507 , n3506 );
xor ( n3508 , n3502 , n3503 );
and ( n3509 , n3508 , n3504 );
and ( n3510 , n3502 , n3503 );
or ( n3511 , n3509 , n3510 );
buf ( n3512 , n3511 );
buf ( n3513 , n3463 );
buf ( n3514 , n3319 );
buf ( n3515 , n3348 );
xor ( n3516 , n3513 , n3514 );
xor ( n3517 , n3516 , n3515 );
buf ( n3518 , n3517 );
xor ( n3519 , n3513 , n3514 );
and ( n3520 , n3519 , n3515 );
and ( n3521 , n3513 , n3514 );
or ( n3522 , n3520 , n3521 );
buf ( n3523 , n3522 );
buf ( n3524 , n3257 );
buf ( n3525 , n391 );
and ( n3526 , n3524 , n3525 );
buf ( n3527 , n3526 );
buf ( n3528 , n3527 );
buf ( n3529 , n3494 );
not ( n3530 , n3397 );
buf ( n3531 , n392 );
not ( n3532 , n3531 );
buf ( n3533 , n3532 );
nor ( n3534 , n3530 , n3533 );
buf ( n3535 , n3534 );
xor ( n3536 , n3528 , n3529 );
xor ( n3537 , n3536 , n3535 );
buf ( n3538 , n3537 );
xor ( n3539 , n3528 , n3529 );
and ( n3540 , n3539 , n3535 );
and ( n3541 , n3528 , n3529 );
or ( n3542 , n3540 , n3541 );
buf ( n3543 , n3542 );
buf ( n3544 , n3507 );
nand ( n3545 , n389 , n392 , n390 , n393 );
nand ( n3546 , n388 , n393 );
not ( n3547 , n3546 );
and ( n3548 , n389 , n392 );
xor ( n3549 , n3547 , n3548 );
not ( n3550 , n390 );
nor ( n3551 , n3550 , n391 );
xor ( n3552 , n3549 , n3551 );
xor ( n3553 , n3545 , n3552 );
not ( n3554 , n3250 );
not ( n3555 , n3554 );
not ( n3556 , n3388 );
or ( n3557 , n3555 , n3556 );
not ( n3558 , n3384 );
not ( n3559 , n3386 );
and ( n3560 , n3558 , n3559 );
not ( n3561 , n3391 );
and ( n3562 , n3388 , n3561 );
nor ( n3563 , n3560 , n3562 );
nand ( n3564 , n3557 , n3563 );
xnor ( n3565 , n3553 , n3564 );
buf ( n3566 , n3565 );
buf ( n3567 , n393 );
and ( n3568 , n3566 , n3567 );
buf ( n3569 , n3568 );
buf ( n3570 , n3569 );
buf ( n3571 , n3359 );
xor ( n3572 , n3544 , n3570 );
xor ( n3573 , n3572 , n3571 );
buf ( n3574 , n3573 );
xor ( n3575 , n3544 , n3570 );
and ( n3576 , n3575 , n3571 );
and ( n3577 , n3544 , n3570 );
or ( n3578 , n3576 , n3577 );
buf ( n3579 , n3578 );
buf ( n3580 , n3370 );
buf ( n3581 , n3518 );
buf ( n3582 , n3538 );
xor ( n3583 , n3580 , n3581 );
xor ( n3584 , n3583 , n3582 );
buf ( n3585 , n3584 );
xor ( n3586 , n3580 , n3581 );
and ( n3587 , n3586 , n3582 );
and ( n3588 , n3580 , n3581 );
or ( n3589 , n3587 , n3588 );
buf ( n3590 , n3589 );
buf ( n3591 , n3411 );
buf ( n3592 , n3574 );
buf ( n3593 , n3585 );
xor ( n3594 , n3591 , n3592 );
xor ( n3595 , n3594 , n3593 );
buf ( n3596 , n3595 );
xor ( n3597 , n3591 , n3592 );
and ( n3598 , n3597 , n3593 );
and ( n3599 , n3591 , n3592 );
or ( n3600 , n3598 , n3599 );
buf ( n3601 , n3600 );
buf ( n3602 , n406 );
buf ( n3603 , n413 );
and ( n3604 , n3602 , n3603 );
buf ( n3605 , n3604 );
buf ( n3606 , n3605 );
buf ( n3607 , n403 );
buf ( n3608 , n416 );
and ( n3609 , n3607 , n3608 );
buf ( n3610 , n3609 );
buf ( n3611 , n3610 );
buf ( n3612 , n404 );
buf ( n3613 , n415 );
and ( n3614 , n3612 , n3613 );
buf ( n3615 , n3614 );
buf ( n3616 , n3615 );
xor ( n3617 , n3606 , n3611 );
xor ( n3618 , n3617 , n3616 );
buf ( n3619 , n3618 );
xor ( n3620 , n3606 , n3611 );
and ( n3621 , n3620 , n3616 );
and ( n3622 , n3606 , n3611 );
or ( n3623 , n3621 , n3622 );
buf ( n3624 , n3623 );
buf ( n3625 , n409 );
buf ( n3626 , n410 );
and ( n3627 , n3625 , n3626 );
buf ( n3628 , n3627 );
buf ( n3629 , n3628 );
and ( n3630 , n405 , n414 );
buf ( n3631 , n3630 );
buf ( n3632 , n407 );
buf ( n3633 , n412 );
and ( n3634 , n3632 , n3633 );
buf ( n3635 , n3634 );
buf ( n3636 , n3635 );
xor ( n3637 , n3629 , n3631 );
xor ( n3638 , n3637 , n3636 );
buf ( n3639 , n3638 );
xor ( n3640 , n3629 , n3631 );
and ( n3641 , n3640 , n3636 );
and ( n3642 , n3629 , n3631 );
or ( n3643 , n3641 , n3642 );
buf ( n3644 , n3643 );
buf ( n3645 , n3590 );
buf ( n3646 , n3543 );
not ( n3647 , n3545 );
not ( n3648 , n3647 );
not ( n3649 , n3552 );
not ( n3650 , n3649 );
not ( n3651 , n3650 );
or ( n3652 , n3648 , n3651 );
not ( n3653 , n3545 );
not ( n3654 , n3649 );
or ( n3655 , n3653 , n3654 );
nand ( n3656 , n3655 , n3564 );
nand ( n3657 , n3652 , n3656 );
not ( n3658 , n3657 );
nand ( n3659 , n389 , n391 );
not ( n3660 , n3659 );
and ( n3661 , n388 , n392 );
xor ( n3662 , n3660 , n3661 );
xor ( n3663 , n3431 , n3662 );
and ( n3664 , n390 , n391 );
xor ( n3665 , n3663 , n3664 );
not ( n3666 , n3665 );
xor ( n3667 , n3547 , n3548 );
and ( n3668 , n3667 , n3551 );
and ( n3669 , n3547 , n3548 );
or ( n3670 , n3668 , n3669 );
and ( n3671 , n3666 , n3670 );
nand ( n3672 , n3658 , n3671 );
not ( n3673 , n3647 );
not ( n3674 , n3552 );
or ( n3675 , n3673 , n3674 );
or ( n3676 , n3552 , n3647 );
nand ( n3677 , n3676 , n3564 );
nand ( n3678 , n3675 , n3677 );
not ( n3679 , n3678 );
not ( n3680 , n3670 );
and ( n3681 , n3665 , n3680 );
nand ( n3682 , n3679 , n3681 );
nand ( n3683 , n3665 , n3670 );
not ( n3684 , n3683 );
nand ( n3685 , n3666 , n3680 );
not ( n3686 , n3685 );
or ( n3687 , n3684 , n3686 );
nand ( n3688 , n3687 , n3657 );
nand ( n3689 , n3672 , n3682 , n3688 );
buf ( n3690 , n3689 );
buf ( n3691 , n393 );
and ( n3692 , n3690 , n3691 );
buf ( n3693 , n3692 );
buf ( n3694 , n3693 );
xor ( n3695 , n3646 , n3694 );
buf ( n3696 , n3499 );
buf ( n3697 , n3258 );
buf ( n3698 , n390 );
and ( n3699 , n3697 , n3698 );
buf ( n3700 , n3699 );
buf ( n3701 , n3700 );
xor ( n3702 , n3696 , n3701 );
buf ( n3703 , n3135 );
buf ( n3704 , n388 );
and ( n3705 , n3703 , n3704 );
buf ( n3706 , n3705 );
buf ( n3707 , n3706 );
not ( n3708 , n3122 );
not ( n3709 , n389 );
nor ( n3710 , n3708 , n3709 );
buf ( n3711 , n3710 );
xor ( n3712 , n3707 , n3711 );
buf ( n3713 , n3445 );
xor ( n3714 , n3712 , n3713 );
buf ( n3715 , n3714 );
buf ( n3716 , n3715 );
xor ( n3717 , n3702 , n3716 );
buf ( n3718 , n3717 );
buf ( n3719 , n3718 );
xor ( n3720 , n3695 , n3719 );
buf ( n3721 , n3720 );
buf ( n3722 , n3721 );
buf ( n3723 , n3579 );
buf ( n3724 , n408 );
buf ( n3725 , n411 );
and ( n3726 , n3724 , n3725 );
buf ( n3727 , n3726 );
buf ( n3728 , n3727 );
buf ( n3729 , n402 );
buf ( n3730 , n417 );
nand ( n3731 , n3729 , n3730 );
buf ( n3732 , n3731 );
buf ( n3733 , n386 );
buf ( n3734 , n393 );
nand ( n3735 , n3733 , n3734 );
buf ( n3736 , n3735 );
xor ( n3737 , n3732 , n3736 );
buf ( n3738 , n3737 );
xor ( n3739 , n3728 , n3738 );
and ( n3740 , n3478 , n3483 );
buf ( n3741 , n3740 );
buf ( n3742 , n3741 );
xor ( n3743 , n3739 , n3742 );
buf ( n3744 , n3743 );
buf ( n3745 , n3744 );
buf ( n3746 , n3397 );
buf ( n3747 , n391 );
and ( n3748 , n3746 , n3747 );
buf ( n3749 , n3748 );
buf ( n3750 , n3749 );
xor ( n3751 , n3745 , n3750 );
buf ( n3752 , n3512 );
xor ( n3753 , n3751 , n3752 );
buf ( n3754 , n3753 );
buf ( n3755 , n3754 );
xor ( n3756 , n3723 , n3755 );
buf ( n3757 , n3523 );
buf ( n3758 , n3565 );
buf ( n3759 , n392 );
and ( n3760 , n3758 , n3759 );
buf ( n3761 , n3760 );
buf ( n3762 , n3761 );
xor ( n3763 , n3757 , n3762 );
buf ( n3764 , n3468 );
buf ( n3765 , n3639 );
xor ( n3766 , n3764 , n3765 );
buf ( n3767 , n3619 );
xor ( n3768 , n3766 , n3767 );
buf ( n3769 , n3768 );
buf ( n3770 , n3769 );
xor ( n3771 , n3763 , n3770 );
buf ( n3772 , n3771 );
buf ( n3773 , n3772 );
xor ( n3774 , n3756 , n3773 );
buf ( n3775 , n3774 );
buf ( n3776 , n3775 );
xor ( n3777 , n3645 , n3722 );
xor ( n3778 , n3777 , n3776 );
buf ( n3779 , n3778 );
xor ( n3780 , n3645 , n3722 );
and ( n3781 , n3780 , n3776 );
and ( n3782 , n3645 , n3722 );
or ( n3783 , n3781 , n3782 );
buf ( n3784 , n3783 );
xor ( n3785 , n3728 , n3738 );
and ( n3786 , n3785 , n3742 );
and ( n3787 , n3728 , n3738 );
or ( n3788 , n3786 , n3787 );
buf ( n3789 , n3788 );
xor ( n3790 , n3707 , n3711 );
and ( n3791 , n3790 , n3713 );
or ( n3792 , n3791 , C0 );
buf ( n3793 , n3792 );
xor ( n3794 , n3764 , n3765 );
and ( n3795 , n3794 , n3767 );
and ( n3796 , n3764 , n3765 );
or ( n3797 , n3795 , n3796 );
buf ( n3798 , n3797 );
xor ( n3799 , n3696 , n3701 );
and ( n3800 , n3799 , n3716 );
and ( n3801 , n3696 , n3701 );
or ( n3802 , n3800 , n3801 );
buf ( n3803 , n3802 );
xor ( n3804 , n3745 , n3750 );
and ( n3805 , n3804 , n3752 );
and ( n3806 , n3745 , n3750 );
or ( n3807 , n3805 , n3806 );
buf ( n3808 , n3807 );
xor ( n3809 , n3757 , n3762 );
and ( n3810 , n3809 , n3770 );
and ( n3811 , n3757 , n3762 );
or ( n3812 , n3810 , n3811 );
buf ( n3813 , n3812 );
xor ( n3814 , n3646 , n3694 );
and ( n3815 , n3814 , n3719 );
and ( n3816 , n3646 , n3694 );
or ( n3817 , n3815 , n3816 );
buf ( n3818 , n3817 );
xor ( n3819 , n3723 , n3755 );
and ( n3820 , n3819 , n3773 );
and ( n3821 , n3723 , n3755 );
or ( n3822 , n3820 , n3821 );
buf ( n3823 , n3822 );
buf ( n3824 , n408 );
buf ( n3825 , n410 );
and ( n3826 , n3824 , n3825 );
buf ( n3827 , n3826 );
buf ( n3828 , n3827 );
buf ( n3829 , n403 );
buf ( n3830 , n415 );
and ( n3831 , n3829 , n3830 );
buf ( n3832 , n3831 );
buf ( n3833 , n3832 );
buf ( n3834 , n404 );
buf ( n3835 , n414 );
and ( n3836 , n3834 , n3835 );
buf ( n3837 , n3836 );
buf ( n3838 , n3837 );
xor ( n3839 , n3828 , n3833 );
xor ( n3840 , n3839 , n3838 );
buf ( n3841 , n3840 );
xor ( n3842 , n3828 , n3833 );
and ( n3843 , n3842 , n3838 );
and ( n3844 , n3828 , n3833 );
or ( n3845 , n3843 , n3844 );
buf ( n3846 , n3845 );
buf ( n3847 , n402 );
buf ( n3848 , n416 );
and ( n3849 , n3847 , n3848 );
buf ( n3850 , n3849 );
buf ( n3851 , n3850 );
buf ( n3852 , n407 );
buf ( n3853 , n411 );
and ( n3854 , n3852 , n3853 );
buf ( n3855 , n3854 );
buf ( n3856 , n3855 );
buf ( n3857 , n405 );
buf ( n3858 , n413 );
and ( n3859 , n3857 , n3858 );
buf ( n3860 , n3859 );
buf ( n3861 , n3860 );
xor ( n3862 , n3851 , n3856 );
xor ( n3863 , n3862 , n3861 );
buf ( n3864 , n3863 );
xor ( n3865 , n3851 , n3856 );
and ( n3866 , n3865 , n3861 );
and ( n3867 , n3851 , n3856 );
or ( n3868 , n3866 , n3867 );
buf ( n3869 , n3868 );
buf ( n3870 , n3864 );
buf ( n3871 , n3841 );
xor ( n3872 , n3870 , n3871 );
buf ( n3873 , n3789 );
xor ( n3874 , n3872 , n3873 );
buf ( n3875 , n3874 );
buf ( n3876 , n3875 );
buf ( n3877 , n3565 );
buf ( n3878 , n391 );
and ( n3879 , n3877 , n3878 );
buf ( n3880 , n3879 );
buf ( n3881 , n3880 );
xor ( n3882 , n3876 , n3881 );
buf ( n3883 , n3803 );
xor ( n3884 , n3882 , n3883 );
buf ( n3885 , n3884 );
buf ( n3886 , n3885 );
buf ( n3887 , n3818 );
buf ( n3888 , n3689 );
buf ( n3889 , n392 );
and ( n3890 , n3888 , n3889 );
buf ( n3891 , n3890 );
buf ( n3892 , n3891 );
buf ( n3893 , n3808 );
xor ( n3894 , n3892 , n3893 );
buf ( n3895 , n406 );
buf ( n3896 , n412 );
and ( n3897 , n3895 , n3896 );
buf ( n3898 , n3897 );
buf ( n3899 , n3898 );
buf ( n3900 , n3736 );
buf ( n3901 , n3732 );
nor ( n3902 , n3900 , n3901 );
buf ( n3903 , n3902 );
buf ( n3904 , n3903 );
xor ( n3905 , n3899 , n3904 );
buf ( n3906 , n3122 );
not ( n3907 , n3906 );
buf ( n3908 , n388 );
not ( n3909 , n3908 );
buf ( n3910 , n3909 );
buf ( n3911 , n3910 );
nor ( n3912 , n3907 , n3911 );
buf ( n3913 , n3912 );
buf ( n3914 , n3913 );
xor ( n3915 , n3905 , n3914 );
buf ( n3916 , n3915 );
buf ( n3917 , n3916 );
buf ( n3918 , n3793 );
xor ( n3919 , n3917 , n3918 );
not ( n3920 , n3258 );
buf ( n3921 , n3920 );
buf ( n3922 , n3709 );
nor ( n3923 , n3921 , n3922 );
buf ( n3924 , n3923 );
buf ( n3925 , n3924 );
xor ( n3926 , n3919 , n3925 );
buf ( n3927 , n3926 );
buf ( n3928 , n3927 );
xor ( n3929 , n3894 , n3928 );
buf ( n3930 , n3929 );
buf ( n3931 , n3930 );
xor ( n3932 , n3886 , n3887 );
xor ( n3933 , n3932 , n3931 );
buf ( n3934 , n3933 );
xor ( n3935 , n3886 , n3887 );
and ( n3936 , n3935 , n3931 );
and ( n3937 , n3886 , n3887 );
or ( n3938 , n3936 , n3937 );
buf ( n3939 , n3938 );
xor ( n3940 , n3431 , n3662 );
and ( n3941 , n3940 , n3664 );
and ( n3942 , n3431 , n3662 );
or ( n3943 , n3941 , n3942 );
and ( n3944 , n389 , n390 );
xor ( n3945 , n389 , n3944 );
and ( n3946 , n3660 , n3661 );
xor ( n3947 , n3945 , n3946 );
nand ( n3948 , n387 , n392 );
not ( n3949 , n3948 );
and ( n3950 , n386 , n393 );
xor ( n3951 , n3949 , n3950 );
and ( n3952 , n388 , n391 );
xor ( n3953 , n3951 , n3952 );
xor ( n3954 , n3947 , n3953 );
not ( n3955 , n3954 );
xor ( n3956 , n3943 , n3955 );
not ( n3957 , n3685 );
not ( n3958 , n3678 );
or ( n3959 , n3957 , n3958 );
buf ( n3960 , n3683 );
nand ( n3961 , n3959 , n3960 );
xnor ( n3962 , n3956 , n3961 );
buf ( n3963 , n3962 );
buf ( n3964 , n3963 );
buf ( n3965 , n393 );
and ( n3966 , n3964 , n3965 );
buf ( n3967 , n3966 );
buf ( n3968 , n3967 );
buf ( n3969 , n3798 );
buf ( n3970 , n3397 );
buf ( n3971 , n390 );
and ( n3972 , n3970 , n3971 );
buf ( n3973 , n3972 );
buf ( n3974 , n3973 );
xor ( n3975 , n3969 , n3974 );
buf ( n3976 , n3135 );
buf ( n3977 , n387 );
and ( n3978 , n3976 , n3977 );
buf ( n3979 , n3978 );
buf ( n3980 , n3979 );
buf ( n3981 , n3624 );
xor ( n3982 , n3980 , n3981 );
buf ( n3983 , n3644 );
xor ( n3984 , n3982 , n3983 );
buf ( n3985 , n3984 );
buf ( n3986 , n3985 );
xor ( n3987 , n3975 , n3986 );
buf ( n3988 , n3987 );
buf ( n3989 , n3988 );
xor ( n3990 , n3968 , n3989 );
buf ( n3991 , n3813 );
xor ( n3992 , n3990 , n3991 );
buf ( n3993 , n3992 );
buf ( n3994 , n3993 );
buf ( n3995 , n3823 );
buf ( n3996 , n3934 );
xor ( n3997 , n3994 , n3995 );
xor ( n3998 , n3997 , n3996 );
buf ( n3999 , n3998 );
xor ( n4000 , n3994 , n3995 );
and ( n4001 , n4000 , n3996 );
and ( n4002 , n3994 , n3995 );
or ( n4003 , n4001 , n4002 );
buf ( n4004 , n4003 );
xor ( n4005 , n3899 , n3904 );
and ( n4006 , n4005 , n3914 );
and ( n4007 , n3899 , n3904 );
or ( n4008 , n4006 , n4007 );
buf ( n4009 , n4008 );
xor ( n4010 , n3980 , n3981 );
and ( n4011 , n4010 , n3983 );
and ( n4012 , n3980 , n3981 );
or ( n4013 , n4011 , n4012 );
buf ( n4014 , n4013 );
xor ( n4015 , n3870 , n3871 );
and ( n4016 , n4015 , n3873 );
and ( n4017 , n3870 , n3871 );
or ( n4018 , n4016 , n4017 );
buf ( n4019 , n4018 );
xor ( n4020 , n3917 , n3918 );
and ( n4021 , n4020 , n3925 );
and ( n4022 , n3917 , n3918 );
or ( n4023 , n4021 , n4022 );
buf ( n4024 , n4023 );
xor ( n4025 , n3969 , n3974 );
and ( n4026 , n4025 , n3986 );
and ( n4027 , n3969 , n3974 );
or ( n4028 , n4026 , n4027 );
buf ( n4029 , n4028 );
xor ( n4030 , n3876 , n3881 );
and ( n4031 , n4030 , n3883 );
and ( n4032 , n3876 , n3881 );
or ( n4033 , n4031 , n4032 );
buf ( n4034 , n4033 );
xor ( n4035 , n3892 , n3893 );
and ( n4036 , n4035 , n3928 );
and ( n4037 , n3892 , n3893 );
or ( n4038 , n4036 , n4037 );
buf ( n4039 , n4038 );
xor ( n4040 , n3968 , n3989 );
and ( n4041 , n4040 , n3991 );
and ( n4042 , n3968 , n3989 );
or ( n4043 , n4041 , n4042 );
buf ( n4044 , n4043 );
buf ( n4045 , n402 );
buf ( n4046 , n415 );
and ( n4047 , n4045 , n4046 );
buf ( n4048 , n4047 );
buf ( n4049 , n4048 );
buf ( n4050 , n403 );
buf ( n4051 , n414 );
and ( n4052 , n4050 , n4051 );
buf ( n4053 , n4052 );
buf ( n4054 , n4053 );
buf ( n4055 , n406 );
buf ( n4056 , n411 );
and ( n4057 , n4055 , n4056 );
buf ( n4058 , n4057 );
buf ( n4059 , n4058 );
xor ( n4060 , n4049 , n4054 );
xor ( n4061 , n4060 , n4059 );
buf ( n4062 , n4061 );
xor ( n4063 , n4049 , n4054 );
and ( n4064 , n4063 , n4059 );
and ( n4065 , n4049 , n4054 );
or ( n4066 , n4064 , n4065 );
buf ( n4067 , n4066 );
buf ( n4068 , n404 );
buf ( n4069 , n413 );
and ( n4070 , n4068 , n4069 );
buf ( n4071 , n4070 );
buf ( n4072 , n4071 );
buf ( n4073 , n405 );
buf ( n4074 , n412 );
and ( n4075 , n4073 , n4074 );
buf ( n4076 , n4075 );
buf ( n4077 , n4076 );
buf ( n4078 , n407 );
buf ( n4079 , n410 );
and ( n4080 , n4078 , n4079 );
buf ( n4081 , n4080 );
buf ( n4082 , n4081 );
xor ( n4083 , n4072 , n4077 );
xor ( n4084 , n4083 , n4082 );
buf ( n4085 , n4084 );
xor ( n4086 , n4072 , n4077 );
and ( n4087 , n4086 , n4082 );
and ( n4088 , n4072 , n4077 );
or ( n4089 , n4087 , n4088 );
buf ( n4090 , n4089 );
buf ( n4091 , n4044 );
buf ( n4092 , n4029 );
buf ( n4093 , n3689 );
buf ( n4094 , n391 );
and ( n4095 , n4093 , n4094 );
buf ( n4096 , n4095 );
buf ( n4097 , n4096 );
xor ( n4098 , n4092 , n4097 );
buf ( n4099 , n4009 );
buf ( n4100 , n3135 );
buf ( n4101 , n386 );
and ( n4102 , n4100 , n4101 );
buf ( n4103 , n4102 );
buf ( n4104 , n4103 );
buf ( n4105 , n3122 );
buf ( n4106 , n387 );
and ( n4107 , n4105 , n4106 );
buf ( n4108 , n4107 );
buf ( n4109 , n4108 );
xor ( n4110 , n4104 , n4109 );
buf ( n4111 , n3869 );
xor ( n4112 , n4110 , n4111 );
buf ( n4113 , n4112 );
buf ( n4114 , n4113 );
xor ( n4115 , n4099 , n4114 );
buf ( n4116 , n3920 );
buf ( n4117 , n3910 );
nor ( n4118 , n4116 , n4117 );
buf ( n4119 , n4118 );
buf ( n4120 , n4119 );
xor ( n4121 , n4115 , n4120 );
buf ( n4122 , n4121 );
buf ( n4123 , n4122 );
xor ( n4124 , n4098 , n4123 );
buf ( n4125 , n4124 );
buf ( n4126 , n4125 );
buf ( n4127 , n3963 );
buf ( n4128 , n392 );
and ( n4129 , n4127 , n4128 );
buf ( n4130 , n4129 );
buf ( n4131 , n4130 );
buf ( n4132 , n4014 );
buf ( n4133 , n3397 );
buf ( n4134 , n389 );
and ( n4135 , n4133 , n4134 );
buf ( n4136 , n4135 );
buf ( n4137 , n4136 );
xor ( n4138 , n4132 , n4137 );
buf ( n4139 , n4019 );
xor ( n4140 , n4138 , n4139 );
buf ( n4141 , n4140 );
buf ( n4142 , n4141 );
xor ( n4143 , n4131 , n4142 );
not ( n4144 , n3954 );
not ( n4145 , n3943 );
nand ( n4146 , n4144 , n4145 );
not ( n4147 , n4146 );
not ( n4148 , n3961 );
or ( n4149 , n4147 , n4148 );
nand ( n4150 , n3954 , n3943 );
nand ( n4151 , n4149 , n4150 );
buf ( n4152 , n4151 );
and ( n4153 , n389 , n3944 );
xor ( n4154 , n3949 , n3950 );
and ( n4155 , n4154 , n3952 );
and ( n4156 , n3949 , n3950 );
or ( n4157 , n4155 , n4156 );
xor ( n4158 , n4153 , n4157 );
and ( n4159 , n388 , n390 );
and ( n4160 , n387 , n391 );
xor ( n4161 , n4159 , n4160 );
and ( n4162 , n386 , n392 );
xor ( n4163 , n4161 , n4162 );
xor ( n4164 , n4158 , n4163 );
not ( n4165 , n4164 );
xor ( n4166 , n3945 , n3946 );
and ( n4167 , n4166 , n3953 );
and ( n4168 , n3945 , n3946 );
or ( n4169 , n4167 , n4168 );
not ( n4170 , n4169 );
nand ( n4171 , n4165 , n4170 );
nand ( n4172 , n4164 , n4169 );
nand ( n4173 , n4171 , n4172 );
not ( n4174 , n4173 );
and ( n4175 , n4152 , n4174 );
not ( n4176 , n4152 );
and ( n4177 , n4176 , n4173 );
nor ( n4178 , n4175 , n4177 );
buf ( n4179 , n4178 );
buf ( n4180 , n4179 );
buf ( n4181 , n4180 );
buf ( n4182 , n4181 );
buf ( n4183 , n393 );
and ( n4184 , n4182 , n4183 );
buf ( n4185 , n4184 );
buf ( n4186 , n4185 );
xor ( n4187 , n4143 , n4186 );
buf ( n4188 , n4187 );
buf ( n4189 , n4188 );
xor ( n4190 , n4091 , n4126 );
xor ( n4191 , n4190 , n4189 );
buf ( n4192 , n4191 );
xor ( n4193 , n4091 , n4126 );
and ( n4194 , n4193 , n4189 );
and ( n4195 , n4091 , n4126 );
or ( n4196 , n4194 , n4195 );
buf ( n4197 , n4196 );
buf ( n4198 , n4034 );
buf ( n4199 , n3846 );
buf ( n4200 , n4085 );
xor ( n4201 , n4199 , n4200 );
buf ( n4202 , n4062 );
xor ( n4203 , n4201 , n4202 );
buf ( n4204 , n4203 );
buf ( n4205 , n4204 );
buf ( n4206 , n3565 );
buf ( n4207 , n390 );
and ( n4208 , n4206 , n4207 );
buf ( n4209 , n4208 );
buf ( n4210 , n4209 );
xor ( n4211 , n4205 , n4210 );
buf ( n4212 , n4024 );
xor ( n4213 , n4211 , n4212 );
buf ( n4214 , n4213 );
buf ( n4215 , n4214 );
xor ( n4216 , n4198 , n4215 );
buf ( n4217 , n4039 );
xor ( n4218 , n4216 , n4217 );
buf ( n4219 , n4218 );
buf ( n4220 , n4219 );
buf ( n4221 , n3939 );
buf ( n4222 , n4192 );
xor ( n4223 , n4220 , n4221 );
xor ( n4224 , n4223 , n4222 );
buf ( n4225 , n4224 );
xor ( n4226 , n4220 , n4221 );
and ( n4227 , n4226 , n4222 );
and ( n4228 , n4220 , n4221 );
or ( n4229 , n4227 , n4228 );
buf ( n4230 , n4229 );
xor ( n4231 , n4104 , n4109 );
and ( n4232 , n4231 , n4111 );
or ( n4233 , n4232 , C0 );
buf ( n4234 , n4233 );
xor ( n4235 , n4199 , n4200 );
and ( n4236 , n4235 , n4202 );
and ( n4237 , n4199 , n4200 );
or ( n4238 , n4236 , n4237 );
buf ( n4239 , n4238 );
xor ( n4240 , n4099 , n4114 );
and ( n4241 , n4240 , n4120 );
and ( n4242 , n4099 , n4114 );
or ( n4243 , n4241 , n4242 );
buf ( n4244 , n4243 );
xor ( n4245 , n4132 , n4137 );
and ( n4246 , n4245 , n4139 );
and ( n4247 , n4132 , n4137 );
or ( n4248 , n4246 , n4247 );
buf ( n4249 , n4248 );
xor ( n4250 , n4205 , n4210 );
and ( n4251 , n4250 , n4212 );
and ( n4252 , n4205 , n4210 );
or ( n4253 , n4251 , n4252 );
buf ( n4254 , n4253 );
xor ( n4255 , n4092 , n4097 );
and ( n4256 , n4255 , n4123 );
and ( n4257 , n4092 , n4097 );
or ( n4258 , n4256 , n4257 );
buf ( n4259 , n4258 );
xor ( n4260 , n4131 , n4142 );
and ( n4261 , n4260 , n4186 );
and ( n4262 , n4131 , n4142 );
or ( n4263 , n4261 , n4262 );
buf ( n4264 , n4263 );
xor ( n4265 , n4198 , n4215 );
and ( n4266 , n4265 , n4217 );
and ( n4267 , n4198 , n4215 );
or ( n4268 , n4266 , n4267 );
buf ( n4269 , n4268 );
buf ( n4270 , n406 );
buf ( n4271 , n410 );
and ( n4272 , n4270 , n4271 );
buf ( n4273 , n4272 );
buf ( n4274 , n4273 );
buf ( n4275 , n404 );
buf ( n4276 , n412 );
and ( n4277 , n4275 , n4276 );
buf ( n4278 , n4277 );
buf ( n4279 , n4278 );
buf ( n4280 , n405 );
buf ( n4281 , n411 );
and ( n4282 , n4280 , n4281 );
buf ( n4283 , n4282 );
buf ( n4284 , n4283 );
xor ( n4285 , n4274 , n4279 );
xor ( n4286 , n4285 , n4284 );
buf ( n4287 , n4286 );
xor ( n4288 , n4274 , n4279 );
and ( n4289 , n4288 , n4284 );
and ( n4290 , n4274 , n4279 );
or ( n4291 , n4289 , n4290 );
buf ( n4292 , n4291 );
buf ( n4293 , n3122 );
buf ( n4294 , n386 );
and ( n4295 , n4293 , n4294 );
buf ( n4296 , n4295 );
buf ( n4297 , n4296 );
buf ( n4298 , n402 );
buf ( n4299 , n414 );
and ( n4300 , n4298 , n4299 );
buf ( n4301 , n4300 );
buf ( n4302 , n4301 );
buf ( n4303 , n403 );
buf ( n4304 , n413 );
and ( n4305 , n4303 , n4304 );
buf ( n4306 , n4305 );
buf ( n4307 , n4306 );
xor ( n4308 , n4302 , n4307 );
buf ( n4309 , n4308 );
buf ( n4310 , n4309 );
buf ( n4311 , n4090 );
xor ( n4312 , n4297 , n4310 );
xor ( n4313 , n4312 , n4311 );
buf ( n4314 , n4313 );
xor ( n4315 , n4297 , n4310 );
and ( n4316 , n4315 , n4311 );
and ( n4317 , n4297 , n4310 );
or ( n4318 , n4316 , n4317 );
buf ( n4319 , n4318 );
buf ( n4320 , n4259 );
buf ( n4321 , n4244 );
buf ( n4322 , n3257 );
not ( n4323 , n4322 );
buf ( n4324 , n387 );
not ( n4325 , n4324 );
buf ( n4326 , n4325 );
buf ( n4327 , n4326 );
nor ( n4328 , n4323 , n4327 );
buf ( n4329 , n4328 );
buf ( n4330 , n4329 );
buf ( n4331 , n4314 );
xor ( n4332 , n4330 , n4331 );
buf ( n4333 , n4239 );
xor ( n4334 , n4332 , n4333 );
buf ( n4335 , n4334 );
buf ( n4336 , n4335 );
xor ( n4337 , n4321 , n4336 );
not ( n4338 , n390 );
buf ( n4339 , n3689 );
not ( n4340 , n4339 );
buf ( n4341 , n4340 );
nor ( n4342 , n4338 , n4341 );
buf ( n4343 , n4342 );
xor ( n4344 , n4337 , n4343 );
buf ( n4345 , n4344 );
buf ( n4346 , n4345 );
xor ( n4347 , n4320 , n4346 );
buf ( n4348 , n4264 );
xor ( n4349 , n4347 , n4348 );
buf ( n4350 , n4349 );
buf ( n4351 , n4350 );
buf ( n4352 , n4197 );
buf ( n4353 , n3962 );
buf ( n4354 , n391 );
and ( n4355 , n4353 , n4354 );
buf ( n4356 , n4355 );
buf ( n4357 , n4356 );
buf ( n4358 , n4249 );
xor ( n4359 , n4357 , n4358 );
buf ( n4360 , n4254 );
xor ( n4361 , n4359 , n4360 );
buf ( n4362 , n4361 );
buf ( n4363 , n4362 );
buf ( n4364 , n4181 );
buf ( n4365 , n392 );
and ( n4366 , n4364 , n4365 );
buf ( n4367 , n4366 );
buf ( n4368 , n4367 );
buf ( n4369 , n3397 );
buf ( n4370 , n388 );
and ( n4371 , n4369 , n4370 );
buf ( n4372 , n4371 );
buf ( n4373 , n4372 );
buf ( n4374 , n3565 );
buf ( n4375 , n389 );
and ( n4376 , n4374 , n4375 );
buf ( n4377 , n4376 );
buf ( n4378 , n4377 );
xor ( n4379 , n4373 , n4378 );
buf ( n4380 , n4067 );
buf ( n4381 , n4287 );
xor ( n4382 , n4380 , n4381 );
buf ( n4383 , n4234 );
xor ( n4384 , n4382 , n4383 );
buf ( n4385 , n4384 );
buf ( n4386 , n4385 );
xor ( n4387 , n4379 , n4386 );
buf ( n4388 , n4387 );
buf ( n4389 , n4388 );
xor ( n4390 , n4368 , n4389 );
not ( n4391 , n4171 );
not ( n4392 , n4152 );
or ( n4393 , n4391 , n4392 );
nand ( n4394 , n4393 , n4172 );
xor ( n4395 , n4153 , n4157 );
and ( n4396 , n4395 , n4163 );
and ( n4397 , n4153 , n4157 );
or ( n4398 , n4396 , n4397 );
and ( n4399 , n387 , n390 );
xor ( n4400 , n4159 , n4160 );
and ( n4401 , n4400 , n4162 );
and ( n4402 , n4159 , n4160 );
or ( n4403 , n4401 , n4402 );
xor ( n4404 , n4399 , n4403 );
and ( n4405 , n388 , n389 );
xor ( n4406 , n388 , n4405 );
and ( n4407 , n386 , n391 );
xor ( n4408 , n4406 , n4407 );
xor ( n4409 , n4404 , n4408 );
buf ( n4410 , n4409 );
xor ( n4411 , n4398 , n4410 );
buf ( n4412 , n4411 );
and ( n4413 , n4394 , n4412 );
not ( n4414 , n4394 );
not ( n4415 , n4411 );
and ( n4416 , n4414 , n4415 );
nor ( n4417 , n4413 , n4416 );
buf ( n4418 , n4417 );
buf ( n4419 , n393 );
and ( n4420 , n4418 , n4419 );
buf ( n4421 , n4420 );
buf ( n4422 , n4421 );
xor ( n4423 , n4390 , n4422 );
buf ( n4424 , n4423 );
buf ( n4425 , n4424 );
xor ( n4426 , n4363 , n4425 );
buf ( n4427 , n4269 );
xor ( n4428 , n4426 , n4427 );
buf ( n4429 , n4428 );
buf ( n4430 , n4429 );
xor ( n4431 , n4351 , n4352 );
xor ( n4432 , n4431 , n4430 );
buf ( n4433 , n4432 );
xor ( n4434 , n4351 , n4352 );
and ( n4435 , n4434 , n4430 );
and ( n4436 , n4351 , n4352 );
or ( n4437 , n4435 , n4436 );
buf ( n4438 , n4437 );
xor ( n4439 , n4380 , n4381 );
and ( n4440 , n4439 , n4383 );
and ( n4441 , n4380 , n4381 );
or ( n4442 , n4440 , n4441 );
buf ( n4443 , n4442 );
xor ( n4444 , n4330 , n4331 );
and ( n4445 , n4444 , n4333 );
and ( n4446 , n4330 , n4331 );
or ( n4447 , n4445 , n4446 );
buf ( n4448 , n4447 );
xor ( n4449 , n4373 , n4378 );
and ( n4450 , n4449 , n4386 );
and ( n4451 , n4373 , n4378 );
or ( n4452 , n4450 , n4451 );
buf ( n4453 , n4452 );
xor ( n4454 , n4321 , n4336 );
and ( n4455 , n4454 , n4343 );
and ( n4456 , n4321 , n4336 );
or ( n4457 , n4455 , n4456 );
buf ( n4458 , n4457 );
xor ( n4459 , n4357 , n4358 );
and ( n4460 , n4459 , n4360 );
and ( n4461 , n4357 , n4358 );
or ( n4462 , n4460 , n4461 );
buf ( n4463 , n4462 );
xor ( n4464 , n4368 , n4389 );
and ( n4465 , n4464 , n4422 );
and ( n4466 , n4368 , n4389 );
or ( n4467 , n4465 , n4466 );
buf ( n4468 , n4467 );
xor ( n4469 , n4320 , n4346 );
and ( n4470 , n4469 , n4348 );
and ( n4471 , n4320 , n4346 );
or ( n4472 , n4470 , n4471 );
buf ( n4473 , n4472 );
xor ( n4474 , n4363 , n4425 );
and ( n4475 , n4474 , n4427 );
and ( n4476 , n4363 , n4425 );
or ( n4477 , n4475 , n4476 );
buf ( n4478 , n4477 );
buf ( n4479 , n402 );
buf ( n4480 , n413 );
and ( n4481 , n4479 , n4480 );
buf ( n4482 , n4481 );
buf ( n4483 , n4482 );
buf ( n4484 , n403 );
buf ( n4485 , n412 );
and ( n4486 , n4484 , n4485 );
buf ( n4487 , n4486 );
buf ( n4488 , n4487 );
buf ( n4489 , n404 );
buf ( n4490 , n411 );
and ( n4491 , n4489 , n4490 );
buf ( n4492 , n4491 );
buf ( n4493 , n4492 );
xor ( n4494 , n4483 , n4488 );
xor ( n4495 , n4494 , n4493 );
buf ( n4496 , n4495 );
xor ( n4497 , n4483 , n4488 );
and ( n4498 , n4497 , n4493 );
and ( n4499 , n4483 , n4488 );
or ( n4500 , n4498 , n4499 );
buf ( n4501 , n4500 );
buf ( n4502 , n405 );
buf ( n4503 , n410 );
and ( n4504 , n4502 , n4503 );
buf ( n4505 , n4504 );
buf ( n4506 , n4505 );
and ( n4507 , n4302 , n4307 );
buf ( n4508 , n4507 );
buf ( n4509 , n4508 );
buf ( n4510 , n4292 );
xor ( n4511 , n4506 , n4509 );
xor ( n4512 , n4511 , n4510 );
buf ( n4513 , n4512 );
xor ( n4514 , n4506 , n4509 );
and ( n4515 , n4514 , n4510 );
and ( n4516 , n4506 , n4509 );
or ( n4517 , n4515 , n4516 );
buf ( n4518 , n4517 );
buf ( n4519 , n4463 );
buf ( n4520 , n4448 );
buf ( n4521 , n3257 );
buf ( n4522 , n386 );
and ( n4523 , n4521 , n4522 );
buf ( n4524 , n4523 );
buf ( n4525 , n4524 );
buf ( n4526 , n3397 );
buf ( n4527 , n387 );
and ( n4528 , n4526 , n4527 );
buf ( n4529 , n4528 );
buf ( n4530 , n4529 );
xor ( n4531 , n4525 , n4530 );
buf ( n4532 , n3565 );
buf ( n4533 , n388 );
and ( n4534 , n4532 , n4533 );
buf ( n4535 , n4534 );
buf ( n4536 , n4535 );
xor ( n4537 , n4531 , n4536 );
buf ( n4538 , n4537 );
buf ( n4539 , n4538 );
xor ( n4540 , n4520 , n4539 );
and ( n4541 , n390 , n3962 );
buf ( n4542 , n4541 );
xor ( n4543 , n4540 , n4542 );
buf ( n4544 , n4543 );
buf ( n4545 , n4544 );
xor ( n4546 , n4519 , n4545 );
buf ( n4547 , n4468 );
xor ( n4548 , n4546 , n4547 );
buf ( n4549 , n4548 );
buf ( n4550 , n4549 );
buf ( n4551 , n4478 );
buf ( n4552 , n4453 );
buf ( n4553 , n4181 );
buf ( n4554 , n391 );
and ( n4555 , n4553 , n4554 );
buf ( n4556 , n4555 );
buf ( n4557 , n4556 );
xor ( n4558 , n4552 , n4557 );
buf ( n4559 , n4417 );
buf ( n4560 , n392 );
and ( n4561 , n4559 , n4560 );
buf ( n4562 , n4561 );
buf ( n4563 , n4562 );
xor ( n4564 , n4558 , n4563 );
buf ( n4565 , n4564 );
buf ( n4566 , n4565 );
buf ( n4567 , n4458 );
not ( n4568 , n4164 );
not ( n4569 , n4169 );
and ( n4570 , n4568 , n4569 );
nor ( n4571 , n4409 , n4398 );
nor ( n4572 , n4570 , n4571 );
not ( n4573 , n4572 );
not ( n4574 , n4151 );
or ( n4575 , n4573 , n4574 );
not ( n4576 , n4409 );
not ( n4577 , n4398 );
nand ( n4578 , n4576 , n4577 );
not ( n4579 , n4164 );
nor ( n4580 , n4579 , n4170 );
and ( n4581 , n4578 , n4580 );
nor ( n4582 , n4576 , n4577 );
nor ( n4583 , n4581 , n4582 );
nand ( n4584 , n4575 , n4583 );
buf ( n4585 , n4584 );
and ( n4586 , n387 , n389 );
and ( n4587 , n386 , n390 );
xor ( n4588 , n4586 , n4587 );
xor ( n4589 , n388 , n4405 );
and ( n4590 , n4589 , n4407 );
and ( n4591 , n388 , n4405 );
or ( n4592 , n4590 , n4591 );
xor ( n4593 , n4588 , n4592 );
xor ( n4594 , n4399 , n4403 );
and ( n4595 , n4594 , n4408 );
and ( n4596 , n4399 , n4403 );
or ( n4597 , n4595 , n4596 );
not ( n4598 , n4597 );
and ( n4599 , n4593 , n4598 );
not ( n4600 , n4593 );
and ( n4601 , n4600 , n4597 );
nor ( n4602 , n4599 , n4601 );
not ( n4603 , n4602 );
and ( n4604 , n4585 , n4603 );
not ( n4605 , n4585 );
and ( n4606 , n4605 , n4602 );
nor ( n4607 , n4604 , n4606 );
buf ( n4608 , n4607 );
buf ( n4609 , n393 );
and ( n4610 , n4608 , n4609 );
buf ( n4611 , n4610 );
buf ( n4612 , n4611 );
xor ( n4613 , n4567 , n4612 );
buf ( n4614 , n4443 );
buf ( n4615 , n4496 );
buf ( n4616 , n4319 );
xor ( n4617 , n4615 , n4616 );
buf ( n4618 , n4513 );
xor ( n4619 , n4617 , n4618 );
buf ( n4620 , n4619 );
buf ( n4621 , n4620 );
xor ( n4622 , n4614 , n4621 );
buf ( n4623 , n4341 );
buf ( n4624 , n3709 );
nor ( n4625 , n4623 , n4624 );
buf ( n4626 , n4625 );
buf ( n4627 , n4626 );
xor ( n4628 , n4622 , n4627 );
buf ( n4629 , n4628 );
buf ( n4630 , n4629 );
xor ( n4631 , n4613 , n4630 );
buf ( n4632 , n4631 );
buf ( n4633 , n4632 );
xor ( n4634 , n4566 , n4633 );
buf ( n4635 , n4473 );
xor ( n4636 , n4634 , n4635 );
buf ( n4637 , n4636 );
buf ( n4638 , n4637 );
xor ( n4639 , n4550 , n4551 );
xor ( n4640 , n4639 , n4638 );
buf ( n4641 , n4640 );
xor ( n4642 , n4550 , n4551 );
and ( n4643 , n4642 , n4638 );
and ( n4644 , n4550 , n4551 );
or ( n4645 , n4643 , n4644 );
buf ( n4646 , n4645 );
xor ( n4647 , n4615 , n4616 );
and ( n4648 , n4647 , n4618 );
and ( n4649 , n4615 , n4616 );
or ( n4650 , n4648 , n4649 );
buf ( n4651 , n4650 );
xor ( n4652 , n4525 , n4530 );
and ( n4653 , n4652 , n4536 );
and ( n4654 , n4525 , n4530 );
or ( n4655 , n4653 , n4654 );
buf ( n4656 , n4655 );
xor ( n4657 , n4614 , n4621 );
and ( n4658 , n4657 , n4627 );
and ( n4659 , n4614 , n4621 );
or ( n4660 , n4658 , n4659 );
buf ( n4661 , n4660 );
xor ( n4662 , n4520 , n4539 );
and ( n4663 , n4662 , n4542 );
and ( n4664 , n4520 , n4539 );
or ( n4665 , n4663 , n4664 );
buf ( n4666 , n4665 );
xor ( n4667 , n4552 , n4557 );
and ( n4668 , n4667 , n4563 );
and ( n4669 , n4552 , n4557 );
or ( n4670 , n4668 , n4669 );
buf ( n4671 , n4670 );
xor ( n4672 , n4567 , n4612 );
and ( n4673 , n4672 , n4630 );
and ( n4674 , n4567 , n4612 );
or ( n4675 , n4673 , n4674 );
buf ( n4676 , n4675 );
xor ( n4677 , n4519 , n4545 );
and ( n4678 , n4677 , n4547 );
and ( n4679 , n4519 , n4545 );
or ( n4680 , n4678 , n4679 );
buf ( n4681 , n4680 );
xor ( n4682 , n4566 , n4633 );
and ( n4683 , n4682 , n4635 );
and ( n4684 , n4566 , n4633 );
or ( n4685 , n4683 , n4684 );
buf ( n4686 , n4685 );
buf ( n4687 , n402 );
buf ( n4688 , n412 );
and ( n4689 , n4687 , n4688 );
buf ( n4690 , n4689 );
buf ( n4691 , n4690 );
buf ( n4692 , n403 );
buf ( n4693 , n411 );
and ( n4694 , n4692 , n4693 );
buf ( n4695 , n4694 );
buf ( n4696 , n4695 );
buf ( n4697 , n404 );
buf ( n4698 , n410 );
and ( n4699 , n4697 , n4698 );
buf ( n4700 , n4699 );
buf ( n4701 , n4700 );
xor ( n4702 , n4691 , n4696 );
xor ( n4703 , n4702 , n4701 );
buf ( n4704 , n4703 );
xor ( n4705 , n4691 , n4696 );
and ( n4706 , n4705 , n4701 );
and ( n4707 , n4691 , n4696 );
or ( n4708 , n4706 , n4707 );
buf ( n4709 , n4708 );
buf ( n4710 , n4501 );
buf ( n4711 , n4704 );
buf ( n4712 , n4518 );
xor ( n4713 , n4710 , n4711 );
xor ( n4714 , n4713 , n4712 );
buf ( n4715 , n4714 );
xor ( n4716 , n4710 , n4711 );
and ( n4717 , n4716 , n4712 );
and ( n4718 , n4710 , n4711 );
or ( n4719 , n4717 , n4718 );
buf ( n4720 , n4719 );
buf ( n4721 , n3397 );
buf ( n4722 , n386 );
and ( n4723 , n4721 , n4722 );
buf ( n4724 , n4723 );
buf ( n4725 , n4724 );
buf ( n4726 , n3565 );
buf ( n4727 , n387 );
and ( n4728 , n4726 , n4727 );
buf ( n4729 , n4728 );
buf ( n4730 , n4729 );
buf ( n4731 , n4651 );
xor ( n4732 , n4725 , n4730 );
xor ( n4733 , n4732 , n4731 );
buf ( n4734 , n4733 );
xor ( n4735 , n4725 , n4730 );
and ( n4736 , n4735 , n4731 );
and ( n4737 , n4725 , n4730 );
or ( n4738 , n4736 , n4737 );
buf ( n4739 , n4738 );
buf ( n4740 , n4715 );
buf ( n4741 , n3689 );
buf ( n4742 , n388 );
and ( n4743 , n4741 , n4742 );
buf ( n4744 , n4743 );
buf ( n4745 , n4744 );
buf ( n4746 , n4656 );
xor ( n4747 , n4740 , n4745 );
xor ( n4748 , n4747 , n4746 );
buf ( n4749 , n4748 );
xor ( n4750 , n4740 , n4745 );
and ( n4751 , n4750 , n4746 );
and ( n4752 , n4740 , n4745 );
or ( n4753 , n4751 , n4752 );
buf ( n4754 , n4753 );
and ( n4755 , n3963 , n389 );
buf ( n4756 , n4755 );
buf ( n4757 , n4734 );
buf ( n4758 , n4181 );
buf ( n4759 , n390 );
and ( n4760 , n4758 , n4759 );
buf ( n4761 , n4760 );
buf ( n4762 , n4761 );
xor ( n4763 , n4756 , n4757 );
xor ( n4764 , n4763 , n4762 );
buf ( n4765 , n4764 );
xor ( n4766 , n4756 , n4757 );
and ( n4767 , n4766 , n4762 );
and ( n4768 , n4756 , n4757 );
or ( n4769 , n4767 , n4768 );
buf ( n4770 , n4769 );
buf ( n4771 , n4661 );
and ( n4772 , n4417 , n391 );
buf ( n4773 , n4772 );
buf ( n4774 , n4749 );
xor ( n4775 , n4771 , n4773 );
xor ( n4776 , n4775 , n4774 );
buf ( n4777 , n4776 );
xor ( n4778 , n4771 , n4773 );
and ( n4779 , n4778 , n4774 );
and ( n4780 , n4771 , n4773 );
or ( n4781 , n4779 , n4780 );
buf ( n4782 , n4781 );
buf ( n4783 , n4666 );
not ( n4784 , n4593 );
nand ( n4785 , n4784 , n4598 );
not ( n4786 , n4785 );
not ( n4787 , n4584 );
or ( n4788 , n4786 , n4787 );
nand ( n4789 , n4593 , n4597 );
buf ( n4790 , n4789 );
nand ( n4791 , n4788 , n4790 );
and ( n4792 , n387 , n388 );
xor ( n4793 , n387 , n4792 );
and ( n4794 , n386 , n389 );
xor ( n4795 , n4793 , n4794 );
not ( n4796 , n4795 );
xor ( n4797 , n4586 , n4587 );
and ( n4798 , n4797 , n4592 );
and ( n4799 , n4586 , n4587 );
or ( n4800 , n4798 , n4799 );
not ( n4801 , n4800 );
or ( n4802 , n4796 , n4801 );
or ( n4803 , n4795 , n4800 );
nand ( n4804 , n4802 , n4803 );
not ( n4805 , n4804 );
and ( n4806 , n4791 , n4805 );
not ( n4807 , n4791 );
buf ( n4808 , n4804 );
and ( n4809 , n4807 , n4808 );
nor ( n4810 , n4806 , n4809 );
buf ( n4811 , n4810 );
buf ( n4812 , n4811 );
buf ( n4813 , n4812 );
buf ( n4814 , n4813 );
buf ( n4815 , n393 );
nand ( n4816 , n4814 , n4815 );
buf ( n4817 , n4816 );
buf ( n4818 , n4817 );
not ( n4819 , n4818 );
buf ( n4820 , n4819 );
buf ( n4821 , n4820 );
buf ( n4822 , n4607 );
not ( n4823 , n4822 );
buf ( n4824 , n3533 );
nor ( n4825 , n4823 , n4824 );
buf ( n4826 , n4825 );
buf ( n4827 , n4826 );
xor ( n4828 , n4783 , n4821 );
xor ( n4829 , n4828 , n4827 );
buf ( n4830 , n4829 );
xor ( n4831 , n4783 , n4821 );
and ( n4832 , n4831 , n4827 );
and ( n4833 , n4783 , n4821 );
or ( n4834 , n4832 , n4833 );
buf ( n4835 , n4834 );
buf ( n4836 , n4765 );
buf ( n4837 , n4671 );
buf ( n4838 , n4676 );
xor ( n4839 , n4836 , n4837 );
xor ( n4840 , n4839 , n4838 );
buf ( n4841 , n4840 );
xor ( n4842 , n4836 , n4837 );
and ( n4843 , n4842 , n4838 );
and ( n4844 , n4836 , n4837 );
or ( n4845 , n4843 , n4844 );
buf ( n4846 , n4845 );
buf ( n4847 , n4777 );
buf ( n4848 , n4830 );
buf ( n4849 , n4681 );
xor ( n4850 , n4847 , n4848 );
xor ( n4851 , n4850 , n4849 );
buf ( n4852 , n4851 );
xor ( n4853 , n4847 , n4848 );
and ( n4854 , n4853 , n4849 );
and ( n4855 , n4847 , n4848 );
or ( n4856 , n4854 , n4855 );
buf ( n4857 , n4856 );
buf ( n4858 , n4841 );
buf ( n4859 , n4686 );
buf ( n4860 , n4852 );
xor ( n4861 , n4858 , n4859 );
xor ( n4862 , n4861 , n4860 );
buf ( n4863 , n4862 );
xor ( n4864 , n4858 , n4859 );
and ( n4865 , n4864 , n4860 );
and ( n4866 , n4858 , n4859 );
or ( n4867 , n4865 , n4866 );
buf ( n4868 , n4867 );
buf ( n4869 , n402 );
buf ( n4870 , n411 );
and ( n4871 , n4869 , n4870 );
buf ( n4872 , n4871 );
buf ( n4873 , n4872 );
buf ( n4874 , n403 );
buf ( n4875 , n410 );
and ( n4876 , n4874 , n4875 );
buf ( n4877 , n4876 );
buf ( n4878 , n4877 );
buf ( n4879 , n4709 );
xor ( n4880 , n4873 , n4878 );
xor ( n4881 , n4880 , n4879 );
buf ( n4882 , n4881 );
xor ( n4883 , n4873 , n4878 );
and ( n4884 , n4883 , n4879 );
and ( n4885 , n4873 , n4878 );
or ( n4886 , n4884 , n4885 );
buf ( n4887 , n4886 );
buf ( n4888 , n4882 );
buf ( n4889 , n3565 );
buf ( n4890 , n386 );
and ( n4891 , n4889 , n4890 );
buf ( n4892 , n4891 );
buf ( n4893 , n4892 );
buf ( n4894 , n4720 );
xor ( n4895 , n4888 , n4893 );
xor ( n4896 , n4895 , n4894 );
buf ( n4897 , n4896 );
xor ( n4898 , n4888 , n4893 );
and ( n4899 , n4898 , n4894 );
and ( n4900 , n4888 , n4893 );
or ( n4901 , n4899 , n4900 );
buf ( n4902 , n4901 );
buf ( n4903 , n3689 );
buf ( n4904 , n387 );
and ( n4905 , n4903 , n4904 );
buf ( n4906 , n4905 );
buf ( n4907 , n4906 );
and ( n4908 , n3963 , n388 );
buf ( n4909 , n4908 );
buf ( n4910 , n4739 );
xor ( n4911 , n4907 , n4909 );
xor ( n4912 , n4911 , n4910 );
buf ( n4913 , n4912 );
xor ( n4914 , n4907 , n4909 );
and ( n4915 , n4914 , n4910 );
and ( n4916 , n4907 , n4909 );
or ( n4917 , n4915 , n4916 );
buf ( n4918 , n4917 );
buf ( n4919 , n4178 );
buf ( n4920 , n389 );
and ( n4921 , n4919 , n4920 );
buf ( n4922 , n4921 );
buf ( n4923 , n4922 );
buf ( n4924 , n4897 );
and ( n4925 , n4394 , n4412 );
not ( n4926 , n4394 );
and ( n4927 , n4926 , n4415 );
nor ( n4928 , n4925 , n4927 );
buf ( n4929 , n4928 );
buf ( n4930 , n390 );
and ( n4931 , n4929 , n4930 );
buf ( n4932 , n4931 );
buf ( n4933 , n4932 );
xor ( n4934 , n4923 , n4924 );
xor ( n4935 , n4934 , n4933 );
buf ( n4936 , n4935 );
xor ( n4937 , n4923 , n4924 );
and ( n4938 , n4937 , n4933 );
and ( n4939 , n4923 , n4924 );
or ( n4940 , n4938 , n4939 );
buf ( n4941 , n4940 );
buf ( n4942 , n4810 );
buf ( n4943 , n392 );
and ( n4944 , n4942 , n4943 );
buf ( n4945 , n4944 );
buf ( n4946 , n4945 );
buf ( n4947 , n4607 );
buf ( n4948 , n391 );
and ( n4949 , n4947 , n4948 );
buf ( n4950 , n4949 );
buf ( n4951 , n4950 );
buf ( n4952 , n4754 );
xor ( n4953 , n4946 , n4951 );
xor ( n4954 , n4953 , n4952 );
buf ( n4955 , n4954 );
xor ( n4956 , n4946 , n4951 );
and ( n4957 , n4956 , n4952 );
and ( n4958 , n4946 , n4951 );
or ( n4959 , n4957 , n4958 );
buf ( n4960 , n4959 );
buf ( n4961 , n4913 );
buf ( n4962 , n4770 );
not ( n4963 , n4803 );
not ( n4964 , n4785 );
not ( n4965 , n4584 );
or ( n4966 , n4964 , n4965 );
nand ( n4967 , n4966 , n4789 );
not ( n4968 , n4967 );
or ( n4969 , n4963 , n4968 );
nand ( n4970 , n4800 , n4795 );
nand ( n4971 , n4969 , n4970 );
xor ( n4972 , n387 , n4792 );
and ( n4973 , n4972 , n4794 );
and ( n4974 , n387 , n4792 );
or ( n4975 , n4973 , n4974 );
and ( n4976 , n386 , n388 );
nor ( n4977 , n4975 , n4976 );
not ( n4978 , n4977 );
nand ( n4979 , n4975 , n4976 );
nand ( n4980 , n4978 , n4979 );
not ( n4981 , n4980 );
and ( n4982 , n4971 , n4981 );
not ( n4983 , n4971 );
and ( n4984 , n4983 , n4980 );
nor ( n4985 , n4982 , n4984 );
buf ( n4986 , n4985 );
buf ( n4987 , n393 );
and ( n4988 , n4986 , n4987 );
buf ( n4989 , n4988 );
buf ( n4990 , n4989 );
xor ( n4991 , n4961 , n4962 );
xor ( n4992 , n4991 , n4990 );
buf ( n4993 , n4992 );
xor ( n4994 , n4961 , n4962 );
and ( n4995 , n4994 , n4990 );
and ( n4996 , n4961 , n4962 );
or ( n4997 , n4995 , n4996 );
buf ( n4998 , n4997 );
buf ( n4999 , n4936 );
buf ( n5000 , n4835 );
buf ( n5001 , n4782 );
xor ( n5002 , n4999 , n5000 );
xor ( n5003 , n5002 , n5001 );
buf ( n5004 , n5003 );
xor ( n5005 , n4999 , n5000 );
and ( n5006 , n5005 , n5001 );
and ( n5007 , n4999 , n5000 );
or ( n5008 , n5006 , n5007 );
buf ( n5009 , n5008 );
buf ( n5010 , n4955 );
buf ( n5011 , n4993 );
buf ( n5012 , n4846 );
xor ( n5013 , n5010 , n5011 );
xor ( n5014 , n5013 , n5012 );
buf ( n5015 , n5014 );
xor ( n5016 , n5010 , n5011 );
and ( n5017 , n5016 , n5012 );
and ( n5018 , n5010 , n5011 );
or ( n5019 , n5017 , n5018 );
buf ( n5020 , n5019 );
buf ( n5021 , n5004 );
buf ( n5022 , n4857 );
buf ( n5023 , n5015 );
xor ( n5024 , n5021 , n5022 );
xor ( n5025 , n5024 , n5023 );
buf ( n5026 , n5025 );
xor ( n5027 , n5021 , n5022 );
and ( n5028 , n5027 , n5023 );
and ( n5029 , n5021 , n5022 );
or ( n5030 , n5028 , n5029 );
buf ( n5031 , n5030 );
buf ( n5032 , n402 );
buf ( n5033 , n410 );
and ( n5034 , n5032 , n5033 );
buf ( n5035 , n5034 );
buf ( n5036 , n5035 );
buf ( n5037 , n4887 );
buf ( n5038 , n386 );
not ( n5039 , n5038 );
buf ( n5040 , n4341 );
nor ( n5041 , n5039 , n5040 );
buf ( n5042 , n5041 );
buf ( n5043 , n5042 );
xor ( n5044 , n5036 , n5037 );
xor ( n5045 , n5044 , n5043 );
buf ( n5046 , n5045 );
xor ( n5047 , n5036 , n5037 );
and ( n5048 , n5047 , n5043 );
and ( n5049 , n5036 , n5037 );
or ( n5050 , n5048 , n5049 );
buf ( n5051 , n5050 );
buf ( n5052 , n3962 );
not ( n5053 , n5052 );
buf ( n5054 , n4326 );
nor ( n5055 , n5053 , n5054 );
buf ( n5056 , n5055 );
buf ( n5057 , n5056 );
buf ( n5058 , n4178 );
buf ( n5059 , n388 );
and ( n5060 , n5058 , n5059 );
buf ( n5061 , n5060 );
buf ( n5062 , n5061 );
buf ( n5063 , n4902 );
xor ( n5064 , n5057 , n5062 );
xor ( n5065 , n5064 , n5063 );
buf ( n5066 , n5065 );
xor ( n5067 , n5057 , n5062 );
and ( n5068 , n5067 , n5063 );
and ( n5069 , n5057 , n5062 );
or ( n5070 , n5068 , n5069 );
buf ( n5071 , n5070 );
buf ( n5072 , n5046 );
buf ( n5073 , n4417 );
buf ( n5074 , n389 );
and ( n5075 , n5073 , n5074 );
buf ( n5076 , n5075 );
buf ( n5077 , n5076 );
and ( n5078 , n4585 , n4603 );
not ( n5079 , n4585 );
and ( n5080 , n5079 , n4602 );
nor ( n5081 , n5078 , n5080 );
buf ( n5082 , n5081 );
buf ( n5083 , n390 );
and ( n5084 , n5082 , n5083 );
buf ( n5085 , n5084 );
buf ( n5086 , n5085 );
xor ( n5087 , n5072 , n5077 );
xor ( n5088 , n5087 , n5086 );
buf ( n5089 , n5088 );
xor ( n5090 , n5072 , n5077 );
and ( n5091 , n5090 , n5086 );
and ( n5092 , n5072 , n5077 );
or ( n5093 , n5091 , n5092 );
buf ( n5094 , n5093 );
buf ( n5095 , n4810 );
buf ( n5096 , n391 );
and ( n5097 , n5095 , n5096 );
buf ( n5098 , n5097 );
buf ( n5099 , n5098 );
not ( n5100 , n393 );
and ( n5101 , n4326 , n386 );
nor ( n5102 , n5100 , n5101 );
not ( n5103 , n5102 );
not ( n5104 , n4795 );
not ( n5105 , n4800 );
and ( n5106 , n5104 , n5105 );
nor ( n5107 , n5106 , n4977 );
not ( n5108 , n5107 );
not ( n5109 , n4967 );
or ( n5110 , n5108 , n5109 );
not ( n5111 , n4970 );
not ( n5112 , n4977 );
and ( n5113 , n5111 , n5112 );
not ( n5114 , n4979 );
nor ( n5115 , n5113 , n5114 );
nand ( n5116 , n5110 , n5115 );
not ( n5117 , n5116 );
or ( n5118 , n5103 , n5117 );
nand ( n5119 , n4967 , n5107 );
and ( n5120 , n5101 , n393 );
nand ( n5121 , n5119 , n5115 , n5120 );
nand ( n5122 , n5118 , n5121 );
buf ( n5123 , n5122 );
buf ( n5124 , n4918 );
xor ( n5125 , n5099 , n5123 );
xor ( n5126 , n5125 , n5124 );
buf ( n5127 , n5126 );
xor ( n5128 , n5099 , n5123 );
and ( n5129 , n5128 , n5124 );
and ( n5130 , n5099 , n5123 );
or ( n5131 , n5129 , n5130 );
buf ( n5132 , n5131 );
buf ( n5133 , n4941 );
and ( n5134 , n4985 , n392 );
buf ( n5135 , n5134 );
buf ( n5136 , n5066 );
xor ( n5137 , n5133 , n5135 );
xor ( n5138 , n5137 , n5136 );
buf ( n5139 , n5138 );
xor ( n5140 , n5133 , n5135 );
and ( n5141 , n5140 , n5136 );
and ( n5142 , n5133 , n5135 );
or ( n5143 , n5141 , n5142 );
buf ( n5144 , n5143 );
buf ( n5145 , n4960 );
buf ( n5146 , n5089 );
buf ( n5147 , n4998 );
xor ( n5148 , n5145 , n5146 );
xor ( n5149 , n5148 , n5147 );
buf ( n5150 , n5149 );
xor ( n5151 , n5145 , n5146 );
and ( n5152 , n5151 , n5147 );
and ( n5153 , n5145 , n5146 );
or ( n5154 , n5152 , n5153 );
buf ( n5155 , n5154 );
buf ( n5156 , n5127 );
buf ( n5157 , n5139 );
buf ( n5158 , n5009 );
xor ( n5159 , n5156 , n5157 );
xor ( n5160 , n5159 , n5158 );
buf ( n5161 , n5160 );
xor ( n5162 , n5156 , n5157 );
and ( n5163 , n5162 , n5158 );
and ( n5164 , n5156 , n5157 );
or ( n5165 , n5163 , n5164 );
buf ( n5166 , n5165 );
buf ( n5167 , n5150 );
buf ( n5168 , n5020 );
buf ( n5169 , n5161 );
xor ( n5170 , n5167 , n5168 );
xor ( n5171 , n5170 , n5169 );
buf ( n5172 , n5171 );
xor ( n5173 , n5167 , n5168 );
and ( n5174 , n5173 , n5169 );
and ( n5175 , n5167 , n5168 );
or ( n5176 , n5174 , n5175 );
buf ( n5177 , n5176 );
and ( n5178 , n386 , n3963 );
buf ( n5179 , n5178 );
buf ( n5180 , n4181 );
buf ( n5181 , n387 );
and ( n5182 , n5180 , n5181 );
buf ( n5183 , n5182 );
buf ( n5184 , n5183 );
buf ( n5185 , n4928 );
buf ( n5186 , n388 );
and ( n5187 , n5185 , n5186 );
buf ( n5188 , n5187 );
buf ( n5189 , n5188 );
xor ( n5190 , n5179 , n5184 );
xor ( n5191 , n5190 , n5189 );
buf ( n5192 , n5191 );
xor ( n5193 , n5179 , n5184 );
and ( n5194 , n5193 , n5189 );
and ( n5195 , n5179 , n5184 );
or ( n5196 , n5194 , n5195 );
buf ( n5197 , n5196 );
buf ( n5198 , n5051 );
buf ( n5199 , n4813 );
buf ( n5200 , n390 );
nand ( n5201 , n5199 , n5200 );
buf ( n5202 , n5201 );
buf ( n5203 , n5202 );
not ( n5204 , n5203 );
buf ( n5205 , n5204 );
buf ( n5206 , n5205 );
buf ( n5207 , n4607 );
buf ( n5208 , n389 );
and ( n5209 , n5207 , n5208 );
buf ( n5210 , n5209 );
buf ( n5211 , n5210 );
xor ( n5212 , n5198 , n5206 );
xor ( n5213 , n5212 , n5211 );
buf ( n5214 , n5213 );
xor ( n5215 , n5198 , n5206 );
and ( n5216 , n5215 , n5211 );
and ( n5217 , n5198 , n5206 );
or ( n5218 , n5216 , n5217 );
buf ( n5219 , n5218 );
and ( n5220 , n5107 , n386 );
not ( n5221 , n5220 );
not ( n5222 , n4791 );
or ( n5223 , n5221 , n5222 );
not ( n5224 , n4326 );
not ( n5225 , n5115 );
or ( n5226 , n5224 , n5225 );
nand ( n5227 , n5226 , n386 );
nand ( n5228 , n5223 , n5227 );
buf ( n5229 , n5228 );
buf ( n5230 , n393 );
and ( n5231 , n5229 , n5230 );
buf ( n5232 , n5231 );
buf ( n5233 , n5232 );
buf ( n5234 , n5071 );
xnor ( n5235 , n5116 , n5101 );
nor ( n5236 , n5235 , n3533 );
buf ( n5237 , n5236 );
xor ( n5238 , n5233 , n5234 );
xor ( n5239 , n5238 , n5237 );
buf ( n5240 , n5239 );
xor ( n5241 , n5233 , n5234 );
and ( n5242 , n5241 , n5237 );
and ( n5243 , n5233 , n5234 );
or ( n5244 , n5242 , n5243 );
buf ( n5245 , n5244 );
buf ( n5246 , n5192 );
buf ( n5247 , n4985 );
buf ( n5248 , n391 );
and ( n5249 , n5247 , n5248 );
buf ( n5250 , n5249 );
buf ( n5251 , n5250 );
buf ( n5252 , n5094 );
xor ( n5253 , n5246 , n5251 );
xor ( n5254 , n5253 , n5252 );
buf ( n5255 , n5254 );
xor ( n5256 , n5246 , n5251 );
and ( n5257 , n5256 , n5252 );
and ( n5258 , n5246 , n5251 );
or ( n5259 , n5257 , n5258 );
buf ( n5260 , n5259 );
buf ( n5261 , n5132 );
buf ( n5262 , n5214 );
buf ( n5263 , n5240 );
xor ( n5264 , n5261 , n5262 );
xor ( n5265 , n5264 , n5263 );
buf ( n5266 , n5265 );
xor ( n5267 , n5261 , n5262 );
and ( n5268 , n5267 , n5263 );
and ( n5269 , n5261 , n5262 );
or ( n5270 , n5268 , n5269 );
buf ( n5271 , n5270 );
buf ( n5272 , n5144 );
buf ( n5273 , n5255 );
buf ( n5274 , n5155 );
xor ( n5275 , n5272 , n5273 );
xor ( n5276 , n5275 , n5274 );
buf ( n5277 , n5276 );
xor ( n5278 , n5272 , n5273 );
and ( n5279 , n5278 , n5274 );
and ( n5280 , n5272 , n5273 );
or ( n5281 , n5279 , n5280 );
buf ( n5282 , n5281 );
buf ( n5283 , n5266 );
buf ( n5284 , n5166 );
buf ( n5285 , n5277 );
xor ( n5286 , n5283 , n5284 );
xor ( n5287 , n5286 , n5285 );
buf ( n5288 , n5287 );
xor ( n5289 , n5283 , n5284 );
and ( n5290 , n5289 , n5285 );
and ( n5291 , n5283 , n5284 );
or ( n5292 , n5290 , n5291 );
buf ( n5293 , n5292 );
buf ( n5294 , n4181 );
buf ( n5295 , n386 );
and ( n5296 , n5294 , n5295 );
buf ( n5297 , n5296 );
buf ( n5298 , n5297 );
buf ( n5299 , n4928 );
buf ( n5300 , n387 );
and ( n5301 , n5299 , n5300 );
buf ( n5302 , n5301 );
buf ( n5303 , n5302 );
buf ( n5304 , n5228 );
buf ( n5305 , n392 );
and ( n5306 , n5304 , n5305 );
buf ( n5307 , n5306 );
buf ( n5308 , n5307 );
xor ( n5309 , n5298 , n5303 );
xor ( n5310 , n5309 , n5308 );
buf ( n5311 , n5310 );
xor ( n5312 , n5298 , n5303 );
and ( n5313 , n5312 , n5308 );
and ( n5314 , n5298 , n5303 );
or ( n5315 , n5313 , n5314 );
buf ( n5316 , n5315 );
buf ( n5317 , n4813 );
buf ( n5318 , n389 );
and ( n5319 , n5317 , n5318 );
buf ( n5320 , n5319 );
buf ( n5321 , n5320 );
buf ( n5322 , n5081 );
buf ( n5323 , n388 );
and ( n5324 , n5322 , n5323 );
buf ( n5325 , n5324 );
buf ( n5326 , n5325 );
not ( n5327 , n5101 );
not ( n5328 , n5116 );
not ( n5329 , n5328 );
or ( n5330 , n5327 , n5329 );
or ( n5331 , n5328 , n5101 );
nand ( n5332 , n5330 , n5331 );
buf ( n5333 , n5332 );
buf ( n5334 , n391 );
and ( n5335 , n5333 , n5334 );
buf ( n5336 , n5335 );
buf ( n5337 , n5336 );
xor ( n5338 , n5321 , n5326 );
xor ( n5339 , n5338 , n5337 );
buf ( n5340 , n5339 );
xor ( n5341 , n5321 , n5326 );
and ( n5342 , n5341 , n5337 );
and ( n5343 , n5321 , n5326 );
or ( n5344 , n5342 , n5343 );
buf ( n5345 , n5344 );
and ( n5346 , n4985 , n390 );
buf ( n5347 , n5346 );
buf ( n5348 , n5197 );
buf ( n5349 , n5219 );
xor ( n5350 , n5347 , n5348 );
xor ( n5351 , n5350 , n5349 );
buf ( n5352 , n5351 );
xor ( n5353 , n5347 , n5348 );
and ( n5354 , n5353 , n5349 );
and ( n5355 , n5347 , n5348 );
or ( n5356 , n5354 , n5355 );
buf ( n5357 , n5356 );
buf ( n5358 , n5311 );
buf ( n5359 , n5245 );
buf ( n5360 , n5340 );
xor ( n5361 , n5358 , n5359 );
xor ( n5362 , n5361 , n5360 );
buf ( n5363 , n5362 );
xor ( n5364 , n5358 , n5359 );
and ( n5365 , n5364 , n5360 );
and ( n5366 , n5358 , n5359 );
or ( n5367 , n5365 , n5366 );
buf ( n5368 , n5367 );
buf ( n5369 , n5352 );
buf ( n5370 , n5260 );
buf ( n5371 , n5271 );
xor ( n5372 , n5369 , n5370 );
xor ( n5373 , n5372 , n5371 );
buf ( n5374 , n5373 );
xor ( n5375 , n5369 , n5370 );
and ( n5376 , n5375 , n5371 );
and ( n5377 , n5369 , n5370 );
or ( n5378 , n5376 , n5377 );
buf ( n5379 , n5378 );
buf ( n5380 , n5363 );
buf ( n5381 , n5374 );
buf ( n5382 , n5282 );
xor ( n5383 , n5380 , n5381 );
xor ( n5384 , n5383 , n5382 );
buf ( n5385 , n5384 );
xor ( n5386 , n5380 , n5381 );
and ( n5387 , n5386 , n5382 );
and ( n5388 , n5380 , n5381 );
or ( n5389 , n5387 , n5388 );
buf ( n5390 , n5389 );
buf ( n5391 , n4417 );
buf ( n5392 , n386 );
and ( n5393 , n5391 , n5392 );
buf ( n5394 , n5393 );
buf ( n5395 , n5394 );
buf ( n5396 , n4813 );
buf ( n5397 , n5396 );
buf ( n5398 , n5397 );
buf ( n5399 , n5398 );
buf ( n5400 , n388 );
nand ( n5401 , n5399 , n5400 );
buf ( n5402 , n5401 );
buf ( n5403 , n5402 );
not ( n5404 , n5403 );
buf ( n5405 , n5404 );
buf ( n5406 , n5405 );
buf ( n5407 , n5081 );
not ( n5408 , n5407 );
buf ( n5409 , n4326 );
nor ( n5410 , n5408 , n5409 );
buf ( n5411 , n5410 );
buf ( n5412 , n5411 );
xor ( n5413 , n5395 , n5406 );
xor ( n5414 , n5413 , n5412 );
buf ( n5415 , n5414 );
xor ( n5416 , n5395 , n5406 );
and ( n5417 , n5416 , n5412 );
and ( n5418 , n5395 , n5406 );
or ( n5419 , n5417 , n5418 );
buf ( n5420 , n5419 );
buf ( n5421 , n5228 );
buf ( n5422 , n5421 );
buf ( n5423 , n5422 );
buf ( n5424 , n5423 );
buf ( n5425 , n391 );
and ( n5426 , n5424 , n5425 );
buf ( n5427 , n5426 );
buf ( n5428 , n5427 );
and ( n5429 , n5332 , n390 );
buf ( n5430 , n5429 );
buf ( n5431 , n4985 );
buf ( n5432 , n389 );
and ( n5433 , n5431 , n5432 );
buf ( n5434 , n5433 );
buf ( n5435 , n5434 );
xor ( n5436 , n5428 , n5430 );
xor ( n5437 , n5436 , n5435 );
buf ( n5438 , n5437 );
xor ( n5439 , n5428 , n5430 );
and ( n5440 , n5439 , n5435 );
and ( n5441 , n5428 , n5430 );
or ( n5442 , n5440 , n5441 );
buf ( n5443 , n5442 );
buf ( n5444 , n5316 );
buf ( n5445 , n5345 );
buf ( n5446 , n5415 );
xor ( n5447 , n5444 , n5445 );
xor ( n5448 , n5447 , n5446 );
buf ( n5449 , n5448 );
xor ( n5450 , n5444 , n5445 );
and ( n5451 , n5450 , n5446 );
and ( n5452 , n5444 , n5445 );
or ( n5453 , n5451 , n5452 );
buf ( n5454 , n5453 );
buf ( n5455 , n5438 );
buf ( n5456 , n5357 );
buf ( n5457 , n5368 );
xor ( n5458 , n5455 , n5456 );
xor ( n5459 , n5458 , n5457 );
buf ( n5460 , n5459 );
xor ( n5461 , n5455 , n5456 );
and ( n5462 , n5461 , n5457 );
and ( n5463 , n5455 , n5456 );
or ( n5464 , n5462 , n5463 );
buf ( n5465 , n5464 );
buf ( n5466 , n5449 );
buf ( n5467 , n5460 );
buf ( n5468 , n5379 );
xor ( n5469 , n5466 , n5467 );
xor ( n5470 , n5469 , n5468 );
buf ( n5471 , n5470 );
xor ( n5472 , n5466 , n5467 );
and ( n5473 , n5472 , n5468 );
and ( n5474 , n5466 , n5467 );
or ( n5475 , n5473 , n5474 );
buf ( n5476 , n5475 );
buf ( n5477 , n5423 );
buf ( n5478 , n390 );
and ( n5479 , n5477 , n5478 );
buf ( n5480 , n5479 );
buf ( n5481 , n5480 );
buf ( n5482 , n5081 );
buf ( n5483 , n386 );
and ( n5484 , n5482 , n5483 );
buf ( n5485 , n5484 );
buf ( n5486 , n5485 );
buf ( n5487 , n5398 );
buf ( n5488 , n387 );
and ( n5489 , n5487 , n5488 );
buf ( n5490 , n5489 );
buf ( n5491 , n5490 );
xor ( n5492 , n5481 , n5486 );
xor ( n5493 , n5492 , n5491 );
buf ( n5494 , n5493 );
xor ( n5495 , n5481 , n5486 );
and ( n5496 , n5495 , n5491 );
and ( n5497 , n5481 , n5486 );
or ( n5498 , n5496 , n5497 );
buf ( n5499 , n5498 );
buf ( n5500 , n5332 );
buf ( n5501 , n389 );
and ( n5502 , n5500 , n5501 );
buf ( n5503 , n5502 );
buf ( n5504 , n5503 );
and ( n5505 , n4985 , n388 );
buf ( n5506 , n5505 );
buf ( n5507 , n5420 );
xor ( n5508 , n5504 , n5506 );
xor ( n5509 , n5508 , n5507 );
buf ( n5510 , n5509 );
xor ( n5511 , n5504 , n5506 );
and ( n5512 , n5511 , n5507 );
and ( n5513 , n5504 , n5506 );
or ( n5514 , n5512 , n5513 );
buf ( n5515 , n5514 );
buf ( n5516 , n5494 );
buf ( n5517 , n5443 );
buf ( n5518 , n5510 );
xor ( n5519 , n5516 , n5517 );
xor ( n5520 , n5519 , n5518 );
buf ( n5521 , n5520 );
xor ( n5522 , n5516 , n5517 );
and ( n5523 , n5522 , n5518 );
and ( n5524 , n5516 , n5517 );
or ( n5525 , n5523 , n5524 );
buf ( n5526 , n5525 );
buf ( n5527 , n5454 );
buf ( n5528 , n5521 );
buf ( n5529 , n5465 );
xor ( n5530 , n5527 , n5528 );
xor ( n5531 , n5530 , n5529 );
buf ( n5532 , n5531 );
xor ( n5533 , n5527 , n5528 );
and ( n5534 , n5533 , n5529 );
and ( n5535 , n5527 , n5528 );
or ( n5536 , n5534 , n5535 );
buf ( n5537 , n5536 );
buf ( n5538 , n5423 );
buf ( n5539 , n389 );
and ( n5540 , n5538 , n5539 );
buf ( n5541 , n5540 );
buf ( n5542 , n5541 );
buf ( n5543 , n5398 );
buf ( n5544 , n386 );
and ( n5545 , n5543 , n5544 );
buf ( n5546 , n5545 );
buf ( n5547 , n5546 );
buf ( n5548 , n5332 );
buf ( n5549 , n388 );
and ( n5550 , n5548 , n5549 );
buf ( n5551 , n5550 );
buf ( n5552 , n5551 );
xor ( n5553 , n5542 , n5547 );
xor ( n5554 , n5553 , n5552 );
buf ( n5555 , n5554 );
xor ( n5556 , n5542 , n5547 );
and ( n5557 , n5556 , n5552 );
and ( n5558 , n5542 , n5547 );
or ( n5559 , n5557 , n5558 );
buf ( n5560 , n5559 );
buf ( n5561 , n4985 );
buf ( n5562 , n387 );
and ( n5563 , n5561 , n5562 );
buf ( n5564 , n5563 );
buf ( n5565 , n5564 );
buf ( n5566 , n5499 );
buf ( n5567 , n5555 );
xor ( n5568 , n5565 , n5566 );
xor ( n5569 , n5568 , n5567 );
buf ( n5570 , n5569 );
xor ( n5571 , n5565 , n5566 );
and ( n5572 , n5571 , n5567 );
and ( n5573 , n5565 , n5566 );
or ( n5574 , n5572 , n5573 );
buf ( n5575 , n5574 );
buf ( n5576 , n5515 );
buf ( n5577 , n5570 );
buf ( n5578 , n5526 );
xor ( n5579 , n5576 , n5577 );
xor ( n5580 , n5579 , n5578 );
buf ( n5581 , n5580 );
xor ( n5582 , n5576 , n5577 );
and ( n5583 , n5582 , n5578 );
and ( n5584 , n5576 , n5577 );
or ( n5585 , n5583 , n5584 );
buf ( n5586 , n5585 );
buf ( n5587 , n5423 );
buf ( n5588 , n388 );
and ( n5589 , n5587 , n5588 );
buf ( n5590 , n5589 );
buf ( n5591 , n5590 );
buf ( n5592 , n5332 );
buf ( n5593 , n387 );
and ( n5594 , n5592 , n5593 );
buf ( n5595 , n5594 );
buf ( n5596 , n5595 );
buf ( n5597 , n4985 );
buf ( n5598 , n386 );
and ( n5599 , n5597 , n5598 );
buf ( n5600 , n5599 );
buf ( n5601 , n5600 );
xor ( n5602 , n5591 , n5596 );
xor ( n5603 , n5602 , n5601 );
buf ( n5604 , n5603 );
and ( n5605 , n5591 , n5596 );
or ( n5606 , C0 , n5605 );
buf ( n5607 , n5606 );
buf ( n5608 , n5560 );
buf ( n5609 , n5604 );
buf ( n5610 , n5575 );
xor ( n5611 , n5608 , n5609 );
xor ( n5612 , n5611 , n5610 );
buf ( n5613 , n5612 );
xor ( n5614 , n5608 , n5609 );
and ( n5615 , n5614 , n5610 );
and ( n5616 , n5608 , n5609 );
or ( n5617 , n5615 , n5616 );
buf ( n5618 , n5617 );
buf ( n5619 , n5423 );
buf ( n5620 , n387 );
and ( n5621 , n5619 , n5620 );
buf ( n5622 , n5621 );
buf ( n5623 , n5622 );
buf ( n5624 , n5332 );
buf ( n5625 , n386 );
and ( n5626 , n5624 , n5625 );
buf ( n5627 , n5626 );
buf ( n5628 , n5627 );
buf ( n5629 , n5607 );
xor ( n5630 , n5623 , n5628 );
xor ( n5631 , n5630 , n5629 );
buf ( n5632 , n5631 );
and ( n5633 , n5623 , n5628 );
or ( n5634 , C0 , n5633 );
buf ( n5635 , n5634 );
not ( n5636 , n5390 );
not ( n5637 , n5636 );
not ( n5638 , n5471 );
not ( n5639 , n5638 );
or ( n5640 , n5637 , n5639 );
not ( n5641 , n5471 );
not ( n5642 , n5390 );
or ( n5643 , n5641 , n5642 );
nand ( n5644 , n5385 , n5293 );
nand ( n5645 , n5643 , n5644 );
nand ( n5646 , n5640 , n5645 );
not ( n5647 , n5646 );
not ( n5648 , n5476 );
not ( n5649 , n5532 );
nand ( n5650 , n5648 , n5649 );
not ( n5651 , n5537 );
not ( n5652 , n5581 );
nand ( n5653 , n5651 , n5652 );
and ( n5654 , n5650 , n5653 );
and ( n5655 , n5647 , n5654 );
not ( n5656 , n5537 );
nand ( n5657 , n5656 , n5652 );
not ( n5658 , n5657 );
nand ( n5659 , n5532 , n5476 );
not ( n5660 , n5659 );
not ( n5661 , n5660 );
or ( n5662 , n5658 , n5661 );
not ( n5663 , n5652 );
nand ( n5664 , n5663 , n5537 );
nand ( n5665 , n5662 , n5664 );
nor ( n5666 , n5655 , n5665 );
buf ( n5667 , n5666 );
not ( n5668 , n5667 );
buf ( n5669 , n5668 );
not ( n5670 , n5636 );
not ( n5671 , n5638 );
or ( n5672 , n5670 , n5671 );
buf ( n5673 , n5385 );
not ( n5674 , n5673 );
buf ( n5675 , n5674 );
buf ( n5676 , n5293 );
not ( n5677 , n5676 );
buf ( n5678 , n5677 );
nand ( n5679 , n5675 , n5678 );
nand ( n5680 , n5672 , n5679 );
not ( n5681 , n5680 );
buf ( n5682 , n5681 );
buf ( n5683 , n5654 );
or ( n5684 , n5613 , n5586 );
buf ( n5685 , n5618 );
buf ( n5686 , n5632 );
or ( n5687 , n5685 , n5686 );
buf ( n5688 , n5687 );
nand ( n5689 , n5684 , n5688 );
not ( n5690 , n5635 );
buf ( n5691 , n5423 );
buf ( n5692 , n386 );
nand ( n5693 , n5691 , n5692 );
buf ( n5694 , n5693 );
nand ( n5695 , n5690 , n5694 );
not ( n5696 , n5695 );
nor ( n5697 , n5689 , n5696 );
buf ( n5698 , n5697 );
and ( n5699 , n5682 , n5683 , n5698 );
buf ( n5700 , n5699 );
buf ( n5701 , n5675 );
not ( n5702 , n5701 );
buf ( n5703 , n5293 );
nand ( n5704 , n5702 , n5703 );
buf ( n5705 , n5704 );
buf ( n5706 , n5705 );
buf ( n5707 , n5679 );
and ( n5708 , n5706 , n5707 );
buf ( n5709 , n5708 );
buf ( n5710 , n5705 );
not ( n5711 , n5710 );
buf ( n5712 , n5711 );
nand ( n5713 , n5177 , n5288 );
buf ( n5714 , n5713 );
not ( n5715 , n5714 );
buf ( n5716 , n5715 );
buf ( n5717 , n5026 );
buf ( n5718 , n4868 );
nand ( n5719 , n5717 , n5718 );
buf ( n5720 , n5719 );
buf ( n5721 , n4863 );
not ( n5722 , n5721 );
buf ( n5723 , n5722 );
or ( n5724 , n4641 , n4438 );
buf ( n5725 , n5724 );
nand ( n5726 , n4641 , n4438 );
buf ( n5727 , n5726 );
buf ( n5728 , n5727 );
nand ( n5729 , n5725 , n5728 );
buf ( n5730 , n5729 );
not ( n5731 , n3422 );
not ( n5732 , n3596 );
or ( n5733 , n5731 , n5732 );
not ( n5734 , n3268 );
not ( n5735 , n3150 );
buf ( n5736 , n3078 );
buf ( n5737 , n3083 );
xnor ( n5738 , n5736 , n5737 );
buf ( n5739 , n5738 );
buf ( n5740 , n5739 );
buf ( n5741 , n393 );
buf ( n5742 , n409 );
nand ( n5743 , n5741 , n5742 );
buf ( n5744 , n5743 );
buf ( n5745 , n5744 );
not ( n5746 , n5745 );
buf ( n5747 , n408 );
nand ( n5748 , n5746 , n5747 );
buf ( n5749 , n5748 );
buf ( n5750 , n5749 );
nand ( n5751 , n5740 , n5750 );
buf ( n5752 , n5751 );
buf ( n5753 , n5752 );
buf ( n5754 , n408 );
not ( n5755 , n5754 );
buf ( n5756 , n5744 );
nand ( n5757 , n5755 , n5756 );
buf ( n5758 , n5757 );
buf ( n5759 , n5758 );
buf ( n5760 , n417 );
and ( n5761 , n5753 , n5759 , n5760 );
buf ( n5762 , n5761 );
buf ( n5763 , n5762 );
not ( n5764 , n5763 );
buf ( n5765 , n3091 );
not ( n5766 , n5765 );
or ( n5767 , n5764 , n5766 );
buf ( n5768 , n3064 );
not ( n5769 , n5768 );
buf ( n5770 , n5769 );
buf ( n5771 , n5770 );
nand ( n5772 , n5767 , n5771 );
buf ( n5773 , n5772 );
buf ( n5774 , n3091 );
buf ( n5775 , n5762 );
or ( n5776 , n5774 , n5775 );
buf ( n5777 , n5776 );
and ( n5778 , n3139 , n5773 , n5777 );
not ( n5779 , n5778 );
and ( n5780 , n5735 , n5779 );
buf ( n5781 , n5773 );
buf ( n5782 , n5777 );
and ( n5783 , n5781 , n5782 );
buf ( n5784 , n3139 );
nor ( n5785 , n5783 , n5784 );
buf ( n5786 , n5785 );
nor ( n5787 , n5780 , n5786 );
nand ( n5788 , n5787 , n3234 );
nand ( n5789 , n5734 , n5788 );
or ( n5790 , n5787 , n3234 );
and ( n5791 , n5789 , n5790 , n3273 );
or ( n5792 , n5791 , n3417 );
not ( n5793 , n3273 );
nand ( n5794 , n5789 , n5790 );
nand ( n5795 , n5793 , n5794 );
nand ( n5796 , n5792 , n5795 );
nand ( n5797 , n5733 , n5796 );
buf ( n5798 , n5797 );
buf ( n5799 , n3596 );
buf ( n5800 , n3422 );
or ( n5801 , n5799 , n5800 );
buf ( n5802 , n5801 );
buf ( n5803 , n5802 );
buf ( n5804 , n3601 );
and ( n5805 , n5798 , n5803 );
nor ( n5806 , n5805 , n5804 );
buf ( n5807 , n5806 );
buf ( n5808 , n5618 );
buf ( n5809 , n5632 );
nand ( n5810 , n5808 , n5809 );
buf ( n5811 , n5810 );
buf ( n5812 , n5811 );
not ( n5813 , n5812 );
buf ( n5814 , n5813 );
buf ( n5815 , n5635 );
not ( n5816 , n5815 );
buf ( n5817 , n5816 );
buf ( n5818 , n5817 );
buf ( n5819 , n5694 );
nor ( n5820 , n5818 , n5819 );
buf ( n5821 , n5820 );
nand ( n5822 , n5684 , n5650 , n5653 );
buf ( n5823 , n5822 );
buf ( n5824 , n5681 );
not ( n5825 , n5823 );
nand ( n5826 , n5825 , n5824 );
buf ( n5827 , n5826 );
buf ( n5828 , n5636 );
buf ( n5829 , n5638 );
or ( n5830 , n5828 , n5829 );
buf ( n5831 , n5830 );
xnor ( n5832 , n413 , n412 );
buf ( n5833 , n411 );
buf ( n5834 , n412 );
xor ( n5835 , n5833 , n5834 );
buf ( n5836 , n5835 );
and ( n5837 , n5832 , n5836 );
buf ( n5838 , n5837 );
not ( n5839 , n5838 );
buf ( n5840 , n5839 );
nand ( n5841 , n5840 , n5832 );
not ( n5842 , n411 );
and ( n5843 , n421 , n425 );
buf ( n5844 , n422 );
buf ( n5845 , n423 );
or ( n5846 , n5844 , n5845 );
buf ( n5847 , n373 );
not ( n5848 , n5847 );
buf ( n5849 , n5848 );
buf ( n5850 , n5849 );
nand ( n5851 , n5846 , n5850 );
buf ( n5852 , n5851 );
nand ( n5853 , n422 , n423 );
nand ( n5854 , n5852 , n5853 );
xor ( n5855 , n5843 , n5854 );
buf ( n5856 , n372 );
not ( n5857 , n5856 );
buf ( n5858 , n421 );
not ( n5859 , n5858 );
and ( n5860 , n5857 , n5859 );
buf ( n5861 , n372 );
buf ( n5862 , n421 );
and ( n5863 , n5861 , n5862 );
nor ( n5864 , n5860 , n5863 );
buf ( n5865 , n5864 );
nand ( n5866 , n424 , n422 );
and ( n5867 , n5865 , n5866 );
not ( n5868 , n5865 );
not ( n5869 , n5866 );
and ( n5870 , n5868 , n5869 );
nor ( n5871 , n5867 , n5870 );
xor ( n5872 , n5855 , n5871 );
buf ( n5873 , n422 );
buf ( n5874 , n425 );
nand ( n5875 , n5873 , n5874 );
buf ( n5876 , n5875 );
buf ( n5877 , n5876 );
not ( n5878 , n5877 );
buf ( n5879 , n424 );
buf ( n5880 , n423 );
nand ( n5881 , n5879 , n5880 );
buf ( n5882 , n5881 );
buf ( n5883 , n5882 );
not ( n5884 , n5883 );
or ( n5885 , n5878 , n5884 );
buf ( n5886 , n424 );
buf ( n5887 , n423 );
nor ( n5888 , n5886 , n5887 );
buf ( n5889 , n5888 );
buf ( n5890 , n5889 );
buf ( n5891 , n374 );
or ( n5892 , n5890 , n5891 );
buf ( n5893 , n5882 );
nand ( n5894 , n5892 , n5893 );
buf ( n5895 , n5894 );
buf ( n5896 , n5895 );
nand ( n5897 , n5885 , n5896 );
buf ( n5898 , n5897 );
buf ( n5899 , n5898 );
not ( n5900 , n5899 );
buf ( n5901 , n5900 );
nor ( n5902 , n5872 , n5901 );
buf ( n5903 , n5902 );
buf ( n5904 , n424 );
buf ( n5905 , n423 );
and ( n5906 , n5904 , n5905 );
buf ( n5907 , n5906 );
buf ( n5908 , n5907 );
buf ( n5909 , n5876 );
and ( n5910 , n5908 , n5909 );
not ( n5911 , n5908 );
buf ( n5912 , n5876 );
not ( n5913 , n5912 );
buf ( n5914 , n5913 );
buf ( n5915 , n5914 );
and ( n5916 , n5911 , n5915 );
nor ( n5917 , n5910 , n5916 );
buf ( n5918 , n5917 );
xnor ( n5919 , n5918 , n5895 );
buf ( n5920 , n5919 );
xor ( n5921 , n423 , n373 );
xnor ( n5922 , n5921 , n422 );
buf ( n5923 , n5922 );
nor ( n5924 , n5920 , n5923 );
buf ( n5925 , n5924 );
buf ( n5926 , n5925 );
nor ( n5927 , n5903 , n5926 );
buf ( n5928 , n5927 );
buf ( n5929 , n5928 );
xor ( n5930 , n5843 , n5854 );
and ( n5931 , n5930 , n5871 );
and ( n5932 , n5843 , n5854 );
or ( n5933 , n5931 , n5932 );
not ( n5934 , n5933 );
not ( n5935 , n421 );
nand ( n5936 , n5935 , n372 );
not ( n5937 , n5936 );
and ( n5938 , n422 , n424 );
not ( n5939 , n5938 );
or ( n5940 , n5937 , n5939 );
not ( n5941 , n372 );
nand ( n5942 , n5941 , n421 );
nand ( n5943 , n5940 , n5942 );
not ( n5944 , n5943 );
xor ( n5945 , n371 , n420 );
and ( n5946 , n5945 , n422 );
not ( n5947 , n5945 );
not ( n5948 , n422 );
and ( n5949 , n5947 , n5948 );
nor ( n5950 , n5946 , n5949 );
not ( n5951 , n5950 );
not ( n5952 , n5951 );
or ( n5953 , n5944 , n5952 );
or ( n5954 , n5943 , n5951 );
nand ( n5955 , n5953 , n5954 );
not ( n5956 , n5955 );
and ( n5957 , n422 , n423 );
buf ( n5958 , n420 );
buf ( n5959 , n425 );
and ( n5960 , n5958 , n5959 );
buf ( n5961 , n5960 );
nand ( n5962 , n424 , n421 );
and ( n5963 , n5961 , n5962 );
not ( n5964 , n5961 );
not ( n5965 , n5962 );
and ( n5966 , n5964 , n5965 );
or ( n5967 , n5963 , n5966 );
xor ( n5968 , n5957 , n5967 );
not ( n5969 , n5968 );
or ( n5970 , n5956 , n5969 );
or ( n5971 , n5955 , n5968 );
nand ( n5972 , n5970 , n5971 );
not ( n5973 , n5972 );
nand ( n5974 , n5934 , n5973 );
buf ( n5975 , n5974 );
not ( n5976 , n425 );
nand ( n5977 , n5976 , n419 );
and ( n5978 , n5977 , n370 );
not ( n5979 , n5977 );
not ( n5980 , n370 );
and ( n5981 , n5979 , n5980 );
nor ( n5982 , n5978 , n5981 );
buf ( n5983 , n5982 );
not ( n5984 , n5957 );
not ( n5985 , n5965 );
or ( n5986 , n5984 , n5985 );
not ( n5987 , n5853 );
not ( n5988 , n5962 );
or ( n5989 , n5987 , n5988 );
nand ( n5990 , n5989 , n5961 );
nand ( n5991 , n5986 , n5990 );
buf ( n5992 , n5991 );
xor ( n5993 , n5983 , n5992 );
buf ( n5994 , n424 );
buf ( n5995 , n420 );
nand ( n5996 , n5994 , n5995 );
buf ( n5997 , n5996 );
buf ( n5998 , n5997 );
not ( n5999 , n5998 );
buf ( n6000 , n5999 );
buf ( n6001 , n6000 );
buf ( n6002 , n421 );
buf ( n6003 , n423 );
and ( n6004 , n6002 , n6003 );
buf ( n6005 , n6004 );
buf ( n6006 , n6005 );
xor ( n6007 , n6001 , n6006 );
buf ( n6008 , n420 );
buf ( n6009 , n422 );
nor ( n6010 , n6008 , n6009 );
buf ( n6011 , n6010 );
buf ( n6012 , n6011 );
buf ( n6013 , n371 );
or ( n6014 , n6012 , n6013 );
buf ( n6015 , n420 );
buf ( n6016 , n422 );
nand ( n6017 , n6015 , n6016 );
buf ( n6018 , n6017 );
buf ( n6019 , n6018 );
nand ( n6020 , n6014 , n6019 );
buf ( n6021 , n6020 );
buf ( n6022 , n6021 );
xor ( n6023 , n6007 , n6022 );
buf ( n6024 , n6023 );
buf ( n6025 , n6024 );
xor ( n6026 , n5993 , n6025 );
buf ( n6027 , n6026 );
buf ( n6028 , n6027 );
not ( n6029 , n6028 );
buf ( n6030 , n5943 );
not ( n6031 , n6030 );
buf ( n6032 , n5950 );
buf ( n6033 , n6032 );
nand ( n6034 , n6031 , n6033 );
buf ( n6035 , n6034 );
and ( n6036 , n5968 , n6035 );
not ( n6037 , n5943 );
nor ( n6038 , n6037 , n6032 );
nor ( n6039 , n6036 , n6038 );
buf ( n6040 , n6039 );
nand ( n6041 , n6029 , n6040 );
buf ( n6042 , n6041 );
buf ( n6043 , n6042 );
xor ( n6044 , n424 , n374 );
not ( n6045 , n423 );
xor ( n6046 , n6044 , n6045 );
buf ( n6047 , n6046 );
buf ( n6048 , n423 );
buf ( n6049 , n425 );
and ( n6050 , n6048 , n6049 );
buf ( n6051 , n6050 );
buf ( n6052 , n6051 );
or ( n6053 , n6047 , n6052 );
not ( n6054 , n376 );
not ( n6055 , n377 );
and ( n6056 , n6054 , n6055 );
nor ( n6057 , n6056 , n425 );
buf ( n6058 , n6057 );
and ( n6059 , n424 , n425 );
nor ( n6060 , n6059 , n706 );
buf ( n6061 , n6060 );
nor ( n6062 , n6058 , n6061 );
buf ( n6063 , n6062 );
buf ( n6064 , n6063 );
nand ( n6065 , n6053 , n6064 );
buf ( n6066 , n6065 );
buf ( n6067 , n6046 );
buf ( n6068 , n6051 );
nand ( n6069 , n6067 , n6068 );
buf ( n6070 , n6069 );
nand ( n6071 , n6066 , n6070 );
buf ( n6072 , n6071 );
nand ( n6073 , n5929 , n5975 , n6043 , n6072 );
buf ( n6074 , n6073 );
buf ( n6075 , n5972 );
buf ( n6076 , n5933 );
nor ( n6077 , n6075 , n6076 );
buf ( n6078 , n6077 );
buf ( n6079 , n6078 );
buf ( n6080 , n5902 );
nor ( n6081 , n6079 , n6080 );
buf ( n6082 , n6081 );
buf ( n6083 , n6082 );
buf ( n6084 , n6042 );
nand ( n6085 , n5872 , n5901 );
buf ( n6086 , n6085 );
nand ( n6087 , n5919 , n5922 );
buf ( n6088 , n6087 );
nand ( n6089 , n6086 , n6088 );
buf ( n6090 , n6089 );
buf ( n6091 , n6090 );
nand ( n6092 , n6083 , n6084 , n6091 );
buf ( n6093 , n6092 );
buf ( n6094 , n6027 );
not ( n6095 , n6094 );
buf ( n6096 , n6039 );
nand ( n6097 , n6095 , n6096 );
buf ( n6098 , n6097 );
buf ( n6099 , n6098 );
buf ( n6100 , n5972 );
buf ( n6101 , n5933 );
and ( n6102 , n6100 , n6101 );
buf ( n6103 , n6102 );
buf ( n6104 , n6103 );
nand ( n6105 , n6099 , n6104 );
buf ( n6106 , n6105 );
buf ( n6107 , n6039 );
not ( n6108 , n6107 );
buf ( n6109 , n6027 );
buf ( n6110 , n6109 );
buf ( n6111 , n6110 );
buf ( n6112 , n6111 );
nand ( n6113 , n6108 , n6112 );
buf ( n6114 , n6113 );
nand ( n6115 , n6074 , n6093 , n6106 , n6114 );
buf ( n6116 , n6115 );
buf ( n6117 , n419 );
not ( n6118 , n6117 );
buf ( n6119 , n418 );
buf ( n6120 , n420 );
nand ( n6121 , n6119 , n6120 );
buf ( n6122 , n6121 );
buf ( n6123 , n6122 );
nand ( n6124 , n6118 , n6123 );
buf ( n6125 , n6124 );
buf ( n6126 , n419 );
not ( n6127 , n6126 );
buf ( n6128 , n418 );
nand ( n6129 , n6127 , n6128 );
buf ( n6130 , n6129 );
or ( n6131 , n6125 , n6130 );
not ( n6132 , n6131 );
buf ( n6133 , n418 );
buf ( n6134 , n422 );
nand ( n6135 , n6133 , n6134 );
buf ( n6136 , n6135 );
buf ( n6137 , n419 );
buf ( n6138 , n421 );
nand ( n6139 , n6137 , n6138 );
buf ( n6140 , n6139 );
nand ( n6141 , n6136 , n6140 );
buf ( n6142 , n6141 );
not ( n6143 , n6142 );
buf ( n6144 , n419 );
not ( n6145 , n6144 );
buf ( n6146 , n420 );
nor ( n6147 , n6145 , n6146 );
buf ( n6148 , n6147 );
buf ( n6149 , n6148 );
not ( n6150 , n6149 );
buf ( n6151 , n6150 );
buf ( n6152 , n6151 );
not ( n6153 , n6152 );
or ( n6154 , n6143 , n6153 );
buf ( n6155 , n418 );
buf ( n6156 , n421 );
nand ( n6157 , n6155 , n6156 );
buf ( n6158 , n6157 );
buf ( n6159 , n6158 );
nand ( n6160 , n6154 , n6159 );
buf ( n6161 , n6160 );
buf ( n6162 , n6161 );
buf ( n6163 , n419 );
not ( n6164 , n6163 );
buf ( n6165 , n6122 );
nor ( n6166 , n6164 , n6165 );
buf ( n6167 , n6166 );
buf ( n6168 , n6167 );
not ( n6169 , n6168 );
buf ( n6170 , n6125 );
nand ( n6171 , n6169 , n6170 );
buf ( n6172 , n6171 );
buf ( n6173 , n6172 );
nor ( n6174 , n6162 , n6173 );
buf ( n6175 , n6174 );
not ( n6176 , n6175 );
not ( n6177 , n420 );
buf ( n6178 , n418 );
buf ( n6179 , n423 );
nand ( n6180 , n6178 , n6179 );
buf ( n6181 , n6180 );
nand ( n6182 , n6177 , n6181 );
not ( n6183 , n6140 );
not ( n6184 , n6136 );
or ( n6185 , n6183 , n6184 );
buf ( n6186 , n419 );
buf ( n6187 , n422 );
nand ( n6188 , n6186 , n6187 );
buf ( n6189 , n6188 );
not ( n6190 , n6189 );
not ( n6191 , n6158 );
nand ( n6192 , n6190 , n6191 );
nand ( n6193 , n6185 , n6192 );
xor ( n6194 , n6182 , n6193 );
buf ( n6195 , n420 );
buf ( n6196 , n421 );
nand ( n6197 , n6195 , n6196 );
buf ( n6198 , n6197 );
buf ( n6199 , n6198 );
buf ( n6200 , n6189 );
nand ( n6201 , n6199 , n6200 );
buf ( n6202 , n6201 );
buf ( n6203 , n6018 );
buf ( n6204 , n419 );
buf ( n6205 , n423 );
nand ( n6206 , n6204 , n6205 );
buf ( n6207 , n6206 );
buf ( n6208 , n6207 );
nand ( n6209 , n6203 , n6208 );
buf ( n6210 , n6209 );
and ( n6211 , n6202 , n6210 );
and ( n6212 , n6194 , n6211 );
and ( n6213 , n6182 , n6193 );
or ( n6214 , n6212 , n6213 );
xor ( n6215 , n6191 , n6148 );
xnor ( n6216 , n6215 , n6141 );
or ( n6217 , n6214 , n6216 );
nand ( n6218 , n6176 , n6217 );
nor ( n6219 , n6132 , n6218 );
xor ( n6220 , n6001 , n6006 );
and ( n6221 , n6220 , n6022 );
and ( n6222 , n6001 , n6006 );
or ( n6223 , n6221 , n6222 );
buf ( n6224 , n6223 );
buf ( n6225 , n6224 );
nand ( n6226 , n421 , n422 );
nand ( n6227 , n420 , n423 );
xor ( n6228 , n6226 , n6227 );
nand ( n6229 , n424 , n419 );
xnor ( n6230 , n6228 , n6229 );
buf ( n6231 , n6230 );
xor ( n6232 , n6225 , n6231 );
buf ( n6233 , n425 );
buf ( n6234 , n418 );
nand ( n6235 , n6233 , n6234 );
buf ( n6236 , n6235 );
buf ( n6237 , n6236 );
not ( n6238 , n6237 );
buf ( n6239 , n6238 );
buf ( n6240 , n6239 );
buf ( n6241 , n418 );
buf ( n6242 , n421 );
xnor ( n6243 , n6241 , n6242 );
buf ( n6244 , n6243 );
buf ( n6245 , n6244 );
xor ( n6246 , n6240 , n6245 );
not ( n6247 , n419 );
not ( n6248 , n5980 );
or ( n6249 , n6247 , n6248 );
nand ( n6250 , n419 , n425 );
nand ( n6251 , n6249 , n6250 );
buf ( n6252 , n6251 );
xor ( n6253 , n6246 , n6252 );
buf ( n6254 , n6253 );
buf ( n6255 , n6254 );
and ( n6256 , n6232 , n6255 );
and ( n6257 , n6225 , n6231 );
or ( n6258 , n6256 , n6257 );
buf ( n6259 , n6258 );
buf ( n6260 , n6259 );
not ( n6261 , n6260 );
or ( n6262 , n6207 , n6018 );
nand ( n6263 , n6262 , n6210 );
xor ( n6264 , n6240 , n6245 );
and ( n6265 , n6264 , n6252 );
and ( n6266 , n6240 , n6245 );
or ( n6267 , n6265 , n6266 );
buf ( n6268 , n6267 );
xor ( n6269 , n6263 , n6268 );
and ( n6270 , n424 , n419 );
not ( n6271 , n6270 );
not ( n6272 , n420 );
not ( n6273 , n423 );
or ( n6274 , n6272 , n6273 );
nand ( n6275 , n421 , n422 );
nand ( n6276 , n6274 , n6275 );
not ( n6277 , n6276 );
or ( n6278 , n6271 , n6277 );
nand ( n6279 , n421 , n422 , n420 , n423 );
nand ( n6280 , n6278 , n6279 );
buf ( n6281 , n418 );
not ( n6282 , n6281 );
buf ( n6283 , n421 );
not ( n6284 , n6283 );
and ( n6285 , n6282 , n6284 );
buf ( n6286 , n424 );
buf ( n6287 , n418 );
and ( n6288 , n6286 , n6287 );
nor ( n6289 , n6285 , n6288 );
buf ( n6290 , n6289 );
and ( n6291 , n6280 , n6290 );
not ( n6292 , n6280 );
not ( n6293 , n6290 );
and ( n6294 , n6292 , n6293 );
nor ( n6295 , n6291 , n6294 );
xor ( n6296 , n6269 , n6295 );
buf ( n6297 , n6296 );
not ( n6298 , n6297 );
and ( n6299 , n6261 , n6298 );
xor ( n6300 , n5983 , n5992 );
and ( n6301 , n6300 , n6025 );
and ( n6302 , n5983 , n5992 );
or ( n6303 , n6301 , n6302 );
buf ( n6304 , n6303 );
xor ( n6305 , n6225 , n6231 );
xor ( n6306 , n6305 , n6255 );
buf ( n6307 , n6306 );
nor ( n6308 , n6304 , n6307 );
buf ( n6309 , n6308 );
nor ( n6310 , n6299 , n6309 );
buf ( n6311 , n6310 );
buf ( n6312 , n6311 );
buf ( n6313 , n423 );
not ( n6314 , n6313 );
buf ( n6315 , n6122 );
not ( n6316 , n6315 );
buf ( n6317 , n6316 );
buf ( n6318 , n6317 );
not ( n6319 , n6318 );
or ( n6320 , n6314 , n6319 );
buf ( n6321 , n6182 );
nand ( n6322 , n6320 , n6321 );
buf ( n6323 , n6322 );
buf ( n6324 , n6323 );
not ( n6325 , n6198 );
not ( n6326 , n6190 );
or ( n6327 , n6325 , n6326 );
nand ( n6328 , n419 , n422 );
nand ( n6329 , n6328 , n420 , n421 );
nand ( n6330 , n6327 , n6329 );
xor ( n6331 , n6330 , n6210 );
buf ( n6332 , n6331 );
xor ( n6333 , n6324 , n6332 );
buf ( n6334 , n421 );
not ( n6335 , n6334 );
buf ( n6336 , n6280 );
not ( n6337 , n6336 );
or ( n6338 , n6335 , n6337 );
buf ( n6339 , n424 );
buf ( n6340 , n418 );
nand ( n6341 , n6339 , n6340 );
buf ( n6342 , n6341 );
buf ( n6343 , n6342 );
nand ( n6344 , n6338 , n6343 );
buf ( n6345 , n6344 );
buf ( n6346 , n6345 );
xor ( n6347 , n6333 , n6346 );
buf ( n6348 , n6347 );
buf ( n6349 , n6295 );
not ( n6350 , n6349 );
buf ( n6351 , n6350 );
not ( n6352 , n6351 );
buf ( n6353 , n6263 );
not ( n6354 , n6353 );
buf ( n6355 , n6354 );
not ( n6356 , n6355 );
and ( n6357 , n6352 , n6356 );
buf ( n6358 , n6351 );
buf ( n6359 , n6355 );
nand ( n6360 , n6358 , n6359 );
buf ( n6361 , n6360 );
buf ( n6362 , n6268 );
buf ( n6363 , n6362 );
buf ( n6364 , n6363 );
and ( n6365 , n6361 , n6364 );
nor ( n6366 , n6357 , n6365 );
buf ( n6367 , n6366 );
not ( n6368 , n6367 );
buf ( n6369 , n6368 );
nor ( n6370 , n6348 , n6369 );
xor ( n6371 , n6324 , n6332 );
and ( n6372 , n6371 , n6346 );
and ( n6373 , n6324 , n6332 );
or ( n6374 , n6372 , n6373 );
buf ( n6375 , n6374 );
xor ( n6376 , n6182 , n6193 );
xor ( n6377 , n6376 , n6211 );
nor ( n6378 , n6375 , n6377 );
nor ( n6379 , n6370 , n6378 );
buf ( n6380 , n6379 );
nand ( n6381 , n6116 , n6219 , n6312 , n6380 );
buf ( n6382 , n6381 );
not ( n6383 , n6379 );
or ( n6384 , n6259 , n6296 );
nand ( n6385 , n6307 , n6304 );
not ( n6386 , n6385 );
nand ( n6387 , n6384 , n6386 );
nand ( n6388 , n6259 , n6296 );
nand ( n6389 , n6387 , n6388 );
not ( n6390 , n6389 );
or ( n6391 , n6383 , n6390 );
nand ( n6392 , n6375 , n6377 );
not ( n6393 , n6392 );
nand ( n6394 , n6348 , n6369 );
nor ( n6395 , n6378 , n6394 );
nor ( n6396 , n6393 , n6395 );
nand ( n6397 , n6391 , n6396 );
nand ( n6398 , n6397 , n6219 );
buf ( n6399 , n6398 );
buf ( n6400 , n6214 );
buf ( n6401 , n6216 );
nand ( n6402 , n6400 , n6401 );
buf ( n6403 , n6402 );
buf ( n6404 , n6403 );
buf ( n6405 , n6175 );
or ( n6406 , n6404 , n6405 );
buf ( n6407 , n6161 );
buf ( n6408 , n6172 );
nand ( n6409 , n6407 , n6408 );
buf ( n6410 , n6409 );
buf ( n6411 , n6410 );
nand ( n6412 , n6406 , n6411 );
buf ( n6413 , n6412 );
and ( n6414 , n6413 , n6131 );
buf ( n6415 , n6414 );
buf ( n6416 , n418 );
not ( n6417 , n6416 );
buf ( n6418 , n6125 );
buf ( n6419 , n6130 );
nand ( n6420 , n6418 , n6419 );
buf ( n6421 , n6420 );
buf ( n6422 , n6421 );
nand ( n6423 , n6417 , n6422 );
buf ( n6424 , n6423 );
buf ( n6425 , n6424 );
nor ( n6426 , n6415 , n6425 );
buf ( n6427 , n6426 );
buf ( n6428 , n6427 );
nand ( n6429 , n6382 , n6399 , n6428 );
buf ( n6430 , n6429 );
buf ( n6431 , n6430 );
not ( n6432 , n6431 );
buf ( n6433 , n6432 );
buf ( n6434 , n6433 );
not ( n6435 , n6434 );
buf ( n6436 , n6435 );
not ( n6437 , n6436 );
or ( n6438 , n5842 , n6437 );
buf ( n6439 , n411 );
not ( n6440 , n6439 );
buf ( n6441 , n6433 );
nand ( n6442 , n6440 , n6441 );
buf ( n6443 , n6442 );
nand ( n6444 , n6438 , n6443 );
nand ( n6445 , n5841 , n6444 );
not ( n6446 , n6445 );
buf ( n6447 , n6433 );
not ( n6448 , n6447 );
buf ( n6449 , n416 );
not ( n6450 , n6449 );
buf ( n6451 , n6450 );
buf ( n6452 , n6451 );
buf ( n6453 , n415 );
and ( n6454 , n6452 , n6453 );
buf ( n6455 , n6454 );
buf ( n6456 , n6455 );
nand ( n6457 , n6448 , n6456 );
buf ( n6458 , n6457 );
buf ( n6459 , n415 );
not ( n6460 , n6459 );
buf ( n6461 , n6430 );
not ( n6462 , n6461 );
or ( n6463 , n6460 , n6462 );
buf ( n6464 , n6433 );
buf ( n6465 , n415 );
not ( n6466 , n6465 );
buf ( n6467 , n6466 );
buf ( n6468 , n6467 );
nand ( n6469 , n6464 , n6468 );
buf ( n6470 , n6469 );
buf ( n6471 , n6470 );
nand ( n6472 , n6463 , n6471 );
buf ( n6473 , n6472 );
buf ( n6474 , n6473 );
buf ( n6475 , n416 );
nand ( n6476 , n6474 , n6475 );
buf ( n6477 , n6476 );
nand ( n6478 , n6458 , n6477 );
not ( n6479 , n6478 );
or ( n6480 , n6446 , n6479 );
buf ( n6481 , n6477 );
buf ( n6482 , n6458 );
nand ( n6483 , n6481 , n6482 );
buf ( n6484 , n6483 );
buf ( n6485 , n6484 );
not ( n6486 , n6485 );
and ( n6487 , n6444 , n5841 );
buf ( n6488 , n6487 );
nand ( n6489 , n6486 , n6488 );
buf ( n6490 , n6489 );
nand ( n6491 , n6480 , n6490 );
not ( n6492 , n413 );
not ( n6493 , n6436 );
or ( n6494 , n6492 , n6493 );
buf ( n6495 , n6433 );
not ( n6496 , n413 );
buf ( n6497 , n6496 );
nand ( n6498 , n6495 , n6497 );
buf ( n6499 , n6498 );
nand ( n6500 , n6494 , n6499 );
buf ( n6501 , n6496 );
buf ( n6502 , n414 );
not ( n6503 , n6502 );
buf ( n6504 , n6503 );
buf ( n6505 , n6504 );
and ( n6506 , n6501 , n6505 );
buf ( n6507 , n413 );
buf ( n6508 , n414 );
and ( n6509 , n6507 , n6508 );
nor ( n6510 , n6506 , n6509 );
buf ( n6511 , n6510 );
not ( n6512 , n415 );
not ( n6513 , n414 );
or ( n6514 , n6512 , n6513 );
buf ( n6515 , n6467 );
buf ( n6516 , n6504 );
nand ( n6517 , n6515 , n6516 );
buf ( n6518 , n6517 );
nand ( n6519 , n6514 , n6518 );
and ( n6520 , n6511 , n6519 );
buf ( n6521 , n6520 );
not ( n6522 , n6521 );
buf ( n6523 , n6522 );
nand ( n6524 , n6523 , n6519 );
nand ( n6525 , n6500 , n6524 );
buf ( n6526 , n6525 );
buf ( n6527 , n6433 );
xor ( n6528 , n410 , n411 );
buf ( n6529 , n6528 );
nand ( n6530 , n6527 , n6529 );
buf ( n6531 , n6530 );
not ( n6532 , n6531 );
buf ( n6533 , n6528 );
not ( n6534 , n6533 );
buf ( n6535 , n6534 );
buf ( n6536 , n6535 );
buf ( n6537 , n410 );
and ( n6538 , n6536 , n6537 );
buf ( n6539 , n6538 );
and ( n6540 , n6539 , n6433 );
nor ( n6541 , n6532 , n6540 );
buf ( n6542 , n6541 );
nand ( n6543 , n6526 , n6542 );
and ( n6544 , n6491 , n6543 );
not ( n6545 , n6491 );
not ( n6546 , n6543 );
and ( n6547 , n6545 , n6546 );
nor ( n6548 , n6544 , n6547 );
not ( n6549 , n6548 );
not ( n6550 , n6525 );
not ( n6551 , n6541 );
nor ( n6552 , n6550 , n6551 );
not ( n6553 , n6552 );
not ( n6554 , n6519 );
not ( n6555 , n6523 );
or ( n6556 , n6554 , n6555 );
nand ( n6557 , n6556 , n6500 );
buf ( n6558 , n6557 );
not ( n6559 , n6558 );
buf ( n6560 , n6559 );
buf ( n6561 , n6560 );
buf ( n6562 , n6551 );
nand ( n6563 , n6561 , n6562 );
buf ( n6564 , n6563 );
nand ( n6565 , n6553 , n6564 );
not ( n6566 , n6565 );
nand ( n6567 , n6549 , n6566 );
not ( n6568 , n6567 );
buf ( n6569 , n6445 );
buf ( n6570 , n6552 );
nand ( n6571 , n6569 , n6570 );
buf ( n6572 , n6571 );
not ( n6573 , n6572 );
buf ( n6574 , n6478 );
not ( n6575 , n6574 );
or ( n6576 , n6573 , n6575 );
not ( n6577 , n6552 );
buf ( n6578 , n6577 );
buf ( n6579 , n6487 );
buf ( n6580 , n6579 );
buf ( n6581 , n6580 );
buf ( n6582 , n6581 );
nand ( n6583 , n6578 , n6582 );
buf ( n6584 , n6583 );
nand ( n6585 , n6576 , n6584 );
not ( n6586 , n6585 );
or ( n6587 , n6568 , n6586 );
nand ( n6588 , n6548 , n6565 );
nand ( n6589 , n6587 , n6588 );
buf ( n6590 , n6589 );
not ( n6591 , n6590 );
buf ( n6592 , n6591 );
buf ( n6593 , n6585 );
not ( n6594 , n6593 );
not ( n6595 , n6549 );
not ( n6596 , n6565 );
or ( n6597 , n6595 , n6596 );
nand ( n6598 , n6548 , n6566 );
nand ( n6599 , n6597 , n6598 );
not ( n6600 , n6599 );
buf ( n6601 , n6600 );
not ( n6602 , n6601 );
or ( n6603 , n6594 , n6602 );
buf ( n6604 , n6599 );
buf ( n6605 , n6585 );
not ( n6606 , n6605 );
buf ( n6607 , n6606 );
buf ( n6608 , n6607 );
nand ( n6609 , n6604 , n6608 );
buf ( n6610 , n6609 );
buf ( n6611 , n6610 );
nand ( n6612 , n6603 , n6611 );
buf ( n6613 , n6612 );
buf ( n6614 , n376 );
buf ( n6615 , n382 );
nand ( n6616 , n6614 , n6615 );
buf ( n6617 , n6616 );
nand ( n6618 , n374 , n380 );
or ( n6619 , n6617 , n6618 );
nand ( n6620 , n377 , n379 );
not ( n6621 , n6620 );
nand ( n6622 , n375 , n381 );
not ( n6623 , n6622 );
or ( n6624 , n6621 , n6623 );
or ( n6625 , n6620 , n6622 );
nand ( n6626 , n372 , n384 );
nand ( n6627 , n6625 , n6626 );
nand ( n6628 , n6624 , n6627 );
xor ( n6629 , n6619 , n6628 );
buf ( n6630 , n374 );
buf ( n6631 , n381 );
nand ( n6632 , n6630 , n6631 );
buf ( n6633 , n6632 );
buf ( n6634 , n373 );
buf ( n6635 , n382 );
nand ( n6636 , n6634 , n6635 );
buf ( n6637 , n6636 );
buf ( n6638 , n370 );
buf ( n6639 , n385 );
nand ( n6640 , n6638 , n6639 );
buf ( n6641 , n6640 );
nand ( n6642 , n6633 , n6637 , n6641 );
not ( n6643 , n6633 );
not ( n6644 , n6641 );
nand ( n6645 , n6643 , n6637 , n6644 );
not ( n6646 , n6637 );
nand ( n6647 , n6646 , n6641 , n6643 );
nand ( n6648 , n6644 , n6646 , n6633 );
nand ( n6649 , n6642 , n6645 , n6647 , n6648 );
xor ( n6650 , n6629 , n6649 );
buf ( n6651 , n6619 );
buf ( n6652 , n376 );
buf ( n6653 , n380 );
nand ( n6654 , n6652 , n6653 );
buf ( n6655 , n6654 );
buf ( n6656 , n6655 );
buf ( n6657 , n374 );
buf ( n6658 , n382 );
nand ( n6659 , n6657 , n6658 );
buf ( n6660 , n6659 );
buf ( n6661 , n6660 );
nand ( n6662 , n6656 , n6661 );
buf ( n6663 , n6662 );
buf ( n6664 , n6663 );
nand ( n6665 , n6651 , n6664 );
buf ( n6666 , n6665 );
not ( n6667 , n6666 );
nand ( n6668 , n375 , n381 );
xor ( n6669 , n6668 , n6620 );
xor ( n6670 , n6669 , n6626 );
buf ( n6671 , n372 );
buf ( n6672 , n385 );
nand ( n6673 , n6671 , n6672 );
buf ( n6674 , n6673 );
not ( n6675 , n6674 );
buf ( n6676 , n376 );
buf ( n6677 , n381 );
nand ( n6678 , n6676 , n6677 );
buf ( n6679 , n6678 );
not ( n6680 , n6679 );
or ( n6681 , n6675 , n6680 );
not ( n6682 , n6674 );
not ( n6683 , n6682 );
not ( n6684 , n6679 );
not ( n6685 , n6684 );
or ( n6686 , n6683 , n6685 );
nand ( n6687 , n374 , n383 );
nand ( n6688 , n6686 , n6687 );
nand ( n6689 , n6681 , n6688 );
or ( n6690 , n6670 , n6689 );
not ( n6691 , n6690 );
or ( n6692 , n6667 , n6691 );
nand ( n6693 , n6670 , n6689 );
nand ( n6694 , n6692 , n6693 );
xor ( n6695 , n6650 , n6694 );
buf ( n6696 , n372 );
buf ( n6697 , n383 );
nand ( n6698 , n6696 , n6697 );
buf ( n6699 , n6698 );
not ( n6700 , n6699 );
buf ( n6701 , n371 );
buf ( n6702 , n384 );
nand ( n6703 , n6701 , n6702 );
buf ( n6704 , n6703 );
not ( n6705 , n6704 );
or ( n6706 , n6700 , n6705 );
nand ( n6707 , n371 , n383 );
not ( n6708 , n6707 );
nand ( n6709 , n6708 , n372 , n384 );
nand ( n6710 , n6706 , n6709 );
nand ( n6711 , n376 , n379 );
nand ( n6712 , n377 , n378 );
xor ( n6713 , n6711 , n6712 );
buf ( n6714 , n375 );
buf ( n6715 , n380 );
nand ( n6716 , n6714 , n6715 );
buf ( n6717 , n6716 );
not ( n6718 , n6717 );
and ( n6719 , n6713 , n6718 );
not ( n6720 , n6713 );
and ( n6721 , n6720 , n6717 );
or ( n6722 , n6719 , n6721 );
xor ( n6723 , n6710 , n6722 );
nand ( n6724 , n377 , n380 );
buf ( n6725 , n6724 );
buf ( n6726 , n373 );
buf ( n6727 , n383 );
nand ( n6728 , n6726 , n6727 );
buf ( n6729 , n6728 );
buf ( n6730 , n6729 );
or ( n6731 , n6725 , n6730 );
buf ( n6732 , n371 );
buf ( n6733 , n385 );
nand ( n6734 , n6732 , n6733 );
buf ( n6735 , n6734 );
buf ( n6736 , n6735 );
nand ( n6737 , n6731 , n6736 );
buf ( n6738 , n6737 );
buf ( n6739 , n6724 );
buf ( n6740 , n6729 );
nand ( n6741 , n6739 , n6740 );
buf ( n6742 , n6741 );
nand ( n6743 , n6738 , n6742 );
xor ( n6744 , n6723 , n6743 );
and ( n6745 , n6695 , n6744 );
and ( n6746 , n6650 , n6694 );
or ( n6747 , n6745 , n6746 );
buf ( n6748 , n6747 );
xor ( n6749 , n6710 , n6722 );
and ( n6750 , n6749 , n6743 );
and ( n6751 , n6710 , n6722 );
or ( n6752 , n6750 , n6751 );
nand ( n6753 , n6633 , n6637 );
not ( n6754 , n6643 );
not ( n6755 , n6646 );
or ( n6756 , n6754 , n6755 );
nand ( n6757 , n6756 , n6641 );
nand ( n6758 , n6753 , n6757 );
nand ( n6759 , n371 , n383 );
xor ( n6760 , n6759 , n6618 );
nand ( n6761 , n376 , n378 );
xor ( n6762 , n6760 , n6761 );
not ( n6763 , n6762 );
not ( n6764 , n6709 );
nand ( n6765 , n6763 , n6764 );
nand ( n6766 , n6762 , n6709 );
nand ( n6767 , n6765 , n6766 );
and ( n6768 , n6758 , n6767 );
not ( n6769 , n6758 );
and ( n6770 , n6762 , n6709 );
not ( n6771 , n6762 );
and ( n6772 , n6771 , n6764 );
nor ( n6773 , n6770 , n6772 );
and ( n6774 , n6769 , n6773 );
or ( n6775 , n6768 , n6774 );
xor ( n6776 , n6752 , n6775 );
buf ( n6777 , n372 );
buf ( n6778 , n382 );
nand ( n6779 , n6777 , n6778 );
buf ( n6780 , n6779 );
buf ( n6781 , n6780 );
not ( n6782 , n6781 );
buf ( n6783 , n6782 );
buf ( n6784 , n370 );
buf ( n6785 , n384 );
nand ( n6786 , n6784 , n6785 );
buf ( n6787 , n6786 );
xor ( n6788 , n6783 , n6787 );
nand ( n6789 , n376 , n379 );
not ( n6790 , n6789 );
not ( n6791 , n6790 );
not ( n6792 , n6718 );
or ( n6793 , n6791 , n6792 );
nand ( n6794 , n6793 , n6712 );
nand ( n6795 , n6717 , n6789 );
nand ( n6796 , n6794 , n6795 );
xnor ( n6797 , n6788 , n6796 );
buf ( n6798 , n373 );
buf ( n6799 , n381 );
nand ( n6800 , n6798 , n6799 );
buf ( n6801 , n6800 );
buf ( n6802 , n6801 );
not ( n6803 , n6802 );
buf ( n6804 , n375 );
buf ( n6805 , n379 );
nand ( n6806 , n6804 , n6805 );
buf ( n6807 , n6806 );
buf ( n6808 , n6807 );
not ( n6809 , n6808 );
or ( n6810 , n6803 , n6809 );
nand ( n6811 , n373 , n379 );
not ( n6812 , n6811 );
nand ( n6813 , n6812 , n375 , n381 );
buf ( n6814 , n6813 );
nand ( n6815 , n6810 , n6814 );
buf ( n6816 , n6815 );
buf ( n6817 , n6816 );
not ( n6818 , n6817 );
buf ( n6819 , n6818 );
xor ( n6820 , n6797 , n6819 );
xor ( n6821 , n6619 , n6628 );
and ( n6822 , n6821 , n6649 );
and ( n6823 , n6619 , n6628 );
or ( n6824 , n6822 , n6823 );
not ( n6825 , n6824 );
xor ( n6826 , n6820 , n6825 );
xor ( n6827 , n6776 , n6826 );
buf ( n6828 , n6827 );
xor ( n6829 , n6748 , n6828 );
not ( n6830 , n6528 );
nand ( n6831 , n5973 , n5934 );
not ( n6832 , n6087 );
not ( n6833 , n5872 );
nand ( n6834 , n6833 , n5898 );
nand ( n6835 , n6832 , n6834 );
nand ( n6836 , n6835 , n6085 );
nand ( n6837 , n6831 , n6836 );
buf ( n6838 , n6831 );
buf ( n6839 , n5928 );
buf ( n6840 , n6071 );
nand ( n6841 , n6838 , n6839 , n6840 );
buf ( n6842 , n6841 );
buf ( n6843 , n6103 );
not ( n6844 , n6843 );
buf ( n6845 , n6844 );
nand ( n6846 , n6837 , n6842 , n6845 );
nand ( n6847 , n6098 , n6114 );
and ( n6848 , n6846 , n6847 );
not ( n6849 , n6846 );
not ( n6850 , n6847 );
and ( n6851 , n6849 , n6850 );
nor ( n6852 , n6848 , n6851 );
buf ( n6853 , n6852 );
not ( n6854 , n6853 );
buf ( n6855 , n6854 );
not ( n6856 , n6855 );
or ( n6857 , n6830 , n6856 );
buf ( n6858 , n6831 );
buf ( n6859 , n6845 );
and ( n6860 , n6858 , n6859 );
buf ( n6861 , n6860 );
not ( n6862 , n6836 );
buf ( n6863 , n5928 );
buf ( n6864 , n6071 );
nand ( n6865 , n6863 , n6864 );
buf ( n6866 , n6865 );
nand ( n6867 , n6862 , n6866 );
xor ( n6868 , n6861 , n6867 );
buf ( n6869 , n6868 );
buf ( n6870 , n6539 );
nand ( n6871 , n6869 , n6870 );
buf ( n6872 , n6871 );
nand ( n6873 , n6857 , n6872 );
buf ( n6874 , n6873 );
xor ( n6875 , n6829 , n6874 );
buf ( n6876 , n6875 );
buf ( n6877 , n6876 );
xor ( n6878 , n6650 , n6694 );
xor ( n6879 , n6878 , n6744 );
buf ( n6880 , n6879 );
not ( n6881 , n6880 );
xor ( n6882 , n6729 , n6735 );
not ( n6883 , n6724 );
xor ( n6884 , n6882 , n6883 );
not ( n6885 , n6884 );
buf ( n6886 , n375 );
buf ( n6887 , n382 );
nand ( n6888 , n6886 , n6887 );
buf ( n6889 , n6888 );
buf ( n6890 , n6889 );
not ( n6891 , n6890 );
buf ( n6892 , n6724 );
nand ( n6893 , n6891 , n6892 );
buf ( n6894 , n6893 );
buf ( n6895 , n6894 );
buf ( n6896 , n373 );
buf ( n6897 , n384 );
nand ( n6898 , n6896 , n6897 );
buf ( n6899 , n6898 );
buf ( n6900 , n6899 );
and ( n6901 , n6895 , n6900 );
buf ( n6902 , n6889 );
not ( n6903 , n6902 );
buf ( n6904 , n6724 );
nor ( n6905 , n6903 , n6904 );
buf ( n6906 , n6905 );
buf ( n6907 , n6906 );
nor ( n6908 , n6901 , n6907 );
buf ( n6909 , n6908 );
not ( n6910 , n6909 );
and ( n6911 , n6885 , n6910 );
xor ( n6912 , n6687 , n6682 );
xnor ( n6913 , n6912 , n6679 );
not ( n6914 , n6913 );
buf ( n6915 , n6637 );
not ( n6916 , n6915 );
buf ( n6917 , n376 );
buf ( n6918 , n385 );
nand ( n6919 , n6917 , n6918 );
buf ( n6920 , n6919 );
buf ( n6921 , n6920 );
not ( n6922 , n6921 );
buf ( n6923 , n6922 );
buf ( n6924 , n6923 );
nand ( n6925 , n6916 , n6924 );
buf ( n6926 , n6925 );
not ( n6927 , n6926 );
nand ( n6928 , n374 , n384 );
not ( n6929 , n6928 );
nand ( n6930 , n377 , n381 );
not ( n6931 , n6930 );
or ( n6932 , n6929 , n6931 );
buf ( n6933 , n375 );
buf ( n6934 , n383 );
nand ( n6935 , n6933 , n6934 );
buf ( n6936 , n6935 );
not ( n6937 , n6936 );
nor ( n6938 , n6928 , n6930 );
or ( n6939 , n6937 , n6938 );
nand ( n6940 , n6932 , n6939 );
not ( n6941 , n6940 );
nand ( n6942 , n6927 , n6941 );
not ( n6943 , n6942 );
or ( n6944 , n6914 , n6943 );
nand ( n6945 , n6926 , n6940 );
nand ( n6946 , n6944 , n6945 );
nand ( n6947 , n6909 , n6884 );
and ( n6948 , n6946 , n6947 );
nor ( n6949 , n6911 , n6948 );
buf ( n6950 , n6949 );
nand ( n6951 , n6881 , n6950 );
buf ( n6952 , n6951 );
buf ( n6953 , n6952 );
not ( n6954 , n6953 );
xor ( n6955 , n6670 , n6689 );
xor ( n6956 , n6955 , n6666 );
buf ( n6957 , n6956 );
not ( n6958 , n6957 );
not ( n6959 , n6071 );
buf ( n6960 , n5925 );
not ( n6961 , n6960 );
buf ( n6962 , n6961 );
not ( n6963 , n6962 );
or ( n6964 , n6959 , n6963 );
nand ( n6965 , n6964 , n6087 );
not ( n6966 , n6965 );
nor ( n6967 , n5872 , n5901 );
not ( n6968 , n6967 );
nand ( n6969 , n6968 , n6085 );
not ( n6970 , n6969 );
or ( n6971 , n6966 , n6970 );
or ( n6972 , n6965 , n6969 );
nand ( n6973 , n6971 , n6972 );
buf ( n6974 , n6973 );
buf ( n6975 , n6528 );
nand ( n6976 , n6974 , n6975 );
buf ( n6977 , n6976 );
buf ( n6978 , n6977 );
not ( n6979 , n6978 );
buf ( n6980 , n6979 );
buf ( n6981 , n6980 );
not ( n6982 , n6981 );
or ( n6983 , n6958 , n6982 );
buf ( n6984 , n6956 );
not ( n6985 , n6984 );
buf ( n6986 , n6985 );
buf ( n6987 , n6986 );
not ( n6988 , n6987 );
buf ( n6989 , n6977 );
not ( n6990 , n6989 );
or ( n6991 , n6988 , n6990 );
xor ( n6992 , n6909 , n6884 );
xor ( n6993 , n6992 , n6946 );
buf ( n6994 , n6993 );
nand ( n6995 , n6991 , n6994 );
buf ( n6996 , n6995 );
buf ( n6997 , n6996 );
nand ( n6998 , n6983 , n6997 );
buf ( n6999 , n6998 );
buf ( n7000 , n6999 );
not ( n7001 , n7000 );
or ( n7002 , n6954 , n7001 );
buf ( n7003 , n6879 );
not ( n7004 , n6949 );
buf ( n7005 , n7004 );
nand ( n7006 , n7003 , n7005 );
buf ( n7007 , n7006 );
buf ( n7008 , n7007 );
nand ( n7009 , n7002 , n7008 );
buf ( n7010 , n7009 );
buf ( n7011 , n7010 );
xor ( n7012 , n6877 , n7011 );
not ( n7013 , n5832 );
buf ( n7014 , n7013 );
not ( n7015 , n7014 );
or ( n7016 , n6307 , n6304 );
not ( n7017 , n7016 );
not ( n7018 , n6115 );
or ( n7019 , n7017 , n7018 );
nand ( n7020 , n6307 , n6304 );
nand ( n7021 , n7019 , n7020 );
buf ( n7022 , n6259 );
buf ( n7023 , n6296 );
or ( n7024 , n7022 , n7023 );
buf ( n7025 , n7024 );
nand ( n7026 , n7025 , n6388 );
not ( n7027 , n7026 );
and ( n7028 , n7021 , n7027 );
not ( n7029 , n7021 );
and ( n7030 , n7029 , n7026 );
nor ( n7031 , n7028 , n7030 );
buf ( n7032 , n7031 );
not ( n7033 , n7032 );
buf ( n7034 , n7033 );
and ( n7035 , n411 , n7034 );
not ( n7036 , n411 );
and ( n7037 , n7036 , n7031 );
or ( n7038 , n7035 , n7037 );
buf ( n7039 , n7038 );
not ( n7040 , n7039 );
or ( n7041 , n7015 , n7040 );
buf ( n7042 , n411 );
and ( n7043 , n7016 , n7020 );
xor ( n7044 , n7043 , n6116 );
buf ( n7045 , n7044 );
and ( n7046 , n7042 , n7045 );
not ( n7047 , n7042 );
buf ( n7048 , n7044 );
not ( n7049 , n7048 );
buf ( n7050 , n7049 );
buf ( n7051 , n7050 );
and ( n7052 , n7047 , n7051 );
nor ( n7053 , n7046 , n7052 );
buf ( n7054 , n7053 );
buf ( n7055 , n7054 );
buf ( n7056 , n5837 );
nand ( n7057 , n7055 , n7056 );
buf ( n7058 , n7057 );
buf ( n7059 , n7058 );
nand ( n7060 , n7041 , n7059 );
buf ( n7061 , n7060 );
buf ( n7062 , n7061 );
xor ( n7063 , n7012 , n7062 );
buf ( n7064 , n7063 );
buf ( n7065 , n7064 );
xor ( n7066 , n6899 , n6889 );
and ( n7067 , n7066 , n6883 );
not ( n7068 , n7066 );
and ( n7069 , n7068 , n6724 );
nor ( n7070 , n7067 , n7069 );
buf ( n7071 , n7070 );
not ( n7072 , n6941 );
not ( n7073 , n6926 );
or ( n7074 , n7072 , n7073 );
nand ( n7075 , n6927 , n6940 );
nand ( n7076 , n7074 , n7075 );
and ( n7077 , n7076 , n6913 );
not ( n7078 , n7076 );
not ( n7079 , n6913 );
and ( n7080 , n7078 , n7079 );
nor ( n7081 , n7077 , n7080 );
buf ( n7082 , n7081 );
xor ( n7083 , n7071 , n7082 );
buf ( n7084 , n374 );
buf ( n7085 , n385 );
nand ( n7086 , n7084 , n7085 );
buf ( n7087 , n7086 );
buf ( n7088 , n7087 );
not ( n7089 , n7088 );
buf ( n7090 , n7089 );
buf ( n7091 , n7090 );
not ( n7092 , n7091 );
xor ( n7093 , n6930 , n6936 );
buf ( n7094 , n7093 );
buf ( n7095 , n6928 );
xnor ( n7096 , n7094 , n7095 );
buf ( n7097 , n7096 );
buf ( n7098 , n7097 );
not ( n7099 , n7098 );
or ( n7100 , n7092 , n7099 );
buf ( n7101 , n377 );
buf ( n7102 , n382 );
nand ( n7103 , n7101 , n7102 );
buf ( n7104 , n7103 );
buf ( n7105 , n375 );
buf ( n7106 , n384 );
nand ( n7107 , n7105 , n7106 );
buf ( n7108 , n7107 );
xor ( n7109 , n7104 , n7108 );
nand ( n7110 , n376 , n383 );
and ( n7111 , n7109 , n7110 );
and ( n7112 , n7104 , n7108 );
nor ( n7113 , n7111 , n7112 );
not ( n7114 , n7113 );
buf ( n7115 , n7114 );
nand ( n7116 , n7100 , n7115 );
buf ( n7117 , n7116 );
buf ( n7118 , n7117 );
buf ( n7119 , n7097 );
not ( n7120 , n7119 );
buf ( n7121 , n7120 );
buf ( n7122 , n7121 );
buf ( n7123 , n7087 );
nand ( n7124 , n7122 , n7123 );
buf ( n7125 , n7124 );
buf ( n7126 , n7125 );
nand ( n7127 , n7118 , n7126 );
buf ( n7128 , n7127 );
buf ( n7129 , n7128 );
and ( n7130 , n7083 , n7129 );
and ( n7131 , n7071 , n7082 );
or ( n7132 , n7130 , n7131 );
buf ( n7133 , n7132 );
buf ( n7134 , n7133 );
buf ( n7135 , n7108 );
buf ( n7136 , n6920 );
nor ( n7137 , n7135 , n7136 );
buf ( n7138 , n7137 );
buf ( n7139 , n7138 );
buf ( n7140 , n7087 );
nand ( n7141 , n7139 , n7140 );
buf ( n7142 , n7141 );
not ( n7143 , n7142 );
xor ( n7144 , n7104 , n7108 );
xor ( n7145 , n7144 , n7110 );
not ( n7146 , n7145 );
or ( n7147 , n7143 , n7146 );
buf ( n7148 , n7138 );
not ( n7149 , n7148 );
buf ( n7150 , n7149 );
buf ( n7151 , n7150 );
buf ( n7152 , n7090 );
nand ( n7153 , n7151 , n7152 );
buf ( n7154 , n7153 );
nand ( n7155 , n7147 , n7154 );
buf ( n7156 , n373 );
buf ( n7157 , n385 );
nand ( n7158 , n7156 , n7157 );
buf ( n7159 , n7158 );
buf ( n7160 , n7159 );
not ( n7161 , n7160 );
buf ( n7162 , n6617 );
not ( n7163 , n7162 );
or ( n7164 , n7161 , n7163 );
buf ( n7165 , n6926 );
nand ( n7166 , n7164 , n7165 );
buf ( n7167 , n7166 );
and ( n7168 , n7155 , n7167 );
not ( n7169 , n7090 );
not ( n7170 , n7113 );
or ( n7171 , n7169 , n7170 );
nand ( n7172 , n7114 , n7087 );
nand ( n7173 , n7171 , n7172 );
xnor ( n7174 , n7173 , n7121 );
or ( n7175 , n7168 , n7174 );
or ( n7176 , n7155 , n7167 );
nand ( n7177 , n7175 , n7176 );
buf ( n7178 , n7177 );
not ( n7179 , n7178 );
buf ( n7180 , n412 );
not ( n7181 , n7180 );
buf ( n7182 , n6496 );
nand ( n7183 , n7181 , n7182 );
buf ( n7184 , n7183 );
buf ( n7185 , n7184 );
not ( n7186 , n7185 );
buf ( n7187 , n6973 );
not ( n7188 , n7187 );
or ( n7189 , n7186 , n7188 );
buf ( n7190 , n412 );
buf ( n7191 , n413 );
and ( n7192 , n7190 , n7191 );
buf ( n7193 , n411 );
not ( n7194 , n7193 );
buf ( n7195 , n7194 );
buf ( n7196 , n7195 );
nor ( n7197 , n7192 , n7196 );
buf ( n7198 , n7197 );
buf ( n7199 , n7198 );
nand ( n7200 , n7189 , n7199 );
buf ( n7201 , n7200 );
buf ( n7202 , n7201 );
not ( n7203 , n7202 );
or ( n7204 , n7179 , n7203 );
xor ( n7205 , n7071 , n7082 );
xor ( n7206 , n7205 , n7129 );
buf ( n7207 , n7206 );
buf ( n7208 , n7207 );
nand ( n7209 , n7204 , n7208 );
buf ( n7210 , n7209 );
buf ( n7211 , n7210 );
buf ( n7212 , n7201 );
buf ( n7213 , n7177 );
or ( n7214 , n7212 , n7213 );
buf ( n7215 , n7214 );
buf ( n7216 , n7215 );
nand ( n7217 , n7211 , n7216 );
buf ( n7218 , n7217 );
buf ( n7219 , n7218 );
xor ( n7220 , n7134 , n7219 );
buf ( n7221 , n6956 );
buf ( n7222 , n6993 );
xor ( n7223 , n7221 , n7222 );
buf ( n7224 , n6977 );
xnor ( n7225 , n7223 , n7224 );
buf ( n7226 , n7225 );
buf ( n7227 , n7226 );
and ( n7228 , n7220 , n7227 );
and ( n7229 , n7134 , n7219 );
or ( n7230 , n7228 , n7229 );
buf ( n7231 , n7230 );
buf ( n7232 , n7231 );
buf ( n7233 , n6520 );
not ( n7234 , n7233 );
xnor ( n7235 , n6496 , n7031 );
buf ( n7236 , n7235 );
not ( n7237 , n7236 );
or ( n7238 , n7234 , n7237 );
buf ( n7239 , n6496 );
not ( n7240 , n7239 );
not ( n7241 , n6115 );
not ( n7242 , n6311 );
or ( n7243 , n7241 , n7242 );
buf ( n7244 , n6389 );
not ( n7245 , n7244 );
buf ( n7246 , n7245 );
nand ( n7247 , n7243 , n7246 );
not ( n7248 , n6394 );
nor ( n7249 , n6370 , n7248 );
xor ( n7250 , n7247 , n7249 );
buf ( n7251 , n7250 );
not ( n7252 , n7251 );
or ( n7253 , n7240 , n7252 );
buf ( n7254 , n7250 );
buf ( n7255 , n6496 );
or ( n7256 , n7254 , n7255 );
nand ( n7257 , n7253 , n7256 );
buf ( n7258 , n7257 );
buf ( n7259 , n7258 );
not ( n7260 , n6519 );
buf ( n7261 , n7260 );
nand ( n7262 , n7259 , n7261 );
buf ( n7263 , n7262 );
buf ( n7264 , n7263 );
nand ( n7265 , n7238 , n7264 );
buf ( n7266 , n7265 );
buf ( n7267 , n7266 );
xor ( n7268 , n7232 , n7267 );
buf ( n7269 , n415 );
not ( n7270 , n7269 );
not ( n7271 , n6378 );
nand ( n7272 , n7271 , n6392 );
not ( n7273 , n7272 );
not ( n7274 , n6311 );
not ( n7275 , n6366 );
nor ( n7276 , n7275 , n6348 );
nor ( n7277 , n7274 , n7276 );
not ( n7278 , n7277 );
not ( n7279 , n6116 );
or ( n7280 , n7278 , n7279 );
nand ( n7281 , n6387 , n6388 );
buf ( n7282 , n7281 );
buf ( n7283 , n6370 );
not ( n7284 , n7283 );
buf ( n7285 , n7284 );
buf ( n7286 , n7285 );
and ( n7287 , n7282 , n7286 );
buf ( n7288 , n7248 );
nor ( n7289 , n7287 , n7288 );
buf ( n7290 , n7289 );
nand ( n7291 , n7280 , n7290 );
not ( n7292 , n7291 );
or ( n7293 , n7273 , n7292 );
or ( n7294 , n7272 , n7291 );
nand ( n7295 , n7293 , n7294 );
buf ( n7296 , n7295 );
not ( n7297 , n7296 );
buf ( n7298 , n7297 );
buf ( n7299 , n7298 );
not ( n7300 , n7299 );
or ( n7301 , n7270 , n7300 );
and ( n7302 , n7291 , n7272 );
not ( n7303 , n7291 );
not ( n7304 , n7272 );
and ( n7305 , n7303 , n7304 );
nor ( n7306 , n7302 , n7305 );
buf ( n7307 , n7306 );
not ( n7308 , n7307 );
buf ( n7309 , n6467 );
nand ( n7310 , n7308 , n7309 );
buf ( n7311 , n7310 );
buf ( n7312 , n7311 );
nand ( n7313 , n7301 , n7312 );
buf ( n7314 , n7313 );
not ( n7315 , n7314 );
not ( n7316 , n6455 );
or ( n7317 , n7315 , n7316 );
buf ( n7318 , n415 );
and ( n7319 , n6311 , n6379 );
not ( n7320 , n7319 );
not ( n7321 , n6116 );
or ( n7322 , n7320 , n7321 );
buf ( n7323 , n6397 );
not ( n7324 , n7323 );
buf ( n7325 , n7324 );
nand ( n7326 , n7322 , n7325 );
nand ( n7327 , n6217 , n6403 );
not ( n7328 , n7327 );
and ( n7329 , n7326 , n7328 );
not ( n7330 , n7326 );
and ( n7331 , n7330 , n7327 );
nor ( n7332 , n7329 , n7331 );
buf ( n7333 , n7332 );
not ( n7334 , n7333 );
buf ( n7335 , n7334 );
buf ( n7336 , n7335 );
and ( n7337 , n7318 , n7336 );
not ( n7338 , n7318 );
buf ( n7339 , n7332 );
not ( n7340 , n7339 );
buf ( n7341 , n7340 );
buf ( n7342 , n7341 );
not ( n7343 , n7342 );
buf ( n7344 , n7343 );
buf ( n7345 , n7344 );
and ( n7346 , n7338 , n7345 );
nor ( n7347 , n7337 , n7346 );
buf ( n7348 , n7347 );
or ( n7349 , n7348 , n6451 );
nand ( n7350 , n7317 , n7349 );
buf ( n7351 , n7350 );
and ( n7352 , n7268 , n7351 );
and ( n7353 , n7232 , n7267 );
or ( n7354 , n7352 , n7353 );
buf ( n7355 , n7354 );
buf ( n7356 , n7355 );
and ( n7357 , n7065 , n7356 );
not ( n7358 , n7065 );
buf ( n7359 , n7355 );
not ( n7360 , n7359 );
buf ( n7361 , n7360 );
buf ( n7362 , n7361 );
and ( n7363 , n7358 , n7362 );
nor ( n7364 , n7357 , n7363 );
buf ( n7365 , n7364 );
not ( n7366 , n7260 );
and ( n7367 , n413 , n7306 );
not ( n7368 , n413 );
and ( n7369 , n7368 , n7295 );
or ( n7370 , n7367 , n7369 );
not ( n7371 , n7370 );
or ( n7372 , n7366 , n7371 );
buf ( n7373 , n7258 );
buf ( n7374 , n6520 );
nand ( n7375 , n7373 , n7374 );
buf ( n7376 , n7375 );
nand ( n7377 , n7372 , n7376 );
buf ( n7378 , n7377 );
buf ( n7379 , n7013 );
not ( n7380 , n7379 );
buf ( n7381 , n7054 );
not ( n7382 , n7381 );
or ( n7383 , n7380 , n7382 );
and ( n7384 , n411 , n6852 );
not ( n7385 , n411 );
and ( n7386 , n7385 , n6855 );
or ( n7387 , n7384 , n7386 );
buf ( n7388 , n7387 );
buf ( n7389 , n5837 );
nand ( n7390 , n7388 , n7389 );
buf ( n7391 , n7390 );
buf ( n7392 , n7391 );
nand ( n7393 , n7383 , n7392 );
buf ( n7394 , n7393 );
buf ( n7395 , n6528 );
not ( n7396 , n7395 );
buf ( n7397 , n6868 );
not ( n7398 , n7397 );
or ( n7399 , n7396 , n7398 );
buf ( n7400 , n6973 );
buf ( n7401 , n7400 );
buf ( n7402 , n7401 );
buf ( n7403 , n7402 );
buf ( n7404 , n6539 );
nand ( n7405 , n7403 , n7404 );
buf ( n7406 , n7405 );
buf ( n7407 , n7406 );
nand ( n7408 , n7399 , n7407 );
buf ( n7409 , n7408 );
or ( n7410 , n7394 , n7409 );
and ( n7411 , n6879 , n6949 );
not ( n7412 , n6879 );
and ( n7413 , n7412 , n7004 );
nor ( n7414 , n7411 , n7413 );
buf ( n7415 , n7414 );
not ( n7416 , n6999 );
and ( n7417 , n7415 , n7416 );
not ( n7418 , n7415 );
and ( n7419 , n7418 , n6999 );
nor ( n7420 , n7417 , n7419 );
nand ( n7421 , n7410 , n7420 );
nand ( n7422 , n7394 , n7409 );
nand ( n7423 , n7421 , n7422 );
buf ( n7424 , n7423 );
xor ( n7425 , n7378 , n7424 );
not ( n7426 , n416 );
not ( n7427 , n6410 );
nor ( n7428 , n7427 , n6175 );
not ( n7429 , n7428 );
buf ( n7430 , n6397 );
buf ( n7431 , n6217 );
nand ( n7432 , n7430 , n7431 );
buf ( n7433 , n7432 );
buf ( n7434 , n7319 );
buf ( n7435 , n6116 );
buf ( n7436 , n6217 );
nand ( n7437 , n7434 , n7435 , n7436 );
buf ( n7438 , n7437 );
nand ( n7439 , n7433 , n7438 , n6403 );
not ( n7440 , n7439 );
not ( n7441 , n7440 );
or ( n7442 , n7429 , n7441 );
not ( n7443 , n7428 );
nand ( n7444 , n7439 , n7443 );
nand ( n7445 , n7442 , n7444 );
xor ( n7446 , n415 , n7445 );
not ( n7447 , n7446 );
or ( n7448 , n7426 , n7447 );
not ( n7449 , n7348 );
nand ( n7450 , n7449 , n6455 );
nand ( n7451 , n7448 , n7450 );
buf ( n7452 , n7451 );
xnor ( n7453 , n7425 , n7452 );
buf ( n7454 , n7453 );
xor ( n7455 , n7365 , n7454 );
buf ( n7456 , n7455 );
xor ( n7457 , n7232 , n7267 );
xor ( n7458 , n7457 , n7351 );
buf ( n7459 , n7458 );
buf ( n7460 , n7459 );
not ( n7461 , n7460 );
buf ( n7462 , n7461 );
not ( n7463 , n7462 );
buf ( n7464 , n7414 );
buf ( n7465 , n7409 );
xor ( n7466 , n7464 , n7465 );
buf ( n7467 , n6999 );
xor ( n7468 , n7466 , n7467 );
buf ( n7469 , n7468 );
buf ( n7470 , n7469 );
buf ( n7471 , n7394 );
not ( n7472 , n7471 );
buf ( n7473 , n7472 );
buf ( n7474 , n7473 );
and ( n7475 , n7470 , n7474 );
not ( n7476 , n7470 );
buf ( n7477 , n7394 );
and ( n7478 , n7476 , n7477 );
nor ( n7479 , n7475 , n7478 );
buf ( n7480 , n7479 );
buf ( n7481 , n7480 );
not ( n7482 , n7481 );
buf ( n7483 , n7482 );
not ( n7484 , n7483 );
and ( n7485 , n7463 , n7484 );
buf ( n7486 , n7462 );
buf ( n7487 , n7483 );
nand ( n7488 , n7486 , n7487 );
buf ( n7489 , n7488 );
buf ( n7490 , n7013 );
not ( n7491 , n7490 );
buf ( n7492 , n7387 );
not ( n7493 , n7492 );
or ( n7494 , n7491 , n7493 );
buf ( n7495 , n6868 );
not ( n7496 , n7495 );
buf ( n7497 , n7496 );
and ( n7498 , n411 , n7497 );
not ( n7499 , n411 );
and ( n7500 , n7499 , n6868 );
or ( n7501 , n7498 , n7500 );
buf ( n7502 , n7501 );
buf ( n7503 , n5837 );
nand ( n7504 , n7502 , n7503 );
buf ( n7505 , n7504 );
buf ( n7506 , n7505 );
nand ( n7507 , n7494 , n7506 );
buf ( n7508 , n7507 );
buf ( n7509 , n7508 );
xor ( n7510 , n7134 , n7219 );
xor ( n7511 , n7510 , n7227 );
buf ( n7512 , n7511 );
buf ( n7513 , n7512 );
xor ( n7514 , n7509 , n7513 );
buf ( n7515 , n7260 );
not ( n7516 , n7515 );
buf ( n7517 , n7235 );
not ( n7518 , n7517 );
or ( n7519 , n7516 , n7518 );
buf ( n7520 , n413 );
not ( n7521 , n7520 );
buf ( n7522 , n7050 );
not ( n7523 , n7522 );
or ( n7524 , n7521 , n7523 );
buf ( n7525 , n7044 );
buf ( n7526 , n6496 );
nand ( n7527 , n7525 , n7526 );
buf ( n7528 , n7527 );
buf ( n7529 , n7528 );
nand ( n7530 , n7524 , n7529 );
buf ( n7531 , n7530 );
buf ( n7532 , n7531 );
buf ( n7533 , n6520 );
nand ( n7534 , n7532 , n7533 );
buf ( n7535 , n7534 );
buf ( n7536 , n7535 );
nand ( n7537 , n7519 , n7536 );
buf ( n7538 , n7537 );
buf ( n7539 , n7538 );
and ( n7540 , n7514 , n7539 );
and ( n7541 , n7509 , n7513 );
or ( n7542 , n7540 , n7541 );
buf ( n7543 , n7542 );
and ( n7544 , n7489 , n7543 );
nor ( n7545 , n7485 , n7544 );
buf ( n7546 , n7545 );
nand ( n7547 , n7456 , n7546 );
buf ( n7548 , n7547 );
buf ( n7549 , n7548 );
buf ( n7550 , n7549 );
buf ( n7551 , n7550 );
buf ( n7552 , n7551 );
not ( n7553 , n7552 );
xor ( n7554 , n7201 , n7177 );
xor ( n7555 , n7554 , n7207 );
buf ( n7556 , n7555 );
buf ( n7557 , n7013 );
not ( n7558 , n7557 );
buf ( n7559 , n7501 );
not ( n7560 , n7559 );
or ( n7561 , n7558 , n7560 );
buf ( n7562 , n7402 );
not ( n7563 , n7562 );
buf ( n7564 , n7563 );
and ( n7565 , n411 , n7564 );
not ( n7566 , n411 );
and ( n7567 , n7566 , n7402 );
or ( n7568 , n7565 , n7567 );
buf ( n7569 , n7568 );
buf ( n7570 , n5837 );
nand ( n7571 , n7569 , n7570 );
buf ( n7572 , n7571 );
buf ( n7573 , n7572 );
nand ( n7574 , n7561 , n7573 );
buf ( n7575 , n7574 );
buf ( n7576 , n7575 );
xor ( n7577 , n7556 , n7576 );
buf ( n7578 , n7260 );
not ( n7579 , n7578 );
buf ( n7580 , n7531 );
not ( n7581 , n7580 );
or ( n7582 , n7579 , n7581 );
buf ( n7583 , n413 );
not ( n7584 , n7583 );
buf ( n7585 , n6852 );
not ( n7586 , n7585 );
or ( n7587 , n7584 , n7586 );
nand ( n7588 , n6855 , n6496 );
buf ( n7589 , n7588 );
nand ( n7590 , n7587 , n7589 );
buf ( n7591 , n7590 );
buf ( n7592 , n7591 );
buf ( n7593 , n6520 );
nand ( n7594 , n7592 , n7593 );
buf ( n7595 , n7594 );
buf ( n7596 , n7595 );
nand ( n7597 , n7582 , n7596 );
buf ( n7598 , n7597 );
buf ( n7599 , n7598 );
and ( n7600 , n7577 , n7599 );
and ( n7601 , n7556 , n7576 );
or ( n7602 , n7600 , n7601 );
buf ( n7603 , n7602 );
buf ( n7604 , n7603 );
not ( n7605 , n7604 );
buf ( n7606 , n416 );
not ( n7607 , n7606 );
buf ( n7608 , n7314 );
not ( n7609 , n7608 );
or ( n7610 , n7607 , n7609 );
buf ( n7611 , n415 );
buf ( n7612 , n7250 );
and ( n7613 , n7611 , n7612 );
not ( n7614 , n7611 );
buf ( n7615 , n7250 );
not ( n7616 , n7615 );
buf ( n7617 , n7616 );
buf ( n7618 , n7617 );
and ( n7619 , n7614 , n7618 );
nor ( n7620 , n7613 , n7619 );
buf ( n7621 , n7620 );
buf ( n7622 , n7621 );
buf ( n7623 , n6455 );
nand ( n7624 , n7622 , n7623 );
buf ( n7625 , n7624 );
buf ( n7626 , n7625 );
nand ( n7627 , n7610 , n7626 );
buf ( n7628 , n7627 );
buf ( n7629 , n7628 );
not ( n7630 , n7629 );
buf ( n7631 , n7630 );
buf ( n7632 , n7631 );
nand ( n7633 , n7605 , n7632 );
buf ( n7634 , n7633 );
buf ( n7635 , n7634 );
not ( n7636 , n7635 );
xor ( n7637 , n7509 , n7513 );
xor ( n7638 , n7637 , n7539 );
buf ( n7639 , n7638 );
buf ( n7640 , n7639 );
not ( n7641 , n7640 );
or ( n7642 , n7636 , n7641 );
buf ( n7643 , n7631 );
not ( n7644 , n7643 );
buf ( n7645 , n7603 );
nand ( n7646 , n7644 , n7645 );
buf ( n7647 , n7646 );
buf ( n7648 , n7647 );
nand ( n7649 , n7642 , n7648 );
buf ( n7650 , n7649 );
buf ( n7651 , n7650 );
not ( n7652 , n7651 );
buf ( n7653 , n7480 );
buf ( n7654 , n7543 );
xor ( n7655 , n7653 , n7654 );
buf ( n7656 , n7459 );
xnor ( n7657 , n7655 , n7656 );
buf ( n7658 , n7657 );
buf ( n7659 , n7658 );
nand ( n7660 , n7652 , n7659 );
buf ( n7661 , n7660 );
buf ( n7662 , n7661 );
buf ( n7663 , n416 );
not ( n7664 , n7663 );
buf ( n7665 , n415 );
not ( n7666 , n7665 );
buf ( n7667 , n7034 );
not ( n7668 , n7667 );
or ( n7669 , n7666 , n7668 );
buf ( n7670 , n6467 );
buf ( n7671 , n7031 );
nand ( n7672 , n7670 , n7671 );
buf ( n7673 , n7672 );
buf ( n7674 , n7673 );
nand ( n7675 , n7669 , n7674 );
buf ( n7676 , n7675 );
buf ( n7677 , n7676 );
not ( n7678 , n7677 );
or ( n7679 , n7664 , n7678 );
buf ( n7680 , n415 );
buf ( n7681 , n7044 );
and ( n7682 , n7680 , n7681 );
not ( n7683 , n7680 );
buf ( n7684 , n7050 );
and ( n7685 , n7683 , n7684 );
nor ( n7686 , n7682 , n7685 );
buf ( n7687 , n7686 );
buf ( n7688 , n7687 );
buf ( n7689 , n6455 );
nand ( n7690 , n7688 , n7689 );
buf ( n7691 , n7690 );
buf ( n7692 , n7691 );
nand ( n7693 , n7679 , n7692 );
buf ( n7694 , n7693 );
buf ( n7695 , n7694 );
xor ( n7696 , n6868 , n6496 );
not ( n7697 , n7696 );
not ( n7698 , n6523 );
and ( n7699 , n7697 , n7698 );
and ( n7700 , n7591 , n7260 );
nor ( n7701 , n7699 , n7700 );
buf ( n7702 , n7701 );
not ( n7703 , n7702 );
buf ( n7704 , n7703 );
buf ( n7705 , n7704 );
nor ( n7706 , n7695 , n7705 );
buf ( n7707 , n7706 );
buf ( n7708 , n7707 );
buf ( n7709 , n7174 );
not ( n7710 , n7709 );
buf ( n7711 , n7155 );
buf ( n7712 , n7167 );
not ( n7713 , n7712 );
xor ( n7714 , n7711 , n7713 );
buf ( n7715 , n7714 );
buf ( n7716 , n7715 );
not ( n7717 , n7716 );
or ( n7718 , n7710 , n7717 );
buf ( n7719 , n7715 );
buf ( n7720 , n7174 );
or ( n7721 , n7719 , n7720 );
nand ( n7722 , n7718 , n7721 );
buf ( n7723 , n7722 );
not ( n7724 , n7723 );
buf ( n7725 , n7402 );
buf ( n7726 , n7013 );
nand ( n7727 , n7725 , n7726 );
buf ( n7728 , n7727 );
not ( n7729 , n7728 );
and ( n7730 , n7724 , n7729 );
and ( n7731 , n7723 , n7728 );
nor ( n7732 , n7730 , n7731 );
buf ( n7733 , n7145 );
buf ( n7734 , n7150 );
buf ( n7735 , n7090 );
and ( n7736 , n7734 , n7735 );
not ( n7737 , n7734 );
buf ( n7738 , n7087 );
and ( n7739 , n7737 , n7738 );
nor ( n7740 , n7736 , n7739 );
buf ( n7741 , n7740 );
buf ( n7742 , n7741 );
xnor ( n7743 , n7733 , n7742 );
buf ( n7744 , n7743 );
not ( n7745 , n7744 );
buf ( n7746 , n375 );
buf ( n7747 , n385 );
and ( n7748 , n7746 , n7747 );
buf ( n7749 , n376 );
buf ( n7750 , n384 );
and ( n7751 , n7749 , n7750 );
nor ( n7752 , n7748 , n7751 );
buf ( n7753 , n7752 );
buf ( n7754 , n7753 );
not ( n7755 , n7754 );
buf ( n7756 , n7150 );
nand ( n7757 , n7755 , n7756 );
buf ( n7758 , n7757 );
buf ( n7759 , n7758 );
buf ( n7760 , n377 );
buf ( n7761 , n383 );
nand ( n7762 , n7760 , n7761 );
buf ( n7763 , n7762 );
buf ( n7764 , n7763 );
buf ( n7765 , n6920 );
or ( n7766 , n7764 , n7765 );
buf ( n7767 , n7766 );
buf ( n7768 , n7767 );
and ( n7769 , n7759 , n7768 );
buf ( n7770 , n7763 );
buf ( n7771 , n6920 );
and ( n7772 , n7770 , n7771 );
nor ( n7773 , n7769 , n7772 );
buf ( n7774 , n7773 );
not ( n7775 , n7774 );
nand ( n7776 , n7745 , n7775 );
not ( n7777 , n7776 );
buf ( n7778 , n6518 );
not ( n7779 , n7778 );
buf ( n7780 , n6973 );
not ( n7781 , n7780 );
or ( n7782 , n7779 , n7781 );
buf ( n7783 , n414 );
buf ( n7784 , n415 );
and ( n7785 , n7783 , n7784 );
buf ( n7786 , n6496 );
nor ( n7787 , n7785 , n7786 );
buf ( n7788 , n7787 );
buf ( n7789 , n7788 );
nand ( n7790 , n7782 , n7789 );
buf ( n7791 , n7790 );
not ( n7792 , n7791 );
or ( n7793 , n7777 , n7792 );
nand ( n7794 , n7744 , n7774 );
nand ( n7795 , n7793 , n7794 );
and ( n7796 , n7732 , n7795 );
not ( n7797 , n7732 );
not ( n7798 , n7795 );
and ( n7799 , n7797 , n7798 );
nor ( n7800 , n7796 , n7799 );
not ( n7801 , n7800 );
buf ( n7802 , n7801 );
or ( n7803 , n7708 , n7802 );
buf ( n7804 , n7694 );
buf ( n7805 , n7704 );
nand ( n7806 , n7804 , n7805 );
buf ( n7807 , n7806 );
buf ( n7808 , n7807 );
nand ( n7809 , n7803 , n7808 );
buf ( n7810 , n7809 );
not ( n7811 , n7810 );
buf ( n7812 , n7723 );
not ( n7813 , n7812 );
buf ( n7814 , n7728 );
nand ( n7815 , n7813 , n7814 );
buf ( n7816 , n7815 );
buf ( n7817 , n7816 );
not ( n7818 , n7817 );
buf ( n7819 , n7798 );
not ( n7820 , n7819 );
or ( n7821 , n7818 , n7820 );
buf ( n7822 , n7728 );
not ( n7823 , n7822 );
buf ( n7824 , n7723 );
nand ( n7825 , n7823 , n7824 );
buf ( n7826 , n7825 );
buf ( n7827 , n7826 );
nand ( n7828 , n7821 , n7827 );
buf ( n7829 , n7828 );
buf ( n7830 , n7829 );
buf ( n7831 , n6455 );
not ( n7832 , n7831 );
buf ( n7833 , n7676 );
not ( n7834 , n7833 );
or ( n7835 , n7832 , n7834 );
buf ( n7836 , n7621 );
buf ( n7837 , n416 );
nand ( n7838 , n7836 , n7837 );
buf ( n7839 , n7838 );
buf ( n7840 , n7839 );
nand ( n7841 , n7835 , n7840 );
buf ( n7842 , n7841 );
buf ( n7843 , n7842 );
xor ( n7844 , n7830 , n7843 );
xor ( n7845 , n7556 , n7576 );
xor ( n7846 , n7845 , n7599 );
buf ( n7847 , n7846 );
buf ( n7848 , n7847 );
xnor ( n7849 , n7844 , n7848 );
buf ( n7850 , n7849 );
nand ( n7851 , n7811 , n7850 );
not ( n7852 , n7851 );
buf ( n7853 , n413 );
not ( n7854 , n7853 );
buf ( n7855 , n7564 );
not ( n7856 , n7855 );
or ( n7857 , n7854 , n7856 );
buf ( n7858 , n7402 );
buf ( n7859 , n6496 );
nand ( n7860 , n7858 , n7859 );
buf ( n7861 , n7860 );
buf ( n7862 , n7861 );
nand ( n7863 , n7857 , n7862 );
buf ( n7864 , n7863 );
not ( n7865 , n7864 );
not ( n7866 , n6520 );
or ( n7867 , n7865 , n7866 );
or ( n7868 , n7696 , n6519 );
nand ( n7869 , n7867 , n7868 );
buf ( n7870 , n7869 );
not ( n7871 , n7870 );
buf ( n7872 , n7871 );
buf ( n7873 , n7872 );
not ( n7874 , n7873 );
buf ( n7875 , n416 );
not ( n7876 , n7875 );
buf ( n7877 , n7687 );
not ( n7878 , n7877 );
or ( n7879 , n7876 , n7878 );
buf ( n7880 , n415 );
buf ( n7881 , n6855 );
and ( n7882 , n7880 , n7881 );
not ( n7883 , n7880 );
buf ( n7884 , n6852 );
and ( n7885 , n7883 , n7884 );
nor ( n7886 , n7882 , n7885 );
buf ( n7887 , n7886 );
buf ( n7888 , n7887 );
buf ( n7889 , n6455 );
nand ( n7890 , n7888 , n7889 );
buf ( n7891 , n7890 );
buf ( n7892 , n7891 );
nand ( n7893 , n7879 , n7892 );
buf ( n7894 , n7893 );
buf ( n7895 , n7894 );
not ( n7896 , n7895 );
buf ( n7897 , n7896 );
buf ( n7898 , n7897 );
not ( n7899 , n7898 );
or ( n7900 , n7874 , n7899 );
not ( n7901 , n7791 );
not ( n7902 , n7775 );
not ( n7903 , n7744 );
or ( n7904 , n7902 , n7903 );
nand ( n7905 , n7745 , n7774 );
nand ( n7906 , n7904 , n7905 );
and ( n7907 , n7901 , n7906 );
not ( n7908 , n7901 );
not ( n7909 , n7906 );
and ( n7910 , n7908 , n7909 );
nor ( n7911 , n7907 , n7910 );
buf ( n7912 , n7911 );
nand ( n7913 , n7900 , n7912 );
buf ( n7914 , n7913 );
buf ( n7915 , n7914 );
buf ( n7916 , n7897 );
not ( n7917 , n7916 );
buf ( n7918 , n7869 );
nand ( n7919 , n7917 , n7918 );
buf ( n7920 , n7919 );
buf ( n7921 , n7920 );
nand ( n7922 , n7915 , n7921 );
buf ( n7923 , n7922 );
buf ( n7924 , n7923 );
not ( n7925 , n7924 );
buf ( n7926 , n7694 );
not ( n7927 , n7926 );
not ( n7928 , n7701 );
not ( n7929 , n7801 );
or ( n7930 , n7928 , n7929 );
or ( n7931 , n7801 , n7701 );
nand ( n7932 , n7930 , n7931 );
buf ( n7933 , n7932 );
not ( n7934 , n7933 );
and ( n7935 , n7927 , n7934 );
buf ( n7936 , n7694 );
buf ( n7937 , n7932 );
and ( n7938 , n7936 , n7937 );
nor ( n7939 , n7935 , n7938 );
buf ( n7940 , n7939 );
buf ( n7941 , n7940 );
nand ( n7942 , n7925 , n7941 );
buf ( n7943 , n7942 );
not ( n7944 , n7943 );
xor ( n7945 , n7911 , n7869 );
xnor ( n7946 , n7945 , n7897 );
buf ( n7947 , n7946 );
buf ( n7948 , n377 );
buf ( n7949 , n384 );
nand ( n7950 , n7948 , n7949 );
buf ( n7951 , n7950 );
buf ( n7952 , n7951 );
not ( n7953 , n7952 );
buf ( n7954 , n6920 );
nand ( n7955 , n7953 , n7954 );
buf ( n7956 , n7955 );
buf ( n7957 , n7956 );
not ( n7958 , n7957 );
buf ( n7959 , n7402 );
buf ( n7960 , n416 );
nand ( n7961 , n7959 , n7960 );
buf ( n7962 , n7961 );
buf ( n7963 , n7962 );
buf ( n7964 , n415 );
nand ( n7965 , n7963 , n7964 );
buf ( n7966 , n7965 );
buf ( n7967 , n7966 );
not ( n7968 , n7967 );
buf ( n7969 , n7968 );
buf ( n7970 , n7969 );
not ( n7971 , n7970 );
or ( n7972 , n7958 , n7971 );
buf ( n7973 , n6923 );
buf ( n7974 , n7951 );
nand ( n7975 , n7973 , n7974 );
buf ( n7976 , n7975 );
buf ( n7977 , n7976 );
nand ( n7978 , n7972 , n7977 );
buf ( n7979 , n7978 );
not ( n7980 , n7979 );
buf ( n7981 , n7402 );
buf ( n7982 , n7260 );
nand ( n7983 , n7981 , n7982 );
buf ( n7984 , n7983 );
or ( n7985 , n7980 , n7984 );
buf ( n7986 , n7984 );
not ( n7987 , n7986 );
buf ( n7988 , n7980 );
not ( n7989 , n7988 );
or ( n7990 , n7987 , n7989 );
buf ( n7991 , n7763 );
buf ( n7992 , n6920 );
and ( n7993 , n7991 , n7992 );
not ( n7994 , n7991 );
buf ( n7995 , n6923 );
and ( n7996 , n7994 , n7995 );
nor ( n7997 , n7993 , n7996 );
buf ( n7998 , n7997 );
buf ( n7999 , n7998 );
not ( n8000 , n7999 );
buf ( n8001 , n7758 );
not ( n8002 , n8001 );
buf ( n8003 , n8002 );
buf ( n8004 , n8003 );
not ( n8005 , n8004 );
or ( n8006 , n8000 , n8005 );
buf ( n8007 , n8003 );
buf ( n8008 , n7998 );
or ( n8009 , n8007 , n8008 );
nand ( n8010 , n8006 , n8009 );
buf ( n8011 , n8010 );
buf ( n8012 , n8011 );
nand ( n8013 , n7990 , n8012 );
buf ( n8014 , n8013 );
nand ( n8015 , n7985 , n8014 );
buf ( n8016 , n8015 );
nor ( n8017 , n7947 , n8016 );
buf ( n8018 , n8017 );
buf ( n8019 , n8018 );
xor ( n8020 , n8011 , n7984 );
and ( n8021 , n8020 , n7979 );
not ( n8022 , n8020 );
and ( n8023 , n8022 , n7980 );
nor ( n8024 , n8021 , n8023 );
buf ( n8025 , n7887 );
buf ( n8026 , n416 );
nand ( n8027 , n8025 , n8026 );
buf ( n8028 , n8027 );
buf ( n8029 , n415 );
not ( n8030 , n8029 );
buf ( n8031 , n7497 );
not ( n8032 , n8031 );
or ( n8033 , n8030 , n8032 );
buf ( n8034 , n6868 );
buf ( n8035 , n6467 );
nand ( n8036 , n8034 , n8035 );
buf ( n8037 , n8036 );
buf ( n8038 , n8037 );
nand ( n8039 , n8033 , n8038 );
buf ( n8040 , n8039 );
buf ( n8041 , n8040 );
buf ( n8042 , n6455 );
nand ( n8043 , n8041 , n8042 );
buf ( n8044 , n8043 );
nand ( n8045 , n8024 , n8028 , n8044 );
buf ( n8046 , n416 );
not ( n8047 , n8046 );
buf ( n8048 , n8040 );
not ( n8049 , n8048 );
or ( n8050 , n8047 , n8049 );
buf ( n8051 , n7564 );
buf ( n8052 , n6455 );
nand ( n8053 , n8051 , n8052 );
buf ( n8054 , n8053 );
buf ( n8055 , n8054 );
nand ( n8056 , n8050 , n8055 );
buf ( n8057 , n8056 );
buf ( n8058 , n8057 );
buf ( n8059 , n7951 );
not ( n8060 , n8059 );
buf ( n8061 , n6920 );
not ( n8062 , n8061 );
and ( n8063 , n8060 , n8062 );
buf ( n8064 , n7951 );
buf ( n8065 , n6920 );
and ( n8066 , n8064 , n8065 );
nor ( n8067 , n8063 , n8066 );
buf ( n8068 , n8067 );
buf ( n8069 , n8068 );
not ( n8070 , n8069 );
buf ( n8071 , n7969 );
not ( n8072 , n8071 );
or ( n8073 , n8070 , n8072 );
buf ( n8074 , n7969 );
buf ( n8075 , n8068 );
or ( n8076 , n8074 , n8075 );
nand ( n8077 , n8073 , n8076 );
buf ( n8078 , n8077 );
buf ( n8079 , n8078 );
nor ( n8080 , n8058 , n8079 );
buf ( n8081 , n8080 );
buf ( n8082 , n8081 );
buf ( n8083 , n7962 );
buf ( n8084 , n377 );
buf ( n8085 , n385 );
and ( n8086 , n8084 , n8085 );
buf ( n8087 , n8086 );
buf ( n8088 , n8087 );
nand ( n8089 , n8083 , n8088 );
buf ( n8090 , n8089 );
buf ( n8091 , n8090 );
not ( n8092 , n8091 );
buf ( n8093 , n8092 );
buf ( n8094 , n8093 );
or ( n8095 , n8082 , n8094 );
buf ( n8096 , n8057 );
buf ( n8097 , n8078 );
nand ( n8098 , n8096 , n8097 );
buf ( n8099 , n8098 );
buf ( n8100 , n8099 );
nand ( n8101 , n8095 , n8100 );
buf ( n8102 , n8101 );
and ( n8103 , n8045 , n8102 );
buf ( n8104 , n8024 );
not ( n8105 , n8104 );
buf ( n8106 , n8105 );
and ( n8107 , n7887 , n416 );
and ( n8108 , n8040 , n6455 );
nor ( n8109 , n8107 , n8108 );
buf ( n8110 , n8109 );
not ( n8111 , n8110 );
buf ( n8112 , n8111 );
and ( n8113 , n8106 , n8112 );
nor ( n8114 , n8103 , n8113 );
buf ( n8115 , n8114 );
or ( n8116 , n8019 , n8115 );
buf ( n8117 , n7946 );
buf ( n8118 , n8015 );
nand ( n8119 , n8117 , n8118 );
buf ( n8120 , n8119 );
buf ( n8121 , n8120 );
nand ( n8122 , n8116 , n8121 );
buf ( n8123 , n8122 );
not ( n8124 , n8123 );
or ( n8125 , n7944 , n8124 );
not ( n8126 , n7940 );
nand ( n8127 , n8126 , n7923 );
nand ( n8128 , n8125 , n8127 );
not ( n8129 , n8128 );
or ( n8130 , n7852 , n8129 );
not ( n8131 , n7850 );
buf ( n8132 , n7707 );
buf ( n8133 , n7801 );
or ( n8134 , n8132 , n8133 );
buf ( n8135 , n7807 );
nand ( n8136 , n8134 , n8135 );
buf ( n8137 , n8136 );
nand ( n8138 , n8131 , n8137 );
nand ( n8139 , n8130 , n8138 );
buf ( n8140 , n8139 );
not ( n8141 , n7829 );
buf ( n8142 , n6455 );
not ( n8143 , n8142 );
buf ( n8144 , n7676 );
not ( n8145 , n8144 );
or ( n8146 , n8143 , n8145 );
buf ( n8147 , n7839 );
nand ( n8148 , n8146 , n8147 );
buf ( n8149 , n8148 );
not ( n8150 , n8149 );
nand ( n8151 , n8141 , n8150 );
not ( n8152 , n8151 );
not ( n8153 , n7847 );
or ( n8154 , n8152 , n8153 );
not ( n8155 , n8150 );
nand ( n8156 , n8155 , n7829 );
nand ( n8157 , n8154 , n8156 );
buf ( n8158 , n8157 );
not ( n8159 , n8158 );
not ( n8160 , n7631 );
and ( n8161 , n7603 , n8160 );
not ( n8162 , n7603 );
and ( n8163 , n8162 , n7631 );
nor ( n8164 , n8161 , n8163 );
not ( n8165 , n7639 );
and ( n8166 , n8164 , n8165 );
not ( n8167 , n8164 );
and ( n8168 , n8167 , n7639 );
nor ( n8169 , n8166 , n8168 );
buf ( n8170 , n8169 );
nand ( n8171 , n8159 , n8170 );
buf ( n8172 , n8171 );
buf ( n8173 , n8172 );
nand ( n8174 , n8140 , n8173 );
buf ( n8175 , n8174 );
buf ( n8176 , n8175 );
not ( n8177 , n8169 );
nand ( n8178 , n8177 , n8157 );
buf ( n8179 , n8178 );
nand ( n8180 , n8176 , n8179 );
buf ( n8181 , n8180 );
buf ( n8182 , n8181 );
and ( n8183 , n7662 , n8182 );
buf ( n8184 , n8183 );
buf ( n8185 , n8184 );
not ( n8186 , n8185 );
or ( n8187 , n7553 , n8186 );
not ( n8188 , n7548 );
buf ( n8189 , n7650 );
not ( n8190 , n8189 );
buf ( n8191 , n7658 );
nor ( n8192 , n8190 , n8191 );
buf ( n8193 , n8192 );
not ( n8194 , n8193 );
or ( n8195 , n8188 , n8194 );
buf ( n8196 , n7455 );
not ( n8197 , n8196 );
buf ( n8198 , n8197 );
buf ( n8199 , n8198 );
buf ( n8200 , n7545 );
not ( n8201 , n8200 );
buf ( n8202 , n8201 );
buf ( n8203 , n8202 );
nand ( n8204 , n8199 , n8203 );
buf ( n8205 , n8204 );
nand ( n8206 , n8195 , n8205 );
buf ( n8207 , n8206 );
not ( n8208 , n8207 );
buf ( n8209 , n8208 );
buf ( n8210 , n8209 );
nand ( n8211 , n8187 , n8210 );
buf ( n8212 , n8211 );
not ( n8213 , n8212 );
not ( n8214 , n6520 );
not ( n8215 , n413 );
not ( n8216 , n7341 );
or ( n8217 , n8215 , n8216 );
buf ( n8218 , n6496 );
buf ( n8219 , n7332 );
nand ( n8220 , n8218 , n8219 );
buf ( n8221 , n8220 );
nand ( n8222 , n8217 , n8221 );
not ( n8223 , n8222 );
or ( n8224 , n8214 , n8223 );
xnor ( n8225 , n7428 , n413 );
and ( n8226 , n8225 , n7439 );
not ( n8227 , n8225 );
and ( n8228 , n8227 , n7440 );
or ( n8229 , n8226 , n8228 );
nand ( n8230 , n8229 , n7260 );
nand ( n8231 , n8224 , n8230 );
not ( n8232 , n8231 );
xor ( n8233 , n6752 , n6775 );
and ( n8234 , n8233 , n6826 );
and ( n8235 , n6752 , n6775 );
or ( n8236 , n8234 , n8235 );
not ( n8237 , n8236 );
nand ( n8238 , n381 , n372 );
not ( n8239 , n8238 );
nand ( n8240 , n373 , n380 );
nand ( n8241 , n383 , n370 );
nor ( n8242 , n8239 , n8240 , n8241 );
not ( n8243 , n8242 );
nand ( n8244 , n381 , n372 );
nand ( n8245 , n8240 , n8244 , n8241 );
not ( n8246 , n8241 );
nand ( n8247 , n8246 , n8239 , n8240 );
not ( n8248 , n8240 );
not ( n8249 , n8244 );
nand ( n8250 , n8248 , n8249 , n8241 );
nand ( n8251 , n8243 , n8245 , n8247 , n8250 );
not ( n8252 , n8251 );
not ( n8253 , n6813 );
not ( n8254 , n6759 );
nand ( n8255 , n374 , n380 );
not ( n8256 , n8255 );
or ( n8257 , n8254 , n8256 );
or ( n8258 , n8255 , n6707 );
nand ( n8259 , n8258 , n6761 );
nand ( n8260 , n8257 , n8259 );
and ( n8261 , n8253 , n8260 );
and ( n8262 , n8252 , n8261 );
not ( n8263 , n8252 );
nor ( n8264 , n6813 , n8260 );
and ( n8265 , n8263 , n8264 );
nor ( n8266 , n8262 , n8265 );
nand ( n8267 , n8251 , n8260 );
or ( n8268 , n8267 , n8253 );
not ( n8269 , n8260 );
nand ( n8270 , n8269 , n8252 , n6813 );
and ( n8271 , n8266 , n8268 , n8270 );
not ( n8272 , n6819 );
not ( n8273 , n6797 );
not ( n8274 , n8273 );
or ( n8275 , n8272 , n8274 );
nand ( n8276 , n8275 , n6824 );
not ( n8277 , n6819 );
nand ( n8278 , n8277 , n6797 );
nand ( n8279 , n8276 , n8278 );
xor ( n8280 , n8271 , n8279 );
buf ( n8281 , n6787 );
not ( n8282 , n8281 );
buf ( n8283 , n6783 );
nand ( n8284 , n8282 , n8283 );
buf ( n8285 , n8284 );
buf ( n8286 , n8285 );
not ( n8287 , n8286 );
buf ( n8288 , n6796 );
not ( n8289 , n8288 );
or ( n8290 , n8287 , n8289 );
buf ( n8291 , n6780 );
buf ( n8292 , n6787 );
nand ( n8293 , n8291 , n8292 );
buf ( n8294 , n8293 );
buf ( n8295 , n8294 );
nand ( n8296 , n8290 , n8295 );
buf ( n8297 , n8296 );
not ( n8298 , n8297 );
buf ( n8299 , n374 );
buf ( n8300 , n379 );
nand ( n8301 , n8299 , n8300 );
buf ( n8302 , n8301 );
buf ( n8303 , n375 );
buf ( n8304 , n378 );
nand ( n8305 , n8303 , n8304 );
buf ( n8306 , n8305 );
xor ( n8307 , n8302 , n8306 );
buf ( n8308 , n371 );
buf ( n8309 , n382 );
nand ( n8310 , n8308 , n8309 );
buf ( n8311 , n8310 );
xnor ( n8312 , n8307 , n8311 );
xor ( n8313 , n8298 , n8312 );
not ( n8314 , n6758 );
not ( n8315 , n6765 );
or ( n8316 , n8314 , n8315 );
nand ( n8317 , n8316 , n6766 );
xor ( n8318 , n8313 , n8317 );
xnor ( n8319 , n8280 , n8318 );
not ( n8320 , n8319 );
nand ( n8321 , n8237 , n8320 );
not ( n8322 , n8321 );
buf ( n8323 , n6528 );
not ( n8324 , n8323 );
buf ( n8325 , n7044 );
not ( n8326 , n8325 );
or ( n8327 , n8324 , n8326 );
buf ( n8328 , n6855 );
buf ( n8329 , n6539 );
nand ( n8330 , n8328 , n8329 );
buf ( n8331 , n8330 );
buf ( n8332 , n8331 );
nand ( n8333 , n8327 , n8332 );
buf ( n8334 , n8333 );
not ( n8335 , n8334 );
or ( n8336 , n8322 , n8335 );
nand ( n8337 , n8319 , n8236 );
nand ( n8338 , n8336 , n8337 );
not ( n8339 , n8338 );
not ( n8340 , n6528 );
not ( n8341 , n7031 );
or ( n8342 , n8340 , n8341 );
buf ( n8343 , n7044 );
buf ( n8344 , n6539 );
nand ( n8345 , n8343 , n8344 );
buf ( n8346 , n8345 );
nand ( n8347 , n8342 , n8346 );
not ( n8348 , n8347 );
not ( n8349 , n8348 );
and ( n8350 , n8339 , n8349 );
and ( n8351 , n8338 , n8348 );
nor ( n8352 , n8350 , n8351 );
not ( n8353 , n8352 );
or ( n8354 , n8232 , n8353 );
or ( n8355 , n8231 , n8352 );
nand ( n8356 , n8354 , n8355 );
not ( n8357 , n8356 );
xor ( n8358 , n8236 , n8320 );
xnor ( n8359 , n8358 , n8334 );
buf ( n8360 , n8359 );
buf ( n8361 , n6455 );
not ( n8362 , n8361 );
buf ( n8363 , n7446 );
not ( n8364 , n8363 );
or ( n8365 , n8362 , n8364 );
nand ( n8366 , n6131 , n6421 );
xor ( n8367 , n8366 , n415 );
not ( n8368 , n6218 );
nand ( n8369 , n6116 , n7319 , n8368 );
nand ( n8370 , n8368 , n6397 );
not ( n8371 , n6413 );
nand ( n8372 , n8369 , n8370 , n8371 );
xnor ( n8373 , n8367 , n8372 );
buf ( n8374 , n8373 );
buf ( n8375 , n416 );
nand ( n8376 , n8374 , n8375 );
buf ( n8377 , n8376 );
buf ( n8378 , n8377 );
nand ( n8379 , n8365 , n8378 );
buf ( n8380 , n8379 );
buf ( n8381 , n8380 );
or ( n8382 , n8360 , n8381 );
xor ( n8383 , n6877 , n7011 );
and ( n8384 , n8383 , n7062 );
and ( n8385 , n6877 , n7011 );
or ( n8386 , n8384 , n8385 );
buf ( n8387 , n8386 );
buf ( n8388 , n8387 );
nand ( n8389 , n8382 , n8388 );
buf ( n8390 , n8389 );
buf ( n8391 , n8390 );
buf ( n8392 , n8380 );
buf ( n8393 , n8359 );
nand ( n8394 , n8392 , n8393 );
buf ( n8395 , n8394 );
buf ( n8396 , n8395 );
nand ( n8397 , n8391 , n8396 );
buf ( n8398 , n8397 );
buf ( n8399 , n8398 );
not ( n8400 , n8399 );
buf ( n8401 , n8400 );
not ( n8402 , n8401 );
or ( n8403 , n8357 , n8402 );
not ( n8404 , n8356 );
nand ( n8405 , n8398 , n8404 );
nand ( n8406 , n8403 , n8405 );
buf ( n8407 , n416 );
not ( n8408 , n8407 );
buf ( n8409 , n415 );
not ( n8410 , n8409 );
buf ( n8411 , n418 );
not ( n8412 , n8411 );
buf ( n8413 , n6398 );
buf ( n8414 , n6381 );
buf ( n8415 , n6421 );
not ( n8416 , n8415 );
buf ( n8417 , n6414 );
nor ( n8418 , n8416 , n8417 );
buf ( n8419 , n8418 );
buf ( n8420 , n8419 );
nand ( n8421 , n8413 , n8414 , n8420 );
buf ( n8422 , n8421 );
buf ( n8423 , n8422 );
not ( n8424 , n8423 );
or ( n8425 , n8412 , n8424 );
buf ( n8426 , n6398 );
buf ( n8427 , n6427 );
buf ( n8428 , n6381 );
nand ( n8429 , n8426 , n8427 , n8428 );
buf ( n8430 , n8429 );
buf ( n8431 , n8430 );
nand ( n8432 , n8425 , n8431 );
buf ( n8433 , n8432 );
buf ( n8434 , n8433 );
not ( n8435 , n8434 );
buf ( n8436 , n8435 );
buf ( n8437 , n8436 );
not ( n8438 , n8437 );
or ( n8439 , n8410 , n8438 );
buf ( n8440 , n8433 );
buf ( n8441 , n6467 );
nand ( n8442 , n8440 , n8441 );
buf ( n8443 , n8442 );
buf ( n8444 , n8443 );
nand ( n8445 , n8439 , n8444 );
buf ( n8446 , n8445 );
buf ( n8447 , n8446 );
not ( n8448 , n8447 );
or ( n8449 , n8408 , n8448 );
buf ( n8450 , n8373 );
buf ( n8451 , n6455 );
nand ( n8452 , n8450 , n8451 );
buf ( n8453 , n8452 );
buf ( n8454 , n8453 );
nand ( n8455 , n8449 , n8454 );
buf ( n8456 , n8455 );
not ( n8457 , n8271 );
not ( n8458 , n8279 );
not ( n8459 , n8458 );
or ( n8460 , n8457 , n8459 );
nand ( n8461 , n8460 , n8318 );
or ( n8462 , n8458 , n8271 );
nand ( n8463 , n8461 , n8462 );
not ( n8464 , n8298 );
not ( n8465 , n8312 );
or ( n8466 , n8464 , n8465 );
nand ( n8467 , n8466 , n8317 );
not ( n8468 , n8312 );
nand ( n8469 , n8468 , n8297 );
nand ( n8470 , n8467 , n8469 );
buf ( n8471 , n8311 );
buf ( n8472 , n8302 );
or ( n8473 , n8471 , n8472 );
buf ( n8474 , n8306 );
nand ( n8475 , n8473 , n8474 );
buf ( n8476 , n8475 );
buf ( n8477 , n8476 );
buf ( n8478 , n8302 );
buf ( n8479 , n8311 );
nand ( n8480 , n8478 , n8479 );
buf ( n8481 , n8480 );
buf ( n8482 , n8481 );
nand ( n8483 , n8477 , n8482 );
buf ( n8484 , n8483 );
buf ( n8485 , n8484 );
nand ( n8486 , n370 , n382 );
buf ( n8487 , n8486 );
not ( n8488 , n8487 );
and ( n8489 , n373 , n379 );
buf ( n8490 , n8489 );
not ( n8491 , n8490 );
or ( n8492 , n8488 , n8491 );
buf ( n8493 , n8486 );
buf ( n8494 , n8489 );
or ( n8495 , n8493 , n8494 );
nand ( n8496 , n8492 , n8495 );
buf ( n8497 , n8496 );
buf ( n8498 , n8497 );
nand ( n8499 , n371 , n381 );
buf ( n8500 , n8499 );
xor ( n8501 , n8498 , n8500 );
buf ( n8502 , n8501 );
buf ( n8503 , n8502 );
xor ( n8504 , n8485 , n8503 );
buf ( n8505 , n372 );
buf ( n8506 , n380 );
nand ( n8507 , n8505 , n8506 );
buf ( n8508 , n8507 );
buf ( n8509 , n374 );
buf ( n8510 , n378 );
nand ( n8511 , n8509 , n8510 );
buf ( n8512 , n8511 );
xor ( n8513 , n8508 , n8512 );
or ( n8514 , n8238 , n8241 );
nand ( n8515 , n8514 , n8240 );
nand ( n8516 , n8244 , n8241 );
nand ( n8517 , n8515 , n8516 );
xor ( n8518 , n8513 , n8517 );
buf ( n8519 , n8518 );
xor ( n8520 , n8504 , n8519 );
buf ( n8521 , n8520 );
not ( n8522 , n8521 );
or ( n8523 , n8251 , n8260 );
nand ( n8524 , n8523 , n6813 );
nand ( n8525 , n8524 , n8267 );
or ( n8526 , n8470 , n8522 , n8525 );
nand ( n8527 , n8522 , n8525 );
or ( n8528 , n8527 , n8470 );
nand ( n8529 , n8526 , n8528 );
not ( n8530 , n8529 );
not ( n8531 , n8525 );
nand ( n8532 , n8531 , n8522 );
not ( n8533 , n8532 );
and ( n8534 , n8533 , n8470 );
and ( n8535 , n8521 , n8525 );
and ( n8536 , n8535 , n8470 );
nor ( n8537 , n8534 , n8536 );
nand ( n8538 , n8530 , n8537 );
xor ( n8539 , n8463 , n8538 );
not ( n8540 , n8539 );
not ( n8541 , n8540 );
buf ( n8542 , n411 );
buf ( n8543 , n7250 );
xor ( n8544 , n8542 , n8543 );
buf ( n8545 , n8544 );
not ( n8546 , n8545 );
not ( n8547 , n8546 );
not ( n8548 , n5840 );
and ( n8549 , n8547 , n8548 );
not ( n8550 , n411 );
not ( n8551 , n7306 );
or ( n8552 , n8550 , n8551 );
nand ( n8553 , n7295 , n7195 );
nand ( n8554 , n8552 , n8553 );
and ( n8555 , n8554 , n7013 );
nor ( n8556 , n8549 , n8555 );
not ( n8557 , n8556 );
not ( n8558 , n8557 );
or ( n8559 , n8541 , n8558 );
nand ( n8560 , n8556 , n8539 );
nand ( n8561 , n8559 , n8560 );
xor ( n8562 , n8456 , n8561 );
buf ( n8563 , n5837 );
not ( n8564 , n8563 );
buf ( n8565 , n7038 );
not ( n8566 , n8565 );
or ( n8567 , n8564 , n8566 );
buf ( n8568 , n8545 );
buf ( n8569 , n7013 );
nand ( n8570 , n8568 , n8569 );
buf ( n8571 , n8570 );
buf ( n8572 , n8571 );
nand ( n8573 , n8567 , n8572 );
buf ( n8574 , n8573 );
not ( n8575 , n8574 );
xor ( n8576 , n6748 , n6828 );
and ( n8577 , n8576 , n6874 );
and ( n8578 , n6748 , n6828 );
or ( n8579 , n8577 , n8578 );
buf ( n8580 , n8579 );
not ( n8581 , n8580 );
nand ( n8582 , n8575 , n8581 );
not ( n8583 , n8582 );
not ( n8584 , n7260 );
not ( n8585 , n8222 );
or ( n8586 , n8584 , n8585 );
nand ( n8587 , n7370 , n6520 );
nand ( n8588 , n8586 , n8587 );
not ( n8589 , n8588 );
or ( n8590 , n8583 , n8589 );
nand ( n8591 , n8580 , n8574 );
nand ( n8592 , n8590 , n8591 );
xor ( n8593 , n8562 , n8592 );
not ( n8594 , n8593 );
and ( n8595 , n8406 , n8594 );
not ( n8596 , n8406 );
and ( n8597 , n8596 , n8593 );
nor ( n8598 , n8595 , n8597 );
not ( n8599 , n7377 );
not ( n8600 , n7451 );
or ( n8601 , n8599 , n8600 );
not ( n8602 , n7422 );
not ( n8603 , n7421 );
or ( n8604 , n8602 , n8603 );
or ( n8605 , n7451 , n7377 );
nand ( n8606 , n8604 , n8605 );
nand ( n8607 , n8601 , n8606 );
not ( n8608 , n8607 );
xor ( n8609 , n8581 , n8574 );
xnor ( n8610 , n8609 , n8588 );
buf ( n8611 , n8610 );
not ( n8612 , n8611 );
or ( n8613 , n8608 , n8612 );
or ( n8614 , n8611 , n8607 );
xor ( n8615 , n8359 , n8380 );
xor ( n8616 , n8615 , n8387 );
nand ( n8617 , n8614 , n8616 );
nand ( n8618 , n8613 , n8617 );
not ( n8619 , n8618 );
nand ( n8620 , n8598 , n8619 );
buf ( n8621 , n8620 );
not ( n8622 , n8621 );
xor ( n8623 , n8610 , n8607 );
xnor ( n8624 , n8623 , n8616 );
not ( n8625 , n8624 );
buf ( n8626 , n7361 );
not ( n8627 , n8626 );
buf ( n8628 , n7064 );
nor ( n8629 , n8627 , n8628 );
buf ( n8630 , n8629 );
buf ( n8631 , n8630 );
buf ( n8632 , n7454 );
or ( n8633 , n8631 , n8632 );
buf ( n8634 , n7361 );
not ( n8635 , n8634 );
buf ( n8636 , n7064 );
nand ( n8637 , n8635 , n8636 );
buf ( n8638 , n8637 );
buf ( n8639 , n8638 );
nand ( n8640 , n8633 , n8639 );
buf ( n8641 , n8640 );
nor ( n8642 , n8625 , n8641 );
buf ( n8643 , n8642 );
nor ( n8644 , n8622 , n8643 );
buf ( n8645 , n8644 );
buf ( n8646 , n8645 );
not ( n8647 , n5837 );
not ( n8648 , n8554 );
or ( n8649 , n8647 , n8648 );
xor ( n8650 , n7327 , n411 );
xnor ( n8651 , n8650 , n7326 );
nand ( n8652 , n7013 , n8651 );
nand ( n8653 , n8649 , n8652 );
buf ( n8654 , n8653 );
buf ( n8655 , n6455 );
not ( n8656 , n8655 );
buf ( n8657 , n8446 );
not ( n8658 , n8657 );
or ( n8659 , n8656 , n8658 );
buf ( n8660 , n6477 );
buf ( n8661 , n8660 );
nand ( n8662 , n8659 , n8661 );
buf ( n8663 , n8662 );
buf ( n8664 , n8663 );
xor ( n8665 , n8654 , n8664 );
buf ( n8666 , n7260 );
not ( n8667 , n8666 );
not ( n8668 , n8366 );
not ( n8669 , n6496 );
and ( n8670 , n8668 , n8669 );
not ( n8671 , n8668 );
not ( n8672 , n413 );
and ( n8673 , n8671 , n8672 );
or ( n8674 , n8670 , n8673 );
and ( n8675 , n8372 , n8674 );
not ( n8676 , n8372 );
not ( n8677 , n6496 );
and ( n8678 , n8366 , n8677 );
not ( n8679 , n8366 );
not ( n8680 , n413 );
and ( n8681 , n8679 , n8680 );
or ( n8682 , n8678 , n8681 );
and ( n8683 , n8676 , n8682 );
or ( n8684 , n8675 , n8683 );
buf ( n8685 , n8684 );
not ( n8686 , n8685 );
or ( n8687 , n8667 , n8686 );
nand ( n8688 , n8229 , n6520 );
buf ( n8689 , n8688 );
nand ( n8690 , n8687 , n8689 );
buf ( n8691 , n8690 );
buf ( n8692 , n8691 );
not ( n8693 , n8692 );
buf ( n8694 , n8693 );
buf ( n8695 , n8694 );
xnor ( n8696 , n8665 , n8695 );
buf ( n8697 , n8696 );
buf ( n8698 , n8697 );
xor ( n8699 , n8456 , n8561 );
and ( n8700 , n8699 , n8592 );
and ( n8701 , n8456 , n8561 );
or ( n8702 , n8700 , n8701 );
buf ( n8703 , n8702 );
xor ( n8704 , n8698 , n8703 );
buf ( n8705 , n6539 );
not ( n8706 , n8705 );
buf ( n8707 , n7031 );
not ( n8708 , n8707 );
or ( n8709 , n8706 , n8708 );
buf ( n8710 , n7617 );
not ( n8711 , n8710 );
buf ( n8712 , n8711 );
buf ( n8713 , n8712 );
buf ( n8714 , n6528 );
nand ( n8715 , n8713 , n8714 );
buf ( n8716 , n8715 );
buf ( n8717 , n8716 );
nand ( n8718 , n8709 , n8717 );
buf ( n8719 , n8718 );
xor ( n8720 , n8508 , n8512 );
and ( n8721 , n8720 , n8517 );
and ( n8722 , n8508 , n8512 );
or ( n8723 , n8721 , n8722 );
nand ( n8724 , n371 , n380 );
nand ( n8725 , n370 , n382 );
not ( n8726 , n8725 );
not ( n8727 , n8499 );
or ( n8728 , n8726 , n8727 );
or ( n8729 , n8499 , n8725 );
nand ( n8730 , n8729 , n6811 );
nand ( n8731 , n8728 , n8730 );
xor ( n8732 , n8724 , n8731 );
nand ( n8733 , n372 , n379 );
nand ( n8734 , n373 , n378 );
xor ( n8735 , n8733 , n8734 );
nand ( n8736 , n370 , n381 );
xor ( n8737 , n8735 , n8736 );
xor ( n8738 , n8732 , n8737 );
buf ( n8739 , n8738 );
not ( n8740 , n8739 );
buf ( n8741 , n8740 );
and ( n8742 , n8723 , n8741 );
not ( n8743 , n8723 );
and ( n8744 , n8743 , n8738 );
or ( n8745 , n8742 , n8744 );
buf ( n8746 , n8745 );
xor ( n8747 , n8485 , n8503 );
and ( n8748 , n8747 , n8519 );
and ( n8749 , n8485 , n8503 );
or ( n8750 , n8748 , n8749 );
buf ( n8751 , n8750 );
buf ( n8752 , n8751 );
xnor ( n8753 , n8746 , n8752 );
buf ( n8754 , n8753 );
not ( n8755 , n8470 );
not ( n8756 , n8532 );
or ( n8757 , n8755 , n8756 );
not ( n8758 , n8535 );
nand ( n8759 , n8757 , n8758 );
xnor ( n8760 , n8754 , n8759 );
xnor ( n8761 , n8719 , n8760 );
buf ( n8762 , n8761 );
or ( n8763 , n8463 , n8538 );
not ( n8764 , n8763 );
not ( n8765 , n8557 );
or ( n8766 , n8764 , n8765 );
nand ( n8767 , n8463 , n8538 );
nand ( n8768 , n8766 , n8767 );
buf ( n8769 , n8768 );
xor ( n8770 , n8762 , n8769 );
or ( n8771 , n8347 , n8231 );
nand ( n8772 , n8771 , n8338 );
buf ( n8773 , n8772 );
nand ( n8774 , n8347 , n8231 );
buf ( n8775 , n8774 );
nand ( n8776 , n8773 , n8775 );
buf ( n8777 , n8776 );
buf ( n8778 , n8777 );
xnor ( n8779 , n8770 , n8778 );
buf ( n8780 , n8779 );
buf ( n8781 , n8780 );
xnor ( n8782 , n8704 , n8781 );
buf ( n8783 , n8782 );
buf ( n8784 , n8783 );
not ( n8785 , n8404 );
not ( n8786 , n8594 );
or ( n8787 , n8785 , n8786 );
buf ( n8788 , n8398 );
buf ( n8789 , n8788 );
buf ( n8790 , n8789 );
nand ( n8791 , n8787 , n8790 );
buf ( n8792 , n8791 );
nand ( n8793 , n8593 , n8356 );
buf ( n8794 , n8793 );
nand ( n8795 , n8792 , n8794 );
buf ( n8796 , n8795 );
not ( n8797 , n8796 );
buf ( n8798 , n8797 );
nand ( n8799 , n8784 , n8798 );
buf ( n8800 , n8799 );
buf ( n8801 , n8800 );
and ( n8802 , n8646 , n8801 );
buf ( n8803 , n8802 );
not ( n8804 , n8803 );
or ( n8805 , n8213 , n8804 );
buf ( n8806 , n8598 );
not ( n8807 , n8806 );
buf ( n8808 , n8618 );
nand ( n8809 , n8807 , n8808 );
buf ( n8810 , n8809 );
buf ( n8811 , n8810 );
not ( n8812 , n8811 );
not ( n8813 , n8641 );
nor ( n8814 , n8624 , n8813 );
buf ( n8815 , n8814 );
buf ( n8816 , n8620 );
nand ( n8817 , n8815 , n8816 );
buf ( n8818 , n8817 );
buf ( n8819 , n8818 );
not ( n8820 , n8819 );
or ( n8821 , n8812 , n8820 );
buf ( n8822 , n8796 );
not ( n8823 , n8822 );
buf ( n8824 , n8783 );
nand ( n8825 , n8823 , n8824 );
buf ( n8826 , n8825 );
buf ( n8827 , n8826 );
nand ( n8828 , n8821 , n8827 );
buf ( n8829 , n8828 );
buf ( n8830 , n8829 );
not ( n8831 , n8783 );
buf ( n8832 , n8796 );
nand ( n8833 , n8831 , n8832 );
buf ( n8834 , n8833 );
nand ( n8835 , n8830 , n8834 );
buf ( n8836 , n8835 );
buf ( n8837 , n8836 );
not ( n8838 , n8837 );
buf ( n8839 , n8838 );
nand ( n8840 , n8805 , n8839 );
buf ( n8841 , n371 );
buf ( n8842 , n379 );
nand ( n8843 , n8841 , n8842 );
buf ( n8844 , n8843 );
buf ( n8845 , n370 );
buf ( n8846 , n380 );
nand ( n8847 , n8845 , n8846 );
buf ( n8848 , n8847 );
xor ( n8849 , n8844 , n8848 );
buf ( n8850 , n372 );
buf ( n8851 , n378 );
nand ( n8852 , n8850 , n8851 );
buf ( n8853 , n8852 );
xor ( n8854 , n8849 , n8853 );
xor ( n8855 , n8733 , n8734 );
and ( n8856 , n8855 , n8736 );
and ( n8857 , n8733 , n8734 );
or ( n8858 , n8856 , n8857 );
xor ( n8859 , n8724 , n8731 );
and ( n8860 , n8859 , n8737 );
and ( n8861 , n8724 , n8731 );
or ( n8862 , n8860 , n8861 );
xor ( n8863 , n8858 , n8862 );
xor ( n8864 , n8854 , n8863 );
not ( n8865 , n8864 );
not ( n8866 , n7298 );
nand ( n8867 , n8866 , n6528 );
not ( n8868 , n7617 );
nand ( n8869 , n8868 , n6539 );
nand ( n8870 , n8867 , n8869 );
not ( n8871 , n8870 );
or ( n8872 , n8865 , n8871 );
not ( n8873 , n8864 );
and ( n8874 , n8869 , n8873 );
not ( n8875 , n8874 );
not ( n8876 , n8867 );
or ( n8877 , n8875 , n8876 );
not ( n8878 , n8723 );
not ( n8879 , n8738 );
or ( n8880 , n8878 , n8879 );
buf ( n8881 , n8751 );
buf ( n8882 , n8723 );
not ( n8883 , n8882 );
buf ( n8884 , n8741 );
nand ( n8885 , n8883 , n8884 );
buf ( n8886 , n8885 );
buf ( n8887 , n8886 );
nand ( n8888 , n8881 , n8887 );
buf ( n8889 , n8888 );
nand ( n8890 , n8880 , n8889 );
nand ( n8891 , n8877 , n8890 );
nand ( n8892 , n8872 , n8891 );
buf ( n8893 , n8892 );
buf ( n8894 , n7013 );
not ( n8895 , n8894 );
xor ( n8896 , n8668 , n8372 );
xor ( n8897 , n8896 , n411 );
buf ( n8898 , n8897 );
not ( n8899 , n8898 );
or ( n8900 , n8895 , n8899 );
not ( n8901 , n411 );
buf ( n8902 , n7445 );
not ( n8903 , n8902 );
buf ( n8904 , n8903 );
not ( n8905 , n8904 );
or ( n8906 , n8901 , n8905 );
buf ( n8907 , n411 );
not ( n8908 , n8907 );
buf ( n8909 , n7445 );
nand ( n8910 , n8908 , n8909 );
buf ( n8911 , n8910 );
nand ( n8912 , n8906 , n8911 );
buf ( n8913 , n8912 );
buf ( n8914 , n5837 );
nand ( n8915 , n8913 , n8914 );
buf ( n8916 , n8915 );
buf ( n8917 , n8916 );
nand ( n8918 , n8900 , n8917 );
buf ( n8919 , n8918 );
buf ( n8920 , n8919 );
xor ( n8921 , n8893 , n8920 );
not ( n8922 , n7013 );
not ( n8923 , n8912 );
or ( n8924 , n8922 , n8923 );
nand ( n8925 , n8651 , n5837 );
nand ( n8926 , n8924 , n8925 );
not ( n8927 , n8926 );
not ( n8928 , n6478 );
and ( n8929 , n8433 , n6496 );
not ( n8930 , n8433 );
and ( n8931 , n8930 , n413 );
or ( n8932 , n8929 , n8931 );
nand ( n8933 , n8932 , n7260 );
buf ( n8934 , n8684 );
buf ( n8935 , n6520 );
nand ( n8936 , n8934 , n8935 );
buf ( n8937 , n8936 );
nand ( n8938 , n8928 , n8933 , n8937 );
not ( n8939 , n8938 );
or ( n8940 , n8927 , n8939 );
buf ( n8941 , n6574 );
nand ( n8942 , n8933 , n8937 );
buf ( n8943 , n8942 );
nand ( n8944 , n8941 , n8943 );
buf ( n8945 , n8944 );
nand ( n8946 , n8940 , n8945 );
buf ( n8947 , n8946 );
xor ( n8948 , n8921 , n8947 );
buf ( n8949 , n8948 );
not ( n8950 , n8890 );
not ( n8951 , n8864 );
and ( n8952 , n8950 , n8951 );
and ( n8953 , n8890 , n8864 );
nor ( n8954 , n8952 , n8953 );
not ( n8955 , n8954 );
not ( n8956 , n8870 );
or ( n8957 , n8955 , n8956 );
or ( n8958 , n8870 , n8954 );
nand ( n8959 , n8957 , n8958 );
buf ( n8960 , n8959 );
buf ( n8961 , n8754 );
not ( n8962 , n8961 );
buf ( n8963 , n8962 );
buf ( n8964 , n8963 );
not ( n8965 , n8964 );
buf ( n8966 , n8719 );
not ( n8967 , n8966 );
or ( n8968 , n8965 , n8967 );
buf ( n8969 , n8719 );
buf ( n8970 , n8963 );
or ( n8971 , n8969 , n8970 );
buf ( n8972 , n8759 );
nand ( n8973 , n8971 , n8972 );
buf ( n8974 , n8973 );
buf ( n8975 , n8974 );
nand ( n8976 , n8968 , n8975 );
buf ( n8977 , n8976 );
buf ( n8978 , n8977 );
not ( n8979 , n8978 );
buf ( n8980 , n8979 );
buf ( n8981 , n8980 );
xor ( n8982 , n8960 , n8981 );
not ( n8983 , n8694 );
buf ( n8984 , n8663 );
not ( n8985 , n8984 );
buf ( n8986 , n8985 );
not ( n8987 , n8986 );
and ( n8988 , n8983 , n8987 );
buf ( n8989 , n8694 );
buf ( n8990 , n8986 );
nand ( n8991 , n8989 , n8990 );
buf ( n8992 , n8991 );
and ( n8993 , n8992 , n8653 );
nor ( n8994 , n8988 , n8993 );
buf ( n8995 , n8994 );
and ( n8996 , n8982 , n8995 );
and ( n8997 , n8960 , n8981 );
or ( n8998 , n8996 , n8997 );
buf ( n8999 , n8998 );
xor ( n9000 , n8949 , n8999 );
buf ( n9001 , n7298 );
not ( n9002 , n9001 );
buf ( n9003 , n6539 );
not ( n9004 , n9003 );
buf ( n9005 , n9004 );
buf ( n9006 , n9005 );
not ( n9007 , n9006 );
and ( n9008 , n9002 , n9007 );
buf ( n9009 , n7335 );
not ( n9010 , n9009 );
buf ( n9011 , n9010 );
buf ( n9012 , n9011 );
buf ( n9013 , n6528 );
and ( n9014 , n9012 , n9013 );
nor ( n9015 , n9008 , n9014 );
buf ( n9016 , n9015 );
buf ( n9017 , n9016 );
buf ( n9018 , n6520 );
not ( n9019 , n9018 );
buf ( n9020 , n8932 );
not ( n9021 , n9020 );
or ( n9022 , n9019 , n9021 );
nand ( n9023 , n6500 , n7260 );
buf ( n9024 , n9023 );
nand ( n9025 , n9022 , n9024 );
buf ( n9026 , n9025 );
buf ( n9027 , n9026 );
not ( n9028 , n9027 );
buf ( n9029 , n9028 );
buf ( n9030 , n9029 );
xor ( n9031 , n9017 , n9030 );
buf ( n9032 , n371 );
buf ( n9033 , n378 );
nand ( n9034 , n9032 , n9033 );
buf ( n9035 , n9034 );
buf ( n9036 , n370 );
buf ( n9037 , n379 );
nand ( n9038 , n9036 , n9037 );
buf ( n9039 , n9038 );
xor ( n9040 , n9035 , n9039 );
xor ( n9041 , n8844 , n8848 );
and ( n9042 , n9041 , n8853 );
and ( n9043 , n8844 , n8848 );
or ( n9044 , n9042 , n9043 );
xor ( n9045 , n9040 , n9044 );
xor ( n9046 , n8844 , n8848 );
xor ( n9047 , n9046 , n8853 );
and ( n9048 , n8858 , n9047 );
xor ( n9049 , n8844 , n8848 );
xor ( n9050 , n9049 , n8853 );
and ( n9051 , n8862 , n9050 );
and ( n9052 , n8858 , n8862 );
or ( n9053 , n9048 , n9051 , n9052 );
xor ( n9054 , n9053 , n6484 );
xor ( n9055 , n9045 , n9054 );
buf ( n9056 , n9055 );
xnor ( n9057 , n9031 , n9056 );
buf ( n9058 , n9057 );
buf ( n9059 , n9058 );
not ( n9060 , n9059 );
buf ( n9061 , n9060 );
and ( n9062 , n9000 , n9061 );
not ( n9063 , n9000 );
and ( n9064 , n9063 , n9058 );
nor ( n9065 , n9062 , n9064 );
buf ( n9066 , n9065 );
xor ( n9067 , n8960 , n8981 );
xor ( n9068 , n9067 , n8995 );
buf ( n9069 , n9068 );
not ( n9070 , n9069 );
xor ( n9071 , n8926 , n8942 );
not ( n9072 , n6574 );
and ( n9073 , n9071 , n9072 );
not ( n9074 , n9071 );
and ( n9075 , n9074 , n6574 );
nor ( n9076 , n9073 , n9075 );
not ( n9077 , n9076 );
and ( n9078 , n9070 , n9077 );
nand ( n9079 , n9069 , n9076 );
not ( n9080 , n8768 );
nand ( n9081 , n9080 , n8761 );
not ( n9082 , n9081 );
not ( n9083 , n8777 );
or ( n9084 , n9082 , n9083 );
buf ( n9085 , n8761 );
not ( n9086 , n9085 );
buf ( n9087 , n8768 );
nand ( n9088 , n9086 , n9087 );
buf ( n9089 , n9088 );
nand ( n9090 , n9084 , n9089 );
and ( n9091 , n9079 , n9090 );
nor ( n9092 , n9078 , n9091 );
buf ( n9093 , n9092 );
nand ( n9094 , n9066 , n9093 );
buf ( n9095 , n9094 );
buf ( n9096 , n9095 );
not ( n9097 , n9076 );
not ( n9098 , n9097 );
not ( n9099 , n9090 );
not ( n9100 , n9099 );
or ( n9101 , n9098 , n9100 );
nand ( n9102 , n9076 , n9090 );
nand ( n9103 , n9101 , n9102 );
not ( n9104 , n9069 );
and ( n9105 , n9103 , n9104 );
not ( n9106 , n9103 );
and ( n9107 , n9106 , n9069 );
nor ( n9108 , n9105 , n9107 );
buf ( n9109 , n9108 );
not ( n9110 , n9109 );
buf ( n9111 , n9110 );
buf ( n9112 , n9111 );
buf ( n9113 , n8697 );
not ( n9114 , n9113 );
buf ( n9115 , n9114 );
buf ( n9116 , n9115 );
not ( n9117 , n9116 );
buf ( n9118 , n8780 );
not ( n9119 , n9118 );
buf ( n9120 , n9119 );
buf ( n9121 , n9120 );
not ( n9122 , n9121 );
or ( n9123 , n9117 , n9122 );
buf ( n9124 , n8702 );
nand ( n9125 , n9123 , n9124 );
buf ( n9126 , n9125 );
buf ( n9127 , n9126 );
buf ( n9128 , n9120 );
buf ( n9129 , n9115 );
or ( n9130 , n9128 , n9129 );
buf ( n9131 , n9130 );
buf ( n9132 , n9131 );
nand ( n9133 , n9127 , n9132 );
buf ( n9134 , n9133 );
buf ( n9135 , n9134 );
not ( n9136 , n9135 );
buf ( n9137 , n9136 );
buf ( n9138 , n9137 );
nand ( n9139 , n9112 , n9138 );
buf ( n9140 , n9139 );
buf ( n9141 , n9140 );
and ( n9142 , n9096 , n9141 );
buf ( n9143 , n9142 );
xor ( n9144 , n8893 , n8920 );
and ( n9145 , n9144 , n8947 );
and ( n9146 , n8893 , n8920 );
or ( n9147 , n9145 , n9146 );
buf ( n9148 , n9147 );
buf ( n9149 , n9029 );
buf ( n9150 , n9016 );
nand ( n9151 , n9149 , n9150 );
buf ( n9152 , n9151 );
buf ( n9153 , n9152 );
not ( n9154 , n9153 );
buf ( n9155 , n9055 );
not ( n9156 , n9155 );
or ( n9157 , n9154 , n9156 );
buf ( n9158 , n9016 );
not ( n9159 , n9158 );
buf ( n9160 , n9026 );
nand ( n9161 , n9159 , n9160 );
buf ( n9162 , n9161 );
buf ( n9163 , n9162 );
nand ( n9164 , n9157 , n9163 );
buf ( n9165 , n9164 );
buf ( n9166 , n9165 );
not ( n9167 , n9166 );
buf ( n9168 , n9167 );
xor ( n9169 , n9148 , n9168 );
xor ( n9170 , n9035 , n9039 );
xor ( n9171 , n9170 , n9044 );
and ( n9172 , n9053 , n9171 );
xor ( n9173 , n9035 , n9039 );
xor ( n9174 , n9173 , n9044 );
and ( n9175 , n6484 , n9174 );
and ( n9176 , n9053 , n6484 );
or ( n9177 , n9172 , n9175 , n9176 );
xor ( n9178 , n6560 , n9177 );
buf ( n9179 , n370 );
buf ( n9180 , n378 );
nand ( n9181 , n9179 , n9180 );
buf ( n9182 , n9181 );
buf ( n9183 , n9182 );
xor ( n9184 , n9035 , n9039 );
and ( n9185 , n9184 , n9044 );
and ( n9186 , n9035 , n9039 );
or ( n9187 , n9185 , n9186 );
buf ( n9188 , n9187 );
xor ( n9189 , n9183 , n9188 );
buf ( n9190 , n6484 );
xor ( n9191 , n9189 , n9190 );
buf ( n9192 , n9191 );
xor ( n9193 , n9178 , n9192 );
buf ( n9194 , n6528 );
not ( n9195 , n9194 );
buf ( n9196 , n8904 );
not ( n9197 , n9196 );
buf ( n9198 , n9197 );
buf ( n9199 , n9198 );
not ( n9200 , n9199 );
or ( n9201 , n9195 , n9200 );
buf ( n9202 , n9011 );
buf ( n9203 , n6539 );
nand ( n9204 , n9202 , n9203 );
buf ( n9205 , n9204 );
buf ( n9206 , n9205 );
nand ( n9207 , n9201 , n9206 );
buf ( n9208 , n9207 );
buf ( n9209 , n9208 );
not ( n9210 , n9209 );
buf ( n9211 , n7013 );
not ( n9212 , n9211 );
and ( n9213 , n411 , n8436 );
not ( n9214 , n411 );
buf ( n9215 , n8436 );
not ( n9216 , n9215 );
buf ( n9217 , n9216 );
and ( n9218 , n9214 , n9217 );
or ( n9219 , n9213 , n9218 );
buf ( n9220 , n9219 );
not ( n9221 , n9220 );
or ( n9222 , n9212 , n9221 );
buf ( n9223 , n8897 );
buf ( n9224 , n5837 );
nand ( n9225 , n9223 , n9224 );
buf ( n9226 , n9225 );
buf ( n9227 , n9226 );
nand ( n9228 , n9222 , n9227 );
buf ( n9229 , n9228 );
buf ( n9230 , n9229 );
not ( n9231 , n9230 );
buf ( n9232 , n9231 );
buf ( n9233 , n9232 );
not ( n9234 , n9233 );
or ( n9235 , n9210 , n9234 );
buf ( n9236 , n9232 );
buf ( n9237 , n9208 );
or ( n9238 , n9236 , n9237 );
nand ( n9239 , n9235 , n9238 );
buf ( n9240 , n9239 );
xor ( n9241 , n9193 , n9240 );
xnor ( n9242 , n9169 , n9241 );
not ( n9243 , n9242 );
buf ( n9244 , n8949 );
not ( n9245 , n9244 );
buf ( n9246 , n9245 );
buf ( n9247 , n9246 );
not ( n9248 , n9247 );
buf ( n9249 , n9058 );
not ( n9250 , n9249 );
or ( n9251 , n9248 , n9250 );
buf ( n9252 , n8999 );
not ( n9253 , n9252 );
buf ( n9254 , n9253 );
buf ( n9255 , n9254 );
nand ( n9256 , n9251 , n9255 );
buf ( n9257 , n9256 );
buf ( n9258 , n9257 );
buf ( n9259 , n9246 );
not ( n9260 , n9259 );
buf ( n9261 , n9061 );
nand ( n9262 , n9260 , n9261 );
buf ( n9263 , n9262 );
buf ( n9264 , n9263 );
nand ( n9265 , n9258 , n9264 );
buf ( n9266 , n9265 );
buf ( n9267 , n9266 );
not ( n9268 , n9267 );
buf ( n9269 , n9268 );
nand ( n9270 , n9243 , n9269 );
xor ( n9271 , n6560 , n9177 );
and ( n9272 , n9271 , n9192 );
and ( n9273 , n6560 , n9177 );
or ( n9274 , n9272 , n9273 );
buf ( n9275 , n9208 );
not ( n9276 , n9275 );
buf ( n9277 , n9232 );
nand ( n9278 , n9276 , n9277 );
buf ( n9279 , n9278 );
not ( n9280 , n9279 );
not ( n9281 , n9193 );
or ( n9282 , n9280 , n9281 );
buf ( n9283 , n9229 );
buf ( n9284 , n9208 );
nand ( n9285 , n9283 , n9284 );
buf ( n9286 , n9285 );
nand ( n9287 , n9282 , n9286 );
xor ( n9288 , n9274 , n9287 );
buf ( n9289 , n6484 );
not ( n9290 , n9289 );
buf ( n9291 , n9290 );
xor ( n9292 , n6557 , n9291 );
buf ( n9293 , n9292 );
xor ( n9294 , n9183 , n9188 );
and ( n9295 , n9294 , n9190 );
and ( n9296 , n9183 , n9188 );
or ( n9297 , n9295 , n9296 );
buf ( n9298 , n9297 );
buf ( n9299 , n9298 );
xor ( n9300 , n9293 , n9299 );
buf ( n9301 , n9300 );
buf ( n9302 , n9301 );
not ( n9303 , n9302 );
buf ( n9304 , n9303 );
not ( n9305 , n9304 );
buf ( n9306 , n5837 );
not ( n9307 , n9306 );
buf ( n9308 , n9219 );
not ( n9309 , n9308 );
or ( n9310 , n9307 , n9309 );
nand ( n9311 , n6444 , n7013 );
buf ( n9312 , n9311 );
nand ( n9313 , n9310 , n9312 );
buf ( n9314 , n9313 );
buf ( n9315 , n9314 );
not ( n9316 , n9315 );
buf ( n9317 , n6539 );
not ( n9318 , n9317 );
buf ( n9319 , n9198 );
not ( n9320 , n9319 );
or ( n9321 , n9318 , n9320 );
buf ( n9322 , n8896 );
buf ( n9323 , n6528 );
nand ( n9324 , n9322 , n9323 );
buf ( n9325 , n9324 );
buf ( n9326 , n9325 );
nand ( n9327 , n9321 , n9326 );
buf ( n9328 , n9327 );
buf ( n9329 , n9328 );
not ( n9330 , n9329 );
buf ( n9331 , n9330 );
buf ( n9332 , n9331 );
not ( n9333 , n9332 );
and ( n9334 , n9316 , n9333 );
buf ( n9335 , n9314 );
buf ( n9336 , n9331 );
and ( n9337 , n9335 , n9336 );
nor ( n9338 , n9334 , n9337 );
buf ( n9339 , n9338 );
buf ( n9340 , n9339 );
not ( n9341 , n9340 );
buf ( n9342 , n9341 );
not ( n9343 , n9342 );
or ( n9344 , n9305 , n9343 );
buf ( n9345 , n9301 );
buf ( n9346 , n9339 );
nand ( n9347 , n9345 , n9346 );
buf ( n9348 , n9347 );
nand ( n9349 , n9344 , n9348 );
xor ( n9350 , n9288 , n9349 );
not ( n9351 , n9350 );
buf ( n9352 , n9148 );
not ( n9353 , n9352 );
buf ( n9354 , n9168 );
nand ( n9355 , n9353 , n9354 );
buf ( n9356 , n9355 );
not ( n9357 , n9356 );
not ( n9358 , n9241 );
or ( n9359 , n9357 , n9358 );
buf ( n9360 , n9148 );
buf ( n9361 , n9165 );
nand ( n9362 , n9360 , n9361 );
buf ( n9363 , n9362 );
nand ( n9364 , n9359 , n9363 );
not ( n9365 , n9364 );
nand ( n9366 , n9351 , n9365 );
and ( n9367 , n8840 , n9143 , n9270 , n9366 );
buf ( n9368 , n9314 );
not ( n9369 , n9368 );
buf ( n9370 , n9331 );
nand ( n9371 , n9369 , n9370 );
buf ( n9372 , n9371 );
not ( n9373 , n9372 );
not ( n9374 , n9301 );
or ( n9375 , n9373 , n9374 );
buf ( n9376 , n9331 );
not ( n9377 , n9376 );
buf ( n9378 , n9314 );
nand ( n9379 , n9377 , n9378 );
buf ( n9380 , n9379 );
nand ( n9381 , n9375 , n9380 );
not ( n9382 , n9381 );
not ( n9383 , n9382 );
not ( n9384 , n9383 );
not ( n9385 , n6445 );
and ( n9386 , n6557 , n9291 );
buf ( n9387 , n9386 );
not ( n9388 , n9387 );
buf ( n9389 , n6574 );
buf ( n9390 , n6560 );
nand ( n9391 , n9389 , n9390 );
buf ( n9392 , n9391 );
buf ( n9393 , n9392 );
nand ( n9394 , n9388 , n9393 );
buf ( n9395 , n9394 );
xor ( n9396 , n9385 , n9395 );
not ( n9397 , n9386 );
buf ( n9398 , n9397 );
not ( n9399 , n9398 );
buf ( n9400 , n9298 );
not ( n9401 , n9400 );
or ( n9402 , n9399 , n9401 );
buf ( n9403 , n9392 );
nand ( n9404 , n9402 , n9403 );
buf ( n9405 , n9404 );
xnor ( n9406 , n9396 , n9405 );
not ( n9407 , n9406 );
not ( n9408 , n9407 );
or ( n9409 , n9384 , n9408 );
not ( n9410 , n9382 );
not ( n9411 , n9406 );
or ( n9412 , n9410 , n9411 );
not ( n9413 , n6528 );
not ( n9414 , n9217 );
or ( n9415 , n9413 , n9414 );
buf ( n9416 , n8896 );
buf ( n9417 , n6539 );
nand ( n9418 , n9416 , n9417 );
buf ( n9419 , n9418 );
nand ( n9420 , n9415 , n9419 );
nand ( n9421 , n9412 , n9420 );
nand ( n9422 , n9409 , n9421 );
or ( n9423 , n9405 , n6581 );
nand ( n9424 , n9423 , n9395 );
buf ( n9425 , n9405 );
buf ( n9426 , n6581 );
nand ( n9427 , n9425 , n9426 );
buf ( n9428 , n9427 );
nand ( n9429 , n9424 , n9428 );
not ( n9430 , n9429 );
buf ( n9431 , n6539 );
not ( n9432 , n9431 );
buf ( n9433 , n9217 );
not ( n9434 , n9433 );
or ( n9435 , n9432 , n9434 );
buf ( n9436 , n6531 );
nand ( n9437 , n9435 , n9436 );
buf ( n9438 , n9437 );
not ( n9439 , n9438 );
not ( n9440 , n9439 );
buf ( n9441 , n9072 );
buf ( n9442 , n9397 );
nand ( n9443 , n9441 , n9442 );
buf ( n9444 , n9443 );
not ( n9445 , n6557 );
not ( n9446 , n6487 );
or ( n9447 , n9445 , n9446 );
buf ( n9448 , n6550 );
buf ( n9449 , n6445 );
nand ( n9450 , n9448 , n9449 );
buf ( n9451 , n9450 );
nand ( n9452 , n9447 , n9451 );
buf ( n9453 , n9452 );
not ( n9454 , n9453 );
buf ( n9455 , n9454 );
xor ( n9456 , n9444 , n9455 );
not ( n9457 , n9456 );
or ( n9458 , n9440 , n9457 );
or ( n9459 , n9456 , n9439 );
nand ( n9460 , n9458 , n9459 );
not ( n9461 , n9460 );
or ( n9462 , n9430 , n9461 );
or ( n9463 , n9429 , n9460 );
nand ( n9464 , n9462 , n9463 );
nor ( n9465 , n9422 , n9464 );
not ( n9466 , n9465 );
not ( n9467 , n9429 );
buf ( n9468 , n9438 );
not ( n9469 , n9468 );
buf ( n9470 , n9456 );
nand ( n9471 , n9469 , n9470 );
buf ( n9472 , n9471 );
not ( n9473 , n9472 );
or ( n9474 , n9467 , n9473 );
buf ( n9475 , n9456 );
not ( n9476 , n9475 );
buf ( n9477 , n9438 );
nand ( n9478 , n9476 , n9477 );
buf ( n9479 , n9478 );
nand ( n9480 , n9474 , n9479 );
buf ( n9481 , n9480 );
not ( n9482 , n9481 );
not ( n9483 , n9072 );
buf ( n9484 , n6550 );
not ( n9485 , n9484 );
buf ( n9486 , n6445 );
nand ( n9487 , n9485 , n9486 );
buf ( n9488 , n9487 );
not ( n9489 , n9488 );
or ( n9490 , n9483 , n9489 );
buf ( n9491 , n9488 );
not ( n9492 , n9491 );
buf ( n9493 , n9492 );
nand ( n9494 , n6574 , n9493 );
nand ( n9495 , n9490 , n9494 );
not ( n9496 , n9452 );
and ( n9497 , n9495 , n9496 );
not ( n9498 , n9495 );
and ( n9499 , n9498 , n9452 );
nor ( n9500 , n9497 , n9499 );
buf ( n9501 , n9500 );
not ( n9502 , n9501 );
buf ( n9503 , n6542 );
not ( n9504 , n9503 );
and ( n9505 , n9502 , n9504 );
buf ( n9506 , n9500 );
buf ( n9507 , n6542 );
and ( n9508 , n9506 , n9507 );
nor ( n9509 , n9505 , n9508 );
buf ( n9510 , n9509 );
buf ( n9511 , n9510 );
buf ( n9512 , n9072 );
buf ( n9513 , n9452 );
nand ( n9514 , n9512 , n9513 );
buf ( n9515 , n9514 );
buf ( n9516 , n9515 );
buf ( n9517 , n9397 );
nand ( n9518 , n9516 , n9517 );
buf ( n9519 , n9518 );
buf ( n9520 , n9519 );
and ( n9521 , n9511 , n9520 );
not ( n9522 , n9511 );
buf ( n9523 , n9519 );
not ( n9524 , n9523 );
buf ( n9525 , n9524 );
buf ( n9526 , n9525 );
and ( n9527 , n9522 , n9526 );
nor ( n9528 , n9521 , n9527 );
buf ( n9529 , n9528 );
buf ( n9530 , n9529 );
not ( n9531 , n9530 );
buf ( n9532 , n9531 );
buf ( n9533 , n9532 );
nand ( n9534 , n9482 , n9533 );
buf ( n9535 , n9534 );
nand ( n9536 , n9466 , n9535 );
buf ( n9537 , n9536 );
not ( n9538 , n9349 );
not ( n9539 , n9274 );
or ( n9540 , n9538 , n9539 );
nor ( n9541 , n9349 , n9274 );
not ( n9542 , n9287 );
or ( n9543 , n9541 , n9542 );
nand ( n9544 , n9540 , n9543 );
xor ( n9545 , n9420 , n9381 );
xnor ( n9546 , n9545 , n9406 );
nor ( n9547 , n9544 , n9546 );
buf ( n9548 , n9547 );
buf ( n9549 , n6542 );
not ( n9550 , n9549 );
buf ( n9551 , n9519 );
not ( n9552 , n9551 );
or ( n9553 , n9550 , n9552 );
buf ( n9554 , n9500 );
nand ( n9555 , n9553 , n9554 );
buf ( n9556 , n9555 );
buf ( n9557 , n9556 );
buf ( n9558 , n9525 );
not ( n9559 , n6542 );
buf ( n9560 , n9559 );
nand ( n9561 , n9558 , n9560 );
buf ( n9562 , n9561 );
buf ( n9563 , n9562 );
nand ( n9564 , n9557 , n9563 );
buf ( n9565 , n9564 );
buf ( n9566 , n6566 );
and ( n9567 , n6491 , n9493 );
not ( n9568 , n6491 );
and ( n9569 , n9568 , n9488 );
or ( n9570 , n9567 , n9569 );
buf ( n9571 , n9570 );
xor ( n9572 , n9566 , n9571 );
not ( n9573 , n9515 );
not ( n9574 , n9488 );
or ( n9575 , n9573 , n9574 );
buf ( n9576 , n9455 );
buf ( n9577 , n6574 );
nand ( n9578 , n9576 , n9577 );
buf ( n9579 , n9578 );
nand ( n9580 , n9575 , n9579 );
buf ( n9581 , n9580 );
xor ( n9582 , n9572 , n9581 );
buf ( n9583 , n9582 );
buf ( n9584 , C1 );
buf ( n9585 , C0 );
buf ( n9586 , n9585 );
nand ( n9587 , n9570 , n6565 );
buf ( n9588 , n9587 );
buf ( n9589 , n6566 );
not ( n9590 , n9589 );
buf ( n9591 , n9570 );
not ( n9592 , n9591 );
buf ( n9593 , n9592 );
buf ( n9594 , n9593 );
not ( n9595 , n9594 );
or ( n9596 , n9590 , n9595 );
buf ( n9597 , n9580 );
nand ( n9598 , n9596 , n9597 );
buf ( n9599 , n9598 );
buf ( n9600 , n9599 );
nand ( n9601 , n9588 , n9600 );
buf ( n9602 , n9601 );
buf ( n9603 , n6574 );
buf ( n9604 , n6581 );
nor ( n9605 , n9603 , n9604 );
buf ( n9606 , n9605 );
or ( n9607 , n9606 , n9493 );
not ( n9608 , n9607 );
not ( n9609 , n6599 );
or ( n9610 , n9608 , n9609 );
buf ( n9611 , n6599 );
or ( n9612 , n9611 , n9607 );
nand ( n9613 , n9610 , n9612 );
buf ( n9614 , n6567 );
nor ( n9615 , n9606 , n9493 );
buf ( n9616 , n9615 );
nand ( n9617 , n9614 , n9616 );
buf ( n9618 , n9617 );
nand ( n9619 , n9618 , n6588 );
buf ( n9620 , C0 );
buf ( n9621 , n9620 );
nor ( n9622 , n9537 , n9548 , n9586 , n9621 );
buf ( n9623 , n9622 );
nand ( n9624 , n9367 , n9623 );
nand ( n9625 , n9546 , n9544 );
nand ( n9626 , n9422 , n9464 );
buf ( n9627 , n9480 );
buf ( n9628 , n9529 );
nand ( n9629 , n9627 , n9628 );
buf ( n9630 , n9629 );
nand ( n9631 , n9625 , n9626 , n9630 );
buf ( n9632 , n6613 );
buf ( n9633 , n9619 );
nand ( n9634 , n9632 , n9633 );
buf ( n9635 , n9634 );
buf ( n9636 , C1 );
and ( n9637 , n9631 , n9636 , n9584 );
buf ( n9638 , n9637 );
buf ( n9639 , n9536 );
buf ( n9640 , n9630 );
nand ( n9641 , n9639 , n9640 );
buf ( n9642 , n9641 );
buf ( n9643 , n9642 );
and ( n9644 , n9638 , n9643 );
buf ( n9645 , n9602 );
not ( n9646 , n9645 );
buf ( n9647 , n9613 );
not ( n9648 , n9647 );
or ( n9649 , n9646 , n9648 );
buf ( n9650 , n9583 );
not ( n9651 , n9650 );
buf ( n9652 , n9565 );
nand ( n9653 , n9651 , n9652 );
buf ( n9654 , n9653 );
buf ( n9655 , n9654 );
nand ( n9656 , n9649 , n9655 );
buf ( n9657 , n9656 );
not ( n9658 , n9657 );
nand ( n9659 , n9658 , n9635 );
not ( n9660 , n9659 );
or ( n9661 , n9660 , C0 );
buf ( n9662 , n6613 );
buf ( n9663 , n6589 );
nand ( n9664 , n9662 , n9663 );
buf ( n9665 , n9664 );
nand ( n9666 , n9661 , n9665 );
buf ( n9667 , n9666 );
nor ( n9668 , n9644 , n9667 );
buf ( n9669 , n9668 );
buf ( n9670 , n9108 );
buf ( n9671 , n9134 );
nand ( n9672 , n9670 , n9671 );
buf ( n9673 , n9672 );
buf ( n9674 , n9673 );
not ( n9675 , n9674 );
buf ( n9676 , n9095 );
nand ( n9677 , n9675 , n9676 );
buf ( n9678 , n9677 );
buf ( n9679 , n9678 );
buf ( n9680 , n9065 );
not ( n9681 , n9680 );
buf ( n9682 , n9681 );
buf ( n9683 , n9682 );
buf ( n9684 , n9092 );
not ( n9685 , n9684 );
buf ( n9686 , n9685 );
buf ( n9687 , n9686 );
nand ( n9688 , n9683 , n9687 );
buf ( n9689 , n9688 );
buf ( n9690 , n9689 );
nand ( n9691 , n9679 , n9690 );
buf ( n9692 , n9691 );
not ( n9693 , n9692 );
not ( n9694 , n9270 );
or ( n9695 , n9693 , n9694 );
buf ( n9696 , n9350 );
buf ( n9697 , n9364 );
nand ( n9698 , n9696 , n9697 );
buf ( n9699 , n9698 );
buf ( n9700 , n9269 );
not ( n9701 , n9700 );
buf ( n9702 , n9242 );
nand ( n9703 , n9701 , n9702 );
buf ( n9704 , n9703 );
nand ( n9705 , n9699 , n9704 );
not ( n9706 , n9705 );
nand ( n9707 , n9695 , n9706 );
not ( n9708 , n9480 );
not ( n9709 , n9529 );
and ( n9710 , n9708 , n9709 );
nor ( n9711 , n9710 , n9585 );
and ( n9712 , n9711 , n9366 );
not ( n9713 , n9547 );
and ( n9714 , n9636 , n9713 , n9466 );
nand ( n9715 , n9707 , n9712 , n9714 );
nand ( n9716 , n9624 , n9669 , n9715 );
not ( n9717 , n9716 );
not ( n9718 , n9717 );
or ( n9719 , C0 , n9718 );
buf ( n9720 , n9665 );
not ( n9721 , n9720 );
or ( n9722 , C0 , n9721 );
not ( n9723 , n9669 );
buf ( n9724 , n9723 );
nand ( n9725 , n9722 , n9724 );
buf ( n9726 , n9725 );
nand ( n9727 , n9719 , n9726 );
buf ( n9728 , n9727 );
buf ( n9729 , n381 );
not ( n9730 , n9729 );
buf ( n9731 , n9730 );
not ( n9732 , n380 );
and ( n9733 , n9731 , n9732 );
and ( n9734 , n380 , n381 );
nor ( n9735 , n9733 , n9734 );
buf ( n9736 , n382 );
not ( n9737 , n9736 );
buf ( n9738 , n9737 );
and ( n9739 , n381 , n9738 );
not ( n9740 , n381 );
and ( n9741 , n9740 , n382 );
nor ( n9742 , n9739 , n9741 );
and ( n9743 , n9735 , n9742 );
buf ( n9744 , n9743 );
not ( n9745 , n9742 );
buf ( n9746 , n9745 );
nor ( n9747 , n9744 , n9746 );
buf ( n9748 , n9747 );
buf ( n9749 , n9748 );
buf ( n9750 , n9732 );
or ( n9751 , n9749 , n9750 );
buf ( n9752 , n9751 );
buf ( n9753 , n9752 );
not ( n9754 , n9753 );
buf ( n9755 , n9754 );
buf ( n9756 , n9755 );
and ( n9757 , n9728 , n9756 );
buf ( n9758 , n9757 );
buf ( n9759 , n9758 );
buf ( n9760 , n9759 );
buf ( n9761 , n9760 );
buf ( n9762 , n9761 );
not ( n9763 , n9762 );
buf ( n9764 , n9763 );
buf ( n9765 , n9764 );
not ( n9766 , n9717 );
or ( n9767 , C0 , n9766 );
nand ( n9768 , n9767 , n9726 );
buf ( n9769 , n9768 );
and ( n9770 , n379 , n9732 );
not ( n9771 , n379 );
and ( n9772 , n9771 , n380 );
or ( n9773 , n9770 , n9772 );
not ( n9774 , n9773 );
buf ( n9775 , n9774 );
not ( n9776 , n378 );
buf ( n9777 , n9776 );
buf ( n9778 , n379 );
not ( n9779 , n9778 );
buf ( n9780 , n9779 );
buf ( n9781 , n9780 );
and ( n9782 , n9777 , n9781 );
buf ( n9783 , n378 );
buf ( n9784 , n379 );
and ( n9785 , n9783 , n9784 );
nor ( n9786 , n9782 , n9785 );
buf ( n9787 , n9786 );
buf ( n9788 , n9787 );
and ( n9789 , n9775 , n9788 );
buf ( n9790 , n9789 );
buf ( n9791 , n9790 );
not ( n9792 , n9791 );
buf ( n9793 , n9792 );
buf ( n9794 , n9793 );
buf ( n9795 , n9774 );
nand ( n9796 , n9794 , n9795 );
buf ( n9797 , n9796 );
buf ( n9798 , n9797 );
buf ( n9799 , n378 );
and ( n9800 , n9798 , n9799 );
buf ( n9801 , n9800 );
buf ( n9802 , n9801 );
nand ( n9803 , n9769 , n9802 );
buf ( n9804 , n9803 );
buf ( n9805 , n9804 );
buf ( n9806 , n9755 );
buf ( n9807 , n9801 );
nand ( n9808 , n9806 , n9807 );
buf ( n9809 , n9808 );
buf ( n9810 , n9809 );
and ( n9811 , n9765 , n9805 , n9810 );
buf ( n9812 , n9811 );
buf ( n9813 , n9812 );
not ( n9814 , n9813 );
buf ( n9815 , n9717 );
not ( n9816 , n9815 );
or ( n9817 , C0 , n9816 );
buf ( n9818 , n9726 );
nand ( n9819 , n9817 , n9818 );
buf ( n9820 , n9819 );
or ( n9821 , n9820 , n9755 );
nand ( n9822 , n9727 , n9755 );
nand ( n9823 , n9821 , n9822 );
buf ( n9824 , n9823 );
buf ( n9825 , n384 );
buf ( n9826 , n9801 );
not ( n9827 , n9826 );
buf ( n9828 , n9827 );
buf ( n9829 , n9828 );
and ( n9830 , n9825 , n9829 );
not ( n9831 , n9825 );
buf ( n9832 , n9801 );
and ( n9833 , n9831 , n9832 );
nor ( n9834 , n9830 , n9833 );
buf ( n9835 , n9834 );
xor ( n9836 , n383 , n384 );
buf ( n9837 , n9836 );
not ( n9838 , n9837 );
buf ( n9839 , n9838 );
buf ( n9840 , n9839 );
not ( n9841 , n9840 );
buf ( n9842 , n9738 );
buf ( n9843 , n383 );
not ( n9844 , n9843 );
buf ( n9845 , n9844 );
buf ( n9846 , n9845 );
and ( n9847 , n9842 , n9846 );
buf ( n9848 , n382 );
buf ( n9849 , n383 );
and ( n9850 , n9848 , n9849 );
nor ( n9851 , n9847 , n9850 );
buf ( n9852 , n9851 );
and ( n9853 , n9839 , n9852 );
not ( n9854 , n9853 );
buf ( n9855 , n9854 );
not ( n9856 , n9855 );
or ( n9857 , n9841 , n9856 );
buf ( n9858 , n382 );
nand ( n9859 , n9857 , n9858 );
buf ( n9860 , n9859 );
buf ( n9861 , n9860 );
not ( n9862 , n9861 );
buf ( n9863 , n9862 );
and ( n9864 , n9835 , n9863 );
not ( n9865 , n9835 );
and ( n9866 , n9865 , n9860 );
or ( n9867 , n9864 , n9866 );
not ( n9868 , n9867 );
buf ( n9869 , n9868 );
nand ( n9870 , n9824 , n9869 );
buf ( n9871 , n9870 );
buf ( n9872 , n9871 );
nand ( n9873 , n9814 , n9872 );
buf ( n9874 , n9873 );
buf ( n9875 , n9874 );
buf ( n9876 , n9868 );
not ( n9877 , n9876 );
buf ( n9878 , n9823 );
not ( n9879 , n9878 );
buf ( n9880 , n9879 );
buf ( n9881 , n9880 );
nand ( n9882 , n9877 , n9881 );
buf ( n9883 , n9882 );
buf ( n9884 , n9883 );
nand ( n9885 , n9875 , n9884 );
buf ( n9886 , n9885 );
buf ( n9887 , n9880 );
not ( n9888 , n9887 );
buf ( n9889 , n9888 );
not ( n9890 , n9889 );
buf ( n9891 , n9758 );
not ( n9892 , n9891 );
buf ( n9893 , n9863 );
buf ( n9894 , n384 );
and ( n9895 , n9893 , n9894 );
buf ( n9896 , n9895 );
buf ( n9897 , n9896 );
not ( n9898 , n9897 );
buf ( n9899 , n9898 );
buf ( n9900 , n384 );
not ( n9901 , n9900 );
buf ( n9902 , n9860 );
nand ( n9903 , n9901 , n9902 );
buf ( n9904 , n9903 );
nand ( n9905 , n9904 , n9801 );
and ( n9906 , n9899 , n9905 );
buf ( n9907 , n9906 );
not ( n9908 , n9907 );
and ( n9909 , n9892 , n9908 );
buf ( n9910 , n9758 );
buf ( n9911 , n9906 );
and ( n9912 , n9910 , n9911 );
nor ( n9913 , n9909 , n9912 );
buf ( n9914 , n9913 );
buf ( n9915 , n9914 );
not ( n9916 , n9915 );
buf ( n9917 , n9916 );
not ( n9918 , n9917 );
or ( n9919 , n9890 , n9918 );
buf ( n9920 , n9914 );
buf ( n9921 , n9880 );
nand ( n9922 , n9920 , n9921 );
buf ( n9923 , n9922 );
nand ( n9924 , n9919 , n9923 );
not ( n9925 , n9867 );
or ( n9926 , n9924 , n9925 );
nand ( n9927 , n9924 , n9868 );
nand ( n9928 , n9926 , n9927 );
buf ( n9929 , n9928 );
not ( n9930 , n9929 );
buf ( n9931 , n9930 );
and ( n9932 , n9886 , n9931 );
not ( n9933 , n9886 );
and ( n9934 , n9933 , n9928 );
or ( n9935 , n9932 , n9934 );
buf ( n9936 , n9904 );
not ( n9937 , n9936 );
buf ( n9938 , n9761 );
not ( n9939 , n9938 );
or ( n9940 , n9937 , n9939 );
buf ( n9941 , n9899 );
nand ( n9942 , n9940 , n9941 );
buf ( n9943 , n9942 );
not ( n9944 , n9812 );
not ( n9945 , n9944 );
and ( n9946 , n9867 , n9889 );
not ( n9947 , n9867 );
and ( n9948 , n9947 , n9880 );
or ( n9949 , n9946 , n9948 );
not ( n9950 , n9949 );
not ( n9951 , n9950 );
or ( n9952 , n9945 , n9951 );
nand ( n9953 , n9949 , n9812 );
nand ( n9954 , n9952 , n9953 );
xor ( n9955 , n9943 , n9954 );
buf ( n9956 , n384 );
buf ( n9957 , n9860 );
and ( n9958 , n9956 , n9957 );
not ( n9959 , n9956 );
buf ( n9960 , n9863 );
and ( n9961 , n9959 , n9960 );
nor ( n9962 , n9958 , n9961 );
buf ( n9963 , n9962 );
not ( n9964 , n9963 );
not ( n9965 , n9764 );
or ( n9966 , n9964 , n9965 );
buf ( n9967 , n9963 );
not ( n9968 , n9967 );
buf ( n9969 , n9968 );
nand ( n9970 , n9969 , n9761 );
nand ( n9971 , n9966 , n9970 );
buf ( n9972 , n9971 );
not ( n9973 , n9972 );
not ( n9974 , n9801 );
not ( n9975 , n9823 );
or ( n9976 , n9974 , n9975 );
buf ( n9977 , n9880 );
buf ( n9978 , n9828 );
nand ( n9979 , n9977 , n9978 );
buf ( n9980 , n9979 );
nand ( n9981 , n9976 , n9980 );
buf ( n9982 , n9981 );
not ( n9983 , n9982 );
buf ( n9984 , n9983 );
buf ( n9985 , n9984 );
not ( n9986 , n9985 );
or ( n9987 , n9973 , n9986 );
not ( n9988 , n9906 );
buf ( n9989 , n9988 );
nand ( n9990 , n9987 , n9989 );
buf ( n9991 , n9990 );
buf ( n9992 , n9991 );
buf ( n9993 , n9971 );
not ( n9994 , n9993 );
buf ( n9995 , n9981 );
nand ( n9996 , n9994 , n9995 );
buf ( n9997 , n9996 );
buf ( n9998 , n9997 );
nand ( n9999 , n9992 , n9998 );
buf ( n10000 , n9999 );
and ( n10001 , n9955 , n10000 );
and ( n10002 , n9943 , n9954 );
or ( n10003 , n10001 , n10002 );
buf ( n10004 , C0 );
nor ( n10005 , n9935 , n10003 );
buf ( n10006 , n10005 );
nor ( n10007 , n10004 , n10006 );
buf ( n10008 , n10007 );
buf ( n10009 , n10008 );
not ( n10010 , n10009 );
buf ( n10011 , n10010 );
buf ( n10012 , n10011 );
buf ( n10013 , n10008 );
xor ( n10014 , n9943 , n9954 );
xor ( n10015 , n10014 , n10000 );
not ( n10016 , n9871 );
not ( n10017 , n9896 );
or ( n10018 , n10016 , n10017 );
nand ( n10019 , n10018 , n9883 );
buf ( n10020 , n10019 );
not ( n10021 , n10020 );
buf ( n10022 , n10021 );
buf ( n10023 , n10022 );
not ( n10024 , n10023 );
xor ( n10025 , n9906 , n9981 );
xnor ( n10026 , n10025 , n9971 );
buf ( n10027 , n10026 );
not ( n10028 , n10027 );
or ( n10029 , n10024 , n10028 );
buf ( n10030 , n9969 );
buf ( n10031 , n9896 );
nor ( n10032 , n10030 , n10031 );
buf ( n10033 , n10032 );
buf ( n10034 , n10033 );
buf ( n10035 , n9752 );
or ( n10036 , n10034 , n10035 );
buf ( n10037 , n10036 );
buf ( n10038 , n10037 );
buf ( n10039 , n9969 );
not ( n10040 , n10039 );
buf ( n10041 , n9896 );
buf ( n10042 , n9752 );
and ( n10043 , n10041 , n10042 );
buf ( n10044 , n9899 );
buf ( n10045 , n9755 );
and ( n10046 , n10044 , n10045 );
nor ( n10047 , n10043 , n10046 );
buf ( n10048 , n10047 );
buf ( n10049 , n10048 );
not ( n10050 , n10049 );
or ( n10051 , n10040 , n10050 );
buf ( n10052 , n10048 );
buf ( n10053 , n9969 );
or ( n10054 , n10052 , n10053 );
nand ( n10055 , n10051 , n10054 );
buf ( n10056 , n10055 );
buf ( n10057 , n10056 );
not ( n10058 , n10057 );
buf ( n10059 , n10037 );
nand ( n10060 , n10058 , n10059 );
buf ( n10061 , n10060 );
nand ( n10062 , n10061 , n9768 );
buf ( n10063 , n10062 );
xor ( n10064 , n10038 , n10063 );
buf ( n10065 , n9896 );
buf ( n10066 , n9867 );
xor ( n10067 , n10065 , n10066 );
buf ( n10068 , n9880 );
xnor ( n10069 , n10067 , n10068 );
buf ( n10070 , n10069 );
buf ( n10071 , n10070 );
and ( n10072 , n10064 , n10071 );
and ( n10073 , n10038 , n10063 );
or ( n10074 , n10072 , n10073 );
buf ( n10075 , n10074 );
buf ( n10076 , n10075 );
not ( n10077 , n10076 );
buf ( n10078 , n10077 );
buf ( n10079 , n10078 );
nand ( n10080 , n10029 , n10079 );
buf ( n10081 , n10080 );
buf ( n10082 , n10081 );
buf ( n10083 , n10026 );
not ( n10084 , n10083 );
buf ( n10085 , n10019 );
nand ( n10086 , n10084 , n10085 );
buf ( n10087 , n10086 );
buf ( n10088 , n10087 );
nand ( n10089 , n10082 , n10088 );
buf ( n10090 , n10089 );
or ( n10091 , n10015 , n10090 );
not ( n10092 , n5695 );
not ( n10093 , n5689 );
not ( n10094 , n10093 );
not ( n10095 , n5669 );
or ( n10096 , n10094 , n10095 );
buf ( n10097 , n5613 );
and ( n10098 , n5688 , n10097 , n5586 );
nor ( n10099 , n10098 , n5814 );
buf ( n10100 , n10099 );
nand ( n10101 , n10096 , n10100 );
not ( n10102 , n10101 );
or ( n10103 , n10092 , n10102 );
not ( n10104 , n5031 );
not ( n10105 , n5172 );
or ( n10106 , n10104 , n10105 );
nand ( n10107 , n10106 , n5720 );
not ( n10108 , n10107 );
buf ( n10109 , n10108 );
not ( n10110 , n5723 );
not ( n10111 , n4646 );
not ( n10112 , n10111 );
or ( n10113 , n10110 , n10112 );
or ( n10114 , n5026 , n4868 );
nand ( n10115 , n10113 , n10114 );
not ( n10116 , n10115 );
not ( n10117 , n4646 );
not ( n10118 , n4863 );
or ( n10119 , n10117 , n10118 );
nand ( n10120 , n10119 , n5726 );
not ( n10121 , n10120 );
buf ( n10122 , n4438 );
not ( n10123 , n10122 );
buf ( n10124 , n10123 );
not ( n10125 , n10124 );
not ( n10126 , n4641 );
not ( n10127 , n10126 );
or ( n10128 , n10125 , n10127 );
nor ( n10129 , n4433 , n4230 );
and ( n10130 , n3999 , n3784 );
nor ( n10131 , n10130 , n4004 );
or ( n10132 , n3999 , n3784 );
not ( n10133 , n3596 );
not ( n10134 , n3422 );
and ( n10135 , n10133 , n10134 );
not ( n10136 , n3601 );
nor ( n10137 , n10135 , n10136 );
and ( n10138 , n5797 , n10137 );
nor ( n10139 , n10138 , n3779 );
nor ( n10140 , n10139 , n5807 );
nand ( n10141 , n10132 , n10140 );
nand ( n10142 , n10131 , n10141 );
and ( n10143 , n10142 , n4225 );
nand ( n10144 , n3999 , n3784 );
and ( n10145 , n10141 , n10144 );
not ( n10146 , n4004 );
nor ( n10147 , n10145 , n10146 );
nor ( n10148 , n10143 , n10147 );
or ( n10149 , n10129 , n10148 );
buf ( n10150 , n4433 );
buf ( n10151 , n4230 );
nand ( n10152 , n10150 , n10151 );
buf ( n10153 , n10152 );
nand ( n10154 , n10149 , n10153 );
nand ( n10155 , n10128 , n10154 );
nand ( n10156 , n10121 , n10155 );
nand ( n10157 , n10116 , n10156 );
buf ( n10158 , n10157 );
and ( n10159 , n10109 , n10158 );
not ( n10160 , n5288 );
not ( n10161 , n5177 );
and ( n10162 , n10160 , n10161 );
nor ( n10163 , n5031 , n5172 );
nor ( n10164 , n10162 , n10163 );
not ( n10165 , n10164 );
nor ( n10166 , n10159 , n10165 );
nor ( n10167 , n10166 , n5716 );
not ( n10168 , n10167 );
and ( n10169 , n5700 , n10168 );
nor ( n10170 , n10169 , n5821 );
nand ( n10171 , n10103 , n10170 );
not ( n10172 , n10171 );
not ( n10173 , n10172 );
buf ( n10174 , n10173 );
buf ( n10175 , n378 );
nand ( n10176 , n10174 , n10175 );
buf ( n10177 , n10176 );
buf ( n10178 , n10177 );
not ( n10179 , n10178 );
xor ( n10180 , n10038 , n10063 );
xor ( n10181 , n10180 , n10071 );
buf ( n10182 , n10181 );
buf ( n10183 , n10182 );
not ( n10184 , n10183 );
or ( n10185 , n10179 , n10184 );
buf ( n10186 , n9790 );
not ( n10187 , n10186 );
buf ( n10188 , n378 );
not ( n10189 , n10188 );
nand ( n10190 , n5694 , n5817 );
not ( n10191 , n10190 );
not ( n10192 , n10101 );
or ( n10193 , n10191 , n10192 );
nand ( n10194 , n10193 , n10170 );
not ( n10195 , n10194 );
buf ( n10196 , n10195 );
not ( n10197 , n10196 );
or ( n10198 , n10189 , n10197 );
buf ( n10199 , n10173 );
buf ( n10200 , n9776 );
nand ( n10201 , n10199 , n10200 );
buf ( n10202 , n10201 );
buf ( n10203 , n10202 );
nand ( n10204 , n10198 , n10203 );
buf ( n10205 , n10204 );
buf ( n10206 , n10205 );
not ( n10207 , n10206 );
or ( n10208 , n10187 , n10207 );
buf ( n10209 , n9773 );
buf ( n10210 , n378 );
nand ( n10211 , n10209 , n10210 );
buf ( n10212 , n10211 );
buf ( n10213 , n10212 );
nand ( n10214 , n10208 , n10213 );
buf ( n10215 , n10214 );
buf ( n10216 , n10215 );
not ( n10217 , n10093 );
nor ( n10218 , n5532 , n5476 );
not ( n10219 , n10218 );
not ( n10220 , n5471 );
nand ( n10221 , n10220 , n5636 );
nand ( n10222 , n10219 , n10221 , n5653 );
buf ( n10223 , n5679 );
not ( n10224 , n10223 );
buf ( n10225 , n10224 );
nor ( n10226 , n10222 , n10225 );
not ( n10227 , n10226 );
not ( n10228 , n10108 );
not ( n10229 , n10115 );
nand ( n10230 , n10229 , n10156 );
not ( n10231 , n10230 );
or ( n10232 , n10228 , n10231 );
nand ( n10233 , n10232 , n10164 );
buf ( n10234 , n5713 );
nand ( n10235 , n10233 , n10234 );
not ( n10236 , n10235 );
or ( n10237 , n10227 , n10236 );
nand ( n10238 , n10237 , n5666 );
not ( n10239 , n10238 );
or ( n10240 , n10217 , n10239 );
nand ( n10241 , n10240 , n10100 );
not ( n10242 , n5821 );
nand ( n10243 , n10242 , n5695 );
not ( n10244 , n10243 );
and ( n10245 , n10241 , n10244 );
not ( n10246 , n10241 );
and ( n10247 , n10246 , n10243 );
nor ( n10248 , n10245 , n10247 );
not ( n10249 , n10248 );
buf ( n10250 , n10249 );
not ( n10251 , n10250 );
buf ( n10252 , n378 );
nand ( n10253 , n10251 , n10252 );
buf ( n10254 , n10253 );
buf ( n10255 , n10254 );
not ( n10256 , n10255 );
buf ( n10257 , n10256 );
buf ( n10258 , n10257 );
or ( n10259 , n10216 , n10258 );
buf ( n10260 , n10061 );
buf ( n10261 , n9768 );
and ( n10262 , n10260 , n10261 );
not ( n10263 , n10260 );
not ( n10264 , n9717 );
or ( n10265 , C0 , n10264 );
nand ( n10266 , n10265 , n9726 );
not ( n10267 , n10266 );
buf ( n10268 , n10267 );
and ( n10269 , n10263 , n10268 );
nor ( n10270 , n10262 , n10269 );
buf ( n10271 , n10270 );
buf ( n10272 , n10271 );
nand ( n10273 , n10259 , n10272 );
buf ( n10274 , n10273 );
buf ( n10275 , n10274 );
buf ( n10276 , n10215 );
buf ( n10277 , n10257 );
nand ( n10278 , n10276 , n10277 );
buf ( n10279 , n10278 );
buf ( n10280 , n10279 );
nand ( n10281 , n10275 , n10280 );
buf ( n10282 , n10281 );
buf ( n10283 , n10282 );
nand ( n10284 , n10185 , n10283 );
buf ( n10285 , n10284 );
buf ( n10286 , n10177 );
not ( n10287 , n10286 );
buf ( n10288 , n10182 );
not ( n10289 , n10288 );
buf ( n10290 , n10289 );
buf ( n10291 , n10290 );
nand ( n10292 , n10287 , n10291 );
buf ( n10293 , n10292 );
nand ( n10294 , n10285 , n10293 );
not ( n10295 , n10294 );
not ( n10296 , n10022 );
not ( n10297 , n10078 );
or ( n10298 , n10296 , n10297 );
nand ( n10299 , n10075 , n10019 );
nand ( n10300 , n10298 , n10299 );
not ( n10301 , n10300 );
and ( n10302 , n10301 , n10026 );
nor ( n10303 , C0 , n10302 );
not ( n10304 , n10303 );
nand ( n10305 , n10295 , n10304 );
buf ( n10306 , n10305 );
and ( n10307 , n10091 , n10306 );
not ( n10308 , n10307 );
buf ( n10309 , n9969 );
buf ( n10310 , n378 );
buf ( n10311 , n5476 );
not ( n10312 , n10311 );
buf ( n10313 , n5532 );
buf ( n10314 , n10313 );
buf ( n10315 , n10314 );
not ( n10316 , n10315 );
and ( n10317 , n10312 , n10316 );
not ( n10318 , n10233 );
nand ( n10319 , n10318 , n5681 );
not ( n10320 , n5471 );
not ( n10321 , n5390 );
and ( n10322 , n10320 , n10321 );
buf ( n10323 , n5288 );
buf ( n10324 , n5177 );
nand ( n10325 , n10323 , n10324 );
buf ( n10326 , n10325 );
nor ( n10327 , n10322 , n10326 );
not ( n10328 , n10327 );
not ( n10329 , n5679 );
or ( n10330 , n10328 , n10329 );
nand ( n10331 , n10330 , n5646 );
nor ( n10332 , n10331 , n5660 );
and ( n10333 , n10319 , n10332 );
nor ( n10334 , n10317 , n10333 );
nand ( n10335 , n5664 , n5657 );
and ( n10336 , n10334 , n10335 );
not ( n10337 , n10334 );
not ( n10338 , n10335 );
and ( n10339 , n10337 , n10338 );
nor ( n10340 , n10336 , n10339 );
not ( n10341 , n10340 );
buf ( n10342 , n10341 );
and ( n10343 , n10310 , n10342 );
buf ( n10344 , n10343 );
buf ( n10345 , n10344 );
xor ( n10346 , n10309 , n10345 );
not ( n10347 , n9713 );
buf ( n10348 , n9367 );
not ( n10349 , n10348 );
buf ( n10350 , n10349 );
buf ( n10351 , n10350 );
not ( n10352 , n10351 );
buf ( n10353 , n10352 );
buf ( n10354 , n9692 );
buf ( n10355 , n9366 );
buf ( n10356 , n9270 );
and ( n10357 , n10354 , n10355 , n10356 );
buf ( n10358 , n10357 );
buf ( n10359 , n10358 );
not ( n10360 , n10359 );
buf ( n10361 , n9705 );
buf ( n10362 , n9366 );
nand ( n10363 , n10361 , n10362 );
buf ( n10364 , n10363 );
buf ( n10365 , n10364 );
nand ( n10366 , n10360 , n10365 );
buf ( n10367 , n10366 );
or ( n10368 , n10353 , n10367 );
not ( n10369 , n10368 );
or ( n10370 , n10347 , n10369 );
nand ( n10371 , n10370 , n9625 );
buf ( n10372 , n10371 );
buf ( n10373 , n9466 );
buf ( n10374 , n9626 );
nand ( n10375 , n10373 , n10374 );
buf ( n10376 , n10375 );
buf ( n10377 , n10376 );
not ( n10378 , n10377 );
buf ( n10379 , n10378 );
buf ( n10380 , n10379 );
and ( n10381 , n10372 , n10380 );
not ( n10382 , n10372 );
buf ( n10383 , n10376 );
and ( n10384 , n10382 , n10383 );
nor ( n10385 , n10381 , n10384 );
buf ( n10386 , n10385 );
buf ( n10387 , n10386 );
and ( n10388 , n10346 , n10387 );
and ( n10389 , n10309 , n10345 );
or ( n10390 , n10388 , n10389 );
buf ( n10391 , n10390 );
not ( n10392 , n9743 );
not ( n10393 , n380 );
not ( n10394 , n10195 );
or ( n10395 , n10393 , n10394 );
or ( n10396 , n10195 , n380 );
nand ( n10397 , n10395 , n10396 );
not ( n10398 , n10397 );
or ( n10399 , n10392 , n10398 );
nand ( n10400 , n9745 , n380 );
nand ( n10401 , n10399 , n10400 );
not ( n10402 , n10401 );
xor ( n10403 , n10391 , n10402 );
not ( n10404 , n9625 );
nor ( n10405 , n9547 , n10404 );
not ( n10406 , n10405 );
not ( n10407 , n10406 );
not ( n10408 , n10368 );
or ( n10409 , n10407 , n10408 );
not ( n10410 , n10353 );
not ( n10411 , n10367 );
nand ( n10412 , n10410 , n10411 , n10405 );
nand ( n10413 , n10409 , n10412 );
and ( n10414 , n384 , n10413 );
not ( n10415 , n10414 );
buf ( n10416 , n9743 );
not ( n10417 , n10416 );
not ( n10418 , n10241 );
not ( n10419 , n9732 );
nor ( n10420 , n10419 , n10243 );
nand ( n10421 , n10418 , n10420 );
and ( n10422 , n10243 , n380 );
nand ( n10423 , n10418 , n10422 );
and ( n10424 , n10243 , n9732 );
nand ( n10425 , n10424 , n10241 );
not ( n10426 , n380 );
nor ( n10427 , n10426 , n10243 );
nand ( n10428 , n10427 , n10241 );
nand ( n10429 , n10421 , n10423 , n10425 , n10428 );
buf ( n10430 , n10429 );
not ( n10431 , n10430 );
or ( n10432 , n10417 , n10431 );
nand ( n10433 , n10397 , n9745 );
buf ( n10434 , n10433 );
nand ( n10435 , n10432 , n10434 );
buf ( n10436 , n10435 );
not ( n10437 , n10436 );
or ( n10438 , n10415 , n10437 );
buf ( n10439 , n10436 );
buf ( n10440 , n10414 );
or ( n10441 , n10439 , n10440 );
buf ( n10442 , n9773 );
not ( n10443 , n10442 );
buf ( n10444 , n378 );
and ( n10445 , n5811 , n5688 );
not ( n10446 , n10445 );
or ( n10447 , n5827 , n10167 );
not ( n10448 , n5822 );
not ( n10449 , n5647 );
not ( n10450 , n10449 );
and ( n10451 , n10448 , n10450 );
not ( n10452 , n5586 );
not ( n10453 , n5613 );
or ( n10454 , n10452 , n10453 );
nand ( n10455 , n5665 , n5684 );
nand ( n10456 , n10454 , n10455 );
nor ( n10457 , n10451 , n10456 );
nand ( n10458 , n10447 , n10457 );
not ( n10459 , n10458 );
or ( n10460 , n10446 , n10459 );
or ( n10461 , n5827 , n10167 );
not ( n10462 , n10445 );
nand ( n10463 , n10461 , n10457 , n10462 );
nand ( n10464 , n10460 , n10463 );
not ( n10465 , n10464 );
buf ( n10466 , n10465 );
not ( n10467 , n10466 );
buf ( n10468 , n10467 );
buf ( n10469 , n10468 );
and ( n10470 , n10444 , n10469 );
not ( n10471 , n10444 );
buf ( n10472 , n10465 );
and ( n10473 , n10471 , n10472 );
nor ( n10474 , n10470 , n10473 );
buf ( n10475 , n10474 );
buf ( n10476 , n10475 );
not ( n10477 , n10476 );
buf ( n10478 , n10477 );
buf ( n10479 , n10478 );
not ( n10480 , n10479 );
or ( n10481 , n10443 , n10480 );
buf ( n10482 , n378 );
nand ( n10483 , n10097 , n5586 );
and ( n10484 , n10483 , n5684 );
xor ( n10485 , n10238 , n10484 );
buf ( n10486 , n10485 );
xor ( n10487 , n10482 , n10486 );
buf ( n10488 , n10487 );
buf ( n10489 , n10488 );
buf ( n10490 , n9790 );
nand ( n10491 , n10489 , n10490 );
buf ( n10492 , n10491 );
buf ( n10493 , n10492 );
nand ( n10494 , n10481 , n10493 );
buf ( n10495 , n10494 );
buf ( n10496 , n10495 );
nand ( n10497 , n10441 , n10496 );
buf ( n10498 , n10497 );
nand ( n10499 , n10438 , n10498 );
xnor ( n10500 , n10403 , n10499 );
buf ( n10501 , n10500 );
not ( n10502 , n5660 );
not ( n10503 , n10502 );
buf ( n10504 , n10311 );
buf ( n10505 , n10315 );
nor ( n10506 , n10504 , n10505 );
buf ( n10507 , n10506 );
nor ( n10508 , n10503 , n10507 );
not ( n10509 , n10508 );
buf ( n10510 , n5031 );
buf ( n10511 , n5172 );
nor ( n10512 , n10510 , n10511 );
buf ( n10513 , n10512 );
not ( n10514 , n10513 );
not ( n10515 , n10514 );
not ( n10516 , n10107 );
or ( n10517 , n10515 , n10516 );
not ( n10518 , n10163 );
nand ( n10519 , n10518 , n10156 , n10229 );
nand ( n10520 , n10517 , n10519 );
not ( n10521 , n10520 );
not ( n10522 , n5288 );
not ( n10523 , n5177 );
nand ( n10524 , n10522 , n10523 );
not ( n10525 , n10524 );
nor ( n10526 , n5680 , n10525 );
not ( n10527 , n10526 );
or ( n10528 , n10521 , n10527 );
not ( n10529 , n10331 );
nand ( n10530 , n10528 , n10529 );
not ( n10531 , n10530 );
not ( n10532 , n10531 );
or ( n10533 , n10509 , n10532 );
not ( n10534 , n10507 );
nand ( n10535 , n10534 , n10502 );
nand ( n10536 , n10535 , n10530 );
nand ( n10537 , n10533 , n10536 );
buf ( n10538 , n10537 );
buf ( n10539 , n378 );
nand ( n10540 , n10538 , n10539 );
buf ( n10541 , n10540 );
nand ( n10542 , n9366 , n9699 );
not ( n10543 , n10542 );
not ( n10544 , n9143 );
not ( n10545 , n8840 );
or ( n10546 , n10544 , n10545 );
buf ( n10547 , n9692 );
not ( n10548 , n10547 );
buf ( n10549 , n10548 );
nand ( n10550 , n10546 , n10549 );
not ( n10551 , n10550 );
not ( n10552 , n9270 );
or ( n10553 , n10551 , n10552 );
buf ( n10554 , n9704 );
nand ( n10555 , n10553 , n10554 );
not ( n10556 , n10555 );
or ( n10557 , n10543 , n10556 );
or ( n10558 , n10542 , n10555 );
nand ( n10559 , n10557 , n10558 );
nand ( n10560 , n10559 , n384 );
nand ( n10561 , n10541 , n10560 );
buf ( n10562 , n10561 );
not ( n10563 , n10562 );
not ( n10564 , n9773 );
not ( n10565 , n10488 );
or ( n10566 , n10564 , n10565 );
xor ( n10567 , n10310 , n10342 );
buf ( n10568 , n10567 );
nand ( n10569 , n10568 , n9790 );
nand ( n10570 , n10566 , n10569 );
buf ( n10571 , n10570 );
not ( n10572 , n10571 );
or ( n10573 , n10563 , n10572 );
not ( n10574 , n10560 );
buf ( n10575 , n10541 );
not ( n10576 , n10575 );
buf ( n10577 , n10576 );
nand ( n10578 , n10574 , n10577 );
buf ( n10579 , n10578 );
nand ( n10580 , n10573 , n10579 );
buf ( n10581 , n10580 );
buf ( n10582 , n10581 );
xor ( n10583 , n10309 , n10345 );
xor ( n10584 , n10583 , n10387 );
buf ( n10585 , n10584 );
buf ( n10586 , n10585 );
xor ( n10587 , n10582 , n10586 );
xor ( n10588 , n384 , n10413 );
buf ( n10589 , n10588 );
buf ( n10590 , n9853 );
not ( n10591 , n10590 );
not ( n10592 , n382 );
not ( n10593 , n10171 );
not ( n10594 , n10593 );
or ( n10595 , n10592 , n10594 );
or ( n10596 , n10172 , n382 );
nand ( n10597 , n10595 , n10596 );
buf ( n10598 , n10597 );
not ( n10599 , n10598 );
or ( n10600 , n10591 , n10599 );
buf ( n10601 , n9836 );
buf ( n10602 , n382 );
nand ( n10603 , n10601 , n10602 );
buf ( n10604 , n10603 );
buf ( n10605 , n10604 );
nand ( n10606 , n10600 , n10605 );
buf ( n10607 , n10606 );
buf ( n10608 , n10607 );
xor ( n10609 , n10589 , n10608 );
buf ( n10610 , n9745 );
not ( n10611 , n10610 );
buf ( n10612 , n10429 );
not ( n10613 , n10612 );
or ( n10614 , n10611 , n10613 );
buf ( n10615 , n380 );
not ( n10616 , n10615 );
buf ( n10617 , n10468 );
not ( n10618 , n10617 );
or ( n10619 , n10616 , n10618 );
not ( n10620 , n10464 );
nand ( n10621 , n10620 , n9732 );
buf ( n10622 , n10621 );
nand ( n10623 , n10619 , n10622 );
buf ( n10624 , n10623 );
buf ( n10625 , n10624 );
buf ( n10626 , n9743 );
nand ( n10627 , n10625 , n10626 );
buf ( n10628 , n10627 );
buf ( n10629 , n10628 );
nand ( n10630 , n10614 , n10629 );
buf ( n10631 , n10630 );
buf ( n10632 , n10631 );
and ( n10633 , n10609 , n10632 );
and ( n10634 , n10589 , n10608 );
or ( n10635 , n10633 , n10634 );
buf ( n10636 , n10635 );
buf ( n10637 , n10636 );
and ( n10638 , n10587 , n10637 );
and ( n10639 , n10582 , n10586 );
or ( n10640 , n10638 , n10639 );
buf ( n10641 , n10640 );
buf ( n10642 , n10641 );
or ( n10643 , n10501 , n10642 );
and ( n10644 , n10482 , n10486 );
buf ( n10645 , n10644 );
buf ( n10646 , n10645 );
buf ( n10647 , n9630 );
buf ( n10648 , n9535 );
nand ( n10649 , n10647 , n10648 );
buf ( n10650 , n10649 );
buf ( n10651 , n10650 );
buf ( n10652 , n10353 );
buf ( n10653 , n10358 );
or ( n10654 , n10652 , n10653 );
buf ( n10655 , n9713 );
buf ( n10656 , n9466 );
nand ( n10657 , n10655 , n10656 );
buf ( n10658 , n10657 );
buf ( n10659 , n10658 );
not ( n10660 , n10659 );
buf ( n10661 , n10660 );
buf ( n10662 , n10661 );
nand ( n10663 , n10654 , n10662 );
buf ( n10664 , n10663 );
buf ( n10665 , n10664 );
not ( n10666 , n10364 );
not ( n10667 , n10658 );
and ( n10668 , n10666 , n10667 );
nand ( n10669 , n9466 , n10404 );
buf ( n10670 , n10669 );
buf ( n10671 , n9626 );
nand ( n10672 , n10670 , n10671 );
buf ( n10673 , n10672 );
nor ( n10674 , n10668 , n10673 );
buf ( n10675 , n10674 );
nand ( n10676 , n10665 , n10675 );
buf ( n10677 , n10676 );
buf ( n10678 , n10677 );
or ( n10679 , n10651 , n10678 );
buf ( n10680 , n10677 );
buf ( n10681 , n10650 );
nand ( n10682 , n10680 , n10681 );
buf ( n10683 , n10682 );
buf ( n10684 , n10683 );
nand ( n10685 , n10679 , n10684 );
buf ( n10686 , n10685 );
buf ( n10687 , n10686 );
buf ( n10688 , n10033 );
xnor ( n10689 , n10687 , n10688 );
buf ( n10690 , n10689 );
buf ( n10691 , n10690 );
xor ( n10692 , n10646 , n10691 );
not ( n10693 , n9773 );
buf ( n10694 , n378 );
not ( n10695 , n10694 );
buf ( n10696 , n10249 );
not ( n10697 , n10696 );
or ( n10698 , n10695 , n10697 );
not ( n10699 , n10244 );
not ( n10700 , n10418 );
or ( n10701 , n10699 , n10700 );
nand ( n10702 , n10243 , n10241 );
nand ( n10703 , n10701 , n10702 );
nand ( n10704 , n10703 , n9776 );
buf ( n10705 , n10704 );
nand ( n10706 , n10698 , n10705 );
buf ( n10707 , n10706 );
not ( n10708 , n10707 );
or ( n10709 , n10693 , n10708 );
or ( n10710 , n10475 , n9793 );
nand ( n10711 , n10709 , n10710 );
buf ( n10712 , n10711 );
xor ( n10713 , n10692 , n10712 );
buf ( n10714 , n10713 );
buf ( n10715 , n10714 );
nand ( n10716 , n10643 , n10715 );
buf ( n10717 , n10716 );
buf ( n10718 , n10717 );
buf ( n10719 , n10641 );
buf ( n10720 , n10500 );
nand ( n10721 , n10719 , n10720 );
buf ( n10722 , n10721 );
buf ( n10723 , n10722 );
nand ( n10724 , n10718 , n10723 );
buf ( n10725 , n10724 );
buf ( n10726 , n10725 );
not ( n10727 , n10726 );
and ( n10728 , n10465 , n378 );
not ( n10729 , n10728 );
xor ( n10730 , n10056 , n10729 );
buf ( n10731 , n9654 );
buf ( n10732 , n9584 );
nand ( n10733 , n10731 , n10732 );
buf ( n10734 , n10733 );
buf ( n10735 , n10734 );
not ( n10736 , n10735 );
not ( n10737 , n9535 );
not ( n10738 , n10677 );
or ( n10739 , n10737 , n10738 );
nand ( n10740 , n10739 , n9630 );
buf ( n10741 , n10740 );
not ( n10742 , n10741 );
or ( n10743 , n10736 , n10742 );
buf ( n10744 , n10740 );
buf ( n10745 , n10734 );
or ( n10746 , n10744 , n10745 );
nand ( n10747 , n10743 , n10746 );
buf ( n10748 , n10747 );
xnor ( n10749 , n10730 , n10748 );
not ( n10750 , n10401 );
not ( n10751 , n10391 );
or ( n10752 , n10750 , n10751 );
not ( n10753 , n10402 );
not ( n10754 , n10391 );
not ( n10755 , n10754 );
or ( n10756 , n10753 , n10755 );
nand ( n10757 , n10756 , n10499 );
nand ( n10758 , n10752 , n10757 );
xor ( n10759 , n10749 , n10758 );
buf ( n10760 , n9790 );
not ( n10761 , n10760 );
buf ( n10762 , n10707 );
not ( n10763 , n10762 );
or ( n10764 , n10761 , n10763 );
buf ( n10765 , n10205 );
buf ( n10766 , n9773 );
nand ( n10767 , n10765 , n10766 );
buf ( n10768 , n10767 );
buf ( n10769 , n10768 );
nand ( n10770 , n10764 , n10769 );
buf ( n10771 , n10770 );
buf ( n10772 , n10771 );
not ( n10773 , n10772 );
buf ( n10774 , n10033 );
not ( n10775 , n10774 );
buf ( n10776 , n10686 );
nand ( n10777 , n10775 , n10776 );
buf ( n10778 , n10777 );
buf ( n10779 , n10778 );
not ( n10780 , n10779 );
and ( n10781 , n10773 , n10780 );
buf ( n10782 , n10771 );
buf ( n10783 , n10778 );
and ( n10784 , n10782 , n10783 );
nor ( n10785 , n10781 , n10784 );
buf ( n10786 , n10785 );
xor ( n10787 , n10646 , n10691 );
and ( n10788 , n10787 , n10712 );
and ( n10789 , n10646 , n10691 );
or ( n10790 , n10788 , n10789 );
buf ( n10791 , n10790 );
xor ( n10792 , n10786 , n10791 );
xnor ( n10793 , n10759 , n10792 );
buf ( n10794 , n10793 );
not ( n10795 , n10794 );
buf ( n10796 , n10795 );
buf ( n10797 , n10796 );
nand ( n10798 , n10727 , n10797 );
buf ( n10799 , n10798 );
buf ( n10800 , n10177 );
buf ( n10801 , n10290 );
xor ( n10802 , n10800 , n10801 );
buf ( n10803 , n10282 );
xor ( n10804 , n10802 , n10803 );
buf ( n10805 , n10804 );
or ( n10806 , n10056 , n10748 );
nand ( n10807 , n10806 , n10728 );
nand ( n10808 , n10748 , n10056 );
nand ( n10809 , n10807 , n10808 );
buf ( n10810 , n10809 );
not ( n10811 , n10810 );
buf ( n10812 , n10811 );
not ( n10813 , n10812 );
buf ( n10814 , n10771 );
not ( n10815 , n10814 );
buf ( n10816 , n10778 );
nand ( n10817 , n10815 , n10816 );
buf ( n10818 , n10817 );
buf ( n10819 , n10818 );
not ( n10820 , n10819 );
buf ( n10821 , n10791 );
not ( n10822 , n10821 );
or ( n10823 , n10820 , n10822 );
buf ( n10824 , n10778 );
not ( n10825 , n10824 );
buf ( n10826 , n10771 );
nand ( n10827 , n10825 , n10826 );
buf ( n10828 , n10827 );
buf ( n10829 , n10828 );
nand ( n10830 , n10823 , n10829 );
buf ( n10831 , n10830 );
buf ( n10832 , n10831 );
not ( n10833 , n10832 );
buf ( n10834 , n10833 );
not ( n10835 , n10834 );
or ( n10836 , n10813 , n10835 );
xor ( n10837 , n10271 , n10254 );
xor ( n10838 , n10837 , n10215 );
not ( n10839 , n10838 );
nand ( n10840 , n10836 , n10839 );
nand ( n10841 , n10831 , n10809 );
nand ( n10842 , n10805 , n10840 , n10841 );
nand ( n10843 , n10799 , n10842 );
not ( n10844 , n10838 );
not ( n10845 , n10809 );
or ( n10846 , n10844 , n10845 );
or ( n10847 , n10838 , n10809 );
nand ( n10848 , n10846 , n10847 );
xor ( n10849 , n10831 , n10848 );
buf ( n10850 , n10849 );
not ( n10851 , n10850 );
buf ( n10852 , n10851 );
not ( n10853 , n10792 );
not ( n10854 , n10853 );
not ( n10855 , n10749 );
not ( n10856 , n10758 );
nand ( n10857 , n10855 , n10856 );
not ( n10858 , n10857 );
or ( n10859 , n10854 , n10858 );
not ( n10860 , n10856 );
nand ( n10861 , n10860 , n10749 );
nand ( n10862 , n10859 , n10861 );
not ( n10863 , n10862 );
nand ( n10864 , n10852 , n10863 );
buf ( n10865 , n10864 );
buf ( n10866 , n10414 );
buf ( n10867 , n10495 );
xor ( n10868 , n10866 , n10867 );
buf ( n10869 , n10436 );
xnor ( n10870 , n10868 , n10869 );
buf ( n10871 , n10870 );
buf ( n10872 , n10871 );
not ( n10873 , n10872 );
buf ( n10874 , n10235 );
buf ( n10875 , n5709 );
xor ( n10876 , n10874 , n10875 );
buf ( n10877 , n10876 );
buf ( n10878 , n10877 );
not ( n10879 , n10878 );
buf ( n10880 , n10879 );
buf ( n10881 , n10880 );
not ( n10882 , n10881 );
buf ( n10883 , n10882 );
buf ( n10884 , n9704 );
buf ( n10885 , n9270 );
nand ( n10886 , n10884 , n10885 );
buf ( n10887 , n10886 );
xnor ( n10888 , n10550 , n10887 );
nand ( n10889 , n378 , n10883 , n10888 );
buf ( n10890 , n10889 );
not ( n10891 , n10890 );
buf ( n10892 , n10891 );
buf ( n10893 , n10892 );
not ( n10894 , n10893 );
and ( n10895 , n9853 , n382 );
and ( n10896 , n10249 , n10895 );
and ( n10897 , n10597 , n9836 );
nor ( n10898 , n10896 , n10897 );
nand ( n10899 , n10703 , n9738 , n9853 );
nand ( n10900 , n10898 , n10899 );
buf ( n10901 , n10900 );
not ( n10902 , n10901 );
or ( n10903 , n10894 , n10902 );
buf ( n10904 , n10900 );
buf ( n10905 , n10892 );
or ( n10906 , n10904 , n10905 );
buf ( n10907 , n9745 );
not ( n10908 , n10907 );
buf ( n10909 , n10624 );
not ( n10910 , n10909 );
or ( n10911 , n10908 , n10910 );
buf ( n10912 , n10485 );
not ( n10913 , n10912 );
buf ( n10914 , n10913 );
nand ( n10915 , n380 , n10914 );
not ( n10916 , n10915 );
not ( n10917 , n380 );
nand ( n10918 , n10917 , n10485 );
not ( n10919 , n10918 );
or ( n10920 , n10916 , n10919 );
nand ( n10921 , n10920 , n9743 );
buf ( n10922 , n10921 );
nand ( n10923 , n10911 , n10922 );
buf ( n10924 , n10923 );
buf ( n10925 , n10924 );
nand ( n10926 , n10906 , n10925 );
buf ( n10927 , n10926 );
buf ( n10928 , n10927 );
nand ( n10929 , n10903 , n10928 );
buf ( n10930 , n10929 );
buf ( n10931 , n10930 );
not ( n10932 , n10931 );
not ( n10933 , n10570 );
not ( n10934 , n10933 );
and ( n10935 , n10560 , n10577 );
not ( n10936 , n10560 );
and ( n10937 , n10936 , n10541 );
nor ( n10938 , n10935 , n10937 );
not ( n10939 , n10938 );
not ( n10940 , n10939 );
or ( n10941 , n10934 , n10940 );
nand ( n10942 , n10938 , n10570 );
nand ( n10943 , n10941 , n10942 );
buf ( n10944 , n10943 );
buf ( n10945 , n10944 );
buf ( n10946 , n10945 );
buf ( n10947 , n10946 );
not ( n10948 , n10947 );
buf ( n10949 , n10948 );
buf ( n10950 , n10949 );
and ( n10951 , n10524 , n5679 );
not ( n10952 , n10951 );
not ( n10953 , n10520 );
or ( n10954 , n10952 , n10953 );
not ( n10955 , n10225 );
not ( n10956 , n5713 );
and ( n10957 , n10955 , n10956 );
nor ( n10958 , n10957 , n5712 );
nand ( n10959 , n10954 , n10958 );
buf ( n10960 , n10959 );
buf ( n10961 , n10221 );
buf ( n10962 , n5831 );
nand ( n10963 , n10961 , n10962 );
buf ( n10964 , n10963 );
buf ( n10965 , n10964 );
not ( n10966 , n10965 );
buf ( n10967 , n10966 );
buf ( n10968 , n10967 );
and ( n10969 , n10960 , n10968 );
not ( n10970 , n10960 );
buf ( n10971 , n10964 );
and ( n10972 , n10970 , n10971 );
nor ( n10973 , n10969 , n10972 );
buf ( n10974 , n10973 );
buf ( n10975 , n10974 );
not ( n10976 , n10975 );
buf ( n10977 , n10976 );
buf ( n10978 , n10977 );
not ( n10979 , n10978 );
buf ( n10980 , n10979 );
buf ( n10981 , n10980 );
buf ( n10982 , n378 );
nand ( n10983 , n10981 , n10982 );
buf ( n10984 , n10983 );
xor ( n10985 , n384 , n10542 );
xor ( n10986 , n10985 , n10555 );
nand ( n10987 , n10984 , n10986 );
not ( n10988 , n10987 );
buf ( n10989 , n9773 );
not ( n10990 , n10989 );
buf ( n10991 , n10568 );
not ( n10992 , n10991 );
or ( n10993 , n10990 , n10992 );
and ( n10994 , n10535 , n9776 );
not ( n10995 , n10535 );
and ( n10996 , n10995 , n378 );
nor ( n10997 , n10994 , n10996 );
buf ( n10998 , n10531 );
not ( n10999 , n10998 );
and ( n11000 , n10997 , n10999 );
not ( n11001 , n10997 );
and ( n11002 , n11001 , n10998 );
nor ( n11003 , n11000 , n11002 );
nand ( n11004 , n11003 , n9790 );
buf ( n11005 , n11004 );
nand ( n11006 , n10993 , n11005 );
buf ( n11007 , n11006 );
not ( n11008 , n11007 );
or ( n11009 , n10988 , n11008 );
or ( n11010 , n10986 , n10984 );
nand ( n11011 , n11009 , n11010 );
not ( n11012 , n11011 );
buf ( n11013 , n11012 );
nand ( n11014 , n10950 , n11013 );
buf ( n11015 , n11014 );
buf ( n11016 , n11015 );
not ( n11017 , n11016 );
or ( n11018 , n10932 , n11017 );
not ( n11019 , n10987 );
not ( n11020 , n11007 );
or ( n11021 , n11019 , n11020 );
nand ( n11022 , n11021 , n11010 );
nand ( n11023 , n10946 , n11022 );
buf ( n11024 , n11023 );
nand ( n11025 , n11018 , n11024 );
buf ( n11026 , n11025 );
buf ( n11027 , n11026 );
not ( n11028 , n11027 );
buf ( n11029 , n11028 );
buf ( n11030 , n11029 );
not ( n11031 , n11030 );
or ( n11032 , n10873 , n11031 );
xor ( n11033 , n10582 , n10586 );
xor ( n11034 , n11033 , n10637 );
buf ( n11035 , n11034 );
buf ( n11036 , n11035 );
buf ( n11037 , n11036 );
buf ( n11038 , n11037 );
buf ( n11039 , n11038 );
nand ( n11040 , n11032 , n11039 );
buf ( n11041 , n11040 );
buf ( n11042 , n11041 );
buf ( n11043 , n10871 );
not ( n11044 , n11043 );
buf ( n11045 , n11026 );
nand ( n11046 , n11044 , n11045 );
buf ( n11047 , n11046 );
buf ( n11048 , n11047 );
and ( n11049 , n11042 , n11048 );
buf ( n11050 , n11049 );
buf ( n11051 , n10714 );
buf ( n11052 , n10641 );
xor ( n11053 , n11051 , n11052 );
buf ( n11054 , n10500 );
xnor ( n11055 , n11053 , n11054 );
buf ( n11056 , n11055 );
nand ( n11057 , n11050 , n11056 );
buf ( n11058 , n11057 );
nand ( n11059 , n10865 , n11058 );
buf ( n11060 , n11059 );
nor ( n11061 , n10843 , n11060 );
not ( n11062 , n11061 );
xor ( n11063 , n10889 , n10924 );
xnor ( n11064 , n11063 , n10900 );
nand ( n11065 , n10524 , n5713 );
not ( n11066 , n11065 );
not ( n11067 , n11066 );
not ( n11068 , n10520 );
not ( n11069 , n11068 );
or ( n11070 , n11067 , n11069 );
nand ( n11071 , n10520 , n11065 );
nand ( n11072 , n11070 , n11071 );
buf ( n11073 , n11072 );
buf ( n11074 , n378 );
and ( n11075 , n11073 , n11074 );
buf ( n11076 , n11075 );
buf ( n11077 , n11076 );
and ( n11078 , n9689 , n9095 );
buf ( n11079 , n9140 );
not ( n11080 , n11079 );
buf ( n11081 , n8840 );
buf ( n11082 , n11081 );
buf ( n11083 , n11082 );
buf ( n11084 , n11083 );
not ( n11085 , n11084 );
or ( n11086 , n11080 , n11085 );
buf ( n11087 , n9673 );
buf ( n11088 , n11087 );
buf ( n11089 , n11088 );
buf ( n11090 , n11089 );
nand ( n11091 , n11086 , n11090 );
buf ( n11092 , n11091 );
xor ( n11093 , n11078 , n11092 );
buf ( n11094 , n11093 );
xor ( n11095 , n11077 , n11094 );
and ( n11096 , n11089 , n9140 );
xor ( n11097 , n11096 , n11083 );
nand ( n11098 , n2967 , n2984 , n3025 );
and ( n11099 , n11097 , n11098 );
buf ( n11100 , n11099 );
xor ( n11101 , n11095 , n11100 );
buf ( n11102 , n11101 );
buf ( n11103 , n11102 );
buf ( n11104 , n9836 );
not ( n11105 , n11104 );
not ( n11106 , n382 );
not ( n11107 , n10468 );
or ( n11108 , n11106 , n11107 );
nand ( n11109 , n10465 , n9738 );
nand ( n11110 , n11108 , n11109 );
buf ( n11111 , n11110 );
not ( n11112 , n11111 );
or ( n11113 , n11105 , n11112 );
buf ( n11114 , n382 );
buf ( n11115 , n10914 );
and ( n11116 , n11114 , n11115 );
not ( n11117 , n11114 );
buf ( n11118 , n10485 );
and ( n11119 , n11117 , n11118 );
nor ( n11120 , n11116 , n11119 );
buf ( n11121 , n11120 );
not ( n11122 , n11121 );
nand ( n11123 , n11122 , n9853 );
buf ( n11124 , n11123 );
nand ( n11125 , n11113 , n11124 );
buf ( n11126 , n11125 );
buf ( n11127 , n11126 );
xor ( n11128 , n11103 , n11127 );
buf ( n11129 , n9790 );
not ( n11130 , n11129 );
buf ( n11131 , n378 );
buf ( n11132 , n11072 );
and ( n11133 , n11131 , n11132 );
not ( n11134 , n11131 );
buf ( n11135 , n11072 );
not ( n11136 , n11135 );
buf ( n11137 , n11136 );
buf ( n11138 , n11137 );
and ( n11139 , n11134 , n11138 );
nor ( n11140 , n11133 , n11139 );
buf ( n11141 , n11140 );
buf ( n11142 , n11141 );
not ( n11143 , n11142 );
or ( n11144 , n11130 , n11143 );
buf ( n11145 , n378 );
not ( n11146 , n11145 );
buf ( n11147 , n10880 );
not ( n11148 , n11147 );
or ( n11149 , n11146 , n11148 );
buf ( n11150 , n9776 );
buf ( n11151 , n10877 );
nand ( n11152 , n11150 , n11151 );
buf ( n11153 , n11152 );
buf ( n11154 , n11153 );
nand ( n11155 , n11149 , n11154 );
buf ( n11156 , n11155 );
buf ( n11157 , n11156 );
buf ( n11158 , n9773 );
nand ( n11159 , n11157 , n11158 );
buf ( n11160 , n11159 );
buf ( n11161 , n11160 );
nand ( n11162 , n11144 , n11161 );
buf ( n11163 , n11162 );
not ( n11164 , n11163 );
buf ( n11165 , n380 );
not ( n11166 , n11165 );
buf ( n11167 , n10537 );
not ( n11168 , n11167 );
buf ( n11169 , n11168 );
buf ( n11170 , n11169 );
not ( n11171 , n11170 );
or ( n11172 , n11166 , n11171 );
buf ( n11173 , n10537 );
buf ( n11174 , n9732 );
nand ( n11175 , n11173 , n11174 );
buf ( n11176 , n11175 );
buf ( n11177 , n11176 );
nand ( n11178 , n11172 , n11177 );
buf ( n11179 , n11178 );
nand ( n11180 , n11179 , n9745 );
not ( n11181 , n9732 );
and ( n11182 , n10959 , n10964 );
not ( n11183 , n10959 );
and ( n11184 , n11183 , n10967 );
nor ( n11185 , n11182 , n11184 );
not ( n11186 , n11185 );
not ( n11187 , n11186 );
or ( n11188 , n11181 , n11187 );
or ( n11189 , n9732 , n11186 );
nand ( n11190 , n11188 , n11189 );
nand ( n11191 , n11190 , n9743 );
nand ( n11192 , n11164 , n11180 , n11191 );
not ( n11193 , n11192 );
buf ( n11194 , n382 );
not ( n11195 , n11194 );
buf ( n11196 , n10340 );
not ( n11197 , n11196 );
or ( n11198 , n11195 , n11197 );
buf ( n11199 , n10341 );
buf ( n11200 , n9738 );
nand ( n11201 , n11199 , n11200 );
buf ( n11202 , n11201 );
buf ( n11203 , n11202 );
nand ( n11204 , n11198 , n11203 );
buf ( n11205 , n11204 );
not ( n11206 , n11205 );
not ( n11207 , n9853 );
or ( n11208 , n11206 , n11207 );
or ( n11209 , n11121 , n9839 );
nand ( n11210 , n11208 , n11209 );
not ( n11211 , n11210 );
or ( n11212 , n11193 , n11211 );
not ( n11213 , n11191 );
not ( n11214 , n11180 );
or ( n11215 , n11213 , n11214 );
nand ( n11216 , n11215 , n11163 );
nand ( n11217 , n11212 , n11216 );
buf ( n11218 , n11217 );
and ( n11219 , n11128 , n11218 );
and ( n11220 , n11103 , n11127 );
or ( n11221 , n11219 , n11220 );
buf ( n11222 , n11221 );
not ( n11223 , n11222 );
nand ( n11224 , n10883 , n378 );
not ( n11225 , n10888 );
and ( n11226 , n11224 , n11225 );
not ( n11227 , n11224 );
and ( n11228 , n11227 , n10888 );
nor ( n11229 , n11226 , n11228 );
not ( n11230 , n9790 );
not ( n11231 , n378 );
not ( n11232 , n11185 );
or ( n11233 , n11231 , n11232 );
buf ( n11234 , n10974 );
buf ( n11235 , n9776 );
nand ( n11236 , n11234 , n11235 );
buf ( n11237 , n11236 );
nand ( n11238 , n11233 , n11237 );
not ( n11239 , n11238 );
or ( n11240 , n11230 , n11239 );
nand ( n11241 , n11003 , n9773 );
nand ( n11242 , n11240 , n11241 );
xor ( n11243 , n11229 , n11242 );
xor ( n11244 , n10335 , n380 );
not ( n11245 , n10311 );
not ( n11246 , n10315 );
and ( n11247 , n11245 , n11246 );
and ( n11248 , n10319 , n10332 );
nor ( n11249 , n11247 , n11248 );
xnor ( n11250 , n11244 , n11249 );
not ( n11251 , n11250 );
not ( n11252 , n9743 );
or ( n11253 , n11251 , n11252 );
not ( n11254 , n10915 );
not ( n11255 , n10918 );
or ( n11256 , n11254 , n11255 );
nand ( n11257 , n11256 , n9745 );
nand ( n11258 , n11253 , n11257 );
xor ( n11259 , n11243 , n11258 );
not ( n11260 , n11259 );
not ( n11261 , n11179 );
not ( n11262 , n9743 );
or ( n11263 , n11261 , n11262 );
nand ( n11264 , n11250 , n9745 );
nand ( n11265 , n11263 , n11264 );
not ( n11266 , n11265 );
nand ( n11267 , n10157 , n5720 );
not ( n11268 , n11267 );
not ( n11269 , n10513 );
nand ( n11270 , n5172 , n5031 );
nand ( n11271 , n11269 , n11270 );
not ( n11272 , n11271 );
or ( n11273 , n11268 , n11272 );
not ( n11274 , n11267 );
not ( n11275 , n11270 );
nor ( n11276 , n11275 , n10513 );
nand ( n11277 , n11274 , n11276 );
nand ( n11278 , n11273 , n11277 );
and ( n11279 , n378 , n11278 );
not ( n11280 , n11279 );
not ( n11281 , n11280 );
buf ( n11282 , n8620 );
buf ( n11283 , n11282 );
buf ( n11284 , n11283 );
buf ( n11285 , n11284 );
not ( n11286 , n11285 );
buf ( n11287 , n8642 );
not ( n11288 , n11287 );
buf ( n11289 , n11288 );
buf ( n11290 , n11289 );
not ( n11291 , n11290 );
buf ( n11292 , n8212 );
not ( n11293 , n11292 );
or ( n11294 , n11291 , n11293 );
buf ( n11295 , n8814 );
not ( n11296 , n11295 );
buf ( n11297 , n11296 );
buf ( n11298 , n11297 );
nand ( n11299 , n11294 , n11298 );
buf ( n11300 , n11299 );
buf ( n11301 , n11300 );
not ( n11302 , n11301 );
or ( n11303 , n11286 , n11302 );
buf ( n11304 , n8810 );
not ( n11305 , n11304 );
buf ( n11306 , n11305 );
buf ( n11307 , n11306 );
not ( n11308 , n11307 );
buf ( n11309 , n11308 );
buf ( n11310 , n11309 );
nand ( n11311 , n11303 , n11310 );
buf ( n11312 , n11311 );
buf ( n11313 , n8833 );
buf ( n11314 , n8800 );
nand ( n11315 , n11313 , n11314 );
buf ( n11316 , n11315 );
not ( n11317 , n11316 );
and ( n11318 , n11312 , n11317 );
not ( n11319 , n11312 );
and ( n11320 , n11319 , n11316 );
nor ( n11321 , n11318 , n11320 );
nand ( n11322 , n5723 , n10111 );
not ( n11323 , n11322 );
not ( n11324 , n10120 );
or ( n11325 , n11323 , n11324 );
nand ( n11326 , n5724 , n10154 , n11322 );
nand ( n11327 , n11325 , n11326 );
not ( n11328 , n4868 );
not ( n11329 , n11328 );
not ( n11330 , n5026 );
not ( n11331 , n11330 );
or ( n11332 , n11329 , n11331 );
nand ( n11333 , n11332 , n5720 );
not ( n11334 , n11333 );
and ( n11335 , n11327 , n11334 );
not ( n11336 , n11327 );
not ( n11337 , n11328 );
not ( n11338 , n11330 );
or ( n11339 , n11337 , n11338 );
nand ( n11340 , n11339 , n5720 );
and ( n11341 , n11336 , n11340 );
nor ( n11342 , n11335 , n11341 );
nand ( n11343 , n11342 , n378 );
not ( n11344 , n11343 );
nand ( n11345 , n11321 , n11344 );
not ( n11346 , n11345 );
or ( n11347 , n11281 , n11346 );
xor ( n11348 , n11097 , n11098 );
nand ( n11349 , n11347 , n11348 );
not ( n11350 , n11345 );
nand ( n11351 , n11350 , n11279 );
nand ( n11352 , n11349 , n11351 );
not ( n11353 , n11352 );
not ( n11354 , n9773 );
not ( n11355 , n11238 );
or ( n11356 , n11354 , n11355 );
nand ( n11357 , n11156 , n9790 );
nand ( n11358 , n11356 , n11357 );
not ( n11359 , n11358 );
nand ( n11360 , n11353 , n11359 );
not ( n11361 , n11360 );
or ( n11362 , n11266 , n11361 );
nand ( n11363 , n11358 , n11352 );
nand ( n11364 , n11362 , n11363 );
buf ( n11365 , n11364 );
not ( n11366 , n11365 );
buf ( n11367 , n11366 );
nand ( n11368 , n11260 , n11367 );
not ( n11369 , n11368 );
or ( n11370 , n11223 , n11369 );
buf ( n11371 , n11260 );
not ( n11372 , n11371 );
buf ( n11373 , n11372 );
buf ( n11374 , n11373 );
buf ( n11375 , n11364 );
nand ( n11376 , n11374 , n11375 );
buf ( n11377 , n11376 );
nand ( n11378 , n11370 , n11377 );
xor ( n11379 , n11064 , n11378 );
xor ( n11380 , n11229 , n11242 );
and ( n11381 , n11380 , n11258 );
and ( n11382 , n11229 , n11242 );
or ( n11383 , n11381 , n11382 );
buf ( n11384 , n11383 );
not ( n11385 , n11384 );
buf ( n11386 , n10984 );
buf ( n11387 , n10986 );
xor ( n11388 , n11386 , n11387 );
buf ( n11389 , n11007 );
xnor ( n11390 , n11388 , n11389 );
buf ( n11391 , n11390 );
buf ( n11392 , n11391 );
not ( n11393 , n11392 );
or ( n11394 , n11385 , n11393 );
buf ( n11395 , n11391 );
buf ( n11396 , n11383 );
or ( n11397 , n11395 , n11396 );
nand ( n11398 , n11394 , n11397 );
buf ( n11399 , n11398 );
not ( n11400 , n9853 );
not ( n11401 , n11110 );
or ( n11402 , n11400 , n11401 );
xor ( n11403 , n10243 , n382 );
xnor ( n11404 , n11403 , n10241 );
nand ( n11405 , n11404 , n9836 );
nand ( n11406 , n11402 , n11405 );
not ( n11407 , n11406 );
not ( n11408 , n385 );
and ( n11409 , n11408 , n384 );
buf ( n11410 , n11409 );
not ( n11411 , n11410 );
buf ( n11412 , n10195 );
not ( n11413 , n11412 );
or ( n11414 , n11411 , n11413 );
buf ( n11415 , n384 );
buf ( n11416 , n385 );
nand ( n11417 , n11415 , n11416 );
buf ( n11418 , n11417 );
buf ( n11419 , n11418 );
nand ( n11420 , n11414 , n11419 );
buf ( n11421 , n11420 );
not ( n11422 , n11421 );
or ( n11423 , n11407 , n11422 );
buf ( n11424 , n11421 );
not ( n11425 , n11424 );
buf ( n11426 , n11425 );
nand ( n11427 , n9853 , n11110 );
and ( n11428 , n11426 , n11427 , n11405 );
xor ( n11429 , n11077 , n11094 );
and ( n11430 , n11429 , n11100 );
and ( n11431 , n11077 , n11094 );
or ( n11432 , n11430 , n11431 );
buf ( n11433 , n11432 );
buf ( n11434 , n11433 );
not ( n11435 , n11434 );
buf ( n11436 , n11435 );
or ( n11437 , n11428 , n11436 );
nand ( n11438 , n11423 , n11437 );
and ( n11439 , n11399 , n11438 );
not ( n11440 , n11399 );
not ( n11441 , n11438 );
and ( n11442 , n11440 , n11441 );
nor ( n11443 , n11439 , n11442 );
xor ( n11444 , n11379 , n11443 );
buf ( n11445 , n11444 );
not ( n11446 , n11445 );
buf ( n11447 , n11446 );
and ( n11448 , n11436 , n11426 );
not ( n11449 , n11436 );
and ( n11450 , n11449 , n11421 );
nor ( n11451 , n11448 , n11450 );
not ( n11452 , n11451 );
not ( n11453 , n11406 );
and ( n11454 , n11452 , n11453 );
and ( n11455 , n11451 , n11406 );
nor ( n11456 , n11454 , n11455 );
buf ( n11457 , n11409 );
not ( n11458 , n11457 );
and ( n11459 , n384 , n10249 );
not ( n11460 , n384 );
and ( n11461 , n11460 , n10248 );
or ( n11462 , n11459 , n11461 );
buf ( n11463 , n11462 );
not ( n11464 , n11463 );
or ( n11465 , n11458 , n11464 );
buf ( n11466 , n384 );
buf ( n11467 , n10173 );
and ( n11468 , n11466 , n11467 );
not ( n11469 , n11466 );
buf ( n11470 , n10195 );
and ( n11471 , n11469 , n11470 );
nor ( n11472 , n11468 , n11471 );
buf ( n11473 , n11472 );
buf ( n11474 , n11473 );
buf ( n11475 , n385 );
nand ( n11476 , n11474 , n11475 );
buf ( n11477 , n11476 );
buf ( n11478 , n11477 );
nand ( n11479 , n11465 , n11478 );
buf ( n11480 , n11479 );
not ( n11481 , n11480 );
and ( n11482 , n11358 , n11352 );
not ( n11483 , n11358 );
and ( n11484 , n11483 , n11353 );
nor ( n11485 , n11482 , n11484 );
not ( n11486 , n11265 );
and ( n11487 , n11485 , n11486 );
not ( n11488 , n11485 );
and ( n11489 , n11488 , n11265 );
nor ( n11490 , n11487 , n11489 );
buf ( n11491 , n11490 );
not ( n11492 , n11491 );
buf ( n11493 , n11492 );
not ( n11494 , n11493 );
or ( n11495 , n11481 , n11494 );
buf ( n11496 , n11493 );
buf ( n11497 , n11480 );
or ( n11498 , n11496 , n11497 );
xor ( n11499 , n11280 , n11350 );
xnor ( n11500 , n11499 , n11348 );
not ( n11501 , n11500 );
buf ( n11502 , n11306 );
not ( n11503 , n11502 );
buf ( n11504 , n11284 );
nand ( n11505 , n11503 , n11504 );
buf ( n11506 , n11505 );
xnor ( n11507 , n11300 , n11506 );
buf ( n11508 , n11507 );
nand ( n11509 , n10155 , n5727 );
not ( n11510 , n4646 );
not ( n11511 , n4863 );
or ( n11512 , n11510 , n11511 );
nand ( n11513 , n11512 , n11322 );
not ( n11514 , n11513 );
and ( n11515 , n11509 , n11514 );
not ( n11516 , n11509 );
and ( n11517 , n11516 , n11513 );
nor ( n11518 , n11515 , n11517 );
and ( n11519 , n11518 , n378 );
buf ( n11520 , n11519 );
and ( n11521 , n11508 , n11520 );
buf ( n11522 , n11521 );
buf ( n11523 , n11522 );
not ( n11524 , n11523 );
nand ( n11525 , n3018 , n1007 );
not ( n11526 , n11525 );
nand ( n11527 , n2980 , n3029 );
nand ( n11528 , n11527 , n2782 );
not ( n11529 , n11528 );
or ( n11530 , n11526 , n11529 );
not ( n11531 , n11525 );
nand ( n11532 , n11531 , n2782 , n11527 );
nand ( n11533 , n11530 , n11532 );
buf ( n11534 , n11533 );
not ( n11535 , n11534 );
or ( n11536 , n11524 , n11535 );
not ( n11537 , n11522 );
not ( n11538 , n11537 );
not ( n11539 , n11533 );
not ( n11540 , n11539 );
or ( n11541 , n11538 , n11540 );
buf ( n11542 , n11321 );
buf ( n11543 , n11343 );
and ( n11544 , n11542 , n11543 );
not ( n11545 , n11542 );
buf ( n11546 , n11344 );
and ( n11547 , n11545 , n11546 );
nor ( n11548 , n11544 , n11547 );
buf ( n11549 , n11548 );
buf ( n11550 , n11549 );
not ( n11551 , n11550 );
buf ( n11552 , n11551 );
nand ( n11553 , n11541 , n11552 );
buf ( n11554 , n11553 );
nand ( n11555 , n11536 , n11554 );
buf ( n11556 , n11555 );
buf ( n11557 , n11556 );
not ( n11558 , n11557 );
buf ( n11559 , n11558 );
nand ( n11560 , n11501 , n11559 );
not ( n11561 , n11560 );
not ( n11562 , n9773 );
not ( n11563 , n11141 );
or ( n11564 , n11562 , n11563 );
xor ( n11565 , n378 , n11278 );
buf ( n11566 , n11565 );
buf ( n11567 , n9790 );
nand ( n11568 , n11566 , n11567 );
buf ( n11569 , n11568 );
nand ( n11570 , n11564 , n11569 );
not ( n11571 , n11570 );
not ( n11572 , n11571 );
buf ( n11573 , n9773 );
not ( n11574 , n11573 );
buf ( n11575 , n11565 );
not ( n11576 , n11575 );
or ( n11577 , n11574 , n11576 );
xor ( n11578 , n378 , n11340 );
xnor ( n11579 , n11578 , n11327 );
buf ( n11580 , n11579 );
buf ( n11581 , n9790 );
nand ( n11582 , n11580 , n11581 );
buf ( n11583 , n11582 );
buf ( n11584 , n11583 );
nand ( n11585 , n11577 , n11584 );
buf ( n11586 , n11585 );
not ( n11587 , n11586 );
buf ( n11588 , n11519 );
buf ( n11589 , n11507 );
not ( n11590 , n11589 );
buf ( n11591 , n11590 );
buf ( n11592 , n11591 );
and ( n11593 , n11588 , n11592 );
not ( n11594 , n11588 );
buf ( n11595 , n11507 );
and ( n11596 , n11594 , n11595 );
nor ( n11597 , n11593 , n11596 );
buf ( n11598 , n11597 );
buf ( n11599 , n11598 );
xor ( n11600 , n4230 , n4433 );
not ( n11601 , n10147 );
nand ( n11602 , n10142 , n4225 );
nand ( n11603 , n11601 , n11602 );
xor ( n11604 , n11600 , n11603 );
buf ( n11605 , n11604 );
buf ( n11606 , n11605 );
buf ( n11607 , n11606 );
nand ( n11608 , n11607 , n378 );
not ( n11609 , n11608 );
not ( n11610 , n8205 );
nor ( n11611 , n11610 , n8184 );
not ( n11612 , n11611 );
buf ( n11613 , n8193 );
not ( n11614 , n11613 );
buf ( n11615 , n11614 );
and ( n11616 , n11615 , n7551 );
not ( n11617 , n11616 );
or ( n11618 , n11612 , n11617 );
not ( n11619 , n8184 );
not ( n11620 , n11619 );
not ( n11621 , n11615 );
or ( n11622 , n11620 , n11621 );
nand ( n11623 , n7551 , n8205 );
nand ( n11624 , n11622 , n11623 );
nand ( n11625 , n11618 , n11624 );
nand ( n11626 , n11609 , n11625 );
buf ( n11627 , n11626 );
not ( n11628 , n11627 );
buf ( n11629 , n11297 );
buf ( n11630 , n11289 );
nand ( n11631 , n11629 , n11630 );
buf ( n11632 , n11631 );
buf ( n11633 , n11632 );
not ( n11634 , n11633 );
buf ( n11635 , n7551 );
not ( n11636 , n11635 );
buf ( n11637 , n8184 );
not ( n11638 , n11637 );
or ( n11639 , n11636 , n11638 );
buf ( n11640 , n8209 );
nand ( n11641 , n11639 , n11640 );
buf ( n11642 , n11641 );
buf ( n11643 , n11642 );
not ( n11644 , n11643 );
or ( n11645 , n11634 , n11644 );
buf ( n11646 , n11642 );
buf ( n11647 , n11632 );
or ( n11648 , n11646 , n11647 );
buf ( n11649 , n11648 );
buf ( n11650 , n11649 );
nand ( n11651 , n11645 , n11650 );
buf ( n11652 , n11651 );
buf ( n11653 , n11652 );
nand ( n11654 , n11628 , n11653 );
buf ( n11655 , n11654 );
buf ( n11656 , n11655 );
nand ( n11657 , n11599 , n11656 );
buf ( n11658 , n11657 );
not ( n11659 , n11658 );
or ( n11660 , n11587 , n11659 );
buf ( n11661 , n11655 );
not ( n11662 , n11661 );
buf ( n11663 , n11598 );
not ( n11664 , n11663 );
buf ( n11665 , n11664 );
buf ( n11666 , n11665 );
nand ( n11667 , n11662 , n11666 );
buf ( n11668 , n11667 );
nand ( n11669 , n11660 , n11668 );
buf ( n11670 , n11669 );
or ( n11671 , n11572 , n11670 );
not ( n11672 , n9745 );
not ( n11673 , n11190 );
or ( n11674 , n11672 , n11673 );
and ( n11675 , n10877 , n9732 );
not ( n11676 , n10877 );
and ( n11677 , n11676 , n380 );
or ( n11678 , n11675 , n11677 );
nand ( n11679 , n11678 , n9743 );
nand ( n11680 , n11674 , n11679 );
nand ( n11681 , n11671 , n11680 );
nand ( n11682 , n11670 , n11572 );
nand ( n11683 , n11681 , n11682 );
not ( n11684 , n11683 );
or ( n11685 , n11561 , n11684 );
nand ( n11686 , n11556 , n11500 );
nand ( n11687 , n11685 , n11686 );
buf ( n11688 , n11687 );
nand ( n11689 , n11498 , n11688 );
buf ( n11690 , n11689 );
nand ( n11691 , n11495 , n11690 );
xor ( n11692 , n11456 , n11691 );
and ( n11693 , n11259 , n11364 );
not ( n11694 , n11259 );
and ( n11695 , n11694 , n11367 );
nor ( n11696 , n11693 , n11695 );
and ( n11697 , n11222 , n11696 );
not ( n11698 , n11222 );
not ( n11699 , n11696 );
and ( n11700 , n11698 , n11699 );
nor ( n11701 , n11697 , n11700 );
and ( n11702 , n11692 , n11701 );
and ( n11703 , n11456 , n11691 );
or ( n11704 , n11702 , n11703 );
not ( n11705 , n11704 );
nand ( n11706 , n11447 , n11705 );
xor ( n11707 , n11456 , n11691 );
xor ( n11708 , n11707 , n11701 );
not ( n11709 , n11708 );
not ( n11710 , n11490 );
not ( n11711 , n11710 );
buf ( n11712 , n11480 );
not ( n11713 , n11712 );
buf ( n11714 , n11713 );
not ( n11715 , n11714 );
or ( n11716 , n11711 , n11715 );
buf ( n11717 , n11480 );
buf ( n11718 , n11490 );
nand ( n11719 , n11717 , n11718 );
buf ( n11720 , n11719 );
nand ( n11721 , n11716 , n11720 );
buf ( n11722 , n11687 );
not ( n11723 , n11722 );
buf ( n11724 , n11723 );
and ( n11725 , n11721 , n11724 );
not ( n11726 , n11721 );
and ( n11727 , n11726 , n11687 );
nor ( n11728 , n11725 , n11727 );
buf ( n11729 , n11728 );
xor ( n11730 , n11103 , n11127 );
xor ( n11731 , n11730 , n11218 );
buf ( n11732 , n11731 );
buf ( n11733 , n11732 );
not ( n11734 , n11733 );
buf ( n11735 , n11734 );
buf ( n11736 , n11735 );
nand ( n11737 , n11729 , n11736 );
buf ( n11738 , n11737 );
not ( n11739 , n11738 );
buf ( n11740 , n385 );
not ( n11741 , n11740 );
buf ( n11742 , n11462 );
not ( n11743 , n11742 );
or ( n11744 , n11741 , n11743 );
not ( n11745 , n384 );
not ( n11746 , n10468 );
or ( n11747 , n11745 , n11746 );
not ( n11748 , n384 );
nand ( n11749 , n11748 , n10465 );
nand ( n11750 , n11747 , n11749 );
buf ( n11751 , n11750 );
buf ( n11752 , n11409 );
nand ( n11753 , n11751 , n11752 );
buf ( n11754 , n11753 );
buf ( n11755 , n11754 );
nand ( n11756 , n11744 , n11755 );
buf ( n11757 , n11756 );
buf ( n11758 , n9836 );
not ( n11759 , n11758 );
buf ( n11760 , n11205 );
not ( n11761 , n11760 );
or ( n11762 , n11759 , n11761 );
not ( n11763 , n9738 );
not ( n11764 , n10508 );
not ( n11765 , n10531 );
or ( n11766 , n11764 , n11765 );
nand ( n11767 , n11766 , n10536 );
not ( n11768 , n11767 );
or ( n11769 , n11763 , n11768 );
or ( n11770 , n9738 , n10537 );
nand ( n11771 , n11769 , n11770 );
buf ( n11772 , n11771 );
buf ( n11773 , n9853 );
nand ( n11774 , n11772 , n11773 );
buf ( n11775 , n11774 );
buf ( n11776 , n11775 );
nand ( n11777 , n11762 , n11776 );
buf ( n11778 , n11777 );
not ( n11779 , n11778 );
buf ( n11780 , n11522 );
buf ( n11781 , n11533 );
xor ( n11782 , n11780 , n11781 );
buf ( n11783 , n11549 );
xor ( n11784 , n11782 , n11783 );
buf ( n11785 , n11784 );
not ( n11786 , n11785 );
not ( n11787 , n11786 );
or ( n11788 , n11779 , n11787 );
not ( n11789 , n11785 );
not ( n11790 , n11775 );
and ( n11791 , n9836 , n11205 );
nor ( n11792 , n11790 , n11791 );
not ( n11793 , n11792 );
or ( n11794 , n11789 , n11793 );
not ( n11795 , n2980 );
not ( n11796 , n3033 );
or ( n11797 , n11795 , n11796 );
nand ( n11798 , n11797 , n2841 );
buf ( n11799 , n2489 );
not ( n11800 , n11799 );
buf ( n11801 , n2495 );
nand ( n11802 , n11800 , n11801 );
buf ( n11803 , n11802 );
buf ( n11804 , n11803 );
not ( n11805 , n11804 );
buf ( n11806 , n11805 );
and ( n11807 , n11798 , n11806 );
not ( n11808 , n11798 );
and ( n11809 , n11808 , n11803 );
nor ( n11810 , n11807 , n11809 );
not ( n11811 , n11810 );
buf ( n11812 , n9743 );
not ( n11813 , n11812 );
not ( n11814 , n9732 );
not ( n11815 , n11072 );
or ( n11816 , n11814 , n11815 );
nand ( n11817 , n380 , n11137 );
nand ( n11818 , n11816 , n11817 );
buf ( n11819 , n11818 );
not ( n11820 , n11819 );
or ( n11821 , n11813 , n11820 );
buf ( n11822 , n11678 );
buf ( n11823 , n9745 );
nand ( n11824 , n11822 , n11823 );
buf ( n11825 , n11824 );
buf ( n11826 , n11825 );
nand ( n11827 , n11821 , n11826 );
buf ( n11828 , n11827 );
not ( n11829 , n11828 );
or ( n11830 , n11811 , n11829 );
buf ( n11831 , n11828 );
buf ( n11832 , n11798 );
buf ( n11833 , n11806 );
and ( n11834 , n11832 , n11833 );
not ( n11835 , n11832 );
buf ( n11836 , n11803 );
and ( n11837 , n11835 , n11836 );
nor ( n11838 , n11834 , n11837 );
buf ( n11839 , n11838 );
buf ( n11840 , n11839 );
or ( n11841 , n11831 , n11840 );
buf ( n11842 , n378 );
not ( n11843 , n10154 );
and ( n11844 , n11843 , n5730 );
not ( n11845 , n11843 );
not ( n11846 , n5730 );
and ( n11847 , n11845 , n11846 );
nor ( n11848 , n11844 , n11847 );
buf ( n11849 , n11848 );
and ( n11850 , n11842 , n11849 );
buf ( n11851 , n11850 );
buf ( n11852 , n11851 );
buf ( n11853 , n11626 );
not ( n11854 , n11853 );
buf ( n11855 , n11652 );
not ( n11856 , n11855 );
or ( n11857 , n11854 , n11856 );
buf ( n11858 , n11652 );
buf ( n11859 , n11626 );
or ( n11860 , n11858 , n11859 );
nand ( n11861 , n11857 , n11860 );
buf ( n11862 , n11861 );
buf ( n11863 , n11862 );
xor ( n11864 , n11852 , n11863 );
buf ( n11865 , n9773 );
not ( n11866 , n11865 );
buf ( n11867 , n11579 );
not ( n11868 , n11867 );
or ( n11869 , n11866 , n11868 );
buf ( n11870 , n378 );
not ( n11871 , n11870 );
buf ( n11872 , n11518 );
not ( n11873 , n11872 );
buf ( n11874 , n11873 );
buf ( n11875 , n11874 );
not ( n11876 , n11875 );
or ( n11877 , n11871 , n11876 );
buf ( n11878 , n11518 );
buf ( n11879 , n9776 );
nand ( n11880 , n11878 , n11879 );
buf ( n11881 , n11880 );
buf ( n11882 , n11881 );
nand ( n11883 , n11877 , n11882 );
buf ( n11884 , n11883 );
buf ( n11885 , n11884 );
buf ( n11886 , n9790 );
nand ( n11887 , n11885 , n11886 );
buf ( n11888 , n11887 );
buf ( n11889 , n11888 );
nand ( n11890 , n11869 , n11889 );
buf ( n11891 , n11890 );
buf ( n11892 , n11891 );
and ( n11893 , n11864 , n11892 );
and ( n11894 , n11852 , n11863 );
or ( n11895 , n11893 , n11894 );
buf ( n11896 , n11895 );
buf ( n11897 , n11896 );
nand ( n11898 , n11841 , n11897 );
buf ( n11899 , n11898 );
nand ( n11900 , n11830 , n11899 );
nand ( n11901 , n11794 , n11900 );
nand ( n11902 , n11788 , n11901 );
xor ( n11903 , n11757 , n11902 );
nand ( n11904 , n11191 , n11180 );
xor ( n11905 , n11164 , n11904 );
xnor ( n11906 , n11905 , n11210 );
and ( n11907 , n11903 , n11906 );
and ( n11908 , n11757 , n11902 );
or ( n11909 , n11907 , n11908 );
not ( n11910 , n11909 );
or ( n11911 , n11739 , n11910 );
not ( n11912 , n11735 );
buf ( n11913 , n11728 );
not ( n11914 , n11913 );
buf ( n11915 , n11914 );
nand ( n11916 , n11912 , n11915 );
nand ( n11917 , n11911 , n11916 );
buf ( n11918 , n11917 );
not ( n11919 , n11918 );
buf ( n11920 , n11919 );
nand ( n11921 , n11709 , n11920 );
and ( n11922 , n11706 , n11921 );
buf ( n11923 , n10871 );
buf ( n11924 , n11035 );
xor ( n11925 , n11923 , n11924 );
buf ( n11926 , n11026 );
xor ( n11927 , n11925 , n11926 );
buf ( n11928 , n11927 );
buf ( n11929 , n11928 );
xor ( n11930 , n10589 , n10608 );
xor ( n11931 , n11930 , n10632 );
buf ( n11932 , n11931 );
buf ( n11933 , n11932 );
not ( n11934 , n11933 );
buf ( n11935 , n10930 );
not ( n11936 , n11935 );
buf ( n11937 , n11936 );
buf ( n11938 , n11937 );
not ( n11939 , n11938 );
not ( n11940 , n11022 );
and ( n11941 , n11940 , n10943 );
not ( n11942 , n11940 );
not ( n11943 , n10943 );
and ( n11944 , n11942 , n11943 );
nor ( n11945 , n11941 , n11944 );
not ( n11946 , n11945 );
buf ( n11947 , n11946 );
not ( n11948 , n11947 );
or ( n11949 , n11939 , n11948 );
buf ( n11950 , n10930 );
buf ( n11951 , n11945 );
nand ( n11952 , n11950 , n11951 );
buf ( n11953 , n11952 );
buf ( n11954 , n11953 );
nand ( n11955 , n11949 , n11954 );
buf ( n11956 , n11955 );
buf ( n11957 , n11956 );
not ( n11958 , n11957 );
or ( n11959 , n11934 , n11958 );
buf ( n11960 , n11932 );
buf ( n11961 , n11937 );
not ( n11962 , n11961 );
buf ( n11963 , n11946 );
not ( n11964 , n11963 );
or ( n11965 , n11962 , n11964 );
buf ( n11966 , n11953 );
nand ( n11967 , n11965 , n11966 );
buf ( n11968 , n11967 );
buf ( n11969 , n11968 );
or ( n11970 , n11960 , n11969 );
buf ( n11971 , n11383 );
not ( n11972 , n11971 );
buf ( n11973 , n11391 );
nand ( n11974 , n11972 , n11973 );
buf ( n11975 , n11974 );
buf ( n11976 , n11975 );
not ( n11977 , n11976 );
buf ( n11978 , n11438 );
not ( n11979 , n11978 );
or ( n11980 , n11977 , n11979 );
buf ( n11981 , n11391 );
not ( n11982 , n11981 );
buf ( n11983 , n11383 );
nand ( n11984 , n11982 , n11983 );
buf ( n11985 , n11984 );
buf ( n11986 , n11985 );
nand ( n11987 , n11980 , n11986 );
buf ( n11988 , n11987 );
buf ( n11989 , n11988 );
nand ( n11990 , n11970 , n11989 );
buf ( n11991 , n11990 );
buf ( n11992 , n11991 );
nand ( n11993 , n11959 , n11992 );
buf ( n11994 , n11993 );
buf ( n11995 , n11994 );
not ( n11996 , n11995 );
buf ( n11997 , n11996 );
buf ( n11998 , n11997 );
nand ( n11999 , n11929 , n11998 );
buf ( n12000 , n11999 );
buf ( n12001 , n12000 );
xor ( n12002 , n11932 , n11956 );
xnor ( n12003 , n12002 , n11988 );
xor ( n12004 , n11064 , n11378 );
and ( n12005 , n12004 , n11443 );
and ( n12006 , n11064 , n11378 );
or ( n12007 , n12005 , n12006 );
buf ( n12008 , n12007 );
not ( n12009 , n12008 );
buf ( n12010 , n12009 );
nand ( n12011 , n12003 , n12010 );
buf ( n12012 , n12011 );
and ( n12013 , n12001 , n12012 );
buf ( n12014 , n12013 );
nand ( n12015 , n11922 , n12014 );
buf ( n12016 , n12015 );
not ( n12017 , n12016 );
buf ( n12018 , n12017 );
not ( n12019 , n11665 );
not ( n12020 , n11655 );
not ( n12021 , n12020 );
and ( n12022 , n12019 , n12021 );
and ( n12023 , n11665 , n12020 );
nor ( n12024 , n12022 , n12023 );
and ( n12025 , n12024 , n11586 );
not ( n12026 , n12024 );
not ( n12027 , n11586 );
and ( n12028 , n12026 , n12027 );
nor ( n12029 , n12025 , n12028 );
buf ( n12030 , n12029 );
buf ( n12031 , n9853 );
not ( n12032 , n12031 );
buf ( n12033 , n382 );
not ( n12034 , n12033 );
buf ( n12035 , n10977 );
not ( n12036 , n12035 );
or ( n12037 , n12034 , n12036 );
buf ( n12038 , n10980 );
buf ( n12039 , n9738 );
nand ( n12040 , n12038 , n12039 );
buf ( n12041 , n12040 );
buf ( n12042 , n12041 );
nand ( n12043 , n12037 , n12042 );
buf ( n12044 , n12043 );
buf ( n12045 , n12044 );
not ( n12046 , n12045 );
or ( n12047 , n12032 , n12046 );
buf ( n12048 , n11771 );
buf ( n12049 , n9836 );
nand ( n12050 , n12048 , n12049 );
buf ( n12051 , n12050 );
buf ( n12052 , n12051 );
nand ( n12053 , n12047 , n12052 );
buf ( n12054 , n12053 );
buf ( n12055 , n12054 );
xor ( n12056 , n12030 , n12055 );
buf ( n12057 , n385 );
not ( n12058 , n12057 );
and ( n12059 , n384 , n10914 );
not ( n12060 , n384 );
and ( n12061 , n12060 , n10485 );
or ( n12062 , n12059 , n12061 );
buf ( n12063 , n12062 );
not ( n12064 , n12063 );
or ( n12065 , n12058 , n12064 );
xor ( n12066 , n384 , n10341 );
buf ( n12067 , n12066 );
buf ( n12068 , n11409 );
nand ( n12069 , n12067 , n12068 );
buf ( n12070 , n12069 );
buf ( n12071 , n12070 );
nand ( n12072 , n12065 , n12071 );
buf ( n12073 , n12072 );
buf ( n12074 , n12073 );
xnor ( n12075 , n12056 , n12074 );
buf ( n12076 , n12075 );
buf ( n12077 , n12076 );
not ( n12078 , n12077 );
buf ( n12079 , n385 );
not ( n12080 , n12079 );
buf ( n12081 , n12066 );
not ( n12082 , n12081 );
or ( n12083 , n12080 , n12082 );
and ( n12084 , n11767 , n384 );
not ( n12085 , n11767 );
not ( n12086 , n384 );
and ( n12087 , n12085 , n12086 );
nor ( n12088 , n12084 , n12087 );
nand ( n12089 , n11409 , n12088 );
buf ( n12090 , n12089 );
nand ( n12091 , n12083 , n12090 );
buf ( n12092 , n12091 );
buf ( n12093 , n12092 );
not ( n12094 , n2837 );
nand ( n12095 , n12094 , n2484 );
not ( n12096 , n12095 );
not ( n12097 , n3007 );
nand ( n12098 , n2954 , n2976 , n12097 );
not ( n12099 , n12098 );
or ( n12100 , n12096 , n12099 );
nor ( n12101 , n3007 , n12095 );
nand ( n12102 , n2954 , n2976 , n12101 );
nand ( n12103 , n12100 , n12102 );
buf ( n12104 , n8181 );
buf ( n12105 , n12104 );
buf ( n12106 , n12105 );
not ( n12107 , n12106 );
buf ( n12108 , n11615 );
buf ( n12109 , n7661 );
nand ( n12110 , n12108 , n12109 );
buf ( n12111 , n12110 );
not ( n12112 , n12111 );
not ( n12113 , n12112 );
or ( n12114 , n12107 , n12113 );
not ( n12115 , n12111 );
or ( n12116 , n12106 , n12115 );
nand ( n12117 , n12114 , n12116 );
not ( n12118 , n394 );
nor ( n12119 , n12117 , n12118 );
buf ( n12120 , n12119 );
not ( n12121 , n11608 );
not ( n12122 , n11625 );
or ( n12123 , n12121 , n12122 );
or ( n12124 , n11608 , n11625 );
nand ( n12125 , n12123 , n12124 );
buf ( n12126 , n12125 );
xor ( n12127 , n12120 , n12126 );
buf ( n12128 , n9773 );
not ( n12129 , n12128 );
buf ( n12130 , n11884 );
not ( n12131 , n12130 );
or ( n12132 , n12129 , n12131 );
xor ( n12133 , n11842 , n11849 );
buf ( n12134 , n12133 );
buf ( n12135 , n12134 );
buf ( n12136 , n9790 );
nand ( n12137 , n12135 , n12136 );
buf ( n12138 , n12137 );
buf ( n12139 , n12138 );
nand ( n12140 , n12132 , n12139 );
buf ( n12141 , n12140 );
buf ( n12142 , n12141 );
and ( n12143 , n12127 , n12142 );
and ( n12144 , n12120 , n12126 );
or ( n12145 , n12143 , n12144 );
buf ( n12146 , n12145 );
not ( n12147 , n12146 );
xor ( n12148 , n12103 , n12147 );
not ( n12149 , n9745 );
not ( n12150 , n11818 );
or ( n12151 , n12149 , n12150 );
not ( n12152 , n11267 );
not ( n12153 , n11271 );
or ( n12154 , n12152 , n12153 );
nand ( n12155 , n12154 , n11277 );
and ( n12156 , n12155 , n380 );
not ( n12157 , n12155 );
not ( n12158 , n380 );
and ( n12159 , n12157 , n12158 );
nor ( n12160 , n12156 , n12159 );
nand ( n12161 , n9743 , n12160 );
nand ( n12162 , n12151 , n12161 );
xnor ( n12163 , n12148 , n12162 );
buf ( n12164 , n12163 );
xor ( n12165 , n12093 , n12164 );
xor ( n12166 , n12120 , n12126 );
xor ( n12167 , n12166 , n12142 );
buf ( n12168 , n12167 );
buf ( n12169 , n12168 );
buf ( n12170 , n9773 );
not ( n12171 , n12170 );
buf ( n12172 , n12134 );
not ( n12173 , n12172 );
or ( n12174 , n12171 , n12173 );
buf ( n12175 , n378 );
not ( n12176 , n12175 );
buf ( n12177 , n11607 );
not ( n12178 , n12177 );
buf ( n12179 , n12178 );
buf ( n12180 , n12179 );
not ( n12181 , n12180 );
or ( n12182 , n12176 , n12181 );
buf ( n12183 , n11604 );
buf ( n12184 , n12183 );
buf ( n12185 , n12184 );
buf ( n12186 , n12185 );
buf ( n12187 , n9776 );
nand ( n12188 , n12186 , n12187 );
buf ( n12189 , n12188 );
buf ( n12190 , n12189 );
nand ( n12191 , n12182 , n12190 );
buf ( n12192 , n12191 );
buf ( n12193 , n12192 );
buf ( n12194 , n9790 );
nand ( n12195 , n12193 , n12194 );
buf ( n12196 , n12195 );
buf ( n12197 , n12196 );
nand ( n12198 , n12174 , n12197 );
buf ( n12199 , n12198 );
buf ( n12200 , n12199 );
buf ( n12201 , n7850 );
not ( n12202 , n12201 );
buf ( n12203 , n7810 );
nand ( n12204 , n12202 , n12203 );
buf ( n12205 , n12204 );
and ( n12206 , n12205 , n7851 );
buf ( n12207 , n8128 );
xor ( n12208 , n12206 , n12207 );
and ( n12209 , n396 , n12208 );
buf ( n12210 , n395 );
and ( n12211 , n8178 , n8172 );
buf ( n12212 , n8139 );
xor ( n12213 , n12211 , n12212 );
buf ( n12214 , n12213 );
xor ( n12215 , n12210 , n12214 );
buf ( n12216 , n11604 );
not ( n12217 , n12216 );
buf ( n12218 , n9774 );
nor ( n12219 , n12217 , n12218 );
buf ( n12220 , n12219 );
buf ( n12221 , n12220 );
xor ( n12222 , n12215 , n12221 );
buf ( n12223 , n12222 );
xor ( n12224 , n12209 , n12223 );
xor ( n12225 , n396 , n12208 );
not ( n12226 , n12225 );
buf ( n12227 , n398 );
not ( n12228 , n8112 );
not ( n12229 , n8106 );
or ( n12230 , n12228 , n12229 );
nand ( n12231 , n12230 , n8045 );
nand ( n12232 , n8102 , n399 );
and ( n12233 , n12231 , n12232 );
not ( n12234 , n12231 );
not ( n12235 , n8102 );
nand ( n12236 , n12235 , n399 );
and ( n12237 , n12234 , n12236 );
nor ( n12238 , n12233 , n12237 );
buf ( n12239 , n12238 );
xor ( n12240 , n12227 , n12239 );
buf ( n12241 , n8018 );
not ( n12242 , n12241 );
buf ( n12243 , n8120 );
nand ( n12244 , n12242 , n12243 );
buf ( n12245 , n12244 );
xor ( n12246 , n8114 , n12245 );
buf ( n12247 , n12246 );
and ( n12248 , n12240 , n12247 );
and ( n12249 , n12227 , n12239 );
or ( n12250 , n12248 , n12249 );
buf ( n12251 , n12250 );
and ( n12252 , n397 , n12251 );
not ( n12253 , n12252 );
nand ( n12254 , n12226 , n12253 );
not ( n12255 , n12254 );
buf ( n12256 , n9738 );
buf ( n12257 , n9731 );
nand ( n12258 , n12256 , n12257 );
buf ( n12259 , n12258 );
not ( n12260 , n12259 );
not ( n12261 , n11607 );
or ( n12262 , n12260 , n12261 );
buf ( n12263 , n381 );
buf ( n12264 , n382 );
and ( n12265 , n12263 , n12264 );
buf ( n12266 , n9732 );
nor ( n12267 , n12265 , n12266 );
buf ( n12268 , n12267 );
nand ( n12269 , n12262 , n12268 );
not ( n12270 , n12269 );
not ( n12271 , n12270 );
or ( n12272 , n12255 , n12271 );
nand ( n12273 , n12225 , n12252 );
nand ( n12274 , n12272 , n12273 );
and ( n12275 , n12224 , n12274 );
and ( n12276 , n12209 , n12223 );
or ( n12277 , n12275 , n12276 );
buf ( n12278 , n12277 );
xor ( n12279 , n12200 , n12278 );
buf ( n12280 , n9732 );
buf ( n12281 , n9780 );
nand ( n12282 , n12280 , n12281 );
buf ( n12283 , n12282 );
buf ( n12284 , n12283 );
not ( n12285 , n12284 );
buf ( n12286 , n11607 );
not ( n12287 , n12286 );
or ( n12288 , n12285 , n12287 );
buf ( n12289 , n379 );
buf ( n12290 , n380 );
and ( n12291 , n12289 , n12290 );
buf ( n12292 , n9776 );
nor ( n12293 , n12291 , n12292 );
buf ( n12294 , n12293 );
buf ( n12295 , n12294 );
nand ( n12296 , n12288 , n12295 );
buf ( n12297 , n12296 );
not ( n12298 , n12118 );
not ( n12299 , n12106 );
not ( n12300 , n12112 );
or ( n12301 , n12299 , n12300 );
or ( n12302 , n12106 , n12115 );
nand ( n12303 , n12301 , n12302 );
not ( n12304 , n12303 );
or ( n12305 , n12298 , n12304 );
or ( n12306 , n12117 , n12118 );
nand ( n12307 , n12305 , n12306 );
not ( n12308 , n12307 );
xor ( n12309 , n12297 , n12308 );
xor ( n12310 , n12210 , n12214 );
and ( n12311 , n12310 , n12221 );
and ( n12312 , n12210 , n12214 );
or ( n12313 , n12311 , n12312 );
buf ( n12314 , n12313 );
xnor ( n12315 , n12309 , n12314 );
buf ( n12316 , n12315 );
and ( n12317 , n12279 , n12316 );
and ( n12318 , n12200 , n12278 );
or ( n12319 , n12317 , n12318 );
buf ( n12320 , n12319 );
buf ( n12321 , n12320 );
xor ( n12322 , n12169 , n12321 );
not ( n12323 , n9836 );
buf ( n12324 , n382 );
not ( n12325 , n12324 );
buf ( n12326 , n10880 );
not ( n12327 , n12326 );
or ( n12328 , n12325 , n12327 );
buf ( n12329 , n10883 );
buf ( n12330 , n9738 );
nand ( n12331 , n12329 , n12330 );
buf ( n12332 , n12331 );
buf ( n12333 , n12332 );
nand ( n12334 , n12328 , n12333 );
buf ( n12335 , n12334 );
not ( n12336 , n12335 );
or ( n12337 , n12323 , n12336 );
not ( n12338 , n382 );
not ( n12339 , n11137 );
or ( n12340 , n12338 , n12339 );
buf ( n12341 , n11072 );
buf ( n12342 , n9738 );
nand ( n12343 , n12341 , n12342 );
buf ( n12344 , n12343 );
nand ( n12345 , n12340 , n12344 );
nand ( n12346 , n12345 , n9853 );
nand ( n12347 , n12337 , n12346 );
buf ( n12348 , n12347 );
and ( n12349 , n12322 , n12348 );
and ( n12350 , n12169 , n12321 );
or ( n12351 , n12349 , n12350 );
buf ( n12352 , n12351 );
buf ( n12353 , n12352 );
and ( n12354 , n12165 , n12353 );
and ( n12355 , n12093 , n12164 );
or ( n12356 , n12354 , n12355 );
buf ( n12357 , n12356 );
buf ( n12358 , n12357 );
not ( n12359 , n12358 );
or ( n12360 , n12078 , n12359 );
buf ( n12361 , n12357 );
buf ( n12362 , n12076 );
or ( n12363 , n12361 , n12362 );
nand ( n12364 , n12360 , n12363 );
buf ( n12365 , n12364 );
buf ( n12366 , n12365 );
not ( n12367 , n12103 );
not ( n12368 , n12367 );
not ( n12369 , n12147 );
or ( n12370 , n12368 , n12369 );
nand ( n12371 , n12370 , n12162 );
nand ( n12372 , n12146 , n12103 );
nand ( n12373 , n12371 , n12372 );
buf ( n12374 , n12373 );
xor ( n12375 , n11810 , n11896 );
xnor ( n12376 , n12375 , n11828 );
buf ( n12377 , n12376 );
xor ( n12378 , n12374 , n12377 );
xor ( n12379 , n11852 , n11863 );
xor ( n12380 , n12379 , n11892 );
buf ( n12381 , n12380 );
buf ( n12382 , n12381 );
buf ( n12383 , n9836 );
not ( n12384 , n12383 );
buf ( n12385 , n12044 );
not ( n12386 , n12385 );
or ( n12387 , n12384 , n12386 );
buf ( n12388 , n12335 );
buf ( n12389 , n9853 );
nand ( n12390 , n12388 , n12389 );
buf ( n12391 , n12390 );
buf ( n12392 , n12391 );
nand ( n12393 , n12387 , n12392 );
buf ( n12394 , n12393 );
buf ( n12395 , n12394 );
xor ( n12396 , n12382 , n12395 );
not ( n12397 , n9745 );
not ( n12398 , n12160 );
or ( n12399 , n12397 , n12398 );
buf ( n12400 , n380 );
not ( n12401 , n12400 );
not ( n12402 , n11342 );
buf ( n12403 , n12402 );
not ( n12404 , n12403 );
or ( n12405 , n12401 , n12404 );
buf ( n12406 , n11342 );
buf ( n12407 , n9732 );
nand ( n12408 , n12406 , n12407 );
buf ( n12409 , n12408 );
buf ( n12410 , n12409 );
nand ( n12411 , n12405 , n12410 );
buf ( n12412 , n12411 );
buf ( n12413 , n12412 );
buf ( n12414 , n9743 );
nand ( n12415 , n12413 , n12414 );
buf ( n12416 , n12415 );
nand ( n12417 , n12399 , n12416 );
not ( n12418 , n12417 );
not ( n12419 , n2479 );
nor ( n12420 , n12419 , n2477 );
not ( n12421 , n12420 );
not ( n12422 , n2905 );
nor ( n12423 , n12422 , n2917 );
not ( n12424 , n12423 );
nand ( n12425 , n2884 , n2948 );
not ( n12426 , n12425 );
or ( n12427 , n12424 , n12426 );
not ( n12428 , n2890 );
nor ( n12429 , n2917 , n12428 );
nand ( n12430 , n2969 , n2471 );
nor ( n12431 , n12429 , n12430 );
nand ( n12432 , n12427 , n12431 );
not ( n12433 , n2471 );
nand ( n12434 , n2465 , n2443 );
not ( n12435 , n12434 );
or ( n12436 , n12433 , n12435 );
nand ( n12437 , n12436 , n2476 );
nor ( n12438 , C0 , n12437 );
nand ( n12439 , n12432 , n12438 );
not ( n12440 , n12439 );
or ( n12441 , n12421 , n12440 );
not ( n12442 , n12420 );
nand ( n12443 , n12438 , n12432 , n12442 );
nand ( n12444 , n12441 , n12443 );
nand ( n12445 , n12418 , n12444 );
not ( n12446 , n12445 );
not ( n12447 , n12308 );
not ( n12448 , n12297 );
not ( n12449 , n12448 );
or ( n12450 , n12447 , n12449 );
not ( n12451 , n12297 );
not ( n12452 , n12307 );
or ( n12453 , n12451 , n12452 );
nand ( n12454 , n12453 , n12314 );
nand ( n12455 , n12450 , n12454 );
not ( n12456 , n12455 );
or ( n12457 , n12446 , n12456 );
not ( n12458 , n12444 );
nand ( n12459 , n12458 , n12417 );
nand ( n12460 , n12457 , n12459 );
buf ( n12461 , n12460 );
and ( n12462 , n12396 , n12461 );
and ( n12463 , n12382 , n12395 );
or ( n12464 , n12462 , n12463 );
buf ( n12465 , n12464 );
buf ( n12466 , n12465 );
xor ( n12467 , n12378 , n12466 );
buf ( n12468 , n12467 );
buf ( n12469 , n12468 );
and ( n12470 , n12366 , n12469 );
not ( n12471 , n12366 );
buf ( n12472 , n12468 );
not ( n12473 , n12472 );
buf ( n12474 , n12473 );
buf ( n12475 , n12474 );
and ( n12476 , n12471 , n12475 );
nor ( n12477 , n12470 , n12476 );
buf ( n12478 , n12477 );
buf ( n12479 , n12478 );
xor ( n12480 , n12382 , n12395 );
xor ( n12481 , n12480 , n12461 );
buf ( n12482 , n12481 );
buf ( n12483 , n12482 );
not ( n12484 , n12483 );
buf ( n12485 , n12484 );
buf ( n12486 , n12485 );
not ( n12487 , n12486 );
not ( n12488 , n385 );
not ( n12489 , n12088 );
or ( n12490 , n12488 , n12489 );
not ( n12491 , n384 );
not ( n12492 , n10977 );
or ( n12493 , n12491 , n12492 );
buf ( n12494 , n384 );
not ( n12495 , n12494 );
buf ( n12496 , n12495 );
nand ( n12497 , n11186 , n12496 );
nand ( n12498 , n12493 , n12497 );
nand ( n12499 , n12498 , n11409 );
nand ( n12500 , n12490 , n12499 );
not ( n12501 , n12500 );
buf ( n12502 , n9745 );
not ( n12503 , n12502 );
buf ( n12504 , n12412 );
not ( n12505 , n12504 );
or ( n12506 , n12503 , n12505 );
buf ( n12507 , n380 );
buf ( n12508 , n11518 );
and ( n12509 , n12507 , n12508 );
not ( n12510 , n12507 );
buf ( n12511 , n11874 );
and ( n12512 , n12510 , n12511 );
nor ( n12513 , n12509 , n12512 );
buf ( n12514 , n12513 );
buf ( n12515 , n12514 );
buf ( n12516 , n9743 );
nand ( n12517 , n12515 , n12516 );
buf ( n12518 , n12517 );
buf ( n12519 , n12518 );
nand ( n12520 , n12506 , n12519 );
buf ( n12521 , n12520 );
buf ( n12522 , n12521 );
nand ( n12523 , n2925 , n2969 , n2936 );
not ( n12524 , n12434 );
nand ( n12525 , n2972 , n12523 , n12524 );
nand ( n12526 , n2471 , n2476 );
xnor ( n12527 , n12525 , n12526 );
buf ( n12528 , n12527 );
xor ( n12529 , n12522 , n12528 );
buf ( n12530 , n9836 );
not ( n12531 , n12530 );
buf ( n12532 , n12345 );
not ( n12533 , n12532 );
or ( n12534 , n12531 , n12533 );
not ( n12535 , n382 );
not ( n12536 , n12155 );
not ( n12537 , n12536 );
or ( n12538 , n12535 , n12537 );
buf ( n12539 , n9738 );
buf ( n12540 , n12155 );
nand ( n12541 , n12539 , n12540 );
buf ( n12542 , n12541 );
nand ( n12543 , n12538 , n12542 );
buf ( n12544 , n12543 );
buf ( n12545 , n9853 );
nand ( n12546 , n12544 , n12545 );
buf ( n12547 , n12546 );
buf ( n12548 , n12547 );
nand ( n12549 , n12534 , n12548 );
buf ( n12550 , n12549 );
buf ( n12551 , n12550 );
and ( n12552 , n12529 , n12551 );
and ( n12553 , n12522 , n12528 );
or ( n12554 , n12552 , n12553 );
buf ( n12555 , n12554 );
not ( n12556 , n12555 );
or ( n12557 , n12501 , n12556 );
buf ( n12558 , n12555 );
buf ( n12559 , n12500 );
or ( n12560 , n12558 , n12559 );
xor ( n12561 , n12455 , n12444 );
xnor ( n12562 , n12561 , n12417 );
buf ( n12563 , n12562 );
nand ( n12564 , n12560 , n12563 );
buf ( n12565 , n12564 );
nand ( n12566 , n12557 , n12565 );
not ( n12567 , n12566 );
buf ( n12568 , n12567 );
not ( n12569 , n12568 );
or ( n12570 , n12487 , n12569 );
xor ( n12571 , n12093 , n12164 );
xor ( n12572 , n12571 , n12353 );
buf ( n12573 , n12572 );
buf ( n12574 , n12573 );
nand ( n12575 , n12570 , n12574 );
buf ( n12576 , n12575 );
buf ( n12577 , n12576 );
buf ( n12578 , n12485 );
buf ( n12579 , n12567 );
or ( n12580 , n12578 , n12579 );
buf ( n12581 , n12580 );
buf ( n12582 , n12581 );
and ( n12583 , n12577 , n12582 );
buf ( n12584 , n12583 );
buf ( n12585 , n12584 );
nand ( n12586 , n12479 , n12585 );
buf ( n12587 , n12586 );
not ( n12588 , n12587 );
buf ( n12589 , n11607 );
buf ( n12590 , n9745 );
and ( n12591 , n12589 , n12590 );
buf ( n12592 , n12591 );
buf ( n12593 , n8127 );
buf ( n12594 , n7923 );
not ( n12595 , n12594 );
buf ( n12596 , n7940 );
nand ( n12597 , n12595 , n12596 );
buf ( n12598 , n12597 );
buf ( n12599 , n12598 );
nand ( n12600 , n12593 , n12599 );
buf ( n12601 , n12600 );
buf ( n12602 , n12601 );
buf ( n12603 , n8123 );
xnor ( n12604 , n12602 , n12603 );
buf ( n12605 , n12604 );
xor ( n12606 , n397 , n12251 );
and ( n12607 , n12605 , n12606 );
not ( n12608 , n12605 );
not ( n12609 , n12606 );
and ( n12610 , n12608 , n12609 );
nor ( n12611 , n12607 , n12610 );
xor ( n12612 , n12592 , n12611 );
not ( n12613 , n9836 );
not ( n12614 , n382 );
not ( n12615 , n11874 );
or ( n12616 , n12614 , n12615 );
buf ( n12617 , n11518 );
buf ( n12618 , n9738 );
nand ( n12619 , n12617 , n12618 );
buf ( n12620 , n12619 );
nand ( n12621 , n12616 , n12620 );
not ( n12622 , n12621 );
or ( n12623 , n12613 , n12622 );
buf ( n12624 , n382 );
not ( n12625 , n12624 );
buf ( n12626 , n11848 );
not ( n12627 , n12626 );
buf ( n12628 , n12627 );
buf ( n12629 , n12628 );
not ( n12630 , n12629 );
or ( n12631 , n12625 , n12630 );
buf ( n12632 , n9738 );
buf ( n12633 , n11848 );
nand ( n12634 , n12632 , n12633 );
buf ( n12635 , n12634 );
buf ( n12636 , n12635 );
nand ( n12637 , n12631 , n12636 );
buf ( n12638 , n12637 );
buf ( n12639 , n12638 );
buf ( n12640 , n9853 );
nand ( n12641 , n12639 , n12640 );
buf ( n12642 , n12641 );
nand ( n12643 , n12623 , n12642 );
xor ( n12644 , n12612 , n12643 );
nand ( n12645 , C1 , n3002 );
nand ( n12646 , n2889 , n2916 );
not ( n12647 , n12646 );
and ( n12648 , n12645 , n12647 );
not ( n12649 , n12645 );
and ( n12650 , n12649 , n12646 );
nor ( n12651 , n12648 , n12650 );
and ( n12652 , n12644 , n12651 );
and ( n12653 , n12612 , n12643 );
or ( n12654 , n12652 , n12653 );
not ( n12655 , n12654 );
nand ( n12656 , n2761 , n2456 );
nand ( n12657 , C1 , n2987 );
or ( n12658 , n12656 , n12657 );
nand ( n12659 , n12657 , n12656 );
nand ( n12660 , n12658 , n12659 );
not ( n12661 , n12660 );
buf ( n12662 , n382 );
not ( n12663 , n12662 );
buf ( n12664 , n12402 );
not ( n12665 , n12664 );
or ( n12666 , n12663 , n12665 );
buf ( n12667 , n9738 );
buf ( n12668 , n11342 );
nand ( n12669 , n12667 , n12668 );
buf ( n12670 , n12669 );
buf ( n12671 , n12670 );
nand ( n12672 , n12666 , n12671 );
buf ( n12673 , n12672 );
and ( n12674 , n12673 , n9836 );
and ( n12675 , n12621 , n9853 );
nor ( n12676 , n12674 , n12675 );
nand ( n12677 , n12661 , n12676 );
not ( n12678 , n12677 );
or ( n12679 , n12655 , n12678 );
not ( n12680 , n12676 );
nand ( n12681 , n12680 , n12660 );
nand ( n12682 , n12679 , n12681 );
not ( n12683 , n12682 );
buf ( n12684 , n12683 );
not ( n12685 , n12684 );
not ( n12686 , n9836 );
not ( n12687 , n12543 );
or ( n12688 , n12686 , n12687 );
nand ( n12689 , n12673 , n9853 );
nand ( n12690 , n12688 , n12689 );
buf ( n12691 , n12690 );
not ( n12692 , n12605 );
nand ( n12693 , n12692 , n12609 );
not ( n12694 , n12693 );
not ( n12695 , n12592 );
or ( n12696 , n12694 , n12695 );
nand ( n12697 , n12606 , n12605 );
nand ( n12698 , n12696 , n12697 );
buf ( n12699 , n12698 );
not ( n12700 , n12699 );
buf ( n12701 , n9745 );
not ( n12702 , n12701 );
buf ( n12703 , n380 );
not ( n12704 , n12703 );
buf ( n12705 , n12628 );
not ( n12706 , n12705 );
or ( n12707 , n12704 , n12706 );
buf ( n12708 , n9732 );
buf ( n12709 , n11848 );
nand ( n12710 , n12708 , n12709 );
buf ( n12711 , n12710 );
buf ( n12712 , n12711 );
nand ( n12713 , n12707 , n12712 );
buf ( n12714 , n12713 );
buf ( n12715 , n12714 );
not ( n12716 , n12715 );
or ( n12717 , n12702 , n12716 );
buf ( n12718 , n12185 );
buf ( n12719 , n9732 );
nand ( n12720 , n12718 , n12719 );
buf ( n12721 , n12720 );
buf ( n12722 , n12721 );
not ( n12723 , n12722 );
not ( n12724 , n12185 );
buf ( n12725 , n12724 );
buf ( n12726 , n380 );
nand ( n12727 , n12725 , n12726 );
buf ( n12728 , n12727 );
buf ( n12729 , n12728 );
not ( n12730 , n12729 );
or ( n12731 , n12723 , n12730 );
buf ( n12732 , n9743 );
nand ( n12733 , n12731 , n12732 );
buf ( n12734 , n12733 );
buf ( n12735 , n12734 );
nand ( n12736 , n12717 , n12735 );
buf ( n12737 , n12736 );
buf ( n12738 , n12737 );
not ( n12739 , n12738 );
or ( n12740 , n12700 , n12739 );
or ( n12741 , n12737 , n12698 );
xor ( n12742 , n12225 , n12253 );
xnor ( n12743 , n12742 , n12269 );
not ( n12744 , n12743 );
nand ( n12745 , n12741 , n12744 );
buf ( n12746 , n12745 );
nand ( n12747 , n12740 , n12746 );
buf ( n12748 , n12747 );
buf ( n12749 , n12748 );
xnor ( n12750 , n12691 , n12749 );
buf ( n12751 , n12750 );
buf ( n12752 , n12751 );
not ( n12753 , n12752 );
not ( n12754 , n385 );
and ( n12755 , n384 , n10880 );
not ( n12756 , n384 );
and ( n12757 , n12756 , n10883 );
or ( n12758 , n12755 , n12757 );
not ( n12759 , n12758 );
or ( n12760 , n12754 , n12759 );
not ( n12761 , n384 );
not ( n12762 , n11137 );
or ( n12763 , n12761 , n12762 );
not ( n12764 , n384 );
nand ( n12765 , n12764 , n11072 );
nand ( n12766 , n12763 , n12765 );
nand ( n12767 , n12766 , n11409 );
nand ( n12768 , n12760 , n12767 );
buf ( n12769 , n12768 );
not ( n12770 , n12769 );
and ( n12771 , n12753 , n12770 );
buf ( n12772 , n12768 );
buf ( n12773 , n12751 );
and ( n12774 , n12772 , n12773 );
nor ( n12775 , n12771 , n12774 );
buf ( n12776 , n12775 );
buf ( n12777 , n12776 );
not ( n12778 , n12777 );
or ( n12779 , n12685 , n12778 );
buf ( n12780 , n9745 );
not ( n12781 , n12780 );
buf ( n12782 , n12514 );
not ( n12783 , n12782 );
or ( n12784 , n12781 , n12783 );
buf ( n12785 , n12714 );
buf ( n12786 , n9743 );
nand ( n12787 , n12785 , n12786 );
buf ( n12788 , n12787 );
buf ( n12789 , n12788 );
nand ( n12790 , n12784 , n12789 );
buf ( n12791 , n12790 );
xor ( n12792 , n12209 , n12223 );
xor ( n12793 , n12792 , n12274 );
xor ( n12794 , n12791 , n12793 );
xnor ( n12795 , n12794 , n3046 );
not ( n12796 , n12795 );
buf ( n12797 , n12796 );
nand ( n12798 , n12779 , n12797 );
buf ( n12799 , n12798 );
buf ( n12800 , n12799 );
buf ( n12801 , n12776 );
not ( n12802 , n12801 );
buf ( n12803 , n12682 );
nand ( n12804 , n12802 , n12803 );
buf ( n12805 , n12804 );
buf ( n12806 , n12805 );
nand ( n12807 , n12800 , n12806 );
buf ( n12808 , n12807 );
buf ( n12809 , n12808 );
xor ( n12810 , n12522 , n12528 );
xor ( n12811 , n12810 , n12551 );
buf ( n12812 , n12811 );
buf ( n12813 , n12812 );
buf ( n12814 , n12690 );
buf ( n12815 , n12814 );
buf ( n12816 , n12815 );
buf ( n12817 , n12816 );
not ( n12818 , n12817 );
buf ( n12819 , n12768 );
not ( n12820 , n12819 );
or ( n12821 , n12818 , n12820 );
buf ( n12822 , n12768 );
buf ( n12823 , n12816 );
or ( n12824 , n12822 , n12823 );
buf ( n12825 , n12748 );
nand ( n12826 , n12824 , n12825 );
buf ( n12827 , n12826 );
buf ( n12828 , n12827 );
nand ( n12829 , n12821 , n12828 );
buf ( n12830 , n12829 );
buf ( n12831 , n12830 );
xor ( n12832 , n12813 , n12831 );
xor ( n12833 , n12200 , n12278 );
xor ( n12834 , n12833 , n12316 );
buf ( n12835 , n12834 );
buf ( n12836 , n12835 );
not ( n12837 , n12791 );
not ( n12838 , n12793 );
or ( n12839 , n12837 , n12838 );
or ( n12840 , n12791 , n12793 );
nand ( n12841 , n12840 , n3046 );
nand ( n12842 , n12839 , n12841 );
buf ( n12843 , n12842 );
xor ( n12844 , n12836 , n12843 );
buf ( n12845 , n385 );
not ( n12846 , n12845 );
buf ( n12847 , n12498 );
not ( n12848 , n12847 );
or ( n12849 , n12846 , n12848 );
buf ( n12850 , n12758 );
buf ( n12851 , n11409 );
nand ( n12852 , n12850 , n12851 );
buf ( n12853 , n12852 );
buf ( n12854 , n12853 );
nand ( n12855 , n12849 , n12854 );
buf ( n12856 , n12855 );
buf ( n12857 , n12856 );
xor ( n12858 , n12844 , n12857 );
buf ( n12859 , n12858 );
buf ( n12860 , n12859 );
xor ( n12861 , n12832 , n12860 );
buf ( n12862 , n12861 );
buf ( n12863 , n12862 );
xor ( n12864 , n12809 , n12863 );
not ( n12865 , n12744 );
buf ( n12866 , n12698 );
not ( n12867 , n12866 );
buf ( n12868 , n12867 );
not ( n12869 , n12868 );
or ( n12870 , n12865 , n12869 );
nand ( n12871 , n12743 , n12698 );
nand ( n12872 , n12870 , n12871 );
not ( n12873 , n12737 );
and ( n12874 , n12872 , n12873 );
not ( n12875 , n12872 );
and ( n12876 , n12875 , n12737 );
nor ( n12877 , n12874 , n12876 );
not ( n12878 , n12877 );
buf ( n12879 , n12878 );
not ( n12880 , n12879 );
not ( n12881 , n385 );
not ( n12882 , n12766 );
or ( n12883 , n12881 , n12882 );
and ( n12884 , n384 , n12536 );
not ( n12885 , n384 );
and ( n12886 , n12885 , n12155 );
or ( n12887 , n12884 , n12886 );
nand ( n12888 , n12887 , n11409 );
nand ( n12889 , n12883 , n12888 );
buf ( n12890 , n12889 );
not ( n12891 , n12890 );
or ( n12892 , n12880 , n12891 );
buf ( n12893 , n12889 );
not ( n12894 , n12893 );
buf ( n12895 , n12877 );
nand ( n12896 , n12894 , n12895 );
buf ( n12897 , n12896 );
not ( n12898 , n385 );
not ( n12899 , n12887 );
or ( n12900 , n12898 , n12899 );
buf ( n12901 , n384 );
buf ( n12902 , n11342 );
and ( n12903 , n12901 , n12902 );
not ( n12904 , n12901 );
buf ( n12905 , n12402 );
and ( n12906 , n12904 , n12905 );
nor ( n12907 , n12903 , n12906 );
buf ( n12908 , n12907 );
buf ( n12909 , n12908 );
buf ( n12910 , n11409 );
nand ( n12911 , n12909 , n12910 );
buf ( n12912 , n12911 );
nand ( n12913 , n12900 , n12912 );
not ( n12914 , n12913 );
xor ( n12915 , n12227 , n12239 );
xor ( n12916 , n12915 , n12247 );
buf ( n12917 , n12916 );
buf ( n12918 , n12917 );
buf ( n12919 , n384 );
not ( n12920 , n12919 );
buf ( n12921 , n9845 );
nand ( n12922 , n12920 , n12921 );
buf ( n12923 , n12922 );
buf ( n12924 , n12923 );
not ( n12925 , n12924 );
buf ( n12926 , n12185 );
not ( n12927 , n12926 );
or ( n12928 , n12925 , n12927 );
buf ( n12929 , n383 );
buf ( n12930 , n384 );
and ( n12931 , n12929 , n12930 );
buf ( n12932 , n9738 );
nor ( n12933 , n12931 , n12932 );
buf ( n12934 , n12933 );
buf ( n12935 , n12934 );
nand ( n12936 , n12928 , n12935 );
buf ( n12937 , n12936 );
buf ( n12938 , n12937 );
not ( n12939 , n12938 );
buf ( n12940 , n12939 );
buf ( n12941 , n12940 );
xor ( n12942 , n12918 , n12941 );
buf ( n12943 , n9836 );
not ( n12944 , n12943 );
buf ( n12945 , n12638 );
not ( n12946 , n12945 );
or ( n12947 , n12944 , n12946 );
not ( n12948 , n12185 );
nand ( n12949 , n12948 , n382 );
not ( n12950 , n12949 );
buf ( n12951 , n12185 );
buf ( n12952 , n9738 );
nand ( n12953 , n12951 , n12952 );
buf ( n12954 , n12953 );
not ( n12955 , n12954 );
or ( n12956 , n12950 , n12955 );
nand ( n12957 , n12956 , n9853 );
buf ( n12958 , n12957 );
nand ( n12959 , n12947 , n12958 );
buf ( n12960 , n12959 );
buf ( n12961 , n12960 );
and ( n12962 , n12942 , n12961 );
and ( n12963 , n12918 , n12941 );
or ( n12964 , n12962 , n12963 );
buf ( n12965 , n12964 );
not ( n12966 , n12965 );
or ( n12967 , n12914 , n12966 );
buf ( n12968 , n12965 );
buf ( n12969 , n12913 );
or ( n12970 , n12968 , n12969 );
xor ( n12971 , n12612 , n12643 );
xor ( n12972 , n12971 , n12651 );
buf ( n12973 , n12972 );
nand ( n12974 , n12970 , n12973 );
buf ( n12975 , n12974 );
nand ( n12976 , n12967 , n12975 );
nand ( n12977 , n12897 , n12976 );
buf ( n12978 , n12977 );
nand ( n12979 , n12892 , n12978 );
buf ( n12980 , n12979 );
buf ( n12981 , n12980 );
not ( n12982 , n12981 );
xnor ( n12983 , n12795 , n12682 );
buf ( n12984 , n12983 );
not ( n12985 , n12984 );
buf ( n12986 , n12776 );
not ( n12987 , n12986 );
and ( n12988 , n12985 , n12987 );
buf ( n12989 , n12983 );
buf ( n12990 , n12776 );
and ( n12991 , n12989 , n12990 );
nor ( n12992 , n12988 , n12991 );
buf ( n12993 , n12992 );
buf ( n12994 , n12993 );
nand ( n12995 , n12982 , n12994 );
buf ( n12996 , n12995 );
buf ( n12997 , n12996 );
not ( n12998 , n12997 );
not ( n12999 , n12889 );
not ( n13000 , n12878 );
or ( n13001 , n12999 , n13000 );
not ( n13002 , n12889 );
nand ( n13003 , n13002 , n12877 );
nand ( n13004 , n13001 , n13003 );
not ( n13005 , n13004 );
not ( n13006 , n12976 );
or ( n13007 , n13005 , n13006 );
not ( n13008 , n12660 );
not ( n13009 , n12676 );
not ( n13010 , n13009 );
or ( n13011 , n13008 , n13010 );
or ( n13012 , n12660 , n13009 );
nand ( n13013 , n13011 , n13012 );
buf ( n13014 , n13013 );
buf ( n13015 , n12654 );
xor ( n13016 , n13014 , n13015 );
buf ( n13017 , n13016 );
nand ( n13018 , n13007 , n13017 );
not ( n13019 , n13018 );
not ( n13020 , n12976 );
not ( n13021 , n13004 );
nand ( n13022 , n13020 , n13021 );
nand ( n13023 , n13019 , n13022 );
not ( n13024 , n13023 );
buf ( n13025 , n11409 );
not ( n13026 , n13025 );
buf ( n13027 , n384 );
not ( n13028 , n13027 );
buf ( n13029 , n12628 );
not ( n13030 , n13029 );
or ( n13031 , n13028 , n13030 );
buf ( n13032 , n384 );
not ( n13033 , n13032 );
buf ( n13034 , n11848 );
nand ( n13035 , n13033 , n13034 );
buf ( n13036 , n13035 );
buf ( n13037 , n13036 );
nand ( n13038 , n13031 , n13037 );
buf ( n13039 , n13038 );
buf ( n13040 , n13039 );
not ( n13041 , n13040 );
or ( n13042 , n13026 , n13041 );
buf ( n13043 , n384 );
buf ( n13044 , n11874 );
and ( n13045 , n13043 , n13044 );
not ( n13046 , n13043 );
buf ( n13047 , n11518 );
and ( n13048 , n13046 , n13047 );
nor ( n13049 , n13045 , n13048 );
buf ( n13050 , n13049 );
buf ( n13051 , n13050 );
buf ( n13052 , n11408 );
or ( n13053 , n13051 , n13052 );
nand ( n13054 , n13042 , n13053 );
buf ( n13055 , n13054 );
buf ( n13056 , n13055 );
not ( n13057 , n8102 );
not ( n13058 , n12231 );
or ( n13059 , n13057 , n13058 );
or ( n13060 , n12231 , n8102 );
nand ( n13061 , n13059 , n13060 );
buf ( n13062 , n13061 );
buf ( n13063 , n399 );
xor ( n13064 , n13062 , n13063 );
buf ( n13065 , n13064 );
buf ( n13066 , n13065 );
buf ( n13067 , n12185 );
buf ( n13068 , n9836 );
and ( n13069 , n13067 , n13068 );
buf ( n13070 , n13069 );
buf ( n13071 , n13070 );
xor ( n13072 , n13066 , n13071 );
buf ( n13073 , n400 );
buf ( n13074 , n8081 );
not ( n13075 , n13074 );
buf ( n13076 , n8099 );
nand ( n13077 , n13075 , n13076 );
buf ( n13078 , n13077 );
buf ( n13079 , n13078 );
buf ( n13080 , n8093 );
xor ( n13081 , n13079 , n13080 );
buf ( n13082 , n13081 );
buf ( n13083 , n13082 );
xor ( n13084 , n13073 , n13083 );
buf ( n13085 , n11604 );
buf ( n13086 , n385 );
nand ( n13087 , n13085 , n13086 );
buf ( n13088 , n13087 );
buf ( n13089 , n13088 );
buf ( n13090 , n384 );
and ( n13091 , n13089 , n13090 );
buf ( n13092 , n13091 );
buf ( n13093 , n13092 );
and ( n13094 , n13084 , n13093 );
and ( n13095 , n13073 , n13083 );
or ( n13096 , n13094 , n13095 );
buf ( n13097 , n13096 );
buf ( n13098 , n13097 );
xor ( n13099 , n13072 , n13098 );
buf ( n13100 , n13099 );
buf ( n13101 , n13100 );
xor ( n13102 , n13056 , n13101 );
buf ( n13103 , n401 );
not ( n13104 , n13103 );
or ( n13105 , n7962 , n8087 );
nand ( n13106 , n13105 , n8090 );
buf ( n13107 , n13106 );
not ( n13108 , n13107 );
or ( n13109 , n13104 , n13108 );
buf ( n13110 , n13088 );
buf ( n13111 , n13106 );
buf ( n13112 , n401 );
nor ( n13113 , n13111 , n13112 );
buf ( n13114 , n13113 );
buf ( n13115 , n13114 );
or ( n13116 , n13110 , n13115 );
nand ( n13117 , n13109 , n13116 );
buf ( n13118 , n13117 );
buf ( n13119 , n13118 );
xor ( n13120 , n13073 , n13083 );
xor ( n13121 , n13120 , n13093 );
buf ( n13122 , n13121 );
buf ( n13123 , n13122 );
xor ( n13124 , n13119 , n13123 );
not ( n13125 , n385 );
not ( n13126 , n13039 );
or ( n13127 , n13125 , n13126 );
nand ( n13128 , n12724 , n11409 );
nand ( n13129 , n13127 , n13128 );
buf ( n13130 , n13129 );
and ( n13131 , n13124 , n13130 );
and ( n13132 , n13119 , n13123 );
or ( n13133 , n13131 , n13132 );
buf ( n13134 , n13133 );
buf ( n13135 , n13134 );
and ( n13136 , n13102 , n13135 );
and ( n13137 , n13056 , n13101 );
or ( n13138 , n13136 , n13137 );
buf ( n13139 , n13138 );
xor ( n13140 , n12918 , n12941 );
xor ( n13141 , n13140 , n12961 );
buf ( n13142 , n13141 );
nor ( n13143 , n13139 , n13142 );
not ( n13144 , n12422 );
and ( n13145 , n12425 , n13144 );
nand ( n13146 , n13145 , n2953 );
and ( n13147 , n13146 , n3038 );
not ( n13148 , n13146 );
and ( n13149 , n13148 , n3035 );
nor ( n13150 , n13147 , n13149 );
xor ( n13151 , n13066 , n13071 );
and ( n13152 , n13151 , n13098 );
and ( n13153 , n13066 , n13071 );
or ( n13154 , n13152 , n13153 );
buf ( n13155 , n13154 );
xor ( n13156 , n13150 , n13155 );
buf ( n13157 , n385 );
not ( n13158 , n13157 );
buf ( n13159 , n12908 );
not ( n13160 , n13159 );
or ( n13161 , n13158 , n13160 );
buf ( n13162 , n13050 );
not ( n13163 , n13162 );
buf ( n13164 , n11409 );
nand ( n13165 , n13163 , n13164 );
buf ( n13166 , n13165 );
buf ( n13167 , n13166 );
nand ( n13168 , n13161 , n13167 );
buf ( n13169 , n13168 );
xor ( n13170 , n13156 , n13169 );
not ( n13171 , n13170 );
or ( n13172 , n13143 , n13171 );
nand ( n13173 , n13139 , n13142 );
nand ( n13174 , n13172 , n13173 );
not ( n13175 , n13174 );
xor ( n13176 , n13150 , n13155 );
and ( n13177 , n13176 , n13169 );
and ( n13178 , n13150 , n13155 );
or ( n13179 , n13177 , n13178 );
not ( n13180 , n13179 );
buf ( n13181 , n12965 );
buf ( n13182 , n12913 );
xor ( n13183 , n13181 , n13182 );
buf ( n13184 , n12972 );
xnor ( n13185 , n13183 , n13184 );
buf ( n13186 , n13185 );
nand ( n13187 , n13180 , n13186 );
not ( n13188 , n13187 );
or ( n13189 , n13175 , n13188 );
not ( n13190 , n13186 );
nand ( n13191 , n13190 , n13179 );
nand ( n13192 , n13189 , n13191 );
not ( n13193 , n13192 );
or ( n13194 , n13024 , n13193 );
buf ( n13195 , n13017 );
not ( n13196 , n13195 );
buf ( n13197 , n13196 );
not ( n13198 , n13020 );
nand ( n13199 , n13198 , n13021 );
not ( n13200 , n12976 );
nand ( n13201 , n13200 , n13004 );
nand ( n13202 , n13197 , n13199 , n13201 );
nand ( n13203 , n13194 , n13202 );
buf ( n13204 , n13203 );
not ( n13205 , n13204 );
or ( n13206 , n12998 , n13205 );
buf ( n13207 , n12993 );
not ( n13208 , n13207 );
buf ( n13209 , n12980 );
nand ( n13210 , n13208 , n13209 );
buf ( n13211 , n13210 );
buf ( n13212 , n13211 );
nand ( n13213 , n13206 , n13212 );
buf ( n13214 , n13213 );
buf ( n13215 , n13214 );
and ( n13216 , n12864 , n13215 );
and ( n13217 , n12809 , n12863 );
or ( n13218 , n13216 , n13217 );
buf ( n13219 , n13218 );
buf ( n13220 , n13219 );
not ( n13221 , n13220 );
buf ( n13222 , n12482 );
buf ( n13223 , n12566 );
and ( n13224 , n13222 , n13223 );
not ( n13225 , n13222 );
buf ( n13226 , n12567 );
and ( n13227 , n13225 , n13226 );
nor ( n13228 , n13224 , n13227 );
buf ( n13229 , n13228 );
buf ( n13230 , n12573 );
not ( n13231 , n13230 );
buf ( n13232 , n13231 );
and ( n13233 , n13229 , n13232 );
not ( n13234 , n13229 );
and ( n13235 , n13234 , n12573 );
nor ( n13236 , n13233 , n13235 );
xor ( n13237 , n12169 , n12321 );
xor ( n13238 , n13237 , n12348 );
buf ( n13239 , n13238 );
xor ( n13240 , n12836 , n12843 );
and ( n13241 , n13240 , n12857 );
and ( n13242 , n12836 , n12843 );
or ( n13243 , n13241 , n13242 );
buf ( n13244 , n13243 );
xor ( n13245 , n13239 , n13244 );
buf ( n13246 , n12562 );
not ( n13247 , n13246 );
buf ( n13248 , n12500 );
not ( n13249 , n13248 );
buf ( n13250 , n13249 );
buf ( n13251 , n13250 );
not ( n13252 , n13251 );
or ( n13253 , n13247 , n13252 );
not ( n13254 , n12562 );
buf ( n13255 , n13254 );
buf ( n13256 , n12500 );
nand ( n13257 , n13255 , n13256 );
buf ( n13258 , n13257 );
buf ( n13259 , n13258 );
nand ( n13260 , n13253 , n13259 );
buf ( n13261 , n13260 );
buf ( n13262 , n13261 );
buf ( n13263 , n12555 );
and ( n13264 , n13262 , n13263 );
not ( n13265 , n13262 );
buf ( n13266 , n12555 );
not ( n13267 , n13266 );
buf ( n13268 , n13267 );
buf ( n13269 , n13268 );
and ( n13270 , n13265 , n13269 );
nor ( n13271 , n13264 , n13270 );
buf ( n13272 , n13271 );
and ( n13273 , n13245 , n13272 );
and ( n13274 , n13239 , n13244 );
or ( n13275 , n13273 , n13274 );
not ( n13276 , n13275 );
nand ( n13277 , n13236 , n13276 );
buf ( n13278 , n13277 );
xor ( n13279 , n12813 , n12831 );
and ( n13280 , n13279 , n12860 );
and ( n13281 , n12813 , n12831 );
or ( n13282 , n13280 , n13281 );
buf ( n13283 , n13282 );
not ( n13284 , n13283 );
xor ( n13285 , n13239 , n13244 );
xor ( n13286 , n13285 , n13272 );
not ( n13287 , n13286 );
nand ( n13288 , n13284 , n13287 );
buf ( n13289 , n13288 );
and ( n13290 , n13278 , n13289 );
buf ( n13291 , n13290 );
buf ( n13292 , n13291 );
not ( n13293 , n13292 );
or ( n13294 , n13221 , n13293 );
buf ( n13295 , n13286 );
buf ( n13296 , n13283 );
nand ( n13297 , n13295 , n13296 );
buf ( n13298 , n13297 );
buf ( n13299 , n13298 );
not ( n13300 , n13299 );
buf ( n13301 , n13277 );
nand ( n13302 , n13300 , n13301 );
buf ( n13303 , n13302 );
not ( n13304 , n13236 );
buf ( n13305 , n13275 );
nand ( n13306 , n13304 , n13305 );
nand ( n13307 , n13303 , n13306 );
buf ( n13308 , n13307 );
not ( n13309 , n13308 );
buf ( n13310 , n13309 );
buf ( n13311 , n13310 );
nand ( n13312 , n13294 , n13311 );
buf ( n13313 , n13312 );
not ( n13314 , n13313 );
or ( n13315 , n12588 , n13314 );
buf ( n13316 , n12478 );
buf ( n13317 , n12584 );
or ( n13318 , n13316 , n13317 );
buf ( n13319 , n13318 );
nand ( n13320 , n13315 , n13319 );
not ( n13321 , n13320 );
buf ( n13322 , n11732 );
buf ( n13323 , n11909 );
xor ( n13324 , n13322 , n13323 );
buf ( n13325 , n11915 );
xnor ( n13326 , n13324 , n13325 );
buf ( n13327 , n13326 );
xor ( n13328 , n11757 , n11902 );
xor ( n13329 , n13328 , n11906 );
buf ( n13330 , n13329 );
not ( n13331 , n13330 );
buf ( n13332 , n13331 );
not ( n13333 , n13332 );
buf ( n13334 , n11683 );
and ( n13335 , n11500 , n11556 );
not ( n13336 , n11500 );
and ( n13337 , n13336 , n11559 );
nor ( n13338 , n13335 , n13337 );
buf ( n13339 , n13338 );
xnor ( n13340 , n13334 , n13339 );
buf ( n13341 , n13340 );
not ( n13342 , n13341 );
and ( n13343 , n13333 , n13342 );
buf ( n13344 , n13332 );
buf ( n13345 , n13341 );
nand ( n13346 , n13344 , n13345 );
buf ( n13347 , n13346 );
and ( n13348 , n11571 , n11669 );
not ( n13349 , n11571 );
not ( n13350 , n11669 );
and ( n13351 , n13349 , n13350 );
nor ( n13352 , n13348 , n13351 );
and ( n13353 , n13352 , n11680 );
not ( n13354 , n13352 );
not ( n13355 , n11680 );
and ( n13356 , n13354 , n13355 );
nor ( n13357 , n13353 , n13356 );
buf ( n13358 , n13357 );
not ( n13359 , n13358 );
not ( n13360 , n11409 );
not ( n13361 , n12062 );
or ( n13362 , n13360 , n13361 );
nand ( n13363 , n11750 , n385 );
nand ( n13364 , n13362 , n13363 );
not ( n13365 , n13364 );
buf ( n13366 , n13365 );
not ( n13367 , n13366 );
or ( n13368 , n13359 , n13367 );
not ( n13369 , n12054 );
not ( n13370 , n12073 );
or ( n13371 , n13369 , n13370 );
buf ( n13372 , n12073 );
buf ( n13373 , n12054 );
or ( n13374 , n13372 , n13373 );
buf ( n13375 , n12029 );
nand ( n13376 , n13374 , n13375 );
buf ( n13377 , n13376 );
nand ( n13378 , n13371 , n13377 );
buf ( n13379 , n13378 );
nand ( n13380 , n13368 , n13379 );
buf ( n13381 , n13380 );
buf ( n13382 , n13381 );
buf ( n13383 , n13357 );
not ( n13384 , n13383 );
buf ( n13385 , n13364 );
nand ( n13386 , n13384 , n13385 );
buf ( n13387 , n13386 );
buf ( n13388 , n13387 );
nand ( n13389 , n13382 , n13388 );
buf ( n13390 , n13389 );
and ( n13391 , n13347 , n13390 );
nor ( n13392 , n13343 , n13391 );
nand ( n13393 , n13327 , n13392 );
buf ( n13394 , n13393 );
not ( n13395 , n11900 );
not ( n13396 , n11786 );
not ( n13397 , n11778 );
not ( n13398 , n13397 );
or ( n13399 , n13396 , n13398 );
nand ( n13400 , n11785 , n11778 );
nand ( n13401 , n13399 , n13400 );
xnor ( n13402 , n13395 , n13401 );
not ( n13403 , n13402 );
buf ( n13404 , n12373 );
not ( n13405 , n13404 );
buf ( n13406 , n13405 );
not ( n13407 , n13406 );
not ( n13408 , n12376 );
or ( n13409 , n13407 , n13408 );
nand ( n13410 , n13409 , n12465 );
not ( n13411 , n12376 );
nand ( n13412 , n13411 , n12373 );
nand ( n13413 , n13410 , n13412 );
not ( n13414 , n13413 );
or ( n13415 , n13403 , n13414 );
not ( n13416 , n13365 );
not ( n13417 , n13357 );
not ( n13418 , n13417 );
or ( n13419 , n13416 , n13418 );
nand ( n13420 , n13357 , n13364 );
nand ( n13421 , n13419 , n13420 );
and ( n13422 , n13421 , n13378 );
not ( n13423 , n13421 );
not ( n13424 , n13378 );
and ( n13425 , n13423 , n13424 );
nor ( n13426 , n13422 , n13425 );
not ( n13427 , n13426 );
not ( n13428 , n13395 );
not ( n13429 , n13401 );
not ( n13430 , n13429 );
or ( n13431 , n13428 , n13430 );
nand ( n13432 , n13401 , n11900 );
nand ( n13433 , n13431 , n13432 );
not ( n13434 , n13433 );
nor ( n13435 , n13434 , n13413 );
or ( n13436 , n13427 , n13435 );
nand ( n13437 , n13415 , n13436 );
not ( n13438 , n13437 );
not ( n13439 , n13341 );
not ( n13440 , n13390 );
not ( n13441 , n13440 );
or ( n13442 , n13439 , n13441 );
not ( n13443 , n13341 );
nand ( n13444 , n13443 , n13390 );
nand ( n13445 , n13442 , n13444 );
and ( n13446 , n13445 , n13329 );
not ( n13447 , n13445 );
not ( n13448 , n13329 );
and ( n13449 , n13447 , n13448 );
nor ( n13450 , n13446 , n13449 );
nand ( n13451 , n13438 , n13450 );
buf ( n13452 , n13451 );
not ( n13453 , n13452 );
buf ( n13454 , n13453 );
buf ( n13455 , n13454 );
and ( n13456 , n13413 , n13402 );
not ( n13457 , n13413 );
and ( n13458 , n13457 , n13433 );
nor ( n13459 , n13456 , n13458 );
and ( n13460 , n13459 , n13427 );
not ( n13461 , n13459 );
and ( n13462 , n13461 , n13426 );
nor ( n13463 , n13460 , n13462 );
not ( n13464 , n13463 );
not ( n13465 , n12076 );
not ( n13466 , n13465 );
not ( n13467 , n12474 );
or ( n13468 , n13466 , n13467 );
not ( n13469 , n12076 );
not ( n13470 , n12468 );
or ( n13471 , n13469 , n13470 );
nand ( n13472 , n13471 , n12357 );
nand ( n13473 , n13468 , n13472 );
nor ( n13474 , n13464 , n13473 );
buf ( n13475 , n13474 );
nor ( n13476 , n13455 , n13475 );
buf ( n13477 , n13476 );
buf ( n13478 , n13477 );
and ( n13479 , n13394 , n13478 );
buf ( n13480 , n13479 );
not ( n13481 , n13480 );
or ( n13482 , n13321 , n13481 );
not ( n13483 , n13393 );
not ( n13484 , n13465 );
not ( n13485 , n12474 );
or ( n13486 , n13484 , n13485 );
nand ( n13487 , n13486 , n13472 );
not ( n13488 , n13487 );
nor ( n13489 , n13488 , n13463 );
not ( n13490 , n13489 );
not ( n13491 , n13451 );
or ( n13492 , n13490 , n13491 );
buf ( n13493 , n13450 );
not ( n13494 , n13493 );
buf ( n13495 , n13437 );
buf ( n13496 , n13495 );
nand ( n13497 , n13494 , n13496 );
buf ( n13498 , n13497 );
nand ( n13499 , n13492 , n13498 );
not ( n13500 , n13499 );
or ( n13501 , n13483 , n13500 );
buf ( n13502 , n13327 );
not ( n13503 , n13502 );
buf ( n13504 , n13503 );
buf ( n13505 , n13392 );
not ( n13506 , n13505 );
buf ( n13507 , n13506 );
nand ( n13508 , n13504 , n13507 );
nand ( n13509 , n13501 , n13508 );
not ( n13510 , n13509 );
nand ( n13511 , n13482 , n13510 );
and ( n13512 , n12018 , n13511 );
not ( n13513 , n13512 );
or ( n13514 , n11062 , n13513 );
not ( n13515 , n10834 );
not ( n13516 , n10812 );
and ( n13517 , n13515 , n13516 );
and ( n13518 , n10834 , n10812 );
nor ( n13519 , n13518 , n10838 );
nor ( n13520 , n13517 , n13519 );
nor ( n13521 , n10805 , n13520 );
not ( n13522 , n13521 );
buf ( n13523 , n10793 );
buf ( n13524 , n10725 );
nand ( n13525 , n13523 , n13524 );
buf ( n13526 , n13525 );
buf ( n13527 , n13526 );
nand ( n13528 , n10849 , n10862 );
buf ( n13529 , n13528 );
and ( n13530 , n13527 , n13529 );
buf ( n13531 , n13530 );
not ( n13532 , n13531 );
buf ( n13533 , n10725 );
not ( n13534 , n13533 );
buf ( n13535 , n10796 );
nand ( n13536 , n13534 , n13535 );
buf ( n13537 , n13536 );
buf ( n13538 , n11056 );
buf ( n13539 , n11050 );
nor ( n13540 , n13538 , n13539 );
buf ( n13541 , n13540 );
nand ( n13542 , n13537 , n13541 );
not ( n13543 , n13542 );
or ( n13544 , n13532 , n13543 );
and ( n13545 , n10842 , n10864 );
nand ( n13546 , n13544 , n13545 );
nand ( n13547 , n13522 , n13546 );
nor ( n13548 , n12010 , n12003 );
not ( n13549 , n13548 );
not ( n13550 , n12000 );
or ( n13551 , n13549 , n13550 );
buf ( n13552 , n11928 );
not ( n13553 , n13552 );
buf ( n13554 , n13553 );
buf ( n13555 , n13554 );
buf ( n13556 , n11994 );
nand ( n13557 , n13555 , n13556 );
buf ( n13558 , n13557 );
nand ( n13559 , n13551 , n13558 );
not ( n13560 , n13559 );
nand ( n13561 , n11708 , n11917 );
nand ( n13562 , n11444 , n11704 );
nand ( n13563 , n13561 , n13562 );
nand ( n13564 , n13563 , n11706 , n12011 , n12000 );
nand ( n13565 , n13560 , n13564 );
nor ( n13566 , n10843 , n11060 );
nand ( n13567 , n13565 , n13566 );
not ( n13568 , n13567 );
nor ( n13569 , n13547 , n13568 );
nand ( n13570 , n13514 , n13569 );
not ( n13571 , n13570 );
or ( n13572 , n10308 , n13571 );
nor ( n13573 , n10090 , n10015 );
nand ( n13574 , n10294 , n10303 );
or ( n13575 , n13573 , n13574 );
nand ( n13576 , n13575 , C1 );
buf ( n13577 , n13576 );
not ( n13578 , n13577 );
buf ( n13579 , n13578 );
nand ( n13580 , n13572 , n13579 );
buf ( n13581 , n13580 );
and ( n13582 , n13581 , n10013 );
not ( n13583 , n13581 );
and ( n13584 , n13583 , n10012 );
nor ( n13585 , n13582 , n13584 );
buf ( n13586 , n13585 );
buf ( n13587 , n13521 );
not ( n13588 , n13587 );
buf ( n13589 , n10842 );
nand ( n13590 , n13588 , n13589 );
buf ( n13591 , n13590 );
buf ( n13592 , n13591 );
buf ( n13593 , n13591 );
not ( n13594 , n13593 );
buf ( n13595 , n13594 );
buf ( n13596 , n13595 );
buf ( n13597 , n10864 );
not ( n13598 , n13597 );
buf ( n13599 , n11057 );
not ( n13600 , n13599 );
buf ( n13601 , n10796 );
not ( n13602 , n13601 );
buf ( n13603 , n10725 );
nor ( n13604 , n13602 , n13603 );
buf ( n13605 , n13604 );
buf ( n13606 , n13605 );
nor ( n13607 , n13600 , n13606 );
buf ( n13608 , n13607 );
buf ( n13609 , n13608 );
not ( n13610 , n13609 );
not ( n13611 , n13511 );
not ( n13612 , n12018 );
or ( n13613 , n13611 , n13612 );
not ( n13614 , n13565 );
nand ( n13615 , n13613 , n13614 );
buf ( n13616 , n13615 );
not ( n13617 , n13616 );
or ( n13618 , n13610 , n13617 );
buf ( n13619 , n13526 );
buf ( n13620 , n13619 );
buf ( n13621 , n13620 );
and ( n13622 , n13542 , n13621 );
buf ( n13623 , n13622 );
nand ( n13624 , n13618 , n13623 );
buf ( n13625 , n13624 );
not ( n13626 , n13625 );
or ( n13627 , n13598 , n13626 );
buf ( n13628 , n13528 );
nand ( n13629 , n13627 , n13628 );
buf ( n13630 , n13629 );
and ( n13631 , n13630 , n13596 );
not ( n13632 , n13630 );
and ( n13633 , n13632 , n13592 );
nor ( n13634 , n13631 , n13633 );
buf ( n13635 , n13634 );
buf ( n13636 , n10864 );
buf ( n13637 , n13628 );
nand ( n13638 , n13636 , n13637 );
buf ( n13639 , n13638 );
buf ( n13640 , n13639 );
buf ( n13641 , n13639 );
not ( n13642 , n13641 );
buf ( n13643 , n13642 );
buf ( n13644 , n13643 );
buf ( n13645 , n13625 );
and ( n13646 , n13645 , n13644 );
not ( n13647 , n13645 );
and ( n13648 , n13647 , n13640 );
nor ( n13649 , n13646 , n13648 );
buf ( n13650 , n13649 );
buf ( n13651 , n9755 );
buf ( n13652 , n9863 );
and ( n13653 , n13651 , n13652 );
buf ( n13654 , n9752 );
buf ( n13655 , n9860 );
and ( n13656 , n13654 , n13655 );
nor ( n13657 , n13653 , n13656 );
buf ( n13658 , n13657 );
buf ( n13659 , n13658 );
buf ( n13660 , n9828 );
and ( n13661 , n13659 , n13660 );
not ( n13662 , n13659 );
buf ( n13663 , n9801 );
and ( n13664 , n13662 , n13663 );
or ( n13665 , n13661 , n13664 );
buf ( n13666 , n13665 );
buf ( n13667 , n13666 );
buf ( n13668 , n9755 );
and ( n13669 , n13667 , n13668 );
not ( n13670 , n13667 );
buf ( n13671 , n9752 );
and ( n13672 , n13670 , n13671 );
nor ( n13673 , n13669 , n13672 );
buf ( n13674 , n13673 );
buf ( n13675 , n13674 );
not ( n13676 , n13675 );
buf ( n13677 , n9755 );
buf ( n13678 , n9860 );
or ( n13679 , n13677 , n13678 );
buf ( n13680 , n9752 );
buf ( n13681 , n9863 );
or ( n13682 , n13680 , n13681 );
buf ( n13683 , n9801 );
nand ( n13684 , n13682 , n13683 );
buf ( n13685 , n13684 );
buf ( n13686 , n13685 );
nand ( n13687 , n13679 , n13686 );
buf ( n13688 , n13687 );
buf ( n13689 , n13688 );
not ( n13690 , n13689 );
and ( n13691 , n13676 , n13690 );
buf ( n13692 , n13674 );
buf ( n13693 , n13688 );
and ( n13694 , n13692 , n13693 );
nor ( n13695 , n13691 , n13694 );
buf ( n13696 , n13695 );
buf ( n13697 , n10267 );
buf ( n13698 , n9860 );
nand ( n13699 , n13697 , n13698 );
buf ( n13700 , n13699 );
buf ( n13701 , n13700 );
not ( n13702 , n13701 );
buf ( n13703 , n13702 );
not ( n13704 , n13703 );
not ( n13705 , n13666 );
and ( n13706 , n13704 , n13705 );
buf ( n13707 , n13666 );
buf ( n13708 , n13703 );
nand ( n13709 , n13707 , n13708 );
buf ( n13710 , n13709 );
buf ( n13711 , n12086 );
not ( n13712 , n13711 );
buf ( n13713 , n9752 );
buf ( n13714 , n9828 );
nand ( n13715 , n13713 , n13714 );
buf ( n13716 , n13715 );
buf ( n13717 , n13716 );
not ( n13718 , n13717 );
or ( n13719 , n13712 , n13718 );
buf ( n13720 , n9809 );
nand ( n13721 , n13719 , n13720 );
buf ( n13722 , n13721 );
and ( n13723 , n13710 , n13722 );
nor ( n13724 , n13706 , n13723 );
buf ( n13725 , n9758 );
not ( n13726 , n13725 );
buf ( n13727 , n9906 );
nand ( n13728 , n13726 , n13727 );
buf ( n13729 , n13728 );
not ( n13730 , n13729 );
not ( n13731 , n10266 );
not ( n13732 , n9863 );
or ( n13733 , n13731 , n13732 );
nand ( n13734 , n13733 , n13700 );
not ( n13735 , n13734 );
or ( n13736 , n13730 , n13735 );
buf ( n13737 , n9761 );
buf ( n13738 , n9988 );
nand ( n13739 , n13737 , n13738 );
buf ( n13740 , n13739 );
nand ( n13741 , n13736 , n13740 );
buf ( n13742 , n13741 );
buf ( n13743 , n13722 );
buf ( n13744 , n13666 );
xor ( n13745 , n13743 , n13744 );
buf ( n13746 , n13700 );
xnor ( n13747 , n13745 , n13746 );
buf ( n13748 , n13747 );
buf ( n13749 , n13748 );
or ( n13750 , n13742 , n13749 );
buf ( n13751 , n13750 );
buf ( n13752 , n13751 );
not ( n13753 , n13752 );
buf ( n13754 , n9835 );
buf ( n13755 , n9755 );
and ( n13756 , n13754 , n13755 );
not ( n13757 , n13754 );
buf ( n13758 , n9752 );
and ( n13759 , n13757 , n13758 );
nor ( n13760 , n13756 , n13759 );
buf ( n13761 , n13760 );
buf ( n13762 , n13761 );
buf ( n13763 , n13729 );
buf ( n13764 , n9880 );
nand ( n13765 , n13763 , n13764 );
buf ( n13766 , n13765 );
buf ( n13767 , n13766 );
buf ( n13768 , n13740 );
nand ( n13769 , n13767 , n13768 );
buf ( n13770 , n13769 );
buf ( n13771 , n13770 );
xor ( n13772 , n13762 , n13771 );
buf ( n13773 , n13734 );
not ( n13774 , n13773 );
buf ( n13775 , n13774 );
buf ( n13776 , n13775 );
not ( n13777 , n13776 );
buf ( n13778 , n9917 );
not ( n13779 , n13778 );
or ( n13780 , n13777 , n13779 );
buf ( n13781 , n9917 );
buf ( n13782 , n13775 );
or ( n13783 , n13781 , n13782 );
nand ( n13784 , n13780 , n13783 );
buf ( n13785 , n13784 );
buf ( n13786 , n13785 );
and ( n13787 , n13772 , n13786 );
and ( n13788 , n13762 , n13771 );
or ( n13789 , n13787 , n13788 );
buf ( n13790 , n13789 );
buf ( n13791 , n13790 );
not ( n13792 , n13791 );
or ( n13793 , n13753 , n13792 );
buf ( n13794 , n13741 );
buf ( n13795 , n13748 );
nand ( n13796 , n13794 , n13795 );
buf ( n13797 , n13796 );
buf ( n13798 , n13797 );
nand ( n13799 , n13793 , n13798 );
buf ( n13800 , n13799 );
buf ( n13801 , n13800 );
not ( n13802 , n13801 );
or ( n13803 , C0 , n13802 );
buf ( n13804 , n13724 );
buf ( n13805 , n13696 );
nor ( n13806 , n13804 , n13805 );
buf ( n13807 , n13806 );
buf ( n13808 , n13807 );
not ( n13809 , n13808 );
buf ( n13810 , n13809 );
buf ( n13811 , n13810 );
nand ( n13812 , n13803 , n13811 );
buf ( n13813 , n13812 );
buf ( n13814 , n6572 );
not ( n13815 , n13814 );
buf ( n13816 , n13815 );
buf ( n13817 , n13816 );
buf ( n13818 , n415 );
buf ( n13819 , n416 );
and ( n13820 , n13818 , n13819 );
buf ( n13821 , n6458 );
not ( n13822 , n13821 );
buf ( n13823 , n13822 );
buf ( n13824 , n13823 );
nor ( n13825 , n13820 , n13824 );
buf ( n13826 , n13825 );
buf ( n13827 , n13826 );
or ( n13828 , n13817 , n13827 );
buf ( n13829 , n6584 );
nand ( n13830 , n13828 , n13829 );
buf ( n13831 , n13830 );
buf ( n13832 , n13831 );
buf ( n13833 , n6577 );
xor ( n13834 , n13832 , n13833 );
buf ( n13835 , n9559 );
buf ( n13836 , n415 );
and ( n13837 , n13835 , n13836 );
not ( n13838 , n13835 );
buf ( n13839 , n6467 );
and ( n13840 , n13838 , n13839 );
nor ( n13841 , n13837 , n13840 );
buf ( n13842 , n13841 );
buf ( n13843 , n13842 );
not ( n13844 , n13843 );
buf ( n13845 , n9452 );
not ( n13846 , n13845 );
or ( n13847 , n13844 , n13846 );
buf ( n13848 , n9452 );
buf ( n13849 , n13842 );
or ( n13850 , n13848 , n13849 );
nand ( n13851 , n13847 , n13850 );
buf ( n13852 , n13851 );
buf ( n13853 , n13852 );
and ( n13854 , n13834 , n13853 );
and ( n13855 , n13832 , n13833 );
or ( n13856 , n13854 , n13855 );
buf ( n13857 , n13856 );
buf ( n13858 , n13857 );
buf ( n13859 , n9493 );
buf ( n13860 , n13842 );
or ( n13861 , n13859 , n13860 );
buf ( n13862 , n6445 );
buf ( n13863 , n6557 );
or ( n13864 , n13862 , n13863 );
nand ( n13865 , n13861 , n13864 );
buf ( n13866 , n13865 );
buf ( n13867 , n13866 );
buf ( n13868 , n6542 );
xor ( n13869 , n13867 , n13868 );
buf ( n13870 , n6581 );
not ( n13871 , n6500 );
buf ( n13872 , n13871 );
buf ( n13873 , n6523 );
or ( n13874 , n13872 , n13873 );
buf ( n13875 , n6519 );
buf ( n13876 , n6496 );
or ( n13877 , n13875 , n13876 );
nand ( n13878 , n13874 , n13877 );
buf ( n13879 , n13878 );
buf ( n13880 , n13879 );
xor ( n13881 , n13870 , n13880 );
buf ( n13882 , n6542 );
buf ( n13883 , n415 );
nor ( n13884 , n13882 , n13883 );
buf ( n13885 , n13884 );
buf ( n13886 , n13885 );
xor ( n13887 , n13881 , n13886 );
buf ( n13888 , n13887 );
buf ( n13889 , n13888 );
xor ( n13890 , n13869 , n13889 );
buf ( n13891 , n13890 );
buf ( n13892 , n13891 );
xor ( n13893 , n13858 , n13892 );
xor ( n13894 , n13832 , n13833 );
xor ( n13895 , n13894 , n13853 );
buf ( n13896 , n13895 );
buf ( n13897 , n13896 );
not ( n13898 , n13897 );
buf ( n13899 , n13826 );
buf ( n13900 , n6581 );
and ( n13901 , n13899 , n13900 );
not ( n13902 , n13899 );
buf ( n13903 , n6445 );
and ( n13904 , n13902 , n13903 );
nor ( n13905 , n13901 , n13904 );
buf ( n13906 , n13905 );
xor ( n13907 , n13906 , n6577 );
buf ( n13908 , n13907 );
buf ( n13909 , n6566 );
xor ( n13910 , n13908 , n13909 );
buf ( n13911 , n6607 );
and ( n13912 , n13910 , n13911 );
and ( n13913 , n13908 , n13909 );
or ( n13914 , n13912 , n13913 );
buf ( n13915 , n13914 );
buf ( n13916 , n13915 );
nand ( n13917 , n13898 , n13916 );
buf ( n13918 , n13917 );
buf ( n13919 , n13918 );
not ( n13920 , n13919 );
xor ( n13921 , n13908 , n13909 );
xor ( n13922 , n13921 , n13911 );
buf ( n13923 , n13922 );
buf ( n13924 , n13923 );
buf ( n13925 , n6592 );
nand ( n13926 , n13924 , n13925 );
buf ( n13927 , n13926 );
not ( n13928 , n13927 );
buf ( n13929 , n9716 );
buf ( n13930 , n13929 );
buf ( n13931 , n13930 );
not ( n13932 , n13931 );
or ( n13933 , n13928 , n13932 );
buf ( n13934 , n13923 );
not ( n13935 , n13934 );
buf ( n13936 , n6589 );
nand ( n13937 , n13935 , n13936 );
buf ( n13938 , n13937 );
nand ( n13939 , n13933 , n13938 );
buf ( n13940 , n13939 );
not ( n13941 , n13940 );
or ( n13942 , n13920 , n13941 );
buf ( n13943 , n13915 );
not ( n13944 , n13943 );
buf ( n13945 , n13896 );
nand ( n13946 , n13944 , n13945 );
buf ( n13947 , n13946 );
buf ( n13948 , n13947 );
nand ( n13949 , n13942 , n13948 );
buf ( n13950 , n13949 );
buf ( n13951 , n13950 );
xor ( n13952 , n13893 , n13951 );
buf ( n13953 , n13952 );
not ( n13954 , n13953 );
buf ( n13955 , C1 );
buf ( n13956 , n13955 );
buf ( n13957 , n13813 );
buf ( n13958 , n13954 );
nand ( n13959 , n13957 , n13958 );
buf ( n13960 , n13959 );
buf ( n13961 , n13960 );
nand ( n13962 , n13956 , n13961 );
buf ( n13963 , n13962 );
buf ( n13964 , n13963 );
buf ( n13965 , n13963 );
not ( n13966 , n13965 );
buf ( n13967 , n13966 );
buf ( n13968 , n13967 );
buf ( n13969 , n13947 );
buf ( n13970 , n13918 );
nand ( n13971 , n13969 , n13970 );
buf ( n13972 , n13971 );
xnor ( n13973 , n13972 , n13939 );
buf ( n13974 , n13973 );
not ( n13975 , n13974 );
xor ( n13976 , n13696 , n13724 );
xnor ( n13977 , n13976 , n13800 );
buf ( n13978 , n13977 );
nand ( n13979 , n13975 , n13978 );
buf ( n13980 , n13979 );
buf ( n13981 , n13980 );
and ( n13982 , n13938 , n13927 );
xor ( n13983 , n13982 , n13931 );
buf ( n13984 , n13983 );
not ( n13985 , n13984 );
buf ( n13986 , n13790 );
buf ( n13987 , n13986 );
buf ( n13988 , n13987 );
buf ( n13989 , n13988 );
buf ( n13990 , n13741 );
buf ( n13991 , n13748 );
xor ( n13992 , n13990 , n13991 );
buf ( n13993 , n13992 );
buf ( n13994 , n13993 );
xnor ( n13995 , n13989 , n13994 );
buf ( n13996 , n13995 );
buf ( n13997 , n13996 );
nand ( n13998 , n13985 , n13997 );
buf ( n13999 , n13998 );
buf ( n14000 , n13999 );
not ( n14001 , n9889 );
not ( n14002 , n9917 );
or ( n14003 , n14001 , n14002 );
nand ( n14004 , n14003 , n9923 );
not ( n14005 , n14004 );
nand ( n14006 , n14005 , n9868 );
not ( n14007 , n14006 );
buf ( n14008 , n13770 );
buf ( n14009 , n14008 );
buf ( n14010 , n14009 );
not ( n14011 , n14010 );
or ( n14012 , n14007 , n14011 );
buf ( n14013 , n14004 );
buf ( n14014 , n9867 );
nand ( n14015 , n14013 , n14014 );
buf ( n14016 , n14015 );
nand ( n14017 , n14012 , n14016 );
xor ( n14018 , n13762 , n13771 );
xor ( n14019 , n14018 , n13786 );
buf ( n14020 , n14019 );
or ( n14021 , n14017 , n14020 );
buf ( n14022 , n14021 );
and ( n14023 , n13981 , n14000 , n14022 );
buf ( n14024 , n14023 );
not ( n14025 , n14024 );
not ( n14026 , n14006 );
not ( n14027 , n9886 );
or ( n14028 , n14026 , n14027 );
nand ( n14029 , n14028 , n14016 );
not ( n14030 , n14029 );
not ( n14031 , n14010 );
not ( n14032 , n9931 );
or ( n14033 , n14031 , n14032 );
buf ( n14034 , n14010 );
not ( n14035 , n14034 );
buf ( n14036 , n9928 );
nand ( n14037 , n14035 , n14036 );
buf ( n14038 , n14037 );
nand ( n14039 , n14033 , n14038 );
not ( n14040 , n14039 );
and ( n14041 , n14030 , n14040 );
not ( n14042 , n9935 );
not ( n14043 , n10003 );
and ( n14044 , n14042 , n14043 );
nor ( n14045 , n14041 , n14044 );
and ( n14046 , n10091 , n14045 , n10305 );
not ( n14047 , n14046 );
nor ( n14048 , n14047 , n10843 );
nor ( n14049 , n12015 , n11060 );
nand ( n14050 , n13511 , n14048 , n14049 );
not ( n14051 , n14045 );
not ( n14052 , n13576 );
or ( n14053 , n14051 , n14052 );
nand ( n14054 , n14053 , C1 );
buf ( n14055 , n14054 );
buf ( n14056 , n13521 );
nor ( n14057 , n14055 , n14056 );
buf ( n14058 , n14057 );
nand ( n14059 , n13546 , n14058 );
or ( n14060 , n13568 , n14059 );
not ( n14061 , n14054 );
not ( n14062 , n14046 );
and ( n14063 , n14061 , n14062 );
nor ( n14064 , n14017 , n14039 );
nor ( n14065 , n14063 , n14064 );
nand ( n14066 , n14060 , n14065 );
nand ( n14067 , n14050 , n14066 );
not ( n14068 , n14067 );
or ( n14069 , n14025 , n14068 );
buf ( n14070 , C0 );
buf ( n14071 , C1 );
nand ( n14072 , n14069 , C1 );
buf ( n14073 , n14072 );
and ( n14074 , n14073 , n13968 );
not ( n14075 , n14073 );
and ( n14076 , n14075 , n13964 );
nor ( n14077 , n14074 , n14076 );
buf ( n14078 , n14077 );
buf ( n14079 , n13605 );
not ( n14080 , n14079 );
buf ( n14081 , n13621 );
nand ( n14082 , n14080 , n14081 );
buf ( n14083 , n14082 );
buf ( n14084 , n14083 );
buf ( n14085 , n14083 );
not ( n14086 , n14085 );
buf ( n14087 , n14086 );
buf ( n14088 , n14087 );
not ( n14089 , n11057 );
not ( n14090 , n13615 );
or ( n14091 , n14089 , n14090 );
not ( n14092 , n13541 );
nand ( n14093 , n14091 , n14092 );
buf ( n14094 , n14093 );
and ( n14095 , n14094 , n14088 );
not ( n14096 , n14094 );
and ( n14097 , n14096 , n14084 );
nor ( n14098 , n14095 , n14097 );
buf ( n14099 , n14098 );
buf ( n14100 , n13548 );
not ( n14101 , n14100 );
buf ( n14102 , n12011 );
nand ( n14103 , n14101 , n14102 );
buf ( n14104 , n14103 );
buf ( n14105 , n14103 );
not ( n14106 , n14105 );
buf ( n14107 , n14106 );
buf ( n14108 , n14107 );
not ( n14109 , n13511 );
not ( n14110 , n11922 );
or ( n14111 , n14109 , n14110 );
buf ( n14112 , n11706 );
buf ( n14113 , n13563 );
nand ( n14114 , n14112 , n14113 );
nand ( n14115 , n14111 , n14114 );
buf ( n14116 , n14115 );
and ( n14117 , n14116 , n14108 );
not ( n14118 , n14116 );
and ( n14119 , n14118 , n14104 );
nor ( n14120 , n14117 , n14119 );
buf ( n14121 , n14120 );
buf ( n14122 , n14092 );
buf ( n14123 , n11057 );
nand ( n14124 , n14122 , n14123 );
buf ( n14125 , n14124 );
buf ( n14126 , n14125 );
buf ( n14127 , n14125 );
not ( n14128 , n14127 );
buf ( n14129 , n14128 );
buf ( n14130 , n14129 );
buf ( n14131 , n13615 );
and ( n14132 , n14131 , n14130 );
not ( n14133 , n14131 );
and ( n14134 , n14133 , n14126 );
nor ( n14135 , n14132 , n14134 );
buf ( n14136 , n14135 );
buf ( n14137 , n13393 );
buf ( n14138 , n13508 );
nand ( n14139 , n14137 , n14138 );
buf ( n14140 , n14139 );
buf ( n14141 , n14140 );
buf ( n14142 , n14140 );
not ( n14143 , n14142 );
buf ( n14144 , n14143 );
buf ( n14145 , n14144 );
buf ( n14146 , n13454 );
not ( n14147 , n14146 );
buf ( n14148 , n14147 );
buf ( n14149 , n14148 );
not ( n14150 , n14149 );
buf ( n14151 , n13474 );
not ( n14152 , n14151 );
buf ( n14153 , n14152 );
not ( n14154 , n14153 );
not ( n14155 , n12587 );
not ( n14156 , n13313 );
or ( n14157 , n14155 , n14156 );
nand ( n14158 , n14157 , n13319 );
not ( n14159 , n14158 );
or ( n14160 , n14154 , n14159 );
buf ( n14161 , n13489 );
not ( n14162 , n14161 );
buf ( n14163 , n14162 );
nand ( n14164 , n14160 , n14163 );
buf ( n14165 , n14164 );
not ( n14166 , n14165 );
or ( n14167 , n14150 , n14166 );
buf ( n14168 , n13498 );
buf ( n14169 , n14168 );
buf ( n14170 , n14169 );
buf ( n14171 , n14170 );
nand ( n14172 , n14167 , n14171 );
buf ( n14173 , n14172 );
buf ( n14174 , n14173 );
and ( n14175 , n14174 , n14145 );
not ( n14176 , n14174 );
and ( n14177 , n14176 , n14141 );
nor ( n14178 , n14175 , n14177 );
buf ( n14179 , n14178 );
nand ( n14180 , n14112 , n13562 );
buf ( n14181 , n14180 );
buf ( n14182 , n14180 );
not ( n14183 , n14182 );
buf ( n14184 , n14183 );
buf ( n14185 , n14184 );
buf ( n14186 , n11921 );
buf ( n14187 , n14186 );
not ( n14188 , n14187 );
buf ( n14189 , n13511 );
not ( n14190 , n14189 );
or ( n14191 , n14188 , n14190 );
buf ( n14192 , n13561 );
nand ( n14193 , n14191 , n14192 );
buf ( n14194 , n14193 );
and ( n14195 , n14194 , n14185 );
not ( n14196 , n14194 );
and ( n14197 , n14196 , n14181 );
nor ( n14198 , n14195 , n14197 );
buf ( n14199 , n14198 );
buf ( n14200 , n13319 );
buf ( n14201 , n12587 );
buf ( n14202 , n14201 );
nand ( n14203 , n14200 , n14202 );
buf ( n14204 , n14203 );
buf ( n14205 , n14204 );
not ( n14206 , n14205 );
buf ( n14207 , n14206 );
buf ( n14208 , n14207 );
buf ( n14209 , n14204 );
buf ( n14210 , n13219 );
not ( n14211 , n14210 );
buf ( n14212 , n13291 );
not ( n14213 , n14212 );
or ( n14214 , n14211 , n14213 );
buf ( n14215 , n13310 );
nand ( n14216 , n14214 , n14215 );
buf ( n14217 , n14216 );
buf ( n14218 , n14217 );
not ( n14219 , n14218 );
buf ( n14220 , n14219 );
buf ( n14221 , n14220 );
and ( n14222 , n14221 , n14209 );
not ( n14223 , n14221 );
and ( n14224 , n14223 , n14208 );
nor ( n14225 , n14222 , n14224 );
buf ( n14226 , n14225 );
nand ( n14227 , n13306 , n13277 );
buf ( n14228 , n14227 );
buf ( n14229 , n13288 );
buf ( n14230 , n14229 );
not ( n14231 , n14230 );
buf ( n14232 , n13219 );
buf ( n14233 , n14232 );
buf ( n14234 , n14233 );
buf ( n14235 , n14234 );
not ( n14236 , n14235 );
or ( n14237 , n14231 , n14236 );
buf ( n14238 , n13298 );
buf ( n14239 , n14238 );
nand ( n14240 , n14237 , n14239 );
buf ( n14241 , n14240 );
buf ( n14242 , n14241 );
buf ( n14243 , n14227 );
buf ( n14244 , n14241 );
not ( n14245 , n14228 );
not ( n14246 , n14242 );
or ( n14247 , n14245 , n14246 );
or ( n14248 , n14243 , n14244 );
nand ( n14249 , n14247 , n14248 );
buf ( n14250 , n14249 );
nand ( n14251 , n14229 , n14238 );
buf ( n14252 , n14251 );
buf ( n14253 , n14234 );
buf ( n14254 , n14234 );
buf ( n14255 , n14251 );
not ( n14256 , n14252 );
not ( n14257 , n14253 );
or ( n14258 , n14256 , n14257 );
or ( n14259 , n14254 , n14255 );
nand ( n14260 , n14258 , n14259 );
buf ( n14261 , n14260 );
or ( n14262 , n5832 , n7195 );
not ( n14263 , n6444 );
or ( n14264 , n14263 , n5840 );
nand ( n14265 , n14262 , n14264 );
xor ( n14266 , n14265 , n6542 );
nand ( n14267 , n6524 , n413 );
xor ( n14268 , n9559 , n14267 );
and ( n14269 , n14268 , n6581 );
and ( n14270 , n9559 , n14267 );
or ( n14271 , n14269 , n14270 );
and ( n14272 , n14266 , n14271 );
and ( n14273 , n14265 , n6542 );
or ( n14274 , n14272 , n14273 );
nand ( n14275 , n5841 , n411 );
xnor ( n14276 , n14274 , n14275 );
not ( n14277 , n14276 );
xor ( n14278 , n9559 , n14267 );
xor ( n14279 , n14278 , n6581 );
xor ( n14280 , n14279 , n9559 );
xor ( n14281 , n13870 , n13880 );
and ( n14282 , n14281 , n13886 );
and ( n14283 , n13870 , n13880 );
or ( n14284 , n14282 , n14283 );
buf ( n14285 , n14284 );
and ( n14286 , n14280 , n14285 );
and ( n14287 , n14279 , n9559 );
or ( n14288 , n14286 , n14287 );
xor ( n14289 , n14265 , n6542 );
xor ( n14290 , n14289 , n14271 );
nor ( n14291 , n14288 , n14290 );
not ( n14292 , n14291 );
xor ( n14293 , n13858 , n13892 );
and ( n14294 , n14293 , n13951 );
and ( n14295 , n13858 , n13892 );
or ( n14296 , n14294 , n14295 );
buf ( n14297 , n14296 );
buf ( n14298 , n14297 );
xor ( n14299 , n13867 , n13868 );
and ( n14300 , n14299 , n13889 );
and ( n14301 , n13867 , n13868 );
or ( n14302 , n14300 , n14301 );
buf ( n14303 , n14302 );
not ( n14304 , n14303 );
xor ( n14305 , n14279 , n9559 );
xor ( n14306 , n14305 , n14285 );
not ( n14307 , n14306 );
nand ( n14308 , n14304 , n14307 );
nand ( n14309 , n14292 , n14298 , n14308 );
not ( n14310 , n14291 );
nand ( n14311 , n14310 , n14303 , n14306 );
nand ( n14312 , n14288 , n14290 );
nand ( n14313 , n14309 , n14311 , n14312 );
not ( n14314 , n14313 );
or ( n14315 , n14277 , n14314 );
or ( n14316 , n14313 , n14276 );
nand ( n14317 , n14315 , n14316 );
not ( n14318 , n14317 );
not ( n14319 , n13800 );
or ( n14320 , C0 , n14319 );
nor ( n14321 , C0 , n13807 );
nand ( n14322 , n14320 , n14321 );
nand ( n14323 , n14318 , n14322 );
buf ( n14324 , n14323 );
not ( n14325 , n14308 );
not ( n14326 , n14298 );
or ( n14327 , n14325 , n14326 );
nand ( n14328 , n14303 , n14306 );
nand ( n14329 , n14327 , n14328 );
not ( n14330 , n14290 );
nand ( n14331 , n14330 , n14288 );
nor ( n14332 , n14329 , n14331 );
not ( n14333 , n14288 );
nand ( n14334 , n14333 , n14290 );
nor ( n14335 , n14329 , n14334 );
nor ( n14336 , n14332 , n14335 );
not ( n14337 , n14312 );
or ( n14338 , n14337 , n14291 );
nand ( n14339 , n14338 , n14329 );
nand ( n14340 , n14336 , n14339 );
not ( n14341 , n14340 );
nand ( n14342 , n14341 , n14322 );
buf ( n14343 , n14342 );
nand ( n14344 , n14324 , n14343 );
buf ( n14345 , n14344 );
nand ( n14346 , n14298 , n14303 , n14306 );
not ( n14347 , n14308 );
nand ( n14348 , n14347 , n14298 );
not ( n14349 , n14298 );
nand ( n14350 , n14349 , n14303 , n14307 );
nand ( n14351 , n14349 , n14304 , n14306 );
nand ( n14352 , n14346 , n14348 , n14350 , n14351 );
buf ( n14353 , n14352 );
not ( n14354 , n14353 );
buf ( n14355 , n14322 );
nand ( n14356 , n14354 , n14355 );
buf ( n14357 , n14356 );
buf ( n14358 , n14357 );
buf ( n14359 , n13960 );
nand ( n14360 , n14358 , n14359 );
buf ( n14361 , n14360 );
buf ( n14362 , n14361 );
not ( n14363 , n14362 );
buf ( n14364 , n14363 );
not ( n14365 , n14322 );
buf ( n14366 , C1 );
buf ( n14367 , C1 );
or ( n14368 , n14274 , n14275 );
not ( n14369 , n14368 );
not ( n14370 , n14313 );
or ( n14371 , n14369 , n14370 );
nand ( n14372 , n14274 , n14275 );
nand ( n14373 , n14371 , n14372 );
not ( n14374 , n6540 );
and ( n14375 , n9559 , n14374 );
nor ( n14376 , n14373 , n14375 );
buf ( n14377 , n14376 );
not ( n14378 , n14377 );
buf ( n14379 , n14373 );
buf ( n14380 , n14375 );
nand ( n14381 , n14379 , n14380 );
buf ( n14382 , n14381 );
buf ( n14383 , n14382 );
nand ( n14384 , n14378 , n14383 );
buf ( n14385 , n14384 );
xnor ( n14386 , n14374 , n14376 );
or ( n14387 , n14386 , n14365 );
buf ( n14388 , n14387 );
buf ( n14389 , n14365 );
buf ( n14390 , n14385 );
or ( n14391 , n14389 , n14390 );
buf ( n14392 , n14391 );
buf ( n14393 , n14392 );
nand ( n14394 , n14388 , n14393 );
buf ( n14395 , n14394 );
buf ( n14396 , C1 );
buf ( n14397 , n14153 );
buf ( n14398 , n14163 );
nand ( n14399 , n14397 , n14398 );
buf ( n14400 , n14399 );
buf ( n14401 , n14400 );
not ( n14402 , n14401 );
buf ( n14403 , n14402 );
nor ( n14404 , n14345 , n14361 );
buf ( n14405 , n14404 );
buf ( n14406 , n14024 );
nand ( n14407 , n14405 , n14406 );
buf ( n14408 , n14407 );
buf ( n14409 , n14408 );
buf ( n14410 , n14395 );
nor ( n14411 , n14409 , n14410 );
buf ( n14412 , n14411 );
buf ( n14413 , n14408 );
not ( n14414 , n14413 );
buf ( n14415 , n14414 );
buf ( n14416 , C0 );
nor ( n14417 , C0 , n14416 );
buf ( n14418 , n14417 );
buf ( n14419 , n13211 );
buf ( n14420 , n12996 );
nand ( n14421 , n14419 , n14420 );
buf ( n14422 , n14421 );
buf ( n14423 , n14422 );
buf ( n14424 , n13203 );
buf ( n14425 , n14424 );
buf ( n14426 , n14425 );
buf ( n14427 , n14426 );
buf ( n14428 , n14426 );
buf ( n14429 , n14422 );
not ( n14430 , n14423 );
not ( n14431 , n14427 );
or ( n14432 , n14430 , n14431 );
or ( n14433 , n14428 , n14429 );
nand ( n14434 , n14432 , n14433 );
buf ( n14435 , n14434 );
buf ( n14436 , n14366 );
buf ( n14437 , n14357 );
nand ( n14438 , n14436 , n14437 );
buf ( n14439 , n14438 );
buf ( n14440 , n14439 );
not ( n14441 , n14440 );
buf ( n14442 , n14441 );
buf ( n14443 , n14323 );
buf ( n14444 , C1 );
nand ( n14445 , n14443 , n14444 );
buf ( n14446 , n14445 );
buf ( n14447 , n14446 );
not ( n14448 , n14447 );
buf ( n14449 , n14448 );
buf ( n14450 , C1 );
buf ( n14451 , n13202 );
buf ( n14452 , n13023 );
and ( n14453 , n14451 , n14452 );
buf ( n14454 , n14453 );
buf ( n14455 , n13191 );
buf ( n14456 , n13187 );
nand ( n14457 , n14455 , n14456 );
buf ( n14458 , n14457 );
buf ( n14459 , C1 );
buf ( n14460 , n14021 );
buf ( n14461 , C1 );
nand ( n14462 , n14460 , n14461 );
buf ( n14463 , n14462 );
xor ( n14464 , n13056 , n13101 );
xor ( n14465 , n14464 , n13135 );
buf ( n14466 , n14465 );
xor ( n14467 , n13119 , n13123 );
xor ( n14468 , n14467 , n13130 );
buf ( n14469 , n14468 );
buf ( n14470 , n14454 );
buf ( n14471 , n13192 );
xor ( n14472 , n14470 , n14471 );
buf ( n14473 , n14472 );
buf ( n14474 , n14458 );
buf ( n14475 , n13174 );
xnor ( n14476 , n14474 , n14475 );
buf ( n14477 , n14476 );
buf ( n14478 , n12000 );
buf ( n14479 , n13558 );
nand ( n14480 , n14478 , n14479 );
buf ( n14481 , n14480 );
buf ( n14482 , n14064 );
buf ( n14483 , C1 );
not ( n14484 , n14482 );
nand ( n14485 , n14484 , n14483 );
buf ( n14486 , n14485 );
xor ( n14487 , n12809 , n12863 );
xor ( n14488 , n14487 , n13215 );
buf ( n14489 , n14488 );
not ( n14490 , n14439 );
nand ( n14491 , n14490 , n13955 );
or ( n14492 , n14072 , n14491 );
not ( n14493 , n13960 );
nor ( n14494 , n14493 , n14442 );
nand ( n14495 , n14072 , n14494 );
nor ( n14496 , n14439 , C0 , n13960 );
nor ( n14497 , C0 , n14496 );
nand ( n14498 , n14492 , n14495 , n14497 );
buf ( n14499 , n14024 );
buf ( n14500 , n14364 );
and ( n14501 , n14499 , n14500 );
buf ( n14502 , n14501 );
and ( n14503 , n14502 , n14342 );
not ( n14504 , n14503 );
not ( n14505 , n14067 );
or ( n14506 , n14504 , n14505 );
nor ( n14507 , C0 , C0 );
nand ( n14508 , n14506 , n14507 );
and ( n14509 , n14508 , n14449 );
not ( n14510 , n14508 );
and ( n14511 , n14510 , n14446 );
nor ( n14512 , n14509 , n14511 );
and ( n14513 , n14387 , C1 );
not ( n14514 , n14415 );
not ( n14515 , n12587 );
not ( n14516 , n13313 );
or ( n14517 , n14515 , n14516 );
nand ( n14518 , n14517 , n13319 );
not ( n14519 , n14518 );
not ( n14520 , n13480 );
or ( n14521 , n14519 , n14520 );
nand ( n14522 , n14521 , n13510 );
and ( n14523 , n14049 , n14522 , n14048 );
nor ( n14524 , n14523 , C0 );
nand ( n14525 , n14066 , n14524 );
not ( n14526 , n14525 );
or ( n14527 , n14514 , n14526 );
nand ( n14528 , n14527 , n14367 );
not ( n14529 , n13142 );
nand ( n14530 , n13170 , n14529 );
or ( n14531 , n14530 , n13139 );
or ( n14532 , n13171 , n13173 );
and ( n14533 , n13171 , n13139 , n14529 );
not ( n14534 , n13139 );
and ( n14535 , n13171 , n14534 , n13142 );
nor ( n14536 , n14533 , n14535 );
nand ( n14537 , n14531 , n14532 , n14536 );
nand ( n14538 , n14071 , n13980 );
not ( n14539 , n14538 );
not ( n14540 , n14486 );
not ( n14541 , n14115 );
nor ( n14542 , n14100 , n14481 );
nand ( n14543 , n14541 , n14542 );
and ( n14544 , n14100 , n14481 );
not ( n14545 , n14100 );
nor ( n14546 , n14481 , n14102 );
and ( n14547 , n14545 , n14546 );
nor ( n14548 , n14544 , n14547 );
and ( n14549 , n14102 , n14481 );
nand ( n14550 , n14549 , n14115 );
nand ( n14551 , n14543 , n14548 , n14550 );
not ( n14552 , n14528 );
and ( n14553 , n14513 , n14450 );
nand ( n14554 , n14552 , n14553 );
nand ( n14555 , n14554 , C1 , C1 );
not ( n14556 , n13999 );
nor ( n14557 , n14556 , n14539 );
nor ( n14558 , n14538 , n14070 , n13999 );
not ( n14559 , n14525 );
and ( n14560 , n14559 , n14540 );
nor ( n14561 , n14560 , C0 );
not ( n14562 , n14561 );
not ( n14563 , n14561 );
or ( n14564 , n14365 , n14385 );
nand ( n14565 , n14564 , n14450 );
xnor ( n14566 , n14565 , n14528 );
and ( n14567 , n10091 , C1 );
not ( n14568 , n10306 );
not ( n14569 , n13570 );
or ( n14570 , n14568 , n14569 );
nand ( n14571 , n10294 , n10303 );
nand ( n14572 , n14570 , n14571 );
and ( n14573 , n14567 , n14572 );
not ( n14574 , n14567 );
and ( n14575 , n13570 , n10306 );
not ( n14576 , n14571 );
nor ( n14577 , n14575 , n14576 );
and ( n14578 , n14574 , n14577 );
nor ( n14579 , n14573 , n14578 );
not ( n14580 , n14412 );
not ( n14581 , n14525 );
or ( n14582 , n14580 , n14581 );
nand ( n14583 , n14582 , n14396 );
and ( n14584 , n14583 , n14365 );
not ( n14585 , n14583 );
and ( n14586 , n14585 , n14322 );
nor ( n14587 , n14584 , n14586 );
and ( n14588 , n14158 , n14403 );
not ( n14589 , n14158 );
and ( n14590 , n14589 , n14400 );
nor ( n14591 , n14588 , n14590 );
nand ( n14592 , n14525 , n14021 );
nand ( n14593 , n14192 , n14187 );
nand ( n14594 , n14592 , n14459 );
nand ( n14595 , C1 , n13999 );
not ( n14596 , n14595 );
and ( n14597 , n14594 , n14596 );
not ( n14598 , n14594 );
and ( n14599 , n14598 , n14595 );
nor ( n14600 , n14597 , n14599 );
nand ( n14601 , n14170 , n14148 );
not ( n14602 , n14601 );
and ( n14603 , n14164 , n14602 );
not ( n14604 , n14164 );
and ( n14605 , n14604 , n14601 );
nor ( n14606 , n14603 , n14605 );
not ( n14607 , n14557 );
or ( n14608 , n14592 , n14607 );
nor ( n14609 , C0 , n14538 );
nand ( n14610 , n14592 , n14609 );
not ( n14611 , n14539 );
and ( n14612 , n14611 , C0 );
nor ( n14613 , n14612 , n14558 );
nand ( n14614 , n14608 , n14610 , n14613 );
nand ( n14615 , n10306 , n14571 );
not ( n14616 , n14615 );
and ( n14617 , n13570 , n14616 );
not ( n14618 , n13570 );
and ( n14619 , n14618 , n14615 );
nor ( n14620 , n14617 , n14619 );
not ( n14621 , n13106 );
not ( n14622 , n401 );
and ( n14623 , n14621 , n14622 );
and ( n14624 , n13106 , n401 );
nor ( n14625 , n14623 , n14624 );
not ( n14626 , n14625 );
not ( n14627 , n13088 );
or ( n14628 , n14626 , n14627 );
or ( n14629 , n13088 , n14625 );
nand ( n14630 , n14628 , n14629 );
not ( n14631 , n14502 );
not ( n14632 , n14067 );
or ( n14633 , n14631 , n14632 );
nand ( n14634 , n14633 , n14418 );
nand ( n14635 , C1 , n14342 );
not ( n14636 , n14635 );
and ( n14637 , n14634 , n14636 );
not ( n14638 , n14634 );
and ( n14639 , n14638 , n14635 );
nor ( n14640 , n14637 , n14639 );
xor ( n14641 , n14559 , n14463 );
buf ( n14642 , n14189 );
buf ( n14643 , n14593 );
xnor ( n14644 , n14642 , n14643 );
buf ( n14645 , n14644 );
not ( C0n , n0 );
and ( C0 , C0n , n0 );
not ( C1n , n0 );
or ( C1 , C1n , n0 );
endmodule
|
(** * Hoare2: Hoare Logic, Part II *)
Require Export Hoare.
(* ####################################################### *)
(** * Decorated Programs *)
(** The beauty of Hoare Logic is that it is _compositional_ --
the structure of proofs exactly follows the structure of programs.
This suggests that we can record the essential ideas of a proof
informally (leaving out some low-level calculational details) by
decorating programs with appropriate assertions around each
statement. Such a _decorated program_ carries with it
an (informal) proof of its own correctness. *)
(** For example, here is a complete decorated program: *)
(**
{{ True }} ->>
{{ m = m }}
X ::= m;
{{ X = m }} ->>
{{ X = m /\ p = p }}
Z ::= p;
{{ X = m /\ Z = p }} ->>
{{ Z - X = p - m }}
WHILE X <> 0 DO
{{ Z - X = p - m /\ X <> 0 }} ->>
{{ (Z - 1) - (X - 1) = p - m }}
Z ::= Z - 1;
{{ Z - (X - 1) = p - m }}
X ::= X - 1
{{ Z - X = p - m }}
END;
{{ Z - X = p - m /\ ~ (X <> 0) }} ->>
{{ Z = p - m }} ->>
*)
(** Concretely, a decorated program consists of the program text
interleaved with assertions. To check that a decorated program
represents a valid proof, we check that each individual command is
_locally consistent_ with its accompanying assertions in the
following sense: *)
(**
- [SKIP] is locally consistent if its precondition and
postcondition are the same:
{{ P }}
SKIP
{{ P }}
- The sequential composition of [c1] and [c2] is locally
consistent (with respect to assertions [P] and [R]) if [c1] is
locally consistent (with respect to [P] and [Q]) and [c2] is
locally consistent (with respect to [Q] and [R]):
{{ P }}
c1;
{{ Q }}
c2
{{ R }}
- An assignment is locally consistent if its precondition is
the appropriate substitution of its postcondition:
{{ P [X |-> a] }}
X ::= a
{{ P }}
- A conditional is locally consistent (with respect to assertions
[P] and [Q]) if the assertions at the top of its "then" and
"else" branches are exactly [P /\ b] and [P /\ ~b] and if its "then"
branch is locally consistent (with respect to [P /\ b] and [Q])
and its "else" branch is locally consistent (with respect to
[P /\ ~b] and [Q]):
{{ P }}
IFB b THEN
{{ P /\ b }}
c1
{{ Q }}
ELSE
{{ P /\ ~b }}
c2
{{ Q }}
FI
{{ Q }}
- A while loop with precondition [P] is locally consistent if its
postcondition is [P /\ ~b] and if the pre- and postconditions of
its body are exactly [P /\ b] and [P]:
{{ P }}
WHILE b DO
{{ P /\ b }}
c1
{{ P }}
END
{{ P /\ ~b }}
- A pair of assertions separated by [->>] is locally consistent if
the first implies the second (in all states):
{{ P }} ->>
{{ P' }}
This corresponds to the application of [hoare_consequence] and
is the only place in a decorated program where checking if
decorations are correct is not fully mechanical and syntactic,
but involves logical and/or arithmetic reasoning.
*)
(** We have seen above how _verifying_ the correctness of a
given proof involves checking that every single command is locally
consistent with the accompanying assertions. If we are instead
interested in _finding_ a proof for a given specification we need
to discover the right assertions. This can be done in an almost
automatic way, with the exception of finding loop invariants,
which is the subject of in the next section. In the reminder of
this section we explain in detail how to construct decorations for
several simple programs that don't involve non-trivial loop
invariants. *)
(* ####################################################### *)
(** ** Example: Swapping Using Addition and Subtraction *)
(** Here is a program that swaps the values of two variables using
addition and subtraction (instead of by assigning to a temporary
variable).
X ::= X + Y;
Y ::= X - Y;
X ::= X - Y
We can prove using decorations that this program is correct --
i.e., it always swaps the values of variables [X] and [Y]. *)
(**
(1) {{ X = m /\ Y = n }} ->>
(2) {{ (X + Y) - ((X + Y) - Y) = n /\ (X + Y) - Y = m }}
X ::= X + Y;
(3) {{ X - (X - Y) = n /\ X - Y = m }}
Y ::= X - Y;
(4) {{ X - Y = n /\ Y = m }}
X ::= X - Y
(5) {{ X = n /\ Y = m }}
The decorations were constructed as follows:
- We begin with the undecorated program (the unnumbered lines).
- We then add the specification -- i.e., the outer
precondition (1) and postcondition (5). In the precondition we
use auxiliary variables (parameters) [m] and [n] to remember
the initial values of variables [X] and respectively [Y], so
that we can refer to them in the postcondition (5).
- We work backwards mechanically starting from (5) all the way
to (2). At each step, we obtain the precondition of the
assignment from its postcondition by substituting the assigned
variable with the right-hand-side of the assignment. For
instance, we obtain (4) by substituting [X] with [X - Y]
in (5), and (3) by substituting [Y] with [X - Y] in (4).
- Finally, we verify that (1) logically implies (2) -- i.e.,
that the step from (1) to (2) is a valid use of the law of
consequence. For this we substitute [X] by [m] and [Y] by [n]
and calculate as follows:
(m + n) - ((m + n) - n) = n /\ (m + n) - n = m
(m + n) - m = n /\ m = m
n = n /\ m = m
(Note that, since we are working with natural numbers, not
fixed-size machine integers, we don't need to worry about the
possibility of arithmetic overflow anywhere in this argument.)
*)
(* ####################################################### *)
(** ** Example: Simple Conditionals *)
(** Here is a simple decorated program using conditionals:
(1) {{True}}
IFB X <= Y THEN
(2) {{True /\ X <= Y}} ->>
(3) {{(Y - X) + X = Y \/ (Y - X) + Y = X}}
Z ::= Y - X
(4) {{Z + X = Y \/ Z + Y = X}}
ELSE
(5) {{True /\ ~(X <= Y) }} ->>
(6) {{(X - Y) + X = Y \/ (X - Y) + Y = X}}
Z ::= X - Y
(7) {{Z + X = Y \/ Z + Y = X}}
FI
(8) {{Z + X = Y \/ Z + Y = X}}
These decorations were constructed as follows:
- We start with the outer precondition (1) and postcondition (8).
- We follow the format dictated by the [hoare_if] rule and copy the
postcondition (8) to (4) and (7). We conjoin the precondition (1)
with the guard of the conditional to obtain (2). We conjoin (1)
with the negated guard of the conditional to obtain (5).
- In order to use the assignment rule and obtain (3), we substitute
[Z] by [Y - X] in (4). To obtain (6) we substitute [Z] by [X - Y]
in (7).
- Finally, we verify that (2) implies (3) and (5) implies (6). Both
of these implications crucially depend on the ordering of [X] and
[Y] obtained from the guard. For instance, knowing that [X <= Y]
ensures that subtracting [X] from [Y] and then adding back [X]
produces [Y], as required by the first disjunct of (3). Similarly,
knowing that [~(X <= Y)] ensures that subtracting [Y] from [X] and
then adding back [Y] produces [X], as needed by the second
disjunct of (6). Note that [n - m + m = n] does _not_ hold for
arbitrary natural numbers [n] and [m] (for example, [3 - 5 + 5 =
5]). *)
(** **** Exercise: 2 stars (if_minus_plus_reloaded) *)
(** Fill in valid decorations for the following program:
{{ True }}
IFB X <= Y THEN
{{ X <= Y }} ->>
{{ Y = X + (Y - X) }}
Z ::= Y - X
{{ Y = X + Z }}
ELSE
{{ ~(X <= Y) }} ->>
{{ X + Z = X + Z }}
Y ::= X + Z
{{ Y = X + Z }}
FI
{{ Y = X + Z }}
*)
(* ####################################################### *)
(** ** Example: Reduce to Zero (Trivial Loop) *)
(** Here is a [WHILE] loop that is so simple it needs no
invariant (i.e., the invariant [True] will do the job).
(1) {{ True }}
WHILE X <> 0 DO
(2) {{ True /\ X <> 0 }} ->>
(3) {{ True }}
X ::= X - 1
(4) {{ True }}
END
(5) {{ True /\ X = 0 }} ->>
(6) {{ X = 0 }}
The decorations can be constructed as follows:
- Start with the outer precondition (1) and postcondition (6).
- Following the format dictated by the [hoare_while] rule, we copy
(1) to (4). We conjoin (1) with the guard to obtain (2) and with
the negation of the guard to obtain (5). Note that, because the
outer postcondition (6) does not syntactically match (5), we need a
trivial use of the consequence rule from (5) to (6).
- Assertion (3) is the same as (4), because [X] does not appear in
[4], so the substitution in the assignment rule is trivial.
- Finally, the implication between (2) and (3) is also trivial.
*)
(** From this informal proof, it is easy to read off a formal proof
using the Coq versions of the Hoare rules. Note that we do _not_
unfold the definition of [hoare_triple] anywhere in this proof --
the idea is to use the Hoare rules as a "self-contained" logic for
reasoning about programs. *)
Definition reduce_to_zero' : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
X ::= AMinus (AId X) (ANum 1)
END.
Theorem reduce_to_zero_correct' :
{{fun st => True}}
reduce_to_zero'
{{fun st => st X = 0}}.
Proof.
unfold reduce_to_zero'.
(* First we need to transform the postcondition so
that hoare_while will apply. *)
eapply hoare_consequence_post.
apply hoare_while.
Case "Loop body preserves invariant".
(* Need to massage precondition before [hoare_asgn] applies *)
eapply hoare_consequence_pre. apply hoare_asgn.
(* Proving trivial implication (2) ->> (3) *)
intros st [HT Hbp]. unfold assn_sub. apply I.
Case "Invariant and negated guard imply postcondition".
intros st [Inv GuardFalse].
unfold bassn in GuardFalse. simpl in GuardFalse.
(* SearchAbout helps to find the right lemmas *)
SearchAbout [not true].
rewrite not_true_iff_false in GuardFalse.
SearchAbout [negb false].
rewrite negb_false_iff in GuardFalse.
SearchAbout [beq_nat true].
apply beq_nat_true in GuardFalse.
apply GuardFalse. Qed.
(* ####################################################### *)
(** ** Example: Division *)
(** The following Imp program calculates the integer division and
remainder of two numbers [m] and [n] that are arbitrary constants
in the program.
X ::= m;
Y ::= 0;
WHILE n <= X DO
X ::= X - n;
Y ::= Y + 1
END;
In other words, if we replace [m] and [n] by concrete numbers and
execute the program, it will terminate with the variable [X] set
to the remainder when [m] is divided by [n] and [Y] set to the
quotient. *)
(** In order to give a specification to this program we need to
remember that dividing [m] by [n] produces a reminder [X] and a
quotient [Y] so that [n * Y + X = m /\ X < n].
It turns out that we get lucky with this program and don't have to
think very hard about the loop invariant: the invariant is the
just first conjunct [n * Y + X = m], so we use that to decorate
the program.
(1) {{ True }} ->>
(2) {{ n * 0 + m = m }}
X ::= m;
(3) {{ n * 0 + X = m }}
Y ::= 0;
(4) {{ n * Y + X = m }}
WHILE n <= X DO
(5) {{ n * Y + X = m /\ n <= X }} ->>
(6) {{ n * (Y + 1) + (X - n) = m }}
X ::= X - n;
(7) {{ n * (Y + 1) + X = m }}
Y ::= Y + 1
(8) {{ n * Y + X = m }}
END
(9) {{ n * Y + X = m /\ X < n }}
Assertions (4), (5), (8), and (9) are derived mechanically from
the invariant and the loop's guard. Assertions (8), (7), and (6)
are derived using the assignment rule going backwards from (8) to
(6). Assertions (4), (3), and (2) are again backwards applications
of the assignment rule.
Now that we've decorated the program it only remains to check that
the two uses of the consequence rule are correct -- i.e., that (1)
implies (2) and that (5) implies (6). This is indeed the case, so
we have a valid decorated program.
*)
(* ####################################################### *)
(** * Finding Loop Invariants *)
(** Once the outermost precondition and postcondition are chosen, the
only creative part in verifying programs with Hoare Logic is
finding the right loop invariants. The reason this is difficult
is the same as the reason that doing inductive mathematical proofs
requires creativity: strengthening the loop invariant (or the
induction hypothesis) means that you have a stronger assumption to
work with when trying to establish the postcondition of the loop
body (complete the induction step of the proof), but it also means
that the loop body postcondition itself is harder to prove!
This section is dedicated to teaching you how to approach the
challenge of finding loop invariants using a series of examples
and exercises. *)
(** ** Example: Slow Subtraction *)
(** The following program subtracts the value of [X] from the value of
[Y] by repeatedly decrementing both [X] and [Y]. We want to verify its
correctness with respect to the following specification:
{{ X = m /\ Y = n }}
WHILE X <> 0 DO
Y ::= Y - 1;
X ::= X - 1
END
{{ Y = n - m }}
To verify this program we need to find an invariant [I] for the
loop. As a first step we can leave [I] as an unknown and build a
_skeleton_ for the proof by applying backward the rules for local
consistency. This process leads to the following skeleton:
(1) {{ X = m /\ Y = n }} ->> (a)
(2) {{ I }}
WHILE X <> 0 DO
(3) {{ I /\ X <> 0 }} ->> (c)
(4) {{ I[X |-> X-1][Y |-> Y-1] }}
Y ::= Y - 1;
(5) {{ I[X |-> X-1] }}
X ::= X - 1
(6) {{ I }}
END
(7) {{ I /\ ~(X <> 0) }} ->> (b)
(8) {{ Y = n - m }}
By examining this skeleton, we can see that any valid [I] will
have to respect three conditions:
- (a) it must be weak enough to be implied by the loop's
precondition, i.e. (1) must imply (2);
- (b) it must be strong enough to imply the loop's postcondition,
i.e. (7) must imply (8);
- (c) it must be preserved by one iteration of the loop, i.e. (3)
must imply (4). *)
(** These conditions are actually independent of the particular
program and specification we are considering. Indeed, every loop
invariant has to satisfy them. One way to find an invariant that
simultaneously satisfies these three conditions is by using an
iterative process: start with a "candidate" invariant (e.g. a
guess or a heuristic choice) and check the three conditions above;
if any of the checks fails, try to use the information that we get
from the failure to produce another (hopefully better) candidate
invariant, and repeat the process.
For instance, in the reduce-to-zero example above, we saw that,
for a very simple loop, choosing [True] as an invariant did the
job. So let's try it again here! I.e., let's instantiate [I] with
[True] in the skeleton above see what we get...
(1) {{ X = m /\ Y = n }} ->> (a - OK)
(2) {{ True }}
WHILE X <> 0 DO
(3) {{ True /\ X <> 0 }} ->> (c - OK)
(4) {{ True }}
Y ::= Y - 1;
(5) {{ True }}
X ::= X - 1
(6) {{ True }}
END
(7) {{ True /\ X = 0 }} ->> (b - WRONG!)
(8) {{ Y = n - m }}
While conditions (a) and (c) are trivially satisfied,
condition (b) is wrong, i.e. it is not the case that (7) [True /\
X = 0] implies (8) [Y = n - m]. In fact, the two assertions are
completely unrelated and it is easy to find a counterexample (say,
[Y = X = m = 0] and [n = 1]).
If we want (b) to hold, we need to strengthen the invariant so
that it implies the postcondition (8). One very simple way to do
this is to let the invariant _be_ the postcondition. So let's
return to our skeleton, instantiate [I] with [Y = n - m], and
check conditions (a) to (c) again.
(1) {{ X = m /\ Y = n }} ->> (a - WRONG!)
(2) {{ Y = n - m }}
WHILE X <> 0 DO
(3) {{ Y = n - m /\ X <> 0 }} ->> (c - WRONG!)
(4) {{ Y - 1 = n - m }}
Y ::= Y - 1;
(5) {{ Y = n - m }}
X ::= X - 1
(6) {{ Y = n - m }}
END
(7) {{ Y = n - m /\ X = 0 }} ->> (b - OK)
(8) {{ Y = n - m }}
This time, condition (b) holds trivially, but (a) and (c) are
broken. Condition (a) requires that (1) [X = m /\ Y = n]
implies (2) [Y = n - m]. If we substitute [X] by [m] we have to
show that [m = n - m] for arbitrary [m] and [n], which does not
hold (for instance, when [m = n = 1]). Condition (c) requires that
[n - m - 1 = n - m], which fails, for instance, for [n = 1] and [m =
0]. So, although [Y = n - m] holds at the end of the loop, it does
not hold from the start, and it doesn't hold on each iteration;
it is not a correct invariant.
This failure is not very surprising: the variable [Y] changes
during the loop, while [m] and [n] are constant, so the assertion
we chose didn't have much chance of being an invariant!
To do better, we need to generalize (8) to some statement that is
equivalent to (8) when [X] is [0], since this will be the case
when the loop terminates, and that "fills the gap" in some
appropriate way when [X] is nonzero. Looking at how the loop
works, we can observe that [X] and [Y] are decremented together
until [X] reaches [0]. So, if [X = 2] and [Y = 5] initially,
after one iteration of the loop we obtain [X = 1] and [Y = 4];
after two iterations [X = 0] and [Y = 3]; and then the loop stops.
Notice that the difference between [Y] and [X] stays constant
between iterations; initially, [Y = n] and [X = m], so this
difference is always [n - m]. So let's try instantiating [I] in
the skeleton above with [Y - X = n - m].
(1) {{ X = m /\ Y = n }} ->> (a - OK)
(2) {{ Y - X = n - m }}
WHILE X <> 0 DO
(3) {{ Y - X = n - m /\ X <> 0 }} ->> (c - OK)
(4) {{ (Y - 1) - (X - 1) = n - m }}
Y ::= Y - 1;
(5) {{ Y - (X - 1) = n - m }}
X ::= X - 1
(6) {{ Y - X = n - m }}
END
(7) {{ Y - X = n - m /\ X = 0 }} ->> (b - OK)
(8) {{ Y = n - m }}
Success! Conditions (a), (b) and (c) all hold now. (To
verify (c), we need to check that, under the assumption that [X <>
0], we have [Y - X = (Y - 1) - (X - 1)]; this holds for all
natural numbers [X] and [Y].) *)
(* ####################################################### *)
(** ** Exercise: Slow Assignment *)
(** **** Exercise: 2 stars (slow_assignment) *)
(** A roundabout way of assigning a number currently stored in [X] to
the variable [Y] is to start [Y] at [0], then decrement [X] until
it hits [0], incrementing [Y] at each step. Here is a program that
implements this idea:
{{ X = m }}
Y ::= 0;
WHILE X <> 0 DO
X ::= X - 1;
Y ::= Y + 1;
END
{{ Y = m }}
Write an informal decorated program showing that this is correct. *)
(* FILL IN HERE
{{ X = m }} ->>
{{ X = m /\ Y = Y }}
Y ::= 0;
{{ X = m /\ Y = 0 }} ->>
{{ X + Y = m }}
WHILE X <> 0 DO
{{ X + Y = m /\ X <> 0 }} ->>
{{ (X-1) + (Y+1) = m }}
X ::= X - 1;
{{ X + (Y+1) = m }}
Y ::= Y + 1;
{{ X + Y = m }}
END
{{ I /\ ~(X <> 0) }} ->>
{{ Y = m }}
*)
(** [] *)
(* ####################################################### *)
(** ** Exercise: Slow Addition *)
(** **** Exercise: 3 stars, optional (add_slowly_decoration) *)
(** The following program adds the variable X into the variable Z
by repeatedly decrementing X and incrementing Z.
WHILE X <> 0 DO
Z ::= Z + 1;
X ::= X - 1
END
Following the pattern of the [subtract_slowly] example above, pick
a precondition and postcondition that give an appropriate
specification of [add_slowly]; then (informally) decorate the
program accordingly. *)
(*
{{ Z = n /\ X = m }} ->>
{{ Z + X = n + m }}
WHILE X <> 0 DO
{{ Z + X = n + m /\ X <> 0 }} ->>
{{ (Z+1) + (X-1) = n + m }}
Z ::= Z + 1;
{{ Z + (X-1) = n + m }}
X ::= X - 1
{{ Z + X = n + m }}
END
{{ Z + X = n + m /\ ~(X <> 0) }} ->>
{{ Z = n + m }}
*)
(** [] *)
(* ####################################################### *)
(** ** Example: Parity *)
(** Here is a cute little program for computing the parity of the
value initially stored in [X] (due to Daniel Cristofani).
{{ X = m }}
WHILE 2 <= X DO
X ::= X - 2
END
{{ X = parity m }}
The mathematical [parity] function used in the specification is
defined in Coq as follows: *)
Fixpoint parity x :=
match x with
| 0 => 0
| 1 => 1
| S (S x') => parity x'
end.
(** The postcondition does not hold at the beginning of the loop,
since [m = parity m] does not hold for an arbitrary [m], so we
cannot use that as an invariant. To find an invariant that works,
let's think a bit about what this loop does. On each iteration it
decrements [X] by [2], which preserves the parity of [X]. So the
parity of [X] does not change, i.e. it is invariant. The initial
value of [X] is [m], so the parity of [X] is always equal to the
parity of [m]. Using [parity X = parity m] as an invariant we
obtain the following decorated program:
{{ X = m }} ->> (a - OK)
{{ parity X = parity m }}
WHILE 2 <= X DO
{{ parity X = parity m /\ 2 <= X }} ->> (c - OK)
{{ parity (X-2) = parity m }}
X ::= X - 2
{{ parity X = parity m }}
END
{{ parity X = parity m /\ X < 2 }} ->> (b - OK)
{{ X = parity m }}
With this invariant, conditions (a), (b), and (c) are all
satisfied. For verifying (b), we observe that, when [X < 2], we
have [parity X = X] (we can easily see this in the definition of
[parity]). For verifying (c), we observe that, when [2 <= X], we
have [parity X = parity (X-2)]. *)
(** **** Exercise: 3 stars, optional (parity_formal) *)
(** Translate this proof to Coq. Refer to the reduce-to-zero example
for ideas. You may find the following two lemmas useful: *)
Lemma parity_ge_2 : forall x,
2 <= x ->
parity (x - 2) = parity x.
Proof.
induction x; intro. reflexivity.
destruct x. inversion H. inversion H1.
simpl. rewrite <- minus_n_O. reflexivity.
Qed.
Lemma parity_lt_2 : forall x,
~ 2 <= x ->
parity (x) = x.
Proof.
intros. induction x. reflexivity. destruct x. reflexivity.
apply ex_falso_quodlibet. apply H. omega.
Qed.
Theorem parity_correct : forall m,
{{ fun st => st X = m }}
WHILE BLe (ANum 2) (AId X) DO
X ::= AMinus (AId X) (ANum 2)
END
{{ fun st => st X = parity m }}.
Proof.
intro m.
eapply hoare_consequence.
apply hoare_while with (P:=fun st => parity (st X) = parity m).
Case "Body preserves invariant".
eapply hoare_consequence_pre.
apply hoare_asgn. intros st [Hpar Hb].
unfold assn_sub, update. simpl. rewrite <- Hpar. apply parity_ge_2.
unfold bassn, beval, aeval in Hb. apply ble_nat_true in Hb. assumption.
Case "Pre condition".
intros st H. rewrite H. reflexivity.
Case "Post condition".
intros st [Hpar Hb]. rewrite <- Hpar. symmetry. apply parity_lt_2.
unfold bassn,beval,aeval in Hb. rewrite not_true_iff_false in Hb.
apply ble_nat_false in Hb. assumption.
Qed.
(** [] *)
(* ####################################################### *)
(** ** Example: Finding Square Roots *)
(** The following program computes the square root of [X]
by naive iteration:
{{ X=m }}
Z ::= 0;
WHILE (Z+1)*(Z+1) <= X DO
Z ::= Z+1
END
{{ Z*Z<=m /\ m<(Z+1)*(Z+1) }}
*)
(** As above, we can try to use the postcondition as a candidate
invariant, obtaining the following decorated program:
(1) {{ X=m }} ->> (a - second conjunct of (2) WRONG!)
(2) {{ 0*0 <= m /\ m<1*1 }}
Z ::= 0;
(3) {{ Z*Z <= m /\ m<(Z+1)*(Z+1) }}
WHILE (Z+1)*(Z+1) <= X DO
(4) {{ Z*Z<=m /\ (Z+1)*(Z+1)<=X }} ->> (c - WRONG!)
(5) {{ (Z+1)*(Z+1)<=m /\ m<(Z+2)*(Z+2) }}
Z ::= Z+1
(6) {{ Z*Z<=m /\ m<(Z+1)*(Z+1) }}
END
(7) {{ Z*Z<=m /\ m<(Z+1)*(Z+1) /\ X<(Z+1)*(Z+1) }} ->> (b - OK)
(8) {{ Z*Z<=m /\ m<(Z+1)*(Z+1) }}
This didn't work very well: both conditions (a) and (c) failed.
Looking at condition (c), we see that the second conjunct of (4)
is almost the same as the first conjunct of (5), except that (4)
mentions [X] while (5) mentions [m]. But note that [X] is never
assigned in this program, so we should have [X=m], but we didn't
propagate this information from (1) into the loop invariant.
Also, looking at the second conjunct of (8), it seems quite
hopeless as an invariant -- and we don't even need it, since we
can obtain it from the negation of the guard (third conjunct
in (7)), again under the assumption that [X=m].
So we now try [X=m /\ Z*Z <= m] as the loop invariant:
{{ X=m }} ->> (a - OK)
{{ X=m /\ 0*0 <= m }}
Z ::= 0;
{{ X=m /\ Z*Z <= m }}
WHILE (Z+1)*(Z+1) <= X DO
{{ X=m /\ Z*Z<=m /\ (Z+1)*(Z+1)<=X }} ->> (c - OK)
{{ X=m /\ (Z+1)*(Z+1)<=m }}
Z ::= Z+1
{{ X=m /\ Z*Z<=m }}
END
{{ X=m /\ Z*Z<=m /\ X<(Z+1)*(Z+1) }} ->> (b - OK)
{{ Z*Z<=m /\ m<(Z+1)*(Z+1) }}
This works, since conditions (a), (b), and (c) are now all
trivially satisfied.
Very often, if a variable is used in a loop in a read-only
fashion (i.e., it is referred to by the program or by the
specification and it is not changed by the loop) it is necessary
to add the fact that it doesn't change to the loop invariant. *)
(* ####################################################### *)
(** ** Example: Squaring *)
(** Here is a program that squares [X] by repeated addition:
{{ X = m }}
Y ::= 0;
Z ::= 0;
WHILE Y <> X DO
Z ::= Z + X;
Y ::= Y + 1
END
{{ Z = m*m }}
*)
(** The first thing to note is that the loop reads [X] but doesn't
change its value. As we saw in the previous example, in such cases
it is a good idea to add [X = m] to the invariant. The other thing
we often use in the invariant is the postcondition, so let's add
that too, leading to the invariant candidate [Z = m * m /\ X = m].
{{ X = m }} ->> (a - WRONG)
{{ 0 = m*m /\ X = m }}
Y ::= 0;
{{ 0 = m*m /\ X = m }}
Z ::= 0;
{{ Z = m*m /\ X = m }}
WHILE Y <> X DO
{{ Z = Y*m /\ X = m /\ Y <> X }} ->> (c - WRONG)
{{ Z+X = m*m /\ X = m }}
Z ::= Z + X;
{{ Z = m*m /\ X = m }}
Y ::= Y + 1
{{ Z = m*m /\ X = m }}
END
{{ Z = m*m /\ X = m /\ Y = X }} ->> (b - OK)
{{ Z = m*m }}
Conditions (a) and (c) fail because of the [Z = m*m] part. While
[Z] starts at [0] and works itself up to [m*m], we can't expect
[Z] to be [m*m] from the start. If we look at how [Z] progesses
in the loop, after the 1st iteration [Z = m], after the 2nd
iteration [Z = 2*m], and at the end [Z = m*m]. Since the variable
[Y] tracks how many times we go through the loop, we derive the
new invariant candidate [Z = Y*m /\ X = m].
{{ X = m }} ->> (a - OK)
{{ 0 = 0*m /\ X = m }}
Y ::= 0;
{{ 0 = Y*m /\ X = m }}
Z ::= 0;
{{ Z = Y*m /\ X = m }}
WHILE Y <> X DO
{{ Z = Y*m /\ X = m /\ Y <> X }} ->> (c - OK)
{{ Z+X = (Y+1)*m /\ X = m }}
Z ::= Z + X;
{{ Z = (Y+1)*m /\ X = m }}
Y ::= Y + 1
{{ Z = Y*m /\ X = m }}
END
{{ Z = Y*m /\ X = m /\ Y = X }} ->> (b - OK)
{{ Z = m*m }}
This new invariant makes the proof go through: all three
conditions are easy to check.
It is worth comparing the postcondition [Z = m*m] and the [Z =
Y*m] conjunct of the invariant. It is often the case that one has
to replace auxiliary variabes (parameters) with variables -- or
with expressions involving both variables and parameters (like
[m - Y]) -- when going from postconditions to invariants. *)
(* ####################################################### *)
(** ** Exercise: Factorial *)
(** **** Exercise: 3 stars (factorial) *)
(** Recall that [n!] denotes the factorial of [n] (i.e. [n! =
1*2*...*n]). Here is an Imp program that calculates the factorial
of the number initially stored in the variable [X] and puts it in
the variable [Y]:
{{ X = m }} ;
Y ::= 1
WHILE X <> 0
DO
Y ::= Y * X
X ::= X - 1
END
{{ Y = m! }}
Fill in the blanks in following decorated program:
{{ X = m }} ->>
{{ 1 = m! / X! }}
Y ::= 1;
{{ Y = m! / X! }}
WHILE X <> 0
DO {{ Y = m! / X! /\ X <> 0 }} ->>
{{ Y*X = m! / (X-1)! }}
Y ::= Y * X;
{{ Y = m! / (X-1)! }}
X ::= X - 1
{{ Y = m! / X! }}
END
{{ Y = m! / X! /\ ~ (X <> 0) }} ->>
{{ Y = m! }}
*)
(** [] *)
(* ####################################################### *)
(** ** Exercise: Min *)
(** **** Exercise: 3 stars (Min_Hoare) *)
(** Fill in valid decorations for the following program.
For the => steps in your annotations, you may rely (silently) on the
following facts about min
Lemma lemma1 : forall x y,
(x=0 \/ y=0) -> min x y = 0.
Lemma lemma2 : forall x y,
min (x-1) (y-1) = (min x y) - 1.
plus, as usual, standard high-school algebra.
{{ True }} ->>
{{ a = a /\ b = b /\ 0 = 0 }}
X ::= a;
{{ X = a /\ b = b /\ 0 = 0 }}
Y ::= b;
{{ X = a /\ Y = b /\ 0 = 0 }}
Z ::= 0;
{{ X = a /\ Y = b /\ Z = 0 }}
WHILE (X <> 0 /\ Y <> 0) DO
{{ Z = min a b - min X Y /\ X <> 0 /\ Y <> 0 }} ->>
{{ Z + 1 = min a b - min (X - 1) (Y - 1) }}
X := X - 1;
{{ Z + 1 = min a b - min X (Y - 1) }}
Y := Y - 1;
{{ Z + 1 = min a b - min X Y }}
Z := Z + 1;
{{ Z = min a b - min X Y }}
END
{{ Z = min a b - min X Y /\ ~( X <> 0 /\ Y <> 0) }} ->>
{{ Z = min a b }}
*)
(** **** Exercise: 3 stars (two_loops) *)
(** Here is a very inefficient way of adding 3 numbers:
X ::= 0;
Y ::= 0;
Z ::= c;
WHILE X <> a DO
X ::= X + 1;
Z ::= Z + 1
END;
WHILE Y <> b DO
Y ::= Y + 1;
Z ::= Z + 1
END
Show that it does what it should by filling in the blanks in the
following decorated program.
{{ True }} ->>
{{ 0 = 0 /\ 0 = 0 /\ c = c }}
X ::= 0;
{{ X = 0 /\ 0 = 0 /\ c = c }}
Y ::= 0;
{{ X = 0 /\ Y = 0 /\ c = c }}
Z ::= c;
{{ X = 0 /\ Y = 0 /\ Z = c }}
WHILE X <> a DO
{{ Z = c + X + Y /\ X <> a }} ->>
{{ Z + 1 = c + (X + 1) + Y }}
X ::= X + 1;
{{ Z + 1 = c + X + Y }}
Z ::= Z + 1
{{ Z = c + X + Y }}
END;
{{ Z = c + X + Y /\ ~ ( X <> a) }} ->>
{{ Z = c + a + Y }}
WHILE Y <> b DO
{{ Z = c + a + Y /\ Y <> b }} ->>
{{ Z + 1 = c + a + Y + 1 }}
Y ::= Y + 1;
{{ Z + 1 = c + a + Y }}
Z ::= Z + 1
{{ Z = c + a + Y }}
END
{{ Z = c + a + Y /\ ~ ( Y <> b ) }} ->>
{{ Z = a + b + c }}
*)
(* ####################################################### *)
(** ** Exercise: Power Series *)
(** **** Exercise: 4 stars, optional (dpow2_down) *)
(** Here is a program that computes the series:
[1 + 2 + 2^2 + ... + 2^m = 2^(m+1) - 1]
X ::= 0;
Y ::= 1;
Z ::= 1;
WHILE X <> m DO
Z ::= 2 * Z;
Y ::= Y + Z;
X ::= X + 1;
END
Write a decorated program for this. *)
(*
{{ 0 = 0 /\ 1 = 1 /\ 1 = 1 }}
X ::= 0;
Y ::= 1;
Z ::= 1;
{{ X = 0 /\ Y = 1 /\ Z = 1 }} ->>
{{ Y = 2^(X+1) - 1 /\ Z = 2^X /\ X = 0}}
WHILE X <> m DO
{{ Y = 2^(X+1) - 1 /\ Z = 2^X /\ X <> m}} ->>
{{ Y = 2^(X+1) - 1 /\ 2*Z = 2^(X+1) }}
Z ::= 2 * Z;
{{ Y = 2^(X+1) - 1 /\ Z = 2^(X+1) }} ->>
{{ Y + Z = 2^(X+1) - 1 + 2^(X+1) /\ Z = 2^(X+1) }}
Y ::= Y + Z;
{{ Y = 2^(X+1) - 1 + 2^(X+1)}} ->>
{{ Y = 2^(X+1+1) - 1 /\ Z = 2^(X+1) }}
X ::= X + 1;
{{ Y = 2^(X+1) - 1 /\ Z = 2^X }}
END
{{ Y = 2^(X+1) - 1 /\ Z = 2^X /\ ~ (X <> m) }} ->>
{{ Y = 2^(m+1) - 1 }}
*)
(* ####################################################### *)
(** * Weakest Preconditions (Advanced) *)
(** Some Hoare triples are more interesting than others.
For example,
{{ False }} X ::= Y + 1 {{ X <= 5 }}
is _not_ very interesting: although it is perfectly valid, it
tells us nothing useful. Since the precondition isn't satisfied
by any state, it doesn't describe any situations where we can use
the command [X ::= Y + 1] to achieve the postcondition [X <= 5].
By contrast,
{{ Y <= 4 /\ Z = 0 }} X ::= Y + 1 {{ X <= 5 }}
is useful: it tells us that, if we can somehow create a situation
in which we know that [Y <= 4 /\ Z = 0], then running this command
will produce a state satisfying the postcondition. However, this
triple is still not as useful as it could be, because the [Z = 0]
clause in the precondition actually has nothing to do with the
postcondition [X <= 5]. The _most_ useful triple (for a given
command and postcondition) is this one:
{{ Y <= 4 }} X ::= Y + 1 {{ X <= 5 }}
In other words, [Y <= 4] is the _weakest_ valid precondition of
the command [X ::= Y + 1] for the postcondition [X <= 5]. *)
(** In general, we say that "[P] is the weakest precondition of
command [c] for postcondition [Q]" if [{{P}} c {{Q}}] and if,
whenever [P'] is an assertion such that [{{P'}} c {{Q}}], we have
[P' st] implies [P st] for all states [st]. *)
Definition is_wp P c Q :=
{{P}} c {{Q}} /\
forall P', {{P'}} c {{Q}} -> (P' ->> P).
(** That is, [P] is the weakest precondition of [c] for [Q]
if (a) [P] _is_ a precondition for [Q] and [c], and (b) [P] is the
_weakest_ (easiest to satisfy) assertion that guarantees [Q] after
executing [c]. *)
(** **** Exercise: 1 star, optional (wp) *)
(** What are the weakest preconditions of the following commands
for the following postconditions?
1) {{ X = 5 }} SKIP {{ X = 5 }}
2) {{ Y + Z = 5 }} X ::= Y + Z {{ X = 5 }}
3) {{ True }} X ::= Y {{ X = Y }}
4) {{ X = 0 /\ Z = 4 \/ X <> 0 /\ W = 3 }}
IFB X == 0 THEN Y ::= Z + 1 ELSE Y ::= W + 2 FI
{{ Y = 5 }}
5) {{ False }}
X ::= 5
{{ X = 0 }}
6) {{ True }}
WHILE True DO X ::= 0 END
{{ X = 0 }}
*)
(** [] *)
(** **** Exercise: 3 stars, advanced, optional (is_wp_formal) *)
(** Prove formally using the definition of [hoare_triple] that [Y <= 4]
is indeed the weakest precondition of [X ::= Y + 1] with respect to
postcondition [X <= 5]. *)
Theorem is_wp_example :
is_wp (fun st => st Y <= 4)
(X ::= APlus (AId Y) (ANum 1)) (fun st => st X <= 5).
Proof.
unfold is_wp. split.
Case "{{P}} c {{Q}}".
eapply hoare_consequence_pre. apply hoare_asgn.
unfold assert_implies, assn_sub, aeval, update. intros st H. simpl. omega.
Case "P' ->> P".
unfold assert_implies, hoare_triple.
intros P Hassn st HP.
apply Hassn with (st' := update st X (aeval st (APlus (AId Y) (ANum 1)))) in HP.
unfold update, aeval in HP. simpl in HP. omega. constructor. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars, advanced (hoare_asgn_weakest) *)
(** Show that the precondition in the rule [hoare_asgn] is in fact the
weakest precondition. *)
Theorem hoare_asgn_weakest : forall Q X a,
is_wp (Q [X |-> a]) (X ::= a) Q.
Proof.
unfold is_wp. intros Q X a. split.
Case "{{P}} c {{Q}}". apply hoare_asgn.
Case "P' ->> P".
unfold assert_implies, hoare_triple, assn_sub. intros P Hassn st HP.
apply Hassn with (st:=st). constructor. reflexivity. assumption.
Qed.
(** [] *)
(** **** Exercise: 2 stars, advanced, optional (hoare_havoc_weakest) *)
(** Show that your [havoc_pre] rule from the [himp_hoare] exercise
in the [Hoare] chapter returns the weakest precondition. *)
Module Himp2.
Import Himp.
Lemma hoare_havoc_weakest : forall (P Q : Assertion) (X : id),
{{ P }} HAVOC X {{ Q }} ->
P ->> havoc_pre X Q.
Proof.
unfold assert_implies, havoc_pre. intros P Q X H st HP n.
apply (H st). constructor. assumption.
Qed.
End Himp2.
(** [] *)
(* ####################################################### *)
(** * Formal Decorated Programs (Advanced) *)
(** The informal conventions for decorated programs amount to a way of
displaying Hoare triples in which commands are annotated with
enough embedded assertions that checking the validity of the
triple is reduced to simple logical and algebraic calculations
showing that some assertions imply others. In this section, we
show that this informal presentation style can actually be made
completely formal and indeed that checking the validity of
decorated programs can mostly be automated. *)
(** ** Syntax *)
(** The first thing we need to do is to formalize a variant of the
syntax of commands with embedded assertions. We call the new
commands _decorated commands_, or [dcom]s. *)
Inductive dcom : Type :=
| DCSkip : Assertion -> dcom
| DCSeq : dcom -> dcom -> dcom
| DCAsgn : id -> aexp -> Assertion -> dcom
| DCIf : bexp -> Assertion -> dcom -> Assertion -> dcom
-> Assertion-> dcom
| DCWhile : bexp -> Assertion -> dcom -> Assertion -> dcom
| DCPre : Assertion -> dcom -> dcom
| DCPost : dcom -> Assertion -> dcom.
Tactic Notation "dcom_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "Skip" | Case_aux c "Seq" | Case_aux c "Asgn"
| Case_aux c "If" | Case_aux c "While"
| Case_aux c "Pre" | Case_aux c "Post" ].
Notation "'SKIP' {{ P }}"
:= (DCSkip P)
(at level 10) : dcom_scope.
Notation "l '::=' a {{ P }}"
:= (DCAsgn l a P)
(at level 60, a at next level) : dcom_scope.
Notation "'WHILE' b 'DO' {{ Pbody }} d 'END' {{ Ppost }}"
:= (DCWhile b Pbody d Ppost)
(at level 80, right associativity) : dcom_scope.
Notation "'IFB' b 'THEN' {{ P }} d 'ELSE' {{ P' }} d' 'FI' {{ Q }}"
:= (DCIf b P d P' d' Q)
(at level 80, right associativity) : dcom_scope.
Notation "'->>' {{ P }} d"
:= (DCPre P d)
(at level 90, right associativity) : dcom_scope.
Notation "{{ P }} d"
:= (DCPre P d)
(at level 90) : dcom_scope.
Notation "d '->>' {{ P }}"
:= (DCPost d P)
(at level 80, right associativity) : dcom_scope.
Notation " d ;; d' "
:= (DCSeq d d')
(at level 80, right associativity) : dcom_scope.
Delimit Scope dcom_scope with dcom.
(** To avoid clashing with the existing [Notation] definitions
for ordinary [com]mands, we introduce these notations in a special
scope called [dcom_scope], and we wrap examples with the
declaration [% dcom] to signal that we want the notations to be
interpreted in this scope.
Careful readers will note that we've defined two notations for the
[DCPre] constructor, one with and one without a [->>]. The
"without" version is intended to be used to supply the initial
precondition at the very top of the program. *)
Example dec_while : dcom := (
{{ fun st => True }}
WHILE (BNot (BEq (AId X) (ANum 0)))
DO
{{ fun st => True /\ st X <> 0}}
X ::= (AMinus (AId X) (ANum 1))
{{ fun _ => True }}
END
{{ fun st => True /\ st X = 0}} ->>
{{ fun st => st X = 0 }}
) % dcom.
(** It is easy to go from a [dcom] to a [com] by erasing all
annotations. *)
Fixpoint extract (d:dcom) : com :=
match d with
| DCSkip _ => SKIP
| DCSeq d1 d2 => (extract d1 ;; extract d2)
| DCAsgn X a _ => X ::= a
| DCIf b _ d1 _ d2 _ => IFB b THEN extract d1 ELSE extract d2 FI
| DCWhile b _ d _ => WHILE b DO extract d END
| DCPre _ d => extract d
| DCPost d _ => extract d
end.
(** The choice of exactly where to put assertions in the definition of
[dcom] is a bit subtle. The simplest thing to do would be to
annotate every [dcom] with a precondition and postcondition. But
this would result in very verbose programs with a lot of repeated
annotations: for example, a program like [SKIP;SKIP] would have to
be annotated as
{{P}} ({{P}} SKIP {{P}}) ;; ({{P}} SKIP {{P}}) {{P}},
with pre- and post-conditions on each [SKIP], plus identical pre-
and post-conditions on the semicolon!
Instead, the rule we've followed is this:
- The _post_-condition expected by each [dcom] [d] is embedded in [d]
- The _pre_-condition is supplied by the context. *)
(** In other words, the invariant of the representation is that a
[dcom] [d] together with a precondition [P] determines a Hoare
triple [{{P}} (extract d) {{post d}}], where [post] is defined as
follows: *)
Fixpoint post (d:dcom) : Assertion :=
match d with
| DCSkip P => P
| DCSeq d1 d2 => post d2
| DCAsgn X a Q => Q
| DCIf _ _ d1 _ d2 Q => Q
| DCWhile b Pbody c Ppost => Ppost
| DCPre _ d => post d
| DCPost c Q => Q
end.
(** Similarly, we can extract the "initial precondition" from a
decorated program. *)
Fixpoint pre (d:dcom) : Assertion :=
match d with
| DCSkip P => fun st => True
| DCSeq c1 c2 => pre c1
| DCAsgn X a Q => fun st => True
| DCIf _ _ t _ e _ => fun st => True
| DCWhile b Pbody c Ppost => fun st => True
| DCPre P c => P
| DCPost c Q => pre c
end.
(** This function is not doing anything sophisticated like calculating
a weakest precondition; it just recursively searches for an
explicit annotation at the very beginning of the program,
returning default answers for programs that lack an explicit
precondition (like a bare assignment or [SKIP]). *)
(** Using [pre] and [post], and assuming that we adopt the convention
of always supplying an explicit precondition annotation at the
very beginning of our decorated programs, we can express what it
means for a decorated program to be correct as follows: *)
Definition dec_correct (d:dcom) :=
{{pre d}} (extract d) {{post d}}.
(** To check whether this Hoare triple is _valid_, we need a way to
extract the "proof obligations" from a decorated program. These
obligations are often called _verification conditions_, because
they are the facts that must be verified to see that the
decorations are logically consistent and thus add up to a complete
proof of correctness. *)
(** ** Extracting Verification Conditions *)
(** The function [verification_conditions] takes a [dcom] [d] together
with a precondition [P] and returns a _proposition_ that, if it
can be proved, implies that the triple [{{P}} (extract d) {{post d}}]
is valid. *)
(** It does this by walking over [d] and generating a big
conjunction including all the "local checks" that we listed when
we described the informal rules for decorated programs. (Strictly
speaking, we need to massage the informal rules a little bit to
add some uses of the rule of consequence, but the correspondence
should be clear.) *)
Fixpoint verification_conditions (P : Assertion) (d:dcom) : Prop :=
match d with
| DCSkip Q =>
(P ->> Q)
| DCSeq d1 d2 =>
verification_conditions P d1
/\ verification_conditions (post d1) d2
| DCAsgn X a Q =>
(P ->> Q [X |-> a])
| DCIf b P1 d1 P2 d2 Q =>
((fun st => P st /\ bassn b st) ->> P1)
/\ ((fun st => P st /\ ~ (bassn b st)) ->> P2)
/\ (Q <<->> post d1) /\ (Q <<->> post d2)
/\ verification_conditions P1 d1
/\ verification_conditions P2 d2
| DCWhile b Pbody d Ppost =>
(* post d is the loop invariant and the initial precondition *)
(P ->> post d)
/\ (Pbody <<->> (fun st => post d st /\ bassn b st))
/\ (Ppost <<->> (fun st => post d st /\ ~(bassn b st)))
/\ verification_conditions Pbody d
| DCPre P' d =>
(P ->> P') /\ verification_conditions P' d
| DCPost d Q =>
verification_conditions P d /\ (post d ->> Q)
end.
(** And now, the key theorem, which states that
[verification_conditions] does its job correctly. Not
surprisingly, we need to use each of the Hoare Logic rules at some
point in the proof. *)
(** We have used _in_ variants of several tactics before to
apply them to values in the context rather than the goal. An
extension of this idea is the syntax [tactic in *], which applies
[tactic] in the goal and every hypothesis in the context. We most
commonly use this facility in conjunction with the [simpl] tactic,
as below. *)
Theorem verification_correct : forall d P,
verification_conditions P d -> {{P}} (extract d) {{post d}}.
Proof.
dcom_cases (induction d) Case; intros P H; simpl in *.
Case "Skip".
eapply hoare_consequence_pre.
apply hoare_skip.
assumption.
Case "Seq".
inversion H as [H1 H2]. clear H.
eapply hoare_seq.
apply IHd2. apply H2.
apply IHd1. apply H1.
Case "Asgn".
eapply hoare_consequence_pre.
apply hoare_asgn.
assumption.
Case "If".
inversion H as [HPre1 [HPre2 [[Hd11 Hd12]
[[Hd21 Hd22] [HThen HElse]]]]].
clear H.
apply IHd1 in HThen. clear IHd1.
apply IHd2 in HElse. clear IHd2.
apply hoare_if.
eapply hoare_consequence_pre; eauto.
eapply hoare_consequence_post; eauto.
eapply hoare_consequence_pre; eauto.
eapply hoare_consequence_post; eauto.
Case "While".
inversion H as [Hpre [[Hbody1 Hbody2] [[Hpost1 Hpost2] Hd]]];
subst; clear H.
eapply hoare_consequence_pre; eauto.
eapply hoare_consequence_post; eauto.
apply hoare_while.
eapply hoare_consequence_pre; eauto.
Case "Pre".
inversion H as [HP Hd]; clear H.
eapply hoare_consequence_pre. apply IHd. apply Hd. assumption.
Case "Post".
inversion H as [Hd HQ]; clear H.
eapply hoare_consequence_post. apply IHd. apply Hd. assumption.
Qed.
(** ** Examples *)
(** The propositions generated by [verification_conditions] are fairly
big, and they contain many conjuncts that are essentially trivial. *)
Eval simpl in (verification_conditions (fun st => True) dec_while).
(**
==>
(((fun _ : state => True) ->> (fun _ : state => True)) /\
((fun _ : state => True) ->> (fun _ : state => True)) /\
(fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st) =
(fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st) /\
(fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st) =
(fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st) /\
(fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st) ->>
(fun _ : state => True) [X |-> AMinus (AId X) (ANum 1)]) /\
(fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st) ->>
(fun st : state => st X = 0)
*)
(** In principle, we could certainly work with them using just the
tactics we have so far, but we can make things much smoother with
a bit of automation. We first define a custom [verify] tactic
that applies splitting repeatedly to turn all the conjunctions
into separate subgoals and then uses [omega] and [eauto] (a handy
general-purpose automation tactic that we'll discuss in detail
later) to deal with as many of them as possible. *)
Lemma ble_nat_true_iff : forall n m : nat,
ble_nat n m = true <-> n <= m.
Proof.
intros n m. split. apply ble_nat_true.
generalize dependent m. induction n; intros m H. reflexivity.
simpl. destruct m. inversion H.
apply le_S_n in H. apply IHn. assumption.
Qed.
Lemma ble_nat_false_iff : forall n m : nat,
ble_nat n m = false <-> ~(n <= m).
Proof.
intros n m. split. apply ble_nat_false.
generalize dependent m. induction n; intros m H.
apply ex_falso_quodlibet. apply H. apply le_0_n.
simpl. destruct m. reflexivity.
apply IHn. intro Hc. apply H. apply le_n_S. assumption.
Qed.
Tactic Notation "verify" :=
apply verification_correct;
repeat split;
simpl; unfold assert_implies;
unfold bassn in *; unfold beval in *; unfold aeval in *;
unfold assn_sub; intros;
repeat rewrite update_eq;
repeat (rewrite update_neq; [| (intro X; inversion X)]);
simpl in *;
repeat match goal with [H : _ /\ _ |- _] => destruct H end;
repeat rewrite not_true_iff_false in *;
repeat rewrite not_false_iff_true in *;
repeat rewrite negb_true_iff in *;
repeat rewrite negb_false_iff in *;
repeat rewrite beq_nat_true_iff in *;
repeat rewrite beq_nat_false_iff in *;
repeat rewrite ble_nat_true_iff in *;
repeat rewrite ble_nat_false_iff in *;
try subst;
repeat
match goal with
[st : state |- _] =>
match goal with
[H : st _ = _ |- _] => rewrite -> H in *; clear H
| [H : _ = st _ |- _] => rewrite <- H in *; clear H
end
end;
try eauto; try omega.
(** What's left after [verify] does its thing is "just the interesting
parts" of checking that the decorations are correct. For very
simple examples [verify] immediately solves the goal (provided
that the annotations are correct). *)
Theorem dec_while_correct :
dec_correct dec_while.
Proof. verify. Qed.
(** Another example (formalizing a decorated program we've seen
before): *)
Example subtract_slowly_dec (m:nat) (p:nat) : dcom := (
{{ fun st => st X = m /\ st Z = p }} ->>
{{ fun st => st Z - st X = p - m }}
WHILE BNot (BEq (AId X) (ANum 0))
DO {{ fun st => st Z - st X = p - m /\ st X <> 0 }} ->>
{{ fun st => (st Z - 1) - (st X - 1) = p - m }}
Z ::= AMinus (AId Z) (ANum 1)
{{ fun st => st Z - (st X - 1) = p - m }} ;;
X ::= AMinus (AId X) (ANum 1)
{{ fun st => st Z - st X = p - m }}
END
{{ fun st => st Z - st X = p - m /\ st X = 0 }} ->>
{{ fun st => st Z = p - m }}
) % dcom.
Theorem subtract_slowly_dec_correct : forall m p,
dec_correct (subtract_slowly_dec m p).
Proof. intros m p. verify. (* this grinds for a bit! *) Qed.
(** **** Exercise: 3 stars, advanced (slow_assignment_dec) *)
(** In the [slow_assignment] exercise above, we saw a roundabout way
of assigning a number currently stored in [X] to the variable [Y]:
start [Y] at [0], then decrement [X] until it hits [0],
incrementing [Y] at each step.
Write a _formal_ version of this decorated program and prove it
correct. *)
Example slow_assignment_dec (m:nat) : dcom := (
{{ fun st => st X = m }} ->>
{{ fun st => st X = m /\ st Y = st Y }}
Y ::= ANum 0
{{ fun st => st X = m /\ st Y = 0 }} ;;
->>
{{ fun st => st X + st Y = m }}
WHILE BNot (BEq (AId X) (ANum 0)) DO
{{ fun st => st X + st Y = m /\ st X <> 0 }} ->>
{{ fun st => (st X - 1) + (st Y + 1) = m }}
X ::= AMinus (AId X) (ANum 1)
{{ fun st => st X + (st Y + 1) = m }} ;;
Y ::= APlus (AId Y) (ANum 1)
{{ fun st => st X + st Y = m }}
END
{{ fun st => st X + st Y = m /\ ~(st X <> 0) }} ->>
{{ fun st => st Y = m }}
) % dcom.
Theorem slow_assignment_dec_correct : forall m,
dec_correct (slow_assignment_dec m).
Proof. intro m. verify. Qed.
(** [] *)
(** **** Exercise: 4 stars, advanced (factorial_dec) *)
(** Remember the factorial function we worked with before: *)
Fixpoint real_fact (n:nat) : nat :=
match n with
| O => 1
| S n' => n * (real_fact n')
end.
Lemma real_fact_succ : forall n,
real_fact (n+1) = (n+1) * real_fact n.
Proof.
intros n. replace (n+1) with (S n) by omega. reflexivity.
Qed.
(** Following the pattern of [subtract_slowly_dec], write a decorated
program that implements the factorial function and prove it
correct. *)
Example factorial_dec (n:nat) : dcom := (
{{ fun _ => True }}
X ::= ANum 1
{{ fun st => st X = 1 }} ;;
Y ::= ANum 1
{{ fun st => st X = 1 /\ st Y = 1 }} ;;
->>
{{ fun st => st Y = real_fact (st X) }}
WHILE BNot (BEq (AId X) (ANum n)) DO
{{ fun st => st Y = real_fact (st X) /\ st X <> n }}
->>
{{ fun st => (st X + 1) * st Y = real_fact ((st X) + 1) }}
X ::= APlus (AId X) (ANum 1)
{{ fun st => st X * st Y = real_fact (st X) }} ;;
Y ::= AMult (AId X) (AId Y)
{{ fun st => st Y = real_fact (st X) }}
END
{{ fun st => st Y = real_fact (st X) /\ ~ (st X <> n) }} ->>
{{ fun st => st Y = real_fact n }}
) % dcom.
Theorem factorial_dec_correct : forall n,
dec_correct (factorial_dec n).
Proof.
intro n. verify. symmetry. apply real_fact_succ.
assert ({st X = n} + {st X <> n}) by (apply eq_nat_dec).
inversion H; clear H. auto.
apply H0 in H1. inversion H1.
Qed.
(* FILL IN HERE *)
(** [] *)
(* $Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
|
/*
* blocksyn1.v
* This tests synthesis where statements in a block override previous
* statements in a block and also uses other previous statements in the
* block. Note in this example that the flag assignment is completely
* overruled by the conditional that is directly after it.
*/
module main;
reg [1:0] out;
reg flag;
reg [1:0] sel;
(* ivl_synthesis_on, ivl_combinational *)
always @*
begin
case (sel)
2'b00: out = 2'b11;
2'b01: out = 2'b10;
2'b10: out = 2'b01;
2'b11: out = 2'b00;
endcase // case(sel)
// This flag is completely overridden by the contintional, so
// the synthesizer should drop it.
flag = 1'b0;
if (out == 2'b00)
flag = 1'b1;
else
flag = 1'b0;
end
reg [2:0] idx;
reg test;
(* ivl_synthesis_off *)
initial begin
for (idx = 0 ; idx < 7 ; idx = idx + 1) begin
sel = idx[1:0];
#1 if (out !== ~sel) begin
$display("FAILED -- sel=%b, out=%b, flag=%b", sel, out, flag);
$finish;
end
test = (out == 2'b00)? 1'b1 : 1'b0;
if (test !== flag) begin
$display("FAILED -- test=%b, sel=%b, out=%b, flag=%b",
test, sel, out, flag);
$finish;
end
end // for (idx = 0 ; idx < 7 ; idx = idx + 1)
$display("PASSED");
end // initial begin
endmodule // main
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_fpga_core;
reg [7:0] current_test = 0;
// clocks
reg clk_250mhz_int = 0;
reg rst_250mhz_int = 0;
reg clk_250mhz = 0;
reg rst_250mhz = 0;
reg clk_10mhz = 0;
reg rst_10mhz = 0;
reg ext_clock_selected = 0;
// SoC interface
reg cntrl_cs = 0;
reg cntrl_sck = 0;
reg cntrl_mosi = 0;
wire cntrl_miso;
// Trigger
reg ext_trig = 0;
// Frequency counter
reg ext_prescale = 0;
// Front end relay control
wire ferc_dat;
wire ferc_clk;
wire ferc_lat;
// Analog mux
wire [2:0] mux_s;
// ADC
wire adc_sclk;
reg adc_sdo = 0;
wire adc_sdi;
wire adc_cs;
reg adc_eoc = 0;
wire adc_convst;
// digital output
wire [15:0] dout;
// Sync DAC
wire [7:0] sync_dac;
// Main DAC
wire dac_clk;
wire [15:0] dac_p1_d;
wire [15:0] dac_p2_d;
reg dac_sdo = 0;
wire dac_sdio;
wire dac_sclk;
wire dac_csb;
wire dac_reset;
// ram 1 MCB (U8)
reg ram1_calib_done = 0;
wire ram1_p0_cmd_clk;
wire ram1_p0_cmd_en;
wire [2:0] ram1_p0_cmd_instr;
wire [5:0] ram1_p0_cmd_bl;
wire [31:0] ram1_p0_cmd_byte_addr;
reg ram1_p0_cmd_empty = 0;
reg ram1_p0_cmd_full = 0;
wire ram1_p0_wr_clk;
wire ram1_p0_wr_en;
wire [3:0] ram1_p0_wr_mask;
wire [31:0] ram1_p0_wr_data;
reg ram1_p0_wr_empty = 0;
reg ram1_p0_wr_full = 0;
reg ram1_p0_wr_underrun = 0;
reg [6:0] ram1_p0_wr_count = 0;
reg ram1_p0_wr_error = 0;
wire ram1_p0_rd_clk;
wire ram1_p0_rd_en;
reg [31:0] ram1_p0_rd_data = 0;
reg ram1_p0_rd_empty = 0;
reg ram1_p0_rd_full = 0;
reg ram1_p0_rd_overflow = 0;
reg [6:0] ram1_p0_rd_count = 0;
reg ram1_p0_rd_error = 0;
wire ram1_p1_cmd_clk;
wire ram1_p1_cmd_en;
wire [2:0] ram1_p1_cmd_instr;
wire [5:0] ram1_p1_cmd_bl;
wire [31:0] ram1_p1_cmd_byte_addr;
reg ram1_p1_cmd_empty = 0;
reg ram1_p1_cmd_full = 0;
wire ram1_p1_wr_clk;
wire ram1_p1_wr_en;
wire [3:0] ram1_p1_wr_mask;
wire [31:0] ram1_p1_wr_data;
reg ram1_p1_wr_empty = 0;
reg ram1_p1_wr_full = 0;
reg ram1_p1_wr_underrun = 0;
reg [6:0] ram1_p1_wr_count = 0;
reg ram1_p1_wr_error = 0;
wire ram1_p1_rd_clk;
wire ram1_p1_rd_en;
reg [31:0] ram1_p1_rd_data = 0;
reg ram1_p1_rd_empty = 0;
reg ram1_p1_rd_full = 0;
reg ram1_p1_rd_overflow = 0;
reg [6:0] ram1_p1_rd_count = 0;
reg ram1_p1_rd_error = 0;
wire ram1_p2_cmd_clk;
wire ram1_p2_cmd_en;
wire [2:0] ram1_p2_cmd_instr;
wire [5:0] ram1_p2_cmd_bl;
wire [31:0] ram1_p2_cmd_byte_addr;
reg ram1_p2_cmd_empty = 0;
reg ram1_p2_cmd_full = 0;
wire ram1_p2_rd_clk;
wire ram1_p2_rd_en;
reg [31:0] ram1_p2_rd_data = 0;
reg ram1_p2_rd_empty = 0;
reg ram1_p2_rd_full = 0;
reg ram1_p2_rd_overflow = 0;
reg [6:0] ram1_p2_rd_count = 0;
reg ram1_p2_rd_error = 0;
wire ram1_p3_cmd_clk;
wire ram1_p3_cmd_en;
wire [2:0] ram1_p3_cmd_instr;
wire [5:0] ram1_p3_cmd_bl;
wire [31:0] ram1_p3_cmd_byte_addr;
reg ram1_p3_cmd_empty = 0;
reg ram1_p3_cmd_full = 0;
wire ram1_p3_rd_clk;
wire ram1_p3_rd_en;
reg [31:0] ram1_p3_rd_data = 0;
reg ram1_p3_rd_empty = 0;
reg ram1_p3_rd_full = 0;
reg ram1_p3_rd_overflow = 0;
reg [6:0] ram1_p3_rd_count = 0;
reg ram1_p3_rd_error = 0;
wire ram1_p4_cmd_clk;
wire ram1_p4_cmd_en;
wire [2:0] ram1_p4_cmd_instr;
wire [5:0] ram1_p4_cmd_bl;
wire [31:0] ram1_p4_cmd_byte_addr;
reg ram1_p4_cmd_empty = 0;
reg ram1_p4_cmd_full = 0;
wire ram1_p4_rd_clk;
wire ram1_p4_rd_en;
reg [31:0] ram1_p4_rd_data = 0;
reg ram1_p4_rd_empty = 0;
reg ram1_p4_rd_full = 0;
reg ram1_p4_rd_overflow = 0;
reg [6:0] ram1_p4_rd_count = 0;
reg ram1_p4_rd_error = 0;
wire ram1_p5_cmd_clk;
wire ram1_p5_cmd_en;
wire [2:0] ram1_p5_cmd_instr;
wire [5:0] ram1_p5_cmd_bl;
wire [31:0] ram1_p5_cmd_byte_addr;
reg ram1_p5_cmd_empty = 0;
reg ram1_p5_cmd_full = 0;
wire ram1_p5_rd_clk;
wire ram1_p5_rd_en;
reg [31:0] ram1_p5_rd_data = 0;
reg ram1_p5_rd_empty = 0;
reg ram1_p5_rd_full = 0;
reg ram1_p5_rd_overflow = 0;
reg [6:0] ram1_p5_rd_count = 0;
reg ram1_p5_rd_error = 0;
// ram 2 MCB (U12)
reg ram2_calib_done = 0;
wire ram2_p0_cmd_clk;
wire ram2_p0_cmd_en;
wire [2:0] ram2_p0_cmd_instr;
wire [5:0] ram2_p0_cmd_bl;
wire [31:0] ram2_p0_cmd_byte_addr;
reg ram2_p0_cmd_empty = 0;
reg ram2_p0_cmd_full = 0;
wire ram2_p0_wr_clk;
wire ram2_p0_wr_en;
wire [3:0] ram2_p0_wr_mask;
wire [31:0] ram2_p0_wr_data;
reg ram2_p0_wr_empty = 0;
reg ram2_p0_wr_full = 0;
reg ram2_p0_wr_underrun = 0;
reg [6:0] ram2_p0_wr_count = 0;
reg ram2_p0_wr_error = 0;
wire ram2_p0_rd_clk;
wire ram2_p0_rd_en;
reg [31:0] ram2_p0_rd_data = 0;
reg ram2_p0_rd_empty = 0;
reg ram2_p0_rd_full = 0;
reg ram2_p0_rd_overflow = 0;
reg [6:0] ram2_p0_rd_count = 0;
reg ram2_p0_rd_error = 0;
wire ram2_p1_cmd_clk;
wire ram2_p1_cmd_en;
wire [2:0] ram2_p1_cmd_instr;
wire [5:0] ram2_p1_cmd_bl;
wire [31:0] ram2_p1_cmd_byte_addr;
reg ram2_p1_cmd_empty = 0;
reg ram2_p1_cmd_full = 0;
wire ram2_p1_wr_clk;
wire ram2_p1_wr_en;
wire [3:0] ram2_p1_wr_mask;
wire [31:0] ram2_p1_wr_data;
reg ram2_p1_wr_empty = 0;
reg ram2_p1_wr_full = 0;
reg ram2_p1_wr_underrun = 0;
reg [6:0] ram2_p1_wr_count = 0;
reg ram2_p1_wr_error = 0;
wire ram2_p1_rd_clk;
wire ram2_p1_rd_en;
reg [31:0] ram2_p1_rd_data = 0;
reg ram2_p1_rd_empty = 0;
reg ram2_p1_rd_full = 0;
reg ram2_p1_rd_overflow = 0;
reg [6:0] ram2_p1_rd_count = 0;
reg ram2_p1_rd_error = 0;
wire ram2_p2_cmd_clk;
wire ram2_p2_cmd_en;
wire [2:0] ram2_p2_cmd_instr;
wire [5:0] ram2_p2_cmd_bl;
wire [31:0] ram2_p2_cmd_byte_addr;
reg ram2_p2_cmd_empty = 0;
reg ram2_p2_cmd_full = 0;
wire ram2_p2_rd_clk;
wire ram2_p2_rd_en;
reg [31:0] ram2_p2_rd_data = 0;
reg ram2_p2_rd_empty = 0;
reg ram2_p2_rd_full = 0;
reg ram2_p2_rd_overflow = 0;
reg [6:0] ram2_p2_rd_count = 0;
reg ram2_p2_rd_error = 0;
wire ram2_p3_cmd_clk;
wire ram2_p3_cmd_en;
wire [2:0] ram2_p3_cmd_instr;
wire [5:0] ram2_p3_cmd_bl;
wire [31:0] ram2_p3_cmd_byte_addr;
reg ram2_p3_cmd_empty = 0;
reg ram2_p3_cmd_full = 0;
wire ram2_p3_rd_clk;
wire ram2_p3_rd_en;
reg [31:0] ram2_p3_rd_data = 0;
reg ram2_p3_rd_empty = 0;
reg ram2_p3_rd_full = 0;
reg ram2_p3_rd_overflow = 0;
reg [6:0] ram2_p3_rd_count = 0;
reg ram2_p3_rd_error = 0;
wire ram2_p4_cmd_clk;
wire ram2_p4_cmd_en;
wire [2:0] ram2_p4_cmd_instr;
wire [5:0] ram2_p4_cmd_bl;
wire [31:0] ram2_p4_cmd_byte_addr;
reg ram2_p4_cmd_empty = 0;
reg ram2_p4_cmd_full = 0;
wire ram2_p4_rd_clk;
wire ram2_p4_rd_en;
reg [31:0] ram2_p4_rd_data = 0;
reg ram2_p4_rd_empty = 0;
reg ram2_p4_rd_full = 0;
reg ram2_p4_rd_overflow = 0;
reg [6:0] ram2_p4_rd_count = 0;
reg ram2_p4_rd_error = 0;
wire ram2_p5_cmd_clk;
wire ram2_p5_cmd_en;
wire [2:0] ram2_p5_cmd_instr;
wire [5:0] ram2_p5_cmd_bl;
wire [31:0] ram2_p5_cmd_byte_addr;
reg ram2_p5_cmd_empty = 0;
reg ram2_p5_cmd_full = 0;
wire ram2_p5_rd_clk;
wire ram2_p5_rd_en;
reg [31:0] ram2_p5_rd_data = 0;
reg ram2_p5_rd_empty = 0;
reg ram2_p5_rd_full = 0;
reg ram2_p5_rd_overflow = 0;
reg [6:0] ram2_p5_rd_count = 0;
reg ram2_p5_rd_error = 0;
initial begin
// myhdl integration
$from_myhdl(current_test,
clk_250mhz_int,
rst_250mhz_int,
clk_250mhz,
rst_250mhz,
clk_10mhz,
rst_10mhz,
ext_clock_selected,
cntrl_cs,
cntrl_sck,
cntrl_mosi,
ext_trig,
ext_prescale,
adc_sdo,
adc_eoc,
dac_sdo,
ram1_calib_done,
ram1_p0_cmd_empty,
ram1_p0_cmd_full,
ram1_p0_wr_empty,
ram1_p0_wr_full,
ram1_p0_wr_underrun,
ram1_p0_wr_count,
ram1_p0_wr_error,
ram1_p0_rd_data,
ram1_p0_rd_empty,
ram1_p0_rd_full,
ram1_p0_rd_overflow,
ram1_p0_rd_count,
ram1_p0_rd_error,
ram1_p1_cmd_empty,
ram1_p1_cmd_full,
ram1_p1_wr_empty,
ram1_p1_wr_full,
ram1_p1_wr_underrun,
ram1_p1_wr_count,
ram1_p1_wr_error,
ram1_p1_rd_data,
ram1_p1_rd_empty,
ram1_p1_rd_full,
ram1_p1_rd_overflow,
ram1_p1_rd_count,
ram1_p1_rd_error,
ram1_p2_cmd_empty,
ram1_p2_cmd_full,
ram1_p2_rd_data,
ram1_p2_rd_empty,
ram1_p2_rd_full,
ram1_p2_rd_overflow,
ram1_p2_rd_count,
ram1_p2_rd_error,
ram1_p3_cmd_empty,
ram1_p3_cmd_full,
ram1_p3_rd_data,
ram1_p3_rd_empty,
ram1_p3_rd_full,
ram1_p3_rd_overflow,
ram1_p3_rd_count,
ram1_p3_rd_error,
ram1_p4_cmd_empty,
ram1_p4_cmd_full,
ram1_p4_rd_data,
ram1_p4_rd_empty,
ram1_p4_rd_full,
ram1_p4_rd_overflow,
ram1_p4_rd_count,
ram1_p4_rd_error,
ram1_p5_cmd_empty,
ram1_p5_cmd_full,
ram1_p5_rd_data,
ram1_p5_rd_empty,
ram1_p5_rd_full,
ram1_p5_rd_overflow,
ram1_p5_rd_count,
ram1_p5_rd_error,
ram2_calib_done,
ram2_p0_cmd_empty,
ram2_p0_cmd_full,
ram2_p0_wr_empty,
ram2_p0_wr_full,
ram2_p0_wr_underrun,
ram2_p0_wr_count,
ram2_p0_wr_error,
ram2_p0_rd_data,
ram2_p0_rd_empty,
ram2_p0_rd_full,
ram2_p0_rd_overflow,
ram2_p0_rd_count,
ram2_p0_rd_error,
ram2_p1_cmd_empty,
ram2_p1_cmd_full,
ram2_p1_wr_empty,
ram2_p1_wr_full,
ram2_p1_wr_underrun,
ram2_p1_wr_count,
ram2_p1_wr_error,
ram2_p1_rd_data,
ram2_p1_rd_empty,
ram2_p1_rd_full,
ram2_p1_rd_overflow,
ram2_p1_rd_count,
ram2_p1_rd_error,
ram2_p2_cmd_empty,
ram2_p2_cmd_full,
ram2_p2_rd_data,
ram2_p2_rd_empty,
ram2_p2_rd_full,
ram2_p2_rd_overflow,
ram2_p2_rd_count,
ram2_p2_rd_error,
ram2_p3_cmd_empty,
ram2_p3_cmd_full,
ram2_p3_rd_data,
ram2_p3_rd_empty,
ram2_p3_rd_full,
ram2_p3_rd_overflow,
ram2_p3_rd_count,
ram2_p3_rd_error,
ram2_p4_cmd_empty,
ram2_p4_cmd_full,
ram2_p4_rd_data,
ram2_p4_rd_empty,
ram2_p4_rd_full,
ram2_p4_rd_overflow,
ram2_p4_rd_count,
ram2_p4_rd_error,
ram2_p5_cmd_empty,
ram2_p5_cmd_full,
ram2_p5_rd_data,
ram2_p5_rd_empty,
ram2_p5_rd_full,
ram2_p5_rd_overflow,
ram2_p5_rd_count,
ram2_p5_rd_error);
$to_myhdl(cntrl_miso,
ferc_dat,
ferc_clk,
ferc_lat,
mux_s,
adc_sclk,
adc_sdi,
adc_cs,
adc_convst,
dout,
sync_dac,
dac_clk,
dac_p1_d,
dac_p2_d,
dac_sdio,
dac_sclk,
dac_csb,
dac_reset,
ram1_p0_cmd_clk,
ram1_p0_cmd_en,
ram1_p0_cmd_instr,
ram1_p0_cmd_bl,
ram1_p0_cmd_byte_addr,
ram1_p0_wr_clk,
ram1_p0_wr_en,
ram1_p0_wr_mask,
ram1_p0_wr_data,
ram1_p0_rd_clk,
ram1_p0_rd_en,
ram1_p1_cmd_clk,
ram1_p1_cmd_en,
ram1_p1_cmd_instr,
ram1_p1_cmd_bl,
ram1_p1_cmd_byte_addr,
ram1_p1_wr_clk,
ram1_p1_wr_en,
ram1_p1_wr_mask,
ram1_p1_wr_data,
ram1_p1_rd_clk,
ram1_p1_rd_en,
ram1_p2_cmd_clk,
ram1_p2_cmd_en,
ram1_p2_cmd_instr,
ram1_p2_cmd_bl,
ram1_p2_cmd_byte_addr,
ram1_p2_rd_clk,
ram1_p2_rd_en,
ram1_p3_cmd_clk,
ram1_p3_cmd_en,
ram1_p3_cmd_instr,
ram1_p3_cmd_bl,
ram1_p3_cmd_byte_addr,
ram1_p3_rd_clk,
ram1_p3_rd_en,
ram1_p4_cmd_clk,
ram1_p4_cmd_en,
ram1_p4_cmd_instr,
ram1_p4_cmd_bl,
ram1_p4_cmd_byte_addr,
ram1_p4_rd_clk,
ram1_p4_rd_en,
ram1_p5_cmd_clk,
ram1_p5_cmd_en,
ram1_p5_cmd_instr,
ram1_p5_cmd_bl,
ram1_p5_cmd_byte_addr,
ram1_p5_rd_clk,
ram1_p5_rd_en,
ram2_p0_cmd_clk,
ram2_p0_cmd_en,
ram2_p0_cmd_instr,
ram2_p0_cmd_bl,
ram2_p0_cmd_byte_addr,
ram2_p0_wr_clk,
ram2_p0_wr_en,
ram2_p0_wr_mask,
ram2_p0_wr_data,
ram2_p0_rd_clk,
ram2_p0_rd_en,
ram2_p1_cmd_clk,
ram2_p1_cmd_en,
ram2_p1_cmd_instr,
ram2_p1_cmd_bl,
ram2_p1_cmd_byte_addr,
ram2_p1_wr_clk,
ram2_p1_wr_en,
ram2_p1_wr_mask,
ram2_p1_wr_data,
ram2_p1_rd_clk,
ram2_p1_rd_en,
ram2_p2_cmd_clk,
ram2_p2_cmd_en,
ram2_p2_cmd_instr,
ram2_p2_cmd_bl,
ram2_p2_cmd_byte_addr,
ram2_p2_rd_clk,
ram2_p2_rd_en,
ram2_p3_cmd_clk,
ram2_p3_cmd_en,
ram2_p3_cmd_instr,
ram2_p3_cmd_bl,
ram2_p3_cmd_byte_addr,
ram2_p3_rd_clk,
ram2_p3_rd_en,
ram2_p4_cmd_clk,
ram2_p4_cmd_en,
ram2_p4_cmd_instr,
ram2_p4_cmd_bl,
ram2_p4_cmd_byte_addr,
ram2_p4_rd_clk,
ram2_p4_rd_en,
ram2_p5_cmd_clk,
ram2_p5_cmd_en,
ram2_p5_cmd_instr,
ram2_p5_cmd_bl,
ram2_p5_cmd_byte_addr,
ram2_p5_rd_clk,
ram2_p5_rd_en);
// dump file
$dumpfile("test_fpga_core.lxt");
$dumpvars(0, test_fpga_core);
end
fpga_core
UUT (
// clocks
.clk_250mhz_int(clk_250mhz_int),
.rst_250mhz_int(rst_250mhz_int),
.clk_250mhz(clk_250mhz),
.rst_250mhz(rst_250mhz),
.clk_10mhz(clk_10mhz),
.rst_10mhz(rst_10mhz),
.ext_clock_selected(ext_clock_selected),
// SoC interface
.cntrl_cs(cntrl_cs),
.cntrl_sck(cntrl_sck),
.cntrl_mosi(cntrl_mosi),
.cntrl_miso(cntrl_miso),
// Trigger
.ext_trig(ext_trig),
// Frequency counter
.ext_prescale(ext_prescale),
// Front end relay control
.ferc_dat(ferc_dat),
.ferc_clk(ferc_clk),
.ferc_lat(ferc_lat),
// Analog mux
.mux_s(mux_s),
// ADC
.adc_sclk(adc_sclk),
.adc_sdo(adc_sdo),
.adc_sdi(adc_sdi),
.adc_cs(adc_cs),
.adc_eoc(adc_eoc),
.adc_convst(adc_convst),
// digital output
.dout(dout),
// Sync DAC
.sync_dac(sync_dac),
// Main DAC
.dac_clk(dac_clk),
.dac_p1_d(dac_p1_d),
.dac_p2_d(dac_p2_d),
.dac_sdo(dac_sdo),
.dac_sdio(dac_sdio),
.dac_sclk(dac_sclk),
.dac_csb(dac_csb),
.dac_reset(dac_reset),
// ram 1 MCB (U8)
.ram1_calib_done(ram1_calib_done),
.ram1_p0_cmd_clk(ram1_p0_cmd_clk),
.ram1_p0_cmd_en(ram1_p0_cmd_en),
.ram1_p0_cmd_instr(ram1_p0_cmd_instr),
.ram1_p0_cmd_bl(ram1_p0_cmd_bl),
.ram1_p0_cmd_byte_addr(ram1_p0_cmd_byte_addr),
.ram1_p0_cmd_empty(ram1_p0_cmd_empty),
.ram1_p0_cmd_full(ram1_p0_cmd_full),
.ram1_p0_wr_clk(ram1_p0_wr_clk),
.ram1_p0_wr_en(ram1_p0_wr_en),
.ram1_p0_wr_mask(ram1_p0_wr_mask),
.ram1_p0_wr_data(ram1_p0_wr_data),
.ram1_p0_wr_empty(ram1_p0_wr_empty),
.ram1_p0_wr_full(ram1_p0_wr_full),
.ram1_p0_wr_underrun(ram1_p0_wr_underrun),
.ram1_p0_wr_count(ram1_p0_wr_count),
.ram1_p0_wr_error(ram1_p0_wr_error),
.ram1_p0_rd_clk(ram1_p0_rd_clk),
.ram1_p0_rd_en(ram1_p0_rd_en),
.ram1_p0_rd_data(ram1_p0_rd_data),
.ram1_p0_rd_empty(ram1_p0_rd_empty),
.ram1_p0_rd_full(ram1_p0_rd_full),
.ram1_p0_rd_overflow(ram1_p0_rd_overflow),
.ram1_p0_rd_count(ram1_p0_rd_count),
.ram1_p0_rd_error(ram1_p0_rd_error),
.ram1_p1_cmd_clk(ram1_p1_cmd_clk),
.ram1_p1_cmd_en(ram1_p1_cmd_en),
.ram1_p1_cmd_instr(ram1_p1_cmd_instr),
.ram1_p1_cmd_bl(ram1_p1_cmd_bl),
.ram1_p1_cmd_byte_addr(ram1_p1_cmd_byte_addr),
.ram1_p1_cmd_empty(ram1_p1_cmd_empty),
.ram1_p1_cmd_full(ram1_p1_cmd_full),
.ram1_p1_wr_clk(ram1_p1_wr_clk),
.ram1_p1_wr_en(ram1_p1_wr_en),
.ram1_p1_wr_mask(ram1_p1_wr_mask),
.ram1_p1_wr_data(ram1_p1_wr_data),
.ram1_p1_wr_empty(ram1_p1_wr_empty),
.ram1_p1_wr_full(ram1_p1_wr_full),
.ram1_p1_wr_underrun(ram1_p1_wr_underrun),
.ram1_p1_wr_count(ram1_p1_wr_count),
.ram1_p1_wr_error(ram1_p1_wr_error),
.ram1_p1_rd_clk(ram1_p1_rd_clk),
.ram1_p1_rd_en(ram1_p1_rd_en),
.ram1_p1_rd_data(ram1_p1_rd_data),
.ram1_p1_rd_empty(ram1_p1_rd_empty),
.ram1_p1_rd_full(ram1_p1_rd_full),
.ram1_p1_rd_overflow(ram1_p1_rd_overflow),
.ram1_p1_rd_count(ram1_p1_rd_count),
.ram1_p1_rd_error(ram1_p1_rd_error),
.ram1_p2_cmd_clk(ram1_p2_cmd_clk),
.ram1_p2_cmd_en(ram1_p2_cmd_en),
.ram1_p2_cmd_instr(ram1_p2_cmd_instr),
.ram1_p2_cmd_bl(ram1_p2_cmd_bl),
.ram1_p2_cmd_byte_addr(ram1_p2_cmd_byte_addr),
.ram1_p2_cmd_empty(ram1_p2_cmd_empty),
.ram1_p2_cmd_full(ram1_p2_cmd_full),
.ram1_p2_rd_clk(ram1_p2_rd_clk),
.ram1_p2_rd_en(ram1_p2_rd_en),
.ram1_p2_rd_data(ram1_p2_rd_data),
.ram1_p2_rd_empty(ram1_p2_rd_empty),
.ram1_p2_rd_full(ram1_p2_rd_full),
.ram1_p2_rd_overflow(ram1_p2_rd_overflow),
.ram1_p2_rd_count(ram1_p2_rd_count),
.ram1_p2_rd_error(ram1_p2_rd_error),
.ram1_p3_cmd_clk(ram1_p3_cmd_clk),
.ram1_p3_cmd_en(ram1_p3_cmd_en),
.ram1_p3_cmd_instr(ram1_p3_cmd_instr),
.ram1_p3_cmd_bl(ram1_p3_cmd_bl),
.ram1_p3_cmd_byte_addr(ram1_p3_cmd_byte_addr),
.ram1_p3_cmd_empty(ram1_p3_cmd_empty),
.ram1_p3_cmd_full(ram1_p3_cmd_full),
.ram1_p3_rd_clk(ram1_p3_rd_clk),
.ram1_p3_rd_en(ram1_p3_rd_en),
.ram1_p3_rd_data(ram1_p3_rd_data),
.ram1_p3_rd_empty(ram1_p3_rd_empty),
.ram1_p3_rd_full(ram1_p3_rd_full),
.ram1_p3_rd_overflow(ram1_p3_rd_overflow),
.ram1_p3_rd_count(ram1_p3_rd_count),
.ram1_p3_rd_error(ram1_p3_rd_error),
.ram1_p4_cmd_clk(ram1_p4_cmd_clk),
.ram1_p4_cmd_en(ram1_p4_cmd_en),
.ram1_p4_cmd_instr(ram1_p4_cmd_instr),
.ram1_p4_cmd_bl(ram1_p4_cmd_bl),
.ram1_p4_cmd_byte_addr(ram1_p4_cmd_byte_addr),
.ram1_p4_cmd_empty(ram1_p4_cmd_empty),
.ram1_p4_cmd_full(ram1_p4_cmd_full),
.ram1_p4_rd_clk(ram1_p4_rd_clk),
.ram1_p4_rd_en(ram1_p4_rd_en),
.ram1_p4_rd_data(ram1_p4_rd_data),
.ram1_p4_rd_empty(ram1_p4_rd_empty),
.ram1_p4_rd_full(ram1_p4_rd_full),
.ram1_p4_rd_overflow(ram1_p4_rd_overflow),
.ram1_p4_rd_count(ram1_p4_rd_count),
.ram1_p4_rd_error(ram1_p4_rd_error),
.ram1_p5_cmd_clk(ram1_p5_cmd_clk),
.ram1_p5_cmd_en(ram1_p5_cmd_en),
.ram1_p5_cmd_instr(ram1_p5_cmd_instr),
.ram1_p5_cmd_bl(ram1_p5_cmd_bl),
.ram1_p5_cmd_byte_addr(ram1_p5_cmd_byte_addr),
.ram1_p5_cmd_empty(ram1_p5_cmd_empty),
.ram1_p5_cmd_full(ram1_p5_cmd_full),
.ram1_p5_rd_clk(ram1_p5_rd_clk),
.ram1_p5_rd_en(ram1_p5_rd_en),
.ram1_p5_rd_data(ram1_p5_rd_data),
.ram1_p5_rd_empty(ram1_p5_rd_empty),
.ram1_p5_rd_full(ram1_p5_rd_full),
.ram1_p5_rd_overflow(ram1_p5_rd_overflow),
.ram1_p5_rd_count(ram1_p5_rd_count),
.ram1_p5_rd_error(ram1_p5_rd_error),
// ram 2 MCB (U12)
.ram2_calib_done(ram2_calib_done),
.ram2_p0_cmd_clk(ram2_p0_cmd_clk),
.ram2_p0_cmd_en(ram2_p0_cmd_en),
.ram2_p0_cmd_instr(ram2_p0_cmd_instr),
.ram2_p0_cmd_bl(ram2_p0_cmd_bl),
.ram2_p0_cmd_byte_addr(ram2_p0_cmd_byte_addr),
.ram2_p0_cmd_empty(ram2_p0_cmd_empty),
.ram2_p0_cmd_full(ram2_p0_cmd_full),
.ram2_p0_wr_clk(ram2_p0_wr_clk),
.ram2_p0_wr_en(ram2_p0_wr_en),
.ram2_p0_wr_mask(ram2_p0_wr_mask),
.ram2_p0_wr_data(ram2_p0_wr_data),
.ram2_p0_wr_empty(ram2_p0_wr_empty),
.ram2_p0_wr_full(ram2_p0_wr_full),
.ram2_p0_wr_underrun(ram2_p0_wr_underrun),
.ram2_p0_wr_count(ram2_p0_wr_count),
.ram2_p0_wr_error(ram2_p0_wr_error),
.ram2_p0_rd_clk(ram2_p0_rd_clk),
.ram2_p0_rd_en(ram2_p0_rd_en),
.ram2_p0_rd_data(ram2_p0_rd_data),
.ram2_p0_rd_empty(ram2_p0_rd_empty),
.ram2_p0_rd_full(ram2_p0_rd_full),
.ram2_p0_rd_overflow(ram2_p0_rd_overflow),
.ram2_p0_rd_count(ram2_p0_rd_count),
.ram2_p0_rd_error(ram2_p0_rd_error),
.ram2_p1_cmd_clk(ram2_p1_cmd_clk),
.ram2_p1_cmd_en(ram2_p1_cmd_en),
.ram2_p1_cmd_instr(ram2_p1_cmd_instr),
.ram2_p1_cmd_bl(ram2_p1_cmd_bl),
.ram2_p1_cmd_byte_addr(ram2_p1_cmd_byte_addr),
.ram2_p1_cmd_empty(ram2_p1_cmd_empty),
.ram2_p1_cmd_full(ram2_p1_cmd_full),
.ram2_p1_wr_clk(ram2_p1_wr_clk),
.ram2_p1_wr_en(ram2_p1_wr_en),
.ram2_p1_wr_mask(ram2_p1_wr_mask),
.ram2_p1_wr_data(ram2_p1_wr_data),
.ram2_p1_wr_empty(ram2_p1_wr_empty),
.ram2_p1_wr_full(ram2_p1_wr_full),
.ram2_p1_wr_underrun(ram2_p1_wr_underrun),
.ram2_p1_wr_count(ram2_p1_wr_count),
.ram2_p1_wr_error(ram2_p1_wr_error),
.ram2_p1_rd_clk(ram2_p1_rd_clk),
.ram2_p1_rd_en(ram2_p1_rd_en),
.ram2_p1_rd_data(ram2_p1_rd_data),
.ram2_p1_rd_empty(ram2_p1_rd_empty),
.ram2_p1_rd_full(ram2_p1_rd_full),
.ram2_p1_rd_overflow(ram2_p1_rd_overflow),
.ram2_p1_rd_count(ram2_p1_rd_count),
.ram2_p1_rd_error(ram2_p1_rd_error),
.ram2_p2_cmd_clk(ram2_p2_cmd_clk),
.ram2_p2_cmd_en(ram2_p2_cmd_en),
.ram2_p2_cmd_instr(ram2_p2_cmd_instr),
.ram2_p2_cmd_bl(ram2_p2_cmd_bl),
.ram2_p2_cmd_byte_addr(ram2_p2_cmd_byte_addr),
.ram2_p2_cmd_empty(ram2_p2_cmd_empty),
.ram2_p2_cmd_full(ram2_p2_cmd_full),
.ram2_p2_rd_clk(ram2_p2_rd_clk),
.ram2_p2_rd_en(ram2_p2_rd_en),
.ram2_p2_rd_data(ram2_p2_rd_data),
.ram2_p2_rd_empty(ram2_p2_rd_empty),
.ram2_p2_rd_full(ram2_p2_rd_full),
.ram2_p2_rd_overflow(ram2_p2_rd_overflow),
.ram2_p2_rd_count(ram2_p2_rd_count),
.ram2_p2_rd_error(ram2_p2_rd_error),
.ram2_p3_cmd_clk(ram2_p3_cmd_clk),
.ram2_p3_cmd_en(ram2_p3_cmd_en),
.ram2_p3_cmd_instr(ram2_p3_cmd_instr),
.ram2_p3_cmd_bl(ram2_p3_cmd_bl),
.ram2_p3_cmd_byte_addr(ram2_p3_cmd_byte_addr),
.ram2_p3_cmd_empty(ram2_p3_cmd_empty),
.ram2_p3_cmd_full(ram2_p3_cmd_full),
.ram2_p3_rd_clk(ram2_p3_rd_clk),
.ram2_p3_rd_en(ram2_p3_rd_en),
.ram2_p3_rd_data(ram2_p3_rd_data),
.ram2_p3_rd_empty(ram2_p3_rd_empty),
.ram2_p3_rd_full(ram2_p3_rd_full),
.ram2_p3_rd_overflow(ram2_p3_rd_overflow),
.ram2_p3_rd_count(ram2_p3_rd_count),
.ram2_p3_rd_error(ram2_p3_rd_error),
.ram2_p4_cmd_clk(ram2_p4_cmd_clk),
.ram2_p4_cmd_en(ram2_p4_cmd_en),
.ram2_p4_cmd_instr(ram2_p4_cmd_instr),
.ram2_p4_cmd_bl(ram2_p4_cmd_bl),
.ram2_p4_cmd_byte_addr(ram2_p4_cmd_byte_addr),
.ram2_p4_cmd_empty(ram2_p4_cmd_empty),
.ram2_p4_cmd_full(ram2_p4_cmd_full),
.ram2_p4_rd_clk(ram2_p4_rd_clk),
.ram2_p4_rd_en(ram2_p4_rd_en),
.ram2_p4_rd_data(ram2_p4_rd_data),
.ram2_p4_rd_empty(ram2_p4_rd_empty),
.ram2_p4_rd_full(ram2_p4_rd_full),
.ram2_p4_rd_overflow(ram2_p4_rd_overflow),
.ram2_p4_rd_count(ram2_p4_rd_count),
.ram2_p4_rd_error(ram2_p4_rd_error),
.ram2_p5_cmd_clk(ram2_p5_cmd_clk),
.ram2_p5_cmd_en(ram2_p5_cmd_en),
.ram2_p5_cmd_instr(ram2_p5_cmd_instr),
.ram2_p5_cmd_bl(ram2_p5_cmd_bl),
.ram2_p5_cmd_byte_addr(ram2_p5_cmd_byte_addr),
.ram2_p5_cmd_empty(ram2_p5_cmd_empty),
.ram2_p5_cmd_full(ram2_p5_cmd_full),
.ram2_p5_rd_clk(ram2_p5_rd_clk),
.ram2_p5_rd_en(ram2_p5_rd_en),
.ram2_p5_rd_data(ram2_p5_rd_data),
.ram2_p5_rd_empty(ram2_p5_rd_empty),
.ram2_p5_rd_full(ram2_p5_rd_full),
.ram2_p5_rd_overflow(ram2_p5_rd_overflow),
.ram2_p5_rd_count(ram2_p5_rd_count),
.ram2_p5_rd_error(ram2_p5_rd_error)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module sky130_fd_io__top_power_hvc_wpadv2 ( P_PAD, AMUXBUS_A, AMUXBUS_B
);
inout P_PAD;
inout AMUXBUS_A;
inout AMUXBUS_B;
supply1 ogc_hvc;
supply1 drn_hvc;
supply0 src_bdy_hvc;
supply1 p_core;
supply1 vddio;
supply1 vddio_q;
supply1 vdda;
supply1 vccd;
supply1 vswitch;
supply1 vcchib;
supply1 vpb;
supply1 vpbhib;
supply0 vssd;
supply0 vssio;
supply0 vssio_q;
supply0 vssa;
tran p1 (p_core, P_PAD);
endmodule
|
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