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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module cf_dac_1c_2p (
// dac interface
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_data_out_a_p,
dac_data_out_a_n,
dac_data_out_b_p,
dac_data_out_b_n,
// vdma interface (for ddr-dds)
vdma_clk,
vdma_valid,
vdma_data,
vdma_ready,
// processor interface
up_rstn,
up_clk,
up_sel,
up_rwn,
up_addr,
up_wdata,
up_rdata,
up_ack,
up_status,
// debug signals (vdma) for chipscope
vdma_dbg_data,
vdma_dbg_trigger,
// debug signals (dac) for chipscope
dac_div3_clk,
dac_dbg_data,
dac_dbg_trigger,
// delay clock (usually 200MHz)
delay_clk);
// dac interface
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output [13:0] dac_data_out_a_p;
output [13:0] dac_data_out_a_n;
output [13:0] dac_data_out_b_p;
output [13:0] dac_data_out_b_n;
// vdma interface (for ddr-dds)
input vdma_clk;
input vdma_valid;
input [63:0] vdma_data;
output vdma_ready;
// processor interface
input up_rstn;
input up_clk;
input up_sel;
input up_rwn;
input [ 4:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
output [ 7:0] up_status;
// debug signals (vdma) for chipscope
output [198:0] vdma_dbg_data;
output [ 7:0] vdma_dbg_trigger;
// debug signals (dac) for chipscope
output dac_div3_clk;
output [292:0] dac_dbg_data;
output [ 7:0] dac_dbg_trigger;
// delay clock (usually 200MHz)
input delay_clk;
reg up_dds_sel = 'd0;
reg up_intp_enable = 'd0;
reg up_dds_enable = 'd0;
reg [15:0] up_dds_incr = 'd0;
reg [15:0] up_intp_scale_b = 'd0;
reg [15:0] up_intp_scale_a = 'd0;
reg [ 7:0] up_status = 'd0;
reg up_vdma_ovf_m1 = 'd0;
reg up_vdma_ovf_m2 = 'd0;
reg up_vdma_ovf = 'd0;
reg up_vdma_unf_m1 = 'd0;
reg up_vdma_unf_m2 = 'd0;
reg up_vdma_unf = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_sel_d = 'd0;
reg up_sel_2d = 'd0;
reg up_ack = 'd0;
wire up_wr_s;
wire up_ack_s;
wire vdma_ovf_s;
wire vdma_unf_s;
wire [13:0] dds_data_00_s;
wire [13:0] dds_data_01_s;
wire [13:0] dds_data_02_s;
wire [13:0] dds_data_03_s;
wire [13:0] dds_data_04_s;
wire [13:0] dds_data_05_s;
wire [13:0] dds_data_06_s;
wire [13:0] dds_data_07_s;
wire [13:0] dds_data_08_s;
wire [13:0] dds_data_09_s;
wire [13:0] dds_data_10_s;
wire [13:0] dds_data_11_s;
// processor write interface (see regmap.txt file for details of address definitions)
assign up_wr_s = up_sel & ~up_rwn;
assign up_ack_s = up_sel_d & ~up_sel_2d;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_dds_sel <= 'd0;
up_intp_enable <= 'd0;
up_dds_enable <= 'd0;
up_dds_incr <= 'd0;
up_intp_scale_b <= 'd0;
up_intp_scale_a <= 'd0;
up_status <= 'd0;
up_vdma_ovf_m1 <= 'd0;
up_vdma_ovf_m2 <= 'd0;
up_vdma_ovf <= 'd0;
up_vdma_unf_m1 <= 'd0;
up_vdma_unf_m2 <= 'd0;
up_vdma_unf <= 'd0;
end else begin
if ((up_addr == 5'h01) && (up_wr_s == 1'b1)) begin
up_dds_sel <= up_wdata[18];
up_intp_enable <= up_wdata[17];
up_dds_enable <= up_wdata[16];
up_dds_incr <= up_wdata[15:0];
end
if ((up_addr == 5'h06) && (up_wr_s == 1'b1)) begin
up_intp_scale_b <= up_wdata[31:16];
up_intp_scale_a <= up_wdata[15:0];
end
up_status <= {5'd0, up_dds_sel, up_intp_enable, up_dds_enable};
up_vdma_ovf_m1 <= vdma_ovf_s;
up_vdma_ovf_m2 <= up_vdma_ovf_m1;
if (up_vdma_ovf_m2 == 1'b1) begin
up_vdma_ovf <= 1'b1;
end else if ((up_addr == 5'h09) && (up_wr_s == 1'b1)) begin
up_vdma_ovf <= up_vdma_ovf & (~up_wdata[1]);
end
up_vdma_unf_m1 <= vdma_unf_s;
up_vdma_unf_m2 <= up_vdma_unf_m1;
if (up_vdma_unf_m2 == 1'b1) begin
up_vdma_unf <= 1'b1;
end else if ((up_addr == 5'h09) && (up_wr_s == 1'b1)) begin
up_vdma_unf <= up_vdma_unf & (~up_wdata[0]);
end
end
end
// process read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_sel_d <= 'd0;
up_sel_2d <= 'd0;
up_ack <= 'd0;
end else begin
case (up_addr)
5'h00: up_rdata <= 32'h00010061;
5'h01: up_rdata <= {13'd0, up_dds_sel, up_intp_enable, up_dds_enable, up_dds_incr};
5'h06: up_rdata <= {up_intp_scale_b, up_intp_scale_a};
5'h09: up_rdata <= {30'd0, up_vdma_ovf, up_vdma_unf};
default: up_rdata <= 0;
endcase
up_sel_d <= up_sel;
up_sel_2d <= up_sel_d;
up_ack <= up_ack_s;
end
end
// DDS top, includes both DDR-DDS and Xilinx-DDS.
cf_dds_top i_dds_top (
.vdma_clk (vdma_clk),
.vdma_valid (vdma_valid),
.vdma_data (vdma_data),
.vdma_ready (vdma_ready),
.vdma_ovf (vdma_ovf_s),
.vdma_unf (vdma_unf_s),
.dac_div3_clk (dac_div3_clk),
.dds_data_00 (dds_data_00_s),
.dds_data_01 (dds_data_01_s),
.dds_data_02 (dds_data_02_s),
.dds_data_03 (dds_data_03_s),
.dds_data_04 (dds_data_04_s),
.dds_data_05 (dds_data_05_s),
.dds_data_06 (dds_data_06_s),
.dds_data_07 (dds_data_07_s),
.dds_data_08 (dds_data_08_s),
.dds_data_09 (dds_data_09_s),
.dds_data_10 (dds_data_10_s),
.dds_data_11 (dds_data_11_s),
.up_dds_sel (up_dds_sel),
.up_dds_incr (up_dds_incr),
.up_dds_enable (up_dds_enable),
.up_intp_enable (up_intp_enable),
.up_intp_scale_a (up_intp_scale_a),
.up_intp_scale_b (up_intp_scale_b),
.vdma_dbg_data (vdma_dbg_data),
.vdma_dbg_trigger (vdma_dbg_trigger),
.dac_dbg_data (dac_dbg_data),
.dac_dbg_trigger (dac_dbg_trigger));
// DAC interface, (transfer samples from low speed clock to the dac clock)
cf_dac_if i_dac_if (
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_data_out_a_p (dac_data_out_a_p),
.dac_data_out_a_n (dac_data_out_a_n),
.dac_data_out_b_p (dac_data_out_b_p),
.dac_data_out_b_n (dac_data_out_b_n),
.dac_div3_clk (dac_div3_clk),
.dds_data_00 (dds_data_00_s),
.dds_data_01 (dds_data_01_s),
.dds_data_02 (dds_data_02_s),
.dds_data_03 (dds_data_03_s),
.dds_data_04 (dds_data_04_s),
.dds_data_05 (dds_data_05_s),
.dds_data_06 (dds_data_06_s),
.dds_data_07 (dds_data_07_s),
.dds_data_08 (dds_data_08_s),
.dds_data_09 (dds_data_09_s),
.dds_data_10 (dds_data_10_s),
.dds_data_11 (dds_data_11_s),
.up_dds_enable (up_dds_enable));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYMETAL6S4S_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DLYMETAL6S4S_FUNCTIONAL_PP_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__dlymetal6s4s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYMETAL6S4S_FUNCTIONAL_PP_V |
`timescale 1ns / 1ps
`include "def.v"
module MMU(clk,
reqType, ofs, lbid, addr, invalid,
lbidw, lbTypew, basew, countw, we);
input clk;
//
input [5:0] reqType;
input [15:0] ofs;
input [11:0] lbid;
//
output [15:0] addr;
output invalid;
//
input [11:0] lbidw;
input [5:0] lbTypew;
input [15:0] basew;
input [15:0] countw;
input we;
//
wire [15:0] base;
wire [15:0] count;
wire [5:0] lbType;
//
LabelTable lbt(clk,
lbid, lbidw,
lbType, lbTypew,
base, basew,
count, countw,
we);
AddrDecoder addrdec(reqType, ofs, base, count, lbType, addr, invalid);
endmodule
module testbench_mmu();
reg clk;
//
reg [5:0] reqType;
reg [15:0] ofs;
reg [11:0] lbid;
//
wire [15:0] addr;
wire invalid;
//
reg [11:0] lbidw;
reg [5:0] lbTypew;
reg [15:0] basew;
reg [15:0] countw;
reg we;
//
MMU mmu(clk,
reqType, ofs, lbid, addr, invalid,
lbidw, lbTypew, basew, countw, we);
initial begin
$dumpfile("mmu.vcd");
$dumpvars(0, testbench_mmu);
//
lbid = 0;
#1;
lbidw = 0;
lbTypew = `LBTYPE_CODE;
basew = 0;
countw = 32;
we = 1;
#2;
we = 0;
ofs = 1;
reqType = `LBTYPE_CODE;
#2;
//
$display ("Simulation end");
$finish;
end
always begin
// γ―γγγ―γηζγγγ
// #1; γ―γ1γ―γγγ―εΎ
ζ©γγγ
clk <= 0; #1;
clk <= 1; #1;
end
always @ (posedge clk)
begin
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 1.5
// \ \ Application : 7 Series FPGAs Transceivers Wizard
// / / Filename : rocketio_wrapper_tile_gt_frame_check.v
// /___/ /\
// \ \ / \
// \___\/\___\
//
//
// Module ROCKETIO_WRAPPER_TILE_GT_FRAME_CHECK
// Generated by Xilinx 7 Series FPGAs Transceivers Wizard
//
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
`timescale 1ns / 1ps
`define DLY #1
//***********************************Entity Declaration************************
module ROCKETIO_WRAPPER_TILE_GT_FRAME_CHECK #
(
// parameter to set the number of words in the BRAM
parameter RX_DATA_WIDTH = 64,
parameter RXCTRL_WIDTH = 2,
parameter WORDS_IN_BRAM = 512,
parameter CHANBOND_SEQ_LEN = 1,
parameter COMMA_DOUBLE = 16'hf628,
parameter START_OF_PACKET_CHAR = 64'h00000000000000fb
)
(
// User Interface
input wire [(RX_DATA_WIDTH-1):0] RX_DATA_IN,
output reg RXENPCOMMADET_OUT,
output reg RXENMCOMMADET_OUT,
// Error Monitoring
output wire [7:0] ERROR_COUNT_OUT,
// Track Data
output wire TRACK_DATA_OUT,
output wire RX_SLIDE,
// System Interface
input wire USER_CLK,
input wire SYSTEM_RESET
);
//***************************Internal Register Declarations********************
reg system_reset_r;
reg begin_r;
reg data_error_detected_r;
reg [8:0] error_count_r;
reg error_detected_r;
reg [9:0] read_counter_i;
reg [79:0] rom [0:511];
reg [(RX_DATA_WIDTH-1):0] rx_data_r;
reg [(RX_DATA_WIDTH-1):0] rx_data_r_track;
reg start_of_packet_detected_r;
reg track_data_r;
reg track_data_r2;
reg track_data_r3;
reg [79:0] rx_data_ram_r;
reg [(RX_DATA_WIDTH-1):0] rx_data_r2;
reg [(RX_DATA_WIDTH-1):0] rx_data_r3;
reg [(RX_DATA_WIDTH-1):0] rx_data_r4;
reg [(RX_DATA_WIDTH-1):0] rx_data_r5;
reg [(RX_DATA_WIDTH-1):0] rx_data_r6;
reg sel;
reg idle_slip_r;
reg slip_assert_r;
reg wait_state_r;
reg bit_align_r;
reg [6:0] wait_before_slip_r;
reg [6:0] wait_before_init_r;
//*********************************Wire Declarations***************************
wire [(RX_DATA_WIDTH-1):0] bram_data_r;
wire error_detected_c;
wire next_begin_c;
wire next_data_error_detected_c;
wire next_track_data_c;
wire start_of_packet_detected_c;
wire [(RX_DATA_WIDTH-1):0] rx_data_aligned;
wire rxdata_or;
wire count_slip_complete_c;
wire next_idle_slip_c;
wire next_slip_assert_c;
wire wait_state_c;
wire rx_data_has_start_char_c;
wire tied_to_ground_i;
wire [31:0] tied_to_ground_vec_i;
wire tied_to_vcc_i;
//*********************************Main Body of Code***************************
//_______________________ Static signal Assigments _______________________
assign tied_to_ground_i = 1'b0;
assign tied_to_ground_vec_i = 32'h0000;
assign tied_to_vcc_i = 1'b1;
//___________ synchronizing the async reset for ease of timing simulation ________
always@(posedge USER_CLK)
system_reset_r <= `DLY SYSTEM_RESET;
//______________________ Register RXDATA once to ease timing ______________
always @(posedge USER_CLK)
begin
rx_data_r <= `DLY RX_DATA_IN;
rx_data_r2 <= `DLY rx_data_r;
end
//________________________________ State machine __________________________
// State registers
always @(posedge USER_CLK)
if(system_reset_r)
{begin_r,track_data_r,data_error_detected_r} <= `DLY 3'b100;
else
begin
begin_r <= `DLY next_begin_c;
track_data_r <= `DLY next_track_data_c;
data_error_detected_r <= `DLY next_data_error_detected_c;
end
// Next state logic
assign next_begin_c = (begin_r && !start_of_packet_detected_r)
|| data_error_detected_r ;
assign next_track_data_c = (begin_r && start_of_packet_detected_r)
|| (track_data_r && !error_detected_r);
assign next_data_error_detected_c = (track_data_r && error_detected_r);
assign start_of_packet_detected_c = rx_data_has_start_char_c;
always @(posedge USER_CLK)
start_of_packet_detected_r <= `DLY start_of_packet_detected_c;
// Registering for timing
always @(posedge USER_CLK)
track_data_r2 <= `DLY track_data_r;
always @(posedge USER_CLK)
track_data_r3 <= `DLY track_data_r2;
//______________________________ Capture incoming data ____________________
always @(posedge USER_CLK)
begin
if(system_reset_r)
begin
rx_data_r4 <= `DLY 'h0;
rx_data_r5 <= `DLY 'h0;
rx_data_r6 <= `DLY 'h0;
rx_data_r_track <= `DLY 'h0;
end
else
begin
rx_data_r4 <= `DLY rx_data_r3;
rx_data_r5 <= `DLY rx_data_r4;
rx_data_r6 <= `DLY rx_data_r5;
rx_data_r_track <= `DLY rx_data_r6;
end
end
assign rx_data_aligned = rx_data_r3;
//______________ Code for Bit Slipping Logic for None encoding______________
assign rxdata_or = |(rx_data_r|rx_data_r2|rx_data_r3);
// State registers
always @(posedge USER_CLK)
if( (system_reset_r == 1'b1) | (wait_before_init_r[6] == 1'b0) | (rxdata_or == 1'b0) )
{idle_slip_r,slip_assert_r,wait_state_r} <= `DLY 3'b100;
else
begin
idle_slip_r <= `DLY next_idle_slip_c;
slip_assert_r <= `DLY next_slip_assert_c;
wait_state_r <= `DLY wait_state_c;
end
// Next state logic
assign next_idle_slip_c = (idle_slip_r & bit_align_r) | (wait_state_r & count_slip_complete_c);
assign next_slip_assert_c = (idle_slip_r & !bit_align_r);
assign wait_state_c = (slip_assert_r) | (wait_state_r & !count_slip_complete_c);
//_______ Counter for waiting clock cycles after RXSLIDE________
always @(posedge USER_CLK)
begin
if (!wait_state_r)
wait_before_slip_r <= `DLY 7'b000000;
else
wait_before_slip_r <= `DLY wait_before_slip_r + 1'b1;
end
//_______ Counter for waiting clock cycles before starting RXSLIDE operation________
//_______ Wait for 64 clock cycles to see if the RXDATA is already byte aligned. If not, start RXSLIDE operation
always @(posedge USER_CLK)
begin
if( (system_reset_r == 1'b1) | (rxdata_or == 1'b0) )
wait_before_init_r <= `DLY 7'b0000000;
else if (wait_before_init_r[6] == 1'b0)
wait_before_init_r <= `DLY wait_before_init_r + 1'b1;
end
assign count_slip_complete_c = wait_before_slip_r[6];
always @(posedge USER_CLK)
begin
if( (system_reset_r == 1'b1) | (rxdata_or == 1'b0) ) begin
bit_align_r <= 1'b0;
end else begin
if( ({rx_data_r[7:0],rx_data_r2[15:8]} == START_OF_PACKET_CHAR) || (rx_data_r[15:0]== START_OF_PACKET_CHAR) )
begin
bit_align_r <= 1'b1;
end
end
end
always @(posedge USER_CLK)
begin
if(system_reset_r) begin
sel <= 1'b0;
end else begin
if({rx_data_r[7:0],rx_data_r2[15:8]} == START_OF_PACKET_CHAR)
begin
sel <= 1'b1;
end
else if(rx_data_r[15:0]== START_OF_PACKET_CHAR)
begin
sel <= 1'b0;
end
end
end
always @(posedge USER_CLK)
begin
if(system_reset_r) rx_data_r3 <= 'h0;
else
begin
if(sel == 1'b1)
begin
rx_data_r3 <= `DLY {rx_data_r[7:0],rx_data_r2[15:8]};
end
else
begin
rx_data_r3 <= `DLY rx_data_r2;
end
end
end
assign rx_data_has_start_char_c = (rx_data_aligned == START_OF_PACKET_CHAR) ;
//_____________________________ Assign output ports _______________________
assign TRACK_DATA_OUT = track_data_r;
assign RX_SLIDE = slip_assert_r;
// Drive the enpcommaalign port of the gt for alignment
always @(posedge USER_CLK)
if(system_reset_r) RXENPCOMMADET_OUT <= `DLY 1'b0;
else RXENPCOMMADET_OUT <= `DLY 1'b1;
// Drive the enmcommaalign port of the gt for alignment
always @(posedge USER_CLK)
if(system_reset_r) RXENMCOMMADET_OUT <= `DLY 1'b0;
else RXENMCOMMADET_OUT <= `DLY 1'b1;
//___________________________ Check incoming data for errors ______________
//An error is detected when data read for the BRAM does not match the incoming data
assign error_detected_c = track_data_r3 && (rx_data_r_track != bram_data_r);
//We register the error_detected signal for use with the error counter logic
always @(posedge USER_CLK)
if(!track_data_r)
error_detected_r <= `DLY 1'b0;
else
error_detected_r <= `DLY error_detected_c;
//We count the total number of errors we detect. By keeping a count we make it less likely that we will miss
//errors we did not directly observe.
always @(posedge USER_CLK)
if(system_reset_r)
error_count_r <= `DLY 9'd0;
else if(error_detected_r)
error_count_r <= `DLY error_count_r + 1;
//Here we connect the lower 8 bits of the count (the MSbit is used only to check when the counter reaches
//max value) to the module output
assign ERROR_COUNT_OUT = error_count_r[7:0];
//____________________________ Counter to read from BRAM __________________________
always @(posedge USER_CLK)
if(system_reset_r || (read_counter_i == (WORDS_IN_BRAM-1)))
begin
read_counter_i <= `DLY 10'd0;
end
else if (start_of_packet_detected_r && !track_data_r)
begin
read_counter_i <= `DLY 10'd0;
end
else
begin
read_counter_i <= `DLY read_counter_i + 10'd1;
end
//________________________________ BRAM Inference Logic _____________________________
//Array slice from dat file to compare against receive data
generate
if(RX_DATA_WIDTH==80)
begin : datapath_80
assign bram_data_r = rx_data_ram_r[(RX_DATA_WIDTH-1):0];
end
else
begin : datapath_16_20_32_40_64
assign bram_data_r = rx_data_ram_r[(16+RX_DATA_WIDTH-1):16];
end
endgenerate
// initial
// begin
// $readmemh("../../mgt/gt_rom_init_rx.dat",rom,0,511);
// end
always @(posedge USER_CLK)
rx_data_ram_r <= `DLY rom[read_counter_i];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKINVLP_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__CLKINVLP_BEHAVIORAL_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__clkinvlp (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKINVLP_BEHAVIORAL_V |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_custom_add_op( clock, resetn, left_mantissa, right_mantissa, left_sign, right_sign, common_exponent,
resulting_mantissa, resulting_exponent, resulting_sign,
valid_in, valid_out, stall_in, stall_out, enable);
parameter HIGH_CAPACITY = 1;
// Latency = 1 cycle.
input clock, resetn, left_sign, right_sign;
input [26:0] left_mantissa;
input [26:0] right_mantissa;
input [8:0] common_exponent;
input valid_in, stall_in, enable;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) output reg [27:0] resulting_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) output reg [8:0] resulting_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) output reg resulting_sign;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) output reg valid_out;
output stall_out;
wire enable_add = (HIGH_CAPACITY==1) ? (~valid_out | ~stall_in) : enable;
wire do_subtraction = right_sign ^ left_sign;
assign stall_out = valid_out & stall_in;
wire [27:0] op_ab = left_mantissa + ({28{do_subtraction}} ^ right_mantissa) + do_subtraction;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
resulting_mantissa <= 28'bxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
resulting_exponent <= 9'bxxxxxxxx;
resulting_sign <= 1'bx;
valid_out <= 1'b0;
end
else if (enable_add)
begin
valid_out <= valid_in;
resulting_mantissa <= op_ab;
resulting_exponent <= common_exponent;
resulting_sign <= left_sign;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFSBP_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__DFSBP_PP_BLACKBOX_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFSBP_PP_BLACKBOX_V
|
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2006 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court 408-826-6000 (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email: [email protected]
// =============================================================================/
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_debug.v
// Title : Hardware debug registers and associated logic.
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// Version : 3.2
// : Fixed simulation bug which flares up when number of
// : watchpoints is zero.
// =============================================================================
`include "lm32_include.v"
`ifdef CFG_DEBUG_ENABLED
// States for single-step FSM
`define LM32_DEBUG_SS_STATE_RNG 2:0
`define LM32_DEBUG_SS_STATE_IDLE 3'b000
`define LM32_DEBUG_SS_STATE_WAIT_FOR_RET 3'b001
`define LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN 3'b010
`define LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT 3'b011
`define LM32_DEBUG_SS_STATE_RESTART 3'b100
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_debug (
// ----- Inputs -------
clk_i,
rst_i,
pc_x,
load_x,
store_x,
load_store_address_x,
csr_write_enable_x,
csr_write_data,
csr_x,
`ifdef CFG_HW_DEBUG_ENABLED
jtag_csr_write_enable,
jtag_csr_write_data,
jtag_csr,
`endif
`ifdef LM32_SINGLE_STEP_ENABLED
eret_q_x,
bret_q_x,
stall_x,
exception_x,
q_x,
`ifdef CFG_DCACHE_ENABLED
dcache_refill_request,
`endif
`endif
// ----- Outputs -------
`ifdef LM32_SINGLE_STEP_ENABLED
dc_ss,
`endif
dc_re,
bp_match,
wp_match
);
/////////////////////////////////////////////////////
// Parameters
/////////////////////////////////////////////////////
parameter breakpoints = 0; // Number of breakpoint CSRs
parameter watchpoints = 0; // Number of watchpoint CSRs
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Clock
input rst_i; // Reset
input [`LM32_PC_RNG] pc_x; // X stage PC
input load_x; // Load instruction in X stage
input store_x; // Store instruction in X stage
input [`LM32_WORD_RNG] load_store_address_x; // Load or store effective address
input csr_write_enable_x; // wcsr instruction in X stage
input [`LM32_WORD_RNG] csr_write_data; // Data to write to CSR
input [`LM32_CSR_RNG] csr_x; // Which CSR to write
`ifdef CFG_HW_DEBUG_ENABLED
input jtag_csr_write_enable; // JTAG interface CSR write enable
input [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to CSR
input [`LM32_CSR_RNG] jtag_csr; // Which CSR to write
`endif
`ifdef LM32_SINGLE_STEP_ENABLED
input eret_q_x; // eret instruction in X stage
input bret_q_x; // bret instruction in X stage
input stall_x; // Instruction in X stage is stalled
input exception_x; // An exception has occured in X stage
input q_x; // Indicates the instruction in the X stage is qualified
`ifdef CFG_DCACHE_ENABLED
input dcache_refill_request; // Indicates data cache wants to be refilled
`endif
`endif
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
`ifdef LM32_SINGLE_STEP_ENABLED
output dc_ss; // Single-step enable
reg dc_ss;
`endif
output dc_re; // Remap exceptions
reg dc_re;
output bp_match; // Indicates a breakpoint has matched
wire bp_match;
output wp_match; // Indicates a watchpoint has matched
wire wp_match;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
genvar i; // Loop index for generate statements
// Debug CSRs
reg [`LM32_PC_RNG] bp_a[0:breakpoints-1]; // Instruction breakpoint address
reg bp_e[0:breakpoints-1]; // Instruction breakpoint enable
wire [0:breakpoints-1]bp_match_n; // Indicates if a h/w instruction breakpoint matched
reg [`LM32_WPC_C_RNG] wpc_c[0:watchpoints-1]; // Watchpoint enable
reg [`LM32_WORD_RNG] wp[0:watchpoints-1]; // Watchpoint address
wire [0:watchpoints]wp_match_n; // Indicates if a h/w data watchpoint matched
wire debug_csr_write_enable; // Debug CSR write enable (from either a wcsr instruction of external debugger)
wire [`LM32_WORD_RNG] debug_csr_write_data; // Data to write to debug CSR
wire [`LM32_CSR_RNG] debug_csr; // Debug CSR to write to
`ifdef LM32_SINGLE_STEP_ENABLED
// FIXME: Declaring this as a reg causes ModelSim 6.1.15b to crash, so use integer for now
//reg [`LM32_DEBUG_SS_STATE_RNG] state; // State of single-step FSM
integer state; // State of single-step FSM
`endif
/////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////
`include "lm32_functions.v"
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
// Check for breakpoints
generate
for (i = 0; i < breakpoints; i = i + 1)
begin : bp_comb
assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == `TRUE));
end
endgenerate
generate
`ifdef LM32_SINGLE_STEP_ENABLED
if (breakpoints > 0)
assign bp_match = (|bp_match_n) || (state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT);
else
assign bp_match = state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT;
`else
if (breakpoints > 0)
assign bp_match = |bp_match_n;
else
assign bp_match = `FALSE;
`endif
endgenerate
// Check for watchpoints
generate
for (i = 0; i < watchpoints; i = i + 1)
begin : wp_comb
assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1]));
end
endgenerate
generate
if (watchpoints > 0)
assign wp_match = |wp_match_n;
else
assign wp_match = `FALSE;
endgenerate
`ifdef CFG_HW_DEBUG_ENABLED
// Multiplex between wcsr instruction writes and debugger writes to the debug CSRs
assign debug_csr_write_enable = (csr_write_enable_x == `TRUE) || (jtag_csr_write_enable == `TRUE);
assign debug_csr_write_data = jtag_csr_write_enable == `TRUE ? jtag_csr_write_data : csr_write_data;
assign debug_csr = jtag_csr_write_enable == `TRUE ? jtag_csr : csr_x;
`else
assign debug_csr_write_enable = csr_write_enable_x;
assign debug_csr_write_data = csr_write_data;
assign debug_csr = csr_x;
`endif
/////////////////////////////////////////////////////
// Sequential Logic
/////////////////////////////////////////////////////
// Breakpoint address and enable CSRs
generate
for (i = 0; i < breakpoints; i = i + 1)
begin : bp_seq
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
bp_a[i] <= {`LM32_PC_WIDTH{1'bx}};
bp_e[i] <= `FALSE;
end
else
begin
if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_BP0 + i))
begin
bp_a[i] <= debug_csr_write_data[`LM32_PC_RNG];
bp_e[i] <= debug_csr_write_data[0];
end
end
end
end
endgenerate
// Watchpoint address and control flags CSRs
generate
for (i = 0; i < watchpoints; i = i + 1)
begin : wp_seq
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
wp[i] <= {`LM32_WORD_WIDTH{1'bx}};
wpc_c[i] <= `LM32_WPC_C_DISABLED;
end
else
begin
if (debug_csr_write_enable == `TRUE)
begin
if (debug_csr == `LM32_CSR_DC)
wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2];
if (debug_csr == `LM32_CSR_WP0 + i)
wp[i] <= debug_csr_write_data;
end
end
end
end
endgenerate
// Remap exceptions control bit
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
dc_re <= `FALSE;
else
begin
if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC))
dc_re <= debug_csr_write_data[1];
end
end
`ifdef LM32_SINGLE_STEP_ENABLED
// Single-step control flag
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
state <= `LM32_DEBUG_SS_STATE_IDLE;
dc_ss <= `FALSE;
end
else
begin
if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC))
begin
dc_ss <= debug_csr_write_data[0];
if (debug_csr_write_data[0] == `FALSE)
state <= `LM32_DEBUG_SS_STATE_IDLE;
else
state <= `LM32_DEBUG_SS_STATE_WAIT_FOR_RET;
end
case (state)
`LM32_DEBUG_SS_STATE_WAIT_FOR_RET:
begin
// Wait for eret or bret instruction to be executed
if ( ( (eret_q_x == `TRUE)
|| (bret_q_x == `TRUE)
)
&& (stall_x == `FALSE)
)
state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
end
`LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN:
begin
// Wait for an instruction to be executed
if ((q_x == `TRUE) && (stall_x == `FALSE))
state <= `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT;
end
`LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT:
begin
// Wait for exception to be raised
`ifdef CFG_DCACHE_ENABLED
if (dcache_refill_request == `TRUE)
state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
else
`endif
if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
begin
dc_ss <= `FALSE;
state <= `LM32_DEBUG_SS_STATE_RESTART;
end
end
`LM32_DEBUG_SS_STATE_RESTART:
begin
// Watch to see if stepped instruction is restarted due to a cache miss
`ifdef CFG_DCACHE_ENABLED
if (dcache_refill_request == `TRUE)
state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
else
`endif
state <= `LM32_DEBUG_SS_STATE_IDLE;
end
endcase
end
end
`endif
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O211A_4_V
`define SKY130_FD_SC_LS__O211A_4_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o211a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o211a_4 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o211a_4 (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O211A_4_V
|
//////////////////////////////////////////////////////////////////
// //
// Memory Access - Instantiates the memory access stage //
// sub-modules of the Amber 25 Core //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Instantiates the Data Cache //
// Also contains a little bit of logic to decode memory //
// accesses to decide if they are cached or not //
// //
// Author(s): //
// - Conor Santifort, [email protected] //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2011 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module a25_mem
(
input i_clk,
input i_fetch_stall, // Fetch stage asserting stall
input i_exec_stall, // Execute stage asserting stall
output o_mem_stall, // Mem stage asserting stall
input [31:0] i_daddress,
input i_daddress_valid,
input [31:0] i_daddress_nxt, // un-registered version of address to the cache rams
input [31:0] i_write_data,
input i_write_enable,
input i_exclusive, // high for read part of swap access
input [3:0] i_byte_enable,
input [8:0] i_exec_load_rd, // The destination register for a load instruction
input i_cache_enable, // cache enable
input i_cache_flush, // cache flush
input [31:0] i_cacheable_area, // each bit corresponds to 2MB address space
output [31:0] o_mem_read_data,
output o_mem_read_data_valid,
output [10:0] o_mem_load_rd, // The destination register for a load instruction
// Wishbone accesses
output o_wb_cached_req, // Cached Request
output o_wb_uncached_req, // Unached Request
output o_wb_write, // Read=0, Write=1
output [15:0] o_wb_byte_enable, // byte eable
output [127:0] o_wb_write_data,
output [31:0] o_wb_address, // wb bus
input [127:0] i_wb_uncached_rdata, // wb bus
input [127:0] i_wb_cached_rdata, // wb bus
input i_wb_cached_ready, // wishbone access complete and read data valid
input i_wb_uncached_ready // wishbone access complete and read data valid
);
`include "memory_configuration.v"
wire [31:0] cache_read_data;
wire address_cachable;
wire sel_cache_p;
wire sel_cache;
wire cached_wb_req;
wire uncached_data_access;
wire uncached_data_access_p;
wire cache_stall;
wire uncached_wb_wait;
reg uncached_wb_req_r = 'd0;
reg uncached_wb_stop_r = 'd0;
reg cached_wb_stop_r = 'd0;
wire daddress_valid_p; // pulse
reg [31:0] mem_read_data_r = 'd0;
reg mem_read_data_valid_r = 'd0;
reg [10:0] mem_load_rd_r = 'd0;
wire [10:0] mem_load_rd_c;
wire [31:0] mem_read_data_c;
wire mem_read_data_valid_c;
reg mem_stall_r = 'd0;
wire use_mem_reg;
reg fetch_only_stall_r = 'd0;
wire fetch_only_stall;
wire void_output;
wire wb_stop;
reg daddress_valid_stop_r = 'd0;
wire [31:0] wb_rdata32;
// ======================================
// Memory Decode
// ======================================
assign address_cachable = in_cachable_mem( i_daddress ) && i_cacheable_area[i_daddress[25:21]];
assign sel_cache_p = daddress_valid_p && address_cachable && i_cache_enable && !i_exclusive;
assign sel_cache = i_daddress_valid && address_cachable && i_cache_enable && !i_exclusive;
assign uncached_data_access = i_daddress_valid && !sel_cache && !cache_stall;
assign uncached_data_access_p = daddress_valid_p && !sel_cache;
assign use_mem_reg = wb_stop && !mem_stall_r;
assign o_mem_read_data = use_mem_reg ? mem_read_data_r : mem_read_data_c;
assign o_mem_load_rd = use_mem_reg ? mem_load_rd_r : mem_load_rd_c;
assign o_mem_read_data_valid = !void_output && (use_mem_reg ? mem_read_data_valid_r : mem_read_data_valid_c);
// Return read data either from the wishbone bus or the cache
assign wb_rdata32 = i_daddress[3:2] == 2'd0 ? i_wb_uncached_rdata[ 31: 0] :
i_daddress[3:2] == 2'd1 ? i_wb_uncached_rdata[ 63:32] :
i_daddress[3:2] == 2'd2 ? i_wb_uncached_rdata[ 95:64] :
i_wb_uncached_rdata[127:96] ;
assign mem_read_data_c = sel_cache ? cache_read_data :
uncached_data_access ? wb_rdata32 :
32'h76543210 ;
assign mem_load_rd_c = {i_daddress[1:0], i_exec_load_rd};
assign mem_read_data_valid_c = i_daddress_valid && !i_write_enable && !o_mem_stall;
assign o_mem_stall = uncached_wb_wait || cache_stall;
// Request wishbone access
assign o_wb_byte_enable = i_daddress[3:2] == 2'd0 ? {12'd0, i_byte_enable } :
i_daddress[3:2] == 2'd1 ? { 8'd0, i_byte_enable, 4'd0} :
i_daddress[3:2] == 2'd2 ? { 4'd0, i_byte_enable, 8'd0} :
{ i_byte_enable, 12'd0} ;
assign o_wb_write = i_write_enable;
assign o_wb_address = {i_daddress[31:2], 2'd0};
assign o_wb_write_data = {4{i_write_data}};
assign o_wb_cached_req = !cached_wb_stop_r && cached_wb_req;
assign o_wb_uncached_req = !uncached_wb_stop_r && uncached_data_access_p;
assign uncached_wb_wait = (o_wb_uncached_req || uncached_wb_req_r) && !i_wb_uncached_ready;
always @( posedge i_clk )
begin
uncached_wb_req_r <= (o_wb_uncached_req || uncached_wb_req_r) && !i_wb_uncached_ready;
end
assign fetch_only_stall = i_fetch_stall && !o_mem_stall;
always @( posedge i_clk )
fetch_only_stall_r <= fetch_only_stall;
assign void_output = (fetch_only_stall_r && fetch_only_stall) || (fetch_only_stall_r && mem_read_data_valid_r);
// pulse this signal
assign daddress_valid_p = i_daddress_valid && !daddress_valid_stop_r;
always @( posedge i_clk )
begin
uncached_wb_stop_r <= (uncached_wb_stop_r || (uncached_data_access_p&&!cache_stall)) && (i_fetch_stall || o_mem_stall);
cached_wb_stop_r <= (cached_wb_stop_r || cached_wb_req) && (i_fetch_stall || o_mem_stall);
daddress_valid_stop_r <= (daddress_valid_stop_r || daddress_valid_p) && (i_fetch_stall || o_mem_stall);
// hold this until the mem access completes
mem_stall_r <= o_mem_stall;
end
assign wb_stop = uncached_wb_stop_r || cached_wb_stop_r;
always @( posedge i_clk )
if ( !wb_stop || o_mem_stall )
begin
mem_read_data_r <= mem_read_data_c;
mem_load_rd_r <= mem_load_rd_c;
mem_read_data_valid_r <= mem_read_data_valid_c;
end
// ======================================
// L1 Data Cache
// ======================================
a25_dcache u_dcache (
.i_clk ( i_clk ),
.i_fetch_stall ( i_fetch_stall ),
.i_exec_stall ( i_exec_stall ),
.o_stall ( cache_stall ),
.i_request ( sel_cache_p ),
.i_exclusive ( i_exclusive ),
.i_write_data ( i_write_data ),
.i_write_enable ( i_write_enable ),
.i_address ( i_daddress ),
.i_address_nxt ( i_daddress_nxt ),
.i_byte_enable ( i_byte_enable ),
.i_cache_enable ( i_cache_enable ),
.i_cache_flush ( i_cache_flush ),
.o_read_data ( cache_read_data ),
.o_wb_cached_req ( cached_wb_req ),
.i_wb_cached_rdata ( i_wb_cached_rdata ),
.i_wb_cached_ready ( i_wb_cached_ready )
);
endmodule
|
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Up-Sizer
// Up-Sizer for generic SI- and MI-side data widths. This module instantiates
// Address, Write Data and Read Data Up-Sizer modules, each one taking care
// of the channel specific tasks.
// The Address Up-Sizer can handle both AR and AW channels.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axi_upsizer
// a_upsizer
// fifo
// fifo_gen
// fifo_coregen
// w_upsizer
// r_upsizer
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_axi_upsizer #
(
parameter C_FAMILY = "virtex7",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_AXI_PROTOCOL = 0,
// Protocol of SI and MI (0=AXI4, 1=AXI3).
parameter integer C_S_AXI_ID_WIDTH = 1,
// Width of all ID signals on SI side of converter.
// Range: 1 - 32.
parameter integer C_SUPPORTS_ID = 0,
// Indicates whether SI-side ID needs to be stored and compared.
// 0 = No, SI is single-threaded, propagate all transactions.
// 1 = Yes, stall any transaction with ID different than outstanding transactions.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI.
// Range (AXI4, AXI3): 12 - 64.
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of s_axi_wdata and s_axi_rdata.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_M_AXI_DATA_WIDTH = 64,
// Width of m_axi_wdata and m_axi_rdata.
// Assume always >= than C_S_AXI_DATA_WIDTH.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1,
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// parameter integer C_FIFO_MODE = 0,
parameter integer C_FIFO_MODE = 1,
// 0=None, 1=Packet_FIFO, 2=Clock_conversion_Packet_FIFO, 3=Simple_FIFO (FUTURE), 4=Clock_conversion_Simple_FIFO (FUTURE)
parameter integer C_S_AXI_ACLK_RATIO = 1, // Clock frequency ratio of SI w.r.t. MI.
// Range = [1..16].
parameter integer C_M_AXI_ACLK_RATIO = 2, // Clock frequency ratio of MI w.r.t. SI.
// Range = [2..16] if C_S_AXI_ACLK_RATIO = 1; else must be 1.
parameter integer C_AXI_IS_ACLK_ASYNC = 0, // Indicates whether S and M clocks are asynchronous.
// FUTURE FEATURE
// Range = [0, 1].
parameter integer C_PACKING_LEVEL = 1,
// 0 = Never pack (expander only); packing logic is omitted.
// 1 = Pack only when CACHE[1] (Modifiable) is high.
// 2 = Always pack, regardless of sub-size transaction or Modifiable bit.
// (Required when used as helper-core by mem-con. Same size AXI interfaces
// should only be used when always packing)
parameter integer C_SYNCHRONIZER_STAGE = 3
)
(
// Slave Interface
input wire s_axi_aresetn,
input wire s_axi_aclk,
// Slave Interface Write Address Ports
input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [8-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [2-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire s_axi_awvalid,
output wire s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire s_axi_wvalid,
output wire s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_S_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire s_axi_bvalid,
input wire s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [8-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [2-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire s_axi_arvalid,
output wire s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_S_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Master Interface
input wire m_axi_aresetn,
input wire m_axi_aclk,
// Master Interface Write Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [8-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [2-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire m_axi_awvalid,
input wire m_axi_awready,
// Master Interface Write Data Ports
output wire [C_M_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_M_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire m_axi_wvalid,
input wire m_axi_wready,
// Master Interface Write Response Ports
input wire [2-1:0] m_axi_bresp,
input wire m_axi_bvalid,
output wire m_axi_bready,
// Master Interface Read Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [8-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [2-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data Ports
input wire [C_M_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire m_axi_rvalid,
output wire m_axi_rready
);
// Log2 of number of 32bit word on SI-side.
localparam integer C_S_AXI_BYTES_LOG = log2(C_S_AXI_DATA_WIDTH/8);
// Log2 of number of 32bit word on MI-side.
localparam integer C_M_AXI_BYTES_LOG = log2(C_M_AXI_DATA_WIDTH/8);
// Log2 of Up-Sizing ratio for data.
localparam integer C_RATIO = C_M_AXI_DATA_WIDTH / C_S_AXI_DATA_WIDTH;
localparam integer C_RATIO_LOG = log2(C_RATIO);
localparam P_BYPASS = 32'h0;
localparam P_LIGHTWT = 32'h7;
localparam P_FWD_REV = 32'h1;
localparam integer P_CONV_LIGHT_WT = 0;
localparam integer P_AXI4 = 0;
localparam integer C_FIFO_DEPTH_LOG = 5;
localparam P_SI_LT_MI = (C_S_AXI_ACLK_RATIO < C_M_AXI_ACLK_RATIO);
localparam integer P_ACLK_RATIO = P_SI_LT_MI ? (C_M_AXI_ACLK_RATIO / C_S_AXI_ACLK_RATIO) : (C_S_AXI_ACLK_RATIO / C_M_AXI_ACLK_RATIO);
localparam integer P_NO_FIFO = 0;
localparam integer P_PKTFIFO = 1;
localparam integer P_PKTFIFO_CLK = 2;
localparam integer P_DATAFIFO = 3;
localparam integer P_DATAFIFO_CLK = 4;
localparam P_CLK_CONV = ((C_FIFO_MODE == P_PKTFIFO_CLK) || (C_FIFO_MODE == P_DATAFIFO_CLK));
localparam integer C_M_AXI_AW_REGISTER = 0;
// Simple register AW output.
// Range: 0, 1
localparam integer C_M_AXI_W_REGISTER = 1; // Parameter not used; W reg always implemented.
localparam integer C_M_AXI_AR_REGISTER = 0;
// Simple register AR output.
// Range: 0, 1
localparam integer C_S_AXI_R_REGISTER = 0;
// Simple register R output (SI).
// Range: 0, 1
localparam integer C_M_AXI_R_REGISTER = 1;
// Register slice on R input (MI) side.
// 0 = Bypass (not recommended due to combinatorial M_RVALID -> M_RREADY path)
// 1 = Fully-registered (needed only when upsizer propagates bursts at 1:1 width ratio)
// 7 = Light-weight (safe when upsizer always packs at 1:n width ratio, as in interconnect)
localparam integer P_RID_QUEUE = ((C_SUPPORTS_ID != 0) && !((C_FIFO_MODE == P_PKTFIFO) || (C_FIFO_MODE == P_PKTFIFO_CLK))) ? 1 : 0;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
// Log2.
function integer log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
log2 = acc;
end
endfunction
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire aclk;
wire m_aclk;
wire sample_cycle;
wire sample_cycle_early;
wire sm_aresetn;
wire s_aresetn_i;
wire [C_S_AXI_ID_WIDTH-1:0] sr_awid ;
wire [C_AXI_ADDR_WIDTH-1:0] sr_awaddr ;
wire [8-1:0] sr_awlen ;
wire [3-1:0] sr_awsize ;
wire [2-1:0] sr_awburst ;
wire [2-1:0] sr_awlock ;
wire [4-1:0] sr_awcache ;
wire [3-1:0] sr_awprot ;
wire [4-1:0] sr_awregion ;
wire [4-1:0] sr_awqos ;
wire sr_awvalid ;
wire sr_awready ;
wire [C_S_AXI_ID_WIDTH-1:0] sr_arid ;
wire [C_AXI_ADDR_WIDTH-1:0] sr_araddr ;
wire [8-1:0] sr_arlen ;
wire [3-1:0] sr_arsize ;
wire [2-1:0] sr_arburst ;
wire [2-1:0] sr_arlock ;
wire [4-1:0] sr_arcache ;
wire [3-1:0] sr_arprot ;
wire [4-1:0] sr_arregion ;
wire [4-1:0] sr_arqos ;
wire sr_arvalid ;
wire sr_arready ;
wire [C_S_AXI_DATA_WIDTH-1:0] sr_wdata ;
wire [(C_S_AXI_DATA_WIDTH/8)-1:0] sr_wstrb ;
wire sr_wlast ;
wire sr_wvalid ;
wire sr_wready ;
wire [C_M_AXI_DATA_WIDTH-1:0] mr_rdata ;
wire [2-1:0] mr_rresp ;
wire mr_rlast ;
wire mr_rvalid ;
wire mr_rready ;
wire m_axi_rready_i;
wire [((C_AXI_PROTOCOL==P_AXI4)?8:4)-1:0] s_axi_awlen_i ;
wire [((C_AXI_PROTOCOL==P_AXI4)?8:4)-1:0] s_axi_arlen_i ;
wire [((C_AXI_PROTOCOL==P_AXI4)?1:2)-1:0] s_axi_awlock_i ;
wire [((C_AXI_PROTOCOL==P_AXI4)?1:2)-1:0] s_axi_arlock_i ;
wire [((C_AXI_PROTOCOL==P_AXI4)?8:4)-1:0] s_axi_awlen_ii ;
wire [((C_AXI_PROTOCOL==P_AXI4)?8:4)-1:0] s_axi_arlen_ii ;
wire [((C_AXI_PROTOCOL==P_AXI4)?1:2)-1:0] s_axi_awlock_ii ;
wire [((C_AXI_PROTOCOL==P_AXI4)?1:2)-1:0] s_axi_arlock_ii ;
wire [3:0] s_axi_awregion_ii;
wire [3:0] s_axi_arregion_ii;
assign s_axi_awlen_i = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_awlen : s_axi_awlen[3:0];
assign s_axi_awlock_i = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_awlock[0] : s_axi_awlock;
assign s_axi_arlen_i = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_arlen : s_axi_arlen[3:0];
assign s_axi_arlock_i = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_arlock[0] : s_axi_arlock;
assign sr_awlen = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_awlen_ii: {4'b0, s_axi_awlen_ii};
assign sr_awlock = (C_AXI_PROTOCOL == P_AXI4) ? {1'b0, s_axi_awlock_ii} : s_axi_awlock_ii;
assign sr_arlen = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_arlen_ii: {4'b0, s_axi_arlen_ii};
assign sr_arlock = (C_AXI_PROTOCOL == P_AXI4) ? {1'b0, s_axi_arlock_ii} : s_axi_arlock_ii;
assign sr_awregion = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_awregion_ii : 4'b0;
assign sr_arregion = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_arregion_ii : 4'b0;
assign aclk = s_axi_aclk;
assign sm_aresetn = s_axi_aresetn & m_axi_aresetn;
generate
if (P_CLK_CONV) begin : gen_clock_conv
if (C_AXI_IS_ACLK_ASYNC) begin : gen_async_conv
assign m_aclk = m_axi_aclk;
assign s_aresetn_i = s_axi_aresetn;
assign sample_cycle_early = 1'b1;
assign sample_cycle = 1'b1;
end else begin : gen_sync_conv
wire fast_aclk;
wire slow_aclk;
reg s_aresetn_r;
if (P_SI_LT_MI) begin : gen_fastclk_mi
assign fast_aclk = m_axi_aclk;
assign slow_aclk = s_axi_aclk;
end else begin : gen_fastclk_si
assign fast_aclk = s_axi_aclk;
assign slow_aclk = m_axi_aclk;
end
assign m_aclk = m_axi_aclk;
assign s_aresetn_i = s_aresetn_r;
always @(negedge sm_aresetn, posedge fast_aclk) begin
if (~sm_aresetn) begin
s_aresetn_r <= 1'b0;
end else if (s_axi_aresetn & m_axi_aresetn & sample_cycle_early) begin
s_aresetn_r <= 1'b1;
end
end
// Sample cycle used to determine when to assert a signal on a fast clock
// to be flopped onto a slow clock.
axi_clock_converter_v2_1_axic_sample_cycle_ratio #(
.C_RATIO ( P_ACLK_RATIO )
)
axic_sample_cycle_inst (
.SLOW_ACLK ( slow_aclk ) ,
.FAST_ACLK ( fast_aclk ) ,
.SAMPLE_CYCLE_EARLY ( sample_cycle_early ) ,
.SAMPLE_CYCLE ( sample_cycle )
);
end
end else begin : gen_no_clk_conv
assign m_aclk = s_axi_aclk;
assign s_aresetn_i = s_axi_aresetn;
assign sample_cycle_early = 1'b1;
assign sample_cycle = 1'b1;
end // gen_clock_conv
axi_register_slice_v2_1_axi_register_slice #
(
.C_FAMILY (C_FAMILY),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_USER_SIGNALS (0),
.C_REG_CONFIG_AW (C_AXI_SUPPORTS_WRITE ? P_LIGHTWT : P_BYPASS),
.C_REG_CONFIG_AR (C_AXI_SUPPORTS_READ ? P_LIGHTWT : P_BYPASS)
)
si_register_slice_inst
(
.aresetn (s_aresetn_i),
.aclk (aclk),
.s_axi_awid (s_axi_awid ),
.s_axi_awaddr (s_axi_awaddr ),
.s_axi_awlen (s_axi_awlen_i ),
.s_axi_awsize (s_axi_awsize ),
.s_axi_awburst (s_axi_awburst ),
.s_axi_awlock (s_axi_awlock_i ),
.s_axi_awcache (s_axi_awcache ),
.s_axi_awprot (s_axi_awprot ),
.s_axi_awregion (s_axi_awregion ),
.s_axi_awqos (s_axi_awqos ),
.s_axi_awuser (1'b0 ),
.s_axi_awvalid (s_axi_awvalid ),
.s_axi_awready (s_axi_awready ),
.s_axi_wid ( {C_S_AXI_ID_WIDTH{1'b0}}),
.s_axi_wdata ( {C_S_AXI_DATA_WIDTH{1'b0}} ),
.s_axi_wstrb ( {C_S_AXI_DATA_WIDTH/8{1'b0}} ),
.s_axi_wlast ( 1'b0 ),
.s_axi_wuser ( 1'b0 ),
.s_axi_wvalid ( 1'b0 ),
.s_axi_wready ( ),
.s_axi_bid ( ),
.s_axi_bresp ( ),
.s_axi_buser ( ),
.s_axi_bvalid ( ),
.s_axi_bready ( 1'b0 ),
.s_axi_arid (s_axi_arid ),
.s_axi_araddr (s_axi_araddr ),
.s_axi_arlen (s_axi_arlen_i ),
.s_axi_arsize (s_axi_arsize ),
.s_axi_arburst (s_axi_arburst ),
.s_axi_arlock (s_axi_arlock_i ),
.s_axi_arcache (s_axi_arcache ),
.s_axi_arprot (s_axi_arprot ),
.s_axi_arregion (s_axi_arregion ),
.s_axi_arqos (s_axi_arqos ),
.s_axi_aruser (1'b0 ),
.s_axi_arvalid (s_axi_arvalid ),
.s_axi_arready (s_axi_arready ),
.s_axi_rid ( ) ,
.s_axi_rdata ( ) ,
.s_axi_rresp ( ) ,
.s_axi_rlast ( ) ,
.s_axi_ruser ( ) ,
.s_axi_rvalid ( ) ,
.s_axi_rready ( 1'b0 ) ,
.m_axi_awid (sr_awid ),
.m_axi_awaddr (sr_awaddr ),
.m_axi_awlen (s_axi_awlen_ii),
.m_axi_awsize (sr_awsize ),
.m_axi_awburst (sr_awburst ),
.m_axi_awlock (s_axi_awlock_ii),
.m_axi_awcache (sr_awcache ),
.m_axi_awprot (sr_awprot ),
.m_axi_awregion (s_axi_awregion_ii ),
.m_axi_awqos (sr_awqos ),
.m_axi_awuser (),
.m_axi_awvalid (sr_awvalid ),
.m_axi_awready (sr_awready ),
.m_axi_wid () ,
.m_axi_wdata (),
.m_axi_wstrb (),
.m_axi_wlast (),
.m_axi_wuser (),
.m_axi_wvalid (),
.m_axi_wready (1'b0),
.m_axi_bid ( {C_S_AXI_ID_WIDTH{1'b0}} ) ,
.m_axi_bresp ( 2'b0 ) ,
.m_axi_buser ( 1'b0 ) ,
.m_axi_bvalid ( 1'b0 ) ,
.m_axi_bready ( ) ,
.m_axi_arid (sr_arid ),
.m_axi_araddr (sr_araddr ),
.m_axi_arlen (s_axi_arlen_ii),
.m_axi_arsize (sr_arsize ),
.m_axi_arburst (sr_arburst ),
.m_axi_arlock (s_axi_arlock_ii),
.m_axi_arcache (sr_arcache ),
.m_axi_arprot (sr_arprot ),
.m_axi_arregion (s_axi_arregion_ii ),
.m_axi_arqos (sr_arqos ),
.m_axi_aruser (),
.m_axi_arvalid (sr_arvalid ),
.m_axi_arready (sr_arready ),
.m_axi_rid ( {C_S_AXI_ID_WIDTH{1'b0}}),
.m_axi_rdata ( {C_S_AXI_DATA_WIDTH{1'b0}} ),
.m_axi_rresp ( 2'b00 ),
.m_axi_rlast ( 1'b0 ),
.m_axi_ruser ( 1'b0 ),
.m_axi_rvalid ( 1'b0 ),
.m_axi_rready ( )
);
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
if (C_AXI_SUPPORTS_WRITE == 1) begin : USE_WRITE
wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr_i ;
wire [8-1:0] m_axi_awlen_i ;
wire [3-1:0] m_axi_awsize_i ;
wire [2-1:0] m_axi_awburst_i ;
wire [2-1:0] m_axi_awlock_i ;
wire [4-1:0] m_axi_awcache_i ;
wire [3-1:0] m_axi_awprot_i ;
wire [4-1:0] m_axi_awregion_i ;
wire [4-1:0] m_axi_awqos_i ;
wire m_axi_awvalid_i ;
wire m_axi_awready_i ;
wire s_axi_bvalid_i ;
wire [2-1:0] s_axi_bresp_i ;
wire [C_AXI_ADDR_WIDTH-1:0] wr_cmd_si_addr;
wire [8-1:0] wr_cmd_si_len;
wire [3-1:0] wr_cmd_si_size;
wire [2-1:0] wr_cmd_si_burst;
// Write Channel Signals for Commands Queue Interface.
wire wr_cmd_valid;
wire wr_cmd_fix;
wire wr_cmd_modified;
wire wr_cmd_complete_wrap;
wire wr_cmd_packed_wrap;
wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_first_word;
wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_next_word;
wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_last_word;
wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_offset;
wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_mask;
wire [C_S_AXI_BYTES_LOG:0] wr_cmd_step;
wire [8-1:0] wr_cmd_length;
wire wr_cmd_ready;
wire wr_cmd_id_ready;
wire [C_S_AXI_ID_WIDTH-1:0] wr_cmd_id;
wire wpush;
wire wpop;
reg [C_FIFO_DEPTH_LOG-1:0] wcnt;
// Write Address Channel.
axi_dwidth_converter_v2_1_a_upsizer #
(
.C_FAMILY ("rtl"),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_SUPPORTS_ID (C_SUPPORTS_ID),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_M_AXI_REGISTER (C_M_AXI_AW_REGISTER),
.C_AXI_CHANNEL (0),
.C_PACKING_LEVEL (C_PACKING_LEVEL),
.C_FIFO_MODE (C_FIFO_MODE),
.C_ID_QUEUE (C_SUPPORTS_ID),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (~s_aresetn_i),
.ACLK (aclk),
// Command Interface
.cmd_valid (wr_cmd_valid),
.cmd_fix (wr_cmd_fix),
.cmd_modified (wr_cmd_modified),
.cmd_complete_wrap (wr_cmd_complete_wrap),
.cmd_packed_wrap (wr_cmd_packed_wrap),
.cmd_first_word (wr_cmd_first_word),
.cmd_next_word (wr_cmd_next_word),
.cmd_last_word (wr_cmd_last_word),
.cmd_offset (wr_cmd_offset),
.cmd_mask (wr_cmd_mask),
.cmd_step (wr_cmd_step),
.cmd_length (wr_cmd_length),
.cmd_ready (wr_cmd_ready),
.cmd_id (wr_cmd_id),
.cmd_id_ready (wr_cmd_id_ready),
.cmd_si_addr (wr_cmd_si_addr ),
.cmd_si_id (),
.cmd_si_len (wr_cmd_si_len ),
.cmd_si_size (wr_cmd_si_size ),
.cmd_si_burst (wr_cmd_si_burst),
// Slave Interface Write Address Ports
.S_AXI_AID (sr_awid),
.S_AXI_AADDR (sr_awaddr),
.S_AXI_ALEN (sr_awlen),
.S_AXI_ASIZE (sr_awsize),
.S_AXI_ABURST (sr_awburst),
.S_AXI_ALOCK (sr_awlock),
.S_AXI_ACACHE (sr_awcache),
.S_AXI_APROT (sr_awprot),
.S_AXI_AREGION (sr_awregion),
.S_AXI_AQOS (sr_awqos),
.S_AXI_AVALID (sr_awvalid),
.S_AXI_AREADY (sr_awready),
// Master Interface Write Address Port
.M_AXI_AADDR (m_axi_awaddr_i ),
.M_AXI_ALEN (m_axi_awlen_i ),
.M_AXI_ASIZE (m_axi_awsize_i ),
.M_AXI_ABURST (m_axi_awburst_i ),
.M_AXI_ALOCK (m_axi_awlock_i ),
.M_AXI_ACACHE (m_axi_awcache_i ),
.M_AXI_APROT (m_axi_awprot_i ),
.M_AXI_AREGION (m_axi_awregion_i ),
.M_AXI_AQOS (m_axi_awqos_i ),
.M_AXI_AVALID (m_axi_awvalid_i ),
.M_AXI_AREADY (m_axi_awready_i )
);
if ((C_FIFO_MODE == P_PKTFIFO) || (C_FIFO_MODE == P_PKTFIFO_CLK)) begin : gen_pktfifo_w_upsizer
// Packet FIFO Write Data channel.
axi_dwidth_converter_v2_1_w_upsizer_pktfifo #
(
.C_FAMILY (C_FAMILY),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO (C_RATIO),
.C_RATIO_LOG (C_RATIO_LOG),
.C_CLK_CONV (P_CLK_CONV),
.C_S_AXI_ACLK_RATIO (C_S_AXI_ACLK_RATIO),
.C_M_AXI_ACLK_RATIO (C_M_AXI_ACLK_RATIO),
.C_AXI_IS_ACLK_ASYNC (C_AXI_IS_ACLK_ASYNC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE)
) pktfifo_write_data_inst
(
.S_AXI_ARESETN ( s_axi_aresetn ) ,
.S_AXI_ACLK ( s_axi_aclk ) ,
.M_AXI_ARESETN ( m_axi_aresetn ) ,
.M_AXI_ACLK ( m_axi_aclk ) ,
// Command Interface
.cmd_si_addr (wr_cmd_si_addr ),
.cmd_si_len (wr_cmd_si_len ),
.cmd_si_size (wr_cmd_si_size ),
.cmd_si_burst (wr_cmd_si_burst),
.cmd_ready (wr_cmd_ready),
// Slave Interface Write Address Ports
.S_AXI_AWADDR (m_axi_awaddr_i ),
.S_AXI_AWLEN (m_axi_awlen_i ),
.S_AXI_AWSIZE (m_axi_awsize_i ),
.S_AXI_AWBURST (m_axi_awburst_i ),
.S_AXI_AWLOCK (m_axi_awlock_i ),
.S_AXI_AWCACHE (m_axi_awcache_i ),
.S_AXI_AWPROT (m_axi_awprot_i ),
.S_AXI_AWREGION (m_axi_awregion_i ),
.S_AXI_AWQOS (m_axi_awqos_i ),
.S_AXI_AWVALID (m_axi_awvalid_i ),
.S_AXI_AWREADY (m_axi_awready_i ),
// Master Interface Write Address Port
.M_AXI_AWADDR (m_axi_awaddr),
.M_AXI_AWLEN (m_axi_awlen),
.M_AXI_AWSIZE (m_axi_awsize),
.M_AXI_AWBURST (m_axi_awburst),
.M_AXI_AWLOCK (m_axi_awlock),
.M_AXI_AWCACHE (m_axi_awcache),
.M_AXI_AWPROT (m_axi_awprot),
.M_AXI_AWREGION (m_axi_awregion),
.M_AXI_AWQOS (m_axi_awqos),
.M_AXI_AWVALID (m_axi_awvalid),
.M_AXI_AWREADY (m_axi_awready),
// Slave Interface Write Data Ports
.S_AXI_WDATA (s_axi_wdata),
.S_AXI_WSTRB (s_axi_wstrb),
.S_AXI_WLAST (s_axi_wlast),
.S_AXI_WVALID (s_axi_wvalid),
.S_AXI_WREADY (s_axi_wready),
// Master Interface Write Data Ports
.M_AXI_WDATA (m_axi_wdata),
.M_AXI_WSTRB (m_axi_wstrb),
.M_AXI_WLAST (m_axi_wlast),
.M_AXI_WVALID (m_axi_wvalid),
.M_AXI_WREADY (m_axi_wready),
.SAMPLE_CYCLE (sample_cycle),
.SAMPLE_CYCLE_EARLY (sample_cycle_early)
);
end else begin : gen_non_fifo_w_upsizer
// Write Data channel.
axi_dwidth_converter_v2_1_w_upsizer #
(
.C_FAMILY ("rtl"),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_M_AXI_REGISTER (1),
.C_PACKING_LEVEL (C_PACKING_LEVEL),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO (C_RATIO),
.C_RATIO_LOG (C_RATIO_LOG)
) write_data_inst
(
// Global Signals
.ARESET (~s_aresetn_i),
.ACLK (aclk),
// Command Interface
.cmd_valid (wr_cmd_valid),
.cmd_fix (wr_cmd_fix),
.cmd_modified (wr_cmd_modified),
.cmd_complete_wrap (wr_cmd_complete_wrap),
.cmd_packed_wrap (wr_cmd_packed_wrap),
.cmd_first_word (wr_cmd_first_word),
.cmd_next_word (wr_cmd_next_word),
.cmd_last_word (wr_cmd_last_word),
.cmd_offset (wr_cmd_offset),
.cmd_mask (wr_cmd_mask),
.cmd_step (wr_cmd_step),
.cmd_length (wr_cmd_length),
.cmd_ready (wr_cmd_ready),
// Slave Interface Write Data Ports
.S_AXI_WDATA (s_axi_wdata),
.S_AXI_WSTRB (s_axi_wstrb),
.S_AXI_WLAST (s_axi_wlast),
.S_AXI_WVALID (s_axi_wvalid),
.S_AXI_WREADY (s_axi_wready),
// Master Interface Write Data Ports
.M_AXI_WDATA (m_axi_wdata),
.M_AXI_WSTRB (m_axi_wstrb),
.M_AXI_WLAST (m_axi_wlast),
.M_AXI_WVALID (m_axi_wvalid),
.M_AXI_WREADY (m_axi_wready)
);
assign m_axi_awaddr = m_axi_awaddr_i ;
assign m_axi_awlen = m_axi_awlen_i ;
assign m_axi_awsize = m_axi_awsize_i ;
assign m_axi_awburst = m_axi_awburst_i ;
assign m_axi_awlock = m_axi_awlock_i ;
assign m_axi_awcache = m_axi_awcache_i ;
assign m_axi_awprot = m_axi_awprot_i ;
assign m_axi_awregion = m_axi_awregion_i ;
assign m_axi_awqos = m_axi_awqos_i ;
assign m_axi_awvalid = m_axi_awvalid_i ;
assign m_axi_awready_i = m_axi_awready ;
end // gen_w_upsizer
// Write Response channel.
assign wr_cmd_id_ready = s_axi_bvalid_i & s_axi_bready;
assign s_axi_bid = wr_cmd_id;
assign s_axi_bresp = s_axi_bresp_i;
assign s_axi_bvalid = s_axi_bvalid_i;
if (P_CLK_CONV) begin : gen_b_clk_conv
if (C_AXI_IS_ACLK_ASYNC == 0) begin : gen_b_sync_conv
axi_clock_converter_v2_1_axic_sync_clock_converter #(
.C_FAMILY ( C_FAMILY ) ,
.C_PAYLOAD_WIDTH ( 2 ) ,
.C_M_ACLK_RATIO ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,
.C_S_ACLK_RATIO ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,
.C_MODE(P_CONV_LIGHT_WT)
)
b_sync_clock_converter (
.SAMPLE_CYCLE (sample_cycle),
.SAMPLE_CYCLE_EARLY (sample_cycle_early),
.S_ACLK ( m_axi_aclk ) ,
.S_ARESETN ( m_axi_aresetn ) ,
.S_PAYLOAD ( m_axi_bresp ) ,
.S_VALID ( m_axi_bvalid ) ,
.S_READY ( m_axi_bready ) ,
.M_ACLK ( s_axi_aclk ) ,
.M_ARESETN ( s_axi_aresetn ) ,
.M_PAYLOAD ( s_axi_bresp_i ) ,
.M_VALID ( s_axi_bvalid_i ) ,
.M_READY ( s_axi_bready )
);
end else begin : gen_b_async_conv
fifo_generator_v12_0 #(
.C_COMMON_CLOCK(0),
.C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),
.C_INTERFACE_TYPE(2),
.C_AXI_TYPE(1),
.C_HAS_AXI_ID(1),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(2),
.C_DIN_WIDTH_WACH(63),
.C_DIN_WIDTH_WDCH(38),
.C_DIN_WIDTH_WRCH(3),
.C_DIN_WIDTH_RACH(63),
.C_DIN_WIDTH_RDCH(36),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(10),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(18),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(18),
.C_ENABLE_RLOCS(0),
.C_FAMILY(C_FAMILY),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("4kx4"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(1022),
.C_PROG_FULL_THRESH_NEGATE_VAL(1021),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(10),
.C_RD_DEPTH(1024),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(10),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(10),
.C_WR_DEPTH(1024),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(10),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_HAS_AXI_WR_CHANNEL(1),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TKEEP_WIDTH(4),
.C_WACH_TYPE(2),
.C_WDCH_TYPE(2),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_AXIS_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(12),
.C_IMPLEMENTATION_TYPE_WDCH(11),
.C_IMPLEMENTATION_TYPE_WRCH(12),
.C_IMPLEMENTATION_TYPE_RACH(12),
.C_IMPLEMENTATION_TYPE_RDCH(11),
.C_IMPLEMENTATION_TYPE_AXIS(11),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(32),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(5),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(31),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(13),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1021),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(29),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(13),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1021),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1021),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0)
) dw_fifogen_b_async (
.m_aclk(m_axi_aclk),
.s_aclk(s_axi_aclk),
.s_aresetn(sm_aresetn),
.s_axi_awid(1'b0),
.s_axi_awaddr(32'b0),
.s_axi_awlen(8'b0),
.s_axi_awsize(3'b0),
.s_axi_awburst(2'b0),
.s_axi_awlock(2'b0),
.s_axi_awcache(4'b0),
.s_axi_awprot(3'b0),
.s_axi_awqos(4'b0),
.s_axi_awregion(4'b0),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_awready(),
.s_axi_wid(1'b0),
.s_axi_wdata(32'b0),
.s_axi_wstrb(4'b0),
.s_axi_wlast(1'b0),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp_i),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid_i),
.s_axi_bready(s_axi_bready),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'b0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axi_wready(1'b0),
.m_axi_bid(1'b0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'b0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.s_axi_arid(1'b0),
.s_axi_araddr(32'b0),
.s_axi_arlen(8'b0),
.s_axi_arsize(3'b0),
.s_axi_arburst(2'b0),
.s_axi_arlock(2'b0),
.s_axi_arcache(4'b0),
.s_axi_arprot(3'b0),
.s_axi_arqos(4'b0),
.s_axi_arregion(4'b0),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'b0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'b0),
.m_axi_rid(1'b0),
.m_axi_rdata(32'b0),
.m_axi_rresp(2'b0),
.m_axi_rlast(1'b0),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_rready(),
.m_aclk_en(1'b0),
.s_aclk_en(1'b0),
.backup(1'b0),
.backup_marker(1'b0),
.clk(1'b0),
.rst(1'b0),
.srst(1'b0),
.wr_clk(1'b0),
.wr_rst(1'b0),
.rd_clk(1'b0),
.rd_rst(1'b0),
.din(18'b0),
.wr_en(1'b0),
.rd_en(1'b0),
.prog_empty_thresh(10'b0),
.prog_empty_thresh_assert(10'b0),
.prog_empty_thresh_negate(10'b0),
.prog_full_thresh(10'b0),
.prog_full_thresh_assert(10'b0),
.prog_full_thresh_negate(10'b0),
.int_clk(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.dout(),
.full(),
.almost_full(),
.wr_ack(),
.overflow(),
.empty(),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(),
.wr_data_count(),
.prog_full(),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.s_axis_tvalid(1'b0),
.s_axis_tready(),
.s_axis_tdata(64'b0),
.s_axis_tstrb(4'b0),
.s_axis_tkeep(4'b0),
.s_axis_tlast(1'b0),
.s_axis_tid(8'b0),
.s_axis_tdest(4'b0),
.s_axis_tuser(4'b0),
.m_axis_tvalid(),
.m_axis_tready(1'b0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_prog_full_thresh(4'b0),
.axi_aw_prog_empty_thresh(4'b0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'b0),
.axi_w_injectdbiterr(1'b0),
.axi_w_prog_full_thresh(10'b0),
.axi_w_prog_empty_thresh(10'b0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_b_injectsbiterr(1'b0),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectdbiterr(1'b0),
.axi_b_prog_full_thresh(5'b0),
.axi_b_prog_empty_thresh(5'b0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_ar_injectsbiterr(1'b0),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_prog_full_thresh(4'b0),
.axi_ar_prog_empty_thresh(4'b0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'b0),
.axi_r_injectdbiterr(1'b0),
.axi_r_prog_full_thresh(10'b0),
.axi_r_prog_empty_thresh(10'b0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axis_injectsbiterr(1'b0),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectdbiterr(1'b0),
.axis_prog_full_thresh(10'b0),
.axis_prog_empty_thresh(10'b0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty(),
.wr_rst_busy(),
.rd_rst_busy(),
.sleep(1'b0)
);
end
end else begin : gen_b_passthru
assign m_axi_bready = s_axi_bready;
assign s_axi_bresp_i = m_axi_bresp;
assign s_axi_bvalid_i = m_axi_bvalid;
end // gen_b
end else begin : NO_WRITE
assign sr_awready = 1'b0;
assign s_axi_wready = 1'b0;
assign s_axi_bid = {C_S_AXI_ID_WIDTH{1'b0}};
assign s_axi_bresp = 2'b0;
assign s_axi_bvalid = 1'b0;
assign m_axi_awaddr = {C_AXI_ADDR_WIDTH{1'b0}};
assign m_axi_awlen = 8'b0;
assign m_axi_awsize = 3'b0;
assign m_axi_awburst = 2'b0;
assign m_axi_awlock = 2'b0;
assign m_axi_awcache = 4'b0;
assign m_axi_awprot = 3'b0;
assign m_axi_awregion = 4'b0;
assign m_axi_awqos = 4'b0;
assign m_axi_awvalid = 1'b0;
assign m_axi_wdata = {C_M_AXI_DATA_WIDTH{1'b0}};
assign m_axi_wstrb = {C_M_AXI_DATA_WIDTH/8{1'b0}};
assign m_axi_wlast = 1'b0;
assign m_axi_wvalid = 1'b0;
assign m_axi_bready = 1'b0;
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
generate
if (C_AXI_SUPPORTS_READ == 1) begin : USE_READ
wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr_i ;
wire [8-1:0] m_axi_arlen_i ;
wire [3-1:0] m_axi_arsize_i ;
wire [2-1:0] m_axi_arburst_i ;
wire [2-1:0] m_axi_arlock_i ;
wire [4-1:0] m_axi_arcache_i ;
wire [3-1:0] m_axi_arprot_i ;
wire [4-1:0] m_axi_arregion_i ;
wire [4-1:0] m_axi_arqos_i ;
wire m_axi_arvalid_i ;
wire m_axi_arready_i ;
// Read Channel Signals for Commands Queue Interface.
wire rd_cmd_valid;
wire rd_cmd_fix;
wire rd_cmd_modified;
wire rd_cmd_complete_wrap;
wire rd_cmd_packed_wrap;
wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_first_word;
wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_next_word;
wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_last_word;
wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_offset;
wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_mask;
wire [C_S_AXI_BYTES_LOG:0] rd_cmd_step;
wire [8-1:0] rd_cmd_length;
wire rd_cmd_ready;
wire [C_S_AXI_ID_WIDTH-1:0] rd_cmd_id;
wire [C_AXI_ADDR_WIDTH-1:0] rd_cmd_si_addr;
wire [C_S_AXI_ID_WIDTH-1:0] rd_cmd_si_id;
wire [8-1:0] rd_cmd_si_len;
wire [3-1:0] rd_cmd_si_size;
wire [2-1:0] rd_cmd_si_burst;
// Read Address Channel.
axi_dwidth_converter_v2_1_a_upsizer #
(
.C_FAMILY ("rtl"),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_SUPPORTS_ID (C_SUPPORTS_ID),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_M_AXI_REGISTER (C_M_AXI_AR_REGISTER),
.C_AXI_CHANNEL (1),
.C_PACKING_LEVEL (C_PACKING_LEVEL),
// .C_FIFO_MODE (0),
.C_FIFO_MODE (C_FIFO_MODE),
.C_ID_QUEUE (P_RID_QUEUE),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG)
) read_addr_inst
(
// Global Signals
.ARESET (~s_aresetn_i),
.ACLK (aclk),
// Command Interface
.cmd_valid (rd_cmd_valid),
.cmd_fix (rd_cmd_fix),
.cmd_modified (rd_cmd_modified),
.cmd_complete_wrap (rd_cmd_complete_wrap),
.cmd_packed_wrap (rd_cmd_packed_wrap),
.cmd_first_word (rd_cmd_first_word),
.cmd_next_word (rd_cmd_next_word),
.cmd_last_word (rd_cmd_last_word),
.cmd_offset (rd_cmd_offset),
.cmd_mask (rd_cmd_mask),
.cmd_step (rd_cmd_step),
.cmd_length (rd_cmd_length),
.cmd_ready (rd_cmd_ready),
.cmd_id_ready (rd_cmd_ready),
.cmd_id (rd_cmd_id),
.cmd_si_addr (rd_cmd_si_addr ),
.cmd_si_id (rd_cmd_si_id ),
.cmd_si_len (rd_cmd_si_len ),
.cmd_si_size (rd_cmd_si_size ),
.cmd_si_burst (rd_cmd_si_burst),
// Slave Interface Write Address Ports
.S_AXI_AID (sr_arid),
.S_AXI_AADDR (sr_araddr),
.S_AXI_ALEN (sr_arlen),
.S_AXI_ASIZE (sr_arsize),
.S_AXI_ABURST (sr_arburst),
.S_AXI_ALOCK (sr_arlock),
.S_AXI_ACACHE (sr_arcache),
.S_AXI_APROT (sr_arprot),
.S_AXI_AREGION (sr_arregion),
.S_AXI_AQOS (sr_arqos),
.S_AXI_AVALID (sr_arvalid),
.S_AXI_AREADY (sr_arready),
// Master Interface Write Address Port
.M_AXI_AADDR (m_axi_araddr_i ),
.M_AXI_ALEN (m_axi_arlen_i ),
.M_AXI_ASIZE (m_axi_arsize_i ),
.M_AXI_ABURST (m_axi_arburst_i ),
.M_AXI_ALOCK (m_axi_arlock_i ),
.M_AXI_ACACHE (m_axi_arcache_i ),
.M_AXI_APROT (m_axi_arprot_i ),
.M_AXI_AREGION (m_axi_arregion_i ),
.M_AXI_AQOS (m_axi_arqos_i ),
.M_AXI_AVALID (m_axi_arvalid_i ),
.M_AXI_AREADY (m_axi_arready_i )
);
if ((C_FIFO_MODE == P_PKTFIFO) || (C_FIFO_MODE == P_PKTFIFO_CLK)) begin : gen_pktfifo_r_upsizer
// Packet FIFO Read Data channel.
axi_dwidth_converter_v2_1_r_upsizer_pktfifo #
(
.C_FAMILY (C_FAMILY),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO (C_RATIO),
.C_RATIO_LOG (C_RATIO_LOG),
.C_CLK_CONV (P_CLK_CONV),
.C_S_AXI_ACLK_RATIO (C_S_AXI_ACLK_RATIO),
.C_M_AXI_ACLK_RATIO (C_M_AXI_ACLK_RATIO),
.C_AXI_IS_ACLK_ASYNC (C_AXI_IS_ACLK_ASYNC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE)
) pktfifo_read_data_inst
(
.S_AXI_ARESETN ( s_axi_aresetn ) ,
.S_AXI_ACLK ( s_axi_aclk ) ,
.M_AXI_ARESETN ( m_axi_aresetn ) ,
.M_AXI_ACLK ( m_axi_aclk ) ,
// Command Interface
.cmd_si_addr (rd_cmd_si_addr ),
.cmd_si_id (rd_cmd_si_id ),
.cmd_si_len (rd_cmd_si_len ),
.cmd_si_size (rd_cmd_si_size ),
.cmd_si_burst (rd_cmd_si_burst),
.cmd_ready (rd_cmd_ready),
// Slave Interface Write Address Ports
.S_AXI_ARADDR (m_axi_araddr_i ),
.S_AXI_ARLEN (m_axi_arlen_i ),
.S_AXI_ARSIZE (m_axi_arsize_i ),
.S_AXI_ARBURST (m_axi_arburst_i ),
.S_AXI_ARLOCK (m_axi_arlock_i ),
.S_AXI_ARCACHE (m_axi_arcache_i ),
.S_AXI_ARPROT (m_axi_arprot_i ),
.S_AXI_ARREGION (m_axi_arregion_i ),
.S_AXI_ARQOS (m_axi_arqos_i ),
.S_AXI_ARVALID (m_axi_arvalid_i ),
.S_AXI_ARREADY (m_axi_arready_i ),
// Master Interface Write Address Port
.M_AXI_ARADDR (m_axi_araddr),
.M_AXI_ARLEN (m_axi_arlen),
.M_AXI_ARSIZE (m_axi_arsize),
.M_AXI_ARBURST (m_axi_arburst),
.M_AXI_ARLOCK (m_axi_arlock),
.M_AXI_ARCACHE (m_axi_arcache),
.M_AXI_ARPROT (m_axi_arprot),
.M_AXI_ARREGION (m_axi_arregion),
.M_AXI_ARQOS (m_axi_arqos),
.M_AXI_ARVALID (m_axi_arvalid),
.M_AXI_ARREADY (m_axi_arready),
// Slave Interface Write Data Ports
.S_AXI_RID (s_axi_rid),
.S_AXI_RDATA (s_axi_rdata),
.S_AXI_RRESP (s_axi_rresp),
.S_AXI_RLAST (s_axi_rlast),
.S_AXI_RVALID (s_axi_rvalid),
.S_AXI_RREADY (s_axi_rready),
// Master Interface Write Data Ports
.M_AXI_RDATA (m_axi_rdata),
.M_AXI_RRESP (m_axi_rresp),
.M_AXI_RLAST (m_axi_rlast),
.M_AXI_RVALID (m_axi_rvalid),
.M_AXI_RREADY (m_axi_rready),
.SAMPLE_CYCLE (sample_cycle),
.SAMPLE_CYCLE_EARLY (sample_cycle_early)
);
end else begin : gen_non_fifo_r_upsizer
// Read Data channel.
axi_dwidth_converter_v2_1_r_upsizer #
(
.C_FAMILY ("rtl"),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_S_AXI_REGISTER (C_S_AXI_R_REGISTER),
.C_PACKING_LEVEL (C_PACKING_LEVEL),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO (C_RATIO),
.C_RATIO_LOG (C_RATIO_LOG)
) read_data_inst
(
// Global Signals
.ARESET (~s_aresetn_i),
.ACLK (aclk),
// Command Interface
.cmd_valid (rd_cmd_valid),
.cmd_fix (rd_cmd_fix),
.cmd_modified (rd_cmd_modified),
.cmd_complete_wrap (rd_cmd_complete_wrap),
.cmd_packed_wrap (rd_cmd_packed_wrap),
.cmd_first_word (rd_cmd_first_word),
.cmd_next_word (rd_cmd_next_word),
.cmd_last_word (rd_cmd_last_word),
.cmd_offset (rd_cmd_offset),
.cmd_mask (rd_cmd_mask),
.cmd_step (rd_cmd_step),
.cmd_length (rd_cmd_length),
.cmd_ready (rd_cmd_ready),
.cmd_id (rd_cmd_id),
// Slave Interface Read Data Ports
.S_AXI_RID (s_axi_rid),
.S_AXI_RDATA (s_axi_rdata),
.S_AXI_RRESP (s_axi_rresp),
.S_AXI_RLAST (s_axi_rlast),
.S_AXI_RVALID (s_axi_rvalid),
.S_AXI_RREADY (s_axi_rready),
// Master Interface Read Data Ports
.M_AXI_RDATA (mr_rdata),
.M_AXI_RRESP (mr_rresp),
.M_AXI_RLAST (mr_rlast),
.M_AXI_RVALID (mr_rvalid),
.M_AXI_RREADY (mr_rready)
);
axi_register_slice_v2_1_axi_register_slice #
(
.C_FAMILY (C_FAMILY),
.C_AXI_PROTOCOL (0),
.C_AXI_ID_WIDTH (1),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_USER_SIGNALS (0),
.C_REG_CONFIG_R (C_M_AXI_R_REGISTER)
)
mi_register_slice_inst
(
.aresetn (s_aresetn_i),
.aclk (m_aclk),
.s_axi_awid ( 1'b0 ),
.s_axi_awaddr ( {C_AXI_ADDR_WIDTH{1'b0}} ),
.s_axi_awlen ( 8'b0 ),
.s_axi_awsize ( 3'b0 ),
.s_axi_awburst ( 2'b0 ),
.s_axi_awlock ( 1'b0 ),
.s_axi_awcache ( 4'b0 ),
.s_axi_awprot ( 3'b0 ),
.s_axi_awregion ( 4'b0 ),
.s_axi_awqos ( 4'b0 ),
.s_axi_awuser ( 1'b0 ),
.s_axi_awvalid ( 1'b0 ),
.s_axi_awready ( ),
.s_axi_wid ( 1'b0 ),
.s_axi_wdata ( {C_M_AXI_DATA_WIDTH{1'b0}} ),
.s_axi_wstrb ( {C_M_AXI_DATA_WIDTH/8{1'b0}} ),
.s_axi_wlast ( 1'b0 ),
.s_axi_wuser ( 1'b0 ),
.s_axi_wvalid ( 1'b0 ),
.s_axi_wready ( ),
.s_axi_bid ( ),
.s_axi_bresp ( ),
.s_axi_buser ( ),
.s_axi_bvalid ( ),
.s_axi_bready ( 1'b0 ),
.s_axi_arid ( 1'b0 ),
.s_axi_araddr ( {C_AXI_ADDR_WIDTH{1'b0}} ),
.s_axi_arlen ( 8'b0 ),
.s_axi_arsize ( 3'b0 ),
.s_axi_arburst ( 2'b0 ),
.s_axi_arlock ( 1'b0 ),
.s_axi_arcache ( 4'b0 ),
.s_axi_arprot ( 3'b0 ),
.s_axi_arregion ( 4'b0 ),
.s_axi_arqos ( 4'b0 ),
.s_axi_aruser ( 1'b0 ),
.s_axi_arvalid ( 1'b0 ),
.s_axi_arready ( ),
.s_axi_rid (),
.s_axi_rdata (mr_rdata ),
.s_axi_rresp (mr_rresp ),
.s_axi_rlast (mr_rlast ),
.s_axi_ruser (),
.s_axi_rvalid (mr_rvalid ),
.s_axi_rready (mr_rready ),
.m_axi_awid (),
.m_axi_awaddr (),
.m_axi_awlen (),
.m_axi_awsize (),
.m_axi_awburst (),
.m_axi_awlock (),
.m_axi_awcache (),
.m_axi_awprot (),
.m_axi_awregion (),
.m_axi_awqos (),
.m_axi_awuser (),
.m_axi_awvalid (),
.m_axi_awready (1'b0),
.m_axi_wid () ,
.m_axi_wdata (),
.m_axi_wstrb (),
.m_axi_wlast (),
.m_axi_wuser (),
.m_axi_wvalid (),
.m_axi_wready (1'b0),
.m_axi_bid ( 1'b0 ) ,
.m_axi_bresp ( 2'b0 ) ,
.m_axi_buser ( 1'b0 ) ,
.m_axi_bvalid ( 1'b0 ) ,
.m_axi_bready ( ) ,
.m_axi_arid (),
.m_axi_araddr (),
.m_axi_arlen (),
.m_axi_arsize (),
.m_axi_arburst (),
.m_axi_arlock (),
.m_axi_arcache (),
.m_axi_arprot (),
.m_axi_arregion (),
.m_axi_arqos (),
.m_axi_aruser (),
.m_axi_arvalid (),
.m_axi_arready (1'b0),
.m_axi_rid (1'b0 ),
.m_axi_rdata (m_axi_rdata ),
.m_axi_rresp (m_axi_rresp ),
.m_axi_rlast (m_axi_rlast ),
.m_axi_ruser (1'b0 ),
.m_axi_rvalid (m_axi_rvalid ),
.m_axi_rready (m_axi_rready_i )
);
assign m_axi_araddr = m_axi_araddr_i ;
assign m_axi_arlen = m_axi_arlen_i ;
assign m_axi_arsize = m_axi_arsize_i ;
assign m_axi_arburst = m_axi_arburst_i ;
assign m_axi_arlock = m_axi_arlock_i ;
assign m_axi_arcache = m_axi_arcache_i ;
assign m_axi_arprot = m_axi_arprot_i ;
assign m_axi_arregion = m_axi_arregion_i ;
assign m_axi_arqos = m_axi_arqos_i ;
assign m_axi_arvalid = m_axi_arvalid_i ;
assign m_axi_arready_i = m_axi_arready ;
assign m_axi_rready = m_axi_rready_i;
end // gen_r_upsizer
end else begin : NO_READ
assign sr_arready = 1'b0;
assign s_axi_rid = {C_S_AXI_ID_WIDTH{1'b0}};
assign s_axi_rdata = {C_S_AXI_DATA_WIDTH{1'b0}};
assign s_axi_rresp = 2'b0;
assign s_axi_rlast = 1'b0;
assign s_axi_rvalid = 1'b0;
assign m_axi_araddr = {C_AXI_ADDR_WIDTH{1'b0}};
assign m_axi_arlen = 8'b0;
assign m_axi_arsize = 3'b0;
assign m_axi_arburst = 2'b0;
assign m_axi_arlock = 2'b0;
assign m_axi_arcache = 4'b0;
assign m_axi_arprot = 3'b0;
assign m_axi_arregion = 4'b0;
assign m_axi_arqos = 4'b0;
assign m_axi_arvalid = 1'b0;
assign mr_rready = 1'b0;
end
endgenerate
endmodule
`default_nettype wire
|
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7_bfm:2.0
// IP Revision: 1
`timescale 1ns/1ps
module system_processing_system7_0_0 (
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
IRQ_F2P,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1 : 0] USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11 : 0] M_AXI_GP0_ARID;
output [11 : 0] M_AXI_GP0_AWID;
output [11 : 0] M_AXI_GP0_WID;
output [1 : 0] M_AXI_GP0_ARBURST;
output [1 : 0] M_AXI_GP0_ARLOCK;
output [2 : 0] M_AXI_GP0_ARSIZE;
output [1 : 0] M_AXI_GP0_AWBURST;
output [1 : 0] M_AXI_GP0_AWLOCK;
output [2 : 0] M_AXI_GP0_AWSIZE;
output [2 : 0] M_AXI_GP0_ARPROT;
output [2 : 0] M_AXI_GP0_AWPROT;
output [31 : 0] M_AXI_GP0_ARADDR;
output [31 : 0] M_AXI_GP0_AWADDR;
output [31 : 0] M_AXI_GP0_WDATA;
output [3 : 0] M_AXI_GP0_ARCACHE;
output [3 : 0] M_AXI_GP0_ARLEN;
output [3 : 0] M_AXI_GP0_ARQOS;
output [3 : 0] M_AXI_GP0_AWCACHE;
output [3 : 0] M_AXI_GP0_AWLEN;
output [3 : 0] M_AXI_GP0_AWQOS;
output [3 : 0] M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11 : 0] M_AXI_GP0_BID;
input [11 : 0] M_AXI_GP0_RID;
input [1 : 0] M_AXI_GP0_BRESP;
input [1 : 0] M_AXI_GP0_RRESP;
input [31 : 0] M_AXI_GP0_RDATA;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1 : 0] S_AXI_HP0_BRESP;
output [1 : 0] S_AXI_HP0_RRESP;
output [5 : 0] S_AXI_HP0_BID;
output [5 : 0] S_AXI_HP0_RID;
output [63 : 0] S_AXI_HP0_RDATA;
output [7 : 0] S_AXI_HP0_RCOUNT;
output [7 : 0] S_AXI_HP0_WCOUNT;
output [2 : 0] S_AXI_HP0_RACOUNT;
output [5 : 0] S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1 : 0] S_AXI_HP0_ARBURST;
input [1 : 0] S_AXI_HP0_ARLOCK;
input [2 : 0] S_AXI_HP0_ARSIZE;
input [1 : 0] S_AXI_HP0_AWBURST;
input [1 : 0] S_AXI_HP0_AWLOCK;
input [2 : 0] S_AXI_HP0_AWSIZE;
input [2 : 0] S_AXI_HP0_ARPROT;
input [2 : 0] S_AXI_HP0_AWPROT;
input [31 : 0] S_AXI_HP0_ARADDR;
input [31 : 0] S_AXI_HP0_AWADDR;
input [3 : 0] S_AXI_HP0_ARCACHE;
input [3 : 0] S_AXI_HP0_ARLEN;
input [3 : 0] S_AXI_HP0_ARQOS;
input [3 : 0] S_AXI_HP0_AWCACHE;
input [3 : 0] S_AXI_HP0_AWLEN;
input [3 : 0] S_AXI_HP0_AWQOS;
input [5 : 0] S_AXI_HP0_ARID;
input [5 : 0] S_AXI_HP0_AWID;
input [5 : 0] S_AXI_HP0_WID;
input [63 : 0] S_AXI_HP0_WDATA;
input [7 : 0] S_AXI_HP0_WSTRB;
input [1 : 0] IRQ_F2P;
output FCLK_CLK0;
output FCLK_RESET0_N;
input [53 : 0] MIO;
input DDR_CAS_n;
input DDR_CKE;
input DDR_Clk_n;
input DDR_Clk;
input DDR_CS_n;
input DDR_DRSTB;
input DDR_ODT;
input DDR_RAS_n;
input DDR_WEB;
input [2 : 0] DDR_BankAddr;
input [14 : 0] DDR_Addr;
input DDR_VRN;
input DDR_VRP;
input [3 : 0] DDR_DM;
input [31 : 0] DDR_DQ;
input [3 : 0] DDR_DQS_n;
input [3 : 0] DDR_DQS;
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
processing_system7_bfm_v2_0_5_processing_system7_bfm #(
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_ACP(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_GP1(0),
.C_USE_S_AXI_HP0(1),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_HIGH_OCM_EN(0),
.C_FCLK_CLK0_FREQ(100.0),
.C_FCLK_CLK1_FREQ(10.0),
.C_FCLK_CLK2_FREQ(10.0),
.C_FCLK_CLK3_FREQ(10.0),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
) inst (
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(S_AXI_HP0_ARREADY),
.S_AXI_HP0_AWREADY(S_AXI_HP0_AWREADY),
.S_AXI_HP0_BVALID(S_AXI_HP0_BVALID),
.S_AXI_HP0_RLAST(S_AXI_HP0_RLAST),
.S_AXI_HP0_RVALID(S_AXI_HP0_RVALID),
.S_AXI_HP0_WREADY(S_AXI_HP0_WREADY),
.S_AXI_HP0_BRESP(S_AXI_HP0_BRESP),
.S_AXI_HP0_RRESP(S_AXI_HP0_RRESP),
.S_AXI_HP0_BID(S_AXI_HP0_BID),
.S_AXI_HP0_RID(S_AXI_HP0_RID),
.S_AXI_HP0_RDATA(S_AXI_HP0_RDATA),
.S_AXI_HP0_ACLK(S_AXI_HP0_ACLK),
.S_AXI_HP0_ARVALID(S_AXI_HP0_ARVALID),
.S_AXI_HP0_AWVALID(S_AXI_HP0_AWVALID),
.S_AXI_HP0_BREADY(S_AXI_HP0_BREADY),
.S_AXI_HP0_RREADY(S_AXI_HP0_RREADY),
.S_AXI_HP0_WLAST(S_AXI_HP0_WLAST),
.S_AXI_HP0_WVALID(S_AXI_HP0_WVALID),
.S_AXI_HP0_ARBURST(S_AXI_HP0_ARBURST),
.S_AXI_HP0_ARLOCK(S_AXI_HP0_ARLOCK),
.S_AXI_HP0_ARSIZE(S_AXI_HP0_ARSIZE),
.S_AXI_HP0_AWBURST(S_AXI_HP0_AWBURST),
.S_AXI_HP0_AWLOCK(S_AXI_HP0_AWLOCK),
.S_AXI_HP0_AWSIZE(S_AXI_HP0_AWSIZE),
.S_AXI_HP0_ARPROT(S_AXI_HP0_ARPROT),
.S_AXI_HP0_AWPROT(S_AXI_HP0_AWPROT),
.S_AXI_HP0_ARADDR(S_AXI_HP0_ARADDR),
.S_AXI_HP0_AWADDR(S_AXI_HP0_AWADDR),
.S_AXI_HP0_ARCACHE(S_AXI_HP0_ARCACHE),
.S_AXI_HP0_ARLEN(S_AXI_HP0_ARLEN),
.S_AXI_HP0_ARQOS(S_AXI_HP0_ARQOS),
.S_AXI_HP0_AWCACHE(S_AXI_HP0_AWCACHE),
.S_AXI_HP0_AWLEN(S_AXI_HP0_AWLEN),
.S_AXI_HP0_AWQOS(S_AXI_HP0_AWQOS),
.S_AXI_HP0_ARID(S_AXI_HP0_ARID),
.S_AXI_HP0_AWID(S_AXI_HP0_AWID),
.S_AXI_HP0_WID(S_AXI_HP0_WID),
.S_AXI_HP0_WDATA(S_AXI_HP0_WDATA),
.S_AXI_HP0_WSTRB(S_AXI_HP0_WSTRB),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.IRQ_F2P(IRQ_F2P),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
//==================================================================================================
// Filename : tb_CORDIC_Arch3.v
// Created On : 2016-10-03 23:39:40
// Last Modified : 2016-10-05 14:22:11
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
//==================================================================================================
// Filename : testbench_CORDICArch2.v
// Created On : 2016-10-03 23:33:09
// Last Modified : 2016-10-03 23:33:09
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
`timescale 1ns/1ps
module testbench_CORDIC_Arch3 (); /* this is automatically generated */
parameter PERIOD = 10;
//ESTAS SON DEFINICIONES QUE SE REALIZAN EN LOS COMANDOS O CONFIGURACIONES
//DEL SIMULADOR O EL SINTETIZADOR
`ifdef SINGLE
parameter W = 32;
parameter EW = 8;
parameter SW = 23;
parameter SWR = 26;
parameter EWR = 5;
`endif
`ifdef DOUBLE
parameter W = 64;
parameter EW = 11;
parameter SW = 52;
parameter SWR = 55;
parameter EWR = 6;
`endif
reg clk; // Reloj del sistema.
reg rst; // SeΓ±al de reset del sistema.
reg beg_fsm_cordic; // SeΓ±al de inicio de la maquina de estados del mΓ³dulo CORDIC.
reg ack_cordic; // SeΓ±al de acknowledge proveniente de otro mΓ³dulo que indica que ha recibido el resultado del modulo CORDIC.
reg operation; // SeΓ±al que indica si se realiza la operacion seno(1'b1) o coseno(1'b0).
//reg [1:0] r_mode;
reg [W-1:0] data_in; // Dato de entrada, contiene el angulo que se desea calcular en radianes.
reg [1:0] shift_region_flag; // SeΓ±al que indica si el Γ‘ngulo a calcular esta fuera del rango de calculo del algoritmo CORDIC.
//Output Signals
wire ready_cordic; // SeΓ±al de salida que indica que se ha completado el calculo del seno/coseno.
wire [W-1:0] data_output; // Bus de datos con el valor final del angulo calculado.
wire overflow_flag; // Bandera de overflow de la operacion.
wire underflow_flag; // Bandera de underflow de la operacion.
wire zero_flag;
wire busy;
CORDIC_Arch3 #(.W(W),.EW(EW),.SW(SW),.SWR(SWR),.EWR(EWR)) inst_CORDIC_Arch3
(
.clk (clk),
.rst (rst),
.beg_fsm_cordic (beg_fsm_cordic),
.ack_cordic (ack_cordic),
.operation (operation),
.data_in (data_in),
.shift_region_flag (shift_region_flag),
.ready_cordic (ready_cordic),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.zero_flag (zero_flag),
.busy (busy),
.data_output (data_output)
);
reg [W-1:0] Array_IN [0:((2**PERIOD)-1)];
//reg [W-1:0] Array_IN_2 [0:((2**PERIOD)-1)];
integer contador;
integer FileSaveData;
integer Cont_CLK;
integer Recept;
initial begin
clk = 0;
beg_fsm_cordic = 0;
ack_cordic = 0;
operation = 0;
data_in = 32'h00000000;
shift_region_flag = 2'b00;
rst = 1;
//Depending upong the sumulator, this directive will
//understand that if the macro is defined (e.g. RMODE00)
//then the following code will be added to the compilation
//simulation or sinthesis.
//This is added in order to simulate the accuracy change of the system.
//Abre el archivo testbench
FileSaveData = $fopen("ResultadoXilinxFLM.txt","w");
//Inicializa las variables del testbench
contador = 0;
Cont_CLK = 0;
Recept = 1;
#100 rst = 0;
// #15
// data_in = 32'h3f25514d; //37 grados
// shift_region_flag = 2'b00;
// #5
// beg_fsm_cordic = 1;
// #10
// beg_fsm_cordic = 0;
end
initial begin
`ifdef SINGLE
$readmemh("CORDIC32_input_angles_hex.txt", Array_IN);
`endif
`ifdef DOUBLE
$readmemh("CORDIC64_input_angles_hex.txt", Array_IN);
`endif
end
// clock
initial forever #5 clk = ~clk;
always @(posedge clk) begin
if(rst) begin
contador = 0;
Cont_CLK = 0;
end
else begin
if (contador == (2**PERIOD)) begin
$fclose(FileSaveData);
$finish;
end
else begin
if(Cont_CLK ==1) begin
contador = contador + 1;
beg_fsm_cordic = 0;
data_in = Array_IN[contador];
#40;
Cont_CLK = Cont_CLK + 1;
ack_cordic = 0;
#40;
end
else if(Cont_CLK ==2) begin
ack_cordic = 0;
beg_fsm_cordic = 1;
Cont_CLK = Cont_CLK +1 ;
#40;
end
else begin
ack_cordic = 0;
Cont_CLK = Cont_CLK + 1;
beg_fsm_cordic = 0;
#40;
end
if(ready_cordic==1) begin
ack_cordic = 1;
Cont_CLK = 0;
#15;
end
if(ready_cordic==1 && ack_cordic) begin
Cont_CLK = 0;
#15;
end
end
end
end
// RecepciΓ³n de datos y almacenamiento en archivo*************
always @(posedge clk) begin
if(ready_cordic) begin
if(Recept == 1) begin
$fwrite(FileSaveData,"%h\n",data_output);
Recept = 0;
end
end
else begin
Recept = 1;
end
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIeGen2x8If128_gtx_cpllpd_ovrd.v
// Version : 3.2
`timescale 1ns / 1ps
module PCIeGen2x8If128_gtx_cpllpd_ovrd (
input i_ibufds_gte2,
output o_cpllpd_ovrd,
output o_cpllreset_ovrd
);
(* equivalent_register_removal="no" *) reg [95:0] cpllpd_wait = 96'hFFFFFFFFFFFFFFFFFFFFFFFF;
(* equivalent_register_removal="no" *) reg [127:0] cpllreset_wait = 128'h000000000000000000000000000000FF;
always @(posedge i_ibufds_gte2)
begin
cpllpd_wait <= {cpllpd_wait[94:0], 1'b0};
cpllreset_wait <= {cpllreset_wait[126:0], 1'b0};
end
assign o_cpllpd_ovrd = cpllpd_wait[95];
assign o_cpllreset_ovrd = cpllreset_wait[127];
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_fmsw_gp.v
*
* Date : 2012-11
*
* Description : Mimics FMSW switch.
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_fmsw_gp(
sw_clk,
rstn,
w_qos_gp0,
r_qos_gp0,
wr_ack_ocm_gp0,
wr_ack_ddr_gp0,
wr_data_gp0,
wr_addr_gp0,
wr_bytes_gp0,
wr_dv_ocm_gp0,
wr_dv_ddr_gp0,
rd_req_ocm_gp0,
rd_req_ddr_gp0,
rd_req_reg_gp0,
rd_addr_gp0,
rd_bytes_gp0,
rd_data_ocm_gp0,
rd_data_ddr_gp0,
rd_data_reg_gp0,
rd_dv_ocm_gp0,
rd_dv_ddr_gp0,
rd_dv_reg_gp0,
w_qos_gp1,
r_qos_gp1,
wr_ack_ocm_gp1,
wr_ack_ddr_gp1,
wr_data_gp1,
wr_addr_gp1,
wr_bytes_gp1,
wr_dv_ocm_gp1,
wr_dv_ddr_gp1,
rd_req_ocm_gp1,
rd_req_ddr_gp1,
rd_req_reg_gp1,
rd_addr_gp1,
rd_bytes_gp1,
rd_data_ocm_gp1,
rd_data_ddr_gp1,
rd_data_reg_gp1,
rd_dv_ocm_gp1,
rd_dv_ddr_gp1,
rd_dv_reg_gp1,
ocm_wr_ack,
ocm_wr_dv,
ocm_rd_req,
ocm_rd_dv,
ddr_wr_ack,
ddr_wr_dv,
ddr_rd_req,
ddr_rd_dv,
reg_rd_req,
reg_rd_dv,
ocm_wr_qos,
ddr_wr_qos,
ocm_rd_qos,
ddr_rd_qos,
reg_rd_qos,
ocm_wr_addr,
ocm_wr_data,
ocm_wr_bytes,
ocm_rd_addr,
ocm_rd_data,
ocm_rd_bytes,
ddr_wr_addr,
ddr_wr_data,
ddr_wr_bytes,
ddr_rd_addr,
ddr_rd_data,
ddr_rd_bytes,
reg_rd_addr,
reg_rd_data,
reg_rd_bytes
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input sw_clk;
input rstn;
input [axi_qos_width-1:0]w_qos_gp0;
input [axi_qos_width-1:0]r_qos_gp0;
input [axi_qos_width-1:0]w_qos_gp1;
input [axi_qos_width-1:0]r_qos_gp1;
output [axi_qos_width-1:0]ocm_wr_qos;
output [axi_qos_width-1:0]ocm_rd_qos;
output [axi_qos_width-1:0]ddr_wr_qos;
output [axi_qos_width-1:0]ddr_rd_qos;
output [axi_qos_width-1:0]reg_rd_qos;
output wr_ack_ocm_gp0;
output wr_ack_ddr_gp0;
input [max_burst_bits-1:0] wr_data_gp0;
input [addr_width-1:0] wr_addr_gp0;
input [max_burst_bytes_width:0] wr_bytes_gp0;
output wr_dv_ocm_gp0;
output wr_dv_ddr_gp0;
input rd_req_ocm_gp0;
input rd_req_ddr_gp0;
input rd_req_reg_gp0;
input [addr_width-1:0] rd_addr_gp0;
input [max_burst_bytes_width:0] rd_bytes_gp0;
output [max_burst_bits-1:0] rd_data_ocm_gp0;
output [max_burst_bits-1:0] rd_data_ddr_gp0;
output [max_burst_bits-1:0] rd_data_reg_gp0;
output rd_dv_ocm_gp0;
output rd_dv_ddr_gp0;
output rd_dv_reg_gp0;
output wr_ack_ocm_gp1;
output wr_ack_ddr_gp1;
input [max_burst_bits-1:0] wr_data_gp1;
input [addr_width-1:0] wr_addr_gp1;
input [max_burst_bytes_width:0] wr_bytes_gp1;
output wr_dv_ocm_gp1;
output wr_dv_ddr_gp1;
input rd_req_ocm_gp1;
input rd_req_ddr_gp1;
input rd_req_reg_gp1;
input [addr_width-1:0] rd_addr_gp1;
input [max_burst_bytes_width:0] rd_bytes_gp1;
output [max_burst_bits-1:0] rd_data_ocm_gp1;
output [max_burst_bits-1:0] rd_data_ddr_gp1;
output [max_burst_bits-1:0] rd_data_reg_gp1;
output rd_dv_ocm_gp1;
output rd_dv_ddr_gp1;
output rd_dv_reg_gp1;
input ocm_wr_ack;
output ocm_wr_dv;
output [addr_width-1:0]ocm_wr_addr;
output [max_burst_bits-1:0]ocm_wr_data;
output [max_burst_bytes_width:0]ocm_wr_bytes;
input ocm_rd_dv;
input [max_burst_bits-1:0] ocm_rd_data;
output ocm_rd_req;
output [addr_width-1:0] ocm_rd_addr;
output [max_burst_bytes_width:0] ocm_rd_bytes;
input ddr_wr_ack;
output ddr_wr_dv;
output [addr_width-1:0]ddr_wr_addr;
output [max_burst_bits-1:0]ddr_wr_data;
output [max_burst_bytes_width:0]ddr_wr_bytes;
input ddr_rd_dv;
input [max_burst_bits-1:0] ddr_rd_data;
output ddr_rd_req;
output [addr_width-1:0] ddr_rd_addr;
output [max_burst_bytes_width:0] ddr_rd_bytes;
input reg_rd_dv;
input [max_burst_bits-1:0] reg_rd_data;
output reg_rd_req;
output [addr_width-1:0] reg_rd_addr;
output [max_burst_bytes_width:0] reg_rd_bytes;
processing_system7_bfm_v2_0_5_arb_wr ocm_gp_wr(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(w_qos_gp0),
.qos2(w_qos_gp1),
.prt_dv1(wr_dv_ocm_gp0),
.prt_dv2(wr_dv_ocm_gp1),
.prt_data1(wr_data_gp0),
.prt_data2(wr_data_gp1),
.prt_addr1(wr_addr_gp0),
.prt_addr2(wr_addr_gp1),
.prt_bytes1(wr_bytes_gp0),
.prt_bytes2(wr_bytes_gp1),
.prt_ack1(wr_ack_ocm_gp0),
.prt_ack2(wr_ack_ocm_gp1),
.prt_req(ocm_wr_dv),
.prt_qos(ocm_wr_qos),
.prt_data(ocm_wr_data),
.prt_addr(ocm_wr_addr),
.prt_bytes(ocm_wr_bytes),
.prt_ack(ocm_wr_ack)
);
processing_system7_bfm_v2_0_5_arb_wr ddr_gp_wr(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(w_qos_gp0),
.qos2(w_qos_gp1),
.prt_dv1(wr_dv_ddr_gp0),
.prt_dv2(wr_dv_ddr_gp1),
.prt_data1(wr_data_gp0),
.prt_data2(wr_data_gp1),
.prt_addr1(wr_addr_gp0),
.prt_addr2(wr_addr_gp1),
.prt_bytes1(wr_bytes_gp0),
.prt_bytes2(wr_bytes_gp1),
.prt_ack1(wr_ack_ddr_gp0),
.prt_ack2(wr_ack_ddr_gp1),
.prt_req(ddr_wr_dv),
.prt_qos(ddr_wr_qos),
.prt_data(ddr_wr_data),
.prt_addr(ddr_wr_addr),
.prt_bytes(ddr_wr_bytes),
.prt_ack(ddr_wr_ack)
);
processing_system7_bfm_v2_0_5_arb_rd ocm_gp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_gp0),
.qos2(r_qos_gp1),
.prt_req1(rd_req_ocm_gp0),
.prt_req2(rd_req_ocm_gp1),
.prt_data1(rd_data_ocm_gp0),
.prt_data2(rd_data_ocm_gp1),
.prt_addr1(rd_addr_gp0),
.prt_addr2(rd_addr_gp1),
.prt_bytes1(rd_bytes_gp0),
.prt_bytes2(rd_bytes_gp1),
.prt_dv1(rd_dv_ocm_gp0),
.prt_dv2(rd_dv_ocm_gp1),
.prt_req(ocm_rd_req),
.prt_qos(ocm_rd_qos),
.prt_data(ocm_rd_data),
.prt_addr(ocm_rd_addr),
.prt_bytes(ocm_rd_bytes),
.prt_dv(ocm_rd_dv)
);
processing_system7_bfm_v2_0_5_arb_rd ddr_gp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_gp0),
.qos2(r_qos_gp1),
.prt_req1(rd_req_ddr_gp0),
.prt_req2(rd_req_ddr_gp1),
.prt_data1(rd_data_ddr_gp0),
.prt_data2(rd_data_ddr_gp1),
.prt_addr1(rd_addr_gp0),
.prt_addr2(rd_addr_gp1),
.prt_bytes1(rd_bytes_gp0),
.prt_bytes2(rd_bytes_gp1),
.prt_dv1(rd_dv_ddr_gp0),
.prt_dv2(rd_dv_ddr_gp1),
.prt_req(ddr_rd_req),
.prt_qos(ddr_rd_qos),
.prt_data(ddr_rd_data),
.prt_addr(ddr_rd_addr),
.prt_bytes(ddr_rd_bytes),
.prt_dv(ddr_rd_dv)
);
processing_system7_bfm_v2_0_5_arb_rd reg_gp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_gp0),
.qos2(r_qos_gp1),
.prt_req1(rd_req_reg_gp0),
.prt_req2(rd_req_reg_gp1),
.prt_data1(rd_data_reg_gp0),
.prt_data2(rd_data_reg_gp1),
.prt_addr1(rd_addr_gp0),
.prt_addr2(rd_addr_gp1),
.prt_bytes1(rd_bytes_gp0),
.prt_bytes2(rd_bytes_gp1),
.prt_dv1(rd_dv_reg_gp0),
.prt_dv2(rd_dv_reg_gp1),
.prt_req(reg_rd_req),
.prt_qos(reg_rd_qos),
.prt_data(reg_rd_data),
.prt_addr(reg_rd_addr),
.prt_bytes(reg_rd_bytes),
.prt_dv(reg_rd_dv)
);
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : V5-Block Plus for PCI Express
// File : pcie_reset_logic.v
//--------------------------------------------------------------------------------
//--------------------------------------------------------------------------------
//
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 1.1
// \ \ Application : Generated by Xilinx PCI Express Wizard
// / / Filename : pcie_reset_logic.v
// /___/ /\ Module : reset_logic
// \ \ / \
// \___\/\___\
//
//------------------------------------------------------------------------------
module reset_logic
(
L0DLUPDOWN,
GSR,
CRMCORECLK,
USERCLK,
L0LTSSMSTATE,
L0STATSCFGTRANSMITTED,
CRMDOHOTRESETN,
CRMPWRSOFTRESETN,
CRMMGMTRSTN,
CRMNVRSTN,
CRMMACRSTN,
CRMLINKRSTN,
CRMURSTN,
CRMUSERCFGRSTN,
user_master_reset_n,
clock_ready
);
input L0DLUPDOWN;
input GSR;
input CRMCORECLK;
input USERCLK;
input [3:0] L0LTSSMSTATE;
input L0STATSCFGTRANSMITTED;
input CRMDOHOTRESETN;
input CRMPWRSOFTRESETN;
output CRMMGMTRSTN;
output CRMNVRSTN;
output CRMMACRSTN;
output CRMLINKRSTN;
output CRMURSTN;
output CRMUSERCFGRSTN;
input user_master_reset_n;
input clock_ready;
parameter G_RESETMODE = "FALSE";
parameter G_RESETSUBMODE = 1;
parameter G_USE_EXTRA_REG = 1;
// Common logic for all reset mode
wire fpga_logic_reset_n;
assign fpga_logic_reset_n = ~GSR && user_master_reset_n;
// L0DLUPDOWN[0] capture
reg dl_down_1, dl_down_2;
reg dl_down_reset_1_n, dl_down_reset_2_n;
reg dl_down_reset_n;
reg crm_pwr_soft_reset_n_aftersentcpl;
reg softreset_wait_for_cpl;
reg crmpwrsoftresetn_d;
reg l0statscfgtransmitted_d;
wire crmpwrsoftresetn_fell;
always @ (posedge CRMCORECLK, negedge fpga_logic_reset_n)
if (!fpga_logic_reset_n) begin
dl_down_1 <= 1'b1;
dl_down_2 <= 1'b1;
end else begin
dl_down_1 <= L0DLUPDOWN;
dl_down_2 <= dl_down_1;
end
// Edge detect and pulse stretch to create dl_down_reset_n pulse
// The pulse can be further stretched for debugging purpose by adding
// more register stages.
always @ (posedge CRMCORECLK, negedge fpga_logic_reset_n)
if (!fpga_logic_reset_n) begin
dl_down_reset_1_n <= 1'b1;
dl_down_reset_2_n <= 1'b1;
dl_down_reset_n <= 1'b1;
end else begin
dl_down_reset_1_n <= ~(~dl_down_1 & dl_down_2);
dl_down_reset_2_n <= dl_down_reset_1_n;
dl_down_reset_n <= dl_down_reset_1_n && dl_down_reset_2_n;
end
// This logic ensures that if we get a D3->D0 transition (which triggers
// soft_reset), then we will not reset until the Cpl is generated
// Wait for CRMPWRSOFTRESETN to assert to indicate this condition, and pulse
// CRMUSERCFGRSTN once the Cfg Cpl exits (L0STATSCFGTRANSMITTED). It is
// possible for L0STATSCFGTRANSMITTED to occur simultaneously or one cycle
// before CRMPWRSOFTRESETN asserts.
always @ (posedge USERCLK, negedge fpga_logic_reset_n)
if (!fpga_logic_reset_n)
softreset_wait_for_cpl <= 1'b0;
else if (crmpwrsoftresetn_fell && !L0STATSCFGTRANSMITTED && !l0statscfgtransmitted_d)
softreset_wait_for_cpl <= 1'b1;
else if (L0STATSCFGTRANSMITTED)
softreset_wait_for_cpl <= 1'b0;
always @ (posedge USERCLK, negedge fpga_logic_reset_n)
if (!fpga_logic_reset_n) begin
crm_pwr_soft_reset_n_aftersentcpl <= 1'b1;
crmpwrsoftresetn_d <= 1'b1;
l0statscfgtransmitted_d <= 1'b0;
end else begin
crm_pwr_soft_reset_n_aftersentcpl <= !((softreset_wait_for_cpl && L0STATSCFGTRANSMITTED) ||
(!CRMPWRSOFTRESETN && L0STATSCFGTRANSMITTED) ||
(!CRMPWRSOFTRESETN && l0statscfgtransmitted_d));
crmpwrsoftresetn_d <= CRMPWRSOFTRESETN;
l0statscfgtransmitted_d <= L0STATSCFGTRANSMITTED;
end
assign crmpwrsoftresetn_fell = !CRMPWRSOFTRESETN && crmpwrsoftresetn_d;
// End common logic section
generate
if (G_RESETMODE == "TRUE") begin : resetmode_true
// 6-domain reset mode (RESETMODE=TRUE)
if (G_RESETSUBMODE == 0) begin : sub_0_mode_true
// a. user_master_reset_n is used to drive CRMMGMTRSTN
assign CRMMGMTRSTN = clock_ready && user_master_reset_n;
assign CRMNVRSTN = 1'b1;
assign CRMMACRSTN = 1'b1;
assign CRMLINKRSTN = dl_down_reset_n && CRMDOHOTRESETN;
assign CRMURSTN = dl_down_reset_n && CRMDOHOTRESETN;
assign CRMUSERCFGRSTN = dl_down_reset_n && CRMDOHOTRESETN && crm_pwr_soft_reset_n_aftersentcpl;
end
else begin : sub_1_mode_true
//b. user_master_reset_n is used but does not drive CRMMGMTRSTN
assign CRMMGMTRSTN = clock_ready;
assign CRMNVRSTN = user_master_reset_n;
assign CRMMACRSTN = user_master_reset_n;
assign CRMLINKRSTN = user_master_reset_n && dl_down_reset_n && CRMDOHOTRESETN;
assign CRMURSTN = user_master_reset_n && dl_down_reset_n && CRMDOHOTRESETN;
assign CRMUSERCFGRSTN = user_master_reset_n && dl_down_reset_n && CRMDOHOTRESETN && crm_pwr_soft_reset_n_aftersentcpl;
end
// End 6-domain reset mode logic
end
endgenerate
generate
if (G_RESETMODE == "FALSE") begin : resetmode_false
// 4-domain hierarchical reset mode (RESETMODE=FALSE)
// This mode requires decoding the L0LTSSMSTATE outputs
// from the PCIe block to detect LTSSM transition from Disabled
// (1011), Loopback (1001) or Hot Reset (1010) to Detect (0001).
wire ltssm_linkdown_hot_reset_n;
reg ltssm_dl_down_last_state;
reg [3:0] ltssm_capture;
reg crmpwrsoftresetn_capture;
reg ltssm_linkdown_hot_reset_reg_n;
// Use with G_USE_EXTRA_REG == 1 for better timing
always @ (posedge CRMCORECLK) begin
ltssm_capture <= L0LTSSMSTATE;
//crmpwrsoftresetn_capture <= CRMPWRSOFTRESETN;
crmpwrsoftresetn_capture <= crm_pwr_soft_reset_n_aftersentcpl;
ltssm_linkdown_hot_reset_reg_n <= ltssm_linkdown_hot_reset_n;
end
always @ (posedge CRMCORECLK, negedge fpga_logic_reset_n) begin
if (G_USE_EXTRA_REG == 1) begin
if (!fpga_logic_reset_n) begin
ltssm_dl_down_last_state <= 1'b0;
end else if ((ltssm_capture == 4'b1010) || (ltssm_capture == 4'b1001) || (ltssm_capture == 4'b1011) ||
(ltssm_capture == 4'b1100) || (ltssm_capture == 4'b0011)) begin
ltssm_dl_down_last_state <= 1'b1;
end else begin
ltssm_dl_down_last_state <= 1'b0;
end
end else begin
if (!fpga_logic_reset_n) begin
ltssm_dl_down_last_state <= 1'b0;
end else if ((L0LTSSMSTATE == 4'b1010) || (L0LTSSMSTATE == 4'b1001) || (L0LTSSMSTATE == 4'b1011) ||
(L0LTSSMSTATE == 4'b1100) || (L0LTSSMSTATE == 4'b0011)) begin
ltssm_dl_down_last_state <= 1'b1;
end else begin
ltssm_dl_down_last_state <= 1'b0;
end
end
end
assign ltssm_linkdown_hot_reset_n = (G_USE_EXTRA_REG == 1) ?
~(ltssm_dl_down_last_state && (ltssm_capture[3:1] == 3'b000)) :
~(ltssm_dl_down_last_state && (L0LTSSMSTATE[3:1] == 3'b000));
if (G_RESETSUBMODE == 0) begin : sub_0_mode_false
// a. user_master_reset_n is used to drive CRMMGMTRSTN
assign CRMMGMTRSTN = clock_ready && user_master_reset_n;
assign CRMNVRSTN = 1'b1;
assign CRMURSTN = (G_USE_EXTRA_REG == 1) ? ltssm_linkdown_hot_reset_reg_n : ltssm_linkdown_hot_reset_n;
assign CRMUSERCFGRSTN = (G_USE_EXTRA_REG == 1) ? crmpwrsoftresetn_capture : crm_pwr_soft_reset_n_aftersentcpl;
assign CRMMACRSTN = 1'b1; // not used, just avoiding 'z' in simulation
assign CRMLINKRSTN = 1'b1; // not used, just avoiding 'z' in simulation
end
else begin : sub_1_mode_false
// b. user_master_reset_n is used but does not drive CRMMGMTRSTN
assign CRMMGMTRSTN = clock_ready;
assign CRMNVRSTN = user_master_reset_n;
assign CRMURSTN = (G_USE_EXTRA_REG == 1) ? ltssm_linkdown_hot_reset_reg_n : ltssm_linkdown_hot_reset_n;
assign CRMUSERCFGRSTN = (G_USE_EXTRA_REG == 1) ? crmpwrsoftresetn_capture : crm_pwr_soft_reset_n_aftersentcpl;
assign CRMMACRSTN = 1'b1; // not used, just avoiding 'z' in simulation
assign CRMLINKRSTN = 1'b1; // not used, just avoiding 'z' in simulation
end
// End 4-domain hierarchical reset mode logic
end
endgenerate
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_rxcounters.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// - Novan Hartadi ([email protected]) ////
//// - Mahmud Galela ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "timescale.v"
module eth_rxcounters
(
MRxClk, Reset, MRxDV, StateIdle, StateSFD, StateData, StateDrop, StatePreamble,
MRxDEqD, DlyCrcEn, DlyCrcCnt, Transmitting, MaxFL, r_IFG, HugEn, IFGCounterEq24,
ByteCntEq0, ByteCntEq1, ByteCntEq2,ByteCntEq3,ByteCntEq4,ByteCntEq5, ByteCntEq6,
ByteCntEq7, ByteCntGreat2, ByteCntSmall7, ByteCntMaxFrame, ByteCntOut
);
input MRxClk;
input Reset;
input MRxDV;
input StateSFD;
input [1:0] StateData;
input MRxDEqD;
input StateIdle;
input StateDrop;
input DlyCrcEn;
input StatePreamble;
input Transmitting;
input HugEn;
input [15:0] MaxFL;
input r_IFG;
output IFGCounterEq24; // IFG counter reaches 9600 ns (960 ns)
output [3:0] DlyCrcCnt; // Delayed CRC counter
output ByteCntEq0; // Byte counter = 0
output ByteCntEq1; // Byte counter = 1
output ByteCntEq2; // Byte counter = 2
output ByteCntEq3; // Byte counter = 3
output ByteCntEq4; // Byte counter = 4
output ByteCntEq5; // Byte counter = 5
output ByteCntEq6; // Byte counter = 6
output ByteCntEq7; // Byte counter = 7
output ByteCntGreat2; // Byte counter > 2
output ByteCntSmall7; // Byte counter < 7
output ByteCntMaxFrame; // Byte counter = MaxFL
output [15:0] ByteCntOut; // Byte counter
wire ResetByteCounter;
wire IncrementByteCounter;
wire ResetIFGCounter;
wire IncrementIFGCounter;
wire ByteCntMax;
reg [15:0] ByteCnt;
reg [3:0] DlyCrcCnt;
reg [4:0] IFGCounter;
wire [15:0] ByteCntDelayed;
assign ResetByteCounter = MRxDV & (StateSFD & MRxDEqD | StateData[0] & ByteCntMaxFrame);
assign IncrementByteCounter = ~ResetByteCounter & MRxDV &
(StatePreamble | StateSFD | StateIdle & ~Transmitting |
StateData[1] & ~ByteCntMax & ~(DlyCrcEn & |DlyCrcCnt)
);
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ByteCnt[15:0] <= 16'd0;
else
begin
if(ResetByteCounter)
ByteCnt[15:0] <= 16'd0;
else
if(IncrementByteCounter)
ByteCnt[15:0] <= ByteCnt[15:0] + 16'd1;
end
end
assign ByteCntDelayed = ByteCnt + 16'd4;
assign ByteCntOut = DlyCrcEn ? ByteCntDelayed : ByteCnt;
assign ByteCntEq0 = ByteCnt == 16'd0;
assign ByteCntEq1 = ByteCnt == 16'd1;
assign ByteCntEq2 = ByteCnt == 16'd2;
assign ByteCntEq3 = ByteCnt == 16'd3;
assign ByteCntEq4 = ByteCnt == 16'd4;
assign ByteCntEq5 = ByteCnt == 16'd5;
assign ByteCntEq6 = ByteCnt == 16'd6;
assign ByteCntEq7 = ByteCnt == 16'd7;
assign ByteCntGreat2 = ByteCnt > 16'd2;
assign ByteCntSmall7 = ByteCnt < 16'd7;
assign ByteCntMax = ByteCnt == 16'hffff;
assign ByteCntMaxFrame = ByteCnt == MaxFL[15:0] & ~HugEn;
assign ResetIFGCounter = StateSFD & MRxDV & MRxDEqD | StateDrop;
assign IncrementIFGCounter = ~ResetIFGCounter & (StateDrop | StateIdle | StatePreamble | StateSFD) & ~IFGCounterEq24;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
IFGCounter[4:0] <= 5'h0;
else
begin
if(ResetIFGCounter)
IFGCounter[4:0] <= 5'h0;
else
if(IncrementIFGCounter)
IFGCounter[4:0] <= IFGCounter[4:0] + 5'd1;
end
end
assign IFGCounterEq24 = (IFGCounter[4:0] == 5'h18) | r_IFG; // 24*400 = 9600 ns or r_IFG is set to 1
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
DlyCrcCnt[3:0] <= 4'h0;
else
begin
if(DlyCrcCnt[3:0] == 4'h9)
DlyCrcCnt[3:0] <= 4'h0;
else
if(DlyCrcEn & StateSFD)
DlyCrcCnt[3:0] <= 4'h1;
else
if(DlyCrcEn & (|DlyCrcCnt[3:0]))
DlyCrcCnt[3:0] <= DlyCrcCnt[3:0] + 4'd1;
end
end
endmodule
|
/* salsaengine.v
*
* Copyright (c) 2013 kramble
* Parts copyright (c) 2011 [email protected]
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
// NB HALFRAM no longer applies, configure via parameters ADDRBITS, THREADS
// Bracket this config option in SIM so we don't accidentally leave it set in a live build
`ifdef SIM
//`define ONETHREAD // Start one thread only (for SIMULATION less confusing and faster startup)
`endif
`timescale 1ns/1ps
module salsaengine (hash_clk, reset, din, dout, shift, start, busy, result );
input hash_clk;
input reset; // NB pbkdf_clk domain (need a long reset (at least THREADS+4) to initialize correctly, this is done in pbkdfengine (15 cycles)
input shift;
input start; // NB pbkdf_clk domain
output busy;
output reg result = 1'b0;
parameter SBITS = 8; // Shift data path width
input [SBITS-1:0] din;
output [SBITS-1:0] dout;
// Configure ADDRBITS to allocate RAM for core (automatically sets LOOKAHEAD_GAP)
// NB do not use ADDRBITS > 13 for THREADS=8 since this corresponds to more than a full scratchpad
// These settings are now overriden in ltcminer_icarus.v determined by LOCAL_MINERS ...
// parameter ADDRBITS = 13; // 8MBit RAM allocated to core, full scratchpad (will not fit LX150)
parameter ADDRBITS = 12; // 4MBit RAM allocated to core, half scratchpad
// parameter ADDRBITS = 11; // 2MBit RAM allocated to core, quarter scratchpad
// parameter ADDRBITS = 10; // 1MBit RAM allocated to core, eighth scratchpad
// Do not change THREADS - this must match the salsa pipeline (code is untested for other values)
parameter THREADS = 16; // NB Phase has THREADS+1 cycles
function integer clog2; // Courtesy of razorfishsl, replaces $clog2()
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
parameter THREADS_BITS = clog2(THREADS);
// Workaround for range-reversal error in inactive code when ADDRBITS=13
parameter ADDRBITSX = (ADDRBITS == 13) ? ADDRBITS-1 : ADDRBITS;
reg [THREADS_BITS:0]phase = 0;
reg [THREADS_BITS:0]phase_d = THREADS+1;
reg reset_d=0, fsmreset=0, start_d=0, fsmstart=0;
always @ (posedge hash_clk) // Phase control and sync
begin
phase <= (phase == THREADS) ? 0 : phase + 1;
phase_d <= phase;
reset_d <= reset; // Synchronise to hash_clk domain
fsmreset <= reset_d;
start_d <= start;
fsmstart <= start_d;
end
// Salsa Mix FSM (handles both loading of the scratchpad ROM and the subsequent processing)
parameter XSnull = 0, XSload = 1, XSmix = 2, XSram = 4; // One-hot since these map directly to mux contrls
reg [2:0] XCtl = XSnull;
parameter R_IDLE=0, R_START=1, R_WRITE=2, R_MIX=3, R_INT=4, R_WAIT=5;
reg [2:0] mstate = R_IDLE;
reg [10:0] cycle = 11'd0;
reg doneROM = 1'd0; // Yes ROM, as its referred thus in the salsa docs
reg addrsourceMix = 1'b0;
reg datasourceLoad = 1'b0;
reg addrsourceSave = 1'b0;
reg resultsourceRam = 1'b0;
reg xoren = 1'b1;
reg [THREADS_BITS+1:0] intcycles = 0; // Number of interpolation cycles required ... How many do we need? Say THREADS_BITS+1
wire [511:0] Xmix;
reg [511:0] X0;
reg [511:0] X1;
wire [511:0] X0in;
wire [511:0] X1in;
wire [511:0] X0out;
reg [1023:0] salsaShiftReg;
reg [31:0] nonce_sr; // In series with salsaShiftReg
assign dout = salsaShiftReg[1023:1024-SBITS];
// sstate is implemented in ram (alternatively could use a rotating shift register)
reg [THREADS_BITS+30:0] sstate [THREADS-1:0]; // NB initialized via a long reset (see pbkdfengine)
// List components of sstate here for ease of maintenance ...
wire [2:0] mstate_in;
wire [10:0] cycle_in;
wire [9:0] writeaddr_in;
wire doneROM_in;
wire addrsourceMix_in;
wire addrsourceSave_in;
wire [THREADS_BITS+1:0] intcycles_in; // How many do we need? Say THREADS_BITS+1
wire [9:0] writeaddr_next = writeaddr_in + 10'd1;
reg [31:0] snonce [THREADS-1:0]; // Nonce store. Note bidirectional loading below, this will either implement
// as registers or dual-port ram, so do NOT integrate with sstate.
// NB no busy_in or result_in as these flag are NOT saved on a per-thread basis
// Convert salsaShiftReg to little-endian word format to match scrypt.c as its easier to debug it
// this way rather than recoding the SMix salsa to work with original buffer
wire [1023:0] X;
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin : Xrewire
wire [31:0] tmp;
assign tmp = salsaShiftReg[`IDX(i)];
assign X[`IDX(i)] = { tmp[7:0], tmp[15:8], tmp[23:16], tmp[31:24] };
end
endgenerate
// NB writeaddr is cycle counter in R_WRITE so use full size regardless of RAM size
(* S = "TRUE" *) reg [9:0] writeaddr = 10'd0;
// ALTRAM Max is 256 bit width, so use four
// Ram is registered on inputs vis ram_addr, ram_din and ram_wren
// Output is unregistered, OLD data on write (less delay than NEW??)
wire [9:0] Xaddr;
wire [ADDRBITS-1:0]rd_addr;
wire [ADDRBITS-1:0]wr_addr1;
wire [ADDRBITS-1:0]wr_addr2;
wire [ADDRBITS-1:0]wr_addr3;
wire [ADDRBITS-1:0]wr_addr4;
wire [255:0]ram1_din;
wire [255:0]ram1_dout;
wire [255:0]ram2_din;
wire [255:0]ram2_dout;
wire [255:0]ram3_din;
wire [255:0]ram3_dout;
wire [255:0]ram4_din;
wire [255:0]ram4_dout;
wire [1023:0]ramout;
(* S = "TRUE" *) reg ram_wren = 1'b0;
wire ram_clk;
assign ram_clk = hash_clk; // Uses same clock as hasher for now
// Top ram address is reserved for X0Save/X1save, so adjust
wire [15:0] memtop = 16'hfffe; // One less than the top memory location (per THREAD bank)
wire [ADDRBITS-THREADS_BITS-1:0] adj_addr;
if (ADDRBITS < 13)
assign adj_addr = (Xaddr[9:THREADS_BITS+10-ADDRBITS] == memtop[9:THREADS_BITS+10-ADDRBITS]) ?
memtop[ADDRBITS-THREADS_BITS-1:0] : Xaddr[9:THREADS_BITS+10-ADDRBITS];
else
assign adj_addr = Xaddr;
wire [THREADS_BITS-1:0] phase_addr;
assign phase_addr = phase[THREADS_BITS-1:0];
// TODO can we remove the +1 and adjust the wr_addr to use the same prefix via phase_d?
assign rd_addr = { phase_addr+1, addrsourceSave_in ? memtop[ADDRBITS-THREADS_BITS:1] : adj_addr }; // LSB are ignored
wire [9:0] writeaddr_adj = addrsourceMix ? memtop[10:1] : writeaddr;
assign wr_addr1 = { phase_addr, writeaddr_adj[9:THREADS_BITS+10-ADDRBITS] };
assign wr_addr2 = { phase_addr, writeaddr_adj[9:THREADS_BITS+10-ADDRBITS] };
assign wr_addr3 = { phase_addr, writeaddr_adj[9:THREADS_BITS+10-ADDRBITS] };
assign wr_addr4 = { phase_addr, writeaddr_adj[9:THREADS_BITS+10-ADDRBITS] };
// Duplicate address to reduce fanout (its a ridiculous kludge, but seems to be the approved method)
(* S = "TRUE" *) reg [ADDRBITS-1:0] rd_addr_z_1 = 0;
(* S = "TRUE" *) reg [ADDRBITS-1:0] rd_addr_z_2 = 0;
(* S = "TRUE" *) reg [ADDRBITS-1:0] rd_addr_z_3 = 0;
(* S = "TRUE" *) reg [ADDRBITS-1:0] rd_addr_z_4 = 0;
(* S = "TRUE" *) wire [ADDRBITS-1:0] rd_addr1 = rd_addr | rd_addr_z_1;
(* S = "TRUE" *) wire [ADDRBITS-1:0] rd_addr2 = rd_addr | rd_addr_z_2;
(* S = "TRUE" *) wire [ADDRBITS-1:0] rd_addr3 = rd_addr | rd_addr_z_3;
(* S = "TRUE" *) wire [ADDRBITS-1:0] rd_addr4 = rd_addr | rd_addr_z_4;
ram # (.ADDRBITS(ADDRBITS)) ram1_blk (rd_addr1, wr_addr1, ram_clk, ram1_din, ram_wren, ram1_dout);
ram # (.ADDRBITS(ADDRBITS)) ram2_blk (rd_addr2, wr_addr2, ram_clk, ram2_din, ram_wren, ram2_dout);
ram # (.ADDRBITS(ADDRBITS)) ram3_blk (rd_addr3, wr_addr3, ram_clk, ram3_din, ram_wren, ram3_dout);
ram # (.ADDRBITS(ADDRBITS)) ram4_blk (rd_addr4, wr_addr4, ram_clk, ram4_din, ram_wren, ram4_dout);
assign ramout = { ram4_dout, ram3_dout, ram2_dout, ram1_dout }; // Unregistered output
assign { ram4_din, ram3_din, ram2_din, ram1_din } = datasourceLoad ? X : { Xmix, X0out}; // Registered input
// Salsa unit
salsa salsa_blk (hash_clk, X0, X1, Xmix, X0out, Xaddr);
// Main multiplexer
wire [511:0] Zbits;
assign Zbits = {512{xoren}}; // xoren enables xor from ram (else we load from ram)
// With luck the synthesizer will interpret this correctly as one-hot control ...
// DEBUG using default state of 0 for XSnull so as to show up issues with preserved values (previously held value X0/X1)
// assign X0in = (XCtl==XSmix) ? X0out : (XCtl==XSram) ? (X0out & Zbits) ^ ramout[511:0] : (XCtl==XSload) ? X[511:0] : 0;
// assign X1in = (XCtl==XSmix) ? Xmix : (XCtl==XSram) ? (Xmix & Zbits) ^ ramout[1023:512] : (XCtl==XSload) ? X[1023:512] : 0;
// Now using explicit control signals (rather than relying on synthesizer to map correctly)
// XSMix is now the default (XSnull is unused as this mapped onto zero in the DEBUG version above) - TODO amend FSM accordingly
assign X0in = XCtl[2] ? (X0out & Zbits) ^ ramout[511:0] : XCtl[0] ? X[511:0] : X0out;
assign X1in = XCtl[2] ? (Xmix & Zbits) ^ ramout[1023:512] : XCtl[0] ? X[1023:512] : Xmix;
// Salsa FSM - TODO may want to move this into a separate function (for floorplanning), see hashvariant-C
// Hold separate state for each thread (a bit of a kludge to avoid rewriting FSM from scratch)
// NB must ensure shift and result do NOT overlap by carefully controlling timing of start signal
// NB Phase has THREADS+1 cycles, but we do not save the state for (phase==THREADS) as it is never active
assign { mstate_in, writeaddr_in, cycle_in, doneROM_in, addrsourceMix_in, addrsourceSave_in, intcycles_in} =
(phase == THREADS ) ? 0 : sstate[phase];
// Interface FSM ensures threads start evenly (required for correct salsa FSM operation)
reg busy_flag = 1'b0;
`ifdef ONETHREAD
// TEST CONTROLLER ... just allow a single thread to run (busy is currently a common flag)
// NB the thread automatically restarts after it completes, so its a slight misnomer to say it starts once.
reg start_once = 1'b0;
wire start_flag;
assign start_flag = fsmstart & ~start_once;
assign busy = busy_flag; // Ack to pbkdfengine
`else
// NB start_flag only has effect when a thread is at R_IDLE, ie after reset, normally a thread will automatically
// restart on completion. We need to spread the R_IDLE starts evenly to ensure proper ooperation. NB the pbkdf
// engine requires busy and result, but this looks alter itself in the salsa FSM, even though these are global
// flags. Reset periodically (on loadnonce in pbkdfengine) to ensure it stays in sync.
reg [15:0] start_count = 0;
// TODO automatic configuration (currently assumes THREADS 8 or 16, and ADDRBITS 12,11,10 calculated as follows...)
// For THREADS=8, lookup_gap=2 salsa takes on average 9*(1024+(1024*1.5)) = 23040 clocks, generically 9*1024*(lookup_gap/2+1.5)
// For THREADS=16, use 17*1024*(lookup_gap/2+1.5), where lookupgap is double that for THREADS=8
parameter START_INTERVAL = (THREADS==16) ? ((ADDRBITS==12) ? 60928 : (ADDRBITS==11) ? 95744 : 165376) / THREADS : // 16 threads
((ADDRBITS==12) ? 23040 : (ADDRBITS==11) ? 36864 : 50688) / THREADS ; // 8 threads
reg start_flag = 1'b0;
assign busy = busy_flag; // Ack to pbkdfengine - this will toggle on transtion through R_START
`endif
always @ (posedge hash_clk)
begin
X0 <= X0in;
X1 <= X1in;
if (phase_d != THREADS)
sstate[phase_d] <= fsmreset ? 0 : { mstate, writeaddr, cycle, doneROM, addrsourceMix, addrsourceSave, intcycles };
mstate <= mstate_in; // Set defaults (overridden below as necessary)
writeaddr <= writeaddr_in;
cycle <= cycle_in;
intcycles <= intcycles_in;
doneROM <= doneROM_in;
addrsourceMix <= addrsourceMix_in;
addrsourceSave <= addrsourceSave_in; // Overwritten below, but addrsourceSave_in is used above
// Duplicate address to reduce fanout (its a ridiculous kludge, but seems to be the approved method)
rd_addr_z_1 <= {ADDRBITS{fsmreset}};
rd_addr_z_2 <= {ADDRBITS{fsmreset}};
rd_addr_z_3 <= {ADDRBITS{fsmreset}};
rd_addr_z_4 <= {ADDRBITS{fsmreset}};
XCtl <= XSnull; // Default states
addrsourceSave <= 0; // NB addrsourceSave_in is the active control so this DOES need to be in sstate
datasourceLoad <= 0; // Does not need to be saved in sstate
resultsourceRam <= 0; // Does not need to be saved in sstate
ram_wren <= 0;
xoren <= 1;
// Interface FSM ensures threads start evenly (required for correct salsa FSM operation)
`ifdef ONETHREAD
if (fsmstart && phase!=THREADS)
start_once <= 1'b1;
if (fsmreset)
start_once <= 1'b0;
`else
start_count <= start_count + 1;
// start_flag <= 1'b0; // Done below when we transition out of R_IDLE
if (fsmreset || start_count == START_INTERVAL)
begin
start_count <= 0;
if (~fsmreset && fsmstart)
start_flag <= 1'b1;
end
`endif
// Could use explicit mux for this ...
if (shift)
begin
salsaShiftReg <= { salsaShiftReg[1023-SBITS:0], nonce_sr[31:32-SBITS] };
nonce_sr <= { nonce_sr[31-SBITS:0], din};
end
else
if (XCtl==XSload && phase_d != THREADS) // Set at end of previous hash - this is executed regardless of phase
begin
salsaShiftReg <= resultsourceRam ? ramout : { Xmix, X0out }; // Simultaneously with XSload
nonce_sr <= snonce[phase_d]; // NB bidirectional load
snonce[phase_d] <= nonce_sr;
end
if (fsmreset == 1'b1)
begin
mstate <= R_IDLE; // This will propagate to all sstate slots as we hold reset for 10 cycles
busy_flag <= 1'b0;
result <= 1'b0;
end
else
begin
case (mstate_in)
R_IDLE: begin
// R_IDLE only applies after reset. Normally each thread will reenter at S_START and
// assumes that input data is waiting (this relies on the threads being started evenly,
// hence the interface FSM at the top of this file)
if (phase!=THREADS && start_flag) // Ensure (phase==THREADS) slot is never active
begin
XCtl <= XSload; // First time only (normally done at end of previous salsa cycle=1023)
`ifndef ONETHREAD
start_flag <= 1'b0;
`endif
busy_flag <= 1'b0; // Toggle the busy flag low to ack pbkdfengine (its usually already set
// since other threads are running)
writeaddr <= 0; // Preset to write X on next cycle
addrsourceMix <= 1'b0;
datasourceLoad <= 1'b1;
ram_wren <= 1'b1;
mstate <= R_START;
end
end
R_START: begin // Reentry point after thread completion. ASSUMES new data is ready.
XCtl <= XSmix;
writeaddr <= writeaddr_next;
cycle <= 0;
if (ADDRBITS == 13)
ram_wren <= 1'b1; // Full scratchpad needs to write to addr=001 next cycle
doneROM <= 1'b0;
busy_flag <= 1'b1;
result <= 1'b0;
mstate <= R_WRITE;
end
R_WRITE: begin
XCtl <= XSmix;
writeaddr <= writeaddr_next;
if (writeaddr_in==1022)
doneROM <= 1'b1; // Need to do one more cycle to update X0,X1
else
if (~doneROM_in)
begin
if (ADDRBITS < 13)
ram_wren <= ~|writeaddr_next[THREADS_BITS+9-ADDRBITSX:0]; // Only write non-interpolated addresses
else
ram_wren <= 1'b1;
end
if (doneROM_in)
begin
addrsourceMix <= 1'b1; // Remains set for duration of R_MIX
mstate <= R_MIX;
XCtl <= XSram; // Load from ram next cycle
// Need this to cover the case of the initial read being interpolated
// NB CODE IS REPLICATED IN R_MIX
if (ADDRBITS < 13)
begin
intcycles <= { {THREADS_BITS+12-ADDRBITSX{1'b0}}, Xaddr[THREADS_BITS+9-ADDRBITSX:0] }; // Interpolated addresses
if ( Xaddr[9:THREADS_BITS+10-ADDRBITSX] == memtop[ADDRBITSX-THREADS_BITS:1] ) // Highest address reserved
intcycles <= { {THREADS_BITS+11-ADDRBITSX{1'b0}}, 1'b1, Xaddr[THREADS_BITS+9-ADDRBITSX:0] };
if ( (Xaddr[9:THREADS_BITS+10-ADDRBITSX] == memtop[ADDRBITSX-THREADS_BITS:1]) || |Xaddr[THREADS_BITS+9-ADDRBITSX:0] )
begin
ram_wren <= 1'b1;
xoren <= 0; // Will do direct load from ram, not xor
mstate <= R_INT; // Interpolate
end
// If intcycles will be set to 1, need to preset for readback
if (
( Xaddr[THREADS_BITS+9-ADDRBITSX:0] == 1 ) &&
!( Xaddr[9:THREADS_BITS+10-ADDRBITSX] == memtop[ADDRBITSX-THREADS_BITS:1] )
)
addrsourceSave <= 1'b1; // Preset to read saved data (9 clocks later)
end
// END REPLICATED BLOCK
end
end
R_MIX: begin
// NB There is an extra step here cf R_WRITE above to read ram data hence 9 not 8 stages.
XCtl <= XSmix;
cycle <= cycle_in + 11'd1;
if (cycle_in==1023)
begin
busy_flag <= 1'b0; // Will hold at 0 for 9 clocks until set at R_START
if (fsmstart) // Check data input is ready
begin
XCtl <= XSload; // Initial load else we overwrite input NB This is
// executed on the next cycle, regardless of phase
// Flag the SHA256 FSM to start final PBKDF2_SHA256_80_128_32
result <= 1'b1;
mstate <= R_START; // Restart immediately
writeaddr <= 0; // Preset to write X on next cycle
datasourceLoad <= 1'b1;
addrsourceMix <= 1'b0;
ram_wren <= 1'b1;
end
else
begin
// mstate <= R_IDLE; // Wait for start_flag
mstate <= R_WAIT;
addrsourceSave <= 1'b1; // Preset to read saved data (9 clocks later)
ram_wren <= 1'b1; // Save result
end
end
else
begin
XCtl <= XSram; // Load from ram next cycle
// NB CODE IS REPLICATED IN R_WRITE
if (ADDRBITS < 13)
begin
intcycles <= { {THREADS_BITS+12-ADDRBITSX{1'b0}}, Xaddr[THREADS_BITS+9-ADDRBITSX:0] }; // Interpolated addresses
if ( Xaddr[9:THREADS_BITS+10-ADDRBITSX] == memtop[ADDRBITSX-THREADS_BITS:1] ) // Highest address reserved
intcycles <= { {THREADS_BITS+11-ADDRBITSX{1'b0}}, 1'b1, Xaddr[THREADS_BITS+9-ADDRBITSX:0] };
if ( (Xaddr[9:THREADS_BITS+10-ADDRBITSX] == memtop[ADDRBITSX-THREADS_BITS:1]) || |Xaddr[THREADS_BITS+9-ADDRBITSX:0] )
begin
ram_wren <= 1'b1;
xoren <= 0; // Will do direct load from ram, not xor
mstate <= R_INT; // Interpolate
end
// If intcycles will be set to 1, need to preset for readback
if (
( Xaddr[THREADS_BITS+9-ADDRBITSX:0] == 1 ) &&
!( Xaddr[9:THREADS_BITS+10-ADDRBITSX] == memtop[ADDRBITSX-THREADS_BITS:1] )
)
addrsourceSave <= 1'b1; // Preset to read saved data (9 clocks later)
end
// END REPLICATED BLOCK
end
end
R_WAIT: begin
if (fsmstart) // Check data input is ready
begin
XCtl <= XSload; // Initial load else we overwrite input NB This is
// executed on the next cycle, regardless of phase
// Flag the SHA256 FSM to start final PBKDF2_SHA256_80_128_32
result <= 1'b1;
mstate <= R_START; // Restart immediately
writeaddr <= 0; // Preset to write X on next cycle
datasourceLoad <= 1'b1;
resultsourceRam <= 1'b1;
addrsourceMix <= 1'b0;
ram_wren <= 1'b1;
end
else
addrsourceSave <= 1'b1; // Preset to read saved data (9 clocks later)
end
R_INT: begin
// Interpolate scratchpad for odd addresses
XCtl <= XSmix;
intcycles <= intcycles_in - 1;
if (intcycles_in==2)
addrsourceSave <= 1'b1; // Preset to read saved data (9 clocks later)
if (intcycles_in==1)
begin
XCtl <= XSram; // Setup to XOR from saved X0/X1 in ram at next cycle
mstate <= R_MIX;
end
// Else mstate remains at R_INT so we continue interpolating
end
endcase
end
`ifdef SIM
// Print the final Xmix for each cycle to compare with scrypt.c (debugging)
if (mstate==R_MIX)
$display ("phase %d cycle %d Xmix %08x\n", phase, cycle-1, Xmix[511:480]);
`endif
end // always @(posedge hash_clk)
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTN_FUNCTIONAL_V
`define SKY130_FD_SC_LP__SDFRTN_FUNCTIONAL_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr/sky130_fd_sc_lp__udp_dff_pr.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_lp__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intclk , CLK_N );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_lp__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, intclk, RESET);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTN_FUNCTIONAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:43:52 03/31/2015
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top(CCLK, SW, BTNN, BTNE, BTNS, BTNW,LED,
LCDE, LCDRS, LCDRW, LCDDAT
);
input wire CCLK;
input wire [3:0] SW;
input wire BTNN,BTNE,BTNW,BTNS;
output wire LCDE, LCDRS, LCDRW;
output wire [3:0] LCDDAT;
output wire [7:0] LED;
wire btnclk;
wire rst;
reg sw_reg,sw_reg_ins;
wire btsw,btreg;
assign LED[3:0]=SW[3:0];
assign LED[4]=btnclk;
assign LED[5]=rst;
assign LED[6]=btsw;
assign LED[7]=btreg;
reg [7:0] clk_cnt;
wire btnbtn = btsw | btreg | btnclk ;
always @(posedge btnclk or posedge rst)
begin
if(rst)
clk_cnt <= 0;
else if(btnclk)
clk_cnt <= clk_cnt+1;
end
always@ (posedge btreg or posedge rst)
begin
if(rst)
sw_reg<=0;
else
sw_reg <= ~sw_reg;
end
always@ (posedge btsw or posedge rst)
begin
if(rst)
sw_reg_ins<=0;
else
sw_reg_ins <= ~sw_reg_ins;
end
wire [31:0] instr;
wire [5:0] op, func;
wire [4:0] rs,rt,rd,shamt,td;
wire [15:0] imm;
wire [25:0] addr;
wire [31:0] saout;
wire JR, J, JAL, LW, WREG, WMEM, RDorRT, SE, SA, IorR, BJ;
wire [4:0] Aluc;
wire [31:0] a, b, aluresult; //alu in/out
wire [4:0] r1, r2, r3, w1; //Reg
wire [31:0] d1, d2, d3, wdata; //Reg
wire [31:0] seout; //signed extended
wire [31:0] pcplus4, pcin, pcout, immaddr, jaddr;
wire [31:0] memdata;
wire equal_result;
//IF
wire [31:0] tmp_pcin,tmp_pcout;
// ID
wire [31:0] id_pcplus4, id_instr;//,tmp_d1,tmp_d2;
wire [4:0] id_td;
// wire WREG_id;
// EX
wire [31:0] ex_a, ex_b, ex_d2,ex_instr,ex_pc;
wire [4:0] ex_td;
wire [4:0] ex_Aluc;
wire ex_WREG, ex_WMEM, ex_LW;
// ME
wire [31:0] me_aluresult, me_d2,me_instr,me_memdata,me_pc;
wire [4:0] me_td;
wire me_WREG, me_WMEM, me_LW;
// WB
wire [31:0] wb_memdata;
wire [4:0] wb_td;
wire wb_WREG;//wb_LW;
//
wire stall;
//pc0
wire jump_en;
wire [1:0] cp_oper;
wire [31:0] CPR, jump_addr, d2_tmp4, pcintmp,pcouttmp,if_pc,id_pc;
wire MFC,swstall;
assign swstall=SW[3] | SW[2];
wire [31:0] dis_data;
wire [7:0] dis_addr;
wire [7:0] IF,ID,EX,MEM;
exin exin1(btnclk, rst, instr, IF);
exin exin2(btnclk, rst, id_instr, ID);
exin exin3(btnclk, rst, ex_instr, EX);
exin exin4(btnclk, rst, me_instr, MEM);
assign dis_data=(sw_reg_ins)?instr:{IF,ID,EX,MEM};//assign dis_data=(sw_reg_ins)?instr:d3;
assign dis_addr=(sw_reg_ins)?{8'b00100001}:{3'b000,r3};
assign r2=rt;
assign r3[4:0]={sw_reg,SW[3:0]};
assign btnclk=BTNN;//anti_jitter at0(.clk(CCLK),.rst(rst),.sig_i(BTNN),.sig_o(btnclk));//
assign rst = BTNE;//anti_jitter at1(.clk(CCLK),.rst(rst),.sig_i(BTNE),.sig_o(rst));//
assign btsw = BTNW;//anti_jitter at2(.clk(CCLK),.rst(rst),.sig_i(BTNW),.sig_o(btsw));//
assign btreg = BTNS;//anti_jitter at3(.clk(CCLK),.rst(rst),.sig_i(BTNS),.sig_o(btreg));//
//////////////////////////////////////////////////////////////////////////////////
// PC
//////////////////////////////////////////////////////////////////////////////////
assign pcin = (jump_en)?(jump_addr+4):pcintmp;
assign pcintmp=(J|JAL|JR|BJ)?(tmp_pcin+4):(tmp_pcin);
assign pcout=(jump_en)?(jump_addr):pcouttmp;
assign pcouttmp=(J|JAL|JR|BJ)?(tmp_pcin):(tmp_pcout);
lock32 lock32(.clk(btnclk), .rst(rst), .in(pcout-4), .out(if_pc));
pc pc(
.clk(btnclk), .rst(rst), .stall(stall),
.i_pc(pcin), .o_pc(tmp_pcout)//?
);
pc_plus4 pc_plus4(
.i_pc(pcout), .o_pc(pcplus4)
);
decode4_32 pc_in(
.in1(jaddr), .in2({d1[29:0],2'd0}), .in3(immaddr), .in4(id_pcplus4), .c1(J | JAL), .c2(JR), .c3(BJ), .out(tmp_pcin)
);
instrmem instrmem(
.clka(btnclk),.addra(pcout[11:2]),.douta(instr[31:0])
);
//////////////////////////////////////////////////////////////////////////////////
// IF-ID
//////////////////////////////////////////////////////////////////////////////////
IF_ID IF_ID(
.clk(btnclk), .rst(rst), .stall(stall|swstall), .BJ(J|JAL|JR|BJ|jump_en),
.if_pcplus4(pcplus4), .if_instr(instr), .if_pc(if_pc),
.id_pcplus4(id_pcplus4), .id_instr(id_instr), .id_pc(id_pc)
);
assign op=id_instr[31:26];
assign rs=id_instr[25:21];
assign rt=id_instr[20:16];
assign rd=id_instr[15:11];
assign shamt=id_instr[10:6];
assign func=id_instr[5:0];
assign imm=id_instr[15:0];
assign addr=id_instr[25:0];
assign saout={27'b0,shamt};
cpu_ctl cpu_ctl(
.op(op), .func(func), .equal_result(equal_result), .rs(rs),
.JR(JR), .J(J), .JAL(JAL), .LW(LW),
.WREG(WREG), .WMEM(WMEM),. RDorRT(RDorRT),
.SE(SE), .SA(SA), .IorR(IorR), .BJ(BJ),
.Aluc(Aluc), .cp_oper(cp_oper), .MFC(MFC)
);
// assign WREG_id=JAL & WREG;
assign td=(JAL)?6'd31:((RDorRT)?rd:rt);
// assign d1 = (wb_td==r1)?wb_memdata:tmp_d1;
//forwarding
wire [31:0] d1_tmp1, d1_tmp2, d2_tmp1, d2_tmp2, d1_tmp3, d2_tmp3;
assign d1 = (ex_td==r1 & |r1 & (ex_WREG | ex_LW))? aluresult : d1_tmp1;
assign d1_tmp1 = (me_td==r1 & |r1 & (me_WREG|me_LW))? me_memdata : d1_tmp2;
assign d1_tmp2 = (wb_td==r1 & |r1 & wb_WREG)? wb_memdata : d1_tmp3;
assign d2 = (MFC)? CPR : d2_tmp4;
assign d2_tmp4 = (ex_td==r2 & |r2 & (ex_WREG | ex_LW))? aluresult : d2_tmp1;
assign d2_tmp1 = (me_td==r2 & |r2 & (me_WREG | me_LW))? me_memdata : d2_tmp2;
assign d2_tmp2 = (wb_td==r2 & |r2 & wb_WREG)? wb_memdata : d2_tmp3;
// assign d2 = (wb_td==r2)?wb_memdata:tmp_d2;
reg32 reg32(
.clk(btnclk), .rst(rst), .wea(wb_WREG),//.wea(WREG_id | me_WREG | me_LW),//
.r1(r1), .r2(r2), .r3(r3), .w1(w1),
.wdata(wdata), .out1(d1_tmp3), .out2(d2_tmp3), .out3(d3)
);
imm_addr imm_addr(
.imm(imm), .pc(id_pcplus4), .out(immaddr)
);
j_addr j_addr(
.addr(addr), .pc(id_pcplus4), .out(jaddr)
);
isequal isequal(
.in1(d1), .in2(d2), .result(equal_result)
);
se se(
.in(imm), .SE(SE), .out(seout)
);
decode3_32 alu_a(
.in1(id_pcplus4-8), .in2(saout), .in3(d1), .c1(JAL), .c2(SA), .out(a)
);
decode3_32 alu_b(
.in1(32'b0), .in2(seout), .in3(d2), .c1(JAL), .c2(IorR), .out(b)
);
assign r1=rs;
// decode2_5 reg_read(
// .in1(5'b11111), .in2(rs), .c(JR), .out(r1)
// );
decode2_5 reg_write(
.in1(wb_td), .in2(5'b11111), .c(wb_WREG), .out(w1)//.in1(me_td), .in2(5'b11111), .c(wb_WREG), .out(w1)//
);
decode2_32 reg_wdata(
.in1(wb_memdata), .in2(id_pcplus4), .c(wb_WREG), .out(wdata)//.in1(me_memdata), .in2(id_pcplus4), .c(wb_WREG), .out(wdata)//
);
//////////////////////////////////////////////////////////////////////////////////
// ID-EX
//////////////////////////////////////////////////////////////////////////////////
wire [31:0] ex_d2_tmp;
assign ex_d2 = ((ex_td==me_td) & (me_WREG|me_LW)) ? me_memdata : ex_d2_tmp;
ID_EX ID_EX(
.clk(btnclk), .rst(rst), .stall(swstall),
.id_a(a), .id_b(b), .id_td(td), .id_d2(d2), .id_Aluc(Aluc), .id_WREG(JAL | WREG & ~LW & |td), .id_WMEM(WMEM), .id_LW(LW & |td),.id_instr(id_instr),.id_pc(id_pc),
.ex_a(ex_a), .ex_b(ex_b), .ex_td(ex_td), .ex_d2(ex_d2_tmp), .ex_Aluc(ex_Aluc), .ex_WREG(ex_WREG), .ex_WMEM(ex_WMEM), .ex_LW(ex_LW),.ex_instr(ex_instr),.ex_pc(ex_pc)
);
alu alu(
.a(ex_a), .b(ex_b), .aluc(ex_Aluc), .result(aluresult)
);
//////////////////////////////////////////////////////////////////////////////////
// EX-MEM
//////////////////////////////////////////////////////////////////////////////////
wire [9:0] ex_addra;
assign ex_addra = (me_WMEM)?me_aluresult[11:2]:aluresult[11:2];
EX_ME EX_ME(
.clk(btnclk), .rst(rst), .stall(swstall),
.ex_aluresult(aluresult), .ex_td(ex_td), .ex_d2(ex_d2), .ex_WREG(ex_WREG ), .ex_WMEM(ex_WMEM), .ex_LW(ex_LW ),.ex_instr(ex_instr),.ex_pc(ex_pc),
.me_aluresult(me_aluresult), .me_td(me_td), .me_d2(me_d2), .me_WREG(me_WREG), .me_WMEM(me_WMEM), .me_LW(me_LW),.me_instr(me_instr),.me_pc(me_pc)
);
Data_Mem Data_Mem(
.clka(btnclk),.wea(me_WMEM),.addra(ex_addra),.dina(me_d2),.douta(memdata)//.clka(btnclk),.wea(me_WMEM),.addra(me_aluresult[11:2]),.dina(me_d2),.douta(memdata)
);
assign me_memdata=(me_WREG)?me_aluresult:memdata;
//////////////////////////////////////////////////////////////////////////////////
// MEM-WB
//////////////////////////////////////////////////////////////////////////////////
ME_WB ME_WB(
.clk(btnclk), .rst(rst), .stall(swstall),
.me_memdata(me_memdata), .me_td(me_td), .me_WREG(me_WREG | me_LW),
.wb_memdata(wb_memdata), .wb_td(wb_td), .wb_WREG(wb_WREG)
);
display2 ds(
.clk(CCLK),.rst(rst),.instr(instr),.reg_data(d3),.stage({IF,ID,EX,MEM}),.clk_cnt(clk_cnt),.reg_addr({3'b0,r3}),
.lcd_rs(LCDRS), .lcd_rw(LCDRW), .lcd_e(LCDE), .lcd_dat(LCDDAT)
);
//////////////////////////////////////////////////////////////////////////////////
// WB
//////////////////////////////////////////////////////////////////////////////////
pc0 pc0(
.clk(CCLK), .rst(rst), .interrupt_signal(SW[3:2]), .cp_oper(cp_oper), .cp_cd(rd), .return_addr(me_pc), .GPR(d2), .jump_en(jump_en), .CPR(CPR), .jump_addr(jump_addr)
);
//////////////////////////////////////////////////////////////////////////////////
// Stall Control Logic
//////////////////////////////////////////////////////////////////////////////////
StallControlLogic scl(
.rs(instr[25:21]),.rt(instr[20:16]),.op(instr[31:26]), .func(instr[5:0]),
.id_td(td), .id_LW(LW & |td),
.stall(stall)
);
endmodule
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo_mixed_widths
// ============================================================
// File Name: async_fifo_512x36_to_72_progfull_500.v
// Megafunction Name(s):
// dcfifo_mixed_widths
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module async_fifo_512x36_to_72_progfull_500 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull,
wrusedw);
input aclr;
input [35:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [71:0] q;
output rdempty;
output wrfull;
output [8:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "512"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "36"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "72"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "36"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "72"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "3"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "3"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 36 0 INPUT NODEFVAL "data[35..0]"
// Retrieval info: USED_PORT: q 0 0 72 0 OUTPUT NODEFVAL "q[71..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL "wrusedw[8..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 36 0 data 0 0 36 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 72 0 @q 0 0 72 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0
// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_512x36_to_72_progfull_500.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_512x36_to_72_progfull_500.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_512x36_to_72_progfull_500.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_512x36_to_72_progfull_500.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_512x36_to_72_progfull_500_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_512x36_to_72_progfull_500_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Read Data Response AXI3 Slave Converter
// Forwards and re-assembles split transactions.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// r_axi3_conv
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_r_axi3_conv #
(
parameter C_FAMILY = "none",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_SUPPORT_SPLITTING = 1,
// Implement transaction splitting logic.
// Disabled whan all connected masters are AXI3 and have same or narrower data width.
parameter integer C_SUPPORT_BURSTS = 1
// Disabled when all connected masters are AxiLite,
// allowing logic to be simplified.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Command Interface
input wire cmd_valid,
input wire cmd_split,
output wire cmd_ready,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Throttling help signals.
wire cmd_ready_i;
wire pop_si_data;
wire si_stalling;
// Internal MI-side control signals.
wire M_AXI_RREADY_I;
// Internal signals for SI-side.
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID_I;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA_I;
wire [2-1:0] S_AXI_RRESP_I;
wire S_AXI_RLAST_I;
wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER_I;
wire S_AXI_RVALID_I;
wire S_AXI_RREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// Forward data from MI-Side to SI-Side while a command is available. When
// the transaction has completed the command is popped from the Command FIFO.
//
//
/////////////////////////////////////////////////////////////////////////////
// Pop word from SI-side.
assign M_AXI_RREADY_I = ~si_stalling & cmd_valid;
assign M_AXI_RREADY = M_AXI_RREADY_I;
// Indicate when there is data available @ SI-side.
assign S_AXI_RVALID_I = M_AXI_RVALID & cmd_valid;
// Get SI-side data.
assign pop_si_data = S_AXI_RVALID_I & S_AXI_RREADY_I;
// Signal that the command is done (so that it can be poped from command queue).
assign cmd_ready_i = cmd_valid & pop_si_data & M_AXI_RLAST;
assign cmd_ready = cmd_ready_i;
// Detect when MI-side is stalling.
assign si_stalling = S_AXI_RVALID_I & ~S_AXI_RREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Simple AXI signal forwarding:
//
// USER, ID, DATA and RRESP passes through untouched.
//
// LAST has to be filtered to remove any intermediate LAST (due to split
// trasactions). LAST is only removed for the first parts of a split
// transaction. When splitting is unsupported is the LAST filtering completely
// completely removed.
//
/////////////////////////////////////////////////////////////////////////////
// Calculate last, i.e. mask from split transactions.
assign S_AXI_RLAST_I = M_AXI_RLAST &
( ~cmd_split | ( C_SUPPORT_SPLITTING == 0 ) );
// Data is passed through.
assign S_AXI_RID_I = M_AXI_RID;
assign S_AXI_RUSER_I = M_AXI_RUSER;
assign S_AXI_RDATA_I = M_AXI_RDATA;
assign S_AXI_RRESP_I = M_AXI_RRESP;
/////////////////////////////////////////////////////////////////////////////
// SI-side output handling
//
/////////////////////////////////////////////////////////////////////////////
// TODO: registered?
assign S_AXI_RREADY_I = S_AXI_RREADY;
assign S_AXI_RVALID = S_AXI_RVALID_I;
assign S_AXI_RID = S_AXI_RID_I;
assign S_AXI_RDATA = S_AXI_RDATA_I;
assign S_AXI_RRESP = S_AXI_RRESP_I;
assign S_AXI_RLAST = S_AXI_RLAST_I;
assign S_AXI_RUSER = S_AXI_RUSER_I;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFSBP_SYMBOL_V
`define SKY130_FD_SC_HD__SDFSBP_SYMBOL_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdfsbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFSBP_SYMBOL_V
|
module tone_lut64 (input [5:0] tone, output [13:0] sixty_fourth_period);
//these constants define the number of 100Mhz cycles needed to emulate each note frequency, divided by 64 to get
//a 64th of the waveform, to use PWM accurately
parameter
REST= 14'd1000, // give a small delay between look-up table advances
C3 = 14'd11945,
C3S = 14'd11275,
D3 = 14'd10642,
D3S = 14'd10045,
E3 = 14'd9481,
F3 = 14'd8949,
F3S = 14'd8446,
G3 = 14'd7972,
G3S = 14'd7525,
A3 = 14'd7103,
A3S = 14'd6704,
B3 = 14'd6328,
C4 = 14'd5973,
C4S = 14'd5638,
D4 = 14'd5321,
D4S = 14'd5022,
E4 = 14'd4741,
F4 = 14'd4475,
F4S = 14'd4223,
G4 = 14'd3986,
G4S = 14'd3763,
A4 = 14'd3552,
A4S = 14'd3352,
B4 = 14'd3164,
C5 = 14'd2987,
C5S = 14'd2819,
D5 = 14'd2661,
D5S = 14'd2511,
E5 = 14'd2370,
F5 = 14'd2237,
F5S = 14'd2112,
G5 = 14'd1993,
G5S = 14'd1882,
A5 = 14'd1776,
A5S = 14'd1676,
B5 = 14'd1582,
C6 = 14'd1493,
C6S = 14'd1410,
D6 = 14'd1331,
D6S = 14'd1256,
E6 = 14'd1185,
F6 = 14'd1119,
F6S = 14'd1056,
G6 = 14'd997,
G6S = 14'd941,
A6 = 14'd888,
A6S = 14'd838,
B6 = 14'd791;
assign sixty_fourth_period =
(tone == 6'd0) ? REST:
(tone == 6'd1) ? C3 :
(tone == 6'd2) ? C3S :
(tone == 6'd3) ? D3 :
(tone == 6'd4) ? D3S :
(tone == 6'd5) ? E3 :
(tone == 6'd6) ? F3 :
(tone == 6'd7) ? F3S :
(tone == 6'd8) ? G3 :
(tone == 6'd9) ? G3S :
(tone == 6'd10) ? A3 :
(tone == 6'd11) ? A3S :
(tone == 6'd12) ? B3 :
(tone == 6'd13) ? C4 :
(tone == 6'd14) ? C4S :
(tone == 6'd15) ? D4 :
(tone == 6'd16) ? D4S :
(tone == 6'd17) ? E4 :
(tone == 6'd18) ? F4 :
(tone == 6'd19) ? F4S :
(tone == 6'd20) ? G4 :
(tone == 6'd21) ? G4S :
(tone == 6'd22) ? A4 :
(tone == 6'd23) ? A4S :
(tone == 6'd24) ? B4 :
(tone == 6'd25) ? C5 :
(tone == 6'd26) ? C5S :
(tone == 6'd27) ? D5 :
(tone == 6'd28) ? D5S :
(tone == 6'd29) ? E5 :
(tone == 6'd30) ? F5 :
(tone == 6'd31) ? F5S :
(tone == 6'd32) ? G5 :
(tone == 6'd33) ? G5S :
(tone == 6'd34) ? A5 :
(tone == 6'd35) ? A5S :
(tone == 6'd36) ? B5 :
(tone == 6'd37) ? C6 :
(tone == 6'd38) ? C6S :
(tone == 6'd39) ? D6 :
(tone == 6'd40) ? D6S :
(tone == 6'd41) ? E6 :
(tone == 6'd42) ? F6 :
(tone == 6'd43) ? F6S :
(tone == 6'd44) ? G6 :
(tone == 6'd45) ? G6S :
(tone == 6'd46) ? A6 :
(tone == 6'd47) ? A6S :
(tone == 6'd48) ? B6 :
/*tone undefined*/ 0 ;
endmodule
|
//////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Ramdac Sync Generator
// File : syncs.v
// Author : Frank Bruno
// Created : 29-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
//////////////////////////////////////////////////////////////////////////////
//
// Description :
//
/////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module syncs
(
input crtclock, // CRT Clock
input pixclk, // Pixel Clock
input hresetn, // Global Reset
input sync_pwr, // Power Save: Disable Syncs
input sclk_pwr, // Power Save: Disable Sclk
input iclk_pwr, // Power Save: Disable Pix Clock
input vsyncin,
input hcsyncin,
input xor_sync,
input vsyn_invt,
input hsyn_invt,
input csyn_invt,
input sog,
input [1:0] hsyn_cntl,
input [1:0] vsyn_cntl,
input [3:0] hsyn_pos,
output syncn2dac,
output reg hsyncout,
output reg vsyncout
);
reg sync_pwr_crt0; // Synchronize pwr reg
reg sync_pwr_pix0; // Synchronize pwr reg
reg sclk_pwr_crt0; // Synchronize sclk
reg iclk_pwr_pix0; // Synchronize iclk
reg sync_pwr_crt; // Synchronize pwr reg
reg sync_pwr_pix; // Synchronize pwr reg
reg sclk_pwr_crt; // Synchronize sclk
reg iclk_pwr_pix; // Synchronize iclk
reg piped_sog;
reg piped_hsync;
reg hsync_l,
csync_l,
hsync_s,
csync_s,
hsync_x,
csync_x,
csync_1,
csync_2,
csync_3,
csync_4,
csync_5,
csync_11,
csync_12,
hsync_1,
hsync_2,
hsync_3,
hsync_4,
hsync_5,
hsync_11,
hsync_12,
piped_hsync1,
piped_hsync2,
piped_hsync3,
piped_hsync4,
piped_hsync5,
piped_hsync6,
piped_hsync7,
piped_hsync8,
piped_hsync9,
piped_hsynca,
piped_hsyncb,
piped_hsyncc,
piped_hsyncd,
piped_hsynce,
piped_csync1,
piped_csync2,
piped_csync3,
piped_csync4,
piped_csync5,
piped_csync6,
piped_csync7,
piped_csync8,
piped_csync9,
piped_csynca,
piped_csyncb,
piped_csyncc,
piped_csyncd,
piped_csynce;
assign syncn2dac = sog ? piped_sog : 1'b0;
// look for vdac sync control (is it pos active or neg active)
// wire hsync = (hsyn_invt | ext_sync_pol[0]) ? !hcsyncin : hcsyncin;
// wire csync = (csyn_invt | ext_sync_pol[2]) ? !hcsyncin : hcsyncin;
// wire vsync = (vsyn_invt | ext_sync_pol[1]) ? !vsyncin : vsyncin;
wire hsync = hsyn_invt ? !hcsyncin : hcsyncin;
wire csync = csyn_invt ? !hcsyncin : hcsyncin;
wire vsync = vsyn_invt ? !vsyncin : vsyncin;
wire composite = xor_sync ? (hsync ^ vsync) : csync;
wire h_out = sog ? composite : piped_hsync;
always@* begin
case(hsyn_cntl)
2'b10: hsyncout = 1'b0;
2'b01: hsyncout = 1'b1;
default: hsyncout = h_out;
endcase
end
always@* begin
case(vsyn_cntl)
2'b10: vsyncout = 1'b0;
2'b01: vsyncout = 1'b1;
default: vsyncout = vsync;
endcase
end
always @(posedge pixclk)
if (crtclock) begin
sync_pwr_crt0 <= sync_pwr;
sclk_pwr_crt0 <= sclk_pwr;
sync_pwr_crt <= sync_pwr_crt0;
sclk_pwr_crt <= sclk_pwr_crt0;
end
always @(posedge pixclk)
if (crtclock) begin
sync_pwr_pix0 <= sync_pwr;
iclk_pwr_pix0 <= iclk_pwr;
sync_pwr_pix <= sync_pwr_pix0;
iclk_pwr_pix <= iclk_pwr_pix0;
end
always @(posedge pixclk or negedge hresetn)
if (!hresetn) begin
csync_l <= 1'b0;
hsync_l <= 1'b0;
end else if (sync_pwr_crt && crtclock) begin
csync_l <= 1'b0;
hsync_l <= 1'b0;
end else if (crtclock) begin
csync_l <= composite;
hsync_l <= hsync ;
end
reg csync_sl, hsync_sl, hsync_10, csync_10;
always @(posedge pixclk or negedge hresetn)
if (!hresetn) begin
csync_s <= 1'b0;
hsync_s <= 1'b0;
csync_sl <= 1'b0;
hsync_sl <= 1'b0;
end else if (crtclock) begin
if (sync_pwr_crt | sclk_pwr_crt) begin
csync_s <= 1'b0;
hsync_s <= 1'b0;
csync_sl <= 1'b0;
hsync_sl <= 1'b0;
end else begin
csync_s <= csync_l;
hsync_s <= hsync_l;
csync_sl <= csync_s;
hsync_sl <= hsync_s;
end
end // if (crtclock)
always @(posedge pixclk or negedge hresetn)
if (!hresetn) begin
csync_x <= 1'b0;
csync_1 <= 1'b0;
csync_10 <= 1'b0;
csync_11 <= 1'b0;
csync_12 <= 1'b0;
csync_2 <= 1'b0;
csync_3 <= 1'b0;
csync_4 <= 1'b0;
csync_5 <= 1'b0;
hsync_x <= 1'b0;
hsync_1 <= 1'b0;
hsync_10 <= 1'b0;
hsync_11 <= 1'b0;
hsync_12 <= 1'b0;
hsync_2 <= 1'b0;
hsync_3 <= 1'b0;
hsync_4 <= 1'b0;
hsync_5 <= 1'b0;
piped_hsync1 <= 1'b0;
piped_hsync2 <= 1'b0;
piped_hsync3 <= 1'b0;
piped_hsync4 <= 1'b0;
piped_hsync5 <= 1'b0;
piped_hsync6 <= 1'b0;
piped_hsync7 <= 1'b0;
piped_hsync8 <= 1'b0;
piped_hsync9 <= 1'b0;
piped_hsynca <= 1'b0;
piped_hsyncb <= 1'b0;
piped_hsyncc <= 1'b0;
piped_hsyncd <= 1'b0;
piped_hsynce <= 1'b0;
piped_csync1 <= 1'b0;
piped_csync2 <= 1'b0;
piped_csync3 <= 1'b0;
piped_csync4 <= 1'b0;
piped_csync5 <= 1'b0;
piped_csync6 <= 1'b0;
piped_csync7 <= 1'b0;
piped_csync8 <= 1'b0;
piped_csync9 <= 1'b0;
piped_csynca <= 1'b0;
piped_csyncb <= 1'b0;
piped_csyncc <= 1'b0;
piped_csyncd <= 1'b0;
piped_csynce <= 1'b0;
end else if (sync_pwr_pix | iclk_pwr_pix) begin
csync_x <= 1'b0;
csync_1 <= 1'b0;
csync_10 <= 1'b0;
csync_11 <= 1'b0;
csync_12 <= 1'b0;
csync_2 <= 1'b0;
csync_3 <= 1'b0;
csync_4 <= 1'b0;
csync_5 <= 1'b0;
hsync_x <= 1'b0;
hsync_1 <= 1'b0;
hsync_10 <= 1'b0;
hsync_11 <= 1'b0;
hsync_12 <= 1'b0;
hsync_2 <= 1'b0;
hsync_3 <= 1'b0;
hsync_4 <= 1'b0;
hsync_5 <= 1'b0;
piped_hsync1 <= 1'b0;
piped_hsync2 <= 1'b0;
piped_hsync3 <= 1'b0;
piped_hsync4 <= 1'b0;
piped_hsync5 <= 1'b0;
piped_hsync6 <= 1'b0;
piped_hsync7 <= 1'b0;
piped_hsync8 <= 1'b0;
piped_hsync9 <= 1'b0;
piped_hsynca <= 1'b0;
piped_hsyncb <= 1'b0;
piped_hsyncc <= 1'b0;
piped_hsyncd <= 1'b0;
piped_hsynce <= 1'b0;
piped_csync1 <= 1'b0;
piped_csync2 <= 1'b0;
piped_csync3 <= 1'b0;
piped_csync4 <= 1'b0;
piped_csync5 <= 1'b0;
piped_csync6 <= 1'b0;
piped_csync7 <= 1'b0;
piped_csync8 <= 1'b0;
piped_csync9 <= 1'b0;
piped_csynca <= 1'b0;
piped_csyncb <= 1'b0;
piped_csyncc <= 1'b0;
piped_csyncd <= 1'b0;
piped_csynce <= 1'b0;
end else begin
csync_x <= csync_sl;
csync_1 <= csync_x;
csync_10 <= csync_1;
csync_11 <= csync_10;
csync_12 <= csync_11;
csync_2 <= csync_12;
csync_3 <= csync_2;
csync_4 <= csync_3;
csync_5 <= csync_4;
hsync_x <= hsync_sl;
hsync_1 <= hsync_x;
hsync_10 <= hsync_1;
hsync_11 <= hsync_10;
hsync_12 <= hsync_11;
hsync_2 <= hsync_12;
hsync_3 <= hsync_2;
hsync_4 <= hsync_3;
hsync_5 <= hsync_4;
piped_hsync1 <= hsync_5;
piped_hsync2 <= piped_hsync1;
piped_hsync3 <= piped_hsync2;
piped_hsync4 <= piped_hsync3;
piped_hsync5 <= piped_hsync4;
piped_hsync6 <= piped_hsync5;
piped_hsync7 <= piped_hsync6;
piped_hsync8 <= piped_hsync7;
piped_hsync9 <= piped_hsync8;
piped_hsynca <= piped_hsync9;
piped_hsyncb <= piped_hsynca;
piped_hsyncc <= piped_hsyncb;
piped_hsyncd <= piped_hsyncc;
piped_hsynce <= piped_hsyncd;
piped_csync1 <= csync_5;
piped_csync2 <= piped_csync1;
piped_csync3 <= piped_csync2;
piped_csync4 <= piped_csync3;
piped_csync5 <= piped_csync4;
piped_csync6 <= piped_csync5;
piped_csync7 <= piped_csync6;
piped_csync8 <= piped_csync7;
piped_csync9 <= piped_csync8;
piped_csynca <= piped_csync9;
piped_csyncb <= piped_csynca;
piped_csyncc <= piped_csyncb;
piped_csyncd <= piped_csyncc;
piped_csynce <= piped_csyncd;
end
// always @*
always @(posedge pixclk)
case(hsyn_pos)
4'b0000: piped_sog = csync_4; //csync_5;
4'b0001: piped_sog = csync_5; //piped_csync1;
4'b0010: piped_sog = piped_csync1;
4'b0011: piped_sog = piped_csync2;
4'b0100: piped_sog = piped_csync3;
4'b0101: piped_sog = piped_csync4;
4'b0110: piped_sog = piped_csync5;
4'b0111: piped_sog = piped_csync6;
4'b1000: piped_sog = piped_csync7;
4'b1001: piped_sog = piped_csync8;
4'b1010: piped_sog = piped_csync9;
4'b1011: piped_sog = piped_csynca;
4'b1100: piped_sog = piped_csyncb;
4'b1101: piped_sog = piped_csyncc;
4'b1110: piped_sog = piped_csyncd;
4'b1111: piped_sog = piped_csynce;
endcase
// always @*
always @(posedge pixclk)
case(hsyn_pos)
4'b0000: piped_hsync = hsync_4; // hsync_5;
4'b0001: piped_hsync = hsync_5; // piped_hsync1;
4'b0010: piped_hsync = piped_hsync1;
4'b0011: piped_hsync = piped_hsync2;
4'b0100: piped_hsync = piped_hsync3;
4'b0101: piped_hsync = piped_hsync4;
4'b0110: piped_hsync = piped_hsync5;
4'b0111: piped_hsync = piped_hsync6;
4'b1000: piped_hsync = piped_hsync7;
4'b1001: piped_hsync = piped_hsync8;
4'b1010: piped_hsync = piped_hsync9;
4'b1011: piped_hsync = piped_hsynca;
4'b1100: piped_hsync = piped_hsyncb;
4'b1101: piped_hsync = piped_hsyncc;
4'b1110: piped_hsync = piped_hsyncd;
4'b1111: piped_hsync = piped_hsynce;
endcase
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// DecWidthConverter16to32.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: Data width up converter
// Module Name: DecWidthConverter16to32
// File Name: DecWidthConverter16to32.v
//
// Version: v1.0.0
//
// Description: Data width up converting unit for decoder
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module DecWidthConverter16to32
#
(
parameter InputDataWidth = 16,
parameter OutputDataWidth = 32
)
(
iClock ,
iReset ,
iSrcDataValid ,
iSrcData ,
iSrcDataLast ,
oConverterReady ,
oConvertedDataValid ,
oConvertedData ,
oConvertedDataLast ,
iDstReady
);
input iClock ;
input iReset ;
input iSrcDataValid ;
input [InputDataWidth - 1:0] iSrcData ;
input iSrcDataLast ;
output oConverterReady ;
output oConvertedDataValid ;
output [OutputDataWidth - 1:0] oConvertedData ;
output oConvertedDataLast ;
input iDstReady ;
reg [InputDataWidth - 1:0] rShiftRegister ;
reg [InputDataWidth - 1:0] rInputRegister ;
reg rConvertedDataValid ;
reg rConvertedDataLast ;
localparam State_Idle = 4'b0001;
localparam State_Input = 4'b0010;
localparam State_Shift = 4'b0100;
localparam State_Pause = 4'b1000;
reg [3:0] rCurState;
reg [3:0] rNextState;
always @ (posedge iClock)
if (iReset)
rCurState <= State_Idle;
else
rCurState <= rNextState;
always @ (*)
case (rCurState)
State_Idle:
rNextState <= (iSrcDataValid) ? State_Input : State_Idle;
State_Input:
rNextState <= State_Shift;
State_Shift:
if (iDstReady)
begin
if (iSrcDataValid)
rNextState <= State_Input;
else
rNextState <= State_Idle;
end
else
rNextState <= State_Pause;
State_Pause:
if (iDstReady)
begin
if (iSrcDataValid)
rNextState <= State_Input;
else
rNextState <= State_Idle;
end
else
rNextState <= State_Pause;
default:
rNextState <= State_Idle;
endcase
always @ (posedge iClock)
if (iReset)
begin
rInputRegister <= 0;
rShiftRegister <= 0;
end
else
case (rNextState)
State_Idle:
begin
rInputRegister <= 0;
rShiftRegister <= 0;
end
State_Input:
begin
rInputRegister <= iSrcData;
rShiftRegister <= 0;
end
State_Shift:
begin
rInputRegister <= iSrcData;
rShiftRegister <= rInputRegister;
end
State_Pause:
begin
rInputRegister <= rInputRegister;
rShiftRegister <= rShiftRegister;
end
default:
begin
rInputRegister <= 0;
rShiftRegister <= 0;
end
endcase
always @ (posedge iClock)
if (iReset)
rConvertedDataValid <= 0;
else
case (rNextState)
State_Idle:
rConvertedDataValid <= 0;
State_Input:
rConvertedDataValid <= 0;
default:
rConvertedDataValid <= 1'b1;
endcase
always @ (posedge iClock)
if (iReset)
rConvertedDataLast <= 0;
else
if (iSrcDataLast)
rConvertedDataLast <= 1'b1;
else
if (rConvertedDataValid && iDstReady && rConvertedDataLast)
rConvertedDataLast <= 1'b0;
assign oConvertedData = {rShiftRegister, rInputRegister};
assign oConvertedDataValid = rConvertedDataValid;
assign oConvertedDataLast = rConvertedDataLast;
assign oConverterReady = !(rNextState == State_Pause);
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPVGND2_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__TAPVGND2_PP_BLACKBOX_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__tapvgnd2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPVGND2_PP_BLACKBOX_V
|
// ====================================================================
// Radio-86RK FPGA REPLICA
//
// Copyright (C) 2011 Dmitry Tselikov
//
// This core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
//
// An open implementation of Radio-86RK home computer
//
// Author: Dmitry Tselikov http://bashkiria-2m.narod.ru/
//
// Minor changes for adaptation to SDRAM: Ivan Gorodetsky, 2014
//
// Design File: rk_wxeda.v
//
// Top level design file.
module rk_wxeda(
input clk48mhz,
input [3:0] KEY,
inout [15:0] DRAM_DQ, // SDRAM Data bus 16 Bits
output [11:0] DRAM_ADDR, // SDRAM Address bus 12 Bits
output DRAM_LDQM, // SDRAM Low-byte Data Mask
output DRAM_UDQM, // SDRAM High-byte Data Mask
output DRAM_WE_N, // SDRAM Write Enable
output DRAM_CAS_N, // SDRAM Column Address Strobe
output DRAM_RAS_N, // SDRAM Row Address Strobe
output DRAM_CS_N, // SDRAM Chip Select
output DRAM_BA_0, // SDRAM Bank Address 0
output DRAM_BA_1, // SDRAM Bank Address 0
output DRAM_CLK, // SDRAM Clock
output DRAM_CKE, // SDRAM Clock Enable
output VGA_HS,
output VGA_VS,
output [4:0] VGA_R,
output [5:0] VGA_G,
output [4:0] VGA_B,
inout PS2_CLK,
inout PS2_DAT,
input SD_DAT, // SD Card Data (MISO)
output SD_DAT3, // SD Card Data 3 (CSn)
output SD_CMD, // SD Card Command Signal (MOSI)
output SD_CLK, // SD Card Clock (SCK)
output UART_TXD,
input UART_RXD,
output BEEP
);
assign UART_TXD = 0;
//////////////////// RESET ////////////////////
reg[3:0] reset_cnt;
reg reset_n;
wire reset = ~reset_n;
always @(posedge clk48mhz) begin
if (KEY[0] && reset_cnt==4'd14)
reset_n <= 1'b1;
else begin
reset_n <= 1'b0;
reset_cnt <= reset_cnt+4'd1;
end
end
//////////////////// STEP & GO ////////////////////
reg stepkey;
reg onestep;
always @(posedge clk48mhz) begin
stepkey <= KEY[1];
onestep <= stepkey & ~KEY[1];
end
//////////////////// MEM ////////////////////
wire sram_msb = 0;
wire[7:0] rom_o;
assign DRAM_CLK=clk48mhz; // SDRAM Clock
assign DRAM_CKE=1; // SDRAM Clock Enable
wire[15:0] dramout;
SDRAM_Controller ramd(
.clk50mhz(clk48mhz), // Clock 50MHz
.reset(reset), // System reset
.DRAM_DQ(DRAM_DQ), // SDRAM Data bus 16 Bits
.DRAM_ADDR(DRAM_ADDR), // SDRAM Address bus 12 Bits
.DRAM_LDQM(DRAM_LDQM), // SDRAM Low-byte Data Mask
.DRAM_UDQM(DRAM_UDQM), // SDRAM High-byte Data Mask
.DRAM_WE_N(DRAM_WE_N), // SDRAM Write Enable
.DRAM_CAS_N(DRAM_CAS_N), // SDRAM Column Address Strobe
.DRAM_RAS_N(DRAM_RAS_N), // SDRAM Row Address Strobe
.DRAM_CS_N(DRAM_CS_N), // SDRAM Chip Select
.DRAM_BA_0(DRAM_BA_0), // SDRAM Bank Address 0
.DRAM_BA_1(DRAM_BA_1), // SDRAM Bank Address 1
.iaddr(vid_rd ? {3'b000,vid_addr[14:0]} : {3'b000,addrbus[14:0]}),
.idata(cpu_o),
.rd(vid_rd ? 1'b1 : cpu_rd&(!addrbus[15])),
.we_n(vid_rd? 1'b1 : cpu_wr_n|addrbus[15]),
.odata(dramout)
);
wire[7:0] mem_o = dramout[7:0];
biossd rom(.address({addrbus[11]|startup,addrbus[10:0]}), .clock(clk48mhz), .q(rom_o));
//////////////////// CPU ////////////////////
wire[15:0] addrbus;
wire[7:0] cpu_o;
wire cpu_sync;
wire cpu_rd;
wire cpu_wr_n;
wire cpu_int;
wire cpu_inta_n;
wire inte;
reg[7:0] cpu_i;
reg startup;
always @(*)
casex (addrbus[15:13])
3'b0xx: cpu_i = startup ? rom_o : mem_o;
3'b100: cpu_i = ppa1_o;
3'b101: cpu_i = sd_o;
3'b110: cpu_i = crt_o;
3'b111: cpu_i = rom_o;
endcase
wire ppa1_we_n = addrbus[15:13]!=3'b100|cpu_wr_n;
wire ppa2_we_n = addrbus[15:13]!=3'b101|cpu_wr_n;
wire crt_we_n = addrbus[15:13]!=3'b110|cpu_wr_n;
wire crt_rd_n = addrbus[15:13]!=3'b110|~cpu_rd;
wire dma_we_n = addrbus[15:13]!=3'b111|cpu_wr_n;
reg[4:0] cpu_cnt;
reg cpu_ce2;
reg[10:0] hldareg;
wire cpu_ce = cpu_ce2;
always @(posedge clk48mhz) begin
if(reset) begin cpu_cnt<=0; cpu_ce2<=0; hldareg=11'd0; end
else
if((hldareg[10:9]==2'b01)&&((cpu_rd==1)||(cpu_wr_n==0))) begin cpu_cnt<=0; cpu_ce2<=1; end
else
if(cpu_cnt<27) begin cpu_cnt <= cpu_cnt + 5'd1; cpu_ce2<=0; end
else begin cpu_cnt<=0; cpu_ce2<=~hlda; end
hldareg<={hldareg[9:0],hlda};
startup <= reset|(startup&~addrbus[15]);
end
k580wm80a CPU(.clk(clk48mhz), .ce(cpu_ce), .reset(reset),
.idata(cpu_i), .addr(addrbus), .sync(cpu_sync), .rd(cpu_rd), .wr_n(cpu_wr_n),
.intr(cpu_int), .inta_n(cpu_inta_n), .odata(cpu_o), .inte_o(inte));
//////////////////// VIDEO ////////////////////
wire[7:0] crt_o;
wire[3:0] vid_line;
wire[6:0] vid_char;
wire[15:0] vid_addr;
wire[3:0] dma_dack;
wire[7:0] dma_o;
wire[1:0] vid_lattr;
wire[1:0] vid_gattr;
wire vid_cce,vid_drq,vid_irq,hlda;
wire vid_lten,vid_vsp,vid_rvv,vid_hilight;
wire dma_owe_n,dma_ord_n,dma_oiowe_n,dma_oiord_n;
wire vid_hr, vid_vr;
wire vid_rd = ~dma_oiord_n;
k580wt57 dma(.clk(clk48mhz), .ce(vid_cce), .reset(reset),
.iaddr(addrbus[3:0]), .idata(cpu_o), .drq({1'b0,vid_drq,2'b00}), .iwe_n(dma_we_n), .ird_n(1'b1),
.hlda(hlda), .hrq(hlda), .dack(dma_dack), .odata(dma_o), .oaddr(vid_addr),
.owe_n(dma_owe_n), .ord_n(dma_ord_n), .oiowe_n(dma_oiowe_n), .oiord_n(dma_oiord_n) );
k580wg75 crt(.clk(clk48mhz), .ce(vid_cce),
.iaddr(addrbus[0]), .idata(cpu_o), .iwe_n(crt_we_n), .ird_n(crt_rd_n),
.vrtc(vid_vr), .hrtc(vid_hr), .dack(dma_dack[2]), .ichar(mem_o), .drq(vid_drq), .irq(vid_irq),
.odata(crt_o), .line(vid_line), .ochar(vid_char), .lten(vid_lten), .vsp(vid_vsp),
.rvv(vid_rvv), .hilight(vid_hilight), .lattr(vid_lattr), .gattr(vid_gattr) );
rk_video vid(.clk(clk48mhz),
.hr(VGA_HS), .vr(VGA_VS),
.r(VGA_R), .g(VGA_G), .b(VGA_B),
.hr_wg75(vid_hr), .vr_wg75(vid_vr), .cce(vid_cce),
.line(vid_line), .ichar(vid_char),
.vsp(vid_vsp), .lten(vid_lten), .rvv(vid_rvv)
);
//////////////////// KBD ////////////////////
wire[7:0] kbd_o;
wire[2:0] kbd_shift;
rk_kbd kbd(.clk(clk48mhz), .reset(reset), .ps2_clk(PS2_CLK), .ps2_dat(PS2_DAT),
.addr(~ppa1_a), .odata(kbd_o), .shift(kbd_shift));
//////////////////// SYS PPA ////////////////////
wire[7:0] ppa1_o;
wire[7:0] ppa1_a;
wire[7:0] ppa1_b;
wire[7:0] ppa1_c;
k580ww55 ppa1(.clk(clk48mhz), .reset(reset), .addr(addrbus[1:0]), .we_n(ppa1_we_n),
.idata(cpu_o), .odata(ppa1_o), .ipa(ppa1_a), .opa(ppa1_a),
.ipb(~kbd_o), .opb(ppa1_b), .ipc({~kbd_shift,tapein,ppa1_c[3:0]}), .opc(ppa1_c));
//////////////////// SOUND ////////////////////
reg tapein;
soundcodec sound(
.clk(clk48mhz),
.pulse(ppa1_c[0]^inte),
.reset_n(reset_n),
.o_pwm(BEEP)
);
//////////////////// SD CARD ////////////////////
reg sdcs;
reg sdclk;
reg sdcmd;
reg[6:0] sddata;
wire[7:0] sd_o = {sddata, SD_DAT};
assign SD_DAT3 = ~sdcs;
assign SD_CMD = sdcmd;
assign SD_CLK = sdclk;
always @(posedge clk48mhz or posedge reset) begin
if (reset) begin
sdcs <= 1'b0;
sdclk <= 1'b0;
sdcmd <= 1'h1;
end else begin
if (addrbus[0]==1'b0 && ~ppa2_we_n) sdcs <= cpu_o[0];
if (addrbus[0]==1'b1 && ~ppa2_we_n) begin
if (sdclk) sddata <= {sddata[5:0],SD_DAT};
sdcmd <= cpu_o[7];
sdclk <= 1'b0;
end
if (cpu_rd) sdclk <= 1'b1;
end
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIeGen2x8If128_pcie_7x.v
// Version : 3.2
//
// Description: Solution wrapper for Virtex7 Hard Block for PCI Express
//
//
//
//--------------------------------------------------------------------------------
`ifndef PCIE_2LM
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module PCIeGen2x8If128_pcie_7x # (
// PCIE_2_1 params
parameter [11:0] AER_BASE_PTR = 12'h140,
parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
parameter [15:0] AER_CAP_ID = 16'h0001,
parameter AER_CAP_MULTIHEADER = "FALSE",
parameter [11:0] AER_CAP_NEXTPTR = 12'h178,
parameter AER_CAP_ON = "FALSE",
parameter [23:0] AER_CAP_OPTIONAL_ERR_SUPPORT = 24'h000000,
parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE",
parameter [3:0] AER_CAP_VERSION = 4'h1,
parameter ALLOW_X8_GEN2 = "FALSE",
parameter [31:0] BAR0 = 32'hFFFFFF00,
parameter [31:0] BAR1 = 32'hFFFF0000,
parameter [31:0] BAR2 = 32'hFFFF000C,
parameter [31:0] BAR3 = 32'hFFFFFFFF,
parameter [31:0] BAR4 = 32'h00000000,
parameter [31:0] BAR5 = 32'h00000000,
parameter [7:0] CAPABILITIES_PTR = 8'h40,
parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000,
parameter CFG_ECRC_ERR_CPLSTAT = 0,
parameter [23:0] CLASS_CODE = 24'h000000,
parameter CMD_INTX_IMPLEMENTED = "TRUE",
parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE",
parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h0,
parameter [6:0] CRM_MODULE_RSTS = 7'h00,
parameter C_DATA_WIDTH = 64,
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1,
parameter KEEP_WIDTH = C_DATA_WIDTH / 8,
parameter DEV_CAP2_ARI_FORWARDING_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED = "FALSE",
parameter DEV_CAP2_CAS128_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED = "FALSE",
parameter DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED = "FALSE",
parameter DEV_CAP2_LTR_MECHANISM_SUPPORTED = "FALSE",
parameter [1:0] DEV_CAP2_MAX_ENDEND_TLP_PREFIXES = 2'h0,
parameter DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING = "FALSE",
parameter [1:0] DEV_CAP2_TPH_COMPLETER_SUPPORTED = 2'h0,
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE",
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE",
parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0,
parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 0,
parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE",
parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE",
parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2,
parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0,
parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE",
parameter integer DEV_CAP_RSVD_14_12 = 0,
parameter integer DEV_CAP_RSVD_17_16 = 0,
parameter integer DEV_CAP_RSVD_31_29 = 0,
parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE",
parameter DEV_CONTROL_EXT_TAG_DEFAULT = "FALSE",
parameter DISABLE_ASPM_L1_TIMER = "FALSE",
parameter DISABLE_BAR_FILTERING = "FALSE",
parameter DISABLE_ERR_MSG = "FALSE",
parameter DISABLE_ID_CHECK = "FALSE",
parameter DISABLE_LANE_REVERSAL = "FALSE",
parameter DISABLE_LOCKED_FILTER = "FALSE",
parameter DISABLE_PPM_FILTER = "FALSE",
parameter DISABLE_RX_POISONED_RESP = "FALSE",
parameter DISABLE_RX_TC_FILTER = "FALSE",
parameter DISABLE_SCRAMBLING = "FALSE",
parameter [7:0] DNSTREAM_LINK_NUM = 8'h00,
parameter [11:0] DSN_BASE_PTR = 12'h100,
parameter [15:0] DSN_CAP_ID = 16'h0003,
parameter [11:0] DSN_CAP_NEXTPTR = 12'h10C,
parameter DSN_CAP_ON = "TRUE",
parameter [3:0] DSN_CAP_VERSION = 4'h1,
parameter [10:0] ENABLE_MSG_ROUTE = 11'h000,
parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE",
parameter ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED = "FALSE",
parameter ENTER_RVRY_EI_L0 = "TRUE",
parameter EXIT_LOOPBACK_ON_EI = "TRUE",
parameter [31:0] EXPANSION_ROM = 32'hFFFFF001,
parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F,
parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF,
parameter [7:0] HEADER_TYPE = 8'h00,
parameter [4:0] INFER_EI = 5'h00,
parameter [7:0] INTERRUPT_PIN = 8'h01,
parameter INTERRUPT_STAT_AUTO = "TRUE",
parameter IS_SWITCH = "FALSE",
parameter [9:0] LAST_CONFIG_DWORD = 10'h3FF,
parameter LINK_CAP_ASPM_OPTIONALITY = "TRUE",
parameter integer LINK_CAP_ASPM_SUPPORT = 1,
parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE",
parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE",
parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7,
parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7,
parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE",
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1,
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08,
parameter integer LINK_CAP_RSVD_23 = 0,
parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE",
parameter integer LINK_CONTROL_RCB = 0,
parameter LINK_CTRL2_DEEMPHASIS = "FALSE",
parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE",
parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h2,
parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE",
parameter [14:0] LL_ACK_TIMEOUT = 15'h0000,
parameter LL_ACK_TIMEOUT_EN = "FALSE",
parameter integer LL_ACK_TIMEOUT_FUNC = 0,
parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000,
parameter LL_REPLAY_TIMEOUT_EN = "FALSE",
parameter integer LL_REPLAY_TIMEOUT_FUNC = 0,
parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'h01,
parameter MPS_FORCE = "FALSE",
parameter [7:0] MSIX_BASE_PTR = 8'h9C,
parameter [7:0] MSIX_CAP_ID = 8'h11,
parameter [7:0] MSIX_CAP_NEXTPTR = 8'h00,
parameter MSIX_CAP_ON = "FALSE",
parameter integer MSIX_CAP_PBA_BIR = 0,
parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h000,
parameter [7:0] MSI_BASE_PTR = 8'h48,
parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE",
parameter [7:0] MSI_CAP_ID = 8'h05,
parameter integer MSI_CAP_MULTIMSGCAP = 0,
parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0,
parameter [7:0] MSI_CAP_NEXTPTR = 8'h60,
parameter MSI_CAP_ON = "FALSE",
parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "TRUE",
parameter integer N_FTS_COMCLK_GEN1 = 255,
parameter integer N_FTS_COMCLK_GEN2 = 255,
parameter integer N_FTS_GEN1 = 255,
parameter integer N_FTS_GEN2 = 255,
parameter [7:0] PCIE_BASE_PTR = 8'h60,
parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10,
parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2,
parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0,
parameter [7:0] PCIE_CAP_NEXTPTR = 8'h9C,
parameter PCIE_CAP_ON = "TRUE",
parameter integer PCIE_CAP_RSVD_15_14 = 0,
parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE",
parameter integer PCIE_REVISION = 2,
parameter integer PL_AUTO_CONFIG = 0,
parameter PL_FAST_TRAIN = "FALSE",
parameter [14:0] PM_ASPML0S_TIMEOUT = 15'h0000,
parameter PM_ASPML0S_TIMEOUT_EN = "FALSE",
parameter integer PM_ASPML0S_TIMEOUT_FUNC = 0,
parameter PM_ASPM_FASTEXIT = "FALSE",
parameter [7:0] PM_BASE_PTR = 8'h40,
parameter integer PM_CAP_AUXCURRENT = 0,
parameter PM_CAP_D1SUPPORT = "TRUE",
parameter PM_CAP_D2SUPPORT = "TRUE",
parameter PM_CAP_DSI = "FALSE",
parameter [7:0] PM_CAP_ID = 8'h01,
parameter [7:0] PM_CAP_NEXTPTR = 8'h48,
parameter PM_CAP_ON = "TRUE",
parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F,
parameter PM_CAP_PME_CLOCK = "FALSE",
parameter integer PM_CAP_RSVD_04 = 0,
parameter integer PM_CAP_VERSION = 3,
parameter PM_CSR_B2B3 = "FALSE",
parameter PM_CSR_BPCCEN = "FALSE",
parameter PM_CSR_NOSOFTRST = "TRUE",
parameter [7:0] PM_DATA0 = 8'h01,
parameter [7:0] PM_DATA1 = 8'h01,
parameter [7:0] PM_DATA2 = 8'h01,
parameter [7:0] PM_DATA3 = 8'h01,
parameter [7:0] PM_DATA4 = 8'h01,
parameter [7:0] PM_DATA5 = 8'h01,
parameter [7:0] PM_DATA6 = 8'h01,
parameter [7:0] PM_DATA7 = 8'h01,
parameter [1:0] PM_DATA_SCALE0 = 2'h1,
parameter [1:0] PM_DATA_SCALE1 = 2'h1,
parameter [1:0] PM_DATA_SCALE2 = 2'h1,
parameter [1:0] PM_DATA_SCALE3 = 2'h1,
parameter [1:0] PM_DATA_SCALE4 = 2'h1,
parameter [1:0] PM_DATA_SCALE5 = 2'h1,
parameter [1:0] PM_DATA_SCALE6 = 2'h1,
parameter [1:0] PM_DATA_SCALE7 = 2'h1,
parameter PM_MF = "FALSE",
parameter [11:0] RBAR_BASE_PTR = 12'h178,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR0 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR1 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR2 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR3 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR4 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR5 = 5'h00,
parameter [15:0] RBAR_CAP_ID = 16'h0015,
parameter [2:0] RBAR_CAP_INDEX0 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX1 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX2 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX3 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX4 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX5 = 3'h0,
parameter [11:0] RBAR_CAP_NEXTPTR = 12'h000,
parameter RBAR_CAP_ON = "FALSE",
parameter [31:0] RBAR_CAP_SUP0 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP1 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP2 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP3 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP4 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP5 = 32'h00000000,
parameter [3:0] RBAR_CAP_VERSION = 4'h1,
parameter [2:0] RBAR_NUM = 3'h1,
parameter integer RECRC_CHK = 0,
parameter RECRC_CHK_TRIM = "FALSE",
parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE",
parameter [1:0] RP_AUTO_SPD = 2'h1,
parameter [4:0] RP_AUTO_SPD_LOOPCNT = 5'h1f,
parameter SELECT_DLL_IF = "FALSE",
parameter SIM_VERSION = "1.0",
parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE",
parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE",
parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE",
parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE",
parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE",
parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE",
parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE",
parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000,
parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE",
parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE",
parameter integer SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0,
parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00,
parameter integer SPARE_BIT0 = 0,
parameter integer SPARE_BIT1 = 0,
parameter integer SPARE_BIT2 = 0,
parameter integer SPARE_BIT3 = 0,
parameter integer SPARE_BIT4 = 0,
parameter integer SPARE_BIT5 = 0,
parameter integer SPARE_BIT6 = 0,
parameter integer SPARE_BIT7 = 0,
parameter integer SPARE_BIT8 = 0,
parameter [7:0] SPARE_BYTE0 = 8'h00,
parameter [7:0] SPARE_BYTE1 = 8'h00,
parameter [7:0] SPARE_BYTE2 = 8'h00,
parameter [7:0] SPARE_BYTE3 = 8'h00,
parameter [31:0] SPARE_WORD0 = 32'h00000000,
parameter [31:0] SPARE_WORD1 = 32'h00000000,
parameter [31:0] SPARE_WORD2 = 32'h00000000,
parameter [31:0] SPARE_WORD3 = 32'h00000000,
parameter SSL_MESSAGE_AUTO = "FALSE",
parameter TECRC_EP_INV = "FALSE",
parameter TL_RBYPASS = "FALSE",
parameter integer TL_RX_RAM_RADDR_LATENCY = 0,
parameter integer TL_RX_RAM_RDATA_LATENCY = 2,
parameter integer TL_RX_RAM_WRITE_LATENCY = 0,
parameter TL_TFC_DISABLE = "FALSE",
parameter TL_TX_CHECKS_DISABLE = "FALSE",
parameter integer TL_TX_RAM_RADDR_LATENCY = 0,
parameter integer TL_TX_RAM_RDATA_LATENCY = 2,
parameter integer TL_TX_RAM_WRITE_LATENCY = 0,
parameter TRN_DW = "FALSE",
parameter TRN_NP_FC = "FALSE",
parameter UPCONFIG_CAPABLE = "TRUE",
parameter UPSTREAM_FACING = "TRUE",
parameter UR_ATOMIC = "TRUE",
parameter UR_CFG1 = "TRUE",
parameter UR_INV_REQ = "TRUE",
parameter UR_PRS_RESPONSE = "TRUE",
parameter USER_CLK2_DIV2 = "FALSE",
parameter integer USER_CLK_FREQ = 3,
parameter USE_RID_PINS = "FALSE",
parameter VC0_CPL_INFINITE = "TRUE",
parameter [12:0] VC0_RX_RAM_LIMIT = 13'h03FF,
parameter integer VC0_TOTAL_CREDITS_CD = 127,
parameter integer VC0_TOTAL_CREDITS_CH = 31,
parameter integer VC0_TOTAL_CREDITS_NPD = 24,
parameter integer VC0_TOTAL_CREDITS_NPH = 12,
parameter integer VC0_TOTAL_CREDITS_PD = 288,
parameter integer VC0_TOTAL_CREDITS_PH = 32,
parameter integer VC0_TX_LASTPACKET = 31,
parameter [11:0] VC_BASE_PTR = 12'h10C,
parameter [15:0] VC_CAP_ID = 16'h0002,
parameter [11:0] VC_CAP_NEXTPTR = 12'h000,
parameter VC_CAP_ON = "FALSE",
parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE",
parameter [3:0] VC_CAP_VERSION = 4'h1,
parameter [11:0] VSEC_BASE_PTR = 12'h128,
parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234,
parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018,
parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1,
parameter [15:0] VSEC_CAP_ID = 16'h000B,
parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE",
parameter [11:0] VSEC_CAP_NEXTPTR = 12'h140,
parameter VSEC_CAP_ON = "FALSE",
parameter [3:0] VSEC_CAP_VERSION = 4'h1
)
(
input wire [C_DATA_WIDTH-1:0] trn_td,
input wire [REM_WIDTH-1:0] trn_trem,
input wire trn_tsof,
input wire trn_teof,
input wire trn_tsrc_rdy,
input wire trn_tsrc_dsc,
input wire trn_terrfwd,
input wire trn_tecrc_gen,
input wire trn_tstr,
input wire trn_tcfg_gnt,
input wire trn_rdst_rdy,
input wire trn_rnp_req,
input wire trn_rfcp_ret,
input wire trn_rnp_ok,
input wire [2:0] trn_fc_sel,
input wire [31:0] trn_tdllp_data,
input wire trn_tdllp_src_rdy,
input wire ll2_tlp_rcv,
input wire ll2_send_enter_l1,
input wire ll2_send_enter_l23,
input wire ll2_send_as_req_l1,
input wire ll2_send_pm_ack,
input wire [4:0] pl2_directed_lstate,
input wire ll2_suspend_now,
input wire tl2_ppm_suspend_req,
input wire tl2_aspm_suspend_credit_check,
input wire [1:0] pl_directed_link_change,
input wire [1:0] pl_directed_link_width,
input wire pl_directed_link_speed,
input wire pl_directed_link_auton,
input wire pl_upstream_prefer_deemph,
input wire pl_downstream_deemph_source,
input wire pl_directed_ltssm_new_vld,
input wire [5:0] pl_directed_ltssm_new,
input wire pl_directed_ltssm_stall,
input wire [1:0] pipe_rx0_char_is_k,
input wire [1:0] pipe_rx1_char_is_k,
input wire [1:0] pipe_rx2_char_is_k,
input wire [1:0] pipe_rx3_char_is_k,
input wire [1:0] pipe_rx4_char_is_k,
input wire [1:0] pipe_rx5_char_is_k,
input wire [1:0] pipe_rx6_char_is_k,
input wire [1:0] pipe_rx7_char_is_k,
input wire pipe_rx0_valid,
input wire pipe_rx1_valid,
input wire pipe_rx2_valid,
input wire pipe_rx3_valid,
input wire pipe_rx4_valid,
input wire pipe_rx5_valid,
input wire pipe_rx6_valid,
input wire pipe_rx7_valid,
input wire [15:0] pipe_rx0_data,
input wire [15:0] pipe_rx1_data,
input wire [15:0] pipe_rx2_data,
input wire [15:0] pipe_rx3_data,
input wire [15:0] pipe_rx4_data,
input wire [15:0] pipe_rx5_data,
input wire [15:0] pipe_rx6_data,
input wire [15:0] pipe_rx7_data,
input wire pipe_rx0_chanisaligned,
input wire pipe_rx1_chanisaligned,
input wire pipe_rx2_chanisaligned,
input wire pipe_rx3_chanisaligned,
input wire pipe_rx4_chanisaligned,
input wire pipe_rx5_chanisaligned,
input wire pipe_rx6_chanisaligned,
input wire pipe_rx7_chanisaligned,
input wire [2:0] pipe_rx0_status,
input wire [2:0] pipe_rx1_status,
input wire [2:0] pipe_rx2_status,
input wire [2:0] pipe_rx3_status,
input wire [2:0] pipe_rx4_status,
input wire [2:0] pipe_rx5_status,
input wire [2:0] pipe_rx6_status,
input wire [2:0] pipe_rx7_status,
input wire pipe_rx0_phy_status,
input wire pipe_rx1_phy_status,
input wire pipe_rx2_phy_status,
input wire pipe_rx3_phy_status,
input wire pipe_rx4_phy_status,
input wire pipe_rx5_phy_status,
input wire pipe_rx6_phy_status,
input wire pipe_rx7_phy_status,
input wire pipe_rx0_elec_idle,
input wire pipe_rx1_elec_idle,
input wire pipe_rx2_elec_idle,
input wire pipe_rx3_elec_idle,
input wire pipe_rx4_elec_idle,
input wire pipe_rx5_elec_idle,
input wire pipe_rx6_elec_idle,
input wire pipe_rx7_elec_idle,
input wire pipe_clk,
input wire user_clk,
input wire user_clk2,
input wire user_clk_prebuf,
input wire user_clk_prebuf_en,
`ifdef B_TESTMODE
input wire scanmode_n,
input wire scanenable_n,
input wire edt_clk,
input wire edt_bypass,
input wire edt_update,
input wire edt_configuration,
input wire edt_single_bypass_chain,
input wire edt_channels_in1,
input wire edt_channels_in2,
input wire edt_channels_in3,
input wire edt_channels_in4,
input wire edt_channels_in5,
input wire edt_channels_in6,
input wire edt_channels_in7,
input wire edt_channels_in8,
input wire pmv_enable_n,
input wire [2:0] pmv_select,
input wire [1:0] pmv_divide,
`endif
input wire sys_rst_n,
input wire cm_rst_n,
input wire cm_sticky_rst_n,
input wire func_lvl_rst_n,
input wire tl_rst_n,
input wire dl_rst_n,
input wire pl_rst_n,
input wire pl_transmit_hot_rst,
// input wire cfg_reset,
// input wire gwe,
// input wire grestore,
// input wire ghigh,
input wire [31:0] cfg_mgmt_di,
input wire [3:0] cfg_mgmt_byte_en_n,
input wire [9:0] cfg_mgmt_dwaddr,
input wire cfg_mgmt_wr_rw1c_as_rw_n,
input wire cfg_mgmt_wr_readonly_n,
input wire cfg_mgmt_wr_en_n,
input wire cfg_mgmt_rd_en_n,
input wire cfg_err_malformed_n,
input wire cfg_err_cor_n,
input wire cfg_err_ur_n,
input wire cfg_err_ecrc_n,
input wire cfg_err_cpl_timeout_n,
input wire cfg_err_cpl_abort_n,
input wire cfg_err_cpl_unexpect_n,
input wire cfg_err_poisoned_n,
input wire cfg_err_acs_n,
input wire cfg_err_atomic_egress_blocked_n,
input wire cfg_err_mc_blocked_n,
input wire cfg_err_internal_uncor_n,
input wire cfg_err_internal_cor_n,
input wire cfg_err_posted_n,
input wire cfg_err_locked_n,
input wire cfg_err_norecovery_n,
input wire [127:0] cfg_err_aer_headerlog,
input wire [47:0] cfg_err_tlp_cpl_header,
input wire cfg_interrupt_n,
input wire [7:0] cfg_interrupt_di,
input wire cfg_interrupt_assert_n,
input wire cfg_interrupt_stat_n,
input wire [7:0] cfg_ds_bus_number,
input wire [4:0] cfg_ds_device_number,
input wire [2:0] cfg_ds_function_number,
input wire [7:0] cfg_port_number,
input wire cfg_pm_halt_aspm_l0s_n,
input wire cfg_pm_halt_aspm_l1_n,
input wire cfg_pm_force_state_en_n,
input wire [1:0] cfg_pm_force_state,
input wire cfg_pm_wake_n,
input wire cfg_pm_turnoff_ok_n,
input wire cfg_pm_send_pme_to_n,
input wire [4:0] cfg_pciecap_interrupt_msgnum,
input wire cfg_trn_pending_n,
input wire [2:0] cfg_force_mps,
input wire cfg_force_common_clock_off,
input wire cfg_force_extended_sync_on,
input wire [63:0] cfg_dsn,
input wire [4:0] cfg_aer_interrupt_msgnum,
input wire [15:0] cfg_dev_id,
input wire [15:0] cfg_vend_id,
input wire [7:0] cfg_rev_id,
input wire [15:0] cfg_subsys_id,
input wire [15:0] cfg_subsys_vend_id,
input wire drp_clk,
input wire drp_en,
input wire drp_we,
input wire [8:0] drp_addr,
input wire [15:0] drp_di,
input wire [1:0] dbg_mode,
input wire dbg_sub_mode,
input wire [2:0] pl_dbg_mode,
output wire trn_clk,
output wire trn_tdst_rdy,
output wire trn_terr_drop,
output wire [5:0] trn_tbuf_av,
output wire trn_tcfg_req,
//output wire [C_DATA_WIDTH-1:0] trn_rd,
output wire [127:0] trn_rd,
output wire [1:0] trn_rrem,
output wire trn_rsof,
output wire trn_reof,
output wire trn_rsrc_rdy,
output wire trn_rsrc_dsc,
output wire trn_recrc_err,
output wire trn_rerrfwd,
output wire [7:0] trn_rbar_hit,
output wire trn_lnk_up,
output wire [7:0] trn_fc_ph,
output wire [11:0] trn_fc_pd,
output wire [7:0] trn_fc_nph,
output wire [11:0] trn_fc_npd,
output wire [7:0] trn_fc_cplh,
output wire [11:0] trn_fc_cpld,
output wire trn_tdllp_dst_rdy,
output wire [63:0] trn_rdllp_data,
output wire [1:0] trn_rdllp_src_rdy,
output wire ll2_tfc_init1_seq,
output wire ll2_tfc_init2_seq,
output wire pl2_suspend_ok,
output wire pl2_recovery,
output wire pl2_rx_elec_idle,
output wire [1:0] pl2_rx_pm_state,
output wire pl2_l0_req,
output wire ll2_suspend_ok,
output wire ll2_tx_idle,
output wire [4:0] ll2_link_status,
output wire tl2_ppm_suspend_ok,
output wire tl2_aspm_suspend_req,
output wire tl2_aspm_suspend_credit_check_ok,
output wire pl2_link_up,
output wire pl2_receiver_err,
output wire ll2_receiver_err,
output wire ll2_protocol_err,
output wire ll2_bad_tlp_err,
output wire ll2_bad_dllp_err,
output wire ll2_replay_ro_err,
output wire ll2_replay_to_err,
output wire [63:0] tl2_err_hdr,
output wire tl2_err_malformed,
output wire tl2_err_rxoverflow,
output wire tl2_err_fcpe,
output wire pl_sel_lnk_rate,
output wire [1:0] pl_sel_lnk_width,
output wire [5:0] pl_ltssm_state,
output wire [1:0] pl_lane_reversal_mode,
output wire pl_phy_lnk_up_n,
output wire [2:0] pl_tx_pm_state,
output wire [1:0] pl_rx_pm_state,
output wire pl_link_upcfg_cap,
output wire pl_link_gen2_cap,
output wire pl_link_partner_gen2_supported,
output wire [2:0] pl_initial_link_width,
output wire pl_directed_change_done,
output wire pipe_tx_rcvr_det,
output wire pipe_tx_reset,
output wire pipe_tx_rate,
output wire pipe_tx_deemph,
output wire [2:0] pipe_tx_margin,
output wire pipe_rx0_polarity,
output wire pipe_rx1_polarity,
output wire pipe_rx2_polarity,
output wire pipe_rx3_polarity,
output wire pipe_rx4_polarity,
output wire pipe_rx5_polarity,
output wire pipe_rx6_polarity,
output wire pipe_rx7_polarity,
output wire pipe_tx0_compliance,
output wire pipe_tx1_compliance,
output wire pipe_tx2_compliance,
output wire pipe_tx3_compliance,
output wire pipe_tx4_compliance,
output wire pipe_tx5_compliance,
output wire pipe_tx6_compliance,
output wire pipe_tx7_compliance,
output wire [1:0] pipe_tx0_char_is_k,
output wire [1:0] pipe_tx1_char_is_k,
output wire [1:0] pipe_tx2_char_is_k,
output wire [1:0] pipe_tx3_char_is_k,
output wire [1:0] pipe_tx4_char_is_k,
output wire [1:0] pipe_tx5_char_is_k,
output wire [1:0] pipe_tx6_char_is_k,
output wire [1:0] pipe_tx7_char_is_k,
output wire [15:0] pipe_tx0_data,
output wire [15:0] pipe_tx1_data,
output wire [15:0] pipe_tx2_data,
output wire [15:0] pipe_tx3_data,
output wire [15:0] pipe_tx4_data,
output wire [15:0] pipe_tx5_data,
output wire [15:0] pipe_tx6_data,
output wire [15:0] pipe_tx7_data,
output wire pipe_tx0_elec_idle,
output wire pipe_tx1_elec_idle,
output wire pipe_tx2_elec_idle,
output wire pipe_tx3_elec_idle,
output wire pipe_tx4_elec_idle,
output wire pipe_tx5_elec_idle,
output wire pipe_tx6_elec_idle,
output wire pipe_tx7_elec_idle,
output wire [1:0] pipe_tx0_powerdown,
output wire [1:0] pipe_tx1_powerdown,
output wire [1:0] pipe_tx2_powerdown,
output wire [1:0] pipe_tx3_powerdown,
output wire [1:0] pipe_tx4_powerdown,
output wire [1:0] pipe_tx5_powerdown,
output wire [1:0] pipe_tx6_powerdown,
output wire [1:0] pipe_tx7_powerdown,
`ifdef B_TESTMODE
output wire pmv_out,
`endif
output wire user_rst_n,
output wire pl_received_hot_rst,
output wire received_func_lvl_rst_n,
output wire lnk_clk_en,
output wire [31:0] cfg_mgmt_do,
output wire cfg_mgmt_rd_wr_done_n,
output wire cfg_err_aer_headerlog_set_n,
output wire cfg_err_cpl_rdy_n,
output wire cfg_interrupt_rdy_n,
output wire [2:0] cfg_interrupt_mmenable,
output wire cfg_interrupt_msienable,
output wire [7:0] cfg_interrupt_do,
output wire cfg_interrupt_msixenable,
output wire cfg_interrupt_msixfm,
output wire cfg_msg_received,
output wire [15:0] cfg_msg_data,
output wire cfg_msg_received_err_cor,
output wire cfg_msg_received_err_non_fatal,
output wire cfg_msg_received_err_fatal,
output wire cfg_msg_received_assert_int_a,
output wire cfg_msg_received_deassert_int_a,
output wire cfg_msg_received_assert_int_b,
output wire cfg_msg_received_deassert_int_b,
output wire cfg_msg_received_assert_int_c,
output wire cfg_msg_received_deassert_int_c,
output wire cfg_msg_received_assert_int_d,
output wire cfg_msg_received_deassert_int_d,
output wire cfg_msg_received_pm_pme,
output wire cfg_msg_received_pme_to_ack,
output wire cfg_msg_received_pme_to,
output wire cfg_msg_received_setslotpowerlimit,
output wire cfg_msg_received_unlock,
output wire cfg_msg_received_pm_as_nak,
output wire [2:0] cfg_pcie_link_state,
output wire cfg_pm_rcv_as_req_l1_n,
output wire cfg_pm_rcv_enter_l1_n,
output wire cfg_pm_rcv_enter_l23_n,
output wire cfg_pm_rcv_req_ack_n,
output wire [1:0] cfg_pmcsr_powerstate,
output wire cfg_pmcsr_pme_en,
output wire cfg_pmcsr_pme_status,
output wire cfg_transaction,
output wire cfg_transaction_type,
output wire [6:0] cfg_transaction_addr,
output wire cfg_command_io_enable,
output wire cfg_command_mem_enable,
output wire cfg_command_bus_master_enable,
output wire cfg_command_interrupt_disable,
output wire cfg_command_serr_en,
output wire cfg_bridge_serr_en,
output wire cfg_dev_status_corr_err_detected,
output wire cfg_dev_status_non_fatal_err_detected,
output wire cfg_dev_status_fatal_err_detected,
output wire cfg_dev_status_ur_detected,
output wire cfg_dev_control_corr_err_reporting_en,
output wire cfg_dev_control_non_fatal_reporting_en,
output wire cfg_dev_control_fatal_err_reporting_en,
output wire cfg_dev_control_ur_err_reporting_en,
output wire cfg_dev_control_enable_ro,
output wire [2:0] cfg_dev_control_max_payload,
output wire cfg_dev_control_ext_tag_en,
output wire cfg_dev_control_phantom_en,
output wire cfg_dev_control_aux_power_en,
output wire cfg_dev_control_no_snoop_en,
output wire [2:0] cfg_dev_control_max_read_req,
output wire [1:0] cfg_link_status_current_speed,
output wire [3:0] cfg_link_status_negotiated_width,
output wire cfg_link_status_link_training,
output wire cfg_link_status_dll_active,
output wire cfg_link_status_bandwidth_status,
output wire cfg_link_status_auto_bandwidth_status,
output wire [1:0] cfg_link_control_aspm_control,
output wire cfg_link_control_rcb,
output wire cfg_link_control_link_disable,
output wire cfg_link_control_retrain_link,
output wire cfg_link_control_common_clock,
output wire cfg_link_control_extended_sync,
output wire cfg_link_control_clock_pm_en,
output wire cfg_link_control_hw_auto_width_dis,
output wire cfg_link_control_bandwidth_int_en,
output wire cfg_link_control_auto_bandwidth_int_en,
output wire [3:0] cfg_dev_control2_cpl_timeout_val,
output wire cfg_dev_control2_cpl_timeout_dis,
output wire cfg_dev_control2_ari_forward_en,
output wire cfg_dev_control2_atomic_requester_en,
output wire cfg_dev_control2_atomic_egress_block,
output wire cfg_dev_control2_ido_req_en,
output wire cfg_dev_control2_ido_cpl_en,
output wire cfg_dev_control2_ltr_en,
output wire cfg_dev_control2_tlp_prefix_block,
output wire cfg_slot_control_electromech_il_ctl_pulse,
output wire cfg_root_control_syserr_corr_err_en,
output wire cfg_root_control_syserr_non_fatal_err_en,
output wire cfg_root_control_syserr_fatal_err_en,
output wire cfg_root_control_pme_int_en,
output wire cfg_aer_ecrc_check_en,
output wire cfg_aer_ecrc_gen_en,
output wire cfg_aer_rooterr_corr_err_reporting_en,
output wire cfg_aer_rooterr_non_fatal_err_reporting_en,
output wire cfg_aer_rooterr_fatal_err_reporting_en,
output wire cfg_aer_rooterr_corr_err_received,
output wire cfg_aer_rooterr_non_fatal_err_received,
output wire cfg_aer_rooterr_fatal_err_received,
output wire [6:0] cfg_vc_tcvc_map,
output wire drp_rdy,
output wire [15:0] drp_do,
output wire [63:0] dbg_vec_a,
output wire [63:0] dbg_vec_b,
output wire [11:0] dbg_vec_c,
output wire dbg_sclr_a,
output wire dbg_sclr_b,
output wire dbg_sclr_c,
output wire dbg_sclr_d,
output wire dbg_sclr_e,
output wire dbg_sclr_f,
output wire dbg_sclr_g,
output wire dbg_sclr_h,
output wire dbg_sclr_i,
output wire dbg_sclr_j,
output wire dbg_sclr_k,
output wire [11:0] pl_dbg_vec
// output wire [18:0] xil_unconn_out
);
localparam TCQ = 1;
wire [3:0] trn_tdst_rdy_bus;
// Assignments to outputs
assign trn_clk = user_clk2;
assign trn_tdst_rdy = trn_tdst_rdy_bus[0];
//----------------------------------------------------------------------//
// BRAM //
//----------------------------------------------------------------------//
// transmit bram interface
wire mim_tx_wen;
wire [12:0] mim_tx_waddr;
wire [68:0] mim_tx_wdata;
wire mim_tx_ren;
wire mim_tx_rce;
wire [12:0] mim_tx_raddr;
wire [68:0] mim_tx_rdata;
wire [2:0] unused_mim_tx_rdata;
// receive bram interface
wire mim_rx_wen;
wire [12:0] mim_rx_waddr;
wire [67:0] mim_rx_wdata;
wire mim_rx_ren;
wire mim_rx_rce;
wire [12:0] mim_rx_raddr;
wire [67:0] mim_rx_rdata;
wire [3:0] unused_mim_rx_rdata;
PCIeGen2x8If128_pcie_bram_top_7x #(
.LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ),
.VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ),
.TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ),
.TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ),
.TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ),
.VC0_RX_RAM_LIMIT ( VC0_RX_RAM_LIMIT ),
.TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ),
.TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ),
.TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY )
) pcie_bram_top (
.user_clk_i ( user_clk ),
.reset_i ( 1'b0 ),
.mim_tx_waddr ( mim_tx_waddr ),
.mim_tx_wen ( mim_tx_wen ),
.mim_tx_ren ( mim_tx_ren ),
.mim_tx_rce ( 1'b1 ),
.mim_tx_wdata ( {3'b0, mim_tx_wdata} ),
.mim_tx_raddr ( mim_tx_raddr ),
.mim_tx_rdata ( {unused_mim_tx_rdata, mim_tx_rdata} ),
.mim_rx_waddr ( mim_rx_waddr ),
.mim_rx_wen ( mim_rx_wen ),
.mim_rx_ren ( mim_rx_ren ),
.mim_rx_rce ( 1'b1 ),
.mim_rx_wdata ( {4'b0, mim_rx_wdata} ),
.mim_rx_raddr ( mim_rx_raddr ),
.mim_rx_rdata ( {unused_mim_rx_rdata, mim_rx_rdata} )
);
//-------------------------------------------------------
// Virtex7 PCI Express Block Module
//-------------------------------------------------------
PCIE_2_1 #( // Verilog-2001
.AER_BASE_PTR ( AER_BASE_PTR ),
.AER_CAP_ECRC_CHECK_CAPABLE ( AER_CAP_ECRC_CHECK_CAPABLE ),
.AER_CAP_ECRC_GEN_CAPABLE ( AER_CAP_ECRC_GEN_CAPABLE ),
.AER_CAP_ID ( AER_CAP_ID ),
.AER_CAP_MULTIHEADER ( AER_CAP_MULTIHEADER ),
.AER_CAP_NEXTPTR ( AER_CAP_NEXTPTR ),
.AER_CAP_ON ( AER_CAP_ON ),
.AER_CAP_OPTIONAL_ERR_SUPPORT ( AER_CAP_OPTIONAL_ERR_SUPPORT ),
.AER_CAP_PERMIT_ROOTERR_UPDATE ( AER_CAP_PERMIT_ROOTERR_UPDATE ),
.AER_CAP_VERSION ( AER_CAP_VERSION ),
.ALLOW_X8_GEN2 ( ALLOW_X8_GEN2 ),
.BAR0 ( BAR0 ),
.BAR1 ( BAR1 ),
.BAR2 ( BAR2 ),
.BAR3 ( BAR3 ),
.BAR4 ( BAR4 ),
.BAR5 ( BAR5 ),
.CAPABILITIES_PTR ( CAPABILITIES_PTR ),
.CARDBUS_CIS_POINTER ( CARDBUS_CIS_POINTER ),
.CFG_ECRC_ERR_CPLSTAT ( CFG_ECRC_ERR_CPLSTAT ),
.CLASS_CODE ( CLASS_CODE ),
.CMD_INTX_IMPLEMENTED ( CMD_INTX_IMPLEMENTED ),
.CPL_TIMEOUT_DISABLE_SUPPORTED ( CPL_TIMEOUT_DISABLE_SUPPORTED ),
.CPL_TIMEOUT_RANGES_SUPPORTED ( CPL_TIMEOUT_RANGES_SUPPORTED ),
.CRM_MODULE_RSTS ( CRM_MODULE_RSTS ),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ),
.DEV_CAP_ENDPOINT_L0S_LATENCY ( DEV_CAP_ENDPOINT_L0S_LATENCY ),
.DEV_CAP_ENDPOINT_L1_LATENCY ( DEV_CAP_ENDPOINT_L1_LATENCY ),
.DEV_CAP_EXT_TAG_SUPPORTED ( DEV_CAP_EXT_TAG_SUPPORTED ),
.DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ( DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ),
.DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ),
.DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ( DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ),
.DEV_CAP_ROLE_BASED_ERROR ( DEV_CAP_ROLE_BASED_ERROR ),
.DEV_CAP_RSVD_14_12 ( DEV_CAP_RSVD_14_12 ),
.DEV_CAP_RSVD_17_16 ( DEV_CAP_RSVD_17_16 ),
.DEV_CAP_RSVD_31_29 ( DEV_CAP_RSVD_31_29 ),
.DEV_CAP2_ARI_FORWARDING_SUPPORTED ( DEV_CAP2_ARI_FORWARDING_SUPPORTED ),
.DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED ( DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED ),
.DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED ( DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED ),
.DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED ( DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED ),
.DEV_CAP2_CAS128_COMPLETER_SUPPORTED ( DEV_CAP2_CAS128_COMPLETER_SUPPORTED ),
.DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED ( DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED ),
.DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED ( DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED ),
.DEV_CAP2_LTR_MECHANISM_SUPPORTED ( DEV_CAP2_LTR_MECHANISM_SUPPORTED ),
.DEV_CAP2_MAX_ENDEND_TLP_PREFIXES ( DEV_CAP2_MAX_ENDEND_TLP_PREFIXES ),
.DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING ( DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING ),
.DEV_CAP2_TPH_COMPLETER_SUPPORTED ( DEV_CAP2_TPH_COMPLETER_SUPPORTED ),
.DEV_CONTROL_AUX_POWER_SUPPORTED ( DEV_CONTROL_AUX_POWER_SUPPORTED ),
.DEV_CONTROL_EXT_TAG_DEFAULT ( DEV_CONTROL_EXT_TAG_DEFAULT ),
.DISABLE_ASPM_L1_TIMER ( DISABLE_ASPM_L1_TIMER ),
.DISABLE_BAR_FILTERING ( DISABLE_BAR_FILTERING ),
.DISABLE_ERR_MSG ( DISABLE_ERR_MSG ),
.DISABLE_ID_CHECK ( DISABLE_ID_CHECK ),
.DISABLE_LANE_REVERSAL ( DISABLE_LANE_REVERSAL ),
.DISABLE_LOCKED_FILTER ( DISABLE_LOCKED_FILTER ),
.DISABLE_PPM_FILTER ( DISABLE_PPM_FILTER ),
.DISABLE_RX_POISONED_RESP ( DISABLE_RX_POISONED_RESP ),
.DISABLE_RX_TC_FILTER ( DISABLE_RX_TC_FILTER ),
.DISABLE_SCRAMBLING ( DISABLE_SCRAMBLING ),
.DNSTREAM_LINK_NUM ( DNSTREAM_LINK_NUM ),
.DSN_BASE_PTR ( DSN_BASE_PTR ),
.DSN_CAP_ID ( DSN_CAP_ID ),
.DSN_CAP_NEXTPTR ( DSN_CAP_NEXTPTR ),
.DSN_CAP_ON ( DSN_CAP_ON ),
.DSN_CAP_VERSION ( DSN_CAP_VERSION ),
.ENABLE_MSG_ROUTE ( ENABLE_MSG_ROUTE ),
.ENABLE_RX_TD_ECRC_TRIM ( ENABLE_RX_TD_ECRC_TRIM ),
.ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED ( ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED ),
.ENTER_RVRY_EI_L0 ( ENTER_RVRY_EI_L0 ),
.EXIT_LOOPBACK_ON_EI ( EXIT_LOOPBACK_ON_EI ),
.EXPANSION_ROM ( EXPANSION_ROM ),
.EXT_CFG_CAP_PTR ( EXT_CFG_CAP_PTR ),
.EXT_CFG_XP_CAP_PTR ( EXT_CFG_XP_CAP_PTR ),
.HEADER_TYPE ( HEADER_TYPE ),
.INFER_EI ( INFER_EI ),
.INTERRUPT_PIN ( INTERRUPT_PIN ),
.INTERRUPT_STAT_AUTO ( INTERRUPT_STAT_AUTO ),
.IS_SWITCH ( IS_SWITCH ),
.LAST_CONFIG_DWORD ( LAST_CONFIG_DWORD ),
.LINK_CAP_ASPM_OPTIONALITY ( LINK_CAP_ASPM_OPTIONALITY ),
.LINK_CAP_ASPM_SUPPORT ( LINK_CAP_ASPM_SUPPORT ),
.LINK_CAP_CLOCK_POWER_MANAGEMENT ( LINK_CAP_CLOCK_POWER_MANAGEMENT ),
.LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ( LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ),
.LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ( LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_GEN2 ),
.LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.LINK_CAP_RSVD_23 ( LINK_CAP_RSVD_23 ),
.LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ( LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ),
.LINK_CONTROL_RCB ( LINK_CONTROL_RCB ),
.LINK_CTRL2_DEEMPHASIS ( LINK_CTRL2_DEEMPHASIS ),
.LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ( LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ),
.LINK_CTRL2_TARGET_LINK_SPEED ( LINK_CTRL2_TARGET_LINK_SPEED ),
.LINK_STATUS_SLOT_CLOCK_CONFIG ( LINK_STATUS_SLOT_CLOCK_CONFIG ),
.LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ),
.LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ),
.LL_ACK_TIMEOUT_FUNC ( LL_ACK_TIMEOUT_FUNC ),
.LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ),
.LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ),
.LL_REPLAY_TIMEOUT_FUNC ( LL_REPLAY_TIMEOUT_FUNC ),
.LTSSM_MAX_LINK_WIDTH ( LTSSM_MAX_LINK_WIDTH ),
.MPS_FORCE ( MPS_FORCE ),
.MSI_BASE_PTR ( MSI_BASE_PTR ),
.MSI_CAP_ID ( MSI_CAP_ID ),
.MSI_CAP_MULTIMSG_EXTENSION ( MSI_CAP_MULTIMSG_EXTENSION ),
.MSI_CAP_MULTIMSGCAP ( MSI_CAP_MULTIMSGCAP ),
.MSI_CAP_NEXTPTR ( MSI_CAP_NEXTPTR ),
.MSI_CAP_ON ( MSI_CAP_ON ),
.MSI_CAP_PER_VECTOR_MASKING_CAPABLE ( MSI_CAP_PER_VECTOR_MASKING_CAPABLE ),
.MSI_CAP_64_BIT_ADDR_CAPABLE ( MSI_CAP_64_BIT_ADDR_CAPABLE ),
.MSIX_BASE_PTR ( MSIX_BASE_PTR ),
.MSIX_CAP_ID ( MSIX_CAP_ID ),
.MSIX_CAP_NEXTPTR ( MSIX_CAP_NEXTPTR ),
.MSIX_CAP_ON ( MSIX_CAP_ON ),
.MSIX_CAP_PBA_BIR ( MSIX_CAP_PBA_BIR ),
.MSIX_CAP_PBA_OFFSET ( MSIX_CAP_PBA_OFFSET ),
.MSIX_CAP_TABLE_BIR ( MSIX_CAP_TABLE_BIR ),
.MSIX_CAP_TABLE_OFFSET ( MSIX_CAP_TABLE_OFFSET ),
.MSIX_CAP_TABLE_SIZE ( MSIX_CAP_TABLE_SIZE ),
.N_FTS_COMCLK_GEN1 ( N_FTS_COMCLK_GEN1 ),
.N_FTS_COMCLK_GEN2 ( N_FTS_COMCLK_GEN2 ),
.N_FTS_GEN1 ( N_FTS_GEN1 ),
.N_FTS_GEN2 ( N_FTS_GEN2 ),
.PCIE_BASE_PTR ( PCIE_BASE_PTR ),
.PCIE_CAP_CAPABILITY_ID ( PCIE_CAP_CAPABILITY_ID ),
.PCIE_CAP_CAPABILITY_VERSION ( PCIE_CAP_CAPABILITY_VERSION ),
.PCIE_CAP_DEVICE_PORT_TYPE ( PCIE_CAP_DEVICE_PORT_TYPE ),
.PCIE_CAP_NEXTPTR ( PCIE_CAP_NEXTPTR ),
.PCIE_CAP_ON ( PCIE_CAP_ON ),
.PCIE_CAP_RSVD_15_14 ( PCIE_CAP_RSVD_15_14 ),
.PCIE_CAP_SLOT_IMPLEMENTED ( PCIE_CAP_SLOT_IMPLEMENTED ),
.PCIE_REVISION ( PCIE_REVISION ),
.PL_AUTO_CONFIG ( PL_AUTO_CONFIG ),
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
.PM_ASPML0S_TIMEOUT ( PM_ASPML0S_TIMEOUT ),
.PM_ASPML0S_TIMEOUT_EN ( PM_ASPML0S_TIMEOUT_EN ),
.PM_ASPML0S_TIMEOUT_FUNC ( PM_ASPML0S_TIMEOUT_FUNC ),
.PM_ASPM_FASTEXIT ( PM_ASPM_FASTEXIT ),
.PM_BASE_PTR ( PM_BASE_PTR ),
.PM_CAP_AUXCURRENT ( PM_CAP_AUXCURRENT ),
.PM_CAP_DSI ( PM_CAP_DSI ),
.PM_CAP_D1SUPPORT ( PM_CAP_D1SUPPORT ),
.PM_CAP_D2SUPPORT ( PM_CAP_D2SUPPORT ),
.PM_CAP_ID ( PM_CAP_ID ),
.PM_CAP_NEXTPTR ( PM_CAP_NEXTPTR ),
.PM_CAP_ON ( PM_CAP_ON ),
.PM_CAP_PME_CLOCK ( PM_CAP_PME_CLOCK ),
.PM_CAP_PMESUPPORT ( PM_CAP_PMESUPPORT ),
.PM_CAP_RSVD_04 ( PM_CAP_RSVD_04 ),
.PM_CAP_VERSION ( PM_CAP_VERSION ),
.PM_CSR_BPCCEN ( PM_CSR_BPCCEN ),
.PM_CSR_B2B3 ( PM_CSR_B2B3 ),
.PM_CSR_NOSOFTRST ( PM_CSR_NOSOFTRST ),
.PM_DATA_SCALE0 ( PM_DATA_SCALE0 ),
.PM_DATA_SCALE1 ( PM_DATA_SCALE1 ),
.PM_DATA_SCALE2 ( PM_DATA_SCALE2 ),
.PM_DATA_SCALE3 ( PM_DATA_SCALE3 ),
.PM_DATA_SCALE4 ( PM_DATA_SCALE4 ),
.PM_DATA_SCALE5 ( PM_DATA_SCALE5 ),
.PM_DATA_SCALE6 ( PM_DATA_SCALE6 ),
.PM_DATA_SCALE7 ( PM_DATA_SCALE7 ),
.PM_DATA0 ( PM_DATA0 ),
.PM_DATA1 ( PM_DATA1 ),
.PM_DATA2 ( PM_DATA2 ),
.PM_DATA3 ( PM_DATA3 ),
.PM_DATA4 ( PM_DATA4 ),
.PM_DATA5 ( PM_DATA5 ),
.PM_DATA6 ( PM_DATA6 ),
.PM_DATA7 ( PM_DATA7 ),
.PM_MF ( PM_MF ),
.RBAR_BASE_PTR ( RBAR_BASE_PTR ),
.RBAR_CAP_CONTROL_ENCODEDBAR0 ( RBAR_CAP_CONTROL_ENCODEDBAR0 ),
.RBAR_CAP_CONTROL_ENCODEDBAR1 ( RBAR_CAP_CONTROL_ENCODEDBAR1 ),
.RBAR_CAP_CONTROL_ENCODEDBAR2 ( RBAR_CAP_CONTROL_ENCODEDBAR2 ),
.RBAR_CAP_CONTROL_ENCODEDBAR3 ( RBAR_CAP_CONTROL_ENCODEDBAR3 ),
.RBAR_CAP_CONTROL_ENCODEDBAR4 ( RBAR_CAP_CONTROL_ENCODEDBAR4 ),
.RBAR_CAP_CONTROL_ENCODEDBAR5 ( RBAR_CAP_CONTROL_ENCODEDBAR5 ),
.RBAR_CAP_ID ( RBAR_CAP_ID ),
.RBAR_CAP_INDEX0 ( RBAR_CAP_INDEX0 ),
.RBAR_CAP_INDEX1 ( RBAR_CAP_INDEX1 ),
.RBAR_CAP_INDEX2 ( RBAR_CAP_INDEX2 ),
.RBAR_CAP_INDEX3 ( RBAR_CAP_INDEX3 ),
.RBAR_CAP_INDEX4 ( RBAR_CAP_INDEX4 ),
.RBAR_CAP_INDEX5 ( RBAR_CAP_INDEX5 ),
.RBAR_CAP_NEXTPTR ( RBAR_CAP_NEXTPTR ),
.RBAR_CAP_ON ( RBAR_CAP_ON ),
.RBAR_CAP_SUP0 ( RBAR_CAP_SUP0 ),
.RBAR_CAP_SUP1 ( RBAR_CAP_SUP1 ),
.RBAR_CAP_SUP2 ( RBAR_CAP_SUP2 ),
.RBAR_CAP_SUP3 ( RBAR_CAP_SUP3 ),
.RBAR_CAP_SUP4 ( RBAR_CAP_SUP4 ),
.RBAR_CAP_SUP5 ( RBAR_CAP_SUP5 ),
.RBAR_CAP_VERSION ( RBAR_CAP_VERSION ),
.RBAR_NUM ( RBAR_NUM ),
.RECRC_CHK ( RECRC_CHK ),
.RECRC_CHK_TRIM ( RECRC_CHK_TRIM ),
.ROOT_CAP_CRS_SW_VISIBILITY ( ROOT_CAP_CRS_SW_VISIBILITY ),
.RP_AUTO_SPD ( RP_AUTO_SPD ),
.RP_AUTO_SPD_LOOPCNT ( RP_AUTO_SPD_LOOPCNT ),
.SELECT_DLL_IF ( SELECT_DLL_IF ),
.SLOT_CAP_ATT_BUTTON_PRESENT ( SLOT_CAP_ATT_BUTTON_PRESENT ),
.SLOT_CAP_ATT_INDICATOR_PRESENT ( SLOT_CAP_ATT_INDICATOR_PRESENT ),
.SLOT_CAP_ELEC_INTERLOCK_PRESENT ( SLOT_CAP_ELEC_INTERLOCK_PRESENT ),
.SLOT_CAP_HOTPLUG_CAPABLE ( SLOT_CAP_HOTPLUG_CAPABLE ),
.SLOT_CAP_HOTPLUG_SURPRISE ( SLOT_CAP_HOTPLUG_SURPRISE ),
.SLOT_CAP_MRL_SENSOR_PRESENT ( SLOT_CAP_MRL_SENSOR_PRESENT ),
.SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ( SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ),
.SLOT_CAP_PHYSICAL_SLOT_NUM ( SLOT_CAP_PHYSICAL_SLOT_NUM ),
.SLOT_CAP_POWER_CONTROLLER_PRESENT ( SLOT_CAP_POWER_CONTROLLER_PRESENT ),
.SLOT_CAP_POWER_INDICATOR_PRESENT ( SLOT_CAP_POWER_INDICATOR_PRESENT ),
.SLOT_CAP_SLOT_POWER_LIMIT_SCALE ( SLOT_CAP_SLOT_POWER_LIMIT_SCALE ),
.SLOT_CAP_SLOT_POWER_LIMIT_VALUE ( SLOT_CAP_SLOT_POWER_LIMIT_VALUE ),
.SPARE_BIT0 ( SPARE_BIT0 ),
.SPARE_BIT1 ( SPARE_BIT1 ),
.SPARE_BIT2 ( SPARE_BIT2 ),
.SPARE_BIT3 ( SPARE_BIT3 ),
.SPARE_BIT4 ( SPARE_BIT4 ),
.SPARE_BIT5 ( SPARE_BIT5 ),
.SPARE_BIT6 ( SPARE_BIT6 ),
.SPARE_BIT7 ( SPARE_BIT7 ),
.SPARE_BIT8 ( SPARE_BIT8 ),
.SPARE_BYTE0 ( SPARE_BYTE0 ),
.SPARE_BYTE1 ( SPARE_BYTE1 ),
.SPARE_BYTE2 ( SPARE_BYTE2 ),
.SPARE_BYTE3 ( SPARE_BYTE3 ),
.SPARE_WORD0 ( SPARE_WORD0 ),
.SPARE_WORD1 ( SPARE_WORD1 ),
.SPARE_WORD2 ( SPARE_WORD2 ),
.SPARE_WORD3 ( SPARE_WORD3 ),
.SSL_MESSAGE_AUTO ( SSL_MESSAGE_AUTO ),
.TECRC_EP_INV ( TECRC_EP_INV ),
.TL_RBYPASS ( TL_RBYPASS ),
.TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ),
.TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ),
.TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ),
.TL_TFC_DISABLE ( TL_TFC_DISABLE ),
.TL_TX_CHECKS_DISABLE ( TL_TX_CHECKS_DISABLE ),
.TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ),
.TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ),
.TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ),
.TRN_DW ( TRN_DW ),
.TRN_NP_FC ( TRN_NP_FC ),
.UPCONFIG_CAPABLE ( UPCONFIG_CAPABLE ),
.UPSTREAM_FACING ( UPSTREAM_FACING ),
.UR_ATOMIC ( UR_ATOMIC ),
.UR_CFG1 ( UR_CFG1 ),
.UR_INV_REQ ( UR_INV_REQ ),
.UR_PRS_RESPONSE ( UR_PRS_RESPONSE ),
.USE_RID_PINS ( USE_RID_PINS ),
.USER_CLK_FREQ ( USER_CLK_FREQ ),
.USER_CLK2_DIV2 ( USER_CLK2_DIV2 ),
.VC_BASE_PTR ( VC_BASE_PTR ),
.VC_CAP_ID ( VC_CAP_ID ),
.VC_CAP_NEXTPTR ( VC_CAP_NEXTPTR ),
.VC_CAP_ON ( VC_CAP_ON ),
.VC_CAP_REJECT_SNOOP_TRANSACTIONS ( VC_CAP_REJECT_SNOOP_TRANSACTIONS ),
.VC_CAP_VERSION ( VC_CAP_VERSION ),
.VC0_CPL_INFINITE ( VC0_CPL_INFINITE ),
.VC0_RX_RAM_LIMIT ( VC0_RX_RAM_LIMIT ),
.VC0_TOTAL_CREDITS_CD ( VC0_TOTAL_CREDITS_CD ),
.VC0_TOTAL_CREDITS_CH ( VC0_TOTAL_CREDITS_CH ),
.VC0_TOTAL_CREDITS_NPD ( VC0_TOTAL_CREDITS_NPD ),
.VC0_TOTAL_CREDITS_NPH ( VC0_TOTAL_CREDITS_NPH ),
.VC0_TOTAL_CREDITS_PD ( VC0_TOTAL_CREDITS_PD ),
.VC0_TOTAL_CREDITS_PH ( VC0_TOTAL_CREDITS_PH ),
.VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ),
.VSEC_BASE_PTR ( VSEC_BASE_PTR ),
.VSEC_CAP_HDR_ID ( VSEC_CAP_HDR_ID ),
.VSEC_CAP_HDR_REVISION ( VSEC_CAP_HDR_REVISION ),
.VSEC_CAP_ID ( VSEC_CAP_ID ),
.VSEC_CAP_IS_LINK_VISIBLE ( VSEC_CAP_IS_LINK_VISIBLE ),
.VSEC_CAP_NEXTPTR ( VSEC_CAP_NEXTPTR ),
.VSEC_CAP_ON ( VSEC_CAP_ON ),
.VSEC_CAP_VERSION ( VSEC_CAP_VERSION )
`ifdef B_TESTMODE
,
.TEST_MODE_PIN_CHAR ( TEST_MODE_PIN_CHAR )
`endif
)
pcie_block_i (
.TRNTD (trn_td ),
.TRNTREM (trn_trem ),
.TRNTSOF (trn_tsof ),
.TRNTEOF (trn_teof ),
.TRNTSRCRDY (trn_tsrc_rdy ),
.TRNTSRCDSC (trn_tsrc_dsc ),
.TRNTERRFWD (trn_terrfwd ),
.TRNTECRCGEN (trn_tecrc_gen ),
.TRNTSTR (trn_tstr ),
.TRNTCFGGNT (trn_tcfg_gnt ),
.TRNRDSTRDY (trn_rdst_rdy ),
.TRNRNPREQ (trn_rnp_req ),
.TRNRFCPRET (trn_rfcp_ret ),
.TRNRNPOK (trn_rnp_ok ),
.TRNFCSEL (trn_fc_sel ),
.MIMTXRDATA (mim_tx_rdata ),
.MIMRXRDATA (mim_rx_rdata ),
.TRNTDLLPDATA (trn_tdllp_data ),
.TRNTDLLPSRCRDY (trn_tdllp_src_rdy ),
.LL2TLPRCV (ll2_tlp_rcv ),
.LL2SENDENTERL1 (ll2_send_enter_l1 ),
.LL2SENDENTERL23 (ll2_send_enter_l23 ),
.LL2SENDASREQL1 (ll2_send_as_req_l1 ),
.LL2SENDPMACK (ll2_send_pm_ack ),
.PL2DIRECTEDLSTATE (pl2_directed_lstate ),
.LL2SUSPENDNOW (ll2_suspend_now ),
.TL2PPMSUSPENDREQ (tl2_ppm_suspend_req ),
.TL2ASPMSUSPENDCREDITCHECK (tl2_aspm_suspend_credit_check ),
.PLDIRECTEDLINKCHANGE (pl_directed_link_change ),
.PLDIRECTEDLINKWIDTH (pl_directed_link_width ),
.PLDIRECTEDLINKSPEED (pl_directed_link_speed ),
.PLDIRECTEDLINKAUTON (pl_directed_link_auton ),
.PLUPSTREAMPREFERDEEMPH (pl_upstream_prefer_deemph ),
.PLDOWNSTREAMDEEMPHSOURCE (pl_downstream_deemph_source ),
.PLDIRECTEDLTSSMNEW (pl_directed_ltssm_new ),
.PLDIRECTEDLTSSMNEWVLD (pl_directed_ltssm_new_vld ),
.PLDIRECTEDLTSSMSTALL (pl_directed_ltssm_stall ),
.PIPERX0CHARISK (pipe_rx0_char_is_k ),
.PIPERX1CHARISK (pipe_rx1_char_is_k ),
.PIPERX2CHARISK (pipe_rx2_char_is_k ),
.PIPERX3CHARISK (pipe_rx3_char_is_k ),
.PIPERX4CHARISK (pipe_rx4_char_is_k ),
.PIPERX5CHARISK (pipe_rx5_char_is_k ),
.PIPERX6CHARISK (pipe_rx6_char_is_k ),
.PIPERX7CHARISK (pipe_rx7_char_is_k ),
.PIPERX0VALID (pipe_rx0_valid ),
.PIPERX1VALID (pipe_rx1_valid ),
.PIPERX2VALID (pipe_rx2_valid ),
.PIPERX3VALID (pipe_rx3_valid ),
.PIPERX4VALID (pipe_rx4_valid ),
.PIPERX5VALID (pipe_rx5_valid ),
.PIPERX6VALID (pipe_rx6_valid ),
.PIPERX7VALID (pipe_rx7_valid ),
.PIPERX0DATA (pipe_rx0_data ),
.PIPERX1DATA (pipe_rx1_data ),
.PIPERX2DATA (pipe_rx2_data ),
.PIPERX3DATA (pipe_rx3_data ),
.PIPERX4DATA (pipe_rx4_data ),
.PIPERX5DATA (pipe_rx5_data ),
.PIPERX6DATA (pipe_rx6_data ),
.PIPERX7DATA (pipe_rx7_data ),
.PIPERX0CHANISALIGNED (pipe_rx0_chanisaligned ),
.PIPERX1CHANISALIGNED (pipe_rx1_chanisaligned ),
.PIPERX2CHANISALIGNED (pipe_rx2_chanisaligned ),
.PIPERX3CHANISALIGNED (pipe_rx3_chanisaligned ),
.PIPERX4CHANISALIGNED (pipe_rx4_chanisaligned ),
.PIPERX5CHANISALIGNED (pipe_rx5_chanisaligned ),
.PIPERX6CHANISALIGNED (pipe_rx6_chanisaligned ),
.PIPERX7CHANISALIGNED (pipe_rx7_chanisaligned ),
.PIPERX0STATUS (pipe_rx0_status ),
.PIPERX1STATUS (pipe_rx1_status ),
.PIPERX2STATUS (pipe_rx2_status ),
.PIPERX3STATUS (pipe_rx3_status ),
.PIPERX4STATUS (pipe_rx4_status ),
.PIPERX5STATUS (pipe_rx5_status ),
.PIPERX6STATUS (pipe_rx6_status ),
.PIPERX7STATUS (pipe_rx7_status ),
.PIPERX0PHYSTATUS (pipe_rx0_phy_status ),
.PIPERX1PHYSTATUS (pipe_rx1_phy_status ),
.PIPERX2PHYSTATUS (pipe_rx2_phy_status ),
.PIPERX3PHYSTATUS (pipe_rx3_phy_status ),
.PIPERX4PHYSTATUS (pipe_rx4_phy_status ),
.PIPERX5PHYSTATUS (pipe_rx5_phy_status ),
.PIPERX6PHYSTATUS (pipe_rx6_phy_status ),
.PIPERX7PHYSTATUS (pipe_rx7_phy_status ),
.PIPERX0ELECIDLE (pipe_rx0_elec_idle ),
.PIPERX1ELECIDLE (pipe_rx1_elec_idle ),
.PIPERX2ELECIDLE (pipe_rx2_elec_idle ),
.PIPERX3ELECIDLE (pipe_rx3_elec_idle ),
.PIPERX4ELECIDLE (pipe_rx4_elec_idle ),
.PIPERX5ELECIDLE (pipe_rx5_elec_idle ),
.PIPERX6ELECIDLE (pipe_rx6_elec_idle ),
.PIPERX7ELECIDLE (pipe_rx7_elec_idle ),
.PIPECLK (pipe_clk ),
.USERCLK (user_clk ),
.USERCLK2 (user_clk2 ),
`ifdef VALIDATION
.USERCLKPREBUF (user_clk_prebuf ),
.USERCLKPREBUFEN (user_clk_prebuf_en ),
`endif
`ifdef B_TESTMODE
.USERCLKPREBUF (user_clk_prebuf ),
.USERCLKPREBUFEN (user_clk_prebuf_en ),
.SCANMODEN (scanmode_n ),
.SCANENABLEN (scanenable_n ),
.EDTCLK (edt_clk ),
.EDTUPDATE (edt_update ),
.EDTBYPASS (edt_bypass ),
.EDTCONFIGURATION (edt_configuration ),
.EDTSINGLEBYPASSCHAIN (edt_single_bypass_chain ),
.EDTCHANNELSIN1 (edt_channels_in1 ),
.EDTCHANNELSIN2 (edt_channels_in2 ),
.EDTCHANNELSIN3 (edt_channels_in3 ),
.EDTCHANNELSIN4 (edt_channels_in4 ),
.EDTCHANNELSIN5 (edt_channels_in5 ),
.EDTCHANNELSIN6 (edt_channels_in6 ),
.EDTCHANNELSIN7 (edt_channels_in7 ),
.EDTCHANNELSIN8 (edt_channels_in8 ),
.PMVENABLEN (pmv_enable_n ),
.PMVSELECT (pmv_select ),
.PMVDIVIDE (pmv_divide ),
`endif
//`ifdef SECUREIP
// .GSR (gsr ),
//`endif
.SYSRSTN (sys_rst_n ),
.CMRSTN (cm_rst_n ),
.CMSTICKYRSTN (cm_sticky_rst_n ),
.FUNCLVLRSTN (func_lvl_rst_n ),
.TLRSTN (tl_rst_n ),
.DLRSTN (dl_rst_n ),
.PLRSTN (pl_rst_n ),
.PLTRANSMITHOTRST (pl_transmit_hot_rst ),
// Global pins not on Holistic model
//.CFGRESET (cfg_reset ),
//.GWE (gwe ),
//.GRESTORE (grestore ),
//.GHIGHB (ghigh_b ),
.CFGMGMTDI (cfg_mgmt_di ),
.CFGMGMTBYTEENN (cfg_mgmt_byte_en_n ),
.CFGMGMTDWADDR (cfg_mgmt_dwaddr ),
.CFGMGMTWRRW1CASRWN (cfg_mgmt_wr_rw1c_as_rw_n ),
.CFGMGMTWRREADONLYN (cfg_mgmt_wr_readonly_n ),
.CFGMGMTWRENN (cfg_mgmt_wr_en_n ),
.CFGMGMTRDENN (cfg_mgmt_rd_en_n ),
.CFGERRMALFORMEDN (cfg_err_malformed_n ),
.CFGERRCORN (cfg_err_cor_n ),
.CFGERRURN (cfg_err_ur_n ),
.CFGERRECRCN (cfg_err_ecrc_n ),
.CFGERRCPLTIMEOUTN (cfg_err_cpl_timeout_n ),
.CFGERRCPLABORTN (cfg_err_cpl_abort_n ),
.CFGERRCPLUNEXPECTN (cfg_err_cpl_unexpect_n ),
.CFGERRPOISONEDN (cfg_err_poisoned_n ),
.CFGERRACSN (cfg_err_acs_n ),
.CFGERRATOMICEGRESSBLOCKEDN (cfg_err_atomic_egress_blocked_n ),
.CFGERRMCBLOCKEDN (cfg_err_mc_blocked_n ),
.CFGERRINTERNALUNCORN (cfg_err_internal_uncor_n ),
.CFGERRINTERNALCORN (cfg_err_internal_cor_n ),
.CFGERRPOSTEDN (cfg_err_posted_n ),
.CFGERRLOCKEDN (cfg_err_locked_n ),
.CFGERRNORECOVERYN (cfg_err_norecovery_n ),
.CFGERRAERHEADERLOG (cfg_err_aer_headerlog ),
.CFGERRTLPCPLHEADER (cfg_err_tlp_cpl_header ),
.CFGINTERRUPTN (cfg_interrupt_n ),
.CFGINTERRUPTDI (cfg_interrupt_di ),
.CFGINTERRUPTASSERTN (cfg_interrupt_assert_n ),
.CFGINTERRUPTSTATN (cfg_interrupt_stat_n ),
.CFGDSBUSNUMBER (cfg_ds_bus_number ),
.CFGDSDEVICENUMBER (cfg_ds_device_number ),
.CFGDSFUNCTIONNUMBER (cfg_ds_function_number ),
.CFGPORTNUMBER (cfg_port_number ),
.CFGPMHALTASPML0SN (cfg_pm_halt_aspm_l0s_n ),
.CFGPMHALTASPML1N (cfg_pm_halt_aspm_l1_n ),
.CFGPMFORCESTATEENN (cfg_pm_force_state_en_n ),
.CFGPMFORCESTATE (cfg_pm_force_state ),
.CFGPMWAKEN (cfg_pm_wake_n ),
.CFGPMTURNOFFOKN (cfg_pm_turnoff_ok_n ),
.CFGPMSENDPMETON (cfg_pm_send_pme_to_n ),
.CFGPCIECAPINTERRUPTMSGNUM (cfg_pciecap_interrupt_msgnum ),
.CFGTRNPENDINGN (cfg_trn_pending_n ),
.CFGFORCEMPS (cfg_force_mps ),
.CFGFORCECOMMONCLOCKOFF (cfg_force_common_clock_off ),
.CFGFORCEEXTENDEDSYNCON (cfg_force_extended_sync_on ),
.CFGDSN (cfg_dsn ),
.CFGDEVID (cfg_dev_id ),
.CFGVENDID (cfg_vend_id ),
.CFGREVID (cfg_rev_id ),
.CFGSUBSYSID (cfg_subsys_id ),
.CFGSUBSYSVENDID (cfg_subsys_vend_id ),
.CFGAERINTERRUPTMSGNUM (cfg_aer_interrupt_msgnum ),
.DRPCLK (drp_clk ),
.DRPEN (drp_en ),
.DRPWE (drp_we ),
.DRPADDR (drp_addr ),
.DRPDI (drp_di ),
//.DRPREADPORT0 (drp_read_port_0 ),
//.DRPREADPORT1 (drp_read_port_1 ),
//.DRPREADPORT2 (drp_read_port_2 ),
//.DRPREADPORT3 (drp_read_port_3 ),
//.DRPREADPORT4 (drp_read_port_4 ),
//.DRPREADPORT5 (drp_read_port_5 ),
//.DRPREADPORT6 (drp_read_port_6 ),
//.DRPREADPORT7 (drp_read_port_7 ),
//.DRPREADPORT8 (drp_read_port_8 ),
//.DRPREADPORT9 (drp_read_port_9 ),
//.DRPREADPORT10 (drp_read_port_10 ),
//.DRPREADPORT11 (drp_read_port_11 ),
//.DRPREADPORT12 (drp_read_port_12 ),
.DBGMODE (dbg_mode ),
.DBGSUBMODE (dbg_sub_mode ),
.PLDBGMODE (pl_dbg_mode ),
.TRNTDSTRDY (trn_tdst_rdy_bus ),
.TRNTERRDROP (trn_terr_drop ),
.TRNTBUFAV (trn_tbuf_av ),
.TRNTCFGREQ (trn_tcfg_req ),
.TRNRD (trn_rd ),
.TRNRREM (trn_rrem ),
.TRNRSOF (trn_rsof ),
.TRNREOF (trn_reof ),
.TRNRSRCRDY (trn_rsrc_rdy ),
.TRNRSRCDSC (trn_rsrc_dsc ),
.TRNRECRCERR (trn_recrc_err ),
.TRNRERRFWD (trn_rerrfwd ),
.TRNRBARHIT (trn_rbar_hit ),
.TRNLNKUP (trn_lnk_up ),
.TRNFCPH (trn_fc_ph ),
.TRNFCPD (trn_fc_pd ),
.TRNFCNPH (trn_fc_nph ),
.TRNFCNPD (trn_fc_npd ),
.TRNFCCPLH (trn_fc_cplh ),
.TRNFCCPLD (trn_fc_cpld ),
.MIMTXWDATA (mim_tx_wdata ),
.MIMTXWADDR (mim_tx_waddr ),
.MIMTXWEN (mim_tx_wen ),
.MIMTXRADDR (mim_tx_raddr ),
.MIMTXREN (mim_tx_ren ),
.MIMRXWDATA (mim_rx_wdata ),
.MIMRXWADDR (mim_rx_waddr ),
.MIMRXWEN (mim_rx_wen ),
.MIMRXRADDR (mim_rx_raddr ),
.MIMRXREN (mim_rx_ren ),
.TRNTDLLPDSTRDY (trn_tdllp_dst_rdy ),
.TRNRDLLPDATA (trn_rdllp_data ),
.TRNRDLLPSRCRDY (trn_rdllp_src_rdy ),
.LL2TFCINIT1SEQ (ll2_tfc_init1_seq ),
.LL2TFCINIT2SEQ (ll2_tfc_init2_seq ),
.PL2SUSPENDOK (pl2_suspend_ok ),
.PL2RECOVERY (pl2_recovery ),
.PL2RXELECIDLE (pl2_rx_elec_idle ),
.PL2RXPMSTATE (pl2_rx_pm_state ),
.PL2L0REQ (pl2_l0_req ),
.LL2SUSPENDOK (ll2_suspend_ok ),
.LL2TXIDLE (ll2_tx_idle ),
.LL2LINKSTATUS (ll2_link_status ),
.TL2PPMSUSPENDOK (tl2_ppm_suspend_ok ),
.TL2ASPMSUSPENDREQ (tl2_aspm_suspend_req ),
.TL2ASPMSUSPENDCREDITCHECKOK (tl2_aspm_suspend_credit_check_ok ),
.PL2LINKUP (pl2_link_up ),
.PL2RECEIVERERR (pl2_receiver_err ),
.LL2RECEIVERERR (ll2_receiver_err ),
.LL2PROTOCOLERR (ll2_protocol_err ),
.LL2BADTLPERR (ll2_bad_tlp_err ),
.LL2BADDLLPERR (ll2_bad_dllp_err ),
.LL2REPLAYROERR (ll2_replay_ro_err ),
.LL2REPLAYTOERR (ll2_replay_to_err ),
.TL2ERRHDR (tl2_err_hdr ),
.TL2ERRMALFORMED (tl2_err_malformed ),
.TL2ERRRXOVERFLOW (tl2_err_rxoverflow ),
.TL2ERRFCPE (tl2_err_fcpe ),
.PLSELLNKRATE (pl_sel_lnk_rate ),
.PLSELLNKWIDTH (pl_sel_lnk_width ),
.PLLTSSMSTATE (pl_ltssm_state ),
.PLLANEREVERSALMODE (pl_lane_reversal_mode ),
.PLPHYLNKUPN (pl_phy_lnk_up_n ),
.PLTXPMSTATE (pl_tx_pm_state ),
.PLRXPMSTATE (pl_rx_pm_state ),
.PLLINKUPCFGCAP (pl_link_upcfg_cap ),
.PLLINKGEN2CAP (pl_link_gen2_cap ),
.PLLINKPARTNERGEN2SUPPORTED (pl_link_partner_gen2_supported ),
.PLINITIALLINKWIDTH (pl_initial_link_width ),
.PLDIRECTEDCHANGEDONE (pl_directed_change_done ),
.PIPETXRCVRDET (pipe_tx_rcvr_det ),
.PIPETXRESET (pipe_tx_reset ),
.PIPETXRATE (pipe_tx_rate ),
.PIPETXDEEMPH (pipe_tx_deemph ),
.PIPETXMARGIN (pipe_tx_margin ),
.PIPERX0POLARITY (pipe_rx0_polarity ),
.PIPERX1POLARITY (pipe_rx1_polarity ),
.PIPERX2POLARITY (pipe_rx2_polarity ),
.PIPERX3POLARITY (pipe_rx3_polarity ),
.PIPERX4POLARITY (pipe_rx4_polarity ),
.PIPERX5POLARITY (pipe_rx5_polarity ),
.PIPERX6POLARITY (pipe_rx6_polarity ),
.PIPERX7POLARITY (pipe_rx7_polarity ),
.PIPETX0COMPLIANCE (pipe_tx0_compliance ),
.PIPETX1COMPLIANCE (pipe_tx1_compliance ),
.PIPETX2COMPLIANCE (pipe_tx2_compliance ),
.PIPETX3COMPLIANCE (pipe_tx3_compliance ),
.PIPETX4COMPLIANCE (pipe_tx4_compliance ),
.PIPETX5COMPLIANCE (pipe_tx5_compliance ),
.PIPETX6COMPLIANCE (pipe_tx6_compliance ),
.PIPETX7COMPLIANCE (pipe_tx7_compliance ),
.PIPETX0CHARISK (pipe_tx0_char_is_k ),
.PIPETX1CHARISK (pipe_tx1_char_is_k ),
.PIPETX2CHARISK (pipe_tx2_char_is_k ),
.PIPETX3CHARISK (pipe_tx3_char_is_k ),
.PIPETX4CHARISK (pipe_tx4_char_is_k ),
.PIPETX5CHARISK (pipe_tx5_char_is_k ),
.PIPETX6CHARISK (pipe_tx6_char_is_k ),
.PIPETX7CHARISK (pipe_tx7_char_is_k ),
.PIPETX0DATA (pipe_tx0_data ),
.PIPETX1DATA (pipe_tx1_data ),
.PIPETX2DATA (pipe_tx2_data ),
.PIPETX3DATA (pipe_tx3_data ),
.PIPETX4DATA (pipe_tx4_data ),
.PIPETX5DATA (pipe_tx5_data ),
.PIPETX6DATA (pipe_tx6_data ),
.PIPETX7DATA (pipe_tx7_data ),
.PIPETX0ELECIDLE (pipe_tx0_elec_idle ),
.PIPETX1ELECIDLE (pipe_tx1_elec_idle ),
.PIPETX2ELECIDLE (pipe_tx2_elec_idle ),
.PIPETX3ELECIDLE (pipe_tx3_elec_idle ),
.PIPETX4ELECIDLE (pipe_tx4_elec_idle ),
.PIPETX5ELECIDLE (pipe_tx5_elec_idle ),
.PIPETX6ELECIDLE (pipe_tx6_elec_idle ),
.PIPETX7ELECIDLE (pipe_tx7_elec_idle ),
.PIPETX0POWERDOWN (pipe_tx0_powerdown ),
.PIPETX1POWERDOWN (pipe_tx1_powerdown ),
.PIPETX2POWERDOWN (pipe_tx2_powerdown ),
.PIPETX3POWERDOWN (pipe_tx3_powerdown ),
.PIPETX4POWERDOWN (pipe_tx4_powerdown ),
.PIPETX5POWERDOWN (pipe_tx5_powerdown ),
.PIPETX6POWERDOWN (pipe_tx6_powerdown ),
.PIPETX7POWERDOWN (pipe_tx7_powerdown ),
`ifdef B_TESTMODE
.PMVOUT (pmv_out ),
.SCANOUT (scanout ),
`endif
.USERRSTN (user_rst_n ),
.PLRECEIVEDHOTRST (pl_received_hot_rst ),
.RECEIVEDFUNCLVLRSTN (received_func_lvl_rst_n ),
.LNKCLKEN (lnk_clk_en ),
.CFGMGMTDO (cfg_mgmt_do ),
.CFGMGMTRDWRDONEN (cfg_mgmt_rd_wr_done_n ),
.CFGERRAERHEADERLOGSETN (cfg_err_aer_headerlog_set_n ),
.CFGERRCPLRDYN (cfg_err_cpl_rdy_n ),
.CFGINTERRUPTRDYN (cfg_interrupt_rdy_n ),
.CFGINTERRUPTMMENABLE (cfg_interrupt_mmenable ),
.CFGINTERRUPTMSIENABLE (cfg_interrupt_msienable ),
.CFGINTERRUPTDO (cfg_interrupt_do ),
.CFGINTERRUPTMSIXENABLE (cfg_interrupt_msixenable ),
.CFGINTERRUPTMSIXFM (cfg_interrupt_msixfm ),
.CFGMSGRECEIVED (cfg_msg_received ),
.CFGMSGDATA (cfg_msg_data ),
.CFGMSGRECEIVEDERRCOR (cfg_msg_received_err_cor ),
.CFGMSGRECEIVEDERRNONFATAL (cfg_msg_received_err_non_fatal ),
.CFGMSGRECEIVEDERRFATAL (cfg_msg_received_err_fatal ),
.CFGMSGRECEIVEDASSERTINTA (cfg_msg_received_assert_int_a ),
.CFGMSGRECEIVEDDEASSERTINTA (cfg_msg_received_deassert_int_a ),
.CFGMSGRECEIVEDASSERTINTB (cfg_msg_received_assert_int_b ),
.CFGMSGRECEIVEDDEASSERTINTB (cfg_msg_received_deassert_int_b ),
.CFGMSGRECEIVEDASSERTINTC (cfg_msg_received_assert_int_c ),
.CFGMSGRECEIVEDDEASSERTINTC (cfg_msg_received_deassert_int_c ),
.CFGMSGRECEIVEDASSERTINTD (cfg_msg_received_assert_int_d ),
.CFGMSGRECEIVEDDEASSERTINTD (cfg_msg_received_deassert_int_d ),
.CFGMSGRECEIVEDPMPME (cfg_msg_received_pm_pme ),
.CFGMSGRECEIVEDPMETOACK (cfg_msg_received_pme_to_ack ),
.CFGMSGRECEIVEDPMETO (cfg_msg_received_pme_to ),
.CFGMSGRECEIVEDSETSLOTPOWERLIMIT (cfg_msg_received_setslotpowerlimit ),
.CFGMSGRECEIVEDUNLOCK (cfg_msg_received_unlock ),
.CFGMSGRECEIVEDPMASNAK (cfg_msg_received_pm_as_nak ),
.CFGPCIELINKSTATE (cfg_pcie_link_state ),
.CFGPMRCVASREQL1N (cfg_pm_rcv_as_req_l1_n ),
.CFGPMRCVREQACKN (cfg_pm_rcv_req_ack_n ),
.CFGPMRCVENTERL1N (cfg_pm_rcv_enter_l1_n ),
.CFGPMRCVENTERL23N (cfg_pm_rcv_enter_l23_n ),
.CFGPMCSRPOWERSTATE (cfg_pmcsr_powerstate ),
.CFGPMCSRPMEEN (cfg_pmcsr_pme_en ),
.CFGPMCSRPMESTATUS (cfg_pmcsr_pme_status ),
.CFGTRANSACTION (cfg_transaction ),
.CFGTRANSACTIONTYPE (cfg_transaction_type ),
.CFGTRANSACTIONADDR (cfg_transaction_addr ),
.CFGCOMMANDIOENABLE (cfg_command_io_enable ),
.CFGCOMMANDMEMENABLE (cfg_command_mem_enable ),
.CFGCOMMANDBUSMASTERENABLE (cfg_command_bus_master_enable ),
.CFGCOMMANDINTERRUPTDISABLE (cfg_command_interrupt_disable ),
.CFGCOMMANDSERREN (cfg_command_serr_en ),
.CFGBRIDGESERREN (cfg_bridge_serr_en ),
.CFGDEVSTATUSCORRERRDETECTED (cfg_dev_status_corr_err_detected ),
.CFGDEVSTATUSNONFATALERRDETECTED (cfg_dev_status_non_fatal_err_detected ),
.CFGDEVSTATUSFATALERRDETECTED (cfg_dev_status_fatal_err_detected ),
.CFGDEVSTATUSURDETECTED (cfg_dev_status_ur_detected ),
.CFGDEVCONTROLCORRERRREPORTINGEN (cfg_dev_control_corr_err_reporting_en ),
.CFGDEVCONTROLNONFATALREPORTINGEN (cfg_dev_control_non_fatal_reporting_en ),
.CFGDEVCONTROLFATALERRREPORTINGEN (cfg_dev_control_fatal_err_reporting_en ),
.CFGDEVCONTROLURERRREPORTINGEN (cfg_dev_control_ur_err_reporting_en ),
.CFGDEVCONTROLENABLERO (cfg_dev_control_enable_ro ),
.CFGDEVCONTROLMAXPAYLOAD (cfg_dev_control_max_payload ),
.CFGDEVCONTROLEXTTAGEN (cfg_dev_control_ext_tag_en ),
.CFGDEVCONTROLPHANTOMEN (cfg_dev_control_phantom_en ),
.CFGDEVCONTROLAUXPOWEREN (cfg_dev_control_aux_power_en ),
.CFGDEVCONTROLNOSNOOPEN (cfg_dev_control_no_snoop_en ),
.CFGDEVCONTROLMAXREADREQ (cfg_dev_control_max_read_req ),
.CFGLINKSTATUSCURRENTSPEED (cfg_link_status_current_speed ),
.CFGLINKSTATUSNEGOTIATEDWIDTH (cfg_link_status_negotiated_width ),
.CFGLINKSTATUSLINKTRAINING (cfg_link_status_link_training ),
.CFGLINKSTATUSDLLACTIVE (cfg_link_status_dll_active ),
.CFGLINKSTATUSBANDWIDTHSTATUS (cfg_link_status_bandwidth_status ),
.CFGLINKSTATUSAUTOBANDWIDTHSTATUS (cfg_link_status_auto_bandwidth_status ),
.CFGLINKCONTROLASPMCONTROL (cfg_link_control_aspm_control ),
.CFGLINKCONTROLRCB (cfg_link_control_rcb ),
.CFGLINKCONTROLLINKDISABLE (cfg_link_control_link_disable ),
.CFGLINKCONTROLRETRAINLINK (cfg_link_control_retrain_link ),
.CFGLINKCONTROLCOMMONCLOCK (cfg_link_control_common_clock ),
.CFGLINKCONTROLEXTENDEDSYNC (cfg_link_control_extended_sync ),
.CFGLINKCONTROLCLOCKPMEN (cfg_link_control_clock_pm_en ),
.CFGLINKCONTROLHWAUTOWIDTHDIS (cfg_link_control_hw_auto_width_dis ),
.CFGLINKCONTROLBANDWIDTHINTEN (cfg_link_control_bandwidth_int_en ),
.CFGLINKCONTROLAUTOBANDWIDTHINTEN (cfg_link_control_auto_bandwidth_int_en ),
.CFGDEVCONTROL2CPLTIMEOUTVAL (cfg_dev_control2_cpl_timeout_val ),
.CFGDEVCONTROL2CPLTIMEOUTDIS (cfg_dev_control2_cpl_timeout_dis ),
.CFGDEVCONTROL2ARIFORWARDEN (cfg_dev_control2_ari_forward_en ),
.CFGDEVCONTROL2ATOMICREQUESTEREN (cfg_dev_control2_atomic_requester_en ),
.CFGDEVCONTROL2ATOMICEGRESSBLOCK (cfg_dev_control2_atomic_egress_block ),
.CFGDEVCONTROL2IDOREQEN (cfg_dev_control2_ido_req_en ),
.CFGDEVCONTROL2IDOCPLEN (cfg_dev_control2_ido_cpl_en ),
.CFGDEVCONTROL2LTREN (cfg_dev_control2_ltr_en ),
.CFGDEVCONTROL2TLPPREFIXBLOCK (cfg_dev_control2_tlp_prefix_block ),
.CFGSLOTCONTROLELECTROMECHILCTLPULSE (cfg_slot_control_electromech_il_ctl_pulse ),
.CFGROOTCONTROLSYSERRCORRERREN (cfg_root_control_syserr_corr_err_en ),
.CFGROOTCONTROLSYSERRNONFATALERREN (cfg_root_control_syserr_non_fatal_err_en ),
.CFGROOTCONTROLSYSERRFATALERREN (cfg_root_control_syserr_fatal_err_en ),
.CFGROOTCONTROLPMEINTEN (cfg_root_control_pme_int_en ),
.CFGAERECRCCHECKEN (cfg_aer_ecrc_check_en ),
.CFGAERECRCGENEN (cfg_aer_ecrc_gen_en ),
.CFGAERROOTERRCORRERRREPORTINGEN (cfg_aer_rooterr_corr_err_reporting_en ),
.CFGAERROOTERRNONFATALERRREPORTINGEN (cfg_aer_rooterr_non_fatal_err_reporting_en ),
.CFGAERROOTERRFATALERRREPORTINGEN (cfg_aer_rooterr_fatal_err_reporting_en ),
.CFGAERROOTERRCORRERRRECEIVED (cfg_aer_rooterr_corr_err_received ),
.CFGAERROOTERRNONFATALERRRECEIVED (cfg_aer_rooterr_non_fatal_err_received ),
.CFGAERROOTERRFATALERRRECEIVED (cfg_aer_rooterr_fatal_err_received ),
.CFGVCTCVCMAP (cfg_vc_tcvc_map ),
.DRPRDY (drp_rdy ),
.DRPDO (drp_do ),
//.DRPWRITEEN (drp_write_en ),
//.DRPWRITEPORT0 (drp_write_port_0 ),
//.DRPWRITEPORT1 (drp_write_port_1 ),
//.DRPWRITEPORT2 (drp_write_port_2 ),
//.DRPWRITEPORT3 (drp_write_port_3 ),
//.DRPWRITEPORT4 (drp_write_port_4 ),
//.DRPWRITEPORT5 (drp_write_port_5 ),
//.DRPWRITEPORT6 (drp_write_port_6 ),
//.DRPWRITEPORT7 (drp_write_port_7 ),
//.DRPWRITEPORT8 (drp_write_port_8 ),
//.DRPWRITEPORT9 (drp_write_port_9 ),
//.DRPWRITEPORT10 (drp_write_port_10 ),
//.DRPWRITEPORT11 (drp_write_port_11 ),
//.DRPWRITEPORT12 (drp_write_port_12 ),
//.DRPREADADDR (drp_read_addr ),
.DBGVECA (dbg_vec_a ),
.DBGVECB (dbg_vec_b ),
.DBGVECC (dbg_vec_c ),
.DBGSCLRA (dbg_sclr_a ),
.DBGSCLRB (dbg_sclr_b ),
.DBGSCLRC (dbg_sclr_c ),
.DBGSCLRD (dbg_sclr_d ),
.DBGSCLRE (dbg_sclr_e ),
.DBGSCLRF (dbg_sclr_f ),
.DBGSCLRG (dbg_sclr_g ),
.DBGSCLRH (dbg_sclr_h ),
.DBGSCLRI (dbg_sclr_i ),
.DBGSCLRJ (dbg_sclr_j ),
.DBGSCLRK (dbg_sclr_k ),
.PLDBGVEC (pl_dbg_vec )
//.XILUNCONNOUT (xil_unconn_out )
);
endmodule
`endif // PCIE_2LM
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND3B_FUNCTIONAL_V
`define SKY130_FD_SC_MS__NAND3B_FUNCTIONAL_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__nand3b (
Y ,
A_N,
B ,
C
);
// Module ports
output Y ;
input A_N;
input B ;
input C ;
// Local signals
wire not0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y, B, not0_out, C );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND3B_FUNCTIONAL_V |
/****************************************************************************************
*
* File Name: ddr3.v
* Version: 1.60
* Model: BUS Functional
*
* Dependencies: ddr3_model_parameters.vh
*
* Description: Micron SDRAM DDR3 (Double Data Rate 3)
*
* Limitation: - doesn't check for average refresh timings
* - positive ck and ck_n edges are used to form internal clock
* - positive dqs and dqs_n edges are used to latch data
* - test mode is not modeled
* - Duty Cycle Corrector is not modeled
* - Temperature Compensated Self Refresh is not modeled
* - DLL off mode is not modeled.
*
* Note: - Set simulator resolution to "ps" accuracy
* - Set DEBUG = 0 to disable $display messages
*
* Disclaimer This software code and all associated documentation, comments or other
* of Warranty: information (collectively "Software") is provided "AS IS" without
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGES. Because some jurisdictions prohibit the exclusion or
* limitation of liability for consequential or incidental damages, the
* above limitation may not apply to you.
*
* Copyright 2003 Micron Technology, Inc. All rights reserved.
*
* Rev Author Date Changes
* ---------------------------------------------------------------------------------------
* 0.41 JMK 05/12/06 Removed auto-precharge to power down error check.
* 0.42 JMK 08/25/06 Created internal clock using ck and ck_n.
* TDQS can only be enabled in EMR for x8 configurations.
* CAS latency is checked vs frequency when DLL locks.
* Improved checking of DQS during writes.
* Added true BL4 operation.
* 0.43 JMK 08/14/06 Added checking for setting reserved bits in Mode Registers.
* Added ODTS Readout.
* Replaced tZQCL with tZQinit and tZQoper
* Fixed tWRPDEN and tWRAPDEN during BC4MRS and BL4MRS.
* Added tRFC checking for Refresh to Power-Down Re-Entry.
* Added tXPDLL checking for Power-Down Exit to Refresh to Power-Down Entry
* Added Clock Frequency Change during Precharge Power-Down.
* Added -125x speed grades.
* Fixed tRCD checking during Write.
* 1.00 JMK 05/11/07 Initial release
* 1.10 JMK 06/26/07 Fixed ODTH8 check during BLOTF
* Removed temp sensor readout from MPR
* Updated initialization sequence
* Updated timing parameters
* 1.20 JMK 09/05/07 Updated clock frequency change
* Added ddr3_dimm module
* 1.30 JMK 01/23/08 Updated timing parameters
* 1.40 JMK 12/02/08 Added support for DDR3-1866 and DDR3-2133
* renamed ddr3_dimm.v to ddr3_module.v and added SODIMM support.
* Added multi-chip package model support in ddr3_mcp.v
* 1.50 JMK 05/04/08 Added 1866 and 2133 speed grades.
* 1.60 MYY 07/10/09 Merging of 1.50 version and pre-1.0 version changes
*****************************************************************************************/
// DO NOT CHANGE THE TIMESCALE
// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION
`timescale 1ps / 1ps
// model flags
// `define MODEL_PASR
module ddr3_model (
rst_n,
ck,
ck_n,
cke,
cs_n,
ras_n,
cas_n,
we_n,
dm_tdqs,
ba,
addr,
dq,
dqs,
dqs_n,
tdqs_n,
odt
);
`include "ddr3_model_parameters.vh"
parameter check_strict_mrbits = 1;
parameter check_strict_timing = 1;
parameter feature_pasr = 1;
parameter feature_truebl4 = 0;
// text macros
`define DQ_PER_DQS DQ_BITS/DQS_BITS
`define BANKS (1<<BA_BITS)
`define MAX_BITS (BA_BITS+ROW_BITS+COL_BITS-BL_BITS)
`define MAX_SIZE (1<<(BA_BITS+ROW_BITS+COL_BITS-BL_BITS))
`define MEM_SIZE (1<<MEM_BITS)
`define MAX_PIPE 4*CL_MAX
// Declare Ports
input rst_n;
input ck;
input ck_n;
input cke;
input cs_n;
input ras_n;
input cas_n;
input we_n;
inout [DM_BITS-1:0] dm_tdqs;
input [BA_BITS-1:0] ba;
input [ADDR_BITS-1:0] addr;
inout [DQ_BITS-1:0] dq;
inout [DQS_BITS-1:0] dqs;
inout [DQS_BITS-1:0] dqs_n;
output [DQS_BITS-1:0] tdqs_n;
input odt;
// clock jitter
real tck_avg;
time tck_sample [TDLLK-1:0];
time tch_sample [TDLLK-1:0];
time tcl_sample [TDLLK-1:0];
time tck_i;
time tch_i;
time tcl_i;
real tch_avg;
real tcl_avg;
time tm_ck_pos;
time tm_ck_neg;
real tjit_per_rtime;
integer tjit_cc_time;
real terr_nper_rtime;
//DDR3 clock jitter variables
real tjit_ch_rtime;
real duty_cycle;
// clock skew
real out_delay;
integer dqsck [DQS_BITS-1:0];
integer dqsck_min;
integer dqsck_max;
integer dqsq_min;
integer dqsq_max;
integer seed;
// Mode Registers
reg [ADDR_BITS-1:0] mode_reg [`BANKS-1:0];
reg burst_order;
reg [BL_BITS:0] burst_length;
reg blotf;
reg truebl4;
integer cas_latency;
reg dll_reset;
reg dll_locked;
integer write_recovery;
reg low_power;
reg dll_en;
reg [2:0] odt_rtt_nom;
reg [1:0] odt_rtt_wr;
reg odt_en;
reg dyn_odt_en;
reg [1:0] al;
integer additive_latency;
reg write_levelization;
reg duty_cycle_corrector;
reg tdqs_en;
reg out_en;
reg [2:0] pasr;
integer cas_write_latency;
reg asr; // auto self refresh
reg srt; // self refresh temperature range
reg [1:0] mpr_select;
reg mpr_en;
reg odts_readout;
integer read_latency;
integer write_latency;
// cmd encoding
parameter // {cs, ras, cas, we}
LOAD_MODE = 4'b0000,
REFRESH = 4'b0001,
PRECHARGE = 4'b0010,
ACTIVATE = 4'b0011,
WRITE = 4'b0100,
READ = 4'b0101,
ZQ = 4'b0110,
NOP = 4'b0111,
// DESEL = 4'b1xxx,
PWR_DOWN = 4'b1000,
SELF_REF = 4'b1001
;
reg [8*9-1:0] cmd_string [9:0];
initial begin
cmd_string[LOAD_MODE] = "Load Mode";
cmd_string[REFRESH ] = "Refresh ";
cmd_string[PRECHARGE] = "Precharge";
cmd_string[ACTIVATE ] = "Activate ";
cmd_string[WRITE ] = "Write ";
cmd_string[READ ] = "Read ";
cmd_string[ZQ ] = "ZQ ";
cmd_string[NOP ] = "No Op ";
cmd_string[PWR_DOWN ] = "Pwr Down ";
cmd_string[SELF_REF ] = "Self Ref ";
end
// command state
reg [`BANKS-1:0] active_bank;
reg [`BANKS-1:0] auto_precharge_bank;
reg [`BANKS-1:0] write_precharge_bank;
reg [`BANKS-1:0] read_precharge_bank;
reg [ROW_BITS-1:0] active_row [`BANKS-1:0];
reg in_power_down;
reg in_self_refresh;
reg [3:0] init_mode_reg;
reg init_dll_reset;
reg init_done;
integer init_step;
reg zq_set;
reg er_trfc_max;
reg odt_state;
reg odt_state_dly;
reg dyn_odt_state;
reg dyn_odt_state_dly;
reg prev_odt;
wire [7:0] calibration_pattern = 8'b10101010; // value returned during mpr pre-defined pattern readout
wire [7:0] temp_sensor = 8'h01; // value returned during mpr temp sensor readout
reg [1:0] mr_chk;
reg rd_bc;
integer banki;
// cmd timers/counters
integer ref_cntr;
integer odt_cntr;
integer ck_cntr;
integer ck_txpr;
integer ck_load_mode;
integer ck_refresh;
integer ck_precharge;
integer ck_activate;
integer ck_write;
integer ck_read;
integer ck_zqinit;
integer ck_zqoper;
integer ck_zqcs;
integer ck_power_down;
integer ck_slow_exit_pd;
integer ck_self_refresh;
integer ck_freq_change;
integer ck_odt;
integer ck_odth8;
integer ck_dll_reset;
integer ck_cke_cmd;
integer ck_bank_write [`BANKS-1:0];
integer ck_bank_read [`BANKS-1:0];
integer ck_group_activate [1:0];
integer ck_group_write [1:0];
integer ck_group_read [1:0];
time tm_txpr;
time tm_load_mode;
time tm_refresh;
time tm_precharge;
time tm_activate;
time tm_write_end;
time tm_power_down;
time tm_slow_exit_pd;
time tm_self_refresh;
time tm_freq_change;
time tm_cke_cmd;
time tm_ttsinit;
time tm_bank_precharge [`BANKS-1:0];
time tm_bank_activate [`BANKS-1:0];
time tm_bank_write_end [`BANKS-1:0];
time tm_bank_read_end [`BANKS-1:0];
time tm_group_activate [1:0];
time tm_group_write_end [1:0];
// pipelines
reg [`MAX_PIPE:0] al_pipeline;
reg [`MAX_PIPE:0] wr_pipeline;
reg [`MAX_PIPE:0] rd_pipeline;
reg [`MAX_PIPE:0] odt_pipeline;
reg [`MAX_PIPE:0] dyn_odt_pipeline;
reg [BL_BITS:0] bl_pipeline [`MAX_PIPE:0];
reg [BA_BITS-1:0] ba_pipeline [`MAX_PIPE:0];
reg [ROW_BITS-1:0] row_pipeline [`MAX_PIPE:0];
reg [COL_BITS-1:0] col_pipeline [`MAX_PIPE:0];
reg prev_cke;
// data state
reg [BL_MAX*DQ_BITS-1:0] memory_data;
reg [BL_MAX*DQ_BITS-1:0] bit_mask;
reg [BL_BITS-1:0] burst_position;
reg [BL_BITS:0] burst_cntr;
reg [DQ_BITS-1:0] dq_temp;
reg [31:0] check_write_postamble;
reg [31:0] check_write_preamble;
reg [31:0] check_write_dqs_high;
reg [31:0] check_write_dqs_low;
reg [15:0] check_dm_tdipw;
reg [63:0] check_dq_tdipw;
// data timers/counters
time tm_rst_n;
time tm_cke;
time tm_odt;
time tm_tdqss;
time tm_dm [15:0];
time tm_dqs [15:0];
time tm_dqs_pos [31:0];
time tm_dqss_pos [31:0];
time tm_dqs_neg [31:0];
time tm_dq [63:0];
time tm_cmd_addr [22:0];
reg [8*7-1:0] cmd_addr_string [22:0];
initial begin
cmd_addr_string[ 0] = "CS_N ";
cmd_addr_string[ 1] = "RAS_N ";
cmd_addr_string[ 2] = "CAS_N ";
cmd_addr_string[ 3] = "WE_N ";
cmd_addr_string[ 4] = "BA 0 ";
cmd_addr_string[ 5] = "BA 1 ";
cmd_addr_string[ 6] = "BA 2 ";
cmd_addr_string[ 7] = "ADDR 0";
cmd_addr_string[ 8] = "ADDR 1";
cmd_addr_string[ 9] = "ADDR 2";
cmd_addr_string[10] = "ADDR 3";
cmd_addr_string[11] = "ADDR 4";
cmd_addr_string[12] = "ADDR 5";
cmd_addr_string[13] = "ADDR 6";
cmd_addr_string[14] = "ADDR 7";
cmd_addr_string[15] = "ADDR 8";
cmd_addr_string[16] = "ADDR 9";
cmd_addr_string[17] = "ADDR 10";
cmd_addr_string[18] = "ADDR 11";
cmd_addr_string[19] = "ADDR 12";
cmd_addr_string[20] = "ADDR 13";
cmd_addr_string[21] = "ADDR 14";
cmd_addr_string[22] = "ADDR 15";
end
reg [8*5-1:0] dqs_string [1:0];
initial begin
dqs_string[0] = "DQS ";
dqs_string[1] = "DQS_N";
end
// Memory Storage
`ifdef MAX_MEM
parameter RFF_BITS = DQ_BITS*BL_MAX;
// %z format uses 8 bytes for every 32 bits or less.
parameter RFF_CHUNK = 8 * (RFF_BITS/32 + (RFF_BITS%32 ? 1 : 0));
reg [1024:1] tmp_model_dir;
integer memfd[`BANKS-1:0];
initial
begin : file_io_open
integer bank;
if (!$value$plusargs("model_data+%s", tmp_model_dir))
begin
tmp_model_dir = "/tmp";
$display(
"%m: at time %t WARNING: no +model_data option specified, using /tmp.",
$time
);
end
for (bank = 0; bank < `BANKS; bank = bank + 1)
memfd[bank] = open_bank_file(bank);
end
`else
reg [BL_MAX*DQ_BITS-1:0] memory [0:`MEM_SIZE-1];
reg [`MAX_BITS-1:0] address [0:`MEM_SIZE-1];
reg [MEM_BITS:0] memory_index;
reg [MEM_BITS:0] memory_used = 0;
`endif
// receive
reg rst_n_in;
reg ck_in;
reg ck_n_in;
reg cke_in;
reg cs_n_in;
reg ras_n_in;
reg cas_n_in;
reg we_n_in;
reg [15:0] dm_in;
reg [2:0] ba_in;
reg [15:0] addr_in;
reg [63:0] dq_in;
reg [31:0] dqs_in;
reg odt_in;
reg [15:0] dm_in_pos;
reg [15:0] dm_in_neg;
reg [63:0] dq_in_pos;
reg [63:0] dq_in_neg;
reg dq_in_valid;
reg dqs_in_valid;
integer wdqs_cntr;
integer wdq_cntr;
integer wdqs_pos_cntr [31:0];
reg b2b_write;
reg [BL_BITS:0] wr_burst_length;
reg [31:0] prev_dqs_in;
reg diff_ck;
always @(rst_n ) rst_n_in <= #BUS_DELAY rst_n;
always @(ck ) ck_in <= #BUS_DELAY ck;
always @(ck_n ) ck_n_in <= #BUS_DELAY ck_n;
always @(cke ) cke_in <= #BUS_DELAY cke;
always @(cs_n ) cs_n_in <= #BUS_DELAY cs_n;
always @(ras_n ) ras_n_in <= #BUS_DELAY ras_n;
always @(cas_n ) cas_n_in <= #BUS_DELAY cas_n;
always @(we_n ) we_n_in <= #BUS_DELAY we_n;
always @(dm_tdqs) dm_in <= #BUS_DELAY dm_tdqs;
always @(ba ) ba_in <= #BUS_DELAY ba;
always @(addr ) addr_in <= #BUS_DELAY addr;
always @(dq ) dq_in <= #BUS_DELAY dq;
always @(dqs or dqs_n) dqs_in <= #BUS_DELAY (dqs_n<<16) | dqs;
always @(odt ) odt_in <= #BUS_DELAY odt;
// create internal clock
always @(posedge ck_in) diff_ck <= ck_in;
always @(posedge ck_n_in) diff_ck <= ~ck_n_in;
wire [15:0] dqs_even = dqs_in[15:0];
wire [15:0] dqs_odd = dqs_in[31:16];
wire [3:0] cmd_n_in = !cs_n_in ? {ras_n_in, cas_n_in, we_n_in} : NOP; //deselect = nop
// transmit
reg dqs_out_en;
reg [DQS_BITS-1:0] dqs_out_en_dly;
reg dqs_out;
reg [DQS_BITS-1:0] dqs_out_dly;
reg dq_out_en;
reg [DQ_BITS-1:0] dq_out_en_dly;
reg [DQ_BITS-1:0] dq_out;
reg [DQ_BITS-1:0] dq_out_dly;
integer rdqsen_cntr;
integer rdqs_cntr;
integer rdqen_cntr;
integer rdq_cntr;
bufif1 buf_dqs [DQS_BITS-1:0] (dqs, dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}});
bufif1 buf_dqs_n [DQS_BITS-1:0] (dqs_n, ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}});
bufif1 buf_dq [DQ_BITS-1:0] (dq, dq_out_dly, dq_out_en_dly & {DQ_BITS {out_en}});
assign tdqs_n = {DQS_BITS{1'bz}};
initial begin
if (BL_MAX < 2)
$display("%m ERROR: BL_MAX parameter must be >= 2. \nBL_MAX = %d", BL_MAX);
if ((1<<BO_BITS) > BL_MAX)
$display("%m ERROR: 2^BO_BITS cannot be greater than BL_MAX parameter.");
$timeformat (-12, 1, " ps", 1);
seed = RANDOM_SEED;
ck_cntr = 0;
end
function integer get_rtt_wr;
input [1:0] rtt;
begin
get_rtt_wr = RZQ/{rtt[0], rtt[1], 1'b0};
end
endfunction
function integer get_rtt_nom;
input [2:0] rtt;
begin
case (rtt)
1: get_rtt_nom = RZQ/4;
2: get_rtt_nom = RZQ/2;
3: get_rtt_nom = RZQ/6;
4: get_rtt_nom = RZQ/12;
5: get_rtt_nom = RZQ/8;
default : get_rtt_nom = 0;
endcase
end
endfunction
// calculate the absolute value of a real number
function real abs_value;
input arg;
real arg;
begin
if (arg < 0.0)
abs_value = -1.0 * arg;
else
abs_value = arg;
end
endfunction
function integer ceil;
input number;
real number;
// LMR 4.1.7
// When either operand of a relational expression is a real operand then the other operand shall be converted
// to an equivalent real value, and the expression shall be interpreted as a comparison between two real values.
if (number > $rtoi(number))
ceil = $rtoi(number) + 1;
else
ceil = number;
endfunction
function integer floor;
input number;
real number;
// LMR 4.1.7
// When either operand of a relational expression is a real operand then the other operand shall be converted
// to an equivalent real value, and the expression shall be interpreted as a comparison between two real values.
if (number < $rtoi(number))
floor = $rtoi(number) - 1;
else
floor = number;
endfunction
`ifdef MAX_MEM
function integer open_bank_file( input integer bank );
integer fd;
reg [2048:1] filename;
begin
$sformat( filename, "%0s/%m.%0d", tmp_model_dir, bank );
fd = $fopen(filename, "w+");
if (fd == 0)
begin
$display("%m: at time %0t ERROR: failed to open %0s.", $time, filename);
$finish;
end
else
begin
if (DEBUG) $display("%m: at time %0t INFO: opening %0s.", $time, filename);
open_bank_file = fd;
end
end
endfunction
function [RFF_BITS:1] read_from_file(
input integer fd,
input integer index
);
integer code;
integer offset;
reg [1024:1] msg;
reg [RFF_BITS:1] read_value;
begin
offset = index * RFF_CHUNK;
code = $fseek( fd, offset, 0 );
// $fseek returns 0 on success, -1 on failure
if (code != 0)
begin
$display("%m: at time %t ERROR: fseek to %d failed", $time, offset);
$finish;
end
code = $fscanf(fd, "%z", read_value);
// $fscanf returns number of items read
if (code != 1)
begin
if ($ferror(fd,msg) != 0)
begin
$display("%m: at time %t ERROR: fscanf failed at %d", $time, index);
$display(msg);
$finish;
end
else
read_value = 'hx;
end
/* when reading from unwritten portions of the file, 0 will be returned.
* Use 0 in bit 1 as indicator that invalid data has been read.
* A true 0 is encoded as Z.
*/
if (read_value[1] === 1'bz)
// true 0 encoded as Z, data is valid
read_value[1] = 1'b0;
else if (read_value[1] === 1'b0)
// read from file section that has not been written
read_value = 'hx;
read_from_file = read_value;
end
endfunction
task write_to_file(
input integer fd,
input integer index,
input [RFF_BITS:1] data
);
integer code;
integer offset;
begin
offset = index * RFF_CHUNK;
code = $fseek( fd, offset, 0 );
if (code != 0)
begin
$display("%m: at time %t ERROR: fseek to %d failed", $time, offset);
$finish;
end
// encode a valid data
if (data[1] === 1'bz)
data[1] = 1'bx;
else if (data[1] === 1'b0)
data[1] = 1'bz;
$fwrite( fd, "%z", data );
end
endtask
`else
function get_index;
input [`MAX_BITS-1:0] addr;
begin : index
get_index = 0;
for (memory_index=0; memory_index<memory_used; memory_index=memory_index+1) begin
if (address[memory_index] == addr) begin
get_index = 1;
disable index;
end
end
end
endfunction
`endif
task memory_write;
input [BA_BITS-1:0] bank;
input [ROW_BITS-1:0] row;
input [COL_BITS-1:0] col;
input [BL_MAX*DQ_BITS-1:0] data;
reg [`MAX_BITS-1:0] addr;
begin
`ifdef MAX_MEM
addr = {row, col}/BL_MAX;
write_to_file( memfd[bank], addr, data );
`else
// chop off the lowest address bits
addr = {bank, row, col}/BL_MAX;
if (get_index(addr)) begin
address[memory_index] = addr;
memory[memory_index] = data;
end else if (memory_used == `MEM_SIZE) begin
$display ("%m: at time %t ERROR: Memory overflow. Write to Address %h with Data %h will be lost.\nYou must increase the MEM_BITS parameter or define MAX_MEM.", $time, addr, data);
if (STOP_ON_ERROR) $stop(0);
end else begin
address[memory_used] = addr;
memory[memory_used] = data;
memory_used = memory_used + 1;
end
`endif
end
endtask
task memory_read;
input [BA_BITS-1:0] bank;
input [ROW_BITS-1:0] row;
input [COL_BITS-1:0] col;
output [BL_MAX*DQ_BITS-1:0] data;
reg [`MAX_BITS-1:0] addr;
begin
`ifdef MAX_MEM
addr = {row, col}/BL_MAX;
data = read_from_file( memfd[bank], addr );
`else
// chop off the lowest address bits
addr = {bank, row, col}/BL_MAX;
if (get_index(addr)) begin
data = memory[memory_index];
end else begin
data = {BL_MAX*DQ_BITS{1'bx}};
end
`endif
end
endtask
task set_latency;
begin
if (al == 0) begin
additive_latency = 0;
end else begin
additive_latency = cas_latency - al;
end
read_latency = cas_latency + additive_latency;
write_latency = cas_write_latency + additive_latency;
end
endtask
// this task will erase the contents of 0 or more banks
task erase_banks;
input [`BANKS-1:0] banks; //one select bit per bank
reg [BA_BITS-1:0] ba;
reg [`MAX_BITS-1:0] i;
integer bank;
begin
`ifdef MAX_MEM
for (bank = 0; bank < `BANKS; bank = bank + 1)
if (banks[bank] === 1'b1) begin
$fclose(memfd[bank]);
memfd[bank] = open_bank_file(bank);
end
`else
memory_index = 0;
i = 0;
// remove the selected banks
for (memory_index=0; memory_index<memory_used; memory_index=memory_index+1) begin
ba = (address[memory_index]>>(ROW_BITS+COL_BITS-BL_BITS));
if (!banks[ba]) begin //bank is selected to keep
address[i] = address[memory_index];
memory[i] = memory[memory_index];
i = i + 1;
end
end
// clean up the unused banks
for (memory_index=i; memory_index<memory_used; memory_index=memory_index+1) begin
address[memory_index] = 'bx;
memory[memory_index] = {8*DQ_BITS{1'bx}};
end
memory_used = i;
`endif
end
endtask
// Before this task runs, the model must be in a valid state for precharge power down and out of reset.
// After this task runs, NOP commands must be issued until TZQINIT has been met
task initialize;
input [ADDR_BITS-1:0] mode_reg0;
input [ADDR_BITS-1:0] mode_reg1;
input [ADDR_BITS-1:0] mode_reg2;
input [ADDR_BITS-1:0] mode_reg3;
begin
if (DEBUG) $display ("%m: at time %t INFO: Performing Initialization Sequence", $time);
cmd_task(1, NOP, 'bx, 'bx);
cmd_task(1, ZQ, 'bx, 'h400); //ZQCL
cmd_task(1, LOAD_MODE, 3, mode_reg3);
cmd_task(1, LOAD_MODE, 2, mode_reg2);
cmd_task(1, LOAD_MODE, 1, mode_reg1);
cmd_task(1, LOAD_MODE, 0, mode_reg0 | 'h100); // DLL Reset
cmd_task(0, NOP, 'bx, 'bx);
end
endtask
task reset_task;
integer i;
begin
// disable inputs
dq_in_valid = 0;
dqs_in_valid <= 0;
wdqs_cntr = 0;
wdq_cntr = 0;
for (i=0; i<31; i=i+1) begin
wdqs_pos_cntr[i] <= 0;
end
b2b_write <= 0;
// disable outputs
out_en = 0;
dq_out_en = 0;
rdq_cntr = 0;
dqs_out_en = 0;
rdqs_cntr = 0;
// disable ODT
odt_en = 0;
dyn_odt_en = 0;
odt_state = 0;
dyn_odt_state = 0;
// reset bank state
active_bank = 0;
auto_precharge_bank = 0;
read_precharge_bank = 0;
write_precharge_bank = 0;
// require initialization sequence
init_done = 0;
mpr_en = 0;
init_step = 0;
init_mode_reg = 0;
init_dll_reset = 0;
zq_set = 0;
// reset DLL
dll_en = 0;
dll_reset = 0;
dll_locked = 0;
// exit power down and self refresh
prev_cke = 1'bx;
in_power_down = 0;
in_self_refresh = 0;
// clear pipelines
al_pipeline = 0;
wr_pipeline = 0;
rd_pipeline = 0;
odt_pipeline = 0;
dyn_odt_pipeline = 0;
end
endtask
parameter SAME_BANK = 2'd0; // same bank, same group
parameter DIFF_BANK = 2'd1; // different bank, same group
parameter DIFF_GROUP = 2'd2; // different bank, different group
task chk_err;
input [1:0] relationship;
input [BA_BITS-1:0] bank;
input [3:0] fromcmd;
input [3:0] cmd;
reg err;
begin
// $display ("truebl4 = %d, relationship = %d, fromcmd = %h, cmd = %h", truebl4, relationship, fromcmd, cmd);
casex ({truebl4, relationship, fromcmd, cmd})
// load mode
{1'bx, DIFF_BANK , LOAD_MODE, LOAD_MODE} : begin if (ck_cntr - ck_load_mode < TMRD) $display ("%m: at time %t ERROR: tMRD violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , LOAD_MODE, READ } : begin if (($time - tm_load_mode < TMOD) || (ck_cntr - ck_load_mode < TMOD_TCK)) $display ("%m: at time %t ERROR: tMOD violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , LOAD_MODE, REFRESH } ,
{1'bx, DIFF_BANK , LOAD_MODE, PRECHARGE} ,
{1'bx, DIFF_BANK , LOAD_MODE, ACTIVATE } ,
{1'bx, DIFF_BANK , LOAD_MODE, ZQ } ,
{1'bx, DIFF_BANK , LOAD_MODE, PWR_DOWN } ,
{1'bx, DIFF_BANK , LOAD_MODE, SELF_REF } : begin if (($time - tm_load_mode < TMOD) || (ck_cntr - ck_load_mode < TMOD_TCK)) $display ("%m: at time %t ERROR: tMOD violation during %s", $time, cmd_string[cmd]); end
// refresh
{1'bx, DIFF_BANK , REFRESH , LOAD_MODE} ,
{1'bx, DIFF_BANK , REFRESH , REFRESH } ,
{1'bx, DIFF_BANK , REFRESH , PRECHARGE} ,
{1'bx, DIFF_BANK , REFRESH , ACTIVATE } ,
{1'bx, DIFF_BANK , REFRESH , ZQ } ,
{1'bx, DIFF_BANK , REFRESH , SELF_REF } : begin if ($time - tm_refresh < TRFC_MIN) $display ("%m: at time %t ERROR: tRFC violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , REFRESH , PWR_DOWN } : begin if (ck_cntr - ck_refresh < TREFPDEN) $display ("%m: at time %t ERROR: tREFPDEN violation during %s", $time, cmd_string[cmd]); end
// precharge
{1'bx, SAME_BANK , PRECHARGE, ACTIVATE } : begin if ($time - tm_bank_precharge[bank] < TRP) $display ("%m: at time %t ERROR: tRP violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, DIFF_BANK , PRECHARGE, LOAD_MODE} ,
{1'bx, DIFF_BANK , PRECHARGE, REFRESH } ,
{1'bx, DIFF_BANK , PRECHARGE, ZQ } ,
{1'bx, DIFF_BANK , PRECHARGE, SELF_REF } : begin if ($time - tm_precharge < TRP) $display ("%m: at time %t ERROR: tRP violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , PRECHARGE, PWR_DOWN } : ; //tPREPDEN = 1 tCK, can be concurrent with auto precharge
// activate
{1'bx, SAME_BANK , ACTIVATE , PRECHARGE} : begin if ($time - tm_bank_activate[bank] > TRAS_MAX) $display ("%m: at time %t ERROR: tRAS maximum violation during %s to bank %d", $time, cmd_string[cmd], bank);
if ($time - tm_bank_activate[bank] < TRAS_MIN) $display ("%m: at time %t ERROR: tRAS minimum violation during %s to bank %d", $time, cmd_string[cmd], bank);end
{1'bx, SAME_BANK , ACTIVATE , ACTIVATE } : begin if ($time - tm_bank_activate[bank] < TRC) $display ("%m: at time %t ERROR: tRC violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, SAME_BANK , ACTIVATE , WRITE } ,
{1'bx, SAME_BANK , ACTIVATE , READ } : ; // tRCD is checked outside this task
{1'b0, DIFF_BANK , ACTIVATE , ACTIVATE } : begin if (($time - tm_activate < TRRD) || (ck_cntr - ck_activate < TRRD_TCK)) $display ("%m: at time %t ERROR: tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_BANK , ACTIVATE , ACTIVATE } : begin if (($time - tm_group_activate[bank[1]] < TRRD) || (ck_cntr - ck_group_activate[bank[1]] < TRRD_TCK)) $display ("%m: at time %t ERROR: tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_GROUP, ACTIVATE , ACTIVATE } : begin if (($time - tm_activate < TRRD_DG) || (ck_cntr - ck_activate < TRRD_DG_TCK)) $display ("%m: at time %t ERROR: tRRD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, DIFF_BANK , ACTIVATE , REFRESH } : begin if ($time - tm_activate < TRC) $display ("%m: at time %t ERROR: tRC violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , ACTIVATE , PWR_DOWN } : begin if (ck_cntr - ck_activate < TACTPDEN) $display ("%m: at time %t ERROR: tACTPDEN violation during %s", $time, cmd_string[cmd]); end
// write
{1'bx, SAME_BANK , WRITE , PRECHARGE} : begin if (($time - tm_bank_write_end[bank] < TWR) || (ck_cntr - ck_bank_write[bank] <= write_latency + burst_length/2)) $display ("%m: at time %t ERROR: tWR violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, DIFF_BANK , WRITE , WRITE } : begin if (ck_cntr - ck_write < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_BANK , WRITE , WRITE } : begin if (ck_cntr - ck_group_write[bank[1]] < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, DIFF_BANK , WRITE , READ } : begin if (ck_cntr - ck_write < write_latency + burst_length/2 + TWTR_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_BANK , WRITE , READ } : begin if (ck_cntr - ck_group_write[bank[1]] < write_latency + burst_length/2 + TWTR_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_GROUP, WRITE , WRITE } : begin if (ck_cntr - ck_write < TCCD_DG) $display ("%m: at time %t ERROR: tCCD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_GROUP, WRITE , READ } : begin if (ck_cntr - ck_write < write_latency + burst_length/2 + TWTR_DG_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, DIFF_BANK , WRITE , PWR_DOWN } : begin if (($time - tm_write_end < TWR) || (ck_cntr - ck_write < write_latency + burst_length/2)) $display ("%m: at time %t ERROR: tWRPDEN violation during %s", $time, cmd_string[cmd]); end
// read
{1'bx, SAME_BANK , READ , PRECHARGE} : begin if (($time - tm_bank_read_end[bank] < TRTP) || (ck_cntr - ck_bank_read[bank] < additive_latency + TRTP_TCK)) $display ("%m: at time %t ERROR: tRTP violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, DIFF_BANK , READ , WRITE } : ; // tRTW is checked outside this task
{1'b1, DIFF_BANK , READ , WRITE } : ; // tRTW is checked outside this task
{1'b0, DIFF_BANK , READ , READ } : begin if (ck_cntr - ck_read < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_BANK , READ , READ } : begin if (ck_cntr - ck_group_read[bank[1]] < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_GROUP, READ , WRITE } : ; // tRTW is checked outside this task
{1'b1, DIFF_GROUP, READ , READ } : begin if (ck_cntr - ck_read < TCCD_DG) $display ("%m: at time %t ERROR: tCCD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, DIFF_BANK , READ , PWR_DOWN } : begin if (ck_cntr - ck_read < read_latency + 5) $display ("%m: at time %t ERROR: tRDPDEN violation during %s", $time, cmd_string[cmd]); end
// zq
{1'bx, DIFF_BANK , ZQ , LOAD_MODE} : ; // 1 tCK
{1'bx, DIFF_BANK , ZQ , REFRESH } ,
{1'bx, DIFF_BANK , ZQ , PRECHARGE} ,
{1'bx, DIFF_BANK , ZQ , ACTIVATE } ,
{1'bx, DIFF_BANK , ZQ , ZQ } ,
{1'bx, DIFF_BANK , ZQ , PWR_DOWN } ,
{1'bx, DIFF_BANK , ZQ , SELF_REF } : begin if (ck_cntr - ck_zqinit < TZQINIT) $display ("%m: at time %t ERROR: tZQinit violation during %s", $time, cmd_string[cmd]);
if (ck_cntr - ck_zqoper < TZQOPER) $display ("%m: at time %t ERROR: tZQoper violation during %s", $time, cmd_string[cmd]);
if (ck_cntr - ck_zqcs < TZQCS) $display ("%m: at time %t ERROR: tZQCS violation during %s", $time, cmd_string[cmd]); end
// power down
{1'bx, DIFF_BANK , PWR_DOWN , LOAD_MODE} ,
{1'bx, DIFF_BANK , PWR_DOWN , REFRESH } ,
{1'bx, DIFF_BANK , PWR_DOWN , PRECHARGE} ,
{1'bx, DIFF_BANK , PWR_DOWN , ACTIVATE } ,
{1'bx, DIFF_BANK , PWR_DOWN , WRITE } ,
{1'bx, DIFF_BANK , PWR_DOWN , ZQ } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , PWR_DOWN , READ } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]);
else if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) $display ("%m: at time %t ERROR: tXPDLL violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , PWR_DOWN , PWR_DOWN } ,
{1'bx, DIFF_BANK , PWR_DOWN , SELF_REF } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]);
if ((tm_power_down > tm_refresh) && ($time - tm_refresh < TRFC_MIN)) $display ("%m: at time %t ERROR: tRFC violation during %s", $time, cmd_string[cmd]);
if ((tm_refresh > tm_power_down) && (($time - tm_power_down < TXPDLL) || (ck_cntr - ck_power_down < TXPDLL_TCK))) $display ("%m: at time %t ERROR: tXPDLL violation during %s", $time, cmd_string[cmd]);
if (($time - tm_cke_cmd < TCKE) || (ck_cntr - ck_cke_cmd < TCKE_TCK)) $display ("%m: at time %t ERROR: tCKE violation on CKE", $time); end
// self refresh
{1'bx, DIFF_BANK , SELF_REF , LOAD_MODE} ,
{1'bx, DIFF_BANK , SELF_REF , REFRESH } ,
{1'bx, DIFF_BANK , SELF_REF , PRECHARGE} ,
{1'bx, DIFF_BANK , SELF_REF , ACTIVATE } ,
{1'bx, DIFF_BANK , SELF_REF , WRITE } ,
{1'bx, DIFF_BANK , SELF_REF , ZQ } : begin if (($time - tm_self_refresh < TXS) || (ck_cntr - ck_self_refresh < TXS_TCK)) $display ("%m: at time %t ERROR: tXS violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , SELF_REF , READ } : begin if (ck_cntr - ck_self_refresh < TXSDLL) $display ("%m: at time %t ERROR: tXSDLL violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , SELF_REF , PWR_DOWN } ,
{1'bx, DIFF_BANK , SELF_REF , SELF_REF } : begin if (($time - tm_self_refresh < TXS) || (ck_cntr - ck_self_refresh < TXS_TCK)) $display ("%m: at time %t ERROR: tXS violation during %s", $time, cmd_string[cmd]);
if (($time - tm_cke_cmd < TCKE) || (ck_cntr - ck_cke_cmd < TCKE_TCK)) $display ("%m: at time %t ERROR: tCKE violation on CKE", $time); end
endcase
end
endtask
task cmd_task;
input cke;
input [2:0] cmd;
input [BA_BITS-1:0] bank;
input [ADDR_BITS-1:0] addr;
reg [`BANKS:0] i;
integer j;
reg [`BANKS:0] tfaw_cntr;
reg [COL_BITS-1:0] col;
reg group;
begin
// tRFC max check
if (!er_trfc_max && !in_self_refresh) begin
if ($time - tm_refresh > TRFC_MAX && check_strict_timing) begin
$display ("%m: at time %t ERROR: tRFC maximum violation during %s", $time, cmd_string[cmd]);
er_trfc_max = 1;
end
end
if (cke) begin
if ((cmd < NOP) && (cmd != PRECHARGE)) begin
if (($time - tm_txpr < TXPR) || (ck_cntr - ck_txpr < TXPR_TCK))
$display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[cmd]);
for (j=0; j<=SELF_REF; j=j+1) begin
chk_err(SAME_BANK , bank, j, cmd);
chk_err(DIFF_BANK , bank, j, cmd);
chk_err(DIFF_GROUP, bank, j, cmd);
end
end
case (cmd)
LOAD_MODE : begin
if (|odt_pipeline)
$display ("%m: at time %t ERROR: ODTL violation during %s", $time, cmd_string[cmd]);
if (odt_state)
$display ("%m: at time %t ERROR: ODT must be off prior to %s", $time, cmd_string[cmd]);
if (|active_bank) begin
$display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d", $time, cmd_string[cmd], bank);
if (bank>>2) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved bank bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
case (bank)
0 : begin
// Burst Length
if (addr[1:0] == 2'b00) begin
burst_length = 8;
blotf = 0;
truebl4 = 0;
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = %d", $time, cmd_string[cmd], bank, burst_length);
end else if (addr[1:0] == 2'b01) begin
burst_length = 8;
blotf = 1;
truebl4 = 0;
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = Select via A12", $time, cmd_string[cmd], bank);
end else if (addr[1:0] == 2'b10) begin
burst_length = 4;
blotf = 0;
truebl4 = 0;
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = Fixed %d (chop)", $time, cmd_string[cmd], bank, burst_length);
end else if (feature_truebl4 && (addr[1:0] == 2'b11)) begin
burst_length = 4;
blotf = 0;
truebl4 = 1;
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = True %d", $time, cmd_string[cmd], bank, burst_length);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Burst Length = %d", $time, cmd_string[cmd], bank, addr[1:0]);
end
// Burst Order
burst_order = addr[3];
if (!burst_order) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Sequential", $time, cmd_string[cmd], bank);
end else if (burst_order) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Interleaved", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Burst Order = %d", $time, cmd_string[cmd], bank, burst_order);
end
// CAS Latency
cas_latency = {addr[2],addr[6:4]} + 4;
set_latency;
if ((cas_latency >= CL_MIN) && (cas_latency <= CL_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
end
// Reserved
if (addr[7] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// DLL Reset
dll_reset = addr[8];
if (!dll_reset) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Normal", $time, cmd_string[cmd], bank);
end else if (dll_reset) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Reset DLL", $time, cmd_string[cmd], bank);
dll_locked = 0;
init_dll_reset = 1;
ck_dll_reset <= ck_cntr;
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal DLL Reset = %d", $time, cmd_string[cmd], bank, dll_reset);
end
// Write Recovery
if (addr[11:9] == 0) begin
write_recovery = 16;
end else if (addr[11:9] < 4) begin
write_recovery = addr[11:9] + 4;
end else begin
write_recovery = 2*addr[11:9];
end
if ((write_recovery >= WR_MIN) && (write_recovery <= WR_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
end
// Power Down Mode
low_power = !addr[12];
if (!low_power) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = DLL on", $time, cmd_string[cmd], bank);
end else if (low_power) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = DLL off", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Power Down Mode = %d", $time, cmd_string[cmd], bank, low_power);
end
// Reserved
if (ADDR_BITS>13 && addr[13] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
1 : begin
// DLL Enable
dll_en = !addr[0];
if (!dll_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Disabled", $time, cmd_string[cmd], bank);
if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d DLL off mode is not modeled", $time, cmd_string[cmd], bank);
end else if (dll_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal DLL Enable = %d", $time, cmd_string[cmd], bank, dll_en);
end
// Output Drive Strength
if ({addr[5], addr[1]} == 2'b00) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/6);
end else if ({addr[5], addr[1]} == 2'b01) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/7);
end else if ({addr[5], addr[1]} == 2'b11) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/5);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Output Drive Strength = %d", $time, cmd_string[cmd], bank, {addr[5], addr[1]});
end
// ODT Rtt (Rtt_NOM)
odt_rtt_nom = {addr[9], addr[6], addr[2]};
if (odt_rtt_nom == 3'b000) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = Disabled", $time, cmd_string[cmd], bank);
odt_en = 0;
end else if ((odt_rtt_nom < 4) || ((!addr[7] || (addr[7] && addr[12])) && (odt_rtt_nom < 6))) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = %d Ohm", $time, cmd_string[cmd], bank, get_rtt_nom(odt_rtt_nom));
odt_en = 1;
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal ODT Rtt = %d", $time, cmd_string[cmd], bank, odt_rtt_nom);
odt_en = 0;
end
// Report the additive latency value
al = addr[4:3];
set_latency;
if (al == 0) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = %d", $time, cmd_string[cmd], bank, al);
end else if ((al >= AL_MIN) && (al <= AL_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = CL - %d", $time, cmd_string[cmd], bank, al);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Additive Latency = %d", $time, cmd_string[cmd], bank, al);
end
// Write Levelization
write_levelization = addr[7];
if (!write_levelization) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Levelization = Disabled", $time, cmd_string[cmd], bank);
end else if (write_levelization) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Levelization = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Write Levelization = %d", $time, cmd_string[cmd], bank, write_levelization);
end
// Reserved
if (addr[8] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// Reserved
if (addr[10] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// TDQS Enable
tdqs_en = addr[11];
if (!tdqs_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d TDQS Enable = Disabled", $time, cmd_string[cmd], bank);
end else if (tdqs_en) begin
if (8 == DQ_BITS) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d TDQS Enable = Enabled", $time, cmd_string[cmd], bank);
end
else begin
$display ("%m: at time %t WARNING: %s %d Illegal TDQS Enable. TDQS only exists on a x8 part", $time, cmd_string[cmd], bank);
tdqs_en = 0;
end
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal TDQS Enable = %d", $time, cmd_string[cmd], bank, tdqs_en);
end
// Output Enable
out_en = !addr[12];
if (!out_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Qoff = Disabled", $time, cmd_string[cmd], bank);
end else if (out_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Qoff = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Qoff = %d", $time, cmd_string[cmd], bank, out_en);
end
// Reserved
if (ADDR_BITS>13 && addr[13] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
2 : begin
if (feature_pasr) begin
// Partial Array Self Refresh
pasr = addr[2:0];
case (pasr)
3'b000 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-7", $time, cmd_string[cmd], bank);
3'b001 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-3", $time, cmd_string[cmd], bank);
3'b010 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-1", $time, cmd_string[cmd], bank);
3'b011 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0", $time, cmd_string[cmd], bank);
3'b100 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 2-7", $time, cmd_string[cmd], bank);
3'b101 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 4-7", $time, cmd_string[cmd], bank);
3'b110 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 6-7", $time, cmd_string[cmd], bank);
3'b111 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 7", $time, cmd_string[cmd], bank);
default : $display ("%m: at time %t ERROR: %s %d Illegal Partial Array Self Refresh = %d", $time, cmd_string[cmd], bank, pasr);
endcase
end
else
if (addr[2:0] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// CAS Write Latency
cas_write_latency = addr[5:3]+5;
set_latency;
if ((cas_write_latency >= CWL_MIN) && (cas_write_latency <= CWL_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Write Latency = %d", $time, cmd_string[cmd], bank, cas_write_latency);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal CAS Write Latency = %d", $time, cmd_string[cmd], bank, cas_write_latency);
end
// Auto Self Refresh Method
asr = addr[6];
if (!asr) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Auto Self Refresh = Disabled", $time, cmd_string[cmd], bank);
end else if (asr) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Auto Self Refresh = Enabled", $time, cmd_string[cmd], bank);
if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d Auto Self Refresh is not modeled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Auto Self Refresh = %d", $time, cmd_string[cmd], bank, asr);
end
// Self Refresh Temperature
srt = addr[7];
if (!srt) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Self Refresh Temperature = Normal", $time, cmd_string[cmd], bank);
end else if (srt) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Self Refresh Temperature = Extended", $time, cmd_string[cmd], bank);
if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d Self Refresh Temperature is not modeled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Self Refresh Temperature = %d", $time, cmd_string[cmd], bank, srt);
end
if (asr && srt)
$display ("%m: at time %t ERROR: %s %d SRT must be set to 0 when ASR is enabled.", $time, cmd_string[cmd], bank);
// Reserved
if (addr[8] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// Dynamic ODT (Rtt_WR)
odt_rtt_wr = addr[10:9];
if (odt_rtt_wr == 2'b00) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Dynamic ODT = Disabled", $time, cmd_string[cmd], bank);
dyn_odt_en = 0;
end else if ((odt_rtt_wr > 0) && (odt_rtt_wr < 3)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Dynamic ODT Rtt = %d Ohm", $time, cmd_string[cmd], bank, get_rtt_wr(odt_rtt_wr));
dyn_odt_en = 1;
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Dynamic ODT = %d", $time, cmd_string[cmd], bank, odt_rtt_wr);
dyn_odt_en = 0;
end
// Reserved
if (ADDR_BITS>13 && addr[13:11] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
3 : begin
mpr_select = addr[1:0];
// MultiPurpose Register Select
if (mpr_select == 2'b00) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Select = Pre-defined pattern", $time, cmd_string[cmd], bank);
end else begin
if (check_strict_mrbits) $display ("%m: at time %t ERROR: %s %d Illegal MultiPurpose Register Select = %d", $time, cmd_string[cmd], bank, mpr_select);
end
// MultiPurpose Register Enable
mpr_en = addr[2];
if (!mpr_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Enable = Disabled", $time, cmd_string[cmd], bank);
end else if (mpr_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Enable = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal MultiPurpose Register Enable = %d", $time, cmd_string[cmd], bank, mpr_en);
end
// Reserved
if (ADDR_BITS>13 && addr[13:3] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
endcase
if (dyn_odt_en && write_levelization)
$display ("%m: at time %t ERROR: Dynamic ODT is not available during Write Leveling mode.", $time);
init_mode_reg[bank] = 1;
mode_reg[bank] = addr;
tm_load_mode <= $time;
ck_load_mode <= ck_cntr;
end
end
REFRESH : begin
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (|active_bank) begin
$display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s", $time, cmd_string[cmd]);
er_trfc_max = 0;
ref_cntr = ref_cntr + 1;
tm_refresh <= $time;
ck_refresh <= ck_cntr;
end
end
PRECHARGE : begin
if (addr[AP]) begin
if (DEBUG) $display ("%m: at time %t INFO: %s All", $time, cmd_string[cmd]);
end
// PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state),
// or if the previously open row is already in the process of precharging
if (|active_bank) begin
if (($time - tm_txpr < TXPR) || (ck_cntr - ck_txpr < TXPR_TCK))
$display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[cmd]);
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
for (i=0; i<`BANKS; i=i+1) begin
if (active_bank[i]) begin
if (addr[AP] || (i == bank)) begin
for (j=0; j<=SELF_REF; j=j+1) begin
chk_err(SAME_BANK, i, j, cmd);
chk_err(DIFF_BANK, i, j, cmd);
end
if (auto_precharge_bank[i]) begin
$display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], i);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d", $time, cmd_string[cmd], i);
active_bank[i] = 1'b0;
tm_bank_precharge[i] <= $time;
tm_precharge <= $time;
ck_precharge <= ck_cntr;
end
end
end
end
end
end
end
ACTIVATE : begin
tfaw_cntr = 0;
for (i=0; i<`BANKS; i=i+1) begin
if ($time - tm_bank_activate[i] < TFAW) begin
tfaw_cntr = tfaw_cntr + 1;
end
end
if (tfaw_cntr > 3) begin
$display ("%m: at time %t ERROR: tFAW violation during %s to bank %d", $time, cmd_string[cmd], bank);
end
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (active_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Bank %d must be Precharged.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (addr >= 1<<ROW_BITS) begin
$display ("%m: at time %t WARNING: row = %h does not exist. Maximum row = %h", $time, addr, (1<<ROW_BITS)-1);
end
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d row %h", $time, cmd_string[cmd], bank, addr);
active_bank[bank] = 1'b1;
active_row[bank] = addr;
tm_group_activate[bank[1]] <= $time;
tm_activate <= $time;
tm_bank_activate[bank] <= $time;
ck_group_activate[bank[1]] <= ck_cntr;
ck_activate <= ck_cntr;
end
end
WRITE : begin
if ((!rd_bc && blotf) || (burst_length == 4)) begin // BL=4
if (truebl4) begin
if (ck_cntr - ck_group_read[bank[1]] < read_latency + TCCD/2 + 2 - write_latency)
$display ("%m: at time %t ERROR: tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank);
if (ck_cntr - ck_read < read_latency + TCCD_DG/2 + 2 - write_latency)
$display ("%m: at time %t ERROR: tRTW_DG violation during %s to bank %d", $time, cmd_string[cmd], bank);
end else begin
if (ck_cntr - ck_read < read_latency + TCCD/2 + 2 - write_latency)
$display ("%m: at time %t ERROR: tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank);
end
end else begin // BL=8
if (ck_cntr - ck_read < read_latency + TCCD + 2 - write_latency)
$display ("%m: at time %t ERROR: tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank);
end
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!active_bank[bank]) begin
if (check_strict_timing) $display ("%m: at time %t ERROR: %s Failure. Bank %d must be Activated.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (auto_precharge_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (ck_cntr - ck_write < burst_length/2) begin
$display ("%m: at time %t ERROR: %s Failure. Illegal burst interruption.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (addr[AP]) begin
auto_precharge_bank[bank] = 1'b1;
write_precharge_bank[bank] = 1'b1;
end
col = {addr[BC-1:AP+1], addr[AP-1:0]}; // assume BC > AP
if (col >= 1<<COL_BITS) begin
$display ("%m: at time %t WARNING: col = %h does not exist. Maximum col = %h", $time, col, (1<<COL_BITS)-1);
end
if ((!addr[BC] && blotf) || (burst_length == 4)) begin // BL=4
col = col & -4;
end else begin // BL=8
col = col & -8;
end
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
wr_pipeline[2*write_latency + 1] = 1;
ba_pipeline[2*write_latency + 1] = bank;
row_pipeline[2*write_latency + 1] = active_row[bank];
col_pipeline[2*write_latency + 1] = col;
if ((!addr[BC] && blotf) || (burst_length == 4)) begin // BL=4
bl_pipeline[2*write_latency + 1] = 4;
if (mpr_en && col%4) begin
$display ("%m: at time %t WARNING: col[1:0] must be set to 2'b00 during a BL4 Multipurpose Register read", $time);
end
end else begin // BL=8
bl_pipeline[2*write_latency + 1] = 8;
if (odt_in) begin
ck_odth8 <= ck_cntr;
end
end
for (j=0; j<(burst_length + 4); j=j+1) begin
dyn_odt_pipeline[2*(write_latency - 2) + j] = 1'b1; // ODTLcnw = WL - 2, ODTLcwn = BL/2 + 2
end
ck_bank_write[bank] <= ck_cntr;
ck_group_write[bank[1]] <= ck_cntr;
ck_write <= ck_cntr;
end
end
READ : begin
if (!dll_locked)
$display ("%m: at time %t WARNING: tDLLK violation during %s.", $time, cmd_string[cmd]);
if (mpr_en && (addr[1:0] != 2'b00)) begin
$display ("%m: at time %t ERROR: %s Failure. addr[1:0] must be zero during Multipurpose Register Read.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!active_bank[bank] && !mpr_en) begin
if (check_strict_timing) $display ("%m: at time %t ERROR: %s Failure. Bank %d must be Activated.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (auto_precharge_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (ck_cntr - ck_read < burst_length/2) begin
$display ("%m: at time %t ERROR: %s Failure. Illegal burst interruption.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (addr[AP] && !mpr_en) begin
auto_precharge_bank[bank] = 1'b1;
read_precharge_bank[bank] = 1'b1;
end
col = {addr[BC-1:AP+1], addr[AP-1:0]}; // assume BC > AP
if (col >= 1<<COL_BITS) begin
$display ("%m: at time %t WARNING: col = %h does not exist. Maximum col = %h", $time, col, (1<<COL_BITS)-1);
end
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
rd_pipeline[2*read_latency - 1] = 1;
ba_pipeline[2*read_latency - 1] = bank;
row_pipeline[2*read_latency - 1] = active_row[bank];
col_pipeline[2*read_latency - 1] = col;
if ((!addr[BC] && blotf) || (burst_length == 4)) begin // BL=4
bl_pipeline[2*read_latency - 1] = 4;
if (mpr_en && col%4) begin
$display ("%m: at time %t WARNING: col[1:0] must be set to 2'b00 during a BL4 Multipurpose Register read", $time);
end
end else begin // BL=8
bl_pipeline[2*read_latency - 1] = 8;
if (mpr_en && col%8) begin
$display ("%m: at time %t WARNING: col[2:0] must be set to 3'b000 during a BL8 Multipurpose Register read", $time);
end
end
rd_bc = addr[BC];
ck_bank_read[bank] <= ck_cntr;
ck_group_read[bank[1]] <= ck_cntr;
ck_read <= ck_cntr;
end
end
ZQ : begin
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (|active_bank) begin
$display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s long = %d", $time, cmd_string[cmd], addr[AP]);
if (addr[AP]) begin
zq_set = 1;
if (init_done) begin
ck_zqoper <= ck_cntr;
end else begin
ck_zqinit <= ck_cntr;
end
end else begin
ck_zqcs <= ck_cntr;
end
end
end
NOP: begin
if (in_power_down) begin
if (($time - tm_freq_change < TCKSRX) || (ck_cntr - ck_freq_change < TCKSRX_TCK))
$display ("%m: at time %t ERROR: tCKSRX violation during Power Down Exit", $time);
if ($time - tm_cke_cmd > TPD_MAX)
$display ("%m: at time %t ERROR: tPD maximum violation during Power Down Exit", $time);
if (DEBUG) $display ("%m: at time %t INFO: Power Down Exit", $time);
in_power_down = 0;
if ((active_bank == 0) && low_power) begin // precharge power down with dll off
if (ck_cntr - ck_odt < write_latency - 1)
$display ("%m: at time %t WARNING: tANPD violation during Power Down Exit. Synchronous or asynchronous change in termination resistance is possible.", $time);
tm_slow_exit_pd <= $time;
ck_slow_exit_pd <= ck_cntr;
end
tm_power_down <= $time;
ck_power_down <= ck_cntr;
end
if (in_self_refresh) begin
if (($time - tm_freq_change < TCKSRX) || (ck_cntr - ck_freq_change < TCKSRX_TCK))
$display ("%m: at time %t ERROR: tCKSRX violation during Self Refresh Exit", $time);
if (ck_cntr - ck_cke_cmd < TCKESR_TCK)
$display ("%m: at time %t ERROR: tCKESR violation during Self Refresh Exit", $time);
if ($time - tm_cke < TISXR)
$display ("%m: at time %t ERROR: tISXR violation during Self Refresh Exit", $time);
if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Exit", $time);
in_self_refresh = 0;
ck_dll_reset <= ck_cntr;
ck_self_refresh <= ck_cntr;
tm_self_refresh <= $time;
tm_refresh <= $time;
end
end
endcase
if ((prev_cke !== 1) && (cmd !== NOP)) begin
$display ("%m: at time %t ERROR: NOP or Deselect is required when CKE goes active.", $time);
end
if (!init_done) begin
case (init_step)
0 : begin
if ($time - tm_rst_n < 500000000 && check_strict_timing)
$display ("%m at time %t WARNING: 500 us is required after RST_N goes inactive before CKE goes active.", $time);
tm_txpr <= $time;
ck_txpr <= ck_cntr;
init_step = init_step + 1;
end
1 : if (dll_en) init_step = init_step + 1;
2 : begin
if (&init_mode_reg && init_dll_reset && zq_set) begin
if (DEBUG) $display ("%m: at time %t INFO: Initialization Sequence is complete", $time);
init_done = 1;
end
end
endcase
end
end else if (prev_cke) begin
if ((!init_done) && (init_step > 1)) begin
$display ("%m: at time %t ERROR: CKE must remain active until the initialization sequence is complete.", $time);
if (STOP_ON_ERROR) $stop(0);
end
case (cmd)
REFRESH : begin
if ($time - tm_txpr < TXPR)
$display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[SELF_REF]);
for (j=0; j<=SELF_REF; j=j+1) begin
chk_err(DIFF_BANK, bank, j, SELF_REF);
end
if (mpr_en) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. Multipurpose Register must be disabled.", $time);
if (STOP_ON_ERROR) $stop(0);
end else if (|active_bank) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. All banks must be Precharged.", $time);
if (STOP_ON_ERROR) $stop(0);
end else if (odt_state) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. ODT must be off prior to entering Self Refresh", $time);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. Initialization sequence is not complete.", $time);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Enter", $time);
if (feature_pasr)
// Partial Array Self Refresh
case (pasr)
3'b000 : ;//keep Bank 0-7
3'b001 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 4-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hF0); end
3'b010 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 2-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hFC); end
3'b011 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 1-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hFE); end
3'b100 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-1 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h03); end
3'b101 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-3 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h0F); end
3'b110 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-5 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h3F); end
3'b111 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-6 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h7F); end
endcase
in_self_refresh = 1;
dll_locked = 0;
end
end
NOP : begin
// entering precharge power down with dll off and tANPD has not been satisfied
if (low_power && (active_bank == 0) && |odt_pipeline)
$display ("%m: at time %t WARNING: tANPD violation during %s. Synchronous or asynchronous change in termination resistance is possible.", $time, cmd_string[PWR_DOWN]);
if ($time - tm_txpr < TXPR)
$display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[PWR_DOWN]);
for (j=0; j<=SELF_REF; j=j+1) begin
chk_err(DIFF_BANK, bank, j, PWR_DOWN);
end
if (mpr_en) begin
$display ("%m: at time %t ERROR: Power Down Failure. Multipurpose Register must be disabled.", $time);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: Power Down Failure. Initialization sequence is not complete.", $time);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) begin
if (|active_bank) begin
$display ("%m: at time %t INFO: Active Power Down Enter", $time);
end else begin
$display ("%m: at time %t INFO: Precharge Power Down Enter", $time);
end
end
in_power_down = 1;
end
end
default : begin
$display ("%m: at time %t ERROR: NOP, Deselect, or Refresh is required when CKE goes inactive.", $time);
end
endcase
end else if (in_self_refresh || in_power_down) begin
if ((ck_cntr - ck_cke_cmd <= TCPDED) && (cmd !== NOP))
$display ("%m: at time %t ERROR: tCPDED violation during Power Down or Self Refresh Entry. NOP or Deselect is required.", $time);
end
prev_cke = cke;
end
endtask
task data_task;
reg [BA_BITS-1:0] bank;
reg [ROW_BITS-1:0] row;
reg [COL_BITS-1:0] col;
integer i;
integer j;
begin
if (diff_ck) begin
for (i=0; i<32; i=i+1) begin
if (dq_in_valid && dll_locked && ($time - tm_dqs_neg[i] < $rtoi(TDSS*tck_avg)))
$display ("%m: at time %t ERROR: tDSS violation on %s bit %d", $time, dqs_string[i/16], i%16);
if (check_write_dqs_high[i])
$display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period.", $time, dqs_string[i/16], i%16);
end
check_write_dqs_high <= 0;
end else begin
for (i=0; i<32; i=i+1) begin
if (dll_locked && dq_in_valid) begin
tm_tdqss = abs_value(1.0*tm_ck_pos - tm_dqss_pos[i]);
if ((tm_tdqss < tck_avg/2.0) && (tm_tdqss > TDQSS*tck_avg))
$display ("%m: at time %t ERROR: tDQSS violation on %s bit %d", $time, dqs_string[i/16], i%16);
end
if (check_write_dqs_low[i])
$display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period", $time, dqs_string[i/16], i%16);
end
check_write_preamble <= 0;
check_write_postamble <= 0;
check_write_dqs_low <= 0;
end
if (wr_pipeline[0] || rd_pipeline[0]) begin
bank = ba_pipeline[0];
row = row_pipeline[0];
col = col_pipeline[0];
burst_cntr = 0;
memory_read(bank, row, col, memory_data);
end
// burst counter
if (burst_cntr < burst_length) begin
burst_position = col ^ burst_cntr;
if (!burst_order) begin
burst_position[BO_BITS-1:0] = col + burst_cntr;
end
burst_cntr = burst_cntr + 1;
end
// write dqs counter
if (wr_pipeline[WDQS_PRE + 1]) begin
wdqs_cntr = WDQS_PRE + bl_pipeline[WDQS_PRE + 1] + WDQS_PST - 1;
end
// write dqs
if ((wr_pipeline[2]) && (wdq_cntr == 0)) begin //write preamble
check_write_preamble <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}};
end
if (wdqs_cntr > 1) begin // write data
if ((wdqs_cntr - WDQS_PST)%2) begin
check_write_dqs_high <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}};
end else begin
check_write_dqs_low <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}};
end
end
if (wdqs_cntr == WDQS_PST) begin // write postamble
check_write_postamble <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}};
end
if (wdqs_cntr > 0) begin
wdqs_cntr = wdqs_cntr - 1;
end
// write dq
if (dq_in_valid) begin // write data
bit_mask = 0;
if (diff_ck) begin
for (i=0; i<DM_BITS; i=i+1) begin
bit_mask = bit_mask | ({`DQ_PER_DQS{~dm_in_neg[i]}}<<(burst_position*DQ_BITS + i*`DQ_PER_DQS));
end
memory_data = (dq_in_neg<<(burst_position*DQ_BITS) & bit_mask) | (memory_data & ~bit_mask);
end else begin
for (i=0; i<DM_BITS; i=i+1) begin
bit_mask = bit_mask | ({`DQ_PER_DQS{~dm_in_pos[i]}}<<(burst_position*DQ_BITS + i*`DQ_PER_DQS));
end
memory_data = (dq_in_pos<<(burst_position*DQ_BITS) & bit_mask) | (memory_data & ~bit_mask);
end
dq_temp = memory_data>>(burst_position*DQ_BITS);
if (DEBUG) $display ("%m: at time %t INFO: WRITE @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp);
if (burst_cntr%BL_MIN == 0) begin
memory_write(bank, row, col, memory_data);
end
end
if (wr_pipeline[1]) begin
wdq_cntr = bl_pipeline[1];
end
if (wdq_cntr > 0) begin
wdq_cntr = wdq_cntr - 1;
dq_in_valid = 1'b1;
end else begin
dq_in_valid = 1'b0;
dqs_in_valid <= 1'b0;
for (i=0; i<31; i=i+1) begin
wdqs_pos_cntr[i] <= 0;
end
end
if (wr_pipeline[0]) begin
b2b_write <= 1'b0;
end
if (wr_pipeline[2]) begin
if (dqs_in_valid) begin
b2b_write <= 1'b1;
end
dqs_in_valid <= 1'b1;
wr_burst_length = bl_pipeline[2];
end
// read dqs enable counter
if (rd_pipeline[RDQSEN_PRE]) begin
rdqsen_cntr = RDQSEN_PRE + bl_pipeline[RDQSEN_PRE] + RDQSEN_PST - 1;
end
if (rdqsen_cntr > 0) begin
rdqsen_cntr = rdqsen_cntr - 1;
dqs_out_en = 1'b1;
end else begin
dqs_out_en = 1'b0;
end
// read dqs counter
if (rd_pipeline[RDQS_PRE]) begin
rdqs_cntr = RDQS_PRE + bl_pipeline[RDQS_PRE] + RDQS_PST - 1;
end
// read dqs
if (((rd_pipeline>>1 & {RDQS_PRE{1'b1}}) > 0) && (rdq_cntr == 0)) begin //read preamble
dqs_out = 1'b0;
end else if (rdqs_cntr > RDQS_PST) begin // read data
dqs_out = rdqs_cntr - RDQS_PST;
end else if (rdqs_cntr > 0) begin // read postamble
dqs_out = 1'b0;
end else begin
dqs_out = 1'b1;
end
if (rdqs_cntr > 0) begin
rdqs_cntr = rdqs_cntr - 1;
end
// read dq enable counter
if (rd_pipeline[RDQEN_PRE]) begin
rdqen_cntr = RDQEN_PRE + bl_pipeline[RDQEN_PRE] + RDQEN_PST;
end
if (rdqen_cntr > 0) begin
rdqen_cntr = rdqen_cntr - 1;
dq_out_en = 1'b1;
end else begin
dq_out_en = 1'b0;
end
// read dq
if (rd_pipeline[0]) begin
rdq_cntr = bl_pipeline[0];
end
if (rdq_cntr > 0) begin // read data
if (mpr_en) begin
`ifdef MPR_DQ0 // DQ0 output MPR data, other DQ low
if (mpr_select == 2'b00) begin // Calibration Pattern
dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, calibration_pattern[burst_position]}};
end else if (odts_readout && (mpr_select == 2'b11)) begin // Temp Sensor (ODTS)
dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, temp_sensor[burst_position]}};
end else begin // Reserved
dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, 1'bx}};
end
`else // all DQ output MPR data
if (mpr_select == 2'b00) begin // Calibration Pattern
dq_temp = {DQS_BITS{{`DQ_PER_DQS{calibration_pattern[burst_position]}}}};
end else if (odts_readout && (mpr_select == 2'b11)) begin // Temp Sensor (ODTS)
dq_temp = {DQS_BITS{{`DQ_PER_DQS{temp_sensor[burst_position]}}}};
end else begin // Reserved
dq_temp = {DQS_BITS{{`DQ_PER_DQS{1'bx}}}};
end
`endif
if (DEBUG) $display ("%m: at time %t READ @ DQS MultiPurpose Register %d, col = %d, data = %b", $time, mpr_select, burst_position, dq_temp[0]);
end else begin
dq_temp = memory_data>>(burst_position*DQ_BITS);
if (DEBUG) $display ("%m: at time %t INFO: READ @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp);
end
dq_out = dq_temp;
rdq_cntr = rdq_cntr - 1;
end else begin
dq_out = {DQ_BITS{1'b1}};
end
// delay signals prior to output
if (RANDOM_OUT_DELAY && (dqs_out_en || (|dqs_out_en_dly) || dq_out_en || (|dq_out_en_dly))) begin
for (i=0; i<DQS_BITS; i=i+1) begin
// DQSCK requirements
// 1.) less than tDQSCK
// 2.) greater than -tDQSCK
// 3.) cannot change more than tQH + tDQSQ from previous DQS edge
dqsck_max = TDQSCK;
if (dqsck_max > dqsck[i] + TQH*tck_avg + TDQSQ) begin
dqsck_max = dqsck[i] + TQH*tck_avg + TDQSQ;
end
dqsck_min = -1*TDQSCK;
if (dqsck_min < dqsck[i] - TQH*tck_avg - TDQSQ) begin
dqsck_min = dqsck[i] - TQH*tck_avg - TDQSQ;
end
// DQSQ requirements
// 1.) less than tDQSQ
// 2.) greater than 0
// 3.) greater than tQH from the previous DQS edge
dqsq_min = 0;
if (dqsq_min < dqsck[i] - TQH*tck_avg) begin
dqsq_min = dqsck[i] - TQH*tck_avg;
end
if (dqsck_min == dqsck_max) begin
dqsck[i] = dqsck_min;
end else begin
dqsck[i] = $dist_uniform(seed, dqsck_min, dqsck_max);
end
dqsq_max = TDQSQ + dqsck[i];
dqs_out_en_dly[i] <= #(tck_avg/2) dqs_out_en;
dqs_out_dly[i] <= #(tck_avg/2 + dqsck[i]) dqs_out;
if (!write_levelization) begin
for (j=0; j<`DQ_PER_DQS; j=j+1) begin
dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2) dq_out_en;
if (dqsq_min == dqsq_max) begin
dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2 + dqsq_min) dq_out[i*`DQ_PER_DQS + j];
end else begin
dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2 + $dist_uniform(seed, dqsq_min, dqsq_max)) dq_out[i*`DQ_PER_DQS + j];
end
end
end
end
end else begin
out_delay = tck_avg/2;
dqs_out_en_dly <= #(out_delay) {DQS_BITS{dqs_out_en}};
dqs_out_dly <= #(out_delay) {DQS_BITS{dqs_out }};
if (write_levelization !== 1'b1) begin
dq_out_en_dly <= #(out_delay) {DQ_BITS {dq_out_en }};
dq_out_dly <= #(out_delay) {DQ_BITS {dq_out }};
end
end
end
endtask
always @ (posedge rst_n_in) begin : reset
integer i;
if (rst_n_in) begin
if ($time < 200000000 && check_strict_timing)
$display ("%m at time %t WARNING: 200 us is required before RST_N goes inactive.", $time);
if (cke_in !== 1'b0)
$display ("%m: at time %t ERROR: CKE must be inactive when RST_N goes inactive.", $time);
if ($time - tm_cke < 10000)
$display ("%m: at time %t ERROR: CKE must be maintained inactive for 10 ns before RST_N goes inactive.", $time);
// clear memory
`ifdef MAX_MEM
// verification group does not erase memory
// for (banki = 0; banki < `BANKS; banki = banki + 1) begin
// $fclose(memfd[banki]);
// memfd[banki] = open_bank_file(banki);
// end
`else
memory_used <= 0; //erase memory
`endif
end
end
always @(negedge rst_n_in or posedge diff_ck or negedge diff_ck) begin : main
integer i;
if (!rst_n_in) begin
reset_task;
end else begin
if (!in_self_refresh && (diff_ck !== 1'b0) && (diff_ck !== 1'b1))
$display ("%m: at time %t ERROR: CK and CK_N are not allowed to go to an unknown state.", $time);
data_task;
// Clock Frequency Change is legal:
// 1.) During Self Refresh
// 2.) During Precharge Power Down (DLL on or off)
if (in_self_refresh || (in_power_down && (active_bank == 0))) begin
if (diff_ck) begin
tjit_per_rtime = $time - tm_ck_pos - tck_avg;
end else begin
tjit_per_rtime = $time - tm_ck_neg - tck_avg;
end
if (dll_locked && (abs_value(tjit_per_rtime) > TJIT_PER)) begin
if ((tm_ck_pos - tm_cke_cmd < TCKSRE) || (ck_cntr - ck_cke_cmd < TCKSRE_TCK))
$display ("%m: at time %t ERROR: tCKSRE violation during Self Refresh or Precharge Power Down Entry", $time);
if (odt_state) begin
$display ("%m: at time %t ERROR: Clock Frequency Change Failure. ODT must be off prior to Clock Frequency Change.", $time);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: Clock Frequency Change detected. DLL Reset is Required.", $time);
tm_freq_change <= $time;
ck_freq_change <= ck_cntr;
dll_locked = 0;
end
end
end
if (diff_ck) begin
// check setup of command signals
if ($time > TIS) begin
if ($time - tm_cke < TIS)
$display ("%m: at time %t ERROR: tIS violation on CKE by %t", $time, tm_cke + TIS - $time);
if (cke_in) begin
for (i=0; i<22; i=i+1) begin
if ($time - tm_cmd_addr[i] < TIS)
$display ("%m: at time %t ERROR: tIS violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIS - $time);
end
end
end
// update current state
if (dll_locked) begin
if (mr_chk == 0) begin
mr_chk = 1;
end else if (init_mode_reg[0] && (mr_chk == 1)) begin
// check CL value against the clock frequency
if (cas_latency*tck_avg < CL_TIME && check_strict_timing)
$display ("%m: at time %t ERROR: CAS Latency = %d is illegal @tCK(avg) = %f", $time, cas_latency, tck_avg);
// check WR value against the clock frequency
if (ceil(write_recovery*tck_avg) < TWR)
$display ("%m: at time %t ERROR: Write Recovery = %d is illegal @tCK(avg) = %f", $time, write_recovery, tck_avg);
// check the CWL value against the clock frequency
if (check_strict_timing) begin
case (cas_write_latency)
5 : if (tck_avg < 2500.0) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
6 : if ((tck_avg < 1875.0) || (tck_avg >= 2500.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
7 : if ((tck_avg < 1500.0) || (tck_avg >= 1875.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
8 : if ((tck_avg < 1250.0) || (tck_avg >= 1500.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
9 : if ((tck_avg < 15e3/14) || (tck_avg >= 1250.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
10: if ((tck_avg < 937.5) || (tck_avg >= 15e3/14)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
default : $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
endcase
// check the CL value against the clock frequency
if (!valid_cl(cas_latency, cas_write_latency))
$display ("%m: at time %t ERROR: CAS Latency = %d is not valid when CAS Write Latency = %d", $time, cas_latency, cas_write_latency);
end
mr_chk = 2;
end
end else if (!in_self_refresh) begin
mr_chk = 0;
if (ck_cntr - ck_dll_reset == TDLLK) begin
dll_locked = 1;
end
end
if (|auto_precharge_bank) begin
for (i=0; i<`BANKS; i=i+1) begin
// Write with Auto Precharge Calculation
// 1. Meet minimum tRAS requirement
// 2. Write Latency PLUS BL/2 cycles PLUS WR after Write command
if (write_precharge_bank[i]) begin
if ($time - tm_bank_activate[i] >= TRAS_MIN) begin
if (ck_cntr - ck_bank_write[i] >= write_latency + burst_length/2 + write_recovery) begin
if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i);
write_precharge_bank[i] = 0;
active_bank[i] = 0;
auto_precharge_bank[i] = 0;
tm_bank_precharge[i] = $time;
tm_precharge = $time;
ck_precharge = ck_cntr;
end
end
end
// Read with Auto Precharge Calculation
// 1. Meet minimum tRAS requirement
// 2. Additive Latency plus 4 cycles after Read command
// 3. tRTP after the last 8-bit prefetch
if (read_precharge_bank[i]) begin
if (($time - tm_bank_activate[i] >= TRAS_MIN) && (ck_cntr - ck_bank_read[i] >= additive_latency + TRTP_TCK)) begin
read_precharge_bank[i] = 0;
// In case the internal precharge is pushed out by tRTP, tRP starts at the point where
// the internal precharge happens (not at the next rising clock edge after this event).
if ($time - tm_bank_read_end[i] < TRTP) begin
if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", tm_bank_read_end[i] + TRTP, i);
active_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0;
auto_precharge_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0;
tm_bank_precharge[i] <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP;
tm_precharge <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP;
ck_precharge = ck_cntr;
end else begin
if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i);
active_bank[i] = 0;
auto_precharge_bank[i] = 0;
tm_bank_precharge[i] = $time;
tm_precharge = $time;
ck_precharge = ck_cntr;
end
end
end
end
end
// respond to incoming command
if (cke_in ^ prev_cke) begin
tm_cke_cmd <= $time;
ck_cke_cmd <= ck_cntr;
end
cmd_task(cke_in, cmd_n_in, ba_in, addr_in);
if ((cmd_n_in == WRITE) || (cmd_n_in == READ)) begin
al_pipeline[2*additive_latency] = 1'b1;
end
if (al_pipeline[0]) begin
// check tRCD after additive latency
if ((rd_pipeline[2*cas_latency - 1]) && ($time - tm_bank_activate[ba_pipeline[2*cas_latency - 1]] < TRCD))
$display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[READ]);
if ((wr_pipeline[2*cas_write_latency + 1]) && ($time - tm_bank_activate[ba_pipeline[2*cas_write_latency + 1]] < TRCD))
$display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[WRITE]);
// check tWTR after additive latency
if (rd_pipeline[2*cas_latency - 1]) begin //{
if (truebl4) begin //{
i = ba_pipeline[2*cas_latency - 1];
if ($time - tm_group_write_end[i[1]] < TWTR)
$display ("%m: at time %t ERROR: tWTR violation during %s", $time, cmd_string[READ]);
if ($time - tm_write_end < TWTR_DG)
$display ("%m: at time %t ERROR: tWTR_DG violation during %s", $time, cmd_string[READ]);
end else begin
if ($time - tm_write_end < TWTR)
$display ("%m: at time %t ERROR: tWTR violation during %s", $time, cmd_string[READ]);
end
end
end
if (rd_pipeline) begin
if (rd_pipeline[2*cas_latency - 1]) begin
tm_bank_read_end[ba_pipeline[2*cas_latency - 1]] <= $time;
end
end
for (i=0; i<`BANKS; i=i+1) begin
if ((ck_cntr - ck_bank_write[i] > write_latency) && (ck_cntr - ck_bank_write[i] <= write_latency + burst_length/2)) begin
tm_bank_write_end[i] <= $time;
tm_group_write_end[i[1]] <= $time;
tm_write_end <= $time;
end
end
// clk pin is disabled during self refresh
if (!in_self_refresh && tm_ck_pos ) begin
tjit_cc_time = $time - tm_ck_pos - tck_i;
tck_i = $time - tm_ck_pos;
tck_avg = tck_avg - tck_sample[ck_cntr%TDLLK]/$itor(TDLLK);
tck_avg = tck_avg + tck_i/$itor(TDLLK);
tck_sample[ck_cntr%TDLLK] = tck_i;
tjit_per_rtime = tck_i - tck_avg;
if (dll_locked && check_strict_timing) begin
// check accumulated error
terr_nper_rtime = 0;
for (i=0; i<12; i=i+1) begin
terr_nper_rtime = terr_nper_rtime + tck_sample[i] - tck_avg;
terr_nper_rtime = abs_value(terr_nper_rtime);
case (i)
0 :;
1 : if (terr_nper_rtime - TERR_2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(2per) violation by %f ps.", $time, terr_nper_rtime - TERR_2PER);
2 : if (terr_nper_rtime - TERR_3PER >= 1.0) $display ("%m: at time %t ERROR: tERR(3per) violation by %f ps.", $time, terr_nper_rtime - TERR_3PER);
3 : if (terr_nper_rtime - TERR_4PER >= 1.0) $display ("%m: at time %t ERROR: tERR(4per) violation by %f ps.", $time, terr_nper_rtime - TERR_4PER);
4 : if (terr_nper_rtime - TERR_5PER >= 1.0) $display ("%m: at time %t ERROR: tERR(5per) violation by %f ps.", $time, terr_nper_rtime - TERR_5PER);
5 : if (terr_nper_rtime - TERR_6PER >= 1.0) $display ("%m: at time %t ERROR: tERR(6per) violation by %f ps.", $time, terr_nper_rtime - TERR_6PER);
6 : if (terr_nper_rtime - TERR_7PER >= 1.0) $display ("%m: at time %t ERROR: tERR(7per) violation by %f ps.", $time, terr_nper_rtime - TERR_7PER);
7 : if (terr_nper_rtime - TERR_8PER >= 1.0) $display ("%m: at time %t ERROR: tERR(8per) violation by %f ps.", $time, terr_nper_rtime - TERR_8PER);
8 : if (terr_nper_rtime - TERR_9PER >= 1.0) $display ("%m: at time %t ERROR: tERR(9per) violation by %f ps.", $time, terr_nper_rtime - TERR_9PER);
9 : if (terr_nper_rtime - TERR_10PER >= 1.0) $display ("%m: at time %t ERROR: tERR(10per) violation by %f ps.", $time, terr_nper_rtime - TERR_10PER);
10 : if (terr_nper_rtime - TERR_11PER >= 1.0) $display ("%m: at time %t ERROR: tERR(11per) violation by %f ps.", $time, terr_nper_rtime - TERR_11PER);
11 : if (terr_nper_rtime - TERR_12PER >= 1.0) $display ("%m: at time %t ERROR: tERR(12per) violation by %f ps.", $time, terr_nper_rtime - TERR_12PER);
endcase
end
// check tCK min/max/jitter
if (abs_value(tjit_per_rtime) - TJIT_PER >= 1.0)
$display ("%m: at time %t ERROR: tJIT(per) violation by %f ps.", $time, abs_value(tjit_per_rtime) - TJIT_PER);
if (abs_value(tjit_cc_time) - TJIT_CC >= 1.0)
$display ("%m: at time %t ERROR: tJIT(cc) violation by %f ps.", $time, abs_value(tjit_cc_time) - TJIT_CC);
if (TCK_MIN - tck_avg >= 1.0)
$display ("%m: at time %t ERROR: tCK(avg) minimum violation by %f ps.", $time, TCK_MIN - tck_avg);
if (tck_avg - TCK_MAX >= 1.0)
$display ("%m: at time %t ERROR: tCK(avg) maximum violation by %f ps.", $time, tck_avg - TCK_MAX);
// check tCL
if (tm_ck_neg - $time < TCL_ABS_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCL(abs) minimum violation on CLK by %t", $time, TCL_ABS_MIN*tck_avg - tm_ck_neg + $time);
if (tcl_avg < TCL_AVG_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCL(avg) minimum violation on CLK by %t", $time, TCL_AVG_MIN*tck_avg - tcl_avg);
if (tcl_avg > TCL_AVG_MAX*tck_avg)
$display ("%m: at time %t ERROR: tCL(avg) maximum violation on CLK by %t", $time, tcl_avg - TCL_AVG_MAX*tck_avg);
end
// calculate the tch avg jitter
tch_avg = tch_avg - tch_sample[ck_cntr%TDLLK]/$itor(TDLLK);
tch_avg = tch_avg + tch_i/$itor(TDLLK);
tch_sample[ck_cntr%TDLLK] = tch_i;
tjit_ch_rtime = tch_i - tch_avg;
duty_cycle = tch_avg/tck_avg;
// update timers/counters
tcl_i <= $time - tm_ck_neg;
end
prev_odt <= odt_in;
// update timers/counters
ck_cntr <= ck_cntr + 1;
tm_ck_pos = $time;
end else begin
// clk pin is disabled during self refresh
if (!in_self_refresh) begin
if (dll_locked && check_strict_timing) begin
if ($time - tm_ck_pos < TCH_ABS_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCH(abs) minimum violation on CLK by %t", $time, TCH_ABS_MIN*tck_avg - $time + tm_ck_pos);
if (tch_avg < TCH_AVG_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCH(avg) minimum violation on CLK by %t", $time, TCH_AVG_MIN*tck_avg - tch_avg);
if (tch_avg > TCH_AVG_MAX*tck_avg)
$display ("%m: at time %t ERROR: tCH(avg) maximum violation on CLK by %t", $time, tch_avg - TCH_AVG_MAX*tck_avg);
end
// calculate the tcl avg jitter
tcl_avg = tcl_avg - tcl_sample[ck_cntr%TDLLK]/$itor(TDLLK);
tcl_avg = tcl_avg + tcl_i/$itor(TDLLK);
tcl_sample[ck_cntr%TDLLK] = tcl_i;
// update timers/counters
tch_i <= $time - tm_ck_pos;
end
tm_ck_neg = $time;
end
// on die termination
if (odt_en || dyn_odt_en) begin
// odt pin is disabled during self refresh
if (!in_self_refresh && diff_ck) begin
if ($time - tm_odt < TIS)
$display ("%m: at time %t ERROR: tIS violation on ODT by %t", $time, tm_odt + TIS - $time);
if (prev_odt ^ odt_in) begin
if (!dll_locked)
$display ("%m: at time %t WARNING: tDLLK violation during ODT transition.", $time);
if (($time - tm_load_mode < TMOD) || (ck_cntr - ck_load_mode < TMOD_TCK))
$display ("%m: at time %t ERROR: tMOD violation during ODT transition", $time);
if (ck_cntr - ck_zqinit < TZQINIT)
$display ("%m: at time %t ERROR: TZQinit violation during ODT transition", $time);
if (ck_cntr - ck_zqoper < TZQOPER)
$display ("%m: at time %t ERROR: TZQoper violation during ODT transition", $time);
if (ck_cntr - ck_zqcs < TZQCS)
$display ("%m: at time %t ERROR: tZQcs violation during ODT transition", $time);
// if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK))
// $display ("%m: at time %t ERROR: tXPDLL violation during ODT transition", $time);
if (ck_cntr - ck_self_refresh < TXSDLL)
$display ("%m: at time %t ERROR: tXSDLL violation during ODT transition", $time);
if (in_self_refresh)
$display ("%m: at time %t ERROR: Illegal ODT transition during Self Refresh.", $time);
if (!odt_in && (ck_cntr - ck_odt < ODTH4))
$display ("%m: at time %t ERROR: ODTH4 violation during ODT transition", $time);
if (!odt_in && (ck_cntr - ck_odth8 < ODTH8))
$display ("%m: at time %t ERROR: ODTH8 violation during ODT transition", $time);
if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK))
$display ("%m: at time %t WARNING: tXPDLL during ODT transition. Synchronous or asynchronous change in termination resistance is possible.", $time);
// async ODT mode applies:
// 1.) during precharge power down with DLL off
// 2.) if tANPD has not been satisfied
// 3.) until tXPDLL has been satisfied
if ((in_power_down && low_power && (active_bank == 0)) || ($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) begin
odt_state = odt_in;
if (DEBUG && odt_en) $display ("%m: at time %t INFO: Async On Die Termination Rtt_NOM = %d Ohm", $time, {32{odt_state}} & get_rtt_nom(odt_rtt_nom));
if (odt_state) begin
odt_state_dly <= #(TAONPD) odt_state;
end else begin
odt_state_dly <= #(TAOFPD) odt_state;
end
// sync ODT mode applies:
// 1.) during normal operation
// 2.) during active power down
// 3.) during precharge power down with DLL on
end else begin
odt_pipeline[2*(write_latency - 2)] = 1'b1; // ODTLon, ODTLoff
end
ck_odt <= ck_cntr;
end
end
if (odt_pipeline[0]) begin
odt_state = ~odt_state;
if (DEBUG && odt_en) $display ("%m: at time %t INFO: Sync On Die Termination Rtt_NOM = %d Ohm", $time, {32{odt_state}} & get_rtt_nom(odt_rtt_nom));
if (odt_state) begin
odt_state_dly <= #(TAON) odt_state;
end else begin
odt_state_dly <= #(TAOF*tck_avg) odt_state;
end
end
if (rd_pipeline[RDQSEN_PRE]) begin
odt_cntr = 1 + RDQSEN_PRE + bl_pipeline[RDQSEN_PRE] + RDQSEN_PST - 1;
end
if (odt_cntr > 0) begin
if (odt_state) begin
$display ("%m: at time %t ERROR: On Die Termination must be OFF during Read data transfer.", $time);
end
odt_cntr = odt_cntr - 1;
end
if (dyn_odt_en && odt_state) begin
if (DEBUG && (dyn_odt_state ^ dyn_odt_pipeline[0]))
$display ("%m: at time %t INFO: Sync On Die Termination Rtt_WR = %d Ohm", $time, {32{dyn_odt_pipeline[0]}} & get_rtt_wr(odt_rtt_wr));
dyn_odt_state = dyn_odt_pipeline[0];
end
dyn_odt_state_dly <= #(TADC*tck_avg) dyn_odt_state;
end
if (cke_in && write_levelization) begin
for (i=0; i<DQS_BITS; i=i+1) begin
if ($time - tm_dqs_pos[i] < TWLH)
$display ("%m: at time %t WARNING: tWLH violation on DQS bit %d positive edge. Indeterminate CK capture is possible.", $time, i);
end
end
// shift pipelines
if (|wr_pipeline || |rd_pipeline || |al_pipeline) begin
al_pipeline = al_pipeline>>1;
wr_pipeline = wr_pipeline>>1;
rd_pipeline = rd_pipeline>>1;
for (i=0; i<`MAX_PIPE; i=i+1) begin
bl_pipeline[i] = bl_pipeline[i+1];
ba_pipeline[i] = ba_pipeline[i+1];
row_pipeline[i] = row_pipeline[i+1];
col_pipeline[i] = col_pipeline[i+1];
end
end
if (|odt_pipeline || |dyn_odt_pipeline) begin
odt_pipeline = odt_pipeline>>1;
dyn_odt_pipeline = dyn_odt_pipeline>>1;
end
end
end
// receiver(s)
task dqs_even_receiver;
input [3:0] i;
reg [63:0] bit_mask;
begin
bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS);
if (dqs_even[i]) begin
if (tdqs_en) begin // tdqs disables dm
dm_in_pos[i] = 1'b0;
end else begin
dm_in_pos[i] = dm_in[i];
end
dq_in_pos = (dq_in & bit_mask) | (dq_in_pos & ~bit_mask);
end
end
endtask
always @(posedge dqs_even[ 0]) dqs_even_receiver( 0);
always @(posedge dqs_even[ 1]) dqs_even_receiver( 1);
always @(posedge dqs_even[ 2]) dqs_even_receiver( 2);
always @(posedge dqs_even[ 3]) dqs_even_receiver( 3);
always @(posedge dqs_even[ 4]) dqs_even_receiver( 4);
always @(posedge dqs_even[ 5]) dqs_even_receiver( 5);
always @(posedge dqs_even[ 6]) dqs_even_receiver( 6);
always @(posedge dqs_even[ 7]) dqs_even_receiver( 7);
always @(posedge dqs_even[ 8]) dqs_even_receiver( 8);
always @(posedge dqs_even[ 9]) dqs_even_receiver( 9);
always @(posedge dqs_even[10]) dqs_even_receiver(10);
always @(posedge dqs_even[11]) dqs_even_receiver(11);
always @(posedge dqs_even[12]) dqs_even_receiver(12);
always @(posedge dqs_even[13]) dqs_even_receiver(13);
always @(posedge dqs_even[14]) dqs_even_receiver(14);
always @(posedge dqs_even[15]) dqs_even_receiver(15);
task dqs_odd_receiver;
input [3:0] i;
reg [63:0] bit_mask;
begin
bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS);
if (dqs_odd[i]) begin
if (tdqs_en) begin // tdqs disables dm
dm_in_neg[i] = 1'b0;
end else begin
dm_in_neg[i] = dm_in[i];
end
dq_in_neg = (dq_in & bit_mask) | (dq_in_neg & ~bit_mask);
end
end
endtask
always @(posedge dqs_odd[ 0]) dqs_odd_receiver( 0);
always @(posedge dqs_odd[ 1]) dqs_odd_receiver( 1);
always @(posedge dqs_odd[ 2]) dqs_odd_receiver( 2);
always @(posedge dqs_odd[ 3]) dqs_odd_receiver( 3);
always @(posedge dqs_odd[ 4]) dqs_odd_receiver( 4);
always @(posedge dqs_odd[ 5]) dqs_odd_receiver( 5);
always @(posedge dqs_odd[ 6]) dqs_odd_receiver( 6);
always @(posedge dqs_odd[ 7]) dqs_odd_receiver( 7);
always @(posedge dqs_odd[ 8]) dqs_odd_receiver( 8);
always @(posedge dqs_odd[ 9]) dqs_odd_receiver( 9);
always @(posedge dqs_odd[10]) dqs_odd_receiver(10);
always @(posedge dqs_odd[11]) dqs_odd_receiver(11);
always @(posedge dqs_odd[12]) dqs_odd_receiver(12);
always @(posedge dqs_odd[13]) dqs_odd_receiver(13);
always @(posedge dqs_odd[14]) dqs_odd_receiver(14);
always @(posedge dqs_odd[15]) dqs_odd_receiver(15);
// Processes to check hold and pulse width of control signals
always @(posedge rst_n_in) begin
if ($time > 100000) begin
if (tm_rst_n + 100000 > $time)
$display ("%m: at time %t ERROR: RST_N pulse width violation by %t", $time, tm_rst_n + 100000 - $time);
end
tm_rst_n = $time;
end
always @(cke_in) begin
if (rst_n_in) begin
if ($time > TIH) begin
if ($time - tm_ck_pos < TIH)
$display ("%m: at time %t ERROR: tIH violation on CKE by %t", $time, tm_ck_pos + TIH - $time);
end
if ($time - tm_cke < TIPW)
$display ("%m: at time %t ERROR: tIPW violation on CKE by %t", $time, tm_cke + TIPW - $time);
end
tm_cke = $time;
end
always @(odt_in) begin
if (rst_n_in && odt_en && !in_self_refresh) begin
if ($time - tm_ck_pos < TIH)
$display ("%m: at time %t ERROR: tIH violation on ODT by %t", $time, tm_ck_pos + TIH - $time);
if ($time - tm_odt < TIPW)
$display ("%m: at time %t ERROR: tIPW violation on ODT by %t", $time, tm_odt + TIPW - $time);
end
tm_odt = $time;
end
task cmd_addr_timing_check;
input i;
reg [4:0] i;
begin
if (rst_n_in && prev_cke) begin
if ($time - tm_ck_pos < TIH)
$display ("%m: at time %t ERROR: tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time);
if ($time - tm_cmd_addr[i] < TIPW)
$display ("%m: at time %t ERROR: tIPW violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIPW - $time);
end
tm_cmd_addr[i] = $time;
end
endtask
always @(cs_n_in ) cmd_addr_timing_check( 0);
always @(ras_n_in ) cmd_addr_timing_check( 1);
always @(cas_n_in ) cmd_addr_timing_check( 2);
always @(we_n_in ) cmd_addr_timing_check( 3);
always @(ba_in [ 0]) cmd_addr_timing_check( 4);
always @(ba_in [ 1]) cmd_addr_timing_check( 5);
always @(ba_in [ 2]) cmd_addr_timing_check( 6);
always @(addr_in[ 0]) cmd_addr_timing_check( 7);
always @(addr_in[ 1]) cmd_addr_timing_check( 8);
always @(addr_in[ 2]) cmd_addr_timing_check( 9);
always @(addr_in[ 3]) cmd_addr_timing_check(10);
always @(addr_in[ 4]) cmd_addr_timing_check(11);
always @(addr_in[ 5]) cmd_addr_timing_check(12);
always @(addr_in[ 6]) cmd_addr_timing_check(13);
always @(addr_in[ 7]) cmd_addr_timing_check(14);
always @(addr_in[ 8]) cmd_addr_timing_check(15);
always @(addr_in[ 9]) cmd_addr_timing_check(16);
always @(addr_in[10]) cmd_addr_timing_check(17);
always @(addr_in[11]) cmd_addr_timing_check(18);
always @(addr_in[12]) cmd_addr_timing_check(19);
always @(addr_in[13]) cmd_addr_timing_check(20);
always @(addr_in[14]) cmd_addr_timing_check(21);
always @(addr_in[15]) cmd_addr_timing_check(22);
// Processes to check setup and hold of data signals
task dm_timing_check;
input i;
reg [3:0] i;
begin
if (dqs_in_valid) begin
if ($time - tm_dqs[i] < TDH)
$display ("%m: at time %t ERROR: tDH violation on DM bit %d by %t", $time, i, tm_dqs[i] + TDH - $time);
if (check_dm_tdipw[i]) begin
if ($time - tm_dm[i] < TDIPW)
$display ("%m: at time %t ERROR: tDIPW violation on DM bit %d by %t", $time, i, tm_dm[i] + TDIPW - $time);
end
end
check_dm_tdipw[i] <= 1'b0;
tm_dm[i] = $time;
end
endtask
always @(dm_in[ 0]) dm_timing_check( 0);
always @(dm_in[ 1]) dm_timing_check( 1);
always @(dm_in[ 2]) dm_timing_check( 2);
always @(dm_in[ 3]) dm_timing_check( 3);
always @(dm_in[ 4]) dm_timing_check( 4);
always @(dm_in[ 5]) dm_timing_check( 5);
always @(dm_in[ 6]) dm_timing_check( 6);
always @(dm_in[ 7]) dm_timing_check( 7);
always @(dm_in[ 8]) dm_timing_check( 8);
always @(dm_in[ 9]) dm_timing_check( 9);
always @(dm_in[10]) dm_timing_check(10);
always @(dm_in[11]) dm_timing_check(11);
always @(dm_in[12]) dm_timing_check(12);
always @(dm_in[13]) dm_timing_check(13);
always @(dm_in[14]) dm_timing_check(14);
always @(dm_in[15]) dm_timing_check(15);
task dq_timing_check;
input i;
reg [5:0] i;
begin
if (dqs_in_valid) begin
if ($time - tm_dqs[i/`DQ_PER_DQS] < TDH)
$display ("%m: at time %t ERROR: tDH violation on DQ bit %d by %t", $time, i, tm_dqs[i/`DQ_PER_DQS] + TDH - $time);
if (check_dq_tdipw[i]) begin
if ($time - tm_dq[i] < TDIPW)
$display ("%m: at time %t ERROR: tDIPW violation on DQ bit %d by %t", $time, i, tm_dq[i] + TDIPW - $time);
end
end
check_dq_tdipw[i] <= 1'b0;
tm_dq[i] = $time;
end
endtask
always @(dq_in[ 0]) dq_timing_check( 0);
always @(dq_in[ 1]) dq_timing_check( 1);
always @(dq_in[ 2]) dq_timing_check( 2);
always @(dq_in[ 3]) dq_timing_check( 3);
always @(dq_in[ 4]) dq_timing_check( 4);
always @(dq_in[ 5]) dq_timing_check( 5);
always @(dq_in[ 6]) dq_timing_check( 6);
always @(dq_in[ 7]) dq_timing_check( 7);
always @(dq_in[ 8]) dq_timing_check( 8);
always @(dq_in[ 9]) dq_timing_check( 9);
always @(dq_in[10]) dq_timing_check(10);
always @(dq_in[11]) dq_timing_check(11);
always @(dq_in[12]) dq_timing_check(12);
always @(dq_in[13]) dq_timing_check(13);
always @(dq_in[14]) dq_timing_check(14);
always @(dq_in[15]) dq_timing_check(15);
always @(dq_in[16]) dq_timing_check(16);
always @(dq_in[17]) dq_timing_check(17);
always @(dq_in[18]) dq_timing_check(18);
always @(dq_in[19]) dq_timing_check(19);
always @(dq_in[20]) dq_timing_check(20);
always @(dq_in[21]) dq_timing_check(21);
always @(dq_in[22]) dq_timing_check(22);
always @(dq_in[23]) dq_timing_check(23);
always @(dq_in[24]) dq_timing_check(24);
always @(dq_in[25]) dq_timing_check(25);
always @(dq_in[26]) dq_timing_check(26);
always @(dq_in[27]) dq_timing_check(27);
always @(dq_in[28]) dq_timing_check(28);
always @(dq_in[29]) dq_timing_check(29);
always @(dq_in[30]) dq_timing_check(30);
always @(dq_in[31]) dq_timing_check(31);
always @(dq_in[32]) dq_timing_check(32);
always @(dq_in[33]) dq_timing_check(33);
always @(dq_in[34]) dq_timing_check(34);
always @(dq_in[35]) dq_timing_check(35);
always @(dq_in[36]) dq_timing_check(36);
always @(dq_in[37]) dq_timing_check(37);
always @(dq_in[38]) dq_timing_check(38);
always @(dq_in[39]) dq_timing_check(39);
always @(dq_in[40]) dq_timing_check(40);
always @(dq_in[41]) dq_timing_check(41);
always @(dq_in[42]) dq_timing_check(42);
always @(dq_in[43]) dq_timing_check(43);
always @(dq_in[44]) dq_timing_check(44);
always @(dq_in[45]) dq_timing_check(45);
always @(dq_in[46]) dq_timing_check(46);
always @(dq_in[47]) dq_timing_check(47);
always @(dq_in[48]) dq_timing_check(48);
always @(dq_in[49]) dq_timing_check(49);
always @(dq_in[50]) dq_timing_check(50);
always @(dq_in[51]) dq_timing_check(51);
always @(dq_in[52]) dq_timing_check(52);
always @(dq_in[53]) dq_timing_check(53);
always @(dq_in[54]) dq_timing_check(54);
always @(dq_in[55]) dq_timing_check(55);
always @(dq_in[56]) dq_timing_check(56);
always @(dq_in[57]) dq_timing_check(57);
always @(dq_in[58]) dq_timing_check(58);
always @(dq_in[59]) dq_timing_check(59);
always @(dq_in[60]) dq_timing_check(60);
always @(dq_in[61]) dq_timing_check(61);
always @(dq_in[62]) dq_timing_check(62);
always @(dq_in[63]) dq_timing_check(63);
task dqs_pos_timing_check;
input i;
reg [4:0] i;
reg [3:0] j;
begin
if (write_levelization && i<16) begin
if (ck_cntr - ck_load_mode < TWLMRD)
$display ("%m: at time %t ERROR: tWLMRD violation on DQS bit %d positive edge.", $time, i);
if (($time - tm_ck_pos < TWLS) || ($time - tm_ck_neg < TWLS))
$display ("%m: at time %t WARNING: tWLS violation on DQS bit %d positive edge. Indeterminate CK capture is possible.", $time, i);
if (DEBUG)
$display ("%m: at time %t Write Leveling @ DQS ck = %b", $time, diff_ck);
dq_out_en_dly[i*`DQ_PER_DQS] <= #(TWLO) 1'b1;
dq_out_dly[i*`DQ_PER_DQS] <= #(TWLO) diff_ck;
for (j=1; j<`DQ_PER_DQS; j=j+1) begin
dq_out_en_dly[i*`DQ_PER_DQS+j] <= #(TWLO + TWLOE) 1'b1;
dq_out_dly[i*`DQ_PER_DQS+j] <= #(TWLO + TWLOE) 1'b0;
end
end
if (dqs_in_valid && ((wdqs_pos_cntr[i] < wr_burst_length/2) || b2b_write)) begin
if (dqs_in[i] ^ prev_dqs_in[i]) begin
if (dll_locked) begin
if (check_write_preamble[i]) begin
if ($time - tm_dqs_pos[i] < $rtoi(TWPRE*tck_avg))
$display ("%m: at time %t ERROR: tWPRE violation on &s bit %d", $time, dqs_string[i/16], i%16);
end else if (check_write_postamble[i]) begin
if ($time - tm_dqs_neg[i] < $rtoi(TWPST*tck_avg))
$display ("%m: at time %t ERROR: tWPST violation on %s bit %d", $time, dqs_string[i/16], i%16);
end else begin
if ($time - tm_dqs_neg[i] < $rtoi(TDQSL*tck_avg))
$display ("%m: at time %t ERROR: tDQSL violation on %s bit %d", $time, dqs_string[i/16], i%16);
end
end
if ($time - tm_dm[i%16] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%16] + TDS - $time);
if (!dq_out_en) begin
for (j=0; j<`DQ_PER_DQS; j=j+1) begin
if ($time - tm_dq[(i%16)*`DQ_PER_DQS+j] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[(i%16)*`DQ_PER_DQS+j] + TDS - $time);
check_dq_tdipw[(i%16)*`DQ_PER_DQS+j] <= 1'b1;
end
end
if ((wdqs_pos_cntr[i] < wr_burst_length/2) && !b2b_write) begin
wdqs_pos_cntr[i] <= wdqs_pos_cntr[i] + 1;
end else begin
wdqs_pos_cntr[i] <= 1;
end
check_dm_tdipw[i%16] <= 1'b1;
check_write_preamble[i] <= 1'b0;
check_write_postamble[i] <= 1'b0;
check_write_dqs_low[i] <= 1'b0;
tm_dqs[i%16] <= $time;
end else begin
$display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/16], i%16);
end
end
tm_dqss_pos[i] <= $time;
tm_dqs_pos[i] = $time;
prev_dqs_in[i] <= dqs_in[i];
end
endtask
always @(posedge dqs_in[ 0]) dqs_pos_timing_check( 0);
always @(posedge dqs_in[ 1]) dqs_pos_timing_check( 1);
always @(posedge dqs_in[ 2]) dqs_pos_timing_check( 2);
always @(posedge dqs_in[ 3]) dqs_pos_timing_check( 3);
always @(posedge dqs_in[ 4]) dqs_pos_timing_check( 4);
always @(posedge dqs_in[ 5]) dqs_pos_timing_check( 5);
always @(posedge dqs_in[ 6]) dqs_pos_timing_check( 6);
always @(posedge dqs_in[ 7]) dqs_pos_timing_check( 7);
always @(posedge dqs_in[ 8]) dqs_pos_timing_check( 8);
always @(posedge dqs_in[ 9]) dqs_pos_timing_check( 9);
always @(posedge dqs_in[10]) dqs_pos_timing_check(10);
always @(posedge dqs_in[11]) dqs_pos_timing_check(11);
always @(posedge dqs_in[12]) dqs_pos_timing_check(12);
always @(posedge dqs_in[13]) dqs_pos_timing_check(13);
always @(posedge dqs_in[14]) dqs_pos_timing_check(14);
always @(posedge dqs_in[15]) dqs_pos_timing_check(15);
always @(negedge dqs_in[16]) dqs_pos_timing_check(16);
always @(negedge dqs_in[17]) dqs_pos_timing_check(17);
always @(negedge dqs_in[18]) dqs_pos_timing_check(18);
always @(negedge dqs_in[19]) dqs_pos_timing_check(19);
always @(negedge dqs_in[20]) dqs_pos_timing_check(20);
always @(negedge dqs_in[21]) dqs_pos_timing_check(21);
always @(negedge dqs_in[22]) dqs_pos_timing_check(22);
always @(negedge dqs_in[23]) dqs_pos_timing_check(23);
always @(negedge dqs_in[24]) dqs_pos_timing_check(24);
always @(negedge dqs_in[25]) dqs_pos_timing_check(25);
always @(negedge dqs_in[26]) dqs_pos_timing_check(26);
always @(negedge dqs_in[27]) dqs_pos_timing_check(27);
always @(negedge dqs_in[28]) dqs_pos_timing_check(28);
always @(negedge dqs_in[29]) dqs_pos_timing_check(29);
always @(negedge dqs_in[30]) dqs_pos_timing_check(30);
always @(negedge dqs_in[31]) dqs_pos_timing_check(31);
task dqs_neg_timing_check;
input i;
reg [4:0] i;
reg [3:0] j;
begin
if (write_levelization && i<16) begin
if (ck_cntr - ck_load_mode < TWLDQSEN)
$display ("%m: at time %t ERROR: tWLDQSEN violation on DQS bit %d.", $time, i);
if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg))
$display ("%m: at time %t ERROR: tDQSH violation on DQS bit %d by %t", $time, i, tm_dqs_pos[i] + TDQSH*tck_avg - $time);
end
if (dqs_in_valid && (wdqs_pos_cntr[i] > 0) && check_write_dqs_high[i]) begin
if (dqs_in[i] ^ prev_dqs_in[i]) begin
if (dll_locked) begin
if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg))
$display ("%m: at time %t ERROR: tDQSH violation on %s bit %d", $time, dqs_string[i/16], i%16);
if ($time - tm_ck_pos < $rtoi(TDSH*tck_avg))
$display ("%m: at time %t ERROR: tDSH violation on %s bit %d", $time, dqs_string[i/16], i%16);
end
if ($time - tm_dm[i%16] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%16] + TDS - $time);
if (!dq_out_en) begin
for (j=0; j<`DQ_PER_DQS; j=j+1) begin
if ($time - tm_dq[(i%16)*`DQ_PER_DQS+j] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[(i%16)*`DQ_PER_DQS+j] + TDS - $time);
check_dq_tdipw[(i%16)*`DQ_PER_DQS+j] <= 1'b1;
end
end
check_dm_tdipw[i%16] <= 1'b1;
tm_dqs[i%16] <= $time;
end else begin
$display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/16], i%16);
end
end
check_write_dqs_high[i] <= 1'b0;
tm_dqs_neg[i] = $time;
prev_dqs_in[i] <= dqs_in[i];
end
endtask
always @(negedge dqs_in[ 0]) dqs_neg_timing_check( 0);
always @(negedge dqs_in[ 1]) dqs_neg_timing_check( 1);
always @(negedge dqs_in[ 2]) dqs_neg_timing_check( 2);
always @(negedge dqs_in[ 3]) dqs_neg_timing_check( 3);
always @(negedge dqs_in[ 4]) dqs_neg_timing_check( 4);
always @(negedge dqs_in[ 5]) dqs_neg_timing_check( 5);
always @(negedge dqs_in[ 6]) dqs_neg_timing_check( 6);
always @(negedge dqs_in[ 7]) dqs_neg_timing_check( 7);
always @(negedge dqs_in[ 8]) dqs_neg_timing_check( 8);
always @(negedge dqs_in[ 9]) dqs_neg_timing_check( 9);
always @(negedge dqs_in[10]) dqs_neg_timing_check(10);
always @(negedge dqs_in[11]) dqs_neg_timing_check(11);
always @(negedge dqs_in[12]) dqs_neg_timing_check(12);
always @(negedge dqs_in[13]) dqs_neg_timing_check(13);
always @(negedge dqs_in[14]) dqs_neg_timing_check(14);
always @(negedge dqs_in[15]) dqs_neg_timing_check(15);
always @(posedge dqs_in[16]) dqs_neg_timing_check(16);
always @(posedge dqs_in[17]) dqs_neg_timing_check(17);
always @(posedge dqs_in[18]) dqs_neg_timing_check(18);
always @(posedge dqs_in[19]) dqs_neg_timing_check(19);
always @(posedge dqs_in[20]) dqs_neg_timing_check(20);
always @(posedge dqs_in[21]) dqs_neg_timing_check(21);
always @(posedge dqs_in[22]) dqs_neg_timing_check(22);
always @(posedge dqs_in[23]) dqs_neg_timing_check(23);
always @(posedge dqs_in[24]) dqs_neg_timing_check(24);
always @(posedge dqs_in[25]) dqs_neg_timing_check(25);
always @(posedge dqs_in[26]) dqs_neg_timing_check(26);
always @(posedge dqs_in[27]) dqs_neg_timing_check(27);
always @(posedge dqs_in[28]) dqs_neg_timing_check(28);
always @(posedge dqs_in[29]) dqs_neg_timing_check(29);
always @(posedge dqs_in[30]) dqs_neg_timing_check(30);
always @(posedge dqs_in[31]) dqs_neg_timing_check(31);
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: lpm_mult_4_hybr_ref.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
// ************************************************************
//Copyright (C) 2020 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module lpm_mult_4_hybr_ref (
clock,
dataa,
datab,
result);
input clock;
input [8:0] dataa;
input [7:0] datab;
output [8:0] result;
wire [8:0] sub_wire0;
wire [8:0] result = sub_wire0[8:0];
lpm_mult lpm_mult_component (
.clock (clock),
.dataa (dataa),
.datab (datab),
.result (sub_wire0),
.aclr (1'b0),
.clken (1'b1),
.sclr (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=9",
lpm_mult_component.lpm_pipeline = 1,
lpm_mult_component.lpm_representation = "UNSIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 9,
lpm_mult_component.lpm_widthb = 8,
lpm_mult_component.lpm_widthp = 9;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "0"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "0"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "9"
// Retrieval info: PRIVATE: WidthB NUMERIC "8"
// Retrieval info: PRIVATE: WidthP NUMERIC "9"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=9"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "9"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "9"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 9 0 INPUT NODEFVAL "dataa[8..0]"
// Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL "datab[7..0]"
// Retrieval info: USED_PORT: result 0 0 9 0 OUTPUT NODEFVAL "result[8..0]"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 9 0 dataa 0 0 9 0
// Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0
// Retrieval info: CONNECT: result 0 0 9 0 @result 0 0 9 0
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
// Computer_System_ARM_A9_HPS.v
// This file was auto-generated from altera_hps_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.1 196
`timescale 1 ps / 1 ps
module Computer_System_ARM_A9_HPS #(
parameter F2S_Width = 2,
parameter S2F_Width = 3
) (
output wire h2f_rst_n, // h2f_reset.reset_n
input wire f2h_axi_clk, // f2h_axi_clock.clk
input wire [7:0] f2h_AWID, // f2h_axi_slave.awid
input wire [31:0] f2h_AWADDR, // .awaddr
input wire [3:0] f2h_AWLEN, // .awlen
input wire [2:0] f2h_AWSIZE, // .awsize
input wire [1:0] f2h_AWBURST, // .awburst
input wire [1:0] f2h_AWLOCK, // .awlock
input wire [3:0] f2h_AWCACHE, // .awcache
input wire [2:0] f2h_AWPROT, // .awprot
input wire f2h_AWVALID, // .awvalid
output wire f2h_AWREADY, // .awready
input wire [4:0] f2h_AWUSER, // .awuser
input wire [7:0] f2h_WID, // .wid
input wire [63:0] f2h_WDATA, // .wdata
input wire [7:0] f2h_WSTRB, // .wstrb
input wire f2h_WLAST, // .wlast
input wire f2h_WVALID, // .wvalid
output wire f2h_WREADY, // .wready
output wire [7:0] f2h_BID, // .bid
output wire [1:0] f2h_BRESP, // .bresp
output wire f2h_BVALID, // .bvalid
input wire f2h_BREADY, // .bready
input wire [7:0] f2h_ARID, // .arid
input wire [31:0] f2h_ARADDR, // .araddr
input wire [3:0] f2h_ARLEN, // .arlen
input wire [2:0] f2h_ARSIZE, // .arsize
input wire [1:0] f2h_ARBURST, // .arburst
input wire [1:0] f2h_ARLOCK, // .arlock
input wire [3:0] f2h_ARCACHE, // .arcache
input wire [2:0] f2h_ARPROT, // .arprot
input wire f2h_ARVALID, // .arvalid
output wire f2h_ARREADY, // .arready
input wire [4:0] f2h_ARUSER, // .aruser
output wire [7:0] f2h_RID, // .rid
output wire [63:0] f2h_RDATA, // .rdata
output wire [1:0] f2h_RRESP, // .rresp
output wire f2h_RLAST, // .rlast
output wire f2h_RVALID, // .rvalid
input wire f2h_RREADY, // .rready
input wire h2f_lw_axi_clk, // h2f_lw_axi_clock.clk
output wire [11:0] h2f_lw_AWID, // h2f_lw_axi_master.awid
output wire [20:0] h2f_lw_AWADDR, // .awaddr
output wire [3:0] h2f_lw_AWLEN, // .awlen
output wire [2:0] h2f_lw_AWSIZE, // .awsize
output wire [1:0] h2f_lw_AWBURST, // .awburst
output wire [1:0] h2f_lw_AWLOCK, // .awlock
output wire [3:0] h2f_lw_AWCACHE, // .awcache
output wire [2:0] h2f_lw_AWPROT, // .awprot
output wire h2f_lw_AWVALID, // .awvalid
input wire h2f_lw_AWREADY, // .awready
output wire [11:0] h2f_lw_WID, // .wid
output wire [31:0] h2f_lw_WDATA, // .wdata
output wire [3:0] h2f_lw_WSTRB, // .wstrb
output wire h2f_lw_WLAST, // .wlast
output wire h2f_lw_WVALID, // .wvalid
input wire h2f_lw_WREADY, // .wready
input wire [11:0] h2f_lw_BID, // .bid
input wire [1:0] h2f_lw_BRESP, // .bresp
input wire h2f_lw_BVALID, // .bvalid
output wire h2f_lw_BREADY, // .bready
output wire [11:0] h2f_lw_ARID, // .arid
output wire [20:0] h2f_lw_ARADDR, // .araddr
output wire [3:0] h2f_lw_ARLEN, // .arlen
output wire [2:0] h2f_lw_ARSIZE, // .arsize
output wire [1:0] h2f_lw_ARBURST, // .arburst
output wire [1:0] h2f_lw_ARLOCK, // .arlock
output wire [3:0] h2f_lw_ARCACHE, // .arcache
output wire [2:0] h2f_lw_ARPROT, // .arprot
output wire h2f_lw_ARVALID, // .arvalid
input wire h2f_lw_ARREADY, // .arready
input wire [11:0] h2f_lw_RID, // .rid
input wire [31:0] h2f_lw_RDATA, // .rdata
input wire [1:0] h2f_lw_RRESP, // .rresp
input wire h2f_lw_RLAST, // .rlast
input wire h2f_lw_RVALID, // .rvalid
output wire h2f_lw_RREADY, // .rready
input wire h2f_axi_clk, // h2f_axi_clock.clk
output wire [11:0] h2f_AWID, // h2f_axi_master.awid
output wire [29:0] h2f_AWADDR, // .awaddr
output wire [3:0] h2f_AWLEN, // .awlen
output wire [2:0] h2f_AWSIZE, // .awsize
output wire [1:0] h2f_AWBURST, // .awburst
output wire [1:0] h2f_AWLOCK, // .awlock
output wire [3:0] h2f_AWCACHE, // .awcache
output wire [2:0] h2f_AWPROT, // .awprot
output wire h2f_AWVALID, // .awvalid
input wire h2f_AWREADY, // .awready
output wire [11:0] h2f_WID, // .wid
output wire [127:0] h2f_WDATA, // .wdata
output wire [15:0] h2f_WSTRB, // .wstrb
output wire h2f_WLAST, // .wlast
output wire h2f_WVALID, // .wvalid
input wire h2f_WREADY, // .wready
input wire [11:0] h2f_BID, // .bid
input wire [1:0] h2f_BRESP, // .bresp
input wire h2f_BVALID, // .bvalid
output wire h2f_BREADY, // .bready
output wire [11:0] h2f_ARID, // .arid
output wire [29:0] h2f_ARADDR, // .araddr
output wire [3:0] h2f_ARLEN, // .arlen
output wire [2:0] h2f_ARSIZE, // .arsize
output wire [1:0] h2f_ARBURST, // .arburst
output wire [1:0] h2f_ARLOCK, // .arlock
output wire [3:0] h2f_ARCACHE, // .arcache
output wire [2:0] h2f_ARPROT, // .arprot
output wire h2f_ARVALID, // .arvalid
input wire h2f_ARREADY, // .arready
input wire [11:0] h2f_RID, // .rid
input wire [127:0] h2f_RDATA, // .rdata
input wire [1:0] h2f_RRESP, // .rresp
input wire h2f_RLAST, // .rlast
input wire h2f_RVALID, // .rvalid
output wire h2f_RREADY, // .rready
input wire [31:0] f2h_irq_p0, // f2h_irq0.irq
input wire [31:0] f2h_irq_p1, // f2h_irq1.irq
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [3:0] mem_dm, // .mem_dm
input wire oct_rzqin, // .oct_rzqin
output wire hps_io_emac1_inst_TX_CLK, // hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire hps_io_qspi_inst_IO0, // .hps_io_qspi_inst_IO0
inout wire hps_io_qspi_inst_IO1, // .hps_io_qspi_inst_IO1
inout wire hps_io_qspi_inst_IO2, // .hps_io_qspi_inst_IO2
inout wire hps_io_qspi_inst_IO3, // .hps_io_qspi_inst_IO3
output wire hps_io_qspi_inst_SS0, // .hps_io_qspi_inst_SS0
output wire hps_io_qspi_inst_CLK, // .hps_io_qspi_inst_CLK
inout wire hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
inout wire hps_io_usb1_inst_D0, // .hps_io_usb1_inst_D0
inout wire hps_io_usb1_inst_D1, // .hps_io_usb1_inst_D1
inout wire hps_io_usb1_inst_D2, // .hps_io_usb1_inst_D2
inout wire hps_io_usb1_inst_D3, // .hps_io_usb1_inst_D3
inout wire hps_io_usb1_inst_D4, // .hps_io_usb1_inst_D4
inout wire hps_io_usb1_inst_D5, // .hps_io_usb1_inst_D5
inout wire hps_io_usb1_inst_D6, // .hps_io_usb1_inst_D6
inout wire hps_io_usb1_inst_D7, // .hps_io_usb1_inst_D7
input wire hps_io_usb1_inst_CLK, // .hps_io_usb1_inst_CLK
output wire hps_io_usb1_inst_STP, // .hps_io_usb1_inst_STP
input wire hps_io_usb1_inst_DIR, // .hps_io_usb1_inst_DIR
input wire hps_io_usb1_inst_NXT, // .hps_io_usb1_inst_NXT
output wire hps_io_spim1_inst_CLK, // .hps_io_spim1_inst_CLK
output wire hps_io_spim1_inst_MOSI, // .hps_io_spim1_inst_MOSI
input wire hps_io_spim1_inst_MISO, // .hps_io_spim1_inst_MISO
output wire hps_io_spim1_inst_SS0, // .hps_io_spim1_inst_SS0
input wire hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire hps_io_i2c0_inst_SDA, // .hps_io_i2c0_inst_SDA
inout wire hps_io_i2c0_inst_SCL, // .hps_io_i2c0_inst_SCL
inout wire hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
inout wire hps_io_gpio_inst_GPIO09, // .hps_io_gpio_inst_GPIO09
inout wire hps_io_gpio_inst_GPIO35, // .hps_io_gpio_inst_GPIO35
inout wire hps_io_gpio_inst_GPIO40, // .hps_io_gpio_inst_GPIO40
inout wire hps_io_gpio_inst_GPIO41, // .hps_io_gpio_inst_GPIO41
inout wire hps_io_gpio_inst_GPIO48, // .hps_io_gpio_inst_GPIO48
inout wire hps_io_gpio_inst_GPIO53, // .hps_io_gpio_inst_GPIO53
inout wire hps_io_gpio_inst_GPIO54, // .hps_io_gpio_inst_GPIO54
inout wire hps_io_gpio_inst_GPIO61 // .hps_io_gpio_inst_GPIO61
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (F2S_Width != 2)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
f2s_width_check ( .error(1'b1) );
end
if (S2F_Width != 3)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
s2f_width_check ( .error(1'b1) );
end
endgenerate
Computer_System_ARM_A9_HPS_fpga_interfaces fpga_interfaces (
.h2f_rst_n (h2f_rst_n), // h2f_reset.reset_n
.f2h_axi_clk (f2h_axi_clk), // f2h_axi_clock.clk
.f2h_AWID (f2h_AWID), // f2h_axi_slave.awid
.f2h_AWADDR (f2h_AWADDR), // .awaddr
.f2h_AWLEN (f2h_AWLEN), // .awlen
.f2h_AWSIZE (f2h_AWSIZE), // .awsize
.f2h_AWBURST (f2h_AWBURST), // .awburst
.f2h_AWLOCK (f2h_AWLOCK), // .awlock
.f2h_AWCACHE (f2h_AWCACHE), // .awcache
.f2h_AWPROT (f2h_AWPROT), // .awprot
.f2h_AWVALID (f2h_AWVALID), // .awvalid
.f2h_AWREADY (f2h_AWREADY), // .awready
.f2h_AWUSER (f2h_AWUSER), // .awuser
.f2h_WID (f2h_WID), // .wid
.f2h_WDATA (f2h_WDATA), // .wdata
.f2h_WSTRB (f2h_WSTRB), // .wstrb
.f2h_WLAST (f2h_WLAST), // .wlast
.f2h_WVALID (f2h_WVALID), // .wvalid
.f2h_WREADY (f2h_WREADY), // .wready
.f2h_BID (f2h_BID), // .bid
.f2h_BRESP (f2h_BRESP), // .bresp
.f2h_BVALID (f2h_BVALID), // .bvalid
.f2h_BREADY (f2h_BREADY), // .bready
.f2h_ARID (f2h_ARID), // .arid
.f2h_ARADDR (f2h_ARADDR), // .araddr
.f2h_ARLEN (f2h_ARLEN), // .arlen
.f2h_ARSIZE (f2h_ARSIZE), // .arsize
.f2h_ARBURST (f2h_ARBURST), // .arburst
.f2h_ARLOCK (f2h_ARLOCK), // .arlock
.f2h_ARCACHE (f2h_ARCACHE), // .arcache
.f2h_ARPROT (f2h_ARPROT), // .arprot
.f2h_ARVALID (f2h_ARVALID), // .arvalid
.f2h_ARREADY (f2h_ARREADY), // .arready
.f2h_ARUSER (f2h_ARUSER), // .aruser
.f2h_RID (f2h_RID), // .rid
.f2h_RDATA (f2h_RDATA), // .rdata
.f2h_RRESP (f2h_RRESP), // .rresp
.f2h_RLAST (f2h_RLAST), // .rlast
.f2h_RVALID (f2h_RVALID), // .rvalid
.f2h_RREADY (f2h_RREADY), // .rready
.h2f_lw_axi_clk (h2f_lw_axi_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (h2f_lw_AWID), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (h2f_lw_AWADDR), // .awaddr
.h2f_lw_AWLEN (h2f_lw_AWLEN), // .awlen
.h2f_lw_AWSIZE (h2f_lw_AWSIZE), // .awsize
.h2f_lw_AWBURST (h2f_lw_AWBURST), // .awburst
.h2f_lw_AWLOCK (h2f_lw_AWLOCK), // .awlock
.h2f_lw_AWCACHE (h2f_lw_AWCACHE), // .awcache
.h2f_lw_AWPROT (h2f_lw_AWPROT), // .awprot
.h2f_lw_AWVALID (h2f_lw_AWVALID), // .awvalid
.h2f_lw_AWREADY (h2f_lw_AWREADY), // .awready
.h2f_lw_WID (h2f_lw_WID), // .wid
.h2f_lw_WDATA (h2f_lw_WDATA), // .wdata
.h2f_lw_WSTRB (h2f_lw_WSTRB), // .wstrb
.h2f_lw_WLAST (h2f_lw_WLAST), // .wlast
.h2f_lw_WVALID (h2f_lw_WVALID), // .wvalid
.h2f_lw_WREADY (h2f_lw_WREADY), // .wready
.h2f_lw_BID (h2f_lw_BID), // .bid
.h2f_lw_BRESP (h2f_lw_BRESP), // .bresp
.h2f_lw_BVALID (h2f_lw_BVALID), // .bvalid
.h2f_lw_BREADY (h2f_lw_BREADY), // .bready
.h2f_lw_ARID (h2f_lw_ARID), // .arid
.h2f_lw_ARADDR (h2f_lw_ARADDR), // .araddr
.h2f_lw_ARLEN (h2f_lw_ARLEN), // .arlen
.h2f_lw_ARSIZE (h2f_lw_ARSIZE), // .arsize
.h2f_lw_ARBURST (h2f_lw_ARBURST), // .arburst
.h2f_lw_ARLOCK (h2f_lw_ARLOCK), // .arlock
.h2f_lw_ARCACHE (h2f_lw_ARCACHE), // .arcache
.h2f_lw_ARPROT (h2f_lw_ARPROT), // .arprot
.h2f_lw_ARVALID (h2f_lw_ARVALID), // .arvalid
.h2f_lw_ARREADY (h2f_lw_ARREADY), // .arready
.h2f_lw_RID (h2f_lw_RID), // .rid
.h2f_lw_RDATA (h2f_lw_RDATA), // .rdata
.h2f_lw_RRESP (h2f_lw_RRESP), // .rresp
.h2f_lw_RLAST (h2f_lw_RLAST), // .rlast
.h2f_lw_RVALID (h2f_lw_RVALID), // .rvalid
.h2f_lw_RREADY (h2f_lw_RREADY), // .rready
.h2f_axi_clk (h2f_axi_clk), // h2f_axi_clock.clk
.h2f_AWID (h2f_AWID), // h2f_axi_master.awid
.h2f_AWADDR (h2f_AWADDR), // .awaddr
.h2f_AWLEN (h2f_AWLEN), // .awlen
.h2f_AWSIZE (h2f_AWSIZE), // .awsize
.h2f_AWBURST (h2f_AWBURST), // .awburst
.h2f_AWLOCK (h2f_AWLOCK), // .awlock
.h2f_AWCACHE (h2f_AWCACHE), // .awcache
.h2f_AWPROT (h2f_AWPROT), // .awprot
.h2f_AWVALID (h2f_AWVALID), // .awvalid
.h2f_AWREADY (h2f_AWREADY), // .awready
.h2f_WID (h2f_WID), // .wid
.h2f_WDATA (h2f_WDATA), // .wdata
.h2f_WSTRB (h2f_WSTRB), // .wstrb
.h2f_WLAST (h2f_WLAST), // .wlast
.h2f_WVALID (h2f_WVALID), // .wvalid
.h2f_WREADY (h2f_WREADY), // .wready
.h2f_BID (h2f_BID), // .bid
.h2f_BRESP (h2f_BRESP), // .bresp
.h2f_BVALID (h2f_BVALID), // .bvalid
.h2f_BREADY (h2f_BREADY), // .bready
.h2f_ARID (h2f_ARID), // .arid
.h2f_ARADDR (h2f_ARADDR), // .araddr
.h2f_ARLEN (h2f_ARLEN), // .arlen
.h2f_ARSIZE (h2f_ARSIZE), // .arsize
.h2f_ARBURST (h2f_ARBURST), // .arburst
.h2f_ARLOCK (h2f_ARLOCK), // .arlock
.h2f_ARCACHE (h2f_ARCACHE), // .arcache
.h2f_ARPROT (h2f_ARPROT), // .arprot
.h2f_ARVALID (h2f_ARVALID), // .arvalid
.h2f_ARREADY (h2f_ARREADY), // .arready
.h2f_RID (h2f_RID), // .rid
.h2f_RDATA (h2f_RDATA), // .rdata
.h2f_RRESP (h2f_RRESP), // .rresp
.h2f_RLAST (h2f_RLAST), // .rlast
.h2f_RVALID (h2f_RVALID), // .rvalid
.h2f_RREADY (h2f_RREADY), // .rready
.f2h_irq_p0 (f2h_irq_p0), // f2h_irq0.irq
.f2h_irq_p1 (f2h_irq_p1) // f2h_irq1.irq
);
Computer_System_ARM_A9_HPS_hps_io hps_io (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_qspi_inst_IO0 (hps_io_qspi_inst_IO0), // .hps_io_qspi_inst_IO0
.hps_io_qspi_inst_IO1 (hps_io_qspi_inst_IO1), // .hps_io_qspi_inst_IO1
.hps_io_qspi_inst_IO2 (hps_io_qspi_inst_IO2), // .hps_io_qspi_inst_IO2
.hps_io_qspi_inst_IO3 (hps_io_qspi_inst_IO3), // .hps_io_qspi_inst_IO3
.hps_io_qspi_inst_SS0 (hps_io_qspi_inst_SS0), // .hps_io_qspi_inst_SS0
.hps_io_qspi_inst_CLK (hps_io_qspi_inst_CLK), // .hps_io_qspi_inst_CLK
.hps_io_sdio_inst_CMD (hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_usb1_inst_D0 (hps_io_usb1_inst_D0), // .hps_io_usb1_inst_D0
.hps_io_usb1_inst_D1 (hps_io_usb1_inst_D1), // .hps_io_usb1_inst_D1
.hps_io_usb1_inst_D2 (hps_io_usb1_inst_D2), // .hps_io_usb1_inst_D2
.hps_io_usb1_inst_D3 (hps_io_usb1_inst_D3), // .hps_io_usb1_inst_D3
.hps_io_usb1_inst_D4 (hps_io_usb1_inst_D4), // .hps_io_usb1_inst_D4
.hps_io_usb1_inst_D5 (hps_io_usb1_inst_D5), // .hps_io_usb1_inst_D5
.hps_io_usb1_inst_D6 (hps_io_usb1_inst_D6), // .hps_io_usb1_inst_D6
.hps_io_usb1_inst_D7 (hps_io_usb1_inst_D7), // .hps_io_usb1_inst_D7
.hps_io_usb1_inst_CLK (hps_io_usb1_inst_CLK), // .hps_io_usb1_inst_CLK
.hps_io_usb1_inst_STP (hps_io_usb1_inst_STP), // .hps_io_usb1_inst_STP
.hps_io_usb1_inst_DIR (hps_io_usb1_inst_DIR), // .hps_io_usb1_inst_DIR
.hps_io_usb1_inst_NXT (hps_io_usb1_inst_NXT), // .hps_io_usb1_inst_NXT
.hps_io_spim1_inst_CLK (hps_io_spim1_inst_CLK), // .hps_io_spim1_inst_CLK
.hps_io_spim1_inst_MOSI (hps_io_spim1_inst_MOSI), // .hps_io_spim1_inst_MOSI
.hps_io_spim1_inst_MISO (hps_io_spim1_inst_MISO), // .hps_io_spim1_inst_MISO
.hps_io_spim1_inst_SS0 (hps_io_spim1_inst_SS0), // .hps_io_spim1_inst_SS0
.hps_io_uart0_inst_RX (hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c0_inst_SDA (hps_io_i2c0_inst_SDA), // .hps_io_i2c0_inst_SDA
.hps_io_i2c0_inst_SCL (hps_io_i2c0_inst_SCL), // .hps_io_i2c0_inst_SCL
.hps_io_i2c1_inst_SDA (hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.hps_io_gpio_inst_GPIO09 (hps_io_gpio_inst_GPIO09), // .hps_io_gpio_inst_GPIO09
.hps_io_gpio_inst_GPIO35 (hps_io_gpio_inst_GPIO35), // .hps_io_gpio_inst_GPIO35
.hps_io_gpio_inst_GPIO40 (hps_io_gpio_inst_GPIO40), // .hps_io_gpio_inst_GPIO40
.hps_io_gpio_inst_GPIO41 (hps_io_gpio_inst_GPIO41), // .hps_io_gpio_inst_GPIO41
.hps_io_gpio_inst_GPIO48 (hps_io_gpio_inst_GPIO48), // .hps_io_gpio_inst_GPIO48
.hps_io_gpio_inst_GPIO53 (hps_io_gpio_inst_GPIO53), // .hps_io_gpio_inst_GPIO53
.hps_io_gpio_inst_GPIO54 (hps_io_gpio_inst_GPIO54), // .hps_io_gpio_inst_GPIO54
.hps_io_gpio_inst_GPIO61 (hps_io_gpio_inst_GPIO61) // .hps_io_gpio_inst_GPIO61
);
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_embedded_workgroup_issuer #(
parameter unsigned MAX_SIMULTANEOUS_WORKGROUPS = 2, // >0
parameter unsigned MAX_WORKGROUP_SIZE = 2147483648, // >0
parameter string WORKGROUP_EXIT_ORDER = "fifo", // fifo|noninterleaved|unknown
parameter unsigned WG_SIZE_BITS = $clog2({1'b0, MAX_WORKGROUP_SIZE} + 1),
parameter unsigned LLID_BITS = (MAX_WORKGROUP_SIZE > 1 ? $clog2(MAX_WORKGROUP_SIZE) : 1),
parameter unsigned WG_ID_BITS = (MAX_SIMULTANEOUS_WORKGROUPS > 1 ? $clog2(MAX_SIMULTANEOUS_WORKGROUPS) : 1)
)
(
input logic clock,
input logic resetn,
// Handshake for item entry into function.
input logic valid_in,
output logic stall_out,
// Handshake with entry basic block
output logic valid_entry,
input logic stall_entry,
// Observe threads exiting the function .
// This is asserted when items are ready to be retired from the workgroup.
input logic valid_exit,
// This is asserted when downstream is not ready to retire an item from
// the workgroup.
input logic stall_exit,
// Need workgroup_size to know when one workgroup ends
// and another begins.
input logic [WG_SIZE_BITS - 1:0] workgroup_size,
// Linearized local id. In range of [0, workgroup_size - 1].
output logic [LLID_BITS - 1:0] linear_local_id_out,
// Hardware work-group id. In range of [0, MAX_SIMULTANEOUS_WORKGROUPS - 1].
output logic [WG_ID_BITS - 1:0] hw_wg_id_out,
// The hardware work-group id of the work-group that is exiting.
input logic [WG_ID_BITS - 1:0] done_hw_wg_id_in,
// Pass though global_id, local_id and group_id.
input logic [31:0] global_id_in[2:0],
input logic [31:0] local_id_in[2:0],
input logic [31:0] group_id_in[2:0],
output logic [31:0] global_id_out[2:0],
output logic [31:0] local_id_out[2:0],
output logic [31:0] group_id_out[2:0]
);
generate
if( WORKGROUP_EXIT_ORDER == "fifo" )
begin
acl_embedded_workgroup_issuer_fifo #(
.MAX_SIMULTANEOUS_WORKGROUPS(MAX_SIMULTANEOUS_WORKGROUPS),
.MAX_WORKGROUP_SIZE(MAX_WORKGROUP_SIZE)
)
issuer(.*);
end
else if( WORKGROUP_EXIT_ORDER == "noninterleaved" || WORKGROUP_EXIT_ORDER == "unknown" )
begin
acl_embedded_workgroup_issuer_complex #(
.MAX_SIMULTANEOUS_WORKGROUPS(MAX_SIMULTANEOUS_WORKGROUPS),
.MAX_WORKGROUP_SIZE(MAX_WORKGROUP_SIZE)
)
issuer(.*);
end
else
begin
// synthesis translate off
initial
$fatal("%m: unsupported configuration (WORKGROUP_EXIT_ORDER=%s)", WORKGROUP_EXIT_ORDER);
// synthesis translate on
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A41OI_2_V
`define SKY130_FD_SC_LP__A41OI_2_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog wrapper for a41oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a41oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a41oi_2 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a41oi_2 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A41OI_2_V
|
`timescale 1 ns / 1 ps
module boolean_generator_v1_1_S_AXI #
(
// Users to add parameters here
parameter C_BOOLEAN_GENERATOR_NUM = 24,
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 8
)
(
// Users to add ports here
input [C_BOOLEAN_GENERATOR_NUM-1:0] boolean_data_i,
output [C_BOOLEAN_GENERATOR_NUM-1:0] boolean_tri_o,
output [C_BOOLEAN_GENERATOR_NUM-1:0] boolean_data_o,
// User ports ends
// Do not modify the ports beyond this line
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Write channel Protection type. This signal indicates the
// privilege and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire S_AXI_AWREADY,
// Write data (issued by master, acceped by Slave)
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether the
// transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire S_AXI_ARREADY,
// Read data (issued by slave)
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of the
// read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
);
// AXI4LITE signals
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam integer OPT_MEM_ADDR_BITS = 5;
//----------------------------------------------
//-- Signals for user logic register space example
//------------------------------------------------
//-- Number of Slave Registers 62
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg7;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg8;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg9;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg10;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg11;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg12;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg13;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg14;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg15;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg16;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg17;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg18;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg19;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg20;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg21;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg22;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg23;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg24;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg25;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg26;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg27;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg28;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg29;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg30;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg31;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg32;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg33;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg34;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg35;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg36;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg37;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg38;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg39;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg40; // LED0 if Arduino otherwise GPIO[20]
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg41; // LED0 if Arduino otherwise GPIO[20]
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg42; // LED1 if Arduino otherwise GPIO[21]
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg43; // LED1 if Arduino otherwise GPIO[21]
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg44; // LED2 if Arduino otherwise GPIO[22]
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg45; // LED2 if Arduino otherwise GPIO[22]
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg46; // LED3 if Arduino otherwise GPIO[23]
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg47; // LED3 if Arduino otherwise GPIO[23]
// following registers are used for Raspberry Pi interface
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg48; // GPIO[24] for Raspberry Pi
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg49; // GPIO[24] for Raspberry Pi
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg50; // GPIO[25] for Raspberry Pi
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg51; // GPIO[25] for Raspberry Pi
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg52; // LED0 if Raspberry Pi used
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg53; // LED0 if Raspberry Pi used
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg54; // LED1 if Raspberry Pi used
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg55; // LED1 if Raspberry Pi used
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg56; // LED2 if Raspberry Pi used
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg57; // LED2 if Raspberry Pi used
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg58; // LED3 if Raspberry Pi used
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg59; // LED3 if Raspberry Pi used
// following registers are used for program and direction
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg62; // direction/tristate control
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg63; // programming
wire slv_reg_rden;
wire slv_reg_wren;
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
integer byte_index;
// I/O Connections assignments
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
end
else
begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1'b1;
end
else
begin
axi_wready <= 1'b0;
end
end
end
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
slv_reg0 <= 0;
slv_reg1 <= 0;
slv_reg2 <= 0;
slv_reg3 <= 0;
slv_reg4 <= 0;
slv_reg5 <= 0;
slv_reg6 <= 0;
slv_reg7 <= 0;
slv_reg8 <= 0;
slv_reg9 <= 0;
slv_reg10 <= 0;
slv_reg11 <= 0;
slv_reg12 <= 0;
slv_reg13 <= 0;
slv_reg14 <= 0;
slv_reg15 <= 0;
slv_reg16 <= 0;
slv_reg17 <= 0;
slv_reg18 <= 0;
slv_reg19 <= 0;
slv_reg20 <= 0;
slv_reg21 <= 0;
slv_reg22 <= 0;
slv_reg23 <= 0;
slv_reg24 <= 0;
slv_reg25 <= 0;
slv_reg26 <= 0;
slv_reg27 <= 0;
slv_reg28 <= 0;
slv_reg29 <= 0;
slv_reg30 <= 0;
slv_reg31 <= 0;
slv_reg32 <= 0;
slv_reg33 <= 0;
slv_reg34 <= 0;
slv_reg35 <= 0;
slv_reg36 <= 0;
slv_reg37 <= 0;
slv_reg38 <= 0;
slv_reg39 <= 0;
slv_reg40 <= 0;
slv_reg41 <= 0;
slv_reg42 <= 0;
slv_reg43 <= 0;
slv_reg44 <= 0;
slv_reg45 <= 0;
slv_reg46 <= 0;
slv_reg47 <= 0;
slv_reg48 <= 0;
slv_reg49 <= 0;
slv_reg50 <= 0;
slv_reg51 <= 0;
slv_reg52 <= 0;
slv_reg53 <= 0;
slv_reg54 <= 0;
slv_reg55 <= 0;
slv_reg56 <= 0;
slv_reg57 <= 0;
slv_reg58 <= 0;
slv_reg59 <= 0;
slv_reg62 <= 0;
slv_reg63 <= 0;
end
else begin
if (slv_reg_wren)
begin
case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
6'h00:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 0
slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h01:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 1
slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h02:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 2
slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h03:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 3
slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h04:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 4
slv_reg4[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h05:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 5
slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h06:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 6
slv_reg6[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h07:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 7
slv_reg7[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h08:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 8
slv_reg8[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h09:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 9
slv_reg9[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h0A:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 10
slv_reg10[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h0B:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 11
slv_reg11[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h0C:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 12
slv_reg12[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h0D:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 13
slv_reg13[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h0E:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 14
slv_reg14[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h0F:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 15
slv_reg15[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h10:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 16
slv_reg16[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h11:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 17
slv_reg17[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h12:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 18
slv_reg18[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h13:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 19
slv_reg19[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h14:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 20
slv_reg20[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h15:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 21
slv_reg21[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h16:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 22
slv_reg22[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h17:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 23
slv_reg23[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h18:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 24
slv_reg24[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h19:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 25
slv_reg25[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h1A:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 26
slv_reg26[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h1B:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 27
slv_reg27[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h1C:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 28
slv_reg28[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h1D:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 29
slv_reg29[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h1E:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 30
slv_reg30[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h1F:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 31
slv_reg31[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h20:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 32
slv_reg32[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h21:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 33
slv_reg33[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h22:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 34
slv_reg34[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h23:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 35
slv_reg35[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h24:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 36
slv_reg36[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h25:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 37
slv_reg37[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h26:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 38
slv_reg38[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h27:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 39
slv_reg39[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h28:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 40
slv_reg40[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h29:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 41
slv_reg41[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h2A:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 42
slv_reg42[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h2B:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 43
slv_reg43[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h2C:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 44
slv_reg44[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h2D:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 45
slv_reg45[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h2E:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 46
slv_reg46[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h2F:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 47
slv_reg47[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h30:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 48
slv_reg48[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h31:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 49
slv_reg49[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h32:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 50
slv_reg50[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h33:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 51
slv_reg51[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h34:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 52
slv_reg52[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h35:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 53
slv_reg53[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h36:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 54
slv_reg54[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h37:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 55
slv_reg55[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h38:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 56
slv_reg56[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h39:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 57
slv_reg57[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h3A:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 58
slv_reg58[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h3B:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 59
slv_reg59[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h3E:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 62
slv_reg62[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
6'h3F:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 63
slv_reg63[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
default : begin
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
slv_reg8 <= slv_reg8;
slv_reg9 <= slv_reg9;
slv_reg10 <= slv_reg10;
slv_reg11 <= slv_reg11;
slv_reg12 <= slv_reg12;
slv_reg13 <= slv_reg13;
slv_reg14 <= slv_reg14;
slv_reg15 <= slv_reg15;
slv_reg16 <= slv_reg16;
slv_reg17 <= slv_reg17;
slv_reg18 <= slv_reg18;
slv_reg19 <= slv_reg19;
slv_reg20 <= slv_reg20;
slv_reg21 <= slv_reg21;
slv_reg22 <= slv_reg22;
slv_reg23 <= slv_reg23;
slv_reg24 <= slv_reg24;
slv_reg25 <= slv_reg25;
slv_reg26 <= slv_reg26;
slv_reg27 <= slv_reg27;
slv_reg28 <= slv_reg28;
slv_reg29 <= slv_reg29;
slv_reg30 <= slv_reg30;
slv_reg31 <= slv_reg31;
slv_reg32 <= slv_reg32;
slv_reg33 <= slv_reg33;
slv_reg34 <= slv_reg34;
slv_reg35 <= slv_reg35;
slv_reg36 <= slv_reg36;
slv_reg37 <= slv_reg37;
slv_reg38 <= slv_reg38;
slv_reg39 <= slv_reg39;
slv_reg40 <= slv_reg40;
slv_reg41 <= slv_reg41;
slv_reg42 <= slv_reg42;
slv_reg43 <= slv_reg43;
slv_reg44 <= slv_reg44;
slv_reg45 <= slv_reg45;
slv_reg46 <= slv_reg46;
slv_reg47 <= slv_reg47;
slv_reg48 <= slv_reg48;
slv_reg49 <= slv_reg49;
slv_reg50 <= slv_reg50;
slv_reg51 <= slv_reg51;
slv_reg52 <= slv_reg52;
slv_reg53 <= slv_reg53;
slv_reg54 <= slv_reg54;
slv_reg55 <= slv_reg55;
slv_reg56 <= slv_reg56;
slv_reg57 <= slv_reg57;
slv_reg58 <= slv_reg58;
slv_reg59 <= slv_reg59;
slv_reg62 <= slv_reg62;
slv_reg63 <= slv_reg63;
end
endcase
end
end
end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
// indicates a valid write response is available
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
end // work error responses in future
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
// indicates that the slave has acceped the valid read address
axi_arready <= 1'b1;
// Read address latching
axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1'b0;
end
end
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
// Valid read data is available at the read data bus
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; // 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
// Read data is accepted by the master
axi_rvalid <= 1'b0;
end
end
end
// Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
always @(*)
begin
// Address decoding for reading registers
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
6'h00 : reg_data_out <= slv_reg0;
6'h01 : reg_data_out <= slv_reg1;
6'h02 : reg_data_out <= slv_reg2;
6'h03 : reg_data_out <= slv_reg3;
6'h04 : reg_data_out <= slv_reg4;
6'h05 : reg_data_out <= slv_reg5;
6'h06 : reg_data_out <= slv_reg6;
6'h07 : reg_data_out <= slv_reg7;
6'h08 : reg_data_out <= slv_reg8;
6'h09 : reg_data_out <= slv_reg9;
6'h0A : reg_data_out <= slv_reg10;
6'h0B : reg_data_out <= slv_reg11;
6'h0C : reg_data_out <= slv_reg12;
6'h0D : reg_data_out <= slv_reg13;
6'h0E : reg_data_out <= slv_reg14;
6'h0F : reg_data_out <= slv_reg15;
6'h10 : reg_data_out <= slv_reg16;
6'h11 : reg_data_out <= slv_reg17;
6'h12 : reg_data_out <= slv_reg18;
6'h13 : reg_data_out <= slv_reg19;
6'h14 : reg_data_out <= slv_reg20;
6'h15 : reg_data_out <= slv_reg21;
6'h16 : reg_data_out <= slv_reg22;
6'h17 : reg_data_out <= slv_reg23;
6'h18 : reg_data_out <= slv_reg24;
6'h19 : reg_data_out <= slv_reg25;
6'h1A : reg_data_out <= slv_reg26;
6'h1B : reg_data_out <= slv_reg27;
6'h1C : reg_data_out <= slv_reg28;
6'h1D : reg_data_out <= slv_reg29;
6'h1E : reg_data_out <= slv_reg30;
6'h1F : reg_data_out <= slv_reg31;
6'h20 : reg_data_out <= slv_reg32;
6'h21 : reg_data_out <= slv_reg33;
6'h22 : reg_data_out <= slv_reg34;
6'h23 : reg_data_out <= slv_reg35;
6'h24 : reg_data_out <= slv_reg36;
6'h25 : reg_data_out <= slv_reg37;
6'h26 : reg_data_out <= slv_reg38;
6'h27 : reg_data_out <= slv_reg39;
6'h28 : reg_data_out <= slv_reg40;
6'h29 : reg_data_out <= slv_reg41;
6'h2A : reg_data_out <= slv_reg42;
6'h2B : reg_data_out <= slv_reg43;
6'h2C : reg_data_out <= slv_reg44;
6'h2D : reg_data_out <= slv_reg45;
6'h2E : reg_data_out <= slv_reg46;
6'h2F : reg_data_out <= slv_reg47;
6'h30 : reg_data_out <= slv_reg48;
6'h31 : reg_data_out <= slv_reg49;
6'h32 : reg_data_out <= slv_reg50;
6'h33 : reg_data_out <= slv_reg51;
6'h34 : reg_data_out <= slv_reg52;
6'h35 : reg_data_out <= slv_reg53;
6'h36 : reg_data_out <= slv_reg54;
6'h37 : reg_data_out <= slv_reg55;
6'h38 : reg_data_out <= slv_reg56;
6'h39 : reg_data_out <= slv_reg57;
6'h3A : reg_data_out <= slv_reg58;
6'h3B : reg_data_out <= slv_reg59;
6'h3E : reg_data_out <= slv_reg62;
6'h3F : reg_data_out <= slv_reg63;
default : reg_data_out <= 0;
endcase
end
// Output register or memory read data
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rdata <= 0;
end
else
begin
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready),
// output the read dada
if (slv_reg_rden)
begin
axi_rdata <= reg_data_out; // register read data
end
end
end
// Add user logic here
assign boolean_tri_o = slv_reg62[C_BOOLEAN_GENERATOR_NUM-1:0]; // if bit=0 then output is driven, otherwise it is input pin
boolean_gr # (
.C_BOOLEAN_GENERATOR_NUM(C_BOOLEAN_GENERATOR_NUM)
) gr_0(
.clk(S_AXI_ACLK),
.boolean_data_i(boolean_data_i),
.start(slv_reg63[31]&slv_reg63[0]),
.fn_init_value(slv_reg1),
.boolean_input_sel(slv_reg0[24:0]),
.boolean_data_o(boolean_data_o[0])
);
boolean_gr # (
.C_BOOLEAN_GENERATOR_NUM(C_BOOLEAN_GENERATOR_NUM)
) gr_1(
.clk(S_AXI_ACLK),
.boolean_data_i(boolean_data_i),
.start(slv_reg63[31]&slv_reg63[1]),
.fn_init_value(slv_reg3),
.boolean_input_sel(slv_reg2[24:0]),
.boolean_data_o(boolean_data_o[1])
);
boolean_gr # (
.C_BOOLEAN_GENERATOR_NUM(C_BOOLEAN_GENERATOR_NUM)
) gr_2(
.clk(S_AXI_ACLK),
.boolean_data_i(boolean_data_i),
.start(slv_reg63[31]&slv_reg63[2]),
.fn_init_value(slv_reg5),
.boolean_input_sel(slv_reg4[24:0]),
.boolean_data_o(boolean_data_o[2])
);
boolean_gr # (
.C_BOOLEAN_GENERATOR_NUM(C_BOOLEAN_GENERATOR_NUM)
) gr_3(
.clk(S_AXI_ACLK),
.boolean_data_i(boolean_data_i),
.start(slv_reg63[31]&slv_reg63[3]),
.fn_init_value(slv_reg7),
.boolean_input_sel(slv_reg6[24:0]),
.boolean_data_o(boolean_data_o[3])
);
boolean_gr # (
.C_BOOLEAN_GENERATOR_NUM(C_BOOLEAN_GENERATOR_NUM)
) gr_4(
.clk(S_AXI_ACLK),
.boolean_data_i(boolean_data_i),
.start(slv_reg63[31]&slv_reg63[4]),
.fn_init_value(slv_reg9),
.boolean_input_sel(slv_reg8[24:0]),
.boolean_data_o(boolean_data_o[4])
);
boolean_gr # (
.C_BOOLEAN_GENERATOR_NUM(C_BOOLEAN_GENERATOR_NUM)
) gr_5(
.clk(S_AXI_ACLK),
.boolean_data_i(boolean_data_i),
.start(slv_reg63[31]&slv_reg63[5]),
.fn_init_value(slv_reg11),
.boolean_input_sel(slv_reg10[24:0]),
.boolean_data_o(boolean_data_o[5])
);
boolean_gr # (
.C_BOOLEAN_GENERATOR_NUM(C_BOOLEAN_GENERATOR_NUM)
) gr_6(
.clk(S_AXI_ACLK),
.boolean_data_i(boolean_data_i),
.start(slv_reg63[31]&slv_reg63[6]),
.fn_init_value(slv_reg13),
.boolean_input_sel(slv_reg12[24:0]),
.boolean_data_o(boolean_data_o[6])
);
boolean_gr # (
.C_BOOLEAN_GENERATOR_NUM(C_BOOLEAN_GENERATOR_NUM)
) gr_7(
.clk(S_AXI_ACLK),
.boolean_data_i(boolean_data_i),
.start(slv_reg63[31]&slv_reg63[7]),
.fn_init_value(slv_reg15),
.boolean_input_sel(slv_reg14[24:0]),
.boolean_data_o(boolean_data_o[7])
);
boolean_gr # (
.C_BOOLEAN_GENERATOR_NUM(C_BOOLEAN_GENERATOR_NUM)
) gr_8(
.clk(S_AXI_ACLK),
.boolean_data_i(boolean_data_i),
.start(slv_reg63[31]&slv_reg63[8]),
.fn_init_value(slv_reg17),
.boolean_input_sel(slv_reg16[24:0]),
.boolean_data_o(boolean_data_o[8])
);
boolean_gr # (
.C_BOOLEAN_GENERATOR_NUM(C_BOOLEAN_GENERATOR_NUM)
) gr_9(
.clk(S_AXI_ACLK),
.boolean_data_i(boolean_data_i),
.start(slv_reg63[31]&slv_reg63[9]),
.fn_init_value(slv_reg19),
.boolean_input_sel(slv_reg18[24:0]),
.boolean_data_o(boolean_data_o[9])
);
boolean_gr # (
.C_BOOLEAN_GENERATOR_NUM(C_BOOLEAN_GENERATOR_NUM)
) gr_10(
.clk(S_AXI_ACLK),
.boolean_data_i(boolean_data_i),
.start(slv_reg63[31]&slv_reg63[10]),
.fn_init_value(slv_reg21),
.boolean_input_sel(slv_reg20[24:0]),
.boolean_data_o(boolean_data_o[10])
);
boolean_gr # (
.C_BOOLEAN_GENERATOR_NUM(C_BOOLEAN_GENERATOR_NUM)
) gr_11(
.clk(S_AXI_ACLK),
.boolean_data_i(boolean_data_i),
.start(slv_reg63[31]&slv_reg63[11]),
.fn_init_value(slv_reg23),
.boolean_input_sel(slv_reg22[24:0]),
.boolean_data_o(boolean_data_o[11])
);
boolean_gr # (
.C_BOOLEAN_GENERATOR_NUM(C_BOOLEAN_GENERATOR_NUM)
) gr_12(
.clk(S_AXI_ACLK),
.boolean_data_i(boolean_data_i),
.start(slv_reg63[31]&slv_reg63[12]),
.fn_init_value(slv_reg25),
.boolean_input_sel(slv_reg24[24:0]),
.boolean_data_o(boolean_data_o[12])
);
boolean_gr # (
.C_BOOLEAN_GENERATOR_NUM(C_BOOLEAN_GENERATOR_NUM)
) gr_13(
.clk(S_AXI_ACLK),
.boolean_data_i(boolean_data_i),
.start(slv_reg63[31]&slv_reg63[13]),
.fn_init_value(slv_reg27),
.boolean_input_sel(slv_reg26[24:0]),
.boolean_data_o(boolean_data_o[13])
);
boolean_gr # (
.C_BOOLEAN_GENERATOR_NUM(C_BOOLEAN_GENERATOR_NUM)
) gr_14(
.clk(S_AXI_ACLK),
.boolean_data_i(boolean_data_i),
.start(slv_reg63[31]&slv_reg63[14]),
.fn_init_value(slv_reg29),
.boolean_input_sel(slv_reg28[24:0]),
.boolean_data_o(boolean_data_o[14])
);
boolean_gr # (
.C_BOOLEAN_GENERATOR_NUM(C_BOOLEAN_GENERATOR_NUM)
) gr_15(
.clk(S_AXI_ACLK),
.boolean_data_i(boolean_data_i),
.start(slv_reg63[31]&slv_reg63[15]),
.fn_init_value(slv_reg31),
.boolean_input_sel(slv_reg30[24:0]),
.boolean_data_o(boolean_data_o[15])
);
boolean_gr # (
.C_BOOLEAN_GENERATOR_NUM(C_BOOLEAN_GENERATOR_NUM)
) gr_16(
.clk(S_AXI_ACLK),
.boolean_data_i(boolean_data_i),
.start(slv_reg63[31]&slv_reg63[16]),
.fn_init_value(slv_reg33),
.boolean_input_sel(slv_reg32[24:0]),
.boolean_data_o(boolean_data_o[16])
);
boolean_gr # (
.C_BOOLEAN_GENERATOR_NUM(C_BOOLEAN_GENERATOR_NUM)
) gr_17(
.clk(S_AXI_ACLK),
.boolean_data_i(boolean_data_i),
.start(slv_reg63[31]&slv_reg63[17]),
.fn_init_value(slv_reg35),
.boolean_input_sel(slv_reg34[24:0]),
.boolean_data_o(boolean_data_o[17])
);
boolean_gr # (
.C_BOOLEAN_GENERATOR_NUM(C_BOOLEAN_GENERATOR_NUM)
) gr_18(
.clk(S_AXI_ACLK),
.boolean_data_i(boolean_data_i),
.start(slv_reg63[31]&slv_reg63[18]),
.fn_init_value(slv_reg37),
.boolean_input_sel(slv_reg36[24:0]),
.boolean_data_o(boolean_data_o[18])
);
boolean_gr # (
.C_BOOLEAN_GENERATOR_NUM(C_BOOLEAN_GENERATOR_NUM)
) gr_19(
.clk(S_AXI_ACLK),
.boolean_data_i(boolean_data_i),
.start(slv_reg63[31]&slv_reg63[19]),
.fn_init_value(slv_reg39),
.boolean_input_sel(slv_reg38[24:0]),
.boolean_data_o(boolean_data_o[19])
);
boolean_gr # (
.C_BOOLEAN_GENERATOR_NUM(C_BOOLEAN_GENERATOR_NUM)
) gr_20(
.clk(S_AXI_ACLK),
.boolean_data_i(boolean_data_i),
.start(slv_reg63[31]&slv_reg63[20]),
.fn_init_value(slv_reg41),
.boolean_input_sel(slv_reg40[24:0]),
.boolean_data_o(boolean_data_o[20])
);
boolean_gr # (
.C_BOOLEAN_GENERATOR_NUM(C_BOOLEAN_GENERATOR_NUM)
) gr_21(
.clk(S_AXI_ACLK),
.boolean_data_i(boolean_data_i),
.start(slv_reg63[31]&slv_reg63[21]),
.fn_init_value(slv_reg43),
.boolean_input_sel(slv_reg42[24:0]),
.boolean_data_o(boolean_data_o[21])
);
boolean_gr # (
.C_BOOLEAN_GENERATOR_NUM(C_BOOLEAN_GENERATOR_NUM)
) gr_22(
.clk(S_AXI_ACLK),
.boolean_data_i(boolean_data_i),
.start(slv_reg63[31]&slv_reg63[22]),
.fn_init_value(slv_reg45),
.boolean_input_sel(slv_reg44[24:0]),
.boolean_data_o(boolean_data_o[22])
);
boolean_gr # (
.C_BOOLEAN_GENERATOR_NUM(C_BOOLEAN_GENERATOR_NUM)
) gr_23(
.clk(S_AXI_ACLK),
.boolean_data_i(boolean_data_i),
.start(slv_reg63[31]&slv_reg63[23]),
.fn_init_value(slv_reg47),
.boolean_input_sel(slv_reg46[24:0]),
.boolean_data_o(boolean_data_o[23])
);
generate
if (C_BOOLEAN_GENERATOR_NUM != 24)
begin
boolean_gr # (
.C_BOOLEAN_GENERATOR_NUM(C_BOOLEAN_GENERATOR_NUM)
) gr_24(
.clk(S_AXI_ACLK),
.boolean_data_i(boolean_data_i),
.start(slv_reg63[31]&slv_reg63[24]),
.fn_init_value(slv_reg49),
.boolean_input_sel(slv_reg48[24:0]),
.boolean_data_o(boolean_data_o[24])
);
boolean_gr # (
.C_BOOLEAN_GENERATOR_NUM(C_BOOLEAN_GENERATOR_NUM)
) gr_25(
.clk(S_AXI_ACLK),
.boolean_data_i(boolean_data_i),
.start(slv_reg63[31]&slv_reg63[25]),
.fn_init_value(slv_reg51),
.boolean_input_sel(slv_reg50[24:0]),
.boolean_data_o(boolean_data_o[25])
);
boolean_gr # (
.C_BOOLEAN_GENERATOR_NUM(C_BOOLEAN_GENERATOR_NUM)
) gr_26(
.clk(S_AXI_ACLK),
.boolean_data_i(boolean_data_i),
.start(slv_reg63[31]&slv_reg63[26]),
.fn_init_value(slv_reg53),
.boolean_input_sel(slv_reg52[24:0]),
.boolean_data_o(boolean_data_o[26])
);
boolean_gr # (
.C_BOOLEAN_GENERATOR_NUM(C_BOOLEAN_GENERATOR_NUM)
) gr_27(
.clk(S_AXI_ACLK),
.boolean_data_i(boolean_data_i),
.start(slv_reg63[31]&slv_reg63[27]),
.fn_init_value(slv_reg55),
.boolean_input_sel(slv_reg54[24:0]),
.boolean_data_o(boolean_data_o[27])
);
boolean_gr # (
.C_BOOLEAN_GENERATOR_NUM(C_BOOLEAN_GENERATOR_NUM)
) gr_28(
.clk(S_AXI_ACLK),
.boolean_data_i(boolean_data_i),
.start(slv_reg63[31]&slv_reg63[28]),
.fn_init_value(slv_reg57),
.boolean_input_sel(slv_reg56[24:0]),
.boolean_data_o(boolean_data_o[28])
);
boolean_gr # (
.C_BOOLEAN_GENERATOR_NUM(C_BOOLEAN_GENERATOR_NUM)
) gr_29(
.clk(S_AXI_ACLK),
.boolean_data_i(boolean_data_i),
.start(slv_reg63[31]&slv_reg63[29]),
.fn_init_value(slv_reg59),
.boolean_input_sel(slv_reg58[24:0]),
.boolean_data_o(boolean_data_o[29])
);
end
endgenerate
// User logic ends
endmodule
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_never (clock, reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_NEVER";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/ovl_never_logic.v"
`endif
`ifdef OVL_SVA
`include "./sva05/ovl_never_logic.sv"
`endif
`ifdef OVL_PSL
`include "./psl05/assert_never_psl_logic.v"
`else
assign fire = {fire_cover, fire_xcheck, fire_2state};
`endmodule // ovl_never
`endif
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
supply0 [1:0] low;
supply1 [1:0] high;
reg [7:0] isizedwire;
reg ionewire;
`ifdef never_just_for_verilog_mode
wire oonewire; // From sub of t_inst_v2k__sub.v
`endif
wire [7:0] osizedreg; // From sub of t_inst_v2k__sub.v
wire [1:0] tied;
wire [3:0] tied_also;
hello hsub (.tied_also);
// Double underscore tests bug631
t_inst_v2k__sub sub
(
// Outputs
.osizedreg (osizedreg[7:0]),
// verilator lint_off IMPLICIT
.oonewire (oonewire),
// verilator lint_on IMPLICIT
.tied (tied[1:0]),
// Inputs
.isizedwire (isizedwire[7:0]),
.ionewire (ionewire));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
ionewire <= 1'b1;
isizedwire <= 8'd8;
end
if (cyc==2) begin
if (low != 2'b00) $stop;
if (high != 2'b11) $stop;
if (oonewire !== 1'b1) $stop;
if (isizedwire !== 8'd8) $stop;
if (tied != 2'b10) $stop;
if (tied_also != 4'b1010) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module hello(tied_also);
initial $write ("Hello\n");
output reg [3:0] tied_also = 4'b1010;
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
///////////////////////////////////////////////////////////////////////////////////////////////////
//
// This module facilitates a transition between two clock domains. We assume that the input
// is provided in the clock domain in parallel (2 data sets) and is to be serialized into two
// subsequent transactions in the clock2x domain.
//
// Note that this operation consumes 3 clock2x cycles. Thus a mirror operation will have to do the
// same, or the data will become desynchronized.
//
///////////////////////////////////////////////////////////////////////////////////////////////////
module acl_vector_to_stream_converter(
clock, clock2x, resetn, start,
a1, a2, b1, b2, dataa, datab,
valid_in, valid_out, stall_in, stall_out);
parameter WIDTH = 32;
input clock, clock2x, resetn, valid_in, stall_in, start;
input [WIDTH-1:0] a1;
input [WIDTH-1:0] b1;
input [WIDTH-1:0] a2;
input [WIDTH-1:0] b2;
output [WIDTH-1:0] dataa;
output [WIDTH-1:0] datab;
output valid_out;
output stall_out;
acl_vector_to_stream_converter_single inst_a(
.clock(clock),
.clock2x(clock2x),
.start(start),
.resetn(resetn),
.valid_in(valid_in),
.stall_in(stall_in),
.a1(a1),
.a2(a2),
.dataa(dataa),
.valid_out(valid_out),
.stall_out(stall_out));
defparam inst_a.WIDTH=WIDTH;
acl_vector_to_stream_converter_single inst_b(
.clock(clock),
.clock2x(clock2x),
.start(start),
.resetn(resetn),
.valid_in(valid_in),
.stall_in(stall_in),
.a1(b1),
.a2(b2),
.dataa(datab),
.valid_out(),
.stall_out());
defparam inst_b.WIDTH=WIDTH;
endmodule
|
/*
# ZUMA Open FPGA Overlay
# Alex Brant
# Email: [email protected]
# 2012
# LUTRAM wrapper
*/
`include "define.v"
`include "def_generated.v"
module elut_custom #(
parameter used = 0,
parameter LUT_MASK={2**K{1'b0}}
) (
a,
d,
dpra,
clk,
we,
dpo,
qdpo_clk,
qdpo_rst,
qdpo);
input [5 : 0] a;
input [0 : 0] d;
input [5 : 0] dpra;
input clk;
input we;
input qdpo_clk;
input qdpo_rst;
output dpo;
output qdpo;
wire lut_output;
wire lut_registered_output;
//no plattform. just for a verificational build.
`ifdef ZUMA_VERIFICATION
generate
if( used == 0)
//nothing will be generated and connected
else
//we generate a lut and a latch
LUT_K #(
.K(ZUMA_LUT_SIZE),
.LUT_MASK(LUT_MASK)
) verification_lut (
.in(dpra),
.out(lut_output)
);
DFF #(
.INITIAL_VALUE(1'b0)
) verification_latch (
.D(lut_output),
.Q(lut_registered_output),
.clock(qdpo_clk)
);
endgenerate
`elsif PLATFORM_XILINX
//uses distributed dual-port RAM
//uses two luts, which can have two different read busses, sharing a common write logic.
elut_xilinx LUT (
//read adress [5 : 0] for the first output, also write adress
.a(a),
//data input [0 : 0]
.d(d),
//read adress [5 : 0] for the second output
.dpra(dpra),
//first input clk and write clock
.clk(clk),
//input write enable
.we(we),
//second input clock
.qdpo_clk(qdpo_clk),
// input qdpo_rst
.qdpo_rst(qdpo_rst),
//first unregistered output [0 : 0]
.dpo(lut_output),
//second registered output [0 : 0]
.qdpo(lut_registered_output)
);
`elsif PLATFORM_ALTERA
SDPR LUT(
.clock(clk),
.data(d),
.rdaddress(dpra),
.wraddress(a),
.wren(we),
.q(lut_output));
`endif
`ifdef XILINX_ISIM //X'd inputs will break the simulation
assign dpo = (lut_output === 1'bx) ? 0 : lut_output ;
assign qdpo = (lut_registered_output === 1'bx) ? 0 : lut_registered_output ;
`else
assign dpo = lut_output;
assign qdpo = lut_registered_output;
`endif
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_v2_3_phy_ocd_po_cntlr.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Manipulates phaser out stg2f and stg3 on behalf of
// scan and DQS centering.
//
// Maintains a shadow of the phaser out stg2f and stg3 tap settings.
// The stg3 shadow is 6 bits, just like the phaser out. stg2f is
// 8 bits. This allows the po_cntlr to track how far past the stg2f
// saturation points we have gone when stepping to the limits of stg3.
// This way we're can stay in sync when we step back from the saturation
// limits.
//
// Looks at the edge values and determines which case has been
// detected by the scan. Uses the results to drive the centering.
//
// Main state machine waits until it sees reset_scan go to zero. While
// waiting it is writing the initialzation values to the stg2 and stg3
// shadows. When reset_scan goes low, taps_set is pulsed. This
// tells the sampling block to begin sampling. When the sampling
// block has finished sampling this setting of the phaser out taps,
// is signals by setting samp_done. When the main state machine
// sees samp_done it sets the next value in the phaser out and
// waits for the phaser out to be ready before beginning the next
// sample.
//
// Turns out phy_init is sensitive to the length of the ocal_num_samples_done
// pulse. Something like a precharge and activate time. Added feature
// to resume_wait to wait at least 32 cycles between assertion and
// subsequent deassertion of ocal_num_samples_done.
//
// Also turns out phy_init needs help to get into consistent
// starting state for complex cal. This can be done by preseting
// ocal_num_samples_done to one. Then waiting for 32 fabric clocks,
// turn off _done and then assert _resume.
//
// Scanning algorithm.
//
// Phaser manipulation algoritm.
//
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_ddr_phy_ocd_po_cntlr #
(parameter DQS_CNT_WIDTH = 3,
parameter DQS_WIDTH = 8,
parameter nCK_PER_CLK = 4,
parameter TCQ = 100)
(/*AUTOARG*/
// Outputs
scan_done, ocal_num_samples_done_r, oclkdelay_center_calib_start,
oclkdelay_center_calib_done, oclk_center_write_resume, ocd2stg2_inc,
ocd2stg2_dec, ocd2stg3_inc, ocd2stg3_dec, stg3, simp_stg3_final,
cmplx_stg3_final, simp_stg3_final_sel, ninety_offsets,
scanning_right, ocd_ktap_left, ocd_ktap_right, ocd_edge_detect_rdy,
taps_set, use_noise_window, ocal_scan_win_not_found,
// Inputs
clk, rst, reset_scan, oclkdelay_init_val, lim2ocal_stg3_right_lim,
lim2ocal_stg3_left_lim, complex_oclkdelay_calib_start,
po_counter_read_val, oclkdelay_calib_cnt, mmcm_edge_detect_done,
mmcm_lbclk_edge_aligned, poc_backup, phy_rddata_en_3, zero2fuzz,
fuzz2zero, oneeighty2fuzz, fuzz2oneeighty, z2f, f2z, o2f, f2o,
scan_right, samp_done, wl_po_fine_cnt_sel, po_rdy
);
input clk;
input rst;
input reset_scan;
reg scan_done_r;
output scan_done;
assign scan_done = scan_done_r;
output [5:0] simp_stg3_final_sel;
reg cmplx_samples_done_ns, cmplx_samples_done_r;
always @(posedge clk) cmplx_samples_done_r <= #TCQ cmplx_samples_done_ns;
output ocal_num_samples_done_r;
assign ocal_num_samples_done_r = cmplx_samples_done_r;
// Write Level signals during OCLKDELAY calibration
input [5:0] oclkdelay_init_val;
input [5:0] lim2ocal_stg3_right_lim;
input [5:0] lim2ocal_stg3_left_lim;
input complex_oclkdelay_calib_start;
reg oclkdelay_center_calib_start_ns, oclkdelay_center_calib_start_r;
always @(posedge clk) oclkdelay_center_calib_start_r <= #TCQ oclkdelay_center_calib_start_ns;
output oclkdelay_center_calib_start;
assign oclkdelay_center_calib_start = oclkdelay_center_calib_start_r;
reg oclkdelay_center_calib_done_ns, oclkdelay_center_calib_done_r;
always @(posedge clk) oclkdelay_center_calib_done_r <= #TCQ oclkdelay_center_calib_done_ns;
output oclkdelay_center_calib_done;
assign oclkdelay_center_calib_done = oclkdelay_center_calib_done_r;
reg oclk_center_write_resume_ns, oclk_center_write_resume_r;
always @(posedge clk) oclk_center_write_resume_r <= #TCQ oclk_center_write_resume_ns;
output oclk_center_write_resume;
assign oclk_center_write_resume = oclk_center_write_resume_r;
reg ocd2stg2_inc_r, ocd2stg2_dec_r, ocd2stg3_inc_r, ocd2stg3_dec_r;
output ocd2stg2_inc, ocd2stg2_dec, ocd2stg3_inc, ocd2stg3_dec;
assign ocd2stg2_inc = ocd2stg2_inc_r;
assign ocd2stg2_dec = ocd2stg2_dec_r;
assign ocd2stg3_inc = ocd2stg3_inc_r;
assign ocd2stg3_dec = ocd2stg3_dec_r;
// Remember, two stage 2 steps for every stg 3 step. And we need a sign bit.
reg [8:0] stg2_ns, stg2_r;
always @(posedge clk) stg2_r <= #TCQ stg2_ns;
reg [5:0] stg3_ns, stg3_r;
always @(posedge clk) stg3_r <= #TCQ stg3_ns;
output [5:0] stg3;
assign stg3 = stg3_r;
input [5:0] wl_po_fine_cnt_sel;
input [8:0] po_counter_read_val;
reg [5:0] po_counter_read_val_r;
always @(posedge clk) po_counter_read_val_r <= #TCQ po_counter_read_val[5:0];
reg [DQS_WIDTH*6-1:0] simp_stg3_final_ns, simp_stg3_final_r, cmplx_stg3_final_ns, cmplx_stg3_final_r;
always @(posedge clk) simp_stg3_final_r <= #TCQ simp_stg3_final_ns;
always @(posedge clk) cmplx_stg3_final_r <= #TCQ cmplx_stg3_final_ns;
output [DQS_WIDTH*6-1:0] simp_stg3_final, cmplx_stg3_final;
assign simp_stg3_final = simp_stg3_final_r;
assign cmplx_stg3_final = cmplx_stg3_final_r;
input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;
wire [DQS_WIDTH*6-1:0] simp_stg3_final_shft = simp_stg3_final_r >> oclkdelay_calib_cnt * 6;
assign simp_stg3_final_sel = simp_stg3_final_shft[5:0];
wire [5:0] stg3_init = complex_oclkdelay_calib_start ? simp_stg3_final_sel : oclkdelay_init_val;
wire signed [8:0] stg2_steps = stg3_r > stg3_init
? -9'sd2 * $signed({3'b0, (stg3_r - stg3_init)})
: 9'sd2 * $signed({3'b0, (stg3_init - stg3_r)});
wire signed [8:0] stg2_target_ns = $signed({3'b0, wl_po_fine_cnt_sel}) + stg2_steps;
reg signed [8:0] stg2_target_r;
always @ (posedge clk) stg2_target_r <= #TCQ stg2_target_ns;
reg [5:0] stg2_final_ns, stg2_final_r;
always @(posedge clk) stg2_final_r <= #TCQ stg2_final_ns;
always @(*) stg2_final_ns = stg2_target_r[8] == 1'b1
? 6'd0
: stg2_target_r > 9'd63
? 6'd63
: stg2_target_r[5:0];
wire final_stg2_inc = stg2_final_r > po_counter_read_val_r;
wire final_stg2_dec = stg2_final_r < po_counter_read_val_r;
wire left_lim = stg3_r == lim2ocal_stg3_left_lim;
wire right_lim = stg3_r == lim2ocal_stg3_right_lim;
reg [1:0] ninety_offsets_ns, ninety_offsets_r;
always @(posedge clk) ninety_offsets_r <= #TCQ ninety_offsets_ns;
output [1:0] ninety_offsets;
assign ninety_offsets = ninety_offsets_r;
reg scanning_right_ns, scanning_right_r;
always @(posedge clk) scanning_right_r <= #TCQ scanning_right_ns;
output scanning_right;
assign scanning_right = scanning_right_r;
reg ocd_ktap_left_ns, ocd_ktap_left_r, ocd_ktap_right_ns, ocd_ktap_right_r;
always @(posedge clk) ocd_ktap_left_r <= #TCQ ocd_ktap_left_ns;
always @(posedge clk) ocd_ktap_right_r <= #TCQ ocd_ktap_right_ns;
output ocd_ktap_left, ocd_ktap_right;
assign ocd_ktap_left = ocd_ktap_left_r;
assign ocd_ktap_right = ocd_ktap_right_r;
reg ocd_edge_detect_rdy_ns, ocd_edge_detect_rdy_r;
always @(posedge clk) ocd_edge_detect_rdy_r <= #TCQ ocd_edge_detect_rdy_ns;
output ocd_edge_detect_rdy;
assign ocd_edge_detect_rdy = ocd_edge_detect_rdy_r;
input mmcm_edge_detect_done;
input mmcm_lbclk_edge_aligned;
input poc_backup;
reg poc_backup_ns, poc_backup_r;
always @(posedge clk) poc_backup_r <= #TCQ poc_backup_ns;
reg taps_set_r;
output taps_set;
assign taps_set = taps_set_r;
input phy_rddata_en_3;
input [5:0] zero2fuzz, fuzz2zero, oneeighty2fuzz, fuzz2oneeighty;
input z2f, f2z, o2f, f2o;
wire zero = f2z && z2f;
wire noise = z2f && f2o;
wire oneeighty = f2o && o2f;
reg win_not_found;
reg [1:0] ninety_offsets_final;
reg [5:0] left, right, current_edge;
always @(*) begin
left = lim2ocal_stg3_left_lim;
right = lim2ocal_stg3_right_lim;
ninety_offsets_final = 2'd0;
win_not_found = 1'b0;
if (zero) begin
left = fuzz2zero;
right = zero2fuzz;
end
else if (noise) begin
left = zero2fuzz;
right = fuzz2oneeighty;
ninety_offsets_final = 2'd1;
end
else if (oneeighty) begin
left = fuzz2oneeighty;
right = oneeighty2fuzz;
ninety_offsets_final = 2'd2;
end
else if (z2f) begin
right = zero2fuzz;
end
else if (f2o) begin
left = fuzz2oneeighty;
ninety_offsets_final = 2'd2;
end
else if (f2z) begin
left = fuzz2zero;
end
else win_not_found = 1'b1;
current_edge = ocd_ktap_left_r ? left : right;
end // always @ begin
output use_noise_window;
assign use_noise_window = ninety_offsets == 2'd1;
reg ocal_scan_win_not_found_ns, ocal_scan_win_not_found_r;
always @(posedge clk) ocal_scan_win_not_found_r <= #TCQ ocal_scan_win_not_found_ns;
output ocal_scan_win_not_found;
assign ocal_scan_win_not_found = ocal_scan_win_not_found_r;
wire inc_po_ns = current_edge > stg3_r;
wire dec_po_ns = current_edge < stg3_r;
reg inc_po_r, dec_po_r;
always @(posedge clk) inc_po_r <= #TCQ inc_po_ns;
always @(posedge clk) dec_po_r <= #TCQ dec_po_ns;
input scan_right;
wire left_stop = left_lim || scan_right;
wire right_stop = right_lim || o2f;
reg [4:0] resume_wait_ns, resume_wait_r;
always @(posedge clk) resume_wait_r <= #TCQ resume_wait_ns;
wire resume_wait = |resume_wait_r;
reg po_done_ns, po_done_r;
always @(posedge clk) po_done_r <= #TCQ po_done_ns;
input samp_done;
input po_rdy;
reg up_ns, up_r;
always @(posedge clk) up_r <= #TCQ up_ns;
reg [1:0] two_ns, two_r;
always @(posedge clk) two_r <= #TCQ two_ns;
/* wire stg2_zero = ~|stg2_r;
wire [8:0] stg2_2_zero = stg2_r[8] ? 9'd0
: stg2_r > 9'd63
? 9'd63
: stg2_r; */
reg [3:0] sm_ns, sm_r;
always @(posedge clk) sm_r <= #TCQ sm_ns;
(* dont_touch = "true" *) reg phy_rddata_en_3_second_ns, phy_rddata_en_3_second_r;
always @(posedge clk) phy_rddata_en_3_second_r <= #TCQ phy_rddata_en_3_second_ns;
always @(*) phy_rddata_en_3_second_ns = ~reset_scan && (phy_rddata_en_3
? ~phy_rddata_en_3_second_r
: phy_rddata_en_3_second_r);
(* dont_touch = "true" *) wire use_samp_done = nCK_PER_CLK == 2 ? phy_rddata_en_3 && phy_rddata_en_3_second_r : phy_rddata_en_3;
reg po_center_wait;
reg po_slew;
reg po_finish_scan;
always @(*) begin
// Default next state assignments.
cmplx_samples_done_ns = cmplx_samples_done_r;
cmplx_stg3_final_ns = cmplx_stg3_final_r;
scanning_right_ns = scanning_right_r;
ninety_offsets_ns = ninety_offsets_r;
ocal_scan_win_not_found_ns = ocal_scan_win_not_found_r;
ocd_edge_detect_rdy_ns = ocd_edge_detect_rdy_r;
ocd_ktap_left_ns = ocd_ktap_left_r;
ocd_ktap_right_ns = ocd_ktap_right_r;
ocd2stg2_inc_r = 1'b0;
ocd2stg2_dec_r = 1'b0;
ocd2stg3_inc_r = 1'b0;
ocd2stg3_dec_r = 1'b0;
oclkdelay_center_calib_start_ns = oclkdelay_center_calib_start_r;
oclkdelay_center_calib_done_ns = 1'b0;
oclk_center_write_resume_ns = oclk_center_write_resume_r;
po_center_wait = 1'b0;
po_done_ns = po_done_r;
po_finish_scan = 1'b0;
po_slew = 1'b0;
poc_backup_ns = poc_backup_r;
scan_done_r = 1'b0;
simp_stg3_final_ns = simp_stg3_final_r;
sm_ns = sm_r;
taps_set_r = 1'b0;
up_ns = up_r;
stg2_ns = stg2_r;
stg3_ns = stg3_r;
two_ns = two_r;
resume_wait_ns = resume_wait_r;
if (rst == 1'b1) begin
// RESET next states
cmplx_samples_done_ns = 1'b0;
ocal_scan_win_not_found_ns = 1'b0;
ocd_ktap_left_ns = 1'b0;
ocd_ktap_right_ns = 1'b0;
ocd_edge_detect_rdy_ns = 1'b0;
oclk_center_write_resume_ns = 1'b0;
oclkdelay_center_calib_start_ns = 1'b0;
po_done_ns = 1'b1;
resume_wait_ns = 5'd0;
sm_ns = /*AK("READY")*/4'd0;
end else
// State based actions and next states.
case (sm_r)
/*AL("READY")*/4'd0:begin
poc_backup_ns = 1'b0;
stg2_ns = {3'b0, wl_po_fine_cnt_sel};
stg3_ns = stg3_init;
scanning_right_ns = 1'b0;
if (complex_oclkdelay_calib_start) cmplx_samples_done_ns = 1'b1;
if (!reset_scan && ~resume_wait) begin
cmplx_samples_done_ns = 1'b0;
ocal_scan_win_not_found_ns = 1'b0;
taps_set_r = 1'b1;
sm_ns = /*AK("SAMPLING")*/4'd1;
end
end
/*AL("SAMPLING")*/4'd1:begin
if (samp_done && use_samp_done) begin
if (complex_oclkdelay_calib_start) cmplx_samples_done_ns = 1'b1;
scanning_right_ns = scanning_right_r || left_stop;
if (right_stop && scanning_right_r) begin
oclkdelay_center_calib_start_ns = 1'b1;
ocd_ktap_left_ns = 1'b1;
ocal_scan_win_not_found_ns = win_not_found;
sm_ns = /*AK("SLEW_PO")*/4'd3;
end else begin
if (scanning_right_ns) ocd2stg3_inc_r = 1'b1;
else ocd2stg3_dec_r = 1'b1;
sm_ns = /*AK("PO_WAIT")*/4'd2;
end
end
end
/*AL("PO_WAIT")*/4'd2:begin
if (po_done_r && ~resume_wait) begin
taps_set_r = 1'b1;
sm_ns = /*AK("SAMPLING")*/4'd1;
cmplx_samples_done_ns = 1'b0;
end
end
/*AL("SLEW_PO")*/4'd3:begin
po_slew = 1'b1;
ninety_offsets_ns = |ninety_offsets_final ? 2'b01 : 2'b00;
if (~resume_wait) begin
if (po_done_r) begin
if (inc_po_r) ocd2stg3_inc_r = 1'b1;
else if (dec_po_r) ocd2stg3_dec_r = 1'b1;
else if (~resume_wait) begin
cmplx_samples_done_ns = 1'b0;
sm_ns = /*AK("ALIGN_EDGES")*/4'd4;
oclk_center_write_resume_ns = 1'b1;
end
end // if (po_done)
end
end // case: 3'd3
/*AL("ALIGN_EDGES")*/4'd4:
if (~resume_wait) begin
if (mmcm_edge_detect_done) begin
ocd_edge_detect_rdy_ns = 1'b0;
if (ocd_ktap_left_r) begin
ocd_ktap_left_ns = 1'b0;
ocd_ktap_right_ns = 1'b1;
oclk_center_write_resume_ns = 1'b0;
sm_ns = /*AK("SLEW_PO")*/4'd3;
end else if (ocd_ktap_right_r) begin
ocd_ktap_right_ns = 1'b0;
sm_ns = /*AK("WAIT_ONE")*/4'd5;
end else if (~mmcm_lbclk_edge_aligned) begin
sm_ns = /*AK("DQS_STOP_WAIT")*/4'd6;
oclk_center_write_resume_ns = 1'b0;
end else begin
if (ninety_offsets_r != ninety_offsets_final && ocd_edge_detect_rdy_r) begin
ninety_offsets_ns = ninety_offsets_r + 2'b01;
sm_ns = /*AK("WAIT_ONE")*/4'd5;
end else begin
oclk_center_write_resume_ns = 1'b0;
poc_backup_ns = poc_backup;
// stg2_ns = stg2_2_zero;
sm_ns = /*AK("FINISH_SCAN")*/4'd8;
end
end // else: !if(~mmcm_lbclk_edge_aligned)
end else ocd_edge_detect_rdy_ns = 1'b1;
end // if (~resume_wait)
/*AL("WAIT_ONE")*/4'd5:
sm_ns = /*AK("ALIGN_EDGES")*/4'd4;
/*AL("DQS_STOP_WAIT")*/4'd6:
if (~resume_wait) begin
ocd2stg3_dec_r = 1'b1;
sm_ns = /*AK("CENTER_PO_WAIT")*/4'd7;
end
/*AL("CENTER_PO_WAIT")*/4'd7: begin
po_center_wait = 1'b1; // Kludge to get around limitation of the AUTOs symbols.
if (po_done_r) begin
sm_ns = /*AK("ALIGN_EDGES")*/4'd4;
oclk_center_write_resume_ns = 1'b1;
end
end
/*AL("FINISH_SCAN")*/4'd8: begin
po_finish_scan = 1'b1;
if (resume_wait_r == 5'd1) begin
if (~poc_backup_r) begin
oclkdelay_center_calib_done_ns = 1'b1;
oclkdelay_center_calib_start_ns = 1'b0;
end
end
if (~resume_wait) begin
if (po_rdy)
if (poc_backup_r) begin
ocd2stg3_inc_r = 1'b1;
poc_backup_ns = 1'b0;
end
else if (~final_stg2_inc && ~final_stg2_dec) begin
if (complex_oclkdelay_calib_start) cmplx_stg3_final_ns[oclkdelay_calib_cnt*6+:6] = stg3_r;
else simp_stg3_final_ns[oclkdelay_calib_cnt*6+:6] = stg3_r;
sm_ns = /*AK("READY")*/4'd0;
scan_done_r = 1'b1;
end else begin
ocd2stg2_inc_r = final_stg2_inc;
ocd2stg2_dec_r = final_stg2_dec;
end
end // if (~resume_wait)
end // case: 4'd8
endcase // case (sm_r)
if (ocd2stg3_inc_r) begin
stg3_ns = stg3_r + 6'h1;
up_ns = 1'b0;
end
if (ocd2stg3_dec_r) begin
stg3_ns = stg3_r - 6'h1;
up_ns = 1'b1;
end
if (ocd2stg3_inc_r || ocd2stg3_dec_r) begin
po_done_ns = 1'b0;
two_ns = 2'b00;
end
if (~po_done_r)
if (po_rdy)
if (two_r == 2'b10 || po_center_wait || po_slew || po_finish_scan) po_done_ns = 1'b1;
else begin
two_ns = two_r + 2'b1;
if (up_r) begin
stg2_ns = stg2_r + 9'b1;
if (stg2_r >= 9'd0 && stg2_r < 9'd63) ocd2stg2_inc_r = 1'b1;
end else begin
stg2_ns = stg2_r - 9'b1;
if (stg2_r > 9'd0 && stg2_r <= 9'd63) ocd2stg2_dec_r = 1'b1;
end
end // else: !if(two_r == 2'b10)
if (ocd_ktap_left_ns && ~ocd_ktap_left_r) resume_wait_ns = 5'b1;
else if (oclk_center_write_resume_ns ^ oclk_center_write_resume_r) resume_wait_ns = 5'd15;
else if (cmplx_samples_done_ns & ~cmplx_samples_done_r ||
complex_oclkdelay_calib_start & reset_scan ||
poc_backup_r & ocd2stg3_inc_r) resume_wait_ns = 5'd31;
else if (|resume_wait_r) resume_wait_ns = resume_wait_r - 5'd1;
end // always @ begin
endmodule // mig_7series_v2_3_ddr_phy_ocd_po_cntlr
// Local Variables:
// verilog-autolabel-prefix: "4'd"
// End:
|
// Copyright (C) 1991-2011 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// Quartus II 11.0 Build 157 04/27/2011
`timescale 1 ps / 1ps
module oper_add ( a, b, cin, cout, o );
parameter width_a = 32;
parameter width_b = 32;
parameter width_o = 32;
parameter sgate_representation = 1;
input [width_a-1:0] a;
input [width_b-1:0] b;
input cin;
output cout;
output [width_o-1:0] o;
initial
begin
// check if width_a > 0
if (width_a <= 0)
begin
$display("Error! width_a must be greater than 0.\n");
$display ("Time: %0t Instance: %m", $time);
end
// check if width_b > 0
if (width_b <= 0)
begin
$display("Error! width_b must be greater than 0.\n");
$display ("Time: %0t Instance: %m", $time);
end
// check if width_o > 0
if (width_o <= 0)
begin
$display("Error! width_o must be greater than 0.\n");
$display ("Time: %0t Instance: %m", $time);
end
if (width_a != width_b)
begin
$display("Error! width_a must be equal to width_b.\n");
$display ("Time: %0t Instance: %m", $time);
end
if (width_a != width_o)
begin
$display("Error! width_a must be equal to width_o.\n");
$display ("Time: %0t Instance: %m", $time);
end
// check for valid lpm_rep value
if (sgate_representation != 1 && sgate_representation != 0)
begin
$display("Error! sgate_representation value must be 1 (SIGNED) or 0 (UNSIGNED).");
$display ("Time: %0t Instance: %m", $time);
end
end
lpm_add_sub lpm_add_sub_component (
.dataa (a),
.datab (b),
.cin (cin),
.cout (cout),
.result (o),
.add_sub (),
.clock (),
.aclr (),
.clken (),
.overflow ()
);
defparam
lpm_add_sub_component.lpm_width = width_a,
lpm_add_sub_component.lpm_direction = "ADD",
lpm_add_sub_component.lpm_representation = (sgate_representation == 1) ? "SIGNED" : "UNSIGNED",
lpm_add_sub_component.lpm_type = "LPM_ADD_SUB",
lpm_add_sub_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO";
endmodule
////------------------------------------------------------------------------------------------
////------------------------------------------------------------------------------------------
`timescale 1 ps / 1ps
module oper_addsub ( a, b, addnsub, o );
parameter width_a = 32;
parameter width_b = 32;
parameter width_o = 32;
parameter sgate_representation = 0;
input [width_a-1:0] a;
input [width_b-1:0] b;
input addnsub;
output [width_o-1:0] o;
reg [width_a-1:0] not_a;
reg [width_b-1:0] not_b;
reg [width_o-1:0] tmp_result;
// reg signed [width_a+2-1:0] a_int, b_int; //(not_a)*(-1)-1
// reg signed [width_a+5-1:0] result_int, i; // a_int + (-b_int)
integer a_int, b_int; //(not_a)*(-1)-1
integer result_int, i; // a_int + (-b_int)
wire i_add_sub;
buf (i_add_sub, addnsub);
initial
begin
// check if width_a > 0
if (width_a <= 0)
$display("Error! width_a must be greater than 0.\n");
// check if width_b > 0
if (width_b <= 0)
$display("Error! width_b must be greater than 0.\n");
// check if width_o > 0
if (width_o <= 0)
$display("Error! width_o must be greater than 0.\n");
if (width_a != width_b)
$display("Error! width_a must be equal to width_b.\n");
if (width_a != width_o)
$display("Error! width_a must be equal to width_o.\n");
if (sgate_representation != 1 &&
sgate_representation != 0)
$display("Error! sgate_representation value must be 1 (SIGNED) or 0 (UNSIGNED).");
tmp_result = 'b0;
end
always @(a or b or i_add_sub)
begin
if (i_add_sub == 1)
begin
tmp_result = a + b;
end
else if (i_add_sub == 0)
begin
tmp_result = a - b;
end
if (sgate_representation == 1)
begin
not_a = ~a;
not_b = ~b;
a_int = (a[width_a-1]) ? (not_a)*(-1)-1 : a;
b_int = (b[width_b-1]) ? (not_b)*(-1)-1 : b;
// perform the addtion or subtraction operation
if (i_add_sub == 1)
begin
result_int = a_int + b_int;
tmp_result = result_int;
end
else if (i_add_sub == 0)
begin
result_int = a_int - b_int;
tmp_result = result_int;
end
tmp_result = result_int;
end
end
assign o = tmp_result;
endmodule //oper_addsub
////------------------------------------------------------------------------------------------
////------------------------------------------------------------------------------------------
`timescale 1 ps / 1ps
module mux21 ( dataa, datab, dataout, outputselect);
input dataa;
input datab;
output dataout;
input outputselect;
reg tmp_result;
integer i;
always @(dataa or datab or outputselect)
begin
tmp_result = 0;
if (outputselect)
begin
tmp_result = datab;
end
else
begin
tmp_result = dataa;
end
end
assign dataout = tmp_result;
endmodule //mux21
////------------------------------------------------------------------------------------------
////------------------------------------------------------------------------------------------
`timescale 1 ps / 1ps
module io_buf_tri (datain, dataout, oe);
input datain;
input oe;
output dataout;
reg tmp_tridata;
always @(datain or oe)
begin
if (oe == 0)
begin
tmp_tridata = 1'bz;
end
else
begin
tmp_tridata = datain;
end
end
assign dataout = tmp_tridata;
endmodule // io_buf_tri
////------------------------------------------------------------------------------------------
////------------------------------------------------------------------------------------------
`timescale 1 ps / 1ps
module io_buf_opdrn (datain, dataout);
input datain;
output dataout;
reg tmp_tridata;
always @(datain)
begin
if (datain == 0)
begin
tmp_tridata = 1'b0;
end
else
begin
tmp_tridata = 1'bz;
end
end
assign dataout = tmp_tridata;
endmodule // io_buf_tri
////------------------------------------------------------------------------------------------
////------------------------------------------------------------------------------------------
`timescale 1 ps / 1ps
module oper_mult ( a, b, o );
parameter width_a = 32;
parameter width_b = 32;
parameter width_o = 32;
parameter sgate_representation = 1;
input [width_a-1:0] a;
input [width_b-1:0] b;
output [width_o-1:0] o;
// local parameter
parameter width_result = (width_o >= width_a + width_b) ? width_o : width_a + width_b;
wire [width_result-1:0] result;
initial
begin
// check if width_a > 0
if (width_a <= 0)
begin
$display("Error! width_a must be greater than 0.\n");
$display ("Time: %0t Instance: %m", $time);
end
// check if width_b > 0
if (width_b <= 0)
begin
$display("Error! width_b must be greater than 0.\n");
$display ("Time: %0t Instance: %m", $time);
end
// check if width_o > 0
if (width_o <= 0)
begin
$display("Error! width_o must be greater than 0.\n");
$display ("Time: %0t Instance: %m", $time);
end
// check for valid lpm_rep value
if ((sgate_representation != 1) && (sgate_representation != 0))
begin
$display("Error! sgate_representation value must be 1 (signed) or 0 (unsigned).", $time);
$display ("Time: %0t Instance: %m", $time);
end
end
lpm_mult lpm_mult_component (
.dataa (a),
.datab (b),
.result (result),
.sum (),
.aclr (),
.clock (),
.clken ()
);
defparam
lpm_mult_component.lpm_widtha = width_a,
lpm_mult_component.lpm_widthb = width_b,
lpm_mult_component.lpm_widthp = width_result,
lpm_mult_component.lpm_widths = width_result,
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_representation = sgate_representation ? "SIGNED" : "UNSIGNED",
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=6";
assign o[width_o-1:0] = result[width_o-1:0];
endmodule // oper_mult
////------------------------------------------------------------------------------------------
////------------------------------------------------------------------------------------------
`timescale 1 ps / 1ps
module tri_bus ( datain, dataout );
parameter width_datain = 1;
parameter width_dataout = 1;
input [(width_datain)-1:0] datain;
output [width_dataout-1:0] dataout;
reg [width_dataout-1:0] tmp_result;
integer i;
initial
begin
tmp_result = 1'bz;
// check if width_a > 0
if (width_datain <= 0)
begin
$display("Error! width_datain must be greater than 0.\n");
$display ("Time: %0t Instance: %m", $time);
end
// check if width_b > 0
if (width_dataout != 1)
begin
$display("Error! width_dataout must be equal to 1.\n");
$display ("Time: %0t Instance: %m", $time);
end
// check if width_o > 0
end
always @(datain)
begin
for (i = 0; i < width_datain; i = i + 1)
if ((datain[i] == 1)||(datain[i] == 0))
begin
tmp_result[0]=datain[i];
end
end
assign dataout = tmp_result;
endmodule // tri_bus
////------------------------------------------------------------------------------------------
////------------------------------------------------------------------------------------------
`timescale 1 ps / 1ps
module oper_div ( a, b, o);
parameter width_a = 6;
parameter width_b = 6;
parameter width_o = 6;
parameter sgate_representation = 0;
input [width_a-1:0] a;
input [width_b-1:0] b;
output [width_o-1:0] o;
wire [width_a-1:0] tmp_result;
reg [width_o-1:0] tmp_result2;
wire [width_b-1:0] hold_rem;
integer i;
lpm_divide u1 (
.numer (a),
.denom (b),
.quotient (tmp_result),
.remain (hold_rem),
.clock (),
.aclr (),
.clken ()
);
defparam u1.lpm_widthn= width_a,
u1.lpm_widthd= width_b,
u1.lpm_nrepresentation= sgate_representation ? "SIGNED" : "UNSIGNED",
u1.lpm_drepresentation= sgate_representation ? "SIGNED" : "UNSIGNED",
u1.lpm_type = "LPM_DIVIDE",
u1.lpm_hint = sgate_representation ? "LPM_REMAINDERPOSITIVE=FALSE" : "LPM_REMAINDERPOSITIVE=TRUE";
initial
begin
// check if width_a > 0
if (width_a <= 0)
begin
$display("Error! width_a must be greater than 0.\n");
$display ("Time: %0t Instance: %m", $time);
end
// check if width_b > 0
if (width_b <= 0)
begin
$display("Error! width_b must be greater than 0.\n");
$display ("Time: %0t Instance: %m", $time);
end
// check if width_o > 0
if (width_o <= 0)
begin
$display("Error! width_o must greater than 0.\n");
$display ("Time: %0t Instance: %m", $time);
end
// check if width_o > 0
if ((sgate_representation != 1) && (sgate_representation != 0))
begin
$display("Error! sgate_representation value must be 1 (signed) or 0 (unsigned).", $time);
$display ("Time: %0t Instance: %m", $time);
end
end
always @(tmp_result)
begin
if (width_a > width_o)
begin
tmp_result2[width_o-1:0] = tmp_result[width_a-1:0];
end
else
begin
tmp_result2[width_a-1:0] = tmp_result[width_a-1:0];
end
if ((width_o - width_a) > 0)
begin
for (i = width_a; i < width_o; i = i + 1)
begin
tmp_result2[i] = sgate_representation ? tmp_result[width_a-1] : 1'b0;
end
end
end
assign o = tmp_result2;
endmodule // oper_div
////------------------------------------------------------------------------------------------
////------------------------------------------------------------------------------------------
`timescale 1 ps / 1ps
module oper_mod ( a, b, o);
parameter width_a = 6;
parameter width_b = 6;
parameter width_o = 6;
parameter sgate_representation = 0;
input [width_a-1:0] a;
input [width_b-1:0] b;
output [width_o-1:0] o;
wire [width_a-1:0] tmp_result;
reg [width_o-1:0] tmp_result2;
wire [width_b-1:0] hold_rem;
integer i;
lpm_divide u1 (
.numer (a),
.denom (b),
.quotient (tmp_result),
.remain (hold_rem),
.clock (),
.aclr (),
.clken ()
);
defparam u1.lpm_widthn= width_a,
u1.lpm_widthd= width_b,
u1.lpm_nrepresentation= sgate_representation ? "SIGNED" : "UNSIGNED",
u1.lpm_drepresentation= sgate_representation ? "SIGNED" : "UNSIGNED",
u1.lpm_type = "LPM_DIVIDE",
u1.lpm_hint = sgate_representation ? "LPM_REMAINDERPOSITIVE=FALSE" : "LPM_REMAINDERPOSITIVE=TRUE";
initial
begin
// check if width_a > 0
if (width_a <= 0)
begin
$display("Error! width_a must be greater than 0.\n");
$display ("Time: %0t Instance: %m", $time);
end
// check if width_b > 0
if (width_b <= 0)
begin
$display("Error! width_b must be greater than 0.\n");
$display ("Time: %0t Instance: %m", $time);
end
// check if width_o > 0
if (width_o <= 0)
begin
$display("Error! width_o must greater than 0.\n");
$display ("Time: %0t Instance: %m", $time);
end
// check if width_o > 0
if ((sgate_representation != 1) && (sgate_representation != 0))
begin
$display("Error! sgate_representation value must be 1 (signed) or 0 (unsigned).", $time);
$display ("Time: %0t Instance: %m", $time);
end
end
always @(hold_rem)
begin
if (width_b > width_o)
begin
tmp_result2[width_o-1:0] = hold_rem[width_o-1:0];
end
else
begin
tmp_result2[width_b-1:0] = hold_rem[width_b-1:0];
end
if ((width_o - width_b) > 0)
begin
for (i = width_b; i < width_o; i = i + 1)
begin
tmp_result2[i] = sgate_representation ? hold_rem[width_b-1] : 1'b0;
end
end
end
assign o = tmp_result2;
endmodule // oper_mod
////------------------------------------------------------------------------------------------
////------------------------------------------------------------------------------------------
`timescale 1 ps / 1ps
module oper_left_shift ( a, amount, cin, o);
parameter width_a = 6;
parameter width_amount = 6;
parameter width_o = 6;
parameter sgate_representation = 0;
input [width_a-1:0] a;
input [width_amount-1:0] amount;
input cin;
output [width_o-1:0] o;
integer i;
reg [width_a-1:0] ONES;
reg [width_a-1:0] tmp_buf;
reg [width_a-1:0] temp_result2;
initial
begin
// check if width_amount > 0
if (width_amount <= 0)
begin
$display("Error! width_amount must be greater than 0.\n");
$display ("Time: %0t Instance: %m", $time);
end
// check if width_a > 0
if (width_a <= 0)
begin
$display("Error! width_a must be greater than 0.\n");
$display ("Time: %0t Instance: %m", $time);
end
// check if width_a = width_o
if (width_a < width_o)
begin
$display("Error! width_a must be greater than or equal to width_o.\n");
$display ("Time: %0t Instance: %m", $time);
end
// check if width_o > 0
if (sgate_representation != 1 && sgate_representation != 0)
begin
$display("Error! sgate_representation value must be 1 (SIGNED) or 0 (UNSIGNED).");
$display ("Time: %0t Instance: %m", $time);
end
end
always @(a or amount or cin)
begin
tmp_buf[width_a-1:0]=a[width_a-1:0];
if (sgate_representation)
begin
for (i=0; i < width_a; i=i+1)
ONES[i] = cin;
end
else
begin
for (i=0; i < width_a; i=i+1)
ONES[i] = cin;
end
temp_result2 = (tmp_buf << amount) | (ONES >> (width_a-amount)) ;
end
assign o = temp_result2[width_o-1:0];
endmodule // oper_left_shift
////------------------------------------------------------------------------------------------
////------------------------------------------------------------------------------------------
`timescale 1 ps / 1ps
module oper_right_shift ( a, amount, cin, o);
parameter width_a = 6;
parameter width_amount = 6;
parameter width_o = 6;
parameter sgate_representation = 0;
input [width_a-1:0] a;
input [width_amount-1:0] amount;
input cin;
output [width_o-1:0] o;
integer i;
reg [width_a-1:0] ONES;
reg [width_a-1:0] tmp_buf;
reg [width_a-1:0] temp_result2;
initial
begin
// check if width_amount > 0
if (width_amount <= 0)
begin
$display("Error! width_amount must be greater than 0.\n");
$display ("Time: %0t Instance: %m", $time);
end
// check if width_a > 0
if (width_a <= 0)
begin
$display("Error! width_a must be greater than 0.\n");
$display ("Time: %0t Instance: %m", $time);
end
// check if width_a = width_o
if (width_a < width_o)
begin
$display("Error! width_a must be greater than or equal to width_o.\n");
$display ("Time: %0t Instance: %m", $time);
end
// check if width_o > 0
if (sgate_representation != 1 && sgate_representation != 0)
begin
$display("Error! sgate_representation value must be 1 (SIGNED) or 0 (UNSIGNED).");
$display ("Time: %0t Instance: %m", $time);
end
end
always @(a or amount or cin)
begin
tmp_buf[width_a-1:0]=a[width_a-1:0];
if (sgate_representation)
begin
for (i=0; i < width_a; i=i+1)
ONES[i] = cin;
end
else
begin
for (i=0; i < width_a; i=i+1)
ONES[i] = cin;
end
if (a[width_a-1] == 0)
begin
temp_result2 = (tmp_buf >> amount);
end
else
begin
temp_result2 = (tmp_buf >> amount) | (ONES << (width_a-amount)) ;
end
end
assign o = temp_result2[width_o-1:0];
endmodule // oper_right_shift
////------------------------------------------------------------------------------------------
////------------------------------------------------------------------------------------------
`timescale 1 ps / 1ps
module oper_rotate_left ( amount, a, o);
parameter width_a = 6;
parameter width_amount = 6;
parameter width_o = 6;
parameter sgate_representation = 0;
input [width_amount-1:0] amount;
input [width_a-1:0] a;
output [width_o-1:0] o;
wire [width_a-1:0] temp_result;
wire temp_direction = 1'h0;
lpm_clshift lpm_clshift_component (
.distance (amount),
.direction (temp_direction),
.data (a),
.result (temp_result),
.underflow (),
.overflow ()
);
defparam
lpm_clshift_component.lpm_type = "LPM_CLSHIFT",
lpm_clshift_component.lpm_shifttype = "ROTATE",
lpm_clshift_component.lpm_width = width_a,
lpm_clshift_component.lpm_widthdist = width_amount;
assign o = temp_result[width_o-1:0];
initial
begin
// check if width_a > 0
if (width_amount <= 0)
begin
$display("Error! width_amount must be greater than 0.\n");
$display ("Time: %0t Instance: %m", $time);
end
if (width_a <= 0)
begin
$display("Error! width_a must be greater than 0.\n");
$display ("Time: %0t Instance: %m", $time);
end
if (width_a != width_o)
begin
$display("Error! width_a must be equal to width_o.\n");
$display ("Time: %0t Instance: %m", $time);
end
if (sgate_representation != 1 && sgate_representation != 0)
begin
$display("Error! sgate_representation value must be 1 (SIGNED) or 0 (UNSIGNED).");
$display ("Time: %0t Instance: %m", $time);
end
end
endmodule //oper_rotate_left
////------------------------------------------------------------------------------------------
////------------------------------------------------------------------------------------------
`timescale 1 ps / 1ps
module oper_rotate_right ( amount, a, o);
parameter width_a = 6;
parameter width_amount = 6;
parameter width_o = 6;
parameter sgate_representation = 0;
input [width_amount-1:0] amount;
input [width_a-1:0] a;
output [width_o-1:0] o;
wire [width_a-1:0] temp_result;
wire temp_direction = 1'h1;
assign o = temp_result[width_o-1:0];
lpm_clshift lpm_clshift_component (
.distance (amount),
.direction (temp_direction),
.data (a),
.result (temp_result),
.underflow (),
.overflow ()
);
defparam
lpm_clshift_component.lpm_type = "LPM_CLSHIFT",
lpm_clshift_component.lpm_shifttype = "ROTATE",
lpm_clshift_component.lpm_width = width_a,
lpm_clshift_component.lpm_widthdist = width_amount;
initial
begin
// check if width_a > 0
if (width_amount <= 0)
begin
$display("Error! width_amount must be greater than 0.\n");
$display ("Time: %0t Instance: %m", $time);
end
if (width_a <= 0)
begin
$display("Error! width_a must be greater than 0.\n");
$display ("Time: %0t Instance: %m", $time);
end
if (width_a != width_o)
begin
$display("Error! width_a must be equal to width_o.\n");
$display ("Time: %0t Instance: %m", $time);
end
if (sgate_representation != 1 && sgate_representation != 0)
begin
$display("Error! sgate_representation value must be 1 (SIGNED) or 0 (UNSIGNED).");
$display ("Time: %0t Instance: %m", $time);
end
end
endmodule //oper_rotate_right
////------------------------------------------------------------------------------------------
////------------------------------------------------------------------------------------------
`timescale 1 ps / 1ps
module oper_less_than (a, b, cin, o);
parameter width_a = 6;
parameter width_b = 6;
parameter sgate_representation = 0;
parameter width_max= width_a>width_b ? width_a : width_b;
input [width_a-1:0] a;
input [width_b-1:0] b;
input cin;
output o;
integer sa;
integer sb;
reg [width_a-1:0] not_a;
reg [width_b-1:0] not_b;
reg tmp_result;
initial
begin
// check if width_a > 0
if (width_a <= 0)
begin
$display("Error! width_a must be greater than 0.\n");
$display ("Time: %0t Instance: %m", $time);
end
if (width_b <= 0)
begin
$display("Error! width_b must be greater than 0.\n");
$display ("Time: %0t Instance: %m", $time);
end
if (sgate_representation != 1 && sgate_representation != 0)
begin
$display("Error! sgate_representation value must be 1 (SIGNED) or 0 (UNSIGNED).");
$display ("Time: %0t Instance: %m", $time);
end
end
always @(a or b or cin)
begin
sa = a;
sb = b;
not_a = ~a;
not_b = ~b;
if (sgate_representation == "SIGNED")
begin
if (a[width_a-1] == 1)
sa = (not_a) * (-1) - 1;
if (b[width_b-1] == 1)
sb = (not_b) * (-1) - 1;
if (sa<sb)
begin
tmp_result = 1;
end
else if ((sa==sb)&&(cin))
begin
tmp_result = 1;
end
else
begin
tmp_result = 0;
end
end
else
begin
if (a<b)
begin
tmp_result = 1;
end
else if ((a==b)&&(cin))
begin
tmp_result = 1;
end
else
begin
tmp_result = 0;
end
end
end
assign o = tmp_result;
endmodule // oper_less_than
////------------------------------------------------------------------------------------------
////------------------------------------------------------------------------------------------
`timescale 1 ps / 1ps
module oper_mux ( sel, data, o);
parameter width_sel = 6;
parameter width_data = 6;
input [width_sel-1:0] sel;
input [width_data-1:0] data;
output o;
reg temp_result;
initial
begin
temp_result = 'bz;
// check if width_a > 0
if (width_data <= 0)
begin
$display("Error! width_data must be greater than 0.\n");
$display ("Time: %0t Instance: %m", $time);
end
// check if width_b > 0
if (width_sel <= 0)
begin
$display("Error! width_sel must be greater than 0.\n");
$display ("Time: %0t Instance: %m", $time);
end
// check if width_o > 0
end
always @(data or sel)
begin
temp_result = data[sel];
end
assign o = temp_result;
endmodule //oper_mux
////------------------------------------------------------------------------------------------
////------------------------------------------------------------------------------------------
`timescale 1 ps / 1ps
module oper_selector ( sel, data, o);
parameter width_sel = 6;
parameter width_data = 6;
input [width_sel-1:0] sel;
input [width_data-1:0] data;
output o;
reg temp_result;
reg [width_data-1:0] result;
integer i;
initial
begin
// check if width_a > 0
if (width_sel <= 0)
begin
$display("Error! width_sel must be greater than 0.\n");
$display ("Time: %0t Instance: %m", $time);
end
if (width_data != width_sel)
begin
$display("Error! width_sel must be equal to width_data.\n");
$display ("Time: %0t Instance: %m", $time);
end
end
always @(data or sel)
begin
temp_result = 1'b0;
for (i = 0; i < width_sel; i = i + 1)
if (sel[i] == 1)
begin
temp_result= temp_result | data[i];
end
end
assign o = temp_result;
endmodule //oper_selector
////------------------------------------------------------------------------------------------
////------------------------------------------------------------------------------------------
`timescale 1 ps / 1ps
module oper_decoder ( i, o);
parameter width_i = 6;
parameter width_o = 6;
input [width_i-1:0] i;
output [width_o-1:0] o;
initial
begin
// check if width_i > 0
if (width_i <= 0)
$display("Error! width_i must be greater than 0.\n");
if (width_o <= 0)
$display("Error! width_o must be greater than 0.\n");
end
lpm_decode lpm_decode_component (
.data (i),
.eq (o),
.enable (),
.clock (),
.aclr (),
.clken ()
);
defparam
lpm_decode_component.lpm_width = width_i,
lpm_decode_component.lpm_decodes = width_o,
lpm_decode_component.lpm_type = "LPM_DECODE";
endmodule //oper_decoder
////------------------------------------------------------------------------------------------
////------------------------------------------------------------------------------------------
`timescale 1 ps / 1ps
module oper_bus_mux ( a, b, sel, o);
parameter width_a = 6;
parameter width_b = 6;
parameter width_o = 6;
input [width_a-1:0] a;
input [width_b-1:0] b;
input sel;
output [width_o-1:0] o;
wire [width_a+width_b-1:0] all_inps;
assign all_inps[width_a-1:0]=a[width_a-1:0];
assign all_inps[width_a+width_b-1:width_a]=b[width_b-1:0];
initial
begin
// check if width_a > 0
if (width_a <= 0)
begin
$display("Error! width_a must be greater than 0.\n");
$display ("Time: %0t Instance: %m", $time);
end
if (width_b <= 0)
begin
$display("Error! width_o must be greater than 0.\n");
$display ("Time: %0t Instance: %m", $time);
end
if (width_a != width_b)
begin
$display("Error! width_a must equal width_b.\n");
$display ("Time: %0t Instance: %m", $time);
end
if (width_a != width_o)
begin
$display("Error! width_a must equal width_o.\n");
$display ("Time: %0t Instance: %m", $time);
end
end
lpm_mux lpm_mux_component (
.data (all_inps),
.sel(sel),
.result (o),
.clock (),
.aclr (),
.clken ()
);
defparam
lpm_mux_component.lpm_width = width_o,
lpm_mux_component.lpm_size = 2,
lpm_mux_component.lpm_widths = 1,
lpm_mux_component.lpm_type = "lpm_mux";
endmodule //oper_bus_mux
////------------------------------------------------------------------------------------------
////------------------------------------------------------------------------------------------
`timescale 1 ps / 1ps
module oper_latch(datain, dataout, latch_enable, aclr, preset);
input datain, latch_enable, aclr, preset;
output dataout;
reg dataout;
always @(datain or latch_enable or aclr or preset)
begin
if (aclr === 1'b1)
dataout = 1'b0;
else if (preset === 1'b1)
dataout = 1'b1;
else if (latch_enable)
dataout = datain;
end
endmodule //oper_latch
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_oclkdelay_cal.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Center write DQS in write DQ valid window using Phaser_Out Stage3
// delay
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_0_ddr_phy_ocd_lim #
(parameter TAPCNTRWIDTH = 7,
parameter DQS_CNT_WIDTH = 3,
parameter DQS_WIDTH = 9,
parameter TCQ = 100,
parameter TAPSPERKCLK = 56,
parameter TDQSS_DEGREES = 60,
parameter BYPASS_COMPLEX_OCAL = "FALSE")
(/*AUTOARG*/
// Outputs
lim2init_write_request, lim2init_prech_req, lim2poc_rdy, lim2poc_ktap_right,
lim2stg3_inc, lim2stg3_dec, lim2stg2_inc, lim2stg2_dec, lim_done,
lim2ocal_stg3_right_lim, lim2ocal_stg3_left_lim, dbg_ocd_lim,
// Inputs
clk, rst, lim_start, po_rdy, poc2lim_rise_align_taps_lead,
poc2lim_rise_align_taps_trail, poc2lim_fall_align_taps_lead,
poc2lim_fall_align_taps_trail, oclkdelay_init_val, wl_po_fine_cnt,
simp_stg3_final_sel, oclkdelay_calib_done, poc2lim_detect_done,
prech_done, oclkdelay_calib_cnt
);
function [TAPCNTRWIDTH:0] mod_sub (input [TAPCNTRWIDTH-1:0] a,
input [TAPCNTRWIDTH-1:0] b,
input integer base);
begin
mod_sub = (a>=b) ? a-b : a+base[TAPCNTRWIDTH-1:0]-b;
end
endfunction // mod_sub
input clk;
input rst;
input lim_start;
input po_rdy;
input [TAPCNTRWIDTH-1:0] poc2lim_rise_align_taps_lead;
input [TAPCNTRWIDTH-1:0] poc2lim_rise_align_taps_trail;
input [TAPCNTRWIDTH-1:0] poc2lim_fall_align_taps_lead;
input [TAPCNTRWIDTH-1:0] poc2lim_fall_align_taps_trail;
input [5:0] oclkdelay_init_val;
input [5:0] wl_po_fine_cnt;
input [5:0] simp_stg3_final_sel;
input oclkdelay_calib_done;
input poc2lim_detect_done;
input prech_done;
input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;
output lim2init_write_request;
output lim2init_prech_req;
output lim2poc_rdy;
output lim2poc_ktap_right; // I think this can be defaulted.
output lim2stg3_inc;
output lim2stg3_dec;
output lim2stg2_inc;
output lim2stg2_dec;
output lim_done;
output [5:0] lim2ocal_stg3_right_lim;
output [5:0] lim2ocal_stg3_left_lim;
output [255:0] dbg_ocd_lim;
// Stage 3 taps can move an additional + or - 60 degrees from the write level position
// Convert 60 degrees to MMCM taps. 360/60=6.
//localparam real DIV_FACTOR = 360/TDQSS_DEGREES;
//localparam real TDQSS_LIM_MMCM_TAPS = TAPSPERKCLK/DIV_FACTOR;
localparam DIV_FACTOR = 360/TDQSS_DEGREES;
localparam TDQSS_LIM_MMCM_TAPS = TAPSPERKCLK/DIV_FACTOR;
localparam WAIT_CNT = 15;
localparam IDLE = 14'b00_0000_0000_0001;
localparam INIT = 14'b00_0000_0000_0010;
localparam WAIT_WR_REQ = 14'b00_0000_0000_0100;
localparam WAIT_POC_DONE = 14'b00_0000_0000_1000;
localparam WAIT_STG3 = 14'b00_0000_0001_0000;
localparam STAGE3_INC = 14'b00_0000_0010_0000;
localparam STAGE3_DEC = 14'b00_0000_0100_0000;
localparam STAGE2_INC = 14'b00_0000_1000_0000;
localparam STAGE2_DEC = 14'b00_0001_0000_0000;
localparam STG3_INCDEC_WAIT = 14'b00_0010_0000_0000;
localparam STG2_INCDEC_WAIT = 14'b00_0100_0000_0000;
localparam STAGE2_TAP_CHK = 14'b00_1000_0000_0000;
localparam PRECH_REQUEST = 14'b01_0000_0000_0000;
localparam LIMIT_DONE = 14'b10_0000_0000_0000;
// Flip-flops
reg [5:0] stg3_init_val;
reg [13:0] lim_state;
reg lim_start_r;
reg ktap_right_r;
reg write_request_r;
reg prech_req_r;
reg poc_ready_r;
reg wait_cnt_en_r;
reg wait_cnt_done;
reg [3:0] wait_cnt_r;
reg [5:0] stg3_tap_cnt;
reg [5:0] stg2_tap_cnt;
reg [5:0] stg3_left_lim;
reg [5:0] stg3_right_lim;
reg [DQS_WIDTH*6-1:0] cmplx_stg3_left_lim;
reg [DQS_WIDTH*6-1:0] simp_stg3_left_lim;
reg [DQS_WIDTH*6-1:0] cmplx_stg3_right_lim;
reg [DQS_WIDTH*6-1:0] simp_stg3_right_lim;
reg [5:0] stg3_dec_val;
reg [5:0] stg3_inc_val;
reg detect_done_r;
reg stg3_dec_r;
reg stg2_inc_r;
reg stg3_inc2init_val_r;
reg stg3_inc2init_val_r1;
reg stg3_dec2init_val_r;
reg stg3_dec2init_val_r1;
reg stg3_dec_req_r;
reg stg3_inc_req_r;
reg stg2_dec_req_r;
reg stg2_inc_req_r;
reg stg3_init_dec_r;
reg [TAPCNTRWIDTH:0] mmcm_current;
reg [TAPCNTRWIDTH:0] mmcm_init_trail;
reg [TAPCNTRWIDTH:0] mmcm_init_lead;
reg done_r;
reg [13:0] lim_nxt_state;
reg ktap_right;
reg write_request;
reg prech_req;
reg poc_ready;
reg stg3_dec;
reg stg2_inc;
reg stg3_inc2init_val;
reg stg3_dec2init_val;
reg stg3_dec_req;
reg stg3_inc_req;
reg stg2_dec_req;
reg stg2_inc_req;
reg stg3_init_dec;
reg done;
reg oclkdelay_calib_done_r;
wire [TAPCNTRWIDTH:0] mmcm_sub_dec = mod_sub (mmcm_init_trail, mmcm_current, TAPSPERKCLK);
wire [TAPCNTRWIDTH:0] mmcm_sub_inc = mod_sub (mmcm_current, mmcm_init_lead, TAPSPERKCLK);
/***************************************************************************/
// Debug signals
/***************************************************************************/
assign dbg_ocd_lim[0+:DQS_WIDTH*6] = simp_stg3_left_lim[DQS_WIDTH*6-1:0];
assign dbg_ocd_lim[54+:DQS_WIDTH*6] = simp_stg3_right_lim[DQS_WIDTH*6-1:0];
assign dbg_ocd_lim[255:108] = 'd0;
assign lim2init_write_request = write_request_r;
assign lim2init_prech_req = prech_req_r;
assign lim2poc_ktap_right = ktap_right_r;
assign lim2poc_rdy = poc_ready_r;
assign lim2ocal_stg3_left_lim = stg3_left_lim;
assign lim2ocal_stg3_right_lim = stg3_right_lim;
assign lim2stg3_dec = stg3_dec_req_r;
assign lim2stg3_inc = stg3_inc_req_r;
assign lim2stg2_dec = stg2_dec_req_r;
assign lim2stg2_inc = stg2_inc_req_r;
assign lim_done = done_r;
/**************************Wait Counter Start*********************************/
// Wait counter enable for wait states WAIT_WR_REQ and WAIT_STG3
// To avoid DQS toggling when stage2 and 3 taps are moving
always @(posedge clk) begin
if ((lim_state == WAIT_WR_REQ) ||
(lim_state == WAIT_STG3) ||
(lim_state == INIT))
wait_cnt_en_r <= #TCQ 1'b1;
else
wait_cnt_en_r <= #TCQ 1'b0;
end
// Wait counter for wait states WAIT_WR_REQ and WAIT_STG3
// To avoid DQS toggling when stage2 and 3 taps are moving
always @(posedge clk) begin
if (!wait_cnt_en_r) begin
wait_cnt_r <= #TCQ 'b0;
wait_cnt_done <= #TCQ 1'b0;
end else begin
if (wait_cnt_r != WAIT_CNT - 1) begin
wait_cnt_r <= #TCQ wait_cnt_r + 1;
wait_cnt_done <= #TCQ 1'b0;
end else begin
wait_cnt_r <= #TCQ 'b0;
wait_cnt_done <= #TCQ 1'b1;
end
end
end
/**************************Wait Counter End***********************************/
// Flip-flops
always @(posedge clk) begin
if (rst)
oclkdelay_calib_done_r <= #TCQ 1'b0;
else
oclkdelay_calib_done_r <= #TCQ oclkdelay_calib_done;
end
always @(posedge clk) begin
if (rst)
stg3_init_val <= #TCQ oclkdelay_init_val;
else if (oclkdelay_calib_done)
stg3_init_val <= #TCQ simp_stg3_final_sel;
else
stg3_init_val <= #TCQ oclkdelay_init_val;
end
always @(posedge clk) begin
if (rst) begin
lim_state <= #TCQ IDLE;
lim_start_r <= #TCQ 1'b0;
ktap_right_r <= #TCQ 1'b0;
write_request_r <= #TCQ 1'b0;
prech_req_r <= #TCQ 1'b0;
poc_ready_r <= #TCQ 1'b0;
detect_done_r <= #TCQ 1'b0;
stg3_dec_r <= #TCQ 1'b0;
stg2_inc_r <= #TCQ 1'b0;
stg3_inc2init_val_r <= #TCQ 1'b0;
stg3_inc2init_val_r1<= #TCQ 1'b0;
stg3_dec2init_val_r <= #TCQ 1'b0;
stg3_dec2init_val_r1<= #TCQ 1'b0;
stg3_dec_req_r <= #TCQ 1'b0;
stg3_inc_req_r <= #TCQ 1'b0;
stg2_dec_req_r <= #TCQ 1'b0;
stg2_inc_req_r <= #TCQ 1'b0;
done_r <= #TCQ 1'b0;
stg3_dec_val <= #TCQ 'd0;
stg3_inc_val <= #TCQ 'd0;
stg3_init_dec_r <= #TCQ 1'b0;
end else begin
lim_state <= #TCQ lim_nxt_state;
lim_start_r <= #TCQ lim_start;
ktap_right_r <= #TCQ ktap_right;
write_request_r <= #TCQ write_request;
prech_req_r <= #TCQ prech_req;
poc_ready_r <= #TCQ poc_ready;
detect_done_r <= #TCQ poc2lim_detect_done;
stg3_dec_r <= #TCQ stg3_dec;
stg2_inc_r <= #TCQ stg2_inc;
stg3_inc2init_val_r <= #TCQ stg3_inc2init_val;
stg3_inc2init_val_r1<= #TCQ stg3_inc2init_val_r;
stg3_dec2init_val_r <= #TCQ stg3_dec2init_val;
stg3_dec2init_val_r1<= #TCQ stg3_dec2init_val_r;
stg3_dec_req_r <= #TCQ stg3_dec_req;
stg3_inc_req_r <= #TCQ stg3_inc_req;
stg2_dec_req_r <= #TCQ stg2_dec_req;
stg2_inc_req_r <= #TCQ stg2_inc_req;
stg3_init_dec_r <= #TCQ stg3_init_dec;
done_r <= #TCQ done;
if (stg3_init_val > (('d63 - wl_po_fine_cnt)/2))
stg3_dec_val <= #TCQ (stg3_init_val - ('d63 - wl_po_fine_cnt)/2);
else
stg3_dec_val <= #TCQ 'd0;
if (stg3_init_val < 'd63 - ((wl_po_fine_cnt)/2))
stg3_inc_val <= #TCQ (stg3_init_val + (wl_po_fine_cnt)/2);
else
stg3_inc_val <= #TCQ 'd63;
end
end
// Keeping track of stage 3 tap count
always @(posedge clk) begin
if (rst)
stg3_tap_cnt <= #TCQ stg3_init_val;
else if ((lim_state == IDLE) || (lim_state == INIT))
stg3_tap_cnt <= #TCQ stg3_init_val;
else if (lim_state == STAGE3_INC)
stg3_tap_cnt <= #TCQ stg3_tap_cnt + 1;
else if (lim_state == STAGE3_DEC)
stg3_tap_cnt <= #TCQ stg3_tap_cnt - 1;
end
// Keeping track of stage 2 tap count
always @(posedge clk) begin
if (rst)
stg2_tap_cnt <= #TCQ 'd0;
else if ((lim_state == IDLE) || (lim_state == INIT))
stg2_tap_cnt <= #TCQ wl_po_fine_cnt;
else if (lim_state == STAGE2_INC)
stg2_tap_cnt <= #TCQ stg2_tap_cnt + 1;
else if (lim_state == STAGE2_DEC)
stg2_tap_cnt <= #TCQ stg2_tap_cnt - 1;
end
// Keeping track of MMCM tap count
always @(posedge clk) begin
if (rst) begin
mmcm_init_trail <= #TCQ 'd0;
mmcm_init_lead <= #TCQ 'd0;
end else if (poc2lim_detect_done && !detect_done_r) begin
if (stg3_tap_cnt == stg3_dec_val)
mmcm_init_trail <= #TCQ poc2lim_rise_align_taps_trail;
if (stg3_tap_cnt == stg3_inc_val)
mmcm_init_lead <= #TCQ poc2lim_rise_align_taps_lead;
end
end
always @(posedge clk) begin
if (rst) begin
mmcm_current <= #TCQ 'd0;
end else if (stg3_dec_r) begin
if (stg3_tap_cnt == stg3_dec_val)
mmcm_current <= #TCQ mmcm_init_trail;
else
mmcm_current <= #TCQ poc2lim_rise_align_taps_lead;
end else begin
if (stg3_tap_cnt == stg3_inc_val)
mmcm_current <= #TCQ mmcm_init_lead;
else
mmcm_current <= #TCQ poc2lim_rise_align_taps_trail;
end
end
// Record Stage3 Left Limit
always @(posedge clk) begin
if (rst) begin
stg3_left_lim <= #TCQ 'd0;
simp_stg3_left_lim <= #TCQ 'd0;
cmplx_stg3_left_lim <= #TCQ 'd0;
end else if (stg3_inc2init_val_r && !stg3_inc2init_val_r1) begin
stg3_left_lim <= #TCQ stg3_tap_cnt;
if (oclkdelay_calib_done)
cmplx_stg3_left_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt;
else
simp_stg3_left_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt;
end else if (lim_start && !lim_start_r)
stg3_left_lim <= #TCQ 'd0;
end
// Record Stage3 Right Limit
always @(posedge clk) begin
if (rst) begin
stg3_right_lim <= #TCQ 'd0;
cmplx_stg3_right_lim <= #TCQ 'd0;
simp_stg3_right_lim <= #TCQ 'd0;
end else if (stg3_dec2init_val_r && !stg3_dec2init_val_r1) begin
stg3_right_lim <= #TCQ stg3_tap_cnt;
if (oclkdelay_calib_done)
cmplx_stg3_right_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt;
else
simp_stg3_right_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt;
end else if (lim_start && !lim_start_r)
stg3_right_lim <= #TCQ 'd0;
end
always @(*) begin
lim_nxt_state = lim_state;
ktap_right = ktap_right_r;
write_request = write_request_r;
prech_req = prech_req_r;
poc_ready = poc_ready_r;
stg3_dec = stg3_dec_r;
stg2_inc = stg2_inc_r;
stg3_inc2init_val = stg3_inc2init_val_r;
stg3_dec2init_val = stg3_dec2init_val_r;
stg3_dec_req = stg3_dec_req_r;
stg3_inc_req = stg3_inc_req_r;
stg2_inc_req = stg2_inc_req_r;
stg2_dec_req = stg2_dec_req_r;
stg3_init_dec = stg3_init_dec_r;
done = done_r;
case(lim_state)
IDLE: begin
if (lim_start && !lim_start_r) begin
lim_nxt_state = INIT;
stg3_dec = 1'b1;
stg2_inc = 1'b1;
stg3_init_dec = 1'b1;
done = 1'b0;
end
//New start of limit module for complex oclkdelay calib
else if (oclkdelay_calib_done && !oclkdelay_calib_done_r && (BYPASS_COMPLEX_OCAL == "FALSE")) begin
done = 1'b0;
end
end
INIT: begin
ktap_right = 1'b1;
// Initial stage 2 increment to 63 for left limit
if (wait_cnt_done)
lim_nxt_state = STAGE2_TAP_CHK;
end
// Wait for DQS to toggle before asserting poc_ready
WAIT_WR_REQ: begin
write_request = 1'b1;
if (wait_cnt_done) begin
poc_ready = 1'b1;
lim_nxt_state = WAIT_POC_DONE;
end
end
// Wait for POC detect done signal
WAIT_POC_DONE: begin
if (poc2lim_detect_done) begin
write_request = 1'b0;
poc_ready = 1'b0;
lim_nxt_state = WAIT_STG3;
end
end
// Wait for DQS to stop toggling before stage3 inc/dec
WAIT_STG3: begin
if (wait_cnt_done) begin
if (stg3_dec_r) begin
// Check for Stage 3 underflow and MMCM tap limit
if ((stg3_tap_cnt > 'd0) && (mmcm_sub_dec < TDQSS_LIM_MMCM_TAPS))
lim_nxt_state = STAGE3_DEC;
else begin
stg3_dec = 1'b0;
stg3_inc2init_val = 1'b1;
lim_nxt_state = STAGE3_INC;
end
end else begin // Stage 3 being incremented
// Check for Stage 3 overflow and MMCM tap limit
if ((stg3_tap_cnt < 'd63) && (mmcm_sub_inc < TDQSS_LIM_MMCM_TAPS))
lim_nxt_state = STAGE3_INC;
else begin
stg3_dec2init_val = 1'b1;
lim_nxt_state = STAGE3_DEC;
end
end
end
end
STAGE3_INC: begin
stg3_inc_req = 1'b1;
lim_nxt_state = STG3_INCDEC_WAIT;
end
STAGE3_DEC: begin
stg3_dec_req = 1'b1;
lim_nxt_state = STG3_INCDEC_WAIT;
end
// Wait for stage3 inc/dec to complete (po_rdy)
STG3_INCDEC_WAIT: begin
stg3_dec_req = 1'b0;
stg3_inc_req = 1'b0;
if (!stg3_dec_req_r && !stg3_inc_req_r && po_rdy) begin
if (stg3_init_dec_r) begin
// Initial decrement of stage 3
if (stg3_tap_cnt > stg3_dec_val)
lim_nxt_state = STAGE3_DEC;
else begin
lim_nxt_state = WAIT_WR_REQ;
stg3_init_dec = 1'b0;
end
end else if (stg3_dec2init_val_r) begin
if (stg3_tap_cnt > stg3_init_val)
lim_nxt_state = STAGE3_DEC;
else
lim_nxt_state = STAGE2_TAP_CHK;
end else if (stg3_inc2init_val_r) begin
if (stg3_tap_cnt < stg3_inc_val)
lim_nxt_state = STAGE3_INC;
else
lim_nxt_state = STAGE2_TAP_CHK;
end else begin
lim_nxt_state = WAIT_WR_REQ;
end
end
end
// Check for overflow and underflow of stage2 taps
STAGE2_TAP_CHK: begin
if (stg3_dec2init_val_r) begin
// Increment stage 2 to write level tap value at the end of limit detection
if (stg2_tap_cnt < wl_po_fine_cnt)
lim_nxt_state = STAGE2_INC;
else begin
lim_nxt_state = PRECH_REQUEST;
end
end else if (stg3_inc2init_val_r) begin
// Decrement stage 2 to '0' to determine right limit
if (stg2_tap_cnt > 'd0)
lim_nxt_state = STAGE2_DEC;
else begin
lim_nxt_state = PRECH_REQUEST;
stg3_inc2init_val = 1'b0;
end
end else if (stg2_inc_r && (stg2_tap_cnt < 'd63)) begin
// Initial increment to 63
lim_nxt_state = STAGE2_INC;
end else begin
lim_nxt_state = STG3_INCDEC_WAIT;
stg2_inc = 1'b0;
end
end
STAGE2_INC: begin
stg2_inc_req = 1'b1;
lim_nxt_state = STG2_INCDEC_WAIT;
end
STAGE2_DEC: begin
stg2_dec_req = 1'b1;
lim_nxt_state = STG2_INCDEC_WAIT;
end
// Wait for stage3 inc/dec to complete (po_rdy)
STG2_INCDEC_WAIT: begin
stg2_inc_req = 1'b0;
stg2_dec_req = 1'b0;
if (!stg2_inc_req_r && !stg2_dec_req_r && po_rdy)
lim_nxt_state = STAGE2_TAP_CHK;
end
PRECH_REQUEST: begin
prech_req = 1'b1;
if (prech_done) begin
prech_req = 1'b0;
if (stg3_dec2init_val_r)
lim_nxt_state = LIMIT_DONE;
else
lim_nxt_state = WAIT_WR_REQ;
end
end
LIMIT_DONE: begin
done = 1'b1;
ktap_right = 1'b0;
stg3_dec2init_val = 1'b0;
lim_nxt_state = IDLE;
end
default: begin
lim_nxt_state = IDLE;
end
endcase
end
endmodule //mig_7_series_v4_0_ddr_phy_ocd_lim
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_pla(clock, resetn,
i_dataa, i_dataa_valid, o_dataa_stall, i_datab, i_datab_valid, o_datab_stall,
i_datac, i_datac_valid, o_datac_stall, i_datad, i_datad_valid, o_datad_stall,
o_dataout, o_dataout_valid, i_stall, i_settings, i_start);
parameter DATA_WIDTH = 1;
parameter CONFIG_WIDTH = 20;
parameter FIFO_DEPTH = 64;
//if upper bits are 0, it means the corresponding data port is not used
input clock, resetn;
input [DATA_WIDTH-1:0] i_dataa;
input [DATA_WIDTH-1:0] i_datab;
input [DATA_WIDTH-1:0] i_datac;
input [DATA_WIDTH-1:0] i_datad;
input i_dataa_valid, i_datab_valid, i_datac_valid, i_datad_valid;
output o_dataa_stall, o_datab_stall, o_datac_stall, o_datad_stall;
output [DATA_WIDTH-1:0] o_dataout;
output o_dataout_valid;
input i_stall;
input [CONFIG_WIDTH-1:0] i_settings;
input i_start;
wire [DATA_WIDTH-1:0] dataa;
wire [DATA_WIDTH-1:0] datab;
wire [DATA_WIDTH-1:0] datac;
wire [DATA_WIDTH-1:0] datad;
//wire [8*DATA_WIDTH-1:0] interim_data;
wire [4*DATA_WIDTH-1:0] interim_data;
wire fifo_a_valid_out;
wire fifo_b_valid_out;
wire fifo_c_valid_out;
wire fifo_d_valid_out;
wire is_fifo_a_valid;
wire is_fifo_b_valid;
wire is_fifo_c_valid;
wire is_fifo_d_valid;
wire is_stalled;
reg [DATA_WIDTH-1:0] and1a;
reg [DATA_WIDTH-1:0] and1b;
reg [DATA_WIDTH-1:0] and2a;
reg [DATA_WIDTH-1:0] and2b;
vfabric_buffered_fifo fifo_a ( .clock(clock), .resetn(resetn),
.data_in(i_dataa), .data_out(dataa), .valid_in(i_dataa_valid),
.valid_out( fifo_a_valid_out ), .stall_in(is_stalled), .stall_out(o_dataa_stall) );
defparam fifo_a.DATA_WIDTH = DATA_WIDTH;
defparam fifo_a.DEPTH = FIFO_DEPTH;
vfabric_buffered_fifo fifo_b ( .clock(clock), .resetn(resetn),
.data_in(i_datab), .data_out(datab), .valid_in(i_datab_valid),
.valid_out( fifo_b_valid_out ), .stall_in(is_stalled), .stall_out(o_datab_stall) );
defparam fifo_b.DATA_WIDTH = DATA_WIDTH;
defparam fifo_b.DEPTH = FIFO_DEPTH;
vfabric_buffered_fifo fifo_c ( .clock(clock), .resetn(resetn),
.data_in(i_datac), .data_out(datac), .valid_in(i_datac_valid),
.valid_out( fifo_c_valid_out ), .stall_in(is_stalled), .stall_out(o_datac_stall) );
defparam fifo_c.DATA_WIDTH = DATA_WIDTH;
defparam fifo_c.DEPTH = FIFO_DEPTH;
vfabric_buffered_fifo fifo_d ( .clock(clock), .resetn(resetn),
.data_in(i_datad), .data_out(datad), .valid_in(i_datad_valid),
.valid_out( fifo_d_valid_out ), .stall_in(is_stalled), .stall_out(o_datad_stall) );
defparam fifo_d.DATA_WIDTH = DATA_WIDTH;
defparam fifo_d.DEPTH = FIFO_DEPTH;
assign is_fifo_a_valid = fifo_a_valid_out | ~i_settings[16];
assign is_fifo_b_valid = fifo_b_valid_out | ~i_settings[17];
assign is_fifo_c_valid = fifo_c_valid_out | ~i_settings[18];
assign is_fifo_d_valid = fifo_d_valid_out | ~i_settings[19];
assign is_stalled = ~(is_fifo_a_valid & is_fifo_b_valid & is_fifo_c_valid & is_fifo_d_valid & ~i_stall);
genvar i;
generate
for(i = 0; i < DATA_WIDTH; i++)
begin : pla_gen
assign interim_data[4*(i+1)-1:4*i] = {datad[i], datac[i], datab[i], dataa[i]};
assign o_dataout[i] = i_settings[interim_data[4*(i+1)-1:4*i]];
end
endgenerate
//assign interim_data = {datad, datac, datab, dataa};
//assign o_dataout = i_settings[interim_data];
// assign interim_data = {datad, datac, datab, dataa, !datad, !datac, !datab, !dataa};
// assign o_dataout = (interim_data[i_settings[11:9]] & interim_data[i_settings[8:6]] & interim_data[i_settings[5:3]] & interim_data[i_settings[2:0]])
// + (interim_data[i_settings[23:21]] & interim_data[i_settings[20:18]] & interim_data[i_settings[17:15]] & interim_data[i_settings[14:12]]);
assign o_dataout_valid = i_start & is_fifo_a_valid & is_fifo_b_valid & is_fifo_c_valid & is_fifo_d_valid;
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : arb_row_col.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// This block receives request to send row and column commands. These requests
// come the individual bank machines. The arbitration winner is selected
// and driven back to the bank machines.
//
// The CS enables are generated. For 2:1 mode, row commands are sent
// in the "0" phase, and column commands are sent in the "1" phase.
//
// In 2T mode, a further arbitration is performed between the row
// and column commands. The winner of this arbitration inhibits
// arbitration by the loser. The winner is allowed to arbitrate, the loser is
// blocked until the next state. The winning address command
// is repeated on both the "0" and the "1" phases and the CS
// is asserted for just the "1" phase.
`timescale 1 ps / 1 ps
module mig_7series_v2_3_arb_row_col #
(
parameter TCQ = 100,
parameter ADDR_CMD_MODE = "1T",
parameter CWL = 5,
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nRAS = 37500, // ACT->PRE cmd period (CKs)
parameter nRCD = 12500, // ACT->R/W delay (CKs)
parameter nWR = 6 // Write recovery (CKs)
)
(/*AUTOARG*/
// Outputs
grant_row_r, grant_pre_r, sent_row, sending_row, sending_pre, grant_config_r,
rnk_config_strobe, rnk_config_valid_r, grant_col_r,
sending_col, sent_col, sent_col_r, grant_col_wr, send_cmd0_row, send_cmd0_col,
send_cmd1_row, send_cmd1_col, send_cmd2_row, send_cmd2_col, send_cmd2_pre,
send_cmd3_col, col_channel_offset, cs_en0, cs_en1, cs_en2, cs_en3,
insert_maint_r1, rnk_config_kill_rts_col,
// Inputs
clk, rst, rts_row, rts_pre, insert_maint_r, rts_col, rtc, col_rdy_wr
);
// Create a delay when switching ranks
localparam RNK2RNK_DLY = 12;
localparam RNK2RNK_DLY_CLKS =
(RNK2RNK_DLY / nCK_PER_CLK) + (RNK2RNK_DLY % nCK_PER_CLK ? 1 : 0);
input clk;
input rst;
input [nBANK_MACHS-1:0] rts_row;
input insert_maint_r;
input [nBANK_MACHS-1:0] rts_col;
reg [RNK2RNK_DLY_CLKS-1:0] rnk_config_strobe_r;
wire block_grant_row;
wire block_grant_col;
wire rnk_config_kill_rts_col_lcl =
RNK2RNK_DLY_CLKS > 0 ? |rnk_config_strobe_r : 1'b0;
output rnk_config_kill_rts_col;
assign rnk_config_kill_rts_col = rnk_config_kill_rts_col_lcl;
wire [nBANK_MACHS-1:0] col_request;
wire granted_col_ns = |col_request;
wire [nBANK_MACHS-1:0] row_request =
rts_row & {nBANK_MACHS{~insert_maint_r}};
wire granted_row_ns = |row_request;
generate
if (ADDR_CMD_MODE == "2T" && nCK_PER_CLK != 4) begin : row_col_2T_arb
assign col_request =
rts_col & {nBANK_MACHS{~(rnk_config_kill_rts_col_lcl || insert_maint_r)}};
// Give column command priority whenever previous state has no row request.
wire [1:0] row_col_grant;
wire [1:0] current_master = ~granted_row_ns ? 2'b10 : row_col_grant;
wire upd_last_master = ~granted_row_ns || |row_col_grant;
mig_7series_v2_3_round_robin_arb #
(.WIDTH (2))
row_col_arb0
(.grant_ns (),
.grant_r (row_col_grant),
.upd_last_master (upd_last_master),
.current_master (current_master),
.clk (clk),
.rst (rst),
.req ({granted_row_ns, granted_col_ns}),
.disable_grant (1'b0));
assign {block_grant_col, block_grant_row} = row_col_grant;
end
else begin : row_col_1T_arb
assign col_request = rts_col & {nBANK_MACHS{~rnk_config_kill_rts_col_lcl}};
assign block_grant_row = 1'b0;
assign block_grant_col = 1'b0;
end
endgenerate
// Row address/command arbitration.
wire[nBANK_MACHS-1:0] grant_row_r_lcl;
output wire[nBANK_MACHS-1:0] grant_row_r;
assign grant_row_r = grant_row_r_lcl;
reg granted_row_r;
always @(posedge clk) granted_row_r <= #TCQ granted_row_ns;
wire sent_row_lcl = granted_row_r && ~block_grant_row;
output wire sent_row;
assign sent_row = sent_row_lcl;
mig_7series_v2_3_round_robin_arb #
(.WIDTH (nBANK_MACHS))
row_arb0
(.grant_ns (),
.grant_r (grant_row_r_lcl[nBANK_MACHS-1:0]),
.upd_last_master (sent_row_lcl),
.current_master (grant_row_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (row_request),
.disable_grant (1'b0));
output wire [nBANK_MACHS-1:0] sending_row;
assign sending_row = grant_row_r_lcl & {nBANK_MACHS{~block_grant_row}};
// Precharge arbitration for 4:1 mode
input [nBANK_MACHS-1:0] rts_pre;
output wire[nBANK_MACHS-1:0] grant_pre_r;
output wire [nBANK_MACHS-1:0] sending_pre;
wire sent_pre_lcl;
generate
if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T")) begin : pre_4_1_1T_arb
reg granted_pre_r;
wire[nBANK_MACHS-1:0] grant_pre_r_lcl;
wire granted_pre_ns = |rts_pre;
assign grant_pre_r = grant_pre_r_lcl;
always @(posedge clk) granted_pre_r <= #TCQ granted_pre_ns;
assign sent_pre_lcl = granted_pre_r;
assign sending_pre = grant_pre_r_lcl;
mig_7series_v2_3_round_robin_arb #
(.WIDTH (nBANK_MACHS))
pre_arb0
(.grant_ns (),
.grant_r (grant_pre_r_lcl[nBANK_MACHS-1:0]),
.upd_last_master (sent_pre_lcl),
.current_master (grant_pre_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (rts_pre),
.disable_grant (1'b0));
end
endgenerate
`ifdef MC_SVA
all_bank_machines_row_arb:
cover property (@(posedge clk) (~rst && &rts_row));
`endif
// Rank config arbitration.
input [nBANK_MACHS-1:0] rtc;
wire [nBANK_MACHS-1:0] grant_config_r_lcl;
output wire [nBANK_MACHS-1:0] grant_config_r;
assign grant_config_r = grant_config_r_lcl;
wire upd_rnk_config_last_master;
mig_7series_v2_3_round_robin_arb #
(.WIDTH (nBANK_MACHS))
config_arb0
(.grant_ns (),
.grant_r (grant_config_r_lcl[nBANK_MACHS-1:0]),
.upd_last_master (upd_rnk_config_last_master),
.current_master (grant_config_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (rtc[nBANK_MACHS-1:0]),
.disable_grant (1'b0));
`ifdef MC_SVA
all_bank_machines_config_arb: cover property (@(posedge clk) (~rst && &rtc));
`endif
wire rnk_config_strobe_ns = ~rnk_config_strobe_r[0] && |rtc && ~granted_col_ns;
always @(posedge clk) rnk_config_strobe_r[0] <= #TCQ rnk_config_strobe_ns;
genvar i;
generate
for(i = 1; i < RNK2RNK_DLY_CLKS; i = i + 1)
always @(posedge clk)
rnk_config_strobe_r[i] <= #TCQ rnk_config_strobe_r[i-1];
endgenerate
output wire rnk_config_strobe;
assign rnk_config_strobe = rnk_config_strobe_r[0];
assign upd_rnk_config_last_master = rnk_config_strobe_r[0];
// Generate rnk_config_valid.
reg rnk_config_valid_r_lcl;
wire rnk_config_valid_ns;
assign rnk_config_valid_ns =
~rst && (rnk_config_valid_r_lcl || rnk_config_strobe_ns);
always @(posedge clk) rnk_config_valid_r_lcl <= #TCQ rnk_config_valid_ns;
output wire rnk_config_valid_r;
assign rnk_config_valid_r = rnk_config_valid_r_lcl;
// Column address/command arbitration.
wire [nBANK_MACHS-1:0] grant_col_r_lcl;
output wire [nBANK_MACHS-1:0] grant_col_r;
assign grant_col_r = grant_col_r_lcl;
reg granted_col_r;
always @(posedge clk) granted_col_r <= #TCQ granted_col_ns;
wire sent_col_lcl;
mig_7series_v2_3_round_robin_arb #
(.WIDTH (nBANK_MACHS))
col_arb0
(.grant_ns (),
.grant_r (grant_col_r_lcl[nBANK_MACHS-1:0]),
.upd_last_master (sent_col_lcl),
.current_master (grant_col_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (col_request),
.disable_grant (1'b0));
`ifdef MC_SVA
all_bank_machines_col_arb:
cover property (@(posedge clk) (~rst && &rts_col));
`endif
output wire [nBANK_MACHS-1:0] sending_col;
assign sending_col = grant_col_r_lcl & {nBANK_MACHS{~block_grant_col}};
assign sent_col_lcl = granted_col_r && ~block_grant_col;
reg sent_col_lcl_r = 1'b0;
always @(posedge clk) sent_col_lcl_r <= #TCQ sent_col_lcl;
output wire sent_col;
assign sent_col = sent_col_lcl;
output wire sent_col_r;
assign sent_col_r = sent_col_lcl_r;
// If we need early wr_data_addr because ECC is on, arbitrate
// to see which bank machine might sent the next wr_data_addr;
input [nBANK_MACHS-1:0] col_rdy_wr;
output wire [nBANK_MACHS-1:0] grant_col_wr;
generate
if (EARLY_WR_DATA_ADDR == "OFF") begin : early_wr_addr_arb_off
assign grant_col_wr = {nBANK_MACHS{1'b0}};
end
else begin : early_wr_addr_arb_on
wire [nBANK_MACHS-1:0] grant_col_wr_raw;
mig_7series_v2_3_round_robin_arb #
(.WIDTH (nBANK_MACHS))
col_arb0
(.grant_ns (grant_col_wr_raw),
.grant_r (),
.upd_last_master (sent_col_lcl),
.current_master (grant_col_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (col_rdy_wr),
.disable_grant (1'b0));
reg [nBANK_MACHS-1:0] grant_col_wr_r;
wire [nBANK_MACHS-1:0] grant_col_wr_ns = granted_col_ns
? grant_col_wr_raw
: grant_col_wr_r;
always @(posedge clk) grant_col_wr_r <= #TCQ grant_col_wr_ns;
assign grant_col_wr = grant_col_wr_ns;
end // block: early_wr_addr_arb_on
endgenerate
output reg send_cmd0_row = 1'b0;
output reg send_cmd0_col = 1'b0;
output reg send_cmd1_row = 1'b0;
output reg send_cmd1_col = 1'b0;
output reg send_cmd2_row = 1'b0;
output reg send_cmd2_col = 1'b0;
output reg send_cmd2_pre = 1'b0;
output reg send_cmd3_col = 1'b0;
output reg cs_en0 = 1'b0;
output reg cs_en1 = 1'b0;
output reg cs_en2 = 1'b0;
output reg cs_en3 = 1'b0;
output wire [5:0] col_channel_offset;
reg insert_maint_r1_lcl;
always @(posedge clk) insert_maint_r1_lcl <= #TCQ insert_maint_r;
output wire insert_maint_r1;
assign insert_maint_r1 = insert_maint_r1_lcl;
wire sent_row_or_maint = sent_row_lcl || insert_maint_r1_lcl;
reg sent_row_or_maint_r = 1'b0;
always @(posedge clk) sent_row_or_maint_r <= #TCQ sent_row_or_maint;
generate
case ({(nCK_PER_CLK == 4), (nCK_PER_CLK == 2), (ADDR_CMD_MODE == "2T")})
3'b000 : begin : one_one_not2T
end
3'b001 : begin : one_one_2T
end
3'b010 : begin : two_one_not2T
if(!(CWL % 2)) begin // Place column commands on slot 0 for even CWL
always @(sent_col_lcl) begin
cs_en0 = sent_col_lcl;
send_cmd0_col = sent_col_lcl;
end
always @(sent_row_or_maint) begin
cs_en1 = sent_row_or_maint;
send_cmd1_row = sent_row_or_maint;
end
assign col_channel_offset = 0;
end
else begin // Place column commands on slot 1 for odd CWL
always @(sent_row_or_maint) begin
cs_en0 = sent_row_or_maint;
send_cmd0_row = sent_row_or_maint;
end
always @(sent_col_lcl) begin
cs_en1 = sent_col_lcl;
send_cmd1_col = sent_col_lcl;
end
assign col_channel_offset = 1;
end
end
3'b011 : begin : two_one_2T
if(!(CWL % 2)) begin // Place column commands on slot 1->0 for even CWL
always @(sent_row_or_maint_r or sent_col_lcl_r)
cs_en0 = sent_row_or_maint_r || sent_col_lcl_r;
always @(sent_row_or_maint or sent_row_or_maint_r) begin
send_cmd0_row = sent_row_or_maint_r;
send_cmd1_row = sent_row_or_maint;
end
always @(sent_col_lcl or sent_col_lcl_r) begin
send_cmd0_col = sent_col_lcl_r;
send_cmd1_col = sent_col_lcl;
end
assign col_channel_offset = 0;
end
else begin // Place column commands on slot 0->1 for odd CWL
always @(sent_col_lcl or sent_row_or_maint)
cs_en1 = sent_row_or_maint || sent_col_lcl;
always @(sent_row_or_maint) begin
send_cmd0_row = sent_row_or_maint;
send_cmd1_row = sent_row_or_maint;
end
always @(sent_col_lcl) begin
send_cmd0_col = sent_col_lcl;
send_cmd1_col = sent_col_lcl;
end
assign col_channel_offset = 1;
end
end
3'b100 : begin : four_one_not2T
if(!(CWL % 2)) begin // Place column commands on slot 0 for even CWL
always @(sent_col_lcl) begin
cs_en0 = sent_col_lcl;
send_cmd0_col = sent_col_lcl;
end
always @(sent_row_or_maint) begin
cs_en1 = sent_row_or_maint;
send_cmd1_row = sent_row_or_maint;
end
assign col_channel_offset = 0;
end
else begin // Place column commands on slot 1 for odd CWL
always @(sent_row_or_maint) begin
cs_en0 = sent_row_or_maint;
send_cmd0_row = sent_row_or_maint;
end
always @(sent_col_lcl) begin
cs_en1 = sent_col_lcl;
send_cmd1_col = sent_col_lcl;
end
assign col_channel_offset = 1;
end
always @(sent_pre_lcl) begin
cs_en2 = sent_pre_lcl;
send_cmd2_pre = sent_pre_lcl;
end
end
3'b101 : begin : four_one_2T
if(!(CWL % 2)) begin // Place column commands on slot 3->0 for even CWL
always @(sent_col_lcl or sent_col_lcl_r) begin
cs_en0 = sent_col_lcl_r;
send_cmd0_col = sent_col_lcl_r;
send_cmd3_col = sent_col_lcl;
end
always @(sent_row_or_maint) begin
cs_en2 = sent_row_or_maint;
send_cmd1_row = sent_row_or_maint;
send_cmd2_row = sent_row_or_maint;
end
assign col_channel_offset = 0;
end
else begin // Place column commands on slot 2->3 for odd CWL
always @(sent_row_or_maint) begin
cs_en1 = sent_row_or_maint;
send_cmd0_row = sent_row_or_maint;
send_cmd1_row = sent_row_or_maint;
end
always @(sent_col_lcl) begin
cs_en3 = sent_col_lcl;
send_cmd2_col = sent_col_lcl;
send_cmd3_col = sent_col_lcl;
end
assign col_channel_offset = 3;
end
end
endcase
endgenerate
endmodule
|
//**************************************************************************
module COUNTER(CLOCK_I, nARST_I, COUNT_O);
parameter CBITS = 3;
input CLOCK_I;
input nARST_I;
output[CBITS-1:0] COUNT_O;
reg[CBITS-1:0] COUNT_O;
always @(posedge CLOCK_I or negedge nARST_I)
if(nARST_I==1'b0)
COUNT_O <= {CBITS{1'b0}};
else
COUNT_O <= COUNT_O + 1;
endmodule
//--------------------------------------------------------------------------
module MULTIPLE_COUNTERS(CLOCK_I, nARST_I, COUNT_O);
parameter M = 3;
parameter CBITS = 4;
input CLOCK_I;
input nARST_I;
output[M*CBITS-1:0] COUNT_O;
COUNTER #(.CBITS(CBITS)) INST_COUNTER[M-1:0] (CLOCK_I, nARST_I, COUNT_O);
endmodule
//--------------------------------------------------------------------------
module TEST_COUNTER;
parameter M = 2;
parameter CBITS = 2;
reg CLOCK;
reg nARST;
reg CTRL_I;
wire[M*CBITS-1:0] COUNTS;
MULTIPLE_COUNTERS #(.M(M),
.CBITS(CBITS)) INST_MCTR(CLOCK, nARST, COUNTS);
initial CLOCK=1;
always #5 CLOCK=~CLOCK;
initial
begin
nARST=1;
#5 nARST=0;
#5 nARST=1;
#200 $display("PASSED");
$finish;
end
endmodule
|
`include "Constants.v"
module StageWriteback (
clk,
reset,
dp,
dce,
da,
dq,
cq,
cwre,
cbsy,
a_in,
operation_in,
ack_in,
operation,
ack
);
parameter A_WIDTH = 12;
parameter D_WIDTH = 8;
input clk;
input reset;
input [A_WIDTH - 1:0] dp;
output dce;
output [A_WIDTH - 1:0] da;
output [D_WIDTH - 1:0] dq;
output [7:0] cq;
output cwre;
input cbsy;
input [D_WIDTH - 1:0] a_in;
input [`OPCODE_MSB:0] operation_in;
output ack;
output reg [`OPCODE_MSB:0] operation;
input ack_in;
/*
* Writing to DRAM
*/
wire need_write_mem;
assign need_write_mem = (operation_in[`OP_INC] || operation_in[`OP_DEC] ||
operation_in[`OP_IN]);
assign da = dp;
assign dce = need_write_mem;
assign dq = a_in;
/*
* Writing to EXT
*/
wire need_write_ext;
assign need_write_ext = operation_in[`OP_OUT];
assign cq = a_in;
assign cwre = !cbsy && need_write_ext;
wire ext_wait;
assign ext_wait = need_write_ext && cbsy;
/*
* ACKing the previous stage
*/
assign ack = ack_in && !ext_wait;
always @(posedge clk) begin
if (reset) begin
operation <= 0;
end else begin
if (ack_in && !ext_wait)
operation <= operation_in;
else if (ack_in)
operation <= 0; /* Bubble */
end
end
endmodule
|
// AJ, Beck, and Ray
// ALUnit testbench
// 5/4/15
`include "adder_subtractor.v"
`include "flag.v"
`include "mux2_1.sv"
`include "adder16b.v"
`include "adder4b.v"
`include "fullAdder1b.v"
`include "lookAhead4b.v"
`include "ALUnit.sv"
`include "addition.v"
`include "subtract.v"
`include "andGate.v"
`include "orGate.v"
`include "xorGate.v"
`include "setLT.v"
`include "shiftll.v"
module ALUnittest();
// localize variables
wire clk; // Clock
wire [2:0] control;
wire [31:0] busADD;
wire [31:0] busA, busB;
wire zero, overflow, carryout, negative;
// declare an instance of the module
ALUnit ALUnit (clk, control, busADD, busA, busB, zero, overflow, carryout, negative);
// Running the GUI part of simulation
ALUnittester tester (clk, control, busADD, busA, busB, zero, overflow, carryout, negative);
// file for gtkwave
initial
begin
$dumpfile("ALUnittest.vcd");
$dumpvars(1, ALUnit);
end
endmodule
module ALUnittester (clk, control, busADD, busA, busB, zero, overflow, carryout, negative);
output clk; // Clock
output [2:0] control;
input [31:0] busADD;
output reg [31:0] busA, busB;
input zero, overflow, carryout, negative;
parameter d = 20;
// generate a clock
always #(d/2) clk = ~clk;
initial // Response
begin
$display("busADD \t busA \t busB \t\t zero \t overflow \t carryout \t negative \t ");
#d;
end
reg [31:0] i;
always @(posedge clk) // Stimulus
begin
$monitor("%b \t %b \t %b \t %b \t %b \t %b \t %b", busADD, busA, busB, zero, overflow, carryout, negative, $time);
// positive + positive
busA = 32'h01010101; busB = 32'h01010101;
#d;
busA = 32'h7FFFFFFF; busB = 32'h7FFFFFFF; // should overflow
#d;
// positive + negative
busA = 32'h01010101; busB = 32'hFFFFFFFF; // 01010101 + -1
#d;
busA = 32'h00000001; busB = 32'hF0000000;
#d;
// negative + positive
busA = 32'hFFFFFFFF; busB = 32'h01010101;
#d;
busA = 32'hF0000000; busB = 32'h00000001;
#d;
// negative + negative
busA = 32'hFFFFFFFF; busB = 32'hFFFFFFFF; // -1 + -1
#d;
busA = 32'h90000000; busB = 32'h80000000; // should overflow
#d;
#(3*d);
$stop;
$finish;
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUX2_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__MUX2_PP_BLACKBOX_V
/**
* mux2: 2-input multiplexer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__mux2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUX2_PP_BLACKBOX_V
|
/*****************************************************************************
* Copyright (c) 2015 by Daniel Grabowski.
*
* This file is part of FrSim.
*
* FrSim is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* FrSim is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with FrSim. If not, see <http://www.gnu.org/licenses/>.
*
* Created by: Daniel Grabowski, Andrew Worcester
*
*****************************************************************************/
`timescale 1ns/1ns
module ivltest();
reg clk;
reg val;
reg c2;
initial
begin
clk <= 0;
val <= 0;
c2 <= 0;
forever
#10 clk <= ~clk;
end
initial
$dumpvars;
initial
#1000 $finish;
initial
begin
$frsim_system;
end
always @ (posedge clk)
c2 <= ~c2;
endmodule // ivltest
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_merge_enc.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_9_ecc_merge_enc
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter CODE_WIDTH = 72,
parameter DATA_BUF_ADDR_WIDTH = 4,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DATA_WIDTH = 64,
parameter DQ_WIDTH = 72,
parameter ECC_WIDTH = 8,
parameter nCK_PER_CLK = 4
)
(
/*AUTOARG*/
// Outputs
mc_wrdata, mc_wrdata_mask,
// Inputs
clk, rst, wr_data, wr_data_mask, rd_merge_data, h_rows, raw_not_ecc
);
input clk;
input rst;
input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data;
input [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask;
input [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data;
reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data_r;
reg [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask_r;
reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data_r;
always @(posedge clk) wr_data_r <= #TCQ wr_data;
always @(posedge clk) wr_data_mask_r <= #TCQ wr_data_mask;
always @(posedge clk) rd_merge_data_r <= #TCQ rd_merge_data;
// Merge new data with memory read data.
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] merged_data;
genvar h;
genvar i;
generate
for (h=0; h<2*nCK_PER_CLK; h=h+1) begin : merge_data_outer
for (i=0; i<DATA_WIDTH/8; i=i+1) begin : merge_data_inner
assign merged_data[h*PAYLOAD_WIDTH+i*8+:8] =
wr_data_mask[h*DATA_WIDTH/8+i]
? rd_merge_data[h*DATA_WIDTH+i*8+:8]
: wr_data[h*PAYLOAD_WIDTH+i*8+:8];
end
if (PAYLOAD_WIDTH > DATA_WIDTH)
assign merged_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH]=
wr_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH];
end
endgenerate
// Generate ECC and overlay onto mc_wrdata.
input [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;
input [2*nCK_PER_CLK-1:0] raw_not_ecc;
reg [2*nCK_PER_CLK-1:0] raw_not_ecc_r;
always @(posedge clk) raw_not_ecc_r <= #TCQ raw_not_ecc;
output reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata;
reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata_c;
genvar j;
integer k;
generate
for (j=0; j<2*nCK_PER_CLK; j=j+1) begin : ecc_word
always @(/*AS*/h_rows or merged_data or raw_not_ecc_r) begin
mc_wrdata_c[j*DQ_WIDTH+:DQ_WIDTH] =
{{DQ_WIDTH-PAYLOAD_WIDTH{1'b0}},
merged_data[j*PAYLOAD_WIDTH+:PAYLOAD_WIDTH]};
for (k=0; k<ECC_WIDTH; k=k+1)
if (~raw_not_ecc_r[j])
mc_wrdata_c[j*DQ_WIDTH+CODE_WIDTH-k-1] =
^(merged_data[j*PAYLOAD_WIDTH+:DATA_WIDTH] &
h_rows[k*CODE_WIDTH+:DATA_WIDTH]);
end
end
endgenerate
always @(posedge clk) mc_wrdata <= mc_wrdata_c;
// Set all DRAM masks to zero.
output wire[2*nCK_PER_CLK*DQ_WIDTH/8-1:0] mc_wrdata_mask;
assign mc_wrdata_mask = {2*nCK_PER_CLK*DQ_WIDTH/8{1'b0}};
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// verilator lint_off UNOPT
// verilator lint_off UNOPTFLAT
reg [31:0] runner; initial runner = 5;
reg [31:0] runnerm1;
reg [59:0] runnerq;
reg [89:0] runnerw;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
`ifdef verilator
if (runner != 0) $stop; // Initial settlement failed
`endif
end
if (cyc==2) begin
runner = 20;
runnerq = 60'h0;
runnerw = 90'h0;
end
if (cyc==3) begin
if (runner != 0) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
// This forms a "loop" where we keep going through the always till runner=0
// This isn't "regular" beh code, but insures our change detection is working properly
always @ (/*AS*/runner) begin
runnerm1 = runner - 32'd1;
end
always @ (/*AS*/runnerm1) begin
if (runner > 0) begin
runner = runnerm1;
runnerq = runnerq - 60'd1;
runnerw = runnerw - 90'd1;
$write ("[%0t] runner=%d\n", $time, runner);
end
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_v2_3_phy_ocd_edge.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Detects and stores edges as the test pattern is scanned via
// manipulating the phaser out stage 3 taps.
//
// Scanning always proceeds from the left to the right. For more
// on the scanning algorithm, see the _po_cntlr block.
//
// Four scan results are reported. The edges at fuzz2zero,
// zero2fuzz, fuzz2oneeighty, and oneeighty2fuzz. Each edge
// has a 6 bit stg3 tap value and a valid bit. The valid bits
// are reset before the scan starts.
//
// Once reset_scan is set low, this block waits for the first
// samp_done while scanning_right. This marks the left end
// of the scan, and initializes prev_samp_r with samp_result and
// sets the prev_samp_r valid bit to one.
//
// At each subesquent samp_done, the previous samp is compared
// to the current samp_result. The case statement details how
// edges are identified.
//
// Original design assumed fuzz between valid regions. Design
// has been updated to tolerate transitions from zero to oneeight
// and vice-versa without fuzz in between.
//
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_ddr_phy_ocd_edge #
(parameter TCQ = 100)
(/*AUTOARG*/
// Outputs
scan_right, z2f, f2z, o2f, f2o, zero2fuzz, fuzz2zero,
oneeighty2fuzz, fuzz2oneeighty,
// Inputs
clk, samp_done, phy_rddata_en_2, reset_scan, scanning_right,
samp_result, stg3
);
localparam [1:0] NULL = 2'b11,
FUZZ = 2'b00,
ONEEIGHTY = 2'b10,
ZERO = 2'b01;
input clk;
input samp_done;
input phy_rddata_en_2;
wire samp_valid = samp_done && phy_rddata_en_2;
input reset_scan;
input scanning_right;
reg prev_samp_valid_ns, prev_samp_valid_r;
always @(posedge clk) prev_samp_valid_r <= #TCQ prev_samp_valid_ns;
always @(*) begin
prev_samp_valid_ns = prev_samp_valid_r;
if (reset_scan) prev_samp_valid_ns = 1'b0;
else if (samp_valid) prev_samp_valid_ns = 1'b1;
end
input [1:0] samp_result;
reg [1:0] prev_samp_ns, prev_samp_r;
always @(posedge clk) prev_samp_r <= #TCQ prev_samp_ns;
always @(*)
if (samp_valid) prev_samp_ns = samp_result;
else prev_samp_ns = prev_samp_r;
reg scan_right_ns, scan_right_r;
always @(posedge clk) scan_right_r <= #TCQ scan_right_ns;
output scan_right;
assign scan_right = scan_right_r;
input [5:0] stg3;
reg z2f_ns, z2f_r, f2z_ns, f2z_r, o2f_ns, o2f_r, f2o_ns, f2o_r;
always @(posedge clk) z2f_r <= #TCQ z2f_ns;
always @(posedge clk) f2z_r <= #TCQ f2z_ns;
always @(posedge clk) o2f_r <= #TCQ o2f_ns;
always @(posedge clk) f2o_r <= #TCQ f2o_ns;
output z2f, f2z, o2f, f2o;
assign z2f = z2f_r;
assign f2z = f2z_r;
assign o2f = o2f_r;
assign f2o = f2o_r;
reg [5:0] zero2fuzz_ns, zero2fuzz_r, fuzz2zero_ns, fuzz2zero_r,
oneeighty2fuzz_ns, oneeighty2fuzz_r, fuzz2oneeighty_ns, fuzz2oneeighty_r;
always @(posedge clk) zero2fuzz_r <= #TCQ zero2fuzz_ns;
always @(posedge clk) fuzz2zero_r <= #TCQ fuzz2zero_ns;
always @(posedge clk) oneeighty2fuzz_r <= #TCQ oneeighty2fuzz_ns;
always @(posedge clk) fuzz2oneeighty_r <= #TCQ fuzz2oneeighty_ns;
output [5:0] zero2fuzz, fuzz2zero, oneeighty2fuzz, fuzz2oneeighty;
assign zero2fuzz = zero2fuzz_r;
assign fuzz2zero = fuzz2zero_r;
assign oneeighty2fuzz = oneeighty2fuzz_r;
assign fuzz2oneeighty = fuzz2oneeighty_r;
always @(*) begin
z2f_ns = z2f_r;
f2z_ns = f2z_r;
o2f_ns = o2f_r;
f2o_ns = f2o_r;
zero2fuzz_ns = zero2fuzz_r;
fuzz2zero_ns = fuzz2zero_r;
oneeighty2fuzz_ns = oneeighty2fuzz_r;
fuzz2oneeighty_ns = fuzz2oneeighty_r;
scan_right_ns = 1'b0;
if (reset_scan) begin
z2f_ns = 1'b0;
f2z_ns = 1'b0;
o2f_ns = 1'b0;
f2o_ns = 1'b0;
end
else if (samp_valid && prev_samp_valid_r)
case (prev_samp_r)
FUZZ :
if (scanning_right) begin
if (samp_result == ZERO) begin
fuzz2zero_ns = stg3;
f2z_ns = 1'b1;
end
if (samp_result == ONEEIGHTY) begin
fuzz2oneeighty_ns = stg3;
f2o_ns = 1'b1;
end
end
ZERO : begin
if (samp_result == FUZZ || samp_result == ONEEIGHTY) scan_right_ns = !scanning_right;
if (scanning_right) begin
if (samp_result == FUZZ) begin
zero2fuzz_ns = stg3 - 6'b1;
z2f_ns = 1'b1;
end
if (samp_result == ONEEIGHTY) begin
zero2fuzz_ns = stg3 - 6'b1;
z2f_ns = 1'b1;
fuzz2oneeighty_ns = stg3;
f2o_ns = 1'b1;
end
end
end
ONEEIGHTY :
if (scanning_right) begin
if (samp_result == FUZZ) begin
oneeighty2fuzz_ns = stg3 - 6'b1;
o2f_ns = 1'b1;
end
if (samp_result == ZERO)
if (f2o_r) begin
oneeighty2fuzz_ns = stg3 - 6'b1;
o2f_ns = 1'b1;
end else begin
fuzz2zero_ns = stg3;
f2z_ns = 1'b1;
end
end // if (scanning_right)
// NULL : // Should never happen
endcase
end
endmodule // mig_7series_v2_3_ddr_phy_ocd_edge
|
`timescale 1ns / 1ps
module Arkanoid(
input iCLK_50,
input btn_W, btn_E, btn_N, btn_S,
input [3:0] iSW,
input iROT_A, iROT_B,
output oVGA_R, oVGA_G, oVGA_B, oHS, oVS,
output [7:0] oLED
);
localparam BALL_NUM = 2;
localparam SHOT_NUM = 2;
reg clk_25;
wire middle, b_dis;
wire [4:0] p_speed;
wire [9:0] p_x, p_y, g_x, g_y;
wire reset, start, btn_r, btn_l;
wire rotary_event, rotary_right;
wire [5:0] b_radius, p_radius;
wire [1:0] b_active;
wire [2:0] g_kind;
wire g_active;
wire [BALL_NUM*10-1:0] b_x, b_y;
wire [10:0] vcounter; // 0~479
wire [11:0] hcounter; // 0~639
wire [3:0] out_back, out_paddle, out_block, out_ball, out_bmem, bm_block, out_gift;
wire [4:0] out_row, out_col, bm_row, bm_col;
wire [1:0] bm_stage, bm_func;
wire bm_ready, bm_enable;
wire st_init, st_dead;
// generate a 25Mhz clock
always @(posedge iCLK_50)
clk_25 = ~clk_25;
// Buttons
syn_edge_detect sed1(iCLK_50, reset, btn_E, btn_r);
syn_edge_detect sed2(iCLK_50, reset, btn_W, btn_l);
syn_edge_detect sed3(iCLK_50, reset, btn_S, start);
// Rotation detection
Rotation_direction r_dir(.CLK(iCLK_50), .ROT_A(iROT_A), .ROT_B(iROT_B),
.rotary_event(rotary_event), .rotary_right(rotary_right));
// Game control
// Paddle control
paddle_control pd_control(.clock(iCLK_50), .reset(reset), .enable(1'b1), .rotary_event(rotary_event),
.rotary_right(rotary_right), .speed(p_speed), .radius(p_radius), .middle(middle), .paddle_x(p_x), .paddle_y(p_y));
state_control s_control(.clock(iCLK_50), .reset(reset), .start(start), .btn_l(btn_l), .btn_r(btn_r), .iSW(iSW),
.bm_ready(bm_ready), .bm_block(bm_block),
.p_x(p_x), .p_y(p_y), .p_radius(p_radius),
.b_active(b_active), .b_radius(b_radius), .o_bx(b_x), .o_by(b_y),
.bm_enable(bm_enable), .bm_row(bm_row), .bm_col(bm_col), .bm_func(bm_func), .bm_stage(bm_stage),
.g_x(g_x), .g_y(g_y), .g_kind(g_kind), .g_active(g_active),
.middle(middle), .p_speed(p_speed), .b_dis(b_dis),
.hp(oLED[7:2]), .dead(st_dead), .init(st_init), .win(st_win));
block_memory b_mem(.clock(iCLK_50), .reset(reset), .enable(bm_enable),
.row1(bm_row), .row2(out_row), .col1(bm_col), .col2(out_col),
.func(bm_func), .stage(bm_stage), .block1(bm_block), .block2(out_bmem), .ready(bm_ready));
// Game display
draw_game d_game(.clock(clk_25), .reset(reset), .visible(visible),
.dead(st_dead), .init(st_init), .win(st_win),
.in_ball(out_ball), .in_gift(out_gift), .in_block(out_block), .in_paddle(out_paddle), .in_back(out_back), .oRGB({oVGA_R, oVGA_G, oVGA_B}));
draw_back d_back(.out(out_back), .vcounter(vcounter), .hcounter(hcounter),
.dead(st_dead), .init(st_init), .win(st_win));
draw_block d_block(.clock(clk_25), .vcounter(vcounter), .hcounter(hcounter), .block(out_bmem),
.sel_row(out_row), .sel_col(out_col), .out(out_block));
draw_ball d_ball(.out(out_ball), .vcounter(vcounter), .hcounter(hcounter), .visible(b_dis),
.xs(b_x), .ys(b_y), .active(b_active), .radius(b_radius));
draw_ball d_shot(.out(out_shot), .vcounter(vcounter), .hcounter(hcounter),
.xs(s_x), .ys(s_y), .active(s_active), .radius(4));
draw_paddle d_paddle(.vcounter(vcounter), .hcounter(hcounter),
.x(p_x), .y(p_y), .radius(p_radius), .out(out_paddle));
draw_gift d_gift(.vcounter(vcounter), .hcounter(hcounter),
.x(g_x), .y(g_y), .kind(g_kind), .active(g_active), .out(out_gift));
VGA_control vga_c(.CLK(clk_25), .reset(reset), .vcounter(vcounter), .hcounter(hcounter),
.visible(visible), .oHS(oHS), .oVS(oVS));
assign reset = btn_N;
assign oLED[1:0] = st_win ? 2'b11 : (st_dead ? 2'b01 : 2'b00);
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <[email protected]>
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module dmac_dest_axi_stream (
input s_axis_aclk,
input s_axis_aresetn,
input enable,
output enabled,
input sync_id,
output sync_id_ret,
input [C_ID_WIDTH-1:0] request_id,
output [C_ID_WIDTH-1:0] response_id,
output [C_ID_WIDTH-1:0] data_id,
input data_eot,
input response_eot,
input m_axis_ready,
output m_axis_valid,
output [C_S_AXIS_DATA_WIDTH-1:0] m_axis_data,
output fifo_ready,
input fifo_valid,
input [C_S_AXIS_DATA_WIDTH-1:0] fifo_data,
input req_valid,
output req_ready,
input [3:0] req_last_burst_length,
output response_valid,
input response_ready,
output response_resp_eot,
output [1:0] response_resp
);
parameter C_ID_WIDTH = 3;
parameter C_S_AXIS_DATA_WIDTH = 64;
parameter C_LENGTH_WIDTH = 24;
assign sync_id_ret = sync_id;
wire data_enabled;
wire [C_ID_WIDTH-1:0] data_id;
wire _fifo_ready;
// We are not allowed to just de-assert valid, but if the streaming target does
// not accept any samples anymore we'd lock up the DMA core. So retain the last
// beat when disabled until it is accepted. But if in the meantime the DMA core
// is re-enabled and new data becomes available overwrite the old.
dmac_data_mover # (
.C_ID_WIDTH(C_ID_WIDTH),
.C_DATA_WIDTH(C_S_AXIS_DATA_WIDTH),
.C_DISABLE_WAIT_FOR_ID(0)
) i_data_mover (
.clk(s_axis_aclk),
.resetn(s_axis_aresetn),
.enable(enable),
.enabled(data_enabled),
.sync_id(sync_id),
.request_id(request_id),
.response_id(data_id),
.eot(data_eot),
.req_valid(req_valid),
.req_ready(req_ready),
.req_last_burst_length(req_last_burst_length),
.m_axi_ready(m_axis_ready),
.m_axi_valid(m_axis_valid),
.m_axi_data(m_axis_data),
.s_axi_ready(_fifo_ready),
.s_axi_valid(fifo_valid),
.s_axi_data(fifo_data)
);
dmac_response_generator # (
.C_ID_WIDTH(C_ID_WIDTH)
) i_response_generator (
.clk(s_axis_aclk),
.resetn(s_axis_aresetn),
.enable(data_enabled),
.enabled(enabled),
.sync_id(sync_id),
.request_id(data_id),
.response_id(response_id),
.eot(response_eot),
.resp_valid(response_valid),
.resp_ready(response_ready),
.resp_eot(response_resp_eot),
.resp_resp(response_resp)
);
assign fifo_ready = _fifo_ready | ~enabled;
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Expert(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Wed Oct 19 14:30:45 2016
/////////////////////////////////////////////////////////////
module add_sub_carry_out_W26_DW01_add_1 ( A, B, CI, SUM, CO );
input [26:0] A;
input [26:0] B;
output [26:0] SUM;
input CI;
output CO;
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n12, n13, n14, n15, n16, n17,
n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31,
n32, n33, n34, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46,
n47, n48, n49, n50, n51, n54, n55, n57, n58, n59, n60, n61, n62, n63,
n64, n66, n67, n68, n69, n70, n174, n175, n176, n177, n178;
AFHCONX2TS U4 ( .A(B[23]), .B(A[23]), .CI(n14), .CON(n13), .S(SUM[23]) );
AFHCONX2TS U6 ( .A(B[21]), .B(A[21]), .CI(n16), .CON(n15), .S(SUM[21]) );
AFHCONX2TS U8 ( .A(B[19]), .B(A[19]), .CI(n18), .CON(n17), .S(SUM[19]) );
AFHCONX2TS U10 ( .A(B[17]), .B(A[17]), .CI(n20), .CON(n19), .S(SUM[17]) );
AFHCONX2TS U12 ( .A(B[15]), .B(A[15]), .CI(n22), .CON(n21), .S(SUM[15]) );
AFHCONX2TS U14 ( .A(B[13]), .B(A[13]), .CI(n24), .CON(n23), .S(SUM[13]) );
AFHCONX2TS U16 ( .A(B[11]), .B(A[11]), .CI(n26), .CON(n25), .S(SUM[11]) );
NOR2X1TS U95 ( .A(A[4]), .B(B[4]), .Y(n54) );
NOR2X1TS U96 ( .A(A[2]), .B(B[2]), .Y(n63) );
NOR2X1TS U97 ( .A(A[3]), .B(B[3]), .Y(n60) );
NOR2X1TS U98 ( .A(A[5]), .B(B[5]), .Y(n49) );
NAND2X1TS U99 ( .A(A[4]), .B(B[4]), .Y(n55) );
NOR2X1TS U100 ( .A(A[1]), .B(B[1]), .Y(n67) );
NAND2X1TS U101 ( .A(A[2]), .B(B[2]), .Y(n64) );
NAND2X1TS U102 ( .A(A[1]), .B(B[1]), .Y(n68) );
AOI21X1TS U103 ( .A0(n177), .A1(n47), .B0(n48), .Y(n46) );
INVX2TS U104 ( .A(n57), .Y(n177) );
INVX2TS U105 ( .A(n36), .Y(n174) );
INVX2TS U106 ( .A(n66), .Y(n178) );
AOI21X1TS U107 ( .A0(n58), .A1(n66), .B0(n59), .Y(n57) );
NOR2X1TS U108 ( .A(n63), .B(n60), .Y(n58) );
OAI21X1TS U109 ( .A0(n60), .A1(n64), .B0(n61), .Y(n59) );
OAI21X1TS U110 ( .A0(n67), .A1(n70), .B0(n68), .Y(n66) );
OAI21X1TS U111 ( .A0(n57), .A1(n37), .B0(n38), .Y(n36) );
NAND2X1TS U112 ( .A(n47), .B(n39), .Y(n37) );
AOI21X1TS U113 ( .A0(n39), .A1(n48), .B0(n40), .Y(n38) );
NOR2X1TS U114 ( .A(n44), .B(n41), .Y(n39) );
OAI21X1TS U115 ( .A0(n49), .A1(n55), .B0(n50), .Y(n48) );
NOR2X1TS U116 ( .A(n54), .B(n49), .Y(n47) );
OAI21X1TS U117 ( .A0(n41), .A1(n45), .B0(n42), .Y(n40) );
OAI21X1TS U118 ( .A0(n174), .A1(n33), .B0(n34), .Y(n32) );
AOI21X1TS U119 ( .A0(n177), .A1(n175), .B0(n176), .Y(n51) );
INVX2TS U120 ( .A(n55), .Y(n176) );
OAI21X1TS U121 ( .A0(n178), .A1(n63), .B0(n64), .Y(n62) );
OAI21X1TS U122 ( .A0(n46), .A1(n44), .B0(n45), .Y(n43) );
NAND2BX1TS U123 ( .AN(n67), .B(n68), .Y(n9) );
NAND2BX1TS U124 ( .AN(n49), .B(n50), .Y(n5) );
NAND2BX1TS U125 ( .AN(n63), .B(n64), .Y(n8) );
NAND2BX1TS U126 ( .AN(n44), .B(n45), .Y(n4) );
NAND2BX1TS U127 ( .AN(n33), .B(n34), .Y(n2) );
NAND2BX1TS U128 ( .AN(n60), .B(n61), .Y(n7) );
NAND2BX1TS U129 ( .AN(n41), .B(n42), .Y(n3) );
NAND2BX1TS U130 ( .AN(n30), .B(n31), .Y(n1) );
NAND2X1TS U131 ( .A(n175), .B(n55), .Y(n6) );
INVX2TS U132 ( .A(n54), .Y(n175) );
AFHCINX2TS U133 ( .CIN(n27), .B(A[10]), .A(B[10]), .S(SUM[10]), .CO(n26) );
AOI21X1TS U134 ( .A0(n36), .A1(n28), .B0(n29), .Y(n27) );
NOR2X1TS U135 ( .A(n33), .B(n30), .Y(n28) );
OAI21X1TS U136 ( .A0(n30), .A1(n34), .B0(n31), .Y(n29) );
AFHCINX2TS U137 ( .CIN(n25), .B(A[12]), .A(B[12]), .S(SUM[12]), .CO(n24) );
AFHCINX2TS U138 ( .CIN(n23), .B(A[14]), .A(B[14]), .S(SUM[14]), .CO(n22) );
AFHCINX2TS U139 ( .CIN(n21), .B(A[16]), .A(B[16]), .S(SUM[16]), .CO(n20) );
AFHCINX2TS U140 ( .CIN(n19), .B(A[18]), .A(B[18]), .S(SUM[18]), .CO(n18) );
AFHCINX2TS U141 ( .CIN(n17), .B(A[20]), .A(B[20]), .S(SUM[20]), .CO(n16) );
AFHCINX2TS U142 ( .CIN(n15), .B(A[22]), .A(B[22]), .S(SUM[22]), .CO(n14) );
AFHCINX2TS U143 ( .CIN(n13), .B(A[24]), .A(B[24]), .S(SUM[24]), .CO(n12) );
NOR2X1TS U144 ( .A(A[6]), .B(B[6]), .Y(n44) );
NOR2X1TS U145 ( .A(A[8]), .B(B[8]), .Y(n33) );
NOR2X1TS U146 ( .A(A[7]), .B(B[7]), .Y(n41) );
NOR2X1TS U147 ( .A(A[9]), .B(B[9]), .Y(n30) );
NAND2X1TS U148 ( .A(A[0]), .B(B[0]), .Y(n70) );
NAND2X1TS U149 ( .A(A[6]), .B(B[6]), .Y(n45) );
NAND2X1TS U150 ( .A(A[8]), .B(B[8]), .Y(n34) );
NAND2X1TS U151 ( .A(A[3]), .B(B[3]), .Y(n61) );
NAND2X1TS U152 ( .A(A[5]), .B(B[5]), .Y(n50) );
NAND2X1TS U153 ( .A(A[7]), .B(B[7]), .Y(n42) );
NAND2X1TS U154 ( .A(A[9]), .B(B[9]), .Y(n31) );
CMPR32X2TS U155 ( .A(A[25]), .B(B[25]), .C(n12), .CO(SUM[26]), .S(SUM[25])
);
XOR2X1TS U156 ( .A(n46), .B(n4), .Y(SUM[6]) );
XOR2X1TS U157 ( .A(n174), .B(n2), .Y(SUM[8]) );
XNOR2X1TS U158 ( .A(n32), .B(n1), .Y(SUM[9]) );
XNOR2X1TS U159 ( .A(n43), .B(n3), .Y(SUM[7]) );
XNOR2X1TS U160 ( .A(n177), .B(n6), .Y(SUM[4]) );
INVX2TS U161 ( .A(n10), .Y(SUM[0]) );
XOR2X1TS U162 ( .A(n9), .B(n70), .Y(SUM[1]) );
XOR2X1TS U163 ( .A(n178), .B(n8), .Y(SUM[2]) );
XOR2X1TS U164 ( .A(n51), .B(n5), .Y(SUM[5]) );
XNOR2X1TS U165 ( .A(n62), .B(n7), .Y(SUM[3]) );
NAND2BX1TS U166 ( .AN(n69), .B(n70), .Y(n10) );
NOR2X1TS U167 ( .A(A[0]), .B(B[0]), .Y(n69) );
endmodule
module add_sub_carry_out_W26_DW01_sub_1 ( A, B, CI, DIFF, CO );
input [26:0] A;
input [26:0] B;
output [26:0] DIFF;
input CI;
output CO;
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n33, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45,
n46, n47, n48, n49, n50, n53, n54, n56, n57, n58, n59, n60, n61, n62,
n63, n65, n66, n67, n68, n224, n225, n226, n227, n228, n229, n230,
n231, n232, n233, n234, n235, n236, n237, n238, n239, n240, n241,
n242, n243, n244, n245, n246, n247, n248, n249, n250, n251, n252,
n253, n254;
AFHCONX2TS U4 ( .A(A[23]), .B(n231), .CI(n13), .CON(n12), .S(DIFF[23]) );
AFHCONX2TS U6 ( .A(A[21]), .B(n233), .CI(n15), .CON(n14), .S(DIFF[21]) );
AFHCONX2TS U8 ( .A(A[19]), .B(n235), .CI(n17), .CON(n16), .S(DIFF[19]) );
AFHCONX2TS U10 ( .A(A[17]), .B(n237), .CI(n19), .CON(n18), .S(DIFF[17]) );
AFHCONX2TS U12 ( .A(A[15]), .B(n239), .CI(n21), .CON(n20), .S(DIFF[15]) );
AFHCONX2TS U14 ( .A(A[13]), .B(n241), .CI(n23), .CON(n22), .S(DIFF[13]) );
AFHCONX2TS U16 ( .A(A[11]), .B(n243), .CI(n25), .CON(n24), .S(DIFF[11]) );
AOI21X1TS U118 ( .A0(n35), .A1(n27), .B0(n28), .Y(n26) );
CMPR32X2TS U119 ( .A(n229), .B(A[25]), .C(n11), .CO(n10), .S(DIFF[25]) );
CLKINVX2TS U120 ( .A(n65), .Y(n228) );
NOR2X1TS U121 ( .A(n250), .B(A[4]), .Y(n53) );
NOR2X1TS U122 ( .A(n249), .B(A[5]), .Y(n48) );
NOR2X1TS U123 ( .A(n254), .B(A[0]), .Y(n68) );
NAND2X1TS U124 ( .A(n250), .B(A[4]), .Y(n54) );
NOR2X1TS U125 ( .A(n253), .B(A[1]), .Y(n66) );
NAND2X1TS U126 ( .A(n252), .B(A[2]), .Y(n63) );
NOR2X1TS U127 ( .A(n252), .B(A[2]), .Y(n62) );
NOR2X1TS U128 ( .A(n251), .B(A[3]), .Y(n59) );
NAND2X1TS U129 ( .A(n253), .B(A[1]), .Y(n67) );
INVX2TS U130 ( .A(B[1]), .Y(n253) );
INVX2TS U131 ( .A(B[0]), .Y(n254) );
AOI21X1TS U132 ( .A0(n227), .A1(n46), .B0(n47), .Y(n45) );
INVX2TS U133 ( .A(n56), .Y(n227) );
INVX2TS U134 ( .A(n35), .Y(n224) );
AOI21X1TS U135 ( .A0(n57), .A1(n65), .B0(n58), .Y(n56) );
NOR2X1TS U136 ( .A(n62), .B(n59), .Y(n57) );
OAI21X1TS U137 ( .A0(n59), .A1(n63), .B0(n60), .Y(n58) );
OAI21X1TS U138 ( .A0(n66), .A1(n68), .B0(n67), .Y(n65) );
OAI21X1TS U139 ( .A0(n56), .A1(n36), .B0(n37), .Y(n35) );
NAND2X1TS U140 ( .A(n46), .B(n38), .Y(n36) );
AOI21X1TS U141 ( .A0(n38), .A1(n47), .B0(n39), .Y(n37) );
NOR2X1TS U142 ( .A(n43), .B(n40), .Y(n38) );
OAI21X1TS U143 ( .A0(n48), .A1(n54), .B0(n49), .Y(n47) );
NOR2X1TS U144 ( .A(n53), .B(n48), .Y(n46) );
OAI21X1TS U145 ( .A0(n40), .A1(n44), .B0(n41), .Y(n39) );
OAI21X1TS U146 ( .A0(n29), .A1(n33), .B0(n30), .Y(n28) );
OAI21X1TS U147 ( .A0(n224), .A1(n32), .B0(n33), .Y(n31) );
OAI21X1TS U148 ( .A0(n45), .A1(n43), .B0(n44), .Y(n42) );
AOI21X1TS U149 ( .A0(n227), .A1(n225), .B0(n226), .Y(n50) );
INVX2TS U150 ( .A(n54), .Y(n226) );
OAI21X1TS U151 ( .A0(n228), .A1(n62), .B0(n63), .Y(n61) );
NAND2BX1TS U152 ( .AN(n66), .B(n67), .Y(n9) );
NAND2BX1TS U153 ( .AN(n48), .B(n49), .Y(n5) );
NAND2BX1TS U154 ( .AN(n62), .B(n63), .Y(n8) );
NAND2BX1TS U155 ( .AN(n43), .B(n44), .Y(n4) );
NAND2BX1TS U156 ( .AN(n32), .B(n33), .Y(n2) );
NAND2BX1TS U157 ( .AN(n59), .B(n60), .Y(n7) );
NAND2BX1TS U158 ( .AN(n40), .B(n41), .Y(n3) );
NAND2BX1TS U159 ( .AN(n29), .B(n30), .Y(n1) );
NAND2X1TS U160 ( .A(n225), .B(n54), .Y(n6) );
INVX2TS U161 ( .A(n53), .Y(n225) );
INVX2TS U162 ( .A(B[11]), .Y(n243) );
INVX2TS U163 ( .A(B[13]), .Y(n241) );
INVX2TS U164 ( .A(B[15]), .Y(n239) );
INVX2TS U165 ( .A(B[17]), .Y(n237) );
INVX2TS U166 ( .A(B[19]), .Y(n235) );
INVX2TS U167 ( .A(B[21]), .Y(n233) );
INVX2TS U168 ( .A(B[23]), .Y(n231) );
AFHCINX2TS U169 ( .CIN(n26), .B(n244), .A(A[10]), .S(DIFF[10]), .CO(n25) );
INVX2TS U170 ( .A(B[10]), .Y(n244) );
NOR2X1TS U171 ( .A(n32), .B(n29), .Y(n27) );
AFHCINX2TS U172 ( .CIN(n24), .B(n242), .A(A[12]), .S(DIFF[12]), .CO(n23) );
INVX2TS U173 ( .A(B[12]), .Y(n242) );
AFHCINX2TS U174 ( .CIN(n22), .B(n240), .A(A[14]), .S(DIFF[14]), .CO(n21) );
INVX2TS U175 ( .A(B[14]), .Y(n240) );
AFHCINX2TS U176 ( .CIN(n20), .B(n238), .A(A[16]), .S(DIFF[16]), .CO(n19) );
INVX2TS U177 ( .A(B[16]), .Y(n238) );
AFHCINX2TS U178 ( .CIN(n18), .B(n236), .A(A[18]), .S(DIFF[18]), .CO(n17) );
INVX2TS U179 ( .A(B[18]), .Y(n236) );
AFHCINX2TS U180 ( .CIN(n16), .B(n234), .A(A[20]), .S(DIFF[20]), .CO(n15) );
INVX2TS U181 ( .A(B[20]), .Y(n234) );
AFHCINX2TS U182 ( .CIN(n14), .B(n232), .A(A[22]), .S(DIFF[22]), .CO(n13) );
INVX2TS U183 ( .A(B[22]), .Y(n232) );
AFHCINX2TS U184 ( .CIN(n12), .B(n230), .A(A[24]), .S(DIFF[24]), .CO(n11) );
INVX2TS U185 ( .A(B[24]), .Y(n230) );
NOR2X1TS U186 ( .A(n248), .B(A[6]), .Y(n43) );
NOR2X1TS U187 ( .A(n246), .B(A[8]), .Y(n32) );
NOR2X1TS U188 ( .A(n247), .B(A[7]), .Y(n40) );
NOR2X1TS U189 ( .A(n245), .B(A[9]), .Y(n29) );
NAND2X1TS U190 ( .A(n248), .B(A[6]), .Y(n44) );
NAND2X1TS U191 ( .A(n246), .B(A[8]), .Y(n33) );
INVX2TS U192 ( .A(n10), .Y(DIFF[26]) );
NAND2X1TS U193 ( .A(n251), .B(A[3]), .Y(n60) );
NAND2X1TS U194 ( .A(n249), .B(A[5]), .Y(n49) );
NAND2X1TS U195 ( .A(n247), .B(A[7]), .Y(n41) );
NAND2X1TS U196 ( .A(n245), .B(A[9]), .Y(n30) );
INVX2TS U197 ( .A(B[4]), .Y(n250) );
INVX2TS U198 ( .A(B[2]), .Y(n252) );
INVX2TS U199 ( .A(B[5]), .Y(n249) );
INVX2TS U200 ( .A(B[3]), .Y(n251) );
INVX2TS U201 ( .A(B[7]), .Y(n247) );
INVX2TS U202 ( .A(B[6]), .Y(n248) );
INVX2TS U203 ( .A(B[8]), .Y(n246) );
INVX2TS U204 ( .A(B[9]), .Y(n245) );
INVX2TS U205 ( .A(B[25]), .Y(n229) );
XOR2X1TS U206 ( .A(n45), .B(n4), .Y(DIFF[6]) );
XOR2X1TS U207 ( .A(n224), .B(n2), .Y(DIFF[8]) );
XNOR2X1TS U208 ( .A(n31), .B(n1), .Y(DIFF[9]) );
XNOR2X1TS U209 ( .A(n42), .B(n3), .Y(DIFF[7]) );
XNOR2X1TS U210 ( .A(n227), .B(n6), .Y(DIFF[4]) );
XNOR2X1TS U211 ( .A(n254), .B(A[0]), .Y(DIFF[0]) );
XOR2X1TS U212 ( .A(n9), .B(n68), .Y(DIFF[1]) );
XOR2X1TS U213 ( .A(n228), .B(n8), .Y(DIFF[2]) );
XOR2X1TS U214 ( .A(n50), .B(n5), .Y(DIFF[5]) );
XNOR2X1TS U215 ( .A(n61), .B(n7), .Y(DIFF[3]) );
endmodule
module add_sub_carry_out_W26 ( op_mode, Data_A, Data_B, Data_S );
input [25:0] Data_A;
input [25:0] Data_B;
output [26:0] Data_S;
input op_mode;
wire N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15, N16, N17,
N18, N19, N20, N21, N22, N23, N24, N25, N26, N27, N28, N29, N30, N31,
N32, N33, N34, N35, N36, N37, N38, N39, N40, N41, N42, N43, N44, N45,
N46, N47, N48, N49, N50, N51, N52, N53, N54, N55, N56, n9, n10, n11,
n12, n13, n14;
add_sub_carry_out_W26_DW01_add_1 add_36 ( .A({1'b0, Data_A}), .B({1'b0,
Data_B}), .CI(1'b0), .SUM({N56, N55, N54, N53, N52, N51, N50, N49, N48,
N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34,
N33, N32, N31, N30}) );
add_sub_carry_out_W26_DW01_sub_1 sub_34 ( .A({1'b0, Data_A}), .B({1'b0,
Data_B}), .CI(1'b0), .DIFF({N29, N28, N27, N26, N25, N24, N23, N22,
N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7,
N6, N5, N4, N3}) );
CLKBUFX2TS U3 ( .A(op_mode), .Y(n13) );
INVX2TS U4 ( .A(n13), .Y(n11) );
INVX2TS U5 ( .A(n13), .Y(n10) );
INVX2TS U6 ( .A(n13), .Y(n12) );
CLKBUFX2TS U7 ( .A(op_mode), .Y(n14) );
AO22X1TS U8 ( .A0(N56), .A1(n10), .B0(N29), .B1(n14), .Y(Data_S[26]) );
AO22X1TS U9 ( .A0(N54), .A1(n10), .B0(N27), .B1(n9), .Y(Data_S[24]) );
AO22X1TS U10 ( .A0(N55), .A1(n10), .B0(N28), .B1(n14), .Y(Data_S[25]) );
AO22X1TS U11 ( .A0(N52), .A1(n10), .B0(N25), .B1(n9), .Y(Data_S[22]) );
AO22X1TS U12 ( .A0(N53), .A1(n10), .B0(N26), .B1(n9), .Y(Data_S[23]) );
AO22X1TS U13 ( .A0(N48), .A1(n11), .B0(N21), .B1(n9), .Y(Data_S[18]) );
AO22X1TS U14 ( .A0(N49), .A1(n11), .B0(N22), .B1(n9), .Y(Data_S[19]) );
AO22X1TS U15 ( .A0(N50), .A1(n10), .B0(N23), .B1(n9), .Y(Data_S[20]) );
AO22X1TS U16 ( .A0(N51), .A1(n10), .B0(N24), .B1(n9), .Y(Data_S[21]) );
AO22X1TS U17 ( .A0(N44), .A1(n11), .B0(N17), .B1(n13), .Y(Data_S[14]) );
AO22X1TS U18 ( .A0(N45), .A1(n11), .B0(N18), .B1(n13), .Y(Data_S[15]) );
AO22X1TS U19 ( .A0(N46), .A1(n11), .B0(N19), .B1(n9), .Y(Data_S[16]) );
AO22X1TS U20 ( .A0(N47), .A1(n11), .B0(N20), .B1(n9), .Y(Data_S[17]) );
AO22X1TS U21 ( .A0(N9), .A1(n14), .B0(N36), .B1(n12), .Y(Data_S[6]) );
AO22X1TS U22 ( .A0(N38), .A1(n10), .B0(N11), .B1(n14), .Y(Data_S[8]) );
AO22X1TS U23 ( .A0(N39), .A1(n10), .B0(n13), .B1(N12), .Y(Data_S[9]) );
AO22X1TS U24 ( .A0(N40), .A1(n11), .B0(N13), .B1(n13), .Y(Data_S[10]) );
AO22X1TS U25 ( .A0(N41), .A1(n12), .B0(N14), .B1(n13), .Y(Data_S[11]) );
AO22X1TS U26 ( .A0(N42), .A1(n11), .B0(N15), .B1(n9), .Y(Data_S[12]) );
AO22X1TS U27 ( .A0(N43), .A1(n11), .B0(N16), .B1(n13), .Y(Data_S[13]) );
AO22X1TS U28 ( .A0(N37), .A1(n10), .B0(N10), .B1(n14), .Y(Data_S[7]) );
AO22X1TS U29 ( .A0(N7), .A1(n14), .B0(N34), .B1(n12), .Y(Data_S[4]) );
AO22X1TS U30 ( .A0(N30), .A1(n11), .B0(N3), .B1(n14), .Y(Data_S[0]) );
AO22X1TS U31 ( .A0(N4), .A1(n14), .B0(N31), .B1(n12), .Y(Data_S[1]) );
AO22X1TS U32 ( .A0(N5), .A1(n14), .B0(N32), .B1(n12), .Y(Data_S[2]) );
AO22X1TS U33 ( .A0(N8), .A1(n13), .B0(N35), .B1(n12), .Y(Data_S[5]) );
CLKBUFX2TS U34 ( .A(op_mode), .Y(n9) );
AO22X1TS U35 ( .A0(N6), .A1(n14), .B0(N33), .B1(n12), .Y(Data_S[3]) );
endmodule
module RegisterAdd_W26 ( clk, rst, load, D, Q );
input [25:0] D;
output [25:0] Q;
input clk, rst, load;
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38,
n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n53,
n72, n73, n74, n75, n76, n77, n78, n79, n84, n85, n86, n87, n88, n89,
n90, n91;
DFFRX2TS \Q_reg[25] ( .D(n53), .CK(clk), .RN(n84), .Q(Q[25]), .QN(n74) );
DFFRX2TS \Q_reg[24] ( .D(n51), .CK(clk), .RN(n84), .Q(Q[24]), .QN(n73) );
DFFRX2TS \Q_reg[23] ( .D(n50), .CK(clk), .RN(n84), .Q(Q[23]), .QN(n72) );
DFFRX2TS \Q_reg[22] ( .D(n49), .CK(clk), .RN(n84), .Q(Q[22]), .QN(n79) );
DFFRX2TS \Q_reg[21] ( .D(n48), .CK(clk), .RN(n84), .Q(Q[21]), .QN(n78) );
DFFRX2TS \Q_reg[20] ( .D(n47), .CK(clk), .RN(n84), .Q(Q[20]), .QN(n77) );
DFFRX2TS \Q_reg[19] ( .D(n46), .CK(clk), .RN(n84), .Q(Q[19]), .QN(n76) );
DFFRX2TS \Q_reg[18] ( .D(n45), .CK(clk), .RN(n84), .Q(Q[18]), .QN(n75) );
DFFRX2TS \Q_reg[17] ( .D(n44), .CK(clk), .RN(n84), .Q(Q[17]), .QN(n18) );
DFFRX2TS \Q_reg[16] ( .D(n43), .CK(clk), .RN(n84), .Q(Q[16]), .QN(n17) );
DFFRX2TS \Q_reg[15] ( .D(n42), .CK(clk), .RN(n85), .Q(Q[15]), .QN(n16) );
DFFRX2TS \Q_reg[14] ( .D(n41), .CK(clk), .RN(n85), .Q(Q[14]), .QN(n15) );
DFFRX2TS \Q_reg[13] ( .D(n40), .CK(clk), .RN(n85), .Q(Q[13]), .QN(n14) );
DFFRX2TS \Q_reg[12] ( .D(n39), .CK(clk), .RN(n85), .Q(Q[12]), .QN(n13) );
DFFRX2TS \Q_reg[11] ( .D(n38), .CK(clk), .RN(n85), .Q(Q[11]), .QN(n12) );
DFFRX2TS \Q_reg[10] ( .D(n37), .CK(clk), .RN(n85), .Q(Q[10]), .QN(n11) );
DFFRX2TS \Q_reg[9] ( .D(n36), .CK(clk), .RN(n85), .Q(Q[9]), .QN(n10) );
DFFRX2TS \Q_reg[8] ( .D(n35), .CK(clk), .RN(n85), .Q(Q[8]), .QN(n9) );
DFFRX2TS \Q_reg[7] ( .D(n34), .CK(clk), .RN(n85), .Q(Q[7]), .QN(n8) );
DFFRX2TS \Q_reg[6] ( .D(n33), .CK(clk), .RN(n85), .Q(Q[6]), .QN(n7) );
DFFRX2TS \Q_reg[5] ( .D(n32), .CK(clk), .RN(n91), .Q(Q[5]), .QN(n6) );
DFFRX2TS \Q_reg[4] ( .D(n31), .CK(clk), .RN(n91), .Q(Q[4]), .QN(n5) );
DFFRX2TS \Q_reg[3] ( .D(n30), .CK(clk), .RN(n91), .Q(Q[3]), .QN(n4) );
DFFRX2TS \Q_reg[2] ( .D(n29), .CK(clk), .RN(n91), .Q(Q[2]), .QN(n3) );
DFFRX2TS \Q_reg[1] ( .D(n28), .CK(clk), .RN(n91), .Q(Q[1]), .QN(n2) );
DFFRX2TS \Q_reg[0] ( .D(n27), .CK(clk), .RN(n91), .Q(Q[0]), .QN(n1) );
CLKBUFX2TS U2 ( .A(n90), .Y(n86) );
CLKBUFX2TS U3 ( .A(n90), .Y(n87) );
CLKBUFX2TS U4 ( .A(n89), .Y(n88) );
CLKBUFX2TS U5 ( .A(n91), .Y(n85) );
CLKBUFX2TS U6 ( .A(n91), .Y(n84) );
OAI2BB2XLTS U7 ( .B0(n73), .B1(load), .A0N(D[24]), .A1N(n88), .Y(n51) );
OAI2BB2XLTS U8 ( .B0(n74), .B1(load), .A0N(n89), .A1N(D[25]), .Y(n53) );
OAI2BB2XLTS U9 ( .B0(n79), .B1(n90), .A0N(D[22]), .A1N(n88), .Y(n49) );
OAI2BB2XLTS U10 ( .B0(n72), .B1(n89), .A0N(D[23]), .A1N(n88), .Y(n50) );
OAI2BB2XLTS U11 ( .B0(n75), .B1(n90), .A0N(D[18]), .A1N(n87), .Y(n45) );
OAI2BB2XLTS U12 ( .B0(n76), .B1(n90), .A0N(D[19]), .A1N(n87), .Y(n46) );
OAI2BB2XLTS U13 ( .B0(n77), .B1(n90), .A0N(D[20]), .A1N(n88), .Y(n47) );
OAI2BB2XLTS U14 ( .B0(n78), .B1(n89), .A0N(D[21]), .A1N(n88), .Y(n48) );
OAI2BB2XLTS U15 ( .B0(n15), .B1(n89), .A0N(D[14]), .A1N(n87), .Y(n41) );
OAI2BB2XLTS U16 ( .B0(n16), .B1(load), .A0N(D[15]), .A1N(n87), .Y(n42) );
OAI2BB2XLTS U17 ( .B0(n17), .B1(load), .A0N(D[16]), .A1N(n87), .Y(n43) );
OAI2BB2XLTS U18 ( .B0(n18), .B1(load), .A0N(D[17]), .A1N(n87), .Y(n44) );
OAI2BB2XLTS U19 ( .B0(n7), .B1(load), .A0N(D[6]), .A1N(n88), .Y(n33) );
OAI2BB2XLTS U20 ( .B0(n9), .B1(n89), .A0N(D[8]), .A1N(n87), .Y(n35) );
OAI2BB2XLTS U21 ( .B0(n10), .B1(n89), .A0N(D[9]), .A1N(n86), .Y(n36) );
OAI2BB2XLTS U22 ( .B0(n11), .B1(n90), .A0N(D[10]), .A1N(n86), .Y(n37) );
OAI2BB2XLTS U23 ( .B0(n12), .B1(n90), .A0N(D[11]), .A1N(n86), .Y(n38) );
OAI2BB2XLTS U24 ( .B0(n13), .B1(n89), .A0N(D[12]), .A1N(n86), .Y(n39) );
OAI2BB2XLTS U25 ( .B0(n14), .B1(n89), .A0N(D[13]), .A1N(n87), .Y(n40) );
OAI2BB2XLTS U26 ( .B0(n8), .B1(n89), .A0N(D[7]), .A1N(n87), .Y(n34) );
OAI2BB2XLTS U27 ( .B0(n5), .B1(n86), .A0N(D[4]), .A1N(n88), .Y(n31) );
OAI2BB2XLTS U28 ( .B0(n1), .B1(n86), .A0N(D[0]), .A1N(n90), .Y(n27) );
OAI2BB2XLTS U29 ( .B0(n2), .B1(n86), .A0N(D[1]), .A1N(n88), .Y(n28) );
OAI2BB2XLTS U30 ( .B0(n3), .B1(n86), .A0N(D[2]), .A1N(n88), .Y(n29) );
OAI2BB2XLTS U31 ( .B0(n6), .B1(n86), .A0N(D[5]), .A1N(n87), .Y(n32) );
OAI2BB2XLTS U32 ( .B0(n4), .B1(n86), .A0N(D[3]), .A1N(n88), .Y(n30) );
CLKBUFX2TS U33 ( .A(load), .Y(n90) );
CLKBUFX2TS U34 ( .A(load), .Y(n89) );
INVX2TS U35 ( .A(rst), .Y(n91) );
endmodule
module RegisterAdd_W1 ( clk, rst, load, D, Q );
input [0:0] D;
output [0:0] Q;
input clk, rst, load;
wire n3, n4, n6;
DFFRX2TS \Q_reg[0] ( .D(n3), .CK(clk), .RN(n6), .Q(Q[0]), .QN(n4) );
OAI2BB2XLTS U2 ( .B0(n4), .B1(load), .A0N(load), .A1N(D[0]), .Y(n3) );
INVX2TS U3 ( .A(rst), .Y(n6) );
endmodule
module Add_Subt ( clk, rst, load_i, Add_Sub_op_i, Data_A_i, PreData_B_i,
Data_Result_o, FSM_C_o );
input [25:0] Data_A_i;
input [25:0] PreData_B_i;
output [25:0] Data_Result_o;
input clk, rst, load_i, Add_Sub_op_i;
output FSM_C_o;
wire [26:0] S_to_D;
add_sub_carry_out_W26 Sgf_AS ( .op_mode(Add_Sub_op_i), .Data_A(Data_A_i),
.Data_B(PreData_B_i), .Data_S(S_to_D) );
RegisterAdd_W26 Add_Subt_Result ( .clk(clk), .rst(rst), .load(load_i), .D(
S_to_D[25:0]), .Q(Data_Result_o) );
RegisterAdd_W1 Add_overflow_Result ( .clk(clk), .rst(rst), .load(load_i),
.D(S_to_D[26]), .Q(FSM_C_o) );
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFSTP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__DFSTP_FUNCTIONAL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps/sky130_fd_sc_hvl__udp_dff_ps.v"
`celldefine
module sky130_fd_sc_hvl__dfstp (
Q ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
// Local signals
wire buf_Q;
wire SET ;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hvl__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , D, CLK, SET );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFSTP_FUNCTIONAL_V |
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module lpddr2_cntrlr_p0_acv_hard_addr_cmd_pads(
/*
config_data_in,
config_clock_in,
config_io_ena,
config_update,
*/
reset_n,
reset_n_afi_clk,
pll_hr_clk,
pll_avl_phy_clk,
pll_afi_clk,
pll_mem_clk,
pll_write_clk,
phy_ddio_address,
dll_delayctrl_in,
phy_ddio_bank,
phy_ddio_cs_n,
phy_ddio_cke,
phy_ddio_odt,
phy_ddio_we_n,
phy_ddio_ras_n,
phy_ddio_cas_n,
phy_ddio_ck,
phy_ddio_reset_n,
phy_mem_address,
phy_mem_bank,
phy_mem_cs_n,
phy_mem_cke,
phy_mem_odt,
phy_mem_we_n,
phy_mem_ras_n,
phy_mem_cas_n,
phy_mem_reset_n,
phy_mem_ck,
phy_mem_ck_n
);
parameter DEVICE_FAMILY = "";
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_CHIP_SELECT_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_BANK_WIDTH = "";
parameter AFI_CHIP_SELECT_WIDTH = "";
parameter AFI_CLK_EN_WIDTH = "";
parameter AFI_ODT_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter DLL_WIDTH = "";
parameter ADC_PHASE_SETTING = "";
parameter ADC_INVERT_PHASE = "";
parameter IS_HHP_HPS = "";
/*
input config_data_in;
input config_clock_in;
input config_io_ena;
input config_update;
*/
input reset_n;
input reset_n_afi_clk;
input pll_afi_clk;
input pll_hr_clk;
input pll_avl_phy_clk;
input pll_mem_clk;
input pll_write_clk;
input [DLL_WIDTH-1:0] dll_delayctrl_in;
input [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
input [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
input [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
input [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ck;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_reset_n;
output [MEM_ADDRESS_WIDTH-1:0] phy_mem_address;
output [MEM_BANK_WIDTH-1:0] phy_mem_bank;
output [MEM_CHIP_SELECT_WIDTH-1:0] phy_mem_cs_n;
output [MEM_CLK_EN_WIDTH-1:0] phy_mem_cke;
output [MEM_ODT_WIDTH-1:0] phy_mem_odt;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_we_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_cas_n;
output phy_mem_reset_n;
output [MEM_CK_WIDTH-1:0] phy_mem_ck;
output [MEM_CK_WIDTH-1:0] phy_mem_ck_n;
/* ********* *
* A/C Logic *
* ********* */
localparam CMD_WIDTH =
MEM_CHIP_SELECT_WIDTH +
MEM_CLK_EN_WIDTH +
MEM_ODT_WIDTH +
MEM_CONTROL_WIDTH +
MEM_CONTROL_WIDTH +
MEM_CONTROL_WIDTH;
localparam AC_CLK_WIDTH = MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH + CMD_WIDTH + 1;
localparam IMPLEMENT_MEM_CLK_IN_SOFT_LOGIC = "false";
wire [AC_CLK_WIDTH-1:0] ac_clk;
generate
genvar i;
for (i = 0; i < AC_CLK_WIDTH; i = i + 1)
begin: address_gen
wire addr_cmd_clk;
lpddr2_cntrlr_p0_acv_ldc # (
.DLL_DELAY_CTRL_WIDTH(DLL_WIDTH),
.ADC_PHASE_SETTING(2),
.ADC_INVERT_PHASE(ADC_INVERT_PHASE),
.IS_HHP_HPS(IS_HHP_HPS)
) acv_ac_ldc (
.pll_hr_clk(pll_avl_phy_clk),
.pll_dq_clk(pll_write_clk),
.pll_dqs_clk (pll_mem_clk),
.dll_phy_delayctrl(dll_delayctrl_in),
.adc_clk_cps(ac_clk[i])
);
end
endgenerate
lpddr2_cntrlr_p0_generic_ddio uaddress_pad(
.datain(phy_ddio_address),
.halfratebypass(1'b1),
.dataout(phy_mem_address),
.clk_hr({MEM_ADDRESS_WIDTH{pll_hr_clk}}),
.clk_fr(ac_clk[MEM_ADDRESS_WIDTH-1:0])
);
defparam uaddress_pad.WIDTH = MEM_ADDRESS_WIDTH;
lpddr2_cntrlr_p0_generic_ddio ubank_pad(
.datain(phy_ddio_bank),
.halfratebypass(1'b1),
.dataout(phy_mem_bank),
.clk_hr({MEM_BANK_WIDTH{pll_hr_clk}}),
.clk_fr(ac_clk[MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH - 1: MEM_ADDRESS_WIDTH])
);
defparam ubank_pad.WIDTH = MEM_BANK_WIDTH;
lpddr2_cntrlr_p0_generic_ddio ucmd_pad(
.datain({
phy_ddio_we_n,
phy_ddio_cas_n,
phy_ddio_ras_n,
phy_ddio_odt,
phy_ddio_cke,
phy_ddio_cs_n
}),
.halfratebypass(1'b1),
.dataout({
phy_mem_we_n,
phy_mem_cas_n,
phy_mem_ras_n,
phy_mem_odt,
phy_mem_cke,
phy_mem_cs_n
}),
.clk_hr({CMD_WIDTH{pll_hr_clk}}),
.clk_fr(ac_clk[MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH + CMD_WIDTH - 1: MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH])
);
defparam ucmd_pad.WIDTH = CMD_WIDTH;
lpddr2_cntrlr_p0_generic_ddio ureset_n_pad(
.datain(phy_ddio_reset_n),
.halfratebypass(1'b1),
.dataout(phy_mem_reset_n),
.clk_hr(pll_hr_clk),
.clk_fr(ac_clk[MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH + CMD_WIDTH])
);
defparam ureset_n_pad.WIDTH = 1;
/* ************ *
* Config Logic *
* ************ */
wire [4:0] outputdelaysetting;
wire [4:0] outputenabledelaysetting;
wire outputhalfratebypass;
wire [4:0] inputdelaysetting;
wire [1:0] rfifo_clock_select;
wire [2:0] rfifo_mode;
/*
cyclonev_io_config ioconfig (
.datain(config_data_in),
.clk(config_clock_in),
.ena(config_io_ena),
.update(config_update),
.outputregdelaysetting(outputdelaysetting),
.outputenabledelaysetting(outputenabledelaysetting),
.outputhalfratebypass(outputhalfratebypass),
.readfiforeadclockselect(rfifo_clock_select),
.readfifomode(rfifo_mode),
.padtoinputregisterdelaysetting(inputdelaysetting),
.dataout()
);
*/
/* *************** *
* Mem Clock Logic *
* *************** */
wire [MEM_CK_WIDTH-1:0] mem_ck_source;
wire [MEM_CK_WIDTH-1:0] mem_ck;
generate
genvar clock_width;
for (clock_width=0; clock_width<MEM_CK_WIDTH; clock_width=clock_width+1)
begin: clock_gen
if(IMPLEMENT_MEM_CLK_IN_SOFT_LOGIC == "true")
begin
lpddr2_cntrlr_p0_acv_ldc # (
.DLL_DELAY_CTRL_WIDTH(DLL_WIDTH),
.ADC_PHASE_SETTING(ADC_PHASE_SETTING),
.ADC_INVERT_PHASE(ADC_INVERT_PHASE),
.IS_HHP_HPS(IS_HHP_HPS)
) acv_ck_ldc (
.pll_hr_clk(pll_avl_phy_clk),
.pll_dq_clk(pll_write_clk),
.pll_dqs_clk (pll_mem_clk),
.dll_phy_delayctrl(dll_delayctrl_in),
.adc_clk_cps(mem_ck_source[clock_width])
);
end
else
begin
wire [3:0] phy_clk_in;
wire [3:0] phy_clk_out;
assign phy_clk_in = {pll_avl_phy_clk,pll_write_clk,pll_mem_clk,1'b0};
if (IS_HHP_HPS == "true") begin
assign phy_clk_out = phy_clk_in;
end else begin
cyclonev_phy_clkbuf phy_clkbuf (
.inclk (phy_clk_in),
.outclk (phy_clk_out)
);
end
wire [3:0] leveled_dqs_clocks;
cyclonev_leveling_delay_chain leveling_delay_chain_dqs (
.clkin (phy_clk_out[1]),
.delayctrlin (dll_delayctrl_in),
.clkout(leveled_dqs_clocks)
);
defparam leveling_delay_chain_dqs.physical_clock_source = "DQS";
cyclonev_clk_phase_select clk_phase_select_dqs (
`ifndef SIMGEN
.clkin (leveled_dqs_clocks[0]),
`else
.clkin (leveled_dqs_clocks),
`endif
.clkout (mem_ck_source[clock_width])
);
defparam clk_phase_select_dqs.physical_clock_source = "DQS";
defparam clk_phase_select_dqs.use_phasectrlin = "false";
defparam clk_phase_select_dqs.phase_setting = 0;
end
wire mem_ck_hi;
wire mem_ck_lo;
if(IMPLEMENT_MEM_CLK_IN_SOFT_LOGIC == "true")
begin
assign mem_ck_hi = 1'b0;
assign mem_ck_lo = 1'b1;
end
else
begin
assign mem_ck_hi = phy_ddio_ck[0];
assign mem_ck_lo = phy_ddio_ck[1];
end
altddio_out umem_ck_pad(
.aclr (1'b0),
.aset (1'b0),
.datain_h (mem_ck_hi),
.datain_l (mem_ck_lo),
.dataout (mem_ck[clock_width]),
.oe (1'b1),
.outclock (mem_ck_source[clock_width]),
.outclocken (1'b1)
);
defparam
umem_ck_pad.extend_oe_disable = "UNUSED",
umem_ck_pad.intended_device_family = DEVICE_FAMILY,
umem_ck_pad.invert_output = "OFF",
umem_ck_pad.lpm_hint = "UNUSED",
umem_ck_pad.lpm_type = "altddio_out",
umem_ck_pad.oe_reg = "UNUSED",
umem_ck_pad.power_up_high = "OFF",
umem_ck_pad.width = 1;
wire mem_ck_temp;
assign mem_ck_temp = mem_ck[clock_width];
lpddr2_cntrlr_p0_clock_pair_generator uclk_generator(
.datain (mem_ck_temp),
.dataout (phy_mem_ck[clock_width]),
.dataout_b (phy_mem_ck_n[clock_width])
);
end
endgenerate
endmodule
|
//Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
//Date : Fri Mar 31 14:00:38 2017
//Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
//Command : generate_target mig_wrap_wrapper.bd
//Design : mig_wrap_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module mig_wrap_wrapper
(ACLK,
ARESETN,
DDR3_addr,
DDR3_ba,
DDR3_cas_n,
DDR3_ck_n,
DDR3_ck_p,
DDR3_cke,
DDR3_cs_n,
DDR3_dm,
DDR3_dq,
DDR3_dqs_n,
DDR3_dqs_p,
DDR3_odt,
DDR3_ras_n,
DDR3_reset_n,
DDR3_we_n,
S00_ARESETN,
S00_AXI_araddr,
S00_AXI_arburst,
S00_AXI_arcache,
S00_AXI_arid,
S00_AXI_arlen,
S00_AXI_arlock,
S00_AXI_arprot,
S00_AXI_arqos,
S00_AXI_arready,
S00_AXI_arregion,
S00_AXI_arsize,
S00_AXI_arvalid,
S00_AXI_awaddr,
S00_AXI_awburst,
S00_AXI_awcache,
S00_AXI_awid,
S00_AXI_awlen,
S00_AXI_awlock,
S00_AXI_awprot,
S00_AXI_awqos,
S00_AXI_awready,
S00_AXI_awregion,
S00_AXI_awsize,
S00_AXI_awvalid,
S00_AXI_bid,
S00_AXI_bready,
S00_AXI_bresp,
S00_AXI_bvalid,
S00_AXI_rdata,
S00_AXI_rid,
S00_AXI_rlast,
S00_AXI_rready,
S00_AXI_rresp,
S00_AXI_rvalid,
S00_AXI_wdata,
S00_AXI_wlast,
S00_AXI_wready,
S00_AXI_wstrb,
S00_AXI_wvalid,
sys_clk_i,
sys_rst);
input ACLK;
input ARESETN;
output [13:0]DDR3_addr;
output [2:0]DDR3_ba;
output DDR3_cas_n;
output [0:0]DDR3_ck_n;
output [0:0]DDR3_ck_p;
output [0:0]DDR3_cke;
output [0:0]DDR3_cs_n;
output [7:0]DDR3_dm;
inout [63:0]DDR3_dq;
inout [7:0]DDR3_dqs_n;
inout [7:0]DDR3_dqs_p;
output [0:0]DDR3_odt;
output DDR3_ras_n;
output DDR3_reset_n;
output DDR3_we_n;
input S00_ARESETN;
input [31:0]S00_AXI_araddr;
input [1:0]S00_AXI_arburst;
input [3:0]S00_AXI_arcache;
input [3:0]S00_AXI_arid;
input [7:0]S00_AXI_arlen;
input [0:0]S00_AXI_arlock;
input [2:0]S00_AXI_arprot;
input [3:0]S00_AXI_arqos;
output S00_AXI_arready;
input [3:0]S00_AXI_arregion;
input [2:0]S00_AXI_arsize;
input S00_AXI_arvalid;
input [31:0]S00_AXI_awaddr;
input [1:0]S00_AXI_awburst;
input [3:0]S00_AXI_awcache;
input [3:0]S00_AXI_awid;
input [7:0]S00_AXI_awlen;
input [0:0]S00_AXI_awlock;
input [2:0]S00_AXI_awprot;
input [3:0]S00_AXI_awqos;
output S00_AXI_awready;
input [3:0]S00_AXI_awregion;
input [2:0]S00_AXI_awsize;
input S00_AXI_awvalid;
output [3:0]S00_AXI_bid;
input S00_AXI_bready;
output [1:0]S00_AXI_bresp;
output S00_AXI_bvalid;
output [31:0]S00_AXI_rdata;
output [3:0]S00_AXI_rid;
output S00_AXI_rlast;
input S00_AXI_rready;
output [1:0]S00_AXI_rresp;
output S00_AXI_rvalid;
input [31:0]S00_AXI_wdata;
input S00_AXI_wlast;
output S00_AXI_wready;
input [3:0]S00_AXI_wstrb;
input S00_AXI_wvalid;
input sys_clk_i;
input sys_rst;
wire ACLK;
wire ARESETN;
wire [13:0]DDR3_addr;
wire [2:0]DDR3_ba;
wire DDR3_cas_n;
wire [0:0]DDR3_ck_n;
wire [0:0]DDR3_ck_p;
wire [0:0]DDR3_cke;
wire [0:0]DDR3_cs_n;
wire [7:0]DDR3_dm;
wire [63:0]DDR3_dq;
wire [7:0]DDR3_dqs_n;
wire [7:0]DDR3_dqs_p;
wire [0:0]DDR3_odt;
wire DDR3_ras_n;
wire DDR3_reset_n;
wire DDR3_we_n;
wire S00_ARESETN;
wire [31:0]S00_AXI_araddr;
wire [1:0]S00_AXI_arburst;
wire [3:0]S00_AXI_arcache;
wire [3:0]S00_AXI_arid;
wire [7:0]S00_AXI_arlen;
wire [0:0]S00_AXI_arlock;
wire [2:0]S00_AXI_arprot;
wire [3:0]S00_AXI_arqos;
wire S00_AXI_arready;
wire [3:0]S00_AXI_arregion;
wire [2:0]S00_AXI_arsize;
wire S00_AXI_arvalid;
wire [31:0]S00_AXI_awaddr;
wire [1:0]S00_AXI_awburst;
wire [3:0]S00_AXI_awcache;
wire [3:0]S00_AXI_awid;
wire [7:0]S00_AXI_awlen;
wire [0:0]S00_AXI_awlock;
wire [2:0]S00_AXI_awprot;
wire [3:0]S00_AXI_awqos;
wire S00_AXI_awready;
wire [3:0]S00_AXI_awregion;
wire [2:0]S00_AXI_awsize;
wire S00_AXI_awvalid;
wire [3:0]S00_AXI_bid;
wire S00_AXI_bready;
wire [1:0]S00_AXI_bresp;
wire S00_AXI_bvalid;
wire [31:0]S00_AXI_rdata;
wire [3:0]S00_AXI_rid;
wire S00_AXI_rlast;
wire S00_AXI_rready;
wire [1:0]S00_AXI_rresp;
wire S00_AXI_rvalid;
wire [31:0]S00_AXI_wdata;
wire S00_AXI_wlast;
wire S00_AXI_wready;
wire [3:0]S00_AXI_wstrb;
wire S00_AXI_wvalid;
wire sys_clk_i;
wire sys_rst;
mig_wrap mig_wrap_i
(.ACLK(ACLK),
.ARESETN(ARESETN),
.DDR3_addr(DDR3_addr),
.DDR3_ba(DDR3_ba),
.DDR3_cas_n(DDR3_cas_n),
.DDR3_ck_n(DDR3_ck_n),
.DDR3_ck_p(DDR3_ck_p),
.DDR3_cke(DDR3_cke),
.DDR3_cs_n(DDR3_cs_n),
.DDR3_dm(DDR3_dm),
.DDR3_dq(DDR3_dq),
.DDR3_dqs_n(DDR3_dqs_n),
.DDR3_dqs_p(DDR3_dqs_p),
.DDR3_odt(DDR3_odt),
.DDR3_ras_n(DDR3_ras_n),
.DDR3_reset_n(DDR3_reset_n),
.DDR3_we_n(DDR3_we_n),
.S00_ARESETN(S00_ARESETN),
.S00_AXI_araddr(S00_AXI_araddr),
.S00_AXI_arburst(S00_AXI_arburst),
.S00_AXI_arcache(S00_AXI_arcache),
.S00_AXI_arid(S00_AXI_arid),
.S00_AXI_arlen(S00_AXI_arlen),
.S00_AXI_arlock(S00_AXI_arlock),
.S00_AXI_arprot(S00_AXI_arprot),
.S00_AXI_arqos(S00_AXI_arqos),
.S00_AXI_arready(S00_AXI_arready),
.S00_AXI_arregion(S00_AXI_arregion),
.S00_AXI_arsize(S00_AXI_arsize),
.S00_AXI_arvalid(S00_AXI_arvalid),
.S00_AXI_awaddr(S00_AXI_awaddr),
.S00_AXI_awburst(S00_AXI_awburst),
.S00_AXI_awcache(S00_AXI_awcache),
.S00_AXI_awid(S00_AXI_awid),
.S00_AXI_awlen(S00_AXI_awlen),
.S00_AXI_awlock(S00_AXI_awlock),
.S00_AXI_awprot(S00_AXI_awprot),
.S00_AXI_awqos(S00_AXI_awqos),
.S00_AXI_awready(S00_AXI_awready),
.S00_AXI_awregion(S00_AXI_awregion),
.S00_AXI_awsize(S00_AXI_awsize),
.S00_AXI_awvalid(S00_AXI_awvalid),
.S00_AXI_bid(S00_AXI_bid),
.S00_AXI_bready(S00_AXI_bready),
.S00_AXI_bresp(S00_AXI_bresp),
.S00_AXI_bvalid(S00_AXI_bvalid),
.S00_AXI_rdata(S00_AXI_rdata),
.S00_AXI_rid(S00_AXI_rid),
.S00_AXI_rlast(S00_AXI_rlast),
.S00_AXI_rready(S00_AXI_rready),
.S00_AXI_rresp(S00_AXI_rresp),
.S00_AXI_rvalid(S00_AXI_rvalid),
.S00_AXI_wdata(S00_AXI_wdata),
.S00_AXI_wlast(S00_AXI_wlast),
.S00_AXI_wready(S00_AXI_wready),
.S00_AXI_wstrb(S00_AXI_wstrb),
.S00_AXI_wvalid(S00_AXI_wvalid),
.sys_clk_i(sys_clk_i),
.sys_rst(sys_rst));
endmodule
|
// Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
// Date : Mon Mar 24 13:58:19 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub
// /home/keith/Documents/VHDL-lib/top/lab_3/part_1/ip/clk_193MHz/clk_193MHz_stub.v
// Design : clk_193MHz
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module clk_193MHz(clk_100MHz, clk_193MHz, locked)
/* synthesis syn_black_box black_box_pad_pin="clk_100MHz,clk_193MHz,locked" */;
input clk_100MHz;
output clk_193MHz;
output locked;
endmodule
|
// megafunction wizard: %LPM_ADD_SUB%CBX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_add_sub
// ============================================================
// File Name: add32.v
// Megafunction Name(s):
// lpm_add_sub
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
//lpm_add_sub DEVICE_FAMILY=Cyclone LPM_DIRECTION=ADD LPM_WIDTH=8 dataa datab result
//VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ VERSION_END
//synthesis_resources = lut 8
module add32_add_sub_nq7
(
dataa,
datab,
result) /* synthesis synthesis_clearbox=1 */;
input [7:0] dataa;
input [7:0] datab;
output [7:0] result;
wire [7:0] wire_add_sub_cella_combout;
wire [0:0] wire_add_sub_cella_0cout;
wire [0:0] wire_add_sub_cella_1cout;
wire [0:0] wire_add_sub_cella_2cout;
wire [0:0] wire_add_sub_cella_3cout;
wire [0:0] wire_add_sub_cella_4cout;
wire [0:0] wire_add_sub_cella_5cout;
wire [0:0] wire_add_sub_cella_6cout;
wire [7:0] wire_add_sub_cella_dataa;
wire [7:0] wire_add_sub_cella_datab;
stratix_lcell add_sub_cella_0
(
.cin(1'b0),
.combout(wire_add_sub_cella_combout[0:0]),
.cout(wire_add_sub_cella_0cout[0:0]),
.dataa(wire_add_sub_cella_dataa[0:0]),
.datab(wire_add_sub_cella_datab[0:0]));
defparam
add_sub_cella_0.cin_used = "true",
add_sub_cella_0.lut_mask = "96e8",
add_sub_cella_0.operation_mode = "arithmetic",
add_sub_cella_0.sum_lutc_input = "cin",
add_sub_cella_0.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_1
(
.cin(wire_add_sub_cella_0cout[0:0]),
.combout(wire_add_sub_cella_combout[1:1]),
.cout(wire_add_sub_cella_1cout[0:0]),
.dataa(wire_add_sub_cella_dataa[1:1]),
.datab(wire_add_sub_cella_datab[1:1]));
defparam
add_sub_cella_1.cin_used = "true",
add_sub_cella_1.lut_mask = "96e8",
add_sub_cella_1.operation_mode = "arithmetic",
add_sub_cella_1.sum_lutc_input = "cin",
add_sub_cella_1.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_2
(
.cin(wire_add_sub_cella_1cout[0:0]),
.combout(wire_add_sub_cella_combout[2:2]),
.cout(wire_add_sub_cella_2cout[0:0]),
.dataa(wire_add_sub_cella_dataa[2:2]),
.datab(wire_add_sub_cella_datab[2:2]));
defparam
add_sub_cella_2.cin_used = "true",
add_sub_cella_2.lut_mask = "96e8",
add_sub_cella_2.operation_mode = "arithmetic",
add_sub_cella_2.sum_lutc_input = "cin",
add_sub_cella_2.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_3
(
.cin(wire_add_sub_cella_2cout[0:0]),
.combout(wire_add_sub_cella_combout[3:3]),
.cout(wire_add_sub_cella_3cout[0:0]),
.dataa(wire_add_sub_cella_dataa[3:3]),
.datab(wire_add_sub_cella_datab[3:3]));
defparam
add_sub_cella_3.cin_used = "true",
add_sub_cella_3.lut_mask = "96e8",
add_sub_cella_3.operation_mode = "arithmetic",
add_sub_cella_3.sum_lutc_input = "cin",
add_sub_cella_3.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_4
(
.cin(wire_add_sub_cella_3cout[0:0]),
.combout(wire_add_sub_cella_combout[4:4]),
.cout(wire_add_sub_cella_4cout[0:0]),
.dataa(wire_add_sub_cella_dataa[4:4]),
.datab(wire_add_sub_cella_datab[4:4]));
defparam
add_sub_cella_4.cin_used = "true",
add_sub_cella_4.lut_mask = "96e8",
add_sub_cella_4.operation_mode = "arithmetic",
add_sub_cella_4.sum_lutc_input = "cin",
add_sub_cella_4.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_5
(
.cin(wire_add_sub_cella_4cout[0:0]),
.combout(wire_add_sub_cella_combout[5:5]),
.cout(wire_add_sub_cella_5cout[0:0]),
.dataa(wire_add_sub_cella_dataa[5:5]),
.datab(wire_add_sub_cella_datab[5:5]));
defparam
add_sub_cella_5.cin_used = "true",
add_sub_cella_5.lut_mask = "96e8",
add_sub_cella_5.operation_mode = "arithmetic",
add_sub_cella_5.sum_lutc_input = "cin",
add_sub_cella_5.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_6
(
.cin(wire_add_sub_cella_5cout[0:0]),
.combout(wire_add_sub_cella_combout[6:6]),
.cout(wire_add_sub_cella_6cout[0:0]),
.dataa(wire_add_sub_cella_dataa[6:6]),
.datab(wire_add_sub_cella_datab[6:6]));
defparam
add_sub_cella_6.cin_used = "true",
add_sub_cella_6.lut_mask = "96e8",
add_sub_cella_6.operation_mode = "arithmetic",
add_sub_cella_6.sum_lutc_input = "cin",
add_sub_cella_6.lpm_type = "stratix_lcell";
stratix_lcell add_sub_cella_7
(
.cin(wire_add_sub_cella_6cout[0:0]),
.combout(wire_add_sub_cella_combout[7:7]),
.dataa(wire_add_sub_cella_dataa[7:7]),
.datab(wire_add_sub_cella_datab[7:7]));
defparam
add_sub_cella_7.cin_used = "true",
add_sub_cella_7.lut_mask = "9696",
add_sub_cella_7.operation_mode = "normal",
add_sub_cella_7.sum_lutc_input = "cin",
add_sub_cella_7.lpm_type = "stratix_lcell";
assign
wire_add_sub_cella_dataa = dataa,
wire_add_sub_cella_datab = datab;
assign
result = wire_add_sub_cella_combout;
endmodule //add32_add_sub_nq7
//VALID FILE
module add32 (
dataa,
datab,
result)/* synthesis synthesis_clearbox = 1 */;
input [7:0] dataa;
input [7:0] datab;
output [7:0] result;
wire [7:0] sub_wire0;
wire [7:0] result = sub_wire0[7:0];
add32_add_sub_nq7 add32_add_sub_nq7_component (
.dataa (dataa),
.datab (datab),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: nBit NUMERIC "8"
// Retrieval info: PRIVATE: Function NUMERIC "0"
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: Overflow NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "0"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0]
// Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL dataa[7..0]
// Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL datab[7..0]
// Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
// Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0
// Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
/*
* Fetch FSM helper for next state
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_next_or_not (
input [1:0] prefix,
input [7:1] opcode,
input cx_zero,
input zf,
input ext_int,
output next_in_opco,
output next_in_exec
);
// Net declarations
wire exit_z, cmp_sca, exit_rep, valid_ops;
// Assignments
assign cmp_sca = opcode[2] & opcode[1];
assign exit_z = prefix[0] ? /* repz */ (cmp_sca ? ~zf : 1'b0 )
: /* repnz */ (cmp_sca ? zf : 1'b0 );
assign exit_rep = cx_zero | exit_z;
assign valid_ops = (opcode[7:1]==7'b1010_010 // movs
|| opcode[7:1]==7'b1010_011 // cmps
|| opcode[7:1]==7'b1010_101 // stos
|| opcode[7:1]==7'b1010_110 // lods
|| opcode[7:1]==7'b1010_111); // scas
assign next_in_exec = prefix[1] && valid_ops && !exit_rep && !ext_int;
assign next_in_opco = prefix[1] && valid_ops && cx_zero;
endmodule
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_MATLAB_Function_block.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_MATLAB_Function_block
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Sin_Cos/Mark_Extract_Bits/MATLAB Function
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_MATLAB_Function_block
(
u,
y
);
input [17:0] u; // ufix18
output [8:0] y; // ufix9
wire [8:0] y1; // ufix9_E9
//MATLAB Function 'Open_Loop_Control/Sin_Cos/Mark_Extract_Bits/MATLAB Function': '<S37>:1'
// Non-tunable mask parameter
//'<S37>:1:8'
//'<S37>:1:10'
assign y1 = u[17:9];
//'<S37>:1:14'
assign y = y1;
endmodule // controllerHdl_MATLAB_Function_block
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 06/30/2009
This block is used to communicate information back and forth between the SGDMA
and the host. When the response port is not set to streaming then this block
will be used to generate interrupts for the host. The address span of this block
differs depending on whether the enhanced features are enabled. The enhanced
features enables sequence number readback capabilties. The address map is as follows:
Enhanced features off:
Bytes Access Type Description
----- ----------- -----------
0-3 R Status(1)
4-7 R/W Control(2)
8-12 R Descriptor Watermark (write watermark[15:0],read watermark [15:0])
13-15 R Response Watermark
16-31 N/A <Reserved>
Enhanced features on:
Bytes Access Type Description
----- ----------- -----------
0-3 R Status(1)
4-7 R/W Control(2)
8-12 R Descriptor Watermark (write watermark[15:0],read watermark [15:0])
13-15 R Response Watermark
16-20 R Sequence Number (write sequence[15:0],read sequence[15:0])
21-31 N/A <Reserved>
(1) Writing to the interrupt bit of the status register clears the interrupt bit (when applicable)
(2) Writing to the software reset bit will clear the entire register (as well as all the registers for the entire SGDMA)
Status Register:
Bits Description
---- -----------
0 Busy
1 Descriptor Buffer Empty
2 Descriptor Buffer Full
3 Response Buffer Empty
4 Response Buffer Full
5 Stop State
6 Reset State
7 Stopped on Error
8 Stopped on Early Termination
9 IRQ
10-15 <Reserved>
15-31 Done count (JSF: Added 06/13/2011)
Control Register:
Bits Description
---- -----------
0 Stop (will also be set if a stop on error/early termination condition occurs)
1 Software Reset
2 Stop on Error
3 Stop on Early Termination
4 Global Interrupt Enable Mask
5 Stop descriptors (stops the dispatcher from issuing more read/write commands)
6-31 <Reserved>
Author: JCJB
Date: 08/18/2010
1.0 - Initial release
1.1 - Removed delayed reset, added set and hold sw_reset
1.2 - Updated the sw_reset register to be set when control[1] is set instead of one cycle after.
This will prevent the read or write masters from starting back up when reset while in the stop state.
1.3 - Added the stop dispatcher bit (5) to the control register
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module csr_block (
clk,
reset,
csr_writedata,
csr_write,
csr_byteenable,
csr_readdata,
csr_read,
csr_address,
csr_irq,
done_strobe,
busy,
descriptor_buffer_empty,
descriptor_buffer_full,
stop_state,
stopped_on_error,
stopped_on_early_termination,
reset_stalled,
stop,
sw_reset,
stop_on_error,
stop_on_early_termination,
stop_descriptors,
sequence_number,
descriptor_watermark,
response_watermark,
response_buffer_empty,
response_buffer_full,
transfer_complete_IRQ_mask,
error_IRQ_mask,
early_termination_IRQ_mask,
error,
early_termination
);
parameter ADDRESS_WIDTH = 3;
localparam CONTROL_REGISTER_ADDRESS = 3'b001;
input clk;
input reset;
input [31:0] csr_writedata;
input csr_write;
input [3:0] csr_byteenable;
output wire [31:0] csr_readdata;
input csr_read;
input [ADDRESS_WIDTH-1:0] csr_address;
output wire csr_irq;
input done_strobe;
input busy;
input descriptor_buffer_empty;
input descriptor_buffer_full;
input stop_state; // when the DMA runs into some error condition and you have enabled the stop on error (or when the stop control bit is written to)
input reset_stalled; // the read or write master could be in the middle of a transfer/burst so it might take a while to flush the buffers
output wire stop;
output reg stopped_on_error;
output reg stopped_on_early_termination;
output reg sw_reset;
output wire stop_on_error;
output wire stop_on_early_termination;
output wire stop_descriptors;
input [31:0] sequence_number;
input [31:0] descriptor_watermark;
input [15:0] response_watermark;
input response_buffer_empty;
input response_buffer_full;
input transfer_complete_IRQ_mask;
input [7:0] error_IRQ_mask;
input early_termination_IRQ_mask;
input [7:0] error;
input early_termination;
/* Internal wires and registers */
wire [31:0] status;
reg [31:0] control;
reg [31:0] readdata;
reg [31:0] readdata_d1;
reg irq; // writing to the status register clears the irq bit
wire set_irq;
wire clear_irq;
reg [15:0] irq_count; // writing to bit 0 clears the counter
wire clear_irq_count;
wire incr_irq_count;
wire set_stopped_on_error;
wire set_stopped_on_early_termination;
wire set_stop;
wire clear_stop;
wire global_interrupt_enable;
wire sw_reset_strobe; // this strobe will be one cycle earlier than sw_reset
wire set_sw_reset;
wire clear_sw_reset;
/********************************************** Registers ***************************************************/
// read latency is 1 cycle
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
readdata_d1 <= 0;
end
else if (csr_read == 1)
begin
readdata_d1 <= readdata;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
control[31:1] <= 0;
end
else
begin
if (sw_reset_strobe == 1) // reset strobe is a strobe due to this sync reset
begin
control[31:1] <= 0;
end
else
begin
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1))
begin
control[7:1] <= csr_writedata[7:1]; // stop bit will be handled seperately since it can be set by the csr slave port access or the SGDMA hitting an error condition
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[1] == 1))
begin
control[15:8] <= csr_writedata[15:8];
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[2] == 1))
begin
control[23:16] <= csr_writedata[23:16];
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[3] == 1))
begin
control[31:24] <= csr_writedata[31:24];
end
end
end
end
// control bit 0 (stop) is set by different sources so handling it seperately
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
control[0] <= 0;
end
else
begin
if (sw_reset_strobe == 1)
begin
control[0] <= 0;
end
else
begin
case ({set_stop, clear_stop})
2'b00: control[0] <= control[0];
2'b01: control[0] <= 1'b0;
2'b10: control[0] <= 1'b1;
2'b11: control[0] <= 1'b1; // setting will win, this case happens control[0] is being set to 0 (resume) at the same time an error/early termination stop condition occurs
endcase
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
sw_reset <= 0;
end
else
begin
if (set_sw_reset == 1)
begin
sw_reset <= 1;
end
else if (clear_sw_reset == 1)
begin
sw_reset <= 0;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped_on_error <= 0;
end
else
begin
case ({set_stopped_on_error, clear_stop})
2'b00: stopped_on_error <= stopped_on_error;
2'b01: stopped_on_error <= 1'b0;
2'b10: stopped_on_error <= 1'b1;
2'b11: stopped_on_error <= 1'b0;
endcase
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped_on_early_termination <= 0;
end
else
begin
case ({set_stopped_on_early_termination, clear_stop})
2'b00: stopped_on_early_termination <= stopped_on_early_termination;
2'b01: stopped_on_early_termination <= 1'b0;
2'b10: stopped_on_early_termination <= 1'b1;
2'b11: stopped_on_early_termination <= 1'b0;
endcase
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
irq <= 0;
end
else
begin
if (sw_reset_strobe == 1)
begin
irq <= 0;
end
else
begin
case ({clear_irq, set_irq})
2'b00: irq <= irq;
2'b01: irq <= 1'b1;
2'b10: irq <= 1'b0;
2'b11: irq <= 1'b1; // setting will win over a clear
endcase
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
irq_count <= {16{1'b0}};
end
else
begin
if (sw_reset_strobe == 1)
begin
irq_count <= {16{1'b0}};
end
else
begin
case ({clear_irq_count, incr_irq_count})
2'b00: irq_count <= irq_count;
2'b01: irq_count <= irq_count + 1;
2'b10: irq_count <= {16{1'b0}};
2'b11: irq_count <= {{15{1'b0}}, 1'b1};
endcase
end
end
end
/******************************************** End Registers *************************************************/
/**************************************** Combinational Signals *********************************************/
generate
if (ADDRESS_WIDTH == 3)
begin
always @ (csr_address or status or control or descriptor_watermark or response_watermark or sequence_number)
begin
case (csr_address)
3'b000: readdata = status;
3'b001: readdata = control;
3'b010: readdata = descriptor_watermark;
3'b011: readdata = response_watermark;
default: readdata = sequence_number; // all other addresses will decode to the sequence number
endcase
end
end
else
begin
always @ (csr_address or status or control or descriptor_watermark or response_watermark)
begin
case (csr_address)
3'b000: readdata = status;
3'b001: readdata = control;
3'b010: readdata = descriptor_watermark;
default: readdata = response_watermark; // all other addresses will decode to the response watermark
endcase
end
end
endgenerate
assign clear_irq = (csr_address == 0) & (csr_write == 1) & (csr_byteenable[1] == 1) & (csr_writedata[9] == 1); // this is the IRQ bit
assign set_irq = (global_interrupt_enable == 1) & (done_strobe == 1) & // transfer ended and interrupts are enabled
((transfer_complete_IRQ_mask == 1) | // transfer ended and the transfer complete IRQ is enabled
((error & error_IRQ_mask) != 0) | // transfer ended with an error and this IRQ is enabled
((early_termination & early_termination_IRQ_mask) == 1)); // transfer ended early due to early termination and this IRQ is enabled
assign csr_irq = irq;
// Done count
assign incr_irq_count = set_irq; // Done count just counts the number of interrupts since the last reset
assign clear_irq_count = (csr_address == 0) & (csr_write == 1) & (csr_byteenable[2] == 1) & (csr_writedata[16] == 1); // the LSB irq_count bit
assign clear_stop = (csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[0] == 0);
assign set_stopped_on_error = (done_strobe == 1) & (stop_on_error == 1) & (error != 0); // when clear_stop is set then the stopped_on_error register will be cleared
assign set_stopped_on_early_termination = (done_strobe == 1) & (stop_on_early_termination == 1) & (early_termination == 1); // when clear_stop is set then the stopped_on_early_termination register will be cleared
assign set_stop = ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[0] == 1)) | // host set the stop bit
(set_stopped_on_error == 1) | // SGDMA setup to stop when an error occurs from the write master
(set_stopped_on_early_termination == 1) ; // SGDMA setup to stop when the write master overflows
assign stop = control[0];
assign set_sw_reset = (csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[1] == 1);
assign clear_sw_reset = (sw_reset == 1) & (reset_stalled == 0);
assign sw_reset_strobe = control[1];
assign stop_on_error = control[2];
assign stop_on_early_termination = control[3];
assign global_interrupt_enable = control[4];
assign stop_descriptors = control[5];
assign csr_readdata = readdata_d1;
assign status = {irq_count, {6{1'b0}}, irq, stopped_on_early_termination, stopped_on_error, sw_reset, stop_state, response_buffer_full, response_buffer_empty, descriptor_buffer_full, descriptor_buffer_empty, busy}; // writing to the lower byte of the status register clears the irq bit
/**************************************** Combinational Signals *********************************************/
endmodule
|
/*
* Wishbone asynchronous bridge
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module wb_abrg (
input sys_rst,
// Wishbone slave interface
input wbs_clk_i,
input [19:1] wbs_adr_i,
input [15:0] wbs_dat_i,
output reg [15:0] wbs_dat_o,
input [ 1:0] wbs_sel_i,
input wbs_tga_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
output wbs_ack_o,
// Wishbone master interface
input wbm_clk_i,
output reg [19:1] wbm_adr_o,
output reg [15:0] wbm_dat_o,
input [15:0] wbm_dat_i,
output reg [ 1:0] wbm_sel_o,
output reg wbm_tga_o,
output wbm_stb_o,
output wbm_cyc_o,
output reg wbm_we_o,
input wbm_ack_i
);
// Registers and nets
wire wbs_stb;
wire init_tr;
reg wbm_stb;
reg [2:0] sync_stb;
reg [2:0] sync_ack;
reg ft_stb;
reg ft_ack;
reg stb_r;
reg ack_r;
reg [19:1] wbm_adr_o_r;
reg [15:0] wbm_dat_o_r;
reg [ 1:0] wbm_sel_o_r;
reg wbm_tga_o_r;
reg wbm_we_o_r;
reg [15:0] wbs_dat_o_r;
reg [15:0] wbm_dat_i_r;
// Continous assignments
assign wbs_stb = wbs_stb_i & wbs_cyc_i;
// recreate the flag from the level change
assign wbs_ack_o = (sync_ack[2] ^ sync_ack[1]);
assign wbm_stb_o = wbm_stb;
assign wbm_cyc_o = wbm_stb;
/*
* A new wishbone transaction is issued:
* . by changing stb from 0 to 1
* . by continue asserting stb after ack is received
*/
assign init_tr = ~stb_r & wbs_stb | ack_r & ~wbs_ack_o & wbs_stb;
// Behaviour
// wbm_stb
always @(posedge wbm_clk_i)
wbm_stb <= sys_rst ? 1'b0
: (wbm_stb ? ~wbm_ack_i : sync_stb[2] ^ sync_stb[1]);
// old stb and ack state
always @(posedge wbs_clk_i) stb_r <= wbs_stb;
always @(posedge wbs_clk_i) ack_r <= wbs_ack_o;
always @(posedge wbs_clk_i)
ft_stb <= sys_rst ? 1'b0 : (init_tr ? ~ft_stb : ft_stb);
// synchronize the last level change
always @(posedge wbm_clk_i)
sync_stb <= sys_rst ? 3'h0 : {sync_stb[1:0], ft_stb};
// this changes level when a flag is seen
always @(posedge wbm_clk_i)
ft_ack <= sys_rst ? 1'b0 : (wbm_ack_i ? ~ft_ack : ft_ack);
// which can then be synched to wbs_clk_i
always @(posedge wbs_clk_i)
sync_ack <= sys_rst ? 3'h0 : {sync_ack[1:0], ft_ack};
// rest of the wishbone signals
always @(posedge wbm_clk_i)
{wbm_adr_o, wbm_adr_o_r} <= {wbm_adr_o_r, wbs_adr_i};
always @(posedge wbm_clk_i)
{wbm_dat_o, wbm_dat_o_r} <= {wbm_dat_o_r, wbs_dat_i};
always @(posedge wbm_clk_i)
{wbm_sel_o, wbm_sel_o_r} <= {wbm_sel_o_r, wbs_sel_i};
always @(posedge wbm_clk_i)
{wbm_we_o, wbm_we_o_r} <= {wbm_we_o_r, wbs_we_i};
always @(posedge wbm_clk_i)
{wbm_tga_o, wbm_tga_o_r} <= {wbm_tga_o_r, wbs_tga_i};
/*
* Register input coming from the slave as that can change
* after the ack is received
*/
always @(posedge wbm_clk_i)
wbm_dat_i_r <= wbm_ack_i ? wbm_dat_i : wbm_dat_i_r;
always @(posedge wbs_clk_i)
{wbs_dat_o, wbs_dat_o_r} <= {wbs_dat_o_r, wbm_dat_i_r};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXBN_1_V
`define SKY130_FD_SC_HS__DLXBN_1_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog wrapper for dlxbn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlxbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlxbn_1 (
Q ,
Q_N ,
D ,
GATE_N,
VPWR ,
VGND
);
output Q ;
output Q_N ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__dlxbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlxbn_1 (
Q ,
Q_N ,
D ,
GATE_N
);
output Q ;
output Q_N ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dlxbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXBN_1_V
|
// MBT 4/1/2014
//
// 2 read-port, 1 write-port ram
//
// reads are asynchronous
//
`define bsg_mem_2r1w_macro(words,bits) \
if (els_p == words && width_p == bits) \
begin: macro \
wire [els_p-1:0] wa_one_hot = (w_v_i << w_addr_i); \
wire [els_p-1:0] ra_one_hot0 = (r0_v_i << r0_addr_i); \
wire [els_p-1:0] ra_one_hot1 = (r1_v_i << r1_addr_i); \
\
bsg_rp_tsmc_250_rf_w``words``_b``bits``_2r1w w``words``_b``bits \
( .clock_i(w_clk_i) \
,.data_i(w_data_i) \
,.write_sel_one_hot_i(wa_one_hot) \
,.read_sel_one_hot_i ({ra_one_hot1,ra_one_hot0}) \
,.data_o({r1_data_o,r0_data_o}) \
); \
end
module bsg_mem_2r1w #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=$clog2(els_p)
)
(input w_clk_i
, input w_reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [width_p-1:0] w_data_i
, input r0_v_i
, input [addr_width_lp-1:0] r0_addr_i
, output logic [width_p-1:0] r0_data_o
, input r1_v_i
, input [addr_width_lp-1:0] r1_addr_i
, output logic [width_p-1:0] r1_data_o
);
`bsg_mem_2r1w_macro(32,32)
else
begin: notmacro
bsg_mem_2r1w_synth
#(.width_p(width_p)
,.els_p(els_p)
,.read_write_same_addr_p(read_write_same_addr_p)
) synth
(.*);
end
// synopsys translate_off
always_ff @(posedge w_clk_i)
if (w_v_i)
begin
assert (w_addr_i < els_p)
else $error("Invalid address %x to %m of size %x\n", w_addr_i, els_p);
assert (~(r0_addr_i == w_addr_i && w_v_i && r0_v_i && !read_write_same_addr_p))
else $error("%m: Attempt to read and write same address");
assert (~(r1_addr_i == w_addr_i && w_v_i && r1_v_i && !read_write_same_addr_p))
else $error("%m: Attempt to read and write same address");
end
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d (%m)",width_p,els_p,read_write_same_addr_p);
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_2r1w)
|
//===----------------------------------------------------------------------===//
//
// Parameterized FIFO with input and output registers and ACL pipeline
// protocol ports. This "FIFO" stores no data and only hands out a sequence of
// numbers from 0..DEPTH-1 (tokens) in round robin fashion.
//
//===----------------------------------------------------------------------===//
module acl_token_fifo_counter
#(
parameter integer DEPTH = 32, // >0
parameter integer STRICT_DEPTH = 1, // 0|1
parameter integer ALLOW_FULL_WRITE = 0 // 0|1
)
(
clock,
resetn,
data_out, // the width of this signal is set by this module, it is the
// responsibility of the top module to make sure the signal
// widths match across this interface.
valid_in,
valid_out,
stall_in,
stall_out,
empty,
full
);
// This fifo is based on acl_valid_fifo
// However, there are 2 differences:
// 1. The fifo is intialized as full
// 2. We keep another counter to serve as the actual token
// STRICT_DEPTH increases FIFO depth to a power of 2 + 1 depth.
// No data, so just build a counter to count the number of valids stored in this "FIFO".
//
// The counter is constructed to count up to a MINIMUM value of DEPTH entries.
// * Logical range of the counter C0 is [0, DEPTH].
// * empty = (C0 <= 0)
// * full = (C0 >= DEPTH)
//
// To have efficient detection of the empty condition (C0 == 0), the range is offset
// by -1 so that a negative number indicates empty.
// * Logical range of the counter C1 is [-1, DEPTH-1].
// * empty = (C1 < 0)
// * full = (C1 >= DEPTH-1)
// The size of counter C1 is $clog2((DEPTH-1) + 1) + 1 => $clog2(DEPTH) + 1.
//
// To have efficient detection of the full condition (C1 >= DEPTH-1), change the
// full condition to C1 == 2^$clog2(DEPTH-1), which is DEPTH-1 rounded up
// to the next power of 2. This is only done if STRICT_DEPTH == 0, otherwise
// the full condition is comparison vs. DEPTH-1.
// * Logical range of the counter C2 is [-1, 2^$clog2(DEPTH-1)]
// * empty = (C2 < 0)
// * full = (C2 == 2^$clog2(DEPTH - 1))
// The size of counter C2 is $clog2(DEPTH-1) + 2.
// * empty = MSB
// * full = ~[MSB] & [MSB-1]
localparam COUNTER_WIDTH = (STRICT_DEPTH == 0) ?
((DEPTH > 1 ? $clog2(DEPTH-1) : 0) + 2) :
($clog2(DEPTH) + 1);
input clock;
input resetn;
output [COUNTER_WIDTH-1:0] data_out;
input valid_in;
output valid_out;
input stall_in;
output stall_out;
output empty;
output full;
logic [COUNTER_WIDTH - 1:0] valid_counter /* synthesis maxfan=1 dont_merge */;
logic incr, decr;
// The logical range for the token is [0,REAL_DEPTH-1], where REAL_DEPTH
// is the actual depth of the fifo taking STRICT_DEPTH into account
// This counter is 1-bit less wide than valid_counter because it is
// unsigned
logic [COUNTER_WIDTH - 2:0] token;
logic token_max;
assign data_out = token;
assign token_max = (STRICT_DEPTH == 0) ?
(~token[$bits(token) - 1] & token[$bits(token) - 2]) :
(token == DEPTH - 1);
assign empty = valid_counter[$bits(valid_counter) - 1];
assign full = (STRICT_DEPTH == 0) ?
(~valid_counter[$bits(valid_counter) - 1] & valid_counter[$bits(valid_counter) - 2]) :
(valid_counter == DEPTH - 1);
assign incr = valid_in & ~stall_out; // push
assign decr = valid_out & ~stall_in; // pop
assign valid_out = ~empty;
assign stall_out = ALLOW_FULL_WRITE ? (full & stall_in) : full;
always @( posedge clock or negedge resetn )
if( !resetn )
begin
valid_counter <= (STRICT_DEPTH == 0) ? (2^$clog2(DEPTH-1)) : DEPTH - 1; // full
token <= 0;
end
else
begin
valid_counter <= valid_counter + incr - decr;
if (decr) // increment token, if popping
token <= token_max ? 0 : token+1;
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: cmd_gen.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:19 $
// \ \ / \ Date Created: Oct 21 2008
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This module genreates different type of commands, address,
// burst_length to mcb_flow_control module.
//Reference:
//Revision History:
// Nov14 2008. Added constraints for generating PRBS_BL when
// generated address is too close to end of address space.
// The BL will be force to 1 to avoid across other port's space.
// April 2 2009 Fixed Sequential Address Circuit to avoide generate any address
// beyond the allowed address range.
// Oct 22 2009 Fixed BRAM interface.
// Fixed run_traffic stop and go problem.
// Merged V6 and SP6 specific requirements.
// Modified syntax for VHDL Formality comparison.
// Dec 1 2011 Fixed Simple Data mode address generation problem.
// Jan 4 2012 Added percent write instruction mode ( mode == 4) to
// let user specify percentage of write commands out of mix
// write/read commands.
//*****************************************************************************
`timescale 1ps/1ps
`define RD 3'b001;
`define RDP 3'b011;
`define WR 3'b000;
`define WRP 3'b010;
`define REFRESH 3'b100;
(* use_dsp48 = "no" *)
module mig_7series_v1_9_cmd_gen #
(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6",
parameter MEM_TYPE = "DDR3",
parameter BL_WIDTH = 6, // User Commands Burst length that send over User Interface.
parameter MEM_BURST_LEN = 8,
parameter nCK_PER_CLK = 4,
parameter PORT_MODE = "BI_MODE",
parameter NUM_DQ_PINS = 8,
parameter DATA_PATTERN = "DGEN_ALL", // "DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter CMD_PATTERN = "CGEN_ALL", // "CGEN_RPBS","CGEN_FIXED", "CGEN_BRAM", "CGEN_SEQUENTIAL", "CGEN_ALL",
parameter ADDR_WIDTH = 30,
parameter BANK_WIDTH = 3,
parameter DWIDTH = 32,
parameter PIPE_STAGES = 0,
parameter MEM_COL_WIDTH = 10, // memory column width
parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000,
parameter PRBS_SADDR_MASK_POS = 32'h00002000,
parameter PRBS_EADDR = 32'h00002000,
parameter PRBS_SADDR = 32'h00002000
)
(
input clk_i,
input [9:0] rst_i,
input run_traffic_i,
input [3:0] vio_instr_mode_value,
input [3:0] vio_percent_write,
input single_operation,
// runtime parameter
input mem_pattern_init_done_i,
input [31:0] start_addr_i, // define the start of address
input [31:0] end_addr_i,
input [31:0] cmd_seed_i, // same seed apply to all addr_prbs_gen, bl_prbs_gen, instr_prbs_gen
input load_seed_i, //
// upper layer inputs to determine the command bus and data pattern
// internal traffic generator initialize the memory with
input [2:0] addr_mode_i, // "00" = bram; takes the address from bram output
// "01" = fixed address from the fixed_addr input
// "10" = psuedo ramdom pattern; generated from internal 64 bit LFSR
// "11" = sequential
input [3:0] data_mode_i, // 4'b0010:address as data
// 4'b0011:DGEN_HAMMER
// 4'b0100:DGEN_NEIGHBOUR
// 4'b0101:DGEN_WALKING1
// 4'b0110:DGEN_WALKING0
// 4'b0111:PRBS_DATA
// for each instr_mode, traffic gen fill up with a predetermined pattern before starting the instr_pattern that defined
// in the instr_mode input. The runtime mode will be automatically loaded inside when it is in
input [3:0] instr_mode_i, // "0000" = bram; takes instruction from bram output
// "0001" = fixed instr from fixed instr input
// "0010" = R/W
// "0011" = RP/WP
// "0100" = R/RP/W/WP
// "0101" = R/RP/W/WP/REF
// "0110" = PRBS
input [1:0] bl_mode_i, // "00" = bram; takes the burst length from bram output
// "01" = fixed , takes the burst length from the fixed_bl input
// "10" = psuedo ramdom pattern; generated from internal 16 bit LFSR
input mode_load_i,
// fixed pattern inputs interface
input [BL_WIDTH - 1:0] fixed_bl_i, // range from 1 to 64
input [2:0] fixed_instr_i, //RD 3'b001
//RDP 3'b011
//WR 3'b000
//WRP 3'b010
//REFRESH 3'b100
input [31:0] fixed_addr_i, // only upper 30 bits will be used
// BRAM FIFO input
input [31:0] bram_addr_i, //
input [2:0] bram_instr_i,
input [5:0] bram_bl_i,
input bram_valid_i,
output bram_rdy_o,
input reading_rd_data_i,
// mcb_flow_control interface
input rdy_i,
output [31:0] addr_o, // generated address
output [2:0] instr_o, // generated instruction
output [BL_WIDTH - 1:0] bl_o, // generated instruction
// output reg [31:0] m_addr_o,
output cmd_o_vld , // valid commands when asserted
output reg mem_init_done_o
);
localparam PRBS_ADDR_WIDTH = 32;
localparam INSTR_PRBS_WIDTH = 16;
localparam BL_PRBS_WIDTH = 16;
localparam BRAM_DATAL_MODE = 4'b0000;
localparam FIXED_DATA_MODE = 4'b0001;
localparam ADDR_DATA_MODE = 4'b0010;
localparam HAMMER_DATA_MODE = 4'b0011;
localparam NEIGHBOR_DATA_MODE = 4'b0100;
localparam WALKING1_DATA_MODE = 4'b0101;
localparam WALKING0_DATA_MODE = 4'b0110;
localparam PRBS_DATA_MODE = 4'b0111;
localparam DWIDTH_BY_8 = (DWIDTH >> 3);
localparam LOGB2_MEM_BURST_INT = (MEM_BURST_LEN == 8)? 3:2;
reg [BL_WIDTH+DWIDTH_BY_8-1:0] bl_x_DWIDTH_BY_8;
reg [BL_WIDTH+2:0] INC_COUNTS /* synthesis syn_dspstyle = logic */ ;
reg [2:0] addr_mode_reg;
reg [1:0] bl_mode_reg;
reg [31:0] addr_counts /* synthesis syn_dspstyle = logic */ ;
reg [31:0] addr_counts_next_r;
reg [BANK_WIDTH-1:0] bank_counts;
wire [14:0] prbs_bl;
reg [2:0] instr_out;
wire [14:0] prbs_instr_a;
wire [14:0] prbs_instr_b;
reg [BL_WIDTH - 1:0] prbs_brlen;
wire [31:0] prbs_addr;
wire [31:0] seq_addr;
wire [31:0] fixed_addr;
reg [31:0] addr_out ;
reg [BL_WIDTH - 1:0] bl_out;
reg [BL_WIDTH + DWIDTH/8 - 1:0]cal_blout;
reg [BL_WIDTH - 1:0] bl_out_reg;
reg mode_load_d1;
reg mode_load_d2;
reg mode_load_pulse;
wire [BL_WIDTH+35:0] pipe_data_o;
wire cmd_clk_en;
wire pipe_out_vld;
reg force_bl1;
reg bl_out_clk_en;
reg [BL_WIDTH+35:0] pipe_data_in;
reg instr_vld;
reg bl_out_vld;
reg gen_addr_larger ;
reg gen_bl_larger;
reg [7:0] buf_avail_r;
reg [6:0] rd_data_received_counts;
reg [6:0] rd_data_counts_asked;
reg instr_vld_dly1;
reg first_load_pulse;
reg mem_init_done;
reg refresh_cmd_en ;
reg [9:0] refresh_timer;
reg refresh_prbs;
reg cmd_vld;
reg run_traffic_r;
reg cmd_clk_en_r;
reg finish_init;
reg mem_init_done_r;
reg first_mode_load_pulse_r1;
reg first_mode_load_pulse_set;
reg mode_load_pulse_r1;
reg n_gen_write_only;
reg [9:0]force_rd_counts;
reg force_rd;
reg bl_64;
reg force_wrcmd_gen;
reg toggle_rw;
reg [3:0] write_percent_cnt;
always @ (posedge clk_i)
if (rst_i[0])
mem_init_done_o <= #TCQ 1'b0;
else if (cmd_clk_en_r)
mem_init_done_o <= #TCQ mem_init_done_r;
always @ (posedge clk_i)
begin
run_traffic_r <= #TCQ run_traffic_i;
end
// commands go through pipeline inserters
assign addr_o = pipe_data_o[31:0];
assign instr_o = pipe_data_o[34:32];
assign bl_o = pipe_data_o[(BL_WIDTH - 1 + 35):35];
// most significant bit
assign cmd_o_vld = pipe_data_o[BL_WIDTH + 35] & run_traffic_r;
assign pipe_out_vld = pipe_data_o[BL_WIDTH + 35] & run_traffic_r;
assign pipe_data_o = pipe_data_in;
always @(posedge clk_i) begin
instr_vld <= #TCQ (cmd_clk_en | (mode_load_pulse & first_load_pulse));
bl_out_clk_en <= #TCQ (cmd_clk_en | (mode_load_pulse & first_load_pulse));
bl_out_vld <= #TCQ bl_out_clk_en;
end
always @ (posedge clk_i) begin
if (rst_i[0] || single_operation)
first_load_pulse <= #TCQ 1'b1;
else if (mode_load_pulse)
first_load_pulse <= #TCQ 1'b0;
else
first_load_pulse <= #TCQ first_load_pulse;
end
always @(posedge clk_i) begin
if (CMD_PATTERN == "CGEN_BRAM")
cmd_vld <= #TCQ (cmd_clk_en );
else //if (CMD_PATTERN != "CGEN_BRAM")
cmd_vld <= #TCQ (cmd_clk_en | (mode_load_pulse & first_load_pulse ));
end
assign cmd_clk_en = ( rdy_i & pipe_out_vld & run_traffic_i || mode_load_pulse && (CMD_PATTERN == "CGEN_BRAM"));
integer i;
always @ (posedge clk_i)
if (rst_i[1])
bl_64 <= 1'b0;
else if (data_mode_i == 7 || data_mode_i == 8 || data_mode_i == 9)
bl_64 <= 1'b1;
else
bl_64 <= 1'b0;
always @ (posedge clk_i) begin
if (rst_i[1])
if (vio_instr_mode_value == 4'h7)
pipe_data_in[31:0] <= #TCQ fixed_addr_i;
else
pipe_data_in[31:0] <= #TCQ start_addr_i;
else if (instr_vld)
// In order to simplify all different test pattern, the V6 generated
// seed address from cmd_gen are aligned to burst length. The PRBS
// burst length for write always 64 else it will break.
// if (MEM_BURST_LEN == 8)
if (data_mode_i == 5 || data_mode_i == 6)
// for walking 1's / walking 0's pattern, the least 8 bits starting address
// has to be all zero. This is to force the DQ pattern of each starting burst
// starts from DQ0.
if (FAMILY == "VIRTEX6")
pipe_data_in[31:0] <= #TCQ {addr_out[31:6], 6'h00};
else
pipe_data_in[31:0] <= #TCQ {addr_out[31:6], 6'h00}; // DWIDTH = 64
else if (data_mode_i == 4)
// pipe_data_in[31:0] <= #TCQ {addr_out[31:3], 3'b000};
pipe_data_in[31:0] <= #TCQ {addr_out[31:6], 6'b000};
else if (bl_64)
// nCK_PER_CLK = 4 && PRBS Length = 8
//force the least 11 bits starting address is always zero to align
// PRBS sequence.
if (nCK_PER_CLK == 4)
if (FAMILY == "VIRTEX6")
pipe_data_in[31:0] <= #TCQ {addr_out[31:11], 11'h000};
else
pipe_data_in[31:0] <= #TCQ {addr_out[31:9], 9'h000};
else
if (FAMILY == "VIRTEX6")
pipe_data_in[31:0] <= #TCQ {addr_out[31:10], 10'h000};
else
pipe_data_in[31:0] <= #TCQ {addr_out[31:9], 9'h000};
else if (gen_addr_larger && mem_init_done)// && (addr_mode_reg == 3'b100 || addr_mode_reg == 3'b010))
pipe_data_in[31:0] <= #TCQ {end_addr_i[31:8],8'h0};
else
pipe_data_in[31:0] <= #TCQ {addr_out[31:2], 2'b00};
// else
// pipe_data_in[31:0] <= #TCQ {addr_out[31:2],2'b00000};
end
//end endgenerate
always @ (posedge clk_i) begin
if (rst_i[0])
force_wrcmd_gen <= #TCQ 1'b0;
else if (buf_avail_r == 63)
force_wrcmd_gen <= #TCQ 1'b0;
else if (instr_vld_dly1 && pipe_data_in[32]== 1 && pipe_data_in[41:35] > 16)
force_wrcmd_gen <= #TCQ 1'b1;
end
reg [3:0]instr_mode_reg;
always @ (posedge clk_i)
begin
instr_mode_reg <= #TCQ instr_mode_i;
end
always @ (posedge clk_i)
begin
if (rst_i[2]) begin
pipe_data_in[40:32] <= #TCQ 'b0;
end
else if (instr_vld) begin
if (instr_mode_reg == 0) begin
pipe_data_in[34:32] <= #TCQ instr_out;
end
else if (instr_out[2]) begin
pipe_data_in[34:32] <= #TCQ 3'b100;
end
//
else if ( FAMILY == "SPARTAN6" && PORT_MODE == "RD_MODE")
begin
pipe_data_in[34:32] <= #TCQ {instr_out[2:1],1'b1};
end
else if ((force_wrcmd_gen || buf_avail_r <= 15) && FAMILY == "SPARTAN6" && PORT_MODE != "RD_MODE")
begin
pipe_data_in[34:32] <= #TCQ {instr_out[2],2'b00};
end
else begin
pipe_data_in[34:32] <= #TCQ instr_out;
end
//********* condition the generated bl value except if TG is programmed for BRAM interface'
// if the generated address is close to end address range, the bl_out will be altered to 1.
if (data_mode_i == 7 )
pipe_data_in[BL_WIDTH-1+35:35] <= #TCQ bl_out;
else if (data_mode_i == 4 )
pipe_data_in[BL_WIDTH-1+35:35] <= #TCQ 10'd32;
else
if (gen_bl_larger && mem_pattern_init_done_i) // this condition is needed
pipe_data_in[BL_WIDTH-1+35:35] <= #TCQ 10'd8;
else if (force_bl1 && mem_pattern_init_done_i)
pipe_data_in[BL_WIDTH-1+35:35] <= #TCQ 10'd2; // for V6
else
pipe_data_in[BL_WIDTH-1+35:35] <= #TCQ bl_out; // 8:2' 4:4
end //else instr_vld
end // always
reg COut;
always @ (posedge clk_i)
begin
if (rst_i[2])
pipe_data_in[BL_WIDTH + 35] <= #TCQ 'b0;
else if (cmd_vld)
pipe_data_in[BL_WIDTH + 35] <= #TCQ instr_vld;//instr_vld;
else if (rdy_i && pipe_out_vld)
pipe_data_in[BL_WIDTH + 35] <= #TCQ 1'b0;
end
always @ (posedge clk_i)
instr_vld_dly1 <= #TCQ instr_vld;
reg COutA;
always @ (posedge clk_i) begin
if (rst_i[0]) begin
rd_data_counts_asked <= #TCQ 'b0;
end else if (instr_vld_dly1 && pipe_data_in[32]== 1) begin
if (pipe_data_in[(BL_WIDTH +35):35] == 0)
{COutA,rd_data_counts_asked} <= #TCQ rd_data_counts_asked + (10'd64) ;
else
{COutA,rd_data_counts_asked} <= #TCQ rd_data_counts_asked + (pipe_data_in[41:35]) ;
end
end
always @ (posedge clk_i) begin
if (rst_i[0]) begin
rd_data_received_counts <= #TCQ 'b0;
end else if(reading_rd_data_i) begin
rd_data_received_counts <= #TCQ rd_data_received_counts + 1'b1;
end
end
reg COut_d;
always @ (posedge clk_i)
if (FAMILY == "SPARTAN6")
{COut_d, buf_avail_r} <= #TCQ ( rd_data_received_counts[6:0] - rd_data_counts_asked[6:0] + 7'd64);
else // Virtex 6 MC has no need to generate such constraints .
buf_avail_r <= #TCQ 8'd64;
localparam BRAM_ADDR = 2'b00;
localparam FIXED_ADDR = 2'b01;
localparam PRBS_ADDR = 2'b10;
localparam SEQUENTIAL_ADDR = 2'b11;
// registered the mode settings
always @ (posedge clk_i) begin
if (rst_i[3])
if (CMD_PATTERN == "CGEN_BRAM")
addr_mode_reg <= #TCQ 3'b000;
else
addr_mode_reg <= #TCQ 3'b011;
else if (mode_load_pulse)
addr_mode_reg <= #TCQ addr_mode_i;
end
always @ (posedge clk_i) begin
if (mode_load_pulse) begin
bl_mode_reg <= #TCQ bl_mode_i ;
end
// mode_load_d1 <= #TCQ mode_load_i;
//
// mode_load_d2 <= #TCQ mode_load_d1;
end
always @ (posedge clk_i)
begin
if (rst_i[0])
begin
mode_load_d1 <= #TCQ 'b0;
mode_load_d2 <= #TCQ 'b0;
end
else
begin
mode_load_d1 <= #TCQ mode_load_i ;
mode_load_d2 <= #TCQ mode_load_d1 ;
end
end
always @ (posedge clk_i)
mode_load_pulse <= #TCQ mode_load_d1 & ~mode_load_d2;
// MUX the addr pattern out depending on the addr_mode setting
// "000" = bram; takes the address from bram output
// "001" = fixed address from the fixed_addr input
// "010" = psuedo ramdom pattern; generated from internal 64 bit LFSR
// "011" = sequential
// "100" = mode that used for prbs addr , prbs bl and prbs data
//always @(addr_mode_reg,prbs_addr,seq_addr,fixed_addr,bram_addr_i,data_mode_i)
always @ (posedge clk_i) begin
if (rst_i[3])
addr_out <= #TCQ start_addr_i;
else if (vio_instr_mode_value == 4'h7)
addr_out <= #TCQ fixed_addr_i;
else
case({addr_mode_reg})
3'b000: addr_out <= #TCQ bram_addr_i;
3'b001: addr_out <= #TCQ fixed_addr;
// 3'b010: addr_out <= #TCQ {prbs_addr[31:10], 10'h00}; // this is specific to
// data mode = PRBS
3'b010: if (FAMILY == "VIRTEX6")
if (data_mode_i == 5) // ??? optimize this
addr_out <= #TCQ {prbs_addr[31:BL_WIDTH+1], {BL_WIDTH+1{1'b0}}}; // this is specific to
else
addr_out <= #TCQ {prbs_addr[31:BL_WIDTH], {BL_WIDTH{1'b0}}}; // this is specific to
else
addr_out <= #TCQ {prbs_addr};
3'b011: addr_out <= #TCQ {2'b0,seq_addr[29:0]};
3'b100: addr_out <= #TCQ {3'b000,seq_addr[6:2],seq_addr[23:0]};//{prbs_addr[31:6],6'b000000} ;
3'b101: addr_out <= #TCQ {prbs_addr[31:20],seq_addr[19:0]} ;
default : addr_out <= #TCQ 'b0;
endcase
end
// ADDR PRBS GENERATION
generate
if (CMD_PATTERN == "CGEN_PRBS" || CMD_PATTERN == "CGEN_ALL" )
begin: gen_prbs_addr
mig_7series_v1_9_cmd_prbs_gen #
(
.TCQ (TCQ),
.FAMILY (FAMILY),
.ADDR_WIDTH (32),
.DWIDTH (DWIDTH),
.MEM_BURST_LEN (MEM_BURST_LEN),
.PRBS_WIDTH (32),
.SEED_WIDTH (32),
.PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS),
.PRBS_SADDR_MASK_POS (PRBS_SADDR_MASK_POS),
.PRBS_EADDR (PRBS_EADDR),
.PRBS_SADDR (PRBS_SADDR)
)
addr_prbs_gen
(
.clk_i (clk_i),
.clk_en (cmd_clk_en),
.prbs_seed_init (mode_load_pulse),
.prbs_seed_i (cmd_seed_i[31:0]),
.prbs_o (prbs_addr)
);
end
else
begin: no_prbs
assign prbs_addr = 'b0;
end
endgenerate
always @ (posedge clk_i) begin
if (addr_out[31:8] >= end_addr_i[31:8])
gen_addr_larger <= 1'b1;
else
gen_addr_larger <= 1'b0;
end
wire [23:0] calc_end_addr /* synthesis syn_dspstyle = logic */ ;
assign calc_end_addr = (bl_out*(DWIDTH/8) + addr_out[31:8]) ;
always @ (posedge clk_i) begin
if (instr_mode_i == 4 && mem_init_done)
gen_bl_larger <= 1'b0;
else if ( calc_end_addr >= end_addr_i[31:8] )
gen_bl_larger <= 1'b1;
else
gen_bl_larger <= 1'b0;
end
//converting string to integer
//localparam MEM_BURST_INT = (MEM_BURST_LEN == "8")? 8 : 4;
localparam MEM_BURST_INT = MEM_BURST_LEN ;
generate
if (FAMILY == "SPARTAN6") begin : INC_COUNTS_S
always @ (posedge clk_i)
if (mem_init_done)
INC_COUNTS <= #TCQ (DWIDTH/8)*(bl_out_reg);
else begin
if (fixed_bl_i == 0)
INC_COUNTS <= #TCQ (DWIDTH/8)*(64);
else
INC_COUNTS <= #TCQ (DWIDTH/8)*(fixed_bl_i);
end
end
else begin : INC_COUNTS_V
always @ (posedge clk_i) begin
if (rst_i[3]) begin
INC_COUNTS[BL_WIDTH-1:0] <= fixed_bl_i * (DWIDTH)/16;
INC_COUNTS[BL_WIDTH+2:BL_WIDTH] <= 'b0;
end
else
if (nCK_PER_CLK == 4 && MEM_BURST_LEN != 2)
INC_COUNTS <= #TCQ (bl_out << LOGB2_MEM_BURST_INT);
else begin
if (MEM_TYPE != "QDR2PLUS") begin //nCK_PER_CK == 2
if (MEM_BURST_LEN == 8 || MEM_BURST_LEN == 2) // 13:11
INC_COUNTS <= #TCQ (bl_out << (LOGB2_MEM_BURST_INT - 1));
else
INC_COUNTS <= #TCQ (bl_out << LOGB2_MEM_BURST_INT);
end
else begin
INC_COUNTS[BL_WIDTH-1:0] <= #TCQ bl_out;
INC_COUNTS[BL_WIDTH+2:BL_WIDTH] <= 'b0;
end
end
end
end
endgenerate
generate
// Sequential Address pattern
// It is generated when rdy_i is valid and write command is valid and bl_cmd is valid.
if (CMD_PATTERN == "CGEN_SEQUENTIAL" || CMD_PATTERN == "CGEN_ALL" )
begin : seq_addr_gen
assign seq_addr = addr_counts;
always @ (posedge clk_i)
begin
if (rst_i[2])
first_mode_load_pulse_set <= 1'b0;
else if (mode_load_pulse_r1)
first_mode_load_pulse_set <= #TCQ 1'b1;
end
always @ (posedge clk_i)
begin
mode_load_pulse_r1 <= #TCQ mode_load_pulse;
first_mode_load_pulse_r1 <= #TCQ mode_load_pulse & ~first_mode_load_pulse_set;
end
always @ (posedge clk_i)
begin
if (rst_i[4])
mem_init_done_r <= #TCQ 1'b0 ;
else if (cmd_clk_en_r)
mem_init_done_r <= #TCQ mem_init_done ;
end
reg COut_b,COut_c;
wire [32:0] addr_counts_added;
assign addr_counts_added = addr_counts + INC_COUNTS /* synthesis syn_dspstyle = logic */ ;
always @ (posedge clk_i)
addr_counts_next_r <= #TCQ addr_counts_added ;
always @ (posedge clk_i)
cmd_clk_en_r <= #TCQ cmd_clk_en;
always @ (posedge clk_i)
begin
if (rst_i[4]) begin
addr_counts <= #TCQ start_addr_i;
mem_init_done <= #TCQ 1'b0;
end
else if (cmd_clk_en_r || first_mode_load_pulse_r1)
if(addr_counts_next_r >= end_addr_i ) begin
addr_counts <= #TCQ start_addr_i;
mem_init_done <= #TCQ 1'b1;
end
else // address counts get incremented by burst_length and port size each wr command generated
{COut_c,addr_counts} <= #TCQ addr_counts_added ;
end
end
else
begin: no_gen_seq_addr
assign seq_addr = 'b0;
end
endgenerate
always @ (posedge clk_i) begin
if (rst_i[4])
n_gen_write_only <= 1'b0;
else if (~n_gen_write_only && addr_counts_next_r>= end_addr_i)
n_gen_write_only <= 1'b1;
else if(addr_counts_next_r>= end_addr_i && instr_out[0] == 1'b0)
n_gen_write_only <= 1'b0;
end
generate
// Fixed Address pattern
if (CMD_PATTERN == "CGEN_FIXED" || CMD_PATTERN == "CGEN_ALL" )
begin : fixed_addr_gen
assign fixed_addr = (DWIDTH == 32)? {fixed_addr_i[31:2],2'b0} :
(DWIDTH == 64)? {fixed_addr_i[31:3],3'b0}:
(DWIDTH <= 128)? {fixed_addr_i[31:4],4'b0}:
(DWIDTH <= 256)? {fixed_addr_i[31:5],5'b0}:
{fixed_addr_i[31:6],6'b0};
end
else
begin : no_fixed_addr_gen
assign fixed_addr = 'b0;
end
endgenerate
generate
// BRAM Address pattern
if (CMD_PATTERN == "CGEN_BRAM" || CMD_PATTERN == "CGEN_ALL" )
begin : bram_addr_gen
assign bram_rdy_o = run_traffic_i & cmd_clk_en & bram_valid_i | mode_load_pulse;
end
else
begin: no_bram_addr_gen
assign bram_rdy_o = 1'b0;
end
endgenerate
///////////////////////////////////////////////////////////////////////////
// INSTR COMMAND GENERATION
// tap points are 3,2
//`define RD 3'b001
//`define RDP 3'b011
//`define WR 3'b000
//`define WRP 3'b010
//`define REFRESH 3'b100
// use 14 stages 1 sr16; tap position 1,3,5,14
always @ (posedge clk_i) begin
if (rst_i[4])
force_rd_counts <= #TCQ 'b0;
else if (instr_vld) begin
force_rd_counts <= #TCQ force_rd_counts + 1'b1;
end
end
always @ (posedge clk_i) begin
if (rst_i[4])
force_rd <= #TCQ 1'b0;
else if (force_rd_counts[3])
force_rd <= #TCQ 1'b1;
else
force_rd <= #TCQ 1'b0;
end
// adding refresh timer to limit the amount of issuing refresh command.
always @ (posedge clk_i) begin
if (rst_i[4])
refresh_timer <= #TCQ 'b0;
else
refresh_timer <= #TCQ refresh_timer + 1'b1;
end
always @ (posedge clk_i) begin
if (rst_i[4])
refresh_cmd_en <= #TCQ 'b0;
//else if (refresh_timer >= 12'hff0 && refresh_timer <= 12'hfff)
else if (refresh_timer == 10'h3ff)
refresh_cmd_en <= #TCQ 'b1;
else if (cmd_clk_en && refresh_cmd_en)
refresh_cmd_en <= #TCQ 'b0;
end
always @ (posedge clk_i) begin
if (FAMILY == "SPARTAN6")
refresh_prbs <= #TCQ prbs_instr_b[3] & refresh_cmd_en;
else
refresh_prbs <= #TCQ 1'b0;
end
always @ (posedge clk_i)
begin
if (rst_i[4])
write_percent_cnt <= 'b0;
else if (cmd_clk_en_r)
if ( write_percent_cnt == 9)
write_percent_cnt <= 'b0;
else
write_percent_cnt <= write_percent_cnt + 1'b1;
end
always @ (posedge clk_i)
begin
if (rst_i[4])
toggle_rw <= 1'b0;
else if (cmd_clk_en_r && mem_init_done)
if (write_percent_cnt >= vio_percent_write)
toggle_rw <= 1'b1;
else
toggle_rw <= 1'b0;
end
always @ (posedge clk_i) begin
case(instr_mode_i)
0: instr_out <= #TCQ bram_instr_i;
1: instr_out <= #TCQ fixed_instr_i;
2: instr_out <= #TCQ {2'b00,(prbs_instr_a[0] | force_rd)};
3: instr_out <= #TCQ {2'b00,prbs_instr_a[0]}; //: WP/RP
4: instr_out <= #TCQ {2'b00,toggle_rw}; // percent write
// may be add another PRBS for generating REFRESH
// 5: instr_out <= #TCQ {prbs_instr_b[3],prbs_instr_b[0], prbs_instr_a[0]}; // W/WP/R/RP/REFRESH W/WP/R/RP/REFRESH
5: instr_out <= #TCQ {refresh_prbs ,prbs_instr_b[0], prbs_instr_a[0]}; // W/WP/R/RP/REFRESH W/WP/R/RP/REFRESH
default : instr_out <= #TCQ {2'b00,1'b1};
endcase
end
generate // PRBS INSTRUCTION generation
// use two PRBS generators and tap off 1 bit from each to create more randomness for
// generating actual read/write commands
if (CMD_PATTERN == "CGEN_PRBS" || CMD_PATTERN == "CGEN_ALL" )
begin: gen_prbs_instr
mig_7series_v1_9_cmd_prbs_gen #
(
.TCQ (TCQ),
.PRBS_CMD ("INSTR"),
.DWIDTH (DWIDTH),
.ADDR_WIDTH (32),
.SEED_WIDTH (15),
.PRBS_WIDTH (20)
)
instr_prbs_gen_a
(
.clk_i (clk_i),
.clk_en (cmd_clk_en),
.prbs_seed_init (load_seed_i),
.prbs_seed_i (cmd_seed_i[14:0]),
.prbs_o (prbs_instr_a)
);
mig_7series_v1_9_cmd_prbs_gen #
(
.PRBS_CMD ("INSTR"),
.DWIDTH (DWIDTH),
.SEED_WIDTH (15),
.PRBS_WIDTH (20)
)
instr_prbs_gen_b
(
.clk_i (clk_i),
.clk_en (cmd_clk_en),
.prbs_seed_init (load_seed_i),
.prbs_seed_i (cmd_seed_i[16:2]),
.prbs_o (prbs_instr_b)
);
end
else
begin: no_prbs_instr_gen
assign prbs_instr_a = 'b0;
assign prbs_instr_b = 'b0;
end
endgenerate
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
// BURST LENGTH GENERATION
// burst length code = user burst length input - 1
// mcb_flow_control does the minus before sending out to mcb\
// when filling up the memory, need to make sure bl doesn't go beyound its upper limit boundary
//assign force_bl1 = (addr_out[31:0] >= (end_addr_i[31:0] - 4*64)) ? 1'b1: 1'b0;
// for neighbour pattern, need to limit the bl to make sure it is within column size boundary.
// This is required in S6 .
always @ (posedge clk_i)
begin
if (rst_i[4] )
cal_blout <= 'b0;
else
cal_blout <= bl_out* (DWIDTH/8);
end
always @(addr_out,mem_init_done, instr_mode_i,bl_out,cal_blout,end_addr_i,rst_i,buf_avail_r,bl_x_DWIDTH_BY_8) begin
if (rst_i[6])
force_bl1 = 1'b0;
else if (mem_init_done && instr_mode_i == 4)
force_bl1 = 1'b0;
else if (((addr_out + cal_blout) >= end_addr_i) || (buf_avail_r <= 50 && PORT_MODE == "RD_MODE"))
force_bl1 = 1'b1;
else
force_bl1 = 1'b0;
end
always @(posedge clk_i) begin
if (rst_i[6])
bl_out_reg <= #TCQ fixed_bl_i;
else if (bl_out_vld)
bl_out_reg <= #TCQ bl_out;
end
// BurstLength defination in Traffic Gen is the consecutive write/read commands
// that sent to Memory Controller User Interface. In V6, cmd_gen module sends
// the number of burst length to rd_data_gen, wr_data_gen and mcb_flow_control_v6.
// The mcb_flow_control takes the base address of the first burst and the bl value,
// it automatically increment the next consecutive address of the back-to-back commands
// until the burst counts decrement to 0.
always @ (posedge clk_i) begin
if (mode_load_pulse || rst_i[3])
if (data_mode_i == 4)
bl_out <= #TCQ 10'd32 ;
else
bl_out <= #TCQ fixed_bl_i ;
else if (cmd_clk_en) begin
case({bl_mode_reg})
0: begin
bl_out[5:0] <= #TCQ bram_bl_i ;
bl_out[BL_WIDTH-1:6] <= #TCQ 'b0 ;
end
1: if (data_mode_i == 4)
bl_out <= #TCQ 10'd32 ;
else
bl_out <= #TCQ fixed_bl_i ;
2: bl_out <= #TCQ prbs_brlen;
default : begin
bl_out[5:0] <= #TCQ 6'h1;
bl_out[BL_WIDTH - 1:6] <= #TCQ 'b0;
end
endcase
end
end
//synthesis translate_off
//always @ (bl_out)
// if(bl_out >2 && FAMILY == "VIRTEX6") begin
// $display("Error ! Not valid burst length");
// $stop;
// end
//synthesis translate_on
generate
if (CMD_PATTERN == "CGEN_PRBS" || CMD_PATTERN == "CGEN_ALL" )
begin: gen_prbs_bl
mig_7series_v1_9_cmd_prbs_gen #
(
.TCQ (TCQ),
.FAMILY (FAMILY),
.PRBS_CMD ("BLEN"),
.ADDR_WIDTH (32),
.SEED_WIDTH (15),
.PRBS_WIDTH (20)
)
bl_prbs_gen
(
.clk_i (clk_i),
.clk_en (cmd_clk_en),
.prbs_seed_init (load_seed_i),
.prbs_seed_i (cmd_seed_i[16:2]),
.prbs_o (prbs_bl)
);
always @ (prbs_bl)
if (FAMILY == "SPARTAN6" || FAMILY == "MCB") // supports 1 throug 64
prbs_brlen[5:0] = (prbs_bl[5:1] == 5'b00000) ? 6'b000010: {prbs_bl[5:1],1'b0};
else // VIRTEX6 only supports 1 or 2 burst on user ports
prbs_brlen = (prbs_bl[BL_WIDTH-1:1] == 5'b00000) ? {{BL_WIDTH-2{1'b0}},2'b10}: {prbs_bl[BL_WIDTH-1:1],1'b0};
end
else
begin: no_gen_prbs_bl
assign prbs_bl = 'b0;
end
endgenerate
endmodule
|
/****************************************************************************************
*
* File Name: ddr2_model.v
* Version: 5.82
* Model: BUS Functional
*
* Dependencies: ddr2_model_parameters.vh
*
* Description: Micron SDRAM DDR2 (Double Data Rate 2)
*
* Limitation: - doesn't check for average refresh timings
* - positive ck and ck_n edges are used to form internal clock
* - positive dqs and dqs_n edges are used to latch data
* - test mode is not modeled
*
* Note: - Set simulator resolution to "ps" accuracy
* - Set Debug = 0 to disable $display messages
*
* Disclaimer This software code and all associated documentation, comments or other
* of Warranty: information (collectively "Software") is provided "AS IS" without
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGES. Because some jurisdictions prohibit the exclusion or
* limitation of liability for consequential or incidental damages, the
* above limitation may not apply to you.
*
* Copyright 2003 Micron Technology, Inc. All rights reserved.
*
* Rev Author Date Changes
* ---------------------------------------------------------------------------------------
* 1.00 JMK 07/29/03 Initial Release
* 1.10 JMK 08/09/03 Timing Parameter updates to tIS, tIH, tDS, tDH
* 2.20 JMK 08/07/03 General cleanup
* 2.30 JMK 11/26/03 Added CL_MIN, CL_MAX, wl_min and wl_max parameters.
* Added AL_MIN and AL_MAX parameters.
* Removed support for OCD.
* 2.40 JMK 01/15/04 Removed verilog 2001 constructs.
* 2.50 JMK 01/29/04 Removed tRP checks during Precharge command.
* 2.60 JMK 04/20/04 Fixed tWTR check.
* 2.70 JMK 04/30/04 Added tRFC maximum check.
* Combined Self Refresh and Power Down always blocks.
* Added Reset Function (CKE LOW Anytime).
* 2.80 JMK 08/19/04 Precharge is treated as NOP when bank is not active.
* Added checks for tRAS, tWR, tRTP to any bank during Pre-All.
* tRFC maximum violation will only display one time.
* 2.90 JMK 11/05/04 Fixed DQS checking during write.
* Fixed false tRFC max assertion during power up and self ref.
* Added warning for 200us CKE low time during initialization.
* Added -3, -3E, and -37V speed grades to ddr2_parameters.v
* 3.00 JMK 04/22/05 Removed ODT off requirement during power down.
* Added tAOND, tAOFD, tANPD, tAXPD, tAONPD, and tAOFPD parameters.
* Added ODT status messages.
* Updated the initialization sequence.
* Disable ODT and CLK pins during self refresh.
* Disable cmd and addr pins during power down and self refresh.
* 3.10 JMK 06/07/05 Disable trpa checking if the part does not have 8 banks.
* Changed tAXPD message from error to a warning.
* Added tDSS checking.
* Removed tDQSL checking during tWPRE and tWPST.
* Fixed a burst order error during writes.
* Renamed parameters file with .vh extension.
* 3.20 JMK 07/18/05 Removed 14 tCK requirement from LMR to READ.
* 3.30 JMK 08/03/05 Added check for interrupting a burst with auto precharge.
* 4.00 JMK 11/21/05 Parameter names all UPPERCASE, signal names all lowercase.
* Clock jitter can be tolerated within specification range.
* Clock frequency is sampled from the CK pin.
* Scaleable up to 64 DQ and 16 DQS bits.
* Read data can be randomly skewed using RANDOM_OUT_DELAY.
* Parameterized read and write DQS, and read DQ.
* Initialization can be bypassed using initialize task.
* 4.10 JMK 11/30/05 Fixed compile errors when `MAX_MEM was defined.
* 4.20 JMK 12/09/05 Fixed memory addressing error when `MAX_MEM was defined.
* 4.30 JMK 02/15/06 Added dummy write to initialization sequence.
* Removed tWPST maximum checking.
* Rising dqs_n edge latches data when enabled in EMR.
* Fixed a sign error in the tJIT(cc) calculation.
* 4.40 JMK 02/16/06 Fixed dummy write when`MAX_MEM was defined.
* 4.50 JMK 02/27/06 Fixed extra tDQSS assertions.
* Fixed tRCD and tWTR checking.
* Errors entering Power Down or Self Refresh will cause reset.
* Ignore dqs_n when disabled in EMR.
* 5.00 JMK 04/24/06 Test stimulus now included from external file (subtest.vh)
* Fixed tRFC max assertion during self refresh.
* Fixed tANPD checking during Power Down.
* Removed dummy write from initialization sequence.
* 5.01 JMK 04/28/06 Fixed Auto Precharge to Load Mode, Refresh and Self Refresh.
* Removed Auto Precharge error message during Power Down Enter.
* 5.10 JMK 07/26/06 Created internal clock using ck and ck_n.
* RDQS can only be enabled in EMR for x8 configurations.
* CAS latency is checked vs frequency when DLL locks.
* tMOD changed from tCK units to ns units.
* Added 50 Ohm setting for Rtt in EMR.
* Improved checking of DQS during writes.
* 5.20 JMK 10/02/06 Fixed DQS checking for interrupting write to write and x16.
* 5.30 JMK 05/25/07 Fixed checking for 0-Z transition on write postamble.
* 5.50 JMK 05/30/08 Renamed ddr2_dimm.v to ddr2_module.v and added SODIMM support.
* Added a register delay to ddr2_module.v when RDIMM is defined.
* Added multi-chip package model support in ddr2_mcp.v
* Added High Temp Self Refresh rate setting in EMRS2[7]
* 5.70 JMK 04/23/09 Updated tRPA definition
* Increased internal width to 72 bit DQ bus
* 5.80 SPH 08/12/09 Fixed tRAS maximum violation (only check if bank still open)
* 5.81 SPH 12/08/09 Only check tIH for cmd_addr if CS# LOW
* 5.82 SPH 04/08/10 Correct debug message for SRT in EMR2
* 5.81 SPH 12/08/09 Only check tIH for cmd_addr if CS# LOW
* 5.81 SPH 12/08/09 Only check tIH for cmd_addr if CS# LOW
****************************************************************************************/
// DO NOT CHANGE THE TIMESCALE
// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION
`timescale 1ps / 1ps
//Memory Details
`define x1Gb
`define sg25E
`define x16
module ddr2_model (
ck,
ck_n,
cke,
cs_n,
ras_n,
cas_n,
we_n,
dm_rdqs,
ba,
addr,
dq,
dqs,
dqs_n,
rdqs_n,
odt
);
`include "ddr2_model_parameters.vh"
// text macros
`define DQ_PER_DQS DQ_BITS/DQS_BITS
`define BANKS (1<<BA_BITS)
`define MAX_BITS (BA_BITS+ROW_BITS+COL_BITS-BL_BITS)
`define MAX_SIZE (1<<(BA_BITS+ROW_BITS+COL_BITS-BL_BITS))
`define MEM_SIZE (1<<MEM_BITS)
`define MAX_PIPE 2*(AL_MAX + CL_MAX)
// Declare Ports
input ck;
input ck_n;
input cke;
input cs_n;
input ras_n;
input cas_n;
input we_n;
inout [DM_BITS-1:0] dm_rdqs;
input [BA_BITS-1:0] ba;
input [ADDR_BITS-1:0] addr;
inout [DQ_BITS-1:0] dq;
inout [DQS_BITS-1:0] dqs;
inout [DQS_BITS-1:0] dqs_n;
output [DQS_BITS-1:0] rdqs_n;
input odt;
// clock jitter
real tck_avg;
time tck_sample [TDLLK-1:0];
time tch_sample [TDLLK-1:0];
time tcl_sample [TDLLK-1:0];
time tck_i;
time tch_i;
time tcl_i;
real tch_avg;
real tcl_avg;
time tm_ck_pos;
time tm_ck_neg;
real tjit_per_rtime;
integer tjit_cc_time;
real terr_nper_rtime;
// clock skew
real out_delay;
integer dqsck [DQS_BITS-1:0];
integer dqsck_min;
integer dqsck_max;
integer dqsq_min;
integer dqsq_max;
integer seed;
// Mode Registers
reg burst_order;
reg [BL_BITS:0] burst_length;
integer cas_latency;
integer additive_latency;
reg dll_reset;
reg dll_locked;
reg dll_en;
integer write_recovery;
reg low_power;
reg [1:0] odt_rtt;
reg odt_en;
reg [2:0] ocd;
reg dqs_n_en;
reg rdqs_en;
reg out_en;
integer read_latency;
integer write_latency;
// cmd encoding
parameter
LOAD_MODE = 4'b0000,
REFRESH = 4'b0001,
PRECHARGE = 4'b0010,
ACTIVATE = 4'b0011,
WRITE = 4'b0100,
READ = 4'b0101,
NOP = 4'b0111,
PWR_DOWN = 4'b1000,
SELF_REF = 4'b1001
;
reg [8*9-1:0] cmd_string [9:0];
initial begin
cmd_string[LOAD_MODE] = "Load Mode";
cmd_string[REFRESH ] = "Refresh ";
cmd_string[PRECHARGE] = "Precharge";
cmd_string[ACTIVATE ] = "Activate ";
cmd_string[WRITE ] = "Write ";
cmd_string[READ ] = "Read ";
cmd_string[NOP ] = "No Op ";
cmd_string[PWR_DOWN ] = "Pwr Down ";
cmd_string[SELF_REF ] = "Self Ref ";
end
// command state
reg [`BANKS-1:0] active_bank;
reg [`BANKS-1:0] auto_precharge_bank;
reg [`BANKS-1:0] write_precharge_bank;
reg [`BANKS-1:0] read_precharge_bank;
reg [ROW_BITS-1:0] active_row [`BANKS-1:0];
reg in_power_down;
reg in_self_refresh;
reg [3:0] init_mode_reg;
reg init_done;
integer init_step;
reg er_trfc_max;
reg odt_state;
reg prev_odt;
// cmd timers/counters
integer ref_cntr;
integer ck_cntr;
integer ck_load_mode;
integer ck_write;
integer ck_read;
integer ck_write_ap;
integer ck_power_down;
integer ck_slow_exit_pd;
integer ck_self_refresh;
integer ck_cke;
integer ck_odt;
integer ck_dll_reset;
integer ck_bank_write [`BANKS-1:0];
integer ck_bank_read [`BANKS-1:0];
time tm_refresh;
time tm_precharge;
time tm_precharge_all;
time tm_activate;
time tm_write_end;
time tm_self_refresh;
time tm_odt_en;
time tm_bank_precharge [`BANKS-1:0];
time tm_bank_activate [`BANKS-1:0];
time tm_bank_write_end [`BANKS-1:0];
time tm_bank_read_end [`BANKS-1:0];
// pipelines
reg [`MAX_PIPE:0] al_pipeline;
reg [`MAX_PIPE:0] wr_pipeline;
reg [`MAX_PIPE:0] rd_pipeline;
reg [`MAX_PIPE:0] odt_pipeline;
reg [BA_BITS-1:0] ba_pipeline [`MAX_PIPE:0];
reg [ROW_BITS-1:0] row_pipeline [`MAX_PIPE:0];
reg [COL_BITS-1:0] col_pipeline [`MAX_PIPE:0];
reg prev_cke;
// data state
reg [BL_MAX*DQ_BITS-1:0] memory_data;
reg [BL_MAX*DQ_BITS-1:0] bit_mask;
reg [BL_BITS-1:0] burst_position;
reg [BL_BITS:0] burst_cntr;
reg [DQ_BITS-1:0] dq_temp;
reg [35:0] check_write_postamble;
reg [35:0] check_write_preamble;
reg [35:0] check_write_dqs_high;
reg [35:0] check_write_dqs_low;
reg [17:0] check_dm_tdipw;
reg [71:0] check_dq_tdipw;
// data timers/counters
time tm_cke;
time tm_odt;
time tm_tdqss;
time tm_dm [17:0];
time tm_dqs [17:0];
time tm_dqs_pos [35:0];
time tm_dqss_pos [35:0];
time tm_dqs_neg [35:0];
time tm_dq [71:0];
time tm_cmd_addr [22:0];
reg [8*7-1:0] cmd_addr_string [22:0];
initial begin
cmd_addr_string[ 0] = "CS_N ";
cmd_addr_string[ 1] = "RAS_N ";
cmd_addr_string[ 2] = "CAS_N ";
cmd_addr_string[ 3] = "WE_N ";
cmd_addr_string[ 4] = "BA 0 ";
cmd_addr_string[ 5] = "BA 1 ";
cmd_addr_string[ 6] = "BA 2 ";
cmd_addr_string[ 7] = "ADDR 0";
cmd_addr_string[ 8] = "ADDR 1";
cmd_addr_string[ 9] = "ADDR 2";
cmd_addr_string[10] = "ADDR 3";
cmd_addr_string[11] = "ADDR 4";
cmd_addr_string[12] = "ADDR 5";
cmd_addr_string[13] = "ADDR 6";
cmd_addr_string[14] = "ADDR 7";
cmd_addr_string[15] = "ADDR 8";
cmd_addr_string[16] = "ADDR 9";
cmd_addr_string[17] = "ADDR 10";
cmd_addr_string[18] = "ADDR 11";
cmd_addr_string[19] = "ADDR 12";
cmd_addr_string[20] = "ADDR 13";
cmd_addr_string[21] = "ADDR 14";
cmd_addr_string[22] = "ADDR 15";
end
reg [8*5-1:0] dqs_string [1:0];
initial begin
dqs_string[0] = "DQS ";
dqs_string[1] = "DQS_N";
end
// Memory Storage
`ifdef MAX_MEM
reg [BL_MAX*DQ_BITS-1:0] memory [0:`MAX_SIZE-1];
`else
reg [BL_MAX*DQ_BITS-1:0] memory [0:`MEM_SIZE-1];
reg [`MAX_BITS-1:0] address [0:`MEM_SIZE-1];
reg [MEM_BITS:0] memory_index;
reg [MEM_BITS:0] memory_used;
`endif
// receive
reg ck_in;
reg ck_n_in;
reg cke_in;
reg cs_n_in;
reg ras_n_in;
reg cas_n_in;
reg we_n_in;
reg [17:0] dm_in;
reg [2:0] ba_in;
reg [15:0] addr_in;
reg [71:0] dq_in;
reg [35:0] dqs_in;
reg odt_in;
reg [17:0] dm_in_pos;
reg [17:0] dm_in_neg;
reg [71:0] dq_in_pos;
reg [71:0] dq_in_neg;
reg dq_in_valid;
reg dqs_in_valid;
integer wdqs_cntr;
integer wdq_cntr;
integer wdqs_pos_cntr [35:0];
reg b2b_write;
reg [35:0] prev_dqs_in;
reg diff_ck;
always @(ck ) ck_in <= #BUS_DELAY ck;
always @(ck_n ) ck_n_in <= #BUS_DELAY ck_n;
always @(cke ) cke_in <= #BUS_DELAY cke;
always @(cs_n ) cs_n_in <= #BUS_DELAY cs_n;
always @(ras_n ) ras_n_in <= #BUS_DELAY ras_n;
always @(cas_n ) cas_n_in <= #BUS_DELAY cas_n;
always @(we_n ) we_n_in <= #BUS_DELAY we_n;
always @(dm_rdqs) dm_in <= #BUS_DELAY dm_rdqs;
always @(ba ) ba_in <= #BUS_DELAY ba;
always @(addr ) addr_in <= #BUS_DELAY addr;
always @(dq ) dq_in <= #BUS_DELAY dq;
always @(dqs or dqs_n) dqs_in <= #BUS_DELAY (dqs_n<<18) | dqs;
always @(odt ) odt_in <= #BUS_DELAY odt;
// create internal clock
always @(posedge ck_in) diff_ck <= ck_in;
always @(posedge ck_n_in) diff_ck <= ~ck_n_in;
wire [17:0] dqs_even = dqs_in[17:0];
wire [17:0] dqs_odd = dqs_n_en ? dqs_in[35:18] : ~dqs_in[17:0];
wire [3:0] cmd_n_in = !cs_n_in ? {ras_n_in, cas_n_in, we_n_in} : NOP; //deselect = nop
// transmit
reg dqs_out_en;
reg [DQS_BITS-1:0] dqs_out_en_dly;
reg dqs_out;
reg [DQS_BITS-1:0] dqs_out_dly;
reg dq_out_en;
reg [DQ_BITS-1:0] dq_out_en_dly;
reg [DQ_BITS-1:0] dq_out;
reg [DQ_BITS-1:0] dq_out_dly;
integer rdqsen_cntr;
integer rdqs_cntr;
integer rdqen_cntr;
integer rdq_cntr;
bufif1 buf_dqs [DQS_BITS-1:0] (dqs, dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}});
bufif1 buf_dm [DM_BITS-1:0] (dm_rdqs, dqs_out_dly, dqs_out_en_dly & {DM_BITS {out_en}} & {DM_BITS{rdqs_en}});
bufif1 buf_dqs_n [DQS_BITS-1:0] (dqs_n, ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}} & {DQS_BITS{dqs_n_en}});
bufif1 buf_rdqs_n [DQS_BITS-1:0] (rdqs_n, ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}} & {DQS_BITS{dqs_n_en}} & {DQS_BITS{rdqs_en}});
bufif1 buf_dq [DQ_BITS-1:0] (dq, dq_out_dly, dq_out_en_dly & {DQ_BITS {out_en}});
initial begin
if (BL_MAX < 2)
$display("%m ERROR: BL_MAX parameter must be >= 2. \nBL_MAX = %d", BL_MAX);
if ((1<<BO_BITS) > BL_MAX)
$display("%m ERROR: 2^BO_BITS cannot be greater than BL_MAX parameter.");
$timeformat (-12, 1, " ps", 1);
reset_task;
seed = RANDOM_SEED;
ck_cntr = 0;
end
// calculate the absolute value of a real number
function real abs_value;
input arg;
real arg;
begin
if (arg < 0.0)
abs_value = -1.0 * arg;
else
abs_value = arg;
end
endfunction
`ifdef MAX_MEM
`else
function get_index;
input [`MAX_BITS-1:0] addr;
begin : index
get_index = 0;
for (memory_index=0; memory_index<memory_used; memory_index=memory_index+1) begin
if (address[memory_index] == addr) begin
get_index = 1;
disable index;
end
end
end
endfunction
`endif
task memory_write;
input [BA_BITS-1:0] bank;
input [ROW_BITS-1:0] row;
input [COL_BITS-1:0] col;
input [BL_MAX*DQ_BITS-1:0] data;
reg [`MAX_BITS-1:0] addr;
begin
// chop off the lowest address bits
addr = {bank, row, col}/BL_MAX;
`ifdef MAX_MEM
memory[addr] = data;
`else
if (get_index(addr)) begin
address[memory_index] = addr;
memory[memory_index] = data;
end else if (memory_used == `MEM_SIZE) begin
$display ("%m: at time %t ERROR: Memory overflow. Write to Address %h with Data %h will be lost.\nYou must increase the MEM_BITS parameter or define MAX_MEM.", $time, addr, data);
if (STOP_ON_ERROR) $stop(0);
end else begin
address[memory_used] = addr;
memory[memory_used] = data;
memory_used = memory_used + 1;
end
`endif
end
endtask
task memory_read;
input [BA_BITS-1:0] bank;
input [ROW_BITS-1:0] row;
input [COL_BITS-1:0] col;
output [BL_MAX*DQ_BITS-1:0] data;
reg [`MAX_BITS-1:0] addr;
begin
// chop off the lowest address bits
addr = {bank, row, col}/BL_MAX;
`ifdef MAX_MEM
data = memory[addr];
`else
if (get_index(addr)) begin
data = memory[memory_index];
end else begin
data = {BL_MAX*DQ_BITS{1'bx}};
end
`endif
end
endtask
// Before this task runs, the model must be in a valid state for precharge power down.
// After this task runs, NOP commands must be issued until tRFC has been met
task initialize;
input [ADDR_BITS-1:0] mode_reg0;
input [ADDR_BITS-1:0] mode_reg1;
input [ADDR_BITS-1:0] mode_reg2;
input [ADDR_BITS-1:0] mode_reg3;
begin
if (DEBUG) $display ("%m: at time %t INFO: Performing Initialization Sequence", $time);
cmd_task(1, NOP, 'bx, 'bx);
cmd_task(1, PRECHARGE, 'bx, 1<<AP); // Precharege ALL
cmd_task(1, LOAD_MODE, 3, mode_reg3);
cmd_task(1, LOAD_MODE, 2, mode_reg2);
cmd_task(1, LOAD_MODE, 1, mode_reg1);
cmd_task(1, LOAD_MODE, 0, mode_reg0 | 'h100); // DLL Reset
cmd_task(1, PRECHARGE, 'bx, 1<<AP); // Precharege ALL
cmd_task(1, REFRESH, 'bx, 'bx);
cmd_task(1, REFRESH, 'bx, 'bx);
cmd_task(1, LOAD_MODE, 0, mode_reg0);
cmd_task(1, LOAD_MODE, 1, mode_reg1 | 'h380); // OCD Default
cmd_task(1, LOAD_MODE, 1, mode_reg1);
cmd_task(0, NOP, 'bx, 'bx);
end
endtask
task reset_task;
integer i;
begin
// disable inputs
dq_in_valid = 0;
dqs_in_valid <= 0;
wdqs_cntr = 0;
wdq_cntr = 0;
for (i=0; i<36; i=i+1) begin
wdqs_pos_cntr[i] <= 0;
end
b2b_write <= 0;
// disable outputs
out_en = 0;
dqs_n_en = 0;
rdqs_en = 0;
dq_out_en = 0;
rdq_cntr = 0;
dqs_out_en = 0;
rdqs_cntr = 0;
// disable ODT
odt_en = 0;
odt_state = 0;
// reset bank state
active_bank = {`BANKS{1'b1}};
auto_precharge_bank = 0;
read_precharge_bank = 0;
write_precharge_bank = 0;
// require initialization sequence
init_done = 0;
init_step = 0;
init_mode_reg = 0;
// reset DLL
dll_en = 0;
dll_reset = 0;
dll_locked = 0;
ocd = 0;
// exit power down and self refresh
in_power_down = 0;
in_self_refresh = 0;
// clear pipelines
al_pipeline = 0;
wr_pipeline = 0;
rd_pipeline = 0;
odt_pipeline = 0;
// clear memory
`ifdef MAX_MEM
for (i=0; i<=`MAX_SIZE; i=i+1) begin //erase memory ... one address at a time
memory[i] <= 'bx;
end
`else
memory_used <= 0; //erase memory
`endif
// clear maximum timing checks
tm_refresh <= 'bx;
for (i=0; i<`BANKS; i=i+1) begin
tm_bank_activate[i] <= 'bx;
end
end
endtask
task chk_err;
input samebank;
input [BA_BITS-1:0] bank;
input [3:0] fromcmd;
input [3:0] cmd;
reg err;
begin
// all matching case expressions will be evaluated
casex ({samebank, fromcmd, cmd})
{1'b0, LOAD_MODE, 4'b0xxx } : begin if (ck_cntr - ck_load_mode < TMRD) $display ("%m: at time %t ERROR: tMRD violation during %s", $time, cmd_string[cmd]); end
{1'b0, LOAD_MODE, 4'b100x } : begin if (ck_cntr - ck_load_mode < TMRD) begin $display ("%m: at time %t INFO: Load Mode to Reset condition.", $time); init_done = 0; end end
{1'b0, REFRESH , 4'b0xxx } : begin if ($time - tm_refresh < TRFC_MIN) $display ("%m: at time %t ERROR: tRFC violation during %s", $time, cmd_string[cmd]); end
{1'b0, REFRESH , PWR_DOWN } : ; // 1 tCK
{1'b0, REFRESH , SELF_REF } : begin if ($time - tm_refresh < TRFC_MIN) begin $display ("%m: at time %t INFO: Refresh to Reset condition", $time); init_done = 0; end end
{1'b0, PRECHARGE, 4'b000x } : begin if ($time - tm_precharge_all < TRPA) $display ("%m: at time %t ERROR: tRPA violation during %s", $time, cmd_string[cmd]);
if ($time - tm_precharge < TRP) $display ("%m: at time %t ERROR: tRP violation during %s", $time, cmd_string[cmd]); end
{1'b1, PRECHARGE, PRECHARGE} : begin if (DEBUG && ($time - tm_precharge_all < TRPA)) $display ("%m: at time %t INFO: Precharge All interruption during %s", $time, cmd_string[cmd]);
if (DEBUG && ($time - tm_bank_precharge[bank] < TRP)) $display ("%m: at time %t INFO: Precharge bank %d interruption during %s", $time, cmd_string[cmd], bank); end
{1'b1, PRECHARGE, ACTIVATE } : begin if ($time - tm_precharge_all < TRPA) $display ("%m: at time %t ERROR: tRPA violation during %s", $time, cmd_string[cmd]);
if ($time - tm_bank_precharge[bank] < TRP) $display ("%m: at time %t ERROR: tRP violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, PRECHARGE, PWR_DOWN } : ; //1 tCK, can be concurrent with auto precharge
{1'b0, PRECHARGE, SELF_REF } : begin if (($time - tm_precharge_all < TRPA) || ($time - tm_precharge < TRP)) begin $display ("%m: at time %t INFO: Precharge to Reset condition", $time); init_done = 0; end end
{1'b0, ACTIVATE , REFRESH } : begin if ($time - tm_activate < TRC) $display ("%m: at time %t ERROR: tRC violation during %s", $time, cmd_string[cmd]); end
{1'b1, ACTIVATE , PRECHARGE} : begin if (($time - tm_bank_activate[bank] > TRAS_MAX) && (active_bank[bank] === 1'b1)) $display ("%m: at time %t ERROR: tRAS maximum violation during %s to bank %d", $time, cmd_string[cmd], bank);
if ($time - tm_bank_activate[bank] < TRAS_MIN) $display ("%m: at time %t ERROR: tRAS minimum violation during %s to bank %d", $time, cmd_string[cmd], bank);end
{1'b0, ACTIVATE , ACTIVATE } : begin if ($time - tm_activate < TRRD) $display ("%m: at time %t ERROR: tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, ACTIVATE , ACTIVATE } : begin if ($time - tm_bank_activate[bank] < TRC) $display ("%m: at time %t ERROR: tRC violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, ACTIVATE , 4'b010x } : ; // tRCD is checked outside this task
{1'b1, ACTIVATE , PWR_DOWN } : ; // 1 tCK
{1'b1, WRITE , PRECHARGE} : begin if ((ck_cntr - ck_bank_write[bank] <= write_latency + burst_length/2) || ($time - tm_bank_write_end[bank] < TWR)) $display ("%m: at time %t ERROR: tWR violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, WRITE , WRITE } : begin if (ck_cntr - ck_write < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, WRITE , READ } : begin if ((ck_load_mode < ck_write) && (ck_cntr - ck_write < write_latency + burst_length/2 + 2 - additive_latency)) $display ("%m: at time %t ERROR: tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, WRITE , PWR_DOWN } : begin if ((ck_load_mode < ck_write) && (
|write_precharge_bank
|| (ck_cntr - ck_write_ap < 1)
|| (ck_cntr - ck_write < write_latency + burst_length/2 + 2)
|| ($time - tm_write_end < TWTR))) begin $display ("%m: at time %t INFO: Write to Reset condition", $time); init_done = 0; end end
{1'b1, READ , PRECHARGE} : begin if ((ck_cntr - ck_bank_read[bank] < additive_latency + burst_length/2) || ($time - tm_bank_read_end[bank] < TRTP)) $display ("%m: at time %t ERROR: tRTP violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, READ , WRITE } : begin if ((ck_load_mode < ck_read) && (ck_cntr - ck_read < read_latency + burst_length/2 + 1 - write_latency)) $display ("%m: at time %t ERROR: tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, READ , READ } : begin if (ck_cntr - ck_read < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, READ , PWR_DOWN } : begin if ((ck_load_mode < ck_read) && (ck_cntr - ck_read < read_latency + burst_length/2 + 1)) begin $display ("%m: at time %t INFO: Read to Reset condition", $time); init_done = 0; end end
{1'b0, PWR_DOWN , 4'b00xx } : begin if (ck_cntr - ck_power_down < TXP) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); end
{1'b0, PWR_DOWN , WRITE } : begin if (ck_cntr - ck_power_down < TXP) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); end
{1'b0, PWR_DOWN , READ } : begin if (ck_cntr - ck_slow_exit_pd < TXARDS - additive_latency) $display ("%m: at time %t ERROR: tXARDS violation during %s", $time, cmd_string[cmd]);
else if (ck_cntr - ck_power_down < TXARD) $display ("%m: at time %t ERROR: tXARD violation during %s", $time, cmd_string[cmd]); end
{1'b0, SELF_REF , 4'b00xx } : begin if ($time - tm_self_refresh < TXSNR) $display ("%m: at time %t ERROR: tXSNR violation during %s", $time, cmd_string[cmd]); end
{1'b0, SELF_REF , WRITE } : begin if ($time - tm_self_refresh < TXSNR) $display ("%m: at time %t ERROR: tXSNR violation during %s", $time, cmd_string[cmd]); end
{1'b0, SELF_REF , READ } : begin if (ck_cntr - ck_self_refresh < TXSRD) $display ("%m: at time %t ERROR: tXSRD violation during %s", $time, cmd_string[cmd]); end
{1'b0, 4'b100x , 4'b100x } : begin if (ck_cntr - ck_cke < TCKE) begin $display ("%m: at time %t ERROR: tCKE violation on CKE", $time); init_done = 0; end end
endcase
end
endtask
task cmd_task;
input cke;
input [2:0] cmd;
input [BA_BITS-1:0] bank;
input [ADDR_BITS-1:0] addr;
reg [`BANKS:0] i;
integer j;
reg [`BANKS:0] tfaw_cntr;
reg [COL_BITS-1:0] col;
begin
// tRFC max check
if (!er_trfc_max && !in_self_refresh) begin
if ($time - tm_refresh > TRFC_MAX) begin
$display ("%m: at time %t ERROR: tRFC maximum violation during %s", $time, cmd_string[cmd]);
er_trfc_max = 1;
end
end
if (cke) begin
if ((cmd < NOP) && ((cmd != PRECHARGE) || !addr[AP])) begin
for (j=0; j<NOP; j=j+1) begin
chk_err(1'b0, bank, j, cmd);
chk_err(1'b1, bank, j, cmd);
end
chk_err(1'b0, bank, PWR_DOWN, cmd);
chk_err(1'b0, bank, SELF_REF, cmd);
end
case (cmd)
LOAD_MODE : begin
if (|active_bank) begin
$display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d", $time, cmd_string[cmd], bank);
case (bank)
0 : begin
// Burst Length
burst_length = 1<<addr[2:0];
if ((burst_length >= BL_MIN) && (burst_length <= BL_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = %d", $time, cmd_string[cmd], bank, burst_length);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Burst Length = %d", $time, cmd_string[cmd], bank, burst_length);
end
// Burst Order
burst_order = addr[3];
if (!burst_order) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Sequential", $time, cmd_string[cmd], bank);
end else if (burst_order) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Interleaved", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Burst Order = %d", $time, cmd_string[cmd], bank, burst_order);
end
// CAS Latency
cas_latency = addr[6:4];
read_latency = cas_latency + additive_latency;
write_latency = read_latency - 1;
if ((cas_latency >= CL_MIN) && (cas_latency <= CL_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
end
// Test Mode
if (!addr[7]) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Test Mode = Normal", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Test Mode = %d", $time, cmd_string[cmd], bank, addr[7]);
end
// DLL Reset
dll_reset = addr[8];
if (!dll_reset) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Normal", $time, cmd_string[cmd], bank);
end else if (dll_reset) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Reset DLL", $time, cmd_string[cmd], bank);
dll_locked = 0;
ck_dll_reset <= ck_cntr;
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal DLL Reset = %d", $time, cmd_string[cmd], bank, dll_reset);
end
// Write Recovery
write_recovery = addr[11:9] + 1;
if ((write_recovery >= WR_MIN) && (write_recovery <= WR_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
end
// Power Down Mode
low_power = addr[12];
if (!low_power) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = Fast Exit", $time, cmd_string[cmd], bank);
end else if (low_power) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = Slow Exit", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Power Down Mode = %d", $time, cmd_string[cmd], bank, low_power);
end
end
1 : begin
// DLL Enable
dll_en = !addr[0];
if (!dll_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Disabled", $time, cmd_string[cmd], bank);
end else if (dll_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal DLL Enable = %d", $time, cmd_string[cmd], bank, dll_en);
end
// Output Drive Strength
if (!addr[1]) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = Full", $time, cmd_string[cmd], bank);
end else if (addr[1]) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = Reduced", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Output Drive Strength = %d", $time, cmd_string[cmd], bank, addr[1]);
end
// ODT Rtt
odt_rtt = {addr[6], addr[2]};
if (odt_rtt == 2'b00) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = Disabled", $time, cmd_string[cmd], bank);
odt_en = 0;
end else if (odt_rtt == 2'b01) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 75 Ohm", $time, cmd_string[cmd], bank);
odt_en = 1;
tm_odt_en <= $time;
end else if (odt_rtt == 2'b10) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 150 Ohm", $time, cmd_string[cmd], bank);
odt_en = 1;
tm_odt_en <= $time;
end else if (odt_rtt == 2'b11) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 50 Ohm", $time, cmd_string[cmd], bank);
odt_en = 1;
tm_odt_en <= $time;
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal ODT Rtt = %d", $time, cmd_string[cmd], bank, odt_rtt);
odt_en = 0;
end
// Additive Latency
additive_latency = addr[5:3];
read_latency = cas_latency + additive_latency;
write_latency = read_latency - 1;
if ((additive_latency >= AL_MIN) && (additive_latency <= AL_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = %d", $time, cmd_string[cmd], bank, additive_latency);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Additive Latency = %d", $time, cmd_string[cmd], bank, additive_latency);
end
// OCD Program
ocd = addr[9:7];
if (ocd == 3'b000) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d OCD Program = OCD Exit", $time, cmd_string[cmd], bank);
end else if (ocd == 3'b111) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d OCD Program = OCD Default", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal OCD Program = %b", $time, cmd_string[cmd], bank, ocd);
end
// DQS_N Enable
dqs_n_en = !addr[10];
if (!dqs_n_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DQS_N Enable = Disabled", $time, cmd_string[cmd], bank);
end else if (dqs_n_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DQS_N Enable = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal DQS_N Enable = %d", $time, cmd_string[cmd], bank, dqs_n_en);
end
// RDQS Enable
rdqs_en = addr[11];
if (!rdqs_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d RDQS Enable = Disabled", $time, cmd_string[cmd], bank);
end else if (rdqs_en) begin
`ifdef x8
if (DEBUG) $display ("%m: at time %t INFO: %s %d RDQS Enable = Enabled", $time, cmd_string[cmd], bank);
`else
$display ("%m: at time %t WARNING: %s %d Illegal RDQS Enable. RDQS only exists on a x8 part", $time, cmd_string[cmd], bank);
rdqs_en = 0;
`endif
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal RDQS Enable = %d", $time, cmd_string[cmd], bank, rdqs_en);
end
// Output Enable
out_en = !addr[12];
if (!out_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Enable = Disabled", $time, cmd_string[cmd], bank);
end else if (out_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Enable = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Output Enable = %d", $time, cmd_string[cmd], bank, out_en);
end
end
2 : begin
// High Temperature Self Refresh rate
if (!addr[7]) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d High Temperature Self Refresh rate = 1X (0C-85C)", $time, cmd_string[cmd], bank);
end else if (addr[7]) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d High Temperature Self Refresh rate = 2X (>85C)", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal High Temperature Self Refresh rate = %d", $time, cmd_string[cmd], bank, addr[7]);
end
if ((addr & ~(1<<7)) !== 0) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
3 : begin
if (addr !== 0) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
endcase
init_mode_reg[bank] = 1;
ck_load_mode <= ck_cntr;
end
end
REFRESH : begin
if (|active_bank) begin
$display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s", $time, cmd_string[cmd]);
er_trfc_max = 0;
ref_cntr = ref_cntr + 1;
tm_refresh <= $time;
end
end
PRECHARGE : begin
if (addr[AP]) begin
// tRPA timing applies when the PRECHARGE (ALL) command is issued, regardless of
// the number of banks already open or closed.
for (i=0; i<`BANKS; i=i+1) begin
for (j=0; j<NOP; j=j+1) begin
chk_err(1'b0, i, j, cmd);
chk_err(1'b1, i, j, cmd);
end
chk_err(1'b0, i, PWR_DOWN, cmd);
chk_err(1'b0, i, SELF_REF, cmd);
end
if (|auto_precharge_bank) begin
$display ("%m: at time %t ERROR: %s All Failure. Auto Precharge is scheduled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s All", $time, cmd_string[cmd]);
active_bank = 0;
tm_precharge_all <= $time;
end
end else begin
// A PRECHARGE command is allowed if there is no open row in that bank (idle state)
// or if the previously open row is already in the process of precharging.
// However, the precharge period will be determined by the last PRECHARGE command issued to the bank.
if (auto_precharge_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d", $time, cmd_string[cmd], bank);
active_bank[bank] = 1'b0;
tm_bank_precharge[bank] <= $time;
tm_precharge <= $time;
end
end
end
ACTIVATE : begin
if (`BANKS == 8) begin
tfaw_cntr = 0;
for (i=0; i<`BANKS; i=i+1) begin
if ($time - tm_bank_activate[i] < TFAW) begin
tfaw_cntr = tfaw_cntr + 1;
end
end
if (tfaw_cntr > 3) begin
$display ("%m: at time %t ERROR: tFAW violation during %s to bank %d", $time, cmd_string[cmd], bank);
end
end
if (!init_done) begin
$display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (active_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Bank %d must be Precharged.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (addr >= 1<<ROW_BITS) begin
$display ("%m: at time %t WARNING: row = %h does not exist. Maximum row = %h", $time, addr, (1<<ROW_BITS)-1);
end
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d row %h", $time, cmd_string[cmd], bank, addr);
active_bank[bank] = 1'b1;
active_row[bank] = addr;
tm_bank_activate[bank] <= $time;
tm_activate <= $time;
end
end
WRITE : begin
if (!init_done) begin
$display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!active_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Bank %d must be Activated.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (auto_precharge_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if ((ck_cntr - ck_write < burst_length/2) && (ck_cntr - ck_write)%2) begin
$display ("%m: at time %t ERROR: %s Failure. Illegal burst interruption.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (addr[AP]) begin
auto_precharge_bank[bank] = 1'b1;
write_precharge_bank[bank] = 1'b1;
end
col = ((addr>>1) & -1*(1<<AP)) | (addr & {AP{1'b1}});
if (col >= 1<<COL_BITS) begin
$display ("%m: at time %t WARNING: col = %h does not exist. Maximum col = %h", $time, col, (1<<COL_BITS)-1);
end
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
wr_pipeline[2*write_latency + 1] = 1;
ba_pipeline[2*write_latency + 1] = bank;
row_pipeline[2*write_latency + 1] = active_row[bank];
col_pipeline[2*write_latency + 1] = col;
ck_bank_write[bank] <= ck_cntr;
ck_write <= ck_cntr;
end
end
READ : begin
if (!dll_locked)
$display ("%m: at time %t WARNING: %s prior to DLL locked. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters.", $time, cmd_string[cmd]);
if (!init_done) begin
$display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!active_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Bank %d must be Activated.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (auto_precharge_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if ((ck_cntr - ck_read < burst_length/2) && (ck_cntr - ck_read)%2) begin
$display ("%m: at time %t ERROR: %s Failure. Illegal burst interruption.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (addr[AP]) begin
auto_precharge_bank[bank] = 1'b1;
read_precharge_bank[bank] = 1'b1;
end
col = ((addr>>1) & -1*(1<<AP)) | (addr & {AP{1'b1}});
if (col >= 1<<COL_BITS) begin
$display ("%m: at time %t WARNING: col = %h does not exist. Maximum col = %h", $time, col, (1<<COL_BITS)-1);
end
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
rd_pipeline[2*read_latency - 1] = 1;
ba_pipeline[2*read_latency - 1] = bank;
row_pipeline[2*read_latency - 1] = active_row[bank];
col_pipeline[2*read_latency - 1] = col;
ck_bank_read[bank] <= ck_cntr;
ck_read <= ck_cntr;
end
end
NOP: begin
if (in_power_down) begin
if (DEBUG) $display ("%m: at time %t INFO: Power Down Exit", $time);
in_power_down = 0;
if (|active_bank & low_power) begin // slow exit active power down
ck_slow_exit_pd <= ck_cntr;
end
ck_power_down <= ck_cntr;
end
if (in_self_refresh) begin
if ($time - tm_cke < TISXR)
$display ("%m: at time %t ERROR: tISXR violation during Self Refresh Exit", $time);
if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Exit", $time);
in_self_refresh = 0;
ck_dll_reset <= ck_cntr;
ck_self_refresh <= ck_cntr;
tm_self_refresh <= $time;
tm_refresh <= $time;
end
end
endcase
if ((prev_cke !== 1) && (cmd !== NOP)) begin
$display ("%m: at time %t ERROR: NOP or Deselect is required when CKE goes active.", $time);
end
if (!init_done) begin
case (init_step)
0 : begin
if ($time < 200000000)
$display ("%m: at time %t WARNING: 200 us is required before CKE goes active.", $time);
// if (cmd_chk + 200000000 > $time)
// $display("%m: at time %t WARNING: NOP or DESELECT is required for 200 us before CKE is brought high", $time);
init_step = init_step + 1;
end
1 : if (dll_en) init_step = init_step + 1;
2 : begin
if (&init_mode_reg && dll_reset) begin
active_bank = {`BANKS{1'b1}}; // require Precharge All or bank Precharges
ref_cntr = 0; // require refresh
init_step = init_step + 1;
end
end
3 : if (ref_cntr == 2) begin
init_step = init_step + 1;
end
4 : if (!dll_reset) init_step = init_step + 1;
5 : if (ocd == 3'b111) init_step = init_step + 1;
6 : begin
if (ocd == 3'b000) begin
if (DEBUG) $display ("%m: at time %t INFO: Initialization Sequence is complete", $time);
init_done = 1;
end
end
endcase
end
end else if (prev_cke) begin
if ((!init_done) && (init_step > 1)) begin
$display ("%m: at time %t ERROR: CKE must remain active until the initialization sequence is complete.", $time);
if (STOP_ON_ERROR) $stop(0);
end
case (cmd)
REFRESH : begin
for (j=0; j<NOP; j=j+1) begin
chk_err(1'b0, bank, j, SELF_REF);
end
chk_err(1'b0, bank, PWR_DOWN, SELF_REF);
chk_err(1'b0, bank, SELF_REF, SELF_REF);
if (|active_bank) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. All banks must be Precharged.", $time);
if (STOP_ON_ERROR) $stop(0);
init_done = 0;
end else if (odt_en && odt_state) begin
$display ("%m: at time %t ERROR: ODT must be off prior to entering Self Refresh", $time);
if (STOP_ON_ERROR) $stop(0);
init_done = 0;
end else if (!init_done) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. Initialization sequence is not complete.", $time);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Enter", $time);
in_self_refresh = 1;
dll_locked = 0;
end
end
NOP : begin
// entering slow_exit or precharge power down and tANPD has not been satisfied
if ((low_power || (active_bank == 0)) && (ck_cntr - ck_odt < TANPD))
$display ("%m: at time %t WARNING: tANPD violation during %s. Synchronous or asynchronous change in termination resistance is possible.", $time, cmd_string[PWR_DOWN]);
for (j=0; j<NOP; j=j+1) begin
chk_err(1'b0, bank, j, PWR_DOWN);
end
chk_err(1'b0, bank, PWR_DOWN, PWR_DOWN);
chk_err(1'b0, bank, SELF_REF, PWR_DOWN);
if (!init_done) begin
$display ("%m: at time %t ERROR: Power Down Failure. Initialization sequence is not complete.", $time);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) begin
if (|active_bank) begin
$display ("%m: at time %t INFO: Active Power Down Enter", $time);
end else begin
$display ("%m: at time %t INFO: Precharge Power Down Enter", $time);
end
end
in_power_down = 1;
end
end
default : begin
$display ("%m: at time %t ERROR: NOP, Deselect, or Refresh is required when CKE goes inactive.", $time);
init_done = 0;
end
endcase
if (!init_done) begin
if (DEBUG) $display ("%m: at time %t WARNING: Reset has occurred. Device must be re-initialized.", $time);
reset_task;
end
end
prev_cke = cke;
end
endtask
task data_task;
reg [BA_BITS-1:0] bank;
reg [ROW_BITS-1:0] row;
reg [COL_BITS-1:0] col;
integer i;
integer j;
begin
if (diff_ck) begin
for (i=0; i<36; i=i+1) begin
if (dq_in_valid && dll_locked && ($time - tm_dqs_neg[i] < $rtoi(TDSS*tck_avg)))
$display ("%m: at time %t ERROR: tDSS violation on %s bit %d", $time, dqs_string[i/18], i%18);
if (check_write_dqs_high[i])
$display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period.", $time, dqs_string[i/18], i%18);
end
check_write_dqs_high <= 0;
end else begin
for (i=0; i<36; i=i+1) begin
if (dll_locked && dq_in_valid) begin
tm_tdqss = abs_value(1.0*tm_ck_pos - tm_dqss_pos[i]);
if ((tm_tdqss < tck_avg/2.0) && (tm_tdqss > TDQSS*tck_avg))
$display ("%m: at time %t ERROR: tDQSS violation on %s bit %d", $time, dqs_string[i/18], i%18);
end
if (check_write_dqs_low[i])
$display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period", $time, dqs_string[i/18], i%18);
end
check_write_preamble <= 0;
check_write_postamble <= 0;
check_write_dqs_low <= 0;
end
if (wr_pipeline[0] || rd_pipeline[0]) begin
bank = ba_pipeline[0];
row = row_pipeline[0];
col = col_pipeline[0];
burst_cntr = 0;
memory_read(bank, row, col, memory_data);
end
// burst counter
if (burst_cntr < burst_length) begin
burst_position = col ^ burst_cntr;
if (!burst_order) begin
burst_position[BO_BITS-1:0] = col + burst_cntr;
end
burst_cntr = burst_cntr + 1;
end
// write dqs counter
if (wr_pipeline[WDQS_PRE + 1]) begin
wdqs_cntr = WDQS_PRE + burst_length + WDQS_PST - 1;
end
// write dqs
if ((wdqs_cntr == burst_length + WDQS_PST) && (wdq_cntr == 0)) begin //write preamble
check_write_preamble <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}};
end
if (wdqs_cntr > 1) begin // write data
if ((wdqs_cntr - WDQS_PST)%2) begin
check_write_dqs_high <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}};
end else begin
check_write_dqs_low <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}};
end
end
if (wdqs_cntr == WDQS_PST) begin // write postamble
check_write_postamble <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}};
end
if (wdqs_cntr > 0) begin
wdqs_cntr = wdqs_cntr - 1;
end
// write dq
if (dq_in_valid) begin // write data
bit_mask = 0;
if (diff_ck) begin
for (i=0; i<DM_BITS; i=i+1) begin
bit_mask = bit_mask | ({`DQ_PER_DQS{~dm_in_neg[i]}}<<(burst_position*DQ_BITS + i*`DQ_PER_DQS));
end
memory_data = (dq_in_neg<<(burst_position*DQ_BITS) & bit_mask) | (memory_data & ~bit_mask);
end else begin
for (i=0; i<DM_BITS; i=i+1) begin
bit_mask = bit_mask | ({`DQ_PER_DQS{~dm_in_pos[i]}}<<(burst_position*DQ_BITS + i*`DQ_PER_DQS));
end
memory_data = (dq_in_pos<<(burst_position*DQ_BITS) & bit_mask) | (memory_data & ~bit_mask);
end
dq_temp = memory_data>>(burst_position*DQ_BITS);
if (DEBUG) $display ("%m: at time %t INFO: WRITE @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp);
if (burst_cntr%BL_MIN == 0) begin
memory_write(bank, row, col, memory_data);
end
end
if (wr_pipeline[1]) begin
wdq_cntr = burst_length;
end
if (wdq_cntr > 0) begin
wdq_cntr = wdq_cntr - 1;
dq_in_valid = 1'b1;
end else begin
dq_in_valid = 1'b0;
dqs_in_valid <= 1'b0;
for (i=0; i<36; i=i+1) begin
wdqs_pos_cntr[i] <= 0;
end
end
if (wr_pipeline[0]) begin
b2b_write <= 1'b0;
end
if (wr_pipeline[2]) begin
if (dqs_in_valid) begin
b2b_write <= 1'b1;
end
dqs_in_valid <= 1'b1;
end
// read dqs enable counter
if (rd_pipeline[RDQSEN_PRE]) begin
rdqsen_cntr = RDQSEN_PRE + burst_length + RDQSEN_PST - 1;
end
if (rdqsen_cntr > 0) begin
rdqsen_cntr = rdqsen_cntr - 1;
dqs_out_en = 1'b1;
end else begin
dqs_out_en = 1'b0;
end
// read dqs counter
if (rd_pipeline[RDQS_PRE]) begin
rdqs_cntr = RDQS_PRE + burst_length + RDQS_PST - 1;
end
// read dqs
if ((rdqs_cntr >= burst_length + RDQS_PST) && (rdq_cntr == 0)) begin //read preamble
dqs_out = 1'b0;
end else if (rdqs_cntr > RDQS_PST) begin // read data
dqs_out = rdqs_cntr - RDQS_PST;
end else if (rdqs_cntr > 0) begin // read postamble
dqs_out = 1'b0;
end else begin
dqs_out = 1'b1;
end
if (rdqs_cntr > 0) begin
rdqs_cntr = rdqs_cntr - 1;
end
// read dq enable counter
if (rd_pipeline[RDQEN_PRE]) begin
rdqen_cntr = RDQEN_PRE + burst_length + RDQEN_PST;
end
if (rdqen_cntr > 0) begin
rdqen_cntr = rdqen_cntr - 1;
dq_out_en = 1'b1;
end else begin
dq_out_en = 1'b0;
end
// read dq
if (rd_pipeline[0]) begin
rdq_cntr = burst_length;
end
if (rdq_cntr > 0) begin // read data
dq_temp = memory_data>>(burst_position*DQ_BITS);
dq_out = dq_temp;
if (DEBUG) $display ("%m: at time %t INFO: READ @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp);
rdq_cntr = rdq_cntr - 1;
end else begin
dq_out = {DQ_BITS{1'b1}};
end
// delay signals prior to output
if (RANDOM_OUT_DELAY && (dqs_out_en || |dqs_out_en_dly || dq_out_en || |dq_out_en_dly)) begin
for (i=0; i<DQS_BITS; i=i+1) begin
// DQSCK requirements
// 1.) less than tDQSCK
// 2.) greater than -tDQSCK
// 3.) cannot change more than tQHS + tDQSQ from previous DQS edge
dqsck_max = TDQSCK;
if (dqsck_max > dqsck[i] + TQHS + TDQSQ) begin
dqsck_max = dqsck[i] + TQHS + TDQSQ;
end
dqsck_min = -1*TDQSCK;
if (dqsck_min < dqsck[i] - TQHS - TDQSQ) begin
dqsck_min = dqsck[i] - TQHS - TDQSQ;
end
// DQSQ requirements
// 1.) less than tAC - DQSCK
// 2.) less than tDQSQ
// 3.) greater than -tAC
// 4.) greater than tQH from previous DQS edge
dqsq_min = -1*TAC;
if (dqsq_min < dqsck[i] - TQHS) begin
dqsq_min = dqsck[i] - TQHS;
end
if (dqsck_min == dqsck_max) begin
dqsck[i] = dqsck_min;
end else begin
dqsck[i] = $dist_uniform(seed, dqsck_min, dqsck_max);
end
dqsq_max = TAC;
if (dqsq_max > TDQSQ + dqsck[i]) begin
dqsq_max = TDQSQ + dqsck[i];
end
dqs_out_en_dly[i] <= #(tck_avg/2.0 + ($random % TAC)) dqs_out_en;
dqs_out_dly[i] <= #(tck_avg/2.0 + dqsck[i]) dqs_out;
for (j=0; j<`DQ_PER_DQS; j=j+1) begin
if (dq_out_en) begin // tLZ2
dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + $dist_uniform(seed, -2*TAC, dqsq_max)) dq_out_en;
end else begin // tHZ
dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + ($random % TAC)) dq_out_en;
end
if (dqsq_min == dqsq_max) begin
dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + dqsq_min) dq_out[i*`DQ_PER_DQS + j];
end else begin
dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + $dist_uniform(seed, dqsq_min, dqsq_max)) dq_out[i*`DQ_PER_DQS + j];
end
end
end
end else begin
out_delay = tck_avg/2.0;
dqs_out_en_dly <= #(out_delay) {DQS_BITS{dqs_out_en}};
dqs_out_dly <= #(out_delay) {DQS_BITS{dqs_out }};
dq_out_en_dly <= #(out_delay) {DQ_BITS {dq_out_en }};
dq_out_dly <= #(out_delay) {DQ_BITS {dq_out }};
end
end
endtask
always @(diff_ck) begin : main
integer i;
if (!in_self_refresh && (diff_ck !== 1'b0) && (diff_ck !== 1'b1))
$display ("%m: at time %t ERROR: CK and CK_N are not allowed to go to an unknown state.", $time);
data_task;
if (diff_ck) begin
// check setup of command signals
if ($time > TIS) begin
if ($time - tm_cke < TIS)
$display ("%m: at time %t ERROR: tIS violation on CKE by %t", $time, tm_cke + TIS - $time);
if (cke_in) begin
for (i=0; i<22; i=i+1) begin
if ($time - tm_cmd_addr[i] < TIS)
$display ("%m: at time %t ERROR: tIS violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIS - $time);
end
end
end
// update current state
if (!dll_locked && !in_self_refresh && (ck_cntr - ck_dll_reset == TDLLK)) begin
// check CL value against the clock frequency
if (cas_latency*tck_avg < CL_TIME)
$display ("%m: at time %t ERROR: CAS Latency = %d is illegal @tCK(avg) = %f", $time, cas_latency, tck_avg);
// check WR value against the clock frequency
if (write_recovery*tck_avg < TWR)
$display ("%m: at time %t ERROR: Write Recovery = %d is illegal @tCK(avg) = %f", $time, write_recovery, tck_avg);
dll_locked = 1;
end
if (|auto_precharge_bank) begin
for (i=0; i<`BANKS; i=i+1) begin
// Write with Auto Precharge Calculation
// 1. Meet minimum tRAS requirement
// 2. Write Latency PLUS BL/2 cycles PLUS WR after Write command
if (write_precharge_bank[i]
&& ($time - tm_bank_activate[i] >= TRAS_MIN)
&& (ck_cntr - ck_bank_write[i] >= write_latency + burst_length/2 + write_recovery)) begin
if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i);
write_precharge_bank[i] = 0;
active_bank[i] = 0;
auto_precharge_bank[i] = 0;
ck_write_ap = ck_cntr;
tm_bank_precharge[i] = $time;
tm_precharge = $time;
end
// Read with Auto Precharge Calculation
// 1. Meet minimum tRAS requirement
// 2. Additive Latency plus BL/2 cycles after Read command
// 3. tRTP after the last 4-bit prefetch
if (read_precharge_bank[i]
&& ($time - tm_bank_activate[i] >= TRAS_MIN)
&& (ck_cntr - ck_bank_read[i] >= additive_latency + burst_length/2)) begin
read_precharge_bank[i] = 0;
// In case the internal precharge is pushed out by tRTP, tRP starts at the point where
// the internal precharge happens (not at the next rising clock edge after this event).
if ($time - tm_bank_read_end[i] < TRTP) begin
if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", tm_bank_read_end[i] + TRTP, i);
active_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0;
auto_precharge_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0;
tm_bank_precharge[i] <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP;
tm_precharge <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP;
end else begin
if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i);
active_bank[i] = 0;
auto_precharge_bank[i] = 0;
tm_bank_precharge[i] = $time;
tm_precharge = $time;
end
end
end
end
// respond to incoming command
if (cke_in ^ prev_cke) begin
ck_cke <= ck_cntr;
end
cmd_task(cke_in, cmd_n_in, ba_in, addr_in);
if ((cmd_n_in == WRITE) || (cmd_n_in == READ)) begin
al_pipeline[2*additive_latency] = 1'b1;
end
if (al_pipeline[0]) begin
// check tRCD after additive latency
if ($time - tm_bank_activate[ba_pipeline[2*cas_latency - 1]] < TRCD) begin
if (rd_pipeline[2*cas_latency - 1]) begin
$display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[READ]);
end else begin
$display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[WRITE]);
end
end
// check tWTR after additive latency
if (rd_pipeline[2*cas_latency - 1]) begin
if ($time - tm_write_end < TWTR)
$display ("%m: at time %t ERROR: tWTR violation during %s", $time, cmd_string[READ]);
end
end
if (rd_pipeline[2*(cas_latency - burst_length/2 + 2) - 1]) begin
tm_bank_read_end[ba_pipeline[2*(cas_latency - burst_length/2 + 2) - 1]] <= $time;
end
for (i=0; i<`BANKS; i=i+1) begin
if ((ck_cntr - ck_bank_write[i] > write_latency) && (ck_cntr - ck_bank_write[i] <= write_latency + burst_length/2)) begin
tm_bank_write_end[i] <= $time;
tm_write_end <= $time;
end
end
// clk pin is disabled during self refresh
if (!in_self_refresh) begin
tjit_cc_time = $time - tm_ck_pos - tck_i;
tck_i = $time - tm_ck_pos;
tck_avg = tck_avg - tck_sample[ck_cntr%TDLLK]/$itor(TDLLK);
tck_avg = tck_avg + tck_i/$itor(TDLLK);
tck_sample[ck_cntr%TDLLK] = tck_i;
tjit_per_rtime = tck_i - tck_avg;
if (dll_locked) begin
// check accumulated error
terr_nper_rtime = 0;
for (i=0; i<50; i=i+1) begin
terr_nper_rtime = terr_nper_rtime + tck_sample[i] - tck_avg;
terr_nper_rtime = abs_value(terr_nper_rtime);
case (i)
0 :;
1 : if (terr_nper_rtime - TERR_2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(2per) violation by %f ps.", $time, terr_nper_rtime - TERR_2PER);
2 : if (terr_nper_rtime - TERR_3PER >= 1.0) $display ("%m: at time %t ERROR: tERR(3per) violation by %f ps.", $time, terr_nper_rtime - TERR_3PER);
3 : if (terr_nper_rtime - TERR_4PER >= 1.0) $display ("%m: at time %t ERROR: tERR(4per) violation by %f ps.", $time, terr_nper_rtime - TERR_4PER);
4 : if (terr_nper_rtime - TERR_5PER >= 1.0) $display ("%m: at time %t ERROR: tERR(5per) violation by %f ps.", $time, terr_nper_rtime - TERR_5PER);
5,6,7,8,9 : if (terr_nper_rtime - TERR_N1PER >= 1.0) $display ("%m: at time %t ERROR: tERR(n1per) violation by %f ps.", $time, terr_nper_rtime - TERR_N1PER);
default : if (terr_nper_rtime - TERR_N2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(n2per) violation by %f ps.", $time, terr_nper_rtime - TERR_N2PER);
endcase
end
// check tCK min/max/jitter
if (abs_value(tjit_per_rtime) - TJIT_PER >= 1.0)
$display ("%m: at time %t ERROR: tJIT(per) violation by %f ps.", $time, abs_value(tjit_per_rtime) - TJIT_PER);
if (abs_value(tjit_cc_time) - TJIT_CC >= 1.0)
$display ("%m: at time %t ERROR: tJIT(cc) violation by %f ps.", $time, abs_value(tjit_cc_time) - TJIT_CC);
if (TCK_MIN - tck_avg >= 1.0)
$display ("%m: at time %t ERROR: tCK(avg) minimum violation by %f ps.", $time, TCK_MIN - tck_avg);
if (tck_avg - TCK_MAX >= 1.0)
$display ("%m: at time %t ERROR: tCK(avg) maximum violation by %f ps.", $time, tck_avg - TCK_MAX);
if (tm_ck_pos + TCK_MIN - TJIT_PER > $time)
$display ("%m: at time %t ERROR: tCK(abs) minimum violation by %t", $time, tm_ck_pos + TCK_MIN - TJIT_PER - $time);
if (tm_ck_pos + TCK_MAX + TJIT_PER < $time)
$display ("%m: at time %t ERROR: tCK(abs) maximum violation by %t", $time, $time - tm_ck_pos - TCK_MAX - TJIT_PER);
// check tCL
if (tm_ck_neg + TCL_MIN*tck_avg - TJIT_DUTY > $time)
$display ("%m: at time %t ERROR: tCL(abs) minimum violation on CLK by %t", $time, tm_ck_neg + TCL_MIN*tck_avg - TJIT_DUTY - $time);
if (tm_ck_neg + TCL_MAX*tck_avg + TJIT_DUTY < $time)
$display ("%m: at time %t ERROR: tCL(abs) maximum violation on CLK by %t", $time, $time - tm_ck_neg - TCL_MAX*tck_avg - TJIT_DUTY);
if (tcl_avg < TCL_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCL(avg) minimum violation on CLK by %t", $time, TCL_MIN*tck_avg - tcl_avg);
if (tcl_avg > TCL_MAX*tck_avg)
$display ("%m: at time %t ERROR: tCL(avg) maximum violation on CLK by %t", $time, tcl_avg - TCL_MAX*tck_avg);
end
// calculate the tch avg jitter
tch_avg = tch_avg - tch_sample[ck_cntr%TDLLK]/$itor(TDLLK);
tch_avg = tch_avg + tch_i/$itor(TDLLK);
tch_sample[ck_cntr%TDLLK] = tch_i;
// update timers/counters
tcl_i <= $time - tm_ck_neg;
end
prev_odt <= odt_in;
// update timers/counters
ck_cntr <= ck_cntr + 1;
tm_ck_pos <= $time;
end else begin
// clk pin is disabled during self refresh
if (!in_self_refresh) begin
if (dll_locked) begin
if (tm_ck_pos + TCH_MIN*tck_avg - TJIT_DUTY > $time)
$display ("%m: at time %t ERROR: tCH(abs) minimum violation on CLK by %t", $time, tm_ck_pos + TCH_MIN*tck_avg - TJIT_DUTY + $time);
if (tm_ck_pos + TCH_MAX*tck_avg + TJIT_DUTY < $time)
$display ("%m: at time %t ERROR: tCH(abs) maximum violation on CLK by %t", $time, $time - tm_ck_pos - TCH_MAX*tck_avg - TJIT_DUTY);
if (tch_avg < TCH_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCH(avg) minimum violation on CLK by %t", $time, TCH_MIN*tck_avg - tch_avg);
if (tch_avg > TCH_MAX*tck_avg)
$display ("%m: at time %t ERROR: tCH(avg) maximum violation on CLK by %t", $time, tch_avg - TCH_MAX*tck_avg);
end
// calculate the tcl avg jitter
tcl_avg = tcl_avg - tcl_sample[ck_cntr%TDLLK]/$itor(TDLLK);
tcl_avg = tcl_avg + tcl_i/$itor(TDLLK);
tcl_sample[ck_cntr%TDLLK] = tcl_i;
// update timers/counters
tch_i <= $time - tm_ck_pos;
end
tm_ck_neg <= $time;
end
// on die termination
if (odt_en) begin
// clk pin is disabled during self refresh
if (!in_self_refresh && diff_ck) begin
if ($time - tm_odt < TIS) begin
$display ("%m: at time %t ERROR: tIS violation on ODT by %t", $time, tm_odt + TIS - $time);
end
if (prev_odt ^ odt_in) begin
if (!dll_locked)
$display ("%m: at time %t WARNING: tDLLK violation during ODT transition.", $time);
if (odt_in && ($time - tm_odt_en < TMOD))
$display ("%m: at time %t ERROR: tMOD violation during ODT transition", $time);
if ($time - tm_self_refresh < TXSNR)
$display ("%m: at time %t ERROR: tXSNR violation during ODT transition", $time);
if (in_self_refresh)
$display ("%m: at time %t ERROR: Illegal ODT transition during Self Refresh.", $time);
// async ODT mode applies:
// 1.) during active power down with slow exit
// 2.) during precharge power down
// 3.) if tANPD has not been satisfied
// 4.) until tAXPD has been satisfied
if ((in_power_down && (low_power || (active_bank == 0))) || (ck_cntr - ck_slow_exit_pd < TAXPD)) begin
if (ck_cntr - ck_slow_exit_pd < TAXPD)
$display ("%m: at time %t WARNING: tAXPD violation during ODT transition. Synchronous or asynchronous change in termination resistance is possible.", $time);
if (odt_in) begin
if (DEBUG) $display ("%m: at time %t INFO: Async On Die Termination = %d", $time + TAONPD, 1'b1);
odt_state <= #(TAONPD) 1'b1;
end else begin
if (DEBUG) $display ("%m: at time %t INFO: Async On Die Termination = %d", $time + TAOFPD, 1'b0);
odt_state <= #(TAOFPD) 1'b0;
end
// sync ODT mode applies:
// 1.) during normal operation
// 2.) during active power down with fast exit
end else begin
if (odt_in) begin
i = TAOND*2;
odt_pipeline[i] = 1'b1;
end else begin
i = TAOFD*2;
odt_pipeline[i] = 1'b1;
end
end
ck_odt <= ck_cntr;
end
end
if (odt_pipeline[0]) begin
odt_state = ~odt_state;
if (DEBUG) $display ("%m: at time %t INFO: Sync On Die Termination = %d", $time, odt_state);
end
end
// shift pipelines
if (|wr_pipeline || |rd_pipeline || |al_pipeline) begin
al_pipeline = al_pipeline>>1;
wr_pipeline = wr_pipeline>>1;
rd_pipeline = rd_pipeline>>1;
for (i=0; i<`MAX_PIPE; i=i+1) begin
ba_pipeline[i] = ba_pipeline[i+1];
row_pipeline[i] = row_pipeline[i+1];
col_pipeline[i] = col_pipeline[i+1];
end
end
if (|odt_pipeline) begin
odt_pipeline = odt_pipeline>>1;
end
end
// receiver(s)
task dqs_even_receiver;
input [4:0] i;
reg [71:0] bit_mask;
begin
bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS);
if (dqs_even[i]) begin
if (rdqs_en) begin // rdqs disables dm
dm_in_pos[i] = 1'b0;
end else begin
dm_in_pos[i] = dm_in[i];
end
dq_in_pos = (dq_in & bit_mask) | (dq_in_pos & ~bit_mask);
end
end
endtask
always @(posedge dqs_even[ 0]) dqs_even_receiver( 0);
always @(posedge dqs_even[ 1]) dqs_even_receiver( 1);
always @(posedge dqs_even[ 2]) dqs_even_receiver( 2);
always @(posedge dqs_even[ 3]) dqs_even_receiver( 3);
always @(posedge dqs_even[ 4]) dqs_even_receiver( 4);
always @(posedge dqs_even[ 5]) dqs_even_receiver( 5);
always @(posedge dqs_even[ 6]) dqs_even_receiver( 6);
always @(posedge dqs_even[ 7]) dqs_even_receiver( 7);
always @(posedge dqs_even[ 8]) dqs_even_receiver( 8);
always @(posedge dqs_even[ 9]) dqs_even_receiver( 9);
always @(posedge dqs_even[10]) dqs_even_receiver(10);
always @(posedge dqs_even[11]) dqs_even_receiver(11);
always @(posedge dqs_even[12]) dqs_even_receiver(12);
always @(posedge dqs_even[13]) dqs_even_receiver(13);
always @(posedge dqs_even[14]) dqs_even_receiver(14);
always @(posedge dqs_even[15]) dqs_even_receiver(15);
always @(posedge dqs_even[16]) dqs_even_receiver(16);
always @(posedge dqs_even[17]) dqs_even_receiver(17);
task dqs_odd_receiver;
input [4:0] i;
reg [71:0] bit_mask;
begin
bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS);
if (dqs_odd[i]) begin
if (rdqs_en) begin // rdqs disables dm
dm_in_neg[i] = 1'b0;
end else begin
dm_in_neg[i] = dm_in[i];
end
dq_in_neg = (dq_in & bit_mask) | (dq_in_neg & ~bit_mask);
end
end
endtask
always @(posedge dqs_odd[ 0]) dqs_odd_receiver( 0);
always @(posedge dqs_odd[ 1]) dqs_odd_receiver( 1);
always @(posedge dqs_odd[ 2]) dqs_odd_receiver( 2);
always @(posedge dqs_odd[ 3]) dqs_odd_receiver( 3);
always @(posedge dqs_odd[ 4]) dqs_odd_receiver( 4);
always @(posedge dqs_odd[ 5]) dqs_odd_receiver( 5);
always @(posedge dqs_odd[ 6]) dqs_odd_receiver( 6);
always @(posedge dqs_odd[ 7]) dqs_odd_receiver( 7);
always @(posedge dqs_odd[ 8]) dqs_odd_receiver( 8);
always @(posedge dqs_odd[ 9]) dqs_odd_receiver( 9);
always @(posedge dqs_odd[10]) dqs_odd_receiver(10);
always @(posedge dqs_odd[11]) dqs_odd_receiver(11);
always @(posedge dqs_odd[12]) dqs_odd_receiver(12);
always @(posedge dqs_odd[13]) dqs_odd_receiver(13);
always @(posedge dqs_odd[14]) dqs_odd_receiver(14);
always @(posedge dqs_odd[15]) dqs_odd_receiver(15);
always @(posedge dqs_odd[16]) dqs_odd_receiver(16);
always @(posedge dqs_odd[17]) dqs_odd_receiver(17);
// Processes to check hold and pulse width of control signals
always @(cke_in) begin
if ($time > TIH) begin
if ($time - tm_ck_pos < TIH)
$display ("%m: at time %t ERROR: tIH violation on CKE by %t", $time, tm_ck_pos + TIH - $time);
end
if (dll_locked && ($time - tm_cke < $rtoi(TIPW*tck_avg)))
$display ("%m: at time %t ERROR: tIPW violation on CKE by %t", $time, tm_cke + TIPW*tck_avg - $time);
tm_cke = $time;
end
always @(odt_in) begin
if (odt_en && !in_self_refresh) begin
if ($time - tm_ck_pos < TIH)
$display ("%m: at time %t ERROR: tIH violation on ODT by %t", $time, tm_ck_pos + TIH - $time);
if (dll_locked && ($time - tm_odt < $rtoi(TIPW*tck_avg)))
$display ("%m: at time %t ERROR: tIPW violation on ODT by %t", $time, tm_odt + TIPW*tck_avg - $time);
end
tm_odt = $time;
end
task cmd_addr_timing_check;
input i;
reg [4:0] i;
begin
if (prev_cke) begin
if ((i == 0) && ($time - tm_ck_pos < TIH)) // Always check tIH for CS#
$display ("%m: at time %t ERROR: tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time);
if ((i > 0) && (cs_n_in == 1'b0) && ($time - tm_ck_pos < TIH)) // Only check tIH for cmd_addr if CS# low
$display ("%m: at time %t ERROR: tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time);
if (dll_locked && ($time - tm_cmd_addr[i] < $rtoi(TIPW*tck_avg)))
$display ("%m: at time %t ERROR: tIPW violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIPW*tck_avg - $time);
end
tm_cmd_addr[i] = $time;
end
endtask
always @(cs_n_in ) cmd_addr_timing_check( 0);
always @(ras_n_in ) cmd_addr_timing_check( 1);
always @(cas_n_in ) cmd_addr_timing_check( 2);
always @(we_n_in ) cmd_addr_timing_check( 3);
always @(ba_in [ 0]) cmd_addr_timing_check( 4);
always @(ba_in [ 1]) cmd_addr_timing_check( 5);
always @(ba_in [ 2]) cmd_addr_timing_check( 6);
always @(addr_in[ 0]) cmd_addr_timing_check( 7);
always @(addr_in[ 1]) cmd_addr_timing_check( 8);
always @(addr_in[ 2]) cmd_addr_timing_check( 9);
always @(addr_in[ 3]) cmd_addr_timing_check(10);
always @(addr_in[ 4]) cmd_addr_timing_check(11);
always @(addr_in[ 5]) cmd_addr_timing_check(12);
always @(addr_in[ 6]) cmd_addr_timing_check(13);
always @(addr_in[ 7]) cmd_addr_timing_check(14);
always @(addr_in[ 8]) cmd_addr_timing_check(15);
always @(addr_in[ 9]) cmd_addr_timing_check(16);
always @(addr_in[10]) cmd_addr_timing_check(17);
always @(addr_in[11]) cmd_addr_timing_check(18);
always @(addr_in[12]) cmd_addr_timing_check(19);
always @(addr_in[13]) cmd_addr_timing_check(20);
always @(addr_in[14]) cmd_addr_timing_check(21);
always @(addr_in[15]) cmd_addr_timing_check(22);
// Processes to check setup and hold of data signals
task dm_timing_check;
input i;
reg [4:0] i;
begin
if (dqs_in_valid) begin
if ($time - tm_dqs[i] < TDH)
$display ("%m: at time %t ERROR: tDH violation on DM bit %d by %t", $time, i, tm_dqs[i] + TDH - $time);
if (check_dm_tdipw[i]) begin
if (dll_locked && ($time - tm_dm[i] < $rtoi(TDIPW*tck_avg)))
$display ("%m: at time %t ERROR: tDIPW violation on DM bit %d by %t", $time, i, tm_dm[i] + TDIPW*tck_avg - $time);
end
end
check_dm_tdipw[i] <= 1'b0;
tm_dm[i] = $time;
end
endtask
always @(dm_in[ 0]) dm_timing_check( 0);
always @(dm_in[ 1]) dm_timing_check( 1);
always @(dm_in[ 2]) dm_timing_check( 2);
always @(dm_in[ 3]) dm_timing_check( 3);
always @(dm_in[ 4]) dm_timing_check( 4);
always @(dm_in[ 5]) dm_timing_check( 5);
always @(dm_in[ 6]) dm_timing_check( 6);
always @(dm_in[ 7]) dm_timing_check( 7);
always @(dm_in[ 8]) dm_timing_check( 8);
always @(dm_in[ 9]) dm_timing_check( 9);
always @(dm_in[10]) dm_timing_check(10);
always @(dm_in[11]) dm_timing_check(11);
always @(dm_in[12]) dm_timing_check(12);
always @(dm_in[13]) dm_timing_check(13);
always @(dm_in[14]) dm_timing_check(14);
always @(dm_in[15]) dm_timing_check(15);
always @(dm_in[16]) dm_timing_check(16);
always @(dm_in[17]) dm_timing_check(17);
task dq_timing_check;
input i;
reg [6:0] i;
begin
if (dqs_in_valid) begin
if ($time - tm_dqs[i/`DQ_PER_DQS] < TDH)
$display ("%m: at time %t ERROR: tDH violation on DQ bit %d by %t", $time, i, tm_dqs[i/`DQ_PER_DQS] + TDH - $time);
if (check_dq_tdipw[i]) begin
if (dll_locked && ($time - tm_dq[i] < $rtoi(TDIPW*tck_avg)))
$display ("%m: at time %t ERROR: tDIPW violation on DQ bit %d by %t", $time, i, tm_dq[i] + TDIPW*tck_avg - $time);
end
end
check_dq_tdipw[i] <= 1'b0;
tm_dq[i] = $time;
end
endtask
always @(dq_in[ 0]) dq_timing_check( 0);
always @(dq_in[ 1]) dq_timing_check( 1);
always @(dq_in[ 2]) dq_timing_check( 2);
always @(dq_in[ 3]) dq_timing_check( 3);
always @(dq_in[ 4]) dq_timing_check( 4);
always @(dq_in[ 5]) dq_timing_check( 5);
always @(dq_in[ 6]) dq_timing_check( 6);
always @(dq_in[ 7]) dq_timing_check( 7);
always @(dq_in[ 8]) dq_timing_check( 8);
always @(dq_in[ 9]) dq_timing_check( 9);
always @(dq_in[10]) dq_timing_check(10);
always @(dq_in[11]) dq_timing_check(11);
always @(dq_in[12]) dq_timing_check(12);
always @(dq_in[13]) dq_timing_check(13);
always @(dq_in[14]) dq_timing_check(14);
always @(dq_in[15]) dq_timing_check(15);
always @(dq_in[16]) dq_timing_check(16);
always @(dq_in[17]) dq_timing_check(17);
always @(dq_in[18]) dq_timing_check(18);
always @(dq_in[19]) dq_timing_check(19);
always @(dq_in[20]) dq_timing_check(20);
always @(dq_in[21]) dq_timing_check(21);
always @(dq_in[22]) dq_timing_check(22);
always @(dq_in[23]) dq_timing_check(23);
always @(dq_in[24]) dq_timing_check(24);
always @(dq_in[25]) dq_timing_check(25);
always @(dq_in[26]) dq_timing_check(26);
always @(dq_in[27]) dq_timing_check(27);
always @(dq_in[28]) dq_timing_check(28);
always @(dq_in[29]) dq_timing_check(29);
always @(dq_in[30]) dq_timing_check(30);
always @(dq_in[31]) dq_timing_check(31);
always @(dq_in[32]) dq_timing_check(32);
always @(dq_in[33]) dq_timing_check(33);
always @(dq_in[34]) dq_timing_check(34);
always @(dq_in[35]) dq_timing_check(35);
always @(dq_in[36]) dq_timing_check(36);
always @(dq_in[37]) dq_timing_check(37);
always @(dq_in[38]) dq_timing_check(38);
always @(dq_in[39]) dq_timing_check(39);
always @(dq_in[40]) dq_timing_check(40);
always @(dq_in[41]) dq_timing_check(41);
always @(dq_in[42]) dq_timing_check(42);
always @(dq_in[43]) dq_timing_check(43);
always @(dq_in[44]) dq_timing_check(44);
always @(dq_in[45]) dq_timing_check(45);
always @(dq_in[46]) dq_timing_check(46);
always @(dq_in[47]) dq_timing_check(47);
always @(dq_in[48]) dq_timing_check(48);
always @(dq_in[49]) dq_timing_check(49);
always @(dq_in[50]) dq_timing_check(50);
always @(dq_in[51]) dq_timing_check(51);
always @(dq_in[52]) dq_timing_check(52);
always @(dq_in[53]) dq_timing_check(53);
always @(dq_in[54]) dq_timing_check(54);
always @(dq_in[55]) dq_timing_check(55);
always @(dq_in[56]) dq_timing_check(56);
always @(dq_in[57]) dq_timing_check(57);
always @(dq_in[58]) dq_timing_check(58);
always @(dq_in[59]) dq_timing_check(59);
always @(dq_in[60]) dq_timing_check(60);
always @(dq_in[61]) dq_timing_check(61);
always @(dq_in[62]) dq_timing_check(62);
always @(dq_in[63]) dq_timing_check(63);
always @(dq_in[64]) dq_timing_check(64);
always @(dq_in[65]) dq_timing_check(65);
always @(dq_in[66]) dq_timing_check(66);
always @(dq_in[67]) dq_timing_check(67);
always @(dq_in[68]) dq_timing_check(68);
always @(dq_in[69]) dq_timing_check(69);
always @(dq_in[70]) dq_timing_check(70);
always @(dq_in[71]) dq_timing_check(71);
task dqs_pos_timing_check;
input i;
reg [5:0] i;
reg [3:0] j;
begin
if (dqs_in_valid && ((wdqs_pos_cntr[i] < burst_length/2) || b2b_write) && (dqs_n_en || i<18)) begin
if (dqs_in[i] ^ prev_dqs_in[i]) begin
if (dll_locked) begin
if (check_write_preamble[i]) begin
if ($time - tm_dqs_neg[i] < $rtoi(TWPRE*tck_avg))
$display ("%m: at time %t ERROR: tWPRE violation on &s bit %d", $time, dqs_string[i/18], i%18);
end else if (check_write_postamble[i]) begin
if ($time - tm_dqs_neg[i] < $rtoi(TWPST*tck_avg))
$display ("%m: at time %t ERROR: tWPST violation on %s bit %d", $time, dqs_string[i/18], i%18);
end else begin
if ($time - tm_dqs_neg[i] < $rtoi(TDQSL*tck_avg))
$display ("%m: at time %t ERROR: tDQSL violation on %s bit %d", $time, dqs_string[i/18], i%18);
end
end
if ($time - tm_dm[i%18] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%18] + TDS - $time);
if (!dq_out_en) begin
for (j=0; j<`DQ_PER_DQS; j=j+1) begin
if ($time - tm_dq[i*`DQ_PER_DQS+j] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[i*`DQ_PER_DQS+j] + TDS - $time);
check_dq_tdipw[i*`DQ_PER_DQS+j] <= 1'b1;
end
end
if ((wdqs_pos_cntr[i] < burst_length/2) && !b2b_write) begin
wdqs_pos_cntr[i] <= wdqs_pos_cntr[i] + 1;
end else begin
wdqs_pos_cntr[i] <= 1;
end
check_dm_tdipw[i%18] <= 1'b1;
check_write_preamble[i] <= 1'b0;
check_write_postamble[i] <= 1'b0;
check_write_dqs_low[i] <= 1'b0;
tm_dqs[i%18] <= $time;
end else begin
$display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/18], i%18);
end
end
tm_dqss_pos[i] <= $time;
tm_dqs_pos[i] = $time;
prev_dqs_in[i] <= dqs_in[i];
end
endtask
always @(posedge dqs_in[ 0]) dqs_pos_timing_check( 0);
always @(posedge dqs_in[ 1]) dqs_pos_timing_check( 1);
always @(posedge dqs_in[ 2]) dqs_pos_timing_check( 2);
always @(posedge dqs_in[ 3]) dqs_pos_timing_check( 3);
always @(posedge dqs_in[ 4]) dqs_pos_timing_check( 4);
always @(posedge dqs_in[ 5]) dqs_pos_timing_check( 5);
always @(posedge dqs_in[ 6]) dqs_pos_timing_check( 6);
always @(posedge dqs_in[ 7]) dqs_pos_timing_check( 7);
always @(posedge dqs_in[ 8]) dqs_pos_timing_check( 8);
always @(posedge dqs_in[ 9]) dqs_pos_timing_check( 9);
always @(posedge dqs_in[10]) dqs_pos_timing_check(10);
always @(posedge dqs_in[11]) dqs_pos_timing_check(11);
always @(posedge dqs_in[12]) dqs_pos_timing_check(12);
always @(posedge dqs_in[13]) dqs_pos_timing_check(13);
always @(posedge dqs_in[14]) dqs_pos_timing_check(14);
always @(posedge dqs_in[15]) dqs_pos_timing_check(15);
always @(posedge dqs_in[16]) dqs_pos_timing_check(16);
always @(posedge dqs_in[17]) dqs_pos_timing_check(17);
always @(negedge dqs_in[18]) dqs_pos_timing_check(18);
always @(negedge dqs_in[19]) dqs_pos_timing_check(19);
always @(negedge dqs_in[20]) dqs_pos_timing_check(20);
always @(negedge dqs_in[21]) dqs_pos_timing_check(21);
always @(negedge dqs_in[22]) dqs_pos_timing_check(22);
always @(negedge dqs_in[23]) dqs_pos_timing_check(23);
always @(negedge dqs_in[24]) dqs_pos_timing_check(24);
always @(negedge dqs_in[25]) dqs_pos_timing_check(25);
always @(negedge dqs_in[26]) dqs_pos_timing_check(26);
always @(negedge dqs_in[27]) dqs_pos_timing_check(27);
always @(negedge dqs_in[28]) dqs_pos_timing_check(28);
always @(negedge dqs_in[29]) dqs_pos_timing_check(29);
always @(negedge dqs_in[30]) dqs_pos_timing_check(30);
always @(negedge dqs_in[31]) dqs_pos_timing_check(31);
always @(negedge dqs_in[32]) dqs_neg_timing_check(32);
always @(negedge dqs_in[33]) dqs_neg_timing_check(33);
always @(negedge dqs_in[34]) dqs_neg_timing_check(34);
always @(negedge dqs_in[35]) dqs_neg_timing_check(35);
task dqs_neg_timing_check;
input i;
reg [5:0] i;
reg [3:0] j;
begin
if (dqs_in_valid && (wdqs_pos_cntr[i] > 0) && check_write_dqs_high[i] && (dqs_n_en || i < 18)) begin
if (dqs_in[i] ^ prev_dqs_in[i]) begin
if (dll_locked) begin
if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg))
$display ("%m: at time %t ERROR: tDQSH violation on %s bit %d", $time, dqs_string[i/18], i%18);
if ($time - tm_ck_pos < $rtoi(TDSH*tck_avg))
$display ("%m: at time %t ERROR: tDSH violation on %s bit %d", $time, dqs_string[i/18], i%18);
end
if ($time - tm_dm[i%18] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%18] + TDS - $time);
if (!dq_out_en) begin
for (j=0; j<`DQ_PER_DQS; j=j+1) begin
if ($time - tm_dq[i*`DQ_PER_DQS+j] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[i*`DQ_PER_DQS+j] + TDS - $time);
check_dq_tdipw[i*`DQ_PER_DQS+j] <= 1'b1;
end
end
check_dm_tdipw[i%18] <= 1'b1;
check_write_dqs_high[i] <= 1'b0;
tm_dqs[i%18] <= $time;
end else begin
$display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/18], i%18);
end
end
tm_dqs_neg[i] = $time;
prev_dqs_in[i] <= dqs_in[i];
end
endtask
always @(negedge dqs_in[ 0]) dqs_neg_timing_check( 0);
always @(negedge dqs_in[ 1]) dqs_neg_timing_check( 1);
always @(negedge dqs_in[ 2]) dqs_neg_timing_check( 2);
always @(negedge dqs_in[ 3]) dqs_neg_timing_check( 3);
always @(negedge dqs_in[ 4]) dqs_neg_timing_check( 4);
always @(negedge dqs_in[ 5]) dqs_neg_timing_check( 5);
always @(negedge dqs_in[ 6]) dqs_neg_timing_check( 6);
always @(negedge dqs_in[ 7]) dqs_neg_timing_check( 7);
always @(negedge dqs_in[ 8]) dqs_neg_timing_check( 8);
always @(negedge dqs_in[ 9]) dqs_neg_timing_check( 9);
always @(negedge dqs_in[10]) dqs_neg_timing_check(10);
always @(negedge dqs_in[11]) dqs_neg_timing_check(11);
always @(negedge dqs_in[12]) dqs_neg_timing_check(12);
always @(negedge dqs_in[13]) dqs_neg_timing_check(13);
always @(negedge dqs_in[14]) dqs_neg_timing_check(14);
always @(negedge dqs_in[15]) dqs_neg_timing_check(15);
always @(negedge dqs_in[16]) dqs_neg_timing_check(16);
always @(negedge dqs_in[17]) dqs_neg_timing_check(17);
always @(posedge dqs_in[18]) dqs_neg_timing_check(18);
always @(posedge dqs_in[19]) dqs_neg_timing_check(19);
always @(posedge dqs_in[20]) dqs_neg_timing_check(20);
always @(posedge dqs_in[21]) dqs_neg_timing_check(21);
always @(posedge dqs_in[22]) dqs_neg_timing_check(22);
always @(posedge dqs_in[23]) dqs_neg_timing_check(23);
always @(posedge dqs_in[24]) dqs_neg_timing_check(24);
always @(posedge dqs_in[25]) dqs_neg_timing_check(25);
always @(posedge dqs_in[26]) dqs_neg_timing_check(26);
always @(posedge dqs_in[27]) dqs_neg_timing_check(27);
always @(posedge dqs_in[28]) dqs_neg_timing_check(28);
always @(posedge dqs_in[29]) dqs_neg_timing_check(29);
always @(posedge dqs_in[30]) dqs_neg_timing_check(30);
always @(posedge dqs_in[31]) dqs_neg_timing_check(31);
always @(posedge dqs_in[32]) dqs_neg_timing_check(32);
always @(posedge dqs_in[33]) dqs_neg_timing_check(33);
always @(posedge dqs_in[34]) dqs_neg_timing_check(34);
always @(posedge dqs_in[35]) dqs_neg_timing_check(35);
endmodule
|
///////////////////////////////////////////////////////
// Copyright (c) 1995/2012 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 14.5
// \ \ Description :
// / /
// /__/ /\ Filename : ICAPE3.v
// \ \ / \
// \__\/\__ \
//
// Revision:
// 10/31/12 - Initial version.
// 02/10/14 - Fixed GSR deassertion (CR 772626).
// 02/28/14 - Updated timing (CR 778416).
// 05/28/14 - New simulation library message format.
// End Revision
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module ICAPE3 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [31:0] DEVICE_ID = 32'h03628093,
parameter ICAP_AUTO_SWITCH = "DISABLE",
parameter SIM_CFG_FILE_NAME = "NONE"
)(
output AVAIL,
output [31:0] O,
output PRDONE,
output PRERROR,
input CLK,
input CSIB,
input [31:0] I,
input RDWRB
);
localparam ICAP_WIDTH = "X32";
wire cso_b;
reg prog_b;
reg init_b;
reg [3:0] bw = 4'b0000;
wire busy_out;
reg cs_bi = 0, rdwr_bi = 0;
wire cs_b_t;
wire clk_in;
wire rdwr_b_t;
wire [31:0] dix;
wire dangle;
reg [31:0] di;
reg [31:0] data_rbt;
reg [7:0] tmp_byte0;
reg [7:0] tmp_byte1;
reg [7:0] tmp_byte2;
reg [7:0] tmp_byte3;
reg icap_idone = 0;
reg clk_osc = 0;
reg sim_file_flag;
integer icap_fd;
reg notifier;
reg AVAIL_reg = 1'b0;
wire delay_CLK;
wire delay_CSIB;
wire delay_RDWRB;
wire [31:0] delay_I;
tri1 p_up;
tri init_tri = (icap_idone == 0) ? init_b : p_up;
tri (weak1, strong0) done_o = p_up;
tri (pull1, supply0) [31:0] di_t = (icap_idone == 1 && delay_RDWRB == 1)? 32'bz : dix;
localparam MODULE_NAME = "ICAPE3";
`ifndef XIL_TIMING
assign delay_I = I;
assign delay_RDWRB = RDWRB;
assign delay_CLK = CLK;
assign delay_CSIB = CSIB;
`endif
assign dix = (icap_idone == 1) ? delay_I : di;
assign cs_b_t = (icap_idone == 1) ? delay_CSIB : cs_bi;
assign clk_in = (icap_idone == 1) ? delay_CLK : clk_osc;
assign rdwr_b_t = (icap_idone == 1) ? delay_RDWRB : rdwr_bi;
assign O = (icap_idone == 1 && delay_RDWRB == 1) ? di_t : 32'b0;
assign AVAIL = AVAIL_reg;
always @(posedge icap_idone)
AVAIL_reg = 1'b1;
always
// if (icap_idone == 0)
#1000 clk_osc <= ~clk_osc;
always @(delay_CSIB or delay_RDWRB)
if ($time > 1 && icap_idone == 0) begin
$display ("Warning: [Unisim %s-1] ICAPE3 at time %t has not finished initialization. A message will be printed after the initialization. User need start read/write operation after that. Instance: %m", MODULE_NAME, $time);
end
SIM_CONFIGE3 #(
.DEVICE_ID(DEVICE_ID),
.ICAP_SUPPORT("TRUE"),
.ICAP_WIDTH(ICAP_WIDTH)
)
SIM_CONFIGE3_INST (
.AVAIL(dangle),
.PRDONE(PRDONE),
.PRERROR(PRERROR),
.CSOB(cso_b),
.DONE(done_o),
.CCLK(clk_in),
.CSB(cs_b_t),
.D(di_t),
.INITB(init_tri),
.M(3'b110),
.PROGB(prog_b),
.RDWRB(rdwr_b_t)
);
initial begin
case (ICAP_AUTO_SWITCH)
"DISABLE", "ENABLE" : ;
default : begin
$display("Error: [Unisim %s-102] ICAP_AUTO_SWITCH attribute is set to %s. Legal values for this attribute are DISABLE or ENABLE. Instance: %m", MODULE_NAME, ICAP_AUTO_SWITCH);
$finish;
end
endcase
icap_idone = 0;
sim_file_flag = 0;
if (SIM_CFG_FILE_NAME == "NONE") begin
sim_file_flag = 1;
end
else begin
icap_fd = $fopen(SIM_CFG_FILE_NAME, "r");
if (icap_fd == 0)
begin
$display("Error: [Unisim %s-2] The configure rbt data file %s was not found. Use the SIM_CFG_FILE_NAME parameter to pass the file name. Instance: %m", MODULE_NAME, SIM_CFG_FILE_NAME);
sim_file_flag = 1;
end
end
init_b = 1;
prog_b = 1;
rdwr_bi = 0;
cs_bi = 1;
#600000;
@(posedge clk_in)
prog_b = 0;
@(negedge clk_in)
init_b = 0;
#600000;
@(posedge clk_in)
prog_b = 1;
@(negedge clk_in) begin
init_b = 1;
cs_bi = 0;
end
if (sim_file_flag == 0) begin
while ($fscanf(icap_fd, "%b", data_rbt) != -1) begin
if (done_o == 0) begin
tmp_byte3 = bit_revers8(data_rbt[31:24]);
tmp_byte2 = bit_revers8(data_rbt[23:16]);
tmp_byte1 = bit_revers8(data_rbt[15:8]);
tmp_byte0 = bit_revers8(data_rbt[7:0]);
if (bw == 4'b0000) begin
@(negedge clk_in)
di = {24'b0, tmp_byte3};
@(negedge clk_in)
di = {24'b0, tmp_byte2};
@(negedge clk_in)
di = {24'b0, tmp_byte1};
@(negedge clk_in)
di = {24'b0, tmp_byte0};
end
else if (bw == 4'b0010) begin
@(negedge clk_in)
di = {16'b0, tmp_byte3, tmp_byte2};
@(negedge clk_in)
di = {16'b0, tmp_byte1, tmp_byte0};
end
else if (bw == 4'b0011) begin
@(negedge clk_in)
di = {tmp_byte3, tmp_byte2, tmp_byte1, tmp_byte0};
end
end
else begin
@(negedge clk_in);
di = 32'hFFFFFFFF;
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
if (icap_idone == 0) begin
$display ("Info: [Unisim %s-3] ICAPE3 at time %t has finished initialization. User can start read/write operation. Instance: %m", MODULE_NAME, $time);
icap_idone = 1;
end
end
end
$fclose(icap_fd);
#1000;
end
else begin
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'h000000DD;
@(negedge clk_in) begin
if (bw == 4'b0000)
di = 32'h00000088;
else if (bw == 4'b0010)
di = 32'h00000044;
else if (bw == 4'b0011)
di = 32'h00000022;
end
rbt_data_wr(32'hFFFFFFFF);
rbt_data_wr(32'hFFFFFFFF);
rbt_data_wr(32'hAA995566);
rbt_data_wr(32'h30008001);
rbt_data_wr(32'h00000005);
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
if (icap_idone == 0) begin
$display ("Info: [Unisim %s-4] ICAPE3 at time %t has finished initialization. User can start read/write operation. Instance: %m", MODULE_NAME, $time);
icap_idone = 1;
end
#1000;
end
end
task rbt_data_wr;
input [31:0] dat_rbt;
reg [7:0] tp_byte3;
reg [7:0] tp_byte2;
reg [7:0] tp_byte1;
reg [7:0] tp_byte0;
begin
tp_byte3 = bit_revers8(dat_rbt[31:24]);
tp_byte2 = bit_revers8(dat_rbt[23:16]);
tp_byte1 = bit_revers8(dat_rbt[15:8]);
tp_byte0 = bit_revers8(dat_rbt[7:0]);
if (bw == 4'b0000) begin
@(negedge clk_in)
di = {24'b0, tp_byte3};
@(negedge clk_in)
di = {24'b0, tp_byte2};
@(negedge clk_in)
di = {24'b0, tp_byte1};
@(negedge clk_in)
di = {24'b0, tp_byte0};
end
else if (bw == 4'b0010) begin
@(negedge clk_in)
di = {16'b0, tp_byte3, tp_byte2};
@(negedge clk_in)
di = {16'b0, tp_byte1, tp_byte0};
end
else if (bw == 4'b0011) begin
@(negedge clk_in)
di = {tp_byte3, tp_byte2, tp_byte1, tp_byte0};
end
end
endtask
function [7:0] bit_revers8;
input [7:0] din8;
begin
bit_revers8[0] = din8[7];
bit_revers8[1] = din8[6];
bit_revers8[2] = din8[5];
bit_revers8[3] = din8[4];
bit_revers8[4] = din8[3];
bit_revers8[5] = din8[2];
bit_revers8[6] = din8[1];
bit_revers8[7] = din8[0];
end
endfunction
specify
(CLK *> O) = (100:100:100, 100:100:100);
(CLK => PRDONE) = (100:100:100, 100:100:100);
(CLK => PRERROR) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (posedge CLK, 0:0:0, notifier);
$period (negedge CLK, 0:0:0, notifier);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
$setuphold (posedge CLK, negedge CSIB, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_CSIB);
$setuphold (posedge CLK, posedge CSIB, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_CSIB);
$setuphold (posedge CLK, negedge I, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_I);
$setuphold (posedge CLK, posedge I, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_I);
$setuphold (posedge CLK, negedge RDWRB, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_RDWRB);
$setuphold (posedge CLK, posedge RDWRB, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_RDWRB);
`endif //
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
// -- (c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// AXI data fifo module:
// 5-channel memory-mapped AXI4 interfaces.
// SRL or BRAM based FIFO on AXI W and/or R channels.
// FIFO to accommodate various data flow rates through the AXI interconnect
//
// Verilog-standard: Verilog 2001
//-----------------------------------------------------------------------------
//
// Structure:
// axi_data_fifo
// fifo_generator
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_data_fifo_v2_1_axi_data_fifo #
(
parameter C_FAMILY = "virtex7",
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_WRITE_FIFO_DEPTH = 0, // Range: (0, 32, 512)
parameter C_AXI_WRITE_FIFO_TYPE = "lut", // "lut" = LUT (SRL) based,
// "bram" = BRAM based
parameter integer C_AXI_WRITE_FIFO_DELAY = 0, // 0 = No, 1 = Yes
// Indicates whether AWVALID and WVALID assertion is delayed until:
// a. the corresponding WLAST is stored in the FIFO, or
// b. no WLAST is stored and the FIFO is full.
// 0 means AW channel is pass-through and
// WVALID is asserted whenever FIFO is not empty.
parameter integer C_AXI_READ_FIFO_DEPTH = 0, // Range: (0, 32, 512)
parameter C_AXI_READ_FIFO_TYPE = "lut", // "lut" = LUT (SRL) based,
// "bram" = BRAM based
parameter integer C_AXI_READ_FIFO_DELAY = 0) // 0 = No, 1 = Yes
// Indicates whether ARVALID assertion is delayed until the
// the remaining vacancy of the FIFO is at least the burst length
// as indicated by ARLEN.
// 0 means AR channel is pass-through.
// System Signals
(input wire aclk,
input wire aresetn,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input wire s_axi_awvalid,
output wire s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input wire s_axi_wvalid,
output wire s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output wire s_axi_bvalid,
input wire s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input wire s_axi_arvalid,
output wire s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output wire m_axi_awvalid,
input wire m_axi_awready,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output wire m_axi_wvalid,
input wire m_axi_wready,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input wire m_axi_bvalid,
output wire m_axi_bready,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output wire m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input wire m_axi_rvalid,
output wire m_axi_rready);
localparam integer P_WIDTH_RACH = 4+4+3+4+2+3+((C_AXI_PROTOCOL==1)?6:9)+C_AXI_ADDR_WIDTH+C_AXI_ID_WIDTH+C_AXI_ARUSER_WIDTH;
localparam integer P_WIDTH_WACH = 4+4+3+4+2+3+((C_AXI_PROTOCOL==1)?6:9)+C_AXI_ADDR_WIDTH+C_AXI_ID_WIDTH+C_AXI_AWUSER_WIDTH;
localparam integer P_WIDTH_RDCH = 1 + 2 + C_AXI_DATA_WIDTH + C_AXI_ID_WIDTH + C_AXI_RUSER_WIDTH;
localparam integer P_WIDTH_WDCH = 1+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8+((C_AXI_PROTOCOL==1)?C_AXI_ID_WIDTH:0)+C_AXI_WUSER_WIDTH;
localparam integer P_WIDTH_WRCH = 2 + C_AXI_ID_WIDTH + C_AXI_BUSER_WIDTH;
localparam P_PRIM_FIFO_TYPE = "512x72" ;
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
localparam integer P_WRITE_FIFO_DEPTH_LOG = (C_AXI_WRITE_FIFO_DEPTH > 1) ? f_ceil_log2(C_AXI_WRITE_FIFO_DEPTH) : 1;
localparam integer P_READ_FIFO_DEPTH_LOG = (C_AXI_READ_FIFO_DEPTH > 1) ? f_ceil_log2(C_AXI_READ_FIFO_DEPTH) : 1;
// Ceiling of log2(x)
function integer f_ceil_log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
f_ceil_log2 = acc;
end
endfunction
generate
if (((C_AXI_WRITE_FIFO_DEPTH == 0) && (C_AXI_READ_FIFO_DEPTH == 0)) || (C_AXI_PROTOCOL == P_AXILITE)) begin : gen_bypass
assign m_axi_awid = s_axi_awid;
assign m_axi_awaddr = s_axi_awaddr;
assign m_axi_awlen = s_axi_awlen;
assign m_axi_awsize = s_axi_awsize;
assign m_axi_awburst = s_axi_awburst;
assign m_axi_awlock = s_axi_awlock;
assign m_axi_awcache = s_axi_awcache;
assign m_axi_awprot = s_axi_awprot;
assign m_axi_awregion = s_axi_awregion;
assign m_axi_awqos = s_axi_awqos;
assign m_axi_awuser = s_axi_awuser;
assign m_axi_awvalid = s_axi_awvalid;
assign s_axi_awready = m_axi_awready;
assign m_axi_wid = s_axi_wid;
assign m_axi_wdata = s_axi_wdata;
assign m_axi_wstrb = s_axi_wstrb;
assign m_axi_wlast = s_axi_wlast;
assign m_axi_wuser = s_axi_wuser;
assign m_axi_wvalid = s_axi_wvalid;
assign s_axi_wready = m_axi_wready;
assign s_axi_bid = m_axi_bid;
assign s_axi_bresp = m_axi_bresp;
assign s_axi_buser = m_axi_buser;
assign s_axi_bvalid = m_axi_bvalid;
assign m_axi_bready = s_axi_bready;
assign m_axi_arid = s_axi_arid;
assign m_axi_araddr = s_axi_araddr;
assign m_axi_arlen = s_axi_arlen;
assign m_axi_arsize = s_axi_arsize;
assign m_axi_arburst = s_axi_arburst;
assign m_axi_arlock = s_axi_arlock;
assign m_axi_arcache = s_axi_arcache;
assign m_axi_arprot = s_axi_arprot;
assign m_axi_arregion = s_axi_arregion;
assign m_axi_arqos = s_axi_arqos;
assign m_axi_aruser = s_axi_aruser;
assign m_axi_arvalid = s_axi_arvalid;
assign s_axi_arready = m_axi_arready;
assign s_axi_rid = m_axi_rid;
assign s_axi_rdata = m_axi_rdata;
assign s_axi_rresp = m_axi_rresp;
assign s_axi_rlast = m_axi_rlast;
assign s_axi_ruser = m_axi_ruser;
assign s_axi_rvalid = m_axi_rvalid;
assign m_axi_rready = s_axi_rready;
end else begin : gen_fifo
wire [4-1:0] s_axi_awregion_i;
wire [4-1:0] s_axi_arregion_i;
wire [4-1:0] m_axi_awregion_i;
wire [4-1:0] m_axi_arregion_i;
wire [C_AXI_ID_WIDTH-1:0] s_axi_wid_i;
wire [C_AXI_ID_WIDTH-1:0] m_axi_wid_i;
assign s_axi_awregion_i = (C_AXI_PROTOCOL == P_AXI3) ? 4'b0 : s_axi_awregion;
assign s_axi_arregion_i = (C_AXI_PROTOCOL == P_AXI3) ? 4'b0 : s_axi_arregion;
assign m_axi_awregion = (C_AXI_PROTOCOL == P_AXI3) ? 4'b0 : m_axi_awregion_i;
assign m_axi_arregion = (C_AXI_PROTOCOL == P_AXI3) ? 4'b0 : m_axi_arregion_i;
assign s_axi_wid_i = (C_AXI_PROTOCOL == P_AXI3) ? s_axi_wid : {C_AXI_ID_WIDTH{1'b0}};
assign m_axi_wid = (C_AXI_PROTOCOL == P_AXI3) ? m_axi_wid_i : {C_AXI_ID_WIDTH{1'b0}};
fifo_generator_v12_0 #(
.C_INTERFACE_TYPE(2),
.C_AXI_TYPE((C_AXI_PROTOCOL == P_AXI4) ? 1 : 3),
.C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),
.C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),
.C_HAS_AXI_ID(1),
.C_AXI_LEN_WIDTH((C_AXI_PROTOCOL == P_AXI4) ? 8 : 4),
.C_AXI_LOCK_WIDTH((C_AXI_PROTOCOL == P_AXI4) ? 1 : 2),
.C_HAS_AXI_ARUSER(1),
.C_HAS_AXI_AWUSER(1),
.C_HAS_AXI_BUSER(1),
.C_HAS_AXI_RUSER(1),
.C_HAS_AXI_WUSER(1),
.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),
.C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),
.C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),
.C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH),
.C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),
.C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),
.C_DIN_WIDTH_RACH(P_WIDTH_RACH),
.C_DIN_WIDTH_RDCH(P_WIDTH_RDCH),
.C_DIN_WIDTH_WACH(P_WIDTH_WACH),
.C_DIN_WIDTH_WDCH(P_WIDTH_WDCH),
.C_DIN_WIDTH_WRCH(P_WIDTH_WDCH),
.C_RACH_TYPE(((C_AXI_READ_FIFO_DEPTH != 0) && C_AXI_READ_FIFO_DELAY) ? 0 : 2),
.C_WACH_TYPE(((C_AXI_WRITE_FIFO_DEPTH != 0) && C_AXI_WRITE_FIFO_DELAY) ? 0 : 2),
.C_WDCH_TYPE((C_AXI_WRITE_FIFO_DEPTH != 0) ? 0 : 2),
.C_RDCH_TYPE((C_AXI_READ_FIFO_DEPTH != 0) ? 0 : 2),
.C_WRCH_TYPE(2),
.C_COMMON_CLOCK(1),
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(C_AXI_READ_FIFO_DELAY ? 1 : 0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(C_AXI_WRITE_FIFO_DELAY ? 1 : 0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(10),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(18),
.C_DIN_WIDTH_AXIS(1),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(18),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY(C_FAMILY),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_RD_CHANNEL(1),
.C_HAS_AXI_WR_CHANNEL(1),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(2),
.C_IMPLEMENTATION_TYPE_RDCH((C_AXI_READ_FIFO_TYPE == "bram") ? 1 : 2),
.C_IMPLEMENTATION_TYPE_WACH(2),
.C_IMPLEMENTATION_TYPE_WDCH((C_AXI_WRITE_FIFO_TYPE == "bram") ? 1 : 2),
.C_IMPLEMENTATION_TYPE_WRCH(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE(P_PRIM_FIFO_TYPE),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(30),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(510),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(30),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(510),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(14),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(1022),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(31),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(511),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(31),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(511),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(15),
.C_PROG_FULL_THRESH_NEGATE_VAL(1021),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RD_DATA_COUNT_WIDTH(10),
.C_RD_DEPTH(1024),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(10),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(10),
.C_WR_DEPTH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(32),
.C_WR_DEPTH_RDCH(C_AXI_READ_FIFO_DEPTH),
.C_WR_DEPTH_WACH(32),
.C_WR_DEPTH_WDCH(C_AXI_WRITE_FIFO_DEPTH),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(5),
.C_WR_PNTR_WIDTH_RDCH((C_AXI_READ_FIFO_DEPTH> 1) ? f_ceil_log2(C_AXI_READ_FIFO_DEPTH) : 1),
.C_WR_PNTR_WIDTH_WACH(5),
.C_WR_PNTR_WIDTH_WDCH((C_AXI_WRITE_FIFO_DEPTH > 1) ? f_ceil_log2(C_AXI_WRITE_FIFO_DEPTH) : 1),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1)
)
fifo_gen_inst (
.s_aclk(aclk),
.s_aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awregion(s_axi_awregion_i),
.s_axi_awuser(s_axi_awuser),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid_i),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(m_axi_awqos),
.m_axi_awregion(m_axi_awregion_i),
.m_axi_awuser(m_axi_awuser),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(m_axi_wid_i),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_arregion(s_axi_arregion_i),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(m_axi_arqos),
.m_axi_arregion(m_axi_arregion_i),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready),
.m_aclk(aclk),
.m_aclk_en(1'b1),
.s_aclk_en(1'b1),
.s_axi_wuser(s_axi_wuser),
.s_axi_buser(s_axi_buser),
.m_axi_wuser(m_axi_wuser),
.m_axi_buser(m_axi_buser),
.s_axi_aruser(s_axi_aruser),
.s_axi_ruser(s_axi_ruser),
.m_axi_aruser(m_axi_aruser),
.m_axi_ruser(m_axi_ruser),
.almost_empty(),
.almost_full(),
.axis_data_count(),
.axis_dbiterr(),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(),
.axis_prog_empty(),
.axis_prog_empty_thresh(10'b0),
.axis_prog_full(),
.axis_prog_full_thresh(10'b0),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_underflow(),
.axis_wr_data_count(),
.axi_ar_data_count(),
.axi_ar_dbiterr(),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(),
.axi_ar_prog_empty(),
.axi_ar_prog_empty_thresh(5'b0),
.axi_ar_prog_full(),
.axi_ar_prog_full_thresh(5'b0),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_underflow(),
.axi_ar_wr_data_count(),
.axi_aw_data_count(),
.axi_aw_dbiterr(),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(),
.axi_aw_prog_empty(),
.axi_aw_prog_empty_thresh(5'b0),
.axi_aw_prog_full(),
.axi_aw_prog_full_thresh(5'b0),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_underflow(),
.axi_aw_wr_data_count(),
.axi_b_data_count(),
.axi_b_dbiterr(),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(),
.axi_b_prog_empty(),
.axi_b_prog_empty_thresh(4'b0),
.axi_b_prog_full(),
.axi_b_prog_full_thresh(4'b0),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_underflow(),
.axi_b_wr_data_count(),
.axi_r_data_count(),
.axi_r_dbiterr(),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(),
.axi_r_prog_empty(),
.axi_r_prog_empty_thresh({P_READ_FIFO_DEPTH_LOG{1'b0}}),
.axi_r_prog_full(),
.axi_r_prog_full_thresh({P_READ_FIFO_DEPTH_LOG{1'b0}}),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_underflow(),
.axi_r_wr_data_count(),
.axi_w_data_count(),
.axi_w_dbiterr(),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(),
.axi_w_prog_empty(),
.axi_w_prog_empty_thresh({P_WRITE_FIFO_DEPTH_LOG{1'b0}}),
.axi_w_prog_full(),
.axi_w_prog_full_thresh({P_WRITE_FIFO_DEPTH_LOG{1'b0}}),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_underflow(),
.axi_w_wr_data_count(),
.backup(1'b0),
.backup_marker(1'b0),
.clk(1'b0),
.data_count(),
.dbiterr(),
.din(18'b0),
.dout(),
.empty(),
.full(),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_axis_tdata(),
.m_axis_tdest(),
.m_axis_tid(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tready(1'b0),
.m_axis_tstrb(),
.m_axis_tuser(),
.m_axis_tvalid(),
.overflow(),
.prog_empty(),
.prog_empty_thresh(10'b0),
.prog_empty_thresh_assert(10'b0),
.prog_empty_thresh_negate(10'b0),
.prog_full(),
.prog_full_thresh(10'b0),
.prog_full_thresh_assert(10'b0),
.prog_full_thresh_negate(10'b0),
.rd_clk(1'b0),
.rd_data_count(),
.rd_en(1'b0),
.rd_rst(1'b0),
.rst(1'b0),
.sbiterr(),
.srst(1'b0),
.s_axis_tdata(64'b0),
.s_axis_tdest(4'b0),
.s_axis_tid(8'b0),
.s_axis_tkeep(4'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(),
.s_axis_tstrb(4'b0),
.s_axis_tuser(4'b0),
.s_axis_tvalid(1'b0),
.underflow(),
.valid(),
.wr_ack(),
.wr_clk(1'b0),
.wr_data_count(),
.wr_en(1'b0),
.wr_rst(1'b0),
.wr_rst_busy(),
.rd_rst_busy(),
.sleep(1'b0)
);
end
endgenerate
endmodule
|
(*
A dependent decide equality tactic that works with or without axioms on
dependent types.
There are several modes of usage. The default is to use typeclasses when
available, and to avoid usage of axioms. To turn off typeclass search,
re-define the handle_sub_eqdec tactic to idtac (from its
default_handle_sub_eqdec value). To enable axioms re-define one or more of
the tactic aliases: proof_irrelevance_alias, inj_pair2_alias and UIP_alias.
If this is done, the algorithm will prefer axioms to typeclass search, as
axiom usage will be faster and lead to smaller proof terms. Note that
inj_pair2_alias needs some proper definition (other than False).
For typeclasses, sumbool and or are made Existing Classes, so that one can add
Existing Instances like Nat.eq_dec. TBD: if use of Existing Class makes for
wild-goose typeclass search, we could instead use normal Class/Instance with
singleton classes.
*)
Require Import utils.
Require Import block.
Require Import debug.
Require Import paramth.
Require Import sigTgen.
Set Injection On Proofs.
(*Redefine these to their respective symbols as desired:*)
(*Valid values for proof_irrelevance_alias are:*)
(*Coq.Logic.ProofIrrelevance.proof_irrelevance*)
(*False -- disable use of proof irrelevance*)
Ltac proof_irrelevance_alias := False.
(*Valid values for inj_pair2_alias are: *)
(*Coq.Logic.Eqdep.EqdepTheory.inj_pair2 -- uses Coq.Logic.Eqdep.Eq_rect_eq.eq_rect_eq axiom*)
(*Coq.Logic.Eqdep_dec.inj_pair2_eq_dec -- no axiom, subgoals are all eqdecs*)
(*Eqdep_em.inj_pair2_eqem -- no axiom, subgoals are all eqems*)
Ltac inj_pair2_alias := False.
(*Coq.Logic.Eqdep.EqdepTheory.UIP -- uses Coq.Logic.Eqdep.Eq_rect_eq.eq_rect_eq axiom*)
(*Coq.Logic.Eqdep_dec.UIP_dec -- no axiom, subgoals are all eqdecs*)
(*Eqdep_em.UIP_em -- no axiom, subgoals are all eqems*)
(*False -- do not use UIP*)
Ltac UIP_alias := False.
(*Note: it does not work to attempt to pick up inj_pair2 as a hint because its
application is too ambiguous in nested sigT cases, as it must infer a function.*)
Lemma eqdec_implies_eqem : forall T (a b : T), {a=b} + {a<>b} -> a=b \/ a<>b.
Proof.
tauto.
Qed.
Hint Extern 100 (?a = ?b \/ ?a <> ?b) =>
intros; apply eqdec_implies_eqem : typeclass_instances.
(* Why care about "eqem" (equality excluded middle) (a=b \/ a<>b) at all? We
will be able to prove eqdec ({a=b} + {a<>b}) on most types that we can prove
eqem on, and eqded implies eqem trivially (as eqdec_implies_eqem above shows).
However, when using proof relevance, and needing a decision procedure on
proofs, it is not possible to do case analysis on any informative Props when
the goal is eqdec, but it is possible when the goal is eqem. It is also the
case that the theorems in Eqdep_dec (inj_pair2_eq_dec and UIP_dec are used
here) only need eqem, although they currently ask for eqdec (I have a copy of
Eqdep_dec that uses eqem instead). Hence it is possible to use eqem to get
eqdec in more cases - such as when the types of certain fields or indexes only
provide eqem.
*)
(* The "practical theory" behind how this algorithm works:
For an eqdec (or eqem) goal of the form {a=b}+{a<>b} (or a=b \/ a<>b), we
start by doing induction on a using its standard induction scheme. Then we
attempt to destruct b in each subgoal. However...
Inductive types come in two major varieties: those with indexes and those
without. Those with indexes will need a kind of dependent destruction (for b
above), while those without indexes won't. Even the simplist inductive type
with indexes will need it:
Inductive Simp : unit -> Type := simp : Simp tt.
Goal forall u (a b : Simp u), {a=b}+{a<>b}.
intros u a. induction a. Fail destruct b.
This is because the type of a constructor is seen by Coq as dependent on the
constructor itself even in this trivial case where there really is only one
type (Simp tt) in the type family and only one constructor for that type.
So, for such indexed types, we will generalize the conclusion over b and its
type's indexes (recursively), freeing the conclusion from the destructee. But
first, to tie the generalized bs and indexes to the destructee, we will create
dependent equalities between them based on nested sigTs, one level of nesting
for each type index involved.
Once we destruct b with the sigT equality in place, the non-generalized side
of the sigT equalities will be allowed to type-change along with b without
illegally impacting the type of the sigT equality itself.
Before going further, we process any equalities that may have come from fields
of a or b, doing injections on them as needed, subject to the requirement that
these early injections don't require us to prove other eqdecs (or eqems).
Then, we "block" any remaining equalities in the goal, so they don't lead us
astray later (into working to prove other eqdecs or eqems that we really don't
need). We will unblock these just before finishing.
In the dependent destruction case, we then turn our attention to the sigT
equalities - we need to process them in each subgoal so that the eqdec (eqem)
goal becomes about constructors on both sides of the (in)equalities. There
are three tools we use to do injections (which are also used above on the
field equalities, if necessary). One is obviously the injection tactic,
although we wrap it in a way so that it will fail if the injection it does
isn't productive. The second is the inj_pair2_alias theorem, which allows us
to break down the sigT equality one nesting level at a time. The third is a
"deslimer" (Conor McBride's paper "A polynomial testing principle" mentions
"green slime" in reference to non-injective functions that appear in inductive
type indexes) - which cuts through the slime also by using a sub-eqdec (or
sub-eqem) on differences between the "green slime" for a's and b's ctors,
using the fact that the right constructor of a sub-eqdec (or sub-eqem) would
imply that any such difference spotted in the slime at the field level is
truly a difference - and that in turn will allow us to prove the right
constructor of the current eqdec (or eqem) by contradiction, possibly after
doing some more of these injections.
Once we force the current eqdec (eqem) to be about constructors (which we can
determine easily by examining the "b" side to see if "is_var b" succeeds or
not - if it succeeds, then b is not a constructor-based term), we can turn our
attention to the fields of the constructors involved in the conclusion.
Actually, when doing injections, we always try to see if each subgoal can be
solved, as those that obviously discriminate will get done quickly here. But,
on those that are left, we turn our attention to the fields of the now like
constructors. Interestingly, we can re-use the deslimer code to handle the
fields quite nicely - whether or not the fields actually contain any green
slime.
*)
(*
TODO:
- I believe that dependent decide equality will not loop if the
inj_pair2_alias is set properly - this is due to the fact that start_eqdec
does induction and destruction on the elements, else it fails. But, might
generalize_eqdep undo this?
- It might be nice to have a way for users to declare that some green-slime
functions are injective on some args - and by doing so possibly avoid extra
eqdep/eqem obligations. I'm not sure how to do this (somehow with
typeclasses?) or whether it would actually work (maybe all those obligations
would still occur).
- What about functional extensionality and function fields? Currently, we
just leave functional fields alone to generate eqdep/eqem obligations, like:
{f = g} + {f <> g}
but if the functions are known to have extensionality on them, or if
extensionality is globally true (by axiom), then we can do this instead:
{forall x, f x = g x} + {~ forall x, f x = g x}
which, although not an eqdec/eqem, may be more tractable.
*)
(*for hyps we process, either clear them or double-block them so that they get
cleared at the end of this eqdep goal*)
Ltac clear_or_double_block_hyp H :=
clear H || (block_hyp H; block_hyp H) || fail 999 "can't clear or block" H.
Ltac clear_useless_eqs :=
repeat
match goal with
| H : ?A = ?A |- _ =>
clear_or_double_block_hyp H
| H : existT ?P ?p ?x = existT ?P ?p ?y, H' : ?x = ?y |- _ =>
clear_or_double_block_hyp H
| H : existT ?P ?p ?x = existT ?P ?p ?y, H' : ?y = ?x |- _ =>
clear_or_double_block_hyp H
end.
Ltac generalize_indexes term :=
let T := type of term in
let pT := get_paramed_type_head T in
let rec f T :=
lazymatch T with
| pT => idtac
| ?F ?A => generalize A; f F
end in
f T.
(* In order to make sure that existing hyps don't interfere with the
algorithm, we generalize the eqdep goal over the type indexes to remove the
possibility of dependencies between it and any existing hyps. This, however,
means that if the initial eqdep target was specific to a particular
parameterization of the indexes, we will attempt to solve instead one that
might be too general. Consider a type like "Inductive Foo : Set -> Set ..."
where the Set index doesn't change among the ctors - in this case, we will
generalize it and lose the ability to solve it. We allow the user to specify
(by setting genindexes to false) that they don't want indexes generalized -
then they are responsible for doing any necessary generalization themselves in
order to prevent interference *)
Ltac generalize_eqdep genindexes :=
repeat intro;
lazymatch goal with
| |- _ (?a = ?b) (?a <> ?b) =>
generalize a, b;
tryif constr_eq genindexes true
then generalize_indexes a
else idtac
end.
Ltac eqdec_needs_injs :=
lazymatch goal with
| |- _ (_ = ?b) _ => is_var b
end.
Ltac clear_unblocked_eqs :=
repeat
match goal with
| H : _ = _ |- _ => clear H
| H : block.block (block.block (_ = _)) |- _ => clear H (*clear double-blocked ones as well*)
end.
Ltac default_handle_sub_eqdec := try typeclasses eauto.
Ltac handle_sub_eqdec := default_handle_sub_eqdec.
Ltac solve_congruences_directly := discriminate || congruence.
Ltac try_hyp :=
try match goal with
H : _ |- ?G => apply H; assumption
end;
try (apply eqdec_implies_eqem;
match goal with
H : _ |- ?G => apply H; assumption
end).
Ltac solve_equality immediate :=
try solve_congruences_directly;
try (let A := proof_irrelevance_alias in apply A);
(let A := UIP_alias in apply A);
solve_or_defer_sub_eqdec immediate
with solve_or_defer_sub_eqdec immediate :=
repeat intro; subst;
clear_unblocked_eqs; clear_all_blocks; try_hyp;
try (left;
(*left changes the goal, so calling solve_equality is safe:*)
solve_equality immediate);
constr_eq immediate false; handle_sub_eqdec; shelve.
Ltac do_injections immediate := fail 999. (*forward def, redefined below, calls solve_it*)
Ltac solve_it immediate :=
let G := goaltype in
Debug 5 idtac "Debug: solve_it" immediate "on" G;
tryif
lazymatch G with
| False => solve_congruences_directly
| _ <> _ => intro; subst; solve_congruences_directly
| _ = _ => solve_equality immediate
| _ (_ = _) _ =>
try_hyp; constructor; try intro; subst;
(*this call to do_injections, which calls solve_it, is safe due to the
use of constructor above - hence the goal must have changed to a = or
<>:*)
do_injections immediate; fail
end
then idtac
else (Debug 5 idtac "Debug: solve_it" immediate "failed on" G; fail).
(* Why do we call solve_or_defer_sub_eqdec below instead of solve_it? And why
doesn't solve_it call solve_or_defer_sub_eqdec? Note that solve_it will call
do_injections on the left/right parts of an eqdec and won't ever call
handle_sub_eqdec, while solve_or_defer_sub_eqdec won't do injections, but will
call handle_sub_eqdec. The difference is that while on the eqdec we're
currently trying to solve, we call solve_it after possibly simplifying that
goal, but on sub eqdecs created in order to help solve that goal, we
call solve_or_defer_sub_eqdec instead, which may defer it. *)
Ltac deslime pair :=
Debug 4 idtac "Debug: deslime" pair;
lazymatch pair with
| (?A, ?A) => fail
| (?A ?X, ?A ?Y) => deslime (X, Y)
| (?X _, ?Y _) => deslime (X, Y)
| (?X, ?Y) =>
let H := fresh in
first
[assert (X<>Y) as H by solve_it false;
right; contradict H; do_injections false; fail
|assert (X=Y) as H by solve_it false;
force_subst H
|let H' := fresh in
let tX := type of X in
Debug 1 idtac "Debug: deslime obligated sub-eqdec on type" tX "to deslime" pair;
(tryif is_prop
then assert ((X=Y)\/(X<>Y)) as H
else assert ({X=Y}+{X<>Y}) as H);
[|case H; intros H'];
revgoals;
[right; contradict H'; do_injections false; fail
|force_subst H'
|solve_or_defer_sub_eqdec false]
]
end.
Ltac do_subless_sigT_inj H :=
let H' := fresh in
(let A :=inj_pair2_alias in apply A in H as H');
[|assumption..];
Debug 1 let tH := type of H in idtac "Debug: do_subless_sigT_inj applied on" tH.
Ltac do_sigT_inj H immediate :=
first
[do_subless_sigT_inj H
|let subT := fresh in
(*use evar sub:subT to capture sub-eqdec needed by inj_pair2_alias for
re-use. Note that using refine to establish the evar will provoke typeclass
search, which we don't want to do yet.*)
evar (subT : Type);
let sub := fresh in
unshelve evar (sub:subT);subst subT;revgoals;
[(*TBD: note that by using inj_pair2_eqem as inj_pair2_alias, the sub
will be an eqem - which means we will be saving eqems as hyps, which are
not useful for future eqdecs. Hence we may have more work to do.*)
let H' := fresh H in
(let A :=inj_pair2_alias in apply A with (1:=sub) in H as H');
(*make sure this apply did something useful:*)
let tH' := type of H' in
lazymatch tH' with ?A = ?A => fail | _ => idtac end;
revert H';
lazymatch goal with H : tH' |- _ => fail | _ => idtac end;
intro H';
clearbody sub (*else not reusable*)
|solve_or_defer_sub_eqdec immediate]
];
clear_or_double_block_hyp H;
subst.
Ltac block_equalities :=
repeat
lazymatch goal with | H : _ = _ |- _ => block_hyp H end.
Ltac do_one_injection immediate :=
Debug 6 idtac "Debug: do_one_injection" immediate;
match goal with
| H : @eq ?T ?X ?Y |- _ =>
first
[ helpful_injection H
| lazymatch T with
| sigT _ => do_sigT_inj H immediate
| _ => constr_eq immediate false; deslime (X, Y)
end
]
end.
Ltac do_injections immediate ::=
repeat
(subst; (*refine _ here for early typeclass search*)
clear_useless_eqs;
try (try solve_it immediate; do_one_injection immediate)).
Ltac do_eqdec_needed_injs :=
repeat
(eqdec_needs_injs;
clear_useless_eqs;
do_one_injection false;
subst);
try (constructor; solve_it false).
Ltac non_dep_destruct_cleanup :=
intros; subst;
Debug 3 idtac "Debug: non_dep_destruct_cleanup doing immediate injections";
do_injections true;
block_equalities.
Ltac dep_destruct_cleanup :=
intros;
subst;
do_injections true;
block_equalities;
unblock_conc;
intros;
do_eqdec_needed_injs;
do_injections false.
Ltac depdestruct H := sigT_generalize_eqs H; block_conc; destruct H.
Ltac start_eqdec genindexes ind :=
generalize_eqdep genindexes;
intros;
let b := last_hyp in
revert b;
let a := last_hyp in
helpful_induction a ind;
intros;
let b := last_hyp in
subst;
tryif destruct b
then non_dep_destruct_cleanup
else (once depdestruct b; dep_destruct_cleanup).
Ltac do_next_field pair :=
Debug 4 idtac "Debug: do_next_field" pair;
lazymatch pair with
| (?A, ?A) => left; reflexivity
| (?A ?X, ?A ?Y) =>
(*may not be slime, if X&Y are constants, but deslime handles that:*)
deslime (X, Y)
| (?X _, ?Y _) => do_next_field (X, Y)
| _ => right; discriminate
end.
Ltac do_fields :=
repeat
(repeat lazymatch goal with
| |- _ (?X = ?Y) _ => do_next_field (X, Y)
end;
do_injections false).
Ltac decide_one_equality genindexes ind :=
unshelve (start_eqdec genindexes ind; do_fields; handle_sub_eqdec).
Ltac check_inj_pair2_alias :=
tryif constr_eq inj_pair2_alias False
then fail "Please re-define Ltac inj_pair2_alias to an acceptable value"
else idtac.
(*the "simple" version doesn't do its own index generalizing:*)
Tactic Notation "simple" "dependent" "decide" "equality" "using" constr(ind) :=
check_inj_pair2_alias;
repeat decide_one_equality false ind.
Tactic Notation "simple" "dependent" "decide" "equality" :=
check_inj_pair2_alias;
repeat decide_one_equality false False.
Tactic Notation "dependent" "decide" "equality" "using" constr(ind) :=
check_inj_pair2_alias;
repeat decide_one_equality true ind.
Tactic Notation "dependent" "decide" "equality" :=
check_inj_pair2_alias;
repeat decide_one_equality true False.
Ltac dependent_compare x y genindexes ind :=
check_inj_pair2_alias;
try typeclasses eauto;
let H := fresh in
first
[assert (x=y \/ x<>y) as [H|H] by (repeat decide_one_equality genindexes ind)
|assert ({x=y}+{x<>y}) as [H|H] by (repeat decide_one_equality genindexes ind)
];
revert H.
Tactic Notation "simple" "dependent" "compare" constr(x) constr(y) "using" constr(ind) :=
dependent_compare x y false ind.
Tactic Notation "simple" "dependent" "compare" constr(x) constr(y) :=
dependent_compare x y false False.
Tactic Notation "dependent" "compare" constr(x) constr(y) "using" constr(ind) :=
dependent_compare x y true ind.
Tactic Notation "dependent" "compare" constr(x) constr(y) :=
dependent_compare x y true False.
Existing Class sumbool.
Hint Mode sumbool + + : typeclass_instances.
Existing Class or.
Hint Mode or + + : typeclass_instances.
(*The eqdec and eqem notations are convenient ways to create an eqdec or eqem
types from another type - see examples:*)
Definition eqthing orfun := fun (x : Type) => forall (a b : x), orfun (a = b) (a <> b).
Ltac make_eq_type type orfun :=
let x := under_binders type ltac:(fun x => constr:(eqthing orfun x)) in
let x' := (eval cbv beta delta [eqthing] in x) in
exact x'.
Notation eq_type type orfun := (ltac:(make_eq_type type orfun)) (only parsing).
Notation eqdec type := (eq_type type sumbool) (only parsing).
Notation eqem type := (eq_type type or) (only parsing).
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21O_4_V
`define SKY130_FD_SC_LS__A21O_4_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog wrapper for a21o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a21o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a21o_4 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a21o_4 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21O_4_V
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
// IP Revision: 6
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module BIOS_ROM (
clka,
ena,
addra,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
input wire ena;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [11 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [7 : 0] douta;
blk_mem_gen_v8_2 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(3),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("BIOS_ROM.mif"),
.C_INIT_FILE("BIOS_ROM.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(1),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_READ_WIDTH_A(8),
.C_WRITE_DEPTH_A(4096),
.C_READ_DEPTH_A(4096),
.C_ADDRA_WIDTH(12),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(8),
.C_READ_WIDTH_B(8),
.C_WRITE_DEPTH_B(4096),
.C_READ_DEPTH_B(4096),
.C_ADDRB_WIDTH(12),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("1"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 2.326399 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(ena),
.regcea(1'D0),
.wea(1'B0),
.addra(addra),
.dina(8'B0),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(12'B0),
.dinb(8'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(8'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : mig_7series_v1_8_tempmon.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Jul 25 2012
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Monitors chip temperature via the XADC and adjusts the
// stage 2 tap values as appropriate.
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v1_8_tempmon #
(
parameter TCQ = 100, // Register delay (sim only)
parameter TEMP_MON_CONTROL = "INTERNAL", // XADC or user temperature source
parameter XADC_CLK_PERIOD = 5000, // pS (default to 200 MHz refclk)
parameter tTEMPSAMPLE = 10000000 // ps (10 us)
)
(
input clk, // Fabric clock
input xadc_clk,
input rst, // System reset
input [11:0] device_temp_i, // User device temperature
output [11:0] device_temp // Sampled temperature
);
//***************************************************************************
// Function cdiv
// Description:
// This function performs ceiling division (divide and round-up)
// Inputs:
// num: integer to be divided
// div: divisor
// Outputs:
// cdiv: result of ceiling division (num/div, rounded up)
//***************************************************************************
function integer cdiv (input integer num, input integer div);
begin
// perform division, then add 1 if and only if remainder is non-zero
cdiv = (num/div) + (((num%div)>0) ? 1 : 0);
end
endfunction // cdiv
//***************************************************************************
// Function clogb2
// Description:
// This function performs binary logarithm and rounds up
// Inputs:
// size: integer to perform binary log upon
// Outputs:
// clogb2: result of binary logarithm, rounded up
//***************************************************************************
function integer clogb2 (input integer size);
begin
size = size - 1;
// increment clogb2 from 1 for each bit in size
for (clogb2 = 1; size > 1; clogb2 = clogb2 + 1)
size = size >> 1;
end
endfunction // clogb2
// Synchronization registers
(* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r1;
(* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r2;
(* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r3 /* synthesis syn_srlstyle="registers" */;
(* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r4;
(* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r5;
// Output register
(* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_r;
wire [11:0] device_temp_lcl;
reg [3:0] sync_cntr = 4'b0000;
reg device_temp_sync_r4_neq_r3;
// (* ASYNC_REG = "TRUE" *) reg rst_r1;
// (* ASYNC_REG = "TRUE" *) reg rst_r2;
// // Synchronization rst to XADC clock domain
// always @(posedge xadc_clk) begin
// rst_r1 <= rst;
// rst_r2 <= rst_r1;
// end
// Synchronization counter
always @(posedge clk) begin
device_temp_sync_r1 <= #TCQ device_temp_lcl;
device_temp_sync_r2 <= #TCQ device_temp_sync_r1;
device_temp_sync_r3 <= #TCQ device_temp_sync_r2;
device_temp_sync_r4 <= #TCQ device_temp_sync_r3;
device_temp_sync_r5 <= #TCQ device_temp_sync_r4;
device_temp_sync_r4_neq_r3 <= #TCQ (device_temp_sync_r4 != device_temp_sync_r3) ? 1'b1 : 1'b0;
end
always @(posedge clk)
if(rst || (device_temp_sync_r4_neq_r3))
sync_cntr <= #TCQ 4'b0000;
else if(~&sync_cntr)
sync_cntr <= #TCQ sync_cntr + 4'b0001;
always @(posedge clk)
if(&sync_cntr)
device_temp_r <= #TCQ device_temp_sync_r5;
assign device_temp = device_temp_r;
generate
if(TEMP_MON_CONTROL == "EXTERNAL") begin : user_supplied_temperature
assign device_temp_lcl = device_temp_i;
end else begin : xadc_supplied_temperature
// calculate polling timer width and limit
localparam nTEMPSAMP = cdiv(tTEMPSAMPLE, XADC_CLK_PERIOD);
localparam nTEMPSAMP_CLKS = nTEMPSAMP;
localparam nTEMPSAMP_CLKS_M6 = nTEMPSAMP - 6;
localparam nTEMPSAMP_CNTR_WIDTH = clogb2(nTEMPSAMP_CLKS);
// Temperature sampler FSM encoding
localparam INIT_IDLE = 2'b00;
localparam REQUEST_READ_TEMP = 2'b01;
localparam WAIT_FOR_READ = 2'b10;
localparam READ = 2'b11;
// polling timer and tick
reg [nTEMPSAMP_CNTR_WIDTH-1:0] sample_timer = {nTEMPSAMP_CNTR_WIDTH{1'b0}};
reg sample_timer_en = 1'b0;
reg sample_timer_clr = 1'b0;
reg sample_en = 1'b0;
// Temperature sampler state
reg [2:0] tempmon_state = INIT_IDLE;
reg [2:0] tempmon_next_state = INIT_IDLE;
// XADC interfacing
reg xadc_den = 1'b0;
wire xadc_drdy;
wire [15:0] xadc_do;
reg xadc_drdy_r = 1'b0;
reg [15:0] xadc_do_r = 1'b0;
// Temperature storage
reg [11:0] temperature = 12'b0;
// Reset sync
(* ASYNC_REG = "TRUE" *) reg rst_r1;
(* ASYNC_REG = "TRUE" *) reg rst_r2;
// Synchronization rst to XADC clock domain
always @(posedge xadc_clk) begin
rst_r1 <= rst;
rst_r2 <= rst_r1;
end
// XADC polling interval timer
always @ (posedge xadc_clk)
if(rst_r2 || sample_timer_clr)
sample_timer <= #TCQ {nTEMPSAMP_CNTR_WIDTH{1'b0}};
else if(sample_timer_en)
sample_timer <= #TCQ sample_timer + 1'b1;
// XADC sampler state transition
always @(posedge xadc_clk)
if(rst_r2)
tempmon_state <= #TCQ INIT_IDLE;
else
tempmon_state <= #TCQ tempmon_next_state;
// Sample enable
always @(posedge xadc_clk)
sample_en <= #TCQ (sample_timer == nTEMPSAMP_CLKS_M6) ? 1'b1 : 1'b0;
// XADC sampler next state transition
always @(tempmon_state or sample_en or xadc_drdy_r) begin
tempmon_next_state = tempmon_state;
case(tempmon_state)
INIT_IDLE:
if(sample_en)
tempmon_next_state = REQUEST_READ_TEMP;
REQUEST_READ_TEMP:
tempmon_next_state = WAIT_FOR_READ;
WAIT_FOR_READ:
if(xadc_drdy_r)
tempmon_next_state = READ;
READ:
tempmon_next_state = INIT_IDLE;
default:
tempmon_next_state = INIT_IDLE;
endcase
end
// Sample timer clear
always @(posedge xadc_clk)
if(rst_r2 || (tempmon_state == WAIT_FOR_READ))
sample_timer_clr <= #TCQ 1'b0;
else if(tempmon_state == REQUEST_READ_TEMP)
sample_timer_clr <= #TCQ 1'b1;
// Sample timer enable
always @(posedge xadc_clk)
if(rst_r2 || (tempmon_state == REQUEST_READ_TEMP))
sample_timer_en <= #TCQ 1'b0;
else if((tempmon_state == INIT_IDLE) || (tempmon_state == READ))
sample_timer_en <= #TCQ 1'b1;
// XADC enable
always @(posedge xadc_clk)
if(rst_r2 || (tempmon_state == WAIT_FOR_READ))
xadc_den <= #TCQ 1'b0;
else if(tempmon_state == REQUEST_READ_TEMP)
xadc_den <= #TCQ 1'b1;
// Register XADC outputs
always @(posedge xadc_clk)
if(rst_r2) begin
xadc_drdy_r <= #TCQ 1'b0;
xadc_do_r <= #TCQ 16'b0;
end
else begin
xadc_drdy_r <= #TCQ xadc_drdy;
xadc_do_r <= #TCQ xadc_do;
end
// Store current read value
always @(posedge xadc_clk)
if(rst_r2)
temperature <= #TCQ 12'b0;
else if(tempmon_state == READ)
temperature <= #TCQ xadc_do_r[15:4];
assign device_temp_lcl = temperature;
// XADC: Dual 12-Bit 1MSPS Analog-to-Digital Converter
// 7 Series
// Xilinx HDL Libraries Guide, version 14.1
XADC #(
// INIT_40 - INIT_42: XADC configuration registers
.INIT_40(16'h8000), // config reg 0
.INIT_41(16'h3f0f), // config reg 1
.INIT_42(16'h0400), // config reg 2
// INIT_48 - INIT_4F: Sequence Registers
.INIT_48(16'h0100), // Sequencer channel selection
.INIT_49(16'h0000), // Sequencer channel selection
.INIT_4A(16'h0000), // Sequencer Average selection
.INIT_4B(16'h0000), // Sequencer Average selection
.INIT_4C(16'h0000), // Sequencer Bipolar selection
.INIT_4D(16'h0000), // Sequencer Bipolar selection
.INIT_4E(16'h0000), // Sequencer Acq time selection
.INIT_4F(16'h0000), // Sequencer Acq time selection
// INIT_50 - INIT_58, INIT5C: Alarm Limit Registers
.INIT_50(16'hb5ed), // Temp alarm trigger
.INIT_51(16'h57e4), // Vccint upper alarm limit
.INIT_52(16'ha147), // Vccaux upper alarm limit
.INIT_53(16'hca33), // Temp alarm OT upper
.INIT_54(16'ha93a), // Temp alarm reset
.INIT_55(16'h52c6), // Vccint lower alarm limit
.INIT_56(16'h9555), // Vccaux lower alarm limit
.INIT_57(16'hae4e), // Temp alarm OT reset
.INIT_58(16'h5999), // VBRAM upper alarm limit
.INIT_5C(16'h5111), // VBRAM lower alarm limit
// Simulation attributes: Set for proepr simulation behavior
.SIM_DEVICE("7SERIES") // Select target device (values)
)
XADC_inst (
// ALARMS: 8-bit (each) output: ALM, OT
.ALM(), // 8-bit output: Output alarm for temp, Vccint, Vccaux and Vccbram
.OT(), // 1-bit output: Over-Temperature alarm
// Dynamic Reconfiguration Port (DRP): 16-bit (each) output: Dynamic Reconfiguration Ports
.DO(xadc_do), // 16-bit output: DRP output data bus
.DRDY(xadc_drdy), // 1-bit output: DRP data ready
// STATUS: 1-bit (each) output: XADC status ports
.BUSY(), // 1-bit output: ADC busy output
.CHANNEL(), // 5-bit output: Channel selection outputs
.EOC(), // 1-bit output: End of Conversion
.EOS(), // 1-bit output: End of Sequence
.JTAGBUSY(), // 1-bit output: JTAG DRP transaction in progress output
.JTAGLOCKED(), // 1-bit output: JTAG requested DRP port lock
.JTAGMODIFIED(), // 1-bit output: JTAG Write to the DRP has occurred
.MUXADDR(), // 5-bit output: External MUX channel decode
// Auxiliary Analog-Input Pairs: 16-bit (each) input: VAUXP[15:0], VAUXN[15:0]
.VAUXN(16'b0), // 16-bit input: N-side auxiliary analog input
.VAUXP(16'b0), // 16-bit input: P-side auxiliary analog input
// CONTROL and CLOCK: 1-bit (each) input: Reset, conversion start and clock inputs
.CONVST(1'b0), // 1-bit input: Convert start input
.CONVSTCLK(1'b0), // 1-bit input: Convert start input
.RESET(1'b0), // 1-bit input: Active-high reset
// Dedicated Analog Input Pair: 1-bit (each) input: VP/VN
.VN(1'b0), // 1-bit input: N-side analog input
.VP(1'b0), // 1-bit input: P-side analog input
// Dynamic Reconfiguration Port (DRP): 7-bit (each) input: Dynamic Reconfiguration Ports
.DADDR(7'b0), // 7-bit input: DRP address bus
.DCLK(xadc_clk), // 1-bit input: DRP clock
.DEN(xadc_den), // 1-bit input: DRP enable signal
.DI(16'b0), // 16-bit input: DRP input data bus
.DWE(1'b0) // 1-bit input: DRP write enable
);
// End of XADC_inst instantiation
end
endgenerate
endmodule
|
module axi_master_stub(
output M2S_AXI_ACLK,
//Read Transaction
output M2S_AXI_ARVALID,
input M2S_AXI_ARREADY,
output [31:0] M2S_AXI_ARADDR,
output [1:0] M2S_AXI_ARBURST,
output [3:0] M2S_AXI_ARLEN,
output [1:0] M2S_AXI_ARSIZE,
//
input M2S_AXI_RVALID,
output M2S_AXI_RREADY,
input M2S_AXI_RLAST,
input [63:0] M2S_AXI_RDATA,
//
input [1:0] M2S_AXI_RRESP,
// Write Transaction
output M2S_AXI_AWVALID,
input M2S_AXI_AWREADY,
output [31:0] M2S_AXI_AWADDR,
output [1:0] M2S_AXI_AWBURST,
output [3:0] M2S_AXI_AWLEN,
output [1:0] M2S_AXI_AWSIZE,
//
output M2S_AXI_WVALID,
input M2S_AXI_WREADY,
output M2S_AXI_WLAST,
output [63:0] M2S_AXI_WDATA,
output [7:0] M2S_AXI_WSTRB,
//
input M2S_AXI_BVALID,
output M2S_AXI_BREADY,
input [1:0] M2S_AXI_BRESP
);
assign M2S_AXI_ACLK = 1'b0;
//Read Transaction
assign M2S_AXI_ARVALID = 1'b0;
assign M2S_AXI_ARADDR = 32'b0;
assign M2S_AXI_ARBURST = 2'b0;
assign M2S_AXI_ARLEN = 4'b0;
assign M2S_AXI_ARSIZE = 2'b0;
assign M2S_AXI_RREADY = 1'b0;
// Write Transaction
assign M2S_AXI_AWVALID = 1'b0;
assign M2S_AXI_AWADDR = 32'b0;
assign M2S_AXI_AWBURST = 2'b0;
assign M2S_AXI_AWLEN = 4'b0;
assign M2S_AXI_AWSIZE = 2'b0;
assign M2S_AXI_WVALID = 1'b0;
assign M2S_AXI_WLAST = 1'b0;
assign M2S_AXI_WDATA = 64'b0;
assign M2S_AXI_WSTRB = 8'b0;
assign M2S_AXI_BREADY = 1'b0;
endmodule : axi_master_stub
/*
axi_master_stub axi_master_XXX_stub (
.M2S_AXI_ACLK(M2S_XXX_AXI_ACLK),
//Read Transaction
.M2S_AXI_ARVALID(M2S_XXX_AXI_ARVALID),
.M2S_AXI_ARREADY(M2S_XXX_AXI_ARREADY),
.M2S_AXI_ARADDR(M2S_XXX_AXI_ARADDR[31:0]),
.M2S_AXI_ARBURST(M2S_XXX_AXI_ARBURST[1:0]),
.M2S_AXI_ARLEN(M2S_XXX_AXI_ARLEN[3:0]),
.M2S_AXI_ARSIZE(M2S_XXX_AXI_ARSIZE[1:0]),
//
.M2S_AXI_RVALID(M2S_XXX_AXI_RVALID),
.M2S_AXI_RREADY(M2S_XXX_AXI_RREADY),
.M2S_AXI_RLAST(M2S_XXX_AXI_RLAST),
.M2S_AXI_RDATA(M2S_XXX_AXI_RDATA[63:0]),
//
.M2S_AXI_RRESP(M2S_XXX_AXI_RRESP[1:0]),
// Write Transaction
.M2S_AXI_AWVALID(M2S_XXX_AXI_AWVALID),
.M2S_AXI_AWREADY(M2S_XXX_AXI_AWREADY),
.M2S_AXI_AWADDR(M2S_XXX_AXI_AWADDR[31:0]),
.M2S_AXI_AWBURST(M2S_XXX_AXI_AWBURST[1:0]),
.M2S_AXI_AWLEN(M2S_XXX_AXI_AWLEN[3:0]),
.M2S_AXI_AWSIZE(M2S_XXX_AXI_AWSIZE[1:0]),
//
.M2S_AXI_WVALID(M2S_XXX_AXI_WVALID),
.M2S_AXI_WREADY(M2S_XXX_AXI_WREADY),
.M2S_AXI_WLAST(M2S_XXX_AXI_WLAST),
.M2S_AXI_WDATA(M2S_XXX_AXI_WDATA[63:0]),
.M2S_AXI_WSTRB(M2S_XXX_AXI_WSTRB[7:0]),
//
.M2S_AXI_BVALID(M2S_XXX_AXI_BVALID),
.M2S_AXI_BREADY(M2S_XXX_AXI_BREADY),
.M2S_AXI_BRESP(M2S_XXX_AXI_BRESP[1:0])
);
*/
|
/*
* Copyright (c) 2009 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module hex_display (
input [15:0] num,
input en,
output [6:0] hex0,
output [6:0] hex1,
output [6:0] hex2,
output [6:0] hex3
);
// Module instantiations
seg_7 hex_group0 (
.num (num[3:0]),
.en (en),
.seg (hex0)
);
seg_7 hex_group1 (
.num (num[7:4]),
.en (en),
.seg (hex1)
);
seg_7 hex_group2 (
.num (num[11:8]),
.en (en),
.seg (hex2)
);
seg_7 hex_group3 (
.num (num[15:12]),
.en (en),
.seg (hex3)
);
endmodule
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
|
/******************************************************************************
* File Name : ks29.v
* Package Module Name : Elliptic Curve Cryptoprocessor for GF(2^233)
* Author : Chester Rebeiro
* Date of Creation : 1/Apr/2008
* Type of file : Verilog source code
* Synopsis : Automatically generated code for karatsuba 29 bit
******************************************************************************/
`ifndef __KS_29_V__
`define __KS_29_V__
//`include "ks15.v"
//`include "ks14.v"
module ks29(a, b, d);
input wire [28:0] a;
input wire [28:0] b;
output wire [56:0] d;
wire [26:0] m1;
wire [28:0] m2;
wire [28:0] m3;
wire [14:0] ahl;
wire [14:0] bhl;
ks15 ksm1(a[14:0], b[14:0], m2);
ks14 ksm2(a[28:15], b[28:15], m1);
assign ahl[13:0] = a[28:15] ^ a[13:0];
assign ahl[14] = a[14];
assign bhl[13:0] = b[28:15] ^ b[13:0];
assign bhl[14] = b[14];
ks15 ksm3(ahl, bhl, m3);
assign d[00] = m2[00];
assign d[01] = m2[01];
assign d[02] = m2[02];
assign d[03] = m2[03];
assign d[04] = m2[04];
assign d[05] = m2[05];
assign d[06] = m2[06];
assign d[07] = m2[07];
assign d[08] = m2[08];
assign d[09] = m2[09];
assign d[10] = m2[10];
assign d[11] = m2[11];
assign d[12] = m2[12];
assign d[13] = m2[13];
assign d[14] = m2[14];
assign d[15] = m2[15] ^ m1[00] ^ m2[00] ^ m3[00];
assign d[16] = m2[16] ^ m1[01] ^ m2[01] ^ m3[01];
assign d[17] = m2[17] ^ m1[02] ^ m2[02] ^ m3[02];
assign d[18] = m2[18] ^ m1[03] ^ m2[03] ^ m3[03];
assign d[19] = m2[19] ^ m1[04] ^ m2[04] ^ m3[04];
assign d[20] = m2[20] ^ m1[05] ^ m2[05] ^ m3[05];
assign d[21] = m2[21] ^ m1[06] ^ m2[06] ^ m3[06];
assign d[22] = m2[22] ^ m1[07] ^ m2[07] ^ m3[07];
assign d[23] = m2[23] ^ m1[08] ^ m2[08] ^ m3[08];
assign d[24] = m2[24] ^ m1[09] ^ m2[09] ^ m3[09];
assign d[25] = m2[25] ^ m1[10] ^ m2[10] ^ m3[10];
assign d[26] = m2[26] ^ m1[11] ^ m2[11] ^ m3[11];
assign d[27] = m2[27] ^ m1[12] ^ m2[12] ^ m3[12];
assign d[28] = m2[28] ^ m1[13] ^ m2[13] ^ m3[13];
assign d[29] = m1[14] ^ m2[14] ^ m3[14];
assign d[30] = m1[15] ^ m2[15] ^ m3[15] ^ m1[00];
assign d[31] = m1[16] ^ m2[16] ^ m3[16] ^ m1[01];
assign d[32] = m1[17] ^ m2[17] ^ m3[17] ^ m1[02];
assign d[33] = m1[18] ^ m2[18] ^ m3[18] ^ m1[03];
assign d[34] = m1[19] ^ m2[19] ^ m3[19] ^ m1[04];
assign d[35] = m1[20] ^ m2[20] ^ m3[20] ^ m1[05];
assign d[36] = m1[21] ^ m2[21] ^ m3[21] ^ m1[06];
assign d[37] = m1[22] ^ m2[22] ^ m3[22] ^ m1[07];
assign d[38] = m1[23] ^ m2[23] ^ m3[23] ^ m1[08];
assign d[39] = m1[24] ^ m2[24] ^ m3[24] ^ m1[09];
assign d[40] = m1[25] ^ m2[25] ^ m3[25] ^ m1[10];
assign d[41] = m1[26] ^ m2[26] ^ m3[26] ^ m1[11];
assign d[42] = m2[27] ^ m3[27] ^ m1[12];
assign d[43] = m2[28] ^ m3[28] ^ m1[13];
assign d[44] = m1[14];
assign d[45] = m1[15];
assign d[46] = m1[16];
assign d[47] = m1[17];
assign d[48] = m1[18];
assign d[49] = m1[19];
assign d[50] = m1[20];
assign d[51] = m1[21];
assign d[52] = m1[22];
assign d[53] = m1[23];
assign d[54] = m1[24];
assign d[55] = m1[25];
assign d[56] = m1[26];
endmodule
`endif
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 07:02:41 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_0_1/system_ov7670_vga_0_0_stub.v
// Design : system_ov7670_vga_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ov7670_vga,Vivado 2016.4" *)
module system_ov7670_vga_0_0(pclk, data, rgb)
/* synthesis syn_black_box black_box_pad_pin="pclk,data[7:0],rgb[15:0]" */;
input pclk;
input [7:0]data;
output [15:0]rgb;
endmodule
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_acv_hard_addr_cmd_pads(
/*
config_data_in,
config_clock_in,
config_io_ena,
config_update,
*/
reset_n,
reset_n_afi_clk,
pll_hr_clk,
pll_avl_phy_clk,
pll_afi_clk,
pll_mem_clk,
pll_write_clk,
phy_ddio_address,
dll_delayctrl_in,
phy_ddio_bank,
phy_ddio_cs_n,
phy_ddio_cke,
phy_ddio_odt,
phy_ddio_we_n,
phy_ddio_ras_n,
phy_ddio_cas_n,
phy_ddio_ck,
phy_ddio_reset_n,
phy_mem_address,
phy_mem_bank,
phy_mem_cs_n,
phy_mem_cke,
phy_mem_odt,
phy_mem_we_n,
phy_mem_ras_n,
phy_mem_cas_n,
phy_mem_reset_n,
phy_mem_ck,
phy_mem_ck_n
);
parameter DEVICE_FAMILY = "";
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_CHIP_SELECT_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_BANK_WIDTH = "";
parameter AFI_CHIP_SELECT_WIDTH = "";
parameter AFI_CLK_EN_WIDTH = "";
parameter AFI_ODT_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter DLL_WIDTH = "";
parameter ADC_PHASE_SETTING = "";
parameter ADC_INVERT_PHASE = "";
parameter IS_HHP_HPS = "";
/*
input config_data_in;
input config_clock_in;
input config_io_ena;
input config_update;
*/
input reset_n;
input reset_n_afi_clk;
input pll_afi_clk;
input pll_hr_clk;
input pll_avl_phy_clk;
input pll_mem_clk;
input pll_write_clk;
input [DLL_WIDTH-1:0] dll_delayctrl_in;
input [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
input [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
input [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
input [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ck;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_reset_n;
output [MEM_ADDRESS_WIDTH-1:0] phy_mem_address;
output [MEM_BANK_WIDTH-1:0] phy_mem_bank;
output [MEM_CHIP_SELECT_WIDTH-1:0] phy_mem_cs_n;
output [MEM_CLK_EN_WIDTH-1:0] phy_mem_cke;
output [MEM_ODT_WIDTH-1:0] phy_mem_odt;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_we_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_cas_n;
output phy_mem_reset_n;
output [MEM_CK_WIDTH-1:0] phy_mem_ck;
output [MEM_CK_WIDTH-1:0] phy_mem_ck_n;
/* ********* *
* A/C Logic *
* ********* */
localparam CMD_WIDTH =
MEM_CHIP_SELECT_WIDTH +
MEM_CLK_EN_WIDTH +
MEM_ODT_WIDTH +
MEM_CONTROL_WIDTH +
MEM_CONTROL_WIDTH +
MEM_CONTROL_WIDTH;
localparam AC_CLK_WIDTH = MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH + CMD_WIDTH + 1;
localparam IMPLEMENT_MEM_CLK_IN_SOFT_LOGIC = "false";
wire [AC_CLK_WIDTH-1:0] ac_clk;
generate
genvar i;
for (i = 0; i < AC_CLK_WIDTH; i = i + 1)
begin: address_gen
wire addr_cmd_clk;
hps_sdram_p0_acv_ldc # (
.DLL_DELAY_CTRL_WIDTH(DLL_WIDTH),
.ADC_PHASE_SETTING(ADC_PHASE_SETTING),
.ADC_INVERT_PHASE(ADC_INVERT_PHASE),
.IS_HHP_HPS(IS_HHP_HPS)
) acv_ac_ldc (
.pll_hr_clk(pll_avl_phy_clk),
.pll_dq_clk(pll_write_clk),
.pll_dqs_clk (pll_mem_clk),
.dll_phy_delayctrl(dll_delayctrl_in),
.adc_clk_cps(ac_clk[i])
);
end
endgenerate
hps_sdram_p0_generic_ddio uaddress_pad(
.datain(phy_ddio_address),
.halfratebypass(1'b1),
.dataout(phy_mem_address),
.clk_hr({MEM_ADDRESS_WIDTH{pll_hr_clk}}),
.clk_fr(ac_clk[MEM_ADDRESS_WIDTH-1:0])
);
defparam uaddress_pad.WIDTH = MEM_ADDRESS_WIDTH;
hps_sdram_p0_generic_ddio ubank_pad(
.datain(phy_ddio_bank),
.halfratebypass(1'b1),
.dataout(phy_mem_bank),
.clk_hr({MEM_BANK_WIDTH{pll_hr_clk}}),
.clk_fr(ac_clk[MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH - 1: MEM_ADDRESS_WIDTH])
);
defparam ubank_pad.WIDTH = MEM_BANK_WIDTH;
hps_sdram_p0_generic_ddio ucmd_pad(
.datain({
phy_ddio_we_n,
phy_ddio_cas_n,
phy_ddio_ras_n,
phy_ddio_odt,
phy_ddio_cke,
phy_ddio_cs_n
}),
.halfratebypass(1'b1),
.dataout({
phy_mem_we_n,
phy_mem_cas_n,
phy_mem_ras_n,
phy_mem_odt,
phy_mem_cke,
phy_mem_cs_n
}),
.clk_hr({CMD_WIDTH{pll_hr_clk}}),
.clk_fr(ac_clk[MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH + CMD_WIDTH - 1: MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH])
);
defparam ucmd_pad.WIDTH = CMD_WIDTH;
hps_sdram_p0_generic_ddio ureset_n_pad(
.datain(phy_ddio_reset_n),
.halfratebypass(1'b1),
.dataout(phy_mem_reset_n),
.clk_hr(pll_hr_clk),
.clk_fr(ac_clk[MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH + CMD_WIDTH])
);
defparam ureset_n_pad.WIDTH = 1;
/* ************ *
* Config Logic *
* ************ */
wire [4:0] outputdelaysetting;
wire [4:0] outputenabledelaysetting;
wire outputhalfratebypass;
wire [4:0] inputdelaysetting;
wire [1:0] rfifo_clock_select;
wire [2:0] rfifo_mode;
/*
cyclonev_io_config ioconfig (
.datain(config_data_in),
.clk(config_clock_in),
.ena(config_io_ena),
.update(config_update),
.outputregdelaysetting(outputdelaysetting),
.outputenabledelaysetting(outputenabledelaysetting),
.outputhalfratebypass(outputhalfratebypass),
.readfiforeadclockselect(rfifo_clock_select),
.readfifomode(rfifo_mode),
.padtoinputregisterdelaysetting(inputdelaysetting),
.dataout()
);
*/
/* *************** *
* Mem Clock Logic *
* *************** */
wire [MEM_CK_WIDTH-1:0] mem_ck_source;
wire [MEM_CK_WIDTH-1:0] mem_ck;
generate
genvar clock_width;
for (clock_width=0; clock_width<MEM_CK_WIDTH; clock_width=clock_width+1)
begin: clock_gen
if(IMPLEMENT_MEM_CLK_IN_SOFT_LOGIC == "true")
begin
hps_sdram_p0_acv_ldc # (
.DLL_DELAY_CTRL_WIDTH(DLL_WIDTH),
.ADC_PHASE_SETTING(ADC_PHASE_SETTING),
.ADC_INVERT_PHASE(ADC_INVERT_PHASE),
.IS_HHP_HPS(IS_HHP_HPS)
) acv_ck_ldc (
.pll_hr_clk(pll_avl_phy_clk),
.pll_dq_clk(pll_write_clk),
.pll_dqs_clk (pll_mem_clk),
.dll_phy_delayctrl(dll_delayctrl_in),
.adc_clk_cps(mem_ck_source[clock_width])
);
end
else
begin
wire [3:0] phy_clk_in;
wire [3:0] phy_clk_out;
assign phy_clk_in = {pll_avl_phy_clk,pll_write_clk,pll_mem_clk,1'b0};
if (IS_HHP_HPS == "true") begin
assign phy_clk_out = phy_clk_in;
end else begin
cyclonev_phy_clkbuf phy_clkbuf (
.inclk (phy_clk_in),
.outclk (phy_clk_out)
);
end
wire [3:0] leveled_dqs_clocks;
cyclonev_leveling_delay_chain leveling_delay_chain_dqs (
.clkin (phy_clk_out[1]),
.delayctrlin (dll_delayctrl_in),
.clkout(leveled_dqs_clocks)
);
defparam leveling_delay_chain_dqs.physical_clock_source = "DQS";
cyclonev_clk_phase_select clk_phase_select_dqs (
`ifndef SIMGEN
.clkin (leveled_dqs_clocks[0]),
`else
.clkin (leveled_dqs_clocks),
`endif
.clkout (mem_ck_source[clock_width])
);
defparam clk_phase_select_dqs.physical_clock_source = "DQS";
defparam clk_phase_select_dqs.use_phasectrlin = "false";
defparam clk_phase_select_dqs.phase_setting = 0;
end
wire mem_ck_hi;
wire mem_ck_lo;
if(IMPLEMENT_MEM_CLK_IN_SOFT_LOGIC == "true")
begin
assign mem_ck_hi = 1'b0;
assign mem_ck_lo = 1'b1;
end
else
begin
assign mem_ck_hi = phy_ddio_ck[0];
assign mem_ck_lo = phy_ddio_ck[1];
end
altddio_out umem_ck_pad(
.aclr (1'b0),
.aset (1'b0),
.datain_h (mem_ck_hi),
.datain_l (mem_ck_lo),
.dataout (mem_ck[clock_width]),
.oe (1'b1),
.outclock (mem_ck_source[clock_width]),
.outclocken (1'b1)
);
defparam
umem_ck_pad.extend_oe_disable = "UNUSED",
umem_ck_pad.intended_device_family = DEVICE_FAMILY,
umem_ck_pad.invert_output = "OFF",
umem_ck_pad.lpm_hint = "UNUSED",
umem_ck_pad.lpm_type = "altddio_out",
umem_ck_pad.oe_reg = "UNUSED",
umem_ck_pad.power_up_high = "OFF",
umem_ck_pad.width = 1;
wire mem_ck_temp;
assign mem_ck_temp = mem_ck[clock_width];
hps_sdram_p0_clock_pair_generator uclk_generator(
.datain (mem_ck_temp),
.dataout (phy_mem_ck[clock_width]),
.dataout_b (phy_mem_ck_n[clock_width])
);
end
endgenerate
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2.3
// \ \ Application : MIG
// / / Filename : dram.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
// \ \ / \ Date Created : Wed Feb 01 2012
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR3 SDRAM
// Purpose :
// Wrapper module for the user design top level file. This module can be
// instantiated in the system and interconnect as shown in example design
// (example_top module).
// Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module dram (
// Inouts
inout [63:0] ddr3_dq,
inout [7:0] ddr3_dqs_n,
inout [7:0] ddr3_dqs_p,
// Outputs
output [15:0] ddr3_addr,
output [2:0] ddr3_ba,
output ddr3_ras_n,
output ddr3_cas_n,
output ddr3_we_n,
output ddr3_reset_n,
output [0:0] ddr3_ck_p,
output [0:0] ddr3_ck_n,
output [0:0] ddr3_cke,
output [0:0] ddr3_cs_n,
output [7:0] ddr3_dm,
output [0:0] ddr3_odt,
// Inputs
// Differential system clocks
input sys_clk_p,
input sys_clk_n,
// user interface signals
input [29:0] app_addr,
input [2:0] app_cmd,
input app_en,
input [511:0] app_wdf_data,
input app_wdf_end,
input [63:0] app_wdf_mask,
input app_wdf_wren,
output [511:0] app_rd_data,
output app_rd_data_end,
output app_rd_data_valid,
output app_rdy,
output app_wdf_rdy,
input app_sr_req,
input app_ref_req,
input app_zq_req,
output app_sr_active,
output app_ref_ack,
output app_zq_ack,
output ui_clk,
output ui_clk_sync_rst,
output init_calib_complete,
input sys_rst
);
// Start of IP top instance
dram_mig u_dram_mig (
// Memory interface ports
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.init_calib_complete (init_calib_complete),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_odt (ddr3_odt),
// Application interface ports
.app_addr (app_addr),
.app_cmd (app_cmd),
.app_en (app_en),
.app_wdf_data (app_wdf_data),
.app_wdf_end (app_wdf_end),
.app_wdf_wren (app_wdf_wren),
.app_rd_data (app_rd_data),
.app_rd_data_end (app_rd_data_end),
.app_rd_data_valid (app_rd_data_valid),
.app_rdy (app_rdy),
.app_wdf_rdy (app_wdf_rdy),
.app_sr_req (app_sr_req),
.app_ref_req (app_ref_req),
.app_zq_req (app_zq_req),
.app_sr_active (app_sr_active),
.app_ref_ack (app_ref_ack),
.app_zq_ack (app_zq_ack),
.ui_clk (ui_clk),
.ui_clk_sync_rst (ui_clk_sync_rst),
.app_wdf_mask (app_wdf_mask),
// System Clock Ports
.sys_clk_p (sys_clk_p),
.sys_clk_n (sys_clk_n),
.sys_rst (sys_rst)
);
// End of IP top instance
endmodule
|
//==================================================================================================
// Filename : Mux_3x1_b.v
// Created On : 2016-10-03 16:53:16
// Last Modified : 2016-10-04 10:26:18
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
module Mux_3x1_bv2 #(parameter W=32)
(
//Input Signals
input wire [1:0] select,
input wire [W-1:0] ch_0,
input wire [W-1:0] ch_1,
input wire [W-1:0] ch_2,
//Output Signals
output reg [W-1:0] data_out
);
always @*
begin
case(select)
2'b00: data_out <= {W{1'b0}};
2'b01: data_out <= ch_0;
2'b10: data_out <= ch_1;
2'b11: data_out <= ch_2;
default : data_out <= ch_0;
endcase
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:53:42 05/12/2015
// Design Name:
// Module Name: EX_ME
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module EX_ME(
clk,rst,
ex_aluresult, ex_td, ex_d2, ex_WREG, ex_WMEM, ex_LW,ex_instr,
me_aluresult, me_td, me_d2, me_WREG, me_WMEM, me_LW,me_instr
);
input clk,rst;
input wire [31:0] ex_aluresult,ex_d2,ex_instr;
input wire [4:0] ex_td;
input wire ex_WREG,ex_WMEM,ex_LW;
output reg [31:0] me_aluresult,me_d2,me_instr;
output reg [4:0] me_td;
output reg me_WREG,me_WMEM,me_LW;
always @(posedge clk or posedge rst)
begin
if(rst)
begin
me_aluresult <= 0;
me_d2 <= 0;
me_td <= 0;
me_WREG <= 0;
me_WMEM <= 0;
me_LW <= 0;
me_instr<=32'b100000;
end
else
begin
me_aluresult <= ex_aluresult;
me_d2 <= ex_d2;
me_td <= ex_td;
me_WREG <= ex_WREG;
me_WMEM <= ex_WMEM;
me_LW <= ex_LW;
me_instr<=ex_instr;
end
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: AXI Splitter
// Each transfer received on the AXI handshake slave port is replicated onto
// each of the master ports, and is completed back to the slave (S_READY)
// once all master ports have completed.
//
// M_VALID is asserted combinatorially from S_VALID assertion.
// Each M_VALID is masked off beginning the cycle after each M_READY is
// received (if S_READY remains low) until the cycle after both S_VALID
// and S_READY are asserted.
// S_READY is asserted combinatorially when the last (or all) of the M_READY
// inputs have been received.
// If all M_READYs are asserted when S_VALID is asserted, back-to-back
// handshakes can occur without bubble cycles.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// splitter
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_splitter #
(
parameter integer C_NUM_M = 2 // Number of master ports = [2:16]
)
(
// Global Signals
input wire ACLK,
input wire ARESET,
// Slave Port
input wire S_VALID,
output wire S_READY,
// Master Ports
output wire [C_NUM_M-1:0] M_VALID,
input wire [C_NUM_M-1:0] M_READY
);
reg [C_NUM_M-1:0] m_ready_d;
wire s_ready_i;
wire [C_NUM_M-1:0] m_valid_i;
always @(posedge ACLK) begin
if (ARESET | s_ready_i) m_ready_d <= {C_NUM_M{1'b0}};
else m_ready_d <= m_ready_d | (m_valid_i & M_READY);
end
assign s_ready_i = &(m_ready_d | M_READY);
assign m_valid_i = {C_NUM_M{S_VALID}} & ~m_ready_d;
assign M_VALID = m_valid_i;
assign S_READY = s_ready_i;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:28:21 04/13/2016
// Design Name: MAIN
// Module Name: Y:/TEOCOA/EXPR5/TESTSTORAGE.v
// Project Name: EXPR5
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: TESTSTORAGE
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TEST;
// Inputs
reg [5:0] Mem_Addr;
reg [1:0] CS;
reg Mem_Write;
reg Clk;
// Outputs
wire [7:0] LED;
// Instantiate the Unit Under Test (UUT)
TESTSTORAGE uut (
.Mem_Addr(Mem_Addr),
.CS(CS),
.Mem_Write(Mem_Write),
.Clk(Clk),
.LED(LED)
);
initial begin
// Initialize Inputs
Clk = 0;
Mem_Addr = 0;
CS = 0;
Mem_Write = 0;
// Wait 100 ns for global reset to finish
#10;
Mem_Addr = 0;
CS = 1;
Mem_Write = 0;
// Wait 100 ns for global reset to finish
#10;
Mem_Addr = 0;
CS = 2;
Mem_Write = 0;
// Wait 100 ns for global reset to finish
#10;
Mem_Addr = 0;
CS = 3;
Mem_Write = 0;
// Wait 100 ns for global reset to finish
#10;
Mem_Addr = 1;
CS = 0;
Mem_Write = 0;
// Wait 100 ns for global reset to finish
#10;
Mem_Addr = 1;
CS = 1;
Mem_Write = 0;
// Wait 100 ns for global reset to finish
#10;
Mem_Addr = 1;
CS = 2;
Mem_Write = 0;
// Wait 100 ns for global reset to finish
#10;
Mem_Addr = 1;
CS = 3;
Mem_Write = 0;
// Wait 100 ns for global reset to finish
#10;
end
always #1 Clk = ~Clk;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_comparator_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 6;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = C_VALUE;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
// file: system_clk_wiz_0_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1____25.000______0.000______50.0______181.828____104.359
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module system_clk_wiz_0_0_clk_wiz
(// Clock in ports
// Clock out ports
output clk_out1,
// Status and control signals
input resetn,
output locked,
input clk_in1
);
// Input buffering
//------------------------------------
wire clk_in1_system_clk_wiz_0_0;
wire clk_in2_system_clk_wiz_0_0;
IBUF clkin1_ibufg
(.O (clk_in1_system_clk_wiz_0_0),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire clk_out1_system_clk_wiz_0_0;
wire clk_out2_system_clk_wiz_0_0;
wire clk_out3_system_clk_wiz_0_0;
wire clk_out4_system_clk_wiz_0_0;
wire clk_out5_system_clk_wiz_0_0;
wire clk_out6_system_clk_wiz_0_0;
wire clk_out7_system_clk_wiz_0_0;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_system_clk_wiz_0_0;
wire clkfbout_buf_system_clk_wiz_0_0;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
wire reset_high;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (9.125),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (36.500),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.0))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_system_clk_wiz_0_0),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_system_clk_wiz_0_0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_system_clk_wiz_0_0),
.CLKIN1 (clk_in1_system_clk_wiz_0_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (reset_high));
assign reset_high = ~resetn;
assign locked = locked_int;
// Clock Monitor clock assigning
//--------------------------------------
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_system_clk_wiz_0_0),
.I (clkfbout_system_clk_wiz_0_0));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_system_clk_wiz_0_0));
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.7
// \ \ Application : MIG
// / / Filename : bank_queue.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : Virtex-6
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Bank machine queue controller.
//
// Bank machines are always associated with a queue. When the system is
// idle, all bank machines are in the idle queue. As requests are
// received, the bank machine at the head of the idle queue accepts
// the request, removes itself from the idle queue and places itself
// in a queue associated with the rank-bank of the new request.
//
// If the new request is to an idle rank-bank, a new queue is created
// for that rank-bank. If the rank-bank is not idle, then the new
// request is added to the end of the existing rank-bank queue.
//
// When the head of the idle queue accepts a new request, all other
// bank machines move down one in the idle queue. When the idle queue
// is empty, the memory interface deasserts its accept signal.
//
// When new requests are received, the first step is to classify them
// as to whether the request targets an already open rank-bank, and if
// so, does the new request also hit on the already open page? As mentioned
// above, a new request places itself in the existing queue for a
// rank-bank hit. If it is also detected that the last entry in the
// existing rank-bank queue has the same page, then the current tail
// sets a bit telling itself to pass the open row when the column
// command is issued. The "passee" knows its in the head minus one
// position and hence takes control of the rank-bank.
//
// Requests are retired out of order to optimize DRAM array resources.
// However it is required that the user cannot "observe" this out of
// order processing as a data corruption. An ordering queue is
// used to enforce some ordering rules. As controlled by a paramter,
// there can be no ordering (RELAXED), ordering of writes only (NORM), and
// strict (STRICT) ordering whereby input request ordering is
// strictly adhered to.
//
// Note that ordering applies only to column commands. Row commands
// such as activate and precharge are allowed to proceed in any order
// with the proviso that within a rank-bank row commands are processed in
// the request order.
//
// When a bank machine accepts a new request, it looks at the ordering
// mode. If no ordering, nothing is done. If strict ordering, then
// it always places itself at the end of the ordering queue. If "normal"
// or write ordering, the row machine places itself in the ordering
// queue only if the new request is a write. The bank state machine
// looks at the ordering queue, and will only issue a column
// command when it sees itself at the head of the ordering queue.
//
// When a bank machine has completed its request, it must re-enter the
// idle queue. This is done by setting the idle_r bit, and setting q_entry_r
// to the idle count.
//
// There are several situations where more than one bank machine
// will enter the idle queue simultaneously. If two or more
// simply use the idle count to place themselves in the idle queue, multiple
// bank machines will end up at the same location in the idle queue, which
// is illegal.
//
// Based on the bank machine instance numbers, a count is made of
// the number of bank machines entering idle "below" this instance. This
// number is added to the idle count to compute the location in
// idle queue.
//
// There is also a single bit computed that says there were bank machines
// entering the idle queue "above" this instance. This is used to
// compute the tail bit.
//
// The word "queue" is used frequently to describe the behavior of the
// bank_queue block. In reality, there are no queues in the ordinary sense.
// As instantiated in this block, each bank machine has a q_entry_r number.
// This number represents the position of the bank machine in its current
// queue. At any given time, a bank machine may be in the idle queue,
// one of the dynamic rank-bank queues, or a single entry manitenance queue.
// A complete description of which queue a bank machine is currently in is
// given by idle_r, its rank-bank, mainteance status and its q_entry_r number.
//
// DRAM refresh and ZQ have a private single entry queue/channel. However,
// when a refresh request is made, it must be injected into the main queue
// properly. At the time of injection, the refresh rank is compared against
// all entryies in the queue. For those that match, if timing allows, and
// they are the tail of the rank-bank queue, then the auto_pre bit is set.
// Otherwise precharge is in progress. This results in a fully precharged
// rank.
//
// At the time of injection, the refresh channel builds a bit
// vector of queue entries that hit on the refresh rank. Once all
// of these entries finish, the refresh is forced in at the row arbiter.
//
// New requests that come after the refresh request will notice that
// a refresh is in progress for their rank and wait for the refresh
// to finish before attempting to arbitrate to send an activate.
//
// Injection of a refresh sets the q_has_rd bit for all queues hitting
// on the refresh rank. This insures a starved write request will not
// indefinitely hold off a refresh.
//
// Periodic reads are required to compare themselves against requests
// that are in progress. Adding a unique compare channel for this
// is not worthwhile. Periodic read requests inhibit the accept
// signal and override any new request that might be trying to
// enter the queue.
//
// Once a periodic read has entered the queue it is nearly indistinguishable
// from a normal read request. The req_periodic_rd_r bit is set for
// queue entry. This signal is used to inhibit the rd_data_en signal.
`timescale 1ps/1ps
`define BM_SHARED_BV (ID+nBANK_MACHS-1):(ID+1)
module bank_queue #
(
parameter TCQ = 100,
parameter BM_CNT_WIDTH = 2,
parameter nBANK_MACHS = 4,
parameter ORDERING = "NORM",
parameter ID = 0
)
(/*AUTOARG*/
// Outputs
head_r, tail_r, idle_ns, idle_r, pass_open_bank_ns,
pass_open_bank_r, auto_pre_r, bm_end, passing_open_bank,
ordered_issued, ordered_r, order_q_zero, rcv_open_bank,
rb_hit_busies_r, q_has_rd, q_has_priority, wait_for_maint_r,
// Inputs
clk, rst, accept_internal_r, use_addr, periodic_rd_ack_r, bm_end_in,
idle_cnt, rb_hit_busy_cnt, accept_req, rb_hit_busy_r, maint_idle,
maint_hit, row_hit_r, pre_wait_r, allow_auto_pre, sending_col,
bank_wait_in_progress, precharge_bm_end, req_wr_r, rd_wr_r,
adv_order_q, order_cnt, rb_hit_busy_ns_in, passing_open_bank_in,
was_wr, maint_req_r, was_priority
);
localparam ZERO = 0;
localparam ONE = 1;
localparam [BM_CNT_WIDTH-1:0] BM_CNT_ZERO = ZERO[0+:BM_CNT_WIDTH];
localparam [BM_CNT_WIDTH-1:0] BM_CNT_ONE = ONE[0+:BM_CNT_WIDTH];
input clk;
input rst;
// Decide if this bank machine should accept a new request.
reg idle_r_lcl;
reg head_r_lcl;
input accept_internal_r;
wire bm_ready = idle_r_lcl && head_r_lcl && accept_internal_r;
// Accept request in this bank machine. Could be maintenance or
// regular request.
input use_addr;
input periodic_rd_ack_r;
wire accept_this_bm = bm_ready && (use_addr || periodic_rd_ack_r);
// Multiple machines may enter the idle queue in a single state.
// Based on bank machine instance number, compute how many
// bank machines with lower instance numbers are entering
// the idle queue.
input [(nBANK_MACHS*2)-1:0] bm_end_in;
reg [BM_CNT_WIDTH-1:0] idlers_below;
integer i;
always @(/*AS*/bm_end_in) begin
idlers_below = BM_CNT_ZERO;
for (i=0; i<ID; i=i+1)
idlers_below = idlers_below + bm_end_in[i];
end
reg idlers_above;
always @(/*AS*/bm_end_in) begin
idlers_above = 1'b0;
for (i=ID+1; i<ID+nBANK_MACHS; i=i+1)
idlers_above = idlers_above || bm_end_in[i];
end
`ifdef MC_SVA
bm_end_and_idlers_above: cover property (@(posedge clk)
(~rst && bm_end && idlers_above));
bm_end_and_idlers_below: cover property (@(posedge clk)
(~rst && bm_end && |idlers_below));
`endif
// Compute the q_entry number.
input [BM_CNT_WIDTH-1:0] idle_cnt;
input [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt;
input accept_req;
wire bm_end_lcl;
reg adv_queue = 1'b0;
reg [BM_CNT_WIDTH-1:0] q_entry_r;
reg [BM_CNT_WIDTH-1:0] q_entry_ns;
always @(/*AS*/accept_req or accept_this_bm or adv_queue
or bm_end_lcl or idle_cnt or idle_r_lcl or idlers_below
or q_entry_r or rb_hit_busy_cnt or rst) begin
if (rst) q_entry_ns = ID[BM_CNT_WIDTH-1:0];
else begin
q_entry_ns = q_entry_r;
if ((~idle_r_lcl && adv_queue) ||
(idle_r_lcl && accept_req && ~accept_this_bm))
q_entry_ns = q_entry_r - BM_CNT_ONE;
if (accept_this_bm)
q_entry_ns = rb_hit_busy_cnt - (adv_queue ? BM_CNT_ONE : BM_CNT_ZERO);
if (bm_end_lcl) begin
q_entry_ns = idle_cnt + idlers_below;
if (accept_req) q_entry_ns = q_entry_ns - BM_CNT_ONE;
end
end
end
always @(posedge clk) q_entry_r <= #TCQ q_entry_ns;
// Determine if this entry is the head of its queue.
reg head_ns;
always @(/*AS*/accept_req or accept_this_bm or adv_queue
or bm_end_lcl or head_r_lcl or idle_cnt or idle_r_lcl
or idlers_below or q_entry_r or rb_hit_busy_cnt or rst) begin
if (rst) head_ns = ~|ID[BM_CNT_WIDTH-1:0];
else begin
head_ns = head_r_lcl;
if (accept_this_bm)
head_ns = ~|(rb_hit_busy_cnt - (adv_queue ? BM_CNT_ONE : BM_CNT_ZERO));
if ((~idle_r_lcl && adv_queue) ||
(idle_r_lcl && accept_req && ~accept_this_bm))
head_ns = ~|(q_entry_r - BM_CNT_ONE);
if (bm_end_lcl) begin
head_ns = ~|(idle_cnt - (accept_req ? BM_CNT_ONE : BM_CNT_ZERO)) &&
~|idlers_below;
end
end
end
always @(posedge clk) head_r_lcl <= #TCQ head_ns;
output wire head_r;
assign head_r = head_r_lcl;
// Determine if this entry is the tail of its queue. Note that
// an entry can be both head and tail.
input rb_hit_busy_r;
reg tail_r_lcl = 1'b1;
generate
if (nBANK_MACHS > 1) begin : compute_tail
reg tail_ns;
always @(accept_req or accept_this_bm
or bm_end_in or bm_end_lcl or idle_r_lcl
or idlers_above or rb_hit_busy_r or rst or tail_r_lcl) begin
if (rst) tail_ns = (ID == nBANK_MACHS);
// The order of the statements below is important in the case where
// another bank machine is retiring and this bank machine is accepting.
else begin
tail_ns = tail_r_lcl;
if ((accept_req && rb_hit_busy_r) ||
(|bm_end_in[`BM_SHARED_BV] && idle_r_lcl))
tail_ns = 1'b0;
if (accept_this_bm || (bm_end_lcl && ~idlers_above)) tail_ns = 1'b1;
end
end
always @(posedge clk) tail_r_lcl <= #TCQ tail_ns;
end // if (nBANK_MACHS > 1)
endgenerate
output wire tail_r;
assign tail_r = tail_r_lcl;
wire clear_req = bm_end_lcl || rst;
// Is this entry in the idle queue?
reg idle_ns_lcl;
always @(/*AS*/accept_this_bm or clear_req or idle_r_lcl) begin
idle_ns_lcl = idle_r_lcl;
if (accept_this_bm) idle_ns_lcl = 1'b0;
if (clear_req) idle_ns_lcl = 1'b1;
end
always @(posedge clk) idle_r_lcl <= #TCQ idle_ns_lcl;
output wire idle_ns;
assign idle_ns = idle_ns_lcl;
output wire idle_r;
assign idle_r = idle_r_lcl;
// Maintenance hitting on this active bank machine is in progress.
input maint_idle;
input maint_hit;
wire maint_hit_this_bm = ~maint_idle && maint_hit;
// Does new request hit on this bank machine while it is able to pass the
// open bank?
input row_hit_r;
input pre_wait_r;
wire pass_open_bank_eligible =
tail_r_lcl && rb_hit_busy_r && row_hit_r && ~pre_wait_r;
// Set pass open bank bit, but not if request preceded active maintenance.
reg wait_for_maint_r_lcl;
reg pass_open_bank_r_lcl;
wire pass_open_bank_ns_lcl = ~clear_req &&
(pass_open_bank_r_lcl ||
(accept_req && pass_open_bank_eligible &&
(~maint_hit_this_bm || wait_for_maint_r_lcl)));
always @(posedge clk) pass_open_bank_r_lcl <= #TCQ pass_open_bank_ns_lcl;
output wire pass_open_bank_ns;
assign pass_open_bank_ns = pass_open_bank_ns_lcl;
output wire pass_open_bank_r;
assign pass_open_bank_r = pass_open_bank_r_lcl;
`ifdef MC_SVA
pass_open_bank: cover property (@(posedge clk) (~rst && pass_open_bank_ns));
pass_open_bank_killed_by_maint: cover property (@(posedge clk)
(~rst && accept_req && pass_open_bank_eligible &&
maint_hit_this_bm && ~wait_for_maint_r_lcl));
pass_open_bank_following_maint: cover property (@(posedge clk)
(~rst && accept_req && pass_open_bank_eligible &&
maint_hit_this_bm && wait_for_maint_r_lcl));
`endif
// Should the column command be sent with the auto precharge bit set? This
// will happen when it is detected that next request is to a different row,
// or the next reqest is the next request is refresh to this rank.
reg auto_pre_r_lcl;
reg auto_pre_ns;
input allow_auto_pre;
always @(/*AS*/accept_req or allow_auto_pre or auto_pre_r_lcl
or clear_req or maint_hit_this_bm or rb_hit_busy_r
or row_hit_r or tail_r_lcl or wait_for_maint_r_lcl) begin
auto_pre_ns = auto_pre_r_lcl;
if (clear_req) auto_pre_ns = 1'b0;
else
if (accept_req && tail_r_lcl && allow_auto_pre && rb_hit_busy_r &&
(~row_hit_r || (maint_hit_this_bm && ~wait_for_maint_r_lcl)))
auto_pre_ns = 1'b1;
end
always @(posedge clk) auto_pre_r_lcl <= #TCQ auto_pre_ns;
output wire auto_pre_r;
assign auto_pre_r = auto_pre_r_lcl;
`ifdef MC_SVA
auto_precharge: cover property (@(posedge clk) (~rst && auto_pre_ns));
maint_triggers_auto_precharge: cover property (@(posedge clk)
(~rst && auto_pre_ns && ~auto_pre_r && row_hit_r));
`endif
// Determine when the current request is finished.
input sending_col;
input req_wr_r;
input rd_wr_r;
wire sending_col_not_rmw_rd = sending_col && !(req_wr_r && rd_wr_r);
input bank_wait_in_progress;
input precharge_bm_end;
reg pre_bm_end_r;
wire pre_bm_end_ns = precharge_bm_end ||
(bank_wait_in_progress && pass_open_bank_ns_lcl);
always @(posedge clk) pre_bm_end_r <= #TCQ pre_bm_end_ns;
assign bm_end_lcl =
pre_bm_end_r || (sending_col_not_rmw_rd && pass_open_bank_r_lcl);
output wire bm_end;
assign bm_end = bm_end_lcl;
// Determine that the open bank should be passed to the successor bank machine.
reg pre_passing_open_bank_r;
wire pre_passing_open_bank_ns =
bank_wait_in_progress && pass_open_bank_ns_lcl;
always @(posedge clk) pre_passing_open_bank_r <= #TCQ
pre_passing_open_bank_ns;
output wire passing_open_bank;
assign passing_open_bank =
pre_passing_open_bank_r || (sending_col_not_rmw_rd && pass_open_bank_r_lcl);
reg ordered_ns;
wire set_order_q = ((ORDERING == "STRICT") || ((ORDERING == "NORM") &&
req_wr_r)) && accept_this_bm;
wire ordered_issued_lcl =
sending_col_not_rmw_rd && !(req_wr_r && rd_wr_r) &&
((ORDERING == "STRICT") || ((ORDERING == "NORM") && req_wr_r));
output wire ordered_issued;
assign ordered_issued = ordered_issued_lcl;
reg ordered_r_lcl;
always @(/*AS*/ordered_issued_lcl or ordered_r_lcl or rst
or set_order_q) begin
if (rst) ordered_ns = 1'b0;
else begin
ordered_ns = ordered_r_lcl;
// Should never see accept_this_bm and adv_order_q at the same time.
if (set_order_q) ordered_ns = 1'b1;
if (ordered_issued_lcl) ordered_ns = 1'b0;
end
end
always @(posedge clk) ordered_r_lcl <= #TCQ ordered_ns;
output wire ordered_r;
assign ordered_r = ordered_r_lcl;
// Figure out when to advance the ordering queue.
input adv_order_q;
input [BM_CNT_WIDTH-1:0] order_cnt;
reg [BM_CNT_WIDTH-1:0] order_q_r;
reg [BM_CNT_WIDTH-1:0] order_q_ns;
always @(/*AS*/adv_order_q or order_cnt or order_q_r or rst
or set_order_q) begin
order_q_ns = order_q_r;
if (rst) order_q_ns = BM_CNT_ZERO;
if (set_order_q)
if (adv_order_q) order_q_ns = order_cnt - BM_CNT_ONE;
else order_q_ns = order_cnt;
if (adv_order_q && |order_q_r) order_q_ns = order_q_r - BM_CNT_ONE;
end
always @(posedge clk) order_q_r <= #TCQ order_q_ns;
output wire order_q_zero;
assign order_q_zero = ~|order_q_r ||
(adv_order_q && (order_q_r == BM_CNT_ONE)) ||
((ORDERING == "NORM") && rd_wr_r);
// Keep track of which other bank machine are ahead of this one in a
// rank-bank queue. This is necessary to know when to advance this bank
// machine in the queue, and when to update bank state machine counter upon
// passing a bank.
input [(nBANK_MACHS*2)-1:0] rb_hit_busy_ns_in;
reg [(nBANK_MACHS*2)-1:0] rb_hit_busies_r_lcl = {nBANK_MACHS*2{1'b0}};
input [(nBANK_MACHS*2)-1:0] passing_open_bank_in;
output reg rcv_open_bank = 1'b0;
generate
if (nBANK_MACHS > 1) begin : rb_hit_busies
// The clear_vector resets bits in the rb_hit_busies vector as bank machines
// completes requests. rst also resets all the bits.
wire [nBANK_MACHS-2:0] clear_vector =
({nBANK_MACHS-1{rst}} | bm_end_in[`BM_SHARED_BV]);
// As this bank machine takes on a new request, capture the vector of
// which other bank machines are in the same queue.
wire [`BM_SHARED_BV] rb_hit_busies_ns =
~clear_vector &
(idle_ns_lcl
? rb_hit_busy_ns_in[`BM_SHARED_BV]
: rb_hit_busies_r_lcl[`BM_SHARED_BV]);
always @(posedge clk) rb_hit_busies_r_lcl[`BM_SHARED_BV] <=
#TCQ rb_hit_busies_ns;
// Compute when to advance this queue entry based on seeing other bank machines
// in the same queue finish.
always @(bm_end_in or rb_hit_busies_r_lcl)
adv_queue =
|(bm_end_in[`BM_SHARED_BV] & rb_hit_busies_r_lcl[`BM_SHARED_BV]);
// Decide when to receive an open bank based on knowing this bank machine is
// one entry from the head, and a passing_open_bank hits on the
// rb_hit_busies vector.
always @(idle_r_lcl
or passing_open_bank_in or q_entry_r
or rb_hit_busies_r_lcl) rcv_open_bank =
|(rb_hit_busies_r_lcl[`BM_SHARED_BV] & passing_open_bank_in[`BM_SHARED_BV])
&& (q_entry_r == BM_CNT_ONE) && ~idle_r_lcl;
end
endgenerate
output wire [nBANK_MACHS*2-1:0] rb_hit_busies_r;
assign rb_hit_busies_r = rb_hit_busies_r_lcl;
// Keep track if the queue this entry is in has priority content.
input was_wr;
input maint_req_r;
reg q_has_rd_r;
wire q_has_rd_ns = ~clear_req &&
(q_has_rd_r || (accept_req && rb_hit_busy_r && ~was_wr) ||
(maint_req_r && maint_hit && ~idle_r_lcl));
always @(posedge clk) q_has_rd_r <= #TCQ q_has_rd_ns;
output wire q_has_rd;
assign q_has_rd = q_has_rd_r;
input was_priority;
reg q_has_priority_r;
wire q_has_priority_ns = ~clear_req &&
(q_has_priority_r || (accept_req && rb_hit_busy_r && was_priority));
always @(posedge clk) q_has_priority_r <= #TCQ q_has_priority_ns;
output wire q_has_priority;
assign q_has_priority = q_has_priority_r;
// Figure out if this entry should wait for maintenance to end.
wire wait_for_maint_ns = ~rst && ~maint_idle &&
(wait_for_maint_r_lcl || (maint_hit && accept_this_bm));
always @(posedge clk) wait_for_maint_r_lcl <= #TCQ wait_for_maint_ns;
output wire wait_for_maint_r;
assign wait_for_maint_r = wait_for_maint_r_lcl;
endmodule // bank_queue
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:54:18 08/11/2009
// Design Name:
// Module Name: STATUS_OUT
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////
/////
///// Generate four patterns for specific states
///// Idle 00000000
///// Reset 01010101
///// FIFO full 00001111
///// Training_done 00110011
/////
/////////////////////////////////////////////////////////////////////////////////
module RCB_FRL_STATUS_OUT( CLK,
RESET, // input indicating whether channel is reset, reset pulse of the whole lvds channel
MODULE_RST, // reset pulse for this module only, should be shorter than RESET
FIFO_FULL, // input indicating whether FIFO is FULL
TRAINING_DONE, // input indicating whether TRAINING is done
STATUS,
INT_SAT // coded status output
);
/////////////////////////////////////////////////////////////////////////////////
input CLK;
input MODULE_RST;
input RESET,
FIFO_FULL,
TRAINING_DONE;
output STATUS;
/////////////////////////////////////////////////////////////////////////////////
reg STATUS;
output reg [1:0] INT_SAT;
parameter RST = 2'b00;
parameter FULL = 2'b01;
parameter DONE = 2'b10;
parameter IDLE = 2'b11;
reg [2:0] counter;
wire MODULE_RST_one;
rising_edge_detect MODULE_RESET_one_inst(
.clk(CLK),
.rst(1'b0),
.in(MODULE_RST),
.one_shot_out(MODULE_RST_one)
);
/////////////////////////////////////////////////////////////////////////////////
/// Determine which state it is
always @ ( posedge CLK ) begin
if ( counter == 3'b000 ) begin
if ( RESET == 1'b1 ) begin
INT_SAT <= RST;
end
else if ( FIFO_FULL == 1'b1 & TRAINING_DONE == 1'b1 ) begin
INT_SAT <= FULL;
end
else if ( TRAINING_DONE == 1'b1 ) begin
INT_SAT <= DONE;
end
else begin
INT_SAT <= IDLE;
end
end
end
/////////////////////////////////////////////////////////////////////////////////
/// Counter runs
always @ ( posedge CLK ) begin
// if ( MODULE_RST == 1'b1 ) begin // Jiansong: how can it send out reset status
if ( MODULE_RST_one == 1'b1 ) begin
counter <= 3'b000;
end
else begin
counter <= counter + 3'b001;
end
end
/////////////////////////////////////////////////////////////////////////////////
/// pattern encode
/// Idle 00000000
/// Reset 01010101
/// FIFO_full 00001111
/// Train Done 00110011
always @ ( posedge CLK) begin
if ( INT_SAT == RST ) begin
if ( counter == 3'b000 | counter == 3'b010 | counter == 3'b100 | counter == 3'b110 ) begin
STATUS <= 1'b0;
end
else if (counter == 3'b001 | counter == 3'b011 | counter == 3'b101 | counter == 3'b111 ) begin
STATUS <= 1'b1;
end
end
else if ( INT_SAT == FULL) begin
if (counter == 3'b000 | counter == 3'b001 | counter == 3'b010 | counter == 3'b011 ) begin
STATUS <= 1'b0;
end
else if ( counter == 3'b100 | counter == 3'b101 | counter == 3'b110 | counter == 3'b111 ) begin
STATUS <= 1'b1;
end
end
else if ( INT_SAT == DONE) begin
if ( counter == 3'b000 | counter == 3'b001 | counter == 3'b100 | counter == 3'b101 ) begin
STATUS <= 1'b0;
end
else if ( counter == 3'b010 | counter == 3'b011 | counter == 3'b110 | counter == 3'b111 )begin
STATUS <= 1'b1;
end
end
else if ( INT_SAT == IDLE) begin
STATUS <= 1'b0;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg b;
wire vconst1 = 1'b0;
wire vconst2 = !(vconst1);
wire vconst3 = !vconst2;
wire vconst = vconst3;
wire qa;
wire qb;
wire qc;
wire qd;
wire qe;
ta ta (.b(b), .vconst(vconst), .q(qa));
tb tb (.clk(clk), .vconst(vconst), .q(qb));
tc tc (.b(b), .vconst(vconst), .q(qc));
td td (.b(b), .vconst(vconst), .q(qd));
te te (.clk(clk), .b(b), .vconst(vconst), .q(qe));
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$display("%b",{qa,qb,qc,qd,qe});
`endif
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
b <= 1'b1;
end
if (cyc==2) begin
if (qa!=1'b1) $stop;
if (qb!=1'b0) $stop;
if (qd!=1'b0) $stop;
b <= 1'b0;
end
if (cyc==3) begin
if (qa!=1'b0) $stop;
if (qb!=1'b0) $stop;
if (qd!=1'b0) $stop;
if (qe!=1'b0) $stop;
b <= 1'b1;
end
if (cyc==4) begin
if (qa!=1'b1) $stop;
if (qb!=1'b0) $stop;
if (qd!=1'b0) $stop;
if (qe!=1'b1) $stop;
b <= 1'b0;
end
if (cyc==5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module ta (
input vconst,
input b,
output reg q);
always @ (/*AS*/b or vconst) begin
q = vconst | b;
end
endmodule
module tb (
input vconst,
input clk,
output reg q);
always @ (posedge clk) begin
q <= vconst;
end
endmodule
module tc (
input vconst,
input b,
output reg q);
always @ (posedge vconst) begin
q <= b;
$stop;
end
endmodule
module td (
input vconst,
input b,
output reg q);
always @ (/*AS*/vconst) begin
q = vconst;
end
endmodule
module te (
input clk,
input vconst,
input b,
output reg q);
reg qmid;
always @ (posedge vconst or posedge clk) begin
qmid <= b;
end
always @ (posedge clk or posedge vconst) begin
q <= qmid;
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_data_shift.v
// Version: 1.0
// Verilog Standard: Verilog-2001
//
// Description: The TX Data Shift module takes arbitrarily 32-bit aligned data
// from the WR_TX_DATA interface and shifts the data so that it is 0-bit aligned
// on the output RD_TX_DATA interface. The VALID, END_OFFSET, and END_FLAG signal
// in the WR_TX_DATA interface are replaced by WORD_VALID and END_FLAGS signals in
// the RD_TX_DATA interface. Each bit in the WORD_VALID bus indicates that the
// corresponding dword in the RD_TX_DATA bus is valid. Each bit in the END_FLAGS
// bus indicates that the end of the payload occurs at the corresponding dword in
// the RD_TX_DATA bus.
//
// The core of the TX_DATA_SHIFT module is a set of N multiplexers, where N =
// (C_DATA_WIDTH/32). The multiplexers are surrounded by a set of optional
// input and output registers with output wires wWrTxData* and input wires
// wRdTxData*. Each register in the array rMuxSelect choses which mux input
// desplay on the mux output. The values of the registers are set based on the
// value of wWrTxDataStartOffset. These registers are enabled when
// wWrTxDataStartFlag is 1 and their value set based on the value of
// wWrTxDataStartOffset.
//
// Each bit in the VALID bus is determined by the result of two masks,
// wRdTxEndFlagMask and wRdTxStartFlagMask, to make wRdTxDataValid. The start flag
// mask is active when wWrTxDataStartFlag is 1, based on wWrTxDataStartOffset. The
// end flag mask is active when wWrTxDataEndFlag is 1, based on
// wWrTxDataEndOffset.
//
// TODO:
// - Using WORD_VALID is a little bit confusing. I should bring back VALID as well
// - WORD_VALID should be DWORD_VALID
// - Use a uniform naming scheme for C_DATA_WIDTH/32
// - Is there a more efficient way to implement the wRdTxStartMaskFlag? Perhaps using the reset of a register?
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh"
module tx_data_shift
#(
parameter C_PIPELINE_OUTPUT = 1,
parameter C_PIPELINE_INPUT = 1,
parameter C_DATA_WIDTH = 128,
parameter C_VENDOR = "ALTERA"
)
(
// Interface: Clocks
input CLK,
// Interface: Reset
input RST_IN,
// Interface: WR TX DATA
input WR_TX_DATA_VALID,
input [C_DATA_WIDTH-1:0] WR_TX_DATA,
input WR_TX_DATA_START_FLAG,
input [clog2s(C_DATA_WIDTH/32)-1:0] WR_TX_DATA_START_OFFSET,
input WR_TX_DATA_END_FLAG,
input [clog2s(C_DATA_WIDTH/32)-1:0] WR_TX_DATA_END_OFFSET,
output WR_TX_DATA_READY,
// Interface: RD TX DATA
input RD_TX_DATA_READY,
output [C_DATA_WIDTH-1:0] RD_TX_DATA,
output RD_TX_DATA_START_FLAG,
output [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_WORD_VALID,
output [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_END_FLAGS,
output RD_TX_DATA_VALID
);
localparam C_ROTATE_BITS = clog2s(C_DATA_WIDTH/32);
localparam C_NUM_MUXES = (C_DATA_WIDTH/32);
localparam C_SELECT_WIDTH = C_DATA_WIDTH/32;
localparam C_MASK_WIDTH = C_DATA_WIDTH/32;
localparam C_AGGREGATE_WIDTH = C_DATA_WIDTH;
genvar i;
wire wWrTxDataValid;
wire [C_DATA_WIDTH-1:0] wWrTxData;
wire wWrTxDataStartFlag;
wire [clog2s(C_DATA_WIDTH/32)-1:0] wWrTxDataStartOffset;
wire wWrTxDataEndFlag;
wire [clog2s(C_DATA_WIDTH/32)-1:0] wWrTxDataEndOffset;
wire [(C_DATA_WIDTH/32)-1:0] wWrTxEndFlagMask;
wire [(C_DATA_WIDTH/32)-1:0] wWrTxDataEndFlags;
wire wWrTxDataReady;
wire wRdTxDataReady;
wire [C_DATA_WIDTH-1:0] wRdTxData;
wire wRdTxDataStartFlag;
wire [(C_DATA_WIDTH/32)-1:0] wRdTxDataEndFlags;
wire [(C_DATA_WIDTH/32)-1:0] wRdTxDataWordValid;
wire [(C_DATA_WIDTH/32)-1:0] wRdTxStartFlagMask;
wire [(C_DATA_WIDTH/32)-1:0] wRdTxEndFlagMask;
wire wRdTxDataValid;
// wSelectDefault is the default select value for each mux, 1 << i where i
// is the mux/dword index.
wire [C_SELECT_WIDTH-1:0] wSelectDefault[C_NUM_MUXES-1:0];
// wSelectRotated is the value the select for each mux after the data's
// start offset has been applied and until the end flag is seen.
wire [C_SELECT_WIDTH-1:0] wSelectRotated[C_NUM_MUXES-1:0];
reg [C_SELECT_WIDTH-1:0] rMuxSelect[C_NUM_MUXES-1:0],_rMuxSelect[C_NUM_MUXES-1:0];
reg [clog2s(C_DATA_WIDTH/32)-1:0] rStartOffset,_rStartOffset;
assign wWrTxDataReady = wRdTxDataReady;
assign wRdTxStartFlagMask = wWrTxDataStartFlag ?
{(C_DATA_WIDTH/32){1'b1}} >> wWrTxDataStartOffset:
{(C_DATA_WIDTH/32){1'b1}};
assign wRdTxDataWordValid = wRdTxEndFlagMask & wRdTxStartFlagMask;
assign wRdTxDataStartFlag = wWrTxDataStartFlag;
assign wRdTxDataValid = wWrTxDataValid;
generate
for (i = 0; i < C_NUM_MUXES; i = i + 1) begin : gen_mux_default
assign wSelectDefault[i] = (1 << i);
end
endgenerate
always @(*) begin
_rStartOffset = WR_TX_DATA_START_OFFSET;
end
always @(posedge CLK) begin
if(WR_TX_DATA_READY & WR_TX_DATA_START_FLAG & WR_TX_DATA_VALID) begin
rStartOffset <= _rStartOffset;
end
end
generate
for (i = 0; i < C_NUM_MUXES; i = i + 1) begin : gen_mux_select
always @(*) begin
_rMuxSelect[i] = wSelectRotated[i];
end
always @(posedge CLK) begin
if(WR_TX_DATA_READY & WR_TX_DATA_START_FLAG) begin
rMuxSelect[i] <= _rMuxSelect[i];
end
end
end
endgenerate
pipeline
#(// Parameters
.C_WIDTH (C_DATA_WIDTH+2*(1+clog2s(C_DATA_WIDTH/32))),
.C_USE_MEMORY (0),
.C_DEPTH (C_PIPELINE_INPUT?1:0)
/*AUTOINSTPARAM*/)
input_register
(
// Outputs
.WR_DATA_READY (WR_TX_DATA_READY),
.RD_DATA ({wWrTxData,wWrTxDataStartFlag,wWrTxDataStartOffset,wWrTxDataEndFlag,wWrTxDataEndOffset}),
.RD_DATA_VALID (wWrTxDataValid),
// Inputs
.WR_DATA ({WR_TX_DATA,WR_TX_DATA_START_FLAG,WR_TX_DATA_START_OFFSET,
WR_TX_DATA_END_FLAG,WR_TX_DATA_END_OFFSET}),
.WR_DATA_VALID (WR_TX_DATA_VALID),
.RD_DATA_READY (wWrTxDataReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
// The pipeline carries the data bus and SOF/EOF.
pipeline
#(// Parameters
.C_WIDTH (C_DATA_WIDTH + 2*C_MASK_WIDTH + 1),
.C_USE_MEMORY (0),
.C_DEPTH ((C_PIPELINE_OUTPUT > 1) ? 1 : 0)
/*AUTOINSTPARAM*/)
output_register
(
// Outputs
.WR_DATA_READY (wRdTxDataReady),
.RD_DATA ({RD_TX_DATA,RD_TX_DATA_START_FLAG,
RD_TX_DATA_END_FLAGS,RD_TX_DATA_WORD_VALID}),
.RD_DATA_VALID (RD_TX_DATA_VALID),
// Inputs
.WR_DATA ({wRdTxData,wRdTxDataStartFlag,
wRdTxDataEndFlags,wRdTxDataWordValid}),
.WR_DATA_VALID (wRdTxDataValid),
.RD_DATA_READY (RD_TX_DATA_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
offset_to_mask
#(
.C_MASK_SWAP (0),
/*AUTOINSTPARAM*/
// Parameters
.C_MASK_WIDTH (C_MASK_WIDTH))
eof_convert
(
// Outputs
.MASK (wWrTxEndFlagMask),
// Inputs
.OFFSET_ENABLE (wWrTxDataEndFlag),
.OFFSET (wWrTxDataEndOffset)
/*AUTOINST*/);
rotate
#(
// Parameters
.C_DIRECTION ("RIGHT"),
.C_WIDTH (C_DATA_WIDTH/32)
/*AUTOINSTPARAM*/)
em_rotate_inst
(
// Outputs
.RD_DATA (wRdTxEndFlagMask),
// Inputs
.WR_DATA (wWrTxEndFlagMask),
.WR_SHIFTAMT (rStartOffset[clog2s(C_DATA_WIDTH/32)-1:0])
/*AUTOINST*/);
// Determine the 1-hot dword end flag
offset_flag_to_one_hot
#(
.C_WIDTH (C_DATA_WIDTH/32)
/*AUTOINSTPARAM*/)
ef_onehot_inst
(
// Outputs
.RD_ONE_HOT (wWrTxDataEndFlags),
// Inputs
.WR_OFFSET (wWrTxDataEndOffset[clog2s(C_DATA_WIDTH/32)-1:0]),
.WR_FLAG (wWrTxDataEndFlag)
/*AUTOINST*/);
rotate
#(
// Parameters
.C_DIRECTION ("RIGHT"),
.C_WIDTH (C_DATA_WIDTH/32)
/*AUTOINSTPARAM*/)
ef_rotate_inst
(
// Outputs
.RD_DATA (wRdTxDataEndFlags),
// Inputs
.WR_DATA (wWrTxDataEndFlags),
.WR_SHIFTAMT (rStartOffset[clog2s(C_DATA_WIDTH/32)-1:0])
/*AUTOINST*/);
generate
for (i = 0; i < C_NUM_MUXES; i = i + 1) begin : gen_rotates
rotate
#(
// Parameters
.C_DIRECTION ("LEFT"),
.C_WIDTH ((C_DATA_WIDTH/32))
/*AUTOINSTPARAM*/)
select_rotate_inst_
(
// Outputs
.RD_DATA (wSelectRotated[i]),
// Inputs
.WR_DATA (wSelectDefault[i]),
.WR_SHIFTAMT (WR_TX_DATA_START_OFFSET[C_ROTATE_BITS-1:0])
/*AUTOINST*/);
end
endgenerate
generate
for (i = 0; i < C_DATA_WIDTH/32; i = i + 1) begin : gen_multiplexers
one_hot_mux
#(
.C_DATA_WIDTH (32),
/*AUTOINSTPARAM*/
// Parameters
.C_SELECT_WIDTH (C_SELECT_WIDTH),
.C_AGGREGATE_WIDTH (C_AGGREGATE_WIDTH))
mux_inst_
(
// Inputs
.ONE_HOT_SELECT (rMuxSelect[i]),
// Outputs
.ONE_HOT_OUTPUT (wRdTxData[32*i +: 32]),
.ONE_HOT_INPUTS (wWrTxData)
/*AUTOINST*/);
end
endgenerate
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common/" "../../common/")
// End:
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// sign_extender.v
// Created: 5.16.2012
// Modified: 5.16.2012
//
// Generic sign extension module
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module sign_extender
#(
parameter
INPUT_WIDTH = 8,
OUTPUT_WIDTH = 16
)
(
input [INPUT_WIDTH-1:0] original,
output reg [OUTPUT_WIDTH-1:0] sign_extended_original
);
wire [OUTPUT_WIDTH-INPUT_WIDTH-1:0] sign_extend;
generate
genvar i;
for (i = 0; i < OUTPUT_WIDTH-INPUT_WIDTH; i = i + 1) begin : gen_sign_extend
assign sign_extend[i] = (original[INPUT_WIDTH-1]) ? 1'b1 : 1'b0;
end
endgenerate
always @ * begin
sign_extended_original = {sign_extend,original};
end
endmodule
|
`include "sd_defines.v"
module sd_controller_fifo_wba
(
// WISHBONE common
wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
// WISHBONE slave
//wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o,
wb_adr_i, // wb_sel_i,
//Avalon-to-wishbone
wb_ava_write_n, wb_ava_read_n, wb_ava_chipselect, wb_ava_waitrequest,
// WISHBONE master
//SD BUS
sd_cmd_dat_i,sd_cmd_out_o, sd_cmd_oe_o,
sd_dat_dat_i, sd_dat_out_o , sd_dat_oe_o, sd_clk_o_pad
//PLL CLK_IN
`ifdef SD_CLK_EXT
,sd_clk_i_pad
`endif
);
input wb_clk_i; // WISHBONE clock
input wb_rst_i; // WISHBONE reset
input [7:0] wb_dat_i; // WISHBONE data input
output [7:0] wb_dat_o; // WISHBONE data output
// WISHBONE error output
// WISHBONE slave
input [2:0] wb_adr_i; // WISHBONE address input
//input [3:0] wb_sel_i; // WISHBONE byte select input
//input wb_we_i; // WISHBONE write enable input
//input wb_cyc_i; // WISHBONE cycle input
input wb_ava_write_n; // WISHBONE-to-avalon write
input wb_ava_read_n; // WISHBONE-to-avalon read
input wb_ava_chipselect; // WISHBONE-to-avalon read
output wb_ava_waitrequest; // WISHBONE-to-avalon read
//input wb_stb_i; // WISHBONE strobe input
//output reg wb_ack_o; // WISHBONE acknowledge output
// WISHBONE master
input wire [3:0] sd_dat_dat_i;
output wire [3:0] sd_dat_out_o;
output wire sd_dat_oe_o;
input wire sd_cmd_dat_i;
output wire sd_cmd_out_o;
output wire sd_cmd_oe_o;
output sd_clk_o_pad;
wire sd_clk_i;
wire wb_we_i; // WISHBONE write enable input
wire wb_cyc_i; // WISHBONE cycle input
wire wb_stb_i; // WISHBONE strobe input
reg wb_ack_o; // WISHBONE acknowledge output
assign wb_we_i = (!wb_ava_write_n) & wb_ava_read_n;
assign wb_cyc_i = (!wb_ava_write_n) | (!wb_ava_read_n);
assign wb_stb_i = wb_ava_chipselect;
assign wb_ava_waitrequest = !wb_ack_o;
`ifdef SD_CLK_EXT
input sd_clk_i_pad;
`endif
`define tx_cmd_fifo 4'h0
`define rx_cmd_fifo 4'h1
`define tx_data_fifo 4'h2
`define rx_data_fifo 4'h3
`define status 4'h4
`define controll 4'h5
`define timer 4'h6
reg [7:0] controll_reg;
reg [7:0] status_reg;
reg [7:0] command_timeout_reg;
`ifdef SD_CLK_BUS_CLK
assign sd_clk_i = wb_clk_i;
`endif
`ifdef SD_CLK_EXT
assign sd_clk_i = sd_clk_i_pad;
`endif
assign sd_clk_o=sd_clk_i;
reg [1:0] wb_fifo_adr_i_writer;
reg [1:0] wb_fifo_adr_i_reader;
wire [1:0] wb_fifo_adr_i;
reg add_token_read;
wire [7:0] wb_fifo_dat_i;
wire [7:0] wb_fifo_dat_o;
reg [7:0] wb_dat_i_storage;
reg [7:0] wb_dat_o_i;
reg time_enable;
assign sd_clk_o_pad = sd_clk_i ;
assign wb_fifo_adr_i = add_token_read ? wb_fifo_adr_i_reader : wb_fifo_adr_i_writer;
assign wb_fifo_dat_i =wb_dat_i_storage;
assign wb_dat_o = wb_adr_i[0] ? wb_fifo_dat_o : wb_dat_o_i ;
wire [1:4]fifo_full ;
wire [1:4]fifo_empty;
reg wb_fifo_we_i;
reg wb_fifo_re_i;
wire [1:0] sd_adr_o;
wire [7:0] sd_dat_o;
wire [7:0] sd_dat_i;
sd_fifo sd_fifo_0
(
.wb_adr_i (wb_fifo_adr_i ),
.wb_dat_i (wb_fifo_dat_i),
.wb_dat_o (wb_fifo_dat_o ),
.wb_we_i (wb_fifo_we_i),
.wb_re_i (wb_fifo_re_i),
.wb_clk (wb_clk_i),
.sd_adr_i (sd_adr_o ),
.sd_dat_i (sd_dat_o),
.sd_dat_o (sd_dat_i ),
.sd_we_i (sd_we_o),
.sd_re_i (sd_re_o),
.sd_clk (sd_clk_o),
.fifo_full ( fifo_full ),
.fifo_empty (fifo_empty ),
.rst (wb_rst_i) // | controll_reg[0])
) ;
wire [1:0] sd_adr_o_cmd;
wire [7:0] sd_dat_i_cmd;
wire [7:0] sd_dat_o_cmd;
wire [1:0] sd_adr_o_dat;
wire [7:0] sd_dat_i_dat;
wire [7:0] sd_dat_o_dat;
wire [1:0] st_dat_t;
sd_cmd_phy sdc_cmd_phy_0
(
.sd_clk (sd_clk_o),
.rst (wb_rst_i ),//| controll_reg[0]),
.cmd_dat_i ( sd_cmd_dat_i ),
.cmd_dat_o (sd_cmd_out_o ),
.cmd_oe_o (sd_cmd_oe_o ),
.sd_adr_o (sd_adr_o_cmd),
.sd_dat_i (sd_dat_i_cmd),
.sd_dat_o (sd_dat_o_cmd),
.sd_we_o (sd_we_o_cmd),
.sd_re_o (sd_re_o_cmd),
.fifo_full ( fifo_full[1:2] ),
.fifo_empty ( fifo_empty [1:2]),
.start_dat_t (st_dat_t),
.fifo_acces_token (fifo_acces_token)
);
sd_data_phy sd_data_phy_0 (
.sd_clk (sd_clk_o),
.rst (wb_rst_i | controll_reg[0]),
.DAT_oe_o ( sd_dat_oe_o ),
.DAT_dat_o (sd_dat_out_o),
.DAT_dat_i (sd_dat_dat_i ),
.sd_adr_o (sd_adr_o_dat ),
.sd_dat_i (sd_dat_i_dat ),
.sd_dat_o (sd_dat_o_dat ),
.sd_we_o (sd_we_o_dat),
.sd_re_o (sd_re_o_dat),
.fifo_full ( fifo_full[3:4] ),
.fifo_empty ( fifo_empty [3:4]),
.start_dat (st_dat_t),
.fifo_acces (~fifo_acces_token)
);
assign sd_adr_o = fifo_acces_token ? sd_adr_o_cmd : sd_adr_o_dat;
assign sd_dat_o = fifo_acces_token ? sd_dat_o_cmd : sd_dat_o_dat;
assign sd_we_o = fifo_acces_token ? sd_we_o_cmd : sd_we_o_dat;
assign sd_re_o = fifo_acces_token ? sd_re_o_cmd : sd_re_o_dat;
assign sd_dat_i_dat = sd_dat_i;
assign sd_dat_i_cmd = sd_dat_i;
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
status_reg<=0;
else begin
status_reg[0] <= fifo_full[1];
status_reg[1] <= fifo_empty[2];
status_reg[2] <= fifo_full[3];
status_reg[3] <= fifo_empty[4];
end
end
reg delayed_ack;
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
wb_ack_o <=0;
else
wb_ack_o <=wb_stb_i & wb_cyc_i & ~wb_ack_o & delayed_ack;
end
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if ( wb_rst_i )begin
command_timeout_reg<=`TIME_OUT_TIME;
wb_dat_i_storage<=0;
controll_reg<=0;
wb_fifo_we_i<=0;
wb_fifo_adr_i_writer<=0;
time_enable<=0;
end
else if (wb_stb_i & wb_cyc_i & (~wb_ack_o))begin //CS
if (wb_we_i) begin
case (wb_adr_i)
`tx_cmd_fifo : begin
wb_fifo_adr_i_writer<=0;
wb_fifo_we_i<=1&!delayed_ack;
wb_dat_i_storage<=wb_dat_i;
command_timeout_reg<=`TIME_OUT_TIME;
time_enable<=1;
end
`tx_data_fifo : begin
wb_fifo_adr_i_writer<=2;
wb_fifo_we_i<=1&!delayed_ack;
wb_dat_i_storage<=wb_dat_i;
command_timeout_reg<=`TIME_OUT_TIME;
time_enable<=0;
end
`controll : controll_reg <= wb_dat_i;
endcase
end
end
else begin
// wb_fifo_adr_i_writer<=0;
wb_fifo_we_i<=0;
if (!status_reg[1])
time_enable<=0;
if ((command_timeout_reg!=0) && (time_enable))
command_timeout_reg<=command_timeout_reg-1;
end
end
always @(posedge wb_clk_i or posedge wb_rst_i )begin
if ( wb_rst_i) begin
add_token_read<=0;
delayed_ack<=0;
wb_fifo_re_i<=0;
wb_fifo_adr_i_reader<=0;
wb_dat_o_i<=0;
end
else begin
delayed_ack<=0;
wb_fifo_re_i<=0;
if (wb_stb_i & wb_cyc_i & (~wb_ack_o)) begin //C
delayed_ack<=delayed_ack+1;
add_token_read<=0;
if (!wb_we_i) begin
case (wb_adr_i)
`rx_cmd_fifo : begin
add_token_read<=1;
wb_fifo_adr_i_reader<=1;
wb_fifo_re_i<=1&delayed_ack;
end
`rx_data_fifo :begin
add_token_read<=1;
wb_fifo_adr_i_reader<=3;
wb_fifo_re_i<=1 & delayed_ack;
end
`status : wb_dat_o_i <= status_reg;
`timer : wb_dat_o_i <= command_timeout_reg;
endcase
end
end
end
end
//just to get rid of warnings....
endmodule
|
// megafunction wizard: %ALTFP_CONVERT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTFP_CONVERT
// ============================================================
// File Name: acl_fp_uitofp_double.v
// Megafunction Name(s):
// ALTFP_CONVERT
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altfp_convert CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" OPERATION="INT2FLOAT" ROUNDING="TO_NEAREST" WIDTH_DATA=33 WIDTH_EXP_INPUT=8 WIDTH_EXP_OUTPUT=11 WIDTH_INT=33 WIDTH_MAN_INPUT=23 WIDTH_MAN_OUTPUT=52 WIDTH_RESULT=64 clk_en clock dataa result
//VERSION_BEGIN 11.0 cbx_altbarrel_shift 2011:04:27:21:09:05:SJ cbx_altfp_convert 2011:04:27:21:09:05:SJ cbx_altpriority_encoder 2011:04:27:21:09:05:SJ cbx_altsyncram 2011:04:27:21:09:05:SJ cbx_cycloneii 2011:04:27:21:09:05:SJ cbx_lpm_abs 2011:04:27:21:09:05:SJ cbx_lpm_add_sub 2011:04:27:21:09:05:SJ cbx_lpm_compare 2011:04:27:21:09:05:SJ cbx_lpm_decode 2011:04:27:21:09:05:SJ cbx_lpm_divide 2011:04:27:21:09:05:SJ cbx_lpm_mux 2011:04:27:21:09:05:SJ cbx_mgl 2011:04:27:21:10:09:SJ cbx_stratix 2011:04:27:21:09:05:SJ cbx_stratixii 2011:04:27:21:09:05:SJ cbx_stratixiii 2011:04:27:21:09:05:SJ cbx_stratixv 2011:04:27:21:09:05:SJ cbx_util_mgl 2011:04:27:21:09:05:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" PIPELINE=2 SHIFTDIR="LEFT" SHIFTTYPE="LOGICAL" WIDTH=33 WIDTHDIST=6 aclr clk_en clock data distance result
//VERSION_BEGIN 11.0 cbx_altbarrel_shift 2011:04:27:21:09:05:SJ cbx_mgl 2011:04:27:21:10:09:SJ VERSION_END
//synthesis_resources = reg 71
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_double_altbarrel_shift_ssf
(
aclr,
clk_en,
clock,
data,
distance,
result) ;
input aclr;
input clk_en;
input clock;
input [32:0] data;
input [5:0] distance;
output [32:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [1:0] dir_pipe;
reg [32:0] sbit_piper1d;
reg [32:0] sbit_piper2d;
reg sel_pipec3r1d;
reg sel_pipec4r1d;
reg sel_pipec5r1d;
wire [6:0] dir_w;
wire direction_w;
wire [31:0] pad_w;
wire [230:0] sbit_w;
wire [5:0] sel_w;
wire [197:0] smux_w;
// synopsys translate_off
initial
dir_pipe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dir_pipe <= 2'b0;
else if (clk_en == 1'b1) dir_pipe <= {dir_w[5], dir_w[2]};
// synopsys translate_off
initial
sbit_piper1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sbit_piper1d <= 33'b0;
else if (clk_en == 1'b1) sbit_piper1d <= smux_w[98:66];
// synopsys translate_off
initial
sbit_piper2d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sbit_piper2d <= 33'b0;
else if (clk_en == 1'b1) sbit_piper2d <= smux_w[197:165];
// synopsys translate_off
initial
sel_pipec3r1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sel_pipec3r1d <= 1'b0;
else if (clk_en == 1'b1) sel_pipec3r1d <= distance[3];
// synopsys translate_off
initial
sel_pipec4r1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sel_pipec4r1d <= 1'b0;
else if (clk_en == 1'b1) sel_pipec4r1d <= distance[4];
// synopsys translate_off
initial
sel_pipec5r1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sel_pipec5r1d <= 1'b0;
else if (clk_en == 1'b1) sel_pipec5r1d <= distance[5];
assign
dir_w = {dir_pipe[1], dir_w[4:3], dir_pipe[0], dir_w[1:0], direction_w},
direction_w = 1'b0,
pad_w = {32{1'b0}},
result = sbit_w[230:198],
sbit_w = {sbit_piper2d, smux_w[164:99], sbit_piper1d, smux_w[65:0], data},
sel_w = {sel_pipec5r1d, sel_pipec4r1d, sel_pipec3r1d, distance[2:0]},
smux_w = {((({33{(sel_w[5] & (~ dir_w[5]))}} & {sbit_w[165], pad_w[31:0]}) | ({33{(sel_w[5] & dir_w[5])}} & {pad_w[31:0], sbit_w[197]})) | ({33{(~ sel_w[5])}} & sbit_w[197:165])), ((({33{(sel_w[4] & (~ dir_w[4]))}} & {sbit_w[148:132], pad_w[15:0]}) | ({33{(sel_w[4] & dir_w[4])}} & {pad_w[15:0], sbit_w[164:148]})) | ({33{(~ sel_w[4])}} & sbit_w[164:132])), ((({33{(sel_w[3] & (~ dir_w[3]))}} & {sbit_w[123:99], pad_w[7:0]}) | ({33{(sel_w[3] & dir_w[3])}} & {pad_w[7:0], sbit_w[131:107]})) | ({33{(~ sel_w[3])}} & sbit_w[131:99])), ((({33{(sel_w[2] & (~ dir_w[2]))}} & {sbit_w[94:66], pad_w[3:0]}) | ({33{(sel_w[2] & dir_w[2])}} & {pad_w[3:0], sbit_w[98:70]})) | ({33{(~ sel_w[2])}} & sbit_w[98:66])), ((({33{(sel_w[1] & (~ dir_w[1]))}} & {sbit_w[63:33], pad_w[1:0]}) | ({33{(sel_w[1] & dir_w[1])}} & {pad_w[1:0], sbit_w[65:35]})) | ({33{(~ sel_w[1])}} & sbit_w[65:33])), ((({33{(sel_w[0] & (~ dir_w[0]))}} & {sbit_w[31:0], pad_w[0]}) | ({33{(sel_w[0] & dir_w[0])}} & {pad_w[0], sbit_w[32:1]})) | ({33{(~ sel_w[0])}} & sbit_w[32:0]))};
endmodule //acl_fp_uitofp_double_altbarrel_shift_ssf
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" WIDTH=64 WIDTHAD=6 data q
//VERSION_BEGIN 11.0 cbx_altpriority_encoder 2011:04:27:21:09:05:SJ cbx_mgl 2011:04:27:21:10:09:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=32 WIDTHAD=5 data q
//VERSION_BEGIN 11.0 cbx_altpriority_encoder 2011:04:27:21:09:05:SJ cbx_mgl 2011:04:27:21:10:09:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q
//VERSION_BEGIN 11.0 cbx_altpriority_encoder 2011:04:27:21:09:05:SJ cbx_mgl 2011:04:27:21:10:09:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q
//VERSION_BEGIN 11.0 cbx_altpriority_encoder 2011:04:27:21:09:05:SJ cbx_mgl 2011:04:27:21:10:09:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q
//VERSION_BEGIN 11.0 cbx_altpriority_encoder 2011:04:27:21:09:05:SJ cbx_mgl 2011:04:27:21:10:09:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q
//VERSION_BEGIN 11.0 cbx_altpriority_encoder 2011:04:27:21:09:05:SJ cbx_mgl 2011:04:27:21:10:09:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_double_altpriority_encoder_3v7
(
data,
q) ;
input [1:0] data;
output [0:0] q;
assign
q = {data[1]};
endmodule //acl_fp_uitofp_double_altpriority_encoder_3v7
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q zero
//VERSION_BEGIN 11.0 cbx_altpriority_encoder 2011:04:27:21:09:05:SJ cbx_mgl 2011:04:27:21:10:09:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_double_altpriority_encoder_3e8
(
data,
q,
zero) ;
input [1:0] data;
output [0:0] q;
output zero;
assign
q = {data[1]},
zero = (~ (data[0] | data[1]));
endmodule //acl_fp_uitofp_double_altpriority_encoder_3e8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_double_altpriority_encoder_6v7
(
data,
q) ;
input [3:0] data;
output [1:0] q;
wire [0:0] wire_altpriority_encoder14_q;
wire [0:0] wire_altpriority_encoder15_q;
wire wire_altpriority_encoder15_zero;
acl_fp_uitofp_double_altpriority_encoder_3v7 altpriority_encoder14
(
.data(data[1:0]),
.q(wire_altpriority_encoder14_q));
acl_fp_uitofp_double_altpriority_encoder_3e8 altpriority_encoder15
(
.data(data[3:2]),
.q(wire_altpriority_encoder15_q),
.zero(wire_altpriority_encoder15_zero));
assign
q = {(~ wire_altpriority_encoder15_zero), ((wire_altpriority_encoder15_zero & wire_altpriority_encoder14_q) | ((~ wire_altpriority_encoder15_zero) & wire_altpriority_encoder15_q))};
endmodule //acl_fp_uitofp_double_altpriority_encoder_6v7
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q zero
//VERSION_BEGIN 11.0 cbx_altpriority_encoder 2011:04:27:21:09:05:SJ cbx_mgl 2011:04:27:21:10:09:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_double_altpriority_encoder_6e8
(
data,
q,
zero) ;
input [3:0] data;
output [1:0] q;
output zero;
wire [0:0] wire_altpriority_encoder16_q;
wire wire_altpriority_encoder16_zero;
wire [0:0] wire_altpriority_encoder17_q;
wire wire_altpriority_encoder17_zero;
acl_fp_uitofp_double_altpriority_encoder_3e8 altpriority_encoder16
(
.data(data[1:0]),
.q(wire_altpriority_encoder16_q),
.zero(wire_altpriority_encoder16_zero));
acl_fp_uitofp_double_altpriority_encoder_3e8 altpriority_encoder17
(
.data(data[3:2]),
.q(wire_altpriority_encoder17_q),
.zero(wire_altpriority_encoder17_zero));
assign
q = {(~ wire_altpriority_encoder17_zero), ((wire_altpriority_encoder17_zero & wire_altpriority_encoder16_q) | ((~ wire_altpriority_encoder17_zero) & wire_altpriority_encoder17_q))},
zero = (wire_altpriority_encoder16_zero & wire_altpriority_encoder17_zero);
endmodule //acl_fp_uitofp_double_altpriority_encoder_6e8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_double_altpriority_encoder_bv7
(
data,
q) ;
input [7:0] data;
output [2:0] q;
wire [1:0] wire_altpriority_encoder12_q;
wire [1:0] wire_altpriority_encoder13_q;
wire wire_altpriority_encoder13_zero;
acl_fp_uitofp_double_altpriority_encoder_6v7 altpriority_encoder12
(
.data(data[3:0]),
.q(wire_altpriority_encoder12_q));
acl_fp_uitofp_double_altpriority_encoder_6e8 altpriority_encoder13
(
.data(data[7:4]),
.q(wire_altpriority_encoder13_q),
.zero(wire_altpriority_encoder13_zero));
assign
q = {(~ wire_altpriority_encoder13_zero), (({2{wire_altpriority_encoder13_zero}} & wire_altpriority_encoder12_q) | ({2{(~ wire_altpriority_encoder13_zero)}} & wire_altpriority_encoder13_q))};
endmodule //acl_fp_uitofp_double_altpriority_encoder_bv7
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q zero
//VERSION_BEGIN 11.0 cbx_altpriority_encoder 2011:04:27:21:09:05:SJ cbx_mgl 2011:04:27:21:10:09:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_double_altpriority_encoder_be8
(
data,
q,
zero) ;
input [7:0] data;
output [2:0] q;
output zero;
wire [1:0] wire_altpriority_encoder18_q;
wire wire_altpriority_encoder18_zero;
wire [1:0] wire_altpriority_encoder19_q;
wire wire_altpriority_encoder19_zero;
acl_fp_uitofp_double_altpriority_encoder_6e8 altpriority_encoder18
(
.data(data[3:0]),
.q(wire_altpriority_encoder18_q),
.zero(wire_altpriority_encoder18_zero));
acl_fp_uitofp_double_altpriority_encoder_6e8 altpriority_encoder19
(
.data(data[7:4]),
.q(wire_altpriority_encoder19_q),
.zero(wire_altpriority_encoder19_zero));
assign
q = {(~ wire_altpriority_encoder19_zero), (({2{wire_altpriority_encoder19_zero}} & wire_altpriority_encoder18_q) | ({2{(~ wire_altpriority_encoder19_zero)}} & wire_altpriority_encoder19_q))},
zero = (wire_altpriority_encoder18_zero & wire_altpriority_encoder19_zero);
endmodule //acl_fp_uitofp_double_altpriority_encoder_be8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_double_altpriority_encoder_r08
(
data,
q) ;
input [15:0] data;
output [3:0] q;
wire [2:0] wire_altpriority_encoder10_q;
wire [2:0] wire_altpriority_encoder11_q;
wire wire_altpriority_encoder11_zero;
acl_fp_uitofp_double_altpriority_encoder_bv7 altpriority_encoder10
(
.data(data[7:0]),
.q(wire_altpriority_encoder10_q));
acl_fp_uitofp_double_altpriority_encoder_be8 altpriority_encoder11
(
.data(data[15:8]),
.q(wire_altpriority_encoder11_q),
.zero(wire_altpriority_encoder11_zero));
assign
q = {(~ wire_altpriority_encoder11_zero), (({3{wire_altpriority_encoder11_zero}} & wire_altpriority_encoder10_q) | ({3{(~ wire_altpriority_encoder11_zero)}} & wire_altpriority_encoder11_q))};
endmodule //acl_fp_uitofp_double_altpriority_encoder_r08
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q zero
//VERSION_BEGIN 11.0 cbx_altpriority_encoder 2011:04:27:21:09:05:SJ cbx_mgl 2011:04:27:21:10:09:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_double_altpriority_encoder_rf8
(
data,
q,
zero) ;
input [15:0] data;
output [3:0] q;
output zero;
wire [2:0] wire_altpriority_encoder20_q;
wire wire_altpriority_encoder20_zero;
wire [2:0] wire_altpriority_encoder21_q;
wire wire_altpriority_encoder21_zero;
acl_fp_uitofp_double_altpriority_encoder_be8 altpriority_encoder20
(
.data(data[7:0]),
.q(wire_altpriority_encoder20_q),
.zero(wire_altpriority_encoder20_zero));
acl_fp_uitofp_double_altpriority_encoder_be8 altpriority_encoder21
(
.data(data[15:8]),
.q(wire_altpriority_encoder21_q),
.zero(wire_altpriority_encoder21_zero));
assign
q = {(~ wire_altpriority_encoder21_zero), (({3{wire_altpriority_encoder21_zero}} & wire_altpriority_encoder20_q) | ({3{(~ wire_altpriority_encoder21_zero)}} & wire_altpriority_encoder21_q))},
zero = (wire_altpriority_encoder20_zero & wire_altpriority_encoder21_zero);
endmodule //acl_fp_uitofp_double_altpriority_encoder_rf8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_double_altpriority_encoder_q08
(
data,
q) ;
input [31:0] data;
output [4:0] q;
wire [3:0] wire_altpriority_encoder8_q;
wire [3:0] wire_altpriority_encoder9_q;
wire wire_altpriority_encoder9_zero;
acl_fp_uitofp_double_altpriority_encoder_r08 altpriority_encoder8
(
.data(data[15:0]),
.q(wire_altpriority_encoder8_q));
acl_fp_uitofp_double_altpriority_encoder_rf8 altpriority_encoder9
(
.data(data[31:16]),
.q(wire_altpriority_encoder9_q),
.zero(wire_altpriority_encoder9_zero));
assign
q = {(~ wire_altpriority_encoder9_zero), (({4{wire_altpriority_encoder9_zero}} & wire_altpriority_encoder8_q) | ({4{(~ wire_altpriority_encoder9_zero)}} & wire_altpriority_encoder9_q))};
endmodule //acl_fp_uitofp_double_altpriority_encoder_q08
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=32 WIDTHAD=5 data q zero
//VERSION_BEGIN 11.0 cbx_altpriority_encoder 2011:04:27:21:09:05:SJ cbx_mgl 2011:04:27:21:10:09:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_double_altpriority_encoder_qf8
(
data,
q,
zero) ;
input [31:0] data;
output [4:0] q;
output zero;
wire [3:0] wire_altpriority_encoder22_q;
wire wire_altpriority_encoder22_zero;
wire [3:0] wire_altpriority_encoder23_q;
wire wire_altpriority_encoder23_zero;
acl_fp_uitofp_double_altpriority_encoder_rf8 altpriority_encoder22
(
.data(data[15:0]),
.q(wire_altpriority_encoder22_q),
.zero(wire_altpriority_encoder22_zero));
acl_fp_uitofp_double_altpriority_encoder_rf8 altpriority_encoder23
(
.data(data[31:16]),
.q(wire_altpriority_encoder23_q),
.zero(wire_altpriority_encoder23_zero));
assign
q = {(~ wire_altpriority_encoder23_zero), (({4{wire_altpriority_encoder23_zero}} & wire_altpriority_encoder22_q) | ({4{(~ wire_altpriority_encoder23_zero)}} & wire_altpriority_encoder23_q))},
zero = (wire_altpriority_encoder22_zero & wire_altpriority_encoder23_zero);
endmodule //acl_fp_uitofp_double_altpriority_encoder_qf8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_double_altpriority_encoder_0c6
(
data,
q) ;
input [63:0] data;
output [5:0] q;
wire [4:0] wire_altpriority_encoder6_q;
wire [4:0] wire_altpriority_encoder7_q;
wire wire_altpriority_encoder7_zero;
acl_fp_uitofp_double_altpriority_encoder_q08 altpriority_encoder6
(
.data(data[31:0]),
.q(wire_altpriority_encoder6_q));
acl_fp_uitofp_double_altpriority_encoder_qf8 altpriority_encoder7
(
.data(data[63:32]),
.q(wire_altpriority_encoder7_q),
.zero(wire_altpriority_encoder7_zero));
assign
q = {(~ wire_altpriority_encoder7_zero), (({5{wire_altpriority_encoder7_zero}} & wire_altpriority_encoder6_q) | ({5{(~ wire_altpriority_encoder7_zero)}} & wire_altpriority_encoder7_q))};
endmodule //acl_fp_uitofp_double_altpriority_encoder_0c6
//synthesis_resources = lpm_add_sub 2 lpm_compare 1 reg 296
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_double_altfp_convert_hkn
(
clk_en,
clock,
dataa,
result) ;
input clk_en;
input clock;
input [32:0] dataa;
output [63:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [32:0] wire_altbarrel_shift5_result;
wire [5:0] wire_altpriority_encoder2_q;
reg [10:0] exponent_bus_pre_reg;
reg [10:0] exponent_bus_pre_reg2;
reg [10:0] exponent_bus_pre_reg3;
reg [31:0] mag_int_a_reg;
reg [31:0] mag_int_a_reg2;
reg [52:0] mantissa_pre_round_reg;
reg [5:0] priority_encoder_reg;
reg [63:0] result_reg;
reg sign_int_a_reg1;
reg sign_int_a_reg2;
reg sign_int_a_reg3;
reg sign_int_a_reg4;
reg sign_int_a_reg5;
wire [31:0] wire_add_sub1_result;
wire [10:0] wire_add_sub3_result;
wire wire_cmpr4_alb;
wire aclr;
wire [10:0] bias_value_w;
wire [10:0] const_bias_value_add_width_int_w;
wire [10:0] exceptions_value;
wire [10:0] exponent_bus;
wire [10:0] exponent_bus_pre;
wire [10:0] exponent_output_w;
wire [10:0] exponent_rounded;
wire [10:0] exponent_zero_w;
wire [31:0] int_a;
wire [31:0] int_a_2s;
wire [31:0] invert_int_a;
wire [5:0] leading_zeroes;
wire [31:0] mag_int_a;
wire [51:0] mantissa_bus;
wire [52:0] mantissa_pre_round;
wire [52:0] mantissa_rounded;
wire max_neg_value_selector;
wire [10:0] max_neg_value_w;
wire [10:0] minus_leading_zero;
wire [32:0] prio_mag_int_a;
wire [30:0] priority_pad_one_w;
wire [63:0] result_w;
wire [31:0] shifted_mag_int_a;
wire sign_bus;
wire sign_int_a;
wire [4:0] zero_padding_w;
acl_fp_uitofp_double_altbarrel_shift_ssf altbarrel_shift5
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.data({1'b0, mag_int_a_reg2}),
.distance(leading_zeroes),
.result(wire_altbarrel_shift5_result));
acl_fp_uitofp_double_altpriority_encoder_0c6 altpriority_encoder2
(
.data({prio_mag_int_a, priority_pad_one_w}),
.q(wire_altpriority_encoder2_q));
// synopsys translate_off
initial
exponent_bus_pre_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exponent_bus_pre_reg <= 11'b0;
else if (clk_en == 1'b1) exponent_bus_pre_reg <= exponent_bus_pre_reg2;
// synopsys translate_off
initial
exponent_bus_pre_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exponent_bus_pre_reg2 <= 11'b0;
else if (clk_en == 1'b1) exponent_bus_pre_reg2 <= exponent_bus_pre_reg3;
// synopsys translate_off
initial
exponent_bus_pre_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exponent_bus_pre_reg3 <= 11'b0;
else if (clk_en == 1'b1) exponent_bus_pre_reg3 <= exponent_bus_pre;
// synopsys translate_off
initial
mag_int_a_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mag_int_a_reg <= 32'b0;
else if (clk_en == 1'b1) mag_int_a_reg <= mag_int_a;
// synopsys translate_off
initial
mag_int_a_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mag_int_a_reg2 <= 32'b0;
else if (clk_en == 1'b1) mag_int_a_reg2 <= mag_int_a_reg;
// synopsys translate_off
initial
mantissa_pre_round_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mantissa_pre_round_reg <= 53'b0;
else if (clk_en == 1'b1) mantissa_pre_round_reg <= mantissa_pre_round;
// synopsys translate_off
initial
priority_encoder_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) priority_encoder_reg <= 6'b0;
else if (clk_en == 1'b1) priority_encoder_reg <= wire_altpriority_encoder2_q;
// synopsys translate_off
initial
result_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) result_reg <= 64'b0;
else if (clk_en == 1'b1) result_reg <= result_w;
// synopsys translate_off
initial
sign_int_a_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg1 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg1 <= sign_int_a;
// synopsys translate_off
initial
sign_int_a_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg2 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg2 <= sign_int_a_reg1;
// synopsys translate_off
initial
sign_int_a_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg3 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg3 <= sign_int_a_reg2;
// synopsys translate_off
initial
sign_int_a_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg4 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg4 <= sign_int_a_reg3;
// synopsys translate_off
initial
sign_int_a_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg5 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg5 <= sign_int_a_reg4;
lpm_add_sub add_sub1
(
.cout(),
.dataa(invert_int_a),
.datab(32'b00000000000000000000000000000001),
.overflow(),
.result(wire_add_sub1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub1.lpm_direction = "ADD",
add_sub1.lpm_width = 32,
add_sub1.lpm_type = "lpm_add_sub",
add_sub1.lpm_hint = "ONE_INPUT_IS_CONSTANT=YES";
lpm_add_sub add_sub3
(
.cout(),
.dataa(const_bias_value_add_width_int_w),
.datab(minus_leading_zero),
.overflow(),
.result(wire_add_sub3_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub3.lpm_direction = "SUB",
add_sub3.lpm_width = 11,
add_sub3.lpm_type = "lpm_add_sub",
add_sub3.lpm_hint = "ONE_INPUT_IS_CONSTANT=YES";
lpm_compare cmpr4
(
.aeb(),
.agb(),
.ageb(),
.alb(wire_cmpr4_alb),
.aleb(),
.aneb(),
.dataa(exponent_output_w),
.datab(bias_value_w)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cmpr4.lpm_representation = "UNSIGNED",
cmpr4.lpm_width = 11,
cmpr4.lpm_type = "lpm_compare";
assign
aclr = 1'b0,
bias_value_w = 11'b01111111111,
const_bias_value_add_width_int_w = 11'b10000011110,
exceptions_value = (({11{(~ max_neg_value_selector)}} & exponent_zero_w) | ({11{max_neg_value_selector}} & max_neg_value_w)),
exponent_bus = exponent_rounded,
exponent_bus_pre = (({11{(~ wire_cmpr4_alb)}} & exponent_output_w) | ({11{wire_cmpr4_alb}} & exceptions_value)),
exponent_output_w = wire_add_sub3_result,
exponent_rounded = exponent_bus_pre_reg,
exponent_zero_w = {11{1'b0}},
int_a = dataa[31:0],
int_a_2s = wire_add_sub1_result,
invert_int_a = (~ int_a),
leading_zeroes = (~ priority_encoder_reg),
mag_int_a = (({32{(~ sign_int_a)}} & int_a) | ({32{sign_int_a}} & int_a_2s)),
mantissa_bus = mantissa_rounded[51:0],
mantissa_pre_round = {shifted_mag_int_a[31:0], {21{1'b0}}},
mantissa_rounded = mantissa_pre_round_reg,
max_neg_value_selector = (wire_cmpr4_alb & sign_int_a_reg2),
max_neg_value_w = 11'b10000011111,
minus_leading_zero = {zero_padding_w, leading_zeroes},
prio_mag_int_a = {mag_int_a_reg, 1'b1},
priority_pad_one_w = {31{1'b1}},
result = result_reg,
result_w = {sign_bus, exponent_bus, mantissa_bus},
shifted_mag_int_a = wire_altbarrel_shift5_result[31:0],
sign_bus = sign_int_a_reg5,
sign_int_a = dataa[32],
zero_padding_w = {5{1'b0}};
endmodule //acl_fp_uitofp_double_altfp_convert_hkn
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_uitofp_double (
enable,
clock,
dataa,
result);
input enable;
input clock;
input [31:0] dataa;
output [63:0] result;
wire [63:0] sub_wire0;
wire [63:0] result = sub_wire0[63:0];
acl_fp_uitofp_double_altfp_convert_hkn acl_fp_uitofp_double_altfp_convert_hkn_component (
.clk_en (enable),
.clock (clock),
.dataa ({1'b0,dataa}),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altfp_convert"
// Retrieval info: CONSTANT: OPERATION STRING "INT2FLOAT"
// Retrieval info: CONSTANT: ROUNDING STRING "TO_NEAREST"
// Retrieval info: CONSTANT: WIDTH_DATA NUMERIC "33"
// Retrieval info: CONSTANT: WIDTH_EXP_INPUT NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_EXP_OUTPUT NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_INT NUMERIC "33"
// Retrieval info: CONSTANT: WIDTH_MAN_INPUT NUMERIC "23"
// Retrieval info: CONSTANT: WIDTH_MAN_OUTPUT NUMERIC "52"
// Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "64"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: USED_PORT: dataa 0 0 33 0 INPUT NODEFVAL "dataa[32..0]"
// Retrieval info: CONNECT: @dataa 0 0 33 0 dataa 0 0 33 0
// Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT NODEFVAL "result[63..0]"
// Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_uitofp_double.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_uitofp_double.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_uitofp_double.bsf FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_uitofp_double_inst.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_uitofp_double_bb.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_uitofp_double.inc FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_uitofp_double.cmp FALSE TRUE
// Retrieval info: LIB_FILE: lpm
|
/*------------------------------------------------------------------------------
Purpose
Synchronous FIFO.
------------------------------------------------------------------------------*/
module mips_fifosync #(parameter S_WORD= 8,
parameter SPOWER2_MEM= 4)
(
input clk,
input rst,
input wr_en,
input[S_WORD-1:0] wr_data,
input rd_en,
output[S_WORD-1:0] rd_data,
output fifo_full,
output fifo_empty
);
localparam S_MEM= 1<<SPOWER2_MEM;
reg[S_WORD-1:0] mem[S_MEM-1:0];
reg[SPOWER2_MEM:0] wr_counter;
reg[SPOWER2_MEM:0] rd_counter;
assign rd_data= mem[rd_counter[SPOWER2_MEM-1:0]];
assign fifo_empty= wr_counter==rd_counter;
assign fifo_full= wr_counter[SPOWER2_MEM]!=rd_counter[SPOWER2_MEM] &
wr_counter[SPOWER2_MEM-1:0]==rd_counter[SPOWER2_MEM-1:0];
always @(posedge clk)
begin
if(rst)
begin
wr_counter<= {(SPOWER2_MEM){1'b0}};
rd_counter<= {(SPOWER2_MEM){1'b0}};
end
else
begin
rd_counter<= rd_en ? rd_counter+1'b1 : rd_counter;
wr_counter<= wr_en ? wr_counter+1'b1 : wr_counter;
end
end
generate
genvar i;
for(i=0; i<S_MEM; i=i+1)
begin:array
always @(posedge clk)
if(rst) mem[i]<= {(S_WORD){1'b0}};
else mem[i]<= wr_counter[SPOWER2_MEM-1:0]==i & wr_en ? wr_data : mem[i];
end
endgenerate
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// dac vdma read
module vdma_core (
// vdma interface
vdma_clk,
vdma_rst,
vdma_fs,
vdma_valid,
vdma_data,
vdma_ready,
vdma_ovf,
vdma_unf,
// dac interface
dac_clk,
dac_rst,
dac_rd,
dac_valid,
dac_data,
// processor interface
vdma_frmcnt);
// parameters
parameter DATA_WIDTH = 64;
localparam DW = DATA_WIDTH - 1;
localparam BUF_THRESHOLD_LO = 6'd3;
localparam BUF_THRESHOLD_HI = 6'd60;
localparam RDY_THRESHOLD_LO = 6'd40;
localparam RDY_THRESHOLD_HI = 6'd50;
// vdma interface
input vdma_clk;
input vdma_rst;
output vdma_fs;
input vdma_valid;
input [DW:0] vdma_data;
output vdma_ready;
output vdma_ovf;
output vdma_unf;
// dac interface
input dac_clk;
input dac_rst;
input dac_rd;
output dac_valid;
output [DW:0] dac_data;
// processor interface
input [31:0] vdma_frmcnt;
// internal registers
reg dac_start_m1 = 'd0;
reg dac_start = 'd0;
reg dac_resync_m1 = 'd0;
reg dac_resync = 'd0;
reg [ 5:0] dac_raddr = 'd0;
reg [ 5:0] dac_raddr_g = 'd0;
reg dac_rd_d = 'd0;
reg dac_rd_2d = 'd0;
reg dac_valid = 'd0;
reg [DW:0] dac_data = 'd0;
reg [31:0] vdma_clkcnt = 'd0;
reg vdma_fs = 'd0;
reg [ 5:0] vdma_raddr_g_m1 = 'd0;
reg [ 5:0] vdma_raddr_g_m2 = 'd0;
reg [ 5:0] vdma_raddr = 'd0;
reg [ 5:0] vdma_addr_diff = 'd0;
reg vdma_ready = 'd0;
reg vdma_almost_full = 'd0;
reg vdma_almost_empty = 'd0;
reg vdma_ovf = 'd0;
reg vdma_unf = 'd0;
reg vdma_resync = 'd0;
reg vdma_start = 'd0;
reg vdma_wr = 'd0;
reg [ 5:0] vdma_waddr = 'd0;
reg [DW:0] vdma_wdata = 'd0;
// internal signals
wire vdma_wr_s;
wire [ 6:0] vdma_addr_diff_s;
wire vdma_ovf_s;
wire vdma_unf_s;
wire [DW:0] dac_rdata_s;
// binary to grey coversion
function [7:0] b2g;
input [7:0] b;
reg [7:0] g;
begin
g[7] = b[7];
g[6] = b[7] ^ b[6];
g[5] = b[6] ^ b[5];
g[4] = b[5] ^ b[4];
g[3] = b[4] ^ b[3];
g[2] = b[3] ^ b[2];
g[1] = b[2] ^ b[1];
g[0] = b[1] ^ b[0];
b2g = g;
end
endfunction
// grey to binary conversion
function [7:0] g2b;
input [7:0] g;
reg [7:0] b;
begin
b[7] = g[7];
b[6] = b[7] ^ g[6];
b[5] = b[6] ^ g[5];
b[4] = b[5] ^ g[4];
b[3] = b[4] ^ g[3];
b[2] = b[3] ^ g[2];
b[1] = b[2] ^ g[1];
b[0] = b[1] ^ g[0];
g2b = b;
end
endfunction
// dac read interface
always @(posedge dac_clk) begin
if (dac_rst == 1'b1) begin
dac_start_m1 <= 'd0;
dac_start <= 'd0;
dac_resync_m1 <= 'd0;
dac_resync <= 'd0;
end else begin
dac_start_m1 <= vdma_start;
dac_start <= dac_start_m1;
dac_resync_m1 <= vdma_resync;
dac_resync <= dac_resync_m1;
end
if ((dac_start == 1'b0) || (dac_resync == 1'b1) || (dac_rst == 1'b1)) begin
dac_raddr <= 6'd0;
end else if (dac_rd == 1'b1) begin
dac_raddr <= dac_raddr + 1'b1;
end
dac_raddr_g <= b2g(dac_raddr);
dac_rd_d <= dac_rd;
dac_rd_2d <= dac_rd_d;
dac_valid <= dac_rd_2d;
dac_data <= dac_rdata_s;
end
// generate fsync
always @(posedge vdma_clk) begin
if ((vdma_resync == 1'b1) || (vdma_rst == 1'b1) || (vdma_clkcnt >= vdma_frmcnt)) begin
vdma_clkcnt <= 16'd0;
end else begin
vdma_clkcnt <= vdma_clkcnt + 1'b1;
end
if (vdma_clkcnt == 32'd1) begin
vdma_fs <= 1'b1;
end else begin
vdma_fs <= 1'b0;
end
end
// overflow or underflow status
assign vdma_addr_diff_s = {1'b1, vdma_waddr} - vdma_raddr;
assign vdma_ovf_s = (vdma_addr_diff < BUF_THRESHOLD_LO) ? vdma_almost_full : 1'b0;
assign vdma_unf_s = (vdma_addr_diff > BUF_THRESHOLD_HI) ? vdma_almost_empty : 1'b0;
always @(posedge vdma_clk) begin
if (vdma_rst == 1'b1) begin
vdma_raddr_g_m1 <= 'd0;
vdma_raddr_g_m2 <= 'd0;
end else begin
vdma_raddr_g_m1 <= dac_raddr_g;
vdma_raddr_g_m2 <= vdma_raddr_g_m1;
end
vdma_raddr <= g2b(vdma_raddr_g_m2);
vdma_addr_diff <= vdma_addr_diff_s[5:0];
if (vdma_addr_diff >= RDY_THRESHOLD_HI) begin
vdma_ready <= 1'b0;
end else if (vdma_addr_diff <= RDY_THRESHOLD_LO) begin
vdma_ready <= 1'b1;
end
if (vdma_addr_diff > BUF_THRESHOLD_HI) begin
vdma_almost_full <= 1'b1;
end else begin
vdma_almost_full <= 1'b0;
end
if (vdma_addr_diff < BUF_THRESHOLD_LO) begin
vdma_almost_empty <= 1'b1;
end else begin
vdma_almost_empty <= 1'b0;
end
vdma_ovf <= vdma_ovf_s;
vdma_unf <= vdma_unf_s;
vdma_resync <= vdma_ovf | vdma_unf;
end
// vdma write
assign vdma_wr_s = vdma_valid & vdma_ready;
always @(posedge vdma_clk) begin
if (vdma_rst == 1'b1) begin
vdma_start <= 1'b0;
end else if (vdma_wr_s == 1'b1) begin
vdma_start <= 1'b1;
end
vdma_wr <= vdma_wr_s;
if ((vdma_resync == 1'b1) || (vdma_rst == 1'b1)) begin
vdma_waddr <= 6'd0;
end else if (vdma_wr == 1'b1) begin
vdma_waddr <= vdma_waddr + 1'b1;
end
vdma_wdata <= vdma_data;
end
// memory
mem #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(6)) i_mem (
.clka (vdma_clk),
.wea (vdma_wr),
.addra (vdma_waddr),
.dina (vdma_wdata),
.clkb (dac_clk),
.addrb (dac_raddr),
.doutb (dac_rdata_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// (C) 1992-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Reduced Normalization module
//
// This module performs realignment of data such that the most significant bit is
// 1 for any number with exponent >= 1, and zero otherwise.
//
module acl_fp_custom_reduced_normalize_double(
clock, resetn,
mantissa, exponent, sign,
// Used in HIGH_CAPACITY = 1 mode
stall_in, valid_in, stall_out, valid_out,
// Used in HIGH_CAPACITY = 0 mode
enable,
mantissa_out, exponent_out, sign_out);
parameter HIGH_CAPACITY = 1;
parameter FLUSH_DENORMS = 0;
parameter HIGH_LATENCY = 1;
parameter REMOVE_STICKY = 1;
parameter FINITE_MATH_ONLY = 1;
input clock, resetn;
input stall_in, valid_in;
output stall_out, valid_out;
input enable;
// Data in
input [56:0] mantissa;
input [11:0] exponent; // Exponent with MSB set to 1 is an exception.
input sign;
// Data output
output [55:0] mantissa_out; // When mantissa_out[54] = 1 and exponent_out[11] == 1 then the number is NaN.
output [11:0] exponent_out; // Exponent with MSB set to 1 is an exception.
output sign_out;
// Stall/valid and enable signals on per-stage basis.
reg c1_valid;
reg c2_valid;
reg c3_valid;
reg c4_valid;
reg c5_valid;
wire c1_stall;
wire c2_stall;
wire c3_stall;
wire c4_stall;
wire c5_stall;
wire c1_enable;
wire c2_enable;
wire c3_enable;
wire c4_enable;
wire c5_enable;
// Cycle 1 - We are just doing the shifting here.
reg [56:0] c1_mantissa;
reg [11:0] c1_exponent;
reg [5:0] c1_max_shift;
reg c1_sign;
reg c1_exponent_is_max;
reg c1_exponent_is_nonzero;
reg [13:0] c1_mantissa_nonzero;
assign c1_enable = (HIGH_CAPACITY == 1) ? (~c1_valid | ~c1_stall) : enable;
assign stall_out = c1_valid & c1_stall;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c1_mantissa <= 57'dx;
c1_exponent <= 12'dx;
c1_sign <= 1'bx;
c1_exponent_is_max <= 1'bx;
c1_exponent_is_nonzero <= 1'bx;
c1_mantissa_nonzero <= 14'dx;
c1_max_shift <= 6'dx;
c1_valid <= 1'b0;
end
else if (c1_enable)
begin
c1_valid <= valid_in;
c1_sign <= sign;
c1_exponent <= exponent;
c1_exponent_is_max <= (&exponent[10:1]) & ~exponent[0];
c1_exponent_is_nonzero <= |exponent[10:0];
c1_mantissa_nonzero <= {|mantissa[55:52], |mantissa[51:48], |mantissa[47:44], |mantissa[43:40], |mantissa[39:36], |mantissa[35:32], |mantissa[31:28], |mantissa[27:24], |mantissa[23:20], |mantissa[19:16], |mantissa[15:12], |mantissa[11:8], |mantissa[7:4], |mantissa[3:0]};
if ((FINITE_MATH_ONLY == 0) && (exponent == 12'h7fe) && mantissa[56])
begin
c1_mantissa[56] <= 1'b1;
c1_mantissa[55:0] <= 56'd0;
end
else
c1_mantissa <= mantissa;
c1_max_shift <= exponent[11] ? 6'd0 : ({6{|exponent[10:6]}} | {exponent[5:0] - 1'b1});
end
end
// Cycle 2 - Shift by 32, 0 or -1.
reg [55:0] c2_mantissa;
reg [11:0] c2_exponent;
reg c2_sign;
reg [4:0] c2_max_shift;
reg [2:0] c2_mantissa_nonzero;
assign c2_enable = (HIGH_CAPACITY == 1) ? (~c2_valid | ~c2_stall) : enable;
assign c1_stall = c2_valid & c2_stall;
generate
if (HIGH_LATENCY == 1)
begin
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c2_mantissa <= 56'dx;
c2_exponent <= 12'dx;
c2_sign <= 1'bx;
c2_mantissa_nonzero <= 3'dx;
c2_max_shift <= 5'dx;
c2_valid <= 1'b0;
end
else if (c2_enable)
begin
c2_valid <= c1_valid;
c2_sign <= c1_sign;
if (c1_mantissa[56])
begin
// -1
c2_mantissa_nonzero <= 3'b111;
if (REMOVE_STICKY == 1)
c2_mantissa <= c1_mantissa[56:1];
else
c2_mantissa <= {c1_mantissa[56:2], |c1_mantissa[1:0]};
c2_mantissa_nonzero <= 3'b111;
c2_max_shift <= 4'd0;
if ((c1_exponent_is_max) && (FINITE_MATH_ONLY == 0))
c2_exponent <= 12'hfff;
else
c2_exponent <= c1_exponent + {1'b0, ~c1_exponent_is_nonzero, c1_exponent_is_nonzero};
end
else
if (~(|c1_mantissa_nonzero[13:6]) && (c1_max_shift[5]) && c1_exponent_is_nonzero)
begin
// 32
c2_mantissa <= {c1_mantissa[23:0], 32'd0};
c2_exponent <= c1_exponent - 7'd32;
c2_mantissa_nonzero <= {|c1_mantissa_nonzero[5:4], |c1_mantissa_nonzero[3:2], |c1_mantissa_nonzero[1:0]};
c2_max_shift <= (c1_max_shift[4:0]) & {5{c1_exponent_is_nonzero}};
end
else
begin
// 0
c2_mantissa <= c1_mantissa[55:0];
c2_exponent <= c1_exponent;
c2_mantissa_nonzero <= {|c1_mantissa_nonzero[13:12], |c1_mantissa_nonzero[11:10], |c1_mantissa_nonzero[9:8]};
c2_max_shift <= ({5{c1_max_shift[5]}} | c1_max_shift[4:0]) & {5{c1_exponent_is_nonzero}};
end
end
end
end
else
begin
// Do not register this stage in low-latency mode.
always@(*)
begin
c2_valid <= c1_valid;
c2_sign <= c1_sign;
if (c1_mantissa[56])
begin
// -1
c2_mantissa_nonzero <= 3'b111;
if (REMOVE_STICKY == 1)
c2_mantissa <= c1_mantissa[56:1];
else
c2_mantissa <= {c1_mantissa[56:2], |c1_mantissa[1:0]};
c2_mantissa_nonzero <= 3'b111;
c2_max_shift <= 4'd0;
if ((c1_exponent_is_max) && (FINITE_MATH_ONLY == 0))
c2_exponent <= 12'hfff;
else
c2_exponent <= c1_exponent + {1'b0, ~c1_exponent_is_nonzero, c1_exponent_is_nonzero};
end
else
if (~(|c1_mantissa_nonzero[13:6]) && (c1_max_shift[5]) && c1_exponent_is_nonzero)
begin
// 32
c2_mantissa <= {c1_mantissa[23:0], 32'd0};
c2_exponent <= c1_exponent - 7'd32;
c2_mantissa_nonzero <= {|c1_mantissa_nonzero[5:4], |c1_mantissa_nonzero[3:2], |c1_mantissa_nonzero[1:0]};
c2_max_shift <= (c1_max_shift[4:0]) & {5{c1_exponent_is_nonzero}};
end
else
begin
// 0
c2_mantissa <= c1_mantissa[55:0];
c2_exponent <= c1_exponent;
c2_mantissa_nonzero <= {|c1_mantissa_nonzero[13:12], |c1_mantissa_nonzero[11:10], |c1_mantissa_nonzero[9:8]};
c2_max_shift <= ({5{c1_max_shift[5]}} | c1_max_shift[4:0]) & {5{c1_exponent_is_nonzero}};
end
end
end
endgenerate
// Cycle 3 - Shift by 16 or 0 here.
reg [55:0] c3_mantissa;
reg [11:0] c3_exponent;
reg [3:0] c3_max_shift;
reg c3_mantissa_nonzero;
reg c3_sign;
assign c3_enable = (HIGH_CAPACITY == 1) ? (~c3_valid | ~c3_stall) : enable;
assign c2_stall = c3_valid & c3_stall;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c3_mantissa <= 56'dx;
c3_exponent <= 12'dx;
c3_sign <= 1'bx;
c3_max_shift <= 4'dx;
c3_mantissa_nonzero <= 1'bx;
c3_valid <= 1'b0;
end
else if (c3_enable)
begin
c3_valid <= c2_valid;
c3_sign <= c2_sign;
if (~(|c2_mantissa_nonzero[2:1]) && (c2_max_shift[4]))
begin
// 16
c3_mantissa <= {c2_mantissa[39:0], 16'd0};
c3_exponent <= c2_exponent - 6'd16;
c3_max_shift <= c2_max_shift[3:0];
c3_mantissa_nonzero <= c2_mantissa_nonzero[0];
end
else
begin
// 0
c3_mantissa <= c2_mantissa;
c3_exponent <= c2_exponent;
c3_max_shift <= c2_max_shift[3:0] | {4{c2_max_shift[4]}};
c3_mantissa_nonzero <= c2_mantissa_nonzero[2];
end
end
end
// Cycle 4 - Shift by 12, 8, 4 or 0 here.
reg [55:0] c4_mantissa;
reg [11:0] c4_exponent;
reg [1:0] c4_max_shift;
reg c4_sign;
assign c4_enable = (HIGH_CAPACITY == 1) ? (~c4_valid | ~c4_stall) : enable;
assign c3_stall = c4_valid & c4_stall;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c4_mantissa <= 56'dx;
c4_exponent <= 12'dx;
c4_sign <= 1'bx;
c4_valid <= 1'b0;
end
else if (c4_enable)
begin
c4_valid <= c3_valid;
c4_sign <= c3_sign;
if (~c3_mantissa_nonzero && (~|c3_mantissa[47:44]) && (&c3_max_shift[3:2]))
begin
// 12
c4_mantissa <= {c3_mantissa[43:0], 12'd0};
c4_exponent <= c3_exponent - 6'd12;
c4_max_shift <= c3_max_shift[1:0];
end
else
if (~c3_mantissa_nonzero && (c3_max_shift[3]))
begin
// 8
c4_mantissa <= {c3_mantissa[47:0], 8'd0};
c4_exponent <= c3_exponent - 6'd8;
c4_max_shift <= c3_max_shift[1:0] | {2{c3_max_shift[2]}};
end
else
if ((~|c3_mantissa[55:52]) && (c3_max_shift[2]))
begin
// 4
c4_mantissa <= {c3_mantissa[51:0], 4'd0};
c4_exponent <= c3_exponent - 6'd4;
c4_max_shift <= c3_max_shift[1:0] | {2{c3_max_shift[3]}};
end
else
begin
// 0
c4_mantissa <= c3_mantissa;
c4_exponent <= c3_exponent;
c4_max_shift <= c3_max_shift[1:0] | {2{|c3_max_shift[3:2]}};
end
end
end
// Cycle 5 - Shift by 3,2,1 or 0 here.
reg [55:0] c5_mantissa;
reg [11:0] c5_exponent;
reg c5_sign;
assign c5_enable = (HIGH_CAPACITY == 1) ? (~c5_valid | ~c5_stall) : enable;
assign c4_stall = c5_valid & c5_stall;
reg [1:0] shift_by;
always@(*)
begin
if (~|c4_mantissa[55:53])
shift_by = c4_max_shift;
else if (~|c4_mantissa[55:54])
shift_by = {c4_max_shift[1], c4_max_shift[0] & ~c4_max_shift[1]};
else if (~c4_mantissa[55])
shift_by = {1'b0, |c4_max_shift};
else
shift_by = 2'b00;
end
wire [55:0] resulting_mantissa = c4_mantissa << shift_by;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c5_mantissa <= 56'dx;
c5_exponent <= 12'dx;
c5_sign <= 1'bx;
c5_valid <= 1'b0;
end
else if (c5_enable)
begin
c5_valid <= c4_valid;
c5_sign <= c4_sign;
c5_mantissa <= resulting_mantissa;
if (~resulting_mantissa[55] && ~c4_exponent[11])
begin
// This number just became denormalized
c5_exponent <= 12'd0;
end
else
begin
c5_exponent <= c4_exponent - {1'b0, shift_by};
end
end
end
assign mantissa_out = c5_mantissa;
assign exponent_out = c5_exponent;
assign sign_out = c5_sign;
assign valid_out = c5_valid;
assign c5_stall = stall_in;
endmodule
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