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/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
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* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
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* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
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* This agreement shall be governed in all respects by the laws of the State *
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******************************************************************************/
/******************************************************************************
* *
* This module drives the vga dac on Altera's DE2 Board. *
* *
******************************************************************************/
module altera_up_avalon_video_vga_timing (
// inputs
clk,
reset,
red_to_vga_display,
green_to_vga_display,
blue_to_vga_display,
color_select,
// bidirectional
// outputs
read_enable,
end_of_active_frame,
end_of_frame,
// dac pins
vga_blank, // VGA BLANK
vga_c_sync, // VGA COMPOSITE SYNC
vga_h_sync, // VGA H_SYNC
vga_v_sync, // VGA V_SYNC
vga_data_enable, // VGA DEN
vga_red, // VGA Red[9:0]
vga_green, // VGA Green[9:0]
vga_blue, // VGA Blue[9:0]
vga_color_data // VGA Color[9:0] for TRDB_LCM
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 9;
/* Number of pixels */
parameter H_ACTIVE = 640;
parameter H_FRONT_PORCH = 16;
parameter H_SYNC = 96;
parameter H_BACK_PORCH = 48;
parameter H_TOTAL = 800;
/* Number of lines */
parameter V_ACTIVE = 480;
parameter V_FRONT_PORCH = 10;
parameter V_SYNC = 2;
parameter V_BACK_PORCH = 33;
parameter V_TOTAL = 525;
parameter PW = 10; // Number of bits for pixels
parameter PIXEL_COUNTER_INCREMENT = 10'h001;
parameter LW = 10; // Number of bits for lines
parameter LINE_COUNTER_INCREMENT = 10'h001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [CW: 0] red_to_vga_display;
input [CW: 0] green_to_vga_display;
input [CW: 0] blue_to_vga_display;
input [ 3: 0] color_select;
// Bidirectionals
// Outputs
output read_enable;
output reg end_of_active_frame;
output reg end_of_frame;
// dac pins
output reg vga_blank; // VGA BLANK
output reg vga_c_sync; // VGA COMPOSITE SYNC
output reg vga_h_sync; // VGA H_SYNC
output reg vga_v_sync; // VGA V_SYNC
output reg vga_data_enable; // VGA DEN
output reg [CW: 0] vga_red; // VGA Red[9:0]
output reg [CW: 0] vga_green; // VGA Green[9:0]
output reg [CW: 0] vga_blue; // VGA Blue[9:0]
output reg [CW: 0] vga_color_data; // VGA Color[9:0] for TRDB_LCM
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
//reg clk_en;
reg [PW:1] pixel_counter;
reg [LW:1] line_counter;
reg early_hsync_pulse;
reg early_vsync_pulse;
reg hsync_pulse;
reg vsync_pulse;
reg csync_pulse;
reg hblanking_pulse;
reg vblanking_pulse;
reg blanking_pulse;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @ (posedge clk)
begin
if (reset)
begin
vga_c_sync <= 1'b1;
vga_blank <= 1'b1;
vga_h_sync <= 1'b1;
vga_v_sync <= 1'b1;
vga_red <= {(CW + 1){1'b0}};
vga_green <= {(CW + 1){1'b0}};
vga_blue <= {(CW + 1){1'b0}};
vga_color_data <= {(CW + 1){1'b0}};
end
else
begin
vga_blank <= ~blanking_pulse;
vga_c_sync <= ~csync_pulse;
vga_h_sync <= ~hsync_pulse;
vga_v_sync <= ~vsync_pulse;
// vga_data_enable <= hsync_pulse | vsync_pulse;
vga_data_enable <= ~blanking_pulse;
if (blanking_pulse)
begin
vga_red <= {(CW + 1){1'b0}};
vga_green <= {(CW + 1){1'b0}};
vga_blue <= {(CW + 1){1'b0}};
vga_color_data <= {(CW + 1){1'b0}};
end
else
begin
vga_red <= red_to_vga_display;
vga_green <= green_to_vga_display;
vga_blue <= blue_to_vga_display;
vga_color_data <= ({(CW + 1){color_select[0]}} & red_to_vga_display) |
({(CW + 1){color_select[1]}} & green_to_vga_display) |
({(CW + 1){color_select[2]}} & blue_to_vga_display);
end
end
end
// Internal Registers
always @ (posedge clk)
begin
if (reset)
begin
pixel_counter <= H_TOTAL - 3; // {PW{1'b0}};
line_counter <= V_TOTAL - 1; // {LW{1'b0}};
end
else
begin
// last pixel in the line
if (pixel_counter == (H_TOTAL - 1))
begin
pixel_counter <= {PW{1'b0}};
// last pixel in last line of frame
if (line_counter == (V_TOTAL - 1))
line_counter <= {LW{1'b0}};
// last pixel but not last line
else
line_counter <= line_counter + LINE_COUNTER_INCREMENT;
end
else
pixel_counter <= pixel_counter + PIXEL_COUNTER_INCREMENT;
end
end
always @ (posedge clk)
begin
if (reset)
begin
end_of_active_frame <= 1'b0;
end_of_frame <= 1'b0;
end
else
begin
if ((line_counter == (V_ACTIVE - 1)) &&
(pixel_counter == (H_ACTIVE - 2)))
end_of_active_frame <= 1'b1;
else
end_of_active_frame <= 1'b0;
if ((line_counter == (V_TOTAL - 1)) &&
(pixel_counter == (H_TOTAL - 2)))
end_of_frame <= 1'b1;
else
end_of_frame <= 1'b0;
end
end
always @ (posedge clk)
begin
if (reset)
begin
early_hsync_pulse <= 1'b0;
early_vsync_pulse <= 1'b0;
hsync_pulse <= 1'b0;
vsync_pulse <= 1'b0;
csync_pulse <= 1'b0;
end
else
begin
// start of horizontal sync
if (pixel_counter == (H_ACTIVE + H_FRONT_PORCH - 2))
early_hsync_pulse <= 1'b1;
// end of horizontal sync
else if (pixel_counter == (H_TOTAL - H_BACK_PORCH - 2))
early_hsync_pulse <= 1'b0;
// start of vertical sync
if ((line_counter == (V_ACTIVE + V_FRONT_PORCH - 1)) &&
(pixel_counter == (H_TOTAL - 2)))
early_vsync_pulse <= 1'b1;
// end of vertical sync
else if ((line_counter == (V_TOTAL - V_BACK_PORCH - 1)) &&
(pixel_counter == (H_TOTAL - 2)))
early_vsync_pulse <= 1'b0;
hsync_pulse <= early_hsync_pulse;
vsync_pulse <= early_vsync_pulse;
csync_pulse <= early_hsync_pulse ^ early_vsync_pulse;
end
end
always @ (posedge clk)
begin
if (reset)
begin
hblanking_pulse <= 1'b1;
vblanking_pulse <= 1'b1;
blanking_pulse <= 1'b1;
end
else
begin
if (pixel_counter == (H_ACTIVE - 2))
hblanking_pulse <= 1'b1;
else if (pixel_counter == (H_TOTAL - 2))
hblanking_pulse <= 1'b0;
if ((line_counter == (V_ACTIVE - 1)) &&
(pixel_counter == (H_TOTAL - 2)))
vblanking_pulse <= 1'b1;
else if ((line_counter == (V_TOTAL - 1)) &&
(pixel_counter == (H_TOTAL - 2)))
vblanking_pulse <= 1'b0;
blanking_pulse <= hblanking_pulse | vblanking_pulse;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign read_enable = ~blanking_pulse;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
// Computer_System_mm_interconnect_4.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.1 196
`timescale 1 ps / 1 ps
module Computer_System_mm_interconnect_4 (
input wire System_PLL_sys_clk_clk, // System_PLL_sys_clk.clk
input wire Expansion_JP1_reset_reset_bridge_in_reset_reset, // Expansion_JP1_reset_reset_bridge_in_reset.reset
input wire Video_In_Subsystem_sys_reset_reset_bridge_in_reset_reset, // Video_In_Subsystem_sys_reset_reset_bridge_in_reset.reset
input wire [3:0] Video_In_Subsystem_top_io_gpi1_streamin_address, // Video_In_Subsystem_top_io_gpi1_streamin.address
input wire Video_In_Subsystem_top_io_gpi1_streamin_chipselect, // .chipselect
input wire Video_In_Subsystem_top_io_gpi1_streamin_read, // .read
output wire [31:0] Video_In_Subsystem_top_io_gpi1_streamin_readdata, // .readdata
input wire [3:0] Video_In_Subsystem_top_io_gpo1_streamout_address, // Video_In_Subsystem_top_io_gpo1_streamout.address
input wire Video_In_Subsystem_top_io_gpo1_streamout_chipselect, // .chipselect
input wire Video_In_Subsystem_top_io_gpo1_streamout_write, // .write
input wire [31:0] Video_In_Subsystem_top_io_gpo1_streamout_writedata, // .writedata
output wire [1:0] Expansion_JP1_s1_address, // Expansion_JP1_s1.address
output wire Expansion_JP1_s1_write, // .write
input wire [31:0] Expansion_JP1_s1_readdata, // .readdata
output wire [31:0] Expansion_JP1_s1_writedata, // .writedata
output wire Expansion_JP1_s1_chipselect // .chipselect
);
wire video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_waitrequest; // Video_In_Subsystem_top_io_gpi1_streamin_agent:av_waitrequest -> Video_In_Subsystem_top_io_gpi1_streamin_translator:uav_waitrequest
wire [31:0] video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_readdata; // Video_In_Subsystem_top_io_gpi1_streamin_agent:av_readdata -> Video_In_Subsystem_top_io_gpi1_streamin_translator:uav_readdata
wire video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_debugaccess; // Video_In_Subsystem_top_io_gpi1_streamin_translator:uav_debugaccess -> Video_In_Subsystem_top_io_gpi1_streamin_agent:av_debugaccess
wire [3:0] video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_address; // Video_In_Subsystem_top_io_gpi1_streamin_translator:uav_address -> Video_In_Subsystem_top_io_gpi1_streamin_agent:av_address
wire video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_read; // Video_In_Subsystem_top_io_gpi1_streamin_translator:uav_read -> Video_In_Subsystem_top_io_gpi1_streamin_agent:av_read
wire [3:0] video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_byteenable; // Video_In_Subsystem_top_io_gpi1_streamin_translator:uav_byteenable -> Video_In_Subsystem_top_io_gpi1_streamin_agent:av_byteenable
wire video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_readdatavalid; // Video_In_Subsystem_top_io_gpi1_streamin_agent:av_readdatavalid -> Video_In_Subsystem_top_io_gpi1_streamin_translator:uav_readdatavalid
wire video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_lock; // Video_In_Subsystem_top_io_gpi1_streamin_translator:uav_lock -> Video_In_Subsystem_top_io_gpi1_streamin_agent:av_lock
wire video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_write; // Video_In_Subsystem_top_io_gpi1_streamin_translator:uav_write -> Video_In_Subsystem_top_io_gpi1_streamin_agent:av_write
wire [31:0] video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_writedata; // Video_In_Subsystem_top_io_gpi1_streamin_translator:uav_writedata -> Video_In_Subsystem_top_io_gpi1_streamin_agent:av_writedata
wire [2:0] video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_burstcount; // Video_In_Subsystem_top_io_gpi1_streamin_translator:uav_burstcount -> Video_In_Subsystem_top_io_gpi1_streamin_agent:av_burstcount
wire rsp_mux_src_valid; // rsp_mux:src_valid -> Video_In_Subsystem_top_io_gpi1_streamin_agent:rp_valid
wire [73:0] rsp_mux_src_data; // rsp_mux:src_data -> Video_In_Subsystem_top_io_gpi1_streamin_agent:rp_data
wire rsp_mux_src_ready; // Video_In_Subsystem_top_io_gpi1_streamin_agent:rp_ready -> rsp_mux:src_ready
wire [1:0] rsp_mux_src_channel; // rsp_mux:src_channel -> Video_In_Subsystem_top_io_gpi1_streamin_agent:rp_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> Video_In_Subsystem_top_io_gpi1_streamin_agent:rp_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> Video_In_Subsystem_top_io_gpi1_streamin_agent:rp_endofpacket
wire video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_waitrequest; // Video_In_Subsystem_top_io_gpo1_streamout_agent:av_waitrequest -> Video_In_Subsystem_top_io_gpo1_streamout_translator:uav_waitrequest
wire [31:0] video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_readdata; // Video_In_Subsystem_top_io_gpo1_streamout_agent:av_readdata -> Video_In_Subsystem_top_io_gpo1_streamout_translator:uav_readdata
wire video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_debugaccess; // Video_In_Subsystem_top_io_gpo1_streamout_translator:uav_debugaccess -> Video_In_Subsystem_top_io_gpo1_streamout_agent:av_debugaccess
wire [3:0] video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_address; // Video_In_Subsystem_top_io_gpo1_streamout_translator:uav_address -> Video_In_Subsystem_top_io_gpo1_streamout_agent:av_address
wire video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_read; // Video_In_Subsystem_top_io_gpo1_streamout_translator:uav_read -> Video_In_Subsystem_top_io_gpo1_streamout_agent:av_read
wire [3:0] video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_byteenable; // Video_In_Subsystem_top_io_gpo1_streamout_translator:uav_byteenable -> Video_In_Subsystem_top_io_gpo1_streamout_agent:av_byteenable
wire video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_readdatavalid; // Video_In_Subsystem_top_io_gpo1_streamout_agent:av_readdatavalid -> Video_In_Subsystem_top_io_gpo1_streamout_translator:uav_readdatavalid
wire video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_lock; // Video_In_Subsystem_top_io_gpo1_streamout_translator:uav_lock -> Video_In_Subsystem_top_io_gpo1_streamout_agent:av_lock
wire video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_write; // Video_In_Subsystem_top_io_gpo1_streamout_translator:uav_write -> Video_In_Subsystem_top_io_gpo1_streamout_agent:av_write
wire [31:0] video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_writedata; // Video_In_Subsystem_top_io_gpo1_streamout_translator:uav_writedata -> Video_In_Subsystem_top_io_gpo1_streamout_agent:av_writedata
wire [2:0] video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_burstcount; // Video_In_Subsystem_top_io_gpo1_streamout_translator:uav_burstcount -> Video_In_Subsystem_top_io_gpo1_streamout_agent:av_burstcount
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> Video_In_Subsystem_top_io_gpo1_streamout_agent:rp_valid
wire [73:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> Video_In_Subsystem_top_io_gpo1_streamout_agent:rp_data
wire rsp_mux_001_src_ready; // Video_In_Subsystem_top_io_gpo1_streamout_agent:rp_ready -> rsp_mux_001:src_ready
wire [1:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> Video_In_Subsystem_top_io_gpo1_streamout_agent:rp_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> Video_In_Subsystem_top_io_gpo1_streamout_agent:rp_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> Video_In_Subsystem_top_io_gpo1_streamout_agent:rp_endofpacket
wire [31:0] expansion_jp1_s1_agent_m0_readdata; // Expansion_JP1_s1_translator:uav_readdata -> Expansion_JP1_s1_agent:m0_readdata
wire expansion_jp1_s1_agent_m0_waitrequest; // Expansion_JP1_s1_translator:uav_waitrequest -> Expansion_JP1_s1_agent:m0_waitrequest
wire expansion_jp1_s1_agent_m0_debugaccess; // Expansion_JP1_s1_agent:m0_debugaccess -> Expansion_JP1_s1_translator:uav_debugaccess
wire [3:0] expansion_jp1_s1_agent_m0_address; // Expansion_JP1_s1_agent:m0_address -> Expansion_JP1_s1_translator:uav_address
wire [3:0] expansion_jp1_s1_agent_m0_byteenable; // Expansion_JP1_s1_agent:m0_byteenable -> Expansion_JP1_s1_translator:uav_byteenable
wire expansion_jp1_s1_agent_m0_read; // Expansion_JP1_s1_agent:m0_read -> Expansion_JP1_s1_translator:uav_read
wire expansion_jp1_s1_agent_m0_readdatavalid; // Expansion_JP1_s1_translator:uav_readdatavalid -> Expansion_JP1_s1_agent:m0_readdatavalid
wire expansion_jp1_s1_agent_m0_lock; // Expansion_JP1_s1_agent:m0_lock -> Expansion_JP1_s1_translator:uav_lock
wire [31:0] expansion_jp1_s1_agent_m0_writedata; // Expansion_JP1_s1_agent:m0_writedata -> Expansion_JP1_s1_translator:uav_writedata
wire expansion_jp1_s1_agent_m0_write; // Expansion_JP1_s1_agent:m0_write -> Expansion_JP1_s1_translator:uav_write
wire [2:0] expansion_jp1_s1_agent_m0_burstcount; // Expansion_JP1_s1_agent:m0_burstcount -> Expansion_JP1_s1_translator:uav_burstcount
wire expansion_jp1_s1_agent_rf_source_valid; // Expansion_JP1_s1_agent:rf_source_valid -> Expansion_JP1_s1_agent_rsp_fifo:in_valid
wire [74:0] expansion_jp1_s1_agent_rf_source_data; // Expansion_JP1_s1_agent:rf_source_data -> Expansion_JP1_s1_agent_rsp_fifo:in_data
wire expansion_jp1_s1_agent_rf_source_ready; // Expansion_JP1_s1_agent_rsp_fifo:in_ready -> Expansion_JP1_s1_agent:rf_source_ready
wire expansion_jp1_s1_agent_rf_source_startofpacket; // Expansion_JP1_s1_agent:rf_source_startofpacket -> Expansion_JP1_s1_agent_rsp_fifo:in_startofpacket
wire expansion_jp1_s1_agent_rf_source_endofpacket; // Expansion_JP1_s1_agent:rf_source_endofpacket -> Expansion_JP1_s1_agent_rsp_fifo:in_endofpacket
wire expansion_jp1_s1_agent_rsp_fifo_out_valid; // Expansion_JP1_s1_agent_rsp_fifo:out_valid -> Expansion_JP1_s1_agent:rf_sink_valid
wire [74:0] expansion_jp1_s1_agent_rsp_fifo_out_data; // Expansion_JP1_s1_agent_rsp_fifo:out_data -> Expansion_JP1_s1_agent:rf_sink_data
wire expansion_jp1_s1_agent_rsp_fifo_out_ready; // Expansion_JP1_s1_agent:rf_sink_ready -> Expansion_JP1_s1_agent_rsp_fifo:out_ready
wire expansion_jp1_s1_agent_rsp_fifo_out_startofpacket; // Expansion_JP1_s1_agent_rsp_fifo:out_startofpacket -> Expansion_JP1_s1_agent:rf_sink_startofpacket
wire expansion_jp1_s1_agent_rsp_fifo_out_endofpacket; // Expansion_JP1_s1_agent_rsp_fifo:out_endofpacket -> Expansion_JP1_s1_agent:rf_sink_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> Expansion_JP1_s1_agent:cp_valid
wire [73:0] cmd_mux_src_data; // cmd_mux:src_data -> Expansion_JP1_s1_agent:cp_data
wire cmd_mux_src_ready; // Expansion_JP1_s1_agent:cp_ready -> cmd_mux:src_ready
wire [1:0] cmd_mux_src_channel; // cmd_mux:src_channel -> Expansion_JP1_s1_agent:cp_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> Expansion_JP1_s1_agent:cp_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> Expansion_JP1_s1_agent:cp_endofpacket
wire video_in_subsystem_top_io_gpi1_streamin_agent_cp_valid; // Video_In_Subsystem_top_io_gpi1_streamin_agent:cp_valid -> router:sink_valid
wire [73:0] video_in_subsystem_top_io_gpi1_streamin_agent_cp_data; // Video_In_Subsystem_top_io_gpi1_streamin_agent:cp_data -> router:sink_data
wire video_in_subsystem_top_io_gpi1_streamin_agent_cp_ready; // router:sink_ready -> Video_In_Subsystem_top_io_gpi1_streamin_agent:cp_ready
wire video_in_subsystem_top_io_gpi1_streamin_agent_cp_startofpacket; // Video_In_Subsystem_top_io_gpi1_streamin_agent:cp_startofpacket -> router:sink_startofpacket
wire video_in_subsystem_top_io_gpi1_streamin_agent_cp_endofpacket; // Video_In_Subsystem_top_io_gpi1_streamin_agent:cp_endofpacket -> router:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire [73:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire [1:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire video_in_subsystem_top_io_gpo1_streamout_agent_cp_valid; // Video_In_Subsystem_top_io_gpo1_streamout_agent:cp_valid -> router_001:sink_valid
wire [73:0] video_in_subsystem_top_io_gpo1_streamout_agent_cp_data; // Video_In_Subsystem_top_io_gpo1_streamout_agent:cp_data -> router_001:sink_data
wire video_in_subsystem_top_io_gpo1_streamout_agent_cp_ready; // router_001:sink_ready -> Video_In_Subsystem_top_io_gpo1_streamout_agent:cp_ready
wire video_in_subsystem_top_io_gpo1_streamout_agent_cp_startofpacket; // Video_In_Subsystem_top_io_gpo1_streamout_agent:cp_startofpacket -> router_001:sink_startofpacket
wire video_in_subsystem_top_io_gpo1_streamout_agent_cp_endofpacket; // Video_In_Subsystem_top_io_gpo1_streamout_agent:cp_endofpacket -> router_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid
wire [73:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data
wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready
wire [1:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
wire expansion_jp1_s1_agent_rp_valid; // Expansion_JP1_s1_agent:rp_valid -> router_002:sink_valid
wire [73:0] expansion_jp1_s1_agent_rp_data; // Expansion_JP1_s1_agent:rp_data -> router_002:sink_data
wire expansion_jp1_s1_agent_rp_ready; // router_002:sink_ready -> Expansion_JP1_s1_agent:rp_ready
wire expansion_jp1_s1_agent_rp_startofpacket; // Expansion_JP1_s1_agent:rp_startofpacket -> router_002:sink_startofpacket
wire expansion_jp1_s1_agent_rp_endofpacket; // Expansion_JP1_s1_agent:rp_endofpacket -> router_002:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux:sink_valid
wire [73:0] router_002_src_data; // router_002:src_data -> rsp_demux:sink_data
wire router_002_src_ready; // rsp_demux:sink_ready -> router_002:src_ready
wire [1:0] router_002_src_channel; // router_002:src_channel -> rsp_demux:sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [73:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [1:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
wire [73:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
wire [1:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [73:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [1:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
wire [73:0] rsp_demux_src1_data; // rsp_demux:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
wire [1:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire expansion_jp1_s1_agent_rdata_fifo_src_valid; // Expansion_JP1_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
wire [33:0] expansion_jp1_s1_agent_rdata_fifo_src_data; // Expansion_JP1_s1_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
wire expansion_jp1_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter:in_0_ready -> Expansion_JP1_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> Expansion_JP1_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> Expansion_JP1_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // Expansion_JP1_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> Expansion_JP1_s1_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (4),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (4),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (1),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) video_in_subsystem_top_io_gpi1_streamin_translator (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_read), // .read
.uav_write (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (Video_In_Subsystem_top_io_gpi1_streamin_address), // avalon_anti_master_0.address
.av_chipselect (Video_In_Subsystem_top_io_gpi1_streamin_chipselect), // .chipselect
.av_read (Video_In_Subsystem_top_io_gpi1_streamin_read), // .read
.av_readdata (Video_In_Subsystem_top_io_gpi1_streamin_readdata), // .readdata
.av_waitrequest (), // (terminated)
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (4),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (4),
.UAV_BURSTCOUNT_W (3),
.USE_READ (0),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (1),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) video_in_subsystem_top_io_gpo1_streamout_translator (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_read), // .read
.uav_write (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (Video_In_Subsystem_top_io_gpo1_streamout_address), // avalon_anti_master_0.address
.av_chipselect (Video_In_Subsystem_top_io_gpo1_streamout_chipselect), // .chipselect
.av_write (Video_In_Subsystem_top_io_gpo1_streamout_write), // .write
.av_writedata (Video_In_Subsystem_top_io_gpo1_streamout_writedata), // .writedata
.av_waitrequest (), // (terminated)
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_read (1'b0), // (terminated)
.av_readdata (), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (4),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) expansion_jp1_s1_translator (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (expansion_jp1_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (expansion_jp1_s1_agent_m0_burstcount), // .burstcount
.uav_read (expansion_jp1_s1_agent_m0_read), // .read
.uav_write (expansion_jp1_s1_agent_m0_write), // .write
.uav_waitrequest (expansion_jp1_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (expansion_jp1_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (expansion_jp1_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (expansion_jp1_s1_agent_m0_readdata), // .readdata
.uav_writedata (expansion_jp1_s1_agent_m0_writedata), // .writedata
.uav_lock (expansion_jp1_s1_agent_m0_lock), // .lock
.uav_debugaccess (expansion_jp1_s1_agent_m0_debugaccess), // .debugaccess
.av_address (Expansion_JP1_s1_address), // avalon_anti_slave_0.address
.av_write (Expansion_JP1_s1_write), // .write
.av_readdata (Expansion_JP1_s1_readdata), // .readdata
.av_writedata (Expansion_JP1_s1_writedata), // .writedata
.av_chipselect (Expansion_JP1_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (73),
.PKT_ORI_BURST_SIZE_L (71),
.PKT_RESPONSE_STATUS_H (70),
.PKT_RESPONSE_STATUS_L (69),
.PKT_QOS_H (58),
.PKT_QOS_L (58),
.PKT_DATA_SIDEBAND_H (56),
.PKT_DATA_SIDEBAND_L (56),
.PKT_ADDR_SIDEBAND_H (55),
.PKT_ADDR_SIDEBAND_L (55),
.PKT_BURST_TYPE_H (54),
.PKT_BURST_TYPE_L (53),
.PKT_CACHE_H (68),
.PKT_CACHE_L (65),
.PKT_THREAD_ID_H (61),
.PKT_THREAD_ID_L (61),
.PKT_BURST_SIZE_H (52),
.PKT_BURST_SIZE_L (50),
.PKT_TRANS_EXCLUSIVE (45),
.PKT_TRANS_LOCK (44),
.PKT_BEGIN_BURST (57),
.PKT_PROTECTION_H (64),
.PKT_PROTECTION_L (62),
.PKT_BURSTWRAP_H (49),
.PKT_BURSTWRAP_L (49),
.PKT_BYTE_CNT_H (48),
.PKT_BYTE_CNT_L (46),
.PKT_ADDR_H (39),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (40),
.PKT_TRANS_POSTED (41),
.PKT_TRANS_WRITE (42),
.PKT_TRANS_READ (43),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (59),
.PKT_SRC_ID_L (59),
.PKT_DEST_ID_H (60),
.PKT_DEST_ID_L (60),
.ST_DATA_W (74),
.ST_CHANNEL_W (2),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) video_in_subsystem_top_io_gpi1_streamin_agent (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_address), // av.address
.av_write (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_write), // .write
.av_read (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_read), // .read
.av_writedata (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (video_in_subsystem_top_io_gpi1_streamin_agent_cp_valid), // cp.valid
.cp_data (video_in_subsystem_top_io_gpi1_streamin_agent_cp_data), // .data
.cp_startofpacket (video_in_subsystem_top_io_gpi1_streamin_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (video_in_subsystem_top_io_gpi1_streamin_agent_cp_endofpacket), // .endofpacket
.cp_ready (video_in_subsystem_top_io_gpi1_streamin_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (73),
.PKT_ORI_BURST_SIZE_L (71),
.PKT_RESPONSE_STATUS_H (70),
.PKT_RESPONSE_STATUS_L (69),
.PKT_QOS_H (58),
.PKT_QOS_L (58),
.PKT_DATA_SIDEBAND_H (56),
.PKT_DATA_SIDEBAND_L (56),
.PKT_ADDR_SIDEBAND_H (55),
.PKT_ADDR_SIDEBAND_L (55),
.PKT_BURST_TYPE_H (54),
.PKT_BURST_TYPE_L (53),
.PKT_CACHE_H (68),
.PKT_CACHE_L (65),
.PKT_THREAD_ID_H (61),
.PKT_THREAD_ID_L (61),
.PKT_BURST_SIZE_H (52),
.PKT_BURST_SIZE_L (50),
.PKT_TRANS_EXCLUSIVE (45),
.PKT_TRANS_LOCK (44),
.PKT_BEGIN_BURST (57),
.PKT_PROTECTION_H (64),
.PKT_PROTECTION_L (62),
.PKT_BURSTWRAP_H (49),
.PKT_BURSTWRAP_L (49),
.PKT_BYTE_CNT_H (48),
.PKT_BYTE_CNT_L (46),
.PKT_ADDR_H (39),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (40),
.PKT_TRANS_POSTED (41),
.PKT_TRANS_WRITE (42),
.PKT_TRANS_READ (43),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (59),
.PKT_SRC_ID_L (59),
.PKT_DEST_ID_H (60),
.PKT_DEST_ID_L (60),
.ST_DATA_W (74),
.ST_CHANNEL_W (2),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) video_in_subsystem_top_io_gpo1_streamout_agent (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_address), // av.address
.av_write (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_write), // .write
.av_read (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_read), // .read
.av_writedata (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (video_in_subsystem_top_io_gpo1_streamout_agent_cp_valid), // cp.valid
.cp_data (video_in_subsystem_top_io_gpo1_streamout_agent_cp_data), // .data
.cp_startofpacket (video_in_subsystem_top_io_gpo1_streamout_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (video_in_subsystem_top_io_gpo1_streamout_agent_cp_endofpacket), // .endofpacket
.cp_ready (video_in_subsystem_top_io_gpo1_streamout_agent_cp_ready), // .ready
.rp_valid (rsp_mux_001_src_valid), // rp.valid
.rp_data (rsp_mux_001_src_data), // .data
.rp_channel (rsp_mux_001_src_channel), // .channel
.rp_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_001_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (73),
.PKT_ORI_BURST_SIZE_L (71),
.PKT_RESPONSE_STATUS_H (70),
.PKT_RESPONSE_STATUS_L (69),
.PKT_BURST_SIZE_H (52),
.PKT_BURST_SIZE_L (50),
.PKT_TRANS_LOCK (44),
.PKT_BEGIN_BURST (57),
.PKT_PROTECTION_H (64),
.PKT_PROTECTION_L (62),
.PKT_BURSTWRAP_H (49),
.PKT_BURSTWRAP_L (49),
.PKT_BYTE_CNT_H (48),
.PKT_BYTE_CNT_L (46),
.PKT_ADDR_H (39),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (40),
.PKT_TRANS_POSTED (41),
.PKT_TRANS_WRITE (42),
.PKT_TRANS_READ (43),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (59),
.PKT_SRC_ID_L (59),
.PKT_DEST_ID_H (60),
.PKT_DEST_ID_L (60),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (2),
.ST_DATA_W (74),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) expansion_jp1_s1_agent (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (expansion_jp1_s1_agent_m0_address), // m0.address
.m0_burstcount (expansion_jp1_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (expansion_jp1_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (expansion_jp1_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (expansion_jp1_s1_agent_m0_lock), // .lock
.m0_readdata (expansion_jp1_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (expansion_jp1_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (expansion_jp1_s1_agent_m0_read), // .read
.m0_waitrequest (expansion_jp1_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (expansion_jp1_s1_agent_m0_writedata), // .writedata
.m0_write (expansion_jp1_s1_agent_m0_write), // .write
.rp_endofpacket (expansion_jp1_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (expansion_jp1_s1_agent_rp_ready), // .ready
.rp_valid (expansion_jp1_s1_agent_rp_valid), // .valid
.rp_data (expansion_jp1_s1_agent_rp_data), // .data
.rp_startofpacket (expansion_jp1_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (expansion_jp1_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (expansion_jp1_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (expansion_jp1_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (expansion_jp1_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (expansion_jp1_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (expansion_jp1_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (expansion_jp1_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (expansion_jp1_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (expansion_jp1_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (expansion_jp1_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (expansion_jp1_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (expansion_jp1_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (expansion_jp1_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (75),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) expansion_jp1_s1_agent_rsp_fifo (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (expansion_jp1_s1_agent_rf_source_data), // in.data
.in_valid (expansion_jp1_s1_agent_rf_source_valid), // .valid
.in_ready (expansion_jp1_s1_agent_rf_source_ready), // .ready
.in_startofpacket (expansion_jp1_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (expansion_jp1_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (expansion_jp1_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (expansion_jp1_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (expansion_jp1_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (expansion_jp1_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (expansion_jp1_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
Computer_System_mm_interconnect_4_router router (
.sink_ready (video_in_subsystem_top_io_gpi1_streamin_agent_cp_ready), // sink.ready
.sink_valid (video_in_subsystem_top_io_gpi1_streamin_agent_cp_valid), // .valid
.sink_data (video_in_subsystem_top_io_gpi1_streamin_agent_cp_data), // .data
.sink_startofpacket (video_in_subsystem_top_io_gpi1_streamin_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (video_in_subsystem_top_io_gpi1_streamin_agent_cp_endofpacket), // .endofpacket
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_router router_001 (
.sink_ready (video_in_subsystem_top_io_gpo1_streamout_agent_cp_ready), // sink.ready
.sink_valid (video_in_subsystem_top_io_gpo1_streamout_agent_cp_valid), // .valid
.sink_data (video_in_subsystem_top_io_gpo1_streamout_agent_cp_data), // .data
.sink_startofpacket (video_in_subsystem_top_io_gpo1_streamout_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (video_in_subsystem_top_io_gpo1_streamout_agent_cp_endofpacket), // .endofpacket
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_router_002 router_002 (
.sink_ready (expansion_jp1_s1_agent_rp_ready), // sink.ready
.sink_valid (expansion_jp1_s1_agent_rp_valid), // .valid
.sink_data (expansion_jp1_s1_agent_rp_data), // .data
.sink_startofpacket (expansion_jp1_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (expansion_jp1_s1_agent_rp_endofpacket), // .endofpacket
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_cmd_demux cmd_demux (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_cmd_demux cmd_demux_001 (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_cmd_mux cmd_mux (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_rsp_demux rsp_demux (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_src1_ready), // src1.ready
.src1_valid (rsp_demux_src1_valid), // .valid
.src1_data (rsp_demux_src1_data), // .data
.src1_channel (rsp_demux_src1_channel), // .channel
.src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_rsp_mux rsp_mux (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_rsp_mux rsp_mux_001 (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_src1_valid), // .valid
.sink0_channel (rsp_demux_src1_channel), // .channel
.sink0_data (rsp_demux_src1_data), // .data
.sink0_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (System_PLL_sys_clk_clk), // in_clk_0.clk
.in_rst_0_reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (expansion_jp1_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (expansion_jp1_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (expansion_jp1_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: altpcie_pll_15625_125.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Build 174 10/19/2005 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altpcie_pll_15625_125 (
areset,
inclk0,
c0);
input areset;
input inclk0;
output c0;
wire [5:0] sub_wire0;
wire [0:0] sub_wire2 = 1'h0;
wire [0:0] sub_wire4 = 1'h1;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire [5:0] sub_wire3 = {sub_wire2, sub_wire2, sub_wire2, sub_wire2, sub_wire2, sub_wire4};
wire sub_wire5 = inclk0;
wire [1:0] sub_wire6 = {sub_wire2, sub_wire5};
wire [3:0] sub_wire7 = {sub_wire2, sub_wire2, sub_wire2, sub_wire2};
altpll altpll_component (
.clkena (sub_wire3),
.inclk (sub_wire6),
.extclkena (sub_wire7),
.areset (areset),
.clk (sub_wire0)
// synopsys translate_off
,
.scanclk (),
.pllena (),
.sclkout1 (),
.sclkout0 (),
.fbin (),
.scandone (),
.clkloss (),
.extclk (),
.clkswitch (),
.pfdena (),
.scanaclr (),
.clkbad (),
.scandata (),
.enable1 (),
.scandataout (),
.enable0 (),
.scanwrite (),
.locked (),
.activeclock (),
.scanread ()
// synopsys translate_on
);
defparam
altpll_component.bandwidth = 500000,
altpll_component.bandwidth_type = "CUSTOM",
altpll_component.clk0_divide_by = 5,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 4,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 6400,
altpll_component.intended_device_family = "Stratix GX",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "ENHANCED",
altpll_component.spread_frequency = 0;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "2.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "10"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "5"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Stratix GX"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "10000"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "0"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "156.250"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "125.000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH NUMERIC "500000"
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "CUSTOM"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "6400"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix GX"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "ENHANCED"
// Retrieval info: CONSTANT: SPREAD_FREQUENCY NUMERIC "0"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: @extclkena 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 4 GND 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @extclkena 0 0 1 2 GND 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 5 GND 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 2 GND 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 0 VCC 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @extclkena 0 0 1 3 GND 0 0 0 0
// Retrieval info: CONNECT: @extclkena 0 0 1 0 GND 0 0 0 0
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 3 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_15625_125.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_15625_125.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_15625_125.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_15625_125.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_15625_125_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_15625_125_bb.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_15625_125_waveforms.html FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_15625_125_wave*.jpg FALSE FALSE
|
module controller(clk, IR, N, Z, P, StateID, Mux1, Mux2, Mux3, Mux4, Mux5, Mux6, Mux7, Mux11, Mux12, wrf, wpc, wir, lccr, aluop, alushop, wmem); // Implements the designed controller for LC-3b.
input [15:0] IR;
input clk, N, Z, P;
output reg [3:0] StateID;
output reg Mux1;
output reg [1:0] Mux2;
output reg [2:0] Mux3;
output reg [1:0] Mux4;
output reg [1:0] Mux5;
output reg [1:0] Mux6;
output reg [1:0] Mux7;
output reg Mux11;
output reg Mux12;
output reg wrf;
output reg wpc;
output reg wir;
output reg lccr;
output reg [1:0] aluop;
output reg [1:0] alushop;
output reg wmem;
assign Mux8 = IR[5];
assign Mux9 = (IR[11] && N) || (IR[10] && Z) || (IR[9] && P);
assign Mux10 = IR[11];
always@(posedge clk) begin
case(StateID)
1: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b111;
Mux4 = 2'b01;
Mux5 = 2'b01;
Mux6 = 2'b10;
Mux7 = 2'b10;
Mux11 = 1'b1;
Mux12 = 1'b0;
wrf = 1'b1;
wpc = 1'b0;
wir = 1'b0;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
end
2: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b000;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
Mux12 = 1'b0;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
end
3: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b111;
Mux4 = 2'b00;
Mux5 = 2'b00;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
Mux12 = 1'b0;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b0;
aluop = {IR[15], IR[14]};
alushop = {IR[5], IR[4]};
wmem = 1'b1;
end
4: begin
Mux1 = 1'b1;
Mux2 = 2'b01;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b0;
Mux12 = 1'b0;
wrf = 1'b0;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
end
5: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b011;
Mux4 = 2'b01;
Mux5 = 2'b00;
Mux6 = 2'b00;
Mux7 = 2'b11;
Mux11 = 1'b1;
Mux12 = 1'b0;
wrf = 1'b1;
wpc = 1'b0;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
end
6: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
Mux12 = 1'b0;
wrf = 1'b1;
wpc = 1'b0;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
end
7: begin
Mux1 = 1'b1;
Mux2 = 2'b10;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
Mux12 = 1'b0;
wrf = 1'b0;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
end
8: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b001;
Mux4 = 2'b01;
Mux5 = 2'b00;
Mux6 = 2'b01;
Mux7 = 2'b11;
Mux11 = 1'b1;
Mux12 = 1'b0;
wrf = 1'b1;
wpc = 1'b0;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
end
9: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b101;
Mux4 = 2'b00;
Mux5 = 2'b00;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
Mux12 = 1'b0;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
end
10: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b01;
Mux11 = 1'b1;
Mux12 = 1'b0;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
end
11: begin
Mux1 = 1'b1;
Mux2 = 2'b00;
Mux3 = 3'b111;
Mux4 = 2'b10;
Mux5 = 2'b10;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b0;
Mux12 = 1'b0;
wrf = 1'b0;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b0;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
end
12: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b010;
Mux4 = 2'b00;
Mux5 = 2'b00;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
Mux12 = 1'b0;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
end
13: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b011;
Mux4 = 2'b01;
Mux5 = 2'b00;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
Mux12 = 1'b0;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b0;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
end
14: begin
Mux1 = 1'b1;
Mux2 = 2'b01;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b0;
Mux12 = 1'b0;
wrf = 1'b0;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
end
15: begin
Mux1 = 1'b0;
Mux2 = 2'b11;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
Mux12 = 1'b0;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
end
16: begin
Mux1 = 1'b0;
Mux2 = 2'b11;
Mux3 = 3'b101;
Mux4 = 2'b00;
Mux5 = 2'b00;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
Mux12 = 1'b0;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
end
17: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b01;
Mux11 = 1'b1;
Mux12 = 1'b0;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b0;
end
18: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b010;
Mux4 = 2'b00;
Mux5 = 2'b00;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
Mux12 = 1'b0;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
end
endcase
end
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O22AI_BEHAVIORAL_V
`define SKY130_FD_SC_HD__O22AI_BEHAVIORAL_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o22ai (
Y ,
A1,
A2,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y, nor1_out, nor0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O22AI_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__O21AI_FUNCTIONAL_PP_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__o21ai (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21AI_FUNCTIONAL_PP_V |
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module system1_nios2_gen2_0_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: channel_64.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Represents a RIFFA channel. Contains a RX port and a
// TX port.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module channel_64 #(
parameter C_DATA_WIDTH = 9'd64,
parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
// Local parameters
parameter C_RX_FIFO_DEPTH = 1024,
parameter C_TX_FIFO_DEPTH = 512,
parameter C_SG_FIFO_DEPTH = 1024,
parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
input [31:0] PIO_DATA, // Single word programmed I/O data
input [C_DATA_WIDTH-1:0] ENG_DATA, // Main incoming data
output SG_RX_BUF_RECVD, // Scatter gather RX buffer completely read (ready for next if applicable)
input SG_RX_BUF_LEN_VALID, // Scatter gather RX buffer length valid
input SG_RX_BUF_ADDR_HI_VALID, // Scatter gather RX buffer high address valid
input SG_RX_BUF_ADDR_LO_VALID, // Scatter gather RX buffer low address valid
output SG_TX_BUF_RECVD, // Scatter gather TX buffer completely read (ready for next if applicable)
input SG_TX_BUF_LEN_VALID, // Scatter gather TX buffer length valid
input SG_TX_BUF_ADDR_HI_VALID, // Scatter gather TX buffer high address valid
input SG_TX_BUF_ADDR_LO_VALID, // Scatter gather TX buffer low address valid
input TXN_RX_LEN_VALID, // Read transaction length valid
input TXN_RX_OFF_LAST_VALID, // Read transaction offset/last valid
output [31:0] TXN_RX_DONE_LEN, // Read transaction actual transfer length
output TXN_RX_DONE, // Read transaction done
input TXN_RX_DONE_ACK, // Read transaction actual transfer length read
output TXN_TX, // Write transaction notification
input TXN_TX_ACK, // Write transaction acknowledged
output [31:0] TXN_TX_LEN, // Write transaction length
output [31:0] TXN_TX_OFF_LAST, // Write transaction offset/last
output [31:0] TXN_TX_DONE_LEN, // Write transaction actual transfer length
output TXN_TX_DONE, // Write transaction done
input TXN_TX_DONE_ACK, // Write transaction actual transfer length read
output RX_REQ, // Read request
input RX_REQ_ACK, // Read request accepted
output [1:0] RX_REQ_TAG, // Read request data tag
output [63:0] RX_REQ_ADDR, // Read request address
output [9:0] RX_REQ_LEN, // Read request length
output TX_REQ, // Outgoing write request
input TX_REQ_ACK, // Outgoing write request acknowledged
output [63:0] TX_ADDR, // Outgoing write high address
output [9:0] TX_LEN, // Outgoing write length (in 32 bit words)
output [C_DATA_WIDTH-1:0] TX_DATA, // Outgoing write data
input TX_DATA_REN, // Outgoing write data read enable
input TX_SENT, // Outgoing write complete
input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN, // Main incoming data enable
input MAIN_DONE, // Main incoming data complete
input MAIN_ERR, // Main incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN, // Scatter gather for RX incoming data enable
input SG_RX_DONE, // Scatter gather for RX incoming data complete
input SG_RX_ERR, // Scatter gather for RX incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN, // Scatter gather for TX incoming data enable
input SG_TX_DONE, // Scatter gather for TX incoming data complete
input SG_TX_ERR, // Scatter gather for TX incoming data completed with error
input CHNL_RX_CLK, // Channel read clock
output CHNL_RX, // Channel read receive signal
input CHNL_RX_ACK, // Channle read received signal
output CHNL_RX_LAST, // Channel last read
output [31:0] CHNL_RX_LEN, // Channel read length
output [30:0] CHNL_RX_OFF, // Channel read offset
output [C_DATA_WIDTH-1:0] CHNL_RX_DATA, // Channel read data
output CHNL_RX_DATA_VALID, // Channel read data valid
input CHNL_RX_DATA_REN, // Channel read data has been recieved
input CHNL_TX_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
`include "functions.vh"
wire [C_DATA_WIDTH-1:0] wTxSgData;
wire wTxSgDataEmpty;
wire wTxSgDataRen;
wire wTxSgDataErr;
wire wTxSgDataRst;
// Receiving port (data to the channel)
rx_port_64 #(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_MAIN_FIFO_DEPTH(C_RX_FIFO_DEPTH),
.C_SG_FIFO_DEPTH(C_SG_FIFO_DEPTH),
.C_MAX_READ_REQ(C_MAX_READ_REQ)
) rxPort (
.RST(RST),
.CLK(CLK),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.SG_RX_BUF_RECVD(SG_RX_BUF_RECVD),
.SG_RX_BUF_DATA(PIO_DATA),
.SG_RX_BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),
.SG_RX_BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),
.SG_RX_BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),
.SG_TX_BUF_RECVD(SG_TX_BUF_RECVD),
.SG_TX_BUF_DATA(PIO_DATA),
.SG_TX_BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),
.SG_TX_BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),
.SG_TX_BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),
.SG_DATA(wTxSgData),
.SG_DATA_EMPTY(wTxSgDataEmpty),
.SG_DATA_REN(wTxSgDataRen),
.SG_RST(wTxSgDataRst),
.SG_ERR(wTxSgDataErr),
.TXN_DATA(PIO_DATA),
.TXN_LEN_VALID(TXN_RX_LEN_VALID),
.TXN_OFF_LAST_VALID(TXN_RX_OFF_LAST_VALID),
.TXN_DONE_LEN(TXN_RX_DONE_LEN),
.TXN_DONE(TXN_RX_DONE),
.TXN_DONE_ACK(TXN_RX_DONE_ACK),
.RX_REQ(RX_REQ),
.RX_REQ_ACK(RX_REQ_ACK),
.RX_REQ_TAG(RX_REQ_TAG),
.RX_REQ_ADDR(RX_REQ_ADDR),
.RX_REQ_LEN(RX_REQ_LEN),
.MAIN_DATA(ENG_DATA),
.MAIN_DATA_EN(MAIN_DATA_EN),
.MAIN_DONE(MAIN_DONE),
.MAIN_ERR(MAIN_ERR),
.SG_RX_DATA(ENG_DATA),
.SG_RX_DATA_EN(SG_RX_DATA_EN),
.SG_RX_DONE(SG_RX_DONE),
.SG_RX_ERR(SG_RX_ERR),
.SG_TX_DATA(ENG_DATA),
.SG_TX_DATA_EN(SG_TX_DATA_EN),
.SG_TX_DONE(SG_TX_DONE),
.SG_TX_ERR(SG_TX_ERR),
.CHNL_CLK(CHNL_RX_CLK),
.CHNL_RX(CHNL_RX),
.CHNL_RX_ACK(CHNL_RX_ACK),
.CHNL_RX_LAST(CHNL_RX_LAST),
.CHNL_RX_LEN(CHNL_RX_LEN),
.CHNL_RX_OFF(CHNL_RX_OFF),
.CHNL_RX_DATA(CHNL_RX_DATA),
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID),
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)
);
// Sending port (data from the channel)
tx_port_64 #(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_FIFO_DEPTH(C_TX_FIFO_DEPTH)
) txPort (
.CLK(CLK),
.RST(RST),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.TXN(TXN_TX),
.TXN_ACK(TXN_TX_ACK),
.TXN_LEN(TXN_TX_LEN),
.TXN_OFF_LAST(TXN_TX_OFF_LAST),
.TXN_DONE_LEN(TXN_TX_DONE_LEN),
.TXN_DONE(TXN_TX_DONE),
.TXN_DONE_ACK(TXN_TX_DONE_ACK),
.SG_DATA(wTxSgData),
.SG_DATA_EMPTY(wTxSgDataEmpty),
.SG_DATA_REN(wTxSgDataRen),
.SG_RST(wTxSgDataRst),
.SG_ERR(wTxSgDataErr),
.TX_REQ(TX_REQ),
.TX_REQ_ACK(TX_REQ_ACK),
.TX_ADDR(TX_ADDR),
.TX_LEN(TX_LEN),
.TX_DATA(TX_DATA),
.TX_DATA_REN(TX_DATA_REN),
.TX_SENT(TX_SENT),
.CHNL_CLK(CHNL_TX_CLK),
.CHNL_TX(CHNL_TX),
.CHNL_TX_ACK(CHNL_TX_ACK),
.CHNL_TX_LAST(CHNL_TX_LAST),
.CHNL_TX_LEN(CHNL_TX_LEN),
.CHNL_TX_OFF(CHNL_TX_OFF),
.CHNL_TX_DATA(CHNL_TX_DATA),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
);
endmodule
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * Copyright INRIA, CNRS and contributors *)
(* <O___,, * (see version control and CREDITS file for authors & dates) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
Require Export NumPrelude NZAxioms.
Require Import NZBase NZOrder NZAddOrder Plus Minus.
(** In this file, we investigate the shape of domains satisfying
the [NZDomainSig] interface. In particular, we define a
translation from Peano numbers [nat] into NZ.
*)
Local Notation "f ^ n" := (fun x => nat_rect _ x (fun _ => f) n).
Instance nat_rect_wd n {A} (R:relation A) :
Proper (R==>(R==>R)==>R) (fun x f => nat_rect (fun _ => _) x (fun _ => f) n).
Proof.
intros x y eq_xy f g eq_fg; induction n; [assumption | now apply eq_fg].
Qed.
Module NZDomainProp (Import NZ:NZDomainSig').
Include NZBaseProp NZ.
(** * Relationship between points thanks to [succ] and [pred]. *)
(** For any two points, one is an iterated successor of the other. *)
Lemma itersucc_or_itersucc n m : exists k, n == (S^k) m \/ m == (S^k) n.
Proof.
revert n.
apply central_induction with (z:=m).
{ intros x y eq_xy; apply ex_iff_morphism.
intros n; apply or_iff_morphism.
+ split; intros; etransitivity; try eassumption; now symmetry.
+ split; intros; (etransitivity; [eassumption|]); [|symmetry];
(eapply nat_rect_wd; [eassumption|apply succ_wd]).
}
exists 0%nat. now left.
intros n. split; intros [k [L|R]].
exists (Datatypes.S k). left. now apply succ_wd.
destruct k as [|k].
simpl in R. exists 1%nat. left. now apply succ_wd.
rewrite nat_rect_succ_r in R. exists k. now right.
destruct k as [|k]; simpl in L.
exists 1%nat. now right.
apply succ_inj in L. exists k. now left.
exists (Datatypes.S k). right. now rewrite nat_rect_succ_r.
Qed.
(** Generalized version of [pred_succ] when iterating *)
Lemma succ_swap_pred : forall k n m, n == (S^k) m -> m == (P^k) n.
Proof.
induction k.
simpl; auto with *.
simpl; intros. apply pred_wd in H. rewrite pred_succ in H. apply IHk in H; auto.
rewrite <- nat_rect_succ_r in H; auto.
Qed.
(** From a given point, all others are iterated successors
or iterated predecessors. *)
Lemma itersucc_or_iterpred : forall n m, exists k, n == (S^k) m \/ n == (P^k) m.
Proof.
intros n m. destruct (itersucc_or_itersucc n m) as (k,[H|H]).
exists k; left; auto.
exists k; right. apply succ_swap_pred; auto.
Qed.
(** In particular, all points are either iterated successors of [0]
or iterated predecessors of [0] (or both). *)
Lemma itersucc0_or_iterpred0 :
forall n, exists p:nat, n == (S^p) 0 \/ n == (P^p) 0.
Proof.
intros n. exact (itersucc_or_iterpred n 0).
Qed.
(** * Study of initial point w.r.t. [succ] (if any). *)
Definition initial n := forall m, n ~= S m.
Lemma initial_alt : forall n, initial n <-> S (P n) ~= n.
Proof.
split. intros Bn EQ. symmetry in EQ. destruct (Bn _ EQ).
intros NEQ m EQ. apply NEQ. rewrite EQ, pred_succ; auto with *.
Qed.
Lemma initial_alt2 : forall n, initial n <-> ~exists m, n == S m.
Proof. firstorder. Qed.
(** First case: let's assume such an initial point exists
(i.e. [S] isn't surjective)... *)
Section InitialExists.
Hypothesis init : t.
Hypothesis Initial : initial init.
(** ... then we have unicity of this initial point. *)
Lemma initial_unique : forall m, initial m -> m == init.
Proof.
intros m Im. destruct (itersucc_or_itersucc init m) as (p,[H|H]).
destruct p. now simpl in *. destruct (Initial _ H).
destruct p. now simpl in *. destruct (Im _ H).
Qed.
(** ... then all other points are descendant of it. *)
Lemma initial_ancestor : forall m, exists p, m == (S^p) init.
Proof.
intros m. destruct (itersucc_or_itersucc init m) as (p,[H|H]).
destruct p; simpl in *; auto. exists O; auto with *. destruct (Initial _ H).
exists p; auto.
Qed.
(** NB : We would like to have [pred n == n] for the initial element,
but nothing forces that. For instance we can have -3 as initial point,
and P(-3) = 2. A bit odd indeed, but legal according to [NZDomainSig].
We can hence have [n == (P^k) m] without [exists k', m == (S^k') n].
*)
(** We need decidability of [eq] (or classical reasoning) for this: *)
Section SuccPred.
Hypothesis eq_decidable : forall n m, n==m \/ n~=m.
Lemma succ_pred_approx : forall n, ~initial n -> S (P n) == n.
Proof.
intros n NB. rewrite initial_alt in NB.
destruct (eq_decidable (S (P n)) n); auto.
elim NB; auto.
Qed.
End SuccPred.
End InitialExists.
(** Second case : let's suppose now [S] surjective, i.e. no initial point. *)
Section InitialDontExists.
Hypothesis succ_onto : forall n, exists m, n == S m.
Lemma succ_onto_gives_succ_pred : forall n, S (P n) == n.
Proof.
intros n. destruct (succ_onto n) as (m,H). rewrite H, pred_succ; auto with *.
Qed.
Lemma succ_onto_pred_injective : forall n m, P n == P m -> n == m.
Proof.
intros n m. intros H; apply succ_wd in H.
rewrite !succ_onto_gives_succ_pred in H; auto.
Qed.
End InitialDontExists.
(** To summarize:
S is always injective, P is always surjective (thanks to [pred_succ]).
I) If S is not surjective, we have an initial point, which is unique.
This bottom is below zero: we have N shifted (or not) to the left.
P cannot be injective: P init = P (S (P init)).
(P init) can be arbitrary.
II) If S is surjective, we have [forall n, S (P n) = n], S and P are
bijective and reciprocal.
IIa) if [exists k<>O, 0 == S^k 0], then we have a cyclic structure Z/nZ
IIb) otherwise, we have Z
*)
(** * An alternative induction principle using [S] and [P]. *)
(** It is weaker than [bi_induction]. For instance it cannot prove that
we can go from one point by many [S] _or_ many [P], but only by many
[S] mixed with many [P]. Think of a model with two copies of N:
0, 1=S 0, 2=S 1, ...
0', 1'=S 0', 2'=S 1', ...
and P 0 = 0' and P 0' = 0.
*)
Lemma bi_induction_pred :
forall A : t -> Prop, Proper (eq==>iff) A ->
A 0 -> (forall n, A n -> A (S n)) -> (forall n, A n -> A (P n)) ->
forall n, A n.
Proof.
intros. apply bi_induction; auto.
clear n. intros n; split; auto.
intros G; apply H2 in G. rewrite pred_succ in G; auto.
Qed.
Lemma central_induction_pred :
forall A : t -> Prop, Proper (eq==>iff) A -> forall n0,
A n0 -> (forall n, A n -> A (S n)) -> (forall n, A n -> A (P n)) ->
forall n, A n.
Proof.
intros.
assert (A 0).
destruct (itersucc_or_iterpred 0 n0) as (k,[Hk|Hk]); rewrite Hk; clear Hk.
clear H2. induction k; simpl in *; auto.
clear H1. induction k; simpl in *; auto.
apply bi_induction_pred; auto.
Qed.
End NZDomainProp.
(** We now focus on the translation from [nat] into [NZ].
First, relationship with [0], [succ], [pred].
*)
Module NZOfNat (Import NZ:NZDomainSig').
Definition ofnat (n : nat) : t := (S^n) 0.
Declare Scope ofnat.
Local Open Scope ofnat.
Notation "[ n ]" := (ofnat n) (at level 7) : ofnat.
Lemma ofnat_zero : [O] == 0.
Proof.
reflexivity.
Qed.
Lemma ofnat_succ : forall n, [Datatypes.S n] == succ [n].
Proof.
now unfold ofnat.
Qed.
Lemma ofnat_pred : forall n, n<>O -> [Peano.pred n] == P [n].
Proof.
unfold ofnat. destruct n. destruct 1; auto.
intros _. simpl. symmetry. apply pred_succ.
Qed.
(** Since [P 0] can be anything in NZ (either [-1], [0], or even other
numbers, we cannot state previous lemma for [n=O]. *)
End NZOfNat.
(** If we require in addition a strict order on NZ, we can prove that
[ofnat] is injective, and hence that NZ is infinite
(i.e. we ban Z/nZ models) *)
Module NZOfNatOrd (Import NZ:NZOrdSig').
Include NZOfNat NZ.
Include NZBaseProp NZ <+ NZOrderProp NZ.
Local Open Scope ofnat.
Theorem ofnat_S_gt_0 :
forall n : nat, 0 < [Datatypes.S n].
Proof.
unfold ofnat.
intros n; induction n as [| n IH]; simpl in *.
apply lt_succ_diag_r.
apply lt_trans with (S 0). apply lt_succ_diag_r. now rewrite <- succ_lt_mono.
Qed.
Theorem ofnat_S_neq_0 :
forall n : nat, 0 ~= [Datatypes.S n].
Proof.
intros. apply lt_neq, ofnat_S_gt_0.
Qed.
Lemma ofnat_injective : forall n m, [n]==[m] -> n = m.
Proof.
induction n as [|n IH]; destruct m; auto.
intros H; elim (ofnat_S_neq_0 _ H).
intros H; symmetry in H; elim (ofnat_S_neq_0 _ H).
intros. f_equal. apply IH. now rewrite <- succ_inj_wd.
Qed.
Lemma ofnat_eq : forall n m, [n]==[m] <-> n = m.
Proof.
split. apply ofnat_injective. intros; now subst.
Qed.
(* In addition, we can prove that [ofnat] preserves order. *)
Lemma ofnat_lt : forall n m : nat, [n]<[m] <-> (n<m)%nat.
Proof.
induction n as [|n IH]; destruct m; repeat rewrite ofnat_zero; split.
intro H; elim (lt_irrefl _ H).
inversion 1.
auto with arith.
intros; apply ofnat_S_gt_0.
intro H; elim (lt_asymm _ _ H); apply ofnat_S_gt_0.
inversion 1.
rewrite !ofnat_succ, <- succ_lt_mono, IH; auto with arith.
rewrite !ofnat_succ, <- succ_lt_mono, IH; auto with arith.
Qed.
Lemma ofnat_le : forall n m : nat, [n]<=[m] <-> (n<=m)%nat.
Proof.
intros. rewrite lt_eq_cases, ofnat_lt, ofnat_eq.
split.
destruct 1; subst; auto with arith.
apply Lt.le_lt_or_eq.
Qed.
End NZOfNatOrd.
(** For basic operations, we can prove correspondence with
their counterpart in [nat]. *)
Module NZOfNatOps (Import NZ:NZAxiomsSig').
Include NZOfNat NZ.
Local Open Scope ofnat.
Lemma ofnat_add_l : forall n m, [n]+m == (S^n) m.
Proof.
induction n; intros.
apply add_0_l.
rewrite ofnat_succ, add_succ_l. simpl. now f_equiv.
Qed.
Lemma ofnat_add : forall n m, [n+m] == [n]+[m].
Proof.
intros. rewrite ofnat_add_l.
induction n; simpl. reflexivity.
now f_equiv.
Qed.
Lemma ofnat_mul : forall n m, [n*m] == [n]*[m].
Proof.
induction n; simpl; intros.
symmetry. apply mul_0_l.
rewrite plus_comm.
rewrite ofnat_add, mul_succ_l.
now f_equiv.
Qed.
Lemma ofnat_sub_r : forall n m, n-[m] == (P^m) n.
Proof.
induction m; simpl; intros.
apply sub_0_r.
rewrite sub_succ_r. now f_equiv.
Qed.
Lemma ofnat_sub : forall n m, m<=n -> [n-m] == [n]-[m].
Proof.
intros n m H. rewrite ofnat_sub_r.
revert n H. induction m. intros.
rewrite <- minus_n_O. now simpl.
intros.
destruct n.
inversion H.
rewrite nat_rect_succ_r.
simpl.
etransitivity. apply IHm. auto with arith.
eapply nat_rect_wd; [symmetry;apply pred_succ|apply pred_wd].
Qed.
End NZOfNatOps.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21OI_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__A21OI_PP_BLACKBOX_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a21oi (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21OI_PP_BLACKBOX_V
|
/* ****************************************************************************
This Source Code Form is subject to the terms of the
Open Hardware Description License, v. 1.0. If a copy
of the OHDL was not distributed with this file, You
can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
Description: mor1kx processor Wishbone bus bridge
For now, very simple, not registering, assumes 32-bit data, addressing
Copyright (C) 2012 Authors
Author(s): Julius Baxter <[email protected]>
***************************************************************************** */
`include "mor1kx-defines.v"
module mor1kx_bus_if_wb32
#(
parameter BUS_IF_TYPE = "CLASSIC",
parameter BURST_LENGTH = 8
)
(
input clk,
input rst,
output cpu_err_o,
output cpu_ack_o,
output [31:0] cpu_dat_o,
input [31:0] cpu_adr_i,
input [31:0] cpu_dat_i,
input cpu_req_i,
input [3:0] cpu_bsel_i,
input cpu_we_i,
input cpu_burst_i,
output [31:0] wbm_adr_o,
output wbm_stb_o,
output wbm_cyc_o,
output [3:0] wbm_sel_o,
output wbm_we_o,
output [2:0] wbm_cti_o,
output [1:0] wbm_bte_o,
output [31:0] wbm_dat_o,
input wbm_err_i,
input wbm_ack_i,
input [31:0] wbm_dat_i,
input wbm_rty_i
);
localparam BADDR_WITH = (BURST_LENGTH==4) ? 2 :
(BURST_LENGTH==8) ? 3 :
(BURST_LENGTH==16)? 4 : 30;
initial
$display("%m: Wishbone bus IF is %s",BUS_IF_TYPE);
generate
/* verilator lint_off WIDTH */
if (BUS_IF_TYPE=="B3_READ_BURSTING") begin : b3_read_bursting
/* verilator lint_on WIDTH */
// Burst until the incoming address is not what it should be
wire finish_burst;
reg finish_burst_r;
reg bursting;
reg [31:2] burst_address;
reg [BADDR_WITH-1:0] burst_wrap_start;
wire [BADDR_WITH-1:0] burst_wrap_finish;
wire address_differs;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
bursting <= 0;
else if (wbm_err_i)
bursting <= 0;
else if (bursting & finish_burst & wbm_ack_i)
bursting <= 0;
else if (cpu_req_i & !bursting & !cpu_we_i)
bursting <= 1;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
begin
burst_address <= 0;
burst_wrap_start <= 0;
end
else if (cpu_req_i & !bursting)
begin
burst_address <= cpu_adr_i[31:2];
burst_wrap_start <= cpu_adr_i[BADDR_WITH+2-1:2];
end
else if (wbm_ack_i)
burst_address[BADDR_WITH+2-1:2] <= burst_address[BADDR_WITH+2-1:2]
+ 1;
assign address_differs = (burst_address!=cpu_adr_i[31:2]);
assign burst_wrap_finish = burst_wrap_start - 1;
assign finish_burst = (bursting & (
(BURST_LENGTH!=0 &&
burst_address[BADDR_WITH+2-1:2]==(burst_wrap_finish))
| address_differs
| !cpu_req_i
)
)
;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
finish_burst_r <= 0;
else if (wbm_ack_i)
finish_burst_r <= finish_burst;
else
finish_burst_r <= 0;
assign wbm_adr_o = bursting ? {burst_address,2'b00} : cpu_adr_i;
assign wbm_stb_o = bursting & !finish_burst_r;
assign wbm_cyc_o = bursting & !finish_burst_r;
assign wbm_sel_o = cpu_bsel_i;
assign wbm_we_o = cpu_we_i;
assign wbm_cti_o = bursting ? (finish_burst ? 3'b111 : 3'b010) :
3'b000;
assign wbm_bte_o = BURST_LENGTH==4 ? 2'b01 :
BURST_LENGTH==8 ? 2'b10 :
BURST_LENGTH==16 ? 2'b11 :
2'b00; // Linear burst
assign wbm_dat_o = cpu_dat_i;
assign cpu_err_o = wbm_err_i;
assign cpu_ack_o = (wbm_ack_i) &
!(bursting & address_differs) & cpu_req_i;
assign cpu_dat_o = wbm_err_i ? 0 : wbm_dat_i;
/* verilator lint_off WIDTH */
end else if (BUS_IF_TYPE=="B3_REGISTERED_FEEDBACK") begin : b3_registered_feedback
/* verilator lint_on WIDTH */
assign wbm_adr_o = cpu_adr_i;
assign wbm_stb_o = cpu_req_i;
assign wbm_cyc_o = cpu_req_i;
assign wbm_sel_o = cpu_bsel_i;
assign wbm_we_o = cpu_we_i;
assign wbm_cti_o = cpu_burst_i ? 3'b010 : 3'b111;
assign wbm_bte_o = BURST_LENGTH==4 ? 2'b01 :
BURST_LENGTH==8 ? 2'b10 :
BURST_LENGTH==16 ? 2'b11 :
2'b00; // Linear burst
assign wbm_dat_o = cpu_dat_i;
assign cpu_err_o = wbm_err_i;
assign cpu_ack_o = wbm_ack_i;
assign cpu_dat_o = wbm_dat_i;
end else begin : classic // CLASSIC only
// Only classic, single cycle accesses
// A register to force de-assertion of access request signals after
// each ack
reg cycle_end;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
cycle_end <= 1;
else
cycle_end <= wbm_ack_i | wbm_err_i;
assign cpu_err_o = wbm_err_i;
assign cpu_ack_o = wbm_ack_i;
assign cpu_dat_o = wbm_dat_i;
assign wbm_adr_o = cpu_adr_i;
assign wbm_stb_o = cpu_req_i & !cycle_end;
assign wbm_cyc_o = cpu_req_i;
assign wbm_sel_o = cpu_bsel_i;
assign wbm_we_o = cpu_we_i;
assign wbm_cti_o = 0;
assign wbm_bte_o = 0;
assign wbm_dat_o = cpu_dat_i;
end // else: !if(BUS_IF_TYPE=="READ_B3_BURSTING")
endgenerate
endmodule // mor1kx_bus_if_wb
|
/*****************************************************************************
-------------------------------------------------------------------------------
-- Entity: mig_interface_model
-- File: mig_interface_model.v
-- Author: Fredrik Ringhage - Aeroflex Gaisler AB
--
-- This is a interface model for Xilinx Virtex-7 MIG used on eval board
-- VC707 and KC705.
--
-------------------------------------------------------------------------------
*****************************************************************************/
`timescale 1ps/1ps
module mig_interface_model
(
// user interface signals
input [27:0] app_addr,
input [2:0] app_cmd,
input app_en,
input [511:0] app_wdf_data,
input app_wdf_end,
input [63:0] app_wdf_mask,
input app_wdf_wren,
output wire [511:0] app_rd_data,
output wire app_rd_data_end,
output wire app_rd_data_valid,
output wire app_rdy,
output wire app_wdf_rdy,
output reg ui_clk,
output reg ui_clk_sync_rst,
output reg init_calib_complete,
input sys_rst
);
parameter AddressSize = 28 - 8;
//parameter AddressSize = 10;
//parameter AddressSize = 7;
parameter WordSize = 512;
parameter MEM_SIZE = (1<<AddressSize);
reg app_rd_data_end_r;
reg app_rd_data_valid_r;
reg app_rdy_r;
reg app_wdf_rdy_r;
reg app_en_r;
reg app_wdf_wren_r;
reg app_wdf_end_r;
reg [27:0] app_addr_r;
reg [27:0] app_addr_r1;
reg [27:0] app_addr_r2;
reg [27:0] app_addr_r3;
reg [27:0] app_addr_r4;
reg [511:0] mask;
reg [WordSize-1:0] Mem [0:MEM_SIZE];
integer k;
assign #100 app_rd_data_end = app_rd_data_end_r;
assign #100 app_rdy = app_rdy_r;
assign #100 app_wdf_rdy = app_wdf_rdy_r;
assign app_rd_data_valid = app_rd_data_valid_r;
assign #100 app_rd_data = Mem[app_addr_r >> 3];
// Clear memory
initial
begin
for (k = 0; k < MEM_SIZE ; k = k + 1)
begin
Mem[k] = 512'd0;
end
end
initial
begin
app_rd_data_valid_r = 1'b0;
app_rd_data_end_r = 1'b0;
app_rdy_r = 1'b1;
app_wdf_rdy_r = 1'b1;
init_calib_complete = 1'b0;
ui_clk_sync_rst = 1'b0;
ui_clk = 1'b0;
end
// Generate clocks
always
begin
forever begin
#5000;
ui_clk = ~ui_clk;
end
end
// Release reset and calibration
initial
begin
#10000;
$display("Reset release of simulation time is %d",$time);
@(posedge ui_clk) ui_clk_sync_rst = 1'b1;
#1000;
$display("Calibration release of simulation time is %d",$time);
@(posedge ui_clk) init_calib_complete = 1'b1;
end
// Write Process
always@(posedge app_wdf_wren)
begin
#100;
for (k = 0; k < 512 ; k = k + 1)
begin
mask[k] = ~ app_wdf_mask[k >> 3];
end
Mem[app_addr >> 3] = (app_wdf_data & mask) | (Mem[app_addr >> 3] & (~ mask) );
#10000;
if (app_wdf_wren) begin
#100;
for (k = 0; k < 512 ; k = k + 1)
begin
mask[k] = ~ app_wdf_mask[k >> 3];
end
Mem[app_addr >> 3] = (app_wdf_data & mask) | (Mem[app_addr >> 3] & (~ mask) );
end
#10000;
if (app_wdf_wren) begin
#100;
for (k = 0; k < 512 ; k = k + 1)
begin
mask[k] = ~ app_wdf_mask[k >> 3];
end
Mem[app_addr >> 3] = (app_wdf_data & mask) | (Mem[app_addr >> 3] & (~ mask) );
end
#10000;
if (app_wdf_wren) begin
#100;
for (k = 0; k < 512 ; k = k + 1)
begin
mask[k] = ~ app_wdf_mask[k >> 3];
end
Mem[app_addr >> 3] = (app_wdf_data & mask) | (Mem[app_addr >> 3] & (~ mask) );
end
end
// Read Process
always@(posedge app_en)
begin
#100;
if (MEM_SIZE < app_addr) begin
$display("Warning read/write access outside memory at %d",$time);
end
if (app_cmd == 3'd1) begin
app_addr_r1 = app_addr;
#10000;
app_addr_r2 = app_addr;
#10000;
app_addr_r3 = app_addr;
#10000;
app_addr_r4 = app_addr;
#40000;
app_addr_r = app_addr_r1;
#100;
app_rd_data_valid_r = 1'b1;
#10000;
app_addr_r = app_addr_r2;
#10000;
app_addr_r = app_addr_r3;
#10000;
app_addr_r = app_addr_r4;
#10000;
app_rd_data_valid_r = 1'b0;
#10000;
end
end
endmodule
|
/*
* regm - register memory
*
* A 32-bit register memory. Two registers can be read at once. The
* variables `read1` and `read2` specifiy which registers to read. The
* output is placed in `data1` and `data2`.
*
* If `regwrite` is high, the value in `wrdata` will be written to the
* register in `wrreg`.
*
* The register at address $zero is treated special, it ignores
* assignment and the value read is always zero.
*
* If the register being read is the same as that being written, the
* value being written will be available immediately without a one
* cycle delay.
*
*/
`ifndef _regm
`define _regm
`ifndef DEBUG_CPU_REG
`define DEBUG_CPU_REG 0
`endif
module regm(
input wire clk,
input wire rst,
input wire [4:0] read1, read2,
output wire [31:0] data1, data2,
input wire regwrite,
input wire [4:0] wrreg,
input wire [31:0] wrdata);
reg [31:0] mem [0:31]; // 32-bit memory with 32 entries
reg [31:0] _data1, _data2;
integer i;
initial begin
if (`DEBUG_CPU_REG) begin
$display(" $v0, $v1, $t0, $t1, $t2, $t3, $t4, $t5, $t6, $t7");
$monitor("%x, %x, %x, %x, %x, %x, %x, %x, %x, %x",
mem[2][31:0], /* $v0 */
mem[3][31:0], /* $v1 */
mem[8][31:0], /* $t0 */
mem[9][31:0], /* $t1 */
mem[10][31:0], /* $t2 */
mem[11][31:0], /* $t3 */
mem[12][31:0], /* $t4 */
mem[13][31:0], /* $t5 */
mem[14][31:0], /* $t6 */
mem[15][31:0], /* $t7 */
);
end
end
always @(*) begin
if (read1 == 5'd0)
_data1 = 32'd0;
else if ((read1 == wrreg) && regwrite)
_data1 = wrdata;
else
_data1 = mem[read1][31:0];
end
always @(*) begin
if (read2 == 5'd0)
_data2 = 32'd0;
else if ((read2 == wrreg) && regwrite)
_data2 = wrdata;
else
_data2 = mem[read2][31:0];
end
assign data1 = _data1;
assign data2 = _data2;
always @(posedge clk, negedge rst) begin
if (!rst) begin
for (i = 0; i < 32; i=i+1) begin
mem[i] <= 32'h0;
end
#1 mem[2] <= 1;
end
else if (regwrite && wrreg != 5'd0) begin
// write a non $zero register
mem[wrreg] <= wrdata;
end
end
endmodule
`endif
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_processing_system7_bfm.v
*
* Date : 2012-11
*
* Description : Processing_system7_bfm Top (zynq_bfm top)
*
*****************************************************************************/
module processing_system7_bfm_v2_0_processing_system7_bfm
(
CAN0_PHY_TX,
CAN0_PHY_RX,
CAN1_PHY_TX,
CAN1_PHY_RX,
ENET0_GMII_TX_EN,
ENET0_GMII_TX_ER,
ENET0_MDIO_MDC,
ENET0_MDIO_O,
ENET0_MDIO_T,
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
ENET0_GMII_TXD,
ENET0_GMII_COL,
ENET0_GMII_CRS,
ENET0_EXT_INTIN,
ENET0_GMII_RX_CLK,
ENET0_GMII_RX_DV,
ENET0_GMII_RX_ER,
ENET0_GMII_TX_CLK,
ENET0_MDIO_I,
ENET0_GMII_RXD,
ENET1_GMII_TX_EN,
ENET1_GMII_TX_ER,
ENET1_MDIO_MDC,
ENET1_MDIO_O,
ENET1_MDIO_T,
ENET1_PTP_DELAY_REQ_RX,
ENET1_PTP_DELAY_REQ_TX,
ENET1_PTP_PDELAY_REQ_RX,
ENET1_PTP_PDELAY_REQ_TX,
ENET1_PTP_PDELAY_RESP_RX,
ENET1_PTP_PDELAY_RESP_TX,
ENET1_PTP_SYNC_FRAME_RX,
ENET1_PTP_SYNC_FRAME_TX,
ENET1_SOF_RX,
ENET1_SOF_TX,
ENET1_GMII_TXD,
ENET1_GMII_COL,
ENET1_GMII_CRS,
ENET1_EXT_INTIN,
ENET1_GMII_RX_CLK,
ENET1_GMII_RX_DV,
ENET1_GMII_RX_ER,
ENET1_GMII_TX_CLK,
ENET1_MDIO_I,
ENET1_GMII_RXD,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
I2C1_SDA_I,
I2C1_SDA_O,
I2C1_SDA_T,
I2C1_SCL_I,
I2C1_SCL_O,
I2C1_SCL_T,
PJTAG_TCK,
PJTAG_TMS,
PJTAG_TD_I,
PJTAG_TD_T,
PJTAG_TD_O,
SDIO0_CLK,
SDIO0_CLK_FB,
SDIO0_CMD_O,
SDIO0_CMD_I,
SDIO0_CMD_T,
SDIO0_DATA_I,
SDIO0_DATA_O,
SDIO0_DATA_T,
SDIO0_LED,
SDIO0_CDN,
SDIO0_WP,
SDIO0_BUSPOW,
SDIO0_BUSVOLT,
SDIO1_CLK,
SDIO1_CLK_FB,
SDIO1_CMD_O,
SDIO1_CMD_I,
SDIO1_CMD_T,
SDIO1_DATA_I,
SDIO1_DATA_O,
SDIO1_DATA_T,
SDIO1_LED,
SDIO1_CDN,
SDIO1_WP,
SDIO1_BUSPOW,
SDIO1_BUSVOLT,
SPI0_SCLK_I,
SPI0_SCLK_O,
SPI0_SCLK_T,
SPI0_MOSI_I,
SPI0_MOSI_O,
SPI0_MOSI_T,
SPI0_MISO_I,
SPI0_MISO_O,
SPI0_MISO_T,
SPI0_SS_I,
SPI0_SS_O,
SPI0_SS1_O,
SPI0_SS2_O,
SPI0_SS_T,
SPI1_SCLK_I,
SPI1_SCLK_O,
SPI1_SCLK_T,
SPI1_MOSI_I,
SPI1_MOSI_O,
SPI1_MOSI_T,
SPI1_MISO_I,
SPI1_MISO_O,
SPI1_MISO_T,
SPI1_SS_I,
SPI1_SS_O,
SPI1_SS1_O,
SPI1_SS2_O,
SPI1_SS_T,
UART0_DTRN,
UART0_RTSN,
UART0_TX,
UART0_CTSN,
UART0_DCDN,
UART0_DSRN,
UART0_RIN,
UART0_RX,
UART1_DTRN,
UART1_RTSN,
UART1_TX,
UART1_CTSN,
UART1_DCDN,
UART1_DSRN,
UART1_RIN,
UART1_RX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
TTC1_WAVE0_OUT,
TTC1_WAVE1_OUT,
TTC1_WAVE2_OUT,
TTC1_CLK0_IN,
TTC1_CLK1_IN,
TTC1_CLK2_IN,
WDT_CLK_IN,
WDT_RST_OUT,
TRACE_CLK,
TRACE_CTL,
TRACE_DATA,
USB0_PORT_INDCTL,
USB1_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB1_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_VBUS_PWRFAULT,
SRAM_INTIN,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_GP0_ARREADY,
S_AXI_GP0_AWREADY,
S_AXI_GP0_BVALID,
S_AXI_GP0_RLAST,
S_AXI_GP0_RVALID,
S_AXI_GP0_WREADY,
S_AXI_GP0_BRESP,
S_AXI_GP0_RRESP,
S_AXI_GP0_RDATA,
S_AXI_GP0_BID,
S_AXI_GP0_RID,
S_AXI_GP0_ACLK,
S_AXI_GP0_ARVALID,
S_AXI_GP0_AWVALID,
S_AXI_GP0_BREADY,
S_AXI_GP0_RREADY,
S_AXI_GP0_WLAST,
S_AXI_GP0_WVALID,
S_AXI_GP0_ARBURST,
S_AXI_GP0_ARLOCK,
S_AXI_GP0_ARSIZE,
S_AXI_GP0_AWBURST,
S_AXI_GP0_AWLOCK,
S_AXI_GP0_AWSIZE,
S_AXI_GP0_ARPROT,
S_AXI_GP0_AWPROT,
S_AXI_GP0_ARADDR,
S_AXI_GP0_AWADDR,
S_AXI_GP0_WDATA,
S_AXI_GP0_ARCACHE,
S_AXI_GP0_ARLEN,
S_AXI_GP0_ARQOS,
S_AXI_GP0_AWCACHE,
S_AXI_GP0_AWLEN,
S_AXI_GP0_AWQOS,
S_AXI_GP0_WSTRB,
S_AXI_GP0_ARID,
S_AXI_GP0_AWID,
S_AXI_GP0_WID,
S_AXI_GP1_ARREADY,
S_AXI_GP1_AWREADY,
S_AXI_GP1_BVALID,
S_AXI_GP1_RLAST,
S_AXI_GP1_RVALID,
S_AXI_GP1_WREADY,
S_AXI_GP1_BRESP,
S_AXI_GP1_RRESP,
S_AXI_GP1_RDATA,
S_AXI_GP1_BID,
S_AXI_GP1_RID,
S_AXI_GP1_ACLK,
S_AXI_GP1_ARVALID,
S_AXI_GP1_AWVALID,
S_AXI_GP1_BREADY,
S_AXI_GP1_RREADY,
S_AXI_GP1_WLAST,
S_AXI_GP1_WVALID,
S_AXI_GP1_ARBURST,
S_AXI_GP1_ARLOCK,
S_AXI_GP1_ARSIZE,
S_AXI_GP1_AWBURST,
S_AXI_GP1_AWLOCK,
S_AXI_GP1_AWSIZE,
S_AXI_GP1_ARPROT,
S_AXI_GP1_AWPROT,
S_AXI_GP1_ARADDR,
S_AXI_GP1_AWADDR,
S_AXI_GP1_WDATA,
S_AXI_GP1_ARCACHE,
S_AXI_GP1_ARLEN,
S_AXI_GP1_ARQOS,
S_AXI_GP1_AWCACHE,
S_AXI_GP1_AWLEN,
S_AXI_GP1_AWQOS,
S_AXI_GP1_WSTRB,
S_AXI_GP1_ARID,
S_AXI_GP1_AWID,
S_AXI_GP1_WID,
S_AXI_ACP_AWREADY,
S_AXI_ACP_ARREADY,
S_AXI_ACP_BVALID,
S_AXI_ACP_RLAST,
S_AXI_ACP_RVALID,
S_AXI_ACP_WREADY,
S_AXI_ACP_BRESP,
S_AXI_ACP_RRESP,
S_AXI_ACP_BID,
S_AXI_ACP_RID,
S_AXI_ACP_RDATA,
S_AXI_ACP_ACLK,
S_AXI_ACP_ARVALID,
S_AXI_ACP_AWVALID,
S_AXI_ACP_BREADY,
S_AXI_ACP_RREADY,
S_AXI_ACP_WLAST,
S_AXI_ACP_WVALID,
S_AXI_ACP_ARID,
S_AXI_ACP_ARPROT,
S_AXI_ACP_AWID,
S_AXI_ACP_AWPROT,
S_AXI_ACP_WID,
S_AXI_ACP_ARADDR,
S_AXI_ACP_AWADDR,
S_AXI_ACP_ARCACHE,
S_AXI_ACP_ARLEN,
S_AXI_ACP_ARQOS,
S_AXI_ACP_AWCACHE,
S_AXI_ACP_AWLEN,
S_AXI_ACP_AWQOS,
S_AXI_ACP_ARBURST,
S_AXI_ACP_ARLOCK,
S_AXI_ACP_ARSIZE,
S_AXI_ACP_AWBURST,
S_AXI_ACP_AWLOCK,
S_AXI_ACP_AWSIZE,
S_AXI_ACP_ARUSER,
S_AXI_ACP_AWUSER,
S_AXI_ACP_WDATA,
S_AXI_ACP_WSTRB,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
S_AXI_HP2_ARREADY,
S_AXI_HP2_AWREADY,
S_AXI_HP2_BVALID,
S_AXI_HP2_RLAST,
S_AXI_HP2_RVALID,
S_AXI_HP2_WREADY,
S_AXI_HP2_BRESP,
S_AXI_HP2_RRESP,
S_AXI_HP2_BID,
S_AXI_HP2_RID,
S_AXI_HP2_RDATA,
S_AXI_HP2_RCOUNT,
S_AXI_HP2_WCOUNT,
S_AXI_HP2_RACOUNT,
S_AXI_HP2_WACOUNT,
S_AXI_HP2_ACLK,
S_AXI_HP2_ARVALID,
S_AXI_HP2_AWVALID,
S_AXI_HP2_BREADY,
S_AXI_HP2_RDISSUECAP1_EN,
S_AXI_HP2_RREADY,
S_AXI_HP2_WLAST,
S_AXI_HP2_WRISSUECAP1_EN,
S_AXI_HP2_WVALID,
S_AXI_HP2_ARBURST,
S_AXI_HP2_ARLOCK,
S_AXI_HP2_ARSIZE,
S_AXI_HP2_AWBURST,
S_AXI_HP2_AWLOCK,
S_AXI_HP2_AWSIZE,
S_AXI_HP2_ARPROT,
S_AXI_HP2_AWPROT,
S_AXI_HP2_ARADDR,
S_AXI_HP2_AWADDR,
S_AXI_HP2_ARCACHE,
S_AXI_HP2_ARLEN,
S_AXI_HP2_ARQOS,
S_AXI_HP2_AWCACHE,
S_AXI_HP2_AWLEN,
S_AXI_HP2_AWQOS,
S_AXI_HP2_ARID,
S_AXI_HP2_AWID,
S_AXI_HP2_WID,
S_AXI_HP2_WDATA,
S_AXI_HP2_WSTRB,
S_AXI_HP3_ARREADY,
S_AXI_HP3_AWREADY,
S_AXI_HP3_BVALID,
S_AXI_HP3_RLAST,
S_AXI_HP3_RVALID,
S_AXI_HP3_WREADY,
S_AXI_HP3_BRESP,
S_AXI_HP3_RRESP,
S_AXI_HP3_BID,
S_AXI_HP3_RID,
S_AXI_HP3_RDATA,
S_AXI_HP3_RCOUNT,
S_AXI_HP3_WCOUNT,
S_AXI_HP3_RACOUNT,
S_AXI_HP3_WACOUNT,
S_AXI_HP3_ACLK,
S_AXI_HP3_ARVALID,
S_AXI_HP3_AWVALID,
S_AXI_HP3_BREADY,
S_AXI_HP3_RDISSUECAP1_EN,
S_AXI_HP3_RREADY,
S_AXI_HP3_WLAST,
S_AXI_HP3_WRISSUECAP1_EN,
S_AXI_HP3_WVALID,
S_AXI_HP3_ARBURST,
S_AXI_HP3_ARLOCK,
S_AXI_HP3_ARSIZE,
S_AXI_HP3_AWBURST,
S_AXI_HP3_AWLOCK,
S_AXI_HP3_AWSIZE,
S_AXI_HP3_ARPROT,
S_AXI_HP3_AWPROT,
S_AXI_HP3_ARADDR,
S_AXI_HP3_AWADDR,
S_AXI_HP3_ARCACHE,
S_AXI_HP3_ARLEN,
S_AXI_HP3_ARQOS,
S_AXI_HP3_AWCACHE,
S_AXI_HP3_AWLEN,
S_AXI_HP3_AWQOS,
S_AXI_HP3_ARID,
S_AXI_HP3_AWID,
S_AXI_HP3_WID,
S_AXI_HP3_WDATA,
S_AXI_HP3_WSTRB,
DMA0_DATYPE,
DMA0_DAVALID,
DMA0_DRREADY,
DMA0_ACLK,
DMA0_DAREADY,
DMA0_DRLAST,
DMA0_DRVALID,
DMA0_DRTYPE,
DMA1_DATYPE,
DMA1_DAVALID,
DMA1_DRREADY,
DMA1_ACLK,
DMA1_DAREADY,
DMA1_DRLAST,
DMA1_DRVALID,
DMA1_DRTYPE,
DMA2_DATYPE,
DMA2_DAVALID,
DMA2_DRREADY,
DMA2_ACLK,
DMA2_DAREADY,
DMA2_DRLAST,
DMA2_DRVALID,
DMA3_DRVALID,
DMA3_DATYPE,
DMA3_DAVALID,
DMA3_DRREADY,
DMA3_ACLK,
DMA3_DAREADY,
DMA3_DRLAST,
DMA2_DRTYPE,
DMA3_DRTYPE,
FTMD_TRACEIN_DATA,
FTMD_TRACEIN_VALID,
FTMD_TRACEIN_CLK,
FTMD_TRACEIN_ATID,
FTMT_F2P_TRIG,
FTMT_F2P_TRIGACK,
FTMT_F2P_DEBUG,
FTMT_P2F_TRIGACK,
FTMT_P2F_TRIG,
FTMT_P2F_DEBUG,
FCLK_CLK3,
FCLK_CLK2,
FCLK_CLK1,
FCLK_CLK0,
FCLK_CLKTRIG3_N,
FCLK_CLKTRIG2_N,
FCLK_CLKTRIG1_N,
FCLK_CLKTRIG0_N,
FCLK_RESET3_N,
FCLK_RESET2_N,
FCLK_RESET1_N,
FCLK_RESET0_N,
FPGA_IDLE_N,
DDR_ARB,
IRQ_F2P,
Core0_nFIQ,
Core0_nIRQ,
Core1_nFIQ,
Core1_nIRQ,
EVENT_EVENTO,
EVENT_STANDBYWFE,
EVENT_STANDBYWFI,
EVENT_EVENTI,
MIO,
DDR_Clk,
DDR_Clk_n,
DDR_CKE,
DDR_CS_n,
DDR_RAS_n,
DDR_CAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_ODT,
DDR_DRSTB,
DDR_DQ,
DDR_DM,
DDR_DQS,
DDR_DQS_n,
DDR_VRN,
DDR_VRP,
PS_SRSTB,
PS_CLK,
PS_PORB,
IRQ_P2F_DMAC_ABORT,
IRQ_P2F_DMAC0,
IRQ_P2F_DMAC1,
IRQ_P2F_DMAC2,
IRQ_P2F_DMAC3,
IRQ_P2F_DMAC4,
IRQ_P2F_DMAC5,
IRQ_P2F_DMAC6,
IRQ_P2F_DMAC7,
IRQ_P2F_SMC,
IRQ_P2F_QSPI,
IRQ_P2F_CTI,
IRQ_P2F_GPIO,
IRQ_P2F_USB0,
IRQ_P2F_ENET0,
IRQ_P2F_ENET_WAKE0,
IRQ_P2F_SDIO0,
IRQ_P2F_I2C0,
IRQ_P2F_SPI0,
IRQ_P2F_UART0,
IRQ_P2F_CAN0,
IRQ_P2F_USB1,
IRQ_P2F_ENET1,
IRQ_P2F_ENET_WAKE1,
IRQ_P2F_SDIO1,
IRQ_P2F_I2C1,
IRQ_P2F_SPI1,
IRQ_P2F_UART1,
IRQ_P2F_CAN1
);
/* parameters for gen_clk */
parameter C_FCLK_CLK0_FREQ = 50;
parameter C_FCLK_CLK1_FREQ = 50;
parameter C_FCLK_CLK3_FREQ = 50;
parameter C_FCLK_CLK2_FREQ = 50;
parameter C_HIGH_OCM_EN = 0;
/* parameters for HP ports */
parameter C_USE_S_AXI_HP0 = 0;
parameter C_USE_S_AXI_HP1 = 0;
parameter C_USE_S_AXI_HP2 = 0;
parameter C_USE_S_AXI_HP3 = 0;
parameter C_S_AXI_HP0_DATA_WIDTH = 32;
parameter C_S_AXI_HP1_DATA_WIDTH = 32;
parameter C_S_AXI_HP2_DATA_WIDTH = 32;
parameter C_S_AXI_HP3_DATA_WIDTH = 32;
parameter C_M_AXI_GP0_THREAD_ID_WIDTH = 12;
parameter C_M_AXI_GP1_THREAD_ID_WIDTH = 12;
parameter C_M_AXI_GP0_ENABLE_STATIC_REMAP = 0;
parameter C_M_AXI_GP1_ENABLE_STATIC_REMAP = 0;
/* Do we need these
parameter C_S_AXI_HP0_ENABLE_HIGHOCM = 0;
parameter C_S_AXI_HP1_ENABLE_HIGHOCM = 0;
parameter C_S_AXI_HP2_ENABLE_HIGHOCM = 0;
parameter C_S_AXI_HP3_ENABLE_HIGHOCM = 0; */
parameter C_S_AXI_HP0_BASEADDR = 32'h0000_0000;
parameter C_S_AXI_HP1_BASEADDR = 32'h0000_0000;
parameter C_S_AXI_HP2_BASEADDR = 32'h0000_0000;
parameter C_S_AXI_HP3_BASEADDR = 32'h0000_0000;
parameter C_S_AXI_HP0_HIGHADDR = 32'hFFFF_FFFF;
parameter C_S_AXI_HP1_HIGHADDR = 32'hFFFF_FFFF;
parameter C_S_AXI_HP2_HIGHADDR = 32'hFFFF_FFFF;
parameter C_S_AXI_HP3_HIGHADDR = 32'hFFFF_FFFF;
/* parameters for GP and ACP ports */
parameter C_USE_M_AXI_GP0 = 0;
parameter C_USE_M_AXI_GP1 = 0;
parameter C_USE_S_AXI_GP0 = 1;
parameter C_USE_S_AXI_GP1 = 1;
/* Do we need this?
parameter C_M_AXI_GP0_ENABLE_HIGHOCM = 0;
parameter C_M_AXI_GP1_ENABLE_HIGHOCM = 0;
parameter C_S_AXI_GP0_ENABLE_HIGHOCM = 0;
parameter C_S_AXI_GP1_ENABLE_HIGHOCM = 0;
parameter C_S_AXI_ACP_ENABLE_HIGHOCM = 0;*/
parameter C_S_AXI_GP0_BASEADDR = 32'h0000_0000;
parameter C_S_AXI_GP1_BASEADDR = 32'h0000_0000;
parameter C_S_AXI_GP0_HIGHADDR = 32'hFFFF_FFFF;
parameter C_S_AXI_GP1_HIGHADDR = 32'hFFFF_FFFF;
parameter C_USE_S_AXI_ACP = 1;
parameter C_S_AXI_ACP_BASEADDR = 32'h0000_0000;
parameter C_S_AXI_ACP_HIGHADDR = 32'hFFFF_FFFF;
`include "processing_system7_bfm_v2_0_local_params.v"
output CAN0_PHY_TX;
input CAN0_PHY_RX;
output CAN1_PHY_TX;
input CAN1_PHY_RX;
output ENET0_GMII_TX_EN;
output ENET0_GMII_TX_ER;
output ENET0_MDIO_MDC;
output ENET0_MDIO_O;
output ENET0_MDIO_T;
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
output [7:0] ENET0_GMII_TXD;
input ENET0_GMII_COL;
input ENET0_GMII_CRS;
input ENET0_EXT_INTIN;
input ENET0_GMII_RX_CLK;
input ENET0_GMII_RX_DV;
input ENET0_GMII_RX_ER;
input ENET0_GMII_TX_CLK;
input ENET0_MDIO_I;
input [7:0] ENET0_GMII_RXD;
output ENET1_GMII_TX_EN;
output ENET1_GMII_TX_ER;
output ENET1_MDIO_MDC;
output ENET1_MDIO_O;
output ENET1_MDIO_T;
output ENET1_PTP_DELAY_REQ_RX;
output ENET1_PTP_DELAY_REQ_TX;
output ENET1_PTP_PDELAY_REQ_RX;
output ENET1_PTP_PDELAY_REQ_TX;
output ENET1_PTP_PDELAY_RESP_RX;
output ENET1_PTP_PDELAY_RESP_TX;
output ENET1_PTP_SYNC_FRAME_RX;
output ENET1_PTP_SYNC_FRAME_TX;
output ENET1_SOF_RX;
output ENET1_SOF_TX;
output [7:0] ENET1_GMII_TXD;
input ENET1_GMII_COL;
input ENET1_GMII_CRS;
input ENET1_EXT_INTIN;
input ENET1_GMII_RX_CLK;
input ENET1_GMII_RX_DV;
input ENET1_GMII_RX_ER;
input ENET1_GMII_TX_CLK;
input ENET1_MDIO_I;
input [7:0] ENET1_GMII_RXD;
input [63:0] GPIO_I;
output [63:0] GPIO_O;
output [63:0] GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input I2C1_SDA_I;
output I2C1_SDA_O;
output I2C1_SDA_T;
input I2C1_SCL_I;
output I2C1_SCL_O;
output I2C1_SCL_T;
input PJTAG_TCK;
input PJTAG_TMS;
input PJTAG_TD_I;
output PJTAG_TD_T;
output PJTAG_TD_O;
output SDIO0_CLK;
input SDIO0_CLK_FB;
output SDIO0_CMD_O;
input SDIO0_CMD_I;
output SDIO0_CMD_T;
input [3:0] SDIO0_DATA_I;
output [3:0] SDIO0_DATA_O;
output [3:0] SDIO0_DATA_T;
output SDIO0_LED;
input SDIO0_CDN;
input SDIO0_WP;
output SDIO0_BUSPOW;
output [2:0] SDIO0_BUSVOLT;
output SDIO1_CLK;
input SDIO1_CLK_FB;
output SDIO1_CMD_O;
input SDIO1_CMD_I;
output SDIO1_CMD_T;
input [3:0] SDIO1_DATA_I;
output [3:0] SDIO1_DATA_O;
output [3:0] SDIO1_DATA_T;
output SDIO1_LED;
input SDIO1_CDN;
input SDIO1_WP;
output SDIO1_BUSPOW;
output [2:0] SDIO1_BUSVOLT;
input SPI0_SCLK_I;
output SPI0_SCLK_O;
output SPI0_SCLK_T;
input SPI0_MOSI_I;
output SPI0_MOSI_O;
output SPI0_MOSI_T;
input SPI0_MISO_I;
output SPI0_MISO_O;
output SPI0_MISO_T;
input SPI0_SS_I;
output SPI0_SS_O;
output SPI0_SS1_O;
output SPI0_SS2_O;
output SPI0_SS_T;
input SPI1_SCLK_I;
output SPI1_SCLK_O;
output SPI1_SCLK_T;
input SPI1_MOSI_I;
output SPI1_MOSI_O;
output SPI1_MOSI_T;
input SPI1_MISO_I;
output SPI1_MISO_O;
output SPI1_MISO_T;
input SPI1_SS_I;
output SPI1_SS_O;
output SPI1_SS1_O;
output SPI1_SS2_O;
output SPI1_SS_T;
output UART0_DTRN;
output UART0_RTSN;
output UART0_TX;
input UART0_CTSN;
input UART0_DCDN;
input UART0_DSRN;
input UART0_RIN;
input UART0_RX;
output UART1_DTRN;
output UART1_RTSN;
output UART1_TX;
input UART1_CTSN;
input UART1_DCDN;
input UART1_DSRN;
input UART1_RIN;
input UART1_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
input TTC0_CLK0_IN;
input TTC0_CLK1_IN;
input TTC0_CLK2_IN;
output TTC1_WAVE0_OUT;
output TTC1_WAVE1_OUT;
output TTC1_WAVE2_OUT;
input TTC1_CLK0_IN;
input TTC1_CLK1_IN;
input TTC1_CLK2_IN;
input WDT_CLK_IN;
output WDT_RST_OUT;
input TRACE_CLK;
output TRACE_CTL;
output [31:0] TRACE_DATA;
output [1:0] USB0_PORT_INDCTL;
output [1:0] USB1_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
output USB1_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
input USB1_VBUS_PWRFAULT;
input SRAM_INTIN;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_ARID;
output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_AWID;
output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_WID;
output [1:0] M_AXI_GP0_ARBURST;
output [1:0] M_AXI_GP0_ARLOCK;
output [2:0] M_AXI_GP0_ARSIZE;
output [1:0] M_AXI_GP0_AWBURST;
output [1:0] M_AXI_GP0_AWLOCK;
output [2:0] M_AXI_GP0_AWSIZE;
output [2:0] M_AXI_GP0_ARPROT;
output [2:0] M_AXI_GP0_AWPROT;
output [31:0] M_AXI_GP0_ARADDR;
output [31:0] M_AXI_GP0_AWADDR;
output [31:0] M_AXI_GP0_WDATA;
output [3:0] M_AXI_GP0_ARCACHE;
output [3:0] M_AXI_GP0_ARLEN;
output [3:0] M_AXI_GP0_ARQOS;
output [3:0] M_AXI_GP0_AWCACHE;
output [3:0] M_AXI_GP0_AWLEN;
output [3:0] M_AXI_GP0_AWQOS;
output [3:0] M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_BID;
input [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_RID;
input [1:0] M_AXI_GP0_BRESP;
input [1:0] M_AXI_GP0_RRESP;
input [31:0] M_AXI_GP0_RDATA;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_ARID;
output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_AWID;
output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_WID;
output [1:0] M_AXI_GP1_ARBURST;
output [1:0] M_AXI_GP1_ARLOCK;
output [2:0] M_AXI_GP1_ARSIZE;
output [1:0] M_AXI_GP1_AWBURST;
output [1:0] M_AXI_GP1_AWLOCK;
output [2:0] M_AXI_GP1_AWSIZE;
output [2:0] M_AXI_GP1_ARPROT;
output [2:0] M_AXI_GP1_AWPROT;
output [31:0] M_AXI_GP1_ARADDR;
output [31:0] M_AXI_GP1_AWADDR;
output [31:0] M_AXI_GP1_WDATA;
output [3:0] M_AXI_GP1_ARCACHE;
output [3:0] M_AXI_GP1_ARLEN;
output [3:0] M_AXI_GP1_ARQOS;
output [3:0] M_AXI_GP1_AWCACHE;
output [3:0] M_AXI_GP1_AWLEN;
output [3:0] M_AXI_GP1_AWQOS;
output [3:0] M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_BID;
input [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_RID;
input [1:0] M_AXI_GP1_BRESP;
input [1:0] M_AXI_GP1_RRESP;
input [31:0] M_AXI_GP1_RDATA;
output S_AXI_GP0_ARREADY;
output S_AXI_GP0_AWREADY;
output S_AXI_GP0_BVALID;
output S_AXI_GP0_RLAST;
output S_AXI_GP0_RVALID;
output S_AXI_GP0_WREADY;
output [1:0] S_AXI_GP0_BRESP;
output [1:0] S_AXI_GP0_RRESP;
output [31:0] S_AXI_GP0_RDATA;
output [5:0] S_AXI_GP0_BID;
output [5:0] S_AXI_GP0_RID;
input S_AXI_GP0_ACLK;
input S_AXI_GP0_ARVALID;
input S_AXI_GP0_AWVALID;
input S_AXI_GP0_BREADY;
input S_AXI_GP0_RREADY;
input S_AXI_GP0_WLAST;
input S_AXI_GP0_WVALID;
input [1:0] S_AXI_GP0_ARBURST;
input [1:0] S_AXI_GP0_ARLOCK;
input [2:0] S_AXI_GP0_ARSIZE;
input [1:0] S_AXI_GP0_AWBURST;
input [1:0] S_AXI_GP0_AWLOCK;
input [2:0] S_AXI_GP0_AWSIZE;
input [2:0] S_AXI_GP0_ARPROT;
input [2:0] S_AXI_GP0_AWPROT;
input [31:0] S_AXI_GP0_ARADDR;
input [31:0] S_AXI_GP0_AWADDR;
input [31:0] S_AXI_GP0_WDATA;
input [3:0] S_AXI_GP0_ARCACHE;
input [3:0] S_AXI_GP0_ARLEN;
input [3:0] S_AXI_GP0_ARQOS;
input [3:0] S_AXI_GP0_AWCACHE;
input [3:0] S_AXI_GP0_AWLEN;
input [3:0] S_AXI_GP0_AWQOS;
input [3:0] S_AXI_GP0_WSTRB;
input [5:0] S_AXI_GP0_ARID;
input [5:0] S_AXI_GP0_AWID;
input [5:0] S_AXI_GP0_WID;
output S_AXI_GP1_ARREADY;
output S_AXI_GP1_AWREADY;
output S_AXI_GP1_BVALID;
output S_AXI_GP1_RLAST;
output S_AXI_GP1_RVALID;
output S_AXI_GP1_WREADY;
output [1:0] S_AXI_GP1_BRESP;
output [1:0] S_AXI_GP1_RRESP;
output [31:0] S_AXI_GP1_RDATA;
output [5:0] S_AXI_GP1_BID;
output [5:0] S_AXI_GP1_RID;
input S_AXI_GP1_ACLK;
input S_AXI_GP1_ARVALID;
input S_AXI_GP1_AWVALID;
input S_AXI_GP1_BREADY;
input S_AXI_GP1_RREADY;
input S_AXI_GP1_WLAST;
input S_AXI_GP1_WVALID;
input [1:0] S_AXI_GP1_ARBURST;
input [1:0] S_AXI_GP1_ARLOCK;
input [2:0] S_AXI_GP1_ARSIZE;
input [1:0] S_AXI_GP1_AWBURST;
input [1:0] S_AXI_GP1_AWLOCK;
input [2:0] S_AXI_GP1_AWSIZE;
input [2:0] S_AXI_GP1_ARPROT;
input [2:0] S_AXI_GP1_AWPROT;
input [31:0] S_AXI_GP1_ARADDR;
input [31:0] S_AXI_GP1_AWADDR;
input [31:0] S_AXI_GP1_WDATA;
input [3:0] S_AXI_GP1_ARCACHE;
input [3:0] S_AXI_GP1_ARLEN;
input [3:0] S_AXI_GP1_ARQOS;
input [3:0] S_AXI_GP1_AWCACHE;
input [3:0] S_AXI_GP1_AWLEN;
input [3:0] S_AXI_GP1_AWQOS;
input [3:0] S_AXI_GP1_WSTRB;
input [5:0] S_AXI_GP1_ARID;
input [5:0] S_AXI_GP1_AWID;
input [5:0] S_AXI_GP1_WID;
output S_AXI_ACP_AWREADY;
output S_AXI_ACP_ARREADY;
output S_AXI_ACP_BVALID;
output S_AXI_ACP_RLAST;
output S_AXI_ACP_RVALID;
output S_AXI_ACP_WREADY;
output [1:0] S_AXI_ACP_BRESP;
output [1:0] S_AXI_ACP_RRESP;
output [2:0] S_AXI_ACP_BID;
output [2:0] S_AXI_ACP_RID;
output [63:0] S_AXI_ACP_RDATA;
input S_AXI_ACP_ACLK;
input S_AXI_ACP_ARVALID;
input S_AXI_ACP_AWVALID;
input S_AXI_ACP_BREADY;
input S_AXI_ACP_RREADY;
input S_AXI_ACP_WLAST;
input S_AXI_ACP_WVALID;
input [2:0] S_AXI_ACP_ARID;
input [2:0] S_AXI_ACP_ARPROT;
input [2:0] S_AXI_ACP_AWID;
input [2:0] S_AXI_ACP_AWPROT;
input [2:0] S_AXI_ACP_WID;
input [31:0] S_AXI_ACP_ARADDR;
input [31:0] S_AXI_ACP_AWADDR;
input [3:0] S_AXI_ACP_ARCACHE;
input [3:0] S_AXI_ACP_ARLEN;
input [3:0] S_AXI_ACP_ARQOS;
input [3:0] S_AXI_ACP_AWCACHE;
input [3:0] S_AXI_ACP_AWLEN;
input [3:0] S_AXI_ACP_AWQOS;
input [1:0] S_AXI_ACP_ARBURST;
input [1:0] S_AXI_ACP_ARLOCK;
input [2:0] S_AXI_ACP_ARSIZE;
input [1:0] S_AXI_ACP_AWBURST;
input [1:0] S_AXI_ACP_AWLOCK;
input [2:0] S_AXI_ACP_AWSIZE;
input [4:0] S_AXI_ACP_ARUSER;
input [4:0] S_AXI_ACP_AWUSER;
input [63:0] S_AXI_ACP_WDATA;
input [7:0] S_AXI_ACP_WSTRB;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1:0] S_AXI_HP0_BRESP;
output [1:0] S_AXI_HP0_RRESP;
output [5:0] S_AXI_HP0_BID;
output [5:0] S_AXI_HP0_RID;
output [C_S_AXI_HP0_DATA_WIDTH-1:0] S_AXI_HP0_RDATA;
output [7:0] S_AXI_HP0_RCOUNT;
output [7:0] S_AXI_HP0_WCOUNT;
output [2:0] S_AXI_HP0_RACOUNT;
output [5:0] S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1:0] S_AXI_HP0_ARBURST;
input [1:0] S_AXI_HP0_ARLOCK;
input [2:0] S_AXI_HP0_ARSIZE;
input [1:0] S_AXI_HP0_AWBURST;
input [1:0] S_AXI_HP0_AWLOCK;
input [2:0] S_AXI_HP0_AWSIZE;
input [2:0] S_AXI_HP0_ARPROT;
input [2:0] S_AXI_HP0_AWPROT;
input [31:0] S_AXI_HP0_ARADDR;
input [31:0] S_AXI_HP0_AWADDR;
input [3:0] S_AXI_HP0_ARCACHE;
input [3:0] S_AXI_HP0_ARLEN;
input [3:0] S_AXI_HP0_ARQOS;
input [3:0] S_AXI_HP0_AWCACHE;
input [3:0] S_AXI_HP0_AWLEN;
input [3:0] S_AXI_HP0_AWQOS;
input [5:0] S_AXI_HP0_ARID;
input [5:0] S_AXI_HP0_AWID;
input [5:0] S_AXI_HP0_WID;
input [C_S_AXI_HP0_DATA_WIDTH-1:0] S_AXI_HP0_WDATA;
input [C_S_AXI_HP0_DATA_WIDTH/8-1:0] S_AXI_HP0_WSTRB;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1:0] S_AXI_HP1_BRESP;
output [1:0] S_AXI_HP1_RRESP;
output [5:0] S_AXI_HP1_BID;
output [5:0] S_AXI_HP1_RID;
output [C_S_AXI_HP1_DATA_WIDTH-1:0] S_AXI_HP1_RDATA;
output [7:0] S_AXI_HP1_RCOUNT;
output [7:0] S_AXI_HP1_WCOUNT;
output [2:0] S_AXI_HP1_RACOUNT;
output [5:0] S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1:0] S_AXI_HP1_ARBURST;
input [1:0] S_AXI_HP1_ARLOCK;
input [2:0] S_AXI_HP1_ARSIZE;
input [1:0] S_AXI_HP1_AWBURST;
input [1:0] S_AXI_HP1_AWLOCK;
input [2:0] S_AXI_HP1_AWSIZE;
input [2:0] S_AXI_HP1_ARPROT;
input [2:0] S_AXI_HP1_AWPROT;
input [31:0] S_AXI_HP1_ARADDR;
input [31:0] S_AXI_HP1_AWADDR;
input [3:0] S_AXI_HP1_ARCACHE;
input [3:0] S_AXI_HP1_ARLEN;
input [3:0] S_AXI_HP1_ARQOS;
input [3:0] S_AXI_HP1_AWCACHE;
input [3:0] S_AXI_HP1_AWLEN;
input [3:0] S_AXI_HP1_AWQOS;
input [5:0] S_AXI_HP1_ARID;
input [5:0] S_AXI_HP1_AWID;
input [5:0] S_AXI_HP1_WID;
input [C_S_AXI_HP1_DATA_WIDTH-1:0] S_AXI_HP1_WDATA;
input [C_S_AXI_HP1_DATA_WIDTH/8-1:0] S_AXI_HP1_WSTRB;
output S_AXI_HP2_ARREADY;
output S_AXI_HP2_AWREADY;
output S_AXI_HP2_BVALID;
output S_AXI_HP2_RLAST;
output S_AXI_HP2_RVALID;
output S_AXI_HP2_WREADY;
output [1:0] S_AXI_HP2_BRESP;
output [1:0] S_AXI_HP2_RRESP;
output [5:0] S_AXI_HP2_BID;
output [5:0] S_AXI_HP2_RID;
output [C_S_AXI_HP2_DATA_WIDTH-1:0] S_AXI_HP2_RDATA;
output [7:0] S_AXI_HP2_RCOUNT;
output [7:0] S_AXI_HP2_WCOUNT;
output [2:0] S_AXI_HP2_RACOUNT;
output [5:0] S_AXI_HP2_WACOUNT;
input S_AXI_HP2_ACLK;
input S_AXI_HP2_ARVALID;
input S_AXI_HP2_AWVALID;
input S_AXI_HP2_BREADY;
input S_AXI_HP2_RDISSUECAP1_EN;
input S_AXI_HP2_RREADY;
input S_AXI_HP2_WLAST;
input S_AXI_HP2_WRISSUECAP1_EN;
input S_AXI_HP2_WVALID;
input [1:0] S_AXI_HP2_ARBURST;
input [1:0] S_AXI_HP2_ARLOCK;
input [2:0] S_AXI_HP2_ARSIZE;
input [1:0] S_AXI_HP2_AWBURST;
input [1:0] S_AXI_HP2_AWLOCK;
input [2:0] S_AXI_HP2_AWSIZE;
input [2:0] S_AXI_HP2_ARPROT;
input [2:0] S_AXI_HP2_AWPROT;
input [31:0] S_AXI_HP2_ARADDR;
input [31:0] S_AXI_HP2_AWADDR;
input [3:0] S_AXI_HP2_ARCACHE;
input [3:0] S_AXI_HP2_ARLEN;
input [3:0] S_AXI_HP2_ARQOS;
input [3:0] S_AXI_HP2_AWCACHE;
input [3:0] S_AXI_HP2_AWLEN;
input [3:0] S_AXI_HP2_AWQOS;
input [5:0] S_AXI_HP2_ARID;
input [5:0] S_AXI_HP2_AWID;
input [5:0] S_AXI_HP2_WID;
input [C_S_AXI_HP2_DATA_WIDTH-1:0] S_AXI_HP2_WDATA;
input [C_S_AXI_HP2_DATA_WIDTH/8-1:0] S_AXI_HP2_WSTRB;
output S_AXI_HP3_ARREADY;
output S_AXI_HP3_AWREADY;
output S_AXI_HP3_BVALID;
output S_AXI_HP3_RLAST;
output S_AXI_HP3_RVALID;
output S_AXI_HP3_WREADY;
output [1:0] S_AXI_HP3_BRESP;
output [1:0] S_AXI_HP3_RRESP;
output [5:0] S_AXI_HP3_BID;
output [5:0] S_AXI_HP3_RID;
output [C_S_AXI_HP3_DATA_WIDTH-1:0] S_AXI_HP3_RDATA;
output [7:0] S_AXI_HP3_RCOUNT;
output [7:0] S_AXI_HP3_WCOUNT;
output [2:0] S_AXI_HP3_RACOUNT;
output [5:0] S_AXI_HP3_WACOUNT;
input S_AXI_HP3_ACLK;
input S_AXI_HP3_ARVALID;
input S_AXI_HP3_AWVALID;
input S_AXI_HP3_BREADY;
input S_AXI_HP3_RDISSUECAP1_EN;
input S_AXI_HP3_RREADY;
input S_AXI_HP3_WLAST;
input S_AXI_HP3_WRISSUECAP1_EN;
input S_AXI_HP3_WVALID;
input [1:0] S_AXI_HP3_ARBURST;
input [1:0] S_AXI_HP3_ARLOCK;
input [2:0] S_AXI_HP3_ARSIZE;
input [1:0] S_AXI_HP3_AWBURST;
input [1:0] S_AXI_HP3_AWLOCK;
input [2:0] S_AXI_HP3_AWSIZE;
input [2:0] S_AXI_HP3_ARPROT;
input [2:0] S_AXI_HP3_AWPROT;
input [31:0] S_AXI_HP3_ARADDR;
input [31:0] S_AXI_HP3_AWADDR;
input [3:0] S_AXI_HP3_ARCACHE;
input [3:0] S_AXI_HP3_ARLEN;
input [3:0] S_AXI_HP3_ARQOS;
input [3:0] S_AXI_HP3_AWCACHE;
input [3:0] S_AXI_HP3_AWLEN;
input [3:0] S_AXI_HP3_AWQOS;
input [5:0] S_AXI_HP3_ARID;
input [5:0] S_AXI_HP3_AWID;
input [5:0] S_AXI_HP3_WID;
input [C_S_AXI_HP3_DATA_WIDTH-1:0] S_AXI_HP3_WDATA;
input [C_S_AXI_HP3_DATA_WIDTH/8-1:0] S_AXI_HP3_WSTRB;
output [1:0] DMA0_DATYPE;
output DMA0_DAVALID;
output DMA0_DRREADY;
input DMA0_ACLK;
input DMA0_DAREADY;
input DMA0_DRLAST;
input DMA0_DRVALID;
input [1:0] DMA0_DRTYPE;
output [1:0] DMA1_DATYPE;
output DMA1_DAVALID;
output DMA1_DRREADY;
input DMA1_ACLK;
input DMA1_DAREADY;
input DMA1_DRLAST;
input DMA1_DRVALID;
input [1:0] DMA1_DRTYPE;
output [1:0] DMA2_DATYPE;
output DMA2_DAVALID;
output DMA2_DRREADY;
input DMA2_ACLK;
input DMA2_DAREADY;
input DMA2_DRLAST;
input DMA2_DRVALID;
input DMA3_DRVALID;
output [1:0] DMA3_DATYPE;
output DMA3_DAVALID;
output DMA3_DRREADY;
input DMA3_ACLK;
input DMA3_DAREADY;
input DMA3_DRLAST;
input [1:0] DMA2_DRTYPE;
input [1:0] DMA3_DRTYPE;
input [31:0] FTMD_TRACEIN_DATA;
input FTMD_TRACEIN_VALID;
input FTMD_TRACEIN_CLK;
input [3:0] FTMD_TRACEIN_ATID;
input [3:0] FTMT_F2P_TRIG;
output [3:0] FTMT_F2P_TRIGACK;
input [31:0] FTMT_F2P_DEBUG;
input [3:0] FTMT_P2F_TRIGACK;
output [3:0] FTMT_P2F_TRIG;
output [31:0] FTMT_P2F_DEBUG;
output FCLK_CLK3;
output FCLK_CLK2;
output FCLK_CLK1;
output FCLK_CLK0;
input FCLK_CLKTRIG3_N;
input FCLK_CLKTRIG2_N;
input FCLK_CLKTRIG1_N;
input FCLK_CLKTRIG0_N;
output FCLK_RESET3_N;
output FCLK_RESET2_N;
output FCLK_RESET1_N;
output FCLK_RESET0_N;
input FPGA_IDLE_N;
input [3:0] DDR_ARB;
input [irq_width-1:0] IRQ_F2P;
input Core0_nFIQ;
input Core0_nIRQ;
input Core1_nFIQ;
input Core1_nIRQ;
output EVENT_EVENTO;
output [1:0] EVENT_STANDBYWFE;
output [1:0] EVENT_STANDBYWFI;
input EVENT_EVENTI;
inout [53:0] MIO;
inout DDR_Clk;
inout DDR_Clk_n;
inout DDR_CKE;
inout DDR_CS_n;
inout DDR_RAS_n;
inout DDR_CAS_n;
output DDR_WEB;
inout [2:0] DDR_BankAddr;
inout [14:0] DDR_Addr;
inout DDR_ODT;
inout DDR_DRSTB;
inout [31:0] DDR_DQ;
inout [3:0] DDR_DM;
inout [3:0] DDR_DQS;
inout [3:0] DDR_DQS_n;
inout DDR_VRN;
inout DDR_VRP;
/* Reset Input & Clock Input */
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
output IRQ_P2F_DMAC_ABORT;
output IRQ_P2F_DMAC0;
output IRQ_P2F_DMAC1;
output IRQ_P2F_DMAC2;
output IRQ_P2F_DMAC3;
output IRQ_P2F_DMAC4;
output IRQ_P2F_DMAC5;
output IRQ_P2F_DMAC6;
output IRQ_P2F_DMAC7;
output IRQ_P2F_SMC;
output IRQ_P2F_QSPI;
output IRQ_P2F_CTI;
output IRQ_P2F_GPIO;
output IRQ_P2F_USB0;
output IRQ_P2F_ENET0;
output IRQ_P2F_ENET_WAKE0;
output IRQ_P2F_SDIO0;
output IRQ_P2F_I2C0;
output IRQ_P2F_SPI0;
output IRQ_P2F_UART0;
output IRQ_P2F_CAN0;
output IRQ_P2F_USB1;
output IRQ_P2F_ENET1;
output IRQ_P2F_ENET_WAKE1;
output IRQ_P2F_SDIO1;
output IRQ_P2F_I2C1;
output IRQ_P2F_SPI1;
output IRQ_P2F_UART1;
output IRQ_P2F_CAN1;
/* Internal wires/nets used for connectivity */
wire net_rstn;
wire net_sw_clk;
wire net_ocm_clk;
wire net_arbiter_clk;
wire net_axi_mgp0_rstn;
wire net_axi_mgp1_rstn;
wire net_axi_gp0_rstn;
wire net_axi_gp1_rstn;
wire net_axi_hp0_rstn;
wire net_axi_hp1_rstn;
wire net_axi_hp2_rstn;
wire net_axi_hp3_rstn;
wire net_axi_acp_rstn;
wire [4:0] net_axi_acp_awuser;
wire [4:0] net_axi_acp_aruser;
/* Dummy */
assign net_axi_acp_awuser = S_AXI_ACP_AWUSER;
assign net_axi_acp_aruser = S_AXI_ACP_ARUSER;
/* Global variables */
reg DEBUG_INFO = 1;
reg STOP_ON_ERROR = 1;
/* local variable acting as semaphore for wait_mem_update and wait_reg_update task */
reg mem_update_key = 1;
reg reg_update_key_0 = 1;
reg reg_update_key_1 = 1;
/* assignments and semantic checks for unused ports */
`include "processing_system7_bfm_v2_0_unused_ports.v"
/* include api definition */
`include "processing_system7_bfm_v2_0_apis.v"
/* Reset Generator */
processing_system7_bfm_v2_0_gen_reset gen_rst(.por_rst_n(PS_PORB),
.sys_rst_n(PS_SRSTB),
.rst_out_n(net_rstn),
.m_axi_gp0_clk(M_AXI_GP0_ACLK),
.m_axi_gp1_clk(M_AXI_GP1_ACLK),
.s_axi_gp0_clk(S_AXI_GP0_ACLK),
.s_axi_gp1_clk(S_AXI_GP1_ACLK),
.s_axi_hp0_clk(S_AXI_HP0_ACLK),
.s_axi_hp1_clk(S_AXI_HP1_ACLK),
.s_axi_hp2_clk(S_AXI_HP2_ACLK),
.s_axi_hp3_clk(S_AXI_HP3_ACLK),
.s_axi_acp_clk(S_AXI_ACP_ACLK),
.m_axi_gp0_rstn(net_axi_mgp0_rstn),
.m_axi_gp1_rstn(net_axi_mgp1_rstn),
.s_axi_gp0_rstn(net_axi_gp0_rstn),
.s_axi_gp1_rstn(net_axi_gp1_rstn),
.s_axi_hp0_rstn(net_axi_hp0_rstn),
.s_axi_hp1_rstn(net_axi_hp1_rstn),
.s_axi_hp2_rstn(net_axi_hp2_rstn),
.s_axi_hp3_rstn(net_axi_hp3_rstn),
.s_axi_acp_rstn(net_axi_acp_rstn),
.fclk_reset3_n(FCLK_RESET3_N),
.fclk_reset2_n(FCLK_RESET2_N),
.fclk_reset1_n(FCLK_RESET1_N),
.fclk_reset0_n(FCLK_RESET0_N),
.fpga_acp_reset_n(), ////S_AXI_ACP_ARESETN), (These are removed from Zynq IP)
.fpga_gp_m0_reset_n(), ////M_AXI_GP0_ARESETN),
.fpga_gp_m1_reset_n(), ////M_AXI_GP1_ARESETN),
.fpga_gp_s0_reset_n(), ////S_AXI_GP0_ARESETN),
.fpga_gp_s1_reset_n(), ////S_AXI_GP1_ARESETN),
.fpga_hp_s0_reset_n(), ////S_AXI_HP0_ARESETN),
.fpga_hp_s1_reset_n(), ////S_AXI_HP1_ARESETN),
.fpga_hp_s2_reset_n(), ////S_AXI_HP2_ARESETN),
.fpga_hp_s3_reset_n() ////S_AXI_HP3_ARESETN)
);
/* Clock Generator */
processing_system7_bfm_v2_0_gen_clock #(C_FCLK_CLK3_FREQ, C_FCLK_CLK2_FREQ, C_FCLK_CLK1_FREQ, C_FCLK_CLK0_FREQ)
gen_clk(.ps_clk(PS_CLK),
.sw_clk(net_sw_clk),
.fclk_clk3(FCLK_CLK3),
.fclk_clk2(FCLK_CLK2),
.fclk_clk1(FCLK_CLK1),
.fclk_clk0(FCLK_CLK0)
);
wire net_wr_ack_ocm_gp0, net_wr_ack_ddr_gp0, net_wr_ack_ocm_gp1, net_wr_ack_ddr_gp1;
wire net_wr_dv_ocm_gp0, net_wr_dv_ddr_gp0, net_wr_dv_ocm_gp1, net_wr_dv_ddr_gp1;
wire [max_burst_bits-1:0] net_wr_data_gp0, net_wr_data_gp1;
wire [addr_width-1:0] net_wr_addr_gp0, net_wr_addr_gp1;
wire [max_burst_bytes_width:0] net_wr_bytes_gp0, net_wr_bytes_gp1;
wire [axi_qos_width-1:0] net_wr_qos_gp0, net_wr_qos_gp1;
wire net_rd_req_ddr_gp0, net_rd_req_ddr_gp1;
wire net_rd_req_ocm_gp0, net_rd_req_ocm_gp1;
wire net_rd_req_reg_gp0, net_rd_req_reg_gp1;
wire [addr_width-1:0] net_rd_addr_gp0, net_rd_addr_gp1;
wire [max_burst_bytes_width:0] net_rd_bytes_gp0, net_rd_bytes_gp1;
wire [max_burst_bits-1:0] net_rd_data_ddr_gp0, net_rd_data_ddr_gp1;
wire [max_burst_bits-1:0] net_rd_data_ocm_gp0, net_rd_data_ocm_gp1;
wire [max_burst_bits-1:0] net_rd_data_reg_gp0, net_rd_data_reg_gp1;
wire net_rd_dv_ddr_gp0, net_rd_dv_ddr_gp1;
wire net_rd_dv_ocm_gp0, net_rd_dv_ocm_gp1;
wire net_rd_dv_reg_gp0, net_rd_dv_reg_gp1;
wire [axi_qos_width-1:0] net_rd_qos_gp0, net_rd_qos_gp1;
wire net_wr_ack_ddr_hp0, net_wr_ack_ddr_hp1, net_wr_ack_ddr_hp2, net_wr_ack_ddr_hp3;
wire net_wr_ack_ocm_hp0, net_wr_ack_ocm_hp1, net_wr_ack_ocm_hp2, net_wr_ack_ocm_hp3;
wire net_wr_dv_ddr_hp0, net_wr_dv_ddr_hp1, net_wr_dv_ddr_hp2, net_wr_dv_ddr_hp3;
wire net_wr_dv_ocm_hp0, net_wr_dv_ocm_hp1, net_wr_dv_ocm_hp2, net_wr_dv_ocm_hp3;
wire [max_burst_bits-1:0] net_wr_data_hp0, net_wr_data_hp1, net_wr_data_hp2, net_wr_data_hp3;
wire [addr_width-1:0] net_wr_addr_hp0, net_wr_addr_hp1, net_wr_addr_hp2, net_wr_addr_hp3;
wire [max_burst_bytes_width:0] net_wr_bytes_hp0, net_wr_bytes_hp1, net_wr_bytes_hp2, net_wr_bytes_hp3;
wire [axi_qos_width-1:0] net_wr_qos_hp0, net_wr_qos_hp1, net_wr_qos_hp2, net_wr_qos_hp3;
wire net_rd_req_ddr_hp0, net_rd_req_ddr_hp1, net_rd_req_ddr_hp2, net_rd_req_ddr_hp3;
wire net_rd_req_ocm_hp0, net_rd_req_ocm_hp1, net_rd_req_ocm_hp2, net_rd_req_ocm_hp3;
wire [addr_width-1:0] net_rd_addr_hp0, net_rd_addr_hp1, net_rd_addr_hp2, net_rd_addr_hp3;
wire [max_burst_bytes_width:0] net_rd_bytes_hp0, net_rd_bytes_hp1, net_rd_bytes_hp2, net_rd_bytes_hp3;
wire [max_burst_bits-1:0] net_rd_data_ddr_hp0, net_rd_data_ddr_hp1, net_rd_data_ddr_hp2, net_rd_data_ddr_hp3;
wire [max_burst_bits-1:0] net_rd_data_ocm_hp0, net_rd_data_ocm_hp1, net_rd_data_ocm_hp2, net_rd_data_ocm_hp3;
wire net_rd_dv_ddr_hp0, net_rd_dv_ddr_hp1, net_rd_dv_ddr_hp2, net_rd_dv_ddr_hp3;
wire net_rd_dv_ocm_hp0, net_rd_dv_ocm_hp1, net_rd_dv_ocm_hp2, net_rd_dv_ocm_hp3;
wire [axi_qos_width-1:0] net_rd_qos_hp0, net_rd_qos_hp1, net_rd_qos_hp2, net_rd_qos_hp3;
wire net_wr_ack_ddr_acp,net_wr_ack_ocm_acp;
wire net_wr_dv_ddr_acp,net_wr_dv_ocm_acp;
wire [max_burst_bits-1:0] net_wr_data_acp;
wire [addr_width-1:0] net_wr_addr_acp;
wire [max_burst_bytes_width:0] net_wr_bytes_acp;
wire [axi_qos_width-1:0] net_wr_qos_acp;
wire net_rd_req_ddr_acp, net_rd_req_ocm_acp;
wire [addr_width-1:0] net_rd_addr_acp;
wire [max_burst_bytes_width:0] net_rd_bytes_acp;
wire [max_burst_bits-1:0] net_rd_data_ddr_acp;
wire [max_burst_bits-1:0] net_rd_data_ocm_acp;
wire net_rd_dv_ddr_acp,net_rd_dv_ocm_acp;
wire [axi_qos_width-1:0] net_rd_qos_acp;
wire ocm_wr_ack_port0;
wire ocm_wr_dv_port0;
wire ocm_rd_req_port0;
wire ocm_rd_dv_port0;
wire [addr_width-1:0] ocm_wr_addr_port0;
wire [max_burst_bits-1:0] ocm_wr_data_port0;
wire [max_burst_bytes_width:0] ocm_wr_bytes_port0;
wire [addr_width-1:0] ocm_rd_addr_port0;
wire [max_burst_bits-1:0] ocm_rd_data_port0;
wire [max_burst_bytes_width:0] ocm_rd_bytes_port0;
wire [axi_qos_width-1:0] ocm_wr_qos_port0;
wire [axi_qos_width-1:0] ocm_rd_qos_port0;
wire ocm_wr_ack_port1;
wire ocm_wr_dv_port1;
wire ocm_rd_req_port1;
wire ocm_rd_dv_port1;
wire [addr_width-1:0] ocm_wr_addr_port1;
wire [max_burst_bits-1:0] ocm_wr_data_port1;
wire [max_burst_bytes_width:0] ocm_wr_bytes_port1;
wire [addr_width-1:0] ocm_rd_addr_port1;
wire [max_burst_bits-1:0] ocm_rd_data_port1;
wire [max_burst_bytes_width:0] ocm_rd_bytes_port1;
wire [axi_qos_width-1:0] ocm_wr_qos_port1;
wire [axi_qos_width-1:0] ocm_rd_qos_port1;
wire ddr_wr_ack_port0;
wire ddr_wr_dv_port0;
wire ddr_rd_req_port0;
wire ddr_rd_dv_port0;
wire[addr_width-1:0] ddr_wr_addr_port0;
wire[max_burst_bits-1:0] ddr_wr_data_port0;
wire[max_burst_bytes_width:0] ddr_wr_bytes_port0;
wire[addr_width-1:0] ddr_rd_addr_port0;
wire[max_burst_bits-1:0] ddr_rd_data_port0;
wire[max_burst_bytes_width:0] ddr_rd_bytes_port0;
wire [axi_qos_width-1:0] ddr_wr_qos_port0;
wire [axi_qos_width-1:0] ddr_rd_qos_port0;
wire ddr_wr_ack_port1;
wire ddr_wr_dv_port1;
wire ddr_rd_req_port1;
wire ddr_rd_dv_port1;
wire[addr_width-1:0] ddr_wr_addr_port1;
wire[max_burst_bits-1:0] ddr_wr_data_port1;
wire[max_burst_bytes_width:0] ddr_wr_bytes_port1;
wire[addr_width-1:0] ddr_rd_addr_port1;
wire[max_burst_bits-1:0] ddr_rd_data_port1;
wire[max_burst_bytes_width:0] ddr_rd_bytes_port1;
wire[axi_qos_width-1:0] ddr_wr_qos_port1;
wire[axi_qos_width-1:0] ddr_rd_qos_port1;
wire ddr_wr_ack_port2;
wire ddr_wr_dv_port2;
wire ddr_rd_req_port2;
wire ddr_rd_dv_port2;
wire[addr_width-1:0] ddr_wr_addr_port2;
wire[max_burst_bits-1:0] ddr_wr_data_port2;
wire[max_burst_bytes_width:0] ddr_wr_bytes_port2;
wire[addr_width-1:0] ddr_rd_addr_port2;
wire[max_burst_bits-1:0] ddr_rd_data_port2;
wire[max_burst_bytes_width:0] ddr_rd_bytes_port2;
wire[axi_qos_width-1:0] ddr_wr_qos_port2;
wire[axi_qos_width-1:0] ddr_rd_qos_port2;
wire ddr_wr_ack_port3;
wire ddr_wr_dv_port3;
wire ddr_rd_req_port3;
wire ddr_rd_dv_port3;
wire[addr_width-1:0] ddr_wr_addr_port3;
wire[max_burst_bits-1:0] ddr_wr_data_port3;
wire[max_burst_bytes_width:0] ddr_wr_bytes_port3;
wire[addr_width-1:0] ddr_rd_addr_port3;
wire[max_burst_bits-1:0] ddr_rd_data_port3;
wire[max_burst_bytes_width:0] ddr_rd_bytes_port3;
wire[axi_qos_width-1:0] ddr_wr_qos_port3;
wire[axi_qos_width-1:0] ddr_rd_qos_port3;
wire reg_rd_req_port0;
wire reg_rd_dv_port0;
wire[addr_width-1:0] reg_rd_addr_port0;
wire[max_burst_bits-1:0] reg_rd_data_port0;
wire[max_burst_bytes_width:0] reg_rd_bytes_port0;
wire [axi_qos_width-1:0] reg_rd_qos_port0;
wire reg_rd_req_port1;
wire reg_rd_dv_port1;
wire[addr_width-1:0] reg_rd_addr_port1;
wire[max_burst_bits-1:0] reg_rd_data_port1;
wire[max_burst_bytes_width:0] reg_rd_bytes_port1;
wire [axi_qos_width-1:0] reg_rd_qos_port1;
wire [11:0] M_AXI_GP0_AWID_FULL;
wire [11:0] M_AXI_GP0_WID_FULL;
wire [11:0] M_AXI_GP0_ARID_FULL;
wire [11:0] M_AXI_GP0_BID_FULL;
wire [11:0] M_AXI_GP0_RID_FULL;
wire [11:0] M_AXI_GP1_AWID_FULL;
wire [11:0] M_AXI_GP1_WID_FULL;
wire [11:0] M_AXI_GP1_ARID_FULL;
wire [11:0] M_AXI_GP1_BID_FULL;
wire [11:0] M_AXI_GP1_RID_FULL;
function [5:0] compress_id;
input [11:0] id;
begin
compress_id = id[5:0];
end
endfunction
function [11:0] uncompress_id;
input [5:0] id;
begin
uncompress_id = {6'b110000, id[5:0]};
end
endfunction
assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL;
assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;
assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID;
assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID;
assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL;
assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;
assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID;
assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID;
processing_system7_bfm_v2_0_interconnect_model icm (
.rstn(net_rstn),
.sw_clk(net_sw_clk),
.w_qos_gp0(net_wr_qos_gp0),
.w_qos_gp1(net_wr_qos_gp1),
.w_qos_hp0(net_wr_qos_hp0),
.w_qos_hp1(net_wr_qos_hp1),
.w_qos_hp2(net_wr_qos_hp2),
.w_qos_hp3(net_wr_qos_hp3),
.r_qos_gp0(net_rd_qos_gp0),
.r_qos_gp1(net_rd_qos_gp1),
.r_qos_hp0(net_rd_qos_hp0),
.r_qos_hp1(net_rd_qos_hp1),
.r_qos_hp2(net_rd_qos_hp2),
.r_qos_hp3(net_rd_qos_hp3),
/* GP Slave ports access */
.wr_ack_ddr_gp0(net_wr_ack_ddr_gp0),
.wr_ack_ocm_gp0(net_wr_ack_ocm_gp0),
.wr_data_gp0(net_wr_data_gp0),
.wr_addr_gp0(net_wr_addr_gp0),
.wr_bytes_gp0(net_wr_bytes_gp0),
.wr_dv_ddr_gp0(net_wr_dv_ddr_gp0),
.wr_dv_ocm_gp0(net_wr_dv_ocm_gp0),
.rd_req_ddr_gp0(net_rd_req_ddr_gp0),
.rd_req_ocm_gp0(net_rd_req_ocm_gp0),
.rd_req_reg_gp0(net_rd_req_reg_gp0),
.rd_addr_gp0(net_rd_addr_gp0),
.rd_bytes_gp0(net_rd_bytes_gp0),
.rd_data_ddr_gp0(net_rd_data_ddr_gp0),
.rd_data_ocm_gp0(net_rd_data_ocm_gp0),
.rd_data_reg_gp0(net_rd_data_reg_gp0),
.rd_dv_ddr_gp0(net_rd_dv_ddr_gp0),
.rd_dv_ocm_gp0(net_rd_dv_ocm_gp0),
.rd_dv_reg_gp0(net_rd_dv_reg_gp0),
.wr_ack_ddr_gp1(net_wr_ack_ddr_gp1),
.wr_ack_ocm_gp1(net_wr_ack_ocm_gp1),
.wr_data_gp1(net_wr_data_gp1),
.wr_addr_gp1(net_wr_addr_gp1),
.wr_bytes_gp1(net_wr_bytes_gp1),
.wr_dv_ddr_gp1(net_wr_dv_ddr_gp1),
.wr_dv_ocm_gp1(net_wr_dv_ocm_gp1),
.rd_req_ddr_gp1(net_rd_req_ddr_gp1),
.rd_req_ocm_gp1(net_rd_req_ocm_gp1),
.rd_req_reg_gp1(net_rd_req_reg_gp1),
.rd_addr_gp1(net_rd_addr_gp1),
.rd_bytes_gp1(net_rd_bytes_gp1),
.rd_data_ddr_gp1(net_rd_data_ddr_gp1),
.rd_data_ocm_gp1(net_rd_data_ocm_gp1),
.rd_data_reg_gp1(net_rd_data_reg_gp1),
.rd_dv_ddr_gp1(net_rd_dv_ddr_gp1),
.rd_dv_ocm_gp1(net_rd_dv_ocm_gp1),
.rd_dv_reg_gp1(net_rd_dv_reg_gp1),
/* HP Slave ports access */
.wr_ack_ddr_hp0(net_wr_ack_ddr_hp0),
.wr_ack_ocm_hp0(net_wr_ack_ocm_hp0),
.wr_data_hp0(net_wr_data_hp0),
.wr_addr_hp0(net_wr_addr_hp0),
.wr_bytes_hp0(net_wr_bytes_hp0),
.wr_dv_ddr_hp0(net_wr_dv_ddr_hp0),
.wr_dv_ocm_hp0(net_wr_dv_ocm_hp0),
.rd_req_ddr_hp0(net_rd_req_ddr_hp0),
.rd_req_ocm_hp0(net_rd_req_ocm_hp0),
.rd_addr_hp0(net_rd_addr_hp0),
.rd_bytes_hp0(net_rd_bytes_hp0),
.rd_data_ddr_hp0(net_rd_data_ddr_hp0),
.rd_data_ocm_hp0(net_rd_data_ocm_hp0),
.rd_dv_ddr_hp0(net_rd_dv_ddr_hp0),
.rd_dv_ocm_hp0(net_rd_dv_ocm_hp0),
.wr_ack_ddr_hp1(net_wr_ack_ddr_hp1),
.wr_ack_ocm_hp1(net_wr_ack_ocm_hp1),
.wr_data_hp1(net_wr_data_hp1),
.wr_addr_hp1(net_wr_addr_hp1),
.wr_bytes_hp1(net_wr_bytes_hp1),
.wr_dv_ddr_hp1(net_wr_dv_ddr_hp1),
.wr_dv_ocm_hp1(net_wr_dv_ocm_hp1),
.rd_req_ddr_hp1(net_rd_req_ddr_hp1),
.rd_req_ocm_hp1(net_rd_req_ocm_hp1),
.rd_addr_hp1(net_rd_addr_hp1),
.rd_bytes_hp1(net_rd_bytes_hp1),
.rd_data_ddr_hp1(net_rd_data_ddr_hp1),
.rd_data_ocm_hp1(net_rd_data_ocm_hp1),
.rd_dv_ocm_hp1(net_rd_dv_ocm_hp1),
.rd_dv_ddr_hp1(net_rd_dv_ddr_hp1),
.wr_ack_ddr_hp2(net_wr_ack_ddr_hp2),
.wr_ack_ocm_hp2(net_wr_ack_ocm_hp2),
.wr_data_hp2(net_wr_data_hp2),
.wr_addr_hp2(net_wr_addr_hp2),
.wr_bytes_hp2(net_wr_bytes_hp2),
.wr_dv_ocm_hp2(net_wr_dv_ocm_hp2),
.wr_dv_ddr_hp2(net_wr_dv_ddr_hp2),
.rd_req_ddr_hp2(net_rd_req_ddr_hp2),
.rd_req_ocm_hp2(net_rd_req_ocm_hp2),
.rd_addr_hp2(net_rd_addr_hp2),
.rd_bytes_hp2(net_rd_bytes_hp2),
.rd_data_ddr_hp2(net_rd_data_ddr_hp2),
.rd_data_ocm_hp2(net_rd_data_ocm_hp2),
.rd_dv_ddr_hp2(net_rd_dv_ddr_hp2),
.rd_dv_ocm_hp2(net_rd_dv_ocm_hp2),
.wr_ack_ocm_hp3(net_wr_ack_ocm_hp3),
.wr_ack_ddr_hp3(net_wr_ack_ddr_hp3),
.wr_data_hp3(net_wr_data_hp3),
.wr_addr_hp3(net_wr_addr_hp3),
.wr_bytes_hp3(net_wr_bytes_hp3),
.wr_dv_ddr_hp3(net_wr_dv_ddr_hp3),
.wr_dv_ocm_hp3(net_wr_dv_ocm_hp3),
.rd_req_ddr_hp3(net_rd_req_ddr_hp3),
.rd_req_ocm_hp3(net_rd_req_ocm_hp3),
.rd_addr_hp3(net_rd_addr_hp3),
.rd_bytes_hp3(net_rd_bytes_hp3),
.rd_data_ddr_hp3(net_rd_data_ddr_hp3),
.rd_data_ocm_hp3(net_rd_data_ocm_hp3),
.rd_dv_ddr_hp3(net_rd_dv_ddr_hp3),
.rd_dv_ocm_hp3(net_rd_dv_ocm_hp3),
/* Goes to port 1 of DDR */
.ddr_wr_ack_port1(ddr_wr_ack_port1),
.ddr_wr_dv_port1(ddr_wr_dv_port1),
.ddr_rd_req_port1(ddr_rd_req_port1),
.ddr_rd_dv_port1 (ddr_rd_dv_port1),
.ddr_wr_addr_port1(ddr_wr_addr_port1),
.ddr_wr_data_port1(ddr_wr_data_port1),
.ddr_wr_bytes_port1(ddr_wr_bytes_port1),
.ddr_rd_addr_port1(ddr_rd_addr_port1),
.ddr_rd_data_port1(ddr_rd_data_port1),
.ddr_rd_bytes_port1(ddr_rd_bytes_port1),
.ddr_wr_qos_port1(ddr_wr_qos_port1),
.ddr_rd_qos_port1(ddr_rd_qos_port1),
/* Goes to port2 of DDR */
.ddr_wr_ack_port2 (ddr_wr_ack_port2),
.ddr_wr_dv_port2 (ddr_wr_dv_port2),
.ddr_rd_req_port2 (ddr_rd_req_port2),
.ddr_rd_dv_port2 (ddr_rd_dv_port2),
.ddr_wr_addr_port2(ddr_wr_addr_port2),
.ddr_wr_data_port2(ddr_wr_data_port2),
.ddr_wr_bytes_port2(ddr_wr_bytes_port2),
.ddr_rd_addr_port2(ddr_rd_addr_port2),
.ddr_rd_data_port2(ddr_rd_data_port2),
.ddr_rd_bytes_port2(ddr_rd_bytes_port2),
.ddr_wr_qos_port2 (ddr_wr_qos_port2),
.ddr_rd_qos_port2 (ddr_rd_qos_port2),
/* Goes to port3 of DDR */
.ddr_wr_ack_port3 (ddr_wr_ack_port3),
.ddr_wr_dv_port3 (ddr_wr_dv_port3),
.ddr_rd_req_port3 (ddr_rd_req_port3),
.ddr_rd_dv_port3 (ddr_rd_dv_port3),
.ddr_wr_addr_port3(ddr_wr_addr_port3),
.ddr_wr_data_port3(ddr_wr_data_port3),
.ddr_wr_bytes_port3(ddr_wr_bytes_port3),
.ddr_rd_addr_port3(ddr_rd_addr_port3),
.ddr_rd_data_port3(ddr_rd_data_port3),
.ddr_rd_bytes_port3(ddr_rd_bytes_port3),
.ddr_wr_qos_port3 (ddr_wr_qos_port3),
.ddr_rd_qos_port3 (ddr_rd_qos_port3),
/* Goes to port 0 of OCM */
.ocm_wr_ack_port1 (ocm_wr_ack_port1),
.ocm_wr_dv_port1 (ocm_wr_dv_port1),
.ocm_rd_req_port1 (ocm_rd_req_port1),
.ocm_rd_dv_port1 (ocm_rd_dv_port1),
.ocm_wr_addr_port1(ocm_wr_addr_port1),
.ocm_wr_data_port1(ocm_wr_data_port1),
.ocm_wr_bytes_port1(ocm_wr_bytes_port1),
.ocm_rd_addr_port1(ocm_rd_addr_port1),
.ocm_rd_data_port1(ocm_rd_data_port1),
.ocm_rd_bytes_port1(ocm_rd_bytes_port1),
.ocm_wr_qos_port1(ocm_wr_qos_port1),
.ocm_rd_qos_port1(ocm_rd_qos_port1),
/* Goes to port 0 of REG */
.reg_rd_qos_port1 (reg_rd_qos_port1) ,
.reg_rd_req_port1 (reg_rd_req_port1),
.reg_rd_dv_port1 (reg_rd_dv_port1),
.reg_rd_addr_port1(reg_rd_addr_port1),
.reg_rd_data_port1(reg_rd_data_port1),
.reg_rd_bytes_port1(reg_rd_bytes_port1)
);
processing_system7_bfm_v2_0_ddrc ddrc (
.rstn(net_rstn),
.sw_clk(net_sw_clk),
/* Goes to port 0 of DDR */
.ddr_wr_ack_port0 (ddr_wr_ack_port0),
.ddr_wr_dv_port0 (ddr_wr_dv_port0),
.ddr_rd_req_port0 (ddr_rd_req_port0),
.ddr_rd_dv_port0 (ddr_rd_dv_port0),
.ddr_wr_addr_port0(net_wr_addr_acp),
.ddr_wr_data_port0(net_wr_data_acp),
.ddr_wr_bytes_port0(net_wr_bytes_acp),
.ddr_rd_addr_port0(net_rd_addr_acp),
.ddr_rd_bytes_port0(net_rd_bytes_acp),
.ddr_rd_data_port0(ddr_rd_data_port0),
.ddr_wr_qos_port0 (net_wr_qos_acp),
.ddr_rd_qos_port0 (net_rd_qos_acp),
/* Goes to port 1 of DDR */
.ddr_wr_ack_port1 (ddr_wr_ack_port1),
.ddr_wr_dv_port1 (ddr_wr_dv_port1),
.ddr_rd_req_port1 (ddr_rd_req_port1),
.ddr_rd_dv_port1 (ddr_rd_dv_port1),
.ddr_wr_addr_port1(ddr_wr_addr_port1),
.ddr_wr_data_port1(ddr_wr_data_port1),
.ddr_wr_bytes_port1(ddr_wr_bytes_port1),
.ddr_rd_addr_port1(ddr_rd_addr_port1),
.ddr_rd_data_port1(ddr_rd_data_port1),
.ddr_rd_bytes_port1(ddr_rd_bytes_port1),
.ddr_wr_qos_port1 (ddr_wr_qos_port1),
.ddr_rd_qos_port1 (ddr_rd_qos_port1),
/* Goes to port2 of DDR */
.ddr_wr_ack_port2 (ddr_wr_ack_port2),
.ddr_wr_dv_port2 (ddr_wr_dv_port2),
.ddr_rd_req_port2 (ddr_rd_req_port2),
.ddr_rd_dv_port2 (ddr_rd_dv_port2),
.ddr_wr_addr_port2(ddr_wr_addr_port2),
.ddr_wr_data_port2(ddr_wr_data_port2),
.ddr_wr_bytes_port2(ddr_wr_bytes_port2),
.ddr_rd_addr_port2(ddr_rd_addr_port2),
.ddr_rd_data_port2(ddr_rd_data_port2),
.ddr_rd_bytes_port2(ddr_rd_bytes_port2),
.ddr_wr_qos_port2 (ddr_wr_qos_port2),
.ddr_rd_qos_port2 (ddr_rd_qos_port2),
/* Goes to port3 of DDR */
.ddr_wr_ack_port3 (ddr_wr_ack_port3),
.ddr_wr_dv_port3 (ddr_wr_dv_port3),
.ddr_rd_req_port3 (ddr_rd_req_port3),
.ddr_rd_dv_port3 (ddr_rd_dv_port3),
.ddr_wr_addr_port3(ddr_wr_addr_port3),
.ddr_wr_data_port3(ddr_wr_data_port3),
.ddr_wr_bytes_port3(ddr_wr_bytes_port3),
.ddr_rd_addr_port3(ddr_rd_addr_port3),
.ddr_rd_data_port3(ddr_rd_data_port3),
.ddr_rd_bytes_port3(ddr_rd_bytes_port3),
.ddr_wr_qos_port3 (ddr_wr_qos_port3),
.ddr_rd_qos_port3 (ddr_rd_qos_port3)
);
processing_system7_bfm_v2_0_ocmc ocmc (
.rstn(net_rstn),
.sw_clk(net_sw_clk),
/* Goes to port 0 of OCM */
.ocm_wr_ack_port0 (ocm_wr_ack_port0),
.ocm_wr_dv_port0 (ocm_wr_dv_port0),
.ocm_rd_req_port0 (ocm_rd_req_port0),
.ocm_rd_dv_port0 (ocm_rd_dv_port0),
.ocm_wr_addr_port0(net_wr_addr_acp),
.ocm_wr_data_port0(net_wr_data_acp),
.ocm_wr_bytes_port0(net_wr_bytes_acp),
.ocm_rd_addr_port0(net_rd_addr_acp),
.ocm_rd_bytes_port0(net_rd_bytes_acp),
.ocm_rd_data_port0(ocm_rd_data_port0),
.ocm_wr_qos_port0 (net_wr_qos_acp),
.ocm_rd_qos_port0 (net_rd_qos_acp),
/* Goes to port 1 of OCM */
.ocm_wr_ack_port1 (ocm_wr_ack_port1),
.ocm_wr_dv_port1 (ocm_wr_dv_port1),
.ocm_rd_req_port1 (ocm_rd_req_port1),
.ocm_rd_dv_port1 (ocm_rd_dv_port1),
.ocm_wr_addr_port1(ocm_wr_addr_port1),
.ocm_wr_data_port1(ocm_wr_data_port1),
.ocm_wr_bytes_port1(ocm_wr_bytes_port1),
.ocm_rd_addr_port1(ocm_rd_addr_port1),
.ocm_rd_data_port1(ocm_rd_data_port1),
.ocm_rd_bytes_port1(ocm_rd_bytes_port1),
.ocm_wr_qos_port1(ocm_wr_qos_port1),
.ocm_rd_qos_port1(ocm_rd_qos_port1)
);
processing_system7_bfm_v2_0_regc regc (
.rstn(net_rstn),
.sw_clk(net_sw_clk),
/* Goes to port 0 of REG */
.reg_rd_req_port0 (reg_rd_req_port0),
.reg_rd_dv_port0 (reg_rd_dv_port0),
.reg_rd_addr_port0(net_rd_addr_acp),
.reg_rd_bytes_port0(net_rd_bytes_acp),
.reg_rd_data_port0(reg_rd_data_port0),
.reg_rd_qos_port0 (net_rd_qos_acp),
/* Goes to port 1 of REG */
.reg_rd_req_port1 (reg_rd_req_port1),
.reg_rd_dv_port1 (reg_rd_dv_port1),
.reg_rd_addr_port1(reg_rd_addr_port1),
.reg_rd_data_port1(reg_rd_data_port1),
.reg_rd_bytes_port1(reg_rd_bytes_port1),
.reg_rd_qos_port1(reg_rd_qos_port1)
);
/* include axi_gp port instantiations */
`include "processing_system7_bfm_v2_0_axi_gp.v"
/* include axi_hp port instantiations */
`include "processing_system7_bfm_v2_0_axi_hp.v"
/* include axi_acp port instantiations */
`include "processing_system7_bfm_v2_0_axi_acp.v"
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKINVLP_4_V
`define SKY130_FD_SC_HDLL__CLKINVLP_4_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Verilog wrapper for clkinvlp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__clkinvlp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkinvlp_4 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__clkinvlp base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkinvlp_4 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__clkinvlp base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKINVLP_4_V
|
/***********************************************************
-- (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). A Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
//
//
// Owner: Gary Martin
// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/mc_phy.v#5 $
// $Author: gary $
// $DateTime: 2010/05/11 18:05:17 $
// $Change: 490882 $
// Description:
// This verilog file is a parameterizable wrapper instantiating
// up to 5 memory banks of 4-lane phy primitives. There
// There are always 2 control banks leaving 18 lanes for data.
//
// History:
// Date Engineer Description
// 04/01/2010 G. Martin Initial Checkin.
//
////////////////////////////////////////////////////////////
***********************************************************/
`timescale 1ps/1ps
module mig_7series_v2_3_ddr_mc_phy
#(
// five fields, one per possible I/O bank, 4 bits in each field, 1 per lane data=1/ctl=0
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
parameter RCLK_SELECT_BANK = 0,
parameter RCLK_SELECT_LANE = "B",
parameter RCLK_SELECT_EDGE = 4'b1111,
parameter GENERATE_DDR_CK_MAP = "0B",
parameter BYTELANES_DDR_CK = 72'h00_0000_0000_0000_0002,
parameter USE_PRE_POST_FIFO = "TRUE",
parameter SYNTHESIS = "FALSE",
parameter PO_CTL_COARSE_BYPASS = "FALSE",
parameter PI_SEL_CLK_OFFSET = 6,
parameter PHYCTL_CMD_FIFO = "FALSE",
parameter PHY_CLK_RATIO = 4, // phy to controller divide ratio
// common to all i/o banks
parameter PHY_FOUR_WINDOW_CLOCKS = 63,
parameter PHY_EVENTS_DELAY = 18,
parameter PHY_COUNT_EN = "TRUE",
parameter PHY_SYNC_MODE = "TRUE",
parameter PHY_DISABLE_SEQ_MATCH = "FALSE",
parameter MASTER_PHY_CTL = 0,
// common to instance 0
parameter PHY_0_BITLANES = 48'hdffd_fffe_dfff,
parameter PHY_0_BITLANES_OUTONLY = 48'h0000_0000_0000,
parameter PHY_0_LANE_REMAP = 16'h3210,
parameter PHY_0_GENERATE_IDELAYCTRL = "FALSE",
parameter PHY_0_IODELAY_GRP = "IODELAY_MIG",
parameter FPGA_SPEED_GRADE = 1,
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter NUM_DDR_CK = 1,
parameter PHY_0_DATA_CTL = DATA_CTL_B0,
parameter PHY_0_CMD_OFFSET = 0,
parameter PHY_0_RD_CMD_OFFSET_0 = 0,
parameter PHY_0_RD_CMD_OFFSET_1 = 0,
parameter PHY_0_RD_CMD_OFFSET_2 = 0,
parameter PHY_0_RD_CMD_OFFSET_3 = 0,
parameter PHY_0_RD_DURATION_0 = 0,
parameter PHY_0_RD_DURATION_1 = 0,
parameter PHY_0_RD_DURATION_2 = 0,
parameter PHY_0_RD_DURATION_3 = 0,
parameter PHY_0_WR_CMD_OFFSET_0 = 0,
parameter PHY_0_WR_CMD_OFFSET_1 = 0,
parameter PHY_0_WR_CMD_OFFSET_2 = 0,
parameter PHY_0_WR_CMD_OFFSET_3 = 0,
parameter PHY_0_WR_DURATION_0 = 0,
parameter PHY_0_WR_DURATION_1 = 0,
parameter PHY_0_WR_DURATION_2 = 0,
parameter PHY_0_WR_DURATION_3 = 0,
parameter PHY_0_AO_WRLVL_EN = 0,
parameter PHY_0_AO_TOGGLE = 4'b0101, // odd bits are toggle (CKE)
parameter PHY_0_OF_ALMOST_FULL_VALUE = 1,
parameter PHY_0_IF_ALMOST_EMPTY_VALUE = 1,
// per lane parameters
parameter PHY_0_A_PI_FREQ_REF_DIV = "NONE",
parameter PHY_0_A_PI_CLKOUT_DIV = 2,
parameter PHY_0_A_PO_CLKOUT_DIV = 2,
parameter PHY_0_A_BURST_MODE = "TRUE",
parameter PHY_0_A_PI_OUTPUT_CLK_SRC = "DELAYED_REF",
parameter PHY_0_A_PO_OUTPUT_CLK_SRC = "DELAYED_REF",
parameter PHY_0_A_PO_OCLK_DELAY = 25,
parameter PHY_0_B_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_0_C_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_0_D_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_0_A_PO_OCLKDELAY_INV = "FALSE",
parameter PHY_0_A_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4",
parameter PHY_0_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_A_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4",
parameter PHY_0_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_A_OSERDES_DATA_RATE = "UNDECLARED",
parameter PHY_0_A_OSERDES_DATA_WIDTH = "UNDECLARED",
parameter PHY_0_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_0_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_0_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_0_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_0_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_0_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_0_A_IDELAYE2_IDELAY_TYPE = "VARIABLE",
parameter PHY_0_A_IDELAYE2_IDELAY_VALUE = 00,
parameter PHY_0_B_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_0_B_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_0_C_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_0_C_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_0_D_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_0_D_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
// common to instance 1
parameter PHY_1_BITLANES = PHY_0_BITLANES,
parameter PHY_1_BITLANES_OUTONLY = 48'h0000_0000_0000,
parameter PHY_1_LANE_REMAP = 16'h3210,
parameter PHY_1_GENERATE_IDELAYCTRL = "FALSE",
parameter PHY_1_IODELAY_GRP = PHY_0_IODELAY_GRP,
parameter PHY_1_DATA_CTL = DATA_CTL_B1,
parameter PHY_1_CMD_OFFSET = PHY_0_CMD_OFFSET,
parameter PHY_1_RD_CMD_OFFSET_0 = PHY_0_RD_CMD_OFFSET_0,
parameter PHY_1_RD_CMD_OFFSET_1 = PHY_0_RD_CMD_OFFSET_1,
parameter PHY_1_RD_CMD_OFFSET_2 = PHY_0_RD_CMD_OFFSET_2,
parameter PHY_1_RD_CMD_OFFSET_3 = PHY_0_RD_CMD_OFFSET_3,
parameter PHY_1_RD_DURATION_0 = PHY_0_RD_DURATION_0,
parameter PHY_1_RD_DURATION_1 = PHY_0_RD_DURATION_1,
parameter PHY_1_RD_DURATION_2 = PHY_0_RD_DURATION_2,
parameter PHY_1_RD_DURATION_3 = PHY_0_RD_DURATION_3,
parameter PHY_1_WR_CMD_OFFSET_0 = PHY_0_WR_CMD_OFFSET_0,
parameter PHY_1_WR_CMD_OFFSET_1 = PHY_0_WR_CMD_OFFSET_1,
parameter PHY_1_WR_CMD_OFFSET_2 = PHY_0_WR_CMD_OFFSET_2,
parameter PHY_1_WR_CMD_OFFSET_3 = PHY_0_WR_CMD_OFFSET_3,
parameter PHY_1_WR_DURATION_0 = PHY_0_WR_DURATION_0,
parameter PHY_1_WR_DURATION_1 = PHY_0_WR_DURATION_1,
parameter PHY_1_WR_DURATION_2 = PHY_0_WR_DURATION_2,
parameter PHY_1_WR_DURATION_3 = PHY_0_WR_DURATION_3,
parameter PHY_1_AO_WRLVL_EN = PHY_0_AO_WRLVL_EN,
parameter PHY_1_AO_TOGGLE = PHY_0_AO_TOGGLE, // odd bits are toggle (CKE)
parameter PHY_1_OF_ALMOST_FULL_VALUE = 1,
parameter PHY_1_IF_ALMOST_EMPTY_VALUE = 1,
// per lane parameters
parameter PHY_1_A_PI_FREQ_REF_DIV = PHY_0_A_PI_FREQ_REF_DIV,
parameter PHY_1_A_PI_CLKOUT_DIV = PHY_0_A_PI_CLKOUT_DIV,
parameter PHY_1_A_PO_CLKOUT_DIV = PHY_0_A_PO_CLKOUT_DIV,
parameter PHY_1_A_BURST_MODE = PHY_0_A_BURST_MODE,
parameter PHY_1_A_PI_OUTPUT_CLK_SRC = PHY_0_A_PI_OUTPUT_CLK_SRC,
parameter PHY_1_A_PO_OUTPUT_CLK_SRC = PHY_0_A_PO_OUTPUT_CLK_SRC ,
parameter PHY_1_A_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_1_B_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,
parameter PHY_1_C_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,
parameter PHY_1_D_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,
parameter PHY_1_A_PO_OCLKDELAY_INV = PHY_0_A_PO_OCLKDELAY_INV,
parameter PHY_1_A_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_A_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_B_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_B_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_C_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_C_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_D_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_D_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_A_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_A_IF_ARRAY_MODE = PHY_0_A_IF_ARRAY_MODE,
parameter PHY_1_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_A_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_A_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_1_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_1_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_1_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
// common to instance 2
parameter PHY_2_BITLANES = PHY_0_BITLANES,
parameter PHY_2_BITLANES_OUTONLY = 48'h0000_0000_0000,
parameter PHY_2_LANE_REMAP = 16'h3210,
parameter PHY_2_GENERATE_IDELAYCTRL = "FALSE",
parameter PHY_2_IODELAY_GRP = PHY_0_IODELAY_GRP,
parameter PHY_2_DATA_CTL = DATA_CTL_B2,
parameter PHY_2_CMD_OFFSET = PHY_0_CMD_OFFSET,
parameter PHY_2_RD_CMD_OFFSET_0 = PHY_0_RD_CMD_OFFSET_0,
parameter PHY_2_RD_CMD_OFFSET_1 = PHY_0_RD_CMD_OFFSET_1,
parameter PHY_2_RD_CMD_OFFSET_2 = PHY_0_RD_CMD_OFFSET_2,
parameter PHY_2_RD_CMD_OFFSET_3 = PHY_0_RD_CMD_OFFSET_3,
parameter PHY_2_RD_DURATION_0 = PHY_0_RD_DURATION_0,
parameter PHY_2_RD_DURATION_1 = PHY_0_RD_DURATION_1,
parameter PHY_2_RD_DURATION_2 = PHY_0_RD_DURATION_2,
parameter PHY_2_RD_DURATION_3 = PHY_0_RD_DURATION_3,
parameter PHY_2_WR_CMD_OFFSET_0 = PHY_0_WR_CMD_OFFSET_0,
parameter PHY_2_WR_CMD_OFFSET_1 = PHY_0_WR_CMD_OFFSET_1,
parameter PHY_2_WR_CMD_OFFSET_2 = PHY_0_WR_CMD_OFFSET_2,
parameter PHY_2_WR_CMD_OFFSET_3 = PHY_0_WR_CMD_OFFSET_3,
parameter PHY_2_WR_DURATION_0 = PHY_0_WR_DURATION_0,
parameter PHY_2_WR_DURATION_1 = PHY_0_WR_DURATION_1,
parameter PHY_2_WR_DURATION_2 = PHY_0_WR_DURATION_2,
parameter PHY_2_WR_DURATION_3 = PHY_0_WR_DURATION_3,
parameter PHY_2_AO_WRLVL_EN = PHY_0_AO_WRLVL_EN,
parameter PHY_2_AO_TOGGLE = PHY_0_AO_TOGGLE, // odd bits are toggle (CKE)
parameter PHY_2_OF_ALMOST_FULL_VALUE = 1,
parameter PHY_2_IF_ALMOST_EMPTY_VALUE = 1,
// per lane parameters
parameter PHY_2_A_PI_FREQ_REF_DIV = PHY_0_A_PI_FREQ_REF_DIV,
parameter PHY_2_A_PI_CLKOUT_DIV = PHY_0_A_PI_CLKOUT_DIV ,
parameter PHY_2_A_PO_CLKOUT_DIV = PHY_0_A_PO_CLKOUT_DIV,
parameter PHY_2_A_BURST_MODE = PHY_0_A_BURST_MODE ,
parameter PHY_2_A_PI_OUTPUT_CLK_SRC = PHY_0_A_PI_OUTPUT_CLK_SRC,
parameter PHY_2_A_PO_OUTPUT_CLK_SRC = PHY_0_A_PO_OUTPUT_CLK_SRC,
parameter PHY_2_A_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_A_IF_ARRAY_MODE = PHY_0_A_IF_ARRAY_MODE,
parameter PHY_2_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_A_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_2_B_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,
parameter PHY_2_C_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,
parameter PHY_2_D_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,
parameter PHY_2_A_PO_OCLKDELAY_INV = PHY_0_A_PO_OCLKDELAY_INV,
parameter PHY_2_A_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_A_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_A_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_A_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_2_B_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_B_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_2_C_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_C_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_2_D_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_D_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_0_IS_LAST_BANK = ((BYTE_LANES_B1 != 0) || (BYTE_LANES_B2 != 0) || (BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0)) ? "FALSE" : "TRUE",
parameter PHY_1_IS_LAST_BANK = ((BYTE_LANES_B1 != 0) && ((BYTE_LANES_B2 != 0) || (BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0))) ? "FALSE" : ((PHY_0_IS_LAST_BANK) ? "FALSE" : "TRUE"),
parameter PHY_2_IS_LAST_BANK = (BYTE_LANES_B2 != 0) && ((BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0)) ? "FALSE" : ((PHY_0_IS_LAST_BANK || PHY_1_IS_LAST_BANK) ? "FALSE" : "TRUE"),
parameter TCK = 2500,
// local computational use, do not pass down
parameter N_LANES = (0+BYTE_LANES_B0[0]) + (0+BYTE_LANES_B0[1]) + (0+BYTE_LANES_B0[2]) + (0+BYTE_LANES_B0[3])
+ (0+BYTE_LANES_B1[0]) + (0+BYTE_LANES_B1[1]) + (0+BYTE_LANES_B1[2]) + (0+BYTE_LANES_B1[3]) + (0+BYTE_LANES_B2[0]) + (0+BYTE_LANES_B2[1]) + (0+BYTE_LANES_B2[2]) + (0+BYTE_LANES_B2[3])
, // must not delete comma for syntax
parameter HIGHEST_BANK = (BYTE_LANES_B4 != 0 ? 5 : (BYTE_LANES_B3 != 0 ? 4 : (BYTE_LANES_B2 != 0 ? 3 : (BYTE_LANES_B1 != 0 ? 2 : 1)))),
parameter HIGHEST_LANE_B0 = ((PHY_0_IS_LAST_BANK == "FALSE") ? 4 : BYTE_LANES_B0[3] ? 4 : BYTE_LANES_B0[2] ? 3 : BYTE_LANES_B0[1] ? 2 : BYTE_LANES_B0[0] ? 1 : 0) ,
parameter HIGHEST_LANE_B1 = (HIGHEST_BANK > 2) ? 4 : ( BYTE_LANES_B1[3] ? 4 : BYTE_LANES_B1[2] ? 3 : BYTE_LANES_B1[1] ? 2 : BYTE_LANES_B1[0] ? 1 : 0) ,
parameter HIGHEST_LANE_B2 = (HIGHEST_BANK > 3) ? 4 : ( BYTE_LANES_B2[3] ? 4 : BYTE_LANES_B2[2] ? 3 : BYTE_LANES_B2[1] ? 2 : BYTE_LANES_B2[0] ? 1 : 0) ,
parameter HIGHEST_LANE_B3 = 0,
parameter HIGHEST_LANE_B4 = 0,
parameter HIGHEST_LANE = (HIGHEST_LANE_B4 != 0) ? (HIGHEST_LANE_B4+16) : ((HIGHEST_LANE_B3 != 0) ? (HIGHEST_LANE_B3 + 12) : ((HIGHEST_LANE_B2 != 0) ? (HIGHEST_LANE_B2 + 8) : ((HIGHEST_LANE_B1 != 0) ? (HIGHEST_LANE_B1 + 4) : HIGHEST_LANE_B0))),
parameter LP_DDR_CK_WIDTH = 2,
parameter GENERATE_SIGNAL_SPLIT = "FALSE"
,parameter CKE_ODT_AUX = "FALSE"
)
(
input rst,
input ddr_rst_in_n ,
input phy_clk,
input freq_refclk,
input mem_refclk,
input mem_refclk_div4,
input pll_lock,
input sync_pulse,
input auxout_clk,
input idelayctrl_refclk,
input [HIGHEST_LANE*80-1:0] phy_dout,
input phy_cmd_wr_en,
input phy_data_wr_en,
input phy_rd_en,
input [31:0] phy_ctl_wd,
input [3:0] aux_in_1,
input [3:0] aux_in_2,
input [5:0] data_offset_1,
input [5:0] data_offset_2,
input phy_ctl_wr,
input if_rst,
input if_empty_def,
input cke_in,
input idelay_ce,
input idelay_ld,
input idelay_inc,
input phyGo,
input input_sink,
output if_a_empty,
output if_empty /* synthesis syn_maxfan = 3 */,
output if_empty_or,
output if_empty_and,
output of_ctl_a_full,
output of_data_a_full,
output of_ctl_full,
output of_data_full,
output pre_data_a_full,
output [HIGHEST_LANE*80-1:0] phy_din,
output phy_ctl_a_full,
output wire [3:0] phy_ctl_full,
output [HIGHEST_LANE*12-1:0] mem_dq_out,
output [HIGHEST_LANE*12-1:0] mem_dq_ts,
input [HIGHEST_LANE*10-1:0] mem_dq_in,
output [HIGHEST_LANE-1:0] mem_dqs_out,
output [HIGHEST_LANE-1:0] mem_dqs_ts,
input [HIGHEST_LANE-1:0] mem_dqs_in,
(* IOB = "FORCE" *) output reg [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out, // to memory, odt , 4 per phy controller
output phy_ctl_ready, // to fabric
output reg rst_out, // to memory
output [(NUM_DDR_CK * LP_DDR_CK_WIDTH)-1:0] ddr_clk,
// output rclk,
output mcGo,
output ref_dll_lock,
// calibration signals
input phy_write_calib,
input phy_read_calib,
input [5:0] calib_sel,
input [HIGHEST_BANK-1:0]calib_zero_inputs, // bit calib_sel[2], one per bank
input [HIGHEST_BANK-1:0]calib_zero_ctrl, // one bit per bank, zero's only control lane calibration inputs
input [HIGHEST_LANE-1:0] calib_zero_lanes, // one bit per lane
input calib_in_common,
input [2:0] po_fine_enable,
input [2:0] po_coarse_enable,
input [2:0] po_fine_inc,
input [2:0] po_coarse_inc,
input po_counter_load_en,
input [2:0] po_sel_fine_oclk_delay,
input [8:0] po_counter_load_val,
input po_counter_read_en,
output reg po_coarse_overflow,
output reg po_fine_overflow,
output reg [8:0] po_counter_read_val,
input [HIGHEST_BANK-1:0] pi_rst_dqs_find,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input pi_counter_read_en,
input [5:0] pi_counter_load_val,
output reg pi_fine_overflow,
output reg [5:0] pi_counter_read_val,
output reg pi_phase_locked,
output pi_phase_locked_all,
output reg pi_dqs_found,
output pi_dqs_found_all,
output pi_dqs_found_any,
output [HIGHEST_LANE-1:0] pi_phase_locked_lanes,
output [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
output reg pi_dqs_out_of_range,
input [29:0] fine_delay,
input fine_delay_sel
);
wire [7:0] calib_zero_inputs_int ;
wire [HIGHEST_BANK*4-1:0] calib_zero_lanes_int ;
//Added the temporary variable for concadination operation
wire [2:0] calib_sel_byte0 ;
wire [2:0] calib_sel_byte1 ;
wire [2:0] calib_sel_byte2 ;
wire [4:0] po_coarse_overflow_w;
wire [4:0] po_fine_overflow_w;
wire [8:0] po_counter_read_val_w[4:0];
wire [4:0] pi_fine_overflow_w;
wire [5:0] pi_counter_read_val_w[4:0];
wire [4:0] pi_dqs_found_w;
wire [4:0] pi_dqs_found_all_w;
wire [4:0] pi_dqs_found_any_w;
wire [4:0] pi_dqs_out_of_range_w;
wire [4:0] pi_phase_locked_w;
wire [4:0] pi_phase_locked_all_w;
wire [4:0] rclk_w;
wire [HIGHEST_BANK-1:0] phy_ctl_ready_w;
wire [(LP_DDR_CK_WIDTH*24)-1:0] ddr_clk_w [HIGHEST_BANK-1:0];
wire [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out_;
wire [3:0] if_q0;
wire [3:0] if_q1;
wire [3:0] if_q2;
wire [3:0] if_q3;
wire [3:0] if_q4;
wire [7:0] if_q5;
wire [7:0] if_q6;
wire [3:0] if_q7;
wire [3:0] if_q8;
wire [3:0] if_q9;
wire [31:0] _phy_ctl_wd;
wire [3:0] aux_in_[4:1];
wire [3:0] rst_out_w;
wire freq_refclk_split;
wire mem_refclk_split;
wire mem_refclk_div4_split;
wire sync_pulse_split;
wire phy_clk_split0;
wire phy_ctl_clk_split0;
wire [31:0] phy_ctl_wd_split0;
wire phy_ctl_wr_split0;
wire phy_ctl_clk_split1;
wire phy_clk_split1;
wire [31:0] phy_ctl_wd_split1;
wire phy_ctl_wr_split1;
wire [5:0] phy_data_offset_1_split1;
wire phy_ctl_clk_split2;
wire phy_clk_split2;
wire [31:0] phy_ctl_wd_split2;
wire phy_ctl_wr_split2;
wire [5:0] phy_data_offset_2_split2;
wire [HIGHEST_LANE*80-1:0] phy_dout_split0;
wire phy_cmd_wr_en_split0;
wire phy_data_wr_en_split0;
wire phy_rd_en_split0;
wire [HIGHEST_LANE*80-1:0] phy_dout_split1;
wire phy_cmd_wr_en_split1;
wire phy_data_wr_en_split1;
wire phy_rd_en_split1;
wire [HIGHEST_LANE*80-1:0] phy_dout_split2;
wire phy_cmd_wr_en_split2;
wire phy_data_wr_en_split2;
wire phy_rd_en_split2;
wire phy_ctl_mstr_empty;
wire [HIGHEST_BANK-1:0] phy_ctl_empty;
wire _phy_ctl_a_full_f;
wire _phy_ctl_a_empty_f;
wire _phy_ctl_full_f;
wire _phy_ctl_empty_f;
wire [HIGHEST_BANK-1:0] _phy_ctl_a_full_p;
wire [HIGHEST_BANK-1:0] _phy_ctl_full_p;
wire [HIGHEST_BANK-1:0] of_ctl_a_full_v;
wire [HIGHEST_BANK-1:0] of_ctl_full_v;
wire [HIGHEST_BANK-1:0] of_data_a_full_v;
wire [HIGHEST_BANK-1:0] of_data_full_v;
wire [HIGHEST_BANK-1:0] pre_data_a_full_v;
wire [HIGHEST_BANK-1:0] if_empty_v;
wire [HIGHEST_BANK-1:0] byte_rd_en_v;
wire [HIGHEST_BANK*2-1:0] byte_rd_en_oth_banks;
wire [HIGHEST_BANK-1:0] if_empty_or_v;
wire [HIGHEST_BANK-1:0] if_empty_and_v;
wire [HIGHEST_BANK-1:0] if_a_empty_v;
localparam IF_ARRAY_MODE = "ARRAY_MODE_4_X_4";
localparam IF_SYNCHRONOUS_MODE = "FALSE";
localparam IF_SLOW_WR_CLK = "FALSE";
localparam IF_SLOW_RD_CLK = "FALSE";
localparam PHY_MULTI_REGION = (HIGHEST_BANK > 1) ? "TRUE" : "FALSE";
localparam RCLK_NEG_EDGE = 3'b000;
localparam RCLK_POS_EDGE = 3'b111;
localparam LP_PHY_0_BYTELANES_DDR_CK = BYTELANES_DDR_CK & 24'hFF_FFFF;
localparam LP_PHY_1_BYTELANES_DDR_CK = (BYTELANES_DDR_CK >> 24) & 24'hFF_FFFF;
localparam LP_PHY_2_BYTELANES_DDR_CK = (BYTELANES_DDR_CK >> 48) & 24'hFF_FFFF;
// hi, lo positions for data offset field, MIG doesn't allow defines
localparam PC_DATA_OFFSET_RANGE_HI = 22;
localparam PC_DATA_OFFSET_RANGE_LO = 17;
/* Phaser_In Output source coding table
"PHASE_REF" : 4'b0000;
"DELAYED_MEM_REF" : 4'b0101;
"DELAYED_PHASE_REF" : 4'b0011;
"DELAYED_REF" : 4'b0001;
"FREQ_REF" : 4'b1000;
"MEM_REF" : 4'b0010;
*/
localparam RCLK_PI_OUTPUT_CLK_SRC = "DELAYED_MEM_REF";
localparam DDR_TCK = TCK;
localparam real FREQ_REF_PERIOD = DDR_TCK / (PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1);
localparam real L_FREQ_REF_PERIOD_NS = FREQ_REF_PERIOD /1000.0;
localparam PO_S3_TAPS = 64 ; // Number of taps per clock cycle in OCLK_DELAYED delay line
localparam PI_S2_TAPS = 128 ; // Number of taps per clock cycle in stage 2 delay line
localparam PO_S2_TAPS = 128 ; // Number of taps per clock cycle in sta
/*
Intrinsic delay of Phaser In Stage 1
@3300ps - 1.939ns - 58.8%
@2500ps - 1.657ns - 66.3%
@1875ps - 1.263ns - 67.4%
@1500ps - 1.021ns - 68.1%
@1250ps - 0.868ns - 69.4%
@1072ps - 0.752ns - 70.1%
@938ps - 0.667ns - 71.1%
*/
// If we use the Delayed Mem_Ref_Clk in the RCLK Phaser_In, then the Stage 1 intrinsic delay is 0.0
// Fraction of a full DDR_TCK period
localparam real PI_STG1_INTRINSIC_DELAY = (RCLK_PI_OUTPUT_CLK_SRC == "DELAYED_MEM_REF") ? 0.0 :
((DDR_TCK < 1005) ? 0.667 :
(DDR_TCK < 1160) ? 0.752 :
(DDR_TCK < 1375) ? 0.868 :
(DDR_TCK < 1685) ? 1.021 :
(DDR_TCK < 2185) ? 1.263 :
(DDR_TCK < 2900) ? 1.657 :
(DDR_TCK < 3100) ? 1.771 : 1.939)*1000;
/*
Intrinsic delay of Phaser In Stage 2
@3300ps - 0.912ns - 27.6% - single tap - 13ps
@3000ps - 0.848ns - 28.3% - single tap - 11ps
@2500ps - 1.264ns - 50.6% - single tap - 19ps
@1875ps - 1.000ns - 53.3% - single tap - 15ps
@1500ps - 0.848ns - 56.5% - single tap - 11ps
@1250ps - 0.736ns - 58.9% - single tap - 9ps
@1072ps - 0.664ns - 61.9% - single tap - 8ps
@938ps - 0.608ns - 64.8% - single tap - 7ps
*/
// Intrinsic delay = (.4218 + .0002freq(MHz))period(ps)
localparam real PI_STG2_INTRINSIC_DELAY = (0.4218*FREQ_REF_PERIOD + 200) + 16.75; // 12ps fudge factor
/*
Intrinsic delay of Phaser Out Stage 2 - coarse bypass = 1
@3300ps - 1.294ns - 39.2%
@2500ps - 1.294ns - 51.8%
@1875ps - 1.030ns - 54.9%
@1500ps - 0.878ns - 58.5%
@1250ps - 0.766ns - 61.3%
@1072ps - 0.694ns - 64.7%
@938ps - 0.638ns - 68.0%
Intrinsic delay of Phaser Out Stage 2 - coarse bypass = 0
@3300ps - 2.084ns - 63.2% - single tap - 20ps
@2500ps - 2.084ns - 81.9% - single tap - 19ps
@1875ps - 1.676ns - 89.4% - single tap - 15ps
@1500ps - 1.444ns - 96.3% - single tap - 11ps
@1250ps - 1.276ns - 102.1% - single tap - 9ps
@1072ps - 1.164ns - 108.6% - single tap - 8ps
@938ps - 1.076ns - 114.7% - single tap - 7ps
*/
// Fraction of a full DDR_TCK period
localparam real PO_STG1_INTRINSIC_DELAY = 0;
localparam real PO_STG2_FINE_INTRINSIC_DELAY = 0.4218*FREQ_REF_PERIOD + 200 + 42; // 42ps fudge factor
localparam real PO_STG2_COARSE_INTRINSIC_DELAY = 0.2256*FREQ_REF_PERIOD + 200 + 29; // 29ps fudge factor
localparam real PO_STG2_INTRINSIC_DELAY = PO_STG2_FINE_INTRINSIC_DELAY +
(PO_CTL_COARSE_BYPASS == "TRUE" ? 30 : PO_STG2_COARSE_INTRINSIC_DELAY);
// When the PO_STG2_INTRINSIC_DELAY is approximately equal to tCK, then the Phaser Out's circular buffer can
// go metastable. The circular buffer must be prevented from getting into a metastable state. To accomplish this,
// a default programmed value must be programmed into the stage 2 delay. This delay is only needed at reset, adjustments
// to the stage 2 delay can be made after reset is removed.
localparam real PO_S2_TAPS_SIZE = 1.0*FREQ_REF_PERIOD / PO_S2_TAPS ; // average delay of taps in stage 2 fine delay line
localparam real PO_CIRC_BUF_META_ZONE = 200.0;
localparam PO_CIRC_BUF_EARLY = (PO_STG2_INTRINSIC_DELAY < DDR_TCK) ? 1'b1 : 1'b0;
localparam real PO_CIRC_BUF_OFFSET = (PO_STG2_INTRINSIC_DELAY < DDR_TCK) ? DDR_TCK - PO_STG2_INTRINSIC_DELAY : PO_STG2_INTRINSIC_DELAY - DDR_TCK;
// If the stage 2 intrinsic delay is less than the clock period, then see if it is less than the threshold
// If it is not more than the threshold than we must push the delay after the clock period plus a guardband.
//A change in PO_CIRC_BUF_DELAY value will affect the localparam TAP_DEC value(=PO_CIRC_BUF_DELAY - 31) in ddr_phy_ck_addr_cmd_delay.v. Update TAP_DEC value when PO_CIRC_BUF_DELAY is updated.
localparam integer PO_CIRC_BUF_DELAY = 60;
//localparam integer PO_CIRC_BUF_DELAY = PO_CIRC_BUF_EARLY ? (PO_CIRC_BUF_OFFSET > PO_CIRC_BUF_META_ZONE) ? 0 :
// (PO_CIRC_BUF_META_ZONE + PO_CIRC_BUF_OFFSET) / PO_S2_TAPS_SIZE :
// (PO_CIRC_BUF_META_ZONE - PO_CIRC_BUF_OFFSET) / PO_S2_TAPS_SIZE;
localparam real PI_S2_TAPS_SIZE = 1.0*FREQ_REF_PERIOD / PI_S2_TAPS ; // average delay of taps in stage 2 fine delay line
localparam real PI_MAX_STG2_DELAY = (PI_S2_TAPS/2 - 1) * PI_S2_TAPS_SIZE;
localparam real PI_INTRINSIC_DELAY = PI_STG1_INTRINSIC_DELAY + PI_STG2_INTRINSIC_DELAY;
localparam real PO_INTRINSIC_DELAY = PO_STG1_INTRINSIC_DELAY + PO_STG2_INTRINSIC_DELAY;
localparam real PO_DELAY = PO_INTRINSIC_DELAY + (PO_CIRC_BUF_DELAY*PO_S2_TAPS_SIZE);
localparam RCLK_BUFIO_DELAY = 1200; // estimate of clock insertion delay of rclk through BUFIO to ioi
// The PI_OFFSET is the difference between the Phaser Out delay path and the intrinsic delay path
// of the Phaser_In that drives the rclk. The objective is to align either the rising edges of the
// oserdes_oclk and the rclk or to align the rising to falling edges depending on which adjustment
// is within the range of the stage 2 delay line in the Phaser_In.
localparam integer RCLK_DELAY_INT= (PI_INTRINSIC_DELAY + RCLK_BUFIO_DELAY);
localparam integer PO_DELAY_INT = PO_DELAY;
localparam PI_OFFSET = (PO_DELAY_INT % DDR_TCK) - (RCLK_DELAY_INT % DDR_TCK);
// if pi_offset >= 0 align to oclk posedge by delaying pi path to where oclk is
// if pi_offset < 0 align to oclk negedge by delaying pi path the additional distance to next oclk edge.
// note that in this case PI_OFFSET is negative so invert before subtracting.
localparam real PI_STG2_DELAY_CAND = PI_OFFSET >= 0
? PI_OFFSET
: ((-PI_OFFSET) < DDR_TCK/2) ?
(DDR_TCK/2 - (- PI_OFFSET)) :
(DDR_TCK - (- PI_OFFSET)) ;
localparam real PI_STG2_DELAY =
(PI_STG2_DELAY_CAND > PI_MAX_STG2_DELAY ?
PI_MAX_STG2_DELAY : PI_STG2_DELAY_CAND);
localparam integer DEFAULT_RCLK_DELAY = PI_STG2_DELAY / PI_S2_TAPS_SIZE;
localparam LP_RCLK_SELECT_EDGE = (RCLK_SELECT_EDGE != 4'b1111 ) ? RCLK_SELECT_EDGE : (PI_OFFSET >= 0 ? RCLK_POS_EDGE : (PI_OFFSET <= TCK/2 ? RCLK_NEG_EDGE : RCLK_POS_EDGE));
localparam integer L_PHY_0_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ;
localparam integer L_PHY_1_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ;
localparam integer L_PHY_2_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ;
localparam L_PHY_0_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[0]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_0_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[1]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_0_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[2]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_0_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[3]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_1_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[0]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_1_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[1]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_1_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[2]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_1_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[3]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_2_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[0]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_2_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[1]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_2_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[2]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_2_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[3]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_0_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_0_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_0_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_0_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_1_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_1_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_1_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_1_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_2_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_2_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_2_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_2_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
wire _phy_clk;
wire [2:0] mcGo_w;
wire [HIGHEST_BANK-1:0] ref_dll_lock_w;
reg [15:0] mcGo_r;
assign ref_dll_lock = & ref_dll_lock_w;
initial begin
if ( SYNTHESIS == "FALSE" ) begin
$display("%m : BYTE_LANES_B0 = %x BYTE_LANES_B1 = %x DATA_CTL_B0 = %x DATA_CTL_B1 = %x", BYTE_LANES_B0, BYTE_LANES_B1, DATA_CTL_B0, DATA_CTL_B1);
$display("%m : HIGHEST_LANE = %d HIGHEST_LANE_B0 = %d HIGHEST_LANE_B1 = %d", HIGHEST_LANE, HIGHEST_LANE_B0, HIGHEST_LANE_B1);
$display("%m : HIGHEST_BANK = %d", HIGHEST_BANK);
$display("%m : FREQ_REF_PERIOD = %0.2f ", FREQ_REF_PERIOD);
$display("%m : DDR_TCK = %0d ", DDR_TCK);
$display("%m : PO_S2_TAPS_SIZE = %0.2f ", PO_S2_TAPS_SIZE);
$display("%m : PO_CIRC_BUF_EARLY = %0d ", PO_CIRC_BUF_EARLY);
$display("%m : PO_CIRC_BUF_OFFSET = %0.2f ", PO_CIRC_BUF_OFFSET);
$display("%m : PO_CIRC_BUF_META_ZONE = %0.2f ", PO_CIRC_BUF_META_ZONE);
$display("%m : PO_STG2_FINE_INTR_DLY = %0.2f ", PO_STG2_FINE_INTRINSIC_DELAY);
$display("%m : PO_STG2_COARSE_INTR_DLY = %0.2f ", PO_STG2_COARSE_INTRINSIC_DELAY);
$display("%m : PO_STG2_INTRINSIC_DELAY = %0.2f ", PO_STG2_INTRINSIC_DELAY);
$display("%m : PO_CIRC_BUF_DELAY = %0d ", PO_CIRC_BUF_DELAY);
$display("%m : PO_INTRINSIC_DELAY = %0.2f ", PO_INTRINSIC_DELAY);
$display("%m : PO_DELAY = %0.2f ", PO_DELAY);
$display("%m : PO_OCLK_DELAY = %0d ", PHY_0_A_PO_OCLK_DELAY);
$display("%m : L_PHY_0_PO_FINE_DELAY = %0d ", L_PHY_0_PO_FINE_DELAY);
$display("%m : PI_STG1_INTRINSIC_DELAY = %0.2f ", PI_STG1_INTRINSIC_DELAY);
$display("%m : PI_STG2_INTRINSIC_DELAY = %0.2f ", PI_STG2_INTRINSIC_DELAY);
$display("%m : PI_INTRINSIC_DELAY = %0.2f ", PI_INTRINSIC_DELAY);
$display("%m : PI_MAX_STG2_DELAY = %0.2f ", PI_MAX_STG2_DELAY);
$display("%m : PI_OFFSET = %0.2f ", PI_OFFSET);
if ( PI_OFFSET < 0) $display("%m : a negative PI_OFFSET means that rclk path is longer than oclk path so rclk will be delayed to next oclk edge and the negedge of rclk may be used.");
$display("%m : PI_STG2_DELAY = %0.2f ", PI_STG2_DELAY);
$display("%m :PI_STG2_DELAY_CAND = %0.2f ",PI_STG2_DELAY_CAND);
$display("%m : DEFAULT_RCLK_DELAY = %0d ", DEFAULT_RCLK_DELAY);
$display("%m : RCLK_SELECT_EDGE = %0b ", LP_RCLK_SELECT_EDGE);
end // SYNTHESIS
if ( PI_STG2_DELAY_CAND > PI_MAX_STG2_DELAY) $display("WARNING: %m: The required delay though the phaser_in to internally match the aux_out clock to ddr clock exceeds the maximum allowable delay. The clock edge will occur at the output registers of aux_out %0.2f ps before the ddr clock edge. If aux_out is used for memory inputs, this may violate setup or hold time.", PI_STG2_DELAY_CAND - PI_MAX_STG2_DELAY);
end
assign sync_pulse_split = sync_pulse;
assign mem_refclk_split = mem_refclk;
assign freq_refclk_split = freq_refclk;
assign mem_refclk_div4_split = mem_refclk_div4;
assign phy_ctl_clk_split0 = _phy_clk;
assign phy_ctl_wd_split0 = phy_ctl_wd;
assign phy_ctl_wr_split0 = phy_ctl_wr;
assign phy_clk_split0 = phy_clk;
assign phy_cmd_wr_en_split0 = phy_cmd_wr_en;
assign phy_data_wr_en_split0 = phy_data_wr_en;
assign phy_rd_en_split0 = phy_rd_en;
assign phy_dout_split0 = phy_dout;
assign phy_ctl_clk_split1 = phy_clk;
assign phy_ctl_wd_split1 = phy_ctl_wd;
assign phy_data_offset_1_split1 = data_offset_1;
assign phy_ctl_wr_split1 = phy_ctl_wr;
assign phy_clk_split1 = phy_clk;
assign phy_cmd_wr_en_split1 = phy_cmd_wr_en;
assign phy_data_wr_en_split1 = phy_data_wr_en;
assign phy_rd_en_split1 = phy_rd_en;
assign phy_dout_split1 = phy_dout;
assign phy_ctl_clk_split2 = phy_clk;
assign phy_ctl_wd_split2 = phy_ctl_wd;
assign phy_data_offset_2_split2 = data_offset_2;
assign phy_ctl_wr_split2 = phy_ctl_wr;
assign phy_clk_split2 = phy_clk;
assign phy_cmd_wr_en_split2 = phy_cmd_wr_en;
assign phy_data_wr_en_split2 = phy_data_wr_en;
assign phy_rd_en_split2 = phy_rd_en;
assign phy_dout_split2 = phy_dout;
// these wires are needed to coerce correct synthesis
// the synthesizer did not always see the widths of the
// parameters as 4 bits.
wire [3:0] blb0 = BYTE_LANES_B0;
wire [3:0] blb1 = BYTE_LANES_B1;
wire [3:0] blb2 = BYTE_LANES_B2;
wire [3:0] dcb0 = DATA_CTL_B0;
wire [3:0] dcb1 = DATA_CTL_B1;
wire [3:0] dcb2 = DATA_CTL_B2;
assign pi_dqs_found_all = & (pi_dqs_found_lanes | ~ {blb2, blb1, blb0} | ~ {dcb2, dcb1, dcb0});
assign pi_dqs_found_any = | (pi_dqs_found_lanes & {blb2, blb1, blb0} & {dcb2, dcb1, dcb0});
assign pi_phase_locked_all = & pi_phase_locked_all_w[HIGHEST_BANK-1:0];
assign calib_zero_inputs_int = {3'bxxx, calib_zero_inputs};
//Added to remove concadination in the instantiation
assign calib_sel_byte0 = {calib_zero_inputs_int[0], calib_sel[1:0]} ;
assign calib_sel_byte1 = {calib_zero_inputs_int[1], calib_sel[1:0]} ;
assign calib_sel_byte2 = {calib_zero_inputs_int[2], calib_sel[1:0]} ;
assign calib_zero_lanes_int = calib_zero_lanes;
assign phy_ctl_ready = &phy_ctl_ready_w[HIGHEST_BANK-1:0];
assign phy_ctl_mstr_empty = phy_ctl_empty[MASTER_PHY_CTL];
assign of_ctl_a_full = |of_ctl_a_full_v;
assign of_ctl_full = |of_ctl_full_v;
assign of_data_a_full = |of_data_a_full_v;
assign of_data_full = |of_data_full_v;
assign pre_data_a_full= |pre_data_a_full_v;
// if if_empty_def == 1, empty is asserted only if all are empty;
// this allows the user to detect a skewed fifo depth and self-clear
// if desired. It avoids a reset to clear the flags.
assign if_empty = !if_empty_def ? |if_empty_v : &if_empty_v;
assign if_empty_or = |if_empty_or_v;
assign if_empty_and = &if_empty_and_v;
assign if_a_empty = |if_a_empty_v;
generate
genvar i;
for (i = 0; i != NUM_DDR_CK; i = i + 1) begin : ddr_clk_gen
case ((GENERATE_DDR_CK_MAP >> (16*i)) & 16'hffff)
16'h3041: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i)) & 2'b11;
16'h3042: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11;
16'h3043: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11;
16'h3044: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11;
16'h3141: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i)) & 2'b11;
16'h3142: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11;
16'h3143: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11;
16'h3144: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11;
16'h3241: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i)) & 2'b11;
16'h3242: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11;
16'h3243: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11;
16'h3244: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11;
default : initial $display("ERROR: mc_phy ddr_clk_gen : invalid specification for parameter GENERATE_DDR_CK_MAP , clock index = %d, spec= %x (hex) ", i, (( GENERATE_DDR_CK_MAP >> (16 * i )) & 16'hffff ));
endcase
end
endgenerate
//assign rclk = rclk_w[RCLK_SELECT_BANK];
reg rst_auxout;
reg rst_auxout_r;
reg rst_auxout_rr;
always @(posedge auxout_clk or posedge rst) begin
if ( rst) begin
rst_auxout_r <= #(1) 1'b1;
rst_auxout_rr <= #(1) 1'b1;
end
else begin
rst_auxout_r <= #(1) rst;
rst_auxout_rr <= #(1) rst_auxout_r;
end
end
if ( LP_RCLK_SELECT_EDGE[0]) begin
always @(posedge auxout_clk or posedge rst) begin
if ( rst) begin
rst_auxout <= #(1) 1'b1;
end
else begin
rst_auxout <= #(1) rst_auxout_rr;
end
end
end
else begin
always @(negedge auxout_clk or posedge rst) begin
if ( rst) begin
rst_auxout <= #(1) 1'b1;
end
else begin
rst_auxout <= #(1) rst_auxout_rr;
end
end
end
localparam L_RESET_SELECT_BANK =
(BYTE_LANES_B1 == 0 && BYTE_LANES_B2 == 0 && RCLK_SELECT_BANK) ? 0 : RCLK_SELECT_BANK;
always @(*) begin
rst_out = rst_out_w[L_RESET_SELECT_BANK] & ddr_rst_in_n;
end
always @(posedge phy_clk) begin
if ( rst)
mcGo_r <= #(1) 0;
else
mcGo_r <= #(1) (mcGo_r << 1) | &mcGo_w;
end
assign mcGo = mcGo_r[15];
generate
// this is an optional 1 clock delay to add latency to the phy_control programming path
if (PHYCTL_CMD_FIFO == "TRUE") begin : cmd_fifo_soft
reg [31:0] phy_wd_reg = 0;
reg [3:0] aux_in1_reg = 0;
reg [3:0] aux_in2_reg = 0;
reg sfifo_ready = 0;
assign _phy_ctl_wd = phy_wd_reg;
assign aux_in_[1] = aux_in1_reg;
assign aux_in_[2] = aux_in2_reg;
assign phy_ctl_a_full = |_phy_ctl_a_full_p;
assign phy_ctl_full[0] = |_phy_ctl_full_p;
assign phy_ctl_full[1] = |_phy_ctl_full_p;
assign phy_ctl_full[2] = |_phy_ctl_full_p;
assign phy_ctl_full[3] = |_phy_ctl_full_p;
assign _phy_clk = phy_clk;
always @(posedge phy_clk) begin
phy_wd_reg <= #1 phy_ctl_wd;
aux_in1_reg <= #1 aux_in_1;
aux_in2_reg <= #1 aux_in_2;
sfifo_ready <= #1 phy_ctl_wr;
end
end
else if (PHYCTL_CMD_FIFO == "FALSE") begin
assign _phy_ctl_wd = phy_ctl_wd;
assign aux_in_[1] = aux_in_1;
assign aux_in_[2] = aux_in_2;
assign phy_ctl_a_full = |_phy_ctl_a_full_p;
assign phy_ctl_full[0] = |_phy_ctl_full_p;
assign phy_ctl_full[3:1] = 3'b000;
assign _phy_clk = phy_clk;
end
endgenerate
// instance of four-lane phy
generate
if (HIGHEST_BANK == 3) begin : banks_3
assign byte_rd_en_oth_banks[1:0] = {byte_rd_en_v[1],byte_rd_en_v[2]};
assign byte_rd_en_oth_banks[3:2] = {byte_rd_en_v[0],byte_rd_en_v[2]};
assign byte_rd_en_oth_banks[5:4] = {byte_rd_en_v[0],byte_rd_en_v[1]};
end
else if (HIGHEST_BANK == 2) begin : banks_2
assign byte_rd_en_oth_banks[1:0] = {byte_rd_en_v[1],1'b1};
assign byte_rd_en_oth_banks[3:2] = {byte_rd_en_v[0],1'b1};
end
else begin : banks_1
assign byte_rd_en_oth_banks[1:0] = {1'b1,1'b1};
end
if ( BYTE_LANES_B0 != 0) begin : ddr_phy_4lanes_0
mig_7series_v2_3_ddr_phy_4lanes #
(
.BYTE_LANES (BYTE_LANES_B0), /* four bits, one per lanes */
.DATA_CTL_N (PHY_0_DATA_CTL), /* four bits, one per lane */
.PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),
.PO_FINE_DELAY (L_PHY_0_PO_FINE_DELAY),
.BITLANES (PHY_0_BITLANES),
.BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY),
.BYTELANES_DDR_CK (LP_PHY_0_BYTELANES_DDR_CK),
.LAST_BANK (PHY_0_IS_LAST_BANK),
.LANE_REMAP (PHY_0_LANE_REMAP),
.OF_ALMOST_FULL_VALUE (PHY_0_OF_ALMOST_FULL_VALUE),
.IF_ALMOST_EMPTY_VALUE (PHY_0_IF_ALMOST_EMPTY_VALUE),
.GENERATE_IDELAYCTRL (PHY_0_GENERATE_IDELAYCTRL),
.IODELAY_GRP (PHY_0_IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.BANK_TYPE (BANK_TYPE),
.NUM_DDR_CK (NUM_DDR_CK),
.TCK (TCK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.PC_CLK_RATIO (PHY_CLK_RATIO),
.PC_EVENTS_DELAY (PHY_EVENTS_DELAY),
.PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),
.PC_BURST_MODE (PHY_0_A_BURST_MODE),
.PC_SYNC_MODE (PHY_SYNC_MODE),
.PC_MULTI_REGION (PHY_MULTI_REGION),
.PC_PHY_COUNT_EN (PHY_COUNT_EN),
.PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),
.PC_CMD_OFFSET (PHY_0_CMD_OFFSET),
.PC_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0),
.PC_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1),
.PC_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2),
.PC_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3),
.PC_RD_DURATION_0 (PHY_0_RD_DURATION_0),
.PC_RD_DURATION_1 (PHY_0_RD_DURATION_1),
.PC_RD_DURATION_2 (PHY_0_RD_DURATION_2),
.PC_RD_DURATION_3 (PHY_0_RD_DURATION_3),
.PC_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0),
.PC_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1),
.PC_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2),
.PC_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3),
.PC_WR_DURATION_0 (PHY_0_WR_DURATION_0),
.PC_WR_DURATION_1 (PHY_0_WR_DURATION_1),
.PC_WR_DURATION_2 (PHY_0_WR_DURATION_2),
.PC_WR_DURATION_3 (PHY_0_WR_DURATION_3),
.PC_AO_WRLVL_EN (PHY_0_AO_WRLVL_EN),
.PC_AO_TOGGLE (PHY_0_AO_TOGGLE),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.A_PI_FINE_DELAY (L_PHY_0_A_PI_FINE_DELAY),
.B_PI_FINE_DELAY (L_PHY_0_B_PI_FINE_DELAY),
.C_PI_FINE_DELAY (L_PHY_0_C_PI_FINE_DELAY),
.D_PI_FINE_DELAY (L_PHY_0_D_PI_FINE_DELAY),
.A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV),
.A_PI_BURST_MODE (PHY_0_A_BURST_MODE),
.A_PI_OUTPUT_CLK_SRC (L_PHY_0_A_PI_OUTPUT_CLK_SRC),
.B_PI_OUTPUT_CLK_SRC (L_PHY_0_B_PI_OUTPUT_CLK_SRC),
.C_PI_OUTPUT_CLK_SRC (L_PHY_0_C_PI_OUTPUT_CLK_SRC),
.D_PI_OUTPUT_CLK_SRC (L_PHY_0_D_PI_OUTPUT_CLK_SRC),
.A_PO_OUTPUT_CLK_SRC (PHY_0_A_PO_OUTPUT_CLK_SRC),
.A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.A_PO_OCLKDELAY_INV (PHY_0_A_PO_OCLKDELAY_INV),
.A_OF_ARRAY_MODE (PHY_0_A_OF_ARRAY_MODE),
.B_OF_ARRAY_MODE (PHY_0_B_OF_ARRAY_MODE),
.C_OF_ARRAY_MODE (PHY_0_C_OF_ARRAY_MODE),
.D_OF_ARRAY_MODE (PHY_0_D_OF_ARRAY_MODE),
.A_IF_ARRAY_MODE (PHY_0_A_IF_ARRAY_MODE),
.B_IF_ARRAY_MODE (PHY_0_B_IF_ARRAY_MODE),
.C_IF_ARRAY_MODE (PHY_0_C_IF_ARRAY_MODE),
.D_IF_ARRAY_MODE (PHY_0_D_IF_ARRAY_MODE),
.A_OS_DATA_RATE (PHY_0_A_OSERDES_DATA_RATE),
.A_OS_DATA_WIDTH (PHY_0_A_OSERDES_DATA_WIDTH),
.B_OS_DATA_RATE (PHY_0_B_OSERDES_DATA_RATE),
.B_OS_DATA_WIDTH (PHY_0_B_OSERDES_DATA_WIDTH),
.C_OS_DATA_RATE (PHY_0_C_OSERDES_DATA_RATE),
.C_OS_DATA_WIDTH (PHY_0_C_OSERDES_DATA_WIDTH),
.D_OS_DATA_RATE (PHY_0_D_OSERDES_DATA_RATE),
.D_OS_DATA_WIDTH (PHY_0_D_OSERDES_DATA_WIDTH),
.A_IDELAYE2_IDELAY_TYPE (PHY_0_A_IDELAYE2_IDELAY_TYPE),
.A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
u_ddr_phy_4lanes
(
.rst (rst),
.phy_clk (phy_clk_split0),
.phy_ctl_clk (phy_ctl_clk_split0),
.phy_ctl_wd (phy_ctl_wd_split0),
.data_offset (phy_ctl_wd_split0[PC_DATA_OFFSET_RANGE_HI : PC_DATA_OFFSET_RANGE_LO]),
.phy_ctl_wr (phy_ctl_wr_split0),
.mem_refclk (mem_refclk_split),
.freq_refclk (freq_refclk_split),
.mem_refclk_div4 (mem_refclk_div4_split),
.sync_pulse (sync_pulse_split),
.phy_dout (phy_dout_split0[HIGHEST_LANE_B0*80-1:0]),
.phy_cmd_wr_en (phy_cmd_wr_en_split0),
.phy_data_wr_en (phy_data_wr_en_split0),
.phy_rd_en (phy_rd_en_split0),
.pll_lock (pll_lock),
.ddr_clk (ddr_clk_w[0]),
.rclk (),
.rst_out (rst_out_w[0]),
.mcGo (mcGo_w[0]),
.ref_dll_lock (ref_dll_lock_w[0]),
.idelayctrl_refclk (idelayctrl_refclk),
.idelay_inc (idelay_inc),
.idelay_ce (idelay_ce),
.idelay_ld (idelay_ld),
.phy_ctl_mstr_empty (phy_ctl_mstr_empty),
.if_rst (if_rst),
.if_empty_def (if_empty_def),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks[1:0]),
.if_a_empty (if_a_empty_v[0]),
.if_empty (if_empty_v[0]),
.byte_rd_en (byte_rd_en_v[0]),
.if_empty_or (if_empty_or_v[0]),
.if_empty_and (if_empty_and_v[0]),
.of_ctl_a_full (of_ctl_a_full_v[0]),
.of_data_a_full (of_data_a_full_v[0]),
.of_ctl_full (of_ctl_full_v[0]),
.of_data_full (of_data_full_v[0]),
.pre_data_a_full (pre_data_a_full_v[0]),
.phy_din (phy_din[HIGHEST_LANE_B0*80-1:0]),
.phy_ctl_a_full (_phy_ctl_a_full_p[0]),
.phy_ctl_full (_phy_ctl_full_p[0]),
.phy_ctl_empty (phy_ctl_empty[0]),
.mem_dq_out (mem_dq_out[HIGHEST_LANE_B0*12-1:0]),
.mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B0*12-1:0]),
.mem_dq_in (mem_dq_in[HIGHEST_LANE_B0*10-1:0]),
.mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B0-1:0]),
.mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B0-1:0]),
.mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B0-1:0]),
.aux_out (aux_out_[3:0]),
.phy_ctl_ready (phy_ctl_ready_w[0]),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
// .scan_test_bus_A (scan_test_bus_A),
// .scan_test_bus_B (),
// .scan_test_bus_C (),
// .scan_test_bus_D (),
.phyGo (phyGo),
.input_sink (input_sink),
.calib_sel (calib_sel_byte0),
.calib_zero_ctrl (calib_zero_ctrl[0]),
.calib_zero_lanes (calib_zero_lanes_int[3:0]),
.calib_in_common (calib_in_common),
.po_coarse_enable (po_coarse_enable[0]),
.po_fine_enable (po_fine_enable[0]),
.po_fine_inc (po_fine_inc[0]),
.po_coarse_inc (po_coarse_inc[0]),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[0]),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (po_coarse_overflow_w[0]),
.po_fine_overflow (po_fine_overflow_w[0]),
.po_counter_read_val (po_counter_read_val_w[0]),
.pi_rst_dqs_find (pi_rst_dqs_find[0]),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (pi_fine_overflow_w[0]),
.pi_counter_read_val (pi_counter_read_val_w[0]),
.pi_dqs_found (pi_dqs_found_w[0]),
.pi_dqs_found_all (pi_dqs_found_all_w[0]),
.pi_dqs_found_any (pi_dqs_found_any_w[0]),
.pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B0-1:0]),
.pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B0-1:0]),
.pi_dqs_out_of_range (pi_dqs_out_of_range_w[0]),
.pi_phase_locked (pi_phase_locked_w[0]),
.pi_phase_locked_all (pi_phase_locked_all_w[0]),
.fine_delay (fine_delay),
.fine_delay_sel (fine_delay_sel)
);
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[0] <= #100 0;
aux_out[2] <= #100 0;
end
else begin
aux_out[0] <= #100 aux_out_[0];
aux_out[2] <= #100 aux_out_[2];
end
end
if ( LP_RCLK_SELECT_EDGE[0]) begin
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[1] <= #100 0;
aux_out[3] <= #100 0;
end
else begin
aux_out[1] <= #100 aux_out_[1];
aux_out[3] <= #100 aux_out_[3];
end
end
end
else begin
always @(negedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[1] <= #100 0;
aux_out[3] <= #100 0;
end
else begin
aux_out[1] <= #100 aux_out_[1];
aux_out[3] <= #100 aux_out_[3];
end
end
end
end
else begin
if ( HIGHEST_BANK > 0) begin
assign phy_din[HIGHEST_LANE_B0*80-1:0] = 0;
assign _phy_ctl_a_full_p[0] = 0;
assign of_ctl_a_full_v[0] = 0;
assign of_ctl_full_v[0] = 0;
assign of_data_a_full_v[0] = 0;
assign of_data_full_v[0] = 0;
assign pre_data_a_full_v[0] = 0;
assign if_empty_v[0] = 0;
assign byte_rd_en_v[0] = 1;
always @(*)
aux_out[3:0] = 0;
end
assign pi_dqs_found_w[0] = 1;
assign pi_dqs_found_all_w[0] = 1;
assign pi_dqs_found_any_w[0] = 0;
assign pi_phase_locked_lanes[HIGHEST_LANE_B0-1:0] = 4'b1111;
assign pi_dqs_found_lanes[HIGHEST_LANE_B0-1:0] = 4'b1111;
assign pi_dqs_out_of_range_w[0] = 0;
assign pi_phase_locked_w[0] = 1;
assign po_fine_overflow_w[0] = 0;
assign po_coarse_overflow_w[0] = 0;
assign po_fine_overflow_w[0] = 0;
assign pi_fine_overflow_w[0] = 0;
assign po_counter_read_val_w[0] = 0;
assign pi_counter_read_val_w[0] = 0;
assign mcGo_w[0] = 1;
if ( RCLK_SELECT_BANK == 0)
always @(*)
aux_out[3:0] = 0;
end
if ( BYTE_LANES_B1 != 0) begin : ddr_phy_4lanes_1
mig_7series_v2_3_ddr_phy_4lanes #
(
.BYTE_LANES (BYTE_LANES_B1), /* four bits, one per lanes */
.DATA_CTL_N (PHY_1_DATA_CTL), /* four bits, one per lane */
.PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),
.PO_FINE_DELAY (L_PHY_1_PO_FINE_DELAY),
.BITLANES (PHY_1_BITLANES),
.BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY),
.BYTELANES_DDR_CK (LP_PHY_1_BYTELANES_DDR_CK),
.LAST_BANK (PHY_1_IS_LAST_BANK ),
.LANE_REMAP (PHY_1_LANE_REMAP),
.OF_ALMOST_FULL_VALUE (PHY_1_OF_ALMOST_FULL_VALUE),
.IF_ALMOST_EMPTY_VALUE (PHY_1_IF_ALMOST_EMPTY_VALUE),
.GENERATE_IDELAYCTRL (PHY_1_GENERATE_IDELAYCTRL),
.IODELAY_GRP (PHY_1_IODELAY_GRP),
.BANK_TYPE (BANK_TYPE),
.NUM_DDR_CK (NUM_DDR_CK),
.TCK (TCK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.PC_CLK_RATIO (PHY_CLK_RATIO),
.PC_EVENTS_DELAY (PHY_EVENTS_DELAY),
.PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),
.PC_BURST_MODE (PHY_1_A_BURST_MODE),
.PC_SYNC_MODE (PHY_SYNC_MODE),
.PC_MULTI_REGION (PHY_MULTI_REGION),
.PC_PHY_COUNT_EN (PHY_COUNT_EN),
.PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),
.PC_CMD_OFFSET (PHY_1_CMD_OFFSET),
.PC_RD_CMD_OFFSET_0 (PHY_1_RD_CMD_OFFSET_0),
.PC_RD_CMD_OFFSET_1 (PHY_1_RD_CMD_OFFSET_1),
.PC_RD_CMD_OFFSET_2 (PHY_1_RD_CMD_OFFSET_2),
.PC_RD_CMD_OFFSET_3 (PHY_1_RD_CMD_OFFSET_3),
.PC_RD_DURATION_0 (PHY_1_RD_DURATION_0),
.PC_RD_DURATION_1 (PHY_1_RD_DURATION_1),
.PC_RD_DURATION_2 (PHY_1_RD_DURATION_2),
.PC_RD_DURATION_3 (PHY_1_RD_DURATION_3),
.PC_WR_CMD_OFFSET_0 (PHY_1_WR_CMD_OFFSET_0),
.PC_WR_CMD_OFFSET_1 (PHY_1_WR_CMD_OFFSET_1),
.PC_WR_CMD_OFFSET_2 (PHY_1_WR_CMD_OFFSET_2),
.PC_WR_CMD_OFFSET_3 (PHY_1_WR_CMD_OFFSET_3),
.PC_WR_DURATION_0 (PHY_1_WR_DURATION_0),
.PC_WR_DURATION_1 (PHY_1_WR_DURATION_1),
.PC_WR_DURATION_2 (PHY_1_WR_DURATION_2),
.PC_WR_DURATION_3 (PHY_1_WR_DURATION_3),
.PC_AO_WRLVL_EN (PHY_1_AO_WRLVL_EN),
.PC_AO_TOGGLE (PHY_1_AO_TOGGLE),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.A_PI_FINE_DELAY (L_PHY_1_A_PI_FINE_DELAY),
.B_PI_FINE_DELAY (L_PHY_1_B_PI_FINE_DELAY),
.C_PI_FINE_DELAY (L_PHY_1_C_PI_FINE_DELAY),
.D_PI_FINE_DELAY (L_PHY_1_D_PI_FINE_DELAY),
.A_PI_FREQ_REF_DIV (PHY_1_A_PI_FREQ_REF_DIV),
.A_PI_BURST_MODE (PHY_1_A_BURST_MODE),
.A_PI_OUTPUT_CLK_SRC (L_PHY_1_A_PI_OUTPUT_CLK_SRC),
.B_PI_OUTPUT_CLK_SRC (L_PHY_1_B_PI_OUTPUT_CLK_SRC),
.C_PI_OUTPUT_CLK_SRC (L_PHY_1_C_PI_OUTPUT_CLK_SRC),
.D_PI_OUTPUT_CLK_SRC (L_PHY_1_D_PI_OUTPUT_CLK_SRC),
.A_PO_OUTPUT_CLK_SRC (PHY_1_A_PO_OUTPUT_CLK_SRC),
.A_PO_OCLK_DELAY (PHY_1_A_PO_OCLK_DELAY),
.A_PO_OCLKDELAY_INV (PHY_1_A_PO_OCLKDELAY_INV),
.A_OF_ARRAY_MODE (PHY_1_A_OF_ARRAY_MODE),
.B_OF_ARRAY_MODE (PHY_1_B_OF_ARRAY_MODE),
.C_OF_ARRAY_MODE (PHY_1_C_OF_ARRAY_MODE),
.D_OF_ARRAY_MODE (PHY_1_D_OF_ARRAY_MODE),
.A_IF_ARRAY_MODE (PHY_1_A_IF_ARRAY_MODE),
.B_IF_ARRAY_MODE (PHY_1_B_IF_ARRAY_MODE),
.C_IF_ARRAY_MODE (PHY_1_C_IF_ARRAY_MODE),
.D_IF_ARRAY_MODE (PHY_1_D_IF_ARRAY_MODE),
.A_OS_DATA_RATE (PHY_1_A_OSERDES_DATA_RATE),
.A_OS_DATA_WIDTH (PHY_1_A_OSERDES_DATA_WIDTH),
.B_OS_DATA_RATE (PHY_1_B_OSERDES_DATA_RATE),
.B_OS_DATA_WIDTH (PHY_1_B_OSERDES_DATA_WIDTH),
.C_OS_DATA_RATE (PHY_1_C_OSERDES_DATA_RATE),
.C_OS_DATA_WIDTH (PHY_1_C_OSERDES_DATA_WIDTH),
.D_OS_DATA_RATE (PHY_1_D_OSERDES_DATA_RATE),
.D_OS_DATA_WIDTH (PHY_1_D_OSERDES_DATA_WIDTH),
.A_IDELAYE2_IDELAY_TYPE (PHY_1_A_IDELAYE2_IDELAY_TYPE),
.A_IDELAYE2_IDELAY_VALUE (PHY_1_A_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
u_ddr_phy_4lanes
(
.rst (rst),
.phy_clk (phy_clk_split1),
.phy_ctl_clk (phy_ctl_clk_split1),
.phy_ctl_wd (phy_ctl_wd_split1),
.data_offset (phy_data_offset_1_split1),
.phy_ctl_wr (phy_ctl_wr_split1),
.mem_refclk (mem_refclk_split),
.freq_refclk (freq_refclk_split),
.mem_refclk_div4 (mem_refclk_div4_split),
.sync_pulse (sync_pulse_split),
.phy_dout (phy_dout_split1[HIGHEST_LANE_B1*80+320-1:320]),
.phy_cmd_wr_en (phy_cmd_wr_en_split1),
.phy_data_wr_en (phy_data_wr_en_split1),
.phy_rd_en (phy_rd_en_split1),
.pll_lock (pll_lock),
.ddr_clk (ddr_clk_w[1]),
.rclk (),
.rst_out (rst_out_w[1]),
.mcGo (mcGo_w[1]),
.ref_dll_lock (ref_dll_lock_w[1]),
.idelayctrl_refclk (idelayctrl_refclk),
.idelay_inc (idelay_inc),
.idelay_ce (idelay_ce),
.idelay_ld (idelay_ld),
.phy_ctl_mstr_empty (phy_ctl_mstr_empty),
.if_rst (if_rst),
.if_empty_def (if_empty_def),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks[3:2]),
.if_a_empty (if_a_empty_v[1]),
.if_empty (if_empty_v[1]),
.byte_rd_en (byte_rd_en_v[1]),
.if_empty_or (if_empty_or_v[1]),
.if_empty_and (if_empty_and_v[1]),
.of_ctl_a_full (of_ctl_a_full_v[1]),
.of_data_a_full (of_data_a_full_v[1]),
.of_ctl_full (of_ctl_full_v[1]),
.of_data_full (of_data_full_v[1]),
.pre_data_a_full (pre_data_a_full_v[1]),
.phy_din (phy_din[HIGHEST_LANE_B1*80+320-1:320]),
.phy_ctl_a_full (_phy_ctl_a_full_p[1]),
.phy_ctl_full (_phy_ctl_full_p[1]),
.phy_ctl_empty (phy_ctl_empty[1]),
.mem_dq_out (mem_dq_out[HIGHEST_LANE_B1*12+48-1:48]),
.mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B1*12+48-1:48]),
.mem_dq_in (mem_dq_in[HIGHEST_LANE_B1*10+40-1:40]),
.mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B1+4-1:4]),
.mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B1+4-1:4]),
.mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B1+4-1:4]),
.aux_out (aux_out_[7:4]),
.phy_ctl_ready (phy_ctl_ready_w[1]),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
// .scan_test_bus_A (scan_test_bus_A),
// .scan_test_bus_B (),
// .scan_test_bus_C (),
// .scan_test_bus_D (),
.phyGo (phyGo),
.input_sink (input_sink),
.calib_sel (calib_sel_byte1),
.calib_zero_ctrl (calib_zero_ctrl[1]),
.calib_zero_lanes (calib_zero_lanes_int[7:4]),
.calib_in_common (calib_in_common),
.po_coarse_enable (po_coarse_enable[1]),
.po_fine_enable (po_fine_enable[1]),
.po_fine_inc (po_fine_inc[1]),
.po_coarse_inc (po_coarse_inc[1]),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[1]),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (po_coarse_overflow_w[1]),
.po_fine_overflow (po_fine_overflow_w[1]),
.po_counter_read_val (po_counter_read_val_w[1]),
.pi_rst_dqs_find (pi_rst_dqs_find[1]),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (pi_fine_overflow_w[1]),
.pi_counter_read_val (pi_counter_read_val_w[1]),
.pi_dqs_found (pi_dqs_found_w[1]),
.pi_dqs_found_all (pi_dqs_found_all_w[1]),
.pi_dqs_found_any (pi_dqs_found_any_w[1]),
.pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B1+4-1:4]),
.pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B1+4-1:4]),
.pi_dqs_out_of_range (pi_dqs_out_of_range_w[1]),
.pi_phase_locked (pi_phase_locked_w[1]),
.pi_phase_locked_all (pi_phase_locked_all_w[1]),
.fine_delay (fine_delay),
.fine_delay_sel (fine_delay_sel)
);
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[4] <= #100 0;
aux_out[6] <= #100 0;
end
else begin
aux_out[4] <= #100 aux_out_[4];
aux_out[6] <= #100 aux_out_[6];
end
end
if ( LP_RCLK_SELECT_EDGE[1]) begin
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[5] <= #100 0;
aux_out[7] <= #100 0;
end
else begin
aux_out[5] <= #100 aux_out_[5];
aux_out[7] <= #100 aux_out_[7];
end
end
end
else begin
always @(negedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[5] <= #100 0;
aux_out[7] <= #100 0;
end
else begin
aux_out[5] <= #100 aux_out_[5];
aux_out[7] <= #100 aux_out_[7];
end
end
end
end
else begin
if ( HIGHEST_BANK > 1) begin
assign phy_din[HIGHEST_LANE_B1*80+320-1:320] = 0;
assign _phy_ctl_a_full_p[1] = 0;
assign of_ctl_a_full_v[1] = 0;
assign of_ctl_full_v[1] = 0;
assign of_data_a_full_v[1] = 0;
assign of_data_full_v[1] = 0;
assign pre_data_a_full_v[1] = 0;
assign if_empty_v[1] = 0;
assign byte_rd_en_v[1] = 1;
assign pi_phase_locked_lanes[HIGHEST_LANE_B1+4-1:4] = 4'b1111;
assign pi_dqs_found_lanes[HIGHEST_LANE_B1+4-1:4] = 4'b1111;
always @(*)
aux_out[7:4] = 0;
end
assign pi_dqs_found_w[1] = 1;
assign pi_dqs_found_all_w[1] = 1;
assign pi_dqs_found_any_w[1] = 0;
assign pi_dqs_out_of_range_w[1] = 0;
assign pi_phase_locked_w[1] = 1;
assign po_coarse_overflow_w[1] = 0;
assign po_fine_overflow_w[1] = 0;
assign pi_fine_overflow_w[1] = 0;
assign po_counter_read_val_w[1] = 0;
assign pi_counter_read_val_w[1] = 0;
assign mcGo_w[1] = 1;
end
if ( BYTE_LANES_B2 != 0) begin : ddr_phy_4lanes_2
mig_7series_v2_3_ddr_phy_4lanes #
(
.BYTE_LANES (BYTE_LANES_B2), /* four bits, one per lanes */
.DATA_CTL_N (PHY_2_DATA_CTL), /* four bits, one per lane */
.PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),
.PO_FINE_DELAY (L_PHY_2_PO_FINE_DELAY),
.BITLANES (PHY_2_BITLANES),
.BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY),
.BYTELANES_DDR_CK (LP_PHY_2_BYTELANES_DDR_CK),
.LAST_BANK (PHY_2_IS_LAST_BANK ),
.LANE_REMAP (PHY_2_LANE_REMAP),
.OF_ALMOST_FULL_VALUE (PHY_2_OF_ALMOST_FULL_VALUE),
.IF_ALMOST_EMPTY_VALUE (PHY_2_IF_ALMOST_EMPTY_VALUE),
.GENERATE_IDELAYCTRL (PHY_2_GENERATE_IDELAYCTRL),
.IODELAY_GRP (PHY_2_IODELAY_GRP),
.BANK_TYPE (BANK_TYPE),
.NUM_DDR_CK (NUM_DDR_CK),
.TCK (TCK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.PC_CLK_RATIO (PHY_CLK_RATIO),
.PC_EVENTS_DELAY (PHY_EVENTS_DELAY),
.PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),
.PC_BURST_MODE (PHY_2_A_BURST_MODE),
.PC_SYNC_MODE (PHY_SYNC_MODE),
.PC_MULTI_REGION (PHY_MULTI_REGION),
.PC_PHY_COUNT_EN (PHY_COUNT_EN),
.PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),
.PC_CMD_OFFSET (PHY_2_CMD_OFFSET),
.PC_RD_CMD_OFFSET_0 (PHY_2_RD_CMD_OFFSET_0),
.PC_RD_CMD_OFFSET_1 (PHY_2_RD_CMD_OFFSET_1),
.PC_RD_CMD_OFFSET_2 (PHY_2_RD_CMD_OFFSET_2),
.PC_RD_CMD_OFFSET_3 (PHY_2_RD_CMD_OFFSET_3),
.PC_RD_DURATION_0 (PHY_2_RD_DURATION_0),
.PC_RD_DURATION_1 (PHY_2_RD_DURATION_1),
.PC_RD_DURATION_2 (PHY_2_RD_DURATION_2),
.PC_RD_DURATION_3 (PHY_2_RD_DURATION_3),
.PC_WR_CMD_OFFSET_0 (PHY_2_WR_CMD_OFFSET_0),
.PC_WR_CMD_OFFSET_1 (PHY_2_WR_CMD_OFFSET_1),
.PC_WR_CMD_OFFSET_2 (PHY_2_WR_CMD_OFFSET_2),
.PC_WR_CMD_OFFSET_3 (PHY_2_WR_CMD_OFFSET_3),
.PC_WR_DURATION_0 (PHY_2_WR_DURATION_0),
.PC_WR_DURATION_1 (PHY_2_WR_DURATION_1),
.PC_WR_DURATION_2 (PHY_2_WR_DURATION_2),
.PC_WR_DURATION_3 (PHY_2_WR_DURATION_3),
.PC_AO_WRLVL_EN (PHY_2_AO_WRLVL_EN),
.PC_AO_TOGGLE (PHY_2_AO_TOGGLE),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.A_PI_FINE_DELAY (L_PHY_2_A_PI_FINE_DELAY),
.B_PI_FINE_DELAY (L_PHY_2_B_PI_FINE_DELAY),
.C_PI_FINE_DELAY (L_PHY_2_C_PI_FINE_DELAY),
.D_PI_FINE_DELAY (L_PHY_2_D_PI_FINE_DELAY),
.A_PI_FREQ_REF_DIV (PHY_2_A_PI_FREQ_REF_DIV),
.A_PI_BURST_MODE (PHY_2_A_BURST_MODE),
.A_PI_OUTPUT_CLK_SRC (L_PHY_2_A_PI_OUTPUT_CLK_SRC),
.B_PI_OUTPUT_CLK_SRC (L_PHY_2_B_PI_OUTPUT_CLK_SRC),
.C_PI_OUTPUT_CLK_SRC (L_PHY_2_C_PI_OUTPUT_CLK_SRC),
.D_PI_OUTPUT_CLK_SRC (L_PHY_2_D_PI_OUTPUT_CLK_SRC),
.A_PO_OUTPUT_CLK_SRC (PHY_2_A_PO_OUTPUT_CLK_SRC),
.A_PO_OCLK_DELAY (PHY_2_A_PO_OCLK_DELAY),
.A_PO_OCLKDELAY_INV (PHY_2_A_PO_OCLKDELAY_INV),
.A_OF_ARRAY_MODE (PHY_2_A_OF_ARRAY_MODE),
.B_OF_ARRAY_MODE (PHY_2_B_OF_ARRAY_MODE),
.C_OF_ARRAY_MODE (PHY_2_C_OF_ARRAY_MODE),
.D_OF_ARRAY_MODE (PHY_2_D_OF_ARRAY_MODE),
.A_IF_ARRAY_MODE (PHY_2_A_IF_ARRAY_MODE),
.B_IF_ARRAY_MODE (PHY_2_B_IF_ARRAY_MODE),
.C_IF_ARRAY_MODE (PHY_2_C_IF_ARRAY_MODE),
.D_IF_ARRAY_MODE (PHY_2_D_IF_ARRAY_MODE),
.A_OS_DATA_RATE (PHY_2_A_OSERDES_DATA_RATE),
.A_OS_DATA_WIDTH (PHY_2_A_OSERDES_DATA_WIDTH),
.B_OS_DATA_RATE (PHY_2_B_OSERDES_DATA_RATE),
.B_OS_DATA_WIDTH (PHY_2_B_OSERDES_DATA_WIDTH),
.C_OS_DATA_RATE (PHY_2_C_OSERDES_DATA_RATE),
.C_OS_DATA_WIDTH (PHY_2_C_OSERDES_DATA_WIDTH),
.D_OS_DATA_RATE (PHY_2_D_OSERDES_DATA_RATE),
.D_OS_DATA_WIDTH (PHY_2_D_OSERDES_DATA_WIDTH),
.A_IDELAYE2_IDELAY_TYPE (PHY_2_A_IDELAYE2_IDELAY_TYPE),
.A_IDELAYE2_IDELAY_VALUE (PHY_2_A_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
u_ddr_phy_4lanes
(
.rst (rst),
.phy_clk (phy_clk_split2),
.phy_ctl_clk (phy_ctl_clk_split2),
.phy_ctl_wd (phy_ctl_wd_split2),
.data_offset (phy_data_offset_2_split2),
.phy_ctl_wr (phy_ctl_wr_split2),
.mem_refclk (mem_refclk_split),
.freq_refclk (freq_refclk_split),
.mem_refclk_div4 (mem_refclk_div4_split),
.sync_pulse (sync_pulse_split),
.phy_dout (phy_dout_split2[HIGHEST_LANE_B2*80+640-1:640]),
.phy_cmd_wr_en (phy_cmd_wr_en_split2),
.phy_data_wr_en (phy_data_wr_en_split2),
.phy_rd_en (phy_rd_en_split2),
.pll_lock (pll_lock),
.ddr_clk (ddr_clk_w[2]),
.rclk (),
.rst_out (rst_out_w[2]),
.mcGo (mcGo_w[2]),
.ref_dll_lock (ref_dll_lock_w[2]),
.idelayctrl_refclk (idelayctrl_refclk),
.idelay_inc (idelay_inc),
.idelay_ce (idelay_ce),
.idelay_ld (idelay_ld),
.phy_ctl_mstr_empty (phy_ctl_mstr_empty),
.if_rst (if_rst),
.if_empty_def (if_empty_def),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks[5:4]),
.if_a_empty (if_a_empty_v[2]),
.if_empty (if_empty_v[2]),
.byte_rd_en (byte_rd_en_v[2]),
.if_empty_or (if_empty_or_v[2]),
.if_empty_and (if_empty_and_v[2]),
.of_ctl_a_full (of_ctl_a_full_v[2]),
.of_data_a_full (of_data_a_full_v[2]),
.of_ctl_full (of_ctl_full_v[2]),
.of_data_full (of_data_full_v[2]),
.pre_data_a_full (pre_data_a_full_v[2]),
.phy_din (phy_din[HIGHEST_LANE_B2*80+640-1:640]),
.phy_ctl_a_full (_phy_ctl_a_full_p[2]),
.phy_ctl_full (_phy_ctl_full_p[2]),
.phy_ctl_empty (phy_ctl_empty[2]),
.mem_dq_out (mem_dq_out[HIGHEST_LANE_B2*12+96-1:96]),
.mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B2*12+96-1:96]),
.mem_dq_in (mem_dq_in[HIGHEST_LANE_B2*10+80-1:80]),
.mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B2-1+8:8]),
.mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B2-1+8:8]),
.mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B2-1+8:8]),
.aux_out (aux_out_[11:8]),
.phy_ctl_ready (phy_ctl_ready_w[2]),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
// .scan_test_bus_A (scan_test_bus_A),
// .scan_test_bus_B (),
// .scan_test_bus_C (),
// .scan_test_bus_D (),
.phyGo (phyGo),
.input_sink (input_sink),
.calib_sel (calib_sel_byte2),
.calib_zero_ctrl (calib_zero_ctrl[2]),
.calib_zero_lanes (calib_zero_lanes_int[11:8]),
.calib_in_common (calib_in_common),
.po_coarse_enable (po_coarse_enable[2]),
.po_fine_enable (po_fine_enable[2]),
.po_fine_inc (po_fine_inc[2]),
.po_coarse_inc (po_coarse_inc[2]),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[2]),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (po_coarse_overflow_w[2]),
.po_fine_overflow (po_fine_overflow_w[2]),
.po_counter_read_val (po_counter_read_val_w[2]),
.pi_rst_dqs_find (pi_rst_dqs_find[2]),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (pi_fine_overflow_w[2]),
.pi_counter_read_val (pi_counter_read_val_w[2]),
.pi_dqs_found (pi_dqs_found_w[2]),
.pi_dqs_found_all (pi_dqs_found_all_w[2]),
.pi_dqs_found_any (pi_dqs_found_any_w[2]),
.pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B2+8-1:8]),
.pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B2+8-1:8]),
.pi_dqs_out_of_range (pi_dqs_out_of_range_w[2]),
.pi_phase_locked (pi_phase_locked_w[2]),
.pi_phase_locked_all (pi_phase_locked_all_w[2]),
.fine_delay (fine_delay),
.fine_delay_sel (fine_delay_sel)
);
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[8] <= #100 0;
aux_out[10] <= #100 0;
end
else begin
aux_out[8] <= #100 aux_out_[8];
aux_out[10] <= #100 aux_out_[10];
end
end
if ( LP_RCLK_SELECT_EDGE[1]) begin
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[9] <= #100 0;
aux_out[11] <= #100 0;
end
else begin
aux_out[9] <= #100 aux_out_[9];
aux_out[11] <= #100 aux_out_[11];
end
end
end
else begin
always @(negedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[9] <= #100 0;
aux_out[11] <= #100 0;
end
else begin
aux_out[9] <= #100 aux_out_[9];
aux_out[11] <= #100 aux_out_[11];
end
end
end
end
else begin
if ( HIGHEST_BANK > 2) begin
assign phy_din[HIGHEST_LANE_B2*80+640-1:640] = 0;
assign _phy_ctl_a_full_p[2] = 0;
assign of_ctl_a_full_v[2] = 0;
assign of_ctl_full_v[2] = 0;
assign of_data_a_full_v[2] = 0;
assign of_data_full_v[2] = 0;
assign pre_data_a_full_v[2] = 0;
assign if_empty_v[2] = 0;
assign byte_rd_en_v[2] = 1;
assign pi_phase_locked_lanes[HIGHEST_LANE_B2+8-1:8] = 4'b1111;
assign pi_dqs_found_lanes[HIGHEST_LANE_B2+8-1:8] = 4'b1111;
always @(*)
aux_out[11:8] = 0;
end
assign pi_dqs_found_w[2] = 1;
assign pi_dqs_found_all_w[2] = 1;
assign pi_dqs_found_any_w[2] = 0;
assign pi_dqs_out_of_range_w[2] = 0;
assign pi_phase_locked_w[2] = 1;
assign po_coarse_overflow_w[2] = 0;
assign po_fine_overflow_w[2] = 0;
assign po_counter_read_val_w[2] = 0;
assign pi_counter_read_val_w[2] = 0;
assign mcGo_w[2] = 1;
end
endgenerate
generate
// for single bank , emit an extra phaser_in to generate rclk
// so that auxout can be placed in another region
// if desired
if ( BYTE_LANES_B1 == 0 && BYTE_LANES_B2 == 0 && RCLK_SELECT_BANK>0)
begin : phaser_in_rclk
localparam L_EXTRA_PI_FINE_DELAY = DEFAULT_RCLK_DELAY;
PHASER_IN_PHY #(
.BURST_MODE ( PHY_0_A_BURST_MODE),
.CLKOUT_DIV ( PHY_0_A_PI_CLKOUT_DIV),
.FREQ_REF_DIV ( PHY_0_A_PI_FREQ_REF_DIV),
.REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS),
.FINE_DELAY ( L_EXTRA_PI_FINE_DELAY),
.OUTPUT_CLK_SRC ( RCLK_PI_OUTPUT_CLK_SRC)
) phaser_in_rclk (
.DQSFOUND (),
.DQSOUTOFRANGE (),
.FINEOVERFLOW (),
.PHASELOCKED (),
.ISERDESRST (),
.ICLKDIV (),
.ICLK (),
.COUNTERREADVAL (),
.RCLK (),
.WRENABLE (),
.BURSTPENDINGPHY (),
.ENCALIBPHY (),
.FINEENABLE (0),
.FREQREFCLK (freq_refclk),
.MEMREFCLK (mem_refclk),
.RANKSELPHY (0),
.PHASEREFCLK (),
.RSTDQSFIND (0),
.RST (rst),
.FINEINC (),
.COUNTERLOADEN (),
.COUNTERREADEN (),
.COUNTERLOADVAL (),
.SYNCIN (sync_pulse),
.SYSCLK (phy_clk)
);
end
endgenerate
always @(*) begin
case (calib_sel[5:3])
3'b000: begin
po_coarse_overflow = po_coarse_overflow_w[0];
po_fine_overflow = po_fine_overflow_w[0];
po_counter_read_val = po_counter_read_val_w[0];
pi_fine_overflow = pi_fine_overflow_w[0];
pi_counter_read_val = pi_counter_read_val_w[0];
pi_phase_locked = pi_phase_locked_w[0];
if ( calib_in_common)
pi_dqs_found = pi_dqs_found_any;
else
pi_dqs_found = pi_dqs_found_w[0];
pi_dqs_out_of_range = pi_dqs_out_of_range_w[0];
end
3'b001: begin
po_coarse_overflow = po_coarse_overflow_w[1];
po_fine_overflow = po_fine_overflow_w[1];
po_counter_read_val = po_counter_read_val_w[1];
pi_fine_overflow = pi_fine_overflow_w[1];
pi_counter_read_val = pi_counter_read_val_w[1];
pi_phase_locked = pi_phase_locked_w[1];
if ( calib_in_common)
pi_dqs_found = pi_dqs_found_any;
else
pi_dqs_found = pi_dqs_found_w[1];
pi_dqs_out_of_range = pi_dqs_out_of_range_w[1];
end
3'b010: begin
po_coarse_overflow = po_coarse_overflow_w[2];
po_fine_overflow = po_fine_overflow_w[2];
po_counter_read_val = po_counter_read_val_w[2];
pi_fine_overflow = pi_fine_overflow_w[2];
pi_counter_read_val = pi_counter_read_val_w[2];
pi_phase_locked = pi_phase_locked_w[2];
if ( calib_in_common)
pi_dqs_found = pi_dqs_found_any;
else
pi_dqs_found = pi_dqs_found_w[2];
pi_dqs_out_of_range = pi_dqs_out_of_range_w[2];
end
default: begin
po_coarse_overflow = 0;
po_fine_overflow = 0;
po_counter_read_val = 0;
pi_fine_overflow = 0;
pi_counter_read_val = 0;
pi_phase_locked = 0;
pi_dqs_found = 0;
pi_dqs_out_of_range = 0;
end
endcase
end
endmodule // mc_phy
|
// This is a component of pluto_servo, a PWM servo driver and quadrature
// counter for emc2
// Copyright 2006 Jeff Epler <[email protected]>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1507 USA
module quad(clk, A, B, Z, zr, out);
parameter W=14;
input clk, A, B, Z, zr;
reg [(W-1):0] c, i; reg zl;
output [2*W:0] out = { zl, i, c };
// reg [(W-1):0] c, i; reg zl;
reg [2:0] Ad, Bd;
reg [2:0] Zc;
always @(posedge clk) Ad <= {Ad[1:0], A};
always @(posedge clk) Bd <= {Bd[1:0], B};
wire good_one = &Zc;
wire good_zero = ~|Zc;
reg last_good;
wire index_pulse = good_one && ! last_good;
wire count_enable = Ad[1] ^ Ad[2] ^ Bd[1] ^ Bd[2];
wire count_direction = Ad[1] ^ Bd[2];
always @(posedge clk)
begin
if(Z && !good_one) Zc <= Zc + 2'b1;
else if(!good_zero) Zc <= Zc - 2'b1;
if(good_one) last_good <= 1;
else if(good_zero) last_good <= 0;
if(count_enable)
begin
if(count_direction) c <= c + 1'd1;
else c <= c - 1'd1;
end
if(index_pulse) begin
i <= c;
zl <= 1;
end else if(zr) begin
zl <= 0;
end
end
endmodule
|
/*
* Copyright (c) 2015, Arch Laboratory
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
module psramcon (
// inputs:
az_addr,
az_be_n,
az_cs,
az_data,
az_rd_n,
az_wr_n,
clk,
reset,
// outputs:
za_data,
za_valid,
za_waitrequest,
PSRAM_CLK,
PSRAM_ADV_N,
PSRAM_CE_N,
PSRAM_OE_N,
PSRAM_WE_N,
PSRAM_LB_N,
PSRAM_UB_N,
PSRAM_DATA,
PSRAM_ADDR
);
output [ 31: 0] za_data;
output za_valid;
output za_waitrequest;
input [ 24: 0] az_addr;
input [ 3: 0] az_be_n;
input az_cs;
input [ 31: 0] az_data;
input az_rd_n;
input az_wr_n;
input clk;
input reset;
output wire PSRAM_CLK;
output wire PSRAM_ADV_N;
output wire PSRAM_CE_N;
output wire PSRAM_OE_N;
output wire PSRAM_WE_N;
output wire PSRAM_LB_N;
output wire PSRAM_UB_N;
inout wire [15:0] PSRAM_DATA;
output wire [22:0] PSRAM_ADDR;
reg [21:0] addr_buf;
reg [31:0] din_buf;
reg [3:0] be_buf;
reg [22:0] addr_16;
reg [15:0] din_16;
reg [1:0] be_16;
reg we_16, re_16;
wire [15:0] dout_16;
wire d_valid_16;
wire busy_16;
wire CLK = clk;
wire RST_X = ~reset;
wire [21:0] ADDR = az_addr[21:0];
wire [31:0] DIN = az_data;
wire WE = ~az_wr_n;
wire RE = ~az_rd_n;
wire [3:0] BE = ~az_be_n;
wire WAITREQUEST;
reg [31:0] DOUT;
reg DVALID;
assign za_waitrequest = WAITREQUEST;
assign za_data = DOUT;
assign za_valid = DVALID;
psramcon_16 psramcon_16(CLK, RST_X, addr_16, addr_16, din_16, we_16, re_16, 2'b11, busy_16, dout_16, d_valid_16,
PSRAM_CLK, PSRAM_ADV_N, PSRAM_CE_N, PSRAM_OE_N, PSRAM_WE_N, PSRAM_LB_N, PSRAM_UB_N, PSRAM_DATA, PSRAM_ADDR);
reg [3:0] state;
parameter IDLE = 0;
parameter W_PHASE0 = 1;
parameter W_PHASE01 = 2;
parameter W_PHASE1 = 3;
parameter W_PHASE11 = 4;
parameter W_PHASE2 = 5;
parameter R_PHASE0 = 6;
parameter R_PHASE1 = 7;
parameter R_PHASE2 = 8;
assign WAITREQUEST = (state != IDLE);
always @(posedge CLK) begin
if(!RST_X) begin
state <= IDLE;
addr_16 <= 0;
din_16 <= 0;
be_16 <= 2'b11;
we_16 <= 0;
re_16 <= 0;
end else begin
case(state)
IDLE: begin
DOUT <= 0;
DVALID <= 0;
state <= (WE) ? W_PHASE0 : (RE) ? R_PHASE0 : IDLE;
addr_buf <= ADDR;
din_buf <= DIN;
be_buf <= BE;
end
W_PHASE0: begin
if(be_buf[1:0] == 2'b11) begin
state <= W_PHASE1;
addr_16 <= {addr_buf, 1'b0};
din_16 <= din_buf[15:0];
we_16 <= 1;
end else begin
state <= W_PHASE01;
addr_16 <= {addr_buf, 1'b0};
re_16 <= 1;
end
end
W_PHASE01: begin
if(busy_16) begin re_16 <= 0; end
else if(d_valid_16) begin
state <= W_PHASE1;
addr_16 <= {addr_buf, 1'b0};
din_16[7:0] <= (be_buf[0]) ? din_buf[7:0] : dout_16[7:0];
din_16[15:8] <= (be_buf[1]) ? din_buf[15:8] : dout_16[15:8];
we_16 <= 1;
end
end
W_PHASE1: begin
if(busy_16) begin we_16 <= 0; end
else if(be_buf[3:2] == 2'b11) begin
state <= W_PHASE2;
addr_16 <= {addr_buf, 1'b1};
din_16 <= din_buf[31:16];
we_16 <= 1;
end else begin
state <= W_PHASE11;
addr_16 <= {addr_buf, 1'b1};
re_16 <= 1;
end
end
W_PHASE11: begin
if(busy_16) begin re_16 <= 0; end
else if(d_valid_16) begin
state <= W_PHASE2;
addr_16 <= {addr_buf, 1'b1};
din_16[7:0] <= (be_buf[2]) ? din_buf[23:16] : dout_16[7:0];
din_16[15:8] <= (be_buf[3]) ? din_buf[31:24] : dout_16[15:8];
we_16 <= 1;
end
end
W_PHASE2: begin
if(busy_16) begin we_16 <= 0; end
else begin
state <= IDLE;
addr_16 <= 0;
din_16 <= 0;
we_16 <= 0;
end
end
R_PHASE0: begin
state <= R_PHASE1;
addr_16 <= {addr_buf, 1'b0};
re_16 <= 1;
end
R_PHASE1: begin
if(busy_16) begin re_16 <= 0; end
else if(d_valid_16) begin
state <= R_PHASE2;
addr_16 <= {addr_buf, 1'b1};
re_16 <= 1;
DOUT[15:0] <= dout_16;
end
end
R_PHASE2: begin
if(busy_16) begin we_16 <= 0; end
else if(d_valid_16) begin
state <= IDLE;
addr_16 <= 0;
re_16 <= 0;
DOUT[31:16] <= dout_16;
DVALID <= 1;
end
end
endcase
end
end
endmodule
/****************************************************************************************/
module psramcon_16(input wire CLK,
input wire RST_X,
input wire [22:0] WADDR, // input write address
input wire [22:0] RADDR, // input read address
input wire [15:0] D_IN, // input data
input wire WE, // write enable
input wire RE, // read enable
input wire [1:0] BE, // byte enable
output wire BUSY, // it's busy during operation
output reg [15:0] RDOUT, // read data
output reg RDOUT_EN, // read data is enable
output wire MCLK, // PSRAM_CLK
output wire ADV_X, // PSRAM_ADV_X
output reg CE_X, // PSRAM_CE_X
output reg OE_X, // PSRAM_OE_X
output reg WE_X, // PSRAM_WE_X
output reg LB_X, // PSRAM_LB_X
output reg UB_X, // PSRAM_UB_X
inout wire [15:0] D_OUT, // PSRAM_DATA
output reg [22:0] A_OUT); // PSRAM_ADDR
parameter IDLE = 0;
parameter W_PHASE0 = 1;
parameter W_PHASE1 = 2;
parameter W_PHASE2 = 3;
parameter W_PHASE3 = 4;
parameter W_PHASE4 = 5;
parameter R_PHASE0 = 6;
parameter R_PHASE1 = 7;
parameter R_PHASE2 = 8;
parameter R_PHASE3 = 9;
parameter R_PHASE4 = 10;
assign MCLK = 0;
assign ADV_X = 0;
assign BUSY = (state != IDLE);
reg [3:0] state;
reg [15:0] D_KEPT;
reg write_mode;
reg read_mode;
always @(negedge CLK) begin
if (!RST_X) begin
A_OUT <= 0;
D_KEPT <= 0;
OE_X <= 1;
WE_X <= 1;
CE_X <= 1;
LB_X <= 0;
UB_X <= 0;
write_mode <= 0;
read_mode <= 0;
state <= IDLE;
RDOUT_EN <= 0;
end else begin
case (state)
/***************************************/
IDLE: begin
RDOUT_EN <= 0;
RDOUT <= 0;
read_mode <= 0;
write_mode <= 0;
state <= (WE) ? W_PHASE0 : (RE) ? R_PHASE0 : state;
A_OUT <= (WE) ? WADDR : (RE) ? RADDR : 0;
D_KEPT <= (WE) ? D_IN : 0;
LB_X <= (WE) ? ~BE[0] : 0;
UB_X <= (WE) ? ~BE[1] : 0;
end
/***** WRITE **********************************/
W_PHASE0: begin
// A_OUT <= WADDR;
// D_KEPT <= D_IN;
CE_X <= 0;
WE_X <= 0;
write_mode <= 1;
state <= W_PHASE1;
end
W_PHASE1: begin
state <= W_PHASE2;
end
W_PHASE2: begin
state <= W_PHASE3;
end
W_PHASE3: begin
state <= W_PHASE4;
end
W_PHASE4: begin
CE_X <= 1;
WE_X <= 1;
write_mode <= 1;
state <= IDLE;
end
/***** READ **********************************/
R_PHASE0: begin
// A_OUT <= RADDR;
CE_X <= 0;
OE_X <= 0;
read_mode <= 1;
state <= R_PHASE1;
end
R_PHASE1: begin
state <= R_PHASE2;
end
R_PHASE2: begin
state <= R_PHASE3;
end
R_PHASE3: begin
state <= R_PHASE4;
end
R_PHASE4: begin
CE_X <= 1;
OE_X <= 1;
read_mode <= 0;
RDOUT_EN <= 1;
RDOUT <= D_OUT;
state <= IDLE;
end
endcase
end
end
assign D_OUT = (write_mode) ? D_KEPT : 16'hzzzz;
endmodule
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
// Date : Fri May 27 06:36:45 2016
// Host : francis-Aspire-E1-570 running 64-bit Ubuntu 15.10
// Command : write_verilog -mode timesim -nolib -sdf_anno true -force -file
// /media/francis/Acer/Users/Francis/Documents/GitHub/Proyecto_De_Graduacion/FPU_FLM/FPU_2.0/FPU_2.0.sim/sim_1/impl/timing/Testbench_FPU_multiplication_time_impl.v
// Design : FPU_Multiplication_Function
// Purpose : This verilog netlist is a timing simulation representation of the design and should not be modified or
// synthesized. Please ensure that this netlist is used with the corresponding SDF file.
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
`define XIL_TIMING
module Adder_Round
(FSM_add_overflow_flag,
D,
Q,
E,
O6,
CLK,
AR,
\Q_reg[46] ,
FSM_Shift_Value,
\Q_reg[0] ,
\Q_reg[0]_0 );
output FSM_add_overflow_flag;
output [22:0]D;
output [0:0]Q;
input [0:0]E;
input [23:0]O6;
input CLK;
input [0:0]AR;
input [23:0]\Q_reg[46] ;
input FSM_Shift_Value;
input \Q_reg[0] ;
input [0:0]\Q_reg[0]_0 ;
wire [0:0]AR;
wire CLK;
wire [22:0]D;
wire [0:0]E;
wire FSM_Shift_Value;
wire FSM_add_overflow_flag;
wire [23:0]O6;
wire [0:0]Q;
wire \Q_reg[0] ;
wire [0:0]\Q_reg[0]_0 ;
wire [23:0]\Q_reg[46] ;
RegisterAdd__parameterized2 Add_Subt_Result
(.AR(AR),
.CLK(CLK),
.D(D),
.E(E),
.FSM_Shift_Value(FSM_Shift_Value),
.Q(Q),
.\Q_reg[0]_0 (\Q_reg[0] ),
.\Q_reg[23]_0 ({O6[22:0],\Q_reg[0]_0 }),
.\Q_reg[46] (\Q_reg[46] ));
RegisterAdd_5 Add_overflow_Result
(.AR(AR),
.CLK(CLK),
.E(E),
.FSM_add_overflow_flag(FSM_add_overflow_flag),
.O6(O6[23]));
endmodule
module Barrel_Shifter_M
(O6,
Q,
\Q_reg[0] ,
E,
D,
clk_IBUF_BUFG,
AR);
output [23:0]O6;
output [22:0]Q;
output [0:0]\Q_reg[0] ;
input [0:0]E;
input [23:0]D;
input clk_IBUF_BUFG;
input [0:0]AR;
wire [0:0]AR;
wire [23:0]D;
wire [0:0]E;
wire [23:0]O6;
wire [22:0]Q;
wire [0:0]\Q_reg[0] ;
wire clk_IBUF_BUFG;
RegisterMult__parameterized3 Output_Reg
(.AR(AR),
.D(D),
.E(E),
.O6(O6),
.Q(Q),
.\Q_reg[0]_0 (\Q_reg[0] ),
.clk_IBUF_BUFG(clk_IBUF_BUFG));
endmodule
module Exp_Operation_m
(underflow_flag_OBUF,
D,
\Q_reg[30] ,
overflow_flag_OBUF,
\Q_reg[3] ,
\Q_reg[0] ,
\Q_reg[0]_0 ,
E,
O,
clk_IBUF_BUFG,
AR,
\Q_reg[0]_1 ,
Q,
\Q_reg[31] ,
\Q_reg[22] ,
\Q_reg[0]_2 ,
\Q_reg[0]_3 ,
\FSM_sequential_state_reg_reg[0] );
output underflow_flag_OBUF;
output [31:0]D;
output [7:0]\Q_reg[30] ;
output overflow_flag_OBUF;
output \Q_reg[3] ;
output \Q_reg[0] ;
output \Q_reg[0]_0 ;
input [0:0]E;
input [1:0]O;
input clk_IBUF_BUFG;
input [0:0]AR;
input \Q_reg[0]_1 ;
input [0:0]Q;
input [1:0]\Q_reg[31] ;
input [22:0]\Q_reg[22] ;
input \Q_reg[0]_2 ;
input [7:0]\Q_reg[0]_3 ;
input [0:0]\FSM_sequential_state_reg_reg[0] ;
wire [0:0]AR;
wire [31:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[0] ;
wire [1:0]O;
wire Overflow_flag_A;
wire [0:0]Q;
wire \Q_reg[0] ;
wire \Q_reg[0]_0 ;
wire \Q_reg[0]_1 ;
wire \Q_reg[0]_2 ;
wire [7:0]\Q_reg[0]_3 ;
wire [22:0]\Q_reg[22] ;
wire [7:0]\Q_reg[30] ;
wire [1:0]\Q_reg[31] ;
wire \Q_reg[3] ;
wire clk_IBUF_BUFG;
wire overflow_flag_OBUF;
wire underflow_flag_OBUF;
RegisterMult__parameterized1 Oflow_A_m
(.AR(AR),
.D(D[31]),
.E(E),
.O(O[1]),
.Overflow_flag_A(Overflow_flag_A),
.Q(Q),
.\Q_reg[0]_0 (underflow_flag_OBUF),
.\Q_reg[31] (\Q_reg[31] [1]),
.\Q_reg[8] (\Q_reg[30] [7]),
.clk_IBUF_BUFG(clk_IBUF_BUFG),
.overflow_flag_OBUF(overflow_flag_OBUF));
RegisterMult__parameterized2 Underflow_m
(.AR(AR),
.D(D[22:0]),
.Overflow_flag_A(Overflow_flag_A),
.Q(\Q_reg[30] [7]),
.\Q_reg[0]_0 (\Q_reg[0] ),
.\Q_reg[0]_1 (\Q_reg[0]_0 ),
.\Q_reg[0]_2 (\Q_reg[0]_1 ),
.\Q_reg[0]_3 ({O[0],\Q_reg[0]_3 [7:2]}),
.\Q_reg[22] (underflow_flag_OBUF),
.\Q_reg[22]_0 (\Q_reg[22] ),
.clk_IBUF_BUFG(clk_IBUF_BUFG));
RegisterMult__parameterized0 exp_result_m
(.AR(AR),
.D(D[30:23]),
.\FSM_sequential_state_reg_reg[0] (\FSM_sequential_state_reg_reg[0] ),
.Overflow_flag_A(Overflow_flag_A),
.Q(\Q_reg[30] ),
.\Q_reg[0]_0 (underflow_flag_OBUF),
.\Q_reg[0]_1 (\Q_reg[0]_2 ),
.\Q_reg[0]_2 ({O[0],\Q_reg[0]_3 }),
.\Q_reg[23] (\Q_reg[31] [0]),
.\Q_reg[3]_0 (\Q_reg[3] ),
.clk_IBUF_BUFG(clk_IBUF_BUFG));
endmodule
(* ECO_CHECKSUM = "447c039b" *) (* EW = "8" *) (* SW = "23" *)
(* W = "32" *)
(* NotValidForBitStream *)
module FPU_Multiplication_Function
(clk,
rst,
beg_FSM,
ack_FSM,
Data_MX,
Data_MY,
round_mode,
overflow_flag,
underflow_flag,
ready,
final_result_ieee);
input clk;
input rst;
input beg_FSM;
input ack_FSM;
input [31:0]Data_MX;
input [31:0]Data_MY;
input [1:0]round_mode;
output overflow_flag;
output underflow_flag;
output ready;
output [31:0]final_result_ieee;
wire Adder_M_n_24;
wire [12:0]B;
wire Barrel_Shifter_module_n_0;
wire Barrel_Shifter_module_n_1;
wire Barrel_Shifter_module_n_10;
wire Barrel_Shifter_module_n_11;
wire Barrel_Shifter_module_n_12;
wire Barrel_Shifter_module_n_13;
wire Barrel_Shifter_module_n_14;
wire Barrel_Shifter_module_n_15;
wire Barrel_Shifter_module_n_16;
wire Barrel_Shifter_module_n_17;
wire Barrel_Shifter_module_n_18;
wire Barrel_Shifter_module_n_19;
wire Barrel_Shifter_module_n_2;
wire Barrel_Shifter_module_n_20;
wire Barrel_Shifter_module_n_21;
wire Barrel_Shifter_module_n_22;
wire Barrel_Shifter_module_n_23;
wire Barrel_Shifter_module_n_24;
wire Barrel_Shifter_module_n_25;
wire Barrel_Shifter_module_n_26;
wire Barrel_Shifter_module_n_27;
wire Barrel_Shifter_module_n_28;
wire Barrel_Shifter_module_n_29;
wire Barrel_Shifter_module_n_3;
wire Barrel_Shifter_module_n_30;
wire Barrel_Shifter_module_n_31;
wire Barrel_Shifter_module_n_32;
wire Barrel_Shifter_module_n_33;
wire Barrel_Shifter_module_n_34;
wire Barrel_Shifter_module_n_35;
wire Barrel_Shifter_module_n_36;
wire Barrel_Shifter_module_n_37;
wire Barrel_Shifter_module_n_38;
wire Barrel_Shifter_module_n_39;
wire Barrel_Shifter_module_n_4;
wire Barrel_Shifter_module_n_40;
wire Barrel_Shifter_module_n_41;
wire Barrel_Shifter_module_n_42;
wire Barrel_Shifter_module_n_43;
wire Barrel_Shifter_module_n_44;
wire Barrel_Shifter_module_n_45;
wire Barrel_Shifter_module_n_46;
wire Barrel_Shifter_module_n_47;
wire Barrel_Shifter_module_n_5;
wire Barrel_Shifter_module_n_6;
wire Barrel_Shifter_module_n_7;
wire Barrel_Shifter_module_n_8;
wire Barrel_Shifter_module_n_9;
wire [10:0]Data_A_i;
wire [31:0]Data_MX;
wire [31:0]Data_MX_IBUF;
wire [31:0]Data_MY;
wire [31:0]Data_MY_IBUF;
wire [23:0]Data_Reg;
wire Exp_module_n_10;
wire Exp_module_n_11;
wire Exp_module_n_12;
wire Exp_module_n_13;
wire Exp_module_n_14;
wire Exp_module_n_15;
wire Exp_module_n_16;
wire Exp_module_n_17;
wire Exp_module_n_18;
wire Exp_module_n_19;
wire Exp_module_n_2;
wire Exp_module_n_20;
wire Exp_module_n_21;
wire Exp_module_n_22;
wire Exp_module_n_23;
wire Exp_module_n_24;
wire Exp_module_n_25;
wire Exp_module_n_26;
wire Exp_module_n_27;
wire Exp_module_n_28;
wire Exp_module_n_29;
wire Exp_module_n_3;
wire Exp_module_n_30;
wire Exp_module_n_31;
wire Exp_module_n_32;
wire Exp_module_n_34;
wire Exp_module_n_35;
wire Exp_module_n_36;
wire Exp_module_n_37;
wire Exp_module_n_38;
wire Exp_module_n_39;
wire Exp_module_n_4;
wire Exp_module_n_40;
wire Exp_module_n_42;
wire Exp_module_n_43;
wire Exp_module_n_44;
wire Exp_module_n_5;
wire Exp_module_n_6;
wire Exp_module_n_7;
wire Exp_module_n_8;
wire Exp_module_n_9;
wire FSM_Shift_Value;
wire FSM_add_overflow_flag;
wire FSM_adder_round_norm_load;
wire FSM_barrel_shifter_load;
wire FSM_exp_operation_A_S;
wire FSM_exp_operation_load_result;
wire FSM_final_result_load;
wire FSM_load_second_step;
wire FSM_round_flag;
wire FS_Module_n_10;
wire FS_Module_n_11;
wire FS_Module_n_12;
wire FS_Module_n_2;
wire FS_Module_n_3;
wire FS_Module_n_4;
wire FS_Module_n_5;
wire FS_Module_n_6;
wire FS_Module_n_7;
wire FS_Module_n_8;
wire FS_Module_n_9;
wire [31:31]Op_MX;
wire [31:31]Op_MY;
wire Operands_load_reg_n_14;
wire Operands_load_reg_n_15;
wire Operands_load_reg_n_16;
wire Operands_load_reg_n_17;
wire Operands_load_reg_n_18;
wire Operands_load_reg_n_19;
wire Operands_load_reg_n_20;
wire Operands_load_reg_n_21;
wire Operands_load_reg_n_22;
wire Operands_load_reg_n_23;
wire Operands_load_reg_n_24;
wire Operands_load_reg_n_25;
wire Operands_load_reg_n_26;
wire Operands_load_reg_n_27;
wire Operands_load_reg_n_28;
wire Operands_load_reg_n_29;
wire Operands_load_reg_n_30;
wire Operands_load_reg_n_31;
wire Operands_load_reg_n_32;
wire Operands_load_reg_n_33;
wire Operands_load_reg_n_34;
wire Operands_load_reg_n_35;
wire Operands_load_reg_n_36;
wire Operands_load_reg_n_37;
wire Operands_load_reg_n_38;
wire Operands_load_reg_n_39;
wire Operands_load_reg_n_40;
wire Operands_load_reg_n_41;
wire Operands_load_reg_n_42;
wire Operands_load_reg_n_43;
wire Operands_load_reg_n_44;
wire Operands_load_reg_n_45;
wire Operands_load_reg_n_46;
wire Operands_load_reg_n_48;
wire Operands_load_reg_n_49;
wire Operands_load_reg_n_50;
wire Operands_load_reg_n_51;
wire Operands_load_reg_n_52;
wire Operands_load_reg_n_53;
wire Operands_load_reg_n_54;
wire Operands_load_reg_n_55;
wire Operands_load_reg_n_67;
wire Operands_load_reg_n_68;
wire Operands_load_reg_n_69;
wire Operands_load_reg_n_70;
wire Operands_load_reg_n_71;
wire Operands_load_reg_n_72;
wire Operands_load_reg_n_73;
wire Operands_load_reg_n_74;
wire Operands_load_reg_n_75;
wire Operands_load_reg_n_76;
wire Operands_load_reg_n_77;
wire Operands_load_reg_n_78;
wire Operands_load_reg_n_79;
wire [47:47]P_Sgf;
wire Sel_A_n_0;
wire Sel_A_n_1;
wire Sel_A_n_2;
wire Sel_B_n_0;
wire Sel_B_n_1;
wire Sel_B_n_2;
wire Sel_B_n_3;
wire Sel_B_n_4;
wire Sel_B_n_5;
wire Sel_B_n_6;
wire Sel_B_n_7;
wire Sel_B_n_8;
wire Sel_C_n_0;
wire Sgf_operation_n_10;
wire Sgf_operation_n_11;
wire Sgf_operation_n_12;
wire Sgf_operation_n_13;
wire Sgf_operation_n_14;
wire Sgf_operation_n_15;
wire Sgf_operation_n_16;
wire Sgf_operation_n_17;
wire Sgf_operation_n_18;
wire Sgf_operation_n_19;
wire Sgf_operation_n_2;
wire Sgf_operation_n_20;
wire Sgf_operation_n_21;
wire Sgf_operation_n_22;
wire Sgf_operation_n_23;
wire Sgf_operation_n_24;
wire Sgf_operation_n_25;
wire Sgf_operation_n_3;
wire Sgf_operation_n_4;
wire Sgf_operation_n_5;
wire Sgf_operation_n_6;
wire Sgf_operation_n_7;
wire Sgf_operation_n_8;
wire Sgf_operation_n_9;
wire Sign_S_mux;
wire ack_FSM;
wire ack_FSM_IBUF;
wire beg_FSM;
wire beg_FSM_IBUF;
wire clk;
wire clk_IBUF;
wire clk_IBUF_BUFG;
wire [8:8]exp_oper_result;
wire [31:0]final_result_ieee;
wire [31:0]final_result_ieee_OBUF;
wire overflow_flag;
wire overflow_flag_OBUF;
wire ready;
wire ready_OBUF;
wire [1:0]round_mode;
wire [1:0]round_mode_IBUF;
wire rst;
wire rst_IBUF;
wire underflow_flag;
wire underflow_flag_OBUF;
wire zero_flag;
initial begin
$sdf_annotate("Testbench_FPU_multiplication_time_impl.sdf",,,,"tool_control");
end
Adder_Round Adder_M
(.AR(FS_Module_n_9),
.CLK(clk_IBUF_BUFG),
.D(Data_Reg[22:0]),
.E(FSM_adder_round_norm_load),
.FSM_Shift_Value(FSM_Shift_Value),
.FSM_add_overflow_flag(FSM_add_overflow_flag),
.O6({Barrel_Shifter_module_n_0,Barrel_Shifter_module_n_1,Barrel_Shifter_module_n_2,Barrel_Shifter_module_n_3,Barrel_Shifter_module_n_4,Barrel_Shifter_module_n_5,Barrel_Shifter_module_n_6,Barrel_Shifter_module_n_7,Barrel_Shifter_module_n_8,Barrel_Shifter_module_n_9,Barrel_Shifter_module_n_10,Barrel_Shifter_module_n_11,Barrel_Shifter_module_n_12,Barrel_Shifter_module_n_13,Barrel_Shifter_module_n_14,Barrel_Shifter_module_n_15,Barrel_Shifter_module_n_16,Barrel_Shifter_module_n_17,Barrel_Shifter_module_n_18,Barrel_Shifter_module_n_19,Barrel_Shifter_module_n_20,Barrel_Shifter_module_n_21,Barrel_Shifter_module_n_22,Barrel_Shifter_module_n_23}),
.Q(Adder_M_n_24),
.\Q_reg[0] (Sel_C_n_0),
.\Q_reg[0]_0 (Barrel_Shifter_module_n_47),
.\Q_reg[46] ({Sgf_operation_n_2,Sgf_operation_n_3,Sgf_operation_n_4,Sgf_operation_n_5,Sgf_operation_n_6,Sgf_operation_n_7,Sgf_operation_n_8,Sgf_operation_n_9,Sgf_operation_n_10,Sgf_operation_n_11,Sgf_operation_n_12,Sgf_operation_n_13,Sgf_operation_n_14,Sgf_operation_n_15,Sgf_operation_n_16,Sgf_operation_n_17,Sgf_operation_n_18,Sgf_operation_n_19,Sgf_operation_n_20,Sgf_operation_n_21,Sgf_operation_n_22,Sgf_operation_n_23,Sgf_operation_n_24,Sgf_operation_n_25}));
Barrel_Shifter_M Barrel_Shifter_module
(.AR(FS_Module_n_9),
.D(Data_Reg),
.E(FSM_barrel_shifter_load),
.O6({Barrel_Shifter_module_n_0,Barrel_Shifter_module_n_1,Barrel_Shifter_module_n_2,Barrel_Shifter_module_n_3,Barrel_Shifter_module_n_4,Barrel_Shifter_module_n_5,Barrel_Shifter_module_n_6,Barrel_Shifter_module_n_7,Barrel_Shifter_module_n_8,Barrel_Shifter_module_n_9,Barrel_Shifter_module_n_10,Barrel_Shifter_module_n_11,Barrel_Shifter_module_n_12,Barrel_Shifter_module_n_13,Barrel_Shifter_module_n_14,Barrel_Shifter_module_n_15,Barrel_Shifter_module_n_16,Barrel_Shifter_module_n_17,Barrel_Shifter_module_n_18,Barrel_Shifter_module_n_19,Barrel_Shifter_module_n_20,Barrel_Shifter_module_n_21,Barrel_Shifter_module_n_22,Barrel_Shifter_module_n_23}),
.Q({Barrel_Shifter_module_n_24,Barrel_Shifter_module_n_25,Barrel_Shifter_module_n_26,Barrel_Shifter_module_n_27,Barrel_Shifter_module_n_28,Barrel_Shifter_module_n_29,Barrel_Shifter_module_n_30,Barrel_Shifter_module_n_31,Barrel_Shifter_module_n_32,Barrel_Shifter_module_n_33,Barrel_Shifter_module_n_34,Barrel_Shifter_module_n_35,Barrel_Shifter_module_n_36,Barrel_Shifter_module_n_37,Barrel_Shifter_module_n_38,Barrel_Shifter_module_n_39,Barrel_Shifter_module_n_40,Barrel_Shifter_module_n_41,Barrel_Shifter_module_n_42,Barrel_Shifter_module_n_43,Barrel_Shifter_module_n_44,Barrel_Shifter_module_n_45,Barrel_Shifter_module_n_46}),
.\Q_reg[0] (Barrel_Shifter_module_n_47),
.clk_IBUF_BUFG(clk_IBUF_BUFG));
IBUF \Data_MX_IBUF[0]_inst
(.I(Data_MX[0]),
.O(Data_MX_IBUF[0]));
IBUF \Data_MX_IBUF[10]_inst
(.I(Data_MX[10]),
.O(Data_MX_IBUF[10]));
IBUF \Data_MX_IBUF[11]_inst
(.I(Data_MX[11]),
.O(Data_MX_IBUF[11]));
IBUF \Data_MX_IBUF[12]_inst
(.I(Data_MX[12]),
.O(Data_MX_IBUF[12]));
IBUF \Data_MX_IBUF[13]_inst
(.I(Data_MX[13]),
.O(Data_MX_IBUF[13]));
IBUF \Data_MX_IBUF[14]_inst
(.I(Data_MX[14]),
.O(Data_MX_IBUF[14]));
IBUF \Data_MX_IBUF[15]_inst
(.I(Data_MX[15]),
.O(Data_MX_IBUF[15]));
IBUF \Data_MX_IBUF[16]_inst
(.I(Data_MX[16]),
.O(Data_MX_IBUF[16]));
IBUF \Data_MX_IBUF[17]_inst
(.I(Data_MX[17]),
.O(Data_MX_IBUF[17]));
IBUF \Data_MX_IBUF[18]_inst
(.I(Data_MX[18]),
.O(Data_MX_IBUF[18]));
IBUF \Data_MX_IBUF[19]_inst
(.I(Data_MX[19]),
.O(Data_MX_IBUF[19]));
IBUF \Data_MX_IBUF[1]_inst
(.I(Data_MX[1]),
.O(Data_MX_IBUF[1]));
IBUF \Data_MX_IBUF[20]_inst
(.I(Data_MX[20]),
.O(Data_MX_IBUF[20]));
IBUF \Data_MX_IBUF[21]_inst
(.I(Data_MX[21]),
.O(Data_MX_IBUF[21]));
IBUF \Data_MX_IBUF[22]_inst
(.I(Data_MX[22]),
.O(Data_MX_IBUF[22]));
IBUF \Data_MX_IBUF[23]_inst
(.I(Data_MX[23]),
.O(Data_MX_IBUF[23]));
IBUF \Data_MX_IBUF[24]_inst
(.I(Data_MX[24]),
.O(Data_MX_IBUF[24]));
IBUF \Data_MX_IBUF[25]_inst
(.I(Data_MX[25]),
.O(Data_MX_IBUF[25]));
IBUF \Data_MX_IBUF[26]_inst
(.I(Data_MX[26]),
.O(Data_MX_IBUF[26]));
IBUF \Data_MX_IBUF[27]_inst
(.I(Data_MX[27]),
.O(Data_MX_IBUF[27]));
IBUF \Data_MX_IBUF[28]_inst
(.I(Data_MX[28]),
.O(Data_MX_IBUF[28]));
IBUF \Data_MX_IBUF[29]_inst
(.I(Data_MX[29]),
.O(Data_MX_IBUF[29]));
IBUF \Data_MX_IBUF[2]_inst
(.I(Data_MX[2]),
.O(Data_MX_IBUF[2]));
IBUF \Data_MX_IBUF[30]_inst
(.I(Data_MX[30]),
.O(Data_MX_IBUF[30]));
IBUF \Data_MX_IBUF[31]_inst
(.I(Data_MX[31]),
.O(Data_MX_IBUF[31]));
IBUF \Data_MX_IBUF[3]_inst
(.I(Data_MX[3]),
.O(Data_MX_IBUF[3]));
IBUF \Data_MX_IBUF[4]_inst
(.I(Data_MX[4]),
.O(Data_MX_IBUF[4]));
IBUF \Data_MX_IBUF[5]_inst
(.I(Data_MX[5]),
.O(Data_MX_IBUF[5]));
IBUF \Data_MX_IBUF[6]_inst
(.I(Data_MX[6]),
.O(Data_MX_IBUF[6]));
IBUF \Data_MX_IBUF[7]_inst
(.I(Data_MX[7]),
.O(Data_MX_IBUF[7]));
IBUF \Data_MX_IBUF[8]_inst
(.I(Data_MX[8]),
.O(Data_MX_IBUF[8]));
IBUF \Data_MX_IBUF[9]_inst
(.I(Data_MX[9]),
.O(Data_MX_IBUF[9]));
IBUF \Data_MY_IBUF[0]_inst
(.I(Data_MY[0]),
.O(Data_MY_IBUF[0]));
IBUF \Data_MY_IBUF[10]_inst
(.I(Data_MY[10]),
.O(Data_MY_IBUF[10]));
IBUF \Data_MY_IBUF[11]_inst
(.I(Data_MY[11]),
.O(Data_MY_IBUF[11]));
IBUF \Data_MY_IBUF[12]_inst
(.I(Data_MY[12]),
.O(Data_MY_IBUF[12]));
IBUF \Data_MY_IBUF[13]_inst
(.I(Data_MY[13]),
.O(Data_MY_IBUF[13]));
IBUF \Data_MY_IBUF[14]_inst
(.I(Data_MY[14]),
.O(Data_MY_IBUF[14]));
IBUF \Data_MY_IBUF[15]_inst
(.I(Data_MY[15]),
.O(Data_MY_IBUF[15]));
IBUF \Data_MY_IBUF[16]_inst
(.I(Data_MY[16]),
.O(Data_MY_IBUF[16]));
IBUF \Data_MY_IBUF[17]_inst
(.I(Data_MY[17]),
.O(Data_MY_IBUF[17]));
IBUF \Data_MY_IBUF[18]_inst
(.I(Data_MY[18]),
.O(Data_MY_IBUF[18]));
IBUF \Data_MY_IBUF[19]_inst
(.I(Data_MY[19]),
.O(Data_MY_IBUF[19]));
IBUF \Data_MY_IBUF[1]_inst
(.I(Data_MY[1]),
.O(Data_MY_IBUF[1]));
IBUF \Data_MY_IBUF[20]_inst
(.I(Data_MY[20]),
.O(Data_MY_IBUF[20]));
IBUF \Data_MY_IBUF[21]_inst
(.I(Data_MY[21]),
.O(Data_MY_IBUF[21]));
IBUF \Data_MY_IBUF[22]_inst
(.I(Data_MY[22]),
.O(Data_MY_IBUF[22]));
IBUF \Data_MY_IBUF[23]_inst
(.I(Data_MY[23]),
.O(Data_MY_IBUF[23]));
IBUF \Data_MY_IBUF[24]_inst
(.I(Data_MY[24]),
.O(Data_MY_IBUF[24]));
IBUF \Data_MY_IBUF[25]_inst
(.I(Data_MY[25]),
.O(Data_MY_IBUF[25]));
IBUF \Data_MY_IBUF[26]_inst
(.I(Data_MY[26]),
.O(Data_MY_IBUF[26]));
IBUF \Data_MY_IBUF[27]_inst
(.I(Data_MY[27]),
.O(Data_MY_IBUF[27]));
IBUF \Data_MY_IBUF[28]_inst
(.I(Data_MY[28]),
.O(Data_MY_IBUF[28]));
IBUF \Data_MY_IBUF[29]_inst
(.I(Data_MY[29]),
.O(Data_MY_IBUF[29]));
IBUF \Data_MY_IBUF[2]_inst
(.I(Data_MY[2]),
.O(Data_MY_IBUF[2]));
IBUF \Data_MY_IBUF[30]_inst
(.I(Data_MY[30]),
.O(Data_MY_IBUF[30]));
IBUF \Data_MY_IBUF[31]_inst
(.I(Data_MY[31]),
.O(Data_MY_IBUF[31]));
IBUF \Data_MY_IBUF[3]_inst
(.I(Data_MY[3]),
.O(Data_MY_IBUF[3]));
IBUF \Data_MY_IBUF[4]_inst
(.I(Data_MY[4]),
.O(Data_MY_IBUF[4]));
IBUF \Data_MY_IBUF[5]_inst
(.I(Data_MY[5]),
.O(Data_MY_IBUF[5]));
IBUF \Data_MY_IBUF[6]_inst
(.I(Data_MY[6]),
.O(Data_MY_IBUF[6]));
IBUF \Data_MY_IBUF[7]_inst
(.I(Data_MY[7]),
.O(Data_MY_IBUF[7]));
IBUF \Data_MY_IBUF[8]_inst
(.I(Data_MY[8]),
.O(Data_MY_IBUF[8]));
IBUF \Data_MY_IBUF[9]_inst
(.I(Data_MY[9]),
.O(Data_MY_IBUF[9]));
Exp_Operation_m Exp_module
(.AR(FS_Module_n_9),
.D({Sign_S_mux,Exp_module_n_2,Exp_module_n_3,Exp_module_n_4,Exp_module_n_5,Exp_module_n_6,Exp_module_n_7,Exp_module_n_8,Exp_module_n_9,Exp_module_n_10,Exp_module_n_11,Exp_module_n_12,Exp_module_n_13,Exp_module_n_14,Exp_module_n_15,Exp_module_n_16,Exp_module_n_17,Exp_module_n_18,Exp_module_n_19,Exp_module_n_20,Exp_module_n_21,Exp_module_n_22,Exp_module_n_23,Exp_module_n_24,Exp_module_n_25,Exp_module_n_26,Exp_module_n_27,Exp_module_n_28,Exp_module_n_29,Exp_module_n_30,Exp_module_n_31,Exp_module_n_32}),
.E(FSM_load_second_step),
.\FSM_sequential_state_reg_reg[0] (FSM_exp_operation_load_result),
.O({Sel_A_n_1,Sel_A_n_2}),
.Q(Op_MY),
.\Q_reg[0] (Exp_module_n_43),
.\Q_reg[0]_0 (Exp_module_n_44),
.\Q_reg[0]_1 (FS_Module_n_7),
.\Q_reg[0]_2 (Sel_A_n_0),
.\Q_reg[0]_3 ({Sel_B_n_0,Sel_B_n_1,Sel_B_n_2,Sel_B_n_3,Sel_B_n_4,Sel_B_n_5,Sel_B_n_6,Sel_B_n_7}),
.\Q_reg[22] ({Barrel_Shifter_module_n_24,Barrel_Shifter_module_n_25,Barrel_Shifter_module_n_26,Barrel_Shifter_module_n_27,Barrel_Shifter_module_n_28,Barrel_Shifter_module_n_29,Barrel_Shifter_module_n_30,Barrel_Shifter_module_n_31,Barrel_Shifter_module_n_32,Barrel_Shifter_module_n_33,Barrel_Shifter_module_n_34,Barrel_Shifter_module_n_35,Barrel_Shifter_module_n_36,Barrel_Shifter_module_n_37,Barrel_Shifter_module_n_38,Barrel_Shifter_module_n_39,Barrel_Shifter_module_n_40,Barrel_Shifter_module_n_41,Barrel_Shifter_module_n_42,Barrel_Shifter_module_n_43,Barrel_Shifter_module_n_44,Barrel_Shifter_module_n_45,Barrel_Shifter_module_n_46}),
.\Q_reg[30] ({exp_oper_result,Exp_module_n_34,Exp_module_n_35,Exp_module_n_36,Exp_module_n_37,Exp_module_n_38,Exp_module_n_39,Exp_module_n_40}),
.\Q_reg[31] ({Op_MX,Operands_load_reg_n_55}),
.\Q_reg[3] (Exp_module_n_42),
.clk_IBUF_BUFG(clk_IBUF_BUFG),
.overflow_flag_OBUF(overflow_flag_OBUF),
.underflow_flag_OBUF(underflow_flag_OBUF));
FSM_Mult_Function FS_Module
(.AR(FS_Module_n_9),
.D(Data_Reg[23]),
.E(FS_Module_n_10),
.FSM_Shift_Value(FSM_Shift_Value),
.FSM_add_overflow_flag(FSM_add_overflow_flag),
.FSM_exp_operation_A_S(FSM_exp_operation_A_S),
.FSM_round_flag(FSM_round_flag),
.Q({P_Sgf,Sgf_operation_n_2}),
.\Q_reg[0] (FS_Module_n_2),
.\Q_reg[0]_0 (FS_Module_n_7),
.\Q_reg[0]_1 (FS_Module_n_8),
.\Q_reg[0]_10 (Exp_module_n_43),
.\Q_reg[0]_11 ({Sel_B_n_6,Sel_B_n_7}),
.\Q_reg[0]_12 (Exp_module_n_44),
.\Q_reg[0]_13 (Operands_load_reg_n_46),
.\Q_reg[0]_14 (Operands_load_reg_n_45),
.\Q_reg[0]_2 (FS_Module_n_12),
.\Q_reg[0]_3 (FSM_barrel_shifter_load),
.\Q_reg[0]_4 (FSM_adder_round_norm_load),
.\Q_reg[0]_5 (FSM_load_second_step),
.\Q_reg[0]_6 (FSM_exp_operation_load_result),
.\Q_reg[0]_7 (FSM_final_result_load),
.\Q_reg[0]_8 (Sel_C_n_0),
.\Q_reg[0]_9 (Sel_A_n_0),
.\Q_reg[23] (Adder_M_n_24),
.\Q_reg[8] (exp_oper_result),
.S(FS_Module_n_11),
.ack_FSM_IBUF(ack_FSM_IBUF),
.beg_FSM_IBUF(beg_FSM_IBUF),
.clk_IBUF_BUFG(clk_IBUF_BUFG),
.out({FS_Module_n_3,FS_Module_n_4,FS_Module_n_5,FS_Module_n_6}),
.ready_OBUF(ready_OBUF),
.rst(rst_IBUF),
.underflow_flag_OBUF(underflow_flag_OBUF),
.zero_flag(zero_flag));
First_Phase_M Operands_load_reg
(.AR(FS_Module_n_9),
.B(B),
.D(Data_MX_IBUF),
.\Data_MY[31] (Data_MY_IBUF),
.E(FS_Module_n_10),
.Q({Op_MY,Operands_load_reg_n_14,Operands_load_reg_n_15,Operands_load_reg_n_16,Operands_load_reg_n_17,Operands_load_reg_n_18,Operands_load_reg_n_19,Operands_load_reg_n_20,Operands_load_reg_n_21,Operands_load_reg_n_22,Operands_load_reg_n_23,Operands_load_reg_n_24,Operands_load_reg_n_25,Operands_load_reg_n_26,Operands_load_reg_n_27,Operands_load_reg_n_28,Operands_load_reg_n_29,Operands_load_reg_n_30,Operands_load_reg_n_31,Operands_load_reg_n_32,Operands_load_reg_n_33,Operands_load_reg_n_34,Operands_load_reg_n_35,Operands_load_reg_n_36,Operands_load_reg_n_37,Operands_load_reg_n_38,Operands_load_reg_n_39,Operands_load_reg_n_40,Operands_load_reg_n_41,Operands_load_reg_n_42,Operands_load_reg_n_43,Operands_load_reg_n_44}),
.\Q_reg[0] (Operands_load_reg_n_45),
.\Q_reg[0]_0 (Operands_load_reg_n_46),
.\Q_reg[0]_1 (Operands_load_reg_n_79),
.\Q_reg[31] ({Op_MX,Operands_load_reg_n_48,Operands_load_reg_n_49,Operands_load_reg_n_50,Operands_load_reg_n_51,Operands_load_reg_n_52,Operands_load_reg_n_53,Operands_load_reg_n_54,Operands_load_reg_n_55,Data_A_i,Operands_load_reg_n_67,Operands_load_reg_n_68,Operands_load_reg_n_69,Operands_load_reg_n_70,Operands_load_reg_n_71,Operands_load_reg_n_72,Operands_load_reg_n_73,Operands_load_reg_n_74,Operands_load_reg_n_75,Operands_load_reg_n_76,Operands_load_reg_n_77,Operands_load_reg_n_78}),
.clk_IBUF_BUFG(clk_IBUF_BUFG),
.round_mode_IBUF(round_mode_IBUF));
RegisterAdd Sel_A
(.AR(FS_Module_n_9),
.CO(Sel_B_n_8),
.\FSM_sequential_state_reg_reg[1] (FS_Module_n_2),
.O({Sel_A_n_1,Sel_A_n_2}),
.\Q_reg[0]_0 (Sel_A_n_0),
.\Q_reg[8] (exp_oper_result),
.S(FS_Module_n_11),
.clk_IBUF_BUFG(clk_IBUF_BUFG));
RegisterAdd__parameterized0 Sel_B
(.AR(FS_Module_n_9),
.CO(Sel_B_n_8),
.FSM_exp_operation_A_S(FSM_exp_operation_A_S),
.Q({Operands_load_reg_n_14,Operands_load_reg_n_15,Operands_load_reg_n_16,Operands_load_reg_n_17,Operands_load_reg_n_18,Operands_load_reg_n_19,Operands_load_reg_n_20,Operands_load_reg_n_21}),
.\Q_reg[0]_0 (Exp_module_n_42),
.\Q_reg[0]_1 (Sel_A_n_0),
.\Q_reg[30] ({Operands_load_reg_n_48,Operands_load_reg_n_49,Operands_load_reg_n_50,Operands_load_reg_n_51,Operands_load_reg_n_52,Operands_load_reg_n_53,Operands_load_reg_n_54}),
.\Q_reg[47] (P_Sgf),
.\Q_reg[7] ({Sel_B_n_0,Sel_B_n_1,Sel_B_n_2,Sel_B_n_3,Sel_B_n_4,Sel_B_n_5,Sel_B_n_6,Sel_B_n_7}),
.\Q_reg[7]_0 ({Exp_module_n_34,Exp_module_n_35,Exp_module_n_36,Exp_module_n_37,Exp_module_n_38,Exp_module_n_39,Exp_module_n_40}),
.clk_IBUF_BUFG(clk_IBUF_BUFG),
.out({FS_Module_n_3,FS_Module_n_4,FS_Module_n_5,FS_Module_n_6}));
RegisterAdd_0 Sel_C
(.AR(FS_Module_n_9),
.\FSM_sequential_state_reg_reg[0] (FS_Module_n_12),
.\Q_reg[23] (Sel_C_n_0),
.clk_IBUF_BUFG(clk_IBUF_BUFG));
Sgf_Multiplication Sgf_operation
(.AR(rst_IBUF),
.B(B),
.E(FSM_load_second_step),
.FSM_round_flag(FSM_round_flag),
.Q({Operands_load_reg_n_22,Operands_load_reg_n_23,Operands_load_reg_n_24,Operands_load_reg_n_25,Operands_load_reg_n_26,Operands_load_reg_n_27,Operands_load_reg_n_28,Operands_load_reg_n_29,Operands_load_reg_n_30,Operands_load_reg_n_31,Operands_load_reg_n_32,Operands_load_reg_n_33,Operands_load_reg_n_34,Operands_load_reg_n_35,Operands_load_reg_n_36,Operands_load_reg_n_37,Operands_load_reg_n_38,Operands_load_reg_n_39,Operands_load_reg_n_40,Operands_load_reg_n_41,Operands_load_reg_n_42,Operands_load_reg_n_43,Operands_load_reg_n_44}),
.\Q_reg[0] ({P_Sgf,Sgf_operation_n_2,Sgf_operation_n_3,Sgf_operation_n_4,Sgf_operation_n_5,Sgf_operation_n_6,Sgf_operation_n_7,Sgf_operation_n_8,Sgf_operation_n_9,Sgf_operation_n_10,Sgf_operation_n_11,Sgf_operation_n_12,Sgf_operation_n_13,Sgf_operation_n_14,Sgf_operation_n_15,Sgf_operation_n_16,Sgf_operation_n_17,Sgf_operation_n_18,Sgf_operation_n_19,Sgf_operation_n_20,Sgf_operation_n_21,Sgf_operation_n_22,Sgf_operation_n_23,Sgf_operation_n_24,Sgf_operation_n_25}),
.\Q_reg[22] ({Data_A_i,Operands_load_reg_n_67,Operands_load_reg_n_68,Operands_load_reg_n_69,Operands_load_reg_n_70,Operands_load_reg_n_71,Operands_load_reg_n_72,Operands_load_reg_n_73,Operands_load_reg_n_74,Operands_load_reg_n_75,Operands_load_reg_n_76,Operands_load_reg_n_77,Operands_load_reg_n_78}),
.\Q_reg[31] (Operands_load_reg_n_79),
.clk_IBUF_BUFG(clk_IBUF_BUFG));
Zero_InfMult_Unit Zero_Result_Detect
(.AR(FS_Module_n_9),
.\FSM_sequential_state_reg_reg[0] (FS_Module_n_8),
.clk_IBUF_BUFG(clk_IBUF_BUFG),
.zero_flag(zero_flag));
IBUF ack_FSM_IBUF_inst
(.I(ack_FSM),
.O(ack_FSM_IBUF));
IBUF beg_FSM_IBUF_inst
(.I(beg_FSM),
.O(beg_FSM_IBUF));
BUFG clk_IBUF_BUFG_inst
(.I(clk_IBUF),
.O(clk_IBUF_BUFG));
IBUF clk_IBUF_inst
(.I(clk),
.O(clk_IBUF));
Tenth_Phase final_result_ieee_Module
(.AR(FS_Module_n_9),
.D({Sign_S_mux,Exp_module_n_2,Exp_module_n_3,Exp_module_n_4,Exp_module_n_5,Exp_module_n_6,Exp_module_n_7,Exp_module_n_8,Exp_module_n_9,Exp_module_n_10,Exp_module_n_11,Exp_module_n_12,Exp_module_n_13,Exp_module_n_14,Exp_module_n_15,Exp_module_n_16,Exp_module_n_17,Exp_module_n_18,Exp_module_n_19,Exp_module_n_20,Exp_module_n_21,Exp_module_n_22,Exp_module_n_23,Exp_module_n_24,Exp_module_n_25,Exp_module_n_26,Exp_module_n_27,Exp_module_n_28,Exp_module_n_29,Exp_module_n_30,Exp_module_n_31,Exp_module_n_32}),
.E(FSM_final_result_load),
.Q(final_result_ieee_OBUF),
.clk_IBUF_BUFG(clk_IBUF_BUFG));
OBUF \final_result_ieee_OBUF[0]_inst
(.I(final_result_ieee_OBUF[0]),
.O(final_result_ieee[0]));
OBUF \final_result_ieee_OBUF[10]_inst
(.I(final_result_ieee_OBUF[10]),
.O(final_result_ieee[10]));
OBUF \final_result_ieee_OBUF[11]_inst
(.I(final_result_ieee_OBUF[11]),
.O(final_result_ieee[11]));
OBUF \final_result_ieee_OBUF[12]_inst
(.I(final_result_ieee_OBUF[12]),
.O(final_result_ieee[12]));
OBUF \final_result_ieee_OBUF[13]_inst
(.I(final_result_ieee_OBUF[13]),
.O(final_result_ieee[13]));
OBUF \final_result_ieee_OBUF[14]_inst
(.I(final_result_ieee_OBUF[14]),
.O(final_result_ieee[14]));
OBUF \final_result_ieee_OBUF[15]_inst
(.I(final_result_ieee_OBUF[15]),
.O(final_result_ieee[15]));
OBUF \final_result_ieee_OBUF[16]_inst
(.I(final_result_ieee_OBUF[16]),
.O(final_result_ieee[16]));
OBUF \final_result_ieee_OBUF[17]_inst
(.I(final_result_ieee_OBUF[17]),
.O(final_result_ieee[17]));
OBUF \final_result_ieee_OBUF[18]_inst
(.I(final_result_ieee_OBUF[18]),
.O(final_result_ieee[18]));
OBUF \final_result_ieee_OBUF[19]_inst
(.I(final_result_ieee_OBUF[19]),
.O(final_result_ieee[19]));
OBUF \final_result_ieee_OBUF[1]_inst
(.I(final_result_ieee_OBUF[1]),
.O(final_result_ieee[1]));
OBUF \final_result_ieee_OBUF[20]_inst
(.I(final_result_ieee_OBUF[20]),
.O(final_result_ieee[20]));
OBUF \final_result_ieee_OBUF[21]_inst
(.I(final_result_ieee_OBUF[21]),
.O(final_result_ieee[21]));
OBUF \final_result_ieee_OBUF[22]_inst
(.I(final_result_ieee_OBUF[22]),
.O(final_result_ieee[22]));
OBUF \final_result_ieee_OBUF[23]_inst
(.I(final_result_ieee_OBUF[23]),
.O(final_result_ieee[23]));
OBUF \final_result_ieee_OBUF[24]_inst
(.I(final_result_ieee_OBUF[24]),
.O(final_result_ieee[24]));
OBUF \final_result_ieee_OBUF[25]_inst
(.I(final_result_ieee_OBUF[25]),
.O(final_result_ieee[25]));
OBUF \final_result_ieee_OBUF[26]_inst
(.I(final_result_ieee_OBUF[26]),
.O(final_result_ieee[26]));
OBUF \final_result_ieee_OBUF[27]_inst
(.I(final_result_ieee_OBUF[27]),
.O(final_result_ieee[27]));
OBUF \final_result_ieee_OBUF[28]_inst
(.I(final_result_ieee_OBUF[28]),
.O(final_result_ieee[28]));
OBUF \final_result_ieee_OBUF[29]_inst
(.I(final_result_ieee_OBUF[29]),
.O(final_result_ieee[29]));
OBUF \final_result_ieee_OBUF[2]_inst
(.I(final_result_ieee_OBUF[2]),
.O(final_result_ieee[2]));
OBUF \final_result_ieee_OBUF[30]_inst
(.I(final_result_ieee_OBUF[30]),
.O(final_result_ieee[30]));
OBUF \final_result_ieee_OBUF[31]_inst
(.I(final_result_ieee_OBUF[31]),
.O(final_result_ieee[31]));
OBUF \final_result_ieee_OBUF[3]_inst
(.I(final_result_ieee_OBUF[3]),
.O(final_result_ieee[3]));
OBUF \final_result_ieee_OBUF[4]_inst
(.I(final_result_ieee_OBUF[4]),
.O(final_result_ieee[4]));
OBUF \final_result_ieee_OBUF[5]_inst
(.I(final_result_ieee_OBUF[5]),
.O(final_result_ieee[5]));
OBUF \final_result_ieee_OBUF[6]_inst
(.I(final_result_ieee_OBUF[6]),
.O(final_result_ieee[6]));
OBUF \final_result_ieee_OBUF[7]_inst
(.I(final_result_ieee_OBUF[7]),
.O(final_result_ieee[7]));
OBUF \final_result_ieee_OBUF[8]_inst
(.I(final_result_ieee_OBUF[8]),
.O(final_result_ieee[8]));
OBUF \final_result_ieee_OBUF[9]_inst
(.I(final_result_ieee_OBUF[9]),
.O(final_result_ieee[9]));
OBUF overflow_flag_OBUF_inst
(.I(overflow_flag_OBUF),
.O(overflow_flag));
OBUF ready_OBUF_inst
(.I(ready_OBUF),
.O(ready));
IBUF \round_mode_IBUF[0]_inst
(.I(round_mode[0]),
.O(round_mode_IBUF[0]));
IBUF \round_mode_IBUF[1]_inst
(.I(round_mode[1]),
.O(round_mode_IBUF[1]));
IBUF rst_IBUF_inst
(.I(rst),
.O(rst_IBUF));
OBUF underflow_flag_OBUF_inst
(.I(underflow_flag_OBUF),
.O(underflow_flag));
endmodule
module FSM_Mult_Function
(D,
FSM_Shift_Value,
\Q_reg[0] ,
out,
\Q_reg[0]_0 ,
\Q_reg[0]_1 ,
AR,
E,
S,
\Q_reg[0]_2 ,
FSM_exp_operation_A_S,
\Q_reg[0]_3 ,
\Q_reg[0]_4 ,
\Q_reg[0]_5 ,
\Q_reg[0]_6 ,
ready_OBUF,
\Q_reg[0]_7 ,
\Q_reg[0]_8 ,
Q,
\Q_reg[23] ,
\Q_reg[0]_9 ,
\Q_reg[0]_10 ,
\Q_reg[0]_11 ,
\Q_reg[0]_12 ,
underflow_flag_OBUF,
\Q_reg[0]_13 ,
\Q_reg[0]_14 ,
zero_flag,
\Q_reg[8] ,
FSM_round_flag,
clk_IBUF_BUFG,
rst,
beg_FSM_IBUF,
ack_FSM_IBUF,
FSM_add_overflow_flag);
output [0:0]D;
output FSM_Shift_Value;
output \Q_reg[0] ;
output [3:0]out;
output \Q_reg[0]_0 ;
output \Q_reg[0]_1 ;
output [0:0]AR;
output [0:0]E;
output [0:0]S;
output \Q_reg[0]_2 ;
output FSM_exp_operation_A_S;
output [0:0]\Q_reg[0]_3 ;
output [0:0]\Q_reg[0]_4 ;
output [0:0]\Q_reg[0]_5 ;
output [0:0]\Q_reg[0]_6 ;
output ready_OBUF;
output [0:0]\Q_reg[0]_7 ;
input \Q_reg[0]_8 ;
input [1:0]Q;
input [0:0]\Q_reg[23] ;
input \Q_reg[0]_9 ;
input \Q_reg[0]_10 ;
input [1:0]\Q_reg[0]_11 ;
input \Q_reg[0]_12 ;
input underflow_flag_OBUF;
input \Q_reg[0]_13 ;
input \Q_reg[0]_14 ;
input zero_flag;
input [0:0]\Q_reg[8] ;
input FSM_round_flag;
input clk_IBUF_BUFG;
input [0:0]rst;
input beg_FSM_IBUF;
input ack_FSM_IBUF;
input FSM_add_overflow_flag;
wire [0:0]AR;
wire [0:0]D;
wire [0:0]E;
wire FSM_Shift_Value;
wire FSM_add_overflow_flag;
wire FSM_exp_operation_A_S;
wire FSM_round_flag;
wire \FSM_sequential_state_reg[0]_i_1_n_0 ;
wire \FSM_sequential_state_reg[1]_i_1_n_0 ;
wire \FSM_sequential_state_reg[2]_i_1_n_0 ;
wire \FSM_sequential_state_reg[3]_i_1_n_0 ;
wire \FSM_sequential_state_reg[3]_i_2_n_0 ;
wire [1:0]Q;
wire \Q[0]_i_4__0_n_0 ;
wire \Q_reg[0] ;
wire \Q_reg[0]_0 ;
wire \Q_reg[0]_1 ;
wire \Q_reg[0]_10 ;
wire [1:0]\Q_reg[0]_11 ;
wire \Q_reg[0]_12 ;
wire \Q_reg[0]_13 ;
wire \Q_reg[0]_14 ;
wire \Q_reg[0]_2 ;
wire [0:0]\Q_reg[0]_3 ;
wire [0:0]\Q_reg[0]_4 ;
wire [0:0]\Q_reg[0]_5 ;
wire [0:0]\Q_reg[0]_6 ;
wire [0:0]\Q_reg[0]_7 ;
wire \Q_reg[0]_8 ;
wire \Q_reg[0]_9 ;
wire [0:0]\Q_reg[23] ;
wire [0:0]\Q_reg[8] ;
wire [0:0]S;
wire ack_FSM_IBUF;
wire beg_FSM_IBUF;
wire clk_IBUF_BUFG;
(* RTL_KEEP = "yes" *) wire [3:0]out;
wire ready_OBUF;
wire [0:0]rst;
wire selector_A;
wire underflow_flag_OBUF;
wire zero_flag;
LUT6 #(
.INIT(64'h00000F1F10100F1F))
\FSM_sequential_state_reg[0]_i_1
(.I0(out[1]),
.I1(out[3]),
.I2(out[2]),
.I3(zero_flag),
.I4(out[0]),
.I5(Q[1]),
.O(\FSM_sequential_state_reg[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h00446766))
\FSM_sequential_state_reg[1]_i_1
(.I0(out[1]),
.I1(out[0]),
.I2(FSM_round_flag),
.I3(out[3]),
.I4(out[2]),
.O(\FSM_sequential_state_reg[1]_i_1_n_0 ));
LUT4 #(
.INIT(16'h3404))
\FSM_sequential_state_reg[2]_i_1
(.I0(out[3]),
.I1(out[2]),
.I2(out[1]),
.I3(out[0]),
.O(\FSM_sequential_state_reg[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h55FF55FF55FFF5EE))
\FSM_sequential_state_reg[3]_i_1
(.I0(out[3]),
.I1(beg_FSM_IBUF),
.I2(ack_FSM_IBUF),
.I3(out[2]),
.I4(out[1]),
.I5(out[0]),
.O(\FSM_sequential_state_reg[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'h00FFF200))
\FSM_sequential_state_reg[3]_i_2
(.I0(zero_flag),
.I1(out[0]),
.I2(out[1]),
.I3(out[2]),
.I4(out[3]),
.O(\FSM_sequential_state_reg[3]_i_2_n_0 ));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[0]
(.C(clk_IBUF_BUFG),
.CE(\FSM_sequential_state_reg[3]_i_1_n_0 ),
.CLR(rst),
.D(\FSM_sequential_state_reg[0]_i_1_n_0 ),
.Q(out[0]));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[1]
(.C(clk_IBUF_BUFG),
.CE(\FSM_sequential_state_reg[3]_i_1_n_0 ),
.CLR(rst),
.D(\FSM_sequential_state_reg[1]_i_1_n_0 ),
.Q(out[1]));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[2]
(.C(clk_IBUF_BUFG),
.CE(\FSM_sequential_state_reg[3]_i_1_n_0 ),
.CLR(rst),
.D(\FSM_sequential_state_reg[2]_i_1_n_0 ),
.Q(out[2]));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[3]
(.C(clk_IBUF_BUFG),
.CE(\FSM_sequential_state_reg[3]_i_1_n_0 ),
.CLR(rst),
.D(\FSM_sequential_state_reg[3]_i_2_n_0 ),
.Q(out[3]));
LUT5 #(
.INIT(32'h11114000))
\Q[0]_i_1
(.I0(out[0]),
.I1(out[3]),
.I2(out[1]),
.I3(FSM_add_overflow_flag),
.I4(out[2]),
.O(\Q_reg[0]_5 ));
LUT5 #(
.INIT(32'hFFFF0008))
\Q[0]_i_1__3
(.I0(out[1]),
.I1(out[0]),
.I2(out[3]),
.I3(out[2]),
.I4(\Q_reg[0]_9 ),
.O(\Q_reg[0] ));
LUT6 #(
.INIT(64'hBFAAFFFFBFAA0000))
\Q[0]_i_1__4
(.I0(\Q_reg[0]_10 ),
.I1(\Q_reg[0]_11 [1]),
.I2(\Q_reg[0]_11 [0]),
.I3(\Q_reg[0]_12 ),
.I4(selector_A),
.I5(underflow_flag_OBUF),
.O(\Q_reg[0]_0 ));
LUT6 #(
.INIT(64'hEFFFFFFFE0000000))
\Q[0]_i_1__5
(.I0(\Q_reg[0]_13 ),
.I1(\Q_reg[0]_14 ),
.I2(\Q[0]_i_4__0_n_0 ),
.I3(out[0]),
.I4(out[1]),
.I5(zero_flag),
.O(\Q_reg[0]_1 ));
LUT6 #(
.INIT(64'hFFFFFFFF00100000))
\Q[0]_i_1__6
(.I0(out[0]),
.I1(out[1]),
.I2(out[3]),
.I3(out[2]),
.I4(FSM_round_flag),
.I5(\Q_reg[0]_8 ),
.O(\Q_reg[0]_2 ));
LUT4 #(
.INIT(16'h1000))
\Q[0]_i_4
(.I0(out[2]),
.I1(out[3]),
.I2(out[0]),
.I3(out[1]),
.O(selector_A));
LUT2 #(
.INIT(4'h1))
\Q[0]_i_4__0
(.I0(out[2]),
.I1(out[3]),
.O(\Q[0]_i_4__0_n_0 ));
LUT4 #(
.INIT(16'h0A20))
\Q[23]_i_1
(.I0(out[1]),
.I1(out[0]),
.I2(out[3]),
.I3(out[2]),
.O(\Q_reg[0]_3 ));
LUT4 #(
.INIT(16'h1000))
\Q[23]_i_1__0
(.I0(out[1]),
.I1(out[2]),
.I2(out[0]),
.I3(out[3]),
.O(\Q_reg[0]_4 ));
LUT4 #(
.INIT(16'hFEBA))
\Q[23]_i_2
(.I0(FSM_Shift_Value),
.I1(\Q_reg[0]_8 ),
.I2(Q[0]),
.I3(\Q_reg[23] ),
.O(D));
LUT5 #(
.INIT(32'h00222000))
\Q[23]_i_3
(.I0(out[1]),
.I1(out[0]),
.I2(FSM_add_overflow_flag),
.I3(out[3]),
.I4(out[2]),
.O(FSM_Shift_Value));
LUT4 #(
.INIT(16'h2000))
\Q[31]_i_1
(.I0(out[3]),
.I1(out[2]),
.I2(out[0]),
.I3(out[1]),
.O(\Q_reg[0]_7 ));
LUT4 #(
.INIT(16'h0010))
\Q[31]_i_1__0
(.I0(out[3]),
.I1(out[2]),
.I2(out[0]),
.I3(out[1]),
.O(E));
LUT4 #(
.INIT(16'h0001))
\Q[31]_i_2__0
(.I0(out[3]),
.I1(out[2]),
.I2(out[0]),
.I3(out[1]),
.O(AR));
LUT4 #(
.INIT(16'h0010))
\Q[3]_i_6
(.I0(out[3]),
.I1(out[0]),
.I2(out[2]),
.I3(out[1]),
.O(FSM_exp_operation_A_S));
LUT5 #(
.INIT(32'h16040604))
\Q[8]_i_1
(.I0(out[0]),
.I1(out[2]),
.I2(out[3]),
.I3(out[1]),
.I4(FSM_add_overflow_flag),
.O(\Q_reg[0]_6 ));
LUT6 #(
.INIT(64'h8888888888888788))
\Q[8]_i_5
(.I0(\Q_reg[8] ),
.I1(\Q_reg[0]_9 ),
.I2(out[1]),
.I3(out[2]),
.I4(out[0]),
.I5(out[3]),
.O(S));
LUT4 #(
.INIT(16'h1000))
ready_OBUF_inst_i_1
(.I0(out[0]),
.I1(out[1]),
.I2(out[3]),
.I3(out[2]),
.O(ready_OBUF));
endmodule
module First_Phase_M
(B,
Q,
\Q_reg[0] ,
\Q_reg[0]_0 ,
\Q_reg[31] ,
\Q_reg[0]_1 ,
round_mode_IBUF,
E,
D,
clk_IBUF_BUFG,
AR,
\Data_MY[31] );
output [12:0]B;
output [31:0]Q;
output \Q_reg[0] ;
output \Q_reg[0]_0 ;
output [31:0]\Q_reg[31] ;
output \Q_reg[0]_1 ;
input [1:0]round_mode_IBUF;
input [0:0]E;
input [31:0]D;
input clk_IBUF_BUFG;
input [0:0]AR;
input [31:0]\Data_MY[31] ;
wire [0:0]AR;
wire [12:0]B;
wire [31:0]D;
wire [31:0]\Data_MY[31] ;
wire [0:0]E;
wire [31:0]Q;
wire \Q_reg[0] ;
wire \Q_reg[0]_0 ;
wire \Q_reg[0]_1 ;
wire [31:0]\Q_reg[31] ;
wire clk_IBUF_BUFG;
wire [1:0]round_mode_IBUF;
RegisterMult XMRegister
(.AR(AR),
.D(D),
.E(E),
.Q(Q[31]),
.\Q_reg[0]_0 (\Q_reg[0]_0 ),
.\Q_reg[0]_1 (\Q_reg[0]_1 ),
.\Q_reg[31]_0 (\Q_reg[31] ),
.clk_IBUF_BUFG(clk_IBUF_BUFG),
.round_mode_IBUF(round_mode_IBUF));
RegisterMult_4 YMRegister
(.AR(AR),
.B(B),
.\Data_MY[31] (\Data_MY[31] ),
.E(E),
.Q(Q),
.\Q_reg[0]_0 (\Q_reg[0] ),
.clk_IBUF_BUFG(clk_IBUF_BUFG));
endmodule
module RegisterAdd
(\Q_reg[0]_0 ,
O,
\FSM_sequential_state_reg_reg[1] ,
clk_IBUF_BUFG,
AR,
CO,
S,
\Q_reg[8] );
output \Q_reg[0]_0 ;
output [1:0]O;
input \FSM_sequential_state_reg_reg[1] ;
input clk_IBUF_BUFG;
input [0:0]AR;
input [0:0]CO;
input [0:0]S;
input [0:0]\Q_reg[8] ;
wire [0:0]AR;
wire [0:0]CO;
wire \FSM_sequential_state_reg_reg[1] ;
wire [1:0]O;
wire \Q[8]_i_3_n_0 ;
wire \Q[8]_i_4_n_0 ;
wire \Q_reg[0]_0 ;
wire [0:0]\Q_reg[8] ;
wire [0:0]S;
wire clk_IBUF_BUFG;
wire [3:0]\NLW_Q_reg[8]_i_2_CO_UNCONNECTED ;
wire [3:2]\NLW_Q_reg[8]_i_2_O_UNCONNECTED ;
LUT2 #(
.INIT(4'h7))
\Q[8]_i_3
(.I0(\Q_reg[0]_0 ),
.I1(\Q_reg[8] ),
.O(\Q[8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h7))
\Q[8]_i_4
(.I0(\Q_reg[0]_0 ),
.I1(\Q_reg[8] ),
.O(\Q[8]_i_4_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk_IBUF_BUFG),
.CE(1'b1),
.CLR(AR),
.D(\FSM_sequential_state_reg_reg[1] ),
.Q(\Q_reg[0]_0 ));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Q_reg[8]_i_2
(.CI(CO),
.CO(\NLW_Q_reg[8]_i_2_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,\Q[8]_i_3_n_0 }),
.O({\NLW_Q_reg[8]_i_2_O_UNCONNECTED [3:2],O}),
.S({1'b0,1'b0,\Q[8]_i_4_n_0 ,S}));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd_0
(\Q_reg[23] ,
\FSM_sequential_state_reg_reg[0] ,
clk_IBUF_BUFG,
AR);
output \Q_reg[23] ;
input \FSM_sequential_state_reg_reg[0] ;
input clk_IBUF_BUFG;
input [0:0]AR;
wire [0:0]AR;
wire \FSM_sequential_state_reg_reg[0] ;
wire \Q_reg[23] ;
wire clk_IBUF_BUFG;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk_IBUF_BUFG),
.CE(1'b1),
.CLR(AR),
.D(\FSM_sequential_state_reg_reg[0] ),
.Q(\Q_reg[23] ));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd_1
(zero_flag,
\FSM_sequential_state_reg_reg[0] ,
clk_IBUF_BUFG,
AR);
output zero_flag;
input \FSM_sequential_state_reg_reg[0] ;
input clk_IBUF_BUFG;
input [0:0]AR;
wire [0:0]AR;
wire \FSM_sequential_state_reg_reg[0] ;
wire clk_IBUF_BUFG;
wire zero_flag;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk_IBUF_BUFG),
.CE(1'b1),
.CLR(AR),
.D(\FSM_sequential_state_reg_reg[0] ),
.Q(zero_flag));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd_5
(FSM_add_overflow_flag,
E,
O6,
CLK,
AR);
output FSM_add_overflow_flag;
input [0:0]E;
input [0:0]O6;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]E;
wire FSM_add_overflow_flag;
wire [0:0]O6;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(O6),
.Q(FSM_add_overflow_flag));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized0
(\Q_reg[7] ,
CO,
\Q_reg[0]_0 ,
FSM_exp_operation_A_S,
\Q_reg[30] ,
\Q_reg[0]_1 ,
\Q_reg[7]_0 ,
Q,
out,
\Q_reg[47] ,
clk_IBUF_BUFG,
AR);
output [7:0]\Q_reg[7] ;
output [0:0]CO;
input \Q_reg[0]_0 ;
input FSM_exp_operation_A_S;
input [6:0]\Q_reg[30] ;
input \Q_reg[0]_1 ;
input [6:0]\Q_reg[7]_0 ;
input [7:0]Q;
input [3:0]out;
input [0:0]\Q_reg[47] ;
input clk_IBUF_BUFG;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]CO;
wire FSM_exp_operation_A_S;
wire [7:0]Q;
wire \Q[0]_i_1_n_0 ;
wire \Q[1]_i_1_n_0 ;
wire \Q[3]_i_10_n_0 ;
wire \Q[3]_i_3_n_0 ;
wire \Q[3]_i_4_n_0 ;
wire \Q[3]_i_5_n_0 ;
wire \Q[3]_i_7_n_0 ;
wire \Q[3]_i_8_n_0 ;
wire \Q[3]_i_9_n_0 ;
wire \Q[7]_i_2_n_0 ;
wire \Q[7]_i_3_n_0 ;
wire \Q[7]_i_4_n_0 ;
wire \Q[7]_i_5_n_0 ;
wire \Q[7]_i_6_n_0 ;
wire \Q[7]_i_7_n_0 ;
wire \Q[7]_i_8_n_0 ;
wire \Q[7]_i_9_n_0 ;
wire \Q_reg[0]_0 ;
wire \Q_reg[0]_1 ;
wire [6:0]\Q_reg[30] ;
wire \Q_reg[3]_i_1_n_0 ;
wire [0:0]\Q_reg[47] ;
wire [7:0]\Q_reg[7] ;
wire [6:0]\Q_reg[7]_0 ;
wire \Q_reg_n_0_[0] ;
wire \Q_reg_n_0_[1] ;
wire clk_IBUF_BUFG;
wire [3:0]out;
wire [2:0]\NLW_Q_reg[3]_i_1_CO_UNCONNECTED ;
wire [2:0]\NLW_Q_reg[7]_i_1_CO_UNCONNECTED ;
LUT6 #(
.INIT(64'hFFFFDFFF02020808))
\Q[0]_i_1
(.I0(out[0]),
.I1(out[3]),
.I2(out[2]),
.I3(\Q_reg[47] ),
.I4(out[1]),
.I5(\Q_reg_n_0_[0] ),
.O(\Q[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFDFDF7F700002000))
\Q[1]_i_1
(.I0(out[0]),
.I1(out[3]),
.I2(out[2]),
.I3(\Q_reg[47] ),
.I4(out[1]),
.I5(\Q_reg_n_0_[1] ),
.O(\Q[1]_i_1_n_0 ));
LUT3 #(
.INIT(8'h5E))
\Q[3]_i_10
(.I0(\Q_reg_n_0_[1] ),
.I1(Q[0]),
.I2(\Q_reg_n_0_[0] ),
.O(\Q[3]_i_10_n_0 ));
LUT4 #(
.INIT(16'hA5A6))
\Q[3]_i_3
(.I0(FSM_exp_operation_A_S),
.I1(\Q_reg_n_0_[0] ),
.I2(\Q_reg_n_0_[1] ),
.I3(Q[3]),
.O(\Q[3]_i_3_n_0 ));
LUT4 #(
.INIT(16'hA5A6))
\Q[3]_i_4
(.I0(FSM_exp_operation_A_S),
.I1(\Q_reg_n_0_[0] ),
.I2(\Q_reg_n_0_[1] ),
.I3(Q[2]),
.O(\Q[3]_i_4_n_0 ));
LUT4 #(
.INIT(16'hA5A6))
\Q[3]_i_5
(.I0(FSM_exp_operation_A_S),
.I1(\Q_reg_n_0_[0] ),
.I2(\Q_reg_n_0_[1] ),
.I3(Q[1]),
.O(\Q[3]_i_5_n_0 ));
LUT4 #(
.INIT(16'h56A6))
\Q[3]_i_7
(.I0(\Q[3]_i_3_n_0 ),
.I1(\Q_reg[30] [2]),
.I2(\Q_reg[0]_1 ),
.I3(\Q_reg[7]_0 [2]),
.O(\Q[3]_i_7_n_0 ));
LUT4 #(
.INIT(16'h56A6))
\Q[3]_i_8
(.I0(\Q[3]_i_4_n_0 ),
.I1(\Q_reg[30] [1]),
.I2(\Q_reg[0]_1 ),
.I3(\Q_reg[7]_0 [1]),
.O(\Q[3]_i_8_n_0 ));
LUT4 #(
.INIT(16'h56A6))
\Q[3]_i_9
(.I0(\Q[3]_i_5_n_0 ),
.I1(\Q_reg[30] [0]),
.I2(\Q_reg[0]_1 ),
.I3(\Q_reg[7]_0 [0]),
.O(\Q[3]_i_9_n_0 ));
LUT4 #(
.INIT(16'hAA9A))
\Q[7]_i_2
(.I0(FSM_exp_operation_A_S),
.I1(\Q_reg_n_0_[0] ),
.I2(Q[7]),
.I3(\Q_reg_n_0_[1] ),
.O(\Q[7]_i_2_n_0 ));
LUT4 #(
.INIT(16'hA5A6))
\Q[7]_i_3
(.I0(FSM_exp_operation_A_S),
.I1(\Q_reg_n_0_[0] ),
.I2(\Q_reg_n_0_[1] ),
.I3(Q[6]),
.O(\Q[7]_i_3_n_0 ));
LUT4 #(
.INIT(16'hA5A6))
\Q[7]_i_4
(.I0(FSM_exp_operation_A_S),
.I1(\Q_reg_n_0_[0] ),
.I2(\Q_reg_n_0_[1] ),
.I3(Q[5]),
.O(\Q[7]_i_4_n_0 ));
LUT4 #(
.INIT(16'hA5A6))
\Q[7]_i_5
(.I0(FSM_exp_operation_A_S),
.I1(\Q_reg_n_0_[0] ),
.I2(\Q_reg_n_0_[1] ),
.I3(Q[4]),
.O(\Q[7]_i_5_n_0 ));
LUT4 #(
.INIT(16'h56A6))
\Q[7]_i_6
(.I0(\Q[7]_i_2_n_0 ),
.I1(\Q_reg[30] [6]),
.I2(\Q_reg[0]_1 ),
.I3(\Q_reg[7]_0 [6]),
.O(\Q[7]_i_6_n_0 ));
LUT4 #(
.INIT(16'h56A6))
\Q[7]_i_7
(.I0(\Q[7]_i_3_n_0 ),
.I1(\Q_reg[30] [5]),
.I2(\Q_reg[0]_1 ),
.I3(\Q_reg[7]_0 [5]),
.O(\Q[7]_i_7_n_0 ));
LUT4 #(
.INIT(16'h56A6))
\Q[7]_i_8
(.I0(\Q[7]_i_4_n_0 ),
.I1(\Q_reg[30] [4]),
.I2(\Q_reg[0]_1 ),
.I3(\Q_reg[7]_0 [4]),
.O(\Q[7]_i_8_n_0 ));
LUT4 #(
.INIT(16'h56A6))
\Q[7]_i_9
(.I0(\Q[7]_i_5_n_0 ),
.I1(\Q_reg[30] [3]),
.I2(\Q_reg[0]_1 ),
.I3(\Q_reg[7]_0 [3]),
.O(\Q[7]_i_9_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk_IBUF_BUFG),
.CE(1'b1),
.CLR(AR),
.D(\Q[0]_i_1_n_0 ),
.Q(\Q_reg_n_0_[0] ));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(clk_IBUF_BUFG),
.CE(1'b1),
.CLR(AR),
.D(\Q[1]_i_1_n_0 ),
.Q(\Q_reg_n_0_[1] ));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Q_reg[3]_i_1
(.CI(1'b0),
.CO({\Q_reg[3]_i_1_n_0 ,\NLW_Q_reg[3]_i_1_CO_UNCONNECTED [2:0]}),
.CYINIT(\Q_reg[0]_0 ),
.DI({\Q[3]_i_3_n_0 ,\Q[3]_i_4_n_0 ,\Q[3]_i_5_n_0 ,FSM_exp_operation_A_S}),
.O(\Q_reg[7] [3:0]),
.S({\Q[3]_i_7_n_0 ,\Q[3]_i_8_n_0 ,\Q[3]_i_9_n_0 ,\Q[3]_i_10_n_0 }));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Q_reg[7]_i_1
(.CI(\Q_reg[3]_i_1_n_0 ),
.CO({CO,\NLW_Q_reg[7]_i_1_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\Q[7]_i_2_n_0 ,\Q[7]_i_3_n_0 ,\Q[7]_i_4_n_0 ,\Q[7]_i_5_n_0 }),
.O(\Q_reg[7] [7:4]),
.S({\Q[7]_i_6_n_0 ,\Q[7]_i_7_n_0 ,\Q[7]_i_8_n_0 ,\Q[7]_i_9_n_0 }));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized1
(FSM_round_flag,
\Q_reg[0]_0 ,
\Q_reg[31]_0 ,
E,
D,
clk_IBUF_BUFG,
AR);
output FSM_round_flag;
output [24:0]\Q_reg[0]_0 ;
input \Q_reg[31]_0 ;
input [0:0]E;
input [47:0]D;
input clk_IBUF_BUFG;
input [0:0]AR;
wire [0:0]AR;
wire [47:0]D;
wire [0:0]E;
wire FSM_round_flag;
wire \FSM_sequential_state_reg[1]_i_3_n_0 ;
wire \FSM_sequential_state_reg[1]_i_4_n_0 ;
wire \FSM_sequential_state_reg[1]_i_5_n_0 ;
wire \FSM_sequential_state_reg[1]_i_6_n_0 ;
wire \FSM_sequential_state_reg[1]_i_7_n_0 ;
wire [24:0]\Q_reg[0]_0 ;
wire \Q_reg[31]_0 ;
wire \Q_reg_n_0_[0] ;
wire \Q_reg_n_0_[10] ;
wire \Q_reg_n_0_[11] ;
wire \Q_reg_n_0_[12] ;
wire \Q_reg_n_0_[13] ;
wire \Q_reg_n_0_[14] ;
wire \Q_reg_n_0_[15] ;
wire \Q_reg_n_0_[16] ;
wire \Q_reg_n_0_[17] ;
wire \Q_reg_n_0_[18] ;
wire \Q_reg_n_0_[19] ;
wire \Q_reg_n_0_[1] ;
wire \Q_reg_n_0_[20] ;
wire \Q_reg_n_0_[21] ;
wire \Q_reg_n_0_[22] ;
wire \Q_reg_n_0_[2] ;
wire \Q_reg_n_0_[3] ;
wire \Q_reg_n_0_[4] ;
wire \Q_reg_n_0_[5] ;
wire \Q_reg_n_0_[6] ;
wire \Q_reg_n_0_[7] ;
wire \Q_reg_n_0_[8] ;
wire \Q_reg_n_0_[9] ;
wire clk_IBUF_BUFG;
LUT5 #(
.INIT(32'hFFFFFFFE))
\FSM_sequential_state_reg[1]_i_2
(.I0(\FSM_sequential_state_reg[1]_i_3_n_0 ),
.I1(\FSM_sequential_state_reg[1]_i_4_n_0 ),
.I2(\FSM_sequential_state_reg[1]_i_5_n_0 ),
.I3(\FSM_sequential_state_reg[1]_i_6_n_0 ),
.I4(\FSM_sequential_state_reg[1]_i_7_n_0 ),
.O(FSM_round_flag));
LUT6 #(
.INIT(64'hFFFF0000FFFE0000))
\FSM_sequential_state_reg[1]_i_3
(.I0(\Q_reg_n_0_[8] ),
.I1(\Q_reg_n_0_[11] ),
.I2(\Q_reg_n_0_[12] ),
.I3(\Q_reg_n_0_[10] ),
.I4(\Q_reg[31]_0 ),
.I5(\Q_reg_n_0_[9] ),
.O(\FSM_sequential_state_reg[1]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFF0000FFFE0000))
\FSM_sequential_state_reg[1]_i_4
(.I0(\Q_reg_n_0_[3] ),
.I1(\Q_reg_n_0_[6] ),
.I2(\Q_reg_n_0_[7] ),
.I3(\Q_reg_n_0_[5] ),
.I4(\Q_reg[31]_0 ),
.I5(\Q_reg_n_0_[4] ),
.O(\FSM_sequential_state_reg[1]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFF0000FFFE0000))
\FSM_sequential_state_reg[1]_i_5
(.I0(\Q_reg_n_0_[13] ),
.I1(\Q_reg_n_0_[16] ),
.I2(\Q_reg_n_0_[17] ),
.I3(\Q_reg_n_0_[15] ),
.I4(\Q_reg[31]_0 ),
.I5(\Q_reg_n_0_[14] ),
.O(\FSM_sequential_state_reg[1]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFFF0000FFFE0000))
\FSM_sequential_state_reg[1]_i_6
(.I0(\Q_reg_n_0_[18] ),
.I1(\Q_reg_n_0_[21] ),
.I2(\Q_reg_n_0_[22] ),
.I3(\Q_reg_n_0_[20] ),
.I4(\Q_reg[31]_0 ),
.I5(\Q_reg_n_0_[19] ),
.O(\FSM_sequential_state_reg[1]_i_6_n_0 ));
LUT4 #(
.INIT(16'hF0E0))
\FSM_sequential_state_reg[1]_i_7
(.I0(\Q_reg_n_0_[2] ),
.I1(\Q_reg_n_0_[1] ),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg_n_0_[0] ),
.O(\FSM_sequential_state_reg[1]_i_7_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[0]),
.Q(\Q_reg_n_0_[0] ));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[10]),
.Q(\Q_reg_n_0_[10] ));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[11]),
.Q(\Q_reg_n_0_[11] ));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[12]),
.Q(\Q_reg_n_0_[12] ));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[13]),
.Q(\Q_reg_n_0_[13] ));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[14]),
.Q(\Q_reg_n_0_[14] ));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[15]),
.Q(\Q_reg_n_0_[15] ));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[16]),
.Q(\Q_reg_n_0_[16] ));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[17]),
.Q(\Q_reg_n_0_[17] ));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[18]),
.Q(\Q_reg_n_0_[18] ));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[19]),
.Q(\Q_reg_n_0_[19] ));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[1]),
.Q(\Q_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[20]),
.Q(\Q_reg_n_0_[20] ));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[21]),
.Q(\Q_reg_n_0_[21] ));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[22]),
.Q(\Q_reg_n_0_[22] ));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[23]),
.Q(\Q_reg[0]_0 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[24]),
.Q(\Q_reg[0]_0 [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[25]),
.Q(\Q_reg[0]_0 [2]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[26]),
.Q(\Q_reg[0]_0 [3]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[27]),
.Q(\Q_reg[0]_0 [4]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[28]),
.Q(\Q_reg[0]_0 [5]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[29]),
.Q(\Q_reg[0]_0 [6]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[2]),
.Q(\Q_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[30]),
.Q(\Q_reg[0]_0 [7]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[31]),
.Q(\Q_reg[0]_0 [8]));
FDCE #(
.INIT(1'b0))
\Q_reg[32]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[32]),
.Q(\Q_reg[0]_0 [9]));
FDCE #(
.INIT(1'b0))
\Q_reg[33]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[33]),
.Q(\Q_reg[0]_0 [10]));
FDCE #(
.INIT(1'b0))
\Q_reg[34]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[34]),
.Q(\Q_reg[0]_0 [11]));
FDCE #(
.INIT(1'b0))
\Q_reg[35]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[35]),
.Q(\Q_reg[0]_0 [12]));
FDCE #(
.INIT(1'b0))
\Q_reg[36]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[36]),
.Q(\Q_reg[0]_0 [13]));
FDCE #(
.INIT(1'b0))
\Q_reg[37]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[37]),
.Q(\Q_reg[0]_0 [14]));
FDCE #(
.INIT(1'b0))
\Q_reg[38]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[38]),
.Q(\Q_reg[0]_0 [15]));
FDCE #(
.INIT(1'b0))
\Q_reg[39]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[39]),
.Q(\Q_reg[0]_0 [16]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[3]),
.Q(\Q_reg_n_0_[3] ));
FDCE #(
.INIT(1'b0))
\Q_reg[40]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[40]),
.Q(\Q_reg[0]_0 [17]));
FDCE #(
.INIT(1'b0))
\Q_reg[41]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[41]),
.Q(\Q_reg[0]_0 [18]));
FDCE #(
.INIT(1'b0))
\Q_reg[42]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[42]),
.Q(\Q_reg[0]_0 [19]));
FDCE #(
.INIT(1'b0))
\Q_reg[43]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[43]),
.Q(\Q_reg[0]_0 [20]));
FDCE #(
.INIT(1'b0))
\Q_reg[44]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[44]),
.Q(\Q_reg[0]_0 [21]));
FDCE #(
.INIT(1'b0))
\Q_reg[45]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[45]),
.Q(\Q_reg[0]_0 [22]));
FDCE #(
.INIT(1'b0))
\Q_reg[46]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[46]),
.Q(\Q_reg[0]_0 [23]));
FDCE #(
.INIT(1'b0))
\Q_reg[47]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[47]),
.Q(\Q_reg[0]_0 [24]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[4]),
.Q(\Q_reg_n_0_[4] ));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[5]),
.Q(\Q_reg_n_0_[5] ));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[6]),
.Q(\Q_reg_n_0_[6] ));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[7]),
.Q(\Q_reg_n_0_[7] ));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[8]),
.Q(\Q_reg_n_0_[8] ));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[9]),
.Q(\Q_reg_n_0_[9] ));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized2
(D,
Q,
\Q_reg[46] ,
FSM_Shift_Value,
\Q_reg[0]_0 ,
E,
\Q_reg[23]_0 ,
CLK,
AR);
output [22:0]D;
output [0:0]Q;
input [23:0]\Q_reg[46] ;
input FSM_Shift_Value;
input \Q_reg[0]_0 ;
input [0:0]E;
input [23:0]\Q_reg[23]_0 ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [22:0]D;
wire [0:0]E;
wire FSM_Shift_Value;
wire [0:0]Q;
wire \Q_reg[0]_0 ;
wire [23:0]\Q_reg[23]_0 ;
wire [23:0]\Q_reg[46] ;
wire \Q_reg_n_0_[0] ;
wire \Q_reg_n_0_[10] ;
wire \Q_reg_n_0_[11] ;
wire \Q_reg_n_0_[12] ;
wire \Q_reg_n_0_[13] ;
wire \Q_reg_n_0_[14] ;
wire \Q_reg_n_0_[15] ;
wire \Q_reg_n_0_[16] ;
wire \Q_reg_n_0_[17] ;
wire \Q_reg_n_0_[18] ;
wire \Q_reg_n_0_[19] ;
wire \Q_reg_n_0_[1] ;
wire \Q_reg_n_0_[20] ;
wire \Q_reg_n_0_[21] ;
wire \Q_reg_n_0_[22] ;
wire \Q_reg_n_0_[2] ;
wire \Q_reg_n_0_[3] ;
wire \Q_reg_n_0_[4] ;
wire \Q_reg_n_0_[5] ;
wire \Q_reg_n_0_[6] ;
wire \Q_reg_n_0_[7] ;
wire \Q_reg_n_0_[8] ;
wire \Q_reg_n_0_[9] ;
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[0]_i_1__2
(.I0(\Q_reg_n_0_[1] ),
.I1(\Q_reg[46] [1]),
.I2(FSM_Shift_Value),
.I3(\Q_reg_n_0_[0] ),
.I4(\Q_reg[46] [0]),
.I5(\Q_reg[0]_0 ),
.O(D[0]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[10]_i_1__0
(.I0(\Q_reg_n_0_[11] ),
.I1(\Q_reg[46] [11]),
.I2(FSM_Shift_Value),
.I3(\Q_reg_n_0_[10] ),
.I4(\Q_reg[46] [10]),
.I5(\Q_reg[0]_0 ),
.O(D[10]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[11]_i_1__0
(.I0(\Q_reg_n_0_[12] ),
.I1(\Q_reg[46] [12]),
.I2(FSM_Shift_Value),
.I3(\Q_reg_n_0_[11] ),
.I4(\Q_reg[46] [11]),
.I5(\Q_reg[0]_0 ),
.O(D[11]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[12]_i_1__0
(.I0(\Q_reg_n_0_[13] ),
.I1(\Q_reg[46] [13]),
.I2(FSM_Shift_Value),
.I3(\Q_reg_n_0_[12] ),
.I4(\Q_reg[46] [12]),
.I5(\Q_reg[0]_0 ),
.O(D[12]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[13]_i_1__0
(.I0(\Q_reg_n_0_[14] ),
.I1(\Q_reg[46] [14]),
.I2(FSM_Shift_Value),
.I3(\Q_reg_n_0_[13] ),
.I4(\Q_reg[46] [13]),
.I5(\Q_reg[0]_0 ),
.O(D[13]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[14]_i_1__0
(.I0(\Q_reg_n_0_[15] ),
.I1(\Q_reg[46] [15]),
.I2(FSM_Shift_Value),
.I3(\Q_reg_n_0_[14] ),
.I4(\Q_reg[46] [14]),
.I5(\Q_reg[0]_0 ),
.O(D[14]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[15]_i_1__0
(.I0(\Q_reg_n_0_[16] ),
.I1(\Q_reg[46] [16]),
.I2(FSM_Shift_Value),
.I3(\Q_reg_n_0_[15] ),
.I4(\Q_reg[46] [15]),
.I5(\Q_reg[0]_0 ),
.O(D[15]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[16]_i_1__0
(.I0(\Q_reg_n_0_[17] ),
.I1(\Q_reg[46] [17]),
.I2(FSM_Shift_Value),
.I3(\Q_reg_n_0_[16] ),
.I4(\Q_reg[46] [16]),
.I5(\Q_reg[0]_0 ),
.O(D[16]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[17]_i_1__0
(.I0(\Q_reg_n_0_[18] ),
.I1(\Q_reg[46] [18]),
.I2(FSM_Shift_Value),
.I3(\Q_reg_n_0_[17] ),
.I4(\Q_reg[46] [17]),
.I5(\Q_reg[0]_0 ),
.O(D[17]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[18]_i_1__0
(.I0(\Q_reg_n_0_[19] ),
.I1(\Q_reg[46] [19]),
.I2(FSM_Shift_Value),
.I3(\Q_reg_n_0_[18] ),
.I4(\Q_reg[46] [18]),
.I5(\Q_reg[0]_0 ),
.O(D[18]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[19]_i_1__0
(.I0(\Q_reg_n_0_[20] ),
.I1(\Q_reg[46] [20]),
.I2(FSM_Shift_Value),
.I3(\Q_reg_n_0_[19] ),
.I4(\Q_reg[46] [19]),
.I5(\Q_reg[0]_0 ),
.O(D[19]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[1]_i_1__0
(.I0(\Q_reg_n_0_[2] ),
.I1(\Q_reg[46] [2]),
.I2(FSM_Shift_Value),
.I3(\Q_reg_n_0_[1] ),
.I4(\Q_reg[46] [1]),
.I5(\Q_reg[0]_0 ),
.O(D[1]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[20]_i_1__0
(.I0(\Q_reg_n_0_[21] ),
.I1(\Q_reg[46] [21]),
.I2(FSM_Shift_Value),
.I3(\Q_reg_n_0_[20] ),
.I4(\Q_reg[46] [20]),
.I5(\Q_reg[0]_0 ),
.O(D[20]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[21]_i_1__0
(.I0(\Q_reg_n_0_[22] ),
.I1(\Q_reg[46] [22]),
.I2(FSM_Shift_Value),
.I3(\Q_reg_n_0_[21] ),
.I4(\Q_reg[46] [21]),
.I5(\Q_reg[0]_0 ),
.O(D[21]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[22]_i_1__0
(.I0(Q),
.I1(\Q_reg[46] [23]),
.I2(FSM_Shift_Value),
.I3(\Q_reg_n_0_[22] ),
.I4(\Q_reg[46] [22]),
.I5(\Q_reg[0]_0 ),
.O(D[22]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[2]_i_1__0
(.I0(\Q_reg_n_0_[3] ),
.I1(\Q_reg[46] [3]),
.I2(FSM_Shift_Value),
.I3(\Q_reg_n_0_[2] ),
.I4(\Q_reg[46] [2]),
.I5(\Q_reg[0]_0 ),
.O(D[2]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[3]_i_1__0
(.I0(\Q_reg_n_0_[4] ),
.I1(\Q_reg[46] [4]),
.I2(FSM_Shift_Value),
.I3(\Q_reg_n_0_[3] ),
.I4(\Q_reg[46] [3]),
.I5(\Q_reg[0]_0 ),
.O(D[3]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[4]_i_1__0
(.I0(\Q_reg_n_0_[5] ),
.I1(\Q_reg[46] [5]),
.I2(FSM_Shift_Value),
.I3(\Q_reg_n_0_[4] ),
.I4(\Q_reg[46] [4]),
.I5(\Q_reg[0]_0 ),
.O(D[4]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[5]_i_1__0
(.I0(\Q_reg_n_0_[6] ),
.I1(\Q_reg[46] [6]),
.I2(FSM_Shift_Value),
.I3(\Q_reg_n_0_[5] ),
.I4(\Q_reg[46] [5]),
.I5(\Q_reg[0]_0 ),
.O(D[5]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[6]_i_1__0
(.I0(\Q_reg_n_0_[7] ),
.I1(\Q_reg[46] [7]),
.I2(FSM_Shift_Value),
.I3(\Q_reg_n_0_[6] ),
.I4(\Q_reg[46] [6]),
.I5(\Q_reg[0]_0 ),
.O(D[6]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[7]_i_1__0
(.I0(\Q_reg_n_0_[8] ),
.I1(\Q_reg[46] [8]),
.I2(FSM_Shift_Value),
.I3(\Q_reg_n_0_[7] ),
.I4(\Q_reg[46] [7]),
.I5(\Q_reg[0]_0 ),
.O(D[7]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[8]_i_1__1
(.I0(\Q_reg_n_0_[9] ),
.I1(\Q_reg[46] [9]),
.I2(FSM_Shift_Value),
.I3(\Q_reg_n_0_[8] ),
.I4(\Q_reg[46] [8]),
.I5(\Q_reg[0]_0 ),
.O(D[8]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[9]_i_1__0
(.I0(\Q_reg_n_0_[10] ),
.I1(\Q_reg[46] [10]),
.I2(FSM_Shift_Value),
.I3(\Q_reg_n_0_[9] ),
.I4(\Q_reg[46] [9]),
.I5(\Q_reg[0]_0 ),
.O(D[9]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[23]_0 [0]),
.Q(\Q_reg_n_0_[0] ));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[23]_0 [10]),
.Q(\Q_reg_n_0_[10] ));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[23]_0 [11]),
.Q(\Q_reg_n_0_[11] ));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[23]_0 [12]),
.Q(\Q_reg_n_0_[12] ));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[23]_0 [13]),
.Q(\Q_reg_n_0_[13] ));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[23]_0 [14]),
.Q(\Q_reg_n_0_[14] ));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[23]_0 [15]),
.Q(\Q_reg_n_0_[15] ));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[23]_0 [16]),
.Q(\Q_reg_n_0_[16] ));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[23]_0 [17]),
.Q(\Q_reg_n_0_[17] ));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[23]_0 [18]),
.Q(\Q_reg_n_0_[18] ));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[23]_0 [19]),
.Q(\Q_reg_n_0_[19] ));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[23]_0 [1]),
.Q(\Q_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[23]_0 [20]),
.Q(\Q_reg_n_0_[20] ));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[23]_0 [21]),
.Q(\Q_reg_n_0_[21] ));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[23]_0 [22]),
.Q(\Q_reg_n_0_[22] ));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[23]_0 [23]),
.Q(Q));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[23]_0 [2]),
.Q(\Q_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[23]_0 [3]),
.Q(\Q_reg_n_0_[3] ));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[23]_0 [4]),
.Q(\Q_reg_n_0_[4] ));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[23]_0 [5]),
.Q(\Q_reg_n_0_[5] ));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[23]_0 [6]),
.Q(\Q_reg_n_0_[6] ));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[23]_0 [7]),
.Q(\Q_reg_n_0_[7] ));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[23]_0 [8]),
.Q(\Q_reg_n_0_[8] ));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[23]_0 [9]),
.Q(\Q_reg_n_0_[9] ));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized3
(Q,
E,
D,
clk_IBUF_BUFG,
AR);
output [31:0]Q;
input [0:0]E;
input [31:0]D;
input clk_IBUF_BUFG;
input [0:0]AR;
wire [0:0]AR;
wire [31:0]D;
wire [0:0]E;
wire [31:0]Q;
wire clk_IBUF_BUFG;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[9]),
.Q(Q[9]));
endmodule
module RegisterMult
(\Q_reg[0]_0 ,
\Q_reg[31]_0 ,
\Q_reg[0]_1 ,
round_mode_IBUF,
Q,
E,
D,
clk_IBUF_BUFG,
AR);
output \Q_reg[0]_0 ;
output [31:0]\Q_reg[31]_0 ;
output \Q_reg[0]_1 ;
input [1:0]round_mode_IBUF;
input [0:0]Q;
input [0:0]E;
input [31:0]D;
input clk_IBUF_BUFG;
input [0:0]AR;
wire [0:0]AR;
wire [31:0]D;
wire [0:0]E;
wire [0:0]Q;
wire \Q[0]_i_5_n_0 ;
wire \Q[0]_i_6_n_0 ;
wire \Q[0]_i_7_n_0 ;
wire \Q[0]_i_8_n_0 ;
wire \Q[0]_i_9_n_0 ;
wire \Q_reg[0]_0 ;
wire \Q_reg[0]_1 ;
wire [31:0]\Q_reg[31]_0 ;
wire clk_IBUF_BUFG;
wire [1:0]round_mode_IBUF;
LUT4 #(
.INIT(16'h2418))
\FSM_sequential_state_reg[1]_i_8
(.I0(\Q_reg[31]_0 [31]),
.I1(round_mode_IBUF[0]),
.I2(round_mode_IBUF[1]),
.I3(Q),
.O(\Q_reg[0]_1 ));
LUT6 #(
.INIT(64'h0000800000000000))
\Q[0]_i_2
(.I0(\Q[0]_i_5_n_0 ),
.I1(\Q[0]_i_6_n_0 ),
.I2(\Q[0]_i_7_n_0 ),
.I3(\Q[0]_i_8_n_0 ),
.I4(\Q_reg[31]_0 [0]),
.I5(\Q[0]_i_9_n_0 ),
.O(\Q_reg[0]_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\Q[0]_i_5
(.I0(\Q_reg[31]_0 [27]),
.I1(\Q_reg[31]_0 [28]),
.I2(\Q_reg[31]_0 [25]),
.I3(\Q_reg[31]_0 [26]),
.I4(\Q_reg[31]_0 [30]),
.I5(\Q_reg[31]_0 [29]),
.O(\Q[0]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\Q[0]_i_6
(.I0(\Q_reg[31]_0 [9]),
.I1(\Q_reg[31]_0 [10]),
.I2(\Q_reg[31]_0 [7]),
.I3(\Q_reg[31]_0 [8]),
.I4(\Q_reg[31]_0 [12]),
.I5(\Q_reg[31]_0 [11]),
.O(\Q[0]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\Q[0]_i_7
(.I0(\Q_reg[31]_0 [3]),
.I1(\Q_reg[31]_0 [4]),
.I2(\Q_reg[31]_0 [1]),
.I3(\Q_reg[31]_0 [2]),
.I4(\Q_reg[31]_0 [6]),
.I5(\Q_reg[31]_0 [5]),
.O(\Q[0]_i_7_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\Q[0]_i_8
(.I0(\Q_reg[31]_0 [21]),
.I1(\Q_reg[31]_0 [22]),
.I2(\Q_reg[31]_0 [19]),
.I3(\Q_reg[31]_0 [20]),
.I4(\Q_reg[31]_0 [24]),
.I5(\Q_reg[31]_0 [23]),
.O(\Q[0]_i_8_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\Q[0]_i_9
(.I0(\Q_reg[31]_0 [15]),
.I1(\Q_reg[31]_0 [16]),
.I2(\Q_reg[31]_0 [13]),
.I3(\Q_reg[31]_0 [14]),
.I4(\Q_reg[31]_0 [18]),
.I5(\Q_reg[31]_0 [17]),
.O(\Q[0]_i_9_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[0]),
.Q(\Q_reg[31]_0 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[10]),
.Q(\Q_reg[31]_0 [10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[11]),
.Q(\Q_reg[31]_0 [11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[12]),
.Q(\Q_reg[31]_0 [12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[13]),
.Q(\Q_reg[31]_0 [13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[14]),
.Q(\Q_reg[31]_0 [14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[15]),
.Q(\Q_reg[31]_0 [15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[16]),
.Q(\Q_reg[31]_0 [16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[17]),
.Q(\Q_reg[31]_0 [17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[18]),
.Q(\Q_reg[31]_0 [18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[19]),
.Q(\Q_reg[31]_0 [19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[1]),
.Q(\Q_reg[31]_0 [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[20]),
.Q(\Q_reg[31]_0 [20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[21]),
.Q(\Q_reg[31]_0 [21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[22]),
.Q(\Q_reg[31]_0 [22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[23]),
.Q(\Q_reg[31]_0 [23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[24]),
.Q(\Q_reg[31]_0 [24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[25]),
.Q(\Q_reg[31]_0 [25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[26]),
.Q(\Q_reg[31]_0 [26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[27]),
.Q(\Q_reg[31]_0 [27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[28]),
.Q(\Q_reg[31]_0 [28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[29]),
.Q(\Q_reg[31]_0 [29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[2]),
.Q(\Q_reg[31]_0 [2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[30]),
.Q(\Q_reg[31]_0 [30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[31]),
.Q(\Q_reg[31]_0 [31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[3]),
.Q(\Q_reg[31]_0 [3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[4]),
.Q(\Q_reg[31]_0 [4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[5]),
.Q(\Q_reg[31]_0 [5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[6]),
.Q(\Q_reg[31]_0 [6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[7]),
.Q(\Q_reg[31]_0 [7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[8]),
.Q(\Q_reg[31]_0 [8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[9]),
.Q(\Q_reg[31]_0 [9]));
endmodule
(* ORIG_REF_NAME = "RegisterMult" *)
module RegisterMult_4
(B,
Q,
\Q_reg[0]_0 ,
E,
\Data_MY[31] ,
clk_IBUF_BUFG,
AR);
output [12:0]B;
output [31:0]Q;
output \Q_reg[0]_0 ;
input [0:0]E;
input [31:0]\Data_MY[31] ;
input clk_IBUF_BUFG;
input [0:0]AR;
wire [0:0]AR;
wire [12:0]B;
wire [31:0]\Data_MY[31] ;
wire Data_S_o0_i_29_n_0;
wire Data_S_o0_i_2_n_0;
wire Data_S_o0_i_30_n_0;
wire Data_S_o0_i_31_n_0;
wire Data_S_o0_i_32_n_0;
wire Data_S_o0_i_33_n_0;
wire Data_S_o0_i_34_n_0;
wire Data_S_o0_i_35_n_0;
wire Data_S_o0_i_36_n_0;
wire Data_S_o0_i_37_n_0;
wire Data_S_o0_i_38_n_0;
wire Data_S_o0_i_39_n_0;
wire Data_S_o0_i_3_n_0;
wire Data_S_o0_i_40_n_0;
wire Data_S_o0_i_4_n_0;
wire [0:0]E;
wire [31:0]Q;
wire \Q[0]_i_10_n_0 ;
wire \Q[0]_i_11_n_0 ;
wire \Q[0]_i_12_n_0 ;
wire \Q[0]_i_13_n_0 ;
wire \Q[0]_i_14_n_0 ;
wire \Q_reg[0]_0 ;
wire clk_IBUF_BUFG;
wire [3:1]NLW_Data_S_o0_i_1_CO_UNCONNECTED;
wire [3:0]NLW_Data_S_o0_i_1_O_UNCONNECTED;
wire [2:0]NLW_Data_S_o0_i_2_CO_UNCONNECTED;
wire [2:0]NLW_Data_S_o0_i_3_CO_UNCONNECTED;
wire [2:0]NLW_Data_S_o0_i_4_CO_UNCONNECTED;
CARRY4 Data_S_o0_i_1
(.CI(Data_S_o0_i_2_n_0),
.CO({NLW_Data_S_o0_i_1_CO_UNCONNECTED[3:1],B[12]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_Data_S_o0_i_1_O_UNCONNECTED[3:0]),
.S({1'b0,1'b0,1'b0,1'b1}));
CARRY4 Data_S_o0_i_2
(.CI(Data_S_o0_i_3_n_0),
.CO({Data_S_o0_i_2_n_0,NLW_Data_S_o0_i_2_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI({Q[11],Q[22:20]}),
.O(B[11:8]),
.S({Data_S_o0_i_29_n_0,Data_S_o0_i_30_n_0,Data_S_o0_i_31_n_0,Data_S_o0_i_32_n_0}));
LUT1 #(
.INIT(2'h1))
Data_S_o0_i_29
(.I0(Q[11]),
.O(Data_S_o0_i_29_n_0));
CARRY4 Data_S_o0_i_3
(.CI(Data_S_o0_i_4_n_0),
.CO({Data_S_o0_i_3_n_0,NLW_Data_S_o0_i_3_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(Q[19:16]),
.O(B[7:4]),
.S({Data_S_o0_i_33_n_0,Data_S_o0_i_34_n_0,Data_S_o0_i_35_n_0,Data_S_o0_i_36_n_0}));
LUT2 #(
.INIT(4'h6))
Data_S_o0_i_30
(.I0(Q[22]),
.I1(Q[10]),
.O(Data_S_o0_i_30_n_0));
LUT2 #(
.INIT(4'h6))
Data_S_o0_i_31
(.I0(Q[21]),
.I1(Q[9]),
.O(Data_S_o0_i_31_n_0));
LUT2 #(
.INIT(4'h6))
Data_S_o0_i_32
(.I0(Q[20]),
.I1(Q[8]),
.O(Data_S_o0_i_32_n_0));
LUT2 #(
.INIT(4'h6))
Data_S_o0_i_33
(.I0(Q[19]),
.I1(Q[7]),
.O(Data_S_o0_i_33_n_0));
LUT2 #(
.INIT(4'h6))
Data_S_o0_i_34
(.I0(Q[18]),
.I1(Q[6]),
.O(Data_S_o0_i_34_n_0));
LUT2 #(
.INIT(4'h6))
Data_S_o0_i_35
(.I0(Q[17]),
.I1(Q[5]),
.O(Data_S_o0_i_35_n_0));
LUT2 #(
.INIT(4'h6))
Data_S_o0_i_36
(.I0(Q[16]),
.I1(Q[4]),
.O(Data_S_o0_i_36_n_0));
LUT2 #(
.INIT(4'h6))
Data_S_o0_i_37
(.I0(Q[15]),
.I1(Q[3]),
.O(Data_S_o0_i_37_n_0));
LUT2 #(
.INIT(4'h6))
Data_S_o0_i_38
(.I0(Q[14]),
.I1(Q[2]),
.O(Data_S_o0_i_38_n_0));
LUT2 #(
.INIT(4'h6))
Data_S_o0_i_39
(.I0(Q[13]),
.I1(Q[1]),
.O(Data_S_o0_i_39_n_0));
CARRY4 Data_S_o0_i_4
(.CI(1'b0),
.CO({Data_S_o0_i_4_n_0,NLW_Data_S_o0_i_4_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(Q[15:12]),
.O(B[3:0]),
.S({Data_S_o0_i_37_n_0,Data_S_o0_i_38_n_0,Data_S_o0_i_39_n_0,Data_S_o0_i_40_n_0}));
LUT2 #(
.INIT(4'h6))
Data_S_o0_i_40
(.I0(Q[12]),
.I1(Q[0]),
.O(Data_S_o0_i_40_n_0));
LUT6 #(
.INIT(64'h0000000000000001))
\Q[0]_i_10
(.I0(Q[27]),
.I1(Q[28]),
.I2(Q[25]),
.I3(Q[26]),
.I4(Q[30]),
.I5(Q[29]),
.O(\Q[0]_i_10_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\Q[0]_i_11
(.I0(Q[9]),
.I1(Q[10]),
.I2(Q[7]),
.I3(Q[8]),
.I4(Q[12]),
.I5(Q[11]),
.O(\Q[0]_i_11_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\Q[0]_i_12
(.I0(Q[3]),
.I1(Q[4]),
.I2(Q[1]),
.I3(Q[2]),
.I4(Q[6]),
.I5(Q[5]),
.O(\Q[0]_i_12_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\Q[0]_i_13
(.I0(Q[21]),
.I1(Q[22]),
.I2(Q[19]),
.I3(Q[20]),
.I4(Q[24]),
.I5(Q[23]),
.O(\Q[0]_i_13_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\Q[0]_i_14
(.I0(Q[15]),
.I1(Q[16]),
.I2(Q[13]),
.I3(Q[14]),
.I4(Q[18]),
.I5(Q[17]),
.O(\Q[0]_i_14_n_0 ));
LUT6 #(
.INIT(64'h0000800000000000))
\Q[0]_i_3
(.I0(\Q[0]_i_10_n_0 ),
.I1(\Q[0]_i_11_n_0 ),
.I2(\Q[0]_i_12_n_0 ),
.I3(\Q[0]_i_13_n_0 ),
.I4(Q[0]),
.I5(\Q[0]_i_14_n_0 ),
.O(\Q_reg[0]_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(\Data_MY[31] [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(\Data_MY[31] [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(\Data_MY[31] [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(\Data_MY[31] [12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(\Data_MY[31] [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(\Data_MY[31] [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(\Data_MY[31] [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(\Data_MY[31] [16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(\Data_MY[31] [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(\Data_MY[31] [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(\Data_MY[31] [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(\Data_MY[31] [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(\Data_MY[31] [20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(\Data_MY[31] [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(\Data_MY[31] [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(\Data_MY[31] [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(\Data_MY[31] [24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(\Data_MY[31] [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(\Data_MY[31] [26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(\Data_MY[31] [27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(\Data_MY[31] [28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(\Data_MY[31] [29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(\Data_MY[31] [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(\Data_MY[31] [30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(\Data_MY[31] [31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(\Data_MY[31] [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(\Data_MY[31] [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(\Data_MY[31] [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(\Data_MY[31] [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(\Data_MY[31] [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(\Data_MY[31] [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(\Data_MY[31] [9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterMult" *)
module RegisterMult__parameterized0
(D,
Q,
\Q_reg[3]_0 ,
\Q_reg[0]_0 ,
Overflow_flag_A,
\Q_reg[0]_1 ,
\Q_reg[23] ,
\FSM_sequential_state_reg_reg[0] ,
\Q_reg[0]_2 ,
clk_IBUF_BUFG,
AR);
output [7:0]D;
output [7:0]Q;
output \Q_reg[3]_0 ;
input \Q_reg[0]_0 ;
input Overflow_flag_A;
input \Q_reg[0]_1 ;
input [0:0]\Q_reg[23] ;
input [0:0]\FSM_sequential_state_reg_reg[0] ;
input [8:0]\Q_reg[0]_2 ;
input clk_IBUF_BUFG;
input [0:0]AR;
wire [0:0]AR;
wire [7:0]D;
wire [0:0]\FSM_sequential_state_reg_reg[0] ;
wire Overflow_flag_A;
wire [7:0]Q;
wire \Q_reg[0]_0 ;
wire \Q_reg[0]_1 ;
wire [8:0]\Q_reg[0]_2 ;
wire [0:0]\Q_reg[23] ;
wire \Q_reg[3]_0 ;
wire \Q_reg_n_0_[0] ;
wire clk_IBUF_BUFG;
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'hFFFE))
\Q[23]_i_1__1
(.I0(\Q_reg[0]_0 ),
.I1(Overflow_flag_A),
.I2(Q[7]),
.I3(\Q_reg_n_0_[0] ),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'hFFFE))
\Q[24]_i_1
(.I0(\Q_reg[0]_0 ),
.I1(Overflow_flag_A),
.I2(Q[7]),
.I3(Q[0]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'hFFFE))
\Q[25]_i_1
(.I0(\Q_reg[0]_0 ),
.I1(Overflow_flag_A),
.I2(Q[7]),
.I3(Q[1]),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'hFFFE))
\Q[26]_i_1
(.I0(\Q_reg[0]_0 ),
.I1(Overflow_flag_A),
.I2(Q[7]),
.I3(Q[2]),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'hFFFE))
\Q[27]_i_1
(.I0(\Q_reg[0]_0 ),
.I1(Overflow_flag_A),
.I2(Q[7]),
.I3(Q[3]),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'hFFFE))
\Q[28]_i_1
(.I0(\Q_reg[0]_0 ),
.I1(Overflow_flag_A),
.I2(Q[7]),
.I3(Q[4]),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'hFFFE))
\Q[29]_i_1
(.I0(\Q_reg[0]_0 ),
.I1(Overflow_flag_A),
.I2(Q[7]),
.I3(Q[5]),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'hFFFE))
\Q[30]_i_1
(.I0(\Q_reg[0]_0 ),
.I1(Overflow_flag_A),
.I2(Q[7]),
.I3(Q[6]),
.O(D[7]));
LUT3 #(
.INIT(8'hB8))
\Q[3]_i_2
(.I0(\Q_reg_n_0_[0] ),
.I1(\Q_reg[0]_1 ),
.I2(\Q_reg[23] ),
.O(\Q_reg[3]_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk_IBUF_BUFG),
.CE(\FSM_sequential_state_reg_reg[0] ),
.CLR(AR),
.D(\Q_reg[0]_2 [0]),
.Q(\Q_reg_n_0_[0] ));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(clk_IBUF_BUFG),
.CE(\FSM_sequential_state_reg_reg[0] ),
.CLR(AR),
.D(\Q_reg[0]_2 [1]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(clk_IBUF_BUFG),
.CE(\FSM_sequential_state_reg_reg[0] ),
.CLR(AR),
.D(\Q_reg[0]_2 [2]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(clk_IBUF_BUFG),
.CE(\FSM_sequential_state_reg_reg[0] ),
.CLR(AR),
.D(\Q_reg[0]_2 [3]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(clk_IBUF_BUFG),
.CE(\FSM_sequential_state_reg_reg[0] ),
.CLR(AR),
.D(\Q_reg[0]_2 [4]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(clk_IBUF_BUFG),
.CE(\FSM_sequential_state_reg_reg[0] ),
.CLR(AR),
.D(\Q_reg[0]_2 [5]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(clk_IBUF_BUFG),
.CE(\FSM_sequential_state_reg_reg[0] ),
.CLR(AR),
.D(\Q_reg[0]_2 [6]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(clk_IBUF_BUFG),
.CE(\FSM_sequential_state_reg_reg[0] ),
.CLR(AR),
.D(\Q_reg[0]_2 [7]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(clk_IBUF_BUFG),
.CE(\FSM_sequential_state_reg_reg[0] ),
.CLR(AR),
.D(\Q_reg[0]_2 [8]),
.Q(Q[7]));
endmodule
(* ORIG_REF_NAME = "RegisterMult" *)
module RegisterMult__parameterized1
(Overflow_flag_A,
D,
overflow_flag_OBUF,
E,
O,
clk_IBUF_BUFG,
AR,
Q,
\Q_reg[31] ,
\Q_reg[8] ,
\Q_reg[0]_0 );
output Overflow_flag_A;
output [0:0]D;
output overflow_flag_OBUF;
input [0:0]E;
input [0:0]O;
input clk_IBUF_BUFG;
input [0:0]AR;
input [0:0]Q;
input [0:0]\Q_reg[31] ;
input [0:0]\Q_reg[8] ;
input \Q_reg[0]_0 ;
wire [0:0]AR;
wire [0:0]D;
wire [0:0]E;
wire [0:0]O;
wire Overflow_flag_A;
wire [0:0]Q;
wire \Q_reg[0]_0 ;
wire [0:0]\Q_reg[31] ;
wire [0:0]\Q_reg[8] ;
wire clk_IBUF_BUFG;
wire overflow_flag_OBUF;
LUT5 #(
.INIT(32'h000F0006))
\Q[31]_i_2
(.I0(Q),
.I1(\Q_reg[31] ),
.I2(Overflow_flag_A),
.I3(\Q_reg[8] ),
.I4(\Q_reg[0]_0 ),
.O(D));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(O),
.Q(Overflow_flag_A));
LUT2 #(
.INIT(4'hE))
overflow_flag_OBUF_inst_i_1
(.I0(Overflow_flag_A),
.I1(\Q_reg[8] ),
.O(overflow_flag_OBUF));
endmodule
(* ORIG_REF_NAME = "RegisterMult" *)
module RegisterMult__parameterized2
(\Q_reg[22] ,
D,
\Q_reg[0]_0 ,
\Q_reg[0]_1 ,
\Q_reg[0]_2 ,
clk_IBUF_BUFG,
AR,
\Q_reg[22]_0 ,
Overflow_flag_A,
Q,
\Q_reg[0]_3 );
output \Q_reg[22] ;
output [22:0]D;
output \Q_reg[0]_0 ;
output \Q_reg[0]_1 ;
input \Q_reg[0]_2 ;
input clk_IBUF_BUFG;
input [0:0]AR;
input [22:0]\Q_reg[22]_0 ;
input Overflow_flag_A;
input [0:0]Q;
input [6:0]\Q_reg[0]_3 ;
wire [0:0]AR;
wire [22:0]D;
wire Overflow_flag_A;
wire [0:0]Q;
wire \Q_reg[0]_0 ;
wire \Q_reg[0]_1 ;
wire \Q_reg[0]_2 ;
wire [6:0]\Q_reg[0]_3 ;
wire \Q_reg[22] ;
wire [22:0]\Q_reg[22]_0 ;
wire clk_IBUF_BUFG;
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h0002))
\Q[0]_i_1__0
(.I0(\Q_reg[22]_0 [0]),
.I1(\Q_reg[22] ),
.I2(Overflow_flag_A),
.I3(Q),
.O(D[0]));
LUT6 #(
.INIT(64'h7F00FF00FF00FF00))
\Q[0]_i_2__0
(.I0(\Q_reg[0]_3 [0]),
.I1(\Q_reg[0]_3 [3]),
.I2(\Q_reg[0]_3 [4]),
.I3(\Q_reg[0]_1 ),
.I4(\Q_reg[0]_3 [2]),
.I5(\Q_reg[0]_3 [1]),
.O(\Q_reg[0]_0 ));
LUT2 #(
.INIT(4'h1))
\Q[0]_i_3__0
(.I0(\Q_reg[0]_3 [5]),
.I1(\Q_reg[0]_3 [6]),
.O(\Q_reg[0]_1 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h0002))
\Q[10]_i_1
(.I0(\Q_reg[22]_0 [10]),
.I1(\Q_reg[22] ),
.I2(Overflow_flag_A),
.I3(Q),
.O(D[10]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h0002))
\Q[11]_i_1
(.I0(\Q_reg[22]_0 [11]),
.I1(\Q_reg[22] ),
.I2(Overflow_flag_A),
.I3(Q),
.O(D[11]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h0002))
\Q[12]_i_1
(.I0(\Q_reg[22]_0 [12]),
.I1(\Q_reg[22] ),
.I2(Overflow_flag_A),
.I3(Q),
.O(D[12]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h0002))
\Q[13]_i_1
(.I0(\Q_reg[22]_0 [13]),
.I1(\Q_reg[22] ),
.I2(Overflow_flag_A),
.I3(Q),
.O(D[13]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h0002))
\Q[14]_i_1
(.I0(\Q_reg[22]_0 [14]),
.I1(\Q_reg[22] ),
.I2(Overflow_flag_A),
.I3(Q),
.O(D[14]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h0002))
\Q[15]_i_1
(.I0(\Q_reg[22]_0 [15]),
.I1(\Q_reg[22] ),
.I2(Overflow_flag_A),
.I3(Q),
.O(D[15]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h0002))
\Q[16]_i_1
(.I0(\Q_reg[22]_0 [16]),
.I1(\Q_reg[22] ),
.I2(Overflow_flag_A),
.I3(Q),
.O(D[16]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h0002))
\Q[17]_i_1
(.I0(\Q_reg[22]_0 [17]),
.I1(\Q_reg[22] ),
.I2(Overflow_flag_A),
.I3(Q),
.O(D[17]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h0002))
\Q[18]_i_1
(.I0(\Q_reg[22]_0 [18]),
.I1(\Q_reg[22] ),
.I2(Overflow_flag_A),
.I3(Q),
.O(D[18]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h0002))
\Q[19]_i_1
(.I0(\Q_reg[22]_0 [19]),
.I1(\Q_reg[22] ),
.I2(Overflow_flag_A),
.I3(Q),
.O(D[19]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h0002))
\Q[1]_i_1
(.I0(\Q_reg[22]_0 [1]),
.I1(\Q_reg[22] ),
.I2(Overflow_flag_A),
.I3(Q),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'h0002))
\Q[20]_i_1
(.I0(\Q_reg[22]_0 [20]),
.I1(\Q_reg[22] ),
.I2(Overflow_flag_A),
.I3(Q),
.O(D[20]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'h0002))
\Q[21]_i_1
(.I0(\Q_reg[22]_0 [21]),
.I1(\Q_reg[22] ),
.I2(Overflow_flag_A),
.I3(Q),
.O(D[21]));
LUT4 #(
.INIT(16'h0002))
\Q[22]_i_1
(.I0(\Q_reg[22]_0 [22]),
.I1(\Q_reg[22] ),
.I2(Overflow_flag_A),
.I3(Q),
.O(D[22]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h0002))
\Q[2]_i_1
(.I0(\Q_reg[22]_0 [2]),
.I1(\Q_reg[22] ),
.I2(Overflow_flag_A),
.I3(Q),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h0002))
\Q[3]_i_1
(.I0(\Q_reg[22]_0 [3]),
.I1(\Q_reg[22] ),
.I2(Overflow_flag_A),
.I3(Q),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0002))
\Q[4]_i_1
(.I0(\Q_reg[22]_0 [4]),
.I1(\Q_reg[22] ),
.I2(Overflow_flag_A),
.I3(Q),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0002))
\Q[5]_i_1
(.I0(\Q_reg[22]_0 [5]),
.I1(\Q_reg[22] ),
.I2(Overflow_flag_A),
.I3(Q),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h0002))
\Q[6]_i_1
(.I0(\Q_reg[22]_0 [6]),
.I1(\Q_reg[22] ),
.I2(Overflow_flag_A),
.I3(Q),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h0002))
\Q[7]_i_1
(.I0(\Q_reg[22]_0 [7]),
.I1(\Q_reg[22] ),
.I2(Overflow_flag_A),
.I3(Q),
.O(D[7]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h0002))
\Q[8]_i_1__0
(.I0(\Q_reg[22]_0 [8]),
.I1(\Q_reg[22] ),
.I2(Overflow_flag_A),
.I3(Q),
.O(D[8]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h0002))
\Q[9]_i_1
(.I0(\Q_reg[22]_0 [9]),
.I1(\Q_reg[22] ),
.I2(Overflow_flag_A),
.I3(Q),
.O(D[9]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk_IBUF_BUFG),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg[0]_2 ),
.Q(\Q_reg[22] ));
endmodule
(* ORIG_REF_NAME = "RegisterMult" *)
module RegisterMult__parameterized3
(O6,
Q,
\Q_reg[0]_0 ,
E,
D,
clk_IBUF_BUFG,
AR);
output [23:0]O6;
output [22:0]Q;
output [0:0]\Q_reg[0]_0 ;
input [0:0]E;
input [23:0]D;
input clk_IBUF_BUFG;
input [0:0]AR;
wire [0:0]AR;
wire [23:0]D;
wire [0:0]E;
wire [23:0]O6;
wire [22:0]Q;
wire \Q[4]_i_2_n_0 ;
wire \Q[4]_i_4_n_0 ;
wire \Q[4]_i_5_n_0 ;
wire [0:0]\Q_reg[0]_0 ;
wire \Q_reg[12]_i_1_n_0 ;
wire \Q_reg[16]_i_1_n_0 ;
wire \Q_reg[20]_i_1_n_0 ;
wire \Q_reg[4]_i_1_n_0 ;
wire \Q_reg[8]_i_1_n_0 ;
wire \Q_reg_n_0_[23] ;
wire clk_IBUF_BUFG;
wire [2:0]\NLW_Q_reg[12]_i_1_CO_UNCONNECTED ;
wire [2:0]\NLW_Q_reg[16]_i_1_CO_UNCONNECTED ;
wire [2:0]\NLW_Q_reg[20]_i_1_CO_UNCONNECTED ;
wire [2:0]\NLW_Q_reg[23]_i_2_CO_UNCONNECTED ;
wire [3:3]\NLW_Q_reg[23]_i_2_O_UNCONNECTED ;
wire [2:0]\NLW_Q_reg[4]_i_1_CO_UNCONNECTED ;
wire [2:0]\NLW_Q_reg[8]_i_1_CO_UNCONNECTED ;
LUT1 #(
.INIT(2'h1))
\Q[0]_i_1__1
(.I0(Q[0]),
.O(\Q_reg[0]_0 ));
LUT1 #(
.INIT(2'h1))
\Q[4]_i_2
(.I0(Q[4]),
.O(\Q[4]_i_2_n_0 ));
LUT1 #(
.INIT(2'h1))
\Q[4]_i_4
(.I0(Q[2]),
.O(\Q[4]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\Q[4]_i_5
(.I0(Q[1]),
.O(\Q[4]_i_5_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[12]),
.Q(Q[12]));
CARRY4 \Q_reg[12]_i_1
(.CI(\Q_reg[8]_i_1_n_0 ),
.CO({\Q_reg[12]_i_1_n_0 ,\NLW_Q_reg[12]_i_1_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(O6[11:8]),
.S(Q[12:9]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[16]),
.Q(Q[16]));
CARRY4 \Q_reg[16]_i_1
(.CI(\Q_reg[12]_i_1_n_0 ),
.CO({\Q_reg[16]_i_1_n_0 ,\NLW_Q_reg[16]_i_1_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(O6[15:12]),
.S(Q[16:13]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[20]),
.Q(Q[20]));
CARRY4 \Q_reg[20]_i_1
(.CI(\Q_reg[16]_i_1_n_0 ),
.CO({\Q_reg[20]_i_1_n_0 ,\NLW_Q_reg[20]_i_1_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(O6[19:16]),
.S(Q[20:17]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[23]),
.Q(\Q_reg_n_0_[23] ));
CARRY4 \Q_reg[23]_i_2
(.CI(\Q_reg[20]_i_1_n_0 ),
.CO({O6[23],\NLW_Q_reg[23]_i_2_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_Q_reg[23]_i_2_O_UNCONNECTED [3],O6[22:20]}),
.S({1'b1,\Q_reg_n_0_[23] ,Q[22:21]}));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[4]),
.Q(Q[4]));
CARRY4 \Q_reg[4]_i_1
(.CI(1'b0),
.CO({\Q_reg[4]_i_1_n_0 ,\NLW_Q_reg[4]_i_1_CO_UNCONNECTED [2:0]}),
.CYINIT(Q[0]),
.DI({Q[4],1'b0,Q[2:1]}),
.O(O6[3:0]),
.S({\Q[4]_i_2_n_0 ,Q[3],\Q[4]_i_4_n_0 ,\Q[4]_i_5_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[8]),
.Q(Q[8]));
CARRY4 \Q_reg[8]_i_1
(.CI(\Q_reg[4]_i_1_n_0 ),
.CO({\Q_reg[8]_i_1_n_0 ,\NLW_Q_reg[8]_i_1_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(O6[7:4]),
.S(Q[8:5]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(clk_IBUF_BUFG),
.CE(E),
.CLR(AR),
.D(D[9]),
.Q(Q[9]));
endmodule
module Sgf_Multiplication
(FSM_round_flag,
\Q_reg[0] ,
clk_IBUF_BUFG,
Q,
\Q_reg[22] ,
B,
\Q_reg[31] ,
E,
AR);
output FSM_round_flag;
output [24:0]\Q_reg[0] ;
input clk_IBUF_BUFG;
input [22:0]Q;
input [22:0]\Q_reg[22] ;
input [12:0]B;
input \Q_reg[31] ;
input [0:0]E;
input [0:0]AR;
wire [0:0]AR;
wire [12:0]B;
wire [37:12]Data_B_i;
wire [0:0]E;
wire FSM_round_flag;
wire [22:0]Q;
wire [24:0]\Q_reg[0] ;
wire [22:0]\Q_reg[22] ;
wire \Q_reg[31] ;
wire clk_IBUF_BUFG;
wire \genblk1.Final_n_0 ;
wire \genblk1.Final_n_1 ;
wire \genblk1.Final_n_10 ;
wire \genblk1.Final_n_11 ;
wire \genblk1.Final_n_12 ;
wire \genblk1.Final_n_13 ;
wire \genblk1.Final_n_14 ;
wire \genblk1.Final_n_15 ;
wire \genblk1.Final_n_16 ;
wire \genblk1.Final_n_17 ;
wire \genblk1.Final_n_18 ;
wire \genblk1.Final_n_19 ;
wire \genblk1.Final_n_2 ;
wire \genblk1.Final_n_20 ;
wire \genblk1.Final_n_21 ;
wire \genblk1.Final_n_22 ;
wire \genblk1.Final_n_23 ;
wire \genblk1.Final_n_24 ;
wire \genblk1.Final_n_25 ;
wire \genblk1.Final_n_26 ;
wire \genblk1.Final_n_27 ;
wire \genblk1.Final_n_28 ;
wire \genblk1.Final_n_29 ;
wire \genblk1.Final_n_3 ;
wire \genblk1.Final_n_30 ;
wire \genblk1.Final_n_31 ;
wire \genblk1.Final_n_32 ;
wire \genblk1.Final_n_33 ;
wire \genblk1.Final_n_34 ;
wire \genblk1.Final_n_35 ;
wire \genblk1.Final_n_4 ;
wire \genblk1.Final_n_5 ;
wire \genblk1.Final_n_6 ;
wire \genblk1.Final_n_7 ;
wire \genblk1.Final_n_8 ;
wire \genblk1.Final_n_9 ;
wire \genblk1.Subtr_1_n_0 ;
wire \genblk1.Subtr_1_n_1 ;
wire \genblk1.Subtr_1_n_10 ;
wire \genblk1.Subtr_1_n_11 ;
wire \genblk1.Subtr_1_n_12 ;
wire \genblk1.Subtr_1_n_13 ;
wire \genblk1.Subtr_1_n_14 ;
wire \genblk1.Subtr_1_n_15 ;
wire \genblk1.Subtr_1_n_16 ;
wire \genblk1.Subtr_1_n_17 ;
wire \genblk1.Subtr_1_n_18 ;
wire \genblk1.Subtr_1_n_19 ;
wire \genblk1.Subtr_1_n_2 ;
wire \genblk1.Subtr_1_n_20 ;
wire \genblk1.Subtr_1_n_21 ;
wire \genblk1.Subtr_1_n_22 ;
wire \genblk1.Subtr_1_n_23 ;
wire \genblk1.Subtr_1_n_24 ;
wire \genblk1.Subtr_1_n_25 ;
wire \genblk1.Subtr_1_n_26 ;
wire \genblk1.Subtr_1_n_27 ;
wire \genblk1.Subtr_1_n_28 ;
wire \genblk1.Subtr_1_n_29 ;
wire \genblk1.Subtr_1_n_3 ;
wire \genblk1.Subtr_1_n_30 ;
wire \genblk1.Subtr_1_n_31 ;
wire \genblk1.Subtr_1_n_32 ;
wire \genblk1.Subtr_1_n_33 ;
wire \genblk1.Subtr_1_n_34 ;
wire \genblk1.Subtr_1_n_35 ;
wire \genblk1.Subtr_1_n_36 ;
wire \genblk1.Subtr_1_n_37 ;
wire \genblk1.Subtr_1_n_38 ;
wire \genblk1.Subtr_1_n_39 ;
wire \genblk1.Subtr_1_n_4 ;
wire \genblk1.Subtr_1_n_40 ;
wire \genblk1.Subtr_1_n_41 ;
wire \genblk1.Subtr_1_n_42 ;
wire \genblk1.Subtr_1_n_43 ;
wire \genblk1.Subtr_1_n_44 ;
wire \genblk1.Subtr_1_n_45 ;
wire \genblk1.Subtr_1_n_46 ;
wire \genblk1.Subtr_1_n_47 ;
wire \genblk1.Subtr_1_n_5 ;
wire \genblk1.Subtr_1_n_6 ;
wire \genblk1.Subtr_1_n_7 ;
wire \genblk1.Subtr_1_n_8 ;
wire \genblk1.Subtr_1_n_9 ;
wire \genblk1.left_n_0 ;
wire \genblk1.left_n_1 ;
wire \genblk1.left_n_10 ;
wire \genblk1.left_n_11 ;
wire \genblk1.left_n_12 ;
wire \genblk1.left_n_13 ;
wire \genblk1.left_n_14 ;
wire \genblk1.left_n_15 ;
wire \genblk1.left_n_16 ;
wire \genblk1.left_n_17 ;
wire \genblk1.left_n_18 ;
wire \genblk1.left_n_19 ;
wire \genblk1.left_n_2 ;
wire \genblk1.left_n_20 ;
wire \genblk1.left_n_21 ;
wire \genblk1.left_n_22 ;
wire \genblk1.left_n_23 ;
wire \genblk1.left_n_24 ;
wire \genblk1.left_n_25 ;
wire \genblk1.left_n_26 ;
wire \genblk1.left_n_27 ;
wire \genblk1.left_n_28 ;
wire \genblk1.left_n_29 ;
wire \genblk1.left_n_3 ;
wire \genblk1.left_n_30 ;
wire \genblk1.left_n_31 ;
wire \genblk1.left_n_32 ;
wire \genblk1.left_n_33 ;
wire \genblk1.left_n_4 ;
wire \genblk1.left_n_5 ;
wire \genblk1.left_n_6 ;
wire \genblk1.left_n_7 ;
wire \genblk1.left_n_8 ;
wire \genblk1.left_n_9 ;
wire \genblk1.right_n_0 ;
wire \genblk1.right_n_1 ;
wire \genblk1.right_n_10 ;
wire \genblk1.right_n_11 ;
wire \genblk1.right_n_12 ;
wire \genblk1.right_n_13 ;
wire \genblk1.right_n_14 ;
wire \genblk1.right_n_15 ;
wire \genblk1.right_n_16 ;
wire \genblk1.right_n_17 ;
wire \genblk1.right_n_18 ;
wire \genblk1.right_n_19 ;
wire \genblk1.right_n_2 ;
wire \genblk1.right_n_20 ;
wire \genblk1.right_n_21 ;
wire \genblk1.right_n_22 ;
wire \genblk1.right_n_23 ;
wire \genblk1.right_n_24 ;
wire \genblk1.right_n_3 ;
wire \genblk1.right_n_4 ;
wire \genblk1.right_n_5 ;
wire \genblk1.right_n_6 ;
wire \genblk1.right_n_7 ;
wire \genblk1.right_n_8 ;
wire \genblk1.right_n_9 ;
adder__parameterized0 \genblk1.Final
(.D({\genblk1.Final_n_0 ,\genblk1.Final_n_1 ,\genblk1.Final_n_2 ,\genblk1.Final_n_3 ,\genblk1.Final_n_4 ,\genblk1.Final_n_5 ,\genblk1.Final_n_6 ,\genblk1.Final_n_7 ,\genblk1.Final_n_8 ,\genblk1.Final_n_9 ,\genblk1.Final_n_10 ,\genblk1.Final_n_11 ,\genblk1.Final_n_12 ,\genblk1.Final_n_13 ,\genblk1.Final_n_14 ,\genblk1.Final_n_15 ,\genblk1.Final_n_16 ,\genblk1.Final_n_17 ,\genblk1.Final_n_18 ,\genblk1.Final_n_19 ,\genblk1.Final_n_20 ,\genblk1.Final_n_21 ,\genblk1.Final_n_22 ,\genblk1.Final_n_23 ,\genblk1.Final_n_24 ,\genblk1.Final_n_25 ,\genblk1.Final_n_26 ,\genblk1.Final_n_27 ,\genblk1.Final_n_28 ,\genblk1.Final_n_29 ,\genblk1.Final_n_30 ,\genblk1.Final_n_31 ,\genblk1.Final_n_32 ,\genblk1.Final_n_33 ,\genblk1.Final_n_34 ,\genblk1.Final_n_35 }),
.Data_A_i({\genblk1.left_n_24 ,\genblk1.left_n_25 ,\genblk1.left_n_26 ,\genblk1.left_n_27 ,\genblk1.left_n_28 ,\genblk1.left_n_29 ,\genblk1.left_n_30 ,\genblk1.left_n_31 ,\genblk1.left_n_32 ,\genblk1.left_n_33 ,\genblk1.left_n_10 ,\genblk1.left_n_11 ,\genblk1.left_n_12 ,\genblk1.left_n_13 ,\genblk1.left_n_14 ,\genblk1.left_n_15 ,\genblk1.left_n_16 ,\genblk1.left_n_17 ,\genblk1.left_n_18 ,\genblk1.left_n_19 ,\genblk1.left_n_20 ,\genblk1.left_n_21 ,\genblk1.left_n_22 ,\genblk1.left_n_23 ,\genblk1.right_n_0 ,\genblk1.right_n_1 ,\genblk1.right_n_2 ,\genblk1.right_n_3 ,\genblk1.right_n_4 ,\genblk1.right_n_5 ,\genblk1.right_n_6 ,\genblk1.right_n_7 ,\genblk1.right_n_8 ,\genblk1.right_n_9 ,\genblk1.right_n_10 ,\genblk1.right_n_11 ,\genblk1.right_n_24 }),
.P(Data_B_i));
substractor \genblk1.Subtr_1
(.B(B),
.P({\genblk1.left_n_0 ,\genblk1.left_n_1 ,\genblk1.left_n_2 ,\genblk1.left_n_3 ,\genblk1.left_n_4 ,\genblk1.left_n_5 ,\genblk1.left_n_6 ,\genblk1.left_n_7 ,\genblk1.left_n_8 ,\genblk1.left_n_9 ,\genblk1.left_n_10 ,\genblk1.left_n_11 ,\genblk1.left_n_12 ,\genblk1.left_n_13 ,\genblk1.left_n_14 ,\genblk1.left_n_15 ,\genblk1.left_n_16 ,\genblk1.left_n_17 ,\genblk1.left_n_18 ,\genblk1.left_n_19 ,\genblk1.left_n_20 ,\genblk1.left_n_21 ,\genblk1.left_n_22 ,\genblk1.left_n_23 }),
.PCOUT({\genblk1.Subtr_1_n_0 ,\genblk1.Subtr_1_n_1 ,\genblk1.Subtr_1_n_2 ,\genblk1.Subtr_1_n_3 ,\genblk1.Subtr_1_n_4 ,\genblk1.Subtr_1_n_5 ,\genblk1.Subtr_1_n_6 ,\genblk1.Subtr_1_n_7 ,\genblk1.Subtr_1_n_8 ,\genblk1.Subtr_1_n_9 ,\genblk1.Subtr_1_n_10 ,\genblk1.Subtr_1_n_11 ,\genblk1.Subtr_1_n_12 ,\genblk1.Subtr_1_n_13 ,\genblk1.Subtr_1_n_14 ,\genblk1.Subtr_1_n_15 ,\genblk1.Subtr_1_n_16 ,\genblk1.Subtr_1_n_17 ,\genblk1.Subtr_1_n_18 ,\genblk1.Subtr_1_n_19 ,\genblk1.Subtr_1_n_20 ,\genblk1.Subtr_1_n_21 ,\genblk1.Subtr_1_n_22 ,\genblk1.Subtr_1_n_23 ,\genblk1.Subtr_1_n_24 ,\genblk1.Subtr_1_n_25 ,\genblk1.Subtr_1_n_26 ,\genblk1.Subtr_1_n_27 ,\genblk1.Subtr_1_n_28 ,\genblk1.Subtr_1_n_29 ,\genblk1.Subtr_1_n_30 ,\genblk1.Subtr_1_n_31 ,\genblk1.Subtr_1_n_32 ,\genblk1.Subtr_1_n_33 ,\genblk1.Subtr_1_n_34 ,\genblk1.Subtr_1_n_35 ,\genblk1.Subtr_1_n_36 ,\genblk1.Subtr_1_n_37 ,\genblk1.Subtr_1_n_38 ,\genblk1.Subtr_1_n_39 ,\genblk1.Subtr_1_n_40 ,\genblk1.Subtr_1_n_41 ,\genblk1.Subtr_1_n_42 ,\genblk1.Subtr_1_n_43 ,\genblk1.Subtr_1_n_44 ,\genblk1.Subtr_1_n_45 ,\genblk1.Subtr_1_n_46 ,\genblk1.Subtr_1_n_47 }),
.\Q_reg[22] (\Q_reg[22] ),
.clk_IBUF_BUFG(clk_IBUF_BUFG));
substractor_2 \genblk1.Subtr_2
(.P(Data_B_i),
.PCOUT({\genblk1.Subtr_1_n_0 ,\genblk1.Subtr_1_n_1 ,\genblk1.Subtr_1_n_2 ,\genblk1.Subtr_1_n_3 ,\genblk1.Subtr_1_n_4 ,\genblk1.Subtr_1_n_5 ,\genblk1.Subtr_1_n_6 ,\genblk1.Subtr_1_n_7 ,\genblk1.Subtr_1_n_8 ,\genblk1.Subtr_1_n_9 ,\genblk1.Subtr_1_n_10 ,\genblk1.Subtr_1_n_11 ,\genblk1.Subtr_1_n_12 ,\genblk1.Subtr_1_n_13 ,\genblk1.Subtr_1_n_14 ,\genblk1.Subtr_1_n_15 ,\genblk1.Subtr_1_n_16 ,\genblk1.Subtr_1_n_17 ,\genblk1.Subtr_1_n_18 ,\genblk1.Subtr_1_n_19 ,\genblk1.Subtr_1_n_20 ,\genblk1.Subtr_1_n_21 ,\genblk1.Subtr_1_n_22 ,\genblk1.Subtr_1_n_23 ,\genblk1.Subtr_1_n_24 ,\genblk1.Subtr_1_n_25 ,\genblk1.Subtr_1_n_26 ,\genblk1.Subtr_1_n_27 ,\genblk1.Subtr_1_n_28 ,\genblk1.Subtr_1_n_29 ,\genblk1.Subtr_1_n_30 ,\genblk1.Subtr_1_n_31 ,\genblk1.Subtr_1_n_32 ,\genblk1.Subtr_1_n_33 ,\genblk1.Subtr_1_n_34 ,\genblk1.Subtr_1_n_35 ,\genblk1.Subtr_1_n_36 ,\genblk1.Subtr_1_n_37 ,\genblk1.Subtr_1_n_38 ,\genblk1.Subtr_1_n_39 ,\genblk1.Subtr_1_n_40 ,\genblk1.Subtr_1_n_41 ,\genblk1.Subtr_1_n_42 ,\genblk1.Subtr_1_n_43 ,\genblk1.Subtr_1_n_44 ,\genblk1.Subtr_1_n_45 ,\genblk1.Subtr_1_n_46 ,\genblk1.Subtr_1_n_47 }),
.pdt_int_reg({\genblk1.right_n_0 ,\genblk1.right_n_1 ,\genblk1.right_n_2 ,\genblk1.right_n_3 ,\genblk1.right_n_4 ,\genblk1.right_n_5 ,\genblk1.right_n_6 ,\genblk1.right_n_7 ,\genblk1.right_n_8 ,\genblk1.right_n_9 ,\genblk1.right_n_10 ,\genblk1.right_n_11 ,\genblk1.right_n_12 ,\genblk1.right_n_13 ,\genblk1.right_n_14 ,\genblk1.right_n_15 ,\genblk1.right_n_16 ,\genblk1.right_n_17 ,\genblk1.right_n_18 ,\genblk1.right_n_19 ,\genblk1.right_n_20 ,\genblk1.right_n_21 ,\genblk1.right_n_22 ,\genblk1.right_n_23 }));
RegisterAdd__parameterized1 \genblk1.finalreg
(.AR(AR),
.D({\genblk1.Final_n_0 ,\genblk1.Final_n_1 ,\genblk1.Final_n_2 ,\genblk1.Final_n_3 ,\genblk1.Final_n_4 ,\genblk1.Final_n_5 ,\genblk1.Final_n_6 ,\genblk1.Final_n_7 ,\genblk1.Final_n_8 ,\genblk1.Final_n_9 ,\genblk1.Final_n_10 ,\genblk1.Final_n_11 ,\genblk1.Final_n_12 ,\genblk1.Final_n_13 ,\genblk1.Final_n_14 ,\genblk1.Final_n_15 ,\genblk1.Final_n_16 ,\genblk1.Final_n_17 ,\genblk1.Final_n_18 ,\genblk1.Final_n_19 ,\genblk1.Final_n_20 ,\genblk1.Final_n_21 ,\genblk1.Final_n_22 ,\genblk1.Final_n_23 ,\genblk1.Final_n_24 ,\genblk1.Final_n_25 ,\genblk1.Final_n_26 ,\genblk1.Final_n_27 ,\genblk1.Final_n_28 ,\genblk1.Final_n_29 ,\genblk1.Final_n_30 ,\genblk1.Final_n_31 ,\genblk1.Final_n_32 ,\genblk1.Final_n_33 ,\genblk1.Final_n_34 ,\genblk1.Final_n_35 ,\genblk1.right_n_12 ,\genblk1.right_n_13 ,\genblk1.right_n_14 ,\genblk1.right_n_15 ,\genblk1.right_n_16 ,\genblk1.right_n_17 ,\genblk1.right_n_18 ,\genblk1.right_n_19 ,\genblk1.right_n_20 ,\genblk1.right_n_21 ,\genblk1.right_n_22 ,\genblk1.right_n_23 }),
.E(E),
.FSM_round_flag(FSM_round_flag),
.\Q_reg[0]_0 (\Q_reg[0] ),
.\Q_reg[31]_0 (\Q_reg[31] ),
.clk_IBUF_BUFG(clk_IBUF_BUFG));
multiplier \genblk1.left
(.Data_A_i({\genblk1.left_n_24 ,\genblk1.left_n_25 ,\genblk1.left_n_26 ,\genblk1.left_n_27 ,\genblk1.left_n_28 ,\genblk1.left_n_29 ,\genblk1.left_n_30 ,\genblk1.left_n_31 ,\genblk1.left_n_32 ,\genblk1.left_n_33 }),
.P({\genblk1.left_n_0 ,\genblk1.left_n_1 ,\genblk1.left_n_2 ,\genblk1.left_n_3 ,\genblk1.left_n_4 ,\genblk1.left_n_5 ,\genblk1.left_n_6 ,\genblk1.left_n_7 ,\genblk1.left_n_8 ,\genblk1.left_n_9 ,\genblk1.left_n_10 ,\genblk1.left_n_11 ,\genblk1.left_n_12 ,\genblk1.left_n_13 ,\genblk1.left_n_14 ,\genblk1.left_n_15 ,\genblk1.left_n_16 ,\genblk1.left_n_17 ,\genblk1.left_n_18 ,\genblk1.left_n_19 ,\genblk1.left_n_20 ,\genblk1.left_n_21 ,\genblk1.left_n_22 ,\genblk1.left_n_23 }),
.Q(Q[22:12]),
.\Q_reg[22] (\Q_reg[22] [22:12]),
.clk_IBUF_BUFG(clk_IBUF_BUFG));
multiplier_3 \genblk1.right
(.Data_A_i(\genblk1.right_n_24 ),
.Data_S_o0({\genblk1.right_n_0 ,\genblk1.right_n_1 ,\genblk1.right_n_2 ,\genblk1.right_n_3 ,\genblk1.right_n_4 ,\genblk1.right_n_5 ,\genblk1.right_n_6 ,\genblk1.right_n_7 ,\genblk1.right_n_8 ,\genblk1.right_n_9 ,\genblk1.right_n_10 ,\genblk1.right_n_11 ,\genblk1.right_n_12 ,\genblk1.right_n_13 ,\genblk1.right_n_14 ,\genblk1.right_n_15 ,\genblk1.right_n_16 ,\genblk1.right_n_17 ,\genblk1.right_n_18 ,\genblk1.right_n_19 ,\genblk1.right_n_20 ,\genblk1.right_n_21 ,\genblk1.right_n_22 ,\genblk1.right_n_23 }),
.Q(Q[11:0]),
.\Q_reg[11] (\Q_reg[22] [11:0]),
.clk_IBUF_BUFG(clk_IBUF_BUFG));
endmodule
module Tenth_Phase
(Q,
E,
D,
clk_IBUF_BUFG,
AR);
output [31:0]Q;
input [0:0]E;
input [31:0]D;
input clk_IBUF_BUFG;
input [0:0]AR;
wire [0:0]AR;
wire [31:0]D;
wire [0:0]E;
wire [31:0]Q;
wire clk_IBUF_BUFG;
RegisterAdd__parameterized3 Final_Result_IEEE
(.AR(AR),
.D(D),
.E(E),
.Q(Q),
.clk_IBUF_BUFG(clk_IBUF_BUFG));
endmodule
module Zero_InfMult_Unit
(zero_flag,
\FSM_sequential_state_reg_reg[0] ,
clk_IBUF_BUFG,
AR);
output zero_flag;
input \FSM_sequential_state_reg_reg[0] ;
input clk_IBUF_BUFG;
input [0:0]AR;
wire [0:0]AR;
wire \FSM_sequential_state_reg_reg[0] ;
wire clk_IBUF_BUFG;
wire zero_flag;
RegisterAdd_1 Zero_Info_Mult
(.AR(AR),
.\FSM_sequential_state_reg_reg[0] (\FSM_sequential_state_reg_reg[0] ),
.clk_IBUF_BUFG(clk_IBUF_BUFG),
.zero_flag(zero_flag));
endmodule
(* ORIG_REF_NAME = "adder" *)
module adder__parameterized0
(D,
Data_A_i,
P);
output [35:0]D;
input [36:0]Data_A_i;
input [25:0]P;
wire [35:0]D;
wire [36:0]Data_A_i;
wire [25:0]P;
wire \Q[14]_i_2_n_0 ;
wire \Q[14]_i_3_n_0 ;
wire \Q[14]_i_4_n_0 ;
wire \Q[18]_i_2_n_0 ;
wire \Q[18]_i_3_n_0 ;
wire \Q[18]_i_4_n_0 ;
wire \Q[18]_i_5_n_0 ;
wire \Q[22]_i_2_n_0 ;
wire \Q[22]_i_3_n_0 ;
wire \Q[22]_i_4_n_0 ;
wire \Q[22]_i_5_n_0 ;
wire \Q[26]_i_2_n_0 ;
wire \Q[26]_i_3_n_0 ;
wire \Q[26]_i_4_n_0 ;
wire \Q[26]_i_5_n_0 ;
wire \Q[30]_i_2_n_0 ;
wire \Q[30]_i_3_n_0 ;
wire \Q[30]_i_4_n_0 ;
wire \Q[30]_i_5_n_0 ;
wire \Q[34]_i_2_n_0 ;
wire \Q[34]_i_3_n_0 ;
wire \Q[34]_i_4_n_0 ;
wire \Q[34]_i_5_n_0 ;
wire \Q[38]_i_3_n_0 ;
wire \Q[38]_i_4_n_0 ;
wire \Q[38]_i_5_n_0 ;
wire \Q_reg[14]_i_1_n_0 ;
wire \Q_reg[18]_i_1_n_0 ;
wire \Q_reg[22]_i_1_n_0 ;
wire \Q_reg[26]_i_1_n_0 ;
wire \Q_reg[30]_i_1_n_0 ;
wire \Q_reg[34]_i_1_n_0 ;
wire \Q_reg[38]_i_1_n_0 ;
wire \Q_reg[42]_i_1_n_0 ;
wire \Q_reg[46]_i_1_n_0 ;
wire [2:0]\NLW_Q_reg[14]_i_1_CO_UNCONNECTED ;
wire [0:0]\NLW_Q_reg[14]_i_1_O_UNCONNECTED ;
wire [2:0]\NLW_Q_reg[18]_i_1_CO_UNCONNECTED ;
wire [2:0]\NLW_Q_reg[22]_i_1_CO_UNCONNECTED ;
wire [2:0]\NLW_Q_reg[26]_i_1_CO_UNCONNECTED ;
wire [2:0]\NLW_Q_reg[30]_i_1_CO_UNCONNECTED ;
wire [2:0]\NLW_Q_reg[34]_i_1_CO_UNCONNECTED ;
wire [2:0]\NLW_Q_reg[38]_i_1_CO_UNCONNECTED ;
wire [2:0]\NLW_Q_reg[42]_i_1_CO_UNCONNECTED ;
wire [2:0]\NLW_Q_reg[46]_i_1_CO_UNCONNECTED ;
wire [3:0]\NLW_Q_reg[47]_i_1_CO_UNCONNECTED ;
wire [3:1]\NLW_Q_reg[47]_i_1_O_UNCONNECTED ;
LUT2 #(
.INIT(4'h6))
\Q[14]_i_2
(.I0(Data_A_i[3]),
.I1(P[2]),
.O(\Q[14]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[14]_i_3
(.I0(Data_A_i[2]),
.I1(P[1]),
.O(\Q[14]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[14]_i_4
(.I0(Data_A_i[1]),
.I1(P[0]),
.O(\Q[14]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[18]_i_2
(.I0(Data_A_i[7]),
.I1(P[6]),
.O(\Q[18]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[18]_i_3
(.I0(Data_A_i[6]),
.I1(P[5]),
.O(\Q[18]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[18]_i_4
(.I0(Data_A_i[5]),
.I1(P[4]),
.O(\Q[18]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[18]_i_5
(.I0(Data_A_i[4]),
.I1(P[3]),
.O(\Q[18]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[22]_i_2
(.I0(Data_A_i[11]),
.I1(P[10]),
.O(\Q[22]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[22]_i_3
(.I0(Data_A_i[10]),
.I1(P[9]),
.O(\Q[22]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[22]_i_4
(.I0(Data_A_i[9]),
.I1(P[8]),
.O(\Q[22]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[22]_i_5
(.I0(Data_A_i[8]),
.I1(P[7]),
.O(\Q[22]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[26]_i_2
(.I0(Data_A_i[15]),
.I1(P[14]),
.O(\Q[26]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[26]_i_3
(.I0(Data_A_i[14]),
.I1(P[13]),
.O(\Q[26]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[26]_i_4
(.I0(Data_A_i[13]),
.I1(P[12]),
.O(\Q[26]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[26]_i_5
(.I0(Data_A_i[12]),
.I1(P[11]),
.O(\Q[26]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[30]_i_2
(.I0(Data_A_i[19]),
.I1(P[18]),
.O(\Q[30]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[30]_i_3
(.I0(Data_A_i[18]),
.I1(P[17]),
.O(\Q[30]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[30]_i_4
(.I0(Data_A_i[17]),
.I1(P[16]),
.O(\Q[30]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[30]_i_5
(.I0(Data_A_i[16]),
.I1(P[15]),
.O(\Q[30]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[34]_i_2
(.I0(Data_A_i[23]),
.I1(P[22]),
.O(\Q[34]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[34]_i_3
(.I0(Data_A_i[22]),
.I1(P[21]),
.O(\Q[34]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[34]_i_4
(.I0(Data_A_i[21]),
.I1(P[20]),
.O(\Q[34]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[34]_i_5
(.I0(Data_A_i[20]),
.I1(P[19]),
.O(\Q[34]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[38]_i_3
(.I0(Data_A_i[26]),
.I1(P[25]),
.O(\Q[38]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[38]_i_4
(.I0(Data_A_i[25]),
.I1(P[24]),
.O(\Q[38]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[38]_i_5
(.I0(Data_A_i[24]),
.I1(P[23]),
.O(\Q[38]_i_5_n_0 ));
CARRY4 \Q_reg[14]_i_1
(.CI(1'b0),
.CO({\Q_reg[14]_i_1_n_0 ,\NLW_Q_reg[14]_i_1_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({Data_A_i[3:1],1'b0}),
.O({D[2:0],\NLW_Q_reg[14]_i_1_O_UNCONNECTED [0]}),
.S({\Q[14]_i_2_n_0 ,\Q[14]_i_3_n_0 ,\Q[14]_i_4_n_0 ,Data_A_i[0]}));
CARRY4 \Q_reg[18]_i_1
(.CI(\Q_reg[14]_i_1_n_0 ),
.CO({\Q_reg[18]_i_1_n_0 ,\NLW_Q_reg[18]_i_1_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI(Data_A_i[7:4]),
.O(D[6:3]),
.S({\Q[18]_i_2_n_0 ,\Q[18]_i_3_n_0 ,\Q[18]_i_4_n_0 ,\Q[18]_i_5_n_0 }));
CARRY4 \Q_reg[22]_i_1
(.CI(\Q_reg[18]_i_1_n_0 ),
.CO({\Q_reg[22]_i_1_n_0 ,\NLW_Q_reg[22]_i_1_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI(Data_A_i[11:8]),
.O(D[10:7]),
.S({\Q[22]_i_2_n_0 ,\Q[22]_i_3_n_0 ,\Q[22]_i_4_n_0 ,\Q[22]_i_5_n_0 }));
CARRY4 \Q_reg[26]_i_1
(.CI(\Q_reg[22]_i_1_n_0 ),
.CO({\Q_reg[26]_i_1_n_0 ,\NLW_Q_reg[26]_i_1_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI(Data_A_i[15:12]),
.O(D[14:11]),
.S({\Q[26]_i_2_n_0 ,\Q[26]_i_3_n_0 ,\Q[26]_i_4_n_0 ,\Q[26]_i_5_n_0 }));
CARRY4 \Q_reg[30]_i_1
(.CI(\Q_reg[26]_i_1_n_0 ),
.CO({\Q_reg[30]_i_1_n_0 ,\NLW_Q_reg[30]_i_1_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI(Data_A_i[19:16]),
.O(D[18:15]),
.S({\Q[30]_i_2_n_0 ,\Q[30]_i_3_n_0 ,\Q[30]_i_4_n_0 ,\Q[30]_i_5_n_0 }));
CARRY4 \Q_reg[34]_i_1
(.CI(\Q_reg[30]_i_1_n_0 ),
.CO({\Q_reg[34]_i_1_n_0 ,\NLW_Q_reg[34]_i_1_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI(Data_A_i[23:20]),
.O(D[22:19]),
.S({\Q[34]_i_2_n_0 ,\Q[34]_i_3_n_0 ,\Q[34]_i_4_n_0 ,\Q[34]_i_5_n_0 }));
CARRY4 \Q_reg[38]_i_1
(.CI(\Q_reg[34]_i_1_n_0 ),
.CO({\Q_reg[38]_i_1_n_0 ,\NLW_Q_reg[38]_i_1_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,Data_A_i[26:24]}),
.O(D[26:23]),
.S({Data_A_i[27],\Q[38]_i_3_n_0 ,\Q[38]_i_4_n_0 ,\Q[38]_i_5_n_0 }));
CARRY4 \Q_reg[42]_i_1
(.CI(\Q_reg[38]_i_1_n_0 ),
.CO({\Q_reg[42]_i_1_n_0 ,\NLW_Q_reg[42]_i_1_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(D[30:27]),
.S(Data_A_i[31:28]));
CARRY4 \Q_reg[46]_i_1
(.CI(\Q_reg[42]_i_1_n_0 ),
.CO({\Q_reg[46]_i_1_n_0 ,\NLW_Q_reg[46]_i_1_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(D[34:31]),
.S(Data_A_i[35:32]));
CARRY4 \Q_reg[47]_i_1
(.CI(\Q_reg[46]_i_1_n_0 ),
.CO(\NLW_Q_reg[47]_i_1_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_Q_reg[47]_i_1_O_UNCONNECTED [3:1],D[35]}),
.S({1'b0,1'b0,1'b0,Data_A_i[36]}));
endmodule
module multiplier
(P,
Data_A_i,
clk_IBUF_BUFG,
Q,
\Q_reg[22] );
output [23:0]P;
output [9:0]Data_A_i;
input clk_IBUF_BUFG;
input [10:0]Q;
input [10:0]\Q_reg[22] ;
wire [23:0]P;
wire [10:0]Q;
wire [10:0]\Q_reg[22] ;
wire clk_IBUF_BUFG;
wire NLW_pdt_int_reg_CARRYCASCOUT_UNCONNECTED;
wire NLW_pdt_int_reg_MULTSIGNOUT_UNCONNECTED;
wire NLW_pdt_int_reg_OVERFLOW_UNCONNECTED;
wire NLW_pdt_int_reg_PATTERNBDETECT_UNCONNECTED;
wire NLW_pdt_int_reg_PATTERNDETECT_UNCONNECTED;
wire NLW_pdt_int_reg_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_pdt_int_reg_ACOUT_UNCONNECTED;
wire [17:0]NLW_pdt_int_reg_BCOUT_UNCONNECTED;
wire [3:0]NLW_pdt_int_reg_CARRYOUT_UNCONNECTED;
wire [47:24]NLW_pdt_int_reg_P_UNCONNECTED;
wire [47:0]NLW_pdt_int_reg_PCOUT_UNCONNECTED;
assign Data_A_i[9:0] = P[23:14];
(* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(1),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
pdt_int_reg
(.A({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,\Q_reg[22] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_pdt_int_reg_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,Q}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_pdt_int_reg_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_pdt_int_reg_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_pdt_int_reg_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b1),
.CEP(1'b0),
.CLK(clk_IBUF_BUFG),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_pdt_int_reg_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_pdt_int_reg_OVERFLOW_UNCONNECTED),
.P({NLW_pdt_int_reg_P_UNCONNECTED[47:24],P}),
.PATTERNBDETECT(NLW_pdt_int_reg_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_pdt_int_reg_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_pdt_int_reg_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_pdt_int_reg_UNDERFLOW_UNCONNECTED));
endmodule
(* ORIG_REF_NAME = "multiplier" *)
module multiplier_3
(Data_S_o0,
Data_A_i,
clk_IBUF_BUFG,
Q,
\Q_reg[11] );
output [23:0]Data_S_o0;
output [0:0]Data_A_i;
input clk_IBUF_BUFG;
input [11:0]Q;
input [11:0]\Q_reg[11] ;
wire [23:0]Data_S_o0;
wire [11:0]Q;
wire [11:0]\Q_reg[11] ;
wire clk_IBUF_BUFG;
wire NLW_pdt_int_reg_CARRYCASCOUT_UNCONNECTED;
wire NLW_pdt_int_reg_MULTSIGNOUT_UNCONNECTED;
wire NLW_pdt_int_reg_OVERFLOW_UNCONNECTED;
wire NLW_pdt_int_reg_PATTERNBDETECT_UNCONNECTED;
wire NLW_pdt_int_reg_PATTERNDETECT_UNCONNECTED;
wire NLW_pdt_int_reg_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_pdt_int_reg_ACOUT_UNCONNECTED;
wire [17:0]NLW_pdt_int_reg_BCOUT_UNCONNECTED;
wire [3:0]NLW_pdt_int_reg_CARRYOUT_UNCONNECTED;
wire [47:24]NLW_pdt_int_reg_P_UNCONNECTED;
wire [47:0]NLW_pdt_int_reg_PCOUT_UNCONNECTED;
assign Data_A_i[0] = Data_S_o0[11];
(* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(1),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
pdt_int_reg
(.A({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\Q_reg[11] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_pdt_int_reg_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,Q}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_pdt_int_reg_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_pdt_int_reg_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_pdt_int_reg_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b1),
.CEP(1'b0),
.CLK(clk_IBUF_BUFG),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_pdt_int_reg_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_pdt_int_reg_OVERFLOW_UNCONNECTED),
.P({NLW_pdt_int_reg_P_UNCONNECTED[47:24],Data_S_o0}),
.PATTERNBDETECT(NLW_pdt_int_reg_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_pdt_int_reg_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_pdt_int_reg_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_pdt_int_reg_UNDERFLOW_UNCONNECTED));
endmodule
module substractor
(PCOUT,
clk_IBUF_BUFG,
B,
\Q_reg[22] ,
P);
output [47:0]PCOUT;
input clk_IBUF_BUFG;
input [12:0]B;
input [22:0]\Q_reg[22] ;
input [23:0]P;
wire [12:0]B;
wire Data_S_o0_i_10_n_0;
wire Data_S_o0_i_11_n_0;
wire Data_S_o0_i_12_n_0;
wire Data_S_o0_i_13_n_0;
wire Data_S_o0_i_14_n_0;
wire Data_S_o0_i_15_n_0;
wire Data_S_o0_i_16_n_0;
wire Data_S_o0_i_17_n_0;
wire Data_S_o0_i_18_n_0;
wire Data_S_o0_i_19_n_0;
wire Data_S_o0_i_20_n_0;
wire Data_S_o0_i_21_n_0;
wire Data_S_o0_i_22_n_0;
wire Data_S_o0_i_23_n_0;
wire Data_S_o0_i_24_n_0;
wire Data_S_o0_i_25_n_0;
wire Data_S_o0_i_26_n_0;
wire Data_S_o0_i_27_n_0;
wire Data_S_o0_i_28_n_0;
wire Data_S_o0_i_5_n_0;
wire Data_S_o0_i_6_n_0;
wire Data_S_o0_i_7_n_0;
wire Data_S_o0_i_8_n_0;
wire Data_S_o0_i_9_n_0;
wire [23:0]P;
wire [47:0]PCOUT;
wire [22:0]\Q_reg[22] ;
wire clk_IBUF_BUFG;
wire NLW_Data_S_o0_CARRYCASCOUT_UNCONNECTED;
wire NLW_Data_S_o0_MULTSIGNOUT_UNCONNECTED;
wire NLW_Data_S_o0_OVERFLOW_UNCONNECTED;
wire NLW_Data_S_o0_PATTERNBDETECT_UNCONNECTED;
wire NLW_Data_S_o0_PATTERNDETECT_UNCONNECTED;
wire NLW_Data_S_o0_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_Data_S_o0_ACOUT_UNCONNECTED;
wire [17:0]NLW_Data_S_o0_BCOUT_UNCONNECTED;
wire [3:0]NLW_Data_S_o0_CARRYOUT_UNCONNECTED;
wire [47:0]NLW_Data_S_o0_P_UNCONNECTED;
(* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(0),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(0),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(1),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("TRUE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
Data_S_o0
(.A({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\Q_reg[22] [11:0]}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_Data_S_o0_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({1'b0,1'b0,1'b0,1'b0,1'b0,B}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_Data_S_o0_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,Data_S_o0_i_5_n_0,Data_S_o0_i_6_n_0,Data_S_o0_i_7_n_0,Data_S_o0_i_8_n_0,Data_S_o0_i_9_n_0,Data_S_o0_i_10_n_0,Data_S_o0_i_11_n_0,Data_S_o0_i_12_n_0,Data_S_o0_i_13_n_0,Data_S_o0_i_14_n_0,Data_S_o0_i_15_n_0,Data_S_o0_i_16_n_0,Data_S_o0_i_17_n_0,Data_S_o0_i_18_n_0,Data_S_o0_i_19_n_0,Data_S_o0_i_20_n_0,Data_S_o0_i_21_n_0,Data_S_o0_i_22_n_0,Data_S_o0_i_23_n_0,Data_S_o0_i_24_n_0,Data_S_o0_i_25_n_0,Data_S_o0_i_26_n_0,Data_S_o0_i_27_n_0,Data_S_o0_i_28_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_Data_S_o0_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b1),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_Data_S_o0_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b1),
.CEP(1'b0),
.CLK(clk_IBUF_BUFG),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,\Q_reg[22] [22:12]}),
.INMODE({1'b0,1'b0,1'b1,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_Data_S_o0_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_Data_S_o0_OVERFLOW_UNCONNECTED),
.P(NLW_Data_S_o0_P_UNCONNECTED[47:0]),
.PATTERNBDETECT(NLW_Data_S_o0_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_Data_S_o0_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(PCOUT),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_Data_S_o0_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
Data_S_o0_i_10
(.I0(P[18]),
.O(Data_S_o0_i_10_n_0));
LUT1 #(
.INIT(2'h1))
Data_S_o0_i_11
(.I0(P[17]),
.O(Data_S_o0_i_11_n_0));
LUT1 #(
.INIT(2'h1))
Data_S_o0_i_12
(.I0(P[16]),
.O(Data_S_o0_i_12_n_0));
LUT1 #(
.INIT(2'h1))
Data_S_o0_i_13
(.I0(P[15]),
.O(Data_S_o0_i_13_n_0));
LUT1 #(
.INIT(2'h1))
Data_S_o0_i_14
(.I0(P[14]),
.O(Data_S_o0_i_14_n_0));
LUT1 #(
.INIT(2'h1))
Data_S_o0_i_15
(.I0(P[13]),
.O(Data_S_o0_i_15_n_0));
LUT1 #(
.INIT(2'h1))
Data_S_o0_i_16
(.I0(P[12]),
.O(Data_S_o0_i_16_n_0));
LUT1 #(
.INIT(2'h1))
Data_S_o0_i_17
(.I0(P[11]),
.O(Data_S_o0_i_17_n_0));
LUT1 #(
.INIT(2'h1))
Data_S_o0_i_18
(.I0(P[10]),
.O(Data_S_o0_i_18_n_0));
LUT1 #(
.INIT(2'h1))
Data_S_o0_i_19
(.I0(P[9]),
.O(Data_S_o0_i_19_n_0));
LUT1 #(
.INIT(2'h1))
Data_S_o0_i_20
(.I0(P[8]),
.O(Data_S_o0_i_20_n_0));
LUT1 #(
.INIT(2'h1))
Data_S_o0_i_21
(.I0(P[7]),
.O(Data_S_o0_i_21_n_0));
LUT1 #(
.INIT(2'h1))
Data_S_o0_i_22
(.I0(P[6]),
.O(Data_S_o0_i_22_n_0));
LUT1 #(
.INIT(2'h1))
Data_S_o0_i_23
(.I0(P[5]),
.O(Data_S_o0_i_23_n_0));
LUT1 #(
.INIT(2'h1))
Data_S_o0_i_24
(.I0(P[4]),
.O(Data_S_o0_i_24_n_0));
LUT1 #(
.INIT(2'h1))
Data_S_o0_i_25
(.I0(P[3]),
.O(Data_S_o0_i_25_n_0));
LUT1 #(
.INIT(2'h1))
Data_S_o0_i_26
(.I0(P[2]),
.O(Data_S_o0_i_26_n_0));
LUT1 #(
.INIT(2'h1))
Data_S_o0_i_27
(.I0(P[1]),
.O(Data_S_o0_i_27_n_0));
LUT1 #(
.INIT(2'h1))
Data_S_o0_i_28
(.I0(P[0]),
.O(Data_S_o0_i_28_n_0));
LUT1 #(
.INIT(2'h1))
Data_S_o0_i_5
(.I0(P[23]),
.O(Data_S_o0_i_5_n_0));
LUT1 #(
.INIT(2'h1))
Data_S_o0_i_6
(.I0(P[22]),
.O(Data_S_o0_i_6_n_0));
LUT1 #(
.INIT(2'h1))
Data_S_o0_i_7
(.I0(P[21]),
.O(Data_S_o0_i_7_n_0));
LUT1 #(
.INIT(2'h1))
Data_S_o0_i_8
(.I0(P[20]),
.O(Data_S_o0_i_8_n_0));
LUT1 #(
.INIT(2'h1))
Data_S_o0_i_9
(.I0(P[19]),
.O(Data_S_o0_i_9_n_0));
endmodule
(* ORIG_REF_NAME = "substractor" *)
module substractor_2
(P,
pdt_int_reg,
PCOUT);
output [25:0]P;
input [23:0]pdt_int_reg;
input [47:0]PCOUT;
wire [25:0]P;
wire [47:0]PCOUT;
wire [23:0]pdt_int_reg;
wire NLW_Data_S_o0_CARRYCASCOUT_UNCONNECTED;
wire NLW_Data_S_o0_MULTSIGNOUT_UNCONNECTED;
wire NLW_Data_S_o0_OVERFLOW_UNCONNECTED;
wire NLW_Data_S_o0_PATTERNBDETECT_UNCONNECTED;
wire NLW_Data_S_o0_PATTERNDETECT_UNCONNECTED;
wire NLW_Data_S_o0_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_Data_S_o0_ACOUT_UNCONNECTED;
wire [17:0]NLW_Data_S_o0_BCOUT_UNCONNECTED;
wire [3:0]NLW_Data_S_o0_CARRYOUT_UNCONNECTED;
wire [47:26]NLW_Data_S_o0_P_UNCONNECTED;
wire [47:0]NLW_Data_S_o0_PCOUT_UNCONNECTED;
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("NONE"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
Data_S_o0
(.A({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,pdt_int_reg[23:18]}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_Data_S_o0_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b1,1'b1}),
.B(pdt_int_reg[17:0]),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_Data_S_o0_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_Data_S_o0_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_Data_S_o0_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_Data_S_o0_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b1,1'b0,1'b0,1'b1,1'b1}),
.OVERFLOW(NLW_Data_S_o0_OVERFLOW_UNCONNECTED),
.P({NLW_Data_S_o0_P_UNCONNECTED[47:26],P}),
.PATTERNBDETECT(NLW_Data_S_o0_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_Data_S_o0_PATTERNDETECT_UNCONNECTED),
.PCIN(PCOUT),
.PCOUT(NLW_Data_S_o0_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_Data_S_o0_UNDERFLOW_UNCONNECTED));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module peripheral_uart(clk , rst , d_in , cs , addr , rd , wr, d_out, uart_tx, ledout );
input clk;
input rst;
input [15:0]d_in;
input cs;
input [3:0]addr; // 4 LSB from j1_io_addr
input rd;
input wr;
output reg [15:0]d_out;
output uart_tx;
output reg ledout=0;
//------------------------------------ regs and wires-------------------------------
reg [2:0] s; //selector mux_4 and demux_4
reg [7:0] d_in_uart; // data in uart
wire uart_busy; // out_uart
//------------------------------------ regs and wires-------------------------------
always @(*) begin//----address_decoder------------------
case (addr)
4'h0:begin s = (cs && rd) ? 3'b001 : 3'b000 ;end //busy
4'h2:begin s = (cs && wr) ? 3'b010 : 3'b000 ;end //data
4'h4:begin s = (cs && wr) ? 3'b100 : 3'b000 ;end //ledout
default:begin s=3'b000 ; end
endcase
end//-----------------address_decoder--------------------
always @(negedge clk) begin//-------------------- escritura de registros
d_in_uart= (s[1]) ? d_in[7:0] : d_in_uart; // data in uart
ledout = (s[2]) ? d_in[0] : ledout; // write ledout register
end//------------------------------------------- escritura de registros
always @(negedge clk) begin//-----------------------mux_4 : multiplexa salidas del periferico
case (s)
3'b001: d_out[0]= uart_busy; // data out uart
default: d_out=0;
endcase
end//----------------------------------------------mux_4
//(addr != 4'h4): se hace para evitar escrituras fantasma
uart uart(.uart_busy(uart_busy), .uart_tx(uart_tx), .uart_wr_i(cs && wr && (addr != 4'h4) ), .uart_dat_i(d_in_uart), .sys_clk_i(clk), .sys_rst_i(rst));// System clock,
endmodule
|
//#############################################################################
//# Function: Isolation (Low) buffer for multi supply domains #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_pwr_isolo #(parameter DW = 1 // width of data inputs
)
(
input iso,// active low isolation signal
input [DW-1:0] in, // input signal
output [DW-1:0] out // out = ~iso & in
);
localparam ASIC = `CFG_ASIC; // use ASIC lib
generate
if(ASIC)
begin : asic
asic_iso_lo iiso [DW-1:0] (.iso(iso),
.in(in[DW-1:0]),
.out(out[DW-1:0]));
end
else
begin : gen
assign out[DW-1:0] = {(DW){~iso}} & in[DW-1:0];
end
endgenerate
endmodule // oh_buf
|
module stimulus (output reg A, B);
initial begin
{A, B} = 2'b00;
#10 {A, B} = 2'b01;
#10 {A, B} = 2'b10;
#10 {A, B} = 2'b11;
end
endmodule
module scoreboard (input Y, A, B);
function truth_table (input a, b);
reg [1:0] gate_operand;
reg gate_output;
begin
gate_operand[1:0] = {a, b};
case (gate_operand)
2'b00: gate_output = 1;
2'b01: gate_output = 0;
2'b10: gate_output = 0;
2'b11: gate_output = 1;
endcase
truth_table = gate_output;
end
endfunction
reg Y_t;
always @(A or B) begin
Y_t = truth_table (A, B);
#1;
//$display ("a = %b, b = %b, Y_s = %b, Y = %b", A, B, Y_s, Y);
if (Y_t !== Y) begin
$display("FAILED! - mismatch found for inputs %b and %b in XNOR operation", A, B);
$finish;
end
end
endmodule
module test;
stimulus stim (A, B);
xnor_gate duv (.a_i(A), .b_i(B), .c_o(Y) );
scoreboard mon (Y, A, B);
initial begin
#100;
$display("PASSED");
$finish;
end
endmodule
|
//======================================================================
//
// chacha.v
// --------
// Top level wrapper for the ChaCha stream, cipher core providing
// a simple memory like interface with 32 bit data access.
//
//
// Copyright (c) 2013 Secworks Sweden AB
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
`default_nettype none
module chacha(
input wire clk,
input wire reset_n,
input wire cs,
input wire we,
input wire [7 : 0] addr,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_NEXT_BIT = 1;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam ADDR_KEYLEN = 8'h0a;
localparam KEYLEN_BIT = 0;
localparam ADDR_ROUNDS = 8'h0b;
localparam ROUNDS_HIGH_BIT = 4;
localparam ROUNDS_LOW_BIT = 0;
localparam ADDR_KEY0 = 8'h10;
localparam ADDR_KEY7 = 8'h17;
localparam ADDR_IV0 = 8'h20;
localparam ADDR_IV1 = 8'h21;
localparam ADDR_DATA_IN0 = 8'h40;
localparam ADDR_DATA_IN15 = 8'h4f;
localparam ADDR_DATA_OUT0 = 8'h80;
localparam ADDR_DATA_OUT15 = 8'h8f;
localparam CORE_NAME0 = 32'h63686163; // "chac"
localparam CORE_NAME1 = 32'h68612020; // "ha "
localparam CORE_VERSION = 32'h302e3830; // "0.80"
localparam DEFAULT_CTR_INIT = 64'h0;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg init_reg;
reg init_new;
reg next_reg;
reg next_new;
reg keylen_reg;
reg keylen_we;
reg [4 : 0] rounds_reg;
reg rounds_we;
reg [31 : 0] key_reg [0 : 7];
reg key_we;
reg [31 : 0] iv_reg[0 : 1];
reg iv_we;
reg [31 : 0] data_in_reg [0 : 15];
reg data_in_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
wire [255 : 0] core_key;
wire [63 : 0] core_iv;
wire core_ready;
wire [511 : 0] core_data_in;
wire [511 : 0] core_data_out;
wire core_data_out_valid;
reg [31 : 0] tmp_read_data;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign core_key = {key_reg[0], key_reg[1], key_reg[2], key_reg[3],
key_reg[4], key_reg[5], key_reg[6], key_reg[7]};
assign core_iv = {iv_reg[0], iv_reg[1]};
assign core_data_in = {data_in_reg[00], data_in_reg[01], data_in_reg[02], data_in_reg[03],
data_in_reg[04], data_in_reg[05], data_in_reg[06], data_in_reg[07],
data_in_reg[08], data_in_reg[09], data_in_reg[10], data_in_reg[11],
data_in_reg[12], data_in_reg[13], data_in_reg[14], data_in_reg[15]};
assign read_data = tmp_read_data;
//----------------------------------------------------------------
// core instantiation.
//----------------------------------------------------------------
chacha_core core (
.clk(clk),
.reset_n(reset_n),
.init(init_reg),
.next(next_reg),
.key(core_key),
.keylen(keylen_reg),
.iv(core_iv),
.ctr(DEFAULT_CTR_INIT),
.rounds(rounds_reg),
.data_in(core_data_in),
.ready(core_ready),
.data_out(core_data_out),
.data_out_valid(core_data_out_valid)
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk)
begin : reg_update
integer i;
if (!reset_n)
begin
init_reg <= 0;
next_reg <= 0;
keylen_reg <= 0;
rounds_reg <= 5'h0;
iv_reg[0] <= 32'h0;
iv_reg[1] <= 32'h0;
for (i = 0 ; i < 8 ; i = i + 1)
key_reg[i] <= 32'h0;
for (i = 0 ; i < 16 ; i = i + 1)
data_in_reg[i] <= 32'h0;
end
else
begin
init_reg <= init_new;
next_reg <= next_new;
if (keylen_we)
keylen_reg <= write_data[KEYLEN_BIT];
if (rounds_we)
rounds_reg <= write_data[ROUNDS_HIGH_BIT : ROUNDS_LOW_BIT];
if (key_we)
key_reg[addr[2 : 0]] <= write_data;
if (iv_we)
iv_reg[addr[0]] <= write_data;
if (data_in_we)
data_in_reg[addr[3 : 0]] <= write_data;
end
end // reg_update
//----------------------------------------------------------------
// Address decoder logic.
//----------------------------------------------------------------
always @*
begin : addr_decoder
keylen_we = 1'h0;
rounds_we = 1'h0;
key_we = 1'h0;
iv_we = 1'h0;
data_in_we = 1'h0;
init_new = 1'h0;
next_new = 1'h0;
tmp_read_data = 32'h0;
if (cs)
begin
if (we)
begin
if (addr == ADDR_CTRL)
begin
init_new = write_data[CTRL_INIT_BIT];
next_new = write_data[CTRL_NEXT_BIT];
end
if (addr == ADDR_KEYLEN)
keylen_we = 1;
if (addr == ADDR_ROUNDS)
rounds_we = 1;
if ((addr >= ADDR_KEY0) && (addr <= ADDR_KEY7))
key_we = 1;
if ((addr >= ADDR_IV0) && (addr <= ADDR_IV1))
iv_we = 1;
if ((addr >= ADDR_DATA_IN0) && (addr <= ADDR_DATA_IN15))
data_in_we = 1;
end // if (we)
else
begin
if ((addr >= ADDR_KEY0) && (addr <= ADDR_KEY7))
tmp_read_data = key_reg[addr[2 : 0]];
if ((addr >= ADDR_DATA_OUT0) && (addr <= ADDR_DATA_OUT15))
tmp_read_data = core_data_out[(15 - (addr - ADDR_DATA_OUT0)) * 32 +: 32];
case (addr)
ADDR_NAME0: tmp_read_data = CORE_NAME0;
ADDR_NAME1: tmp_read_data = CORE_NAME1;
ADDR_VERSION: tmp_read_data = CORE_VERSION;
ADDR_CTRL: tmp_read_data = {30'h0, next_reg, init_reg};
ADDR_STATUS: tmp_read_data = {30'h0, core_data_out_valid, core_ready};
ADDR_KEYLEN: tmp_read_data = {31'h0, keylen_reg};
ADDR_ROUNDS: tmp_read_data = {27'h0, rounds_reg};
ADDR_IV0: tmp_read_data = iv_reg[0];
ADDR_IV1: tmp_read_data = iv_reg[1];
default:
begin
end
endcase // case (address)
end
end
end // addr_decoder
endmodule // chacha
//======================================================================
// EOF chacha.v
//======================================================================
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
// A quick define to help index 32-bit words inside a larger register.
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
// Perform a SHA-256 transformation on the given 512-bit data, and 256-bit
// initial state,
// Outputs one 256-bit hash every LOOP cycle(s).
//
// The LOOP parameter determines both the size and speed of this module.
// A value of 1 implies a fully unrolled SHA-256 calculation spanning 64 round
// modules and calculating a full SHA-256 hash every clock cycle. A value of
// 2 implies a half-unrolled loop, with 32 round modules and calculating
// a full hash in 2 clock cycles. And so forth.
module sha256_transform #(
parameter LOOP = 6'd4
) (
input clk,
input feedback,
input [5:0] cnt,
input [255:0] rx_state,
input [511:0] rx_input,
output reg [255:0] tx_hash
);
// Constants defined by the SHA-2 standard.
localparam Ks = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
32'h72be5d74, 32'h80deb1fe, 32'h9bdc06a7, 32'hc19bf174,
32'he49b69c1, 32'hefbe4786, 32'h0fc19dc6, 32'h240ca1cc,
32'h2de92c6f, 32'h4a7484aa, 32'h5cb0a9dc, 32'h76f988da,
32'h983e5152, 32'ha831c66d, 32'hb00327c8, 32'hbf597fc7,
32'hc6e00bf3, 32'hd5a79147, 32'h06ca6351, 32'h14292967,
32'h27b70a85, 32'h2e1b2138, 32'h4d2c6dfc, 32'h53380d13,
32'h650a7354, 32'h766a0abb, 32'h81c2c92e, 32'h92722c85,
32'ha2bfe8a1, 32'ha81a664b, 32'hc24b8b70, 32'hc76c51a3,
32'hd192e819, 32'hd6990624, 32'hf40e3585, 32'h106aa070,
32'h19a4c116, 32'h1e376c08, 32'h2748774c, 32'h34b0bcb5,
32'h391c0cb3, 32'h4ed8aa4a, 32'h5b9cca4f, 32'h682e6ff3,
32'h748f82ee, 32'h78a5636f, 32'h84c87814, 32'h8cc70208,
32'h90befffa, 32'ha4506ceb, 32'hbef9a3f7, 32'hc67178f2};
genvar i;
generate
for (i = 0; i < 64/LOOP; i = i + 1) begin : HASHERS
wire [511:0] W;
wire [255:0] state;
if(i == 0)
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-cnt) +: 32]),
.rx_w(feedback ? W : rx_input),
.rx_state(feedback ? state : rx_state),
.tx_w(W),
.tx_state(state)
);
else
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-LOOP*i-cnt) +: 32]),
.rx_w(feedback ? W : HASHERS[i-1].W),
.rx_state(feedback ? state : HASHERS[i-1].state),
.tx_w(W),
.tx_state(state)
);
end
endgenerate
always @ (posedge clk)
begin
if (!feedback)
begin
tx_hash[`IDX(0)] <= rx_state[`IDX(0)] + HASHERS[64/LOOP-6'd1].state[`IDX(0)];
tx_hash[`IDX(1)] <= rx_state[`IDX(1)] + HASHERS[64/LOOP-6'd1].state[`IDX(1)];
tx_hash[`IDX(2)] <= rx_state[`IDX(2)] + HASHERS[64/LOOP-6'd1].state[`IDX(2)];
tx_hash[`IDX(3)] <= rx_state[`IDX(3)] + HASHERS[64/LOOP-6'd1].state[`IDX(3)];
tx_hash[`IDX(4)] <= rx_state[`IDX(4)] + HASHERS[64/LOOP-6'd1].state[`IDX(4)];
tx_hash[`IDX(5)] <= rx_state[`IDX(5)] + HASHERS[64/LOOP-6'd1].state[`IDX(5)];
tx_hash[`IDX(6)] <= rx_state[`IDX(6)] + HASHERS[64/LOOP-6'd1].state[`IDX(6)];
tx_hash[`IDX(7)] <= rx_state[`IDX(7)] + HASHERS[64/LOOP-6'd1].state[`IDX(7)];
end
end
endmodule
module sha256_digester (clk, k, rx_w, rx_state, tx_w, tx_state);
input clk;
input [31:0] k;
input [511:0] rx_w;
input [255:0] rx_state;
output reg [511:0] tx_w;
output reg [255:0] tx_state;
wire [31:0] e0_w, e1_w, ch_w, maj_w, s0_w, s1_w;
e0 e0_blk (rx_state[`IDX(0)], e0_w);
e1 e1_blk (rx_state[`IDX(4)], e1_w);
ch ch_blk (rx_state[`IDX(4)], rx_state[`IDX(5)], rx_state[`IDX(6)], ch_w);
maj maj_blk (rx_state[`IDX(0)], rx_state[`IDX(1)], rx_state[`IDX(2)], maj_w);
s0 s0_blk (rx_w[63:32], s0_w);
s1 s1_blk (rx_w[479:448], s1_w);
wire [31:0] t1 = rx_state[`IDX(7)] + e1_w + ch_w + rx_w[31:0] + k;
wire [31:0] t2 = e0_w + maj_w;
wire [31:0] new_w = s1_w + rx_w[319:288] + s0_w + rx_w[31:0];
always @ (posedge clk)
begin
tx_w[511:480] <= new_w;
tx_w[479:0] <= rx_w[511:32];
tx_state[`IDX(7)] <= rx_state[`IDX(6)];
tx_state[`IDX(6)] <= rx_state[`IDX(5)];
tx_state[`IDX(5)] <= rx_state[`IDX(4)];
tx_state[`IDX(4)] <= rx_state[`IDX(3)] + t1;
tx_state[`IDX(3)] <= rx_state[`IDX(2)];
tx_state[`IDX(2)] <= rx_state[`IDX(1)];
tx_state[`IDX(1)] <= rx_state[`IDX(0)];
tx_state[`IDX(0)] <= t1 + t2;
end
endmodule
|
module bw_clk_cl_fpu_cmp ( so, dbginit_l, cluster_grst_l, rclk, si, se,
adbginit_l, gdbginit_l, arst_l, grst_l, cluster_cken, gclk );
input si, se, adbginit_l, gdbginit_l, arst_l, grst_l, cluster_cken, gclk;
output so, dbginit_l, cluster_grst_l, rclk;
wire \I0/sync_cluster_master/N3 , \I0/sync_cluster_slave/so_l ,
\I0/rst_repeater/pre_sync_out , \I0/dbginit_repeater/pre_sync_out ,
\I0/rst_repeater/repeater/i0/N10 , \I0/rst_repeater/syncff/i0/N10 ,
\I0/dbginit_repeater/repeater/i0/N10 ,
\I0/dbginit_repeater/syncff/i0/N10 , n10, n11, n12, n13, n14, n15,
n16;
assign \I0/sync_cluster_master/N3 = cluster_cken;
DFFX1 \I0/sync_cluster_master/q_r_reg ( .D(\I0/sync_cluster_master/N3 ),
.CLK(gclk), .QN(n11) );
LATCHX1 \I0/sync_cluster_slave/so_l_reg ( .CLK(n10), .D(n11), .Q(
\I0/sync_cluster_slave/so_l ) );
DFFARX1 \I0/rst_repeater/repeater/i0/q_reg ( .D(
\I0/rst_repeater/repeater/i0/N10 ), .CLK(gclk), .RSTB(arst_l), .Q(
\I0/rst_repeater/pre_sync_out ) );
LATCHX1 \I0/rst_repeater/lockup/so_l_reg ( .CLK(n10), .D(n15), .QN(n12) );
DFFARX1 \I0/rst_repeater/syncff/i0/q_reg ( .D(
\I0/rst_repeater/syncff/i0/N10 ), .CLK(rclk), .RSTB(arst_l), .Q(
cluster_grst_l) );
DFFARX1 \I0/dbginit_repeater/repeater/i0/q_reg ( .D(
\I0/dbginit_repeater/repeater/i0/N10 ), .CLK(gclk), .RSTB(adbginit_l),
.Q(\I0/dbginit_repeater/pre_sync_out ) );
LATCHX1 \I0/dbginit_repeater/lockup/so_l_reg ( .CLK(n10), .D(n14), .QN(n13)
);
DFFARX1 \I0/dbginit_repeater/syncff/i0/q_reg ( .D(
\I0/dbginit_repeater/syncff/i0/N10 ), .CLK(rclk), .RSTB(adbginit_l),
.Q(dbginit_l) );
INVX0 U11 ( .INP(se), .ZN(n16) );
OA221X1 U12 ( .IN1(se), .IN2(gdbginit_l), .IN3(n16), .IN4(cluster_grst_l),
.IN5(adbginit_l), .Q(\I0/dbginit_repeater/repeater/i0/N10 ) );
OA221X1 U13 ( .IN1(se), .IN2(\I0/dbginit_repeater/pre_sync_out ), .IN3(n16),
.IN4(n13), .IN5(adbginit_l), .Q(\I0/dbginit_repeater/syncff/i0/N10 )
);
OA221X1 U14 ( .IN1(se), .IN2(grst_l), .IN3(n16), .IN4(si), .IN5(arst_l), .Q(
\I0/rst_repeater/repeater/i0/N10 ) );
OA221X1 U15 ( .IN1(se), .IN2(\I0/rst_repeater/pre_sync_out ), .IN3(n16),
.IN4(n12), .IN5(arst_l), .Q(\I0/rst_repeater/syncff/i0/N10 ) );
NOR2X0 U16 ( .IN1(\I0/rst_repeater/pre_sync_out ), .IN2(n16), .QN(n15) );
NOR2X0 U17 ( .IN1(\I0/dbginit_repeater/pre_sync_out ), .IN2(n16), .QN(n14)
);
INVX0 U18 ( .INP(gclk), .ZN(n10) );
NOR2X0 U19 ( .IN1(\I0/sync_cluster_slave/so_l ), .IN2(n10), .QN(rclk) );
OR2X1 U20 ( .IN1(dbginit_l), .IN2(n16), .Q(so) );
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [255:0] sum;
// Take CRC data and apply to testblock inputs
wire [127:0] in = {~crc[63:0], crc[63:0]};
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [127:0] o1; // From test of Test.v
wire [127:0] o2; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.o1 (o1[127:0]),
.o2 (o2[127:0]),
// Inputs
.in (in[127:0]));
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x %x\n", $time, cyc, crc, o1, o2);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= {o1,o2} ^ {sum[254:0],sum[255]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc<10) begin
sum <= '0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 256'h008a080aaa000000140550404115dc7b008a080aaae7c8cd897bc1ca49c9350a
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
o1, o2,
// Inputs
in
);
input [127:0] in;
output logic [127:0] o1;
output logic [127:0] o2;
always_comb begin: b_test
logic [127:0] tmpp;
logic [127:0] tmp;
tmp = '0;
tmpp = '0;
tmp[63:0] = in[63:0];
tmpp[63:0] = in[63:0];
tmpp[63:0] = {tmp[0+:32], tmp[32+:32]};
tmp[63:0] = {tmp[0+:32], tmp[32+:32]};
o1 = tmp;
o2 = tmpp;
end
endmodule
|
`timescale 1ns/1ns
`include "aluop_def.v"
module ShiftRight(
input signed [31:0] inp,
input [4:0] shamt,
input isSrl,
output [31:0] out
);
assign out = (isSrl)? $signed(inp>>shamt):
(inp>>>shamt);
endmodule
module alu (a,b,op,c,over);
input [31:0] a,b;
input [3:0] op;
output [31:0] c;
output over;
wire [31:0] tmp,slt_result;
wire [31:0] sr_result;
wire [32:0] sltu_result;
ShiftRight sr(b,a[4:0],op==`ALU_SRL,sr_result);
assign tmp=((op==`ALU_SUB)?~b+1:b);
assign slt_result=a-b;
assign sltu_result={1'b0,a}-{1'b0,b};
assign c=(op==`ALU_ADD)?a+b:
(op==`ALU_SUB)?a-b:
(op==`ALU_OR)?a|b:
(op==`ALU_AND)?a & b:
(op==`ALU_XOR)?a ^ b:
(op==`ALU_NOR)?~(a|b):
(op==`ALU_SLL)?b<<a[4:0]:
(op==`ALU_SRL||op==`ALU_SRA)?sr_result:
(op==`ALU_SLT)?{31'd0,slt_result[31]}:
(op==`ALU_SLTU)?{31'd0,sltu_result[32]}:
32'hBBAACCDD;//for debug
assign over=((op==`ALU_ADD || op==`ALU_SUB) &&
a[31]==tmp[31] && tmp[31]==~c[31]);
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.2 (win64) Build 932637 Wed Jun 11 13:33:10 MDT 2014
// Date : Fri Sep 26 21:45:04 2014
// Host : ECE-411-6 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// C:/Users/coltmw/Documents/GitHub/ecen4024-microphone-array/microphone-array/microphone-array.srcs/sources_1/ip/cascaded_integrator_comb/cascaded_integrator_comb_stub.v
// Design : cascaded_integrator_comb
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "cic_compiler_v4_0,Vivado 2014.2" *)
module cascaded_integrator_comb(aclk, s_axis_data_tdata, s_axis_data_tvalid, s_axis_data_tready, m_axis_data_tdata, m_axis_data_tvalid)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tdata[7:0],s_axis_data_tvalid,s_axis_data_tready,m_axis_data_tdata[23:0],m_axis_data_tvalid" */;
input aclk;
input [7:0]s_axis_data_tdata;
input s_axis_data_tvalid;
output s_axis_data_tready;
output [23:0]m_axis_data_tdata;
output m_axis_data_tvalid;
endmodule
|
// megafunction wizard: %ALTDDIO_OUT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altddio_out
// ============================================================
// File Name: ddio_out_1.v
// Megafunction Name(s):
// altddio_out
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 222 10/21/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ddio_out_1 (
aclr,
datain_h,
datain_l,
outclock,
dataout);
input aclr;
input datain_h;
input datain_l;
input outclock;
output dataout;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire dataout = sub_wire1;
wire sub_wire2 = datain_h;
wire sub_wire3 = sub_wire2;
wire sub_wire4 = datain_l;
wire sub_wire5 = sub_wire4;
altddio_out altddio_out_component (
.outclock (outclock),
.datain_h (sub_wire3),
.aclr (aclr),
.datain_l (sub_wire5),
.dataout (sub_wire0),
.aset (1'b0),
.oe (1'b1),
.oe_out (),
.outclocken (1'b1),
.sclr (1'b0),
.sset (1'b0));
defparam
altddio_out_component.extend_oe_disable = "UNUSED",
altddio_out_component.intended_device_family = "Arria II GX",
altddio_out_component.lpm_type = "altddio_out",
altddio_out_component.oe_reg = "UNUSED",
altddio_out_component.width = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: OE NUMERIC "0"
// Retrieval info: PRIVATE: OE_REG NUMERIC "0"
// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
// Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
// Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
// Retrieval info: CONSTANT: WIDTH NUMERIC "1"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: datain_h 0 0 0 0 INPUT NODEFVAL datain_h
// Retrieval info: USED_PORT: datain_l 0 0 0 0 INPUT NODEFVAL datain_l
// Retrieval info: USED_PORT: dataout 0 0 0 0 OUTPUT NODEFVAL dataout
// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
// Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 0 0
// Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 0 0
// Retrieval info: CONNECT: dataout 0 0 0 0 @dataout 0 0 1 0
// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out_1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out_1.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out_1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out_1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out_1.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out_1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out_1_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
//-----------------------------------------------------------------------------
// processing_system7
// processor sub system wrapper
//-----------------------------------------------------------------------------
//
// ************************************************************************
// ** DISCLAIMER OF LIABILITY **
// ** **
// ** This file contains proprietary and confidential information of **
// ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
// ** from Xilinx, and may be used, copied and/or diSCLosed only **
// ** pursuant to the terms of a valid license agreement with Xilinx. **
// ** **
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
// ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
// ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
// ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
// ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
// ** does not warrant that functions included in the Materials will **
// ** meet the requirements of Licensee, or that the operation of the **
// ** Materials will be uninterrupted or error-free, or that defects **
// ** in the Materials will be corrected. Furthermore, Xilinx does **
// ** not warrant or make any representations regarding use, or the **
// ** results of the use, of the Materials in terms of correctness, **
// ** accuracy, reliability or otherwise. **
// ** **
// ** Xilinx products are not designed or intended to be fail-safe, **
// ** or for use in any application requiring fail-safe performance, **
// ** such as life-support or safety devices or systems, Class III **
// ** medical devices, nuclear facilities, applications related to **
// ** the deployment of airbags, or any other applications that could **
// ** lead to death, personal injury or severe property or **
// ** environmental damage (individually and collectively, "critical **
// ** applications"). Customer assumes the sole risk and liability **
// ** of any use of Xilinx products in critical applications, **
// ** subject only to applicable laws and regulations governing **
// ** limitations on product liability. **
// ** **
// ** Copyright 2010 Xilinx, Inc. **
// ** All rights reserved. **
// ** **
// ** This disclaimer and copyright notice must be retained as part **
// ** of this file at all times. **
// ************************************************************************
//
//-----------------------------------------------------------------------------
// Filename: processing_system7_v5_5_processing_system7.v
// Version: v1.00.a
// Description: This is the wrapper file for PSS.
//-----------------------------------------------------------------------------
// Structure: This section shows the hierarchical structure of
// pss_wrapper.
//
// --processing_system7_v5_5_processing_system7.v
// --PS7.v - Unisim component
//-----------------------------------------------------------------------------
// Author: SD
//
// History:
//
// SD 09/20/11 -- First version
// ~~~~~~
// Created the first version v2.00.a
// ^^^^^^
//------------------------------------------------------------------------------
// ^^^^^^
// SR 11/25/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// 1. Changed all clock, reset and clktrig ports to be individual
// signals instead of vectors. This is required for modeling of tools.
// 2. Interrupts are now defined as individual signals as well.
// 3. Added Clk buffer logic for FCLK_CLK
// 4. Includes the ACP related changes done
//
// TODO:
// 1. C_NUM_F2P_INTR_INPUTS needs to have control on the
// number of interrupt ports connected for IRQ_F2P.
//
//------------------------------------------------------------------------------
// ^^^^^^
// KP 12/07/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_NUM_F2P_INTR_INPUTS taken into account for IRQ_F2P
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/09/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_FCLK_CLK0_BUF to C_FCLK_CLK3_BUF parameters were updated
// to STRING and fix for CR 640523
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/13/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// Updated IRQ_F2P logic to address CR 641523.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/01/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Updated SDIO logic to address CR 636210.
// |
// Added C_PS7_SI_REV parameter to track SI Rev
// Removed compress/decompress logic to address CR 642527.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/27/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// TTC(0,1)_WAVE_OUT and TTC(0,1)_CLK_IN vector signals are made as individual
// ports as fix for CR 646379
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/05/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Added/updated compress/decompress logic to address 648393
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/14/12 -- v4.00.a version
// ~~~~~~~
// Unused parameters deleted CR 651120
// Addressed CR 651751
//------------------------------------------------------------------------------
// ^^^^^^
// NR 04/17/12 -- v4.01.a version
// ~~~~~~~
// Added FTM trace buffer functionality
// Added support for ACP AxUSER ports local update
//------------------------------------------------------------------------------
// ^^^^^^
// VR 05/18/12 -- v4.01.a version
// ~~~~~~~
// Fixed CR#659157
//------------------------------------------------------------------------------
// ^^^^^^
// VR 07/25/12 -- v4.01.a version
// ~~~~~~~
// Changed S_AXI_HP{1,2}_WACOUNT port's width to 6 from 8 to match unisim model
// Changed fclk_clktrig_gnd width to 4 from 16 to match unisim model
//------------------------------------------------------------------------------
// ^^^^^^
// VR 11/06/12 -- v5.00 version
// ~~~~~~~
// CR #682573
// Added BIBUF to fixed IO ports and IBUF to fixed input ports
//------------------------------------------------------------------------------
(*POWER= "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={S_AXI_HP1} dataWidth={64} clockFreq={150} usageRate={0.5} /><AXI interface={S_AXI_HP0} dataWidth={64} clockFreq={150} usageRate={0.5} /><AXI interface={S_AXI_ACP} dataWidth={32} clockFreq={150} usageRate={0.5} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={150} usageRate={0.5} />/>" *)
(* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=533.333313, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=14, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=49.5, PCW_UIPARAM_DDR_T_RAS_MIN=36.0, PCW_UIPARAM_DDR_T_FAW=45.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=0.025, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=0.028, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=-0.009, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=-0.061, PCW_UIPARAM_DDR_BOARD_DELAY0=0.41, PCW_UIPARAM_DDR_BOARD_DELAY1=0.411, PCW_UIPARAM_DDR_BOARD_DELAY2=0.341, PCW_UIPARAM_DDR_BOARD_DELAY3=0.358, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=68.4725, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=71.086, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=66.794, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=108.7385, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=64.1705, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=63.686, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=68.46, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=105.4895, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=33.333333, PCW_APU_PERIPHERAL_FREQMHZ=666.666667, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=50, PCW_UART_PERIPHERAL_FREQMHZ=50, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100.000000, PCW_FPGA1_PERIPHERAL_FREQMHZ=150.000000, PCW_FPGA2_PERIPHERAL_FREQMHZ=50, PCW_FPGA3_PERIPHERAL_FREQMHZ=50, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=40, PCW_IOPLL_CTRL_FBDIV=30, PCW_DDRPLL_CTRL_FBDIV=32, PCW_CPU_CPU_PLL_FREQMHZ=1333.333, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1066.667, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=1, PCW_USE_S_AXI_HP0=1, PCW_USE_S_AXI_HP1=1, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=150, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=150, PCW_S_AXI_HP0_FREQMHZ=150, PCW_S_AXI_HP1_FREQMHZ=150, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_FTM_CTI_IN0=DISABLED, PCW_FTM_CTI_IN1=DISABLED, PCW_FTM_CTI_IN2=DISABLED, PCW_FTM_CTI_IN3=DISABLED, PCW_FTM_CTI_OUT0=DISABLED, PCW_FTM_CTI_OUT1=DISABLED, PCW_FTM_CTI_OUT2=DISABLED, PCW_FTM_CTI_OUT3=DISABLED, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=64, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3, PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41J128M16 HA-15E, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=2048 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=1, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=0, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=1, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=1, PCW_SD0_SD0_IO=MIO 40 .. 45, PCW_SD0_GRP_CD_ENABLE=1, PCW_SD0_GRP_CD_IO=MIO 47, PCW_SD0_GRP_WP_ENABLE=1, PCW_SD0_GRP_WP_IO=MIO 46, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=0, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=0, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 48 .. 49, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=1, PCW_TTC0_TTC0_IO=EMIO, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=0, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=0, PCW_I2C0_GRP_INT_ENABLE=0, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=0, PCW_GPIO_MIO_GPIO_ENABLE=1, PCW_GPIO_MIO_GPIO_IO=MIO, PCW_GPIO_EMIO_GPIO_ENABLE=0, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=0, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=0, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=2, PCW_NOR_SRAM_CS0_T_RC=2, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=2, PCW_NOR_SRAM_CS1_T_RC=2, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=2, PCW_NOR_CS0_T_RC=2, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=2, PCW_NOR_CS1_T_RC=2, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=2, PCW_NAND_CYCLES_T_RC=2 }" *)
//(* HW_HANDOFF = "design_1_processing_system7_0_3.hwdef" *)
module processing_system7_v5_5_processing_system7
#(
parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1,
parameter integer C_S_AXI_ACP_ARUSER_VAL = 31,
parameter integer C_S_AXI_ACP_AWUSER_VAL = 31,
parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP0_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_ID_WIDTH = 12,
parameter integer C_S_AXI_GP0_ID_WIDTH = 6,
parameter integer C_S_AXI_GP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP0_ID_WIDTH = 6,
parameter integer C_S_AXI_HP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP2_ID_WIDTH = 6,
parameter integer C_S_AXI_HP3_ID_WIDTH = 6,
parameter integer C_S_AXI_ACP_ID_WIDTH = 3,
parameter integer C_S_AXI_HP0_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP1_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP2_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP3_DATA_WIDTH = 64,
parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0,
parameter integer C_NUM_F2P_INTR_INPUTS = 1,
parameter C_FCLK_CLK0_BUF = "TRUE",
parameter C_FCLK_CLK1_BUF = "TRUE",
parameter C_FCLK_CLK2_BUF = "TRUE",
parameter C_FCLK_CLK3_BUF = "TRUE",
parameter integer C_EMIO_GPIO_WIDTH = 64,
parameter integer C_INCLUDE_TRACE_BUFFER = 0,
parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128,
parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter integer C_TRACE_PIPELINE_WIDTH = 8,
parameter C_PS7_SI_REV = "PRODUCTION",
parameter integer C_EN_EMIO_ENET0 = 0,
parameter integer C_EN_EMIO_ENET1 = 0,
parameter integer C_EN_EMIO_TRACE = 0,
parameter integer C_DQ_WIDTH = 32,
parameter integer C_DQS_WIDTH = 4,
parameter integer C_DM_WIDTH = 4,
parameter integer C_MIO_PRIMITIVE = 54,
parameter C_PACKAGE_NAME = "clg484",
parameter C_IRQ_F2P_MODE = "DIRECT",
parameter C_TRACE_INTERNAL_WIDTH = 32,
parameter integer C_EN_EMIO_PJTAG = 0,
// Enable and disable AFI Secure transaction
parameter C_USE_AXI_NONSECURE = 0,
//parameters for HP enable ports
parameter C_USE_S_AXI_HP0 = 0,
parameter C_USE_S_AXI_HP1 = 0,
parameter C_USE_S_AXI_HP2 = 0,
parameter C_USE_S_AXI_HP3 = 0,
//parameters for GP and ACP enable ports */
parameter C_USE_M_AXI_GP0 = 0,
parameter C_USE_M_AXI_GP1 = 0,
parameter C_USE_S_AXI_GP0 = 0,
parameter C_USE_S_AXI_GP1 = 0,
parameter C_USE_S_AXI_ACP = 0
)
(
//FMIO =========================================
//FMIO CAN0
output CAN0_PHY_TX,
input CAN0_PHY_RX,
//FMIO CAN1
output CAN1_PHY_TX,
input CAN1_PHY_RX,
//FMIO ENET0
output reg ENET0_GMII_TX_EN,
output reg ENET0_GMII_TX_ER,
output ENET0_MDIO_MDC,
output ENET0_MDIO_O,
output ENET0_MDIO_T,
output ENET0_PTP_DELAY_REQ_RX,
output ENET0_PTP_DELAY_REQ_TX,
output ENET0_PTP_PDELAY_REQ_RX,
output ENET0_PTP_PDELAY_REQ_TX,
output ENET0_PTP_PDELAY_RESP_RX,
output ENET0_PTP_PDELAY_RESP_TX,
output ENET0_PTP_SYNC_FRAME_RX,
output ENET0_PTP_SYNC_FRAME_TX,
output ENET0_SOF_RX,
output ENET0_SOF_TX,
output reg [7:0] ENET0_GMII_TXD,
input ENET0_GMII_COL,
input ENET0_GMII_CRS,
input ENET0_GMII_RX_CLK,
input ENET0_GMII_RX_DV,
input ENET0_GMII_RX_ER,
input ENET0_GMII_TX_CLK,
input ENET0_MDIO_I,
input ENET0_EXT_INTIN,
input [7:0] ENET0_GMII_RXD,
//FMIO ENET1
output reg ENET1_GMII_TX_EN,
output reg ENET1_GMII_TX_ER,
output ENET1_MDIO_MDC,
output ENET1_MDIO_O,
output ENET1_MDIO_T,
output ENET1_PTP_DELAY_REQ_RX,
output ENET1_PTP_DELAY_REQ_TX,
output ENET1_PTP_PDELAY_REQ_RX,
output ENET1_PTP_PDELAY_REQ_TX,
output ENET1_PTP_PDELAY_RESP_RX,
output ENET1_PTP_PDELAY_RESP_TX,
output ENET1_PTP_SYNC_FRAME_RX,
output ENET1_PTP_SYNC_FRAME_TX,
output ENET1_SOF_RX,
output ENET1_SOF_TX,
output reg [7:0] ENET1_GMII_TXD,
input ENET1_GMII_COL,
input ENET1_GMII_CRS,
input ENET1_GMII_RX_CLK,
input ENET1_GMII_RX_DV,
input ENET1_GMII_RX_ER,
input ENET1_GMII_TX_CLK,
input ENET1_MDIO_I,
input ENET1_EXT_INTIN,
input [7:0] ENET1_GMII_RXD,
//FMIO GPIO
input [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T,
//FMIO I2C0
input I2C0_SDA_I,
output I2C0_SDA_O,
output I2C0_SDA_T,
input I2C0_SCL_I,
output I2C0_SCL_O,
output I2C0_SCL_T,
//FMIO I2C1
input I2C1_SDA_I,
output I2C1_SDA_O,
output I2C1_SDA_T,
input I2C1_SCL_I,
output I2C1_SCL_O,
output I2C1_SCL_T,
//FMIO PJTAG
input PJTAG_TCK,
input PJTAG_TMS,
input PJTAG_TDI,
output PJTAG_TDO,
//FMIO SDIO0
output SDIO0_CLK,
input SDIO0_CLK_FB,
output SDIO0_CMD_O,
input SDIO0_CMD_I,
output SDIO0_CMD_T,
input [3:0] SDIO0_DATA_I,
output [3:0] SDIO0_DATA_O,
output [3:0] SDIO0_DATA_T,
output SDIO0_LED,
input SDIO0_CDN,
input SDIO0_WP,
output SDIO0_BUSPOW,
output [2:0] SDIO0_BUSVOLT,
//FMIO SDIO1
output SDIO1_CLK,
input SDIO1_CLK_FB,
output SDIO1_CMD_O,
input SDIO1_CMD_I,
output SDIO1_CMD_T,
input [3:0] SDIO1_DATA_I,
output [3:0] SDIO1_DATA_O,
output [3:0] SDIO1_DATA_T,
output SDIO1_LED,
input SDIO1_CDN,
input SDIO1_WP,
output SDIO1_BUSPOW,
output [2:0] SDIO1_BUSVOLT,
//FMIO SPI0
input SPI0_SCLK_I,
output SPI0_SCLK_O,
output SPI0_SCLK_T,
input SPI0_MOSI_I,
output SPI0_MOSI_O,
output SPI0_MOSI_T,
input SPI0_MISO_I,
output SPI0_MISO_O,
output SPI0_MISO_T,
input SPI0_SS_I,
output SPI0_SS_O,
output SPI0_SS1_O,
output SPI0_SS2_O,
output SPI0_SS_T,
//FMIO SPI1
input SPI1_SCLK_I,
output SPI1_SCLK_O,
output SPI1_SCLK_T,
input SPI1_MOSI_I,
output SPI1_MOSI_O,
output SPI1_MOSI_T,
input SPI1_MISO_I,
output SPI1_MISO_O,
output SPI1_MISO_T,
input SPI1_SS_I,
output SPI1_SS_O,
output SPI1_SS1_O,
output SPI1_SS2_O,
output SPI1_SS_T,
//FMIO UART0
output UART0_DTRN,
output UART0_RTSN,
output UART0_TX,
input UART0_CTSN,
input UART0_DCDN,
input UART0_DSRN,
input UART0_RIN,
input UART0_RX,
//FMIO UART1
output UART1_DTRN,
output UART1_RTSN,
output UART1_TX,
input UART1_CTSN,
input UART1_DCDN,
input UART1_DSRN,
input UART1_RIN,
input UART1_RX,
//FMIO TTC0
output TTC0_WAVE0_OUT,
output TTC0_WAVE1_OUT,
output TTC0_WAVE2_OUT,
input TTC0_CLK0_IN,
input TTC0_CLK1_IN,
input TTC0_CLK2_IN,
//FMIO TTC1
output TTC1_WAVE0_OUT,
output TTC1_WAVE1_OUT,
output TTC1_WAVE2_OUT,
input TTC1_CLK0_IN,
input TTC1_CLK1_IN,
input TTC1_CLK2_IN,
//WDT
input WDT_CLK_IN,
output WDT_RST_OUT,
//FTPORT
input TRACE_CLK,
output TRACE_CTL,
output [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA,
output reg TRACE_CLK_OUT,
// USB
output [1:0] USB0_PORT_INDCTL,
output USB0_VBUS_PWRSELECT,
input USB0_VBUS_PWRFAULT,
output [1:0] USB1_PORT_INDCTL,
output USB1_VBUS_PWRSELECT,
input USB1_VBUS_PWRFAULT,
input SRAM_INTIN,
//AIO ===================================================
//M_AXI_GP0
// -- Output
output M_AXI_GP0_ARESETN,
output M_AXI_GP0_ARVALID,
output M_AXI_GP0_AWVALID,
output M_AXI_GP0_BREADY,
output M_AXI_GP0_RREADY,
output M_AXI_GP0_WLAST,
output M_AXI_GP0_WVALID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID,
output [1:0] M_AXI_GP0_ARBURST,
output [1:0] M_AXI_GP0_ARLOCK,
output [2:0] M_AXI_GP0_ARSIZE,
output [1:0] M_AXI_GP0_AWBURST,
output [1:0] M_AXI_GP0_AWLOCK,
output [2:0] M_AXI_GP0_AWSIZE,
output [2:0] M_AXI_GP0_ARPROT,
output [2:0] M_AXI_GP0_AWPROT,
output [31:0] M_AXI_GP0_ARADDR,
output [31:0] M_AXI_GP0_AWADDR,
output [31:0] M_AXI_GP0_WDATA,
output [3:0] M_AXI_GP0_ARCACHE,
output [3:0] M_AXI_GP0_ARLEN,
output [3:0] M_AXI_GP0_ARQOS,
output [3:0] M_AXI_GP0_AWCACHE,
output [3:0] M_AXI_GP0_AWLEN,
output [3:0] M_AXI_GP0_AWQOS,
output [3:0] M_AXI_GP0_WSTRB,
// -- Input
input M_AXI_GP0_ACLK,
input M_AXI_GP0_ARREADY,
input M_AXI_GP0_AWREADY,
input M_AXI_GP0_BVALID,
input M_AXI_GP0_RLAST,
input M_AXI_GP0_RVALID,
input M_AXI_GP0_WREADY,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID,
input [1:0] M_AXI_GP0_BRESP,
input [1:0] M_AXI_GP0_RRESP,
input [31:0] M_AXI_GP0_RDATA,
//M_AXI_GP1
// -- Output
output M_AXI_GP1_ARESETN,
output M_AXI_GP1_ARVALID,
output M_AXI_GP1_AWVALID,
output M_AXI_GP1_BREADY,
output M_AXI_GP1_RREADY,
output M_AXI_GP1_WLAST,
output M_AXI_GP1_WVALID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID,
output [1:0] M_AXI_GP1_ARBURST,
output [1:0] M_AXI_GP1_ARLOCK,
output [2:0] M_AXI_GP1_ARSIZE,
output [1:0] M_AXI_GP1_AWBURST,
output [1:0] M_AXI_GP1_AWLOCK,
output [2:0] M_AXI_GP1_AWSIZE,
output [2:0] M_AXI_GP1_ARPROT,
output [2:0] M_AXI_GP1_AWPROT,
output [31:0] M_AXI_GP1_ARADDR,
output [31:0] M_AXI_GP1_AWADDR,
output [31:0] M_AXI_GP1_WDATA,
output [3:0] M_AXI_GP1_ARCACHE,
output [3:0] M_AXI_GP1_ARLEN,
output [3:0] M_AXI_GP1_ARQOS,
output [3:0] M_AXI_GP1_AWCACHE,
output [3:0] M_AXI_GP1_AWLEN,
output [3:0] M_AXI_GP1_AWQOS,
output [3:0] M_AXI_GP1_WSTRB,
// -- Input
input M_AXI_GP1_ACLK,
input M_AXI_GP1_ARREADY,
input M_AXI_GP1_AWREADY,
input M_AXI_GP1_BVALID,
input M_AXI_GP1_RLAST,
input M_AXI_GP1_RVALID,
input M_AXI_GP1_WREADY,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID,
input [1:0] M_AXI_GP1_BRESP,
input [1:0] M_AXI_GP1_RRESP,
input [31:0] M_AXI_GP1_RDATA,
// S_AXI_GP0
// -- Output
output S_AXI_GP0_ARESETN,
output S_AXI_GP0_ARREADY,
output S_AXI_GP0_AWREADY,
output S_AXI_GP0_BVALID,
output S_AXI_GP0_RLAST,
output S_AXI_GP0_RVALID,
output S_AXI_GP0_WREADY,
output [1:0] S_AXI_GP0_BRESP,
output [1:0] S_AXI_GP0_RRESP,
output [31:0] S_AXI_GP0_RDATA,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID,
// -- Input
input S_AXI_GP0_ACLK,
input S_AXI_GP0_ARVALID,
input S_AXI_GP0_AWVALID,
input S_AXI_GP0_BREADY,
input S_AXI_GP0_RREADY,
input S_AXI_GP0_WLAST,
input S_AXI_GP0_WVALID,
input [1:0] S_AXI_GP0_ARBURST,
input [1:0] S_AXI_GP0_ARLOCK,
input [2:0] S_AXI_GP0_ARSIZE,
input [1:0] S_AXI_GP0_AWBURST,
input [1:0] S_AXI_GP0_AWLOCK,
input [2:0] S_AXI_GP0_AWSIZE,
input [2:0] S_AXI_GP0_ARPROT,
input [2:0] S_AXI_GP0_AWPROT,
input [31:0] S_AXI_GP0_ARADDR,
input [31:0] S_AXI_GP0_AWADDR,
input [31:0] S_AXI_GP0_WDATA,
input [3:0] S_AXI_GP0_ARCACHE,
input [3:0] S_AXI_GP0_ARLEN,
input [3:0] S_AXI_GP0_ARQOS,
input [3:0] S_AXI_GP0_AWCACHE,
input [3:0] S_AXI_GP0_AWLEN,
input [3:0] S_AXI_GP0_AWQOS,
input [3:0] S_AXI_GP0_WSTRB,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID,
// S_AXI_GP1
// -- Output
output S_AXI_GP1_ARESETN,
output S_AXI_GP1_ARREADY,
output S_AXI_GP1_AWREADY,
output S_AXI_GP1_BVALID,
output S_AXI_GP1_RLAST,
output S_AXI_GP1_RVALID,
output S_AXI_GP1_WREADY,
output [1:0] S_AXI_GP1_BRESP,
output [1:0] S_AXI_GP1_RRESP,
output [31:0] S_AXI_GP1_RDATA,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID,
// -- Input
input S_AXI_GP1_ACLK,
input S_AXI_GP1_ARVALID,
input S_AXI_GP1_AWVALID,
input S_AXI_GP1_BREADY,
input S_AXI_GP1_RREADY,
input S_AXI_GP1_WLAST,
input S_AXI_GP1_WVALID,
input [1:0] S_AXI_GP1_ARBURST,
input [1:0] S_AXI_GP1_ARLOCK,
input [2:0] S_AXI_GP1_ARSIZE,
input [1:0] S_AXI_GP1_AWBURST,
input [1:0] S_AXI_GP1_AWLOCK,
input [2:0] S_AXI_GP1_AWSIZE,
input [2:0] S_AXI_GP1_ARPROT,
input [2:0] S_AXI_GP1_AWPROT,
input [31:0] S_AXI_GP1_ARADDR,
input [31:0] S_AXI_GP1_AWADDR,
input [31:0] S_AXI_GP1_WDATA,
input [3:0] S_AXI_GP1_ARCACHE,
input [3:0] S_AXI_GP1_ARLEN,
input [3:0] S_AXI_GP1_ARQOS,
input [3:0] S_AXI_GP1_AWCACHE,
input [3:0] S_AXI_GP1_AWLEN,
input [3:0] S_AXI_GP1_AWQOS,
input [3:0] S_AXI_GP1_WSTRB,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID,
//S_AXI_ACP
// -- Output
output S_AXI_ACP_ARESETN,
output S_AXI_ACP_ARREADY,
output S_AXI_ACP_AWREADY,
output S_AXI_ACP_BVALID,
output S_AXI_ACP_RLAST,
output S_AXI_ACP_RVALID,
output S_AXI_ACP_WREADY,
output [1:0] S_AXI_ACP_BRESP,
output [1:0] S_AXI_ACP_RRESP,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID,
output [63:0] S_AXI_ACP_RDATA,
// -- Input
input S_AXI_ACP_ACLK,
input S_AXI_ACP_ARVALID,
input S_AXI_ACP_AWVALID,
input S_AXI_ACP_BREADY,
input S_AXI_ACP_RREADY,
input S_AXI_ACP_WLAST,
input S_AXI_ACP_WVALID,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID,
input [2:0] S_AXI_ACP_ARPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID,
input [2:0] S_AXI_ACP_AWPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID,
input [31:0] S_AXI_ACP_ARADDR,
input [31:0] S_AXI_ACP_AWADDR,
input [3:0] S_AXI_ACP_ARCACHE,
input [3:0] S_AXI_ACP_ARLEN,
input [3:0] S_AXI_ACP_ARQOS,
input [3:0] S_AXI_ACP_AWCACHE,
input [3:0] S_AXI_ACP_AWLEN,
input [3:0] S_AXI_ACP_AWQOS,
input [1:0] S_AXI_ACP_ARBURST,
input [1:0] S_AXI_ACP_ARLOCK,
input [2:0] S_AXI_ACP_ARSIZE,
input [1:0] S_AXI_ACP_AWBURST,
input [1:0] S_AXI_ACP_AWLOCK,
input [2:0] S_AXI_ACP_AWSIZE,
input [4:0] S_AXI_ACP_ARUSER,
input [4:0] S_AXI_ACP_AWUSER,
input [63:0] S_AXI_ACP_WDATA,
input [7:0] S_AXI_ACP_WSTRB,
// S_AXI_HP_0
// -- Output
output S_AXI_HP0_ARESETN,
output S_AXI_HP0_ARREADY,
output S_AXI_HP0_AWREADY,
output S_AXI_HP0_BVALID,
output S_AXI_HP0_RLAST,
output S_AXI_HP0_RVALID,
output S_AXI_HP0_WREADY,
output [1:0] S_AXI_HP0_BRESP,
output [1:0] S_AXI_HP0_RRESP,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID,
output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA,
output [7:0] S_AXI_HP0_RCOUNT,
output [7:0] S_AXI_HP0_WCOUNT,
output [2:0] S_AXI_HP0_RACOUNT,
output [5:0] S_AXI_HP0_WACOUNT,
// -- Input
input S_AXI_HP0_ACLK,
input S_AXI_HP0_ARVALID,
input S_AXI_HP0_AWVALID,
input S_AXI_HP0_BREADY,
input S_AXI_HP0_RDISSUECAP1_EN,
input S_AXI_HP0_RREADY,
input S_AXI_HP0_WLAST,
input S_AXI_HP0_WRISSUECAP1_EN,
input S_AXI_HP0_WVALID,
input [1:0] S_AXI_HP0_ARBURST,
input [1:0] S_AXI_HP0_ARLOCK,
input [2:0] S_AXI_HP0_ARSIZE,
input [1:0] S_AXI_HP0_AWBURST,
input [1:0] S_AXI_HP0_AWLOCK,
input [2:0] S_AXI_HP0_AWSIZE,
input [2:0] S_AXI_HP0_ARPROT,
input [2:0] S_AXI_HP0_AWPROT,
input [31:0] S_AXI_HP0_ARADDR,
input [31:0] S_AXI_HP0_AWADDR,
input [3:0] S_AXI_HP0_ARCACHE,
input [3:0] S_AXI_HP0_ARLEN,
input [3:0] S_AXI_HP0_ARQOS,
input [3:0] S_AXI_HP0_AWCACHE,
input [3:0] S_AXI_HP0_AWLEN,
input [3:0] S_AXI_HP0_AWQOS,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID,
input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA,
input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB,
// S_AXI_HP1
// -- Output
output S_AXI_HP1_ARESETN,
output S_AXI_HP1_ARREADY,
output S_AXI_HP1_AWREADY,
output S_AXI_HP1_BVALID,
output S_AXI_HP1_RLAST,
output S_AXI_HP1_RVALID,
output S_AXI_HP1_WREADY,
output [1:0] S_AXI_HP1_BRESP,
output [1:0] S_AXI_HP1_RRESP,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID,
output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA,
output [7:0] S_AXI_HP1_RCOUNT,
output [7:0] S_AXI_HP1_WCOUNT,
output [2:0] S_AXI_HP1_RACOUNT,
output [5:0] S_AXI_HP1_WACOUNT,
// -- Input
input S_AXI_HP1_ACLK,
input S_AXI_HP1_ARVALID,
input S_AXI_HP1_AWVALID,
input S_AXI_HP1_BREADY,
input S_AXI_HP1_RDISSUECAP1_EN,
input S_AXI_HP1_RREADY,
input S_AXI_HP1_WLAST,
input S_AXI_HP1_WRISSUECAP1_EN,
input S_AXI_HP1_WVALID,
input [1:0] S_AXI_HP1_ARBURST,
input [1:0] S_AXI_HP1_ARLOCK,
input [2:0] S_AXI_HP1_ARSIZE,
input [1:0] S_AXI_HP1_AWBURST,
input [1:0] S_AXI_HP1_AWLOCK,
input [2:0] S_AXI_HP1_AWSIZE,
input [2:0] S_AXI_HP1_ARPROT,
input [2:0] S_AXI_HP1_AWPROT,
input [31:0] S_AXI_HP1_ARADDR,
input [31:0] S_AXI_HP1_AWADDR,
input [3:0] S_AXI_HP1_ARCACHE,
input [3:0] S_AXI_HP1_ARLEN,
input [3:0] S_AXI_HP1_ARQOS,
input [3:0] S_AXI_HP1_AWCACHE,
input [3:0] S_AXI_HP1_AWLEN,
input [3:0] S_AXI_HP1_AWQOS,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID,
input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA,
input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB,
// S_AXI_HP2
// -- Output
output S_AXI_HP2_ARESETN,
output S_AXI_HP2_ARREADY,
output S_AXI_HP2_AWREADY,
output S_AXI_HP2_BVALID,
output S_AXI_HP2_RLAST,
output S_AXI_HP2_RVALID,
output S_AXI_HP2_WREADY,
output [1:0] S_AXI_HP2_BRESP,
output [1:0] S_AXI_HP2_RRESP,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID,
output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA,
output [7:0] S_AXI_HP2_RCOUNT,
output [7:0] S_AXI_HP2_WCOUNT,
output [2:0] S_AXI_HP2_RACOUNT,
output [5:0] S_AXI_HP2_WACOUNT,
// -- Input
input S_AXI_HP2_ACLK,
input S_AXI_HP2_ARVALID,
input S_AXI_HP2_AWVALID,
input S_AXI_HP2_BREADY,
input S_AXI_HP2_RDISSUECAP1_EN,
input S_AXI_HP2_RREADY,
input S_AXI_HP2_WLAST,
input S_AXI_HP2_WRISSUECAP1_EN,
input S_AXI_HP2_WVALID,
input [1:0] S_AXI_HP2_ARBURST,
input [1:0] S_AXI_HP2_ARLOCK,
input [2:0] S_AXI_HP2_ARSIZE,
input [1:0] S_AXI_HP2_AWBURST,
input [1:0] S_AXI_HP2_AWLOCK,
input [2:0] S_AXI_HP2_AWSIZE,
input [2:0] S_AXI_HP2_ARPROT,
input [2:0] S_AXI_HP2_AWPROT,
input [31:0] S_AXI_HP2_ARADDR,
input [31:0] S_AXI_HP2_AWADDR,
input [3:0] S_AXI_HP2_ARCACHE,
input [3:0] S_AXI_HP2_ARLEN,
input [3:0] S_AXI_HP2_ARQOS,
input [3:0] S_AXI_HP2_AWCACHE,
input [3:0] S_AXI_HP2_AWLEN,
input [3:0] S_AXI_HP2_AWQOS,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID,
input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA,
input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB,
// S_AXI_HP_3
// -- Output
output S_AXI_HP3_ARESETN,
output S_AXI_HP3_ARREADY,
output S_AXI_HP3_AWREADY,
output S_AXI_HP3_BVALID,
output S_AXI_HP3_RLAST,
output S_AXI_HP3_RVALID,
output S_AXI_HP3_WREADY,
output [1:0] S_AXI_HP3_BRESP,
output [1:0] S_AXI_HP3_RRESP,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID,
output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA,
output [7:0] S_AXI_HP3_RCOUNT,
output [7:0] S_AXI_HP3_WCOUNT,
output [2:0] S_AXI_HP3_RACOUNT,
output [5:0] S_AXI_HP3_WACOUNT,
// -- Input
input S_AXI_HP3_ACLK,
input S_AXI_HP3_ARVALID,
input S_AXI_HP3_AWVALID,
input S_AXI_HP3_BREADY,
input S_AXI_HP3_RDISSUECAP1_EN,
input S_AXI_HP3_RREADY,
input S_AXI_HP3_WLAST,
input S_AXI_HP3_WRISSUECAP1_EN,
input S_AXI_HP3_WVALID,
input [1:0] S_AXI_HP3_ARBURST,
input [1:0] S_AXI_HP3_ARLOCK,
input [2:0] S_AXI_HP3_ARSIZE,
input [1:0] S_AXI_HP3_AWBURST,
input [1:0] S_AXI_HP3_AWLOCK,
input [2:0] S_AXI_HP3_AWSIZE,
input [2:0] S_AXI_HP3_ARPROT,
input [2:0] S_AXI_HP3_AWPROT,
input [31:0] S_AXI_HP3_ARADDR,
input [31:0] S_AXI_HP3_AWADDR,
input [3:0] S_AXI_HP3_ARCACHE,
input [3:0] S_AXI_HP3_ARLEN,
input [3:0] S_AXI_HP3_ARQOS,
input [3:0] S_AXI_HP3_AWCACHE,
input [3:0] S_AXI_HP3_AWLEN,
input [3:0] S_AXI_HP3_AWQOS,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID,
input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA,
input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB,
//FIO ========================================
//IRQ
//output [28:0] IRQ_P2F,
output IRQ_P2F_DMAC_ABORT ,
output IRQ_P2F_DMAC0,
output IRQ_P2F_DMAC1,
output IRQ_P2F_DMAC2,
output IRQ_P2F_DMAC3,
output IRQ_P2F_DMAC4,
output IRQ_P2F_DMAC5,
output IRQ_P2F_DMAC6,
output IRQ_P2F_DMAC7,
output IRQ_P2F_SMC,
output IRQ_P2F_QSPI,
output IRQ_P2F_CTI,
output IRQ_P2F_GPIO,
output IRQ_P2F_USB0,
output IRQ_P2F_ENET0,
output IRQ_P2F_ENET_WAKE0,
output IRQ_P2F_SDIO0,
output IRQ_P2F_I2C0,
output IRQ_P2F_SPI0,
output IRQ_P2F_UART0,
output IRQ_P2F_CAN0,
output IRQ_P2F_USB1,
output IRQ_P2F_ENET1,
output IRQ_P2F_ENET_WAKE1,
output IRQ_P2F_SDIO1,
output IRQ_P2F_I2C1,
output IRQ_P2F_SPI1,
output IRQ_P2F_UART1,
output IRQ_P2F_CAN1,
input [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P,
input Core0_nFIQ,
input Core0_nIRQ,
input Core1_nFIQ,
input Core1_nIRQ,
//DMA
output [1:0] DMA0_DATYPE,
output DMA0_DAVALID,
output DMA0_DRREADY,
output DMA0_RSTN,
output [1:0] DMA1_DATYPE,
output DMA1_DAVALID,
output DMA1_DRREADY,
output DMA1_RSTN,
output [1:0] DMA2_DATYPE,
output DMA2_DAVALID,
output DMA2_DRREADY,
output DMA2_RSTN,
output [1:0] DMA3_DATYPE,
output DMA3_DAVALID,
output DMA3_DRREADY,
output DMA3_RSTN,
input DMA0_ACLK,
input DMA0_DAREADY,
input DMA0_DRLAST,
input DMA0_DRVALID,
input DMA1_ACLK,
input DMA1_DAREADY,
input DMA1_DRLAST,
input DMA1_DRVALID,
input DMA2_ACLK,
input DMA2_DAREADY,
input DMA2_DRLAST,
input DMA2_DRVALID,
input DMA3_ACLK,
input DMA3_DAREADY,
input DMA3_DRLAST,
input DMA3_DRVALID,
input [1:0] DMA0_DRTYPE,
input [1:0] DMA1_DRTYPE,
input [1:0] DMA2_DRTYPE,
input [1:0] DMA3_DRTYPE,
//FCLK
output FCLK_CLK3,
output FCLK_CLK2,
output FCLK_CLK1,
output FCLK_CLK0,
input FCLK_CLKTRIG3_N,
input FCLK_CLKTRIG2_N,
input FCLK_CLKTRIG1_N,
input FCLK_CLKTRIG0_N,
output FCLK_RESET3_N,
output FCLK_RESET2_N,
output FCLK_RESET1_N,
output FCLK_RESET0_N,
//FTMD
input [31:0] FTMD_TRACEIN_DATA,
input FTMD_TRACEIN_VALID,
input FTMD_TRACEIN_CLK,
input [3:0] FTMD_TRACEIN_ATID,
//FTMT
input FTMT_F2P_TRIG_0,
output FTMT_F2P_TRIGACK_0,
input FTMT_F2P_TRIG_1,
output FTMT_F2P_TRIGACK_1,
input FTMT_F2P_TRIG_2,
output FTMT_F2P_TRIGACK_2,
input FTMT_F2P_TRIG_3,
output FTMT_F2P_TRIGACK_3,
input [31:0] FTMT_F2P_DEBUG,
input FTMT_P2F_TRIGACK_0,
output FTMT_P2F_TRIG_0,
input FTMT_P2F_TRIGACK_1,
output FTMT_P2F_TRIG_1,
input FTMT_P2F_TRIGACK_2,
output FTMT_P2F_TRIG_2,
input FTMT_P2F_TRIGACK_3,
output FTMT_P2F_TRIG_3,
output [31:0] FTMT_P2F_DEBUG,
//FIDLE
input FPGA_IDLE_N,
//EVENT
output EVENT_EVENTO,
output [1:0] EVENT_STANDBYWFE,
output [1:0] EVENT_STANDBYWFI,
input EVENT_EVENTI,
//DARB
input [3:0] DDR_ARB,
inout [C_MIO_PRIMITIVE - 1:0] MIO,
//DDR
inout DDR_CAS_n, // CASB
inout DDR_CKE, // CKE
inout DDR_Clk_n, // CKN
inout DDR_Clk, // CKP
inout DDR_CS_n, // CSB
inout DDR_DRSTB, // DDR_DRSTB
inout DDR_ODT, // ODT
inout DDR_RAS_n, // RASB
inout DDR_WEB,
inout [2:0] DDR_BankAddr, // BA
inout [14:0] DDR_Addr, // A
inout DDR_VRN,
inout DDR_VRP,
inout [C_DM_WIDTH - 1:0] DDR_DM, // DM
inout [C_DQ_WIDTH - 1:0] DDR_DQ, // DQ
inout [C_DQS_WIDTH -1:0] DDR_DQS_n, // DQSN
inout [C_DQS_WIDTH - 1:0] DDR_DQS, // DQSP
inout PS_SRSTB, // SRSTB
inout PS_CLK, // CLK
inout PS_PORB // PORB
);
wire [11:0] M_AXI_GP0_AWID_FULL;
wire [11:0] M_AXI_GP0_WID_FULL;
wire [11:0] M_AXI_GP0_ARID_FULL;
wire [11:0] M_AXI_GP0_BID_FULL;
wire [11:0] M_AXI_GP0_RID_FULL;
wire [11:0] M_AXI_GP1_AWID_FULL;
wire [11:0] M_AXI_GP1_WID_FULL;
wire [11:0] M_AXI_GP1_ARID_FULL;
wire [11:0] M_AXI_GP1_BID_FULL;
wire [11:0] M_AXI_GP1_RID_FULL;
//wire ENET0_GMII_TX_EN_i;
//wire ENET0_GMII_TX_ER_i;
reg ENET0_GMII_COL_i;
reg ENET0_GMII_CRS_i;
reg ENET0_GMII_RX_DV_i;
reg ENET0_GMII_RX_ER_i;
reg [7:0] ENET0_GMII_RXD_i;
wire [7:0] ENET0_GMII_TXD_i;
wire ENET1_GMII_TX_EN_i;
wire ENET1_GMII_TX_ER_i;
reg ENET1_GMII_COL_i;
reg ENET1_GMII_CRS_i;
reg ENET1_GMII_RX_DV_i;
reg ENET1_GMII_RX_ER_i;
reg [7:0] ENET1_GMII_RXD_i;
wire [7:0] ENET1_GMII_TXD_i;
reg [31:0] FTMD_TRACEIN_DATA_notracebuf;
reg FTMD_TRACEIN_VALID_notracebuf;
reg [3:0] FTMD_TRACEIN_ATID_notracebuf;
wire [31:0] FTMD_TRACEIN_DATA_i;
wire FTMD_TRACEIN_VALID_i;
wire [3:0] FTMD_TRACEIN_ATID_i;
wire [31:0] FTMD_TRACEIN_DATA_tracebuf;
wire FTMD_TRACEIN_VALID_tracebuf;
wire [3:0] FTMD_TRACEIN_ATID_tracebuf;
wire [5:0] S_AXI_GP0_BID_out;
wire [5:0] S_AXI_GP0_RID_out;
wire [5:0] S_AXI_GP0_ARID_in;
wire [5:0] S_AXI_GP0_AWID_in;
wire [5:0] S_AXI_GP0_WID_in;
wire [5:0] S_AXI_GP1_BID_out;
wire [5:0] S_AXI_GP1_RID_out;
wire [5:0] S_AXI_GP1_ARID_in;
wire [5:0] S_AXI_GP1_AWID_in;
wire [5:0] S_AXI_GP1_WID_in;
wire [5:0] S_AXI_HP0_BID_out;
wire [5:0] S_AXI_HP0_RID_out;
wire [5:0] S_AXI_HP0_ARID_in;
wire [5:0] S_AXI_HP0_AWID_in;
wire [5:0] S_AXI_HP0_WID_in;
wire [5:0] S_AXI_HP1_BID_out;
wire [5:0] S_AXI_HP1_RID_out;
wire [5:0] S_AXI_HP1_ARID_in;
wire [5:0] S_AXI_HP1_AWID_in;
wire [5:0] S_AXI_HP1_WID_in;
wire [5:0] S_AXI_HP2_BID_out;
wire [5:0] S_AXI_HP2_RID_out;
wire [5:0] S_AXI_HP2_ARID_in;
wire [5:0] S_AXI_HP2_AWID_in;
wire [5:0] S_AXI_HP2_WID_in;
wire [5:0] S_AXI_HP3_BID_out;
wire [5:0] S_AXI_HP3_RID_out;
wire [5:0] S_AXI_HP3_ARID_in;
wire [5:0] S_AXI_HP3_AWID_in;
wire [5:0] S_AXI_HP3_WID_in;
wire [2:0] S_AXI_ACP_BID_out;
wire [2:0] S_AXI_ACP_RID_out;
wire [2:0] S_AXI_ACP_ARID_in;
wire [2:0] S_AXI_ACP_AWID_in;
wire [2:0] S_AXI_ACP_WID_in;
wire [63:0] S_AXI_HP0_WDATA_in;
wire [7:0] S_AXI_HP0_WSTRB_in;
wire [63:0] S_AXI_HP0_RDATA_out;
wire [63:0] S_AXI_HP1_WDATA_in;
wire [7:0] S_AXI_HP1_WSTRB_in;
wire [63:0] S_AXI_HP1_RDATA_out;
wire [63:0] S_AXI_HP2_WDATA_in;
wire [7:0] S_AXI_HP2_WSTRB_in;
wire [63:0] S_AXI_HP2_RDATA_out;
wire [63:0] S_AXI_HP3_WDATA_in;
wire [7:0] S_AXI_HP3_WSTRB_in;
wire [63:0] S_AXI_HP3_RDATA_out;
wire [1:0] M_AXI_GP0_ARSIZE_i;
wire [1:0] M_AXI_GP0_AWSIZE_i;
wire [1:0] M_AXI_GP1_ARSIZE_i;
wire [1:0] M_AXI_GP1_AWSIZE_i;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPBID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPRID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPARID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPAWID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPWID_W;
wire SAXIACPARREADY_W;
wire SAXIACPAWREADY_W;
wire SAXIACPBVALID_W;
wire SAXIACPRLAST_W;
wire SAXIACPRVALID_W;
wire SAXIACPWREADY_W;
wire [1:0] SAXIACPBRESP_W;
wire [1:0] SAXIACPRRESP_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_BID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_RID;
wire [63:0] SAXIACPRDATA_W;
wire S_AXI_ATC_ARVALID;
wire S_AXI_ATC_AWVALID;
wire S_AXI_ATC_BREADY;
wire S_AXI_ATC_RREADY;
wire S_AXI_ATC_WLAST;
wire S_AXI_ATC_WVALID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_ARID;
wire [2:0] S_AXI_ATC_ARPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_AWID;
wire [2:0] S_AXI_ATC_AWPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_WID;
wire [31:0] S_AXI_ATC_ARADDR;
wire [31:0] S_AXI_ATC_AWADDR;
wire [3:0] S_AXI_ATC_ARCACHE;
wire [3:0] S_AXI_ATC_ARLEN;
wire [3:0] S_AXI_ATC_ARQOS;
wire [3:0] S_AXI_ATC_AWCACHE;
wire [3:0] S_AXI_ATC_AWLEN;
wire [3:0] S_AXI_ATC_AWQOS;
wire [1:0] S_AXI_ATC_ARBURST;
wire [1:0] S_AXI_ATC_ARLOCK;
wire [2:0] S_AXI_ATC_ARSIZE;
wire [1:0] S_AXI_ATC_AWBURST;
wire [1:0] S_AXI_ATC_AWLOCK;
wire [2:0] S_AXI_ATC_AWSIZE;
wire [4:0] S_AXI_ATC_ARUSER;
wire [4:0] S_AXI_ATC_AWUSER;
wire [63:0] S_AXI_ATC_WDATA;
wire [7:0] S_AXI_ATC_WSTRB;
wire SAXIACPARVALID_W;
wire SAXIACPAWVALID_W;
wire SAXIACPBREADY_W;
wire SAXIACPRREADY_W;
wire SAXIACPWLAST_W;
wire SAXIACPWVALID_W;
wire [2:0] SAXIACPARPROT_W;
wire [2:0] SAXIACPAWPROT_W;
wire [31:0] SAXIACPARADDR_W;
wire [31:0] SAXIACPAWADDR_W;
wire [3:0] SAXIACPARCACHE_W;
wire [3:0] SAXIACPARLEN_W;
wire [3:0] SAXIACPARQOS_W;
wire [3:0] SAXIACPAWCACHE_W;
wire [3:0] SAXIACPAWLEN_W;
wire [3:0] SAXIACPAWQOS_W;
wire [1:0] SAXIACPARBURST_W;
wire [1:0] SAXIACPARLOCK_W;
wire [2:0] SAXIACPARSIZE_W;
wire [1:0] SAXIACPAWBURST_W;
wire [1:0] SAXIACPAWLOCK_W;
wire [2:0] SAXIACPAWSIZE_W;
wire [4:0] SAXIACPARUSER_W;
wire [4:0] SAXIACPAWUSER_W;
wire [63:0] SAXIACPWDATA_W;
wire [7:0] SAXIACPWSTRB_W;
// AxUSER signal update
wire [4:0] param_aruser;
wire [4:0] param_awuser;
// Added to address CR 651751
wire [3:0] fclk_clktrig_gnd = 4'h0;
wire [19:0] irq_f2p_i;
wire [15:0] irq_f2p_null = 16'h0000;
// EMIO I2C0
wire I2C0_SDA_T_n;
wire I2C0_SCL_T_n;
// EMIO I2C1
wire I2C1_SDA_T_n;
wire I2C1_SCL_T_n;
// EMIO SPI0
wire SPI0_SCLK_T_n;
wire SPI0_MOSI_T_n;
wire SPI0_MISO_T_n;
wire SPI0_SS_T_n;
// EMIO SPI1
wire SPI1_SCLK_T_n;
wire SPI1_MOSI_T_n;
wire SPI1_MISO_T_n;
wire SPI1_SS_T_n;
// EMIO GEM0
wire ENET0_MDIO_T_n;
// EMIO GEM1
wire ENET1_MDIO_T_n;
// EMIO GPIO
wire [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T_n;
wire [63:0] gpio_out_t_n;
wire [63:0] gpio_out;
wire [63:0] gpio_in63_0;
//For Clock buffering
wire [3:0] FCLK_CLK_unbuffered;
wire [3:0] FCLK_CLK_buffered;
wire FCLK_CLK0_temp;
// EMIO PJTAG
wire PJTAG_TDO_O;
wire PJTAG_TDO_T;
wire PJTAG_TDO_T_n;
// EMIO SDIO0
wire SDIO0_CMD_T_n;
wire [3:0] SDIO0_DATA_T_n;
// EMIO SDIO1
wire SDIO1_CMD_T_n;
wire [3:0] SDIO1_DATA_T_n;
// buffered IO
wire [C_MIO_PRIMITIVE - 1:0] buffered_MIO;
wire buffered_DDR_WEB;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_Clk_n;
wire buffered_DDR_Clk;
wire buffered_DDR_CS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire [2:0] buffered_DDR_BankAddr;
wire [14:0] buffered_DDR_Addr;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire [C_DM_WIDTH - 1:0] buffered_DDR_DM;
wire [C_DQ_WIDTH - 1:0] buffered_DDR_DQ;
wire [C_DQS_WIDTH -1:0] buffered_DDR_DQS_n;
wire [C_DQS_WIDTH - 1:0] buffered_DDR_DQS;
wire buffered_PS_SRSTB;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire [31:0] TRACE_DATA_i;
wire TRACE_CTL_i;
(* keep = "true" *) reg TRACE_CTL_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
(* keep = "true" *) reg [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
// fixed CR #665394
integer j;
generate
if (C_EN_EMIO_TRACE == 1) begin
always @(posedge TRACE_CLK)
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_CTL_i;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_DATA_i[(C_TRACE_INTERNAL_WIDTH-1):0];
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= TRACE_CTL_PIPE[j];
TRACE_DATA_PIPE[j-1] <= TRACE_DATA_PIPE[j];
end
TRACE_CLK_OUT <= ~TRACE_CLK_OUT;
end
end
else
begin
always @*
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= 1'b0;
TRACE_DATA_PIPE[j-1] <= 1'b0;
end
TRACE_CLK_OUT <= 1'b0;
end
end
endgenerate
assign TRACE_CTL = TRACE_CTL_PIPE[0];
assign TRACE_DATA = TRACE_DATA_PIPE[0];
//irq_p2f
// Updated IRQ_F2P logic to address CR 641523
generate
if(C_NUM_F2P_INTR_INPUTS == 0) begin : irq_f2p_select_null
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,irq_f2p_null[15:0]};
end else if(C_NUM_F2P_INTR_INPUTS == 16) begin : irq_f2p_select_all
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,IRQ_F2P[15:0]};
end else begin : irq_f2p_select
if (C_IRQ_F2P_MODE == "DIRECT") begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0],
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0]};
end else begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0],
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0]};
end
end
endgenerate
assign M_AXI_GP0_ARSIZE[2:0] = {1'b0, M_AXI_GP0_ARSIZE_i[1:0]};
assign M_AXI_GP0_AWSIZE[2:0] = {1'b0, M_AXI_GP0_AWSIZE_i[1:0]};
assign M_AXI_GP1_ARSIZE[2:0] = {1'b0, M_AXI_GP1_ARSIZE_i[1:0]};
assign M_AXI_GP1_AWSIZE[2:0] = {1'b0, M_AXI_GP1_AWSIZE_i[1:0]};
// Compress Function
// Modified as per CR 631955
//function [11:0] uncompress_id;
// input [5:0] id;
// begin
// case (id[5:0])
// // dmac0
// 6'd1 : uncompress_id = 12'b010000_1000_00 ;
// 6'd2 : uncompress_id = 12'b010000_0000_00 ;
// 6'd3 : uncompress_id = 12'b010000_0001_00 ;
// 6'd4 : uncompress_id = 12'b010000_0010_00 ;
// 6'd5 : uncompress_id = 12'b010000_0011_00 ;
// 6'd6 : uncompress_id = 12'b010000_0100_00 ;
// 6'd7 : uncompress_id = 12'b010000_0101_00 ;
// 6'd8 : uncompress_id = 12'b010000_0110_00 ;
// 6'd9 : uncompress_id = 12'b010000_0111_00 ;
// // ioum
// 6'd10 : uncompress_id = 12'b0100000_000_01 ;
// 6'd11 : uncompress_id = 12'b0100000_001_01 ;
// 6'd12 : uncompress_id = 12'b0100000_010_01 ;
// 6'd13 : uncompress_id = 12'b0100000_011_01 ;
// 6'd14 : uncompress_id = 12'b0100000_100_01 ;
// 6'd15 : uncompress_id = 12'b0100000_101_01 ;
// // devci
// 6'd16 : uncompress_id = 12'b1000_0000_0000 ;
// // dap
// 6'd17 : uncompress_id = 12'b1000_0000_0001 ;
// // l2m1 (CPU000)
// 6'd18 : uncompress_id = 12'b11_000_000_00_00 ;
// 6'd19 : uncompress_id = 12'b11_010_000_00_00 ;
// 6'd20 : uncompress_id = 12'b11_011_000_00_00 ;
// 6'd21 : uncompress_id = 12'b11_100_000_00_00 ;
// 6'd22 : uncompress_id = 12'b11_101_000_00_00 ;
// 6'd23 : uncompress_id = 12'b11_110_000_00_00 ;
// 6'd24 : uncompress_id = 12'b11_111_000_00_00 ;
// // l2m1 (CPU001)
// 6'd25 : uncompress_id = 12'b11_000_001_00_00 ;
// 6'd26 : uncompress_id = 12'b11_010_001_00_00 ;
// 6'd27 : uncompress_id = 12'b11_011_001_00_00 ;
// 6'd28 : uncompress_id = 12'b11_100_001_00_00 ;
// 6'd29 : uncompress_id = 12'b11_101_001_00_00 ;
// 6'd30 : uncompress_id = 12'b11_110_001_00_00 ;
// 6'd31 : uncompress_id = 12'b11_111_001_00_00 ;
// // l2m1 (L2CC)
// 6'd32 : uncompress_id = 12'b11_000_00101_00 ;
// 6'd33 : uncompress_id = 12'b11_000_01001_00 ;
// 6'd34 : uncompress_id = 12'b11_000_01101_00 ;
// 6'd35 : uncompress_id = 12'b11_000_10011_00 ;
// 6'd36 : uncompress_id = 12'b11_000_10111_00 ;
// 6'd37 : uncompress_id = 12'b11_000_11011_00 ;
// 6'd38 : uncompress_id = 12'b11_000_11111_00 ;
// 6'd39 : uncompress_id = 12'b11_000_00011_00 ;
// 6'd40 : uncompress_id = 12'b11_000_00111_00 ;
// 6'd41 : uncompress_id = 12'b11_000_01011_00 ;
// 6'd42 : uncompress_id = 12'b11_000_01111_00 ;
// 6'd43 : uncompress_id = 12'b11_000_00001_00 ;
// // l2m1 (ACP)
// 6'd44 : uncompress_id = 12'b11_000_10000_00 ;
// 6'd45 : uncompress_id = 12'b11_001_10000_00 ;
// 6'd46 : uncompress_id = 12'b11_010_10000_00 ;
// 6'd47 : uncompress_id = 12'b11_011_10000_00 ;
// 6'd48 : uncompress_id = 12'b11_100_10000_00 ;
// 6'd49 : uncompress_id = 12'b11_101_10000_00 ;
// 6'd50 : uncompress_id = 12'b11_110_10000_00 ;
// 6'd51 : uncompress_id = 12'b11_111_10000_00 ;
// default : uncompress_id = ~0;
// endcase
// end
//endfunction
//
//function [5:0] compress_id;
// input [11:0] id;
// begin
// case (id[11:0])
// // dmac0
// 12'b010000_1000_00 : compress_id = 'd1 ;
// 12'b010000_0000_00 : compress_id = 'd2 ;
// 12'b010000_0001_00 : compress_id = 'd3 ;
// 12'b010000_0010_00 : compress_id = 'd4 ;
// 12'b010000_0011_00 : compress_id = 'd5 ;
// 12'b010000_0100_00 : compress_id = 'd6 ;
// 12'b010000_0101_00 : compress_id = 'd7 ;
// 12'b010000_0110_00 : compress_id = 'd8 ;
// 12'b010000_0111_00 : compress_id = 'd9 ;
// // ioum
// 12'b0100000_000_01 : compress_id = 'd10 ;
// 12'b0100000_001_01 : compress_id = 'd11 ;
// 12'b0100000_010_01 : compress_id = 'd12 ;
// 12'b0100000_011_01 : compress_id = 'd13 ;
// 12'b0100000_100_01 : compress_id = 'd14 ;
// 12'b0100000_101_01 : compress_id = 'd15 ;
// // devci
// 12'b1000_0000_0000 : compress_id = 'd16 ;
// // dap
// 12'b1000_0000_0001 : compress_id = 'd17 ;
// // l2m1 (CPU000)
// 12'b11_000_000_00_00 : compress_id = 'd18 ;
// 12'b11_010_000_00_00 : compress_id = 'd19 ;
// 12'b11_011_000_00_00 : compress_id = 'd20 ;
// 12'b11_100_000_00_00 : compress_id = 'd21 ;
// 12'b11_101_000_00_00 : compress_id = 'd22 ;
// 12'b11_110_000_00_00 : compress_id = 'd23 ;
// 12'b11_111_000_00_00 : compress_id = 'd24 ;
// // l2m1 (CPU001)
// 12'b11_000_001_00_00 : compress_id = 'd25 ;
// 12'b11_010_001_00_00 : compress_id = 'd26 ;
// 12'b11_011_001_00_00 : compress_id = 'd27 ;
// 12'b11_100_001_00_00 : compress_id = 'd28 ;
// 12'b11_101_001_00_00 : compress_id = 'd29 ;
// 12'b11_110_001_00_00 : compress_id = 'd30 ;
// 12'b11_111_001_00_00 : compress_id = 'd31 ;
// // l2m1 (L2CC)
// 12'b11_000_00101_00 : compress_id = 'd32 ;
// 12'b11_000_01001_00 : compress_id = 'd33 ;
// 12'b11_000_01101_00 : compress_id = 'd34 ;
// 12'b11_000_10011_00 : compress_id = 'd35 ;
// 12'b11_000_10111_00 : compress_id = 'd36 ;
// 12'b11_000_11011_00 : compress_id = 'd37 ;
// 12'b11_000_11111_00 : compress_id = 'd38 ;
// 12'b11_000_00011_00 : compress_id = 'd39 ;
// 12'b11_000_00111_00 : compress_id = 'd40 ;
// 12'b11_000_01011_00 : compress_id = 'd41 ;
// 12'b11_000_01111_00 : compress_id = 'd42 ;
// 12'b11_000_00001_00 : compress_id = 'd43 ;
// // l2m1 (ACP)
// 12'b11_000_10000_00 : compress_id = 'd44 ;
// 12'b11_001_10000_00 : compress_id = 'd45 ;
// 12'b11_010_10000_00 : compress_id = 'd46 ;
// 12'b11_011_10000_00 : compress_id = 'd47 ;
// 12'b11_100_10000_00 : compress_id = 'd48 ;
// 12'b11_101_10000_00 : compress_id = 'd49 ;
// 12'b11_110_10000_00 : compress_id = 'd50 ;
// 12'b11_111_10000_00 : compress_id = 'd51 ;
// default: compress_id = ~0;
// endcase
// end
//endfunction
// Modified as per CR 648393
function [5:0] compress_id;
input [11:0] id;
begin
compress_id[0] = id[7] | (id[4] & id[2]) | (~id[11] & id[2]) | (id[11] & id[0]);
compress_id[1] = id[8] | id[5] | (~id[11] & id[3]);
compress_id[2] = id[9] | (id[6] & id[3] & id[2]) | (~id[11] & id[4]);
compress_id[3] = (id[11] & id[10] & id[4]) | (id[11] & id[10] & id[2]) | (~id[11] & id[10] & ~id[5] & ~id[0]);
compress_id[4] = (id[11] & id[3]) | (id[10] & id[0]) | (id[11] & id[10] & ~id[2] &~id[6]);
compress_id[5] = id[11] & id[10] & ~id[3];
end
endfunction
function [11:0] uncompress_id;
input [5:0] id;
begin
case (id[5:0])
// dmac0
6'b000_010 : uncompress_id = 12'b010000_1000_00 ;
6'b001_000 : uncompress_id = 12'b010000_0000_00 ;
6'b001_001 : uncompress_id = 12'b010000_0001_00 ;
6'b001_010 : uncompress_id = 12'b010000_0010_00 ;
6'b001_011 : uncompress_id = 12'b010000_0011_00 ;
6'b001_100 : uncompress_id = 12'b010000_0100_00 ;
6'b001_101 : uncompress_id = 12'b010000_0101_00 ;
6'b001_110 : uncompress_id = 12'b010000_0110_00 ;
6'b001_111 : uncompress_id = 12'b010000_0111_00 ;
// ioum
6'b010_000 : uncompress_id = 12'b0100000_000_01 ;
6'b010_001 : uncompress_id = 12'b0100000_001_01 ;
6'b010_010 : uncompress_id = 12'b0100000_010_01 ;
6'b010_011 : uncompress_id = 12'b0100000_011_01 ;
6'b010_100 : uncompress_id = 12'b0100000_100_01 ;
6'b010_101 : uncompress_id = 12'b0100000_101_01 ;
// devci
6'b000_000 : uncompress_id = 12'b1000_0000_0000 ;
// dap
6'b000_001 : uncompress_id = 12'b1000_0000_0001 ;
// l2m1 (CPU000)
6'b110_000 : uncompress_id = 12'b11_000_000_00_00 ;
6'b110_010 : uncompress_id = 12'b11_010_000_00_00 ;
6'b110_011 : uncompress_id = 12'b11_011_000_00_00 ;
6'b110_100 : uncompress_id = 12'b11_100_000_00_00 ;
6'b110_101 : uncompress_id = 12'b11_101_000_00_00 ;
6'b110_110 : uncompress_id = 12'b11_110_000_00_00 ;
6'b110_111 : uncompress_id = 12'b11_111_000_00_00 ;
// l2m1 (CPU001)
6'b111_000 : uncompress_id = 12'b11_000_001_00_00 ;
6'b111_010 : uncompress_id = 12'b11_010_001_00_00 ;
6'b111_011 : uncompress_id = 12'b11_011_001_00_00 ;
6'b111_100 : uncompress_id = 12'b11_100_001_00_00 ;
6'b111_101 : uncompress_id = 12'b11_101_001_00_00 ;
6'b111_110 : uncompress_id = 12'b11_110_001_00_00 ;
6'b111_111 : uncompress_id = 12'b11_111_001_00_00 ;
// l2m1 (L2CC)
6'b101_001 : uncompress_id = 12'b11_000_00101_00 ;
6'b101_010 : uncompress_id = 12'b11_000_01001_00 ;
6'b101_011 : uncompress_id = 12'b11_000_01101_00 ;
6'b011_100 : uncompress_id = 12'b11_000_10011_00 ;
6'b011_101 : uncompress_id = 12'b11_000_10111_00 ;
6'b011_110 : uncompress_id = 12'b11_000_11011_00 ;
6'b011_111 : uncompress_id = 12'b11_000_11111_00 ;
6'b011_000 : uncompress_id = 12'b11_000_00011_00 ;
6'b011_001 : uncompress_id = 12'b11_000_00111_00 ;
6'b011_010 : uncompress_id = 12'b11_000_01011_00 ;
6'b011_011 : uncompress_id = 12'b11_000_01111_00 ;
6'b101_000 : uncompress_id = 12'b11_000_00001_00 ;
// l2m1 (ACP)
6'b100_000 : uncompress_id = 12'b11_000_10000_00 ;
6'b100_001 : uncompress_id = 12'b11_001_10000_00 ;
6'b100_010 : uncompress_id = 12'b11_010_10000_00 ;
6'b100_011 : uncompress_id = 12'b11_011_10000_00 ;
6'b100_100 : uncompress_id = 12'b11_100_10000_00 ;
6'b100_101 : uncompress_id = 12'b11_101_10000_00 ;
6'b100_110 : uncompress_id = 12'b11_110_10000_00 ;
6'b100_111 : uncompress_id = 12'b11_111_10000_00 ;
default : uncompress_id = 12'hx ;
endcase
end
endfunction
// Static Remap logic Enablement and Disablement for C_M_AXI0 port
assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL;
assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;
assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID;
assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID;
// Static Remap logic Enablement and Disablement for C_M_AXI1 port
assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL;
assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;
assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID;
assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID;
//// Compress_id and uncompress_id has been removed to address CR 642527
//// AXI interconnect v1.05.a and beyond implements dynamic ID compression/decompression.
// assign M_AXI_GP0_AWID = M_AXI_GP0_AWID_FULL;
// assign M_AXI_GP0_WID = M_AXI_GP0_WID_FULL;
// assign M_AXI_GP0_ARID = M_AXI_GP0_ARID_FULL;
// assign M_AXI_GP0_BID_FULL = M_AXI_GP0_BID;
// assign M_AXI_GP0_RID_FULL = M_AXI_GP0_RID;
//
// assign M_AXI_GP1_AWID = M_AXI_GP1_AWID_FULL;
// assign M_AXI_GP1_WID = M_AXI_GP1_WID_FULL;
// assign M_AXI_GP1_ARID = M_AXI_GP1_ARID_FULL;
// assign M_AXI_GP1_BID_FULL = M_AXI_GP1_BID;
// assign M_AXI_GP1_RID_FULL = M_AXI_GP1_RID;
// Pipeline Stage for ENET0
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_TX_CLK)
begin
ENET0_GMII_TXD <= ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= 1'b0; //ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= 1'b0;//ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= ENET0_GMII_COL;
ENET0_GMII_CRS_i <= ENET0_GMII_CRS;
end
end
else
begin
assign ENET0_GMII_TX_EN_i = 1'b0;
assign ENET0_GMII_TX_ER_i = 1'b0;
assign ENET0_GMII_TXD_i = 1'b0;
always@*
begin
ENET0_GMII_TXD <= 0;
ENET0_GMII_TX_EN <= 0;
ENET0_GMII_TX_ER <= 0;
ENET0_GMII_COL_i <= 0;
ENET0_GMII_CRS_i <= 0;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_RX_CLK)
begin
ENET0_GMII_RXD_i <= ENET0_GMII_RXD;
ENET0_GMII_RX_DV_i <= ENET0_GMII_RX_DV;
ENET0_GMII_RX_ER_i <= ENET0_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET0_GMII_RXD_i <= 0;
ENET0_GMII_RX_DV_i <= 0;
ENET0_GMII_RX_ER_i <= 0;
end
end
endgenerate
// Pipeline Stage for ENET1
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_TX_CLK)
begin
ENET1_GMII_TXD <= ENET1_GMII_TXD_i;
ENET1_GMII_TX_EN <= ENET1_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= ENET1_GMII_TX_ER_i;
ENET1_GMII_COL_i <= ENET1_GMII_COL;
ENET1_GMII_CRS_i <= ENET1_GMII_CRS;
end
end
else
begin
assign ENET1_GMII_TX_EN_i = 1'b0;
assign ENET1_GMII_TX_ER_i = 1'b0;
assign ENET1_GMII_TXD_i = 1'b0;
always@*
begin
ENET1_GMII_TXD <= 0;
ENET1_GMII_TX_EN <= 0;
ENET1_GMII_TX_ER <= 0;
ENET1_GMII_COL_i <= 0;
ENET1_GMII_CRS_i <= 0;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_RX_CLK)
begin
ENET1_GMII_RXD_i <= ENET1_GMII_RXD;
ENET1_GMII_RX_DV_i <= ENET1_GMII_RX_DV;
ENET1_GMII_RX_ER_i <= ENET1_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET1_GMII_RXD_i <= 0;
ENET1_GMII_RX_DV_i <= 0;
ENET1_GMII_RX_ER_i <= 0;
end
end
endgenerate
// Trace buffer instantiated when C_INCLUDE_TRACE_BUFFER is 1.
generate
if (C_EN_EMIO_TRACE == 1) begin
if (C_INCLUDE_TRACE_BUFFER == 0) begin : gen_no_trace_buffer
// Pipeline Stage for Traceport ATID
always @(posedge FTMD_TRACEIN_CLK)
begin
FTMD_TRACEIN_DATA_notracebuf <= FTMD_TRACEIN_DATA;
FTMD_TRACEIN_VALID_notracebuf <= FTMD_TRACEIN_VALID;
FTMD_TRACEIN_ATID_notracebuf <= FTMD_TRACEIN_ATID;
end
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_notracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_notracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_notracebuf;
end else begin : gen_trace_buffer
processing_system7_v5_5_trace_buffer #(.FIFO_SIZE (C_TRACE_BUFFER_FIFO_SIZE),
.USE_TRACE_DATA_EDGE_DETECTOR(USE_TRACE_DATA_EDGE_DETECTOR),
.C_DELAY_CLKS(C_TRACE_BUFFER_CLOCK_DELAY)
)
trace_buffer_i (
.TRACE_CLK(FTMD_TRACEIN_CLK),
.RST(~FCLK_RESET0_N),
.TRACE_VALID_IN(FTMD_TRACEIN_VALID),
.TRACE_DATA_IN(FTMD_TRACEIN_DATA),
.TRACE_ATID_IN(FTMD_TRACEIN_ATID),
.TRACE_ATID_OUT(FTMD_TRACEIN_ATID_tracebuf),
.TRACE_VALID_OUT(FTMD_TRACEIN_VALID_tracebuf),
.TRACE_DATA_OUT(FTMD_TRACEIN_DATA_tracebuf)
);
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_tracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_tracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_tracebuf;
end
end
else
begin
assign FTMD_TRACEIN_DATA_i = 1'b0;
assign FTMD_TRACEIN_VALID_i = 1'b0;
assign FTMD_TRACEIN_ATID_i = 1'b0;
end
endgenerate
// ID Width Control on AXI Slave ports
// S_AXI_GP0
function [5:0] id_in_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_in;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_in_gp0 = {5'b0, axi_id_gp0_in};
2: id_in_gp0 = {4'b0, axi_id_gp0_in};
3: id_in_gp0 = {3'b0, axi_id_gp0_in};
4: id_in_gp0 = {2'b0, axi_id_gp0_in};
5: id_in_gp0 = {1'b0, axi_id_gp0_in};
6: id_in_gp0 = axi_id_gp0_in;
default : id_in_gp0 = axi_id_gp0_in;
endcase
end
endfunction
assign S_AXI_GP0_ARID_in = id_in_gp0(S_AXI_GP0_ARID);
assign S_AXI_GP0_AWID_in = id_in_gp0(S_AXI_GP0_AWID);
assign S_AXI_GP0_WID_in = id_in_gp0(S_AXI_GP0_WID);
function [5:0] id_out_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_out;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_out_gp0 = axi_id_gp0_out[0];
2: id_out_gp0 = axi_id_gp0_out[1:0];
3: id_out_gp0 = axi_id_gp0_out[2:0];
4: id_out_gp0 = axi_id_gp0_out[3:0];
5: id_out_gp0 = axi_id_gp0_out[4:0];
6: id_out_gp0 = axi_id_gp0_out;
default : id_out_gp0 = axi_id_gp0_out;
endcase
end
endfunction
assign S_AXI_GP0_BID = id_out_gp0(S_AXI_GP0_BID_out);
assign S_AXI_GP0_RID = id_out_gp0(S_AXI_GP0_RID_out);
// S_AXI_GP1
function [5:0] id_in_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_in;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_in_gp1 = {5'b0, axi_id_gp1_in};
2: id_in_gp1 = {4'b0, axi_id_gp1_in};
3: id_in_gp1 = {3'b0, axi_id_gp1_in};
4: id_in_gp1 = {2'b0, axi_id_gp1_in};
5: id_in_gp1 = {1'b0, axi_id_gp1_in};
6: id_in_gp1 = axi_id_gp1_in;
default : id_in_gp1 = axi_id_gp1_in;
endcase
end
endfunction
assign S_AXI_GP1_ARID_in = id_in_gp1(S_AXI_GP1_ARID);
assign S_AXI_GP1_AWID_in = id_in_gp1(S_AXI_GP1_AWID);
assign S_AXI_GP1_WID_in = id_in_gp1(S_AXI_GP1_WID);
function [5:0] id_out_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_out;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_out_gp1 = axi_id_gp1_out[0];
2: id_out_gp1 = axi_id_gp1_out[1:0];
3: id_out_gp1 = axi_id_gp1_out[2:0];
4: id_out_gp1 = axi_id_gp1_out[3:0];
5: id_out_gp1 = axi_id_gp1_out[4:0];
6: id_out_gp1 = axi_id_gp1_out;
default : id_out_gp1 = axi_id_gp1_out;
endcase
end
endfunction
assign S_AXI_GP1_BID = id_out_gp1(S_AXI_GP1_BID_out);
assign S_AXI_GP1_RID = id_out_gp1(S_AXI_GP1_RID_out);
// S_AXI_HP0
function [5:0] id_in_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_in;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_in_hp0 = {5'b0, axi_id_hp0_in};
2: id_in_hp0 = {4'b0, axi_id_hp0_in};
3: id_in_hp0 = {3'b0, axi_id_hp0_in};
4: id_in_hp0 = {2'b0, axi_id_hp0_in};
5: id_in_hp0 = {1'b0, axi_id_hp0_in};
6: id_in_hp0 = axi_id_hp0_in;
default : id_in_hp0 = axi_id_hp0_in;
endcase
end
endfunction
assign S_AXI_HP0_ARID_in = id_in_hp0(S_AXI_HP0_ARID);
assign S_AXI_HP0_AWID_in = id_in_hp0(S_AXI_HP0_AWID);
assign S_AXI_HP0_WID_in = id_in_hp0(S_AXI_HP0_WID);
function [5:0] id_out_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_out;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_out_hp0 = axi_id_hp0_out[0];
2: id_out_hp0 = axi_id_hp0_out[1:0];
3: id_out_hp0 = axi_id_hp0_out[2:0];
4: id_out_hp0 = axi_id_hp0_out[3:0];
5: id_out_hp0 = axi_id_hp0_out[4:0];
6: id_out_hp0 = axi_id_hp0_out;
default : id_out_hp0 = axi_id_hp0_out;
endcase
end
endfunction
assign S_AXI_HP0_BID = id_out_hp0(S_AXI_HP0_BID_out);
assign S_AXI_HP0_RID = id_out_hp0(S_AXI_HP0_RID_out);
assign S_AXI_HP0_WDATA_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WDATA : {32'b0,S_AXI_HP0_WDATA};
assign S_AXI_HP0_WSTRB_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WSTRB : {4'b0,S_AXI_HP0_WSTRB};
assign S_AXI_HP0_RDATA = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_RDATA_out : S_AXI_HP0_RDATA_out[31:0];
// S_AXI_HP1
function [5:0] id_in_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_in;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_in_hp1 = {5'b0, axi_id_hp1_in};
2: id_in_hp1 = {4'b0, axi_id_hp1_in};
3: id_in_hp1 = {3'b0, axi_id_hp1_in};
4: id_in_hp1 = {2'b0, axi_id_hp1_in};
5: id_in_hp1 = {1'b0, axi_id_hp1_in};
6: id_in_hp1 = axi_id_hp1_in;
default : id_in_hp1 = axi_id_hp1_in;
endcase
end
endfunction
assign S_AXI_HP1_ARID_in = id_in_hp1(S_AXI_HP1_ARID);
assign S_AXI_HP1_AWID_in = id_in_hp1(S_AXI_HP1_AWID);
assign S_AXI_HP1_WID_in = id_in_hp1(S_AXI_HP1_WID);
function [5:0] id_out_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_out;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_out_hp1 = axi_id_hp1_out[0];
2: id_out_hp1 = axi_id_hp1_out[1:0];
3: id_out_hp1 = axi_id_hp1_out[2:0];
4: id_out_hp1 = axi_id_hp1_out[3:0];
5: id_out_hp1 = axi_id_hp1_out[4:0];
6: id_out_hp1 = axi_id_hp1_out;
default : id_out_hp1 = axi_id_hp1_out;
endcase
end
endfunction
assign S_AXI_HP1_BID = id_out_hp1(S_AXI_HP1_BID_out);
assign S_AXI_HP1_RID = id_out_hp1(S_AXI_HP1_RID_out);
assign S_AXI_HP1_WDATA_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WDATA : {32'b0,S_AXI_HP1_WDATA};
assign S_AXI_HP1_WSTRB_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WSTRB : {4'b0,S_AXI_HP1_WSTRB};
assign S_AXI_HP1_RDATA = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_RDATA_out : S_AXI_HP1_RDATA_out[31:0];
// S_AXI_HP2
function [5:0] id_in_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_in;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_in_hp2 = {5'b0, axi_id_hp2_in};
2: id_in_hp2 = {4'b0, axi_id_hp2_in};
3: id_in_hp2 = {3'b0, axi_id_hp2_in};
4: id_in_hp2 = {2'b0, axi_id_hp2_in};
5: id_in_hp2 = {1'b0, axi_id_hp2_in};
6: id_in_hp2 = axi_id_hp2_in;
default : id_in_hp2 = axi_id_hp2_in;
endcase
end
endfunction
assign S_AXI_HP2_ARID_in = id_in_hp2(S_AXI_HP2_ARID);
assign S_AXI_HP2_AWID_in = id_in_hp2(S_AXI_HP2_AWID);
assign S_AXI_HP2_WID_in = id_in_hp2(S_AXI_HP2_WID);
function [5:0] id_out_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_out;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_out_hp2 = axi_id_hp2_out[0];
2: id_out_hp2 = axi_id_hp2_out[1:0];
3: id_out_hp2 = axi_id_hp2_out[2:0];
4: id_out_hp2 = axi_id_hp2_out[3:0];
5: id_out_hp2 = axi_id_hp2_out[4:0];
6: id_out_hp2 = axi_id_hp2_out;
default : id_out_hp2 = axi_id_hp2_out;
endcase
end
endfunction
assign S_AXI_HP2_BID = id_out_hp2(S_AXI_HP2_BID_out);
assign S_AXI_HP2_RID = id_out_hp2(S_AXI_HP2_RID_out);
assign S_AXI_HP2_WDATA_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WDATA : {32'b0,S_AXI_HP2_WDATA};
assign S_AXI_HP2_WSTRB_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WSTRB : {4'b0,S_AXI_HP2_WSTRB};
assign S_AXI_HP2_RDATA = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_RDATA_out : S_AXI_HP2_RDATA_out[31:0];
// S_AXI_HP3
function [5:0] id_in_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_in;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_in_hp3 = {5'b0, axi_id_hp3_in};
2: id_in_hp3 = {4'b0, axi_id_hp3_in};
3: id_in_hp3 = {3'b0, axi_id_hp3_in};
4: id_in_hp3 = {2'b0, axi_id_hp3_in};
5: id_in_hp3 = {1'b0, axi_id_hp3_in};
6: id_in_hp3 = axi_id_hp3_in;
default : id_in_hp3 = axi_id_hp3_in;
endcase
end
endfunction
assign S_AXI_HP3_ARID_in = id_in_hp3(S_AXI_HP3_ARID);
assign S_AXI_HP3_AWID_in = id_in_hp3(S_AXI_HP3_AWID);
assign S_AXI_HP3_WID_in = id_in_hp3(S_AXI_HP3_WID);
function [5:0] id_out_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_out;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_out_hp3 = axi_id_hp3_out[0];
2: id_out_hp3 = axi_id_hp3_out[1:0];
3: id_out_hp3 = axi_id_hp3_out[2:0];
4: id_out_hp3 = axi_id_hp3_out[3:0];
5: id_out_hp3 = axi_id_hp3_out[4:0];
6: id_out_hp3 = axi_id_hp3_out;
default : id_out_hp3 = axi_id_hp3_out;
endcase
end
endfunction
assign S_AXI_HP3_BID = id_out_hp3(S_AXI_HP3_BID_out);
assign S_AXI_HP3_RID = id_out_hp3(S_AXI_HP3_RID_out);
assign S_AXI_HP3_WDATA_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WDATA : {32'b0,S_AXI_HP3_WDATA};
assign S_AXI_HP3_WSTRB_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WSTRB : {4'b0,S_AXI_HP3_WSTRB};
assign S_AXI_HP3_RDATA = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_RDATA_out : S_AXI_HP3_RDATA_out[31:0];
// S_AXI_ACP
function [2:0] id_in_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_in;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_in_acp = {2'b0, axi_id_acp_in};
2: id_in_acp = {1'b0, axi_id_acp_in};
3: id_in_acp = axi_id_acp_in;
default : id_in_acp = axi_id_acp_in;
endcase
end
endfunction
assign S_AXI_ACP_ARID_in = id_in_acp(SAXIACPARID_W);
assign S_AXI_ACP_AWID_in = id_in_acp(SAXIACPAWID_W);
assign S_AXI_ACP_WID_in = id_in_acp(SAXIACPWID_W);
function [2:0] id_out_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_out;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_out_acp = axi_id_acp_out[0];
2: id_out_acp = axi_id_acp_out[1:0];
3: id_out_acp = axi_id_acp_out;
default : id_out_acp = axi_id_acp_out;
endcase
end
endfunction
assign SAXIACPBID_W = id_out_acp(S_AXI_ACP_BID_out);
assign SAXIACPRID_W = id_out_acp(S_AXI_ACP_RID_out);
// FMIO Tristate Inversion logic
//FMIO I2C0
assign I2C0_SDA_T = ~ I2C0_SDA_T_n;
assign I2C0_SCL_T = ~ I2C0_SCL_T_n;
//FMIO I2C1
assign I2C1_SDA_T = ~ I2C1_SDA_T_n;
assign I2C1_SCL_T = ~ I2C1_SCL_T_n;
//FMIO SPI0
assign SPI0_SCLK_T = ~ SPI0_SCLK_T_n;
assign SPI0_MOSI_T = ~ SPI0_MOSI_T_n;
assign SPI0_MISO_T = ~ SPI0_MISO_T_n;
assign SPI0_SS_T = ~ SPI0_SS_T_n;
//FMIO SPI1
assign SPI1_SCLK_T = ~ SPI1_SCLK_T_n;
assign SPI1_MOSI_T = ~ SPI1_MOSI_T_n;
assign SPI1_MISO_T = ~ SPI1_MISO_T_n;
assign SPI1_SS_T = ~ SPI1_SS_T_n;
// EMIO GEM0 MDIO
assign ENET0_MDIO_T = ~ ENET0_MDIO_T_n;
// EMIO GEM1 MDIO
assign ENET1_MDIO_T = ~ ENET1_MDIO_T_n;
// EMIO GPIO
assign GPIO_T = ~ GPIO_T_n;
// EMIO GPIO Width Control
function [63:0] gpio_width_adjust_in;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_in;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_in = {63'b0, gpio_in};
2: gpio_width_adjust_in = {62'b0, gpio_in};
3: gpio_width_adjust_in = {61'b0, gpio_in};
4: gpio_width_adjust_in = {60'b0, gpio_in};
5: gpio_width_adjust_in = {59'b0, gpio_in};
6: gpio_width_adjust_in = {58'b0, gpio_in};
7: gpio_width_adjust_in = {57'b0, gpio_in};
8: gpio_width_adjust_in = {56'b0, gpio_in};
9: gpio_width_adjust_in = {55'b0, gpio_in};
10: gpio_width_adjust_in = {54'b0, gpio_in};
11: gpio_width_adjust_in = {53'b0, gpio_in};
12: gpio_width_adjust_in = {52'b0, gpio_in};
13: gpio_width_adjust_in = {51'b0, gpio_in};
14: gpio_width_adjust_in = {50'b0, gpio_in};
15: gpio_width_adjust_in = {49'b0, gpio_in};
16: gpio_width_adjust_in = {48'b0, gpio_in};
17: gpio_width_adjust_in = {47'b0, gpio_in};
18: gpio_width_adjust_in = {46'b0, gpio_in};
19: gpio_width_adjust_in = {45'b0, gpio_in};
20: gpio_width_adjust_in = {44'b0, gpio_in};
21: gpio_width_adjust_in = {43'b0, gpio_in};
22: gpio_width_adjust_in = {42'b0, gpio_in};
23: gpio_width_adjust_in = {41'b0, gpio_in};
24: gpio_width_adjust_in = {40'b0, gpio_in};
25: gpio_width_adjust_in = {39'b0, gpio_in};
26: gpio_width_adjust_in = {38'b0, gpio_in};
27: gpio_width_adjust_in = {37'b0, gpio_in};
28: gpio_width_adjust_in = {36'b0, gpio_in};
29: gpio_width_adjust_in = {35'b0, gpio_in};
30: gpio_width_adjust_in = {34'b0, gpio_in};
31: gpio_width_adjust_in = {33'b0, gpio_in};
32: gpio_width_adjust_in = {32'b0, gpio_in};
33: gpio_width_adjust_in = {31'b0, gpio_in};
34: gpio_width_adjust_in = {30'b0, gpio_in};
35: gpio_width_adjust_in = {29'b0, gpio_in};
36: gpio_width_adjust_in = {28'b0, gpio_in};
37: gpio_width_adjust_in = {27'b0, gpio_in};
38: gpio_width_adjust_in = {26'b0, gpio_in};
39: gpio_width_adjust_in = {25'b0, gpio_in};
40: gpio_width_adjust_in = {24'b0, gpio_in};
41: gpio_width_adjust_in = {23'b0, gpio_in};
42: gpio_width_adjust_in = {22'b0, gpio_in};
43: gpio_width_adjust_in = {21'b0, gpio_in};
44: gpio_width_adjust_in = {20'b0, gpio_in};
45: gpio_width_adjust_in = {19'b0, gpio_in};
46: gpio_width_adjust_in = {18'b0, gpio_in};
47: gpio_width_adjust_in = {17'b0, gpio_in};
48: gpio_width_adjust_in = {16'b0, gpio_in};
49: gpio_width_adjust_in = {15'b0, gpio_in};
50: gpio_width_adjust_in = {14'b0, gpio_in};
51: gpio_width_adjust_in = {13'b0, gpio_in};
52: gpio_width_adjust_in = {12'b0, gpio_in};
53: gpio_width_adjust_in = {11'b0, gpio_in};
54: gpio_width_adjust_in = {10'b0, gpio_in};
55: gpio_width_adjust_in = {9'b0, gpio_in};
56: gpio_width_adjust_in = {8'b0, gpio_in};
57: gpio_width_adjust_in = {7'b0, gpio_in};
58: gpio_width_adjust_in = {6'b0, gpio_in};
59: gpio_width_adjust_in = {5'b0, gpio_in};
60: gpio_width_adjust_in = {4'b0, gpio_in};
61: gpio_width_adjust_in = {3'b0, gpio_in};
62: gpio_width_adjust_in = {2'b0, gpio_in};
63: gpio_width_adjust_in = {1'b0, gpio_in};
64: gpio_width_adjust_in = gpio_in;
default : gpio_width_adjust_in = gpio_in;
endcase
end
endfunction
assign gpio_in63_0 = gpio_width_adjust_in(GPIO_I);
function [63:0] gpio_width_adjust_out;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_o;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_out = gpio_o[0];
2: gpio_width_adjust_out = gpio_o[1:0];
3: gpio_width_adjust_out = gpio_o[2:0];
4: gpio_width_adjust_out = gpio_o[3:0];
5: gpio_width_adjust_out = gpio_o[4:0];
6: gpio_width_adjust_out = gpio_o[5:0];
7: gpio_width_adjust_out = gpio_o[6:0];
8: gpio_width_adjust_out = gpio_o[7:0];
9: gpio_width_adjust_out = gpio_o[8:0];
10: gpio_width_adjust_out = gpio_o[9:0];
11: gpio_width_adjust_out = gpio_o[10:0];
12: gpio_width_adjust_out = gpio_o[11:0];
13: gpio_width_adjust_out = gpio_o[12:0];
14: gpio_width_adjust_out = gpio_o[13:0];
15: gpio_width_adjust_out = gpio_o[14:0];
16: gpio_width_adjust_out = gpio_o[15:0];
17: gpio_width_adjust_out = gpio_o[16:0];
18: gpio_width_adjust_out = gpio_o[17:0];
19: gpio_width_adjust_out = gpio_o[18:0];
20: gpio_width_adjust_out = gpio_o[19:0];
21: gpio_width_adjust_out = gpio_o[20:0];
22: gpio_width_adjust_out = gpio_o[21:0];
23: gpio_width_adjust_out = gpio_o[22:0];
24: gpio_width_adjust_out = gpio_o[23:0];
25: gpio_width_adjust_out = gpio_o[24:0];
26: gpio_width_adjust_out = gpio_o[25:0];
27: gpio_width_adjust_out = gpio_o[26:0];
28: gpio_width_adjust_out = gpio_o[27:0];
29: gpio_width_adjust_out = gpio_o[28:0];
30: gpio_width_adjust_out = gpio_o[29:0];
31: gpio_width_adjust_out = gpio_o[30:0];
32: gpio_width_adjust_out = gpio_o[31:0];
33: gpio_width_adjust_out = gpio_o[32:0];
34: gpio_width_adjust_out = gpio_o[33:0];
35: gpio_width_adjust_out = gpio_o[34:0];
36: gpio_width_adjust_out = gpio_o[35:0];
37: gpio_width_adjust_out = gpio_o[36:0];
38: gpio_width_adjust_out = gpio_o[37:0];
39: gpio_width_adjust_out = gpio_o[38:0];
40: gpio_width_adjust_out = gpio_o[39:0];
41: gpio_width_adjust_out = gpio_o[40:0];
42: gpio_width_adjust_out = gpio_o[41:0];
43: gpio_width_adjust_out = gpio_o[42:0];
44: gpio_width_adjust_out = gpio_o[43:0];
45: gpio_width_adjust_out = gpio_o[44:0];
46: gpio_width_adjust_out = gpio_o[45:0];
47: gpio_width_adjust_out = gpio_o[46:0];
48: gpio_width_adjust_out = gpio_o[47:0];
49: gpio_width_adjust_out = gpio_o[48:0];
50: gpio_width_adjust_out = gpio_o[49:0];
51: gpio_width_adjust_out = gpio_o[50:0];
52: gpio_width_adjust_out = gpio_o[51:0];
53: gpio_width_adjust_out = gpio_o[52:0];
54: gpio_width_adjust_out = gpio_o[53:0];
55: gpio_width_adjust_out = gpio_o[54:0];
56: gpio_width_adjust_out = gpio_o[55:0];
57: gpio_width_adjust_out = gpio_o[56:0];
58: gpio_width_adjust_out = gpio_o[57:0];
59: gpio_width_adjust_out = gpio_o[58:0];
60: gpio_width_adjust_out = gpio_o[59:0];
61: gpio_width_adjust_out = gpio_o[60:0];
62: gpio_width_adjust_out = gpio_o[61:0];
63: gpio_width_adjust_out = gpio_o[62:0];
64: gpio_width_adjust_out = gpio_o;
default : gpio_width_adjust_out = gpio_o;
endcase
end
endfunction
assign GPIO_O[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out);
assign GPIO_T_n[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out_t_n);
// Adding OBUFT to JTAG out port
generate
if ( C_EN_EMIO_PJTAG == 1 ) begin : PJTAG_OBUFT_TRUE
OBUFT jtag_obuft_inst (
.O(PJTAG_TDO),
.I(PJTAG_TDO_O),
.T(PJTAG_TDO_T)
);
end
else
begin
assign PJTAG_TDO = 1'b0;
end
endgenerate
// -------
// EMIO PJTAG
assign PJTAG_TDO_T = ~ PJTAG_TDO_T_n;
// EMIO SDIO0 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO0_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO0_CMD_T_n) : (~ SDIO0_CMD_T_n);
assign SDIO0_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO0_DATA_T_n[3:0]) : (~ SDIO0_DATA_T_n[3:0]);
// EMIO SDIO1 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO1_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO1_CMD_T_n) : (~ SDIO1_CMD_T_n);
assign SDIO1_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO1_DATA_T_n[3:0]) : (~ SDIO1_DATA_T_n[3:0]);
// FCLK_CLK optional clock buffers
generate
if (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") begin : buffer_fclk_clk_0
BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0]));
end
if (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") begin : buffer_fclk_clk_1
BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1]));
end
if (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") begin : buffer_fclk_clk_2
BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2]));
end
if (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") begin : buffer_fclk_clk_3
BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3]));
end
endgenerate
assign FCLK_CLK0_temp = (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") ? FCLK_CLK_buffered[0] : FCLK_CLK_unbuffered[0];
assign FCLK_CLK1 = (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") ? FCLK_CLK_buffered[1] : FCLK_CLK_unbuffered[1];
assign FCLK_CLK2 = (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") ? FCLK_CLK_buffered[2] : FCLK_CLK_unbuffered[2];
assign FCLK_CLK3 = (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") ? FCLK_CLK_buffered[3] : FCLK_CLK_unbuffered[3];
assign FCLK_CLK0 = FCLK_CLK0_temp;
// Adding BIBUF for fixed IO Ports and IBUF for fixed Input Ports
BIBUF DDR_CAS_n_BIBUF (.PAD(DDR_CAS_n), .IO(buffered_DDR_CAS_n));
BIBUF DDR_CKE_BIBUF (.PAD(DDR_CKE), .IO(buffered_DDR_CKE));
BIBUF DDR_Clk_n_BIBUF (.PAD(DDR_Clk_n), .IO(buffered_DDR_Clk_n));
BIBUF DDR_Clk_BIBUF (.PAD(DDR_Clk), .IO(buffered_DDR_Clk));
BIBUF DDR_CS_n_BIBUF (.PAD(DDR_CS_n), .IO(buffered_DDR_CS_n));
BIBUF DDR_DRSTB_BIBUF (.PAD(DDR_DRSTB), .IO(buffered_DDR_DRSTB));
BIBUF DDR_ODT_BIBUF (.PAD(DDR_ODT), .IO(buffered_DDR_ODT));
BIBUF DDR_RAS_n_BIBUF (.PAD(DDR_RAS_n), .IO(buffered_DDR_RAS_n));
BIBUF DDR_WEB_BIBUF (.PAD(DDR_WEB), .IO(buffered_DDR_WEB));
BIBUF DDR_VRN_BIBUF (.PAD(DDR_VRN), .IO(buffered_DDR_VRN));
BIBUF DDR_VRP_BIBUF (.PAD(DDR_VRP), .IO(buffered_DDR_VRP));
BIBUF PS_SRSTB_BIBUF (.PAD(PS_SRSTB), .IO(buffered_PS_SRSTB));
BIBUF PS_CLK_BIBUF (.PAD(PS_CLK), .IO(buffered_PS_CLK));
BIBUF PS_PORB_BIBUF (.PAD(PS_PORB), .IO(buffered_PS_PORB));
genvar i;
generate
for (i=0; i < C_MIO_PRIMITIVE; i=i+1) begin
BIBUF MIO_BIBUF (.PAD(MIO[i]), .IO(buffered_MIO[i]));
end
endgenerate
generate
for (i=0; i < 3; i=i+1) begin
BIBUF DDR_BankAddr_BIBUF (.PAD(DDR_BankAddr[i]), .IO(buffered_DDR_BankAddr[i]));
end
endgenerate
generate
for (i=0; i < 15; i=i+1) begin
BIBUF DDR_Addr_BIBUF (.PAD(DDR_Addr[i]), .IO(buffered_DDR_Addr[i]));
end
endgenerate
generate
for (i=0; i < C_DM_WIDTH; i=i+1) begin
BIBUF DDR_DM_BIBUF (.PAD(DDR_DM[i]), .IO(buffered_DDR_DM[i]));
end
endgenerate
generate
for (i=0; i < C_DQ_WIDTH; i=i+1) begin
BIBUF DDR_DQ_BIBUF (.PAD(DDR_DQ[i]), .IO(buffered_DDR_DQ[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_n_BIBUF (.PAD(DDR_DQS_n[i]), .IO(buffered_DDR_DQS_n[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_BIBUF (.PAD(DDR_DQS[i]), .IO(buffered_DDR_DQS[i]));
end
endgenerate
// Connect FCLK in case of disable the AXI port for non Secure Transaction
//Start
wire S_AXI_HP0_ACLK_temp;
wire S_AXI_HP1_ACLK_temp;
wire S_AXI_HP2_ACLK_temp;
wire S_AXI_HP3_ACLK_temp;
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP0 == 0) begin
assign S_AXI_HP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP0_ACLK_temp = S_AXI_HP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP1 == 0) begin
assign S_AXI_HP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP1_ACLK_temp = S_AXI_HP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP2 == 0) begin
assign S_AXI_HP2_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP2_ACLK_temp = S_AXI_HP2_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP3 == 0) begin
assign S_AXI_HP3_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP3_ACLK_temp = S_AXI_HP2_ACLK;
end
endgenerate
//Start
wire M_AXI_GP0_ACLK_temp;
wire M_AXI_GP1_ACLK_temp;
wire S_AXI_GP0_ACLK_temp;
wire S_AXI_GP1_ACLK_temp;
wire S_AXI_ACP_ACLK_temp;
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP0 == 0) begin
assign M_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP0_ACLK_temp = M_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP1 == 0) begin
assign M_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP1_ACLK_temp = M_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP0 == 0) begin
assign S_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP0_ACLK_temp = S_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP1 == 0) begin
assign S_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP1_ACLK_temp = S_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_ACP == 0) begin
assign S_AXI_ACP_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_ACP_ACLK_temp = S_AXI_ACP_ACLK;
end
endgenerate
//END
//====================
//PSS TOP
//====================
generate
if (C_PACKAGE_NAME == "clg225" ) begin
wire [21:0] dummy;
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (), //(ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO ({buffered_MIO[31:30],dummy[21:20],buffered_MIO[29:28],dummy[19:12],buffered_MIO[27:16],dummy[11:0],buffered_MIO[15:0]}),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
else begin
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (), // (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO (buffered_MIO),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
endgenerate
// Generating the AxUSER Values locally when the C_USE_DEFAULT_ACP_USER_VAL is enabled.
// Otherwise a master connected to the ACP port will drive the AxUSER Ports
assign param_aruser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_ARUSER_VAL : S_AXI_ACP_ARUSER;
assign param_awuser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_AWUSER_VAL : S_AXI_ACP_AWUSER;
assign SAXIACPARADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARADDR : S_AXI_ACP_ARADDR;
assign SAXIACPARBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARBURST : S_AXI_ACP_ARBURST;
assign SAXIACPARCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARCACHE : S_AXI_ACP_ARCACHE;
assign SAXIACPARLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLEN : S_AXI_ACP_ARLEN;
assign SAXIACPARLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLOCK : S_AXI_ACP_ARLOCK;
assign SAXIACPARPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARPROT : S_AXI_ACP_ARPROT;
assign SAXIACPARSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARSIZE : S_AXI_ACP_ARSIZE;
//assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : S_AXI_ACP_ARUSER;
assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : param_aruser;
assign SAXIACPARVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARVALID : S_AXI_ACP_ARVALID ;
assign SAXIACPAWADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWADDR : S_AXI_ACP_AWADDR;
assign SAXIACPAWBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWBURST : S_AXI_ACP_AWBURST;
assign SAXIACPAWCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWCACHE : S_AXI_ACP_AWCACHE;
assign SAXIACPAWLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLEN : S_AXI_ACP_AWLEN;
assign SAXIACPAWLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLOCK : S_AXI_ACP_AWLOCK;
assign SAXIACPAWPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWPROT : S_AXI_ACP_AWPROT;
assign SAXIACPAWSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWSIZE : S_AXI_ACP_AWSIZE;
//assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : S_AXI_ACP_AWUSER;
assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : param_awuser;
assign SAXIACPAWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWVALID : S_AXI_ACP_AWVALID;
assign SAXIACPBREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_BREADY : S_AXI_ACP_BREADY;
assign SAXIACPRREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_RREADY : S_AXI_ACP_RREADY;
assign SAXIACPWDATA_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WDATA : S_AXI_ACP_WDATA;
assign SAXIACPWLAST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WLAST : S_AXI_ACP_WLAST;
assign SAXIACPWSTRB_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WSTRB : S_AXI_ACP_WSTRB;
assign SAXIACPWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WVALID : S_AXI_ACP_WVALID;
assign SAXIACPARID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARID : S_AXI_ACP_ARID;
assign SAXIACPAWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWID : S_AXI_ACP_AWID;
assign SAXIACPWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WID : S_AXI_ACP_WID;
generate
if (C_INCLUDE_ACP_TRANS_CHECK == 0) begin : gen_no_atc
assign S_AXI_ACP_AWREADY = SAXIACPAWREADY_W;
assign S_AXI_ACP_WREADY = SAXIACPWREADY_W;
assign S_AXI_ACP_BID = SAXIACPBID_W;
assign S_AXI_ACP_BRESP = SAXIACPBRESP_W;
assign S_AXI_ACP_BVALID = SAXIACPBVALID_W;
assign S_AXI_ACP_RDATA = SAXIACPRDATA_W;
assign S_AXI_ACP_RID = SAXIACPRID_W;
assign S_AXI_ACP_RLAST = SAXIACPRLAST_W;
assign S_AXI_ACP_RRESP = SAXIACPRRESP_W;
assign S_AXI_ACP_RVALID = SAXIACPRVALID_W;
assign S_AXI_ACP_ARREADY = SAXIACPARREADY_W;
end else begin : gen_atc
processing_system7_v5_5_atc #(
.C_AXI_ID_WIDTH (C_S_AXI_ACP_ID_WIDTH),
.C_AXI_AWUSER_WIDTH (5),
.C_AXI_ARUSER_WIDTH (5)
)
atc_i (
// Global Signals
.ACLK (S_AXI_ACP_ACLK_temp),
.ARESETN (S_AXI_ACP_ARESETN),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_ACP_AWID),
.S_AXI_AWADDR (S_AXI_ACP_AWADDR),
.S_AXI_AWLEN (S_AXI_ACP_AWLEN),
.S_AXI_AWSIZE (S_AXI_ACP_AWSIZE),
.S_AXI_AWBURST (S_AXI_ACP_AWBURST),
.S_AXI_AWLOCK (S_AXI_ACP_AWLOCK),
.S_AXI_AWCACHE (S_AXI_ACP_AWCACHE),
.S_AXI_AWPROT (S_AXI_ACP_AWPROT),
//.S_AXI_AWUSER (S_AXI_ACP_AWUSER),
.S_AXI_AWUSER (param_awuser),
.S_AXI_AWVALID (S_AXI_ACP_AWVALID),
.S_AXI_AWREADY (S_AXI_ACP_AWREADY),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_ACP_WID),
.S_AXI_WDATA (S_AXI_ACP_WDATA),
.S_AXI_WSTRB (S_AXI_ACP_WSTRB),
.S_AXI_WLAST (S_AXI_ACP_WLAST),
.S_AXI_WUSER (),
.S_AXI_WVALID (S_AXI_ACP_WVALID),
.S_AXI_WREADY (S_AXI_ACP_WREADY),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_ACP_BID),
.S_AXI_BRESP (S_AXI_ACP_BRESP),
.S_AXI_BUSER (),
.S_AXI_BVALID (S_AXI_ACP_BVALID),
.S_AXI_BREADY (S_AXI_ACP_BREADY),
// Slave Interface Read Address Ports
.S_AXI_ARID (S_AXI_ACP_ARID),
.S_AXI_ARADDR (S_AXI_ACP_ARADDR),
.S_AXI_ARLEN (S_AXI_ACP_ARLEN),
.S_AXI_ARSIZE (S_AXI_ACP_ARSIZE),
.S_AXI_ARBURST (S_AXI_ACP_ARBURST),
.S_AXI_ARLOCK (S_AXI_ACP_ARLOCK),
.S_AXI_ARCACHE (S_AXI_ACP_ARCACHE),
.S_AXI_ARPROT (S_AXI_ACP_ARPROT),
//.S_AXI_ARUSER (S_AXI_ACP_ARUSER),
.S_AXI_ARUSER (param_aruser),
.S_AXI_ARVALID (S_AXI_ACP_ARVALID),
.S_AXI_ARREADY (S_AXI_ACP_ARREADY),
// Slave Interface Read Data Ports
.S_AXI_RID (S_AXI_ACP_RID),
.S_AXI_RDATA (S_AXI_ACP_RDATA),
.S_AXI_RRESP (S_AXI_ACP_RRESP),
.S_AXI_RLAST (S_AXI_ACP_RLAST),
.S_AXI_RUSER (),
.S_AXI_RVALID (S_AXI_ACP_RVALID),
.S_AXI_RREADY (S_AXI_ACP_RREADY),
// Slave Interface Write Address Ports
.M_AXI_AWID (S_AXI_ATC_AWID),
.M_AXI_AWADDR (S_AXI_ATC_AWADDR),
.M_AXI_AWLEN (S_AXI_ATC_AWLEN),
.M_AXI_AWSIZE (S_AXI_ATC_AWSIZE),
.M_AXI_AWBURST (S_AXI_ATC_AWBURST),
.M_AXI_AWLOCK (S_AXI_ATC_AWLOCK),
.M_AXI_AWCACHE (S_AXI_ATC_AWCACHE),
.M_AXI_AWPROT (S_AXI_ATC_AWPROT),
.M_AXI_AWUSER (S_AXI_ATC_AWUSER),
.M_AXI_AWVALID (S_AXI_ATC_AWVALID),
.M_AXI_AWREADY (SAXIACPAWREADY_W),
// Slave Interface Write Data Ports
.M_AXI_WID (S_AXI_ATC_WID),
.M_AXI_WDATA (S_AXI_ATC_WDATA),
.M_AXI_WSTRB (S_AXI_ATC_WSTRB),
.M_AXI_WLAST (S_AXI_ATC_WLAST),
.M_AXI_WUSER (),
.M_AXI_WVALID (S_AXI_ATC_WVALID),
.M_AXI_WREADY (SAXIACPWREADY_W),
// Slave Interface Write Response Ports
.M_AXI_BID (SAXIACPBID_W),
.M_AXI_BRESP (SAXIACPBRESP_W),
.M_AXI_BUSER (),
.M_AXI_BVALID (SAXIACPBVALID_W),
.M_AXI_BREADY (S_AXI_ATC_BREADY),
// Slave Interface Read Address Ports
.M_AXI_ARID (S_AXI_ATC_ARID),
.M_AXI_ARADDR (S_AXI_ATC_ARADDR),
.M_AXI_ARLEN (S_AXI_ATC_ARLEN),
.M_AXI_ARSIZE (S_AXI_ATC_ARSIZE),
.M_AXI_ARBURST (S_AXI_ATC_ARBURST),
.M_AXI_ARLOCK (S_AXI_ATC_ARLOCK),
.M_AXI_ARCACHE (S_AXI_ATC_ARCACHE),
.M_AXI_ARPROT (S_AXI_ATC_ARPROT),
.M_AXI_ARUSER (S_AXI_ATC_ARUSER),
.M_AXI_ARVALID (S_AXI_ATC_ARVALID),
.M_AXI_ARREADY (SAXIACPARREADY_W),
// Slave Interface Read Data Ports
.M_AXI_RID (SAXIACPRID_W),
.M_AXI_RDATA (SAXIACPRDATA_W),
.M_AXI_RRESP (SAXIACPRRESP_W),
.M_AXI_RLAST (SAXIACPRLAST_W),
.M_AXI_RUSER (),
.M_AXI_RVALID (SAXIACPRVALID_W),
.M_AXI_RREADY (S_AXI_ATC_RREADY),
.ERROR_TRIGGER(),
.ERROR_TRANSACTION_ID()
);
end
endgenerate
endmodule
|
// system_acl_iface_mm_interconnect_2.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.0 200 at 2015.04.28.12:23:12
`timescale 1 ps / 1 ps
module system_acl_iface_mm_interconnect_2 (
input wire pll_outclk0_clk, // pll_outclk0.clk
input wire address_span_extender_kernel_reset_reset_bridge_in_reset_reset, // address_span_extender_kernel_reset_reset_bridge_in_reset.reset
input wire hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset, // hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset.reset
input wire [31:0] address_span_extender_kernel_expanded_master_address, // address_span_extender_kernel_expanded_master.address
output wire address_span_extender_kernel_expanded_master_waitrequest, // .waitrequest
input wire [4:0] address_span_extender_kernel_expanded_master_burstcount, // .burstcount
input wire [31:0] address_span_extender_kernel_expanded_master_byteenable, // .byteenable
input wire address_span_extender_kernel_expanded_master_read, // .read
output wire [255:0] address_span_extender_kernel_expanded_master_readdata, // .readdata
output wire address_span_extender_kernel_expanded_master_readdatavalid, // .readdatavalid
input wire address_span_extender_kernel_expanded_master_write, // .write
input wire [255:0] address_span_extender_kernel_expanded_master_writedata, // .writedata
output wire [26:0] hps_f2h_sdram0_data_address, // hps_f2h_sdram0_data.address
output wire hps_f2h_sdram0_data_write, // .write
output wire hps_f2h_sdram0_data_read, // .read
input wire [255:0] hps_f2h_sdram0_data_readdata, // .readdata
output wire [255:0] hps_f2h_sdram0_data_writedata, // .writedata
output wire [7:0] hps_f2h_sdram0_data_burstcount, // .burstcount
output wire [31:0] hps_f2h_sdram0_data_byteenable, // .byteenable
input wire hps_f2h_sdram0_data_readdatavalid, // .readdatavalid
input wire hps_f2h_sdram0_data_waitrequest // .waitrequest
);
wire address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_waitrequest; // address_span_extender_kernel_expanded_master_agent:av_waitrequest -> address_span_extender_kernel_expanded_master_translator:uav_waitrequest
wire [9:0] address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_burstcount; // address_span_extender_kernel_expanded_master_translator:uav_burstcount -> address_span_extender_kernel_expanded_master_agent:av_burstcount
wire [255:0] address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_writedata; // address_span_extender_kernel_expanded_master_translator:uav_writedata -> address_span_extender_kernel_expanded_master_agent:av_writedata
wire [31:0] address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_address; // address_span_extender_kernel_expanded_master_translator:uav_address -> address_span_extender_kernel_expanded_master_agent:av_address
wire address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_lock; // address_span_extender_kernel_expanded_master_translator:uav_lock -> address_span_extender_kernel_expanded_master_agent:av_lock
wire address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_write; // address_span_extender_kernel_expanded_master_translator:uav_write -> address_span_extender_kernel_expanded_master_agent:av_write
wire address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_read; // address_span_extender_kernel_expanded_master_translator:uav_read -> address_span_extender_kernel_expanded_master_agent:av_read
wire [255:0] address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_readdata; // address_span_extender_kernel_expanded_master_agent:av_readdata -> address_span_extender_kernel_expanded_master_translator:uav_readdata
wire address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_debugaccess; // address_span_extender_kernel_expanded_master_translator:uav_debugaccess -> address_span_extender_kernel_expanded_master_agent:av_debugaccess
wire [31:0] address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_byteenable; // address_span_extender_kernel_expanded_master_translator:uav_byteenable -> address_span_extender_kernel_expanded_master_agent:av_byteenable
wire address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_readdatavalid; // address_span_extender_kernel_expanded_master_agent:av_readdatavalid -> address_span_extender_kernel_expanded_master_translator:uav_readdatavalid
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> address_span_extender_kernel_expanded_master_agent:rp_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> address_span_extender_kernel_expanded_master_agent:rp_valid
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> address_span_extender_kernel_expanded_master_agent:rp_startofpacket
wire [363:0] rsp_mux_src_data; // rsp_mux:src_data -> address_span_extender_kernel_expanded_master_agent:rp_data
wire [0:0] rsp_mux_src_channel; // rsp_mux:src_channel -> address_span_extender_kernel_expanded_master_agent:rp_channel
wire rsp_mux_src_ready; // address_span_extender_kernel_expanded_master_agent:rp_ready -> rsp_mux:src_ready
wire hps_f2h_sdram0_data_agent_m0_waitrequest; // hps_f2h_sdram0_data_translator:uav_waitrequest -> hps_f2h_sdram0_data_agent:m0_waitrequest
wire [12:0] hps_f2h_sdram0_data_agent_m0_burstcount; // hps_f2h_sdram0_data_agent:m0_burstcount -> hps_f2h_sdram0_data_translator:uav_burstcount
wire [255:0] hps_f2h_sdram0_data_agent_m0_writedata; // hps_f2h_sdram0_data_agent:m0_writedata -> hps_f2h_sdram0_data_translator:uav_writedata
wire [31:0] hps_f2h_sdram0_data_agent_m0_address; // hps_f2h_sdram0_data_agent:m0_address -> hps_f2h_sdram0_data_translator:uav_address
wire hps_f2h_sdram0_data_agent_m0_write; // hps_f2h_sdram0_data_agent:m0_write -> hps_f2h_sdram0_data_translator:uav_write
wire hps_f2h_sdram0_data_agent_m0_lock; // hps_f2h_sdram0_data_agent:m0_lock -> hps_f2h_sdram0_data_translator:uav_lock
wire hps_f2h_sdram0_data_agent_m0_read; // hps_f2h_sdram0_data_agent:m0_read -> hps_f2h_sdram0_data_translator:uav_read
wire [255:0] hps_f2h_sdram0_data_agent_m0_readdata; // hps_f2h_sdram0_data_translator:uav_readdata -> hps_f2h_sdram0_data_agent:m0_readdata
wire hps_f2h_sdram0_data_agent_m0_readdatavalid; // hps_f2h_sdram0_data_translator:uav_readdatavalid -> hps_f2h_sdram0_data_agent:m0_readdatavalid
wire hps_f2h_sdram0_data_agent_m0_debugaccess; // hps_f2h_sdram0_data_agent:m0_debugaccess -> hps_f2h_sdram0_data_translator:uav_debugaccess
wire [31:0] hps_f2h_sdram0_data_agent_m0_byteenable; // hps_f2h_sdram0_data_agent:m0_byteenable -> hps_f2h_sdram0_data_translator:uav_byteenable
wire hps_f2h_sdram0_data_agent_rf_source_endofpacket; // hps_f2h_sdram0_data_agent:rf_source_endofpacket -> hps_f2h_sdram0_data_agent_rsp_fifo:in_endofpacket
wire hps_f2h_sdram0_data_agent_rf_source_valid; // hps_f2h_sdram0_data_agent:rf_source_valid -> hps_f2h_sdram0_data_agent_rsp_fifo:in_valid
wire hps_f2h_sdram0_data_agent_rf_source_startofpacket; // hps_f2h_sdram0_data_agent:rf_source_startofpacket -> hps_f2h_sdram0_data_agent_rsp_fifo:in_startofpacket
wire [364:0] hps_f2h_sdram0_data_agent_rf_source_data; // hps_f2h_sdram0_data_agent:rf_source_data -> hps_f2h_sdram0_data_agent_rsp_fifo:in_data
wire hps_f2h_sdram0_data_agent_rf_source_ready; // hps_f2h_sdram0_data_agent_rsp_fifo:in_ready -> hps_f2h_sdram0_data_agent:rf_source_ready
wire hps_f2h_sdram0_data_agent_rsp_fifo_out_endofpacket; // hps_f2h_sdram0_data_agent_rsp_fifo:out_endofpacket -> hps_f2h_sdram0_data_agent:rf_sink_endofpacket
wire hps_f2h_sdram0_data_agent_rsp_fifo_out_valid; // hps_f2h_sdram0_data_agent_rsp_fifo:out_valid -> hps_f2h_sdram0_data_agent:rf_sink_valid
wire hps_f2h_sdram0_data_agent_rsp_fifo_out_startofpacket; // hps_f2h_sdram0_data_agent_rsp_fifo:out_startofpacket -> hps_f2h_sdram0_data_agent:rf_sink_startofpacket
wire [364:0] hps_f2h_sdram0_data_agent_rsp_fifo_out_data; // hps_f2h_sdram0_data_agent_rsp_fifo:out_data -> hps_f2h_sdram0_data_agent:rf_sink_data
wire hps_f2h_sdram0_data_agent_rsp_fifo_out_ready; // hps_f2h_sdram0_data_agent:rf_sink_ready -> hps_f2h_sdram0_data_agent_rsp_fifo:out_ready
wire hps_f2h_sdram0_data_agent_rdata_fifo_src_valid; // hps_f2h_sdram0_data_agent:rdata_fifo_src_valid -> hps_f2h_sdram0_data_agent:rdata_fifo_sink_valid
wire [257:0] hps_f2h_sdram0_data_agent_rdata_fifo_src_data; // hps_f2h_sdram0_data_agent:rdata_fifo_src_data -> hps_f2h_sdram0_data_agent:rdata_fifo_sink_data
wire hps_f2h_sdram0_data_agent_rdata_fifo_src_ready; // hps_f2h_sdram0_data_agent:rdata_fifo_sink_ready -> hps_f2h_sdram0_data_agent:rdata_fifo_src_ready
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> hps_f2h_sdram0_data_agent:cp_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> hps_f2h_sdram0_data_agent:cp_valid
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> hps_f2h_sdram0_data_agent:cp_startofpacket
wire [363:0] cmd_mux_src_data; // cmd_mux:src_data -> hps_f2h_sdram0_data_agent:cp_data
wire [0:0] cmd_mux_src_channel; // cmd_mux:src_channel -> hps_f2h_sdram0_data_agent:cp_channel
wire cmd_mux_src_ready; // hps_f2h_sdram0_data_agent:cp_ready -> cmd_mux:src_ready
wire address_span_extender_kernel_expanded_master_agent_cp_endofpacket; // address_span_extender_kernel_expanded_master_agent:cp_endofpacket -> router:sink_endofpacket
wire address_span_extender_kernel_expanded_master_agent_cp_valid; // address_span_extender_kernel_expanded_master_agent:cp_valid -> router:sink_valid
wire address_span_extender_kernel_expanded_master_agent_cp_startofpacket; // address_span_extender_kernel_expanded_master_agent:cp_startofpacket -> router:sink_startofpacket
wire [363:0] address_span_extender_kernel_expanded_master_agent_cp_data; // address_span_extender_kernel_expanded_master_agent:cp_data -> router:sink_data
wire address_span_extender_kernel_expanded_master_agent_cp_ready; // router:sink_ready -> address_span_extender_kernel_expanded_master_agent:cp_ready
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire [363:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire [0:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire hps_f2h_sdram0_data_agent_rp_endofpacket; // hps_f2h_sdram0_data_agent:rp_endofpacket -> router_001:sink_endofpacket
wire hps_f2h_sdram0_data_agent_rp_valid; // hps_f2h_sdram0_data_agent:rp_valid -> router_001:sink_valid
wire hps_f2h_sdram0_data_agent_rp_startofpacket; // hps_f2h_sdram0_data_agent:rp_startofpacket -> router_001:sink_startofpacket
wire [363:0] hps_f2h_sdram0_data_agent_rp_data; // hps_f2h_sdram0_data_agent:rp_data -> router_001:sink_data
wire hps_f2h_sdram0_data_agent_rp_ready; // router_001:sink_ready -> hps_f2h_sdram0_data_agent:rp_ready
wire router_001_src_endofpacket; // router_001:src_endofpacket -> rsp_demux:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> rsp_demux:sink_valid
wire router_001_src_startofpacket; // router_001:src_startofpacket -> rsp_demux:sink_startofpacket
wire [363:0] router_001_src_data; // router_001:src_data -> rsp_demux:sink_data
wire [0:0] router_001_src_channel; // router_001:src_channel -> rsp_demux:sink_channel
wire router_001_src_ready; // rsp_demux:sink_ready -> router_001:src_ready
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire [363:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire [0:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire [363:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire [0:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
altera_merlin_master_translator #(
.AV_ADDRESS_W (32),
.AV_DATA_W (256),
.AV_BURSTCOUNT_W (5),
.AV_BYTEENABLE_W (32),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (10),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (32),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (1),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) address_span_extender_kernel_expanded_master_translator (
.clk (pll_outclk0_clk), // clk.clk
.reset (address_span_extender_kernel_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_read), // .read
.uav_write (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (address_span_extender_kernel_expanded_master_address), // avalon_anti_master_0.address
.av_waitrequest (address_span_extender_kernel_expanded_master_waitrequest), // .waitrequest
.av_burstcount (address_span_extender_kernel_expanded_master_burstcount), // .burstcount
.av_byteenable (address_span_extender_kernel_expanded_master_byteenable), // .byteenable
.av_read (address_span_extender_kernel_expanded_master_read), // .read
.av_readdata (address_span_extender_kernel_expanded_master_readdata), // .readdata
.av_readdatavalid (address_span_extender_kernel_expanded_master_readdatavalid), // .readdatavalid
.av_write (address_span_extender_kernel_expanded_master_write), // .write
.av_writedata (address_span_extender_kernel_expanded_master_writedata), // .writedata
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (27),
.AV_DATA_W (256),
.UAV_DATA_W (256),
.AV_BURSTCOUNT_W (8),
.AV_BYTEENABLE_W (32),
.UAV_BYTEENABLE_W (32),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (13),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (32),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hps_f2h_sdram0_data_translator (
.clk (pll_outclk0_clk), // clk.clk
.reset (hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hps_f2h_sdram0_data_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hps_f2h_sdram0_data_agent_m0_burstcount), // .burstcount
.uav_read (hps_f2h_sdram0_data_agent_m0_read), // .read
.uav_write (hps_f2h_sdram0_data_agent_m0_write), // .write
.uav_waitrequest (hps_f2h_sdram0_data_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hps_f2h_sdram0_data_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hps_f2h_sdram0_data_agent_m0_byteenable), // .byteenable
.uav_readdata (hps_f2h_sdram0_data_agent_m0_readdata), // .readdata
.uav_writedata (hps_f2h_sdram0_data_agent_m0_writedata), // .writedata
.uav_lock (hps_f2h_sdram0_data_agent_m0_lock), // .lock
.uav_debugaccess (hps_f2h_sdram0_data_agent_m0_debugaccess), // .debugaccess
.av_address (hps_f2h_sdram0_data_address), // avalon_anti_slave_0.address
.av_write (hps_f2h_sdram0_data_write), // .write
.av_read (hps_f2h_sdram0_data_read), // .read
.av_readdata (hps_f2h_sdram0_data_readdata), // .readdata
.av_writedata (hps_f2h_sdram0_data_writedata), // .writedata
.av_burstcount (hps_f2h_sdram0_data_burstcount), // .burstcount
.av_byteenable (hps_f2h_sdram0_data_byteenable), // .byteenable
.av_readdatavalid (hps_f2h_sdram0_data_readdatavalid), // .readdatavalid
.av_waitrequest (hps_f2h_sdram0_data_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (354),
.PKT_PROTECTION_L (352),
.PKT_BEGIN_BURST (347),
.PKT_BURSTWRAP_H (339),
.PKT_BURSTWRAP_L (339),
.PKT_BURST_SIZE_H (342),
.PKT_BURST_SIZE_L (340),
.PKT_BURST_TYPE_H (344),
.PKT_BURST_TYPE_L (343),
.PKT_BYTE_CNT_H (338),
.PKT_BYTE_CNT_L (326),
.PKT_ADDR_H (319),
.PKT_ADDR_L (288),
.PKT_TRANS_COMPRESSED_READ (320),
.PKT_TRANS_POSTED (321),
.PKT_TRANS_WRITE (322),
.PKT_TRANS_READ (323),
.PKT_TRANS_LOCK (324),
.PKT_TRANS_EXCLUSIVE (325),
.PKT_DATA_H (255),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (287),
.PKT_BYTEEN_L (256),
.PKT_SRC_ID_H (349),
.PKT_SRC_ID_L (349),
.PKT_DEST_ID_H (350),
.PKT_DEST_ID_L (350),
.PKT_THREAD_ID_H (351),
.PKT_THREAD_ID_L (351),
.PKT_CACHE_H (358),
.PKT_CACHE_L (355),
.PKT_DATA_SIDEBAND_H (346),
.PKT_DATA_SIDEBAND_L (346),
.PKT_QOS_H (348),
.PKT_QOS_L (348),
.PKT_ADDR_SIDEBAND_H (345),
.PKT_ADDR_SIDEBAND_L (345),
.PKT_RESPONSE_STATUS_H (360),
.PKT_RESPONSE_STATUS_L (359),
.PKT_ORI_BURST_SIZE_L (361),
.PKT_ORI_BURST_SIZE_H (363),
.ST_DATA_W (364),
.ST_CHANNEL_W (1),
.AV_BURSTCOUNT_W (10),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) address_span_extender_kernel_expanded_master_agent (
.clk (pll_outclk0_clk), // clk.clk
.reset (address_span_extender_kernel_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_address), // av.address
.av_write (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_write), // .write
.av_read (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (address_span_extender_kernel_expanded_master_agent_cp_valid), // cp.valid
.cp_data (address_span_extender_kernel_expanded_master_agent_cp_data), // .data
.cp_startofpacket (address_span_extender_kernel_expanded_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (address_span_extender_kernel_expanded_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (address_span_extender_kernel_expanded_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (255),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (347),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (287),
.PKT_BYTEEN_L (256),
.PKT_ADDR_H (319),
.PKT_ADDR_L (288),
.PKT_TRANS_COMPRESSED_READ (320),
.PKT_TRANS_POSTED (321),
.PKT_TRANS_WRITE (322),
.PKT_TRANS_READ (323),
.PKT_TRANS_LOCK (324),
.PKT_SRC_ID_H (349),
.PKT_SRC_ID_L (349),
.PKT_DEST_ID_H (350),
.PKT_DEST_ID_L (350),
.PKT_BURSTWRAP_H (339),
.PKT_BURSTWRAP_L (339),
.PKT_BYTE_CNT_H (338),
.PKT_BYTE_CNT_L (326),
.PKT_PROTECTION_H (354),
.PKT_PROTECTION_L (352),
.PKT_RESPONSE_STATUS_H (360),
.PKT_RESPONSE_STATUS_L (359),
.PKT_BURST_SIZE_H (342),
.PKT_BURST_SIZE_L (340),
.PKT_ORI_BURST_SIZE_L (361),
.PKT_ORI_BURST_SIZE_H (363),
.ST_CHANNEL_W (1),
.ST_DATA_W (364),
.AVS_BURSTCOUNT_W (13),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) hps_f2h_sdram0_data_agent (
.clk (pll_outclk0_clk), // clk.clk
.reset (hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (hps_f2h_sdram0_data_agent_m0_address), // m0.address
.m0_burstcount (hps_f2h_sdram0_data_agent_m0_burstcount), // .burstcount
.m0_byteenable (hps_f2h_sdram0_data_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hps_f2h_sdram0_data_agent_m0_debugaccess), // .debugaccess
.m0_lock (hps_f2h_sdram0_data_agent_m0_lock), // .lock
.m0_readdata (hps_f2h_sdram0_data_agent_m0_readdata), // .readdata
.m0_readdatavalid (hps_f2h_sdram0_data_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hps_f2h_sdram0_data_agent_m0_read), // .read
.m0_waitrequest (hps_f2h_sdram0_data_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hps_f2h_sdram0_data_agent_m0_writedata), // .writedata
.m0_write (hps_f2h_sdram0_data_agent_m0_write), // .write
.rp_endofpacket (hps_f2h_sdram0_data_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hps_f2h_sdram0_data_agent_rp_ready), // .ready
.rp_valid (hps_f2h_sdram0_data_agent_rp_valid), // .valid
.rp_data (hps_f2h_sdram0_data_agent_rp_data), // .data
.rp_startofpacket (hps_f2h_sdram0_data_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (hps_f2h_sdram0_data_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hps_f2h_sdram0_data_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hps_f2h_sdram0_data_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hps_f2h_sdram0_data_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hps_f2h_sdram0_data_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hps_f2h_sdram0_data_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hps_f2h_sdram0_data_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hps_f2h_sdram0_data_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hps_f2h_sdram0_data_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hps_f2h_sdram0_data_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (hps_f2h_sdram0_data_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (hps_f2h_sdram0_data_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (hps_f2h_sdram0_data_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (hps_f2h_sdram0_data_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hps_f2h_sdram0_data_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hps_f2h_sdram0_data_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (365),
.FIFO_DEPTH (15),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hps_f2h_sdram0_data_agent_rsp_fifo (
.clk (pll_outclk0_clk), // clk.clk
.reset (hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (hps_f2h_sdram0_data_agent_rf_source_data), // in.data
.in_valid (hps_f2h_sdram0_data_agent_rf_source_valid), // .valid
.in_ready (hps_f2h_sdram0_data_agent_rf_source_ready), // .ready
.in_startofpacket (hps_f2h_sdram0_data_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hps_f2h_sdram0_data_agent_rf_source_endofpacket), // .endofpacket
.out_data (hps_f2h_sdram0_data_agent_rsp_fifo_out_data), // out.data
.out_valid (hps_f2h_sdram0_data_agent_rsp_fifo_out_valid), // .valid
.out_ready (hps_f2h_sdram0_data_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hps_f2h_sdram0_data_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hps_f2h_sdram0_data_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
system_acl_iface_mm_interconnect_2_router router (
.sink_ready (address_span_extender_kernel_expanded_master_agent_cp_ready), // sink.ready
.sink_valid (address_span_extender_kernel_expanded_master_agent_cp_valid), // .valid
.sink_data (address_span_extender_kernel_expanded_master_agent_cp_data), // .data
.sink_startofpacket (address_span_extender_kernel_expanded_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (address_span_extender_kernel_expanded_master_agent_cp_endofpacket), // .endofpacket
.clk (pll_outclk0_clk), // clk.clk
.reset (address_span_extender_kernel_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_2_router_001 router_001 (
.sink_ready (hps_f2h_sdram0_data_agent_rp_ready), // sink.ready
.sink_valid (hps_f2h_sdram0_data_agent_rp_valid), // .valid
.sink_data (hps_f2h_sdram0_data_agent_rp_data), // .data
.sink_startofpacket (hps_f2h_sdram0_data_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hps_f2h_sdram0_data_agent_rp_endofpacket), // .endofpacket
.clk (pll_outclk0_clk), // clk.clk
.reset (hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_2_cmd_demux cmd_demux (
.clk (pll_outclk0_clk), // clk.clk
.reset (address_span_extender_kernel_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_2_cmd_mux cmd_mux (
.clk (pll_outclk0_clk), // clk.clk
.reset (hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_2_cmd_demux rsp_demux (
.clk (pll_outclk0_clk), // clk.clk
.reset (hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_2_rsp_mux rsp_mux (
.clk (pll_outclk0_clk), // clk.clk
.reset (address_span_extender_kernel_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
endmodule
|
/*
Copyright (c) 2014-2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream UART
*/
module uart_tx #
(
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire input_axis_tvalid,
output wire input_axis_tready,
/*
* UART interface
*/
output wire txd,
/*
* Status
*/
output wire busy,
/*
* Configuration
*/
input wire [15:0] prescale
);
reg input_axis_tready_reg = 0;
reg txd_reg = 1;
reg busy_reg = 0;
reg [DATA_WIDTH:0] data_reg = 0;
reg [18:0] prescale_reg = 0;
reg [3:0] bit_cnt = 0;
assign input_axis_tready = input_axis_tready_reg;
assign txd = txd_reg;
assign busy = busy_reg;
always @(posedge clk) begin
if (rst) begin
input_axis_tready_reg <= 0;
txd_reg <= 1;
prescale_reg <= 0;
bit_cnt <= 0;
busy_reg <= 0;
end else begin
if (prescale_reg > 0) begin
input_axis_tready_reg <= 0;
prescale_reg <= prescale_reg - 1;
end else if (bit_cnt == 0) begin
input_axis_tready_reg <= 1;
busy_reg <= 0;
if (input_axis_tvalid) begin
input_axis_tready_reg <= ~input_axis_tready_reg;
prescale_reg <= (prescale << 3)-1;
bit_cnt <= DATA_WIDTH+1;
data_reg <= {1'b1, input_axis_tdata};
txd_reg <= 0;
busy_reg <= 1;
end
end else begin
if (bit_cnt > 1) begin
bit_cnt <= bit_cnt - 1;
prescale_reg <= (prescale << 3)-1;
{data_reg, txd_reg} <= {1'b0, data_reg};
end else if (bit_cnt == 1) begin
bit_cnt <= bit_cnt - 1;
prescale_reg <= (prescale << 3);
txd_reg <= 1;
end
end
end
end
endmodule
|
/*****************************************************************************
* Copyright 1994-2005, Elliot Mednick and Mark Hummel
* This file is part of Veriwell.
*
* Veriwell is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* Veriwell is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Foobar; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*****************************************************************************/
`timescale 1 ns /1 ps
module inv(o,i);
input i;
output o;
assign o = ~i;
endmodule
module test;
reg clk;
wire clk1;
wire clk2;
wire clk3;
integer count;
time t1;
event xevent;
real xyz;
initial begin
// $lxt2_recordvars("space");
$lxt_recordvars("speed");
xyz = 0.0001;
#1
clk = 0;
count = 0;
#500000 $lxt_recordoff();
#500000 $lxt_recordon();
#10000000 $finish;
end
always begin
clk = 0;
clk <= #5 1;
#10;
end
always @(posedge clk) begin
t1 = $time;
count = count+1;
xyz = xyz + xyz;
-> xevent;
end
inv i0(clk1,clk);
inv i1(clk2,clk1);
inv i2(clk3,clk2);
endmodule
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for wb_dp_ram
*/
module test_wb_dp_ram;
// Parameters
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 16;
parameter SELECT_WIDTH = 4;
// Inputs
reg a_clk = 0;
reg a_rst = 0;
reg b_clk = 0;
reg b_rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] a_adr_i = 0;
reg [DATA_WIDTH-1:0] a_dat_i = 0;
reg a_we_i = 0;
reg [SELECT_WIDTH-1:0] a_sel_i = 0;
reg a_stb_i = 0;
reg a_cyc_i = 0;
reg [ADDR_WIDTH-1:0] b_adr_i = 0;
reg [DATA_WIDTH-1:0] b_dat_i = 0;
reg b_we_i = 0;
reg [SELECT_WIDTH-1:0] b_sel_i = 0;
reg b_stb_i = 0;
reg b_cyc_i = 0;
// Outputs
wire [DATA_WIDTH-1:0] a_dat_o;
wire a_ack_o;
wire [DATA_WIDTH-1:0] b_dat_o;
wire b_ack_o;
initial begin
// myhdl integration
$from_myhdl(a_clk,
a_rst,
b_clk,
b_rst,
current_test,
a_adr_i,
a_dat_i,
a_we_i,
a_sel_i,
a_stb_i,
a_cyc_i,
b_adr_i,
b_dat_i,
b_we_i,
b_sel_i,
b_stb_i,
b_cyc_i);
$to_myhdl(a_dat_o,
a_ack_o,
b_dat_o,
b_ack_o);
// dump file
$dumpfile("test_wb_dp_ram.lxt");
$dumpvars(0, test_wb_dp_ram);
end
wb_dp_ram #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.SELECT_WIDTH(SELECT_WIDTH)
)
UUT (
.a_clk(a_clk),
.a_adr_i(a_adr_i),
.a_dat_i(a_dat_i),
.a_dat_o(a_dat_o),
.a_we_i(a_we_i),
.a_sel_i(a_sel_i),
.a_stb_i(a_stb_i),
.a_ack_o(a_ack_o),
.a_cyc_i(a_cyc_i),
.b_clk(b_clk),
.b_adr_i(b_adr_i),
.b_dat_i(b_dat_i),
.b_dat_o(b_dat_o),
.b_we_i(b_we_i),
.b_sel_i(b_sel_i),
.b_stb_i(b_stb_i),
.b_ack_o(b_ack_o),
.b_cyc_i(b_cyc_i)
);
endmodule
|
`include "./Definition.v"
// color correction registering constants
`define CC1 430 // 860.0 / 512 * 256 = 10'b 0110101110
`define CC2 127 // 253.0 / 512 * 256 = 10'b 0001111111
`define CC3 48 // 95.0 / 512 * 256 = 10'b 0000110000
`define CC4 55 // 109.0 / 512 * 256 = 10'b 0000110111
`define CC5 464 // 928.0 / 512 * 256 = 10'b 0111010000
`define CC6 154 // 307.0 / 512 * 256 = 10'b 0010011010
`define CC7 10 // 20.0 / 512 * 256 = 10'b 0000001010
`define CC8 145 // 290.0 / 512 * 256 = 10'b 0010010001
`define CC9 391 // 782.0 / 512 * 256 = 10'b 0110000111
module ColorCorrection
(
input[ `size_int - 1 : 0 ]R,
input[ `size_int - 1 : 0 ]G,
input[ `size_int - 1 : 0 ]B,
output wire[ `size_int - 1 : 0 ]R_out,
output wire[ `size_int - 1 : 0 ]G_out,
output wire[ `size_int - 1 : 0 ]B_out
);
reg[ `size_int : 0 ]R_int;
reg[ `size_int : 0 ]G_int;
reg[ `size_int : 0 ]B_int;
always@( R or G or B )
begin
R_int = ( R * `CC1 - G * `CC2 - B * `CC3 ) >> `ScaleBit;
G_int = ( -R * `CC4 + G * `CC5 - B * `CC6 ) >> `ScaleBit;
B_int = ( R * `CC7 - G * `CC8 + B * `CC9 ) >> `ScaleBit;
end
assign R_out = ( R_int[ 17 : 16 ] == 2'b00 ) ? R_int : ( R_int[ 17 ] == 1'b1 ) ? `MinThreshold : `MaxThreshold;
assign G_out = ( G_int[ 17 : 16 ] == 2'b00 ) ? G_int : ( G_int[ 17 ] == 1'b1 ) ? `MinThreshold : `MaxThreshold;
assign B_out = ( B_int[ 17 : 16 ] == 2'b00 ) ? B_int : ( B_int[ 17 ] == 1'b1 ) ? `MinThreshold : `MaxThreshold;
endmodule
module ColorCorrection_testbench;
reg[ `size_int - 1 : 0 ]R;
reg[ `size_int - 1 : 0 ]G;
reg[ `size_int - 1 : 0 ]B;
wire[ `size_int - 1 : 0 ]R_out;
wire[ `size_int - 1 : 0 ]G_out;
wire[ `size_int - 1 : 0 ]B_out;
ColorCorrection ColorCorrection_test( R, G, B, R_out, G_out, B_out );
initial
begin
#100
begin
R = 200 << `ScaleBit;
G = 0 << `ScaleBit;
B = 0 << `ScaleBit;
end
//X=(200*( 860.0/512)+0*(-253.0/512)+0*( -95.0/512))*256=86000
//Y=(200*(-109.0/512)+0*( 928.0/512)+0*(-307.0/512))*256=-10900
//Z=(200*( 20.0/512)+0*(-290.0/512)+0*( 782.0/512))*256=2000
#100 $display( "R_out = %d", R_out );
#100 $display( "G_out = %d", G_out );
#100 $display( "B_out = %d", B_out );
#100
begin
R = 200 << `ScaleBit;
G = 180 << `ScaleBit;
B = 160 << `ScaleBit;
end
//X=(200*( 860.0/512)+180*(-253.0/512)+160*( -95.0/512))*256=55630
//Y=(200*(-109.0/512)+180*( 928.0/512)+160*(-307.0/512))*256=48060
//Z=(200*( 20.0/512)+180*(-290.0/512)+160*( 782.0/512))*256=38460
#100 $display( "R_out = %d", R_out );
#100 $display( "G_out = %d", G_out );
#100 $display( "B_out = %d", B_out );
#100 $stop;
#100 $finish;
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2013.4
// Copyright (C) 2013 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module nfa_accept_samples_generic_hw_top (
m_axi_nfa_initials_buckets_AWID,
m_axi_nfa_initials_buckets_AWADDR,
m_axi_nfa_initials_buckets_AWLEN,
m_axi_nfa_initials_buckets_AWSIZE,
m_axi_nfa_initials_buckets_AWBURST,
m_axi_nfa_initials_buckets_AWLOCK,
m_axi_nfa_initials_buckets_AWCACHE,
m_axi_nfa_initials_buckets_AWPROT,
m_axi_nfa_initials_buckets_AWQOS,
m_axi_nfa_initials_buckets_AWUSER,
m_axi_nfa_initials_buckets_AWVALID,
m_axi_nfa_initials_buckets_AWREADY,
m_axi_nfa_initials_buckets_WDATA,
m_axi_nfa_initials_buckets_WSTRB,
m_axi_nfa_initials_buckets_WLAST,
m_axi_nfa_initials_buckets_WUSER,
m_axi_nfa_initials_buckets_WVALID,
m_axi_nfa_initials_buckets_WREADY,
m_axi_nfa_initials_buckets_BID,
m_axi_nfa_initials_buckets_BRESP,
m_axi_nfa_initials_buckets_BUSER,
m_axi_nfa_initials_buckets_BVALID,
m_axi_nfa_initials_buckets_BREADY,
m_axi_nfa_initials_buckets_ARID,
m_axi_nfa_initials_buckets_ARADDR,
m_axi_nfa_initials_buckets_ARLEN,
m_axi_nfa_initials_buckets_ARSIZE,
m_axi_nfa_initials_buckets_ARBURST,
m_axi_nfa_initials_buckets_ARLOCK,
m_axi_nfa_initials_buckets_ARCACHE,
m_axi_nfa_initials_buckets_ARPROT,
m_axi_nfa_initials_buckets_ARQOS,
m_axi_nfa_initials_buckets_ARUSER,
m_axi_nfa_initials_buckets_ARVALID,
m_axi_nfa_initials_buckets_ARREADY,
m_axi_nfa_initials_buckets_RID,
m_axi_nfa_initials_buckets_RDATA,
m_axi_nfa_initials_buckets_RRESP,
m_axi_nfa_initials_buckets_RLAST,
m_axi_nfa_initials_buckets_RUSER,
m_axi_nfa_initials_buckets_RVALID,
m_axi_nfa_initials_buckets_RREADY,
m_axi_nfa_finals_buckets_AWID,
m_axi_nfa_finals_buckets_AWADDR,
m_axi_nfa_finals_buckets_AWLEN,
m_axi_nfa_finals_buckets_AWSIZE,
m_axi_nfa_finals_buckets_AWBURST,
m_axi_nfa_finals_buckets_AWLOCK,
m_axi_nfa_finals_buckets_AWCACHE,
m_axi_nfa_finals_buckets_AWPROT,
m_axi_nfa_finals_buckets_AWQOS,
m_axi_nfa_finals_buckets_AWUSER,
m_axi_nfa_finals_buckets_AWVALID,
m_axi_nfa_finals_buckets_AWREADY,
m_axi_nfa_finals_buckets_WDATA,
m_axi_nfa_finals_buckets_WSTRB,
m_axi_nfa_finals_buckets_WLAST,
m_axi_nfa_finals_buckets_WUSER,
m_axi_nfa_finals_buckets_WVALID,
m_axi_nfa_finals_buckets_WREADY,
m_axi_nfa_finals_buckets_BID,
m_axi_nfa_finals_buckets_BRESP,
m_axi_nfa_finals_buckets_BUSER,
m_axi_nfa_finals_buckets_BVALID,
m_axi_nfa_finals_buckets_BREADY,
m_axi_nfa_finals_buckets_ARID,
m_axi_nfa_finals_buckets_ARADDR,
m_axi_nfa_finals_buckets_ARLEN,
m_axi_nfa_finals_buckets_ARSIZE,
m_axi_nfa_finals_buckets_ARBURST,
m_axi_nfa_finals_buckets_ARLOCK,
m_axi_nfa_finals_buckets_ARCACHE,
m_axi_nfa_finals_buckets_ARPROT,
m_axi_nfa_finals_buckets_ARQOS,
m_axi_nfa_finals_buckets_ARUSER,
m_axi_nfa_finals_buckets_ARVALID,
m_axi_nfa_finals_buckets_ARREADY,
m_axi_nfa_finals_buckets_RID,
m_axi_nfa_finals_buckets_RDATA,
m_axi_nfa_finals_buckets_RRESP,
m_axi_nfa_finals_buckets_RLAST,
m_axi_nfa_finals_buckets_RUSER,
m_axi_nfa_finals_buckets_RVALID,
m_axi_nfa_finals_buckets_RREADY,
m_axi_nfa_forward_buckets_AWID,
m_axi_nfa_forward_buckets_AWADDR,
m_axi_nfa_forward_buckets_AWLEN,
m_axi_nfa_forward_buckets_AWSIZE,
m_axi_nfa_forward_buckets_AWBURST,
m_axi_nfa_forward_buckets_AWLOCK,
m_axi_nfa_forward_buckets_AWCACHE,
m_axi_nfa_forward_buckets_AWPROT,
m_axi_nfa_forward_buckets_AWQOS,
m_axi_nfa_forward_buckets_AWUSER,
m_axi_nfa_forward_buckets_AWVALID,
m_axi_nfa_forward_buckets_AWREADY,
m_axi_nfa_forward_buckets_WDATA,
m_axi_nfa_forward_buckets_WSTRB,
m_axi_nfa_forward_buckets_WLAST,
m_axi_nfa_forward_buckets_WUSER,
m_axi_nfa_forward_buckets_WVALID,
m_axi_nfa_forward_buckets_WREADY,
m_axi_nfa_forward_buckets_BID,
m_axi_nfa_forward_buckets_BRESP,
m_axi_nfa_forward_buckets_BUSER,
m_axi_nfa_forward_buckets_BVALID,
m_axi_nfa_forward_buckets_BREADY,
m_axi_nfa_forward_buckets_ARID,
m_axi_nfa_forward_buckets_ARADDR,
m_axi_nfa_forward_buckets_ARLEN,
m_axi_nfa_forward_buckets_ARSIZE,
m_axi_nfa_forward_buckets_ARBURST,
m_axi_nfa_forward_buckets_ARLOCK,
m_axi_nfa_forward_buckets_ARCACHE,
m_axi_nfa_forward_buckets_ARPROT,
m_axi_nfa_forward_buckets_ARQOS,
m_axi_nfa_forward_buckets_ARUSER,
m_axi_nfa_forward_buckets_ARVALID,
m_axi_nfa_forward_buckets_ARREADY,
m_axi_nfa_forward_buckets_RID,
m_axi_nfa_forward_buckets_RDATA,
m_axi_nfa_forward_buckets_RRESP,
m_axi_nfa_forward_buckets_RLAST,
m_axi_nfa_forward_buckets_RUSER,
m_axi_nfa_forward_buckets_RVALID,
m_axi_nfa_forward_buckets_RREADY,
m_axi_sample_buffer_AWID,
m_axi_sample_buffer_AWADDR,
m_axi_sample_buffer_AWLEN,
m_axi_sample_buffer_AWSIZE,
m_axi_sample_buffer_AWBURST,
m_axi_sample_buffer_AWLOCK,
m_axi_sample_buffer_AWCACHE,
m_axi_sample_buffer_AWPROT,
m_axi_sample_buffer_AWQOS,
m_axi_sample_buffer_AWUSER,
m_axi_sample_buffer_AWVALID,
m_axi_sample_buffer_AWREADY,
m_axi_sample_buffer_WDATA,
m_axi_sample_buffer_WSTRB,
m_axi_sample_buffer_WLAST,
m_axi_sample_buffer_WUSER,
m_axi_sample_buffer_WVALID,
m_axi_sample_buffer_WREADY,
m_axi_sample_buffer_BID,
m_axi_sample_buffer_BRESP,
m_axi_sample_buffer_BUSER,
m_axi_sample_buffer_BVALID,
m_axi_sample_buffer_BREADY,
m_axi_sample_buffer_ARID,
m_axi_sample_buffer_ARADDR,
m_axi_sample_buffer_ARLEN,
m_axi_sample_buffer_ARSIZE,
m_axi_sample_buffer_ARBURST,
m_axi_sample_buffer_ARLOCK,
m_axi_sample_buffer_ARCACHE,
m_axi_sample_buffer_ARPROT,
m_axi_sample_buffer_ARQOS,
m_axi_sample_buffer_ARUSER,
m_axi_sample_buffer_ARVALID,
m_axi_sample_buffer_ARREADY,
m_axi_sample_buffer_RID,
m_axi_sample_buffer_RDATA,
m_axi_sample_buffer_RRESP,
m_axi_sample_buffer_RLAST,
m_axi_sample_buffer_RUSER,
m_axi_sample_buffer_RVALID,
m_axi_sample_buffer_RREADY,
m_axi_indices_begin_AWID,
m_axi_indices_begin_AWADDR,
m_axi_indices_begin_AWLEN,
m_axi_indices_begin_AWSIZE,
m_axi_indices_begin_AWBURST,
m_axi_indices_begin_AWLOCK,
m_axi_indices_begin_AWCACHE,
m_axi_indices_begin_AWPROT,
m_axi_indices_begin_AWQOS,
m_axi_indices_begin_AWUSER,
m_axi_indices_begin_AWVALID,
m_axi_indices_begin_AWREADY,
m_axi_indices_begin_WDATA,
m_axi_indices_begin_WSTRB,
m_axi_indices_begin_WLAST,
m_axi_indices_begin_WUSER,
m_axi_indices_begin_WVALID,
m_axi_indices_begin_WREADY,
m_axi_indices_begin_BID,
m_axi_indices_begin_BRESP,
m_axi_indices_begin_BUSER,
m_axi_indices_begin_BVALID,
m_axi_indices_begin_BREADY,
m_axi_indices_begin_ARID,
m_axi_indices_begin_ARADDR,
m_axi_indices_begin_ARLEN,
m_axi_indices_begin_ARSIZE,
m_axi_indices_begin_ARBURST,
m_axi_indices_begin_ARLOCK,
m_axi_indices_begin_ARCACHE,
m_axi_indices_begin_ARPROT,
m_axi_indices_begin_ARQOS,
m_axi_indices_begin_ARUSER,
m_axi_indices_begin_ARVALID,
m_axi_indices_begin_ARREADY,
m_axi_indices_begin_RID,
m_axi_indices_begin_RDATA,
m_axi_indices_begin_RRESP,
m_axi_indices_begin_RLAST,
m_axi_indices_begin_RUSER,
m_axi_indices_begin_RVALID,
m_axi_indices_begin_RREADY,
m_axi_indices_samples_AWID,
m_axi_indices_samples_AWADDR,
m_axi_indices_samples_AWLEN,
m_axi_indices_samples_AWSIZE,
m_axi_indices_samples_AWBURST,
m_axi_indices_samples_AWLOCK,
m_axi_indices_samples_AWCACHE,
m_axi_indices_samples_AWPROT,
m_axi_indices_samples_AWQOS,
m_axi_indices_samples_AWUSER,
m_axi_indices_samples_AWVALID,
m_axi_indices_samples_AWREADY,
m_axi_indices_samples_WDATA,
m_axi_indices_samples_WSTRB,
m_axi_indices_samples_WLAST,
m_axi_indices_samples_WUSER,
m_axi_indices_samples_WVALID,
m_axi_indices_samples_WREADY,
m_axi_indices_samples_BID,
m_axi_indices_samples_BRESP,
m_axi_indices_samples_BUSER,
m_axi_indices_samples_BVALID,
m_axi_indices_samples_BREADY,
m_axi_indices_samples_ARID,
m_axi_indices_samples_ARADDR,
m_axi_indices_samples_ARLEN,
m_axi_indices_samples_ARSIZE,
m_axi_indices_samples_ARBURST,
m_axi_indices_samples_ARLOCK,
m_axi_indices_samples_ARCACHE,
m_axi_indices_samples_ARPROT,
m_axi_indices_samples_ARQOS,
m_axi_indices_samples_ARUSER,
m_axi_indices_samples_ARVALID,
m_axi_indices_samples_ARREADY,
m_axi_indices_samples_RID,
m_axi_indices_samples_RDATA,
m_axi_indices_samples_RRESP,
m_axi_indices_samples_RLAST,
m_axi_indices_samples_RUSER,
m_axi_indices_samples_RVALID,
m_axi_indices_samples_RREADY,
m_axi_indices_stride_AWID,
m_axi_indices_stride_AWADDR,
m_axi_indices_stride_AWLEN,
m_axi_indices_stride_AWSIZE,
m_axi_indices_stride_AWBURST,
m_axi_indices_stride_AWLOCK,
m_axi_indices_stride_AWCACHE,
m_axi_indices_stride_AWPROT,
m_axi_indices_stride_AWQOS,
m_axi_indices_stride_AWUSER,
m_axi_indices_stride_AWVALID,
m_axi_indices_stride_AWREADY,
m_axi_indices_stride_WDATA,
m_axi_indices_stride_WSTRB,
m_axi_indices_stride_WLAST,
m_axi_indices_stride_WUSER,
m_axi_indices_stride_WVALID,
m_axi_indices_stride_WREADY,
m_axi_indices_stride_BID,
m_axi_indices_stride_BRESP,
m_axi_indices_stride_BUSER,
m_axi_indices_stride_BVALID,
m_axi_indices_stride_BREADY,
m_axi_indices_stride_ARID,
m_axi_indices_stride_ARADDR,
m_axi_indices_stride_ARLEN,
m_axi_indices_stride_ARSIZE,
m_axi_indices_stride_ARBURST,
m_axi_indices_stride_ARLOCK,
m_axi_indices_stride_ARCACHE,
m_axi_indices_stride_ARPROT,
m_axi_indices_stride_ARQOS,
m_axi_indices_stride_ARUSER,
m_axi_indices_stride_ARVALID,
m_axi_indices_stride_ARREADY,
m_axi_indices_stride_RID,
m_axi_indices_stride_RDATA,
m_axi_indices_stride_RRESP,
m_axi_indices_stride_RLAST,
m_axi_indices_stride_RUSER,
m_axi_indices_stride_RVALID,
m_axi_indices_stride_RREADY,
s_axi_slv0_AWADDR,
s_axi_slv0_AWVALID,
s_axi_slv0_AWREADY,
s_axi_slv0_WDATA,
s_axi_slv0_WSTRB,
s_axi_slv0_WVALID,
s_axi_slv0_WREADY,
s_axi_slv0_BRESP,
s_axi_slv0_BVALID,
s_axi_slv0_BREADY,
s_axi_slv0_ARADDR,
s_axi_slv0_ARVALID,
s_axi_slv0_ARREADY,
s_axi_slv0_RDATA,
s_axi_slv0_RRESP,
s_axi_slv0_RVALID,
s_axi_slv0_RREADY,
interrupt,
aresetn,
aclk
);
parameter C_M_AXI_NFA_INITIALS_BUCKETS_ID_WIDTH = 1;
parameter C_M_AXI_NFA_INITIALS_BUCKETS_ADDR_WIDTH = 32;
parameter C_M_AXI_NFA_INITIALS_BUCKETS_DATA_WIDTH = 32;
parameter C_M_AXI_NFA_INITIALS_BUCKETS_AWUSER_WIDTH = 1;
parameter C_M_AXI_NFA_INITIALS_BUCKETS_ARUSER_WIDTH = 1;
parameter C_M_AXI_NFA_INITIALS_BUCKETS_WUSER_WIDTH = 1;
parameter C_M_AXI_NFA_INITIALS_BUCKETS_RUSER_WIDTH = 1;
parameter C_M_AXI_NFA_INITIALS_BUCKETS_BUSER_WIDTH = 1;
parameter C_M_AXI_NFA_INITIALS_BUCKETS_USER_DATA_WIDTH = 32;
parameter C_M_AXI_NFA_INITIALS_BUCKETS_TARGET_ADDR = 32'h00000000;
parameter C_M_AXI_NFA_INITIALS_BUCKETS_USER_VALUE = 1'b0;
parameter C_M_AXI_NFA_INITIALS_BUCKETS_PROT_VALUE = 3'b010;
parameter C_M_AXI_NFA_INITIALS_BUCKETS_CACHE_VALUE = 4'b0000;
parameter C_M_AXI_NFA_FINALS_BUCKETS_ID_WIDTH = 1;
parameter C_M_AXI_NFA_FINALS_BUCKETS_ADDR_WIDTH = 32;
parameter C_M_AXI_NFA_FINALS_BUCKETS_DATA_WIDTH = 32;
parameter C_M_AXI_NFA_FINALS_BUCKETS_AWUSER_WIDTH = 1;
parameter C_M_AXI_NFA_FINALS_BUCKETS_ARUSER_WIDTH = 1;
parameter C_M_AXI_NFA_FINALS_BUCKETS_WUSER_WIDTH = 1;
parameter C_M_AXI_NFA_FINALS_BUCKETS_RUSER_WIDTH = 1;
parameter C_M_AXI_NFA_FINALS_BUCKETS_BUSER_WIDTH = 1;
parameter C_M_AXI_NFA_FINALS_BUCKETS_USER_DATA_WIDTH = 32;
parameter C_M_AXI_NFA_FINALS_BUCKETS_TARGET_ADDR = 32'h00000000;
parameter C_M_AXI_NFA_FINALS_BUCKETS_USER_VALUE = 1'b0;
parameter C_M_AXI_NFA_FINALS_BUCKETS_PROT_VALUE = 3'b010;
parameter C_M_AXI_NFA_FINALS_BUCKETS_CACHE_VALUE = 4'b0000;
parameter C_M_AXI_NFA_FORWARD_BUCKETS_ID_WIDTH = 1;
parameter C_M_AXI_NFA_FORWARD_BUCKETS_ADDR_WIDTH = 32;
parameter C_M_AXI_NFA_FORWARD_BUCKETS_DATA_WIDTH = 32;
parameter C_M_AXI_NFA_FORWARD_BUCKETS_AWUSER_WIDTH = 1;
parameter C_M_AXI_NFA_FORWARD_BUCKETS_ARUSER_WIDTH = 1;
parameter C_M_AXI_NFA_FORWARD_BUCKETS_WUSER_WIDTH = 1;
parameter C_M_AXI_NFA_FORWARD_BUCKETS_RUSER_WIDTH = 1;
parameter C_M_AXI_NFA_FORWARD_BUCKETS_BUSER_WIDTH = 1;
parameter C_M_AXI_NFA_FORWARD_BUCKETS_USER_DATA_WIDTH = 32;
parameter C_M_AXI_NFA_FORWARD_BUCKETS_TARGET_ADDR = 32'h00000000;
parameter C_M_AXI_NFA_FORWARD_BUCKETS_USER_VALUE = 1'b0;
parameter C_M_AXI_NFA_FORWARD_BUCKETS_PROT_VALUE = 3'b010;
parameter C_M_AXI_NFA_FORWARD_BUCKETS_CACHE_VALUE = 4'b0000;
parameter C_M_AXI_SAMPLE_BUFFER_ID_WIDTH = 1;
parameter C_M_AXI_SAMPLE_BUFFER_ADDR_WIDTH = 32;
parameter C_M_AXI_SAMPLE_BUFFER_DATA_WIDTH = 32;
parameter C_M_AXI_SAMPLE_BUFFER_AWUSER_WIDTH = 1;
parameter C_M_AXI_SAMPLE_BUFFER_ARUSER_WIDTH = 1;
parameter C_M_AXI_SAMPLE_BUFFER_WUSER_WIDTH = 1;
parameter C_M_AXI_SAMPLE_BUFFER_RUSER_WIDTH = 1;
parameter C_M_AXI_SAMPLE_BUFFER_BUSER_WIDTH = 1;
parameter C_M_AXI_SAMPLE_BUFFER_USER_DATA_WIDTH = 8;
parameter C_M_AXI_SAMPLE_BUFFER_TARGET_ADDR = 32'h00000000;
parameter C_M_AXI_SAMPLE_BUFFER_USER_VALUE = 1'b0;
parameter C_M_AXI_SAMPLE_BUFFER_PROT_VALUE = 3'b010;
parameter C_M_AXI_SAMPLE_BUFFER_CACHE_VALUE = 4'b0000;
parameter C_M_AXI_INDICES_BEGIN_ID_WIDTH = 1;
parameter C_M_AXI_INDICES_BEGIN_ADDR_WIDTH = 32;
parameter C_M_AXI_INDICES_BEGIN_DATA_WIDTH = 32;
parameter C_M_AXI_INDICES_BEGIN_AWUSER_WIDTH = 1;
parameter C_M_AXI_INDICES_BEGIN_ARUSER_WIDTH = 1;
parameter C_M_AXI_INDICES_BEGIN_WUSER_WIDTH = 1;
parameter C_M_AXI_INDICES_BEGIN_RUSER_WIDTH = 1;
parameter C_M_AXI_INDICES_BEGIN_BUSER_WIDTH = 1;
parameter C_M_AXI_INDICES_BEGIN_USER_DATA_WIDTH = 32;
parameter C_M_AXI_INDICES_BEGIN_TARGET_ADDR = 32'h00000000;
parameter C_M_AXI_INDICES_BEGIN_USER_VALUE = 1'b0;
parameter C_M_AXI_INDICES_BEGIN_PROT_VALUE = 3'b010;
parameter C_M_AXI_INDICES_BEGIN_CACHE_VALUE = 4'b0000;
parameter C_M_AXI_INDICES_SAMPLES_ID_WIDTH = 1;
parameter C_M_AXI_INDICES_SAMPLES_ADDR_WIDTH = 32;
parameter C_M_AXI_INDICES_SAMPLES_DATA_WIDTH = 32;
parameter C_M_AXI_INDICES_SAMPLES_AWUSER_WIDTH = 1;
parameter C_M_AXI_INDICES_SAMPLES_ARUSER_WIDTH = 1;
parameter C_M_AXI_INDICES_SAMPLES_WUSER_WIDTH = 1;
parameter C_M_AXI_INDICES_SAMPLES_RUSER_WIDTH = 1;
parameter C_M_AXI_INDICES_SAMPLES_BUSER_WIDTH = 1;
parameter C_M_AXI_INDICES_SAMPLES_USER_DATA_WIDTH = 16;
parameter C_M_AXI_INDICES_SAMPLES_TARGET_ADDR = 32'h00000000;
parameter C_M_AXI_INDICES_SAMPLES_USER_VALUE = 1'b0;
parameter C_M_AXI_INDICES_SAMPLES_PROT_VALUE = 3'b010;
parameter C_M_AXI_INDICES_SAMPLES_CACHE_VALUE = 4'b0000;
parameter C_M_AXI_INDICES_STRIDE_ID_WIDTH = 1;
parameter C_M_AXI_INDICES_STRIDE_ADDR_WIDTH = 32;
parameter C_M_AXI_INDICES_STRIDE_DATA_WIDTH = 32;
parameter C_M_AXI_INDICES_STRIDE_AWUSER_WIDTH = 1;
parameter C_M_AXI_INDICES_STRIDE_ARUSER_WIDTH = 1;
parameter C_M_AXI_INDICES_STRIDE_WUSER_WIDTH = 1;
parameter C_M_AXI_INDICES_STRIDE_RUSER_WIDTH = 1;
parameter C_M_AXI_INDICES_STRIDE_BUSER_WIDTH = 1;
parameter C_M_AXI_INDICES_STRIDE_USER_DATA_WIDTH = 8;
parameter C_M_AXI_INDICES_STRIDE_TARGET_ADDR = 32'h00000000;
parameter C_M_AXI_INDICES_STRIDE_USER_VALUE = 1'b0;
parameter C_M_AXI_INDICES_STRIDE_PROT_VALUE = 3'b010;
parameter C_M_AXI_INDICES_STRIDE_CACHE_VALUE = 4'b0000;
parameter C_S_AXI_SLV0_ADDR_WIDTH = 7;
parameter C_S_AXI_SLV0_DATA_WIDTH = 32;
parameter RESET_ACTIVE_LOW = 1;
output [C_M_AXI_NFA_INITIALS_BUCKETS_ID_WIDTH - 1:0] m_axi_nfa_initials_buckets_AWID ;
output [C_M_AXI_NFA_INITIALS_BUCKETS_ADDR_WIDTH - 1:0] m_axi_nfa_initials_buckets_AWADDR ;
output [8 - 1:0] m_axi_nfa_initials_buckets_AWLEN ;
output [3 - 1:0] m_axi_nfa_initials_buckets_AWSIZE ;
output [2 - 1:0] m_axi_nfa_initials_buckets_AWBURST ;
output [2 - 1:0] m_axi_nfa_initials_buckets_AWLOCK ;
output [4 - 1:0] m_axi_nfa_initials_buckets_AWCACHE ;
output [3 - 1:0] m_axi_nfa_initials_buckets_AWPROT ;
output [4 - 1:0] m_axi_nfa_initials_buckets_AWQOS ;
output [C_M_AXI_NFA_INITIALS_BUCKETS_AWUSER_WIDTH - 1:0] m_axi_nfa_initials_buckets_AWUSER ;
output m_axi_nfa_initials_buckets_AWVALID ;
input m_axi_nfa_initials_buckets_AWREADY ;
output [C_M_AXI_NFA_INITIALS_BUCKETS_DATA_WIDTH - 1:0] m_axi_nfa_initials_buckets_WDATA ;
output [C_M_AXI_NFA_INITIALS_BUCKETS_DATA_WIDTH/8 - 1:0] m_axi_nfa_initials_buckets_WSTRB ;
output m_axi_nfa_initials_buckets_WLAST ;
output [C_M_AXI_NFA_INITIALS_BUCKETS_WUSER_WIDTH - 1:0] m_axi_nfa_initials_buckets_WUSER ;
output m_axi_nfa_initials_buckets_WVALID ;
input m_axi_nfa_initials_buckets_WREADY ;
input [C_M_AXI_NFA_INITIALS_BUCKETS_ID_WIDTH - 1:0] m_axi_nfa_initials_buckets_BID ;
input [2 - 1:0] m_axi_nfa_initials_buckets_BRESP ;
input [C_M_AXI_NFA_INITIALS_BUCKETS_BUSER_WIDTH - 1:0] m_axi_nfa_initials_buckets_BUSER ;
input m_axi_nfa_initials_buckets_BVALID ;
output m_axi_nfa_initials_buckets_BREADY ;
output [C_M_AXI_NFA_INITIALS_BUCKETS_ID_WIDTH - 1:0] m_axi_nfa_initials_buckets_ARID ;
output [C_M_AXI_NFA_INITIALS_BUCKETS_ADDR_WIDTH - 1:0] m_axi_nfa_initials_buckets_ARADDR ;
output [8 - 1:0] m_axi_nfa_initials_buckets_ARLEN ;
output [3 - 1:0] m_axi_nfa_initials_buckets_ARSIZE ;
output [2 - 1:0] m_axi_nfa_initials_buckets_ARBURST ;
output [2 - 1:0] m_axi_nfa_initials_buckets_ARLOCK ;
output [4 - 1:0] m_axi_nfa_initials_buckets_ARCACHE ;
output [3 - 1:0] m_axi_nfa_initials_buckets_ARPROT ;
output [4 - 1:0] m_axi_nfa_initials_buckets_ARQOS ;
output [C_M_AXI_NFA_INITIALS_BUCKETS_ARUSER_WIDTH - 1:0] m_axi_nfa_initials_buckets_ARUSER ;
output m_axi_nfa_initials_buckets_ARVALID ;
input m_axi_nfa_initials_buckets_ARREADY ;
input [C_M_AXI_NFA_INITIALS_BUCKETS_ID_WIDTH - 1:0] m_axi_nfa_initials_buckets_RID ;
input [C_M_AXI_NFA_INITIALS_BUCKETS_DATA_WIDTH - 1:0] m_axi_nfa_initials_buckets_RDATA ;
input [2 - 1:0] m_axi_nfa_initials_buckets_RRESP ;
input m_axi_nfa_initials_buckets_RLAST ;
input [C_M_AXI_NFA_INITIALS_BUCKETS_RUSER_WIDTH - 1:0] m_axi_nfa_initials_buckets_RUSER ;
input m_axi_nfa_initials_buckets_RVALID ;
output m_axi_nfa_initials_buckets_RREADY ;
output [C_M_AXI_NFA_FINALS_BUCKETS_ID_WIDTH - 1:0] m_axi_nfa_finals_buckets_AWID ;
output [C_M_AXI_NFA_FINALS_BUCKETS_ADDR_WIDTH - 1:0] m_axi_nfa_finals_buckets_AWADDR ;
output [8 - 1:0] m_axi_nfa_finals_buckets_AWLEN ;
output [3 - 1:0] m_axi_nfa_finals_buckets_AWSIZE ;
output [2 - 1:0] m_axi_nfa_finals_buckets_AWBURST ;
output [2 - 1:0] m_axi_nfa_finals_buckets_AWLOCK ;
output [4 - 1:0] m_axi_nfa_finals_buckets_AWCACHE ;
output [3 - 1:0] m_axi_nfa_finals_buckets_AWPROT ;
output [4 - 1:0] m_axi_nfa_finals_buckets_AWQOS ;
output [C_M_AXI_NFA_FINALS_BUCKETS_AWUSER_WIDTH - 1:0] m_axi_nfa_finals_buckets_AWUSER ;
output m_axi_nfa_finals_buckets_AWVALID ;
input m_axi_nfa_finals_buckets_AWREADY ;
output [C_M_AXI_NFA_FINALS_BUCKETS_DATA_WIDTH - 1:0] m_axi_nfa_finals_buckets_WDATA ;
output [C_M_AXI_NFA_FINALS_BUCKETS_DATA_WIDTH/8 - 1:0] m_axi_nfa_finals_buckets_WSTRB ;
output m_axi_nfa_finals_buckets_WLAST ;
output [C_M_AXI_NFA_FINALS_BUCKETS_WUSER_WIDTH - 1:0] m_axi_nfa_finals_buckets_WUSER ;
output m_axi_nfa_finals_buckets_WVALID ;
input m_axi_nfa_finals_buckets_WREADY ;
input [C_M_AXI_NFA_FINALS_BUCKETS_ID_WIDTH - 1:0] m_axi_nfa_finals_buckets_BID ;
input [2 - 1:0] m_axi_nfa_finals_buckets_BRESP ;
input [C_M_AXI_NFA_FINALS_BUCKETS_BUSER_WIDTH - 1:0] m_axi_nfa_finals_buckets_BUSER ;
input m_axi_nfa_finals_buckets_BVALID ;
output m_axi_nfa_finals_buckets_BREADY ;
output [C_M_AXI_NFA_FINALS_BUCKETS_ID_WIDTH - 1:0] m_axi_nfa_finals_buckets_ARID ;
output [C_M_AXI_NFA_FINALS_BUCKETS_ADDR_WIDTH - 1:0] m_axi_nfa_finals_buckets_ARADDR ;
output [8 - 1:0] m_axi_nfa_finals_buckets_ARLEN ;
output [3 - 1:0] m_axi_nfa_finals_buckets_ARSIZE ;
output [2 - 1:0] m_axi_nfa_finals_buckets_ARBURST ;
output [2 - 1:0] m_axi_nfa_finals_buckets_ARLOCK ;
output [4 - 1:0] m_axi_nfa_finals_buckets_ARCACHE ;
output [3 - 1:0] m_axi_nfa_finals_buckets_ARPROT ;
output [4 - 1:0] m_axi_nfa_finals_buckets_ARQOS ;
output [C_M_AXI_NFA_FINALS_BUCKETS_ARUSER_WIDTH - 1:0] m_axi_nfa_finals_buckets_ARUSER ;
output m_axi_nfa_finals_buckets_ARVALID ;
input m_axi_nfa_finals_buckets_ARREADY ;
input [C_M_AXI_NFA_FINALS_BUCKETS_ID_WIDTH - 1:0] m_axi_nfa_finals_buckets_RID ;
input [C_M_AXI_NFA_FINALS_BUCKETS_DATA_WIDTH - 1:0] m_axi_nfa_finals_buckets_RDATA ;
input [2 - 1:0] m_axi_nfa_finals_buckets_RRESP ;
input m_axi_nfa_finals_buckets_RLAST ;
input [C_M_AXI_NFA_FINALS_BUCKETS_RUSER_WIDTH - 1:0] m_axi_nfa_finals_buckets_RUSER ;
input m_axi_nfa_finals_buckets_RVALID ;
output m_axi_nfa_finals_buckets_RREADY ;
output [C_M_AXI_NFA_FORWARD_BUCKETS_ID_WIDTH - 1:0] m_axi_nfa_forward_buckets_AWID ;
output [C_M_AXI_NFA_FORWARD_BUCKETS_ADDR_WIDTH - 1:0] m_axi_nfa_forward_buckets_AWADDR ;
output [8 - 1:0] m_axi_nfa_forward_buckets_AWLEN ;
output [3 - 1:0] m_axi_nfa_forward_buckets_AWSIZE ;
output [2 - 1:0] m_axi_nfa_forward_buckets_AWBURST ;
output [2 - 1:0] m_axi_nfa_forward_buckets_AWLOCK ;
output [4 - 1:0] m_axi_nfa_forward_buckets_AWCACHE ;
output [3 - 1:0] m_axi_nfa_forward_buckets_AWPROT ;
output [4 - 1:0] m_axi_nfa_forward_buckets_AWQOS ;
output [C_M_AXI_NFA_FORWARD_BUCKETS_AWUSER_WIDTH - 1:0] m_axi_nfa_forward_buckets_AWUSER ;
output m_axi_nfa_forward_buckets_AWVALID ;
input m_axi_nfa_forward_buckets_AWREADY ;
output [C_M_AXI_NFA_FORWARD_BUCKETS_DATA_WIDTH - 1:0] m_axi_nfa_forward_buckets_WDATA ;
output [C_M_AXI_NFA_FORWARD_BUCKETS_DATA_WIDTH/8 - 1:0] m_axi_nfa_forward_buckets_WSTRB ;
output m_axi_nfa_forward_buckets_WLAST ;
output [C_M_AXI_NFA_FORWARD_BUCKETS_WUSER_WIDTH - 1:0] m_axi_nfa_forward_buckets_WUSER ;
output m_axi_nfa_forward_buckets_WVALID ;
input m_axi_nfa_forward_buckets_WREADY ;
input [C_M_AXI_NFA_FORWARD_BUCKETS_ID_WIDTH - 1:0] m_axi_nfa_forward_buckets_BID ;
input [2 - 1:0] m_axi_nfa_forward_buckets_BRESP ;
input [C_M_AXI_NFA_FORWARD_BUCKETS_BUSER_WIDTH - 1:0] m_axi_nfa_forward_buckets_BUSER ;
input m_axi_nfa_forward_buckets_BVALID ;
output m_axi_nfa_forward_buckets_BREADY ;
output [C_M_AXI_NFA_FORWARD_BUCKETS_ID_WIDTH - 1:0] m_axi_nfa_forward_buckets_ARID ;
output [C_M_AXI_NFA_FORWARD_BUCKETS_ADDR_WIDTH - 1:0] m_axi_nfa_forward_buckets_ARADDR ;
output [8 - 1:0] m_axi_nfa_forward_buckets_ARLEN ;
output [3 - 1:0] m_axi_nfa_forward_buckets_ARSIZE ;
output [2 - 1:0] m_axi_nfa_forward_buckets_ARBURST ;
output [2 - 1:0] m_axi_nfa_forward_buckets_ARLOCK ;
output [4 - 1:0] m_axi_nfa_forward_buckets_ARCACHE ;
output [3 - 1:0] m_axi_nfa_forward_buckets_ARPROT ;
output [4 - 1:0] m_axi_nfa_forward_buckets_ARQOS ;
output [C_M_AXI_NFA_FORWARD_BUCKETS_ARUSER_WIDTH - 1:0] m_axi_nfa_forward_buckets_ARUSER ;
output m_axi_nfa_forward_buckets_ARVALID ;
input m_axi_nfa_forward_buckets_ARREADY ;
input [C_M_AXI_NFA_FORWARD_BUCKETS_ID_WIDTH - 1:0] m_axi_nfa_forward_buckets_RID ;
input [C_M_AXI_NFA_FORWARD_BUCKETS_DATA_WIDTH - 1:0] m_axi_nfa_forward_buckets_RDATA ;
input [2 - 1:0] m_axi_nfa_forward_buckets_RRESP ;
input m_axi_nfa_forward_buckets_RLAST ;
input [C_M_AXI_NFA_FORWARD_BUCKETS_RUSER_WIDTH - 1:0] m_axi_nfa_forward_buckets_RUSER ;
input m_axi_nfa_forward_buckets_RVALID ;
output m_axi_nfa_forward_buckets_RREADY ;
output [C_M_AXI_SAMPLE_BUFFER_ID_WIDTH - 1:0] m_axi_sample_buffer_AWID ;
output [C_M_AXI_SAMPLE_BUFFER_ADDR_WIDTH - 1:0] m_axi_sample_buffer_AWADDR ;
output [8 - 1:0] m_axi_sample_buffer_AWLEN ;
output [3 - 1:0] m_axi_sample_buffer_AWSIZE ;
output [2 - 1:0] m_axi_sample_buffer_AWBURST ;
output [2 - 1:0] m_axi_sample_buffer_AWLOCK ;
output [4 - 1:0] m_axi_sample_buffer_AWCACHE ;
output [3 - 1:0] m_axi_sample_buffer_AWPROT ;
output [4 - 1:0] m_axi_sample_buffer_AWQOS ;
output [C_M_AXI_SAMPLE_BUFFER_AWUSER_WIDTH - 1:0] m_axi_sample_buffer_AWUSER ;
output m_axi_sample_buffer_AWVALID ;
input m_axi_sample_buffer_AWREADY ;
output [C_M_AXI_SAMPLE_BUFFER_DATA_WIDTH - 1:0] m_axi_sample_buffer_WDATA ;
output [C_M_AXI_SAMPLE_BUFFER_DATA_WIDTH/8 - 1:0] m_axi_sample_buffer_WSTRB ;
output m_axi_sample_buffer_WLAST ;
output [C_M_AXI_SAMPLE_BUFFER_WUSER_WIDTH - 1:0] m_axi_sample_buffer_WUSER ;
output m_axi_sample_buffer_WVALID ;
input m_axi_sample_buffer_WREADY ;
input [C_M_AXI_SAMPLE_BUFFER_ID_WIDTH - 1:0] m_axi_sample_buffer_BID ;
input [2 - 1:0] m_axi_sample_buffer_BRESP ;
input [C_M_AXI_SAMPLE_BUFFER_BUSER_WIDTH - 1:0] m_axi_sample_buffer_BUSER ;
input m_axi_sample_buffer_BVALID ;
output m_axi_sample_buffer_BREADY ;
output [C_M_AXI_SAMPLE_BUFFER_ID_WIDTH - 1:0] m_axi_sample_buffer_ARID ;
output [C_M_AXI_SAMPLE_BUFFER_ADDR_WIDTH - 1:0] m_axi_sample_buffer_ARADDR ;
output [8 - 1:0] m_axi_sample_buffer_ARLEN ;
output [3 - 1:0] m_axi_sample_buffer_ARSIZE ;
output [2 - 1:0] m_axi_sample_buffer_ARBURST ;
output [2 - 1:0] m_axi_sample_buffer_ARLOCK ;
output [4 - 1:0] m_axi_sample_buffer_ARCACHE ;
output [3 - 1:0] m_axi_sample_buffer_ARPROT ;
output [4 - 1:0] m_axi_sample_buffer_ARQOS ;
output [C_M_AXI_SAMPLE_BUFFER_ARUSER_WIDTH - 1:0] m_axi_sample_buffer_ARUSER ;
output m_axi_sample_buffer_ARVALID ;
input m_axi_sample_buffer_ARREADY ;
input [C_M_AXI_SAMPLE_BUFFER_ID_WIDTH - 1:0] m_axi_sample_buffer_RID ;
input [C_M_AXI_SAMPLE_BUFFER_DATA_WIDTH - 1:0] m_axi_sample_buffer_RDATA ;
input [2 - 1:0] m_axi_sample_buffer_RRESP ;
input m_axi_sample_buffer_RLAST ;
input [C_M_AXI_SAMPLE_BUFFER_RUSER_WIDTH - 1:0] m_axi_sample_buffer_RUSER ;
input m_axi_sample_buffer_RVALID ;
output m_axi_sample_buffer_RREADY ;
output [C_M_AXI_INDICES_BEGIN_ID_WIDTH - 1:0] m_axi_indices_begin_AWID ;
output [C_M_AXI_INDICES_BEGIN_ADDR_WIDTH - 1:0] m_axi_indices_begin_AWADDR ;
output [8 - 1:0] m_axi_indices_begin_AWLEN ;
output [3 - 1:0] m_axi_indices_begin_AWSIZE ;
output [2 - 1:0] m_axi_indices_begin_AWBURST ;
output [2 - 1:0] m_axi_indices_begin_AWLOCK ;
output [4 - 1:0] m_axi_indices_begin_AWCACHE ;
output [3 - 1:0] m_axi_indices_begin_AWPROT ;
output [4 - 1:0] m_axi_indices_begin_AWQOS ;
output [C_M_AXI_INDICES_BEGIN_AWUSER_WIDTH - 1:0] m_axi_indices_begin_AWUSER ;
output m_axi_indices_begin_AWVALID ;
input m_axi_indices_begin_AWREADY ;
output [C_M_AXI_INDICES_BEGIN_DATA_WIDTH - 1:0] m_axi_indices_begin_WDATA ;
output [C_M_AXI_INDICES_BEGIN_DATA_WIDTH/8 - 1:0] m_axi_indices_begin_WSTRB ;
output m_axi_indices_begin_WLAST ;
output [C_M_AXI_INDICES_BEGIN_WUSER_WIDTH - 1:0] m_axi_indices_begin_WUSER ;
output m_axi_indices_begin_WVALID ;
input m_axi_indices_begin_WREADY ;
input [C_M_AXI_INDICES_BEGIN_ID_WIDTH - 1:0] m_axi_indices_begin_BID ;
input [2 - 1:0] m_axi_indices_begin_BRESP ;
input [C_M_AXI_INDICES_BEGIN_BUSER_WIDTH - 1:0] m_axi_indices_begin_BUSER ;
input m_axi_indices_begin_BVALID ;
output m_axi_indices_begin_BREADY ;
output [C_M_AXI_INDICES_BEGIN_ID_WIDTH - 1:0] m_axi_indices_begin_ARID ;
output [C_M_AXI_INDICES_BEGIN_ADDR_WIDTH - 1:0] m_axi_indices_begin_ARADDR ;
output [8 - 1:0] m_axi_indices_begin_ARLEN ;
output [3 - 1:0] m_axi_indices_begin_ARSIZE ;
output [2 - 1:0] m_axi_indices_begin_ARBURST ;
output [2 - 1:0] m_axi_indices_begin_ARLOCK ;
output [4 - 1:0] m_axi_indices_begin_ARCACHE ;
output [3 - 1:0] m_axi_indices_begin_ARPROT ;
output [4 - 1:0] m_axi_indices_begin_ARQOS ;
output [C_M_AXI_INDICES_BEGIN_ARUSER_WIDTH - 1:0] m_axi_indices_begin_ARUSER ;
output m_axi_indices_begin_ARVALID ;
input m_axi_indices_begin_ARREADY ;
input [C_M_AXI_INDICES_BEGIN_ID_WIDTH - 1:0] m_axi_indices_begin_RID ;
input [C_M_AXI_INDICES_BEGIN_DATA_WIDTH - 1:0] m_axi_indices_begin_RDATA ;
input [2 - 1:0] m_axi_indices_begin_RRESP ;
input m_axi_indices_begin_RLAST ;
input [C_M_AXI_INDICES_BEGIN_RUSER_WIDTH - 1:0] m_axi_indices_begin_RUSER ;
input m_axi_indices_begin_RVALID ;
output m_axi_indices_begin_RREADY ;
output [C_M_AXI_INDICES_SAMPLES_ID_WIDTH - 1:0] m_axi_indices_samples_AWID ;
output [C_M_AXI_INDICES_SAMPLES_ADDR_WIDTH - 1:0] m_axi_indices_samples_AWADDR ;
output [8 - 1:0] m_axi_indices_samples_AWLEN ;
output [3 - 1:0] m_axi_indices_samples_AWSIZE ;
output [2 - 1:0] m_axi_indices_samples_AWBURST ;
output [2 - 1:0] m_axi_indices_samples_AWLOCK ;
output [4 - 1:0] m_axi_indices_samples_AWCACHE ;
output [3 - 1:0] m_axi_indices_samples_AWPROT ;
output [4 - 1:0] m_axi_indices_samples_AWQOS ;
output [C_M_AXI_INDICES_SAMPLES_AWUSER_WIDTH - 1:0] m_axi_indices_samples_AWUSER ;
output m_axi_indices_samples_AWVALID ;
input m_axi_indices_samples_AWREADY ;
output [C_M_AXI_INDICES_SAMPLES_DATA_WIDTH - 1:0] m_axi_indices_samples_WDATA ;
output [C_M_AXI_INDICES_SAMPLES_DATA_WIDTH/8 - 1:0] m_axi_indices_samples_WSTRB ;
output m_axi_indices_samples_WLAST ;
output [C_M_AXI_INDICES_SAMPLES_WUSER_WIDTH - 1:0] m_axi_indices_samples_WUSER ;
output m_axi_indices_samples_WVALID ;
input m_axi_indices_samples_WREADY ;
input [C_M_AXI_INDICES_SAMPLES_ID_WIDTH - 1:0] m_axi_indices_samples_BID ;
input [2 - 1:0] m_axi_indices_samples_BRESP ;
input [C_M_AXI_INDICES_SAMPLES_BUSER_WIDTH - 1:0] m_axi_indices_samples_BUSER ;
input m_axi_indices_samples_BVALID ;
output m_axi_indices_samples_BREADY ;
output [C_M_AXI_INDICES_SAMPLES_ID_WIDTH - 1:0] m_axi_indices_samples_ARID ;
output [C_M_AXI_INDICES_SAMPLES_ADDR_WIDTH - 1:0] m_axi_indices_samples_ARADDR ;
output [8 - 1:0] m_axi_indices_samples_ARLEN ;
output [3 - 1:0] m_axi_indices_samples_ARSIZE ;
output [2 - 1:0] m_axi_indices_samples_ARBURST ;
output [2 - 1:0] m_axi_indices_samples_ARLOCK ;
output [4 - 1:0] m_axi_indices_samples_ARCACHE ;
output [3 - 1:0] m_axi_indices_samples_ARPROT ;
output [4 - 1:0] m_axi_indices_samples_ARQOS ;
output [C_M_AXI_INDICES_SAMPLES_ARUSER_WIDTH - 1:0] m_axi_indices_samples_ARUSER ;
output m_axi_indices_samples_ARVALID ;
input m_axi_indices_samples_ARREADY ;
input [C_M_AXI_INDICES_SAMPLES_ID_WIDTH - 1:0] m_axi_indices_samples_RID ;
input [C_M_AXI_INDICES_SAMPLES_DATA_WIDTH - 1:0] m_axi_indices_samples_RDATA ;
input [2 - 1:0] m_axi_indices_samples_RRESP ;
input m_axi_indices_samples_RLAST ;
input [C_M_AXI_INDICES_SAMPLES_RUSER_WIDTH - 1:0] m_axi_indices_samples_RUSER ;
input m_axi_indices_samples_RVALID ;
output m_axi_indices_samples_RREADY ;
output [C_M_AXI_INDICES_STRIDE_ID_WIDTH - 1:0] m_axi_indices_stride_AWID ;
output [C_M_AXI_INDICES_STRIDE_ADDR_WIDTH - 1:0] m_axi_indices_stride_AWADDR ;
output [8 - 1:0] m_axi_indices_stride_AWLEN ;
output [3 - 1:0] m_axi_indices_stride_AWSIZE ;
output [2 - 1:0] m_axi_indices_stride_AWBURST ;
output [2 - 1:0] m_axi_indices_stride_AWLOCK ;
output [4 - 1:0] m_axi_indices_stride_AWCACHE ;
output [3 - 1:0] m_axi_indices_stride_AWPROT ;
output [4 - 1:0] m_axi_indices_stride_AWQOS ;
output [C_M_AXI_INDICES_STRIDE_AWUSER_WIDTH - 1:0] m_axi_indices_stride_AWUSER ;
output m_axi_indices_stride_AWVALID ;
input m_axi_indices_stride_AWREADY ;
output [C_M_AXI_INDICES_STRIDE_DATA_WIDTH - 1:0] m_axi_indices_stride_WDATA ;
output [C_M_AXI_INDICES_STRIDE_DATA_WIDTH/8 - 1:0] m_axi_indices_stride_WSTRB ;
output m_axi_indices_stride_WLAST ;
output [C_M_AXI_INDICES_STRIDE_WUSER_WIDTH - 1:0] m_axi_indices_stride_WUSER ;
output m_axi_indices_stride_WVALID ;
input m_axi_indices_stride_WREADY ;
input [C_M_AXI_INDICES_STRIDE_ID_WIDTH - 1:0] m_axi_indices_stride_BID ;
input [2 - 1:0] m_axi_indices_stride_BRESP ;
input [C_M_AXI_INDICES_STRIDE_BUSER_WIDTH - 1:0] m_axi_indices_stride_BUSER ;
input m_axi_indices_stride_BVALID ;
output m_axi_indices_stride_BREADY ;
output [C_M_AXI_INDICES_STRIDE_ID_WIDTH - 1:0] m_axi_indices_stride_ARID ;
output [C_M_AXI_INDICES_STRIDE_ADDR_WIDTH - 1:0] m_axi_indices_stride_ARADDR ;
output [8 - 1:0] m_axi_indices_stride_ARLEN ;
output [3 - 1:0] m_axi_indices_stride_ARSIZE ;
output [2 - 1:0] m_axi_indices_stride_ARBURST ;
output [2 - 1:0] m_axi_indices_stride_ARLOCK ;
output [4 - 1:0] m_axi_indices_stride_ARCACHE ;
output [3 - 1:0] m_axi_indices_stride_ARPROT ;
output [4 - 1:0] m_axi_indices_stride_ARQOS ;
output [C_M_AXI_INDICES_STRIDE_ARUSER_WIDTH - 1:0] m_axi_indices_stride_ARUSER ;
output m_axi_indices_stride_ARVALID ;
input m_axi_indices_stride_ARREADY ;
input [C_M_AXI_INDICES_STRIDE_ID_WIDTH - 1:0] m_axi_indices_stride_RID ;
input [C_M_AXI_INDICES_STRIDE_DATA_WIDTH - 1:0] m_axi_indices_stride_RDATA ;
input [2 - 1:0] m_axi_indices_stride_RRESP ;
input m_axi_indices_stride_RLAST ;
input [C_M_AXI_INDICES_STRIDE_RUSER_WIDTH - 1:0] m_axi_indices_stride_RUSER ;
input m_axi_indices_stride_RVALID ;
output m_axi_indices_stride_RREADY ;
input [C_S_AXI_SLV0_ADDR_WIDTH - 1:0] s_axi_slv0_AWADDR ;
input s_axi_slv0_AWVALID ;
output s_axi_slv0_AWREADY ;
input [C_S_AXI_SLV0_DATA_WIDTH - 1:0] s_axi_slv0_WDATA ;
input [C_S_AXI_SLV0_DATA_WIDTH/8 - 1:0] s_axi_slv0_WSTRB ;
input s_axi_slv0_WVALID ;
output s_axi_slv0_WREADY ;
output [2 - 1:0] s_axi_slv0_BRESP ;
output s_axi_slv0_BVALID ;
input s_axi_slv0_BREADY ;
input [C_S_AXI_SLV0_ADDR_WIDTH - 1:0] s_axi_slv0_ARADDR ;
input s_axi_slv0_ARVALID ;
output s_axi_slv0_ARREADY ;
output [C_S_AXI_SLV0_DATA_WIDTH - 1:0] s_axi_slv0_RDATA ;
output [2 - 1:0] s_axi_slv0_RRESP ;
output s_axi_slv0_RVALID ;
input s_axi_slv0_RREADY ;
output interrupt ;
input aresetn ;
input aclk ;
wire [C_M_AXI_NFA_INITIALS_BUCKETS_ID_WIDTH - 1:0] m_axi_nfa_initials_buckets_AWID;
wire [C_M_AXI_NFA_INITIALS_BUCKETS_ADDR_WIDTH - 1:0] m_axi_nfa_initials_buckets_AWADDR;
wire [8 - 1:0] m_axi_nfa_initials_buckets_AWLEN;
wire [3 - 1:0] m_axi_nfa_initials_buckets_AWSIZE;
wire [2 - 1:0] m_axi_nfa_initials_buckets_AWBURST;
wire [2 - 1:0] m_axi_nfa_initials_buckets_AWLOCK;
wire [4 - 1:0] m_axi_nfa_initials_buckets_AWCACHE;
wire [3 - 1:0] m_axi_nfa_initials_buckets_AWPROT;
wire [4 - 1:0] m_axi_nfa_initials_buckets_AWQOS;
wire [C_M_AXI_NFA_INITIALS_BUCKETS_AWUSER_WIDTH - 1:0] m_axi_nfa_initials_buckets_AWUSER;
wire m_axi_nfa_initials_buckets_AWVALID;
wire m_axi_nfa_initials_buckets_AWREADY;
wire [C_M_AXI_NFA_INITIALS_BUCKETS_DATA_WIDTH - 1:0] m_axi_nfa_initials_buckets_WDATA;
wire [C_M_AXI_NFA_INITIALS_BUCKETS_DATA_WIDTH/8 - 1:0] m_axi_nfa_initials_buckets_WSTRB;
wire m_axi_nfa_initials_buckets_WLAST;
wire [C_M_AXI_NFA_INITIALS_BUCKETS_WUSER_WIDTH - 1:0] m_axi_nfa_initials_buckets_WUSER;
wire m_axi_nfa_initials_buckets_WVALID;
wire m_axi_nfa_initials_buckets_WREADY;
wire [C_M_AXI_NFA_INITIALS_BUCKETS_ID_WIDTH - 1:0] m_axi_nfa_initials_buckets_BID;
wire [2 - 1:0] m_axi_nfa_initials_buckets_BRESP;
wire [C_M_AXI_NFA_INITIALS_BUCKETS_BUSER_WIDTH - 1:0] m_axi_nfa_initials_buckets_BUSER;
wire m_axi_nfa_initials_buckets_BVALID;
wire m_axi_nfa_initials_buckets_BREADY;
wire [C_M_AXI_NFA_INITIALS_BUCKETS_ID_WIDTH - 1:0] m_axi_nfa_initials_buckets_ARID;
wire [C_M_AXI_NFA_INITIALS_BUCKETS_ADDR_WIDTH - 1:0] m_axi_nfa_initials_buckets_ARADDR;
wire [8 - 1:0] m_axi_nfa_initials_buckets_ARLEN;
wire [3 - 1:0] m_axi_nfa_initials_buckets_ARSIZE;
wire [2 - 1:0] m_axi_nfa_initials_buckets_ARBURST;
wire [2 - 1:0] m_axi_nfa_initials_buckets_ARLOCK;
wire [4 - 1:0] m_axi_nfa_initials_buckets_ARCACHE;
wire [3 - 1:0] m_axi_nfa_initials_buckets_ARPROT;
wire [4 - 1:0] m_axi_nfa_initials_buckets_ARQOS;
wire [C_M_AXI_NFA_INITIALS_BUCKETS_ARUSER_WIDTH - 1:0] m_axi_nfa_initials_buckets_ARUSER;
wire m_axi_nfa_initials_buckets_ARVALID;
wire m_axi_nfa_initials_buckets_ARREADY;
wire [C_M_AXI_NFA_INITIALS_BUCKETS_ID_WIDTH - 1:0] m_axi_nfa_initials_buckets_RID;
wire [C_M_AXI_NFA_INITIALS_BUCKETS_DATA_WIDTH - 1:0] m_axi_nfa_initials_buckets_RDATA;
wire [2 - 1:0] m_axi_nfa_initials_buckets_RRESP;
wire m_axi_nfa_initials_buckets_RLAST;
wire [C_M_AXI_NFA_INITIALS_BUCKETS_RUSER_WIDTH - 1:0] m_axi_nfa_initials_buckets_RUSER;
wire m_axi_nfa_initials_buckets_RVALID;
wire m_axi_nfa_initials_buckets_RREADY;
wire [C_M_AXI_NFA_FINALS_BUCKETS_ID_WIDTH - 1:0] m_axi_nfa_finals_buckets_AWID;
wire [C_M_AXI_NFA_FINALS_BUCKETS_ADDR_WIDTH - 1:0] m_axi_nfa_finals_buckets_AWADDR;
wire [8 - 1:0] m_axi_nfa_finals_buckets_AWLEN;
wire [3 - 1:0] m_axi_nfa_finals_buckets_AWSIZE;
wire [2 - 1:0] m_axi_nfa_finals_buckets_AWBURST;
wire [2 - 1:0] m_axi_nfa_finals_buckets_AWLOCK;
wire [4 - 1:0] m_axi_nfa_finals_buckets_AWCACHE;
wire [3 - 1:0] m_axi_nfa_finals_buckets_AWPROT;
wire [4 - 1:0] m_axi_nfa_finals_buckets_AWQOS;
wire [C_M_AXI_NFA_FINALS_BUCKETS_AWUSER_WIDTH - 1:0] m_axi_nfa_finals_buckets_AWUSER;
wire m_axi_nfa_finals_buckets_AWVALID;
wire m_axi_nfa_finals_buckets_AWREADY;
wire [C_M_AXI_NFA_FINALS_BUCKETS_DATA_WIDTH - 1:0] m_axi_nfa_finals_buckets_WDATA;
wire [C_M_AXI_NFA_FINALS_BUCKETS_DATA_WIDTH/8 - 1:0] m_axi_nfa_finals_buckets_WSTRB;
wire m_axi_nfa_finals_buckets_WLAST;
wire [C_M_AXI_NFA_FINALS_BUCKETS_WUSER_WIDTH - 1:0] m_axi_nfa_finals_buckets_WUSER;
wire m_axi_nfa_finals_buckets_WVALID;
wire m_axi_nfa_finals_buckets_WREADY;
wire [C_M_AXI_NFA_FINALS_BUCKETS_ID_WIDTH - 1:0] m_axi_nfa_finals_buckets_BID;
wire [2 - 1:0] m_axi_nfa_finals_buckets_BRESP;
wire [C_M_AXI_NFA_FINALS_BUCKETS_BUSER_WIDTH - 1:0] m_axi_nfa_finals_buckets_BUSER;
wire m_axi_nfa_finals_buckets_BVALID;
wire m_axi_nfa_finals_buckets_BREADY;
wire [C_M_AXI_NFA_FINALS_BUCKETS_ID_WIDTH - 1:0] m_axi_nfa_finals_buckets_ARID;
wire [C_M_AXI_NFA_FINALS_BUCKETS_ADDR_WIDTH - 1:0] m_axi_nfa_finals_buckets_ARADDR;
wire [8 - 1:0] m_axi_nfa_finals_buckets_ARLEN;
wire [3 - 1:0] m_axi_nfa_finals_buckets_ARSIZE;
wire [2 - 1:0] m_axi_nfa_finals_buckets_ARBURST;
wire [2 - 1:0] m_axi_nfa_finals_buckets_ARLOCK;
wire [4 - 1:0] m_axi_nfa_finals_buckets_ARCACHE;
wire [3 - 1:0] m_axi_nfa_finals_buckets_ARPROT;
wire [4 - 1:0] m_axi_nfa_finals_buckets_ARQOS;
wire [C_M_AXI_NFA_FINALS_BUCKETS_ARUSER_WIDTH - 1:0] m_axi_nfa_finals_buckets_ARUSER;
wire m_axi_nfa_finals_buckets_ARVALID;
wire m_axi_nfa_finals_buckets_ARREADY;
wire [C_M_AXI_NFA_FINALS_BUCKETS_ID_WIDTH - 1:0] m_axi_nfa_finals_buckets_RID;
wire [C_M_AXI_NFA_FINALS_BUCKETS_DATA_WIDTH - 1:0] m_axi_nfa_finals_buckets_RDATA;
wire [2 - 1:0] m_axi_nfa_finals_buckets_RRESP;
wire m_axi_nfa_finals_buckets_RLAST;
wire [C_M_AXI_NFA_FINALS_BUCKETS_RUSER_WIDTH - 1:0] m_axi_nfa_finals_buckets_RUSER;
wire m_axi_nfa_finals_buckets_RVALID;
wire m_axi_nfa_finals_buckets_RREADY;
wire [C_M_AXI_NFA_FORWARD_BUCKETS_ID_WIDTH - 1:0] m_axi_nfa_forward_buckets_AWID;
wire [C_M_AXI_NFA_FORWARD_BUCKETS_ADDR_WIDTH - 1:0] m_axi_nfa_forward_buckets_AWADDR;
wire [8 - 1:0] m_axi_nfa_forward_buckets_AWLEN;
wire [3 - 1:0] m_axi_nfa_forward_buckets_AWSIZE;
wire [2 - 1:0] m_axi_nfa_forward_buckets_AWBURST;
wire [2 - 1:0] m_axi_nfa_forward_buckets_AWLOCK;
wire [4 - 1:0] m_axi_nfa_forward_buckets_AWCACHE;
wire [3 - 1:0] m_axi_nfa_forward_buckets_AWPROT;
wire [4 - 1:0] m_axi_nfa_forward_buckets_AWQOS;
wire [C_M_AXI_NFA_FORWARD_BUCKETS_AWUSER_WIDTH - 1:0] m_axi_nfa_forward_buckets_AWUSER;
wire m_axi_nfa_forward_buckets_AWVALID;
wire m_axi_nfa_forward_buckets_AWREADY;
wire [C_M_AXI_NFA_FORWARD_BUCKETS_DATA_WIDTH - 1:0] m_axi_nfa_forward_buckets_WDATA;
wire [C_M_AXI_NFA_FORWARD_BUCKETS_DATA_WIDTH/8 - 1:0] m_axi_nfa_forward_buckets_WSTRB;
wire m_axi_nfa_forward_buckets_WLAST;
wire [C_M_AXI_NFA_FORWARD_BUCKETS_WUSER_WIDTH - 1:0] m_axi_nfa_forward_buckets_WUSER;
wire m_axi_nfa_forward_buckets_WVALID;
wire m_axi_nfa_forward_buckets_WREADY;
wire [C_M_AXI_NFA_FORWARD_BUCKETS_ID_WIDTH - 1:0] m_axi_nfa_forward_buckets_BID;
wire [2 - 1:0] m_axi_nfa_forward_buckets_BRESP;
wire [C_M_AXI_NFA_FORWARD_BUCKETS_BUSER_WIDTH - 1:0] m_axi_nfa_forward_buckets_BUSER;
wire m_axi_nfa_forward_buckets_BVALID;
wire m_axi_nfa_forward_buckets_BREADY;
wire [C_M_AXI_NFA_FORWARD_BUCKETS_ID_WIDTH - 1:0] m_axi_nfa_forward_buckets_ARID;
wire [C_M_AXI_NFA_FORWARD_BUCKETS_ADDR_WIDTH - 1:0] m_axi_nfa_forward_buckets_ARADDR;
wire [8 - 1:0] m_axi_nfa_forward_buckets_ARLEN;
wire [3 - 1:0] m_axi_nfa_forward_buckets_ARSIZE;
wire [2 - 1:0] m_axi_nfa_forward_buckets_ARBURST;
wire [2 - 1:0] m_axi_nfa_forward_buckets_ARLOCK;
wire [4 - 1:0] m_axi_nfa_forward_buckets_ARCACHE;
wire [3 - 1:0] m_axi_nfa_forward_buckets_ARPROT;
wire [4 - 1:0] m_axi_nfa_forward_buckets_ARQOS;
wire [C_M_AXI_NFA_FORWARD_BUCKETS_ARUSER_WIDTH - 1:0] m_axi_nfa_forward_buckets_ARUSER;
wire m_axi_nfa_forward_buckets_ARVALID;
wire m_axi_nfa_forward_buckets_ARREADY;
wire [C_M_AXI_NFA_FORWARD_BUCKETS_ID_WIDTH - 1:0] m_axi_nfa_forward_buckets_RID;
wire [C_M_AXI_NFA_FORWARD_BUCKETS_DATA_WIDTH - 1:0] m_axi_nfa_forward_buckets_RDATA;
wire [2 - 1:0] m_axi_nfa_forward_buckets_RRESP;
wire m_axi_nfa_forward_buckets_RLAST;
wire [C_M_AXI_NFA_FORWARD_BUCKETS_RUSER_WIDTH - 1:0] m_axi_nfa_forward_buckets_RUSER;
wire m_axi_nfa_forward_buckets_RVALID;
wire m_axi_nfa_forward_buckets_RREADY;
wire [C_M_AXI_SAMPLE_BUFFER_ID_WIDTH - 1:0] m_axi_sample_buffer_AWID;
wire [C_M_AXI_SAMPLE_BUFFER_ADDR_WIDTH - 1:0] m_axi_sample_buffer_AWADDR;
wire [8 - 1:0] m_axi_sample_buffer_AWLEN;
wire [3 - 1:0] m_axi_sample_buffer_AWSIZE;
wire [2 - 1:0] m_axi_sample_buffer_AWBURST;
wire [2 - 1:0] m_axi_sample_buffer_AWLOCK;
wire [4 - 1:0] m_axi_sample_buffer_AWCACHE;
wire [3 - 1:0] m_axi_sample_buffer_AWPROT;
wire [4 - 1:0] m_axi_sample_buffer_AWQOS;
wire [C_M_AXI_SAMPLE_BUFFER_AWUSER_WIDTH - 1:0] m_axi_sample_buffer_AWUSER;
wire m_axi_sample_buffer_AWVALID;
wire m_axi_sample_buffer_AWREADY;
wire [C_M_AXI_SAMPLE_BUFFER_DATA_WIDTH - 1:0] m_axi_sample_buffer_WDATA;
wire [C_M_AXI_SAMPLE_BUFFER_DATA_WIDTH/8 - 1:0] m_axi_sample_buffer_WSTRB;
wire m_axi_sample_buffer_WLAST;
wire [C_M_AXI_SAMPLE_BUFFER_WUSER_WIDTH - 1:0] m_axi_sample_buffer_WUSER;
wire m_axi_sample_buffer_WVALID;
wire m_axi_sample_buffer_WREADY;
wire [C_M_AXI_SAMPLE_BUFFER_ID_WIDTH - 1:0] m_axi_sample_buffer_BID;
wire [2 - 1:0] m_axi_sample_buffer_BRESP;
wire [C_M_AXI_SAMPLE_BUFFER_BUSER_WIDTH - 1:0] m_axi_sample_buffer_BUSER;
wire m_axi_sample_buffer_BVALID;
wire m_axi_sample_buffer_BREADY;
wire [C_M_AXI_SAMPLE_BUFFER_ID_WIDTH - 1:0] m_axi_sample_buffer_ARID;
wire [C_M_AXI_SAMPLE_BUFFER_ADDR_WIDTH - 1:0] m_axi_sample_buffer_ARADDR;
wire [8 - 1:0] m_axi_sample_buffer_ARLEN;
wire [3 - 1:0] m_axi_sample_buffer_ARSIZE;
wire [2 - 1:0] m_axi_sample_buffer_ARBURST;
wire [2 - 1:0] m_axi_sample_buffer_ARLOCK;
wire [4 - 1:0] m_axi_sample_buffer_ARCACHE;
wire [3 - 1:0] m_axi_sample_buffer_ARPROT;
wire [4 - 1:0] m_axi_sample_buffer_ARQOS;
wire [C_M_AXI_SAMPLE_BUFFER_ARUSER_WIDTH - 1:0] m_axi_sample_buffer_ARUSER;
wire m_axi_sample_buffer_ARVALID;
wire m_axi_sample_buffer_ARREADY;
wire [C_M_AXI_SAMPLE_BUFFER_ID_WIDTH - 1:0] m_axi_sample_buffer_RID;
wire [C_M_AXI_SAMPLE_BUFFER_DATA_WIDTH - 1:0] m_axi_sample_buffer_RDATA;
wire [2 - 1:0] m_axi_sample_buffer_RRESP;
wire m_axi_sample_buffer_RLAST;
wire [C_M_AXI_SAMPLE_BUFFER_RUSER_WIDTH - 1:0] m_axi_sample_buffer_RUSER;
wire m_axi_sample_buffer_RVALID;
wire m_axi_sample_buffer_RREADY;
wire [C_M_AXI_INDICES_BEGIN_ID_WIDTH - 1:0] m_axi_indices_begin_AWID;
wire [C_M_AXI_INDICES_BEGIN_ADDR_WIDTH - 1:0] m_axi_indices_begin_AWADDR;
wire [8 - 1:0] m_axi_indices_begin_AWLEN;
wire [3 - 1:0] m_axi_indices_begin_AWSIZE;
wire [2 - 1:0] m_axi_indices_begin_AWBURST;
wire [2 - 1:0] m_axi_indices_begin_AWLOCK;
wire [4 - 1:0] m_axi_indices_begin_AWCACHE;
wire [3 - 1:0] m_axi_indices_begin_AWPROT;
wire [4 - 1:0] m_axi_indices_begin_AWQOS;
wire [C_M_AXI_INDICES_BEGIN_AWUSER_WIDTH - 1:0] m_axi_indices_begin_AWUSER;
wire m_axi_indices_begin_AWVALID;
wire m_axi_indices_begin_AWREADY;
wire [C_M_AXI_INDICES_BEGIN_DATA_WIDTH - 1:0] m_axi_indices_begin_WDATA;
wire [C_M_AXI_INDICES_BEGIN_DATA_WIDTH/8 - 1:0] m_axi_indices_begin_WSTRB;
wire m_axi_indices_begin_WLAST;
wire [C_M_AXI_INDICES_BEGIN_WUSER_WIDTH - 1:0] m_axi_indices_begin_WUSER;
wire m_axi_indices_begin_WVALID;
wire m_axi_indices_begin_WREADY;
wire [C_M_AXI_INDICES_BEGIN_ID_WIDTH - 1:0] m_axi_indices_begin_BID;
wire [2 - 1:0] m_axi_indices_begin_BRESP;
wire [C_M_AXI_INDICES_BEGIN_BUSER_WIDTH - 1:0] m_axi_indices_begin_BUSER;
wire m_axi_indices_begin_BVALID;
wire m_axi_indices_begin_BREADY;
wire [C_M_AXI_INDICES_BEGIN_ID_WIDTH - 1:0] m_axi_indices_begin_ARID;
wire [C_M_AXI_INDICES_BEGIN_ADDR_WIDTH - 1:0] m_axi_indices_begin_ARADDR;
wire [8 - 1:0] m_axi_indices_begin_ARLEN;
wire [3 - 1:0] m_axi_indices_begin_ARSIZE;
wire [2 - 1:0] m_axi_indices_begin_ARBURST;
wire [2 - 1:0] m_axi_indices_begin_ARLOCK;
wire [4 - 1:0] m_axi_indices_begin_ARCACHE;
wire [3 - 1:0] m_axi_indices_begin_ARPROT;
wire [4 - 1:0] m_axi_indices_begin_ARQOS;
wire [C_M_AXI_INDICES_BEGIN_ARUSER_WIDTH - 1:0] m_axi_indices_begin_ARUSER;
wire m_axi_indices_begin_ARVALID;
wire m_axi_indices_begin_ARREADY;
wire [C_M_AXI_INDICES_BEGIN_ID_WIDTH - 1:0] m_axi_indices_begin_RID;
wire [C_M_AXI_INDICES_BEGIN_DATA_WIDTH - 1:0] m_axi_indices_begin_RDATA;
wire [2 - 1:0] m_axi_indices_begin_RRESP;
wire m_axi_indices_begin_RLAST;
wire [C_M_AXI_INDICES_BEGIN_RUSER_WIDTH - 1:0] m_axi_indices_begin_RUSER;
wire m_axi_indices_begin_RVALID;
wire m_axi_indices_begin_RREADY;
wire [C_M_AXI_INDICES_SAMPLES_ID_WIDTH - 1:0] m_axi_indices_samples_AWID;
wire [C_M_AXI_INDICES_SAMPLES_ADDR_WIDTH - 1:0] m_axi_indices_samples_AWADDR;
wire [8 - 1:0] m_axi_indices_samples_AWLEN;
wire [3 - 1:0] m_axi_indices_samples_AWSIZE;
wire [2 - 1:0] m_axi_indices_samples_AWBURST;
wire [2 - 1:0] m_axi_indices_samples_AWLOCK;
wire [4 - 1:0] m_axi_indices_samples_AWCACHE;
wire [3 - 1:0] m_axi_indices_samples_AWPROT;
wire [4 - 1:0] m_axi_indices_samples_AWQOS;
wire [C_M_AXI_INDICES_SAMPLES_AWUSER_WIDTH - 1:0] m_axi_indices_samples_AWUSER;
wire m_axi_indices_samples_AWVALID;
wire m_axi_indices_samples_AWREADY;
wire [C_M_AXI_INDICES_SAMPLES_DATA_WIDTH - 1:0] m_axi_indices_samples_WDATA;
wire [C_M_AXI_INDICES_SAMPLES_DATA_WIDTH/8 - 1:0] m_axi_indices_samples_WSTRB;
wire m_axi_indices_samples_WLAST;
wire [C_M_AXI_INDICES_SAMPLES_WUSER_WIDTH - 1:0] m_axi_indices_samples_WUSER;
wire m_axi_indices_samples_WVALID;
wire m_axi_indices_samples_WREADY;
wire [C_M_AXI_INDICES_SAMPLES_ID_WIDTH - 1:0] m_axi_indices_samples_BID;
wire [2 - 1:0] m_axi_indices_samples_BRESP;
wire [C_M_AXI_INDICES_SAMPLES_BUSER_WIDTH - 1:0] m_axi_indices_samples_BUSER;
wire m_axi_indices_samples_BVALID;
wire m_axi_indices_samples_BREADY;
wire [C_M_AXI_INDICES_SAMPLES_ID_WIDTH - 1:0] m_axi_indices_samples_ARID;
wire [C_M_AXI_INDICES_SAMPLES_ADDR_WIDTH - 1:0] m_axi_indices_samples_ARADDR;
wire [8 - 1:0] m_axi_indices_samples_ARLEN;
wire [3 - 1:0] m_axi_indices_samples_ARSIZE;
wire [2 - 1:0] m_axi_indices_samples_ARBURST;
wire [2 - 1:0] m_axi_indices_samples_ARLOCK;
wire [4 - 1:0] m_axi_indices_samples_ARCACHE;
wire [3 - 1:0] m_axi_indices_samples_ARPROT;
wire [4 - 1:0] m_axi_indices_samples_ARQOS;
wire [C_M_AXI_INDICES_SAMPLES_ARUSER_WIDTH - 1:0] m_axi_indices_samples_ARUSER;
wire m_axi_indices_samples_ARVALID;
wire m_axi_indices_samples_ARREADY;
wire [C_M_AXI_INDICES_SAMPLES_ID_WIDTH - 1:0] m_axi_indices_samples_RID;
wire [C_M_AXI_INDICES_SAMPLES_DATA_WIDTH - 1:0] m_axi_indices_samples_RDATA;
wire [2 - 1:0] m_axi_indices_samples_RRESP;
wire m_axi_indices_samples_RLAST;
wire [C_M_AXI_INDICES_SAMPLES_RUSER_WIDTH - 1:0] m_axi_indices_samples_RUSER;
wire m_axi_indices_samples_RVALID;
wire m_axi_indices_samples_RREADY;
wire [C_M_AXI_INDICES_STRIDE_ID_WIDTH - 1:0] m_axi_indices_stride_AWID;
wire [C_M_AXI_INDICES_STRIDE_ADDR_WIDTH - 1:0] m_axi_indices_stride_AWADDR;
wire [8 - 1:0] m_axi_indices_stride_AWLEN;
wire [3 - 1:0] m_axi_indices_stride_AWSIZE;
wire [2 - 1:0] m_axi_indices_stride_AWBURST;
wire [2 - 1:0] m_axi_indices_stride_AWLOCK;
wire [4 - 1:0] m_axi_indices_stride_AWCACHE;
wire [3 - 1:0] m_axi_indices_stride_AWPROT;
wire [4 - 1:0] m_axi_indices_stride_AWQOS;
wire [C_M_AXI_INDICES_STRIDE_AWUSER_WIDTH - 1:0] m_axi_indices_stride_AWUSER;
wire m_axi_indices_stride_AWVALID;
wire m_axi_indices_stride_AWREADY;
wire [C_M_AXI_INDICES_STRIDE_DATA_WIDTH - 1:0] m_axi_indices_stride_WDATA;
wire [C_M_AXI_INDICES_STRIDE_DATA_WIDTH/8 - 1:0] m_axi_indices_stride_WSTRB;
wire m_axi_indices_stride_WLAST;
wire [C_M_AXI_INDICES_STRIDE_WUSER_WIDTH - 1:0] m_axi_indices_stride_WUSER;
wire m_axi_indices_stride_WVALID;
wire m_axi_indices_stride_WREADY;
wire [C_M_AXI_INDICES_STRIDE_ID_WIDTH - 1:0] m_axi_indices_stride_BID;
wire [2 - 1:0] m_axi_indices_stride_BRESP;
wire [C_M_AXI_INDICES_STRIDE_BUSER_WIDTH - 1:0] m_axi_indices_stride_BUSER;
wire m_axi_indices_stride_BVALID;
wire m_axi_indices_stride_BREADY;
wire [C_M_AXI_INDICES_STRIDE_ID_WIDTH - 1:0] m_axi_indices_stride_ARID;
wire [C_M_AXI_INDICES_STRIDE_ADDR_WIDTH - 1:0] m_axi_indices_stride_ARADDR;
wire [8 - 1:0] m_axi_indices_stride_ARLEN;
wire [3 - 1:0] m_axi_indices_stride_ARSIZE;
wire [2 - 1:0] m_axi_indices_stride_ARBURST;
wire [2 - 1:0] m_axi_indices_stride_ARLOCK;
wire [4 - 1:0] m_axi_indices_stride_ARCACHE;
wire [3 - 1:0] m_axi_indices_stride_ARPROT;
wire [4 - 1:0] m_axi_indices_stride_ARQOS;
wire [C_M_AXI_INDICES_STRIDE_ARUSER_WIDTH - 1:0] m_axi_indices_stride_ARUSER;
wire m_axi_indices_stride_ARVALID;
wire m_axi_indices_stride_ARREADY;
wire [C_M_AXI_INDICES_STRIDE_ID_WIDTH - 1:0] m_axi_indices_stride_RID;
wire [C_M_AXI_INDICES_STRIDE_DATA_WIDTH - 1:0] m_axi_indices_stride_RDATA;
wire [2 - 1:0] m_axi_indices_stride_RRESP;
wire m_axi_indices_stride_RLAST;
wire [C_M_AXI_INDICES_STRIDE_RUSER_WIDTH - 1:0] m_axi_indices_stride_RUSER;
wire m_axi_indices_stride_RVALID;
wire m_axi_indices_stride_RREADY;
wire [C_S_AXI_SLV0_ADDR_WIDTH - 1:0] s_axi_slv0_AWADDR;
wire s_axi_slv0_AWVALID;
wire s_axi_slv0_AWREADY;
wire [C_S_AXI_SLV0_DATA_WIDTH - 1:0] s_axi_slv0_WDATA;
wire [C_S_AXI_SLV0_DATA_WIDTH/8 - 1:0] s_axi_slv0_WSTRB;
wire s_axi_slv0_WVALID;
wire s_axi_slv0_WREADY;
wire [2 - 1:0] s_axi_slv0_BRESP;
wire s_axi_slv0_BVALID;
wire s_axi_slv0_BREADY;
wire [C_S_AXI_SLV0_ADDR_WIDTH - 1:0] s_axi_slv0_ARADDR;
wire s_axi_slv0_ARVALID;
wire s_axi_slv0_ARREADY;
wire [C_S_AXI_SLV0_DATA_WIDTH - 1:0] s_axi_slv0_RDATA;
wire [2 - 1:0] s_axi_slv0_RRESP;
wire s_axi_slv0_RVALID;
wire s_axi_slv0_RREADY;
wire interrupt;
wire aresetn;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_datain;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_dataout;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_address;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_size;
wire sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_req_din;
wire sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_req_full_n;
wire sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_req_write;
wire sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_rsp_empty_n;
wire sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_rsp_read;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_datain;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_dataout;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_address;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_size;
wire sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_req_din;
wire sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_req_full_n;
wire sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_req_write;
wire sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_rsp_empty_n;
wire sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_rsp_read;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_datain;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_dataout;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_address;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_size;
wire sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_req_din;
wire sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_req_full_n;
wire sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_req_write;
wire sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_rsp_empty_n;
wire sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_rsp_read;
wire [8 - 1:0] sig_nfa_accept_samples_generic_hw_sample_buffer_datain;
wire [8 - 1:0] sig_nfa_accept_samples_generic_hw_sample_buffer_dataout;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_sample_buffer_address;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_sample_buffer_size;
wire sig_nfa_accept_samples_generic_hw_sample_buffer_req_din;
wire sig_nfa_accept_samples_generic_hw_sample_buffer_req_full_n;
wire sig_nfa_accept_samples_generic_hw_sample_buffer_req_write;
wire sig_nfa_accept_samples_generic_hw_sample_buffer_rsp_empty_n;
wire sig_nfa_accept_samples_generic_hw_sample_buffer_rsp_read;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_indices_begin_datain;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_indices_begin_dataout;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_indices_begin_address;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_indices_begin_size;
wire sig_nfa_accept_samples_generic_hw_indices_begin_req_din;
wire sig_nfa_accept_samples_generic_hw_indices_begin_req_full_n;
wire sig_nfa_accept_samples_generic_hw_indices_begin_req_write;
wire sig_nfa_accept_samples_generic_hw_indices_begin_rsp_empty_n;
wire sig_nfa_accept_samples_generic_hw_indices_begin_rsp_read;
wire [16 - 1:0] sig_nfa_accept_samples_generic_hw_indices_samples_datain;
wire [16 - 1:0] sig_nfa_accept_samples_generic_hw_indices_samples_dataout;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_indices_samples_address;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_indices_samples_size;
wire sig_nfa_accept_samples_generic_hw_indices_samples_req_din;
wire sig_nfa_accept_samples_generic_hw_indices_samples_req_full_n;
wire sig_nfa_accept_samples_generic_hw_indices_samples_req_write;
wire sig_nfa_accept_samples_generic_hw_indices_samples_rsp_empty_n;
wire sig_nfa_accept_samples_generic_hw_indices_samples_rsp_read;
wire [8 - 1:0] sig_nfa_accept_samples_generic_hw_indices_stride_datain;
wire [8 - 1:0] sig_nfa_accept_samples_generic_hw_indices_stride_dataout;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_indices_stride_address;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_indices_stride_size;
wire sig_nfa_accept_samples_generic_hw_indices_stride_req_din;
wire sig_nfa_accept_samples_generic_hw_indices_stride_req_full_n;
wire sig_nfa_accept_samples_generic_hw_indices_stride_req_write;
wire sig_nfa_accept_samples_generic_hw_indices_stride_rsp_empty_n;
wire sig_nfa_accept_samples_generic_hw_indices_stride_rsp_read;
wire [8 - 1:0] sig_nfa_accept_samples_generic_hw_nfa_symbols;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_sample_buffer_length;
wire [16 - 1:0] sig_nfa_accept_samples_generic_hw_sample_length;
wire [16 - 1:0] sig_nfa_accept_samples_generic_hw_i_size;
wire [16 - 1:0] sig_nfa_accept_samples_generic_hw_begin_index;
wire [16 - 1:0] sig_nfa_accept_samples_generic_hw_begin_sample;
wire [16 - 1:0] sig_nfa_accept_samples_generic_hw_end_index;
wire [16 - 1:0] sig_nfa_accept_samples_generic_hw_end_sample;
wire [1 - 1:0] sig_nfa_accept_samples_generic_hw_stop_on_first;
wire [1 - 1:0] sig_nfa_accept_samples_generic_hw_accept;
wire sig_nfa_accept_samples_generic_hw_ap_start;
wire sig_nfa_accept_samples_generic_hw_ap_ready;
wire sig_nfa_accept_samples_generic_hw_ap_done;
wire sig_nfa_accept_samples_generic_hw_ap_idle;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_ap_return;
wire sig_nfa_accept_samples_generic_hw_ap_rst;
nfa_accept_samples_generic_hw nfa_accept_samples_generic_hw_U(
.nfa_initials_buckets_datain(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_datain),
.nfa_initials_buckets_dataout(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_dataout),
.nfa_initials_buckets_address(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_address),
.nfa_initials_buckets_size(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_size),
.nfa_initials_buckets_req_din(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_req_din),
.nfa_initials_buckets_req_full_n(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_req_full_n),
.nfa_initials_buckets_req_write(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_req_write),
.nfa_initials_buckets_rsp_empty_n(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_rsp_empty_n),
.nfa_initials_buckets_rsp_read(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_rsp_read),
.nfa_finals_buckets_datain(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_datain),
.nfa_finals_buckets_dataout(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_dataout),
.nfa_finals_buckets_address(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_address),
.nfa_finals_buckets_size(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_size),
.nfa_finals_buckets_req_din(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_req_din),
.nfa_finals_buckets_req_full_n(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_req_full_n),
.nfa_finals_buckets_req_write(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_req_write),
.nfa_finals_buckets_rsp_empty_n(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_rsp_empty_n),
.nfa_finals_buckets_rsp_read(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_rsp_read),
.nfa_forward_buckets_datain(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_datain),
.nfa_forward_buckets_dataout(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_dataout),
.nfa_forward_buckets_address(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_address),
.nfa_forward_buckets_size(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_size),
.nfa_forward_buckets_req_din(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_req_din),
.nfa_forward_buckets_req_full_n(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_req_full_n),
.nfa_forward_buckets_req_write(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_req_write),
.nfa_forward_buckets_rsp_empty_n(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_rsp_empty_n),
.nfa_forward_buckets_rsp_read(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_rsp_read),
.sample_buffer_datain(sig_nfa_accept_samples_generic_hw_sample_buffer_datain),
.sample_buffer_dataout(sig_nfa_accept_samples_generic_hw_sample_buffer_dataout),
.sample_buffer_address(sig_nfa_accept_samples_generic_hw_sample_buffer_address),
.sample_buffer_size(sig_nfa_accept_samples_generic_hw_sample_buffer_size),
.sample_buffer_req_din(sig_nfa_accept_samples_generic_hw_sample_buffer_req_din),
.sample_buffer_req_full_n(sig_nfa_accept_samples_generic_hw_sample_buffer_req_full_n),
.sample_buffer_req_write(sig_nfa_accept_samples_generic_hw_sample_buffer_req_write),
.sample_buffer_rsp_empty_n(sig_nfa_accept_samples_generic_hw_sample_buffer_rsp_empty_n),
.sample_buffer_rsp_read(sig_nfa_accept_samples_generic_hw_sample_buffer_rsp_read),
.indices_begin_datain(sig_nfa_accept_samples_generic_hw_indices_begin_datain),
.indices_begin_dataout(sig_nfa_accept_samples_generic_hw_indices_begin_dataout),
.indices_begin_address(sig_nfa_accept_samples_generic_hw_indices_begin_address),
.indices_begin_size(sig_nfa_accept_samples_generic_hw_indices_begin_size),
.indices_begin_req_din(sig_nfa_accept_samples_generic_hw_indices_begin_req_din),
.indices_begin_req_full_n(sig_nfa_accept_samples_generic_hw_indices_begin_req_full_n),
.indices_begin_req_write(sig_nfa_accept_samples_generic_hw_indices_begin_req_write),
.indices_begin_rsp_empty_n(sig_nfa_accept_samples_generic_hw_indices_begin_rsp_empty_n),
.indices_begin_rsp_read(sig_nfa_accept_samples_generic_hw_indices_begin_rsp_read),
.indices_samples_datain(sig_nfa_accept_samples_generic_hw_indices_samples_datain),
.indices_samples_dataout(sig_nfa_accept_samples_generic_hw_indices_samples_dataout),
.indices_samples_address(sig_nfa_accept_samples_generic_hw_indices_samples_address),
.indices_samples_size(sig_nfa_accept_samples_generic_hw_indices_samples_size),
.indices_samples_req_din(sig_nfa_accept_samples_generic_hw_indices_samples_req_din),
.indices_samples_req_full_n(sig_nfa_accept_samples_generic_hw_indices_samples_req_full_n),
.indices_samples_req_write(sig_nfa_accept_samples_generic_hw_indices_samples_req_write),
.indices_samples_rsp_empty_n(sig_nfa_accept_samples_generic_hw_indices_samples_rsp_empty_n),
.indices_samples_rsp_read(sig_nfa_accept_samples_generic_hw_indices_samples_rsp_read),
.indices_stride_datain(sig_nfa_accept_samples_generic_hw_indices_stride_datain),
.indices_stride_dataout(sig_nfa_accept_samples_generic_hw_indices_stride_dataout),
.indices_stride_address(sig_nfa_accept_samples_generic_hw_indices_stride_address),
.indices_stride_size(sig_nfa_accept_samples_generic_hw_indices_stride_size),
.indices_stride_req_din(sig_nfa_accept_samples_generic_hw_indices_stride_req_din),
.indices_stride_req_full_n(sig_nfa_accept_samples_generic_hw_indices_stride_req_full_n),
.indices_stride_req_write(sig_nfa_accept_samples_generic_hw_indices_stride_req_write),
.indices_stride_rsp_empty_n(sig_nfa_accept_samples_generic_hw_indices_stride_rsp_empty_n),
.indices_stride_rsp_read(sig_nfa_accept_samples_generic_hw_indices_stride_rsp_read),
.nfa_symbols(sig_nfa_accept_samples_generic_hw_nfa_symbols),
.sample_buffer_length(sig_nfa_accept_samples_generic_hw_sample_buffer_length),
.sample_length(sig_nfa_accept_samples_generic_hw_sample_length),
.i_size(sig_nfa_accept_samples_generic_hw_i_size),
.begin_index(sig_nfa_accept_samples_generic_hw_begin_index),
.begin_sample(sig_nfa_accept_samples_generic_hw_begin_sample),
.end_index(sig_nfa_accept_samples_generic_hw_end_index),
.end_sample(sig_nfa_accept_samples_generic_hw_end_sample),
.stop_on_first(sig_nfa_accept_samples_generic_hw_stop_on_first),
.accept(sig_nfa_accept_samples_generic_hw_accept),
.ap_start(sig_nfa_accept_samples_generic_hw_ap_start),
.ap_ready(sig_nfa_accept_samples_generic_hw_ap_ready),
.ap_done(sig_nfa_accept_samples_generic_hw_ap_done),
.ap_idle(sig_nfa_accept_samples_generic_hw_ap_idle),
.ap_return(sig_nfa_accept_samples_generic_hw_ap_return),
.ap_rst(sig_nfa_accept_samples_generic_hw_ap_rst),
.ap_clk(aclk)
);
nfa_accept_samples_generic_hw_nfa_initials_buckets_if #(
.C_ID_WIDTH(C_M_AXI_NFA_INITIALS_BUCKETS_ID_WIDTH),
.C_ADDR_WIDTH(C_M_AXI_NFA_INITIALS_BUCKETS_ADDR_WIDTH),
.C_DATA_WIDTH(C_M_AXI_NFA_INITIALS_BUCKETS_DATA_WIDTH),
.C_AWUSER_WIDTH(C_M_AXI_NFA_INITIALS_BUCKETS_AWUSER_WIDTH),
.C_ARUSER_WIDTH(C_M_AXI_NFA_INITIALS_BUCKETS_ARUSER_WIDTH),
.C_WUSER_WIDTH(C_M_AXI_NFA_INITIALS_BUCKETS_WUSER_WIDTH),
.C_RUSER_WIDTH(C_M_AXI_NFA_INITIALS_BUCKETS_RUSER_WIDTH),
.C_BUSER_WIDTH(C_M_AXI_NFA_INITIALS_BUCKETS_BUSER_WIDTH),
.C_USER_DATA_WIDTH(C_M_AXI_NFA_INITIALS_BUCKETS_USER_DATA_WIDTH),
.C_TARGET_ADDR(C_M_AXI_NFA_INITIALS_BUCKETS_TARGET_ADDR),
.C_USER_VALUE(C_M_AXI_NFA_INITIALS_BUCKETS_USER_VALUE),
.C_PROT_VALUE(C_M_AXI_NFA_INITIALS_BUCKETS_PROT_VALUE),
.C_CACHE_VALUE(C_M_AXI_NFA_INITIALS_BUCKETS_CACHE_VALUE))
nfa_accept_samples_generic_hw_nfa_initials_buckets_if_U(
.ACLK(aclk),
.ARESETN(aresetn),
.USER_datain(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_datain),
.USER_dataout(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_dataout),
.USER_address(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_address),
.USER_size(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_size),
.USER_req_din(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_req_din),
.USER_req_full_n(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_req_full_n),
.USER_req_write(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_req_write),
.USER_rsp_empty_n(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_rsp_empty_n),
.USER_rsp_read(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_rsp_read),
.AWID(m_axi_nfa_initials_buckets_AWID),
.AWADDR(m_axi_nfa_initials_buckets_AWADDR),
.AWLEN(m_axi_nfa_initials_buckets_AWLEN),
.AWSIZE(m_axi_nfa_initials_buckets_AWSIZE),
.AWBURST(m_axi_nfa_initials_buckets_AWBURST),
.AWLOCK(m_axi_nfa_initials_buckets_AWLOCK),
.AWCACHE(m_axi_nfa_initials_buckets_AWCACHE),
.AWPROT(m_axi_nfa_initials_buckets_AWPROT),
.AWQOS(m_axi_nfa_initials_buckets_AWQOS),
.AWUSER(m_axi_nfa_initials_buckets_AWUSER),
.AWVALID(m_axi_nfa_initials_buckets_AWVALID),
.AWREADY(m_axi_nfa_initials_buckets_AWREADY),
.WDATA(m_axi_nfa_initials_buckets_WDATA),
.WSTRB(m_axi_nfa_initials_buckets_WSTRB),
.WLAST(m_axi_nfa_initials_buckets_WLAST),
.WUSER(m_axi_nfa_initials_buckets_WUSER),
.WVALID(m_axi_nfa_initials_buckets_WVALID),
.WREADY(m_axi_nfa_initials_buckets_WREADY),
.BID(m_axi_nfa_initials_buckets_BID),
.BRESP(m_axi_nfa_initials_buckets_BRESP),
.BUSER(m_axi_nfa_initials_buckets_BUSER),
.BVALID(m_axi_nfa_initials_buckets_BVALID),
.BREADY(m_axi_nfa_initials_buckets_BREADY),
.ARID(m_axi_nfa_initials_buckets_ARID),
.ARADDR(m_axi_nfa_initials_buckets_ARADDR),
.ARLEN(m_axi_nfa_initials_buckets_ARLEN),
.ARSIZE(m_axi_nfa_initials_buckets_ARSIZE),
.ARBURST(m_axi_nfa_initials_buckets_ARBURST),
.ARLOCK(m_axi_nfa_initials_buckets_ARLOCK),
.ARCACHE(m_axi_nfa_initials_buckets_ARCACHE),
.ARPROT(m_axi_nfa_initials_buckets_ARPROT),
.ARQOS(m_axi_nfa_initials_buckets_ARQOS),
.ARUSER(m_axi_nfa_initials_buckets_ARUSER),
.ARVALID(m_axi_nfa_initials_buckets_ARVALID),
.ARREADY(m_axi_nfa_initials_buckets_ARREADY),
.RID(m_axi_nfa_initials_buckets_RID),
.RDATA(m_axi_nfa_initials_buckets_RDATA),
.RRESP(m_axi_nfa_initials_buckets_RRESP),
.RLAST(m_axi_nfa_initials_buckets_RLAST),
.RUSER(m_axi_nfa_initials_buckets_RUSER),
.RVALID(m_axi_nfa_initials_buckets_RVALID),
.RREADY(m_axi_nfa_initials_buckets_RREADY));
nfa_accept_samples_generic_hw_nfa_finals_buckets_if #(
.C_ID_WIDTH(C_M_AXI_NFA_FINALS_BUCKETS_ID_WIDTH),
.C_ADDR_WIDTH(C_M_AXI_NFA_FINALS_BUCKETS_ADDR_WIDTH),
.C_DATA_WIDTH(C_M_AXI_NFA_FINALS_BUCKETS_DATA_WIDTH),
.C_AWUSER_WIDTH(C_M_AXI_NFA_FINALS_BUCKETS_AWUSER_WIDTH),
.C_ARUSER_WIDTH(C_M_AXI_NFA_FINALS_BUCKETS_ARUSER_WIDTH),
.C_WUSER_WIDTH(C_M_AXI_NFA_FINALS_BUCKETS_WUSER_WIDTH),
.C_RUSER_WIDTH(C_M_AXI_NFA_FINALS_BUCKETS_RUSER_WIDTH),
.C_BUSER_WIDTH(C_M_AXI_NFA_FINALS_BUCKETS_BUSER_WIDTH),
.C_USER_DATA_WIDTH(C_M_AXI_NFA_FINALS_BUCKETS_USER_DATA_WIDTH),
.C_TARGET_ADDR(C_M_AXI_NFA_FINALS_BUCKETS_TARGET_ADDR),
.C_USER_VALUE(C_M_AXI_NFA_FINALS_BUCKETS_USER_VALUE),
.C_PROT_VALUE(C_M_AXI_NFA_FINALS_BUCKETS_PROT_VALUE),
.C_CACHE_VALUE(C_M_AXI_NFA_FINALS_BUCKETS_CACHE_VALUE))
nfa_accept_samples_generic_hw_nfa_finals_buckets_if_U(
.ACLK(aclk),
.ARESETN(aresetn),
.USER_datain(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_datain),
.USER_dataout(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_dataout),
.USER_address(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_address),
.USER_size(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_size),
.USER_req_din(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_req_din),
.USER_req_full_n(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_req_full_n),
.USER_req_write(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_req_write),
.USER_rsp_empty_n(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_rsp_empty_n),
.USER_rsp_read(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_rsp_read),
.AWID(m_axi_nfa_finals_buckets_AWID),
.AWADDR(m_axi_nfa_finals_buckets_AWADDR),
.AWLEN(m_axi_nfa_finals_buckets_AWLEN),
.AWSIZE(m_axi_nfa_finals_buckets_AWSIZE),
.AWBURST(m_axi_nfa_finals_buckets_AWBURST),
.AWLOCK(m_axi_nfa_finals_buckets_AWLOCK),
.AWCACHE(m_axi_nfa_finals_buckets_AWCACHE),
.AWPROT(m_axi_nfa_finals_buckets_AWPROT),
.AWQOS(m_axi_nfa_finals_buckets_AWQOS),
.AWUSER(m_axi_nfa_finals_buckets_AWUSER),
.AWVALID(m_axi_nfa_finals_buckets_AWVALID),
.AWREADY(m_axi_nfa_finals_buckets_AWREADY),
.WDATA(m_axi_nfa_finals_buckets_WDATA),
.WSTRB(m_axi_nfa_finals_buckets_WSTRB),
.WLAST(m_axi_nfa_finals_buckets_WLAST),
.WUSER(m_axi_nfa_finals_buckets_WUSER),
.WVALID(m_axi_nfa_finals_buckets_WVALID),
.WREADY(m_axi_nfa_finals_buckets_WREADY),
.BID(m_axi_nfa_finals_buckets_BID),
.BRESP(m_axi_nfa_finals_buckets_BRESP),
.BUSER(m_axi_nfa_finals_buckets_BUSER),
.BVALID(m_axi_nfa_finals_buckets_BVALID),
.BREADY(m_axi_nfa_finals_buckets_BREADY),
.ARID(m_axi_nfa_finals_buckets_ARID),
.ARADDR(m_axi_nfa_finals_buckets_ARADDR),
.ARLEN(m_axi_nfa_finals_buckets_ARLEN),
.ARSIZE(m_axi_nfa_finals_buckets_ARSIZE),
.ARBURST(m_axi_nfa_finals_buckets_ARBURST),
.ARLOCK(m_axi_nfa_finals_buckets_ARLOCK),
.ARCACHE(m_axi_nfa_finals_buckets_ARCACHE),
.ARPROT(m_axi_nfa_finals_buckets_ARPROT),
.ARQOS(m_axi_nfa_finals_buckets_ARQOS),
.ARUSER(m_axi_nfa_finals_buckets_ARUSER),
.ARVALID(m_axi_nfa_finals_buckets_ARVALID),
.ARREADY(m_axi_nfa_finals_buckets_ARREADY),
.RID(m_axi_nfa_finals_buckets_RID),
.RDATA(m_axi_nfa_finals_buckets_RDATA),
.RRESP(m_axi_nfa_finals_buckets_RRESP),
.RLAST(m_axi_nfa_finals_buckets_RLAST),
.RUSER(m_axi_nfa_finals_buckets_RUSER),
.RVALID(m_axi_nfa_finals_buckets_RVALID),
.RREADY(m_axi_nfa_finals_buckets_RREADY));
nfa_accept_samples_generic_hw_nfa_forward_buckets_if #(
.C_ID_WIDTH(C_M_AXI_NFA_FORWARD_BUCKETS_ID_WIDTH),
.C_ADDR_WIDTH(C_M_AXI_NFA_FORWARD_BUCKETS_ADDR_WIDTH),
.C_DATA_WIDTH(C_M_AXI_NFA_FORWARD_BUCKETS_DATA_WIDTH),
.C_AWUSER_WIDTH(C_M_AXI_NFA_FORWARD_BUCKETS_AWUSER_WIDTH),
.C_ARUSER_WIDTH(C_M_AXI_NFA_FORWARD_BUCKETS_ARUSER_WIDTH),
.C_WUSER_WIDTH(C_M_AXI_NFA_FORWARD_BUCKETS_WUSER_WIDTH),
.C_RUSER_WIDTH(C_M_AXI_NFA_FORWARD_BUCKETS_RUSER_WIDTH),
.C_BUSER_WIDTH(C_M_AXI_NFA_FORWARD_BUCKETS_BUSER_WIDTH),
.C_USER_DATA_WIDTH(C_M_AXI_NFA_FORWARD_BUCKETS_USER_DATA_WIDTH),
.C_TARGET_ADDR(C_M_AXI_NFA_FORWARD_BUCKETS_TARGET_ADDR),
.C_USER_VALUE(C_M_AXI_NFA_FORWARD_BUCKETS_USER_VALUE),
.C_PROT_VALUE(C_M_AXI_NFA_FORWARD_BUCKETS_PROT_VALUE),
.C_CACHE_VALUE(C_M_AXI_NFA_FORWARD_BUCKETS_CACHE_VALUE))
nfa_accept_samples_generic_hw_nfa_forward_buckets_if_U(
.ACLK(aclk),
.ARESETN(aresetn),
.USER_datain(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_datain),
.USER_dataout(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_dataout),
.USER_address(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_address),
.USER_size(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_size),
.USER_req_din(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_req_din),
.USER_req_full_n(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_req_full_n),
.USER_req_write(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_req_write),
.USER_rsp_empty_n(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_rsp_empty_n),
.USER_rsp_read(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_rsp_read),
.AWID(m_axi_nfa_forward_buckets_AWID),
.AWADDR(m_axi_nfa_forward_buckets_AWADDR),
.AWLEN(m_axi_nfa_forward_buckets_AWLEN),
.AWSIZE(m_axi_nfa_forward_buckets_AWSIZE),
.AWBURST(m_axi_nfa_forward_buckets_AWBURST),
.AWLOCK(m_axi_nfa_forward_buckets_AWLOCK),
.AWCACHE(m_axi_nfa_forward_buckets_AWCACHE),
.AWPROT(m_axi_nfa_forward_buckets_AWPROT),
.AWQOS(m_axi_nfa_forward_buckets_AWQOS),
.AWUSER(m_axi_nfa_forward_buckets_AWUSER),
.AWVALID(m_axi_nfa_forward_buckets_AWVALID),
.AWREADY(m_axi_nfa_forward_buckets_AWREADY),
.WDATA(m_axi_nfa_forward_buckets_WDATA),
.WSTRB(m_axi_nfa_forward_buckets_WSTRB),
.WLAST(m_axi_nfa_forward_buckets_WLAST),
.WUSER(m_axi_nfa_forward_buckets_WUSER),
.WVALID(m_axi_nfa_forward_buckets_WVALID),
.WREADY(m_axi_nfa_forward_buckets_WREADY),
.BID(m_axi_nfa_forward_buckets_BID),
.BRESP(m_axi_nfa_forward_buckets_BRESP),
.BUSER(m_axi_nfa_forward_buckets_BUSER),
.BVALID(m_axi_nfa_forward_buckets_BVALID),
.BREADY(m_axi_nfa_forward_buckets_BREADY),
.ARID(m_axi_nfa_forward_buckets_ARID),
.ARADDR(m_axi_nfa_forward_buckets_ARADDR),
.ARLEN(m_axi_nfa_forward_buckets_ARLEN),
.ARSIZE(m_axi_nfa_forward_buckets_ARSIZE),
.ARBURST(m_axi_nfa_forward_buckets_ARBURST),
.ARLOCK(m_axi_nfa_forward_buckets_ARLOCK),
.ARCACHE(m_axi_nfa_forward_buckets_ARCACHE),
.ARPROT(m_axi_nfa_forward_buckets_ARPROT),
.ARQOS(m_axi_nfa_forward_buckets_ARQOS),
.ARUSER(m_axi_nfa_forward_buckets_ARUSER),
.ARVALID(m_axi_nfa_forward_buckets_ARVALID),
.ARREADY(m_axi_nfa_forward_buckets_ARREADY),
.RID(m_axi_nfa_forward_buckets_RID),
.RDATA(m_axi_nfa_forward_buckets_RDATA),
.RRESP(m_axi_nfa_forward_buckets_RRESP),
.RLAST(m_axi_nfa_forward_buckets_RLAST),
.RUSER(m_axi_nfa_forward_buckets_RUSER),
.RVALID(m_axi_nfa_forward_buckets_RVALID),
.RREADY(m_axi_nfa_forward_buckets_RREADY));
nfa_accept_samples_generic_hw_sample_buffer_if #(
.C_ID_WIDTH(C_M_AXI_SAMPLE_BUFFER_ID_WIDTH),
.C_ADDR_WIDTH(C_M_AXI_SAMPLE_BUFFER_ADDR_WIDTH),
.C_DATA_WIDTH(C_M_AXI_SAMPLE_BUFFER_DATA_WIDTH),
.C_AWUSER_WIDTH(C_M_AXI_SAMPLE_BUFFER_AWUSER_WIDTH),
.C_ARUSER_WIDTH(C_M_AXI_SAMPLE_BUFFER_ARUSER_WIDTH),
.C_WUSER_WIDTH(C_M_AXI_SAMPLE_BUFFER_WUSER_WIDTH),
.C_RUSER_WIDTH(C_M_AXI_SAMPLE_BUFFER_RUSER_WIDTH),
.C_BUSER_WIDTH(C_M_AXI_SAMPLE_BUFFER_BUSER_WIDTH),
.C_USER_DATA_WIDTH(C_M_AXI_SAMPLE_BUFFER_USER_DATA_WIDTH),
.C_TARGET_ADDR(C_M_AXI_SAMPLE_BUFFER_TARGET_ADDR),
.C_USER_VALUE(C_M_AXI_SAMPLE_BUFFER_USER_VALUE),
.C_PROT_VALUE(C_M_AXI_SAMPLE_BUFFER_PROT_VALUE),
.C_CACHE_VALUE(C_M_AXI_SAMPLE_BUFFER_CACHE_VALUE))
nfa_accept_samples_generic_hw_sample_buffer_if_U(
.ACLK(aclk),
.ARESETN(aresetn),
.USER_datain(sig_nfa_accept_samples_generic_hw_sample_buffer_datain),
.USER_dataout(sig_nfa_accept_samples_generic_hw_sample_buffer_dataout),
.USER_address(sig_nfa_accept_samples_generic_hw_sample_buffer_address),
.USER_size(sig_nfa_accept_samples_generic_hw_sample_buffer_size),
.USER_req_din(sig_nfa_accept_samples_generic_hw_sample_buffer_req_din),
.USER_req_full_n(sig_nfa_accept_samples_generic_hw_sample_buffer_req_full_n),
.USER_req_write(sig_nfa_accept_samples_generic_hw_sample_buffer_req_write),
.USER_rsp_empty_n(sig_nfa_accept_samples_generic_hw_sample_buffer_rsp_empty_n),
.USER_rsp_read(sig_nfa_accept_samples_generic_hw_sample_buffer_rsp_read),
.AWID(m_axi_sample_buffer_AWID),
.AWADDR(m_axi_sample_buffer_AWADDR),
.AWLEN(m_axi_sample_buffer_AWLEN),
.AWSIZE(m_axi_sample_buffer_AWSIZE),
.AWBURST(m_axi_sample_buffer_AWBURST),
.AWLOCK(m_axi_sample_buffer_AWLOCK),
.AWCACHE(m_axi_sample_buffer_AWCACHE),
.AWPROT(m_axi_sample_buffer_AWPROT),
.AWQOS(m_axi_sample_buffer_AWQOS),
.AWUSER(m_axi_sample_buffer_AWUSER),
.AWVALID(m_axi_sample_buffer_AWVALID),
.AWREADY(m_axi_sample_buffer_AWREADY),
.WDATA(m_axi_sample_buffer_WDATA),
.WSTRB(m_axi_sample_buffer_WSTRB),
.WLAST(m_axi_sample_buffer_WLAST),
.WUSER(m_axi_sample_buffer_WUSER),
.WVALID(m_axi_sample_buffer_WVALID),
.WREADY(m_axi_sample_buffer_WREADY),
.BID(m_axi_sample_buffer_BID),
.BRESP(m_axi_sample_buffer_BRESP),
.BUSER(m_axi_sample_buffer_BUSER),
.BVALID(m_axi_sample_buffer_BVALID),
.BREADY(m_axi_sample_buffer_BREADY),
.ARID(m_axi_sample_buffer_ARID),
.ARADDR(m_axi_sample_buffer_ARADDR),
.ARLEN(m_axi_sample_buffer_ARLEN),
.ARSIZE(m_axi_sample_buffer_ARSIZE),
.ARBURST(m_axi_sample_buffer_ARBURST),
.ARLOCK(m_axi_sample_buffer_ARLOCK),
.ARCACHE(m_axi_sample_buffer_ARCACHE),
.ARPROT(m_axi_sample_buffer_ARPROT),
.ARQOS(m_axi_sample_buffer_ARQOS),
.ARUSER(m_axi_sample_buffer_ARUSER),
.ARVALID(m_axi_sample_buffer_ARVALID),
.ARREADY(m_axi_sample_buffer_ARREADY),
.RID(m_axi_sample_buffer_RID),
.RDATA(m_axi_sample_buffer_RDATA),
.RRESP(m_axi_sample_buffer_RRESP),
.RLAST(m_axi_sample_buffer_RLAST),
.RUSER(m_axi_sample_buffer_RUSER),
.RVALID(m_axi_sample_buffer_RVALID),
.RREADY(m_axi_sample_buffer_RREADY));
nfa_accept_samples_generic_hw_indices_begin_if #(
.C_ID_WIDTH(C_M_AXI_INDICES_BEGIN_ID_WIDTH),
.C_ADDR_WIDTH(C_M_AXI_INDICES_BEGIN_ADDR_WIDTH),
.C_DATA_WIDTH(C_M_AXI_INDICES_BEGIN_DATA_WIDTH),
.C_AWUSER_WIDTH(C_M_AXI_INDICES_BEGIN_AWUSER_WIDTH),
.C_ARUSER_WIDTH(C_M_AXI_INDICES_BEGIN_ARUSER_WIDTH),
.C_WUSER_WIDTH(C_M_AXI_INDICES_BEGIN_WUSER_WIDTH),
.C_RUSER_WIDTH(C_M_AXI_INDICES_BEGIN_RUSER_WIDTH),
.C_BUSER_WIDTH(C_M_AXI_INDICES_BEGIN_BUSER_WIDTH),
.C_USER_DATA_WIDTH(C_M_AXI_INDICES_BEGIN_USER_DATA_WIDTH),
.C_TARGET_ADDR(C_M_AXI_INDICES_BEGIN_TARGET_ADDR),
.C_USER_VALUE(C_M_AXI_INDICES_BEGIN_USER_VALUE),
.C_PROT_VALUE(C_M_AXI_INDICES_BEGIN_PROT_VALUE),
.C_CACHE_VALUE(C_M_AXI_INDICES_BEGIN_CACHE_VALUE))
nfa_accept_samples_generic_hw_indices_begin_if_U(
.ACLK(aclk),
.ARESETN(aresetn),
.USER_datain(sig_nfa_accept_samples_generic_hw_indices_begin_datain),
.USER_dataout(sig_nfa_accept_samples_generic_hw_indices_begin_dataout),
.USER_address(sig_nfa_accept_samples_generic_hw_indices_begin_address),
.USER_size(sig_nfa_accept_samples_generic_hw_indices_begin_size),
.USER_req_din(sig_nfa_accept_samples_generic_hw_indices_begin_req_din),
.USER_req_full_n(sig_nfa_accept_samples_generic_hw_indices_begin_req_full_n),
.USER_req_write(sig_nfa_accept_samples_generic_hw_indices_begin_req_write),
.USER_rsp_empty_n(sig_nfa_accept_samples_generic_hw_indices_begin_rsp_empty_n),
.USER_rsp_read(sig_nfa_accept_samples_generic_hw_indices_begin_rsp_read),
.AWID(m_axi_indices_begin_AWID),
.AWADDR(m_axi_indices_begin_AWADDR),
.AWLEN(m_axi_indices_begin_AWLEN),
.AWSIZE(m_axi_indices_begin_AWSIZE),
.AWBURST(m_axi_indices_begin_AWBURST),
.AWLOCK(m_axi_indices_begin_AWLOCK),
.AWCACHE(m_axi_indices_begin_AWCACHE),
.AWPROT(m_axi_indices_begin_AWPROT),
.AWQOS(m_axi_indices_begin_AWQOS),
.AWUSER(m_axi_indices_begin_AWUSER),
.AWVALID(m_axi_indices_begin_AWVALID),
.AWREADY(m_axi_indices_begin_AWREADY),
.WDATA(m_axi_indices_begin_WDATA),
.WSTRB(m_axi_indices_begin_WSTRB),
.WLAST(m_axi_indices_begin_WLAST),
.WUSER(m_axi_indices_begin_WUSER),
.WVALID(m_axi_indices_begin_WVALID),
.WREADY(m_axi_indices_begin_WREADY),
.BID(m_axi_indices_begin_BID),
.BRESP(m_axi_indices_begin_BRESP),
.BUSER(m_axi_indices_begin_BUSER),
.BVALID(m_axi_indices_begin_BVALID),
.BREADY(m_axi_indices_begin_BREADY),
.ARID(m_axi_indices_begin_ARID),
.ARADDR(m_axi_indices_begin_ARADDR),
.ARLEN(m_axi_indices_begin_ARLEN),
.ARSIZE(m_axi_indices_begin_ARSIZE),
.ARBURST(m_axi_indices_begin_ARBURST),
.ARLOCK(m_axi_indices_begin_ARLOCK),
.ARCACHE(m_axi_indices_begin_ARCACHE),
.ARPROT(m_axi_indices_begin_ARPROT),
.ARQOS(m_axi_indices_begin_ARQOS),
.ARUSER(m_axi_indices_begin_ARUSER),
.ARVALID(m_axi_indices_begin_ARVALID),
.ARREADY(m_axi_indices_begin_ARREADY),
.RID(m_axi_indices_begin_RID),
.RDATA(m_axi_indices_begin_RDATA),
.RRESP(m_axi_indices_begin_RRESP),
.RLAST(m_axi_indices_begin_RLAST),
.RUSER(m_axi_indices_begin_RUSER),
.RVALID(m_axi_indices_begin_RVALID),
.RREADY(m_axi_indices_begin_RREADY));
nfa_accept_samples_generic_hw_indices_samples_if #(
.C_ID_WIDTH(C_M_AXI_INDICES_SAMPLES_ID_WIDTH),
.C_ADDR_WIDTH(C_M_AXI_INDICES_SAMPLES_ADDR_WIDTH),
.C_DATA_WIDTH(C_M_AXI_INDICES_SAMPLES_DATA_WIDTH),
.C_AWUSER_WIDTH(C_M_AXI_INDICES_SAMPLES_AWUSER_WIDTH),
.C_ARUSER_WIDTH(C_M_AXI_INDICES_SAMPLES_ARUSER_WIDTH),
.C_WUSER_WIDTH(C_M_AXI_INDICES_SAMPLES_WUSER_WIDTH),
.C_RUSER_WIDTH(C_M_AXI_INDICES_SAMPLES_RUSER_WIDTH),
.C_BUSER_WIDTH(C_M_AXI_INDICES_SAMPLES_BUSER_WIDTH),
.C_USER_DATA_WIDTH(C_M_AXI_INDICES_SAMPLES_USER_DATA_WIDTH),
.C_TARGET_ADDR(C_M_AXI_INDICES_SAMPLES_TARGET_ADDR),
.C_USER_VALUE(C_M_AXI_INDICES_SAMPLES_USER_VALUE),
.C_PROT_VALUE(C_M_AXI_INDICES_SAMPLES_PROT_VALUE),
.C_CACHE_VALUE(C_M_AXI_INDICES_SAMPLES_CACHE_VALUE))
nfa_accept_samples_generic_hw_indices_samples_if_U(
.ACLK(aclk),
.ARESETN(aresetn),
.USER_datain(sig_nfa_accept_samples_generic_hw_indices_samples_datain),
.USER_dataout(sig_nfa_accept_samples_generic_hw_indices_samples_dataout),
.USER_address(sig_nfa_accept_samples_generic_hw_indices_samples_address),
.USER_size(sig_nfa_accept_samples_generic_hw_indices_samples_size),
.USER_req_din(sig_nfa_accept_samples_generic_hw_indices_samples_req_din),
.USER_req_full_n(sig_nfa_accept_samples_generic_hw_indices_samples_req_full_n),
.USER_req_write(sig_nfa_accept_samples_generic_hw_indices_samples_req_write),
.USER_rsp_empty_n(sig_nfa_accept_samples_generic_hw_indices_samples_rsp_empty_n),
.USER_rsp_read(sig_nfa_accept_samples_generic_hw_indices_samples_rsp_read),
.AWID(m_axi_indices_samples_AWID),
.AWADDR(m_axi_indices_samples_AWADDR),
.AWLEN(m_axi_indices_samples_AWLEN),
.AWSIZE(m_axi_indices_samples_AWSIZE),
.AWBURST(m_axi_indices_samples_AWBURST),
.AWLOCK(m_axi_indices_samples_AWLOCK),
.AWCACHE(m_axi_indices_samples_AWCACHE),
.AWPROT(m_axi_indices_samples_AWPROT),
.AWQOS(m_axi_indices_samples_AWQOS),
.AWUSER(m_axi_indices_samples_AWUSER),
.AWVALID(m_axi_indices_samples_AWVALID),
.AWREADY(m_axi_indices_samples_AWREADY),
.WDATA(m_axi_indices_samples_WDATA),
.WSTRB(m_axi_indices_samples_WSTRB),
.WLAST(m_axi_indices_samples_WLAST),
.WUSER(m_axi_indices_samples_WUSER),
.WVALID(m_axi_indices_samples_WVALID),
.WREADY(m_axi_indices_samples_WREADY),
.BID(m_axi_indices_samples_BID),
.BRESP(m_axi_indices_samples_BRESP),
.BUSER(m_axi_indices_samples_BUSER),
.BVALID(m_axi_indices_samples_BVALID),
.BREADY(m_axi_indices_samples_BREADY),
.ARID(m_axi_indices_samples_ARID),
.ARADDR(m_axi_indices_samples_ARADDR),
.ARLEN(m_axi_indices_samples_ARLEN),
.ARSIZE(m_axi_indices_samples_ARSIZE),
.ARBURST(m_axi_indices_samples_ARBURST),
.ARLOCK(m_axi_indices_samples_ARLOCK),
.ARCACHE(m_axi_indices_samples_ARCACHE),
.ARPROT(m_axi_indices_samples_ARPROT),
.ARQOS(m_axi_indices_samples_ARQOS),
.ARUSER(m_axi_indices_samples_ARUSER),
.ARVALID(m_axi_indices_samples_ARVALID),
.ARREADY(m_axi_indices_samples_ARREADY),
.RID(m_axi_indices_samples_RID),
.RDATA(m_axi_indices_samples_RDATA),
.RRESP(m_axi_indices_samples_RRESP),
.RLAST(m_axi_indices_samples_RLAST),
.RUSER(m_axi_indices_samples_RUSER),
.RVALID(m_axi_indices_samples_RVALID),
.RREADY(m_axi_indices_samples_RREADY));
nfa_accept_samples_generic_hw_indices_stride_if #(
.C_ID_WIDTH(C_M_AXI_INDICES_STRIDE_ID_WIDTH),
.C_ADDR_WIDTH(C_M_AXI_INDICES_STRIDE_ADDR_WIDTH),
.C_DATA_WIDTH(C_M_AXI_INDICES_STRIDE_DATA_WIDTH),
.C_AWUSER_WIDTH(C_M_AXI_INDICES_STRIDE_AWUSER_WIDTH),
.C_ARUSER_WIDTH(C_M_AXI_INDICES_STRIDE_ARUSER_WIDTH),
.C_WUSER_WIDTH(C_M_AXI_INDICES_STRIDE_WUSER_WIDTH),
.C_RUSER_WIDTH(C_M_AXI_INDICES_STRIDE_RUSER_WIDTH),
.C_BUSER_WIDTH(C_M_AXI_INDICES_STRIDE_BUSER_WIDTH),
.C_USER_DATA_WIDTH(C_M_AXI_INDICES_STRIDE_USER_DATA_WIDTH),
.C_TARGET_ADDR(C_M_AXI_INDICES_STRIDE_TARGET_ADDR),
.C_USER_VALUE(C_M_AXI_INDICES_STRIDE_USER_VALUE),
.C_PROT_VALUE(C_M_AXI_INDICES_STRIDE_PROT_VALUE),
.C_CACHE_VALUE(C_M_AXI_INDICES_STRIDE_CACHE_VALUE))
nfa_accept_samples_generic_hw_indices_stride_if_U(
.ACLK(aclk),
.ARESETN(aresetn),
.USER_datain(sig_nfa_accept_samples_generic_hw_indices_stride_datain),
.USER_dataout(sig_nfa_accept_samples_generic_hw_indices_stride_dataout),
.USER_address(sig_nfa_accept_samples_generic_hw_indices_stride_address),
.USER_size(sig_nfa_accept_samples_generic_hw_indices_stride_size),
.USER_req_din(sig_nfa_accept_samples_generic_hw_indices_stride_req_din),
.USER_req_full_n(sig_nfa_accept_samples_generic_hw_indices_stride_req_full_n),
.USER_req_write(sig_nfa_accept_samples_generic_hw_indices_stride_req_write),
.USER_rsp_empty_n(sig_nfa_accept_samples_generic_hw_indices_stride_rsp_empty_n),
.USER_rsp_read(sig_nfa_accept_samples_generic_hw_indices_stride_rsp_read),
.AWID(m_axi_indices_stride_AWID),
.AWADDR(m_axi_indices_stride_AWADDR),
.AWLEN(m_axi_indices_stride_AWLEN),
.AWSIZE(m_axi_indices_stride_AWSIZE),
.AWBURST(m_axi_indices_stride_AWBURST),
.AWLOCK(m_axi_indices_stride_AWLOCK),
.AWCACHE(m_axi_indices_stride_AWCACHE),
.AWPROT(m_axi_indices_stride_AWPROT),
.AWQOS(m_axi_indices_stride_AWQOS),
.AWUSER(m_axi_indices_stride_AWUSER),
.AWVALID(m_axi_indices_stride_AWVALID),
.AWREADY(m_axi_indices_stride_AWREADY),
.WDATA(m_axi_indices_stride_WDATA),
.WSTRB(m_axi_indices_stride_WSTRB),
.WLAST(m_axi_indices_stride_WLAST),
.WUSER(m_axi_indices_stride_WUSER),
.WVALID(m_axi_indices_stride_WVALID),
.WREADY(m_axi_indices_stride_WREADY),
.BID(m_axi_indices_stride_BID),
.BRESP(m_axi_indices_stride_BRESP),
.BUSER(m_axi_indices_stride_BUSER),
.BVALID(m_axi_indices_stride_BVALID),
.BREADY(m_axi_indices_stride_BREADY),
.ARID(m_axi_indices_stride_ARID),
.ARADDR(m_axi_indices_stride_ARADDR),
.ARLEN(m_axi_indices_stride_ARLEN),
.ARSIZE(m_axi_indices_stride_ARSIZE),
.ARBURST(m_axi_indices_stride_ARBURST),
.ARLOCK(m_axi_indices_stride_ARLOCK),
.ARCACHE(m_axi_indices_stride_ARCACHE),
.ARPROT(m_axi_indices_stride_ARPROT),
.ARQOS(m_axi_indices_stride_ARQOS),
.ARUSER(m_axi_indices_stride_ARUSER),
.ARVALID(m_axi_indices_stride_ARVALID),
.ARREADY(m_axi_indices_stride_ARREADY),
.RID(m_axi_indices_stride_RID),
.RDATA(m_axi_indices_stride_RDATA),
.RRESP(m_axi_indices_stride_RRESP),
.RLAST(m_axi_indices_stride_RLAST),
.RUSER(m_axi_indices_stride_RUSER),
.RVALID(m_axi_indices_stride_RVALID),
.RREADY(m_axi_indices_stride_RREADY));
nfa_accept_samples_generic_hw_slv0_if #(
.C_ADDR_WIDTH(C_S_AXI_SLV0_ADDR_WIDTH),
.C_DATA_WIDTH(C_S_AXI_SLV0_DATA_WIDTH))
nfa_accept_samples_generic_hw_slv0_if_U(
.ACLK(aclk),
.ARESETN(aresetn),
.I_nfa_symbols(sig_nfa_accept_samples_generic_hw_nfa_symbols),
.I_sample_buffer_length(sig_nfa_accept_samples_generic_hw_sample_buffer_length),
.I_sample_length(sig_nfa_accept_samples_generic_hw_sample_length),
.I_i_size(sig_nfa_accept_samples_generic_hw_i_size),
.I_begin_index(sig_nfa_accept_samples_generic_hw_begin_index),
.I_begin_sample(sig_nfa_accept_samples_generic_hw_begin_sample),
.I_end_index(sig_nfa_accept_samples_generic_hw_end_index),
.I_end_sample(sig_nfa_accept_samples_generic_hw_end_sample),
.I_stop_on_first(sig_nfa_accept_samples_generic_hw_stop_on_first),
.I_accept(sig_nfa_accept_samples_generic_hw_accept),
.I_ap_start(sig_nfa_accept_samples_generic_hw_ap_start),
.O_ap_ready(sig_nfa_accept_samples_generic_hw_ap_ready),
.O_ap_done(sig_nfa_accept_samples_generic_hw_ap_done),
.O_ap_idle(sig_nfa_accept_samples_generic_hw_ap_idle),
.O_ap_return(sig_nfa_accept_samples_generic_hw_ap_return),
.AWADDR(s_axi_slv0_AWADDR),
.AWVALID(s_axi_slv0_AWVALID),
.AWREADY(s_axi_slv0_AWREADY),
.WDATA(s_axi_slv0_WDATA),
.WSTRB(s_axi_slv0_WSTRB),
.WVALID(s_axi_slv0_WVALID),
.WREADY(s_axi_slv0_WREADY),
.BRESP(s_axi_slv0_BRESP),
.BVALID(s_axi_slv0_BVALID),
.BREADY(s_axi_slv0_BREADY),
.ARADDR(s_axi_slv0_ARADDR),
.ARVALID(s_axi_slv0_ARVALID),
.ARREADY(s_axi_slv0_ARREADY),
.RDATA(s_axi_slv0_RDATA),
.RRESP(s_axi_slv0_RRESP),
.RVALID(s_axi_slv0_RVALID),
.RREADY(s_axi_slv0_RREADY),
.interrupt(interrupt));
nfa_accept_samples_generic_hw_ap_rst_if #(
.RESET_ACTIVE_LOW(RESET_ACTIVE_LOW))
ap_rst_if_U(
.dout(sig_nfa_accept_samples_generic_hw_ap_rst),
.din(aresetn));
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Compound ifdef test with else, exterior define
//
`define DOUBLE
module ifdef1;
reg error ;
`ifdef DOUBLE
`ifdef NOCODE
initial
begin
#20;
error = 1;
#20;
end
`else
initial
begin
#20;
error = 0;
#20;
end
`endif
`endif
initial
begin
#1;
error = 1;
#40;
if(error == 0)
$display("PASSED");
else
$display("FAILED");
end
endmodule // main
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:clk_gen:1.0
// IP Revision: 0
(* X_CORE_INFO = "clk_gen,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "design_1_clk_gen_0_0,clk_gen,{}" *)
(* CORE_GENERATION_INFO = "design_1_clk_gen_0_0,clk_gen,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=clk_gen,x_ipVersion=1.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,CLOCK_PERIOD=8.0,INITIAL_RESET_CLOCK_CYCLES=100,RESET_POLARITY=0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_clk_gen_0_0 (
clk,
sync_rst
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
output wire clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 sync_rst RST" *)
output wire sync_rst;
clk_gen #(
.CLOCK_PERIOD(8.0),
.INITIAL_RESET_CLOCK_CYCLES(100),
.RESET_POLARITY(0)
) inst (
.clk(clk),
.clk_n(),
.clk_p(),
.sync_rst(sync_rst)
);
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module minimac2 #(
parameter csr_addr = 4'h0
) (
input sys_clk,
input sys_rst,
/* CSR */
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output [31:0] csr_do,
/* IRQ */
output irq_rx,
output irq_tx,
/* WISHBONE to access RAM */
input [31:0] wb_adr_i,
output [31:0] wb_dat_o,
input [31:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
input wb_we_i,
/* To PHY */
input phy_tx_clk,
output [3:0] phy_tx_data,
output phy_tx_en,
output phy_tx_er,
input phy_rx_clk,
input [3:0] phy_rx_data,
input phy_dv,
input phy_rx_er,
input phy_col,
input phy_crs,
output phy_mii_clk,
inout phy_mii_data,
output phy_rst_n
);
wire [1:0] sys_rx_ready;
wire [1:0] sys_rx_done;
wire [10:0] sys_rx_count_0;
wire [10:0] sys_rx_count_1;
wire sys_tx_start;
wire sys_tx_done;
wire [10:0] sys_tx_count;
wire [1:0] phy_rx_ready;
wire [1:0] phy_rx_done;
wire [10:0] phy_rx_count_0;
wire [10:0] phy_rx_count_1;
wire phy_tx_start;
wire phy_tx_done;
wire [10:0] phy_tx_count;
minimac2_ctlif #(
.csr_addr(csr_addr)
) ctlif (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.irq_rx(irq_rx),
.irq_tx(irq_tx),
.rx_ready(sys_rx_ready),
.rx_done(sys_rx_done),
.rx_count_0(sys_rx_count_0),
.rx_count_1(sys_rx_count_1),
.tx_start(sys_tx_start),
.tx_done(sys_tx_done),
.tx_count(sys_tx_count),
.phy_mii_clk(phy_mii_clk),
.phy_mii_data(phy_mii_data),
.phy_rst_n(phy_rst_n)
);
minimac2_sync sync(
.sys_clk(sys_clk),
.phy_rx_clk(phy_rx_clk),
.phy_tx_clk(phy_tx_clk),
.sys_rx_ready(sys_rx_ready),
.sys_rx_done(sys_rx_done),
.sys_rx_count_0(sys_rx_count_0),
.sys_rx_count_1(sys_rx_count_1),
.sys_tx_start(sys_tx_start),
.sys_tx_done(sys_tx_done),
.sys_tx_count(sys_tx_count),
.phy_rx_ready(phy_rx_ready),
.phy_rx_done(phy_rx_done),
.phy_rx_count_0(phy_rx_count_0),
.phy_rx_count_1(phy_rx_count_1),
.phy_tx_start(phy_tx_start),
.phy_tx_done(phy_tx_done),
.phy_tx_count(phy_tx_count)
);
wire [7:0] rxb0_dat;
wire [10:0] rxb0_adr;
wire rxb0_we;
wire [7:0] rxb1_dat;
wire [10:0] rxb1_adr;
wire rxb1_we;
wire [7:0] txb_dat;
wire [10:0] txb_adr;
minimac2_memory memory(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.phy_rx_clk(phy_rx_clk),
.phy_tx_clk(phy_tx_clk),
.wb_adr_i(wb_adr_i),
.wb_dat_o(wb_dat_o),
.wb_dat_i(wb_dat_i),
.wb_sel_i(wb_sel_i),
.wb_stb_i(wb_stb_i),
.wb_cyc_i(wb_cyc_i),
.wb_ack_o(wb_ack_o),
.wb_we_i(wb_we_i),
.rxb0_dat(rxb0_dat),
.rxb0_adr(rxb0_adr),
.rxb0_we(rxb0_we),
.rxb1_dat(rxb1_dat),
.rxb1_adr(rxb1_adr),
.rxb1_we(rxb1_we),
.txb_dat(txb_dat),
.txb_adr(txb_adr)
);
minimac2_tx tx(
.phy_tx_clk(phy_tx_clk),
.tx_start(phy_tx_start),
.tx_done(phy_tx_done),
.tx_count(phy_tx_count),
.txb_dat(txb_dat),
.txb_adr(txb_adr),
.phy_tx_en(phy_tx_en),
.phy_tx_data(phy_tx_data)
);
assign phy_tx_er = 1'b0;
minimac2_rx rx(
.phy_rx_clk(phy_rx_clk),
.rx_ready(phy_rx_ready),
.rx_done(phy_rx_done),
.rx_count_0(phy_rx_count_0),
.rx_count_1(phy_rx_count_1),
.rxb0_dat(rxb0_dat),
.rxb0_adr(rxb0_adr),
.rxb0_we(rxb0_we),
.rxb1_dat(rxb1_dat),
.rxb1_adr(rxb1_adr),
.rxb1_we(rxb1_we),
.phy_dv(phy_dv),
.phy_rx_data(phy_rx_data),
.phy_rx_er(phy_rx_er)
);
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ps / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_altmemddr_0_controller_phy (
// inputs:
dqs_delay_ctrl_import,
dqs_offset_delay_ctrl,
global_reset_n,
hc_scan_ck,
hc_scan_din,
hc_scan_enable_access,
hc_scan_enable_dm,
hc_scan_enable_dq,
hc_scan_enable_dqs,
hc_scan_enable_dqs_config,
hc_scan_update,
local_address,
local_autopch_req,
local_be,
local_burstbegin,
local_multicast_req,
local_read_req,
local_refresh_chip,
local_refresh_req,
local_self_rfsh_chip,
local_self_rfsh_req,
local_size,
local_wdata,
local_write_req,
oct_ctl_rs_value,
oct_ctl_rt_value,
pll_phasecounterselect,
pll_phasestep,
pll_phaseupdown,
pll_reconfig,
pll_reconfig_counter_param,
pll_reconfig_counter_type,
pll_reconfig_data_in,
pll_reconfig_enable,
pll_reconfig_read_param,
pll_reconfig_soft_reset_en_n,
pll_reconfig_write_param,
pll_ref_clk,
soft_reset_n,
// outputs:
aux_full_rate_clk,
aux_half_rate_clk,
aux_scan_clk,
aux_scan_clk_reset_n,
dll_reference_clk,
dqs_delay_ctrl_export,
ecc_interrupt,
hc_scan_dout,
local_init_done,
local_power_down_ack,
local_rdata,
local_rdata_valid,
local_ready,
local_refresh_ack,
local_self_rfsh_ack,
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_clk,
mem_clk_n,
mem_cs_n,
mem_dm,
mem_dq,
mem_dqs,
mem_dqsn,
mem_odt,
mem_ras_n,
mem_reset_n,
mem_we_n,
phy_clk,
pll_phase_done,
pll_reconfig_busy,
pll_reconfig_clk,
pll_reconfig_data_out,
pll_reconfig_reset,
reset_phy_clk_n,
reset_request_n
)
;
output aux_full_rate_clk;
output aux_half_rate_clk;
output aux_scan_clk;
output aux_scan_clk_reset_n;
output dll_reference_clk;
output [ 5: 0] dqs_delay_ctrl_export;
output ecc_interrupt;
output [ 7: 0] hc_scan_dout;
output local_init_done;
output local_power_down_ack;
output [ 31: 0] local_rdata;
output local_rdata_valid;
output local_ready;
output local_refresh_ack;
output local_self_rfsh_ack;
output [ 13: 0] mem_addr;
output [ 1: 0] mem_ba;
output mem_cas_n;
output [ 0: 0] mem_cke;
inout [ 0: 0] mem_clk;
inout [ 0: 0] mem_clk_n;
output [ 0: 0] mem_cs_n;
output [ 0: 0] mem_dm;
inout [ 7: 0] mem_dq;
inout [ 0: 0] mem_dqs;
inout [ 0: 0] mem_dqsn;
output [ 0: 0] mem_odt;
output mem_ras_n;
output mem_reset_n;
output mem_we_n;
output phy_clk;
output pll_phase_done;
output pll_reconfig_busy;
output pll_reconfig_clk;
output [ 8: 0] pll_reconfig_data_out;
output pll_reconfig_reset;
output reset_phy_clk_n;
output reset_request_n;
input [ 5: 0] dqs_delay_ctrl_import;
input [ 5: 0] dqs_offset_delay_ctrl;
input global_reset_n;
input hc_scan_ck;
input [ 0: 0] hc_scan_din;
input hc_scan_enable_access;
input [ 0: 0] hc_scan_enable_dm;
input [ 7: 0] hc_scan_enable_dq;
input [ 0: 0] hc_scan_enable_dqs;
input [ 0: 0] hc_scan_enable_dqs_config;
input [ 0: 0] hc_scan_update;
input [ 23: 0] local_address;
input local_autopch_req;
input [ 3: 0] local_be;
input local_burstbegin;
input local_multicast_req;
input local_read_req;
input local_refresh_chip;
input local_refresh_req;
input local_self_rfsh_chip;
input local_self_rfsh_req;
input [ 2: 0] local_size;
input [ 31: 0] local_wdata;
input local_write_req;
input [ 13: 0] oct_ctl_rs_value;
input [ 13: 0] oct_ctl_rt_value;
input [ 3: 0] pll_phasecounterselect;
input pll_phasestep;
input pll_phaseupdown;
input pll_reconfig;
input [ 2: 0] pll_reconfig_counter_param;
input [ 3: 0] pll_reconfig_counter_type;
input [ 8: 0] pll_reconfig_data_in;
input pll_reconfig_enable;
input pll_reconfig_read_param;
input pll_reconfig_soft_reset_en_n;
input pll_reconfig_write_param;
input pll_ref_clk;
input soft_reset_n;
wire [ 27: 0] afi_addr;
wire [ 3: 0] afi_ba;
wire [ 1: 0] afi_cas_n;
wire [ 1: 0] afi_cke;
wire [ 1: 0] afi_cs_n;
wire afi_ctl_long_idle;
wire afi_ctl_refresh_done;
wire [ 3: 0] afi_dm;
wire [ 1: 0] afi_dqs_burst;
wire [ 1: 0] afi_odt;
wire [ 1: 0] afi_ras_n;
wire [ 31: 0] afi_rdata;
wire [ 1: 0] afi_rdata_en;
wire [ 1: 0] afi_rdata_en_full;
wire [ 1: 0] afi_rdata_valid;
wire [ 1: 0] afi_rst_n;
wire [ 31: 0] afi_wdata;
wire [ 1: 0] afi_wdata_valid;
wire [ 1: 0] afi_we_n;
wire [ 4: 0] afi_wlat;
wire aux_full_rate_clk;
wire aux_half_rate_clk;
wire aux_scan_clk;
wire aux_scan_clk_reset_n;
wire [ 31: 0] csr_rdata_sig;
wire csr_rdata_valid_sig;
wire csr_waitrequest_sig;
wire ctl_cal_byte_lane_sel_n;
wire ctl_cal_fail;
wire ctl_cal_req;
wire ctl_cal_success;
wire ctl_clk;
wire ctl_mem_clk_disable;
wire [ 4: 0] ctl_rlat;
wire [ 31: 0] dbg_rd_data_sig;
wire dbg_waitrequest_sig;
wire dll_reference_clk;
wire [ 5: 0] dqs_delay_ctrl_export;
wire ecc_interrupt;
wire [ 7: 0] hc_scan_dout;
wire local_init_done;
wire local_power_down_ack;
wire [ 31: 0] local_rdata;
wire local_rdata_valid;
wire local_ready;
wire local_refresh_ack;
wire local_self_rfsh_ack;
wire [ 13: 0] mem_addr;
wire [ 1: 0] mem_ba;
wire mem_cas_n;
wire [ 0: 0] mem_cke;
wire [ 0: 0] mem_clk;
wire [ 0: 0] mem_clk_n;
wire [ 0: 0] mem_cs_n;
wire [ 0: 0] mem_dm;
wire [ 7: 0] mem_dq;
wire [ 0: 0] mem_dqs;
wire [ 0: 0] mem_dqsn;
wire [ 0: 0] mem_odt;
wire mem_ras_n;
wire mem_reset_n;
wire mem_we_n;
wire phy_clk;
wire pll_phase_done;
wire pll_reconfig_busy;
wire pll_reconfig_clk;
wire [ 8: 0] pll_reconfig_data_out;
wire pll_reconfig_reset;
wire reset_ctl_clk_n;
wire reset_phy_clk_n;
wire reset_request_n;
assign phy_clk = ctl_clk;
assign reset_phy_clk_n = reset_ctl_clk_n;
nios_altmemddr_0_alt_mem_ddrx_controller_top nios_altmemddr_0_alt_mem_ddrx_controller_top_inst
(
.afi_addr (afi_addr),
.afi_ba (afi_ba),
.afi_cal_byte_lane_sel_n (ctl_cal_byte_lane_sel_n),
.afi_cal_fail (ctl_cal_fail),
.afi_cal_req (ctl_cal_req),
.afi_cal_success (ctl_cal_success),
.afi_cas_n (afi_cas_n),
.afi_cke (afi_cke),
.afi_cs_n (afi_cs_n),
.afi_ctl_long_idle (afi_ctl_long_idle),
.afi_ctl_refresh_done (afi_ctl_refresh_done),
.afi_dm (afi_dm),
.afi_dqs_burst (afi_dqs_burst),
.afi_mem_clk_disable (ctl_mem_clk_disable),
.afi_odt (afi_odt),
.afi_ras_n (afi_ras_n),
.afi_rdata (afi_rdata),
.afi_rdata_en (afi_rdata_en),
.afi_rdata_en_full (afi_rdata_en_full),
.afi_rdata_valid (afi_rdata_valid),
.afi_rlat (ctl_rlat),
.afi_rst_n (afi_rst_n),
.afi_seq_busy ({1{1'b0}}),
.afi_wdata (afi_wdata),
.afi_wdata_valid (afi_wdata_valid),
.afi_we_n (afi_we_n),
.afi_wlat (afi_wlat),
.clk (ctl_clk),
.csr_addr (16'b0),
.csr_be (4'b0),
.csr_beginbursttransfer (1'b0),
.csr_burst_count (1'b0),
.csr_rdata (csr_rdata_sig),
.csr_rdata_valid (csr_rdata_valid_sig),
.csr_read_req (1'b0),
.csr_waitrequest (csr_waitrequest_sig),
.csr_wdata (32'b0),
.csr_write_req (1'b0),
.ecc_interrupt (ecc_interrupt),
.half_clk (aux_half_rate_clk),
.local_address (local_address),
.local_autopch_req (local_autopch_req),
.local_beginbursttransfer (local_burstbegin),
.local_burstcount (local_size),
.local_byteenable (local_be),
.local_init_done (local_init_done),
.local_multicast (local_multicast_req),
.local_powerdn_ack (local_power_down_ack),
.local_powerdn_req (1'b0),
.local_priority (1'b1),
.local_read (local_read_req),
.local_readdata (local_rdata),
.local_readdatavalid (local_rdata_valid),
.local_ready (local_ready),
.local_refresh_ack (local_refresh_ack),
.local_refresh_chip (local_refresh_chip),
.local_refresh_req (local_refresh_req),
.local_self_rfsh_ack (local_self_rfsh_ack),
.local_self_rfsh_chip (local_self_rfsh_chip),
.local_self_rfsh_req (local_self_rfsh_req),
.local_write (local_write_req),
.local_writedata (local_wdata),
.reset_n (reset_ctl_clk_n)
);
nios_altmemddr_0_phy nios_altmemddr_0_phy_inst
(
.aux_full_rate_clk (aux_full_rate_clk),
.aux_half_rate_clk (aux_half_rate_clk),
.ctl_addr (afi_addr),
.ctl_ba (afi_ba),
.ctl_cal_byte_lane_sel_n (ctl_cal_byte_lane_sel_n),
.ctl_cal_fail (ctl_cal_fail),
.ctl_cal_req (ctl_cal_req),
.ctl_cal_success (ctl_cal_success),
.ctl_cas_n (afi_cas_n),
.ctl_cke (afi_cke),
.ctl_clk (ctl_clk),
.ctl_cs_n (afi_cs_n),
.ctl_dm (afi_dm),
.ctl_doing_rd (afi_rdata_en),
.ctl_dqs_burst (afi_dqs_burst),
.ctl_mem_clk_disable (ctl_mem_clk_disable),
.ctl_odt (afi_odt),
.ctl_ras_n (afi_ras_n),
.ctl_rdata (afi_rdata),
.ctl_rdata_valid (afi_rdata_valid),
.ctl_reset_n (reset_ctl_clk_n),
.ctl_rlat (ctl_rlat),
.ctl_rst_n (afi_rst_n),
.ctl_wdata (afi_wdata),
.ctl_wdata_valid (afi_wdata_valid),
.ctl_we_n (afi_we_n),
.ctl_wlat (afi_wlat),
.dbg_addr (13'b0),
.dbg_clk (ctl_clk),
.dbg_cs (1'b0),
.dbg_rd (1'b0),
.dbg_rd_data (dbg_rd_data_sig),
.dbg_reset_n (reset_ctl_clk_n),
.dbg_waitrequest (dbg_waitrequest_sig),
.dbg_wr (1'b0),
.dbg_wr_data (32'b0),
.global_reset_n (global_reset_n),
.mem_addr (mem_addr),
.mem_ba (mem_ba),
.mem_cas_n (mem_cas_n),
.mem_cke (mem_cke),
.mem_clk (mem_clk),
.mem_clk_n (mem_clk_n),
.mem_cs_n (mem_cs_n),
.mem_dm (mem_dm),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs),
.mem_dqs_n (mem_dqsn),
.mem_odt (mem_odt),
.mem_ras_n (mem_ras_n),
.mem_reset_n (mem_reset_n),
.mem_we_n (mem_we_n),
.pll_ref_clk (pll_ref_clk),
.reset_request_n (reset_request_n),
.soft_reset_n (soft_reset_n)
);
//<< start europa
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Fri Sep 22 20:11:26 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// c:/Projects/srio_test/srio_test/srio_test.srcs/sources_1/ip/tx_axis_gen/tx_axis_gen_stub.v
// Design : tx_axis_gen
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *)
module tx_axis_gen(clk, rst, din, wr_en, rd_en, dout, full, almost_full,
empty)
/* synthesis syn_black_box black_box_pad_pin="clk,rst,din[64:0],wr_en,rd_en,dout[64:0],full,almost_full,empty" */;
input clk;
input rst;
input [64:0]din;
input wr_en;
input rd_en;
output [64:0]dout;
output full;
output almost_full;
output empty;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Module Name: coeff_store
// Description: Stores coefficients for polynomial approximation of the ICDF
//////////////////////////////////////////////////////////////////////////////////
module coeff_store(
input clk,
input [7:0] addr,
output [17:0] coeff1,
output [17:0] coeff2,
output [20:0] coeff3
);
reg [56:0] val = 57'd0;
reg [17:0] coeff1_reg = 18'd0;
reg [17:0] coeff2_reg = 18'd0;
reg [20:0] coeff3_reg = 21'd0;
assign coeff1 = coeff1_reg;
assign coeff2 = coeff2_reg;
assign coeff3 = coeff3_reg;
always @ (posedge clk) begin
coeff1_reg <= val[56:39];
coeff2_reg <= val[38:21];
coeff3_reg <= val[20:0];
case (addr)
8'd0 : val <= 57'b000011111110100110_101000000000011001_000000000000000000100;
8'd1 : val <= 57'b001100101001111111_101000011111010100_000000101000010010000;
8'd2 : val <= 57'b010111110111100101_101010000010010001_000001010001100101100;
8'd3 : val <= 57'b101000111011111100_101100111100000011_000001111101001001100;
8'd4 : val <= 57'b001111011010110010_011001000111110010_000010101100101011001;
8'd5 : val <= 57'b010100110110100101_011011000001110101_000011000110110001011;
8'd6 : val <= 57'b011101010000010110_011101100110001111_000011100011000111110;
8'd7 : val <= 57'b101011011100110101_100001001011010101_000100000010100100111;
8'd8 : val <= 57'b001111011001000101_010011011000100110_000100100110011111101;
8'd9 : val <= 57'b010100001111101111_010101010010100001_000100111010110110011;
8'd10 : val <= 57'b011011110101110100_010111110010010000_000101010001011010111;
8'd11 : val <= 57'b101000110010001001_011011001100011010_000101101010111110010;
8'd12 : val <= 57'b001110010110010011_010000001110000001_000110001000101111010;
8'd13 : val <= 57'b010010110100001001_010001111111101100_000110011001110111010;
8'd14 : val <= 57'b011001110100101001_010100010100001001_000110101101000011001;
8'd15 : val <= 57'b100101110011000101_010111011110011110_000111000011000000010;
8'd16 : val <= 57'b001101010011010010_001110001010110001_000111011100110111010;
8'd17 : val <= 57'b010001011100111101_001111110100001000_000111101011110111110;
8'd18 : val <= 57'b010111111110100011_010001111101110100_000111111100110010100;
8'd19 : val <= 57'b100011001001101010_010100111001101010_001000010000010001110;
8'd20 : val <= 57'b001100011000110111_001100101101011110_001000100111011001010;
8'd21 : val <= 57'b010000010001101000_001110001111100110_001000110100111000111;
8'd22 : val <= 57'b010110011001010001_010000001111111111_001001000100001010011;
8'd23 : val <= 57'b100000111001000100_010010111111011001_001001010101110101011;
8'd24 : val <= 57'b001011100111001000_001011100111000100_001001101010111001100;
8'd25 : val <= 57'b001111010001100011_001101000011000001_001001110111001111100;
8'd26 : val <= 57'b010101000011000101_001110111011100000_001010000101010000011;
8'd27 : val <= 57'b011110111101111011_010001100000010101_001010010101100001011;
8'd28 : val <= 57'b001010111100101100_001010101111101000_001010101000111110110;
8'd29 : val <= 57'b001110011010110011_001100000110010101_001010110100011010101;
8'd30 : val <= 57'b010011111001010100_001101111000000011_001011000001011011011;
8'd31 : val <= 57'b011101010100001111_010000010011110101_001011010000100100010;
8'd32 : val <= 57'b001010011000001100_001010000010100110_001011100010101110011;
8'd33 : val <= 57'b001101101011100111_001011010100110001_001011101101011011000;
8'd34 : val <= 57'b010010111001100100_001101000000101010_001011111001100111001;
8'd35 : val <= 57'b011011111000101001_001111010100101000_001100000111110100101;
8'd36 : val <= 57'b001001111000011111_001001011101000111_001100011000111001111;
8'd37 : val <= 57'b001101000010100001_001010101011010111_001100100010111110111;
8'd38 : val <= 57'b010010000001111100_001100010010001100_001100101110011111001;
8'd39 : val <= 57'b011010101000100000_001110011111010101_001100111011111010100;
8'd40 : val <= 57'b001001011100101010_001000111101010100_001101001100000101011;
8'd41 : val <= 57'b001100011110011010_001010001000000111_001101010101101000111;
8'd42 : val <= 57'b010001010000111011_001011101010011111_001101100000100011100;
8'd43 : val <= 57'b011001100001101101_001101110001101000_001101101101010100010;
8'd44 : val <= 57'b001001000100000010_001000100001111010_001101111100101100111;
8'd45 : val <= 57'b001011111110011001_001001101001101011_001110000101110011011;
8'd46 : val <= 57'b010000100101011001_001011001000000101_001110010000001101101;
8'd47 : val <= 57'b011000100010101011_001101001001111000_001110011100011001001;
8'd48 : val <= 57'b001000101110000100_001000001010000000_001110101011000110000;
8'd49 : val <= 57'b001011100001110001_001001001111000010_001110110011110011010;
8'd50 : val <= 57'b001111111110011010_001010101001111010_001110111101110001000;
8'd51 : val <= 57'b010111101010001000_001100100110111100_001111001001011011111;
8'd52 : val <= 57'b001000011010010100_000111110100111001_001111010111100010011;
8'd53 : val <= 57'b001011001000000001_001000110111011110_001111011111111001010;
8'd54 : val <= 57'b001111011011010010_001010001111001100_001111101001011101110;
8'd55 : val <= 57'b010110110111000011_001100000111111010_001111110100101011110;
8'd56 : val <= 57'b001000001000011100_000111100010000110_010000000010001111111;
8'd57 : val <= 57'b001010110000101100_001000100010011110_010000001010010010111;
8'd58 : val <= 57'b001110111011011010_001001110111010011_010000010011100000111;
8'd59 : val <= 57'b010110001000101000_001011101100000111_010000011110010100111;
8'd60 : val <= 57'b000111111000001100_000111010001001101_010000101011011010011;
8'd61 : val <= 57'b001010011011011100_001000001111100101_010000110011001011011;
8'd62 : val <= 57'b001110011110010101_001001100001110010_010000111100000101010;
8'd63 : val <= 57'b010101011110001111_001011010011000010_010001000110100001111;
8'd64 : val <= 57'b000111101001010100_000111000001111101_010001010011001011101;
8'd65 : val <= 57'b001010000111111110_000111111110011110_010001011010101100100;
8'd66 : val <= 57'b001110000011101100_001001001110010010_010001100011010100000;
8'd67 : val <= 57'b010100110111010101_001010111100010010_010001101101011011011;
8'd68 : val <= 57'b000111011011101010_000110110100000100_010001111001101011111;
8'd69 : val <= 57'b001001110110000101_000111101110111001_010010000000111110000;
8'd70 : val <= 57'b001101101011001010_001000111100100000_010010001001010100111;
8'd71 : val <= 57'b010100010011011101_001010100111011111_010010010011001000111;
8'd72 : val <= 57'b000111001111000011_000110100111010111_010010011111000010011;
8'd73 : val <= 57'b001001100101100011_000111100000101001_010010100110000111000;
8'd74 : val <= 57'b001101010100011110_001000101100001101_010010101110001110100;
8'd75 : val <= 57'b010011110010010000_001010010100011010_010010110111110000111;
8'd76 : val <= 57'b000111000011010111_000110011011101100_010011000011010101001;
8'd77 : val <= 57'b001001010110001110_000111010011100001_010011001010001101011;
8'd78 : val <= 57'b001100111111011010_001000011101001101_010011010010000110110;
8'd79 : val <= 57'b010011010011011010_001010000010110101_010011011011011000110;
8'd80 : val <= 57'b000110111000100000_000110010000111011_010011100110101001100;
8'd81 : val <= 57'b001001000111111101_000111000111011010_010011101101010110010;
8'd82 : val <= 57'b001100101011110100_001000001111010100_010011110101000010101;
8'd83 : val <= 57'b010010110110101011_001001110010100011_010011111110000101100;
8'd84 : val <= 57'b000110101110010111_000110000110111100_010100001001000100010;
8'd85 : val <= 57'b001000111010101010_000110111100001010_010100001111100110011;
8'd86 : val <= 57'b001100011001100000_001000000010011100_010100010111000110101;
8'd87 : val <= 57'b010010011011110011_001001100011011100_010100011111111011100;
8'd88 : val <= 57'b000110100100111001_000101111101101001_010100101010101001011;
8'd89 : val <= 57'b001000101110001100_000110110001101101_010100110001000001101;
8'd90 : val <= 57'b001100001000010111_000111110110011100_010100111000010110101;
8'd91 : val <= 57'b010010000010100111_001001010101010101_010101000000111110011;
8'd92 : val <= 57'b000110011100000000_000101110100111110_010101001011011100100;
8'd93 : val <= 57'b001000100010100000_000110100111111011_010101010001101011100;
8'd94 : val <= 57'b001011111000010000_000111101011001111_010101011000110110001;
8'd95 : val <= 57'b010001101010111011_001001001000001010_010101100001010001101;
8'd96 : val <= 57'b000110010011101001_000101101100110111_010101101011100001001;
8'd97 : val <= 57'b001000010111100000_000110011110110010_010101110001100111100;
8'd98 : val <= 57'b001011101001000110_000111100000101111_010101111000101000001;
8'd99 : val <= 57'b010001010100101000_001000111011110011_010110000000111000010;
8'd100 : val <= 57'b000110001011110000_000101100101010000_010110001010111010000;
8'd101 : val <= 57'b001000001101001000_000110010110001100_010110010000111000010;
8'd102 : val <= 57'b001011011010110010_000111010110110111_010110010111101111101;
8'd103 : val <= 57'b010000111111100100_001000110000001011_010110011111110101000;
8'd104 : val <= 57'b000110000100010100_000101011110000101_010110101001101001110;
8'd105 : val <= 57'b001000000011010100_000110001110000111_010110101111100000011;
8'd106 : val <= 57'b001011001101010000_000111001101100100_010110110110001111001;
8'd107 : val <= 57'b010000101011101001_001000100101001111_010110111110001010010;
8'd108 : val <= 57'b000101111101010000_000101010111010101_010111000111110010111;
8'd109 : val <= 57'b000111111010000010_000110000110011111_010111001101100010010;
8'd110 : val <= 57'b001011000000011100_000111000100110011_010111010100001000110;
8'd111 : val <= 57'b010000011000110001_001000011010111001_010111011011111010011;
8'd112 : val <= 57'b000101110110100101_000101010000111100_010111100101010111011;
8'd113 : val <= 57'b000111110001001110_000101111111010001_010111101011000000000;
8'd114 : val <= 57'b001010110100010010_000110111100100000_010111110001011110110;
8'd115 : val <= 57'b010000000110110101_001000010001000111_010111111001000111010;
8'd116 : val <= 57'b000101110000001110_000101001010111010_011000000010011001011;
8'd117 : val <= 57'b000111101000110110_000101111000011100_011000000111111011100;
8'd118 : val <= 57'b001010101000101101_000110110100101001_011000001110010010111;
8'd119 : val <= 57'b001111110101110001_001000000111110101_011000010101110010110;
8'd120 : val <= 57'b000101101010001011_000101000101001010_011000011110111010101;
8'd121 : val <= 57'b000111100000111000_000101110001111101_011000100100010110101;
8'd122 : val <= 57'b001010011101101101_000110101101001011_011000101010100111000;
8'd123 : val <= 57'b001111100101100001_000111111111000001_011000110001111110110;
8'd124 : val <= 57'b000101100100011011_000100111111101101_011000111010111100101;
8'd125 : val <= 57'b000111011001010010_000101101011110010_011001000000010010111;
8'd126 : val <= 57'b001010010011001100_000110100110000100_011001000110011100101;
8'd127 : val <= 57'b001111010110000001_000111110110101000_011001001101101100101;
8'd128 : val <= 57'b000101011110111011_000100111010100001_011001010110100001010;
8'd129 : val <= 57'b000111010010000010_000101100101111011_011001011011110001111;
8'd130 : val <= 57'b001010001001001010_000110011111010011_011001100001110101011;
8'd131 : val <= 57'b001111000111001100_000111101110101001_011001101000111101111;
8'd132 : val <= 57'b000101011001101011_000100110101100101_011001110001101001100;
8'd133 : val <= 57'b000111001011000110_000101100000010100_011001110110110100111;
8'd134 : val <= 57'b001001111111100100_000110011000110110_011001111100110010011;
8'd135 : val <= 57'b001110111001000001_000111100111000001_011010000011110011111;
8'd136 : val <= 57'b000101010100101001_000100110000110110_011010001100010110111;
8'd137 : val <= 57'b000111000100011101_000101011010111110_011010010001011101010;
8'd138 : val <= 57'b001001110110011001_000110010010101100_011010010111010100111;
8'd139 : val <= 57'b001110101011011100_000111011111101110_011010011110001111101;
8'd140 : val <= 57'b000101001111110101_000100101100010101_011010100110101010101;
8'd141 : val <= 57'b000110111110000110_000101010101110111_011010101011101100010;
8'd142 : val <= 57'b001001101101100101_000110001100110010_011010110001011110011;
8'd143 : val <= 57'b001110011110011011_000111011000110000_011010111000010010101;
8'd144 : val <= 57'b000101001011001101_000100101000000000_011011000000100101110;
8'd145 : val <= 57'b000110110111111111_000101010000111110_011011000101100010110;
8'd146 : val <= 57'b001001100101001000_000110000111001001_011011001011001111100;
8'd147 : val <= 57'b001110010001111011_000111010010000100_011011010001111101101;
8'd148 : val <= 57'b000101000110110001_000100100011110111_011011011010001001011;
8'd149 : val <= 57'b000110110010001000_000101001100010001_011011011111000001111;
8'd150 : val <= 57'b001001011101000000_000110000001101110_011011100100101001101;
8'd151 : val <= 57'b001110000101111010_000111001011101010_011011101011010001110;
8'd152 : val <= 57'b000101000010100000_000100011111111000_011011110011010110011;
8'd153 : val <= 57'b000110101100011111_000101000111110001_011011111000001010101;
8'd154 : val <= 57'b001001010101001100_000101111100100001_011011111101101101100;
8'd155 : val <= 57'b001101111010010110_000111000101100000_011100000100010000000;
8'd156 : val <= 57'b000100111110011001_000100011100000100_011100001100001101101;
8'd157 : val <= 57'b000110100111000011_000101000011011100_011100010000111101110;
8'd158 : val <= 57'b001001001101101011_000101110111100001_011100010110011100000;
8'd159 : val <= 57'b001101101111001110_000110111111100101_011100011100111001000;
8'd160 : val <= 57'b000100111010011100_000100011000011001_011100100100110000000;
8'd161 : val <= 57'b000110100001110101_000100111111010001_011100101001011100010;
8'd162 : val <= 57'b001001000110011011_000101110010101110_011100101110110110000;
8'd163 : val <= 57'b001101100100100000_000110111001111001_011100110101001101110;
8'd164 : val <= 57'b000100110110101000_000100010100110110_011100111100111110011;
8'd165 : val <= 57'b000110011100110010_000100111011010001_011101000001100110111;
8'd166 : val <= 57'b001000111111011100_000101101110000101_011101000110111100010;
8'd167 : val <= 57'b001101011010001001_000110110100011010_011101001101001111000;
8'd168 : val <= 57'b000100110010111100_000100010001011100_011101010100111001100;
8'd169 : val <= 57'b000110010111111011_000100110111011001_011101011001011110010;
8'd170 : val <= 57'b001000111000101101_000101101001101000_011101011110101111100;
8'd171 : val <= 57'b001101010000001010_000110101111000111_011101100100111101010;
8'd172 : val <= 57'b000100101111011001_000100001110001010_011101101100100001111;
8'd173 : val <= 57'b000110010011001110_000100110011101011_011101110001000011010;
8'd174 : val <= 57'b001000110010001100_000101100101010100_011101110110010000100;
8'd175 : val <= 57'b001101000110100000_000110101010000001_011101111100011001100;
8'd176 : val <= 57'b000100101011111101_000100001010111111_011110000011111000011;
8'd177 : val <= 57'b000110001110101011_000100110000000101_011110001000010110011;
8'd178 : val <= 57'b001000101011111000_000101100001001010_011110001101011111101;
8'd179 : val <= 57'b001100111101001011_000110100101000101_011110010011100100001;
8'd180 : val <= 57'b000100101000101001_000100000111111011_011110011010111101100;
8'd181 : val <= 57'b000110001010010010_000100101100100110_011110011111011000001;
8'd182 : val <= 57'b001000100101110010_000101011101001001_011110100100011101110;
8'd183 : val <= 57'b001100110100001000_000110100000010101_011110101010011101111;
8'd184 : val <= 57'b000100100101011011_000100000100111101_011110110001110001111;
8'd185 : val <= 57'b000110000110000010_000100101001001111_011110110110001001011;
8'd186 : val <= 57'b001000011111111001_000101011001010001_011110111011001011011;
8'd187 : val <= 57'b001100101011011001_000110011011101110_011111000001000111001;
8'd188 : val <= 57'b000100100010010100_000100000010000110_011111001000010110000;
8'd189 : val <= 57'b000110000001111010_000100100101111111_011111001100101010100;
8'd190 : val <= 57'b001000011010001011_000101010101100000_011111010001101000111;
8'd191 : val <= 57'b001100100010111010_000110010111010001_011111010111100000101;
8'd192 : val <= 57'b000100011111010011_000011111111010100_011111011110101010100;
8'd193 : val <= 57'b000101111101111011_000100100010110110_011111100010111100000;
8'd194 : val <= 57'b001000010100101000_000101010001110111_011111100111110111000;
8'd195 : val <= 57'b001100011010101100_000110010010111101_011111101101101010110;
8'd196 : val <= 57'b000100011100010111_000011111100101000_011111110100101111110;
8'd197 : val <= 57'b000101111010000011_000100011111110011_011111111000111110011;
8'd198 : val <= 57'b001000001111010000_000101001110010110_011111111101110110001;
8'd199 : val <= 57'b001100010010101110_000110001110110001_100000000011100110000;
8'd200 : val <= 57'b000100011001100010_000011111010000001_100000001010100110011;
8'd201 : val <= 57'b000101110110010010_000100011100110110_100000001110110010001;
8'd202 : val <= 57'b001000001010000010_000101001010111011_100000010011100110110;
8'd203 : val <= 57'b001100001010111110_000110001010101101_100000011001010010111;
8'd204 : val <= 57'b000100010110110001_000011110111100000_100000100000001110101;
8'd205 : val <= 57'b000101110010101001_000100011001111110_100000100100010111110;
8'd206 : val <= 57'b001000000100111110_000101000111100111_100000101001001001010;
8'd207 : val <= 57'b001100000011011101_000110000110110001_100000101110110001101;
8'd208 : val <= 57'b000100010100000110_000011110101000011_100000110101101001001;
8'd209 : val <= 57'b000101101111000110_000100010111001100_100000111001101111101;
8'd210 : val <= 57'b001000000000000011_000101000100011001_100000111110011110000;
8'd211 : val <= 57'b001011111100001010_000110000010111101_100001000100000011000;
8'd212 : val <= 57'b000100010001011111_000011110010101010_100001001010110110001;
8'd213 : val <= 57'b000101101011101001_000100010100011111_100001001110111010001;
8'd214 : val <= 57'b000111111011010001_000101000001010000_100001010011100101101;
8'd215 : val <= 57'b001011110101000011_000101111111001111_100001011001000111001;
8'd216 : val <= 57'b000100001110111110_000011110000010110_100001011111110110000;
8'd217 : val <= 57'b000101101000010010_000100010001110111_100001100011110111100;
8'd218 : val <= 57'b000111110110100111_000100111110001110_100001101000100000010;
8'd219 : val <= 57'b001011101110001000_000101111011101000_100001101101111110011;
8'd220 : val <= 57'b000100001100100000_000011101110000110_100001110100101001010;
8'd221 : val <= 57'b000101100101000010_000100001111010011_100001111000101000011;
8'd222 : val <= 57'b000111110010000101_000100111011010001_100001111101001110010;
8'd223 : val <= 57'b001011100111011010_000101111000001000_100010000010101001010;
8'd224 : val <= 57'b000100001010000110_000011101011111010_100010001001010000010;
8'd225 : val <= 57'b000101100001110110_000100001100110100_100010001101001101000;
8'd226 : val <= 57'b000111101101101010_000100111000011001_100010010001110000001;
8'd227 : val <= 57'b001011100000110111_000101110100101101_100010010111001000000;
8'd228 : val <= 57'b000100000111110001_000011101001110010_100010011101101011001;
8'd229 : val <= 57'b000101011110110000_000100001010011010_100010100001100101101;
8'd230 : val <= 57'b000111101001010111_000100110101100110_100010100110000110010;
8'd231 : val <= 57'b001011011010011110_000101110001011000_100010101011011010111;
8'd232 : val <= 57'b000100000101011111_000011100111101110_100010110001111010011;
8'd233 : val <= 57'b000101011011110000_000100001000000011_100010110101110010101;
8'd234 : val <= 57'b000111100101001011_000100110010110111_100010111010010000101;
8'd235 : val <= 57'b001011010100010000_000101101110001001_100010111111100010011;
8'd236 : val <= 57'b000100000011010010_000011100101101100_100011000101111110001;
8'd237 : val <= 57'b000101011000110011_000100000101110000_100011001001110100010;
8'd238 : val <= 57'b000111100001000110_000100110000001101_100011001110001111111;
8'd239 : val <= 57'b001011001110001100_000101101010111111_100011010011011110101;
8'd240 : val <= 57'b000100000001000111_000011100011101110_100011011001110110111;
8'd241 : val <= 57'b000101010101111100_000100000011100001_100011011101101010111;
8'd242 : val <= 57'b000111011101000111_000100101101101000_100011100010000100000;
8'd243 : val <= 57'b001011001000010001_000101100111111010_100011100111010000000;
8'd244 : val <= 57'b000011111111000000_000011100001110100_100011101101100100111;
8'd245 : val <= 57'b000101010011001001_000100000001010110_100011110001010110110;
8'd246 : val <= 57'b000111011001001110_000100101011000110_100011110101101101101;
8'd247 : val <= 57'b001011000010011111_000101100100111010_100011111010110110110;
default: val <= 57'd0;
endcase
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 15:35:10 2016
/////////////////////////////////////////////////////////////
module FPU_Multiplication_Function_W64_EW11_SW52 ( clk, rst, beg_FSM, ack_FSM,
Data_MX, Data_MY, round_mode, overflow_flag, underflow_flag, ready,
final_result_ieee );
input [63:0] Data_MX;
input [63:0] Data_MY;
input [1:0] round_mode;
output [63:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM;
output overflow_flag, underflow_flag, ready;
wire zero_flag, FSM_add_overflow_flag, FSM_selector_A, FSM_selector_C,
Exp_module_Overflow_flag_A, Sgf_operation_ODD1_left_N51,
Sgf_operation_ODD1_left_N50, Sgf_operation_ODD1_left_N49,
Sgf_operation_ODD1_left_N48, Sgf_operation_ODD1_left_N47,
Sgf_operation_ODD1_left_N46, Sgf_operation_ODD1_left_N45,
Sgf_operation_ODD1_left_N44, Sgf_operation_ODD1_left_N43,
Sgf_operation_ODD1_left_N42, Sgf_operation_ODD1_left_N41,
Sgf_operation_ODD1_left_N40, Sgf_operation_ODD1_left_N39,
Sgf_operation_ODD1_left_N38, Sgf_operation_ODD1_left_N37,
Sgf_operation_ODD1_left_N36, Sgf_operation_ODD1_left_N35,
Sgf_operation_ODD1_left_N34, Sgf_operation_ODD1_left_N33,
Sgf_operation_ODD1_left_N32, Sgf_operation_ODD1_left_N31,
Sgf_operation_ODD1_left_N30, Sgf_operation_ODD1_left_N29,
Sgf_operation_ODD1_left_N28, Sgf_operation_ODD1_left_N27,
Sgf_operation_ODD1_left_N26, Sgf_operation_ODD1_left_N25,
Sgf_operation_ODD1_left_N24, Sgf_operation_ODD1_left_N23,
Sgf_operation_ODD1_left_N22, Sgf_operation_ODD1_left_N21,
Sgf_operation_ODD1_left_N20, Sgf_operation_ODD1_left_N19,
Sgf_operation_ODD1_left_N18, Sgf_operation_ODD1_left_N17,
Sgf_operation_ODD1_left_N16, Sgf_operation_ODD1_left_N15,
Sgf_operation_ODD1_left_N14, Sgf_operation_ODD1_left_N13,
Sgf_operation_ODD1_left_N12, Sgf_operation_ODD1_left_N11,
Sgf_operation_ODD1_left_N10, Sgf_operation_ODD1_left_N9,
Sgf_operation_ODD1_left_N8, Sgf_operation_ODD1_left_N7,
Sgf_operation_ODD1_left_N6, Sgf_operation_ODD1_left_N5,
Sgf_operation_ODD1_left_N4, Sgf_operation_ODD1_left_N3,
Sgf_operation_ODD1_left_N2, Sgf_operation_ODD1_left_N1,
Sgf_operation_ODD1_left_N0, Sgf_operation_ODD1_right_N53,
Sgf_operation_ODD1_right_N52, Sgf_operation_ODD1_right_N51,
Sgf_operation_ODD1_right_N50, Sgf_operation_ODD1_right_N49,
Sgf_operation_ODD1_right_N48, Sgf_operation_ODD1_right_N47,
Sgf_operation_ODD1_right_N46, Sgf_operation_ODD1_right_N45,
Sgf_operation_ODD1_right_N44, Sgf_operation_ODD1_right_N43,
Sgf_operation_ODD1_right_N42, Sgf_operation_ODD1_right_N41,
Sgf_operation_ODD1_right_N40, Sgf_operation_ODD1_right_N39,
Sgf_operation_ODD1_right_N38, Sgf_operation_ODD1_right_N37,
Sgf_operation_ODD1_right_N36, Sgf_operation_ODD1_right_N35,
Sgf_operation_ODD1_right_N34, Sgf_operation_ODD1_right_N33,
Sgf_operation_ODD1_right_N32, Sgf_operation_ODD1_right_N31,
Sgf_operation_ODD1_right_N30, Sgf_operation_ODD1_right_N29,
Sgf_operation_ODD1_right_N28, Sgf_operation_ODD1_right_N27,
Sgf_operation_ODD1_right_N26, Sgf_operation_ODD1_right_N25,
Sgf_operation_ODD1_right_N24, Sgf_operation_ODD1_right_N23,
Sgf_operation_ODD1_right_N22, Sgf_operation_ODD1_right_N21,
Sgf_operation_ODD1_right_N20, Sgf_operation_ODD1_right_N19,
Sgf_operation_ODD1_right_N18, Sgf_operation_ODD1_right_N17,
Sgf_operation_ODD1_right_N16, Sgf_operation_ODD1_right_N15,
Sgf_operation_ODD1_right_N14, Sgf_operation_ODD1_right_N13,
Sgf_operation_ODD1_right_N12, Sgf_operation_ODD1_right_N11,
Sgf_operation_ODD1_right_N10, Sgf_operation_ODD1_right_N9,
Sgf_operation_ODD1_right_N8, Sgf_operation_ODD1_right_N7,
Sgf_operation_ODD1_right_N6, Sgf_operation_ODD1_right_N5,
Sgf_operation_ODD1_right_N4, Sgf_operation_ODD1_right_N3,
Sgf_operation_ODD1_right_N2, Sgf_operation_ODD1_right_N1,
Sgf_operation_ODD1_right_N0, Sgf_operation_ODD1_middle_N55,
Sgf_operation_ODD1_middle_N54, Sgf_operation_ODD1_middle_N53,
Sgf_operation_ODD1_middle_N52, Sgf_operation_ODD1_middle_N51,
Sgf_operation_ODD1_middle_N50, Sgf_operation_ODD1_middle_N49,
Sgf_operation_ODD1_middle_N48, Sgf_operation_ODD1_middle_N47,
Sgf_operation_ODD1_middle_N46, Sgf_operation_ODD1_middle_N45,
Sgf_operation_ODD1_middle_N44, Sgf_operation_ODD1_middle_N43,
Sgf_operation_ODD1_middle_N42, Sgf_operation_ODD1_middle_N41,
Sgf_operation_ODD1_middle_N40, Sgf_operation_ODD1_middle_N39,
Sgf_operation_ODD1_middle_N38, Sgf_operation_ODD1_middle_N37,
Sgf_operation_ODD1_middle_N36, Sgf_operation_ODD1_middle_N35,
Sgf_operation_ODD1_middle_N34, Sgf_operation_ODD1_middle_N33,
Sgf_operation_ODD1_middle_N32, Sgf_operation_ODD1_middle_N31,
Sgf_operation_ODD1_middle_N30, Sgf_operation_ODD1_middle_N29,
Sgf_operation_ODD1_middle_N28, Sgf_operation_ODD1_middle_N27,
Sgf_operation_ODD1_middle_N26, Sgf_operation_ODD1_middle_N25,
Sgf_operation_ODD1_middle_N24, Sgf_operation_ODD1_middle_N23,
Sgf_operation_ODD1_middle_N22, Sgf_operation_ODD1_middle_N21,
Sgf_operation_ODD1_middle_N20, Sgf_operation_ODD1_middle_N19,
Sgf_operation_ODD1_middle_N18, Sgf_operation_ODD1_middle_N17,
Sgf_operation_ODD1_middle_N16, Sgf_operation_ODD1_middle_N15,
Sgf_operation_ODD1_middle_N14, Sgf_operation_ODD1_middle_N13,
Sgf_operation_ODD1_middle_N12, Sgf_operation_ODD1_middle_N11,
Sgf_operation_ODD1_middle_N10, Sgf_operation_ODD1_middle_N9,
Sgf_operation_ODD1_middle_N8, Sgf_operation_ODD1_middle_N7,
Sgf_operation_ODD1_middle_N6, Sgf_operation_ODD1_middle_N5,
Sgf_operation_ODD1_middle_N4, Sgf_operation_ODD1_middle_N3,
Sgf_operation_ODD1_middle_N2, Sgf_operation_ODD1_middle_N0, n287,
n289, n290, n291, n292, n293, n294, n295, n296, n297, n298, n299,
n300, n301, n302, n303, n304, n305, n306, n307, n308, n309, n310,
n311, n312, n313, n314, n315, n316, n317, n318, n319, n320, n321,
n322, n323, n324, n325, n326, n327, n328, n329, n330, n331, n332,
n333, n334, n335, n336, n337, n338, n339, n340, n341, n342, n343,
n344, n345, n346, n347, n348, n349, n350, n351, n352, n353, n354,
n355, n356, n357, n358, n359, n360, n361, n362, n363, n364, n365,
n366, n367, n368, n369, n370, n371, n372, n373, n374, n375, n376,
n377, n378, n379, n380, n381, n382, n383, n384, n385, n386, n387,
n388, n389, n390, n391, n392, n393, n394, n395, n396, n397, n398,
n399, n400, n401, n402, n403, n404, n405, n406, n407, n408, n409,
n410, n411, n412, n413, n414, n415, n416, n417, n418, n419, n420,
n421, n422, n423, n424, n425, n426, n427, n428, n429, n430, n431,
n432, n433, n434, n435, n436, n437, n438, n439, n440, n441, n442,
n443, n444, n445, n446, n447, n448, n449, n450, n451, n452, n453,
n454, n455, n456, n457, n458, n459, n460, n461, n462, n463, n464,
n465, n466, n467, n468, n469, n470, n471, n472, n473, n474, n475,
n476, n477, n478, n479, n480, n481, n482, n483, n484, n485, n486,
n487, n488, n489, n490, n491, n492, n493, n494, n495, n496, n497,
n498, n499, n500, n501, n502, n503, n504, n505, n506, n507, n508,
n509, n510, n511, n512, n513, n514, n515, n516, n517, n518, n519,
n520, n521, n522, n523, n524, n525, n526, n527, n528, n529, n530,
n531, n532, n533, n534, n535, n536, n537, n538, n539, n540, n541,
n542, n543, n544, n545, n546, n547, n548, n549, n550, n551, n552,
n553, n554, n555, n556, n557, n558, n559, n560, n561, n562, n563,
n564, n565, n566, n567, n568, n569, n570, n571, n572, n573, n574,
n575, n576, n577, n578, n579, n580, n581, n582, n583, n584, n585,
n586, n587, n588, n589, n590, n591, n592, n593, n594, n595, n596,
n597, n598, n599, n600, n601, n602, n603, n604, n605, n606, n607,
n608, n609, n610, n611, n612, n613, n614, n615, n616, n617, n618,
n619, n620, n621, n622, n623, n624, n625, n626, n627, n628, n629,
n630, n631, n632, n633, n634, n635, n636, n637, n638, n639, n640,
n641, n642, n643, n644, n645, n646, n647, n648, n649, n650, n651,
n652, n653, n654, n655, n656, n657, n658, n659, n660, n661, n662,
n663, n664, n665, n666, n667, n668, n669, n670, n671, n672, n673,
n674, n676, n677, n678, n679, n680, n681, n682, n683, n684, n685,
n686, n687, n688, n689, n690, n691, n692, n693, n694, n695, n696,
n697, n698, n699, n700, n701, n702, n703, n704, n705, n706, n707,
n708, n709, n710, n711, n712, n713, n714, n715, mult_x_24_n940,
mult_x_24_n939, mult_x_24_n938, mult_x_24_n937, mult_x_24_n936,
mult_x_24_n935, mult_x_24_n934, mult_x_24_n933, mult_x_24_n932,
mult_x_24_n931, mult_x_24_n930, mult_x_24_n929, mult_x_24_n928,
mult_x_24_n927, mult_x_24_n926, mult_x_24_n925, mult_x_24_n924,
mult_x_24_n923, mult_x_24_n922, mult_x_24_n921, mult_x_24_n920,
mult_x_24_n918, mult_x_24_n913, mult_x_24_n912, mult_x_24_n911,
mult_x_24_n910, mult_x_24_n909, mult_x_24_n908, mult_x_24_n907,
mult_x_24_n906, mult_x_24_n905, mult_x_24_n904, mult_x_24_n903,
mult_x_24_n902, mult_x_24_n901, mult_x_24_n900, mult_x_24_n899,
mult_x_24_n898, mult_x_24_n897, mult_x_24_n896, mult_x_24_n895,
mult_x_24_n894, mult_x_24_n893, mult_x_24_n892, mult_x_24_n891,
mult_x_24_n890, mult_x_24_n889, mult_x_24_n888, mult_x_24_n880,
mult_x_24_n879, mult_x_24_n878, mult_x_24_n877, mult_x_24_n876,
mult_x_24_n875, mult_x_24_n874, mult_x_24_n873, mult_x_24_n872,
mult_x_24_n871, mult_x_24_n870, mult_x_24_n869, mult_x_24_n868,
mult_x_24_n867, mult_x_24_n866, mult_x_24_n865, mult_x_24_n864,
mult_x_24_n863, mult_x_24_n862, mult_x_24_n861, mult_x_24_n860,
mult_x_24_n859, mult_x_24_n858, mult_x_24_n853, mult_x_24_n852,
mult_x_24_n851, mult_x_24_n850, mult_x_24_n849, mult_x_24_n848,
mult_x_24_n847, mult_x_24_n846, mult_x_24_n845, mult_x_24_n844,
mult_x_24_n843, mult_x_24_n842, mult_x_24_n841, mult_x_24_n840,
mult_x_24_n839, mult_x_24_n838, mult_x_24_n837, mult_x_24_n836,
mult_x_24_n835, mult_x_24_n834, mult_x_24_n833, mult_x_24_n832,
mult_x_24_n831, mult_x_24_n830, mult_x_24_n829, mult_x_24_n828,
mult_x_24_n820, mult_x_24_n819, mult_x_24_n818, mult_x_24_n817,
mult_x_24_n816, mult_x_24_n815, mult_x_24_n814, mult_x_24_n813,
mult_x_24_n812, mult_x_24_n811, mult_x_24_n810, mult_x_24_n809,
mult_x_24_n808, mult_x_24_n807, mult_x_24_n806, mult_x_24_n805,
mult_x_24_n804, mult_x_24_n803, mult_x_24_n802, mult_x_24_n801,
mult_x_24_n800, mult_x_24_n799, mult_x_24_n798, mult_x_24_n793,
mult_x_24_n792, mult_x_24_n791, mult_x_24_n790, mult_x_24_n789,
mult_x_24_n788, mult_x_24_n787, mult_x_24_n786, mult_x_24_n785,
mult_x_24_n784, mult_x_24_n783, mult_x_24_n782, mult_x_24_n781,
mult_x_24_n780, mult_x_24_n779, mult_x_24_n778, mult_x_24_n777,
mult_x_24_n776, mult_x_24_n775, mult_x_24_n774, mult_x_24_n773,
mult_x_24_n772, mult_x_24_n771, mult_x_24_n770, mult_x_24_n769,
mult_x_24_n768, mult_x_24_n760, mult_x_24_n759, mult_x_24_n758,
mult_x_24_n757, mult_x_24_n756, mult_x_24_n755, mult_x_24_n754,
mult_x_24_n753, mult_x_24_n752, mult_x_24_n751, mult_x_24_n750,
mult_x_24_n749, mult_x_24_n748, mult_x_24_n747, mult_x_24_n746,
mult_x_24_n745, mult_x_24_n744, mult_x_24_n743, mult_x_24_n742,
mult_x_24_n741, mult_x_24_n740, mult_x_24_n739, mult_x_24_n738,
mult_x_24_n733, mult_x_24_n732, mult_x_24_n731, mult_x_24_n730,
mult_x_24_n729, mult_x_24_n728, mult_x_24_n725, mult_x_24_n724,
mult_x_24_n723, mult_x_24_n722, mult_x_24_n719, mult_x_24_n718,
mult_x_24_n717, mult_x_24_n716, mult_x_24_n714, mult_x_24_n713,
mult_x_24_n712, mult_x_24_n711, mult_x_24_n710, mult_x_24_n625,
mult_x_24_n624, mult_x_24_n623, mult_x_24_n622, mult_x_24_n621,
mult_x_24_n620, mult_x_24_n616, mult_x_24_n615, mult_x_24_n614,
mult_x_24_n610, mult_x_24_n609, mult_x_24_n608, mult_x_24_n604,
mult_x_24_n603, mult_x_24_n602, mult_x_24_n583, mult_x_24_n581,
mult_x_24_n580, mult_x_24_n578, mult_x_24_n577, mult_x_24_n576,
mult_x_24_n575, mult_x_24_n573, mult_x_24_n572, mult_x_24_n571,
mult_x_24_n570, mult_x_24_n568, mult_x_24_n567, mult_x_24_n566,
mult_x_24_n563, mult_x_24_n561, mult_x_24_n560, mult_x_24_n559,
mult_x_24_n556, mult_x_24_n554, mult_x_24_n553, mult_x_24_n552,
mult_x_24_n550, mult_x_24_n549, mult_x_24_n548, mult_x_24_n547,
mult_x_24_n546, mult_x_24_n545, mult_x_24_n544, mult_x_24_n542,
mult_x_24_n541, mult_x_24_n540, mult_x_24_n539, mult_x_24_n538,
mult_x_24_n537, mult_x_24_n536, mult_x_24_n534, mult_x_24_n533,
mult_x_24_n532, mult_x_24_n531, mult_x_24_n530, mult_x_24_n529,
mult_x_24_n528, mult_x_24_n526, mult_x_24_n525, mult_x_24_n524,
mult_x_24_n523, mult_x_24_n522, mult_x_24_n521, mult_x_24_n518,
mult_x_24_n516, mult_x_24_n515, mult_x_24_n514, mult_x_24_n513,
mult_x_24_n512, mult_x_24_n511, mult_x_24_n508, mult_x_24_n506,
mult_x_24_n505, mult_x_24_n504, mult_x_24_n503, mult_x_24_n502,
mult_x_24_n501, mult_x_24_n499, mult_x_24_n498, mult_x_24_n497,
mult_x_24_n496, mult_x_24_n495, mult_x_24_n494, mult_x_24_n493,
mult_x_24_n492, mult_x_24_n491, mult_x_24_n490, mult_x_24_n488,
mult_x_24_n487, mult_x_24_n486, mult_x_24_n485, mult_x_24_n484,
mult_x_24_n483, mult_x_24_n482, mult_x_24_n481, mult_x_24_n480,
mult_x_24_n479, mult_x_24_n477, mult_x_24_n476, mult_x_24_n475,
mult_x_24_n474, mult_x_24_n473, mult_x_24_n472, mult_x_24_n471,
mult_x_24_n470, mult_x_24_n469, mult_x_24_n468, mult_x_24_n466,
mult_x_24_n465, mult_x_24_n464, mult_x_24_n463, mult_x_24_n462,
mult_x_24_n461, mult_x_24_n460, mult_x_24_n459, mult_x_24_n458,
mult_x_24_n455, mult_x_24_n453, mult_x_24_n452, mult_x_24_n451,
mult_x_24_n450, mult_x_24_n449, mult_x_24_n448, mult_x_24_n447,
mult_x_24_n446, mult_x_24_n445, mult_x_24_n442, mult_x_24_n440,
mult_x_24_n439, mult_x_24_n438, mult_x_24_n437, mult_x_24_n436,
mult_x_24_n435, mult_x_24_n434, mult_x_24_n433, mult_x_24_n432,
mult_x_24_n430, mult_x_24_n429, mult_x_24_n428, mult_x_24_n427,
mult_x_24_n426, mult_x_24_n425, mult_x_24_n424, mult_x_24_n423,
mult_x_24_n422, mult_x_24_n421, mult_x_24_n420, mult_x_24_n419,
mult_x_24_n418, mult_x_24_n417, mult_x_24_n416, mult_x_24_n415,
mult_x_24_n414, mult_x_24_n413, mult_x_24_n412, mult_x_24_n411,
mult_x_24_n410, mult_x_24_n409, mult_x_24_n408, mult_x_24_n407,
mult_x_24_n406, mult_x_24_n405, mult_x_24_n404, mult_x_24_n403,
mult_x_24_n402, mult_x_24_n401, mult_x_24_n400, mult_x_24_n399,
mult_x_24_n398, mult_x_24_n397, mult_x_24_n396, mult_x_24_n395,
mult_x_24_n394, mult_x_24_n393, mult_x_24_n392, mult_x_24_n391,
mult_x_24_n390, mult_x_24_n389, mult_x_24_n388, mult_x_24_n387,
mult_x_24_n386, mult_x_24_n385, mult_x_24_n384, mult_x_24_n383,
mult_x_24_n382, mult_x_24_n381, mult_x_24_n380, mult_x_24_n379,
mult_x_24_n378, mult_x_24_n377, mult_x_24_n376, mult_x_24_n375,
mult_x_24_n374, mult_x_24_n373, mult_x_24_n372, mult_x_24_n371,
mult_x_24_n370, mult_x_24_n369, mult_x_24_n368, mult_x_24_n367,
mult_x_24_n366, mult_x_24_n365, mult_x_24_n364, mult_x_24_n363,
mult_x_24_n362, mult_x_24_n361, mult_x_24_n360, mult_x_24_n359,
mult_x_24_n358, mult_x_24_n357, mult_x_24_n356, mult_x_24_n355,
mult_x_24_n354, mult_x_24_n353, mult_x_24_n352, mult_x_24_n351,
mult_x_24_n350, mult_x_24_n349, mult_x_24_n348, mult_x_24_n347,
mult_x_24_n345, mult_x_24_n344, mult_x_24_n343, mult_x_24_n342,
mult_x_24_n341, mult_x_24_n340, mult_x_24_n339, mult_x_24_n338,
mult_x_24_n337, mult_x_24_n336, mult_x_24_n335, mult_x_24_n333,
mult_x_24_n332, mult_x_24_n331, mult_x_24_n330, mult_x_24_n329,
mult_x_24_n328, mult_x_24_n327, mult_x_24_n326, mult_x_24_n325,
mult_x_24_n324, mult_x_24_n323, mult_x_24_n322, mult_x_24_n321,
mult_x_24_n320, mult_x_24_n319, mult_x_24_n318, mult_x_24_n317,
mult_x_24_n316, mult_x_24_n315, mult_x_24_n314, mult_x_24_n313,
mult_x_24_n312, mult_x_24_n311, mult_x_24_n310, mult_x_24_n309,
mult_x_24_n308, mult_x_24_n307, mult_x_24_n306, mult_x_24_n305,
mult_x_24_n304, mult_x_24_n303, mult_x_24_n302, mult_x_24_n301,
mult_x_24_n300, mult_x_24_n299, mult_x_24_n298, mult_x_24_n297,
mult_x_24_n296, mult_x_24_n295, mult_x_24_n294, mult_x_24_n293,
mult_x_24_n292, mult_x_24_n291, mult_x_24_n290, mult_x_24_n289,
mult_x_24_n288, mult_x_24_n287, mult_x_24_n286, mult_x_24_n285,
mult_x_24_n284, mult_x_24_n283, mult_x_24_n281, mult_x_24_n280,
mult_x_24_n279, mult_x_24_n278, mult_x_24_n277, mult_x_24_n276,
mult_x_24_n275, mult_x_24_n274, mult_x_24_n272, mult_x_24_n271,
mult_x_24_n270, mult_x_24_n269, mult_x_24_n268, mult_x_24_n267,
mult_x_24_n266, mult_x_24_n265, mult_x_24_n264, mult_x_24_n263,
mult_x_24_n262, mult_x_24_n261, mult_x_24_n260, mult_x_24_n259,
mult_x_24_n258, mult_x_24_n257, mult_x_24_n256, mult_x_24_n255,
mult_x_24_n254, mult_x_24_n253, mult_x_24_n252, mult_x_24_n251,
mult_x_24_n250, mult_x_24_n249, mult_x_24_n248, mult_x_24_n247,
mult_x_24_n246, mult_x_24_n245, mult_x_24_n244, mult_x_24_n243,
mult_x_24_n242, mult_x_24_n241, mult_x_24_n240, mult_x_24_n239,
mult_x_24_n238, mult_x_24_n237, mult_x_24_n235, mult_x_24_n233,
mult_x_24_n232, mult_x_24_n231, mult_x_24_n229, mult_x_24_n228,
mult_x_24_n227, mult_x_24_n226, mult_x_24_n225, mult_x_24_n224,
mult_x_24_n223, mult_x_24_n222, mult_x_24_n221, mult_x_24_n220,
mult_x_24_n219, mult_x_24_n218, mult_x_24_n217, mult_x_24_n216,
mult_x_24_n214, mult_x_24_n213, mult_x_24_n212, mult_x_24_n211,
mult_x_24_n210, mult_x_24_n209, DP_OP_36J45_124_1029_n42,
DP_OP_36J45_124_1029_n28, DP_OP_36J45_124_1029_n27,
DP_OP_36J45_124_1029_n26, DP_OP_36J45_124_1029_n25,
DP_OP_36J45_124_1029_n24, DP_OP_36J45_124_1029_n23,
DP_OP_36J45_124_1029_n22, DP_OP_36J45_124_1029_n21,
DP_OP_36J45_124_1029_n20, DP_OP_36J45_124_1029_n19,
DP_OP_36J45_124_1029_n18, DP_OP_36J45_124_1029_n12,
DP_OP_36J45_124_1029_n11, DP_OP_36J45_124_1029_n10,
DP_OP_36J45_124_1029_n9, DP_OP_36J45_124_1029_n8,
DP_OP_36J45_124_1029_n7, DP_OP_36J45_124_1029_n6,
DP_OP_36J45_124_1029_n5, DP_OP_36J45_124_1029_n4,
DP_OP_36J45_124_1029_n3, DP_OP_36J45_124_1029_n2,
DP_OP_36J45_124_1029_n1, mult_x_23_n872, mult_x_23_n871,
mult_x_23_n864, mult_x_23_n863, mult_x_23_n862, mult_x_23_n861,
mult_x_23_n860, mult_x_23_n859, mult_x_23_n858, mult_x_23_n857,
mult_x_23_n856, mult_x_23_n855, mult_x_23_n854, mult_x_23_n853,
mult_x_23_n852, mult_x_23_n851, mult_x_23_n850, mult_x_23_n849,
mult_x_23_n848, mult_x_23_n847, mult_x_23_n846, mult_x_23_n844,
mult_x_23_n843, mult_x_23_n838, mult_x_23_n837, mult_x_23_n836,
mult_x_23_n835, mult_x_23_n834, mult_x_23_n833, mult_x_23_n832,
mult_x_23_n831, mult_x_23_n830, mult_x_23_n829, mult_x_23_n828,
mult_x_23_n827, mult_x_23_n826, mult_x_23_n825, mult_x_23_n824,
mult_x_23_n823, mult_x_23_n822, mult_x_23_n821, mult_x_23_n820,
mult_x_23_n819, mult_x_23_n818, mult_x_23_n817, mult_x_23_n815,
mult_x_23_n814, mult_x_23_n806, mult_x_23_n805, mult_x_23_n804,
mult_x_23_n803, mult_x_23_n802, mult_x_23_n801, mult_x_23_n800,
mult_x_23_n799, mult_x_23_n798, mult_x_23_n797, mult_x_23_n796,
mult_x_23_n795, mult_x_23_n794, mult_x_23_n793, mult_x_23_n792,
mult_x_23_n791, mult_x_23_n790, mult_x_23_n789, mult_x_23_n788,
mult_x_23_n786, mult_x_23_n785, mult_x_23_n780, mult_x_23_n779,
mult_x_23_n778, mult_x_23_n777, mult_x_23_n776, mult_x_23_n775,
mult_x_23_n774, mult_x_23_n773, mult_x_23_n772, mult_x_23_n771,
mult_x_23_n770, mult_x_23_n769, mult_x_23_n768, mult_x_23_n767,
mult_x_23_n766, mult_x_23_n765, mult_x_23_n764, mult_x_23_n763,
mult_x_23_n762, mult_x_23_n761, mult_x_23_n760, mult_x_23_n759,
mult_x_23_n757, mult_x_23_n756, mult_x_23_n748, mult_x_23_n747,
mult_x_23_n746, mult_x_23_n745, mult_x_23_n744, mult_x_23_n743,
mult_x_23_n742, mult_x_23_n741, mult_x_23_n740, mult_x_23_n739,
mult_x_23_n738, mult_x_23_n737, mult_x_23_n736, mult_x_23_n735,
mult_x_23_n734, mult_x_23_n733, mult_x_23_n732, mult_x_23_n731,
mult_x_23_n730, mult_x_23_n728, mult_x_23_n727, mult_x_23_n722,
mult_x_23_n721, mult_x_23_n720, mult_x_23_n719, mult_x_23_n718,
mult_x_23_n717, mult_x_23_n716, mult_x_23_n715, mult_x_23_n714,
mult_x_23_n713, mult_x_23_n712, mult_x_23_n711, mult_x_23_n710,
mult_x_23_n709, mult_x_23_n708, mult_x_23_n707, mult_x_23_n706,
mult_x_23_n705, mult_x_23_n704, mult_x_23_n703, mult_x_23_n702,
mult_x_23_n701, mult_x_23_n699, mult_x_23_n698, mult_x_23_n686,
mult_x_23_n685, mult_x_23_n684, mult_x_23_n683, mult_x_23_n680,
mult_x_23_n679, mult_x_23_n678, mult_x_23_n677, mult_x_23_n675,
mult_x_23_n674, mult_x_23_n673, mult_x_23_n672, mult_x_23_n659,
mult_x_23_n658, mult_x_23_n654, mult_x_23_n653, mult_x_23_n652,
mult_x_23_n648, mult_x_23_n647, mult_x_23_n646, mult_x_23_n518,
mult_x_23_n516, mult_x_23_n515, mult_x_23_n513, mult_x_23_n512,
mult_x_23_n511, mult_x_23_n510, mult_x_23_n508, mult_x_23_n507,
mult_x_23_n506, mult_x_23_n505, mult_x_23_n503, mult_x_23_n502,
mult_x_23_n501, mult_x_23_n498, mult_x_23_n496, mult_x_23_n495,
mult_x_23_n494, mult_x_23_n491, mult_x_23_n489, mult_x_23_n488,
mult_x_23_n487, mult_x_23_n485, mult_x_23_n484, mult_x_23_n483,
mult_x_23_n482, mult_x_23_n481, mult_x_23_n480, mult_x_23_n479,
mult_x_23_n477, mult_x_23_n476, mult_x_23_n475, mult_x_23_n474,
mult_x_23_n473, mult_x_23_n472, mult_x_23_n471, mult_x_23_n469,
mult_x_23_n468, mult_x_23_n467, mult_x_23_n466, mult_x_23_n465,
mult_x_23_n464, mult_x_23_n463, mult_x_23_n461, mult_x_23_n460,
mult_x_23_n459, mult_x_23_n458, mult_x_23_n457, mult_x_23_n456,
mult_x_23_n453, mult_x_23_n451, mult_x_23_n450, mult_x_23_n449,
mult_x_23_n448, mult_x_23_n447, mult_x_23_n446, mult_x_23_n443,
mult_x_23_n441, mult_x_23_n440, mult_x_23_n439, mult_x_23_n438,
mult_x_23_n437, mult_x_23_n436, mult_x_23_n434, mult_x_23_n433,
mult_x_23_n432, mult_x_23_n431, mult_x_23_n430, mult_x_23_n429,
mult_x_23_n428, mult_x_23_n427, mult_x_23_n426, mult_x_23_n425,
mult_x_23_n423, mult_x_23_n422, mult_x_23_n421, mult_x_23_n420,
mult_x_23_n419, mult_x_23_n418, mult_x_23_n417, mult_x_23_n416,
mult_x_23_n415, mult_x_23_n414, mult_x_23_n412, mult_x_23_n411,
mult_x_23_n410, mult_x_23_n409, mult_x_23_n408, mult_x_23_n407,
mult_x_23_n406, mult_x_23_n405, mult_x_23_n404, mult_x_23_n403,
mult_x_23_n401, mult_x_23_n400, mult_x_23_n399, mult_x_23_n398,
mult_x_23_n397, mult_x_23_n396, mult_x_23_n395, mult_x_23_n394,
mult_x_23_n393, mult_x_23_n392, mult_x_23_n390, mult_x_23_n389,
mult_x_23_n388, mult_x_23_n387, mult_x_23_n386, mult_x_23_n385,
mult_x_23_n384, mult_x_23_n383, mult_x_23_n382, mult_x_23_n381,
mult_x_23_n379, mult_x_23_n378, mult_x_23_n377, mult_x_23_n376,
mult_x_23_n375, mult_x_23_n374, mult_x_23_n373, mult_x_23_n372,
mult_x_23_n371, mult_x_23_n370, mult_x_23_n368, mult_x_23_n367,
mult_x_23_n366, mult_x_23_n365, mult_x_23_n364, mult_x_23_n363,
mult_x_23_n362, mult_x_23_n361, mult_x_23_n360, mult_x_23_n359,
mult_x_23_n358, mult_x_23_n357, mult_x_23_n356, mult_x_23_n355,
mult_x_23_n354, mult_x_23_n353, mult_x_23_n352, mult_x_23_n351,
mult_x_23_n350, mult_x_23_n349, mult_x_23_n348, mult_x_23_n347,
mult_x_23_n346, mult_x_23_n345, mult_x_23_n344, mult_x_23_n343,
mult_x_23_n342, mult_x_23_n341, mult_x_23_n340, mult_x_23_n339,
mult_x_23_n338, mult_x_23_n337, mult_x_23_n336, mult_x_23_n335,
mult_x_23_n334, mult_x_23_n333, mult_x_23_n332, mult_x_23_n331,
mult_x_23_n330, mult_x_23_n329, mult_x_23_n328, mult_x_23_n327,
mult_x_23_n326, mult_x_23_n325, mult_x_23_n324, mult_x_23_n323,
mult_x_23_n322, mult_x_23_n321, mult_x_23_n320, mult_x_23_n319,
mult_x_23_n318, mult_x_23_n317, mult_x_23_n316, mult_x_23_n315,
mult_x_23_n314, mult_x_23_n313, mult_x_23_n312, mult_x_23_n311,
mult_x_23_n310, mult_x_23_n309, mult_x_23_n308, mult_x_23_n307,
mult_x_23_n306, mult_x_23_n305, mult_x_23_n304, mult_x_23_n303,
mult_x_23_n302, mult_x_23_n301, mult_x_23_n300, mult_x_23_n299,
mult_x_23_n298, mult_x_23_n297, mult_x_23_n296, mult_x_23_n295,
mult_x_23_n293, mult_x_23_n292, mult_x_23_n291, mult_x_23_n290,
mult_x_23_n289, mult_x_23_n288, mult_x_23_n287, mult_x_23_n286,
mult_x_23_n285, mult_x_23_n284, mult_x_23_n283, mult_x_23_n282,
mult_x_23_n281, mult_x_23_n280, mult_x_23_n279, mult_x_23_n278,
mult_x_23_n277, mult_x_23_n276, mult_x_23_n274, mult_x_23_n273,
mult_x_23_n272, mult_x_23_n271, mult_x_23_n270, mult_x_23_n269,
mult_x_23_n268, mult_x_23_n267, mult_x_23_n265, mult_x_23_n264,
mult_x_23_n263, mult_x_23_n262, mult_x_23_n261, mult_x_23_n260,
mult_x_23_n259, mult_x_23_n258, mult_x_23_n257, mult_x_23_n256,
mult_x_23_n255, mult_x_23_n254, mult_x_23_n253, mult_x_23_n252,
mult_x_23_n251, mult_x_23_n250, mult_x_23_n249, mult_x_23_n248,
mult_x_23_n247, mult_x_23_n246, mult_x_23_n245, mult_x_23_n244,
mult_x_23_n243, mult_x_23_n241, mult_x_23_n240, mult_x_23_n239,
mult_x_23_n238, mult_x_23_n237, mult_x_23_n236, mult_x_23_n235,
mult_x_23_n234, mult_x_23_n233, mult_x_23_n232, mult_x_23_n231,
mult_x_23_n230, mult_x_23_n228, mult_x_23_n226, mult_x_23_n225,
mult_x_23_n224, mult_x_23_n222, mult_x_23_n221, mult_x_23_n220,
mult_x_23_n219, mult_x_23_n218, mult_x_23_n217, mult_x_23_n216,
mult_x_23_n215, mult_x_23_n214, mult_x_23_n213, mult_x_23_n212,
mult_x_23_n211, mult_x_23_n210, mult_x_23_n209, mult_x_23_n207,
mult_x_23_n206, mult_x_23_n205, mult_x_23_n204, mult_x_23_n203,
mult_x_23_n202, mult_x_23_n197, DP_OP_168J45_122_1342_n600,
DP_OP_168J45_122_1342_n599, DP_OP_168J45_122_1342_n598,
DP_OP_168J45_122_1342_n597, DP_OP_168J45_122_1342_n596,
DP_OP_168J45_122_1342_n595, DP_OP_168J45_122_1342_n594,
DP_OP_168J45_122_1342_n593, DP_OP_168J45_122_1342_n592,
DP_OP_168J45_122_1342_n591, DP_OP_168J45_122_1342_n590,
DP_OP_168J45_122_1342_n589, DP_OP_168J45_122_1342_n588,
DP_OP_168J45_122_1342_n587, DP_OP_168J45_122_1342_n586,
DP_OP_168J45_122_1342_n585, DP_OP_168J45_122_1342_n584,
DP_OP_168J45_122_1342_n583, DP_OP_168J45_122_1342_n582,
DP_OP_168J45_122_1342_n581, DP_OP_168J45_122_1342_n580,
DP_OP_168J45_122_1342_n579, DP_OP_168J45_122_1342_n578,
DP_OP_168J45_122_1342_n577, DP_OP_168J45_122_1342_n576,
DP_OP_168J45_122_1342_n575, DP_OP_168J45_122_1342_n574,
DP_OP_168J45_122_1342_n573, DP_OP_168J45_122_1342_n572,
DP_OP_168J45_122_1342_n571, DP_OP_168J45_122_1342_n570,
DP_OP_168J45_122_1342_n569, DP_OP_168J45_122_1342_n568,
DP_OP_168J45_122_1342_n567, DP_OP_168J45_122_1342_n566,
DP_OP_168J45_122_1342_n565, DP_OP_168J45_122_1342_n564,
DP_OP_168J45_122_1342_n563, DP_OP_168J45_122_1342_n549,
DP_OP_168J45_122_1342_n548, DP_OP_168J45_122_1342_n547,
DP_OP_168J45_122_1342_n546, DP_OP_168J45_122_1342_n545,
DP_OP_168J45_122_1342_n544, DP_OP_168J45_122_1342_n543,
DP_OP_168J45_122_1342_n542, DP_OP_168J45_122_1342_n541,
DP_OP_168J45_122_1342_n540, DP_OP_168J45_122_1342_n539,
DP_OP_168J45_122_1342_n538, DP_OP_168J45_122_1342_n537,
DP_OP_168J45_122_1342_n536, DP_OP_168J45_122_1342_n535,
DP_OP_168J45_122_1342_n534, DP_OP_168J45_122_1342_n533,
DP_OP_168J45_122_1342_n532, DP_OP_168J45_122_1342_n531,
DP_OP_168J45_122_1342_n530, DP_OP_168J45_122_1342_n529,
DP_OP_168J45_122_1342_n528, DP_OP_168J45_122_1342_n527,
DP_OP_168J45_122_1342_n526, DP_OP_168J45_122_1342_n525,
DP_OP_168J45_122_1342_n524, DP_OP_168J45_122_1342_n523,
DP_OP_168J45_122_1342_n522, DP_OP_168J45_122_1342_n521,
DP_OP_168J45_122_1342_n520, DP_OP_168J45_122_1342_n519,
DP_OP_168J45_122_1342_n518, DP_OP_168J45_122_1342_n517,
DP_OP_168J45_122_1342_n516, DP_OP_168J45_122_1342_n515,
DP_OP_168J45_122_1342_n514, DP_OP_168J45_122_1342_n513,
DP_OP_168J45_122_1342_n512, DP_OP_168J45_122_1342_n511,
DP_OP_168J45_122_1342_n510, DP_OP_168J45_122_1342_n509,
DP_OP_168J45_122_1342_n508, DP_OP_168J45_122_1342_n507,
DP_OP_168J45_122_1342_n506, DP_OP_169J45_123_4229_n2458,
DP_OP_169J45_123_4229_n1203, DP_OP_169J45_123_4229_n1202,
DP_OP_169J45_123_4229_n1201, DP_OP_169J45_123_4229_n1200,
DP_OP_169J45_123_4229_n1199, DP_OP_169J45_123_4229_n1198,
DP_OP_169J45_123_4229_n1197, DP_OP_169J45_123_4229_n1196,
DP_OP_169J45_123_4229_n1195, DP_OP_169J45_123_4229_n1194,
DP_OP_169J45_123_4229_n1193, DP_OP_169J45_123_4229_n1192,
DP_OP_169J45_123_4229_n1191, DP_OP_169J45_123_4229_n1190,
DP_OP_169J45_123_4229_n1189, DP_OP_169J45_123_4229_n1188,
DP_OP_169J45_123_4229_n1187, DP_OP_169J45_123_4229_n1186,
DP_OP_169J45_123_4229_n1185, DP_OP_169J45_123_4229_n1184,
DP_OP_169J45_123_4229_n1183, DP_OP_169J45_123_4229_n1182,
DP_OP_169J45_123_4229_n1181, DP_OP_169J45_123_4229_n1180,
DP_OP_169J45_123_4229_n1175, DP_OP_169J45_123_4229_n1174,
DP_OP_169J45_123_4229_n1173, DP_OP_169J45_123_4229_n1172,
DP_OP_169J45_123_4229_n1171, DP_OP_169J45_123_4229_n1170,
DP_OP_169J45_123_4229_n1169, DP_OP_169J45_123_4229_n1168,
DP_OP_169J45_123_4229_n1167, DP_OP_169J45_123_4229_n1166,
DP_OP_169J45_123_4229_n1165, DP_OP_169J45_123_4229_n1164,
DP_OP_169J45_123_4229_n1163, DP_OP_169J45_123_4229_n1162,
DP_OP_169J45_123_4229_n1161, DP_OP_169J45_123_4229_n1160,
DP_OP_169J45_123_4229_n1159, DP_OP_169J45_123_4229_n1158,
DP_OP_169J45_123_4229_n1157, DP_OP_169J45_123_4229_n1156,
DP_OP_169J45_123_4229_n1155, DP_OP_169J45_123_4229_n1154,
DP_OP_169J45_123_4229_n1153, DP_OP_169J45_123_4229_n1152,
DP_OP_169J45_123_4229_n1151, DP_OP_169J45_123_4229_n1150,
DP_OP_169J45_123_4229_n1147, DP_OP_169J45_123_4229_n1146,
DP_OP_169J45_123_4229_n1145, DP_OP_169J45_123_4229_n1144,
DP_OP_169J45_123_4229_n1143, DP_OP_169J45_123_4229_n1142,
DP_OP_169J45_123_4229_n1141, DP_OP_169J45_123_4229_n1140,
DP_OP_169J45_123_4229_n1139, DP_OP_169J45_123_4229_n1138,
DP_OP_169J45_123_4229_n1137, DP_OP_169J45_123_4229_n1136,
DP_OP_169J45_123_4229_n1135, DP_OP_169J45_123_4229_n1134,
DP_OP_169J45_123_4229_n1133, DP_OP_169J45_123_4229_n1132,
DP_OP_169J45_123_4229_n1131, DP_OP_169J45_123_4229_n1130,
DP_OP_169J45_123_4229_n1129, DP_OP_169J45_123_4229_n1128,
DP_OP_169J45_123_4229_n1127, DP_OP_169J45_123_4229_n1126,
DP_OP_169J45_123_4229_n1125, DP_OP_169J45_123_4229_n1124,
DP_OP_169J45_123_4229_n1123, DP_OP_169J45_123_4229_n1122,
DP_OP_169J45_123_4229_n1121, DP_OP_169J45_123_4229_n1120,
DP_OP_169J45_123_4229_n1119, DP_OP_169J45_123_4229_n1115,
DP_OP_169J45_123_4229_n1114, DP_OP_169J45_123_4229_n1113,
DP_OP_169J45_123_4229_n1112, DP_OP_169J45_123_4229_n1111,
DP_OP_169J45_123_4229_n1110, DP_OP_169J45_123_4229_n1109,
DP_OP_169J45_123_4229_n1108, DP_OP_169J45_123_4229_n1107,
DP_OP_169J45_123_4229_n1106, DP_OP_169J45_123_4229_n1105,
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DP_OP_169J45_123_4229_n1100, DP_OP_169J45_123_4229_n1099,
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DP_OP_169J45_123_4229_n1002, DP_OP_169J45_123_4229_n1001,
DP_OP_169J45_123_4229_n1000, DP_OP_169J45_123_4229_n999,
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DP_OP_169J45_123_4229_n555, DP_OP_169J45_123_4229_n554,
DP_OP_169J45_123_4229_n553, DP_OP_169J45_123_4229_n552,
DP_OP_169J45_123_4229_n551, DP_OP_169J45_123_4229_n550,
DP_OP_169J45_123_4229_n549, DP_OP_169J45_123_4229_n548,
DP_OP_169J45_123_4229_n547, DP_OP_169J45_123_4229_n546,
DP_OP_169J45_123_4229_n545, DP_OP_169J45_123_4229_n544,
DP_OP_169J45_123_4229_n543, DP_OP_169J45_123_4229_n542,
DP_OP_169J45_123_4229_n541, DP_OP_169J45_123_4229_n540,
DP_OP_169J45_123_4229_n539, DP_OP_169J45_123_4229_n538,
DP_OP_169J45_123_4229_n537, DP_OP_169J45_123_4229_n536,
DP_OP_169J45_123_4229_n535, DP_OP_169J45_123_4229_n534,
DP_OP_169J45_123_4229_n533, DP_OP_169J45_123_4229_n532,
DP_OP_169J45_123_4229_n531, DP_OP_169J45_123_4229_n530,
DP_OP_169J45_123_4229_n529, DP_OP_169J45_123_4229_n528,
DP_OP_169J45_123_4229_n527, DP_OP_169J45_123_4229_n526,
DP_OP_169J45_123_4229_n525, DP_OP_169J45_123_4229_n524,
DP_OP_169J45_123_4229_n523, DP_OP_169J45_123_4229_n522,
DP_OP_169J45_123_4229_n521, DP_OP_169J45_123_4229_n520,
DP_OP_169J45_123_4229_n519, DP_OP_169J45_123_4229_n518,
DP_OP_169J45_123_4229_n517, DP_OP_169J45_123_4229_n516,
DP_OP_169J45_123_4229_n515, DP_OP_169J45_123_4229_n514,
DP_OP_169J45_123_4229_n512, DP_OP_169J45_123_4229_n511,
DP_OP_169J45_123_4229_n510, DP_OP_169J45_123_4229_n509,
DP_OP_169J45_123_4229_n508, DP_OP_169J45_123_4229_n507,
DP_OP_169J45_123_4229_n506, DP_OP_169J45_123_4229_n505,
DP_OP_169J45_123_4229_n504, DP_OP_169J45_123_4229_n503,
DP_OP_169J45_123_4229_n502, DP_OP_169J45_123_4229_n501,
DP_OP_169J45_123_4229_n500, DP_OP_169J45_123_4229_n499,
DP_OP_169J45_123_4229_n498, DP_OP_169J45_123_4229_n497,
DP_OP_169J45_123_4229_n496, DP_OP_169J45_123_4229_n495,
DP_OP_169J45_123_4229_n494, DP_OP_169J45_123_4229_n492,
DP_OP_169J45_123_4229_n491, DP_OP_169J45_123_4229_n490,
DP_OP_169J45_123_4229_n489, DP_OP_169J45_123_4229_n488,
DP_OP_169J45_123_4229_n487, DP_OP_169J45_123_4229_n486,
DP_OP_169J45_123_4229_n485, DP_OP_169J45_123_4229_n484,
DP_OP_169J45_123_4229_n483, DP_OP_169J45_123_4229_n482,
DP_OP_169J45_123_4229_n481, DP_OP_169J45_123_4229_n480,
DP_OP_169J45_123_4229_n479, DP_OP_169J45_123_4229_n478,
DP_OP_169J45_123_4229_n477, DP_OP_169J45_123_4229_n476,
DP_OP_169J45_123_4229_n475, DP_OP_169J45_123_4229_n473,
DP_OP_169J45_123_4229_n472, DP_OP_169J45_123_4229_n471,
DP_OP_169J45_123_4229_n470, DP_OP_169J45_123_4229_n469,
DP_OP_169J45_123_4229_n468, DP_OP_169J45_123_4229_n467,
DP_OP_169J45_123_4229_n466, DP_OP_169J45_123_4229_n465,
DP_OP_169J45_123_4229_n464, DP_OP_169J45_123_4229_n463,
DP_OP_169J45_123_4229_n462, DP_OP_169J45_123_4229_n461,
DP_OP_169J45_123_4229_n460, DP_OP_169J45_123_4229_n459,
DP_OP_169J45_123_4229_n458, DP_OP_169J45_123_4229_n457,
DP_OP_169J45_123_4229_n456, DP_OP_169J45_123_4229_n455,
DP_OP_169J45_123_4229_n454, DP_OP_169J45_123_4229_n451,
DP_OP_169J45_123_4229_n450, DP_OP_169J45_123_4229_n449,
DP_OP_169J45_123_4229_n448, DP_OP_169J45_123_4229_n447,
DP_OP_169J45_123_4229_n446, DP_OP_169J45_123_4229_n445,
DP_OP_169J45_123_4229_n444, DP_OP_169J45_123_4229_n443,
DP_OP_169J45_123_4229_n442, DP_OP_169J45_123_4229_n441,
DP_OP_169J45_123_4229_n440, DP_OP_169J45_123_4229_n439,
DP_OP_169J45_123_4229_n438, DP_OP_169J45_123_4229_n437,
DP_OP_169J45_123_4229_n436, DP_OP_169J45_123_4229_n435,
DP_OP_169J45_123_4229_n434, DP_OP_169J45_123_4229_n433,
DP_OP_169J45_123_4229_n432, DP_OP_169J45_123_4229_n431,
DP_OP_169J45_123_4229_n430, DP_OP_169J45_123_4229_n429,
DP_OP_169J45_123_4229_n428, DP_OP_169J45_123_4229_n427,
DP_OP_169J45_123_4229_n426, DP_OP_169J45_123_4229_n425,
DP_OP_169J45_123_4229_n424, DP_OP_169J45_123_4229_n423,
DP_OP_169J45_123_4229_n422, DP_OP_169J45_123_4229_n421,
DP_OP_169J45_123_4229_n420, DP_OP_169J45_123_4229_n419,
DP_OP_169J45_123_4229_n418, DP_OP_169J45_123_4229_n417,
DP_OP_169J45_123_4229_n416, DP_OP_169J45_123_4229_n415,
DP_OP_169J45_123_4229_n414, DP_OP_169J45_123_4229_n413,
DP_OP_169J45_123_4229_n412, DP_OP_169J45_123_4229_n411,
DP_OP_169J45_123_4229_n410, DP_OP_169J45_123_4229_n409,
DP_OP_169J45_123_4229_n408, DP_OP_169J45_123_4229_n407,
DP_OP_169J45_123_4229_n406, DP_OP_169J45_123_4229_n405,
DP_OP_169J45_123_4229_n404, DP_OP_169J45_123_4229_n403,
DP_OP_169J45_123_4229_n402, DP_OP_169J45_123_4229_n401,
DP_OP_169J45_123_4229_n400, DP_OP_169J45_123_4229_n399,
DP_OP_169J45_123_4229_n398, DP_OP_169J45_123_4229_n397,
DP_OP_169J45_123_4229_n396, DP_OP_169J45_123_4229_n395,
DP_OP_169J45_123_4229_n394, DP_OP_169J45_123_4229_n393,
DP_OP_169J45_123_4229_n392, DP_OP_169J45_123_4229_n391,
DP_OP_169J45_123_4229_n390, DP_OP_169J45_123_4229_n389,
DP_OP_169J45_123_4229_n388, DP_OP_169J45_123_4229_n387,
DP_OP_169J45_123_4229_n386, DP_OP_169J45_123_4229_n385,
DP_OP_169J45_123_4229_n384, DP_OP_169J45_123_4229_n383,
DP_OP_169J45_123_4229_n382, DP_OP_169J45_123_4229_n381,
DP_OP_169J45_123_4229_n380, DP_OP_169J45_123_4229_n379,
DP_OP_169J45_123_4229_n378, DP_OP_169J45_123_4229_n377,
DP_OP_169J45_123_4229_n376, DP_OP_169J45_123_4229_n375,
DP_OP_169J45_123_4229_n374, DP_OP_169J45_123_4229_n371,
DP_OP_169J45_123_4229_n370, DP_OP_169J45_123_4229_n369,
DP_OP_169J45_123_4229_n368, DP_OP_169J45_123_4229_n367,
DP_OP_169J45_123_4229_n366, DP_OP_169J45_123_4229_n365,
DP_OP_169J45_123_4229_n364, DP_OP_169J45_123_4229_n363,
DP_OP_169J45_123_4229_n362, DP_OP_169J45_123_4229_n361,
DP_OP_169J45_123_4229_n360, DP_OP_169J45_123_4229_n359,
DP_OP_169J45_123_4229_n358, DP_OP_169J45_123_4229_n357,
DP_OP_169J45_123_4229_n356, DP_OP_169J45_123_4229_n355,
DP_OP_169J45_123_4229_n354, DP_OP_169J45_123_4229_n353,
DP_OP_169J45_123_4229_n352, DP_OP_169J45_123_4229_n351,
DP_OP_169J45_123_4229_n350, DP_OP_169J45_123_4229_n349,
DP_OP_169J45_123_4229_n348, DP_OP_169J45_123_4229_n347,
DP_OP_169J45_123_4229_n346, DP_OP_169J45_123_4229_n345,
DP_OP_169J45_123_4229_n344, DP_OP_169J45_123_4229_n343,
DP_OP_169J45_123_4229_n342, DP_OP_169J45_123_4229_n341,
DP_OP_169J45_123_4229_n340, DP_OP_169J45_123_4229_n339,
DP_OP_169J45_123_4229_n338, DP_OP_169J45_123_4229_n337,
DP_OP_169J45_123_4229_n336, DP_OP_169J45_123_4229_n335,
DP_OP_169J45_123_4229_n334, DP_OP_169J45_123_4229_n333,
DP_OP_169J45_123_4229_n332, DP_OP_169J45_123_4229_n331,
DP_OP_169J45_123_4229_n330, DP_OP_169J45_123_4229_n329,
DP_OP_169J45_123_4229_n328, DP_OP_169J45_123_4229_n327,
DP_OP_169J45_123_4229_n326, DP_OP_169J45_123_4229_n325,
DP_OP_169J45_123_4229_n324, DP_OP_169J45_123_4229_n323,
DP_OP_169J45_123_4229_n322, DP_OP_169J45_123_4229_n321,
DP_OP_169J45_123_4229_n320, DP_OP_169J45_123_4229_n319,
DP_OP_169J45_123_4229_n318, DP_OP_169J45_123_4229_n317,
DP_OP_169J45_123_4229_n316, DP_OP_169J45_123_4229_n315,
DP_OP_169J45_123_4229_n314, DP_OP_169J45_123_4229_n313,
DP_OP_169J45_123_4229_n312, DP_OP_169J45_123_4229_n311,
DP_OP_169J45_123_4229_n310, DP_OP_169J45_123_4229_n309,
DP_OP_169J45_123_4229_n308, DP_OP_169J45_123_4229_n307,
DP_OP_169J45_123_4229_n306, DP_OP_169J45_123_4229_n303,
DP_OP_169J45_123_4229_n302, DP_OP_169J45_123_4229_n301,
DP_OP_169J45_123_4229_n300, DP_OP_169J45_123_4229_n299,
DP_OP_169J45_123_4229_n298, DP_OP_169J45_123_4229_n297,
DP_OP_169J45_123_4229_n296, DP_OP_169J45_123_4229_n295,
DP_OP_169J45_123_4229_n294, DP_OP_169J45_123_4229_n293,
DP_OP_169J45_123_4229_n292, DP_OP_169J45_123_4229_n291,
DP_OP_169J45_123_4229_n290, DP_OP_169J45_123_4229_n289,
DP_OP_169J45_123_4229_n288, DP_OP_169J45_123_4229_n287,
DP_OP_169J45_123_4229_n286, DP_OP_169J45_123_4229_n285,
DP_OP_169J45_123_4229_n284, DP_OP_169J45_123_4229_n283,
DP_OP_169J45_123_4229_n282, DP_OP_169J45_123_4229_n281,
DP_OP_169J45_123_4229_n280, DP_OP_169J45_123_4229_n279,
DP_OP_169J45_123_4229_n278, DP_OP_169J45_123_4229_n277,
DP_OP_169J45_123_4229_n276, DP_OP_169J45_123_4229_n275,
DP_OP_169J45_123_4229_n274, DP_OP_169J45_123_4229_n273,
DP_OP_169J45_123_4229_n272, DP_OP_169J45_123_4229_n271,
DP_OP_169J45_123_4229_n270, DP_OP_169J45_123_4229_n269,
DP_OP_169J45_123_4229_n268, DP_OP_169J45_123_4229_n267,
DP_OP_169J45_123_4229_n266, DP_OP_169J45_123_4229_n265,
DP_OP_169J45_123_4229_n264, DP_OP_169J45_123_4229_n263,
DP_OP_169J45_123_4229_n262, DP_OP_169J45_123_4229_n261,
DP_OP_169J45_123_4229_n260, DP_OP_169J45_123_4229_n259,
DP_OP_169J45_123_4229_n258, DP_OP_169J45_123_4229_n257,
DP_OP_169J45_123_4229_n256, DP_OP_169J45_123_4229_n255,
DP_OP_169J45_123_4229_n254, DP_OP_169J45_123_4229_n253,
DP_OP_169J45_123_4229_n252, DP_OP_169J45_123_4229_n251,
DP_OP_169J45_123_4229_n250, DP_OP_169J45_123_4229_n247,
DP_OP_169J45_123_4229_n246, DP_OP_169J45_123_4229_n245,
DP_OP_169J45_123_4229_n244, DP_OP_169J45_123_4229_n243,
DP_OP_169J45_123_4229_n242, DP_OP_169J45_123_4229_n241,
DP_OP_169J45_123_4229_n240, DP_OP_169J45_123_4229_n239,
DP_OP_169J45_123_4229_n238, DP_OP_169J45_123_4229_n237,
DP_OP_169J45_123_4229_n236, DP_OP_169J45_123_4229_n235,
DP_OP_169J45_123_4229_n234, DP_OP_169J45_123_4229_n233,
DP_OP_169J45_123_4229_n232, DP_OP_169J45_123_4229_n231,
DP_OP_169J45_123_4229_n230, DP_OP_169J45_123_4229_n229,
DP_OP_169J45_123_4229_n228, DP_OP_169J45_123_4229_n227,
DP_OP_169J45_123_4229_n226, DP_OP_169J45_123_4229_n225,
DP_OP_169J45_123_4229_n224, DP_OP_169J45_123_4229_n223,
DP_OP_169J45_123_4229_n222, DP_OP_169J45_123_4229_n221,
DP_OP_169J45_123_4229_n220, DP_OP_169J45_123_4229_n219,
DP_OP_169J45_123_4229_n218, DP_OP_169J45_123_4229_n217,
DP_OP_169J45_123_4229_n216, DP_OP_169J45_123_4229_n215,
DP_OP_169J45_123_4229_n214, DP_OP_169J45_123_4229_n213,
DP_OP_169J45_123_4229_n212, DP_OP_169J45_123_4229_n211,
DP_OP_169J45_123_4229_n210, DP_OP_169J45_123_4229_n209,
DP_OP_169J45_123_4229_n208, DP_OP_169J45_123_4229_n207,
DP_OP_169J45_123_4229_n206, DP_OP_169J45_123_4229_n203,
DP_OP_169J45_123_4229_n202, DP_OP_169J45_123_4229_n201,
DP_OP_169J45_123_4229_n200, DP_OP_169J45_123_4229_n199,
DP_OP_169J45_123_4229_n198, DP_OP_169J45_123_4229_n197,
DP_OP_169J45_123_4229_n196, DP_OP_169J45_123_4229_n195,
DP_OP_169J45_123_4229_n194, DP_OP_169J45_123_4229_n193,
DP_OP_169J45_123_4229_n192, DP_OP_169J45_123_4229_n191,
DP_OP_169J45_123_4229_n190, DP_OP_169J45_123_4229_n189,
DP_OP_169J45_123_4229_n188, DP_OP_169J45_123_4229_n187,
DP_OP_169J45_123_4229_n186, DP_OP_169J45_123_4229_n185,
DP_OP_169J45_123_4229_n184, DP_OP_169J45_123_4229_n183,
DP_OP_169J45_123_4229_n182, DP_OP_169J45_123_4229_n181,
DP_OP_169J45_123_4229_n180, DP_OP_169J45_123_4229_n179,
DP_OP_169J45_123_4229_n178, DP_OP_169J45_123_4229_n177,
DP_OP_169J45_123_4229_n176, DP_OP_169J45_123_4229_n175,
DP_OP_169J45_123_4229_n174, DP_OP_169J45_123_4229_n171,
DP_OP_169J45_123_4229_n170, DP_OP_169J45_123_4229_n169,
DP_OP_169J45_123_4229_n168, DP_OP_169J45_123_4229_n167,
DP_OP_169J45_123_4229_n166, DP_OP_169J45_123_4229_n165,
DP_OP_169J45_123_4229_n164, DP_OP_169J45_123_4229_n163,
DP_OP_169J45_123_4229_n162, DP_OP_169J45_123_4229_n161,
DP_OP_169J45_123_4229_n160, DP_OP_169J45_123_4229_n159,
DP_OP_169J45_123_4229_n158, DP_OP_169J45_123_4229_n157,
DP_OP_169J45_123_4229_n156, DP_OP_169J45_123_4229_n155,
DP_OP_169J45_123_4229_n154, DP_OP_169J45_123_4229_n147,
DP_OP_169J45_123_4229_n86, n728, n729, n730, n731, n732, n733, n734,
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n911, n912, n913, n914, n915, n916, n917, n918, n919, n920, n921,
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n955, n956, n957, n958, n959, n960, n961, n962, n963, n964, n965,
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n988, n989, n990, n991, n992, n993, n994, n995, n996, n997, n998,
n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008,
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n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038,
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n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058,
n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068,
n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078,
n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088,
n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098,
n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108,
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n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128,
n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138,
n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148,
n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158,
n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168,
n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178,
n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188,
n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198,
n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208,
n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218,
n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228,
n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238,
n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248,
n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258,
n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268,
n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278,
n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288,
n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298,
n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308,
n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318,
n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328,
n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338,
n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348,
n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358,
n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368,
n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378,
n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388,
n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398,
n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408,
n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418,
n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428,
n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438,
n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448,
n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458,
n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468,
n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478,
n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488,
n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498,
n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508,
n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518,
n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528,
n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538,
n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548,
n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558,
n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568,
n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577, n1578,
n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588,
n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598,
n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608,
n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618,
n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628,
n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638,
n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648,
n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658,
n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668,
n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678,
n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688,
n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698,
n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708,
n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719,
n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729,
n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739,
n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749,
n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759,
n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769,
n1770, n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779,
n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789,
n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799,
n1800, n1801, n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809,
n1810, n1811, n1812, n1813, n1814, n1815, n1816, n1817, n1818, n1819,
n1820, n1821, n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829,
n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1837, n1838, n1839,
n1840, n1841, n1842, n1843, n1844, n1845, n1846, n1847, n1848, n1849,
n1850, n1851, n1852, n1853, n1854, n1855, n1856, n1857, n1858, n1859,
n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867, n1868, n1869,
n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877, n1878, n1879,
n1880, n1881, n1882, n1883, n1884, n1885, n1886, n1887, n1888, n1889,
n1890, n1891, n1892, n1893, n1894, n1895, n1896, n1897, n1898, n1899,
n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909,
n1910, n1911, n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919,
n1920, n1921, n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929,
n1930, n1931, n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939,
n1940, n1941, n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949,
n1950, n1951, n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959,
n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967, n1968, n1969,
n1970, n1971, n1972, n1973, n1974, n1975, n1976, n1977, n1978, n1979,
n1980, n1981, n1982, n1983, n1984, n1985, n1986, n1987, n1988, n1989,
n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997, n1998, n1999,
n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007, n2008, n2009,
n2010, n2011, n2012, n2013, n2014, n2015, n2016, n2017, n2018, n2019,
n2020, n2021, n2022, n2023, n2024, n2025, n2026, n2027, n2028, n2029,
n2030, n2031, n2032, n2033, n2034, n2035, n2036, n2037, n2038, n2039,
n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2047, n2048, n2049,
n2050, n2051, n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059,
n2060, n2061, n2062, n2063, n2064, n2065, n2066, n2067, n2068, n2069,
n2070, n2071, n2072, n2073, n2074, n2075, n2076, n2077, n2078, n2079,
n2080, n2081, n2082, n2083, n2084, n2085, n2086, n2087, n2088, n2089,
n2090, n2091, n2092, n2093, n2094, n2095, n2096, n2097, n2098, n2099,
n2100, n2101, n2102, n2103, n2104, n2105, n2106, n2107, n2108, n2109,
n2110, n2111, n2112, n2113, n2114, n2115, n2116, n2117, n2118, n2119,
n2120, n2121, n2122, n2123, n2124, n2125, n2126, n2127, n2128, n2129,
n2130, n2131, n2132, n2133, n2134, n2135, n2136, n2137, n2138, n2139,
n2140, n2141, n2142, n2143, n2144, n2145, n2146, n2147, n2148, n2149,
n2150, n2151, n2152, n2153, n2154, n2155, n2156, n2157, n2158, n2159,
n2160, n2161, n2162, n2163, n2164, n2165, n2166, n2167, n2168, n2169,
n2170, n2171, n2172, n2173, n2174, n2175, n2176, n2177, n2178, n2179,
n2180, n2181, n2182, n2183, n2184, n2185, n2186, n2187, n2188, n2189,
n2190, n2191, n2192, n2193, n2194, n2195, n2196, n2197, n2198, n2199,
n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209,
n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219,
n2220, n2221, n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229,
n2230, n2231, n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239,
n2240, n2241, n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249,
n2250, n2251, n2252, n2253, n2254, n2255, n2256, n2257, n2258, n2259,
n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2269,
n2270, n2271, n2272, n2273, n2274, n2275, n2276, n2277, n2278, n2279,
n2280, n2281, n2282, n2283, n2284, n2285, n2286, n2287, n2288, n2289,
n2290, n2291, n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299,
n2300, n2301, n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309,
n2310, n2311, n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319,
n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2329,
n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337, n2338, n2339,
n2340, n2341, n2342, n2343, n2344, n2345, n2346, n2347, n2348, n2349,
n2350, n2351, n2352, n2353, n2354, n2355, n2356, n2357, n2358, n2359,
n2360, n2361, n2362, n2363, n2364, n2365, n2366, n2367, n2368, n2369,
n2370, n2371, n2372, n2373, n2374, n2375, n2376, n2377, n2378, n2379,
n2380, n2381, n2382, n2383, n2384, n2385, n2386, n2387, n2388, n2389,
n2390, n2391, n2392, n2393, n2394, n2395, n2396, n2397, n2398, n2399,
n2400, n2401, n2402, n2403, n2404, n2405, n2406, n2407, n2408, n2409,
n2410, n2411, n2412, n2413, n2414, n2415, n2416, n2417, n2418, n2419,
n2420, n2421, n2422, n2423, n2424, n2425, n2426, n2427, n2428, n2429,
n2430, n2431, n2432, n2433, n2434, n2435, n2436, n2437, n2438, n2439,
n2440, n2441, n2442, n2443, n2444, n2445, n2446, n2447, n2448, n2449,
n2450, n2451, n2452, n2453, n2454, n2455, n2456, n2457, n2458, n2459,
n2460, n2461, n2462, n2463, n2464, n2465, n2466, n2467, n2468, n2469,
n2470, n2471, n2472, n2473, n2474, n2475, n2476, n2477, n2478, n2479,
n2480, n2481, n2482, n2483, n2484, n2485, n2486, n2487, n2488, n2489,
n2490, n2491, n2492, n2493, n2494, n2495, n2496, n2497, n2498, n2499,
n2500, n2501, n2502, n2503, n2504, n2505, n2506, n2507, n2508, n2509,
n2510, n2511, n2512, n2513, n2514, n2515, n2516, n2517, n2518, n2519,
n2520, n2521, n2522, n2523, n2524, n2525, n2526, n2527, n2528, n2529,
n2530, n2531, n2532, n2533, n2534, n2535, n2536, n2537, n2538, n2539,
n2540, n2541, n2542, n2543, n2544, n2545, n2546, n2547, n2548, n2549,
n2550, n2551, n2552, n2553, n2554, n2555, n2556, n2557, n2558, n2559,
n2560, n2561, n2562, n2563, n2564, n2565, n2566, n2567, n2568, n2569,
n2570, n2571, n2572, n2573, n2574, n2575, n2576, n2577, n2578, n2579,
n2580, n2581, n2582, n2583, n2584, n2585, n2586, n2587, n2588, n2589,
n2590, n2591, n2592, n2593, n2594, n2595, n2596, n2597, n2598, n2599,
n2600, n2601, n2602, n2603, n2604, n2605, n2606, n2607, n2608, n2609,
n2610, n2611, n2612, n2613, n2614, n2615, n2616, n2617, n2618, n2619,
n2620, n2621, n2622, n2623, n2624, n2625, n2626, n2627, n2628, n2629,
n2630, n2631, n2632, n2633, n2634, n2635, n2636, n2637, n2638, n2639,
n2640, n2641, n2642, n2643, n2644, n2645, n2646, n2647, n2648, n2649,
n2650, n2651, n2652, n2653, n2654, n2655, n2656, n2657, n2658, n2659,
n2660, n2661, n2662, n2663, n2664, n2665, n2666, n2667, n2668, n2669,
n2670, n2671, n2672, n2673, n2674, n2675, n2676, n2677, n2678, n2679,
n2680, n2681, n2682, n2683, n2684, n2685, n2686, n2687, n2688, n2689,
n2690, n2691, n2692, n2693, n2694, n2695, n2696, n2697, n2698, n2699,
n2700, n2701, n2702, n2703, n2704, n2705, n2706, n2707, n2708, n2709,
n2710, n2711, n2712, n2713, n2714, n2715, n2716, n2717, n2718, n2719,
n2720, n2721, n2722, n2723, n2724, n2725, n2726, n2727, n2728, n2729,
n2730, n2731, n2732, n2733, n2734, n2735, n2736, n2737, n2738, n2739,
n2740, n2741, n2742, n2743, n2744, n2745, n2746, n2747, n2748, n2749,
n2750, n2751, n2752, n2753, n2754, n2755, n2756, n2757, n2758, n2759,
n2760, n2761, n2762, n2763, n2764, n2765, n2766, n2767, n2768, n2769,
n2770, n2771, n2772, n2773, n2774, n2775, n2776, n2777, n2778, n2779,
n2780, n2781, n2782, n2783, n2784, n2785, n2786, n2787, n2788, n2789,
n2790, n2791, n2792, n2793, n2794, n2795, n2796, n2797, n2798, n2799,
n2800, n2801, n2802, n2803, n2804, n2805, n2806, n2807, n2808, n2809,
n2810, n2811, n2812, n2813, n2814, n2815, n2816, n2817, n2818, n2819,
n2820, n2821, n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829,
n2830, n2831, n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839,
n2840, n2841, n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849,
n2850, n2851, n2852, n2853, n2854, n2855, n2856, n2857, n2858, n2859,
n2860, n2861, n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869,
n2870, n2871, n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879,
n2880, n2881, n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889,
n2890, n2891, n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899,
n2900, n2901, n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909,
n2910, n2911, n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919,
n2920, n2921, n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929,
n2930, n2931, n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939,
n2940, n2941, n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949,
n2950, n2951, n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959,
n2960, n2961, n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969,
n2970, n2971, n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979,
n2980, n2981, n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989,
n2990, n2991, n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999,
n3000, n3001, n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009,
n3010, n3011, n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019,
n3020, n3021, n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029,
n3030, n3031, n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039,
n3040, n3041, n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049,
n3050, n3051, n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059,
n3060, n3061, n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069,
n3070, n3071, n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079,
n3080, n3081, n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089,
n3090, n3091, n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099,
n3100, n3101, n3102, n3103, n3104, n3105, n3106, n3107, n3108, n3109,
n3110, n3111, n3112, n3113, n3114, n3115, n3116, n3117, n3118, n3119,
n3120, n3121, n3122, n3123, n3124, n3125, n3126, n3127, n3128, n3129,
n3130, n3131, n3132, n3133, n3134, n3135, n3136, n3137, n3138, n3139,
n3140, n3141, n3142, n3143, n3144, n3145, n3146, n3147, n3148, n3149,
n3150, n3151, n3152, n3153, n3154, n3155, n3156, n3157, n3158, n3159,
n3160, n3161, n3162, n3163, n3164, n3165, n3166, n3167, n3168, n3169,
n3170, n3171, n3172, n3173, n3174, n3175, n3176, n3177, n3178, n3179,
n3180, n3181, n3182, n3183, n3184, n3185, n3186, n3187, n3188, n3189,
n3190, n3191, n3192, n3193, n3194, n3195, n3196, n3197, n3198, n3199,
n3200, n3201, n3202, n3203, n3204, n3205, n3206, n3207, n3208, n3209,
n3210, n3211, n3212, n3213, n3214, n3215, n3216, n3217, n3218, n3219,
n3220, n3221, n3222, n3223, n3224, n3225, n3226, n3227, n3228, n3229,
n3230, n3231, n3232, n3233, n3234, n3235, n3236, n3237, n3238, n3239,
n3240, n3241, n3242, n3243, n3244, n3245, n3246, n3247, n3248, n3249,
n3250, n3251, n3252, n3253, n3254, n3255, n3256, n3257, n3258, n3259,
n3260, n3261, n3262, n3263, n3264, n3265, n3266, n3267, n3268, n3269,
n3270, n3271, n3272, n3273, n3274, n3275, n3276, n3277, n3278, n3279,
n3280, n3281, n3282, n3283, n3284, n3285, n3286, n3287, n3288, n3289,
n3290, n3291, n3292, n3293, n3294, n3295, n3296, n3297, n3298, n3299,
n3300, n3301, n3302, n3303, n3304, n3305, n3306, n3307, n3308, n3309,
n3310, n3311, n3312, n3313, n3314, n3315, n3316, n3317, n3318, n3319,
n3320, n3321, n3322, n3323, n3324, n3325, n3326, n3327, n3328, n3329,
n3330, n3331, n3332, n3333, n3334, n3335, n3336, n3337, n3338, n3339,
n3340, n3341, n3342, n3343, n3344, n3345, n3346, n3347, n3348, n3349,
n3350, n3351, n3352, n3353, n3354, n3355, n3356, n3357, n3358, n3359,
n3360, n3361, n3362, n3363, n3364, n3365, n3366, n3367, n3368, n3369,
n3370, n3371, n3372, n3373, n3374, n3375, n3376, n3377, n3378, n3379,
n3380, n3381, n3382, n3383, n3384, n3385, n3386, n3387, n3388, n3389,
n3390, n3391, n3392, n3393, n3394, n3395, n3396, n3397, n3398, n3399,
n3400, n3401, n3402, n3403, n3404, n3405, n3406, n3407, n3408, n3409,
n3410, n3411, n3412, n3413, n3414, n3415, n3416, n3417, n3418, n3419,
n3420, n3421, n3422, n3423, n3424, n3425, n3426, n3427, n3428, n3429,
n3430, n3431, n3432, n3433, n3434, n3435, n3436, n3437, n3438, n3439,
n3440, n3441, n3442, n3443, n3444, n3445, n3446, n3447, n3448, n3449,
n3450, n3451, n3452, n3453, n3454, n3455, n3456, n3457, n3458, n3459,
n3460, n3461, n3462, n3463, n3464, n3465, n3466, n3467, n3468, n3469,
n3470, n3471, n3472, n3473, n3474, n3475, n3476, n3477, n3478, n3479,
n3480, n3481, n3482, n3483, n3484, n3485, n3486, n3487, n3488, n3489,
n3490, n3491, n3492, n3493, n3494, n3495, n3496, n3497, n3498, n3499,
n3500, n3501, n3502, n3503, n3504, n3505, n3506, n3507, n3508, n3509,
n3510, n3511, n3512, n3513, n3514, n3515, n3516, n3517, n3518, n3519,
n3520, n3521, n3522, n3523, n3524, n3525, n3526, n3527, n3528, n3529,
n3530, n3531, n3532, n3533, n3534, n3535, n3536, n3537, n3538, n3539,
n3540, n3541, n3542, n3543, n3544, n3545, n3546, n3547, n3548, n3549,
n3550, n3551, n3552, n3553, n3554, n3555, n3556, n3557, n3558, n3559,
n3560, n3561, n3562, n3563, n3564, n3565, n3566, n3567, n3568, n3569,
n3570, n3571, n3572, n3573, n3574, n3575, n3576, n3577, n3578, n3579,
n3580, n3581, n3582, n3583, n3584, n3585, n3586, n3587, n3588, n3589,
n3590, n3591, n3592, n3593, n3594, n3595, n3596, n3597, n3598, n3599,
n3600, n3601, n3602, n3603, n3604, n3605, n3606, n3607, n3608, n3609,
n3610, n3611, n3612, n3613, n3614, n3615, n3616, n3617, n3618, n3619,
n3620, n3621, n3622, n3623, n3624, n3625, n3626, n3627, n3628, n3629,
n3630, n3631, n3632, n3633, n3634, n3635, n3636, n3637, n3638, n3639,
n3640, n3641, n3642, n3643, n3644, n3645, n3646, n3647, n3648, n3649,
n3650, n3651, n3652, n3653, n3654, n3656, n3657, n3658, n3659, n3660,
n3661, n3662, n3663, n3664, n3665, n3666, n3667, n3668, n3669, n3670,
n3671, n3672, n3673, n3674, n3675, n3676, n3677, n3678, n3679, n3680,
n3681, n3682, n3683, n3684, n3685, n3686, n3687, n3688, n3689, n3690,
n3691, n3692, n3693, n3694, n3695, n3696, n3697, n3698, n3699, n3700,
n3701, n3702, n3703, n3704, n3705, n3706, n3707, n3708, n3709, n3710,
n3711, n3712, n3713, n3714, n3715, n3716, n3717, n3718, n3719, n3720,
n3721, n3722, n3723, n3724, n3725, n3726, n3727, n3728, n3729, n3730,
n3731, n3732, n3733, n3734, n3735, n3736, n3737, n3738, n3739, n3740,
n3741, n3742, n3743, n3744, n3745, n3746, n3747, n3748, n3749, n3750,
n3751, n3752, n3753, n3754, n3755, n3756, n3757, n3758, n3759, n3760,
n3761, n3762, n3763, n3764, n3765, n3766, n3767, n3768, n3769, n3770,
n3771, n3773, n3774, n3775, n3776, n3777, n3778, n3779, n3780, n3781,
n3782, n3783, n3784, n3785, n3786, n3787, n3788, n3789, n3790, n3791,
n3792, n3793, n3794, n3795, n3796, n3797, n3798, n3799, n3800, n3801,
n3802, n3803, n3804, n3805, n3806, n3807, n3808, n3809, n3810, n3811,
n3812, n3813, n3814, n3815, n3816, n3817, n3818, n3819, n3820, n3821,
n3822, n3823, n3824, n3825, n3826, n3827, n3828, n3829, n3830, n3831,
n3832, n3833, n3834, n3835, n3836, n3837, n3838, n3839, n3840, n3841,
n3842, n3843, n3844, n3845, n3846, n3847, n3848, n3849, n3850, n3851,
n3852, n3853, n3854, n3855, n3856, n3857, n3858, n3859, n3860, n3861,
n3862, n3863, n3864, n3865, n3866, n3867, n3868, n3869, n3870, n3871,
n3872, n3873, n3874, n3875, n3876, n3877, n3878, n3879, n3880, n3881,
n3882, n3883, n3884, n3885, n3886, n3887, n3888, n3889, n3890, n3891,
n3892, n3893, n3894, n3895, n3896, n3897, n3898, n3899, n3900, n3901,
n3902, n3903, n3904, n3905, n3906, n3907, n3908, n3909, n3910, n3911,
n3912, n3913, n3914, n3915, n3916, n3917, n3918, n3919, n3920, n3921,
n3922, n3923, n3924, n3925, n3926, n3927, n3928, n3929, n3930, n3931,
n3932, n3933, n3934, n3935, n3936, n3937, n3938, n3939, n3940, n3941,
n3942, n3943, n3944, n3945, n3946, n3947, n3948, n3949, n3950, n3951,
n3952, n3953, n3954, n3955, n3956, n3957, n3958, n3959, n3960, n3961,
n3962, n3963, n3964, n3965, n3966, n3967, n3968, n3969, n3970, n3971,
n3972, n3973, n3974, n3975, n3976, n3977, n3978, n3979, n3980, n3981,
n3982, n3983, n3984, n3985, n3986, n3987, n3988, n3989, n3990, n3991,
n3992, n3993, n3994, n3995, n3996, n3997, n3998, n3999, n4000, n4001,
n4002, n4003, n4004, n4005, n4006, n4007, n4008, n4009, n4010, n4011,
n4012, n4013, n4014, n4015, n4016, n4017, n4018, n4019, n4020, n4021,
n4022, n4023, n4024, n4025, n4026, n4027, n4028, n4029, n4030, n4031,
n4032, n4033, n4034, n4035, n4036, n4037, n4038, n4039, n4040, n4041,
n4042, n4043, n4044, n4045, n4046, n4047, n4048, n4049, n4050, n4051,
n4052, n4053, n4054, n4055, n4056, n4057, n4058, n4059, n4060, n4061,
n4062, n4063, n4064, n4065, n4066, n4067, n4068, n4069, n4070, n4071,
n4072, n4073, n4074, n4075, n4076, n4077, n4078, n4079, n4080, n4081,
n4082, n4083, n4084, n4085, n4086, n4087, n4088, n4089, n4090, n4091,
n4092, n4093, n4094, n4095, n4096, n4097, n4098, n4099, n4100, n4101,
n4102, n4103, n4104, n4105, n4106, n4107, n4108, n4109, n4110, n4111,
n4112, n4113, n4114, n4115, n4116, n4117, n4118, n4119, n4120, n4121,
n4122, n4123, n4124, n4125, n4126, n4127, n4128, n4129, n4130, n4131,
n4132, n4133, n4134, n4135, n4136, n4137, n4138, n4139, n4140, n4141,
n4142, n4143, n4144, n4145, n4146, n4147, n4148, n4149, n4150, n4151,
n4152, n4153, n4154, n4155, n4156, n4157, n4158, n4159, n4160, n4161,
n4162, n4163, n4164, n4165, n4166, n4167, n4168, n4169, n4170, n4171,
n4172, n4173, n4174, n4175, n4176, n4177, n4178, n4179, n4180, n4181,
n4182, n4183, n4184, n4185, n4186, n4187, n4189, n4190, n4191, n4192,
n4193, n4194, n4195, n4196, n4197, n4198, n4199, n4200, n4201, n4202,
n4203, n4204, n4205, n4206, n4207, n4208, n4209, n4210, n4211, n4212,
n4213, n4214, n4215, n4216, n4217, n4218, n4219, n4220, n4221, n4222,
n4223, n4224, n4225, n4227, n4228, n4229, n4230, n4231, n4232, n4233,
n4234, n4235, n4236, n4237, n4238, n4239, n4240, n4241, n4242, n4243,
n4244, n4245, n4246, n4247, n4248, n4249, n4250, n4252, n4253, n4254,
n4255, n4256, n4257, n4258, n4259, n4260, n4261, n4262, n4263, n4264,
n4265, n4266, n4267, n4268, n4269, n4270, n4271, n4272, n4273, n4274,
n4275, n4276, n4277, n4278, n4279, n4280, n4281, n4282, n4283, n4284,
n4285, n4286, n4287, n4288, n4289, n4290, n4291, n4292, n4293, n4294,
n4295, n4296, n4297, n4298, n4299, n4300, n4301, n4302, n4303, n4304,
n4305, n4306, n4307, n4308, n4309, n4310, n4311, n4312, n4313, n4314,
n4315, n4316, n4317, n4318, n4319, n4320, n4321, n4322, n4323, n4324,
n4325, n4326, n4327, n4328, n4329, n4330, n4331, n4332, n4333, n4334,
n4336, n4337, n4338, n4339, n4340, n4341, n4342, n4343, n4344, n4345,
n4346, n4347, n4348, n4349, n4350, n4351, n4352, n4353, n4354, n4355,
n4356, n4357, n4358, n4359, n4360, n4361, n4362, n4363, n4364, n4365,
n4366, n4367, n4368, n4369, n4370, n4371, n4372, n4373, n4374, n4375,
n4376, n4377, n4378, n4379, n4380, n4381, n4382, n4383, n4384, n4385,
n4386, n4387, n4388, n4389, n4390, n4391, n4392, n4393, n4394, n4395,
n4396, n4397, n4398, n4399, n4400, n4401, n4402, n4403, n4404, n4405,
n4406, n4407, n4408, n4409, n4410, n4411, n4412, n4413, n4414, n4415,
n4416, n4417, n4418, n4419, n4420, n4421, n4422, n4423, n4424, n4425,
n4426, n4427, n4428, n4429, n4430, n4431, n4432, n4433, n4434, n4435,
n4436, n4437, n4438, n4439, n4440, n4441, n4442, n4443, n4444, n4445,
n4446, n4447, n4448, n4449, n4450, n4451, n4452, n4453, n4454, n4455,
n4456, n4457, n4458, n4459, n4460, n4461, n4462, n4463, n4464, n4465,
n4466, n4467, n4468, n4469, n4470, n4471, n4472, n4473, n4474, n4475,
n4476, n4477, n4478, n4479, n4480, n4481, n4482, n4483, n4484, n4485,
n4486, n4487, n4488, n4489, n4490, n4491, n4492, n4493, n4494, n4495,
n4496, n4497, n4498, n4499, n4500, n4501, n4502, n4503, n4504, n4505,
n4506, n4507, n4508, n4509, n4510, n4511, n4512, n4513, n4514, n4515,
n4516, n4517, n4518, n4519, n4520, n4521, n4522, n4523, n4524, n4525,
n4526, n4527, n4528, n4529, n4530, n4531, n4532, n4533, n4534, n4535,
n4536, n4537, n4538, n4539, n4540, n4541, n4542, n4543, n4544, n4545,
n4546, n4547, n4548, n4549, n4550, n4551, n4552, n4553, n4554, n4555,
n4556, n4557, n4558, n4559, n4560, n4561, n4562, n4563, n4564, n4565,
n4566, n4567, n4568, n4569, n4570, n4571, n4572, n4573, n4574, n4575,
n4576, n4577, n4578, n4579, n4580, n4581, n4582, n4583, n4584, n4585,
n4586, n4587, n4588, n4589, n4590, n4591, n4592, n4593, n4594, n4595,
n4596, n4597, n4598, n4599, n4600, n4601, n4602, n4603, n4604, n4605,
n4606, n4607, n4608, n4609, n4611, n4612, n4613, n4614, n4615, n4616,
n4617, n4618, n4619, n4620, n4621, n4622, n4623, n4624, n4625, n4626,
n4627, n4629, n4630, n4631, n4632, n4633, n4634, n4635, n4636, n4637,
n4638, n4639, n4640, n4641, n4642, n4643, n4644, n4645, n4647, n4648,
n4649, n4650, n4651, n4652, n4653, n4654, n4655, n4656, n4657, n4658,
n4659, n4660, n4661, n4662, n4663, n4664, n4665, n4666, n4667, n4668,
n4669, n4670, n4671, n4672, n4673, n4674, n4675, n4676, n4677, n4678,
n4679, n4680, n4681, n4682, n4683, n4684, n4685, n4686, n4687, n4688,
n4689, n4690, n4691, n4692, n4693, n4694, n4695, n4696, n4697, n4698,
n4699, n4700, n4701, n4702, n4703, n4704, n4705, n4706, n4707, n4708,
n4709, n4710, n4711, n4712, n4713, n4714, n4715, n4716, n4717, n4718,
n4719, n4720, n4721, n4722, n4723, n4724, n4725, n4726, n4727, n4728,
n4729, n4730, n4731, n4732, n4733, n4734, n4735, n4736, n4737, n4738,
n4739, n4740, n4741, n4742, n4743, n4744, n4745, n4746, n4747, n4748,
n4749, n4750, n4751, n4752, n4753, n4754, n4755, n4756, n4757, n4758,
n4759, n4760, n4761, n4762, n4763, n4764, n4765, n4766, n4767, n4768,
n4769, n4770, n4771, n4772, n4773, n4774, n4775, n4776, n4777, n4778,
n4779, n4781, n4782, n4783, n4784, n4785, n4786, n4787, n4788, n4789,
n4790, n4791, n4792, n4793, n4794, n4795, n4796, n4797, n4798, n4799,
n4800, n4801, n4802, n4803, n4804, n4805, n4806, n4807, n4808, n4809,
n4810, n4811, n4812, n4813, n4814, n4815, n4816, n4817, n4818, n4819,
n4820, n4821, n4822, n4823, n4824, n4825, n4826, n4827, n4828, n4829,
n4830, n4831, n4832, n4833, n4834, n4835, n4836, n4837, n4838, n4839,
n4840, n4841, n4842, n4843, n4844, n4845, n4846, n4847, n4848, n4849,
n4850, n4851, n4852, n4853, n4854, n4855, n4856, n4857, n4858, n4859,
n4860, n4861, n4862, n4864, n4865, n4866, n4867, n4868, n4869, n4870,
n4871, n4872, n4873, n4874, n4875, n4876, n4877, n4878, n4879, n4880,
n4881, n4882, n4883, n4884, n4885, n4886, n4887, n4888, n4890, n4891,
n4892, n4893, n4894, n4895, n4896, n4897, n4898, n4899, n4900, n4901,
n4902, n4903, n4904, n4905, n4906, n4907, n4908, n4909, n4910, n4911,
n4912, n4913, n4914, n4915, n4916, n4920, n4921, n4922, n4923, n4924,
n4925, n4926, n4927, n4928, n4929, n4930, n4931, n4932, n4933, n4934,
n4935, n4936, n4937, n4938, n4939, n4940, n4941, n4942, n4943, n4944,
n4945, n4946, n4947, n4948, n4949, n4950, n4951, n4952, n4953, n4954,
n4955, n4956, n4957, n4958, n4959, n4960, n4961, n4962, n4963, n4964,
n4965, n4966, n4967, n4968, n4969, n4970, n4971, n4972, n4973, n4974,
n4975, n4976, n4977, n4978, n4979, n4980, n4981, n4982, n4983, n4984,
n4985, n4986, n4987, n4988, n4989, n4990, n4991, n4992, n4993, n4994,
n4995, n4996, n4997, n4998, n4999, n5000, n5001, n5002, n5003, n5004,
n5005, n5006, n5007, n5008, n5009, n5010, n5011, n5012, n5013, n5014,
n5015, n5016, n5017, n5018, n5019, n5020, n5021, n5022, n5023, n5024,
n5025, n5026, n5027, n5028, n5029, n5030, n5031, n5032, n5033, n5034,
n5035, n5036, n5037, n5038, n5039, n5040, n5041, n5042, n5043, n5044,
n5045, n5046, n5047, n5048, n5049, n5050, n5051, n5052, n5053, n5054,
n5055, n5056, n5057, n5058, n5059, n5060, n5061, n5062, n5063, n5064,
n5065, n5066, n5067, n5068, n5069, n5070, n5071, n5072, n5073, n5074,
n5075, n5076, n5077, n5078, n5079, n5080, n5081, n5082, n5083, n5084,
n5085, n5086, n5087, n5088, n5089, n5090, n5091, n5092, n5093, n5094,
n5095, n5096, n5097, n5098, n5099, n5100, n5101, n5102, n5103, n5104,
n5105, n5106, n5107, n5108, n5109, n5110, n5111, n5112, n5113, n5114,
n5115, n5116, n5117, n5118, n5119, n5120, n5121, n5122, n5123, n5124,
n5125, n5126, n5127, n5128, n5129, n5130, n5131, n5132, n5133, n5134,
n5135, n5136, n5137, n5138, n5139, n5140, n5141, n5142, n5143, n5144,
n5145, n5146, n5147, n5148, n5149, n5150, n5151, n5152, n5153, n5154,
n5155, n5156, n5157, n5158, n5159, n5160, n5161, n5162, n5163, n5164,
n5165, n5166, n5167, n5168, n5169, n5170, n5171, n5172, n5173, n5174,
n5175, n5176, n5177, n5178, n5179, n5180, n5181, n5182, n5183, n5184,
n5185, n5186, n5187, n5188, n5189, n5190, n5191, n5192, n5193, n5194,
n5195, n5196, n5197, n5198, n5199, n5200, n5201, n5202, n5203, n5204,
n5205, n5206, n5207, n5334, n5335, n5336, n5338, n5340, n5341, n5342,
n5343, n5344, n5345, n5346, n5347, n5348, n5349, n5350, n5351, n5352,
n5353, n5354, n5355, n5356, n5357, n5358, n5359, n5360, n5362, n5363,
n5364, n5365, n5366, n5367, n5368, n5369, n5370, n5371, n5372, n5373,
n5374, n5375, n5376, n5377, n5378, n5379, n5380, n5381, n5382, n5383,
n5384, n5385, n5386, n5387, n5388, n5389, n5390, n5391, n5392, n5393,
n5394, n5395, n5396, n5397, n5398, n5399, n5400, n5401, n5402, n5403,
n5404, n5405, n5406, n5407, n5408, n5409, n5410, n5411, n5412, n5413,
n5414, n5415, n5416, n5417, n5418, n5419, n5420, n5421, n5422, n5423,
n5424, n5425, n5426, n5427, n5428, n5429, n5430, n5431, n5432, n5433,
n5434, n5435, n5436, n5437, n5438, n5439, n5440, n5441, n5442, n5443,
n5444, n5445, n5446, n5447, n5448, n5449, n5450, n5451, n5452, n5453,
n5454, n5455, n5456, n5457, n5458, n5459, n5460, n5461, n5462, n5463,
n5464, n5465, n5466, n5467, n5468, n5469, n5470, n5471, n5472, n5473,
n5474, n5475, n5476, n5477, n5478;
wire [105:0] P_Sgf;
wire [1:0] FSM_selector_B;
wire [63:0] Op_MX;
wire [63:0] Op_MY;
wire [11:0] exp_oper_result;
wire [11:0] S_Oper_A_exp;
wire [52:0] Add_result;
wire [52:0] Sgf_normalized_result;
wire [3:0] FS_Module_state_reg;
wire [11:0] Exp_module_Data_S;
wire [26:0] Sgf_operation_Result;
wire [55:0] Sgf_operation_ODD1_Q_middle;
wire [53:27] Sgf_operation_ODD1_Q_right;
wire [51:0] Sgf_operation_ODD1_Q_left;
DFFQX1TS Sgf_operation_ODD1_left_DatO_reg_0_ ( .D(Sgf_operation_ODD1_left_N0), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[0]) );
DFFQX1TS Sgf_operation_ODD1_left_DatO_reg_39_ ( .D(
Sgf_operation_ODD1_left_N39), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[39]) );
DFFQX1TS Sgf_operation_ODD1_left_DatO_reg_40_ ( .D(
Sgf_operation_ODD1_left_N40), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[40]) );
DFFQX1TS Sgf_operation_ODD1_left_DatO_reg_41_ ( .D(
Sgf_operation_ODD1_left_N41), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[41]) );
DFFQX1TS Sgf_operation_ODD1_left_DatO_reg_42_ ( .D(
Sgf_operation_ODD1_left_N42), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[42]) );
DFFQX1TS Sgf_operation_ODD1_left_DatO_reg_43_ ( .D(
Sgf_operation_ODD1_left_N43), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[43]) );
DFFQX1TS Sgf_operation_ODD1_left_DatO_reg_44_ ( .D(
Sgf_operation_ODD1_left_N44), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[44]) );
DFFQX1TS Sgf_operation_ODD1_left_DatO_reg_45_ ( .D(
Sgf_operation_ODD1_left_N45), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[45]) );
DFFQX1TS Sgf_operation_ODD1_left_DatO_reg_46_ ( .D(
Sgf_operation_ODD1_left_N46), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[46]) );
DFFQX1TS Sgf_operation_ODD1_left_DatO_reg_47_ ( .D(
Sgf_operation_ODD1_left_N47), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[47]) );
DFFQX1TS Sgf_operation_ODD1_left_DatO_reg_48_ ( .D(
Sgf_operation_ODD1_left_N48), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[48]) );
DFFQX1TS Sgf_operation_ODD1_left_DatO_reg_49_ ( .D(
Sgf_operation_ODD1_left_N49), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[49]) );
DFFQX1TS Sgf_operation_ODD1_left_DatO_reg_50_ ( .D(
Sgf_operation_ODD1_left_N50), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[50]) );
DFFQX1TS Sgf_operation_ODD1_left_DatO_reg_51_ ( .D(
Sgf_operation_ODD1_left_N51), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[51]) );
DFFQX1TS Sgf_operation_ODD1_right_DatO_reg_44_ ( .D(
Sgf_operation_ODD1_right_N44), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[44]) );
DFFQX1TS Sgf_operation_ODD1_right_DatO_reg_45_ ( .D(
Sgf_operation_ODD1_right_N45), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[45]) );
DFFQX1TS Sgf_operation_ODD1_right_DatO_reg_46_ ( .D(
Sgf_operation_ODD1_right_N46), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[46]) );
DFFQX1TS Sgf_operation_ODD1_right_DatO_reg_47_ ( .D(
Sgf_operation_ODD1_right_N47), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[47]) );
DFFQX1TS Sgf_operation_ODD1_right_DatO_reg_48_ ( .D(
Sgf_operation_ODD1_right_N48), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[48]) );
DFFQX1TS Sgf_operation_ODD1_right_DatO_reg_49_ ( .D(
Sgf_operation_ODD1_right_N49), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[49]) );
DFFQX1TS Sgf_operation_ODD1_right_DatO_reg_50_ ( .D(
Sgf_operation_ODD1_right_N50), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[50]) );
DFFQX1TS Sgf_operation_ODD1_right_DatO_reg_51_ ( .D(
Sgf_operation_ODD1_right_N51), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[51]) );
DFFQX1TS Sgf_operation_ODD1_right_DatO_reg_52_ ( .D(
Sgf_operation_ODD1_right_N52), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[52]) );
DFFQX1TS Sgf_operation_ODD1_right_DatO_reg_53_ ( .D(
Sgf_operation_ODD1_right_N53), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[53]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_0_ ( .D(
Sgf_operation_ODD1_middle_N0), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[0]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_46_ ( .D(
Sgf_operation_ODD1_middle_N46), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[46]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_47_ ( .D(
Sgf_operation_ODD1_middle_N47), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[47]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_48_ ( .D(
Sgf_operation_ODD1_middle_N48), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[48]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_49_ ( .D(
Sgf_operation_ODD1_middle_N49), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[49]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_50_ ( .D(
Sgf_operation_ODD1_middle_N50), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[50]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_51_ ( .D(
Sgf_operation_ODD1_middle_N51), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[51]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_52_ ( .D(
Sgf_operation_ODD1_middle_N52), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[52]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_53_ ( .D(
Sgf_operation_ODD1_middle_N53), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[53]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_54_ ( .D(
Sgf_operation_ODD1_middle_N54), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[54]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_55_ ( .D(
Sgf_operation_ODD1_middle_N55), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[55]) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_63_ ( .D(n715), .CK(clk), .RN(
n5468), .Q(Op_MY[63]) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_46_ ( .D(n692), .CK(clk), .RN(
n5466), .QN(n792) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_43_ ( .D(n689), .CK(clk), .RN(
n3684), .QN(n793) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n657), .CK(clk), .RN(
n5465), .Q(Op_MX[11]) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n651), .CK(clk), .RN(
n5476), .Q(Op_MX[5]), .QN(n934) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n579), .CK(clk), .RN(n5464),
.Q(Add_result[0]) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_52_ ( .D(n527), .CK(clk), .RN(n5462),
.Q(Add_result[52]) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_48_ ( .D(n630), .CK(clk), .RN(
n5472), .QN(n944) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_42_ ( .D(n624), .CK(clk), .RN(
n5468), .QN(n947) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n612), .CK(clk), .RN(
n5471), .QN(n945) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n583), .CK(clk), .RN(
n5459), .QN(n762) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_103_ ( .D(n525), .CK(clk), .RN(
n5458), .Q(P_Sgf[103]), .QN(n5407) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_102_ ( .D(n524), .CK(clk), .RN(
n5456), .Q(P_Sgf[102]), .QN(n5399) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_101_ ( .D(n523), .CK(clk), .RN(
n5458), .Q(P_Sgf[101]), .QN(n5408) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_100_ ( .D(n522), .CK(clk), .RN(
n5455), .Q(P_Sgf[100]), .QN(n5409) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_99_ ( .D(n521), .CK(clk), .RN(
n761), .Q(P_Sgf[99]), .QN(n5410) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_104_ ( .D(n520), .CK(clk), .RN(
n5478), .Q(P_Sgf[104]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_98_ ( .D(n519), .CK(clk), .RN(
n5454), .Q(P_Sgf[98]), .QN(n5411) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_97_ ( .D(n518), .CK(clk), .RN(
n5456), .Q(P_Sgf[97]), .QN(n5412) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_96_ ( .D(n517), .CK(clk), .RN(
n5456), .Q(P_Sgf[96]), .QN(n5413) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_95_ ( .D(n516), .CK(clk), .RN(
n761), .Q(P_Sgf[95]), .QN(n5414) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_94_ ( .D(n515), .CK(clk), .RN(
n5455), .Q(P_Sgf[94]), .QN(n5415) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_93_ ( .D(n514), .CK(clk), .RN(
n5478), .Q(P_Sgf[93]), .QN(n5416) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_92_ ( .D(n513), .CK(clk), .RN(
n5455), .Q(P_Sgf[92]), .QN(n5417) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_91_ ( .D(n512), .CK(clk), .RN(
n761), .Q(P_Sgf[91]), .QN(n5418) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_90_ ( .D(n511), .CK(clk), .RN(
n5455), .Q(P_Sgf[90]), .QN(n5419) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_89_ ( .D(n510), .CK(clk), .RN(
n761), .Q(P_Sgf[89]), .QN(n5420) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_88_ ( .D(n509), .CK(clk), .RN(
n5456), .Q(P_Sgf[88]), .QN(n5421) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_87_ ( .D(n508), .CK(clk), .RN(
n5454), .Q(P_Sgf[87]), .QN(n5422) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_86_ ( .D(n507), .CK(clk), .RN(
n5455), .Q(P_Sgf[86]), .QN(n5423) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_85_ ( .D(n506), .CK(clk), .RN(
n5458), .Q(P_Sgf[85]), .QN(n5424) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_84_ ( .D(n505), .CK(clk), .RN(
n5455), .Q(P_Sgf[84]), .QN(n5425) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_83_ ( .D(n504), .CK(clk), .RN(
n5478), .Q(P_Sgf[83]), .QN(n5426) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_82_ ( .D(n503), .CK(clk), .RN(
n5478), .Q(P_Sgf[82]), .QN(n5427) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_81_ ( .D(n502), .CK(clk), .RN(
n5457), .Q(P_Sgf[81]), .QN(n5428) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_80_ ( .D(n501), .CK(clk), .RN(
n5457), .Q(P_Sgf[80]), .QN(n5429) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_79_ ( .D(n500), .CK(clk), .RN(
n761), .Q(P_Sgf[79]), .QN(n5430) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_78_ ( .D(n499), .CK(clk), .RN(
n761), .Q(P_Sgf[78]), .QN(n5431) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_77_ ( .D(n498), .CK(clk), .RN(
n5454), .Q(P_Sgf[77]), .QN(n5432) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_76_ ( .D(n497), .CK(clk), .RN(
n761), .Q(P_Sgf[76]), .QN(n5433) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_75_ ( .D(n496), .CK(clk), .RN(
n761), .Q(P_Sgf[75]), .QN(n5434) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_74_ ( .D(n495), .CK(clk), .RN(
n761), .Q(P_Sgf[74]), .QN(n5435) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_73_ ( .D(n494), .CK(clk), .RN(
n5458), .Q(P_Sgf[73]), .QN(n5436) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_72_ ( .D(n493), .CK(clk), .RN(
n761), .Q(P_Sgf[72]), .QN(n5437) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_71_ ( .D(n492), .CK(clk), .RN(
n5454), .Q(P_Sgf[71]), .QN(n5438) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_70_ ( .D(n491), .CK(clk), .RN(
n5457), .Q(P_Sgf[70]), .QN(n5439) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_69_ ( .D(n490), .CK(clk), .RN(
n5458), .Q(P_Sgf[69]), .QN(n5440) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_68_ ( .D(n489), .CK(clk), .RN(
n5455), .Q(P_Sgf[68]), .QN(n5441) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_67_ ( .D(n488), .CK(clk), .RN(
n5458), .Q(P_Sgf[67]), .QN(n5442) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_66_ ( .D(n487), .CK(clk), .RN(
n5458), .Q(P_Sgf[66]), .QN(n5443) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_65_ ( .D(n486), .CK(clk), .RN(
n761), .Q(P_Sgf[65]), .QN(n5444) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_64_ ( .D(n485), .CK(clk), .RN(
n5457), .Q(P_Sgf[64]), .QN(n5445) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_63_ ( .D(n484), .CK(clk), .RN(
n761), .Q(P_Sgf[63]), .QN(n5446) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_62_ ( .D(n483), .CK(clk), .RN(
n5456), .Q(P_Sgf[62]), .QN(n5447) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_61_ ( .D(n482), .CK(clk), .RN(
n761), .Q(P_Sgf[61]), .QN(n5448) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_60_ ( .D(n481), .CK(clk), .RN(
n5457), .Q(P_Sgf[60]), .QN(n5449) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_59_ ( .D(n480), .CK(clk), .RN(
n761), .Q(P_Sgf[59]), .QN(n5400) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_58_ ( .D(n479), .CK(clk), .RN(
n5478), .Q(P_Sgf[58]), .QN(n5401) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_57_ ( .D(n478), .CK(clk), .RN(
n5457), .Q(P_Sgf[57]), .QN(n5402) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_56_ ( .D(n477), .CK(clk), .RN(
n5457), .Q(P_Sgf[56]), .QN(n5403) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_55_ ( .D(n476), .CK(clk), .RN(
n5458), .Q(P_Sgf[55]), .QN(n5404) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_54_ ( .D(n475), .CK(clk), .RN(
n761), .Q(P_Sgf[54]), .QN(n5405) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_53_ ( .D(n474), .CK(clk), .RN(
n5478), .Q(P_Sgf[53]), .QN(n5406) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_52_ ( .D(n473), .CK(clk), .RN(
n761), .Q(P_Sgf[52]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_51_ ( .D(n472), .CK(clk), .RN(
n5455), .Q(P_Sgf[51]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_50_ ( .D(n471), .CK(clk), .RN(
n5478), .Q(P_Sgf[50]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_49_ ( .D(n470), .CK(clk), .RN(
n5457), .Q(P_Sgf[49]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_48_ ( .D(n469), .CK(clk), .RN(
n5458), .Q(P_Sgf[48]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_47_ ( .D(n468), .CK(clk), .RN(
n761), .Q(P_Sgf[47]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_46_ ( .D(n467), .CK(clk), .RN(
n5455), .Q(P_Sgf[46]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_45_ ( .D(n466), .CK(clk), .RN(
n5457), .Q(P_Sgf[45]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_44_ ( .D(n465), .CK(clk), .RN(
n761), .Q(P_Sgf[44]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_43_ ( .D(n464), .CK(clk), .RN(
n5456), .Q(P_Sgf[43]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_42_ ( .D(n463), .CK(clk), .RN(
n761), .Q(P_Sgf[42]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_41_ ( .D(n462), .CK(clk), .RN(
n761), .Q(P_Sgf[41]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_40_ ( .D(n461), .CK(clk), .RN(
n761), .Q(P_Sgf[40]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_39_ ( .D(n460), .CK(clk), .RN(
n5456), .Q(P_Sgf[39]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_38_ ( .D(n459), .CK(clk), .RN(
n5456), .Q(P_Sgf[38]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_37_ ( .D(n458), .CK(clk), .RN(
n5455), .Q(P_Sgf[37]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_36_ ( .D(n457), .CK(clk), .RN(
n761), .Q(P_Sgf[36]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_35_ ( .D(n456), .CK(clk), .RN(
n5454), .Q(P_Sgf[35]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_34_ ( .D(n455), .CK(clk), .RN(
n5456), .Q(P_Sgf[34]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_33_ ( .D(n454), .CK(clk), .RN(
n5478), .Q(P_Sgf[33]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_32_ ( .D(n453), .CK(clk), .RN(
n5454), .Q(P_Sgf[32]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_31_ ( .D(n452), .CK(clk), .RN(
n5458), .Q(P_Sgf[31]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_30_ ( .D(n451), .CK(clk), .RN(
n5458), .Q(P_Sgf[30]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_29_ ( .D(n450), .CK(clk), .RN(
n5478), .Q(P_Sgf[29]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_28_ ( .D(n449), .CK(clk), .RN(
n5454), .Q(P_Sgf[28]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_27_ ( .D(n448), .CK(clk), .RN(
n5458), .Q(P_Sgf[27]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_26_ ( .D(n447), .CK(clk), .RN(
n5457), .Q(P_Sgf[26]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_25_ ( .D(n446), .CK(clk), .RN(
n5478), .Q(P_Sgf[25]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_24_ ( .D(n445), .CK(clk), .RN(
n5455), .Q(P_Sgf[24]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_23_ ( .D(n444), .CK(clk), .RN(
n5458), .Q(P_Sgf[23]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_22_ ( .D(n443), .CK(clk), .RN(
n5458), .Q(P_Sgf[22]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_21_ ( .D(n442), .CK(clk), .RN(
n5456), .Q(P_Sgf[21]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_20_ ( .D(n441), .CK(clk), .RN(
n5456), .Q(P_Sgf[20]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_19_ ( .D(n440), .CK(clk), .RN(
n5454), .Q(P_Sgf[19]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_18_ ( .D(n439), .CK(clk), .RN(
n5454), .Q(P_Sgf[18]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_17_ ( .D(n438), .CK(clk), .RN(
n5456), .Q(P_Sgf[17]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_16_ ( .D(n437), .CK(clk), .RN(
n5478), .Q(P_Sgf[16]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_15_ ( .D(n436), .CK(clk), .RN(
n5478), .Q(P_Sgf[15]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_14_ ( .D(n435), .CK(clk), .RN(
n5454), .Q(P_Sgf[14]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_13_ ( .D(n434), .CK(clk), .RN(
n5456), .Q(P_Sgf[13]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_12_ ( .D(n433), .CK(clk), .RN(
n5454), .Q(P_Sgf[12]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_11_ ( .D(n432), .CK(clk), .RN(
n5456), .Q(P_Sgf[11]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_10_ ( .D(n431), .CK(clk), .RN(
n5456), .Q(P_Sgf[10]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_9_ ( .D(n430), .CK(clk), .RN(
n5478), .Q(P_Sgf[9]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_8_ ( .D(n429), .CK(clk), .RN(
n5478), .Q(P_Sgf[8]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_7_ ( .D(n428), .CK(clk), .RN(
n5478), .Q(P_Sgf[7]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_6_ ( .D(n427), .CK(clk), .RN(
n5458), .Q(P_Sgf[6]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_5_ ( .D(n426), .CK(clk), .RN(
n5456), .Q(P_Sgf[5]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_4_ ( .D(n425), .CK(clk), .RN(
n5454), .Q(P_Sgf[4]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_3_ ( .D(n424), .CK(clk), .RN(
n5454), .Q(P_Sgf[3]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_2_ ( .D(n423), .CK(clk), .RN(
n5454), .Q(P_Sgf[2]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_1_ ( .D(n422), .CK(clk), .RN(
n5454), .Q(P_Sgf[1]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_0_ ( .D(n421), .CK(clk), .RN(
n5454), .Q(P_Sgf[0]) );
DFFRXLTS Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n405), .CK(clk), .RN(n5459), .Q(
Exp_module_Overflow_flag_A) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n356), .CK(clk),
.RN(n5473), .QN(n790) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n351),
.CK(clk), .RN(n5473), .Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n350),
.CK(clk), .RN(n5473), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n349),
.CK(clk), .RN(n5473), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n348),
.CK(clk), .RN(n5473), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n347),
.CK(clk), .RN(n5473), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n346),
.CK(clk), .RN(n5473), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n345),
.CK(clk), .RN(n5464), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n344),
.CK(clk), .RN(n5462), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n343),
.CK(clk), .RN(n5466), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n342),
.CK(clk), .RN(n3684), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n341),
.CK(clk), .RN(n5470), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n340),
.CK(clk), .RN(n5465), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n339),
.CK(clk), .RN(n5476), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n338),
.CK(clk), .RN(n5475), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n337),
.CK(clk), .RN(n5464), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n336),
.CK(clk), .RN(n5462), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n335),
.CK(clk), .RN(n5466), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n334),
.CK(clk), .RN(n3684), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n333),
.CK(clk), .RN(n5473), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n332),
.CK(clk), .RN(n5473), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n331),
.CK(clk), .RN(n5476), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n330),
.CK(clk), .RN(n5475), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n329),
.CK(clk), .RN(n5464), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n328),
.CK(clk), .RN(n5462), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n327),
.CK(clk), .RN(n5466), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n326),
.CK(clk), .RN(n3684), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n325),
.CK(clk), .RN(n5465), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n324),
.CK(clk), .RN(n5470), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n323),
.CK(clk), .RN(n5476), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n322),
.CK(clk), .RN(n5475), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n321),
.CK(clk), .RN(n5460), .Q(final_result_ieee[30]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n320),
.CK(clk), .RN(n5472), .Q(final_result_ieee[31]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_32_ ( .D(n319),
.CK(clk), .RN(n5477), .Q(final_result_ieee[32]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_33_ ( .D(n318),
.CK(clk), .RN(n5469), .Q(final_result_ieee[33]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_34_ ( .D(n317),
.CK(clk), .RN(n5461), .Q(final_result_ieee[34]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_35_ ( .D(n316),
.CK(clk), .RN(n5471), .Q(final_result_ieee[35]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_36_ ( .D(n315),
.CK(clk), .RN(n5467), .Q(final_result_ieee[36]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_37_ ( .D(n314),
.CK(clk), .RN(n5474), .Q(final_result_ieee[37]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_38_ ( .D(n313),
.CK(clk), .RN(n5468), .Q(final_result_ieee[38]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_39_ ( .D(n312),
.CK(clk), .RN(n5472), .Q(final_result_ieee[39]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_40_ ( .D(n311),
.CK(clk), .RN(n5477), .Q(final_result_ieee[40]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_41_ ( .D(n310),
.CK(clk), .RN(n3683), .Q(final_result_ieee[41]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_42_ ( .D(n309),
.CK(clk), .RN(n5474), .Q(final_result_ieee[42]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_43_ ( .D(n308),
.CK(clk), .RN(n5467), .Q(final_result_ieee[43]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_44_ ( .D(n307),
.CK(clk), .RN(n3683), .Q(final_result_ieee[44]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_45_ ( .D(n306),
.CK(clk), .RN(n5463), .Q(final_result_ieee[45]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_46_ ( .D(n305),
.CK(clk), .RN(n5468), .Q(final_result_ieee[46]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_47_ ( .D(n304),
.CK(clk), .RN(n5472), .Q(final_result_ieee[47]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_48_ ( .D(n303),
.CK(clk), .RN(n5467), .Q(final_result_ieee[48]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_49_ ( .D(n302),
.CK(clk), .RN(n5474), .Q(final_result_ieee[49]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_50_ ( .D(n301),
.CK(clk), .RN(n744), .Q(final_result_ieee[50]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_51_ ( .D(n300),
.CK(clk), .RN(n744), .Q(final_result_ieee[51]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_52_ ( .D(n299),
.CK(clk), .RN(n3683), .Q(final_result_ieee[52]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_53_ ( .D(n298),
.CK(clk), .RN(n5463), .Q(final_result_ieee[53]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_54_ ( .D(n297),
.CK(clk), .RN(n5474), .Q(final_result_ieee[54]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_55_ ( .D(n296),
.CK(clk), .RN(n5467), .Q(final_result_ieee[55]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_56_ ( .D(n295),
.CK(clk), .RN(n5468), .Q(final_result_ieee[56]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_57_ ( .D(n294),
.CK(clk), .RN(n5472), .Q(final_result_ieee[57]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_58_ ( .D(n293),
.CK(clk), .RN(n744), .Q(final_result_ieee[58]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_59_ ( .D(n292),
.CK(clk), .RN(n744), .Q(final_result_ieee[59]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_60_ ( .D(n291),
.CK(clk), .RN(n3683), .Q(final_result_ieee[60]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_61_ ( .D(n290),
.CK(clk), .RN(n5463), .Q(final_result_ieee[61]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_62_ ( .D(n289),
.CK(clk), .RN(n5467), .Q(final_result_ieee[62]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_63_ ( .D(n287),
.CK(clk), .RN(n5474), .Q(final_result_ieee[63]), .QN(n5450) );
CMPR42X1TS mult_x_24_U350 ( .A(mult_x_24_n580), .B(mult_x_24_n913), .C(
mult_x_24_n583), .D(mult_x_24_n940), .ICI(mult_x_24_n581), .S(
mult_x_24_n578), .ICO(mult_x_24_n576), .CO(mult_x_24_n577) );
CMPR42X1TS mult_x_24_U348 ( .A(mult_x_24_n912), .B(mult_x_24_n575), .C(
mult_x_24_n576), .D(mult_x_24_n939), .ICI(mult_x_24_n577), .S(
mult_x_24_n573), .ICO(mult_x_24_n571), .CO(mult_x_24_n572) );
CMPR42X1TS mult_x_24_U346 ( .A(mult_x_24_n911), .B(mult_x_24_n570), .C(
mult_x_24_n571), .D(mult_x_24_n938), .ICI(mult_x_24_n572), .S(
mult_x_24_n568), .ICO(mult_x_24_n566), .CO(mult_x_24_n567) );
CMPR42X1TS mult_x_24_U343 ( .A(mult_x_24_n910), .B(mult_x_24_n563), .C(
mult_x_24_n566), .D(mult_x_24_n937), .ICI(mult_x_24_n567), .S(
mult_x_24_n561), .ICO(mult_x_24_n559), .CO(mult_x_24_n560) );
CMPR42X1TS mult_x_24_U340 ( .A(mult_x_24_n909), .B(mult_x_24_n556), .C(
mult_x_24_n559), .D(mult_x_24_n936), .ICI(mult_x_24_n560), .S(
mult_x_24_n554), .ICO(mult_x_24_n552), .CO(mult_x_24_n553) );
CMPR42X1TS mult_x_24_U337 ( .A(mult_x_24_n908), .B(mult_x_24_n549), .C(
mult_x_24_n552), .D(mult_x_24_n935), .ICI(mult_x_24_n553), .S(
mult_x_24_n547), .ICO(mult_x_24_n545), .CO(mult_x_24_n546) );
CMPR42X1TS mult_x_24_U335 ( .A(mult_x_24_n544), .B(mult_x_24_n853), .C(
mult_x_24_n550), .D(mult_x_24_n880), .ICI(mult_x_24_n548), .S(
mult_x_24_n542), .ICO(mult_x_24_n540), .CO(mult_x_24_n541) );
CMPR42X1TS mult_x_24_U334 ( .A(mult_x_24_n907), .B(mult_x_24_n542), .C(
mult_x_24_n545), .D(mult_x_24_n934), .ICI(mult_x_24_n546), .S(
mult_x_24_n539), .ICO(mult_x_24_n537), .CO(mult_x_24_n538) );
CMPR42X1TS mult_x_24_U332 ( .A(mult_x_24_n852), .B(mult_x_24_n536), .C(
mult_x_24_n540), .D(mult_x_24_n879), .ICI(mult_x_24_n541), .S(
mult_x_24_n534), .ICO(mult_x_24_n532), .CO(mult_x_24_n533) );
CMPR42X1TS mult_x_24_U331 ( .A(mult_x_24_n906), .B(mult_x_24_n534), .C(
mult_x_24_n537), .D(mult_x_24_n933), .ICI(mult_x_24_n538), .S(
mult_x_24_n531), .ICO(mult_x_24_n529), .CO(mult_x_24_n530) );
CMPR42X1TS mult_x_24_U329 ( .A(mult_x_24_n851), .B(mult_x_24_n528), .C(
mult_x_24_n532), .D(mult_x_24_n878), .ICI(mult_x_24_n533), .S(
mult_x_24_n526), .ICO(mult_x_24_n524), .CO(mult_x_24_n525) );
CMPR42X1TS mult_x_24_U328 ( .A(mult_x_24_n905), .B(mult_x_24_n526), .C(
mult_x_24_n529), .D(mult_x_24_n932), .ICI(mult_x_24_n530), .S(
mult_x_24_n523), .ICO(mult_x_24_n521), .CO(mult_x_24_n522) );
CMPR42X1TS mult_x_24_U325 ( .A(mult_x_24_n850), .B(mult_x_24_n518), .C(
mult_x_24_n524), .D(mult_x_24_n877), .ICI(mult_x_24_n525), .S(
mult_x_24_n516), .ICO(mult_x_24_n514), .CO(mult_x_24_n515) );
CMPR42X1TS mult_x_24_U324 ( .A(mult_x_24_n904), .B(mult_x_24_n516), .C(
mult_x_24_n521), .D(mult_x_24_n931), .ICI(mult_x_24_n522), .S(
mult_x_24_n513), .ICO(mult_x_24_n511), .CO(mult_x_24_n512) );
CMPR42X1TS mult_x_24_U321 ( .A(mult_x_24_n849), .B(mult_x_24_n508), .C(
mult_x_24_n514), .D(mult_x_24_n876), .ICI(mult_x_24_n515), .S(
mult_x_24_n506), .ICO(mult_x_24_n504), .CO(mult_x_24_n505) );
CMPR42X1TS mult_x_24_U320 ( .A(mult_x_24_n506), .B(mult_x_24_n903), .C(
mult_x_24_n511), .D(mult_x_24_n930), .ICI(mult_x_24_n512), .S(
mult_x_24_n503), .ICO(mult_x_24_n501), .CO(mult_x_24_n502) );
CMPR42X1TS mult_x_24_U317 ( .A(mult_x_24_n848), .B(mult_x_24_n498), .C(
mult_x_24_n504), .D(mult_x_24_n875), .ICI(mult_x_24_n505), .S(
mult_x_24_n496), .ICO(mult_x_24_n494), .CO(mult_x_24_n495) );
CMPR42X1TS mult_x_24_U316 ( .A(mult_x_24_n496), .B(mult_x_24_n902), .C(
mult_x_24_n501), .D(mult_x_24_n929), .ICI(mult_x_24_n502), .S(
mult_x_24_n493), .ICO(mult_x_24_n491), .CO(mult_x_24_n492) );
CMPR42X1TS mult_x_24_U314 ( .A(mult_x_24_n490), .B(mult_x_24_n793), .C(
mult_x_24_n499), .D(mult_x_24_n820), .ICI(mult_x_24_n497), .S(
mult_x_24_n488), .ICO(mult_x_24_n486), .CO(mult_x_24_n487) );
CMPR42X1TS mult_x_24_U313 ( .A(mult_x_24_n847), .B(mult_x_24_n488), .C(
mult_x_24_n494), .D(mult_x_24_n874), .ICI(mult_x_24_n495), .S(
mult_x_24_n485), .ICO(mult_x_24_n483), .CO(mult_x_24_n484) );
CMPR42X1TS mult_x_24_U312 ( .A(mult_x_24_n485), .B(mult_x_24_n901), .C(
mult_x_24_n491), .D(mult_x_24_n928), .ICI(mult_x_24_n492), .S(
mult_x_24_n482), .ICO(mult_x_24_n480), .CO(mult_x_24_n481) );
CMPR42X1TS mult_x_24_U310 ( .A(mult_x_24_n792), .B(mult_x_24_n479), .C(
mult_x_24_n486), .D(mult_x_24_n819), .ICI(mult_x_24_n487), .S(
mult_x_24_n477), .ICO(mult_x_24_n475), .CO(mult_x_24_n476) );
CMPR42X1TS mult_x_24_U309 ( .A(mult_x_24_n846), .B(mult_x_24_n477), .C(
mult_x_24_n483), .D(mult_x_24_n873), .ICI(mult_x_24_n484), .S(
mult_x_24_n474), .ICO(mult_x_24_n472), .CO(mult_x_24_n473) );
CMPR42X1TS mult_x_24_U308 ( .A(mult_x_24_n474), .B(mult_x_24_n900), .C(
mult_x_24_n480), .D(mult_x_24_n927), .ICI(mult_x_24_n481), .S(
mult_x_24_n471), .ICO(mult_x_24_n469), .CO(mult_x_24_n470) );
CMPR42X1TS mult_x_24_U306 ( .A(mult_x_24_n791), .B(mult_x_24_n468), .C(
mult_x_24_n475), .D(mult_x_24_n818), .ICI(mult_x_24_n476), .S(
mult_x_24_n466), .ICO(mult_x_24_n464), .CO(mult_x_24_n465) );
CMPR42X1TS mult_x_24_U305 ( .A(mult_x_24_n845), .B(mult_x_24_n466), .C(
mult_x_24_n472), .D(mult_x_24_n872), .ICI(mult_x_24_n473), .S(
mult_x_24_n463), .ICO(mult_x_24_n461), .CO(mult_x_24_n462) );
CMPR42X1TS mult_x_24_U304 ( .A(mult_x_24_n463), .B(mult_x_24_n899), .C(
mult_x_24_n469), .D(mult_x_24_n926), .ICI(mult_x_24_n470), .S(
mult_x_24_n460), .ICO(mult_x_24_n458), .CO(mult_x_24_n459) );
CMPR42X1TS mult_x_24_U301 ( .A(mult_x_24_n790), .B(mult_x_24_n455), .C(
mult_x_24_n464), .D(mult_x_24_n817), .ICI(mult_x_24_n465), .S(
mult_x_24_n453), .ICO(mult_x_24_n451), .CO(mult_x_24_n452) );
CMPR42X1TS mult_x_24_U300 ( .A(mult_x_24_n844), .B(mult_x_24_n453), .C(
mult_x_24_n461), .D(mult_x_24_n871), .ICI(mult_x_24_n462), .S(
mult_x_24_n450), .ICO(mult_x_24_n448), .CO(mult_x_24_n449) );
CMPR42X1TS mult_x_24_U299 ( .A(mult_x_24_n450), .B(mult_x_24_n898), .C(
mult_x_24_n458), .D(mult_x_24_n925), .ICI(mult_x_24_n459), .S(
mult_x_24_n447), .ICO(mult_x_24_n445), .CO(mult_x_24_n446) );
CMPR42X1TS mult_x_24_U296 ( .A(mult_x_24_n789), .B(mult_x_24_n442), .C(
mult_x_24_n451), .D(mult_x_24_n816), .ICI(mult_x_24_n452), .S(
mult_x_24_n440), .ICO(mult_x_24_n438), .CO(mult_x_24_n439) );
CMPR42X1TS mult_x_24_U295 ( .A(mult_x_24_n440), .B(mult_x_24_n843), .C(
mult_x_24_n448), .D(mult_x_24_n870), .ICI(mult_x_24_n449), .S(
mult_x_24_n437), .ICO(mult_x_24_n435), .CO(mult_x_24_n436) );
CMPR42X1TS mult_x_24_U294 ( .A(mult_x_24_n437), .B(mult_x_24_n897), .C(
mult_x_24_n445), .D(mult_x_24_n924), .ICI(mult_x_24_n446), .S(
mult_x_24_n434), .ICO(mult_x_24_n432), .CO(mult_x_24_n433) );
CMPR42X1TS mult_x_24_U291 ( .A(mult_x_24_n788), .B(mult_x_24_n429), .C(
mult_x_24_n438), .D(mult_x_24_n815), .ICI(mult_x_24_n439), .S(
mult_x_24_n427), .ICO(mult_x_24_n425), .CO(mult_x_24_n426) );
CMPR42X1TS mult_x_24_U290 ( .A(mult_x_24_n427), .B(mult_x_24_n842), .C(
mult_x_24_n435), .D(mult_x_24_n869), .ICI(mult_x_24_n436), .S(
mult_x_24_n424), .ICO(mult_x_24_n422), .CO(mult_x_24_n423) );
CMPR42X1TS mult_x_24_U289 ( .A(mult_x_24_n424), .B(mult_x_24_n896), .C(
mult_x_24_n432), .D(mult_x_24_n923), .ICI(mult_x_24_n433), .S(
mult_x_24_n421), .ICO(mult_x_24_n419), .CO(mult_x_24_n420) );
CMPR42X1TS mult_x_24_U288 ( .A(mult_x_24_n625), .B(mult_x_24_n733), .C(
mult_x_24_n430), .D(mult_x_24_n760), .ICI(mult_x_24_n428), .S(
mult_x_24_n418), .ICO(mult_x_24_n416), .CO(mult_x_24_n417) );
CMPR42X1TS mult_x_24_U287 ( .A(mult_x_24_n787), .B(mult_x_24_n418), .C(
mult_x_24_n425), .D(mult_x_24_n814), .ICI(mult_x_24_n426), .S(
mult_x_24_n415), .ICO(mult_x_24_n413), .CO(mult_x_24_n414) );
CMPR42X1TS mult_x_24_U286 ( .A(mult_x_24_n415), .B(mult_x_24_n841), .C(
mult_x_24_n422), .D(mult_x_24_n868), .ICI(mult_x_24_n423), .S(
mult_x_24_n412), .ICO(mult_x_24_n410), .CO(mult_x_24_n411) );
CMPR42X1TS mult_x_24_U285 ( .A(mult_x_24_n412), .B(mult_x_24_n419), .C(
mult_x_24_n895), .D(mult_x_24_n922), .ICI(mult_x_24_n420), .S(
mult_x_24_n409), .ICO(mult_x_24_n407), .CO(mult_x_24_n408) );
CMPR42X1TS mult_x_24_U284 ( .A(mult_x_24_n624), .B(mult_x_24_n732), .C(
mult_x_24_n416), .D(mult_x_24_n759), .ICI(mult_x_24_n417), .S(
mult_x_24_n406), .ICO(mult_x_24_n404), .CO(mult_x_24_n405) );
CMPR42X1TS mult_x_24_U283 ( .A(mult_x_24_n786), .B(mult_x_24_n406), .C(
mult_x_24_n413), .D(mult_x_24_n813), .ICI(mult_x_24_n414), .S(
mult_x_24_n403), .ICO(mult_x_24_n401), .CO(mult_x_24_n402) );
CMPR42X1TS mult_x_24_U282 ( .A(mult_x_24_n403), .B(mult_x_24_n840), .C(
mult_x_24_n410), .D(mult_x_24_n867), .ICI(mult_x_24_n411), .S(
mult_x_24_n400), .ICO(mult_x_24_n398), .CO(mult_x_24_n399) );
CMPR42X1TS mult_x_24_U281 ( .A(mult_x_24_n400), .B(mult_x_24_n407), .C(
mult_x_24_n894), .D(mult_x_24_n921), .ICI(mult_x_24_n408), .S(
mult_x_24_n397), .ICO(mult_x_24_n395), .CO(mult_x_24_n396) );
CMPR42X1TS mult_x_24_U280 ( .A(n731), .B(mult_x_24_n623), .C(mult_x_24_n731),
.D(mult_x_24_n404), .ICI(mult_x_24_n758), .S(mult_x_24_n394), .ICO(
mult_x_24_n392), .CO(mult_x_24_n393) );
CMPR42X1TS mult_x_24_U279 ( .A(mult_x_24_n394), .B(mult_x_24_n405), .C(
mult_x_24_n785), .D(mult_x_24_n401), .ICI(mult_x_24_n812), .S(
mult_x_24_n391), .ICO(mult_x_24_n389), .CO(mult_x_24_n390) );
CMPR42X1TS mult_x_24_U278 ( .A(mult_x_24_n391), .B(mult_x_24_n402), .C(
mult_x_24_n839), .D(mult_x_24_n398), .ICI(mult_x_24_n866), .S(
mult_x_24_n388), .ICO(mult_x_24_n386), .CO(mult_x_24_n387) );
CMPR42X1TS mult_x_24_U277 ( .A(mult_x_24_n399), .B(mult_x_24_n388), .C(
mult_x_24_n395), .D(mult_x_24_n893), .ICI(mult_x_24_n920), .S(
mult_x_24_n385), .ICO(mult_x_24_n383), .CO(mult_x_24_n384) );
CMPR42X1TS mult_x_24_U276 ( .A(n731), .B(mult_x_24_n622), .C(mult_x_24_n392),
.D(mult_x_24_n730), .ICI(mult_x_24_n393), .S(mult_x_24_n382), .ICO(
mult_x_24_n380), .CO(mult_x_24_n381) );
CMPR42X1TS mult_x_24_U275 ( .A(mult_x_24_n757), .B(mult_x_24_n382), .C(
mult_x_24_n389), .D(mult_x_24_n784), .ICI(mult_x_24_n390), .S(
mult_x_24_n379), .ICO(mult_x_24_n377), .CO(mult_x_24_n378) );
CMPR42X1TS mult_x_24_U274 ( .A(mult_x_24_n811), .B(mult_x_24_n379), .C(
mult_x_24_n386), .D(mult_x_24_n838), .ICI(mult_x_24_n387), .S(
mult_x_24_n376), .ICO(mult_x_24_n374), .CO(mult_x_24_n375) );
CMPR42X1TS mult_x_24_U273 ( .A(mult_x_24_n865), .B(mult_x_24_n376), .C(
mult_x_24_n383), .D(mult_x_24_n892), .ICI(mult_x_24_n384), .S(
mult_x_24_n373), .ICO(mult_x_24_n371), .CO(mult_x_24_n372) );
CMPR42X1TS mult_x_24_U272 ( .A(n731), .B(mult_x_24_n621), .C(mult_x_24_n380),
.D(mult_x_24_n729), .ICI(mult_x_24_n381), .S(mult_x_24_n370), .ICO(
mult_x_24_n368), .CO(mult_x_24_n369) );
CMPR42X1TS mult_x_24_U271 ( .A(mult_x_24_n756), .B(mult_x_24_n370), .C(
mult_x_24_n377), .D(mult_x_24_n783), .ICI(mult_x_24_n378), .S(
mult_x_24_n367), .ICO(mult_x_24_n365), .CO(mult_x_24_n366) );
CMPR42X1TS mult_x_24_U270 ( .A(mult_x_24_n810), .B(mult_x_24_n367), .C(
mult_x_24_n374), .D(mult_x_24_n837), .ICI(mult_x_24_n375), .S(
mult_x_24_n364), .ICO(mult_x_24_n362), .CO(mult_x_24_n363) );
CMPR42X1TS mult_x_24_U269 ( .A(mult_x_24_n864), .B(mult_x_24_n364), .C(
mult_x_24_n371), .D(mult_x_24_n891), .ICI(mult_x_24_n918), .S(
mult_x_24_n361), .ICO(mult_x_24_n359), .CO(mult_x_24_n360) );
CMPR42X1TS mult_x_24_U268 ( .A(n4510), .B(n5453), .C(mult_x_24_n620), .D(
mult_x_24_n368), .ICI(mult_x_24_n728), .S(mult_x_24_n358), .ICO(
mult_x_24_n356), .CO(mult_x_24_n357) );
CMPR42X1TS mult_x_24_U267 ( .A(mult_x_24_n358), .B(mult_x_24_n369), .C(
mult_x_24_n755), .D(mult_x_24_n365), .ICI(mult_x_24_n782), .S(
mult_x_24_n355), .ICO(mult_x_24_n353), .CO(mult_x_24_n354) );
CMPR42X1TS mult_x_24_U266 ( .A(mult_x_24_n355), .B(mult_x_24_n366), .C(
mult_x_24_n809), .D(mult_x_24_n362), .ICI(mult_x_24_n836), .S(
mult_x_24_n352), .ICO(mult_x_24_n350), .CO(mult_x_24_n351) );
CMPR42X1TS mult_x_24_U265 ( .A(mult_x_24_n352), .B(mult_x_24_n363), .C(
mult_x_24_n863), .D(mult_x_24_n359), .ICI(mult_x_24_n890), .S(
mult_x_24_n349), .ICO(mult_x_24_n347), .CO(mult_x_24_n348) );
CMPR42X1TS mult_x_24_U262 ( .A(mult_x_24_n357), .B(mult_x_24_n345), .C(
mult_x_24_n353), .D(mult_x_24_n754), .ICI(mult_x_24_n781), .S(
mult_x_24_n343), .ICO(mult_x_24_n341), .CO(mult_x_24_n342) );
CMPR42X1TS mult_x_24_U261 ( .A(mult_x_24_n354), .B(mult_x_24_n343), .C(
mult_x_24_n350), .D(mult_x_24_n808), .ICI(mult_x_24_n835), .S(
mult_x_24_n340), .ICO(mult_x_24_n338), .CO(mult_x_24_n339) );
CMPR42X1TS mult_x_24_U260 ( .A(mult_x_24_n351), .B(mult_x_24_n340), .C(
mult_x_24_n347), .D(mult_x_24_n862), .ICI(mult_x_24_n889), .S(
mult_x_24_n337), .ICO(mult_x_24_n335), .CO(mult_x_24_n336) );
CMPR42X1TS mult_x_24_U257 ( .A(mult_x_24_n344), .B(mult_x_24_n333), .C(
mult_x_24_n341), .D(mult_x_24_n753), .ICI(mult_x_24_n342), .S(
mult_x_24_n331), .ICO(mult_x_24_n329), .CO(mult_x_24_n330) );
CMPR42X1TS mult_x_24_U256 ( .A(mult_x_24_n780), .B(mult_x_24_n331), .C(
mult_x_24_n338), .D(mult_x_24_n807), .ICI(mult_x_24_n339), .S(
mult_x_24_n328), .ICO(mult_x_24_n326), .CO(mult_x_24_n327) );
CMPR42X1TS mult_x_24_U255 ( .A(mult_x_24_n834), .B(mult_x_24_n328), .C(
mult_x_24_n335), .D(mult_x_24_n861), .ICI(mult_x_24_n888), .S(
mult_x_24_n325), .ICO(mult_x_24_n323), .CO(mult_x_24_n324) );
CMPR42X1TS mult_x_24_U253 ( .A(mult_x_24_n322), .B(mult_x_24_n725), .C(
mult_x_24_n332), .D(mult_x_24_n329), .ICI(mult_x_24_n752), .S(
mult_x_24_n320), .ICO(mult_x_24_n318), .CO(mult_x_24_n319) );
CMPR42X1TS mult_x_24_U252 ( .A(mult_x_24_n320), .B(mult_x_24_n330), .C(
mult_x_24_n779), .D(mult_x_24_n326), .ICI(mult_x_24_n806), .S(
mult_x_24_n317), .ICO(mult_x_24_n315), .CO(mult_x_24_n316) );
CMPR42X1TS mult_x_24_U251 ( .A(mult_x_24_n317), .B(mult_x_24_n327), .C(
mult_x_24_n833), .D(mult_x_24_n323), .ICI(mult_x_24_n860), .S(
mult_x_24_n314), .ICO(mult_x_24_n312), .CO(mult_x_24_n313) );
CMPR42X1TS mult_x_24_U249 ( .A(mult_x_24_n311), .B(mult_x_24_n321), .C(
mult_x_24_n318), .D(mult_x_24_n724), .ICI(mult_x_24_n751), .S(
mult_x_24_n310), .ICO(mult_x_24_n308), .CO(mult_x_24_n309) );
CMPR42X1TS mult_x_24_U248 ( .A(mult_x_24_n319), .B(mult_x_24_n310), .C(
mult_x_24_n315), .D(mult_x_24_n778), .ICI(mult_x_24_n805), .S(
mult_x_24_n307), .ICO(mult_x_24_n305), .CO(mult_x_24_n306) );
CMPR42X1TS mult_x_24_U247 ( .A(mult_x_24_n316), .B(mult_x_24_n307), .C(
mult_x_24_n312), .D(mult_x_24_n832), .ICI(mult_x_24_n859), .S(
mult_x_24_n304), .ICO(mult_x_24_n302), .CO(mult_x_24_n303) );
CMPR42X1TS mult_x_24_U245 ( .A(mult_x_24_n616), .B(mult_x_24_n301), .C(
mult_x_24_n308), .D(mult_x_24_n723), .ICI(mult_x_24_n309), .S(
mult_x_24_n300), .ICO(mult_x_24_n298), .CO(mult_x_24_n299) );
CMPR42X1TS mult_x_24_U244 ( .A(mult_x_24_n750), .B(mult_x_24_n300), .C(
mult_x_24_n305), .D(mult_x_24_n777), .ICI(mult_x_24_n306), .S(
mult_x_24_n297), .ICO(mult_x_24_n295), .CO(mult_x_24_n296) );
CMPR42X1TS mult_x_24_U243 ( .A(mult_x_24_n804), .B(mult_x_24_n297), .C(
mult_x_24_n302), .D(mult_x_24_n831), .ICI(mult_x_24_n858), .S(
mult_x_24_n294), .ICO(mult_x_24_n292), .CO(mult_x_24_n293) );
CMPR42X1TS mult_x_24_U242 ( .A(n5452), .B(mult_x_24_n614), .C(mult_x_24_n615), .D(mult_x_24_n298), .ICI(mult_x_24_n722), .S(mult_x_24_n291), .ICO(
mult_x_24_n289), .CO(mult_x_24_n290) );
CMPR42X1TS mult_x_24_U241 ( .A(mult_x_24_n291), .B(mult_x_24_n299), .C(
mult_x_24_n749), .D(mult_x_24_n295), .ICI(mult_x_24_n776), .S(
mult_x_24_n288), .ICO(mult_x_24_n286), .CO(mult_x_24_n287) );
CMPR42X1TS mult_x_24_U240 ( .A(mult_x_24_n288), .B(mult_x_24_n296), .C(
mult_x_24_n803), .D(mult_x_24_n292), .ICI(mult_x_24_n830), .S(
mult_x_24_n285), .ICO(mult_x_24_n283), .CO(mult_x_24_n284) );
CMPR42X1TS mult_x_24_U237 ( .A(mult_x_24_n290), .B(mult_x_24_n281), .C(
mult_x_24_n286), .D(mult_x_24_n748), .ICI(mult_x_24_n775), .S(
mult_x_24_n279), .ICO(mult_x_24_n277), .CO(mult_x_24_n278) );
CMPR42X1TS mult_x_24_U236 ( .A(mult_x_24_n287), .B(mult_x_24_n279), .C(
mult_x_24_n283), .D(mult_x_24_n802), .ICI(mult_x_24_n829), .S(
mult_x_24_n276), .ICO(mult_x_24_n274), .CO(mult_x_24_n275) );
CMPR42X1TS mult_x_24_U233 ( .A(mult_x_24_n280), .B(mult_x_24_n272), .C(
mult_x_24_n277), .D(mult_x_24_n747), .ICI(mult_x_24_n278), .S(
mult_x_24_n270), .ICO(mult_x_24_n268), .CO(mult_x_24_n269) );
CMPR42X1TS mult_x_24_U232 ( .A(mult_x_24_n774), .B(mult_x_24_n270), .C(
mult_x_24_n274), .D(mult_x_24_n801), .ICI(mult_x_24_n828), .S(
mult_x_24_n267), .ICO(mult_x_24_n265), .CO(mult_x_24_n266) );
CMPR42X1TS mult_x_24_U230 ( .A(mult_x_24_n264), .B(mult_x_24_n271), .C(
mult_x_24_n719), .D(mult_x_24_n268), .ICI(mult_x_24_n746), .S(
mult_x_24_n262), .ICO(mult_x_24_n260), .CO(mult_x_24_n261) );
CMPR42X1TS mult_x_24_U229 ( .A(mult_x_24_n262), .B(mult_x_24_n269), .C(
mult_x_24_n773), .D(mult_x_24_n265), .ICI(mult_x_24_n800), .S(
mult_x_24_n259), .ICO(mult_x_24_n257), .CO(mult_x_24_n258) );
CMPR42X1TS mult_x_24_U227 ( .A(mult_x_24_n256), .B(mult_x_24_n263), .C(
mult_x_24_n260), .D(mult_x_24_n718), .ICI(mult_x_24_n745), .S(
mult_x_24_n255), .ICO(mult_x_24_n253), .CO(mult_x_24_n254) );
CMPR42X1TS mult_x_24_U226 ( .A(mult_x_24_n261), .B(mult_x_24_n255), .C(
mult_x_24_n257), .D(mult_x_24_n772), .ICI(mult_x_24_n799), .S(
mult_x_24_n252), .ICO(mult_x_24_n250), .CO(mult_x_24_n251) );
CMPR42X1TS mult_x_24_U224 ( .A(mult_x_24_n610), .B(mult_x_24_n249), .C(
mult_x_24_n253), .D(mult_x_24_n717), .ICI(mult_x_24_n254), .S(
mult_x_24_n248), .ICO(mult_x_24_n246), .CO(mult_x_24_n247) );
CMPR42X1TS mult_x_24_U223 ( .A(mult_x_24_n744), .B(mult_x_24_n248), .C(
mult_x_24_n250), .D(mult_x_24_n771), .ICI(mult_x_24_n798), .S(
mult_x_24_n245), .ICO(mult_x_24_n243), .CO(mult_x_24_n244) );
CMPR42X1TS mult_x_24_U222 ( .A(n4174), .B(mult_x_24_n609), .C(mult_x_24_n608), .D(mult_x_24_n246), .ICI(mult_x_24_n716), .S(mult_x_24_n242), .ICO(
mult_x_24_n240), .CO(mult_x_24_n241) );
CMPR42X1TS mult_x_24_U221 ( .A(mult_x_24_n242), .B(mult_x_24_n247), .C(
mult_x_24_n743), .D(mult_x_24_n243), .ICI(mult_x_24_n770), .S(
mult_x_24_n239), .ICO(mult_x_24_n237), .CO(mult_x_24_n238) );
CMPR42X1TS mult_x_24_U218 ( .A(mult_x_24_n241), .B(mult_x_24_n235), .C(
mult_x_24_n237), .D(mult_x_24_n742), .ICI(mult_x_24_n769), .S(
mult_x_24_n233), .ICO(mult_x_24_n231), .CO(mult_x_24_n232) );
CMPR42X1TS mult_x_24_U215 ( .A(mult_x_24_n714), .B(mult_x_24_n229), .C(
mult_x_24_n231), .D(mult_x_24_n741), .ICI(mult_x_24_n768), .S(
mult_x_24_n227), .ICO(mult_x_24_n225), .CO(mult_x_24_n226) );
CMPR42X1TS mult_x_24_U213 ( .A(mult_x_24_n224), .B(mult_x_24_n228), .C(
mult_x_24_n713), .D(mult_x_24_n225), .ICI(mult_x_24_n740), .S(
mult_x_24_n222), .ICO(mult_x_24_n220), .CO(mult_x_24_n221) );
CMPR42X1TS mult_x_24_U211 ( .A(mult_x_24_n219), .B(mult_x_24_n223), .C(
mult_x_24_n220), .D(mult_x_24_n712), .ICI(mult_x_24_n739), .S(
mult_x_24_n218), .ICO(mult_x_24_n216), .CO(mult_x_24_n217) );
CMPR42X1TS mult_x_24_U209 ( .A(mult_x_24_n603), .B(mult_x_24_n219), .C(
mult_x_24_n216), .D(mult_x_24_n711), .ICI(mult_x_24_n738), .S(
mult_x_24_n214), .ICO(mult_x_24_n212), .CO(mult_x_24_n213) );
CMPR42X1TS mult_x_24_U208 ( .A(n5451), .B(mult_x_24_n604), .C(mult_x_24_n602), .D(mult_x_24_n212), .ICI(mult_x_24_n710), .S(mult_x_24_n211), .ICO(
mult_x_24_n209), .CO(mult_x_24_n210) );
CMPR32X2TS DP_OP_36J45_124_1029_U13 ( .A(S_Oper_A_exp[0]), .B(
DP_OP_36J45_124_1029_n42), .C(DP_OP_36J45_124_1029_n28), .CO(
DP_OP_36J45_124_1029_n12), .S(Exp_module_Data_S[0]) );
CMPR32X2TS DP_OP_36J45_124_1029_U12 ( .A(DP_OP_36J45_124_1029_n27), .B(
S_Oper_A_exp[1]), .C(DP_OP_36J45_124_1029_n12), .CO(
DP_OP_36J45_124_1029_n11), .S(Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_36J45_124_1029_U11 ( .A(DP_OP_36J45_124_1029_n26), .B(
S_Oper_A_exp[2]), .C(DP_OP_36J45_124_1029_n11), .CO(
DP_OP_36J45_124_1029_n10), .S(Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_36J45_124_1029_U10 ( .A(DP_OP_36J45_124_1029_n25), .B(
S_Oper_A_exp[3]), .C(DP_OP_36J45_124_1029_n10), .CO(
DP_OP_36J45_124_1029_n9), .S(Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_36J45_124_1029_U9 ( .A(DP_OP_36J45_124_1029_n24), .B(
S_Oper_A_exp[4]), .C(DP_OP_36J45_124_1029_n9), .CO(
DP_OP_36J45_124_1029_n8), .S(Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_36J45_124_1029_U8 ( .A(DP_OP_36J45_124_1029_n23), .B(
S_Oper_A_exp[5]), .C(DP_OP_36J45_124_1029_n8), .CO(
DP_OP_36J45_124_1029_n7), .S(Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_36J45_124_1029_U7 ( .A(DP_OP_36J45_124_1029_n22), .B(
S_Oper_A_exp[6]), .C(DP_OP_36J45_124_1029_n7), .CO(
DP_OP_36J45_124_1029_n6), .S(Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_36J45_124_1029_U6 ( .A(DP_OP_36J45_124_1029_n21), .B(
S_Oper_A_exp[7]), .C(DP_OP_36J45_124_1029_n6), .CO(
DP_OP_36J45_124_1029_n5), .S(Exp_module_Data_S[7]) );
CMPR32X2TS DP_OP_36J45_124_1029_U5 ( .A(DP_OP_36J45_124_1029_n20), .B(
S_Oper_A_exp[8]), .C(DP_OP_36J45_124_1029_n5), .CO(
DP_OP_36J45_124_1029_n4), .S(Exp_module_Data_S[8]) );
CMPR32X2TS DP_OP_36J45_124_1029_U4 ( .A(DP_OP_36J45_124_1029_n19), .B(
S_Oper_A_exp[9]), .C(DP_OP_36J45_124_1029_n4), .CO(
DP_OP_36J45_124_1029_n3), .S(Exp_module_Data_S[9]) );
CMPR32X2TS DP_OP_36J45_124_1029_U3 ( .A(DP_OP_36J45_124_1029_n18), .B(
S_Oper_A_exp[10]), .C(DP_OP_36J45_124_1029_n3), .CO(
DP_OP_36J45_124_1029_n2), .S(Exp_module_Data_S[10]) );
CMPR32X2TS DP_OP_36J45_124_1029_U2 ( .A(DP_OP_36J45_124_1029_n42), .B(
S_Oper_A_exp[11]), .C(DP_OP_36J45_124_1029_n2), .CO(
DP_OP_36J45_124_1029_n1), .S(Exp_module_Data_S[11]) );
DFFRX1TS Exp_module_Underflow_m_Q_reg_0_ ( .D(n352), .CK(clk), .RN(n5469),
.Q(underflow_flag), .QN(n5398) );
DFFRX1TS Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n581), .CK(clk),
.RN(n3683), .Q(zero_flag), .QN(n5396) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_51_ ( .D(n404), .CK(clk),
.RN(n5460), .Q(Sgf_normalized_result[51]), .QN(n5394) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_49_ ( .D(n402), .CK(clk),
.RN(n5465), .Q(Sgf_normalized_result[49]), .QN(n5393) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_47_ ( .D(n400), .CK(clk),
.RN(n5461), .Q(Sgf_normalized_result[47]), .QN(n5392) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_45_ ( .D(n398), .CK(clk),
.RN(n5469), .Q(Sgf_normalized_result[45]), .QN(n5391) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_43_ ( .D(n396), .CK(clk),
.RN(n5471), .Q(Sgf_normalized_result[43]), .QN(n5390) );
DFFRX1TS Sel_B_Q_reg_0_ ( .D(n419), .CK(clk), .RN(n5459), .Q(
FSM_selector_B[0]), .QN(n5388) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_41_ ( .D(n394), .CK(clk),
.RN(n5477), .Q(Sgf_normalized_result[41]), .QN(n5387) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_39_ ( .D(n392), .CK(clk),
.RN(n3684), .Q(Sgf_normalized_result[39]), .QN(n5386) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_37_ ( .D(n390), .CK(clk),
.RN(n5476), .Q(Sgf_normalized_result[37]), .QN(n5385) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_35_ ( .D(n388), .CK(clk),
.RN(n5465), .Q(Sgf_normalized_result[35]), .QN(n5384) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_33_ ( .D(n386), .CK(clk),
.RN(n5470), .Q(Sgf_normalized_result[33]), .QN(n5383) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_31_ ( .D(n384), .CK(clk),
.RN(n5466), .Q(Sgf_normalized_result[31]), .QN(n5382) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_29_ ( .D(n382), .CK(clk),
.RN(n3683), .Q(Sgf_normalized_result[29]), .QN(n5381) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_27_ ( .D(n380), .CK(clk),
.RN(n744), .Q(Sgf_normalized_result[27]), .QN(n5380) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_25_ ( .D(n378), .CK(clk),
.RN(n5474), .Q(Sgf_normalized_result[25]), .QN(n5378) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n376), .CK(clk),
.RN(n744), .Q(Sgf_normalized_result[23]), .QN(n5376) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n374), .CK(clk),
.RN(n5459), .Q(Sgf_normalized_result[21]), .QN(n5375) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n372), .CK(clk),
.RN(n5467), .Q(Sgf_normalized_result[19]), .QN(n5373) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n370), .CK(clk),
.RN(n5472), .Q(Sgf_normalized_result[17]), .QN(n5370) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n368), .CK(clk),
.RN(n3683), .Q(Sgf_normalized_result[15]), .QN(n5368) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n366), .CK(clk),
.RN(n5465), .Q(Sgf_normalized_result[13]), .QN(n5367) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n364), .CK(clk),
.RN(n5475), .Q(Sgf_normalized_result[11]), .QN(n5366) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n362), .CK(clk),
.RN(n5476), .Q(Sgf_normalized_result[9]), .QN(n5365) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n360), .CK(clk),
.RN(n5464), .Q(Sgf_normalized_result[7]), .QN(n5364) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n358), .CK(clk),
.RN(n5462), .Q(Sgf_normalized_result[5]), .QN(n5363) );
DFFRX1TS Sel_C_Q_reg_0_ ( .D(n709), .CK(clk), .RN(n5460), .Q(FSM_selector_C),
.QN(n5362) );
CMPR42X1TS mult_x_23_U319 ( .A(mult_x_23_n515), .B(mult_x_23_n838), .C(
mult_x_23_n518), .D(mult_x_23_n864), .ICI(mult_x_23_n516), .S(
mult_x_23_n513), .ICO(mult_x_23_n511), .CO(mult_x_23_n512) );
CMPR42X1TS mult_x_23_U317 ( .A(mult_x_23_n837), .B(mult_x_23_n510), .C(
mult_x_23_n511), .D(mult_x_23_n863), .ICI(mult_x_23_n512), .S(
mult_x_23_n508), .ICO(mult_x_23_n506), .CO(mult_x_23_n507) );
CMPR42X1TS mult_x_23_U315 ( .A(mult_x_23_n836), .B(mult_x_23_n505), .C(
mult_x_23_n506), .D(mult_x_23_n862), .ICI(mult_x_23_n507), .S(
mult_x_23_n503), .ICO(mult_x_23_n501), .CO(mult_x_23_n502) );
CMPR42X1TS mult_x_23_U312 ( .A(mult_x_23_n835), .B(mult_x_23_n498), .C(
mult_x_23_n501), .D(mult_x_23_n861), .ICI(mult_x_23_n502), .S(
mult_x_23_n496), .ICO(mult_x_23_n494), .CO(mult_x_23_n495) );
CMPR42X1TS mult_x_23_U309 ( .A(mult_x_23_n834), .B(mult_x_23_n491), .C(
mult_x_23_n494), .D(mult_x_23_n860), .ICI(mult_x_23_n495), .S(
mult_x_23_n489), .ICO(mult_x_23_n487), .CO(mult_x_23_n488) );
CMPR42X1TS mult_x_23_U306 ( .A(mult_x_23_n833), .B(mult_x_23_n484), .C(
mult_x_23_n487), .D(mult_x_23_n859), .ICI(mult_x_23_n488), .S(
mult_x_23_n482), .ICO(mult_x_23_n480), .CO(mult_x_23_n481) );
CMPR42X1TS mult_x_23_U304 ( .A(mult_x_23_n479), .B(mult_x_23_n780), .C(
mult_x_23_n485), .D(mult_x_23_n806), .ICI(mult_x_23_n483), .S(
mult_x_23_n477), .ICO(mult_x_23_n475), .CO(mult_x_23_n476) );
CMPR42X1TS mult_x_23_U303 ( .A(mult_x_23_n832), .B(mult_x_23_n477), .C(
mult_x_23_n480), .D(mult_x_23_n858), .ICI(mult_x_23_n481), .S(
mult_x_23_n474), .ICO(mult_x_23_n472), .CO(mult_x_23_n473) );
CMPR42X1TS mult_x_23_U301 ( .A(mult_x_23_n779), .B(mult_x_23_n471), .C(
mult_x_23_n475), .D(mult_x_23_n805), .ICI(mult_x_23_n476), .S(
mult_x_23_n469), .ICO(mult_x_23_n467), .CO(mult_x_23_n468) );
CMPR42X1TS mult_x_23_U300 ( .A(mult_x_23_n831), .B(mult_x_23_n469), .C(
mult_x_23_n472), .D(mult_x_23_n857), .ICI(mult_x_23_n473), .S(
mult_x_23_n466), .ICO(mult_x_23_n464), .CO(mult_x_23_n465) );
CMPR42X1TS mult_x_23_U298 ( .A(mult_x_23_n778), .B(mult_x_23_n463), .C(
mult_x_23_n467), .D(mult_x_23_n804), .ICI(mult_x_23_n468), .S(
mult_x_23_n461), .ICO(mult_x_23_n459), .CO(mult_x_23_n460) );
CMPR42X1TS mult_x_23_U297 ( .A(mult_x_23_n830), .B(mult_x_23_n461), .C(
mult_x_23_n464), .D(mult_x_23_n856), .ICI(mult_x_23_n465), .S(
mult_x_23_n458), .ICO(mult_x_23_n456), .CO(mult_x_23_n457) );
CMPR42X1TS mult_x_23_U294 ( .A(mult_x_23_n777), .B(mult_x_23_n453), .C(
mult_x_23_n459), .D(mult_x_23_n803), .ICI(mult_x_23_n460), .S(
mult_x_23_n451), .ICO(mult_x_23_n449), .CO(mult_x_23_n450) );
CMPR42X1TS mult_x_23_U293 ( .A(mult_x_23_n829), .B(mult_x_23_n451), .C(
mult_x_23_n456), .D(mult_x_23_n855), .ICI(mult_x_23_n457), .S(
mult_x_23_n448), .ICO(mult_x_23_n446), .CO(mult_x_23_n447) );
CMPR42X1TS mult_x_23_U290 ( .A(mult_x_23_n776), .B(mult_x_23_n443), .C(
mult_x_23_n449), .D(mult_x_23_n802), .ICI(mult_x_23_n450), .S(
mult_x_23_n441), .ICO(mult_x_23_n439), .CO(mult_x_23_n440) );
CMPR42X1TS mult_x_23_U289 ( .A(mult_x_23_n441), .B(mult_x_23_n828), .C(
mult_x_23_n446), .D(mult_x_23_n854), .ICI(mult_x_23_n447), .S(
mult_x_23_n438), .ICO(mult_x_23_n436), .CO(mult_x_23_n437) );
CMPR42X1TS mult_x_23_U286 ( .A(mult_x_23_n775), .B(mult_x_23_n433), .C(
mult_x_23_n439), .D(mult_x_23_n801), .ICI(mult_x_23_n440), .S(
mult_x_23_n431), .ICO(mult_x_23_n429), .CO(mult_x_23_n430) );
CMPR42X1TS mult_x_23_U285 ( .A(mult_x_23_n431), .B(mult_x_23_n827), .C(
mult_x_23_n436), .D(mult_x_23_n853), .ICI(mult_x_23_n437), .S(
mult_x_23_n428), .ICO(mult_x_23_n426), .CO(mult_x_23_n427) );
CMPR42X1TS mult_x_23_U283 ( .A(mult_x_23_n425), .B(mult_x_23_n722), .C(
mult_x_23_n434), .D(mult_x_23_n748), .ICI(mult_x_23_n432), .S(
mult_x_23_n423), .ICO(mult_x_23_n421), .CO(mult_x_23_n422) );
CMPR42X1TS mult_x_23_U282 ( .A(mult_x_23_n774), .B(mult_x_23_n423), .C(
mult_x_23_n429), .D(mult_x_23_n800), .ICI(mult_x_23_n430), .S(
mult_x_23_n420), .ICO(mult_x_23_n418), .CO(mult_x_23_n419) );
CMPR42X1TS mult_x_23_U281 ( .A(mult_x_23_n420), .B(mult_x_23_n826), .C(
mult_x_23_n426), .D(mult_x_23_n852), .ICI(mult_x_23_n427), .S(
mult_x_23_n417), .ICO(mult_x_23_n415), .CO(mult_x_23_n416) );
CMPR42X1TS mult_x_23_U279 ( .A(mult_x_23_n721), .B(mult_x_23_n414), .C(
mult_x_23_n421), .D(mult_x_23_n747), .ICI(mult_x_23_n422), .S(
mult_x_23_n412), .ICO(mult_x_23_n410), .CO(mult_x_23_n411) );
CMPR42X1TS mult_x_23_U278 ( .A(mult_x_23_n773), .B(mult_x_23_n412), .C(
mult_x_23_n418), .D(mult_x_23_n799), .ICI(mult_x_23_n419), .S(
mult_x_23_n409), .ICO(mult_x_23_n407), .CO(mult_x_23_n408) );
CMPR42X1TS mult_x_23_U277 ( .A(mult_x_23_n409), .B(mult_x_23_n825), .C(
mult_x_23_n415), .D(mult_x_23_n851), .ICI(mult_x_23_n416), .S(
mult_x_23_n406), .ICO(mult_x_23_n404), .CO(mult_x_23_n405) );
CMPR42X1TS mult_x_23_U275 ( .A(mult_x_23_n720), .B(mult_x_23_n403), .C(
mult_x_23_n410), .D(mult_x_23_n746), .ICI(mult_x_23_n411), .S(
mult_x_23_n401), .ICO(mult_x_23_n399), .CO(mult_x_23_n400) );
CMPR42X1TS mult_x_23_U274 ( .A(mult_x_23_n772), .B(mult_x_23_n401), .C(
mult_x_23_n407), .D(mult_x_23_n798), .ICI(mult_x_23_n408), .S(
mult_x_23_n398), .ICO(mult_x_23_n396), .CO(mult_x_23_n397) );
CMPR42X1TS mult_x_23_U273 ( .A(mult_x_23_n398), .B(mult_x_23_n824), .C(
mult_x_23_n404), .D(mult_x_23_n850), .ICI(mult_x_23_n405), .S(
mult_x_23_n395), .ICO(mult_x_23_n393), .CO(mult_x_23_n394) );
CMPR42X1TS mult_x_23_U271 ( .A(mult_x_23_n719), .B(mult_x_23_n392), .C(
mult_x_23_n399), .D(mult_x_23_n745), .ICI(mult_x_23_n400), .S(
mult_x_23_n390), .ICO(mult_x_23_n388), .CO(mult_x_23_n389) );
CMPR42X1TS mult_x_23_U270 ( .A(mult_x_23_n771), .B(mult_x_23_n390), .C(
mult_x_23_n396), .D(mult_x_23_n797), .ICI(mult_x_23_n397), .S(
mult_x_23_n387), .ICO(mult_x_23_n385), .CO(mult_x_23_n386) );
CMPR42X1TS mult_x_23_U269 ( .A(mult_x_23_n387), .B(mult_x_23_n823), .C(
mult_x_23_n393), .D(mult_x_23_n849), .ICI(mult_x_23_n394), .S(
mult_x_23_n384), .ICO(mult_x_23_n382), .CO(mult_x_23_n383) );
CMPR42X1TS mult_x_23_U267 ( .A(mult_x_23_n718), .B(mult_x_23_n381), .C(
mult_x_23_n388), .D(mult_x_23_n744), .ICI(mult_x_23_n389), .S(
mult_x_23_n379), .ICO(mult_x_23_n377), .CO(mult_x_23_n378) );
CMPR42X1TS mult_x_23_U266 ( .A(mult_x_23_n379), .B(mult_x_23_n770), .C(
mult_x_23_n385), .D(mult_x_23_n796), .ICI(mult_x_23_n386), .S(
mult_x_23_n376), .ICO(mult_x_23_n374), .CO(mult_x_23_n375) );
CMPR42X1TS mult_x_23_U265 ( .A(mult_x_23_n376), .B(mult_x_23_n822), .C(
mult_x_23_n382), .D(mult_x_23_n848), .ICI(mult_x_23_n383), .S(
mult_x_23_n373), .ICO(mult_x_23_n371), .CO(mult_x_23_n372) );
CMPR42X1TS mult_x_23_U263 ( .A(mult_x_23_n717), .B(mult_x_23_n370), .C(
mult_x_23_n377), .D(mult_x_23_n743), .ICI(mult_x_23_n378), .S(
mult_x_23_n368), .ICO(mult_x_23_n366), .CO(mult_x_23_n367) );
CMPR42X1TS mult_x_23_U262 ( .A(mult_x_23_n368), .B(mult_x_23_n769), .C(
mult_x_23_n374), .D(mult_x_23_n795), .ICI(mult_x_23_n375), .S(
mult_x_23_n365), .ICO(mult_x_23_n363), .CO(mult_x_23_n364) );
CMPR42X1TS mult_x_23_U261 ( .A(mult_x_23_n365), .B(mult_x_23_n821), .C(
mult_x_23_n371), .D(mult_x_23_n847), .ICI(mult_x_23_n372), .S(
mult_x_23_n362), .ICO(mult_x_23_n360), .CO(mult_x_23_n361) );
CMPR42X1TS mult_x_23_U259 ( .A(mult_x_23_n716), .B(mult_x_23_n359), .C(
mult_x_23_n366), .D(mult_x_23_n742), .ICI(mult_x_23_n367), .S(
mult_x_23_n357), .ICO(mult_x_23_n355), .CO(mult_x_23_n356) );
CMPR42X1TS mult_x_23_U258 ( .A(mult_x_23_n357), .B(mult_x_23_n768), .C(
mult_x_23_n363), .D(mult_x_23_n794), .ICI(mult_x_23_n364), .S(
mult_x_23_n354), .ICO(mult_x_23_n352), .CO(mult_x_23_n353) );
CMPR42X1TS mult_x_23_U257 ( .A(mult_x_23_n354), .B(mult_x_23_n360), .C(
mult_x_23_n820), .D(mult_x_23_n846), .ICI(mult_x_23_n872), .S(
mult_x_23_n351), .ICO(mult_x_23_n349), .CO(mult_x_23_n350) );
CMPR42X1TS mult_x_23_U255 ( .A(mult_x_23_n348), .B(mult_x_23_n358), .C(
mult_x_23_n715), .D(mult_x_23_n355), .ICI(mult_x_23_n741), .S(
mult_x_23_n346), .ICO(mult_x_23_n344), .CO(mult_x_23_n345) );
CMPR42X1TS mult_x_23_U254 ( .A(mult_x_23_n346), .B(mult_x_23_n356), .C(
mult_x_23_n767), .D(mult_x_23_n352), .ICI(mult_x_23_n793), .S(
mult_x_23_n343), .ICO(mult_x_23_n341), .CO(mult_x_23_n342) );
CMPR42X1TS mult_x_23_U253 ( .A(mult_x_23_n353), .B(mult_x_23_n343), .C(
mult_x_23_n349), .D(mult_x_23_n819), .ICI(mult_x_23_n350), .S(
mult_x_23_n340), .ICO(mult_x_23_n338), .CO(mult_x_23_n339) );
CMPR42X1TS mult_x_23_U251 ( .A(mult_x_23_n347), .B(mult_x_23_n337), .C(
mult_x_23_n344), .D(mult_x_23_n714), .ICI(mult_x_23_n345), .S(
mult_x_23_n335), .ICO(mult_x_23_n333), .CO(mult_x_23_n334) );
CMPR42X1TS mult_x_23_U250 ( .A(mult_x_23_n740), .B(mult_x_23_n335), .C(
mult_x_23_n341), .D(mult_x_23_n766), .ICI(mult_x_23_n342), .S(
mult_x_23_n332), .ICO(mult_x_23_n330), .CO(mult_x_23_n331) );
CMPR42X1TS mult_x_23_U249 ( .A(mult_x_23_n792), .B(mult_x_23_n332), .C(
mult_x_23_n338), .D(mult_x_23_n818), .ICI(mult_x_23_n844), .S(
mult_x_23_n329), .ICO(mult_x_23_n327), .CO(mult_x_23_n328) );
CMPR42X1TS mult_x_23_U247 ( .A(mult_x_23_n336), .B(mult_x_23_n326), .C(
mult_x_23_n333), .D(mult_x_23_n713), .ICI(mult_x_23_n334), .S(
mult_x_23_n324), .ICO(mult_x_23_n322), .CO(mult_x_23_n323) );
CMPR42X1TS mult_x_23_U246 ( .A(mult_x_23_n739), .B(mult_x_23_n324), .C(
mult_x_23_n330), .D(mult_x_23_n765), .ICI(mult_x_23_n331), .S(
mult_x_23_n321), .ICO(mult_x_23_n319), .CO(mult_x_23_n320) );
CMPR42X1TS mult_x_23_U245 ( .A(mult_x_23_n791), .B(mult_x_23_n321), .C(
mult_x_23_n327), .D(mult_x_23_n817), .ICI(mult_x_23_n843), .S(
mult_x_23_n318), .ICO(mult_x_23_n316), .CO(mult_x_23_n317) );
CMPR42X1TS mult_x_23_U243 ( .A(mult_x_23_n315), .B(mult_x_23_n686), .C(
mult_x_23_n325), .D(mult_x_23_n322), .ICI(mult_x_23_n712), .S(
mult_x_23_n313), .ICO(mult_x_23_n311), .CO(mult_x_23_n312) );
CMPR42X1TS mult_x_23_U242 ( .A(mult_x_23_n313), .B(mult_x_23_n323), .C(
mult_x_23_n738), .D(mult_x_23_n319), .ICI(mult_x_23_n764), .S(
mult_x_23_n310), .ICO(mult_x_23_n308), .CO(mult_x_23_n309) );
CMPR42X1TS mult_x_23_U241 ( .A(mult_x_23_n310), .B(mult_x_23_n320), .C(
mult_x_23_n790), .D(mult_x_23_n316), .ICI(mult_x_23_n317), .S(
mult_x_23_n307), .ICO(mult_x_23_n305), .CO(mult_x_23_n306) );
CMPR42X1TS mult_x_23_U239 ( .A(mult_x_23_n314), .B(mult_x_23_n304), .C(
mult_x_23_n311), .D(mult_x_23_n685), .ICI(mult_x_23_n711), .S(
mult_x_23_n303), .ICO(mult_x_23_n301), .CO(mult_x_23_n302) );
CMPR42X1TS mult_x_23_U238 ( .A(mult_x_23_n312), .B(mult_x_23_n303), .C(
mult_x_23_n308), .D(mult_x_23_n737), .ICI(mult_x_23_n763), .S(
mult_x_23_n300), .ICO(mult_x_23_n298), .CO(mult_x_23_n299) );
CMPR42X1TS mult_x_23_U237 ( .A(mult_x_23_n309), .B(mult_x_23_n300), .C(
mult_x_23_n305), .D(mult_x_23_n789), .ICI(mult_x_23_n815), .S(
mult_x_23_n297), .ICO(mult_x_23_n295), .CO(mult_x_23_n296) );
CMPR42X1TS mult_x_23_U235 ( .A(mult_x_23_n304), .B(mult_x_23_n659), .C(
mult_x_23_n301), .D(mult_x_23_n684), .ICI(mult_x_23_n302), .S(
mult_x_23_n292), .ICO(mult_x_23_n290), .CO(mult_x_23_n291) );
CMPR42X1TS mult_x_23_U234 ( .A(mult_x_23_n710), .B(mult_x_23_n292), .C(
mult_x_23_n298), .D(mult_x_23_n736), .ICI(mult_x_23_n299), .S(
mult_x_23_n289), .ICO(mult_x_23_n287), .CO(mult_x_23_n288) );
CMPR42X1TS mult_x_23_U233 ( .A(mult_x_23_n762), .B(mult_x_23_n289), .C(
mult_x_23_n295), .D(mult_x_23_n788), .ICI(mult_x_23_n814), .S(
mult_x_23_n286), .ICO(mult_x_23_n284), .CO(mult_x_23_n285) );
CMPR42X1TS mult_x_23_U232 ( .A(n5336), .B(mult_x_23_n293), .C(mult_x_23_n658), .D(mult_x_23_n290), .ICI(mult_x_23_n683), .S(mult_x_23_n283), .ICO(
mult_x_23_n265), .CO(mult_x_23_n282) );
CMPR42X1TS mult_x_23_U231 ( .A(mult_x_23_n283), .B(mult_x_23_n291), .C(
mult_x_23_n709), .D(mult_x_23_n287), .ICI(mult_x_23_n735), .S(
mult_x_23_n281), .ICO(mult_x_23_n279), .CO(mult_x_23_n280) );
CMPR42X1TS mult_x_23_U230 ( .A(mult_x_23_n281), .B(mult_x_23_n288), .C(
mult_x_23_n761), .D(mult_x_23_n284), .ICI(mult_x_23_n285), .S(
mult_x_23_n278), .ICO(mult_x_23_n276), .CO(mult_x_23_n277) );
CMPR42X1TS mult_x_23_U227 ( .A(mult_x_23_n282), .B(mult_x_23_n274), .C(
mult_x_23_n279), .D(mult_x_23_n708), .ICI(mult_x_23_n734), .S(
mult_x_23_n272), .ICO(mult_x_23_n270), .CO(mult_x_23_n271) );
CMPR42X1TS mult_x_23_U226 ( .A(mult_x_23_n280), .B(mult_x_23_n272), .C(
mult_x_23_n276), .D(mult_x_23_n760), .ICI(mult_x_23_n786), .S(
mult_x_23_n269), .ICO(mult_x_23_n267), .CO(mult_x_23_n268) );
CMPR42X1TS mult_x_23_U223 ( .A(mult_x_23_n273), .B(mult_x_23_n264), .C(
mult_x_23_n270), .D(mult_x_23_n707), .ICI(mult_x_23_n271), .S(
mult_x_23_n262), .ICO(mult_x_23_n260), .CO(mult_x_23_n261) );
CMPR42X1TS mult_x_23_U222 ( .A(mult_x_23_n733), .B(mult_x_23_n262), .C(
mult_x_23_n267), .D(mult_x_23_n759), .ICI(mult_x_23_n785), .S(
mult_x_23_n259), .ICO(mult_x_23_n257), .CO(mult_x_23_n258) );
CMPR42X1TS mult_x_23_U220 ( .A(mult_x_23_n256), .B(mult_x_23_n263), .C(
mult_x_23_n680), .D(mult_x_23_n260), .ICI(mult_x_23_n706), .S(
mult_x_23_n255), .ICO(mult_x_23_n253), .CO(mult_x_23_n254) );
CMPR42X1TS mult_x_23_U219 ( .A(mult_x_23_n255), .B(mult_x_23_n261), .C(
mult_x_23_n732), .D(mult_x_23_n257), .ICI(mult_x_23_n258), .S(
mult_x_23_n252), .ICO(mult_x_23_n250), .CO(mult_x_23_n251) );
CMPR42X1TS mult_x_23_U217 ( .A(mult_x_23_n654), .B(mult_x_23_n249), .C(
mult_x_23_n253), .D(mult_x_23_n679), .ICI(mult_x_23_n705), .S(
mult_x_23_n248), .ICO(mult_x_23_n246), .CO(mult_x_23_n247) );
CMPR42X1TS mult_x_23_U216 ( .A(mult_x_23_n254), .B(mult_x_23_n248), .C(
mult_x_23_n250), .D(mult_x_23_n731), .ICI(mult_x_23_n757), .S(
mult_x_23_n245), .ICO(mult_x_23_n243), .CO(mult_x_23_n244) );
CMPR42X1TS mult_x_23_U214 ( .A(mult_x_23_n249), .B(mult_x_23_n653), .C(
mult_x_23_n246), .D(mult_x_23_n678), .ICI(mult_x_23_n247), .S(
mult_x_23_n240), .ICO(mult_x_23_n238), .CO(mult_x_23_n239) );
CMPR42X1TS mult_x_23_U213 ( .A(mult_x_23_n704), .B(mult_x_23_n240), .C(
mult_x_23_n243), .D(mult_x_23_n730), .ICI(mult_x_23_n756), .S(
mult_x_23_n237), .ICO(mult_x_23_n235), .CO(mult_x_23_n236) );
CMPR42X1TS mult_x_23_U212 ( .A(n5335), .B(mult_x_23_n241), .C(mult_x_23_n652), .D(mult_x_23_n238), .ICI(mult_x_23_n677), .S(mult_x_23_n234), .ICO(
mult_x_23_n222), .CO(mult_x_23_n233) );
CMPR42X1TS mult_x_23_U211 ( .A(mult_x_23_n234), .B(mult_x_23_n239), .C(
mult_x_23_n703), .D(mult_x_23_n235), .ICI(mult_x_23_n236), .S(
mult_x_23_n232), .ICO(mult_x_23_n230), .CO(mult_x_23_n231) );
CMPR42X1TS mult_x_23_U208 ( .A(mult_x_23_n233), .B(mult_x_23_n228), .C(
mult_x_23_n230), .D(mult_x_23_n702), .ICI(mult_x_23_n728), .S(
mult_x_23_n226), .ICO(mult_x_23_n224), .CO(mult_x_23_n225) );
CMPR42X1TS mult_x_23_U205 ( .A(mult_x_23_n675), .B(mult_x_23_n221), .C(
mult_x_23_n224), .D(mult_x_23_n701), .ICI(mult_x_23_n727), .S(
mult_x_23_n219), .ICO(mult_x_23_n217), .CO(mult_x_23_n218) );
CMPR42X1TS mult_x_23_U203 ( .A(mult_x_23_n216), .B(mult_x_23_n220), .C(
mult_x_23_n674), .D(mult_x_23_n217), .ICI(mult_x_23_n218), .S(
mult_x_23_n215), .ICO(mult_x_23_n213), .CO(mult_x_23_n214) );
CMPR42X1TS mult_x_23_U201 ( .A(mult_x_23_n648), .B(mult_x_23_n212), .C(
mult_x_23_n213), .D(mult_x_23_n673), .ICI(mult_x_23_n699), .S(
mult_x_23_n211), .ICO(mult_x_23_n209), .CO(mult_x_23_n210) );
CMPR42X1TS mult_x_23_U199 ( .A(mult_x_23_n212), .B(mult_x_23_n647), .C(
mult_x_23_n209), .D(mult_x_23_n672), .ICI(mult_x_23_n698), .S(
mult_x_23_n206), .ICO(mult_x_23_n204), .CO(mult_x_23_n205) );
CMPR42X1TS mult_x_23_U198 ( .A(n5334), .B(mult_x_23_n207), .C(mult_x_23_n646), .D(mult_x_23_n204), .ICI(mult_x_23_n205), .S(mult_x_23_n203), .ICO(
mult_x_23_n197), .CO(mult_x_23_n202) );
DFFSX4TS Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n941), .CK(clk), .SN(
n5460), .Q(mult_x_23_n871), .QN(Op_MX[29]) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_52_ ( .D(n580), .CK(clk),
.RN(n5473), .Q(Sgf_normalized_result[52]), .QN(n5397) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n663), .CK(clk), .RN(
n5467), .Q(DP_OP_169J45_123_4229_n2458), .QN(n959) );
DFFRX2TS Sel_B_Q_reg_1_ ( .D(n418), .CK(clk), .RN(n5459), .Q(
FSM_selector_B[1]), .QN(n5389) );
DFFRX2TS FS_Module_state_reg_reg_0_ ( .D(n713), .CK(clk), .RN(n5457), .Q(
FS_Module_state_reg[0]), .QN(n5360) );
DFFRX2TS FS_Module_state_reg_reg_2_ ( .D(n711), .CK(clk), .RN(n5478), .Q(
FS_Module_state_reg[2]), .QN(n5359) );
DFFRX2TS FS_Module_state_reg_reg_3_ ( .D(n714), .CK(clk), .RN(n5458), .Q(
FS_Module_state_reg[3]), .QN(n5340) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_1_ ( .D(n971), .RN(
DP_OP_169J45_123_4229_n147), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[1]) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_1_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N1), .CK(clk), .Q(Sgf_operation_Result[1]),
.QN(DP_OP_168J45_122_1342_n548) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_4_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N4), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[4]), .QN(DP_OP_168J45_122_1342_n597) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_10_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N10), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[10]), .QN(DP_OP_168J45_122_1342_n591) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_14_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N14), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[14]), .QN(DP_OP_168J45_122_1342_n587) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_19_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N19), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[19]) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_26_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N26), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[26]) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_27_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N27), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[27]), .QN(DP_OP_168J45_122_1342_n574) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_32_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N32), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[32]), .QN(DP_OP_168J45_122_1342_n569) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_42_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N42), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[42]), .QN(DP_OP_168J45_122_1342_n507) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_45_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N45), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[45]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n610), .CK(clk), .RN(
n5461), .Q(Op_MY[28]), .QN(n764) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_50_ ( .D(n632), .CK(clk), .RN(
n5474), .Q(Op_MY[50]), .QN(n789) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n608), .CK(clk), .RN(
n5469), .Q(Op_MY[26]), .QN(DP_OP_169J45_123_4229_n86) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n607), .CK(clk), .RN(
n5477), .Q(Op_MY[25]), .QN(n5358) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_50_ ( .D(n696), .CK(clk), .RN(
n5471), .Q(Op_MX[50]), .QN(n975) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_41_ ( .D(n687), .CK(clk), .RN(
n5476), .Q(Op_MX[41]), .QN(n978) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_35_ ( .D(n681), .CK(clk), .RN(
n5465), .Q(Op_MX[35]), .QN(n976) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_33_ ( .D(n615), .CK(clk), .RN(
n5470), .Q(Op_MY[33]), .QN(n955) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_35_ ( .D(n617), .CK(clk), .RN(
n5471), .Q(Op_MY[35]), .QN(n939) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_39_ ( .D(n621), .CK(clk), .RN(
n744), .Q(Op_MY[39]), .QN(n957) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_47_ ( .D(n629), .CK(clk), .RN(
n5463), .Q(Op_MY[47]), .QN(n915) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_43_ ( .D(n625), .CK(clk), .RN(
n744), .Q(Op_MY[43]), .QN(n943) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_47_ ( .D(n693), .CK(clk), .RN(
n5475), .Q(Op_MX[47]), .QN(n963) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_44_ ( .D(n690), .CK(clk), .RN(
n5464), .Q(Op_MX[44]), .QN(n968) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_32_ ( .D(n678), .CK(clk), .RN(
n5460), .Q(Op_MX[32]), .QN(n970) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n592), .CK(clk), .RN(
n5459), .Q(Op_MY[10]), .QN(n5347) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n673), .CK(clk), .RN(
n5465), .Q(Op_MX[27]), .QN(n913) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n586), .CK(clk), .RN(
n5459), .Q(Op_MY[4]), .QN(n5343) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n650), .CK(clk), .RN(
n3684), .Q(Op_MX[4]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n658), .CK(clk), .RN(
n5470), .Q(Op_MX[12]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n664), .CK(clk), .RN(
n5468), .Q(Op_MX[18]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n671), .CK(clk), .RN(
n5467), .Q(Op_MX[25]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n652), .CK(clk), .RN(
n5465), .Q(Op_MX[6]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n661), .CK(clk), .RN(
n5474), .Q(Op_MX[15]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n647), .CK(clk), .RN(
n5463), .Q(Op_MX[1]) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n355), .CK(clk),
.RN(n5477), .Q(Sgf_normalized_result[2]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_40_ ( .D(n393), .CK(clk),
.RN(n5460), .Q(Sgf_normalized_result[40]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_46_ ( .D(n399), .CK(clk),
.RN(n5471), .Q(Sgf_normalized_result[46]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n359), .CK(clk),
.RN(n5466), .Q(Sgf_normalized_result[6]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n361), .CK(clk),
.RN(n3684), .Q(Sgf_normalized_result[8]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n363), .CK(clk),
.RN(n5465), .Q(Sgf_normalized_result[10]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n365), .CK(clk),
.RN(n5470), .Q(Sgf_normalized_result[12]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n367), .CK(clk),
.RN(n5476), .Q(Sgf_normalized_result[14]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n369), .CK(clk),
.RN(n5463), .Q(Sgf_normalized_result[16]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n371), .CK(clk),
.RN(n5468), .Q(Sgf_normalized_result[18]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n373), .CK(clk),
.RN(n5472), .Q(Sgf_normalized_result[20]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n375), .CK(clk),
.RN(n5474), .Q(Sgf_normalized_result[22]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_24_ ( .D(n377), .CK(clk),
.RN(n5467), .Q(Sgf_normalized_result[24]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_48_ ( .D(n401), .CK(clk),
.RN(n5461), .Q(Sgf_normalized_result[48]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n585), .CK(clk), .RN(
n5459), .Q(Op_MY[3]), .QN(n5344) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n596), .CK(clk), .RN(
n5474), .Q(Op_MY[14]), .QN(n5349) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n605), .CK(clk), .RN(
n5461), .Q(Op_MY[23]), .QN(n5354) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_105_ ( .D(n420), .CK(clk), .RN(
n5478), .Q(P_Sgf[105]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_56_ ( .D(n702), .CK(clk), .RN(
n5465), .Q(Op_MX[56]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_60_ ( .D(n706), .CK(clk), .RN(
n5460), .Q(Op_MX[60]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n578), .CK(clk), .RN(n5466),
.Q(Add_result[1]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_62_ ( .D(n644), .CK(clk), .RN(
n3684), .Q(Op_MY[62]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n575), .CK(clk), .RN(n3683),
.Q(Add_result[4]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_46_ ( .D(n533), .CK(clk), .RN(n5463),
.Q(Add_result[46]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_48_ ( .D(n531), .CK(clk), .RN(n5468),
.Q(Add_result[48]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_60_ ( .D(n642), .CK(clk), .RN(
n5472), .Q(Op_MY[60]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n574), .CK(clk), .RN(n5470),
.Q(Add_result[5]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_53_ ( .D(n635), .CK(clk), .RN(
n5459), .Q(Op_MY[53]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n573), .CK(clk), .RN(n5465),
.Q(Add_result[6]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_53_ ( .D(n699), .CK(clk), .RN(
n5471), .Q(Op_MX[53]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_10_ ( .D(n407), .CK(clk), .RN(n5471),
.Q(exp_oper_result[10]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_9_ ( .D(n408), .CK(clk), .RN(n5461),
.Q(exp_oper_result[9]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_7_ ( .D(n410), .CK(clk), .RN(n5469),
.Q(exp_oper_result[7]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_6_ ( .D(n411), .CK(clk), .RN(n5477),
.Q(exp_oper_result[6]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_5_ ( .D(n412), .CK(clk), .RN(n5470),
.Q(exp_oper_result[5]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_3_ ( .D(n414), .CK(clk), .RN(n5460),
.Q(exp_oper_result[3]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_2_ ( .D(n415), .CK(clk), .RN(n5471),
.Q(exp_oper_result[2]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_0_ ( .D(n417), .CK(clk), .RN(n5459),
.Q(exp_oper_result[0]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_11_ ( .D(n406), .CK(clk), .RN(n5469),
.Q(exp_oper_result[11]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_49_ ( .D(n695), .CK(clk), .RN(
n3684), .Q(Op_MX[49]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n653), .CK(clk), .RN(
n3683), .Q(Op_MX[7]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_38_ ( .D(n684), .CK(clk), .RN(
n5462), .Q(Op_MX[38]), .QN(n977) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n665), .CK(clk), .RN(
n5472), .Q(Op_MX[19]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n662), .CK(clk), .RN(
n5468), .Q(Op_MX[16]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n659), .CK(clk), .RN(
n5476), .Q(Op_MX[13]), .QN(n791) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n668), .CK(clk), .RN(
n744), .Q(Op_MX[22]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_34_ ( .D(n680), .CK(clk), .RN(
n5460), .Q(Op_MX[34]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n598), .CK(clk), .RN(
n5463), .Q(Op_MY[16]), .QN(n5348) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_37_ ( .D(n619), .CK(clk), .RN(
n5467), .Q(Op_MY[37]), .QN(n958) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_41_ ( .D(n623), .CK(clk), .RN(
n5474), .Q(Op_MY[41]), .QN(n938) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_63_ ( .D(n645), .CK(clk), .RN(
n5472), .Q(Op_MX[63]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n609), .CK(clk), .RN(
n5460), .QN(n911) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n611), .CK(clk), .RN(
n5461), .Q(Op_MY[29]), .QN(n952) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_45_ ( .D(n627), .CK(clk), .RN(
n5463), .Q(Op_MY[45]), .QN(n942) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_49_ ( .D(n631), .CK(clk), .RN(
n5460), .Q(Op_MY[49]), .QN(n951) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n613), .CK(clk), .RN(
n5469), .Q(Op_MY[31]), .QN(n954) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_46_ ( .D(n628), .CK(clk), .RN(
n5472), .Q(Op_MY[46]), .QN(n916) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_38_ ( .D(n620), .CK(clk), .RN(
n744), .Q(Op_MY[38]), .QN(n948) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_44_ ( .D(n626), .CK(clk), .RN(
n744), .Q(Op_MY[44]), .QN(n937) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_32_ ( .D(n614), .CK(clk), .RN(
n5470), .Q(Op_MY[32]), .QN(n946) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n676), .CK(clk), .RN(
n5471), .Q(Op_MX[30]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n674), .CK(clk), .RN(
n5461), .Q(Op_MX[28]), .QN(n972) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n670), .CK(clk), .RN(
n744), .Q(Op_MX[24]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n655), .CK(clk), .RN(
n5475), .Q(Op_MX[9]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_37_ ( .D(n683), .CK(clk), .RN(
n5469), .Q(Op_MX[37]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n677), .CK(clk), .RN(
n5477), .Q(Op_MX[31]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n649), .CK(clk), .RN(
n5464), .Q(Op_MX[3]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_39_ ( .D(n685), .CK(clk), .RN(
n5470), .Q(Op_MX[39]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n667), .CK(clk), .RN(
n5473), .Q(Op_MX[21]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_51_ ( .D(n633), .CK(clk), .RN(
n5468), .Q(Op_MY[51]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n587), .CK(clk), .RN(
n5459), .Q(Op_MY[5]), .QN(n5345) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_51_ ( .D(n697), .CK(clk), .RN(
n5471), .Q(Op_MX[51]), .QN(n908) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n656), .CK(clk), .RN(
n5462), .Q(Op_MX[10]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_42_ ( .D(n688), .CK(clk), .RN(
n5465), .Q(Op_MX[42]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_45_ ( .D(n691), .CK(clk), .RN(
n3683), .Q(Op_MX[45]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_40_ ( .D(n686), .CK(clk), .RN(
n5470), .Q(Op_MX[40]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_48_ ( .D(n694), .CK(clk), .RN(
n5465), .Q(Op_MX[48]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_33_ ( .D(n679), .CK(clk), .RN(
n3683), .Q(Op_MX[33]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_36_ ( .D(n682), .CK(clk), .RN(
n5460), .Q(Op_MX[36]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n603), .CK(clk), .RN(
n5469), .Q(Op_MY[21]), .QN(n5379) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n600), .CK(clk), .RN(
n5466), .Q(Op_MY[18]), .QN(n5377) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n597), .CK(clk), .RN(
n5471), .Q(Op_MY[15]), .QN(n5374) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n594), .CK(clk), .RN(
n5460), .Q(Op_MY[12]), .QN(n5372) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n591), .CK(clk), .RN(
n5467), .Q(Op_MY[9]), .QN(n5371) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n588), .CK(clk), .RN(
n5459), .Q(Op_MY[6]), .QN(n5369) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n602), .CK(clk), .RN(
n5477), .Q(Op_MY[20]), .QN(n5353) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n590), .CK(clk), .RN(
n5469), .Q(Op_MY[8]), .QN(n5346) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_44_ ( .D(n397), .CK(clk),
.RN(n5469), .Q(Sgf_normalized_result[44]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_42_ ( .D(n395), .CK(clk),
.RN(n5477), .Q(Sgf_normalized_result[42]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_38_ ( .D(n391), .CK(clk),
.RN(n5475), .Q(Sgf_normalized_result[38]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_36_ ( .D(n389), .CK(clk),
.RN(n5464), .Q(Sgf_normalized_result[36]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_34_ ( .D(n387), .CK(clk),
.RN(n5462), .Q(Sgf_normalized_result[34]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_32_ ( .D(n385), .CK(clk),
.RN(n5466), .Q(Sgf_normalized_result[32]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_30_ ( .D(n383), .CK(clk),
.RN(n3684), .Q(Sgf_normalized_result[30]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n357), .CK(clk),
.RN(n5461), .Q(Sgf_normalized_result[4]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_50_ ( .D(n403), .CK(clk),
.RN(n3683), .Q(Sgf_normalized_result[50]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_28_ ( .D(n381), .CK(clk),
.RN(n5470), .Q(Sgf_normalized_result[28]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_26_ ( .D(n379), .CK(clk),
.RN(n5468), .Q(Sgf_normalized_result[26]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_62_ ( .D(n708), .CK(clk), .RN(
n5461), .Q(Op_MX[62]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_58_ ( .D(n704), .CK(clk), .RN(
n5475), .Q(Op_MX[58]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_52_ ( .D(n698), .CK(clk), .RN(
n5469), .Q(Op_MX[52]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_59_ ( .D(n705), .CK(clk), .RN(
n5461), .Q(Op_MX[59]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_55_ ( .D(n701), .CK(clk), .RN(
n5470), .Q(Op_MX[55]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_61_ ( .D(n707), .CK(clk), .RN(
n5477), .Q(Op_MX[61]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_57_ ( .D(n703), .CK(clk), .RN(
n5460), .Q(Op_MX[57]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_54_ ( .D(n700), .CK(clk), .RN(
n5471), .Q(Op_MX[54]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n577), .CK(clk), .RN(n5476),
.Q(Add_result[2]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_52_ ( .D(n634), .CK(clk), .RN(
n744), .Q(Op_MY[52]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_49_ ( .D(n530), .CK(clk), .RN(n5467),
.Q(Add_result[49]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_47_ ( .D(n532), .CK(clk), .RN(n5474),
.Q(Add_result[47]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_45_ ( .D(n534), .CK(clk), .RN(n744),
.Q(Add_result[45]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_43_ ( .D(n536), .CK(clk), .RN(n744),
.Q(Add_result[43]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_41_ ( .D(n538), .CK(clk), .RN(n5464),
.Q(Add_result[41]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_39_ ( .D(n540), .CK(clk), .RN(n5462),
.Q(Add_result[39]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_37_ ( .D(n542), .CK(clk), .RN(n3683),
.Q(Add_result[37]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_35_ ( .D(n544), .CK(clk), .RN(n5466),
.Q(Add_result[35]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_33_ ( .D(n546), .CK(clk), .RN(n3684),
.Q(Add_result[33]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_31_ ( .D(n548), .CK(clk), .RN(n744),
.Q(Add_result[31]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_29_ ( .D(n550), .CK(clk), .RN(n5472),
.Q(Add_result[29]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_27_ ( .D(n552), .CK(clk), .RN(n5459),
.Q(Add_result[27]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_25_ ( .D(n554), .CK(clk), .RN(n5463),
.Q(Add_result[25]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n556), .CK(clk), .RN(n5467),
.Q(Add_result[23]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n558), .CK(clk), .RN(n5474),
.Q(Add_result[21]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n560), .CK(clk), .RN(n5468),
.Q(Add_result[19]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n562), .CK(clk), .RN(n5460),
.Q(Add_result[17]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n564), .CK(clk), .RN(n5472),
.Q(Add_result[15]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n566), .CK(clk), .RN(n5477),
.Q(Add_result[13]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n568), .CK(clk), .RN(n5461),
.Q(Add_result[11]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n570), .CK(clk), .RN(n744),
.Q(Add_result[9]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_51_ ( .D(n528), .CK(clk), .RN(n3683),
.Q(Add_result[51]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_50_ ( .D(n529), .CK(clk), .RN(n5463),
.Q(Add_result[50]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_44_ ( .D(n535), .CK(clk), .RN(n5472),
.Q(Add_result[44]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_42_ ( .D(n537), .CK(clk), .RN(n5465),
.Q(Add_result[42]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_40_ ( .D(n539), .CK(clk), .RN(n5470),
.Q(Add_result[40]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_38_ ( .D(n541), .CK(clk), .RN(n5476),
.Q(Add_result[38]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_36_ ( .D(n543), .CK(clk), .RN(n5475),
.Q(Add_result[36]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_34_ ( .D(n545), .CK(clk), .RN(n5464),
.Q(Add_result[34]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_32_ ( .D(n547), .CK(clk), .RN(n5462),
.Q(Add_result[32]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_30_ ( .D(n549), .CK(clk), .RN(n5468),
.Q(Add_result[30]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_28_ ( .D(n551), .CK(clk), .RN(n5472),
.Q(Add_result[28]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_26_ ( .D(n553), .CK(clk), .RN(n5467),
.Q(Add_result[26]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_24_ ( .D(n555), .CK(clk), .RN(n5474),
.Q(Add_result[24]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n557), .CK(clk), .RN(n744),
.Q(Add_result[22]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n559), .CK(clk), .RN(n744),
.Q(Add_result[20]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n561), .CK(clk), .RN(n5469),
.Q(Add_result[18]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n563), .CK(clk), .RN(n5471),
.Q(Add_result[16]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n565), .CK(clk), .RN(n5467),
.Q(Add_result[14]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n567), .CK(clk), .RN(n5474),
.Q(Add_result[12]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n569), .CK(clk), .RN(n5468),
.Q(Add_result[10]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n571), .CK(clk), .RN(n5461),
.Q(Add_result[8]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_56_ ( .D(n638), .CK(clk), .RN(
n5477), .Q(Op_MY[56]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n572), .CK(clk), .RN(n5475),
.Q(Add_result[7]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_58_ ( .D(n640), .CK(clk), .RN(
n744), .Q(Op_MY[58]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_59_ ( .D(n641), .CK(clk), .RN(
n5461), .Q(Op_MY[59]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_55_ ( .D(n637), .CK(clk), .RN(
n5469), .Q(Op_MY[55]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n576), .CK(clk), .RN(n5464),
.Q(Add_result[3]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_61_ ( .D(n643), .CK(clk), .RN(
n5462), .Q(Op_MY[61]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_57_ ( .D(n639), .CK(clk), .RN(
n5471), .Q(Op_MY[57]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_54_ ( .D(n636), .CK(clk), .RN(
n5467), .Q(Op_MY[54]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n354), .CK(clk),
.RN(n5477), .Q(Sgf_normalized_result[1]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n353), .CK(clk),
.RN(n5465), .Q(Sgf_normalized_result[0]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_1_ ( .D(n416), .CK(clk), .RN(n5459),
.Q(exp_oper_result[1]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_4_ ( .D(n413), .CK(clk), .RN(n5461),
.Q(exp_oper_result[4]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_8_ ( .D(n409), .CK(clk), .RN(n5477),
.Q(exp_oper_result[8]) );
DFFRX1TS Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n526), .CK(clk), .RN(
n5466), .Q(FSM_add_overflow_flag) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_34_ ( .D(n616), .CK(clk), .RN(
n5477), .Q(Op_MY[34]), .QN(n917) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n606), .CK(clk), .RN(
n5471), .Q(Op_MY[24]), .QN(n949) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n646), .CK(clk), .RN(
n5474), .Q(Op_MX[0]), .QN(n5341) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_0_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N0), .CK(clk), .Q(Sgf_operation_Result[0]),
.QN(DP_OP_168J45_122_1342_n549) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_2_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N2), .CK(clk), .Q(Sgf_operation_Result[2]),
.QN(DP_OP_168J45_122_1342_n547) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_3_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N3), .CK(clk), .Q(Sgf_operation_Result[3]),
.QN(DP_OP_168J45_122_1342_n546) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_4_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N4), .CK(clk), .Q(Sgf_operation_Result[4]),
.QN(DP_OP_168J45_122_1342_n545) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_5_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N5), .CK(clk), .Q(Sgf_operation_Result[5]),
.QN(DP_OP_168J45_122_1342_n544) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_6_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N6), .CK(clk), .Q(Sgf_operation_Result[6]),
.QN(DP_OP_168J45_122_1342_n543) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_7_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N7), .CK(clk), .Q(Sgf_operation_Result[7]),
.QN(DP_OP_168J45_122_1342_n542) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_8_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N8), .CK(clk), .Q(Sgf_operation_Result[8]),
.QN(DP_OP_168J45_122_1342_n541) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_9_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N9), .CK(clk), .Q(Sgf_operation_Result[9]),
.QN(DP_OP_168J45_122_1342_n540) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_10_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N10), .CK(clk), .Q(Sgf_operation_Result[10]),
.QN(DP_OP_168J45_122_1342_n539) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_1_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N1), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[1]), .QN(DP_OP_168J45_122_1342_n600) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_11_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N11), .CK(clk), .Q(Sgf_operation_Result[11]),
.QN(DP_OP_168J45_122_1342_n538) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_2_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N2), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[2]), .QN(DP_OP_168J45_122_1342_n599) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_3_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N3), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[3]), .QN(DP_OP_168J45_122_1342_n598) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_12_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N12), .CK(clk), .Q(Sgf_operation_Result[12]),
.QN(DP_OP_168J45_122_1342_n537) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_13_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N13), .CK(clk), .Q(Sgf_operation_Result[13]),
.QN(DP_OP_168J45_122_1342_n536) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_5_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N5), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[5]), .QN(DP_OP_168J45_122_1342_n596) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_2_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N2), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[2]) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_6_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N6), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[6]), .QN(DP_OP_168J45_122_1342_n595) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_14_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N14), .CK(clk), .Q(Sgf_operation_Result[14]),
.QN(DP_OP_168J45_122_1342_n535) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_7_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N7), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[7]), .QN(DP_OP_168J45_122_1342_n594) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_15_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N15), .CK(clk), .Q(Sgf_operation_Result[15]),
.QN(DP_OP_168J45_122_1342_n534) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_8_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N8), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[8]), .QN(DP_OP_168J45_122_1342_n593) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_3_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N3), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[3]) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_16_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N16), .CK(clk), .Q(Sgf_operation_Result[16]),
.QN(DP_OP_168J45_122_1342_n533) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_4_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N4), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[4]) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_9_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N9), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[9]), .QN(DP_OP_168J45_122_1342_n592) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_5_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N5), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[5]) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_17_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N17), .CK(clk), .Q(Sgf_operation_Result[17]),
.QN(DP_OP_168J45_122_1342_n532) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_6_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N6), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[6]) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_7_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N7), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[7]) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_18_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N18), .CK(clk), .Q(Sgf_operation_Result[18]),
.QN(DP_OP_168J45_122_1342_n531) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_11_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N11), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[11]), .QN(DP_OP_168J45_122_1342_n590) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_8_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N8), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[8]) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_19_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N19), .CK(clk), .Q(Sgf_operation_Result[19]),
.QN(DP_OP_168J45_122_1342_n530) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_9_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N9), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[9]) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_12_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N12), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[12]), .QN(DP_OP_168J45_122_1342_n589) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_10_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N10), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[10]) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_20_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N20), .CK(clk), .Q(Sgf_operation_Result[20]),
.QN(DP_OP_168J45_122_1342_n529) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_13_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N13), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[13]), .QN(DP_OP_168J45_122_1342_n588) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_11_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N11), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[11]) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_12_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N12), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[12]) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_21_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N21), .CK(clk), .Q(Sgf_operation_Result[21]),
.QN(DP_OP_168J45_122_1342_n528) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_13_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N13), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[13]) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_22_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N22), .CK(clk), .Q(Sgf_operation_Result[22]),
.QN(DP_OP_168J45_122_1342_n527) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_14_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N14), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[14]) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_15_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N15), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[15]), .QN(DP_OP_168J45_122_1342_n586) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_15_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N15), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[15]) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_23_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N23), .CK(clk), .Q(Sgf_operation_Result[23]),
.QN(DP_OP_168J45_122_1342_n526) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_16_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N16), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[16]), .QN(DP_OP_168J45_122_1342_n585) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_16_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N16), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[16]) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_17_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N17), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[17]) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_24_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N24), .CK(clk), .Q(Sgf_operation_Result[24]),
.QN(DP_OP_168J45_122_1342_n525) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_17_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N17), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[17]), .QN(DP_OP_168J45_122_1342_n584) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_18_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N18), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[18]) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_25_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N25), .CK(clk), .Q(Sgf_operation_Result[25]),
.QN(DP_OP_168J45_122_1342_n524) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_18_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N18), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[18]), .QN(DP_OP_168J45_122_1342_n583) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_20_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N20), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[20]) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_26_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N26), .CK(clk), .Q(Sgf_operation_Result[26]),
.QN(DP_OP_168J45_122_1342_n523) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_19_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N19), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[19]), .QN(DP_OP_168J45_122_1342_n582) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_21_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N21), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[21]) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_22_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N22), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[22]) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_20_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N20), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[20]), .QN(DP_OP_168J45_122_1342_n581) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_27_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N27), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[27]), .QN(DP_OP_168J45_122_1342_n522) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_23_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N23), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[23]) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_28_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N28), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[28]), .QN(DP_OP_168J45_122_1342_n521) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_24_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N24), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[24]) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_21_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N21), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[21]), .QN(DP_OP_168J45_122_1342_n580) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_25_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N25), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[25]) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_29_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N29), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[29]), .QN(DP_OP_168J45_122_1342_n520) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_22_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N22), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[22]), .QN(DP_OP_168J45_122_1342_n579) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_23_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N23), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[23]), .QN(DP_OP_168J45_122_1342_n578) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_30_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N30), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[30]), .QN(DP_OP_168J45_122_1342_n519) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_27_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N27), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[27]) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_28_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N28), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[28]) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_24_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N24), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[24]), .QN(DP_OP_168J45_122_1342_n577) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_31_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N31), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[31]), .QN(DP_OP_168J45_122_1342_n518) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_29_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N29), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[29]) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_25_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N25), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[25]), .QN(DP_OP_168J45_122_1342_n576) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_30_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N30), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[30]) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_32_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N32), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[32]), .QN(DP_OP_168J45_122_1342_n517) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_26_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N26), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[26]), .QN(DP_OP_168J45_122_1342_n575) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_31_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N31), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[31]) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_32_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N32), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[32]) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_33_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N33), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[33]), .QN(DP_OP_168J45_122_1342_n516) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_33_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N33), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[33]) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_28_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N28), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[28]), .QN(DP_OP_168J45_122_1342_n573) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_34_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N34), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[34]), .QN(DP_OP_168J45_122_1342_n515) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_34_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N34), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[34]) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_29_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N29), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[29]), .QN(DP_OP_168J45_122_1342_n572) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_35_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N35), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[35]) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_35_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N35), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[35]), .QN(DP_OP_168J45_122_1342_n514) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_36_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N36), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[36]) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_30_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N30), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[30]), .QN(DP_OP_168J45_122_1342_n571) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_36_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N36), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[36]), .QN(DP_OP_168J45_122_1342_n513) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_37_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N37), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[37]) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_31_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N31), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[31]), .QN(DP_OP_168J45_122_1342_n570) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_38_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N38), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[38]) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_37_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N37), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[37]), .QN(DP_OP_168J45_122_1342_n512) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_39_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N39), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[39]) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_38_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N38), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[38]), .QN(DP_OP_168J45_122_1342_n511) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_40_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N40), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[40]) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_33_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N33), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[33]), .QN(DP_OP_168J45_122_1342_n568) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_39_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N39), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[39]), .QN(DP_OP_168J45_122_1342_n510) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_41_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N41), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[41]) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_34_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N34), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[34]), .QN(DP_OP_168J45_122_1342_n567) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_35_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N35), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[35]), .QN(DP_OP_168J45_122_1342_n566) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_40_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N40), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[40]), .QN(DP_OP_168J45_122_1342_n509) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_42_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N42), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[42]) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_36_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N36), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[36]), .QN(DP_OP_168J45_122_1342_n565) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_41_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N41), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[41]), .QN(DP_OP_168J45_122_1342_n508) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_43_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N43), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[43]) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_37_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N37), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[37]), .QN(DP_OP_168J45_122_1342_n564) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_44_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N44), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[44]) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_38_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N38), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[38]), .QN(DP_OP_168J45_122_1342_n563) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_43_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N43), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[43]), .QN(DP_OP_168J45_122_1342_n506) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n648), .CK(clk), .RN(
n5475), .Q(n731), .QN(n931) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n582), .CK(clk), .RN(
n5459), .Q(Op_MY[0]), .QN(n930) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n654), .CK(clk), .RN(
n5470), .QN(n929) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n584), .CK(clk), .RN(
n5459), .Q(Op_MY[2]), .QN(n5342) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_36_ ( .D(n618), .CK(clk), .RN(
n5460), .Q(Op_MY[36]), .QN(n950) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n660), .CK(clk), .RN(
n5472), .Q(n763) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_40_ ( .D(n622), .CK(clk), .RN(
n5468), .Q(Op_MY[40]), .QN(n940) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n589), .CK(clk), .RN(
n744), .Q(Op_MY[7]), .QN(n5350) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n593), .CK(clk), .RN(
n5469), .Q(Op_MY[11]), .QN(n5351) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n666), .CK(clk), .RN(
n744), .Q(n730), .QN(n5338) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n595), .CK(clk), .RN(
n5477), .Q(Op_MY[13]), .QN(n5352) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n669), .CK(clk), .RN(
n5468), .Q(n729) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n599), .CK(clk), .RN(
n744), .Q(Op_MY[17]), .QN(n5355) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n672), .CK(clk), .RN(
n5473), .Q(Op_MX[26]), .QN(n935) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n601), .CK(clk), .RN(
n5469), .Q(Op_MY[19]), .QN(n5356) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n604), .CK(clk), .RN(
n5461), .Q(Op_MY[22]), .QN(n5357) );
DFFRX4TS FS_Module_state_reg_reg_1_ ( .D(n712), .CK(clk), .RN(n5478), .Q(
n728) );
DFFRX4TS Sel_A_Q_reg_0_ ( .D(n710), .CK(clk), .RN(n5473), .Q(FSM_selector_A),
.QN(n5395) );
CMPR32X2TS U746 ( .A(n3241), .B(n3240), .C(n3239), .CO(n1214), .S(
Sgf_operation_ODD1_left_N50) );
CMPR32X2TS U747 ( .A(n4853), .B(n4852), .C(n4851), .CO(n4861), .S(
Sgf_operation_ODD1_right_N52) );
CMPR32X2TS U748 ( .A(n3428), .B(n3427), .C(n3426), .CO(n3239), .S(
Sgf_operation_ODD1_left_N49) );
CMPR32X2TS U749 ( .A(n1785), .B(n1784), .C(DP_OP_169J45_123_4229_n154), .CO(
n1789), .S(n1793) );
CMPR32X2TS U750 ( .A(n3431), .B(n3430), .C(n3429), .CO(n3426), .S(
Sgf_operation_ODD1_left_N48) );
CMPR32X2TS U751 ( .A(mult_x_24_n209), .B(n4856), .C(n4843), .CO(n4853), .S(
n4850) );
CMPR32X2TS U752 ( .A(mult_x_23_n203), .B(n1222), .C(n1221), .CO(n2663), .S(
Sgf_operation_ODD1_left_N46) );
CMPR32X2TS U753 ( .A(n1880), .B(n1881), .C(n1879), .CO(
DP_OP_169J45_123_4229_n165), .S(DP_OP_169J45_123_4229_n166) );
CMPR32X2TS U754 ( .A(n1903), .B(n1902), .C(n1901), .CO(
DP_OP_169J45_123_4229_n170), .S(DP_OP_169J45_123_4229_n171) );
CMPR32X2TS U755 ( .A(mult_x_23_n215), .B(n1238), .C(n1237), .CO(n2665), .S(
Sgf_operation_ODD1_left_N43) );
CMPR32X2TS U756 ( .A(mult_x_23_n232), .B(n1234), .C(n1233), .CO(n2667), .S(
Sgf_operation_ODD1_left_N40) );
CMPR32X2TS U757 ( .A(n1929), .B(n1928), .C(DP_OP_169J45_123_4229_n212), .CO(
DP_OP_169J45_123_4229_n202), .S(DP_OP_169J45_123_4229_n203) );
CMPR32X2TS U758 ( .A(n1926), .B(n1927), .C(n1925), .CO(
DP_OP_169J45_123_4229_n194), .S(DP_OP_169J45_123_4229_n195) );
CMPR32X2TS U759 ( .A(mult_x_23_n252), .B(n1240), .C(n1239), .CO(n2669), .S(
Sgf_operation_ODD1_left_N37) );
CMPR32X2TS U760 ( .A(n1956), .B(n1957), .C(n1955), .CO(
DP_OP_169J45_123_4229_n235), .S(DP_OP_169J45_123_4229_n236) );
CMPR32X2TS U761 ( .A(n1975), .B(n1974), .C(n1973), .CO(
DP_OP_169J45_123_4229_n246), .S(DP_OP_169J45_123_4229_n247) );
CMPR32X2TS U762 ( .A(mult_x_23_n278), .B(n1236), .C(n1235), .CO(n2671), .S(
Sgf_operation_ODD1_left_N34) );
CMPR32X2TS U763 ( .A(n2000), .B(n2001), .C(n1999), .CO(
DP_OP_169J45_123_4229_n288), .S(DP_OP_169J45_123_4229_n289) );
CMPR32X2TS U764 ( .A(n2011), .B(n2010), .C(n2009), .CO(
DP_OP_169J45_123_4229_n302), .S(DP_OP_169J45_123_4229_n303) );
CMPR32X2TS U765 ( .A(mult_x_23_n307), .B(n1245), .C(n1244), .CO(n2673), .S(
Sgf_operation_ODD1_left_N31) );
CMPR32X2TS U766 ( .A(mult_x_23_n340), .B(n1220), .C(n1219), .CO(n2675), .S(
Sgf_operation_ODD1_left_N28) );
CMPR32X2TS U767 ( .A(n2037), .B(n2038), .C(n2036), .CO(
DP_OP_169J45_123_4229_n353), .S(DP_OP_169J45_123_4229_n354) );
CMPR32X2TS U768 ( .A(n3741), .B(Sgf_operation_ODD1_Q_left[27]), .C(n3740),
.CO(n3743), .S(n3742) );
CMPR32X2TS U769 ( .A(n2041), .B(n2040), .C(n2039), .CO(
DP_OP_169J45_123_4229_n370), .S(DP_OP_169J45_123_4229_n371) );
CMPR32X2TS U770 ( .A(n1218), .B(mult_x_23_n373), .C(n1217), .CO(n2677), .S(
Sgf_operation_ODD1_left_N25) );
CMPR32X2TS U771 ( .A(n3735), .B(Sgf_operation_ODD1_Q_left[25]), .C(n3734),
.CO(n3737), .S(n3736) );
OAI21X1TS U772 ( .A0(n1417), .A1(n1413), .B0(n1414), .Y(n1412) );
CMPR32X2TS U773 ( .A(n2058), .B(n2057), .C(n2056), .CO(
DP_OP_169J45_123_4229_n430), .S(DP_OP_169J45_123_4229_n431) );
CMPR32X2TS U774 ( .A(n2068), .B(n2060), .C(n2059), .CO(
DP_OP_169J45_123_4229_n450), .S(DP_OP_169J45_123_4229_n451) );
OAI21X1TS U775 ( .A0(n1425), .A1(n1421), .B0(n1422), .Y(n1420) );
CMPR32X2TS U776 ( .A(n2068), .B(n2067), .C(n2066), .CO(
DP_OP_169J45_123_4229_n472), .S(DP_OP_169J45_123_4229_n473) );
AOI21X2TS U777 ( .A0(n1428), .A1(n921), .B0(n1392), .Y(n1425) );
CMPR32X2TS U778 ( .A(n2071), .B(n2070), .C(n2069), .CO(n2066), .S(
DP_OP_169J45_123_4229_n494) );
OAI21X1TS U779 ( .A0(n1433), .A1(n1429), .B0(n1430), .Y(n1428) );
CMPR32X2TS U780 ( .A(Op_MY[50]), .B(n2832), .C(n984), .CO(n982), .S(n985) );
CMPR32X2TS U781 ( .A(Op_MY[49]), .B(Op_MY[50]), .C(n989), .CO(n984), .S(n990) );
CMPR32X2TS U782 ( .A(Sgf_operation_ODD1_Q_middle[50]), .B(n1394), .C(n1393),
.CO(n1395), .S(n1391) );
CMPR32X2TS U783 ( .A(Sgf_operation_ODD1_Q_middle[51]), .B(n1398), .C(n1397),
.CO(n1399), .S(n1396) );
OAI21X2TS U784 ( .A0(n1441), .A1(n1437), .B0(n1438), .Y(n1436) );
CMPR32X2TS U785 ( .A(n845), .B(Op_MY[49]), .C(n1064), .CO(n989), .S(n1065)
);
CMPR32X2TS U786 ( .A(n2099), .B(n2098), .C(n2097), .CO(
DP_OP_169J45_123_4229_n548), .S(DP_OP_169J45_123_4229_n549) );
AOI21X2TS U787 ( .A0(n1444), .A1(n925), .B0(n1374), .Y(n1441) );
ADDFHX2TS U788 ( .A(n3714), .B(Sgf_operation_ODD1_Q_left[18]), .CI(n3713),
.CO(n3716), .S(n3715) );
CMPR32X2TS U789 ( .A(Op_MY[47]), .B(n845), .C(n1069), .CO(n1064), .S(n1070)
);
CMPR32X2TS U790 ( .A(Op_MY[22]), .B(Op_MY[23]), .C(n3502), .CO(n3497), .S(
n3503) );
CMPR32X2TS U791 ( .A(n2145), .B(n2144), .C(n2143), .CO(
DP_OP_169J45_123_4229_n567), .S(DP_OP_169J45_123_4229_n568) );
CMPR32X2TS U792 ( .A(Sgf_operation_ODD1_Q_middle[48]), .B(n1385), .C(n1384),
.CO(n1386), .S(n1382) );
CMPR32X2TS U793 ( .A(Sgf_operation_ODD1_Q_middle[49]), .B(n1389), .C(n1388),
.CO(n1390), .S(n1387) );
OAI21X2TS U794 ( .A0(n1449), .A1(n1445), .B0(n1446), .Y(n1444) );
CMPR32X2TS U795 ( .A(Op_MY[46]), .B(Op_MY[47]), .C(n1074), .CO(n1069), .S(
n1075) );
CMPR32X2TS U796 ( .A(Op_MY[21]), .B(Op_MY[22]), .C(n3508), .CO(n3502), .S(
n3509) );
CMPR32X2TS U797 ( .A(n1216), .B(mult_x_23_n474), .C(n1215), .CO(n2695), .S(
Sgf_operation_ODD1_left_N15) );
AOI21X2TS U798 ( .A0(n1452), .A1(n924), .B0(n1365), .Y(n1449) );
CMPR32X2TS U799 ( .A(n2157), .B(n2156), .C(n2155), .CO(
DP_OP_169J45_123_4229_n613), .S(DP_OP_169J45_123_4229_n614) );
CMPR32X2TS U800 ( .A(Op_MY[45]), .B(Op_MY[46]), .C(n1079), .CO(n1074), .S(
n1080) );
CMPR32X2TS U801 ( .A(Sgf_operation_ODD1_Q_middle[46]), .B(n1376), .C(n1375),
.CO(n1377), .S(n1373) );
CMPR32X2TS U802 ( .A(Sgf_operation_ODD1_Q_middle[47]), .B(n1380), .C(n1379),
.CO(n1381), .S(n1378) );
OAI21X2TS U803 ( .A0(n1457), .A1(n1453), .B0(n1454), .Y(n1452) );
CMPR32X2TS U804 ( .A(n3702), .B(Sgf_operation_ODD1_Q_left[14]), .C(n3701),
.CO(n3704), .S(n3703) );
CMPR32X2TS U805 ( .A(n2162), .B(n2161), .C(n2160), .CO(n2155), .S(
DP_OP_169J45_123_4229_n630) );
CMPR32X2TS U806 ( .A(Op_MY[44]), .B(Op_MY[45]), .C(n1084), .CO(n1079), .S(
n1085) );
CMPR32X2TS U807 ( .A(Op_MY[19]), .B(Op_MY[20]), .C(n3518), .CO(n3513), .S(
n3519) );
AOI21X2TS U808 ( .A0(n1460), .A1(n923), .B0(n1358), .Y(n1457) );
CMPR32X2TS U809 ( .A(Op_MY[43]), .B(Op_MY[44]), .C(n1089), .CO(n1084), .S(
n1090) );
CMPR32X2TS U810 ( .A(Op_MY[18]), .B(Op_MY[19]), .C(n3523), .CO(n3518), .S(
n3524) );
CMPR32X2TS U811 ( .A(mult_x_23_n496), .B(n1226), .C(n1225), .CO(n2699), .S(
Sgf_operation_ODD1_left_N12) );
CMPR32X2TS U812 ( .A(Sgf_operation_ODD1_Q_middle[44]), .B(n1367), .C(n1366),
.CO(n1368), .S(n1364) );
CMPR32X2TS U813 ( .A(Sgf_operation_ODD1_Q_middle[45]), .B(n1371), .C(n1370),
.CO(n1372), .S(n1369) );
OAI21X2TS U814 ( .A0(n1465), .A1(n1461), .B0(n1462), .Y(n1460) );
CMPR32X2TS U815 ( .A(n3696), .B(Sgf_operation_ODD1_Q_left[12]), .C(n3695),
.CO(n3698), .S(n3697) );
CMPR32X2TS U816 ( .A(n847), .B(Op_MY[43]), .C(n1094), .CO(n1089), .S(n1095)
);
CMPR32X2TS U817 ( .A(Op_MY[17]), .B(Op_MY[18]), .C(n3528), .CO(n3523), .S(
n3529) );
CMPR32X2TS U818 ( .A(n2185), .B(n2184), .C(n2183), .CO(
DP_OP_169J45_123_4229_n666), .S(DP_OP_169J45_123_4229_n667) );
CMPR32X2TS U819 ( .A(Op_MY[41]), .B(n847), .C(n1099), .CO(n1094), .S(n1100)
);
CMPR32X2TS U820 ( .A(Op_MY[16]), .B(Op_MY[17]), .C(n3533), .CO(n3528), .S(
n3534) );
CMPR32X2TS U821 ( .A(mult_x_23_n508), .B(n1224), .C(n1223), .CO(n3378), .S(
Sgf_operation_ODD1_left_N10) );
CMPR32X2TS U822 ( .A(Sgf_operation_ODD1_Q_middle[42]), .B(n1359), .C(
DP_OP_168J45_122_1342_n507), .CO(n1360), .S(n1357) );
CMPR32X2TS U823 ( .A(Sgf_operation_ODD1_Q_middle[43]), .B(n1362), .C(
DP_OP_168J45_122_1342_n506), .CO(n1363), .S(n1361) );
OAI21X2TS U824 ( .A0(n1473), .A1(n1469), .B0(n1470), .Y(n1468) );
CMPR32X2TS U825 ( .A(n5085), .B(Sgf_operation_ODD1_Q_left[10]), .C(n5084),
.CO(n5081), .S(n5086) );
CMPR32X2TS U826 ( .A(n2190), .B(n2189), .C(n2188), .CO(n2183), .S(
DP_OP_169J45_123_4229_n680) );
CMPR32X2TS U827 ( .A(Op_MY[40]), .B(Op_MY[41]), .C(n1104), .CO(n1099), .S(
n1105) );
CMPR32X2TS U828 ( .A(Op_MY[39]), .B(Op_MY[40]), .C(n1109), .CO(n1104), .S(
n1110) );
CMPR32X2TS U829 ( .A(n1232), .B(n1231), .C(n1230), .CO(n3376), .S(
Sgf_operation_ODD1_left_N8) );
CMPR32X2TS U830 ( .A(Sgf_operation_ODD1_Q_middle[40]), .B(n1352), .C(
DP_OP_168J45_122_1342_n509), .CO(n1353), .S(n1350) );
CMPR32X2TS U831 ( .A(Sgf_operation_ODD1_Q_middle[41]), .B(n1355), .C(
DP_OP_168J45_122_1342_n508), .CO(n1356), .S(n1354) );
INVX4TS U832 ( .A(n4072), .Y(n3978) );
CMPR32X2TS U833 ( .A(n2201), .B(n2200), .C(n2199), .CO(
DP_OP_169J45_123_4229_n707), .S(DP_OP_169J45_123_4229_n708) );
CMPR32X2TS U834 ( .A(Op_MY[38]), .B(Op_MY[39]), .C(n1114), .CO(n1109), .S(
n1115) );
CMPR32X2TS U835 ( .A(Op_MY[13]), .B(Op_MY[14]), .C(n3548), .CO(n3543), .S(
n3549) );
AOI21X1TS U836 ( .A0(n1484), .A1(n906), .B0(n1340), .Y(n1481) );
CMPR32X2TS U837 ( .A(Sgf_operation_ODD1_Q_middle[38]), .B(
DP_OP_168J45_122_1342_n563), .C(DP_OP_168J45_122_1342_n511), .CO(n1346), .S(n1344) );
CMPR32X2TS U838 ( .A(Op_MY[37]), .B(Op_MY[38]), .C(n1119), .CO(n1114), .S(
n1120) );
CMPR32X2TS U839 ( .A(Op_MY[12]), .B(Op_MY[13]), .C(n3553), .CO(n3548), .S(
n3554) );
CMPR32X2TS U840 ( .A(n1229), .B(n1228), .C(n1227), .CO(n3414), .S(
Sgf_operation_ODD1_left_N6) );
CMPR32X2TS U841 ( .A(Sgf_operation_ODD1_Q_middle[39]), .B(n1348), .C(
DP_OP_168J45_122_1342_n510), .CO(n1349), .S(n1347) );
OAI21X1TS U842 ( .A0(n1489), .A1(n1485), .B0(n1486), .Y(n1484) );
CMPR32X2TS U843 ( .A(n5097), .B(Sgf_operation_ODD1_Q_left[6]), .C(n5096),
.CO(n5093), .S(n5098) );
CMPR32X2TS U844 ( .A(n2206), .B(n2205), .C(n2204), .CO(n2199), .S(
DP_OP_169J45_123_4229_n718) );
CMPR32X2TS U845 ( .A(Op_MY[11]), .B(Op_MY[12]), .C(n3558), .CO(n3553), .S(
n3559) );
INVX4TS U846 ( .A(n4750), .Y(n4013) );
AOI21X1TS U847 ( .A0(n1492), .A1(n905), .B0(n1335), .Y(n1489) );
CMPR32X2TS U848 ( .A(Sgf_operation_ODD1_Q_middle[36]), .B(
DP_OP_168J45_122_1342_n565), .C(DP_OP_168J45_122_1342_n513), .CO(n1341), .S(n1339) );
CMPR32X2TS U849 ( .A(Sgf_operation_ODD1_Q_middle[37]), .B(
DP_OP_168J45_122_1342_n564), .C(DP_OP_168J45_122_1342_n512), .CO(n1343), .S(n1342) );
CMPR32X2TS U850 ( .A(Op_MY[10]), .B(Op_MY[11]), .C(n3563), .CO(n3558), .S(
n3564) );
CMPR32X2TS U851 ( .A(n1243), .B(n1242), .C(n1241), .CO(n3373), .S(
Sgf_operation_ODD1_left_N4) );
CMPR32X2TS U852 ( .A(n2217), .B(n2216), .C(n2215), .CO(
DP_OP_169J45_123_4229_n736), .S(DP_OP_169J45_123_4229_n737) );
CMPR32X2TS U853 ( .A(n5103), .B(Sgf_operation_ODD1_Q_left[4]), .C(n5102),
.CO(n5099), .S(n5104) );
CMPR32X2TS U854 ( .A(Op_MY[9]), .B(Op_MY[10]), .C(n3568), .CO(n3563), .S(
n3569) );
CMPR32X2TS U855 ( .A(Op_MY[34]), .B(Op_MY[35]), .C(n1168), .CO(n1129), .S(
n1169) );
INVX4TS U856 ( .A(n4033), .Y(n4041) );
AOI21X1TS U857 ( .A0(n1500), .A1(n904), .B0(n1330), .Y(n1497) );
CMPR32X2TS U858 ( .A(n2222), .B(n2221), .C(n2220), .CO(n2215), .S(
DP_OP_169J45_123_4229_n744) );
CMPR32X2TS U859 ( .A(Sgf_operation_ODD1_Q_middle[34]), .B(
DP_OP_168J45_122_1342_n567), .C(DP_OP_168J45_122_1342_n515), .CO(n1336), .S(n1334) );
CMPR32X2TS U860 ( .A(Sgf_operation_ODD1_Q_middle[35]), .B(
DP_OP_168J45_122_1342_n566), .C(DP_OP_168J45_122_1342_n514), .CO(n1338), .S(n1337) );
CMPR32X2TS U861 ( .A(Op_MY[33]), .B(Op_MY[34]), .C(n1176), .CO(n1168), .S(
n1177) );
OAI21X1TS U862 ( .A0(n1505), .A1(n1501), .B0(n1502), .Y(n1500) );
CMPR32X2TS U863 ( .A(Op_MY[32]), .B(Op_MY[33]), .C(n1184), .CO(n1176), .S(
n1185) );
CMPR32X2TS U864 ( .A(Op_MY[7]), .B(Op_MY[8]), .C(n3620), .CO(n3573), .S(
n3621) );
AOI21X1TS U865 ( .A0(n1508), .A1(n903), .B0(n1325), .Y(n1505) );
CMPR32X2TS U866 ( .A(Sgf_operation_ODD1_Q_middle[32]), .B(
DP_OP_168J45_122_1342_n569), .C(DP_OP_168J45_122_1342_n517), .CO(n1331), .S(n1329) );
CMPR32X2TS U867 ( .A(Sgf_operation_ODD1_Q_middle[33]), .B(
DP_OP_168J45_122_1342_n568), .C(DP_OP_168J45_122_1342_n516), .CO(n1333), .S(n1332) );
CMPR32X2TS U868 ( .A(Op_MY[6]), .B(Op_MY[7]), .C(n3628), .CO(n3620), .S(
n3629) );
CMPR32X2TS U869 ( .A(Op_MY[31]), .B(Op_MY[32]), .C(n1143), .CO(n1184), .S(
n1144) );
CMPR32X2TS U870 ( .A(n1772), .B(n1771), .C(n1770), .CO(n1842), .S(n1844) );
INVX4TS U871 ( .A(n3587), .Y(n4051) );
OAI21X1TS U872 ( .A0(n1513), .A1(n1509), .B0(n1510), .Y(n1508) );
CMPR32X2TS U873 ( .A(Op_MY[5]), .B(Op_MY[6]), .C(n3636), .CO(n3628), .S(
n3637) );
CMPR32X2TS U874 ( .A(n846), .B(Op_MY[31]), .C(n1150), .CO(n1143), .S(n1151)
);
CMPR32X2TS U875 ( .A(n1778), .B(n1777), .C(n1776), .CO(n1845), .S(n1847) );
AOI21X1TS U876 ( .A0(n1516), .A1(n902), .B0(n1320), .Y(n1513) );
CMPR32X2TS U877 ( .A(Sgf_operation_ODD1_Q_middle[30]), .B(
DP_OP_168J45_122_1342_n571), .C(DP_OP_168J45_122_1342_n519), .CO(n1326), .S(n1324) );
CMPR32X2TS U878 ( .A(Sgf_operation_ODD1_Q_middle[31]), .B(
DP_OP_168J45_122_1342_n570), .C(DP_OP_168J45_122_1342_n518), .CO(n1328), .S(n1327) );
CMPR32X2TS U879 ( .A(Op_MY[4]), .B(Op_MY[5]), .C(n3593), .CO(n3636), .S(
n3594) );
OAI21X1TS U880 ( .A0(n1521), .A1(n1517), .B0(n1518), .Y(n1516) );
ADDFHX2TS U881 ( .A(n5116), .B(Sgf_operation_ODD1_Q_right[53]), .CI(n5115),
.CO(n5112), .S(n5117) );
CMPR32X2TS U882 ( .A(Op_MY[3]), .B(Op_MY[4]), .C(n3601), .CO(n3593), .S(
n3602) );
CMPR32X2TS U883 ( .A(Op_MY[28]), .B(Op_MY[29]), .C(n1134), .CO(n1155), .S(
n1135) );
AOI21X1TS U884 ( .A0(n1524), .A1(n901), .B0(n1315), .Y(n1521) );
CMPR32X2TS U885 ( .A(Sgf_operation_ODD1_Q_middle[28]), .B(
DP_OP_168J45_122_1342_n573), .C(DP_OP_168J45_122_1342_n521), .CO(n1321), .S(n1319) );
CMPR32X2TS U886 ( .A(Sgf_operation_ODD1_Q_middle[29]), .B(
DP_OP_168J45_122_1342_n572), .C(DP_OP_168J45_122_1342_n520), .CO(n1323), .S(n1322) );
CMPR32X2TS U887 ( .A(Op_MY[2]), .B(Op_MY[3]), .C(n3606), .CO(n3601), .S(
n3607) );
CMPR32X2TS U888 ( .A(n5119), .B(Sgf_operation_ODD1_Q_right[51]), .C(n5118),
.CO(n3687), .S(n5120) );
CMPR32X2TS U889 ( .A(n4892), .B(Op_MY[2]), .C(n3579), .CO(n3606), .S(n3580)
);
CMPR32X2TS U890 ( .A(n5122), .B(Sgf_operation_ODD1_Q_right[50]), .C(n5121),
.CO(n5118), .S(n5123) );
CMPR32X2TS U891 ( .A(Sgf_operation_ODD1_Q_middle[26]), .B(
DP_OP_168J45_122_1342_n523), .C(DP_OP_168J45_122_1342_n575), .CO(n1316), .S(n1314) );
CMPR32X2TS U892 ( .A(Sgf_operation_ODD1_Q_middle[27]), .B(
DP_OP_168J45_122_1342_n522), .C(DP_OP_168J45_122_1342_n574), .CO(n1318), .S(n1317) );
CMPR32X2TS U893 ( .A(n5129), .B(Sgf_operation_ODD1_Q_right[48]), .C(n5128),
.CO(n5124), .S(n5130) );
CMPR32X2TS U894 ( .A(Sgf_operation_ODD1_Q_middle[24]), .B(
DP_OP_168J45_122_1342_n525), .C(DP_OP_168J45_122_1342_n577), .CO(n1311), .S(n1309) );
CMPR32X2TS U895 ( .A(Sgf_operation_ODD1_Q_middle[25]), .B(
DP_OP_168J45_122_1342_n524), .C(DP_OP_168J45_122_1342_n576), .CO(n1313), .S(n1312) );
ADDFHX2TS U896 ( .A(n5132), .B(Sgf_operation_ODD1_Q_right[47]), .CI(n5131),
.CO(n5128), .S(n5133) );
CMPR32X2TS U897 ( .A(n5135), .B(Sgf_operation_ODD1_Q_right[46]), .C(n5134),
.CO(n5131), .S(n5136) );
CMPR32X2TS U898 ( .A(Sgf_operation_ODD1_Q_middle[22]), .B(
DP_OP_168J45_122_1342_n527), .C(DP_OP_168J45_122_1342_n579), .CO(n1306), .S(n1304) );
CMPR32X2TS U899 ( .A(Sgf_operation_ODD1_Q_middle[23]), .B(
DP_OP_168J45_122_1342_n526), .C(DP_OP_168J45_122_1342_n578), .CO(n1308), .S(n1307) );
CMPR32X2TS U900 ( .A(n5141), .B(Sgf_operation_ODD1_Q_right[44]), .C(n5140),
.CO(n5137), .S(n5142) );
CMPR32X2TS U901 ( .A(Sgf_operation_ODD1_Q_middle[21]), .B(
DP_OP_168J45_122_1342_n528), .C(DP_OP_168J45_122_1342_n580), .CO(n1303), .S(n1302) );
CMPR32X2TS U902 ( .A(Sgf_operation_ODD1_Q_middle[20]), .B(
DP_OP_168J45_122_1342_n529), .C(DP_OP_168J45_122_1342_n581), .CO(n1301), .S(n1299) );
CMPR32X2TS U903 ( .A(Sgf_operation_ODD1_Q_middle[18]), .B(
DP_OP_168J45_122_1342_n531), .C(DP_OP_168J45_122_1342_n583), .CO(n1296), .S(n1294) );
CMPR32X2TS U904 ( .A(Sgf_operation_ODD1_Q_middle[19]), .B(
DP_OP_168J45_122_1342_n530), .C(DP_OP_168J45_122_1342_n582), .CO(n1298), .S(n1297) );
CMPR32X2TS U905 ( .A(n5153), .B(Sgf_operation_ODD1_Q_right[40]), .C(n5152),
.CO(n5149), .S(n5154) );
CMPR32X2TS U906 ( .A(Sgf_operation_ODD1_Q_middle[16]), .B(
DP_OP_168J45_122_1342_n533), .C(DP_OP_168J45_122_1342_n585), .CO(n1291), .S(n1289) );
CMPR32X2TS U907 ( .A(Sgf_operation_ODD1_Q_middle[17]), .B(
DP_OP_168J45_122_1342_n532), .C(DP_OP_168J45_122_1342_n584), .CO(n1293), .S(n1292) );
ADDFHX2TS U908 ( .A(n5160), .B(Sgf_operation_ODD1_Q_right[38]), .CI(n5159),
.CO(n5156), .S(n5161) );
CMPR32X2TS U909 ( .A(n5163), .B(Sgf_operation_ODD1_Q_right[37]), .C(n5162),
.CO(n5159), .S(n5164) );
CMPR32X2TS U910 ( .A(Sgf_operation_ODD1_Q_middle[15]), .B(
DP_OP_168J45_122_1342_n534), .C(DP_OP_168J45_122_1342_n586), .CO(n1288), .S(n1283) );
CMPR32X2TS U911 ( .A(n5169), .B(Sgf_operation_ODD1_Q_right[35]), .C(n5168),
.CO(n5165), .S(n5170) );
CMPR32X2TS U912 ( .A(Sgf_operation_ODD1_Q_middle[10]), .B(
DP_OP_168J45_122_1342_n539), .C(DP_OP_168J45_122_1342_n591), .CO(n1272), .S(n1271) );
CMPR32X2TS U913 ( .A(Sgf_operation_ODD1_Q_middle[9]), .B(
DP_OP_168J45_122_1342_n540), .C(DP_OP_168J45_122_1342_n592), .CO(n1270), .S(n1269) );
CMPR32X2TS U914 ( .A(Sgf_operation_ODD1_Q_middle[8]), .B(
DP_OP_168J45_122_1342_n541), .C(DP_OP_168J45_122_1342_n593), .CO(n1268), .S(n1267) );
CMPR32X2TS U915 ( .A(n5188), .B(Sgf_operation_ODD1_Q_right[29]), .C(n5187),
.CO(n5184), .S(n5189) );
CMPR32X2TS U916 ( .A(Sgf_operation_ODD1_Q_middle[6]), .B(
DP_OP_168J45_122_1342_n543), .C(DP_OP_168J45_122_1342_n595), .CO(n1260), .S(n1259) );
CMPR32X2TS U917 ( .A(Sgf_operation_ODD1_Q_middle[7]), .B(
DP_OP_168J45_122_1342_n542), .C(DP_OP_168J45_122_1342_n594), .CO(n1266), .S(n1261) );
CMPR32X2TS U918 ( .A(Sgf_operation_ODD1_Q_middle[5]), .B(
DP_OP_168J45_122_1342_n544), .C(DP_OP_168J45_122_1342_n596), .CO(n1258), .S(n1257) );
NOR2X1TS U919 ( .A(n1255), .B(n1254), .Y(n1648) );
CMPR32X2TS U920 ( .A(Sgf_operation_ODD1_Q_middle[4]), .B(
DP_OP_168J45_122_1342_n545), .C(DP_OP_168J45_122_1342_n597), .CO(n1256), .S(n1255) );
NAND2X1TS U921 ( .A(n1249), .B(n1248), .Y(n1666) );
CMPR32X2TS U922 ( .A(Sgf_operation_ODD1_Q_middle[3]), .B(
DP_OP_168J45_122_1342_n546), .C(DP_OP_168J45_122_1342_n598), .CO(n1254), .S(n1251) );
NOR2X2TS U923 ( .A(n1249), .B(n1248), .Y(n1665) );
CMPR32X2TS U924 ( .A(Sgf_operation_ODD1_Q_middle[2]), .B(
DP_OP_168J45_122_1342_n547), .C(DP_OP_168J45_122_1342_n599), .CO(n1250), .S(n1249) );
NAND2X1TS U925 ( .A(DP_OP_168J45_122_1342_n549), .B(
Sgf_operation_ODD1_Q_middle[0]), .Y(n1675) );
OR2X1TS U926 ( .A(Op_MX[9]), .B(Op_MX[36]), .Y(n956) );
OR2X1TS U927 ( .A(Op_MX[6]), .B(Op_MX[33]), .Y(n953) );
OAI21XLTS U928 ( .A0(n2125), .A1(n1996), .B0(n1995), .Y(n1998) );
OAI21XLTS U929 ( .A0(n4651), .A1(n4650), .B0(n4656), .Y(n4649) );
OAI21XLTS U930 ( .A0(n2719), .A1(n2718), .B0(n3402), .Y(n2717) );
OAI21XLTS U931 ( .A0(n2125), .A1(n1951), .B0(n1950), .Y(n1954) );
OAI21XLTS U932 ( .A0(n2710), .A1(n2709), .B0(n3402), .Y(n2708) );
OAI21XLTS U933 ( .A0(n3964), .A1(n3963), .B0(n5451), .Y(n3962) );
OAI21XLTS U934 ( .A0(n3358), .A1(n3262), .B0(n2728), .Y(n2733) );
OAI21XLTS U935 ( .A0(n3993), .A1(n3992), .B0(n4699), .Y(n3991) );
OAI21XLTS U936 ( .A0(n4168), .A1(n4167), .B0(n4699), .Y(n4166) );
OAI21XLTS U937 ( .A0(n3358), .A1(n3254), .B0(n2722), .Y(n2727) );
OAI21XLTS U938 ( .A0(n3369), .A1(n3112), .B0(n2714), .Y(n2715) );
NOR2XLTS U939 ( .A(n1665), .B(n1660), .Y(n1253) );
OAI21XLTS U940 ( .A0(n3168), .A1(n3167), .B0(n3391), .Y(n3166) );
OAI21XLTS U941 ( .A0(n3967), .A1(n3966), .B0(n4699), .Y(n3965) );
OAI21XLTS U942 ( .A0(n3970), .A1(n3969), .B0(n4699), .Y(n3968) );
OAI21XLTS U943 ( .A0(n4119), .A1(n4118), .B0(n4674), .Y(n4117) );
OAI21XLTS U944 ( .A0(n3996), .A1(n3995), .B0(n4726), .Y(n3994) );
OAI21XLTS U945 ( .A0(n4028), .A1(n4027), .B0(n4744), .Y(n4026) );
OAI21XLTS U946 ( .A0(n4178), .A1(n4177), .B0(n4726), .Y(n4176) );
OAI21XLTS U947 ( .A0(n4229), .A1(n4228), .B0(n4744), .Y(n4227) );
OAI21XLTS U948 ( .A0(n4187), .A1(n4186), .B0(n4726), .Y(n4185) );
OAI21XLTS U949 ( .A0(n4303), .A1(n4302), .B0(n4782), .Y(n4301) );
OAI21XLTS U950 ( .A0(n4241), .A1(n4240), .B0(n4744), .Y(n4239) );
OAI21XLTS U951 ( .A0(n3942), .A1(n3941), .B0(n4674), .Y(n3940) );
OAI21XLTS U952 ( .A0(n3297), .A1(n3296), .B0(n3384), .Y(n3295) );
NAND2X1TS U953 ( .A(n1255), .B(n1254), .Y(n1655) );
OR2X1TS U954 ( .A(n1324), .B(n1323), .Y(n903) );
OAI21XLTS U955 ( .A0(n2244), .A1(n1889), .B0(n1888), .Y(n1890) );
OAI21XLTS U956 ( .A0(n3330), .A1(n3329), .B0(n3391), .Y(n3328) );
OAI21XLTS U957 ( .A0(n3165), .A1(n3164), .B0(n3318), .Y(n3163) );
OAI21XLTS U958 ( .A0(n2834), .A1(n3396), .B0(n2821), .Y(n2822) );
OAI21XLTS U959 ( .A0(n3981), .A1(n3980), .B0(n4726), .Y(n3979) );
OAI21XLTS U960 ( .A0(n3101), .A1(n3100), .B0(n3098), .Y(n3099) );
OAI21XLTS U961 ( .A0(n4153), .A1(n4152), .B0(n4726), .Y(n4151) );
OAI21XLTS U962 ( .A0(n4156), .A1(n4155), .B0(n4726), .Y(n4154) );
OAI21XLTS U963 ( .A0(n3059), .A1(n3058), .B0(n3098), .Y(n3057) );
OAI21XLTS U964 ( .A0(n3055), .A1(n3054), .B0(n3407), .Y(n3053) );
OAI21XLTS U965 ( .A0(n4195), .A1(n4193), .B0(n4744), .Y(n4192) );
OAI21XLTS U966 ( .A0(n4044), .A1(n4043), .B0(n4782), .Y(n4042) );
OAI21XLTS U967 ( .A0(n4054), .A1(n4053), .B0(n929), .Y(n4052) );
OAI21XLTS U968 ( .A0(n4279), .A1(n4277), .B0(n4782), .Y(n4276) );
OAI21XLTS U969 ( .A0(n4057), .A1(n4056), .B0(n929), .Y(n4055) );
OAI21XLTS U970 ( .A0(n4071), .A1(n4070), .B0(n4510), .Y(n4069) );
OAI21XLTS U971 ( .A0(n4084), .A1(n4083), .B0(n4510), .Y(n4082) );
OAI21XLTS U972 ( .A0(n3977), .A1(n3976), .B0(n4174), .Y(n3975) );
OAI21XLTS U973 ( .A0(n3955), .A1(n3954), .B0(n4699), .Y(n3953) );
OAI21XLTS U974 ( .A0(n3084), .A1(n3083), .B0(n3098), .Y(n3082) );
INVX2TS U975 ( .A(n1621), .Y(n1630) );
OAI21XLTS U976 ( .A0(n1630), .A1(n1605), .B0(n1604), .Y(n1610) );
OAI21X1TS U977 ( .A0(n1529), .A1(n1525), .B0(n1526), .Y(n1524) );
OAI21X1TS U978 ( .A0(n1497), .A1(n1493), .B0(n1494), .Y(n1492) );
AOI21X1TS U979 ( .A0(n1468), .A1(n922), .B0(n1351), .Y(n1465) );
AOI21X1TS U980 ( .A0(n1436), .A1(n926), .B0(n1383), .Y(n1433) );
OAI21XLTS U981 ( .A0(n3952), .A1(n3951), .B0(n5338), .Y(n3950) );
OAI21XLTS U982 ( .A0(n2834), .A1(n3332), .B0(n2807), .Y(n2808) );
OAI21XLTS U983 ( .A0(n3215), .A1(n3214), .B0(n5334), .Y(n3213) );
OAI21XLTS U984 ( .A0(n3195), .A1(n3194), .B0(n3391), .Y(n3193) );
OAI21XLTS U985 ( .A0(n3299), .A1(n1054), .B0(n1025), .Y(n1026) );
OAI21XLTS U986 ( .A0(n3396), .A1(n1054), .B0(n1032), .Y(n1033) );
OAI21XLTS U987 ( .A0(n3010), .A1(n1054), .B0(n1039), .Y(n1040) );
OAI21XLTS U988 ( .A0(n3491), .A1(n3490), .B0(n3659), .Y(n3489) );
OAI21XLTS U989 ( .A0(n3496), .A1(n3495), .B0(n3659), .Y(n3494) );
OAI211XLTS U990 ( .A0(Sgf_normalized_result[50]), .A1(n5039), .B0(n5038),
.C0(n5041), .Y(n5040) );
ADDFHX2TS U991 ( .A(n5150), .B(Sgf_operation_ODD1_Q_right[41]), .CI(n5149),
.CO(n5146), .S(n5151) );
ADDFHX2TS U992 ( .A(n3691), .B(Sgf_operation_ODD1_Q_left[1]), .CI(n3690),
.CO(n5108), .S(n3692) );
XNOR2X2TS U993 ( .A(DP_OP_168J45_122_1342_n548), .B(
Sgf_operation_ODD1_Q_middle[1]), .Y(n732) );
CLKXOR2X2TS U994 ( .A(n2103), .B(n2102), .Y(n733) );
ADDHX1TS U995 ( .A(Sgf_operation_ODD1_Q_left[50]), .B(n3680), .CO(n1678),
.S(n3681) );
ADDHX1TS U996 ( .A(Sgf_operation_ODD1_Q_left[49]), .B(n3678), .CO(n3680),
.S(n3679) );
ADDHX1TS U997 ( .A(Sgf_operation_ODD1_Q_left[46]), .B(n3672), .CO(n3674),
.S(n3673) );
ADDHX1TS U998 ( .A(Sgf_operation_ODD1_Q_left[45]), .B(n3466), .CO(n3672),
.S(n3467) );
ADDHX1TS U999 ( .A(Sgf_operation_ODD1_Q_left[44]), .B(n5048), .CO(n3466),
.S(n5049) );
AO22X1TS U1000 ( .A0(n5080), .A1(P_Sgf[87]), .B0(n3465), .B1(n5071), .Y(n508) );
AO22X1TS U1001 ( .A0(n5024), .A1(n3766), .B0(n753), .B1(Add_result[49]), .Y(
n530) );
AOI21X2TS U1002 ( .A0(n1476), .A1(n907), .B0(n1345), .Y(n1473) );
AOI2BB2X1TS U1003 ( .B0(n4838), .B1(n4846), .A0N(n853), .A1N(n4834), .Y(
n4832) );
AOI2BB2X1TS U1004 ( .B0(n4841), .B1(n4846), .A0N(n853), .A1N(n4840), .Y(
n4842) );
OAI21X2TS U1005 ( .A0(n1481), .A1(n1477), .B0(n1478), .Y(n1476) );
OAI21X1TS U1006 ( .A0(n4079), .A1(n4078), .B0(n4510), .Y(n4077) );
OAI21X1TS U1007 ( .A0(n2834), .A1(n2891), .B0(n2833), .Y(n2835) );
OAI21X1TS U1008 ( .A0(n3018), .A1(n3017), .B0(n3015), .Y(n3016) );
OAI21X1TS U1009 ( .A0(n3013), .A1(n3012), .B0(n976), .Y(n3011) );
OAI21X1TS U1010 ( .A0(n3010), .A1(n3395), .B0(n2930), .Y(n2823) );
OAI21X1TS U1011 ( .A0(n3396), .A1(n3395), .B0(n3056), .Y(n3397) );
OAI21X1TS U1012 ( .A0(n3093), .A1(n3092), .B0(n3098), .Y(n3091) );
OAI21X1TS U1013 ( .A0(n4333), .A1(n4332), .B0(n4516), .Y(n4331) );
OAI21X1TS U1014 ( .A0(n4437), .A1(n4436), .B0(n4510), .Y(n4435) );
OAI21X1TS U1015 ( .A0(n4341), .A1(n4340), .B0(n4516), .Y(n4339) );
OAI21X1TS U1016 ( .A0(n4344), .A1(n4343), .B0(n4516), .Y(n4342) );
OAI21X1TS U1017 ( .A0(n3302), .A1(n3301), .B0(n3384), .Y(n3300) );
OAI21X1TS U1018 ( .A0(n3319), .A1(n3317), .B0(n968), .Y(n3316) );
OAI21X1TS U1019 ( .A0(n4050), .A1(n4049), .B0(n4782), .Y(n4048) );
OAI21X1TS U1020 ( .A0(n4375), .A1(n4374), .B0(n4516), .Y(n4373) );
OAI21X1TS U1021 ( .A0(n3308), .A1(n3307), .B0(n968), .Y(n3306) );
OAI21X1TS U1022 ( .A0(n4110), .A1(n4109), .B0(n4674), .Y(n4108) );
OAI21X1TS U1023 ( .A0(n3154), .A1(n3153), .B0(n968), .Y(n3152) );
OAI21X1TS U1024 ( .A0(n3104), .A1(n3103), .B0(n3384), .Y(n3102) );
OAI21X1TS U1025 ( .A0(n3189), .A1(n3188), .B0(n3391), .Y(n3187) );
OAI21X1TS U1026 ( .A0(n4135), .A1(n4134), .B0(n4699), .Y(n4133) );
OAI21X1TS U1027 ( .A0(n4222), .A1(n4221), .B0(n4744), .Y(n4220) );
OAI21X1TS U1028 ( .A0(n4315), .A1(n4314), .B0(n4782), .Y(n4313) );
OAI21X1TS U1029 ( .A0(n4171), .A1(n4170), .B0(n4726), .Y(n4169) );
OAI21X1TS U1030 ( .A0(n3133), .A1(n3132), .B0(n968), .Y(n3131) );
OAI21X1TS U1031 ( .A0(n3081), .A1(n3080), .B0(n3384), .Y(n3079) );
OAI21X1TS U1032 ( .A0(n4232), .A1(n4231), .B0(n4744), .Y(n4230) );
OAI21X1TS U1033 ( .A0(n4184), .A1(n4183), .B0(n4726), .Y(n4182) );
OAI21X1TS U1034 ( .A0(n3162), .A1(n3161), .B0(n3391), .Y(n3160) );
OAI21X1TS U1035 ( .A0(n3990), .A1(n3989), .B0(n4699), .Y(n3988) );
OAI21X1TS U1036 ( .A0(n4247), .A1(n4246), .B0(n4744), .Y(n4245) );
AOI21X1TS U1037 ( .A0(n1532), .A1(n974), .B0(n1310), .Y(n1529) );
OAI21X1TS U1038 ( .A0(n4138), .A1(n4137), .B0(n4674), .Y(n4136) );
OAI21X1TS U1039 ( .A0(n1553), .A1(n1549), .B0(n1550), .Y(n1548) );
AOI21X1TS U1040 ( .A0(n1556), .A1(n960), .B0(n1295), .Y(n1553) );
XNOR2X1TS U1041 ( .A(n1610), .B(n1609), .Y(n5160) );
XOR2X1TS U1042 ( .A(n1626), .B(n1625), .Y(n5166) );
INVX6TS U1043 ( .A(n4751), .Y(n4400) );
XNOR2X1TS U1044 ( .A(n1664), .B(n1663), .Y(n5185) );
CLKBUFX2TS U1045 ( .A(n2423), .Y(n809) );
INVX6TS U1046 ( .A(n4841), .Y(n745) );
INVX6TS U1047 ( .A(n4073), .Y(n4725) );
OAI21X1TS U1048 ( .A0(n1631), .A1(n1265), .B0(n1264), .Y(n1621) );
INVX6TS U1049 ( .A(n4838), .Y(n743) );
INVX6TS U1050 ( .A(n4661), .Y(n3933) );
BUFX6TS U1051 ( .A(n3465), .Y(n734) );
INVX4TS U1052 ( .A(n5207), .Y(n5201) );
NAND2XLTS U1053 ( .A(n1519), .B(n1518), .Y(n1520) );
NAND2XLTS U1054 ( .A(n1511), .B(n1510), .Y(n1512) );
NAND2XLTS U1055 ( .A(n1503), .B(n1502), .Y(n1504) );
NAND2XLTS U1056 ( .A(n1495), .B(n1494), .Y(n1496) );
BUFX6TS U1057 ( .A(n4947), .Y(n753) );
INVX6TS U1058 ( .A(n3665), .Y(n751) );
NAND2XLTS U1059 ( .A(n1527), .B(n1526), .Y(n1528) );
NAND2XLTS U1060 ( .A(n1535), .B(n1534), .Y(n1536) );
NAND2XLTS U1061 ( .A(n902), .B(n1514), .Y(n1515) );
NAND2XLTS U1062 ( .A(n903), .B(n1506), .Y(n1507) );
INVX1TS U1063 ( .A(n1509), .Y(n1511) );
NAND2XLTS U1064 ( .A(n974), .B(n1530), .Y(n1531) );
INVX1TS U1065 ( .A(n1533), .Y(n1535) );
NAND2XLTS U1066 ( .A(n973), .B(n1538), .Y(n1539) );
OR2X6TS U1067 ( .A(n728), .B(n3682), .Y(n3683) );
BUFX6TS U1068 ( .A(n979), .Y(n4888) );
INVX1TS U1069 ( .A(n1541), .Y(n1543) );
INVX1TS U1070 ( .A(n1525), .Y(n1527) );
INVX1TS U1071 ( .A(n1517), .Y(n1519) );
NAND2XLTS U1072 ( .A(n901), .B(n1522), .Y(n1523) );
NAND2X1TS U1073 ( .A(n1267), .B(n1266), .Y(n1627) );
INVX2TS U1074 ( .A(n763), .Y(n4194) );
OR2X2TS U1075 ( .A(n1319), .B(n1318), .Y(n902) );
OR2X2TS U1076 ( .A(n1314), .B(n1313), .Y(n901) );
OR2X2TS U1077 ( .A(n1309), .B(n1308), .Y(n974) );
OR2X2TS U1078 ( .A(n1304), .B(n1303), .Y(n973) );
INVX6TS U1079 ( .A(rst), .Y(n5478) );
AO22X1TS U1080 ( .A0(n5199), .A1(P_Sgf[105]), .B0(n3465), .B1(n1679), .Y(
n420) );
AO22X1TS U1081 ( .A0(n5080), .A1(P_Sgf[103]), .B0(n734), .B1(n3679), .Y(n525) );
AO22X1TS U1082 ( .A0(n5080), .A1(P_Sgf[102]), .B0(n734), .B1(n3677), .Y(n524) );
ADDHX2TS U1083 ( .A(Sgf_operation_ODD1_Q_left[48]), .B(n3676), .CO(n3678),
.S(n3677) );
AO22X1TS U1084 ( .A0(n5080), .A1(P_Sgf[101]), .B0(n734), .B1(n3675), .Y(n523) );
ADDHX2TS U1085 ( .A(Sgf_operation_ODD1_Q_left[47]), .B(n3674), .CO(n3676),
.S(n3675) );
AO22X1TS U1086 ( .A0(n5080), .A1(P_Sgf[100]), .B0(n734), .B1(n3673), .Y(n522) );
AO22X1TS U1087 ( .A0(n5127), .A1(P_Sgf[99]), .B0(n734), .B1(n3467), .Y(n521)
);
AO22X1TS U1088 ( .A0(n5080), .A1(P_Sgf[98]), .B0(n734), .B1(n5049), .Y(n519)
);
AO22X1TS U1089 ( .A0(n5127), .A1(P_Sgf[97]), .B0(n734), .B1(n5051), .Y(n518)
);
ADDHX2TS U1090 ( .A(Sgf_operation_ODD1_Q_left[43]), .B(n5050), .CO(n5048),
.S(n5051) );
AO22X1TS U1091 ( .A0(n5080), .A1(P_Sgf[96]), .B0(n734), .B1(n5053), .Y(n517)
);
AO22X1TS U1092 ( .A0(n5127), .A1(P_Sgf[95]), .B0(n734), .B1(n5055), .Y(n516)
);
ADDHX2TS U1093 ( .A(Sgf_operation_ODD1_Q_left[42]), .B(n5052), .CO(n5050),
.S(n5053) );
AO22X1TS U1094 ( .A0(n5080), .A1(P_Sgf[94]), .B0(n734), .B1(n5057), .Y(n515)
);
ADDHX1TS U1095 ( .A(Sgf_operation_ODD1_Q_left[41]), .B(n5054), .CO(n5052),
.S(n5055) );
ADDHX2TS U1096 ( .A(Sgf_operation_ODD1_Q_left[40]), .B(n5056), .CO(n5054),
.S(n5057) );
AO22X1TS U1097 ( .A0(n5080), .A1(P_Sgf[93]), .B0(n3465), .B1(n5059), .Y(n514) );
ADDHX2TS U1098 ( .A(Sgf_operation_ODD1_Q_left[39]), .B(n5058), .CO(n5056),
.S(n5059) );
AO22X1TS U1099 ( .A0(n5080), .A1(P_Sgf[92]), .B0(n3465), .B1(n5061), .Y(n513) );
AO22X1TS U1100 ( .A0(n5080), .A1(P_Sgf[91]), .B0(n3465), .B1(n5063), .Y(n512) );
ADDHX2TS U1101 ( .A(Sgf_operation_ODD1_Q_left[38]), .B(n5060), .CO(n5058),
.S(n5061) );
AO22X1TS U1102 ( .A0(n5080), .A1(P_Sgf[90]), .B0(n3465), .B1(n5065), .Y(n511) );
ADDHX1TS U1103 ( .A(Sgf_operation_ODD1_Q_left[37]), .B(n5062), .CO(n5060),
.S(n5063) );
AO22X1TS U1104 ( .A0(n5080), .A1(P_Sgf[89]), .B0(n3465), .B1(n5067), .Y(n510) );
ADDHX1TS U1105 ( .A(Sgf_operation_ODD1_Q_left[36]), .B(n5064), .CO(n5062),
.S(n5065) );
AO22X1TS U1106 ( .A0(n5080), .A1(P_Sgf[88]), .B0(n3465), .B1(n5069), .Y(n509) );
ADDHX2TS U1107 ( .A(Sgf_operation_ODD1_Q_left[35]), .B(n5066), .CO(n5064),
.S(n5067) );
ADDHX2TS U1108 ( .A(Sgf_operation_ODD1_Q_left[34]), .B(n5068), .CO(n5066),
.S(n5069) );
ADDHX2TS U1109 ( .A(Sgf_operation_ODD1_Q_left[33]), .B(n5070), .CO(n5068),
.S(n5071) );
ADDHX1TS U1110 ( .A(Sgf_operation_ODD1_Q_left[32]), .B(n5072), .CO(n5070),
.S(n5073) );
ADDHX2TS U1111 ( .A(Sgf_operation_ODD1_Q_left[31]), .B(n5074), .CO(n5072),
.S(n5075) );
ADDHX1TS U1112 ( .A(Sgf_operation_ODD1_Q_left[30]), .B(n5076), .CO(n5074),
.S(n5077) );
AOI2BB1X1TS U1113 ( .A0N(n5047), .A1N(FSM_add_overflow_flag), .B0(n5046),
.Y(n526) );
AND2X2TS U1114 ( .A(n1409), .B(n1408), .Y(n909) );
XOR2X1TS U1115 ( .A(n1417), .B(n1416), .Y(n3738) );
AOI21X2TS U1116 ( .A0(n1420), .A1(n927), .B0(n1401), .Y(n1417) );
XNOR2X1TS U1117 ( .A(n1444), .B(n1443), .Y(n3717) );
OAI21X1TS U1118 ( .A0(n4009), .A1(n4008), .B0(n4194), .Y(n4007) );
OAI21X1TS U1119 ( .A0(n4040), .A1(n4039), .B0(n4782), .Y(n4038) );
OAI21X1TS U1120 ( .A0(n4047), .A1(n4046), .B0(n4782), .Y(n4045) );
OAI21X1TS U1121 ( .A0(n3958), .A1(n3957), .B0(n4699), .Y(n3956) );
OAI21X1TS U1122 ( .A0(n4022), .A1(n4021), .B0(n4744), .Y(n4020) );
OAI21X1TS U1123 ( .A0(n3984), .A1(n3983), .B0(n4726), .Y(n3982) );
BUFX3TS U1124 ( .A(n4837), .Y(n842) );
OAI21X1TS U1125 ( .A0(n4338), .A1(n4337), .B0(n929), .Y(n4336) );
OAI21X1TS U1126 ( .A0(n3192), .A1(n3191), .B0(n3318), .Y(n3190) );
OAI21XLTS U1127 ( .A0(n2834), .A1(n3400), .B0(n993), .Y(n994) );
OAI21X1TS U1128 ( .A0(n3148), .A1(n3147), .B0(n5335), .Y(n3146) );
OAI21X1TS U1129 ( .A0(n2834), .A1(n3010), .B0(n2826), .Y(n2827) );
OAI21X1TS U1130 ( .A0(n2834), .A1(n3315), .B0(n2812), .Y(n2813) );
OAI21X1TS U1131 ( .A0(n2834), .A1(n3299), .B0(n2817), .Y(n2818) );
OAI21X1TS U1132 ( .A0(n3332), .A1(n1054), .B0(n1011), .Y(n1012) );
OAI21X1TS U1133 ( .A0(n4016), .A1(n4015), .B0(n4744), .Y(n4014) );
OAI21X1TS U1134 ( .A0(n3315), .A1(n1054), .B0(n1018), .Y(n1019) );
OAI21XLTS U1135 ( .A0(n4087), .A1(n4086), .B0(n4659), .Y(n4085) );
OAI21X1TS U1136 ( .A0(n4122), .A1(n4121), .B0(n4699), .Y(n4120) );
OAI21X1TS U1137 ( .A0(n4260), .A1(n4259), .B0(n4782), .Y(n4258) );
OAI21X1TS U1138 ( .A0(n3145), .A1(n3144), .B0(n3384), .Y(n3143) );
OAI21X1TS U1139 ( .A0(n4096), .A1(n4095), .B0(n4674), .Y(n4094) );
OAI21X1TS U1140 ( .A0(n4191), .A1(n4190), .B0(n4744), .Y(n4189) );
OAI21X1TS U1141 ( .A0(n3209), .A1(n3208), .B0(n3391), .Y(n3207) );
OAI21X1TS U1142 ( .A0(n3181), .A1(n3180), .B0(n3318), .Y(n3179) );
OAI21X1TS U1143 ( .A0(n3223), .A1(n3222), .B0(n3402), .Y(n3221) );
OAI21X1TS U1144 ( .A0(n4100), .A1(n4099), .B0(n4674), .Y(n4098) );
OAI21X1TS U1145 ( .A0(n3202), .A1(n3201), .B0(n3391), .Y(n3200) );
OAI21X1TS U1146 ( .A0(n3171), .A1(n3170), .B0(n3318), .Y(n3169) );
OAI21X1TS U1147 ( .A0(n4126), .A1(n4124), .B0(n4699), .Y(n4123) );
AOI2BB2X1TS U1148 ( .B0(n2832), .B1(n982), .A0N(n982), .A1N(n2832), .Y(n980)
);
OAI21X1TS U1149 ( .A0(n3136), .A1(n3135), .B0(n3384), .Y(n3134) );
OAI21X1TS U1150 ( .A0(n4614), .A1(n4613), .B0(n4844), .Y(n4612) );
OAI21X1TS U1151 ( .A0(n3939), .A1(n3938), .B0(n4674), .Y(n3937) );
OAI21X1TS U1152 ( .A0(n4275), .A1(n4274), .B0(n4782), .Y(n4273) );
OAI21X1TS U1153 ( .A0(n3127), .A1(n3126), .B0(n3384), .Y(n3125) );
OAI21XLTS U1154 ( .A0(n3913), .A1(n3912), .B0(n4844), .Y(n3911) );
OAI21X1TS U1155 ( .A0(n3335), .A1(n3334), .B0(n3391), .Y(n3333) );
OAI21X1TS U1156 ( .A0(n3999), .A1(n3998), .B0(n4726), .Y(n3997) );
OAI21X1TS U1157 ( .A0(n3346), .A1(n3345), .B0(n3402), .Y(n3344) );
OAI21X1TS U1158 ( .A0(n4031), .A1(n4030), .B0(n4744), .Y(n4029) );
OAI21X1TS U1159 ( .A0(n4141), .A1(n4140), .B0(n4699), .Y(n4139) );
OAI21X1TS U1160 ( .A0(n4175), .A1(n4173), .B0(n4726), .Y(n4172) );
OAI21XLTS U1161 ( .A0(n3369), .A1(n3399), .B0(n3361), .Y(n3362) );
XNOR2X1TS U1162 ( .A(n1508), .B(n1507), .Y(n5106) );
OAI21X1TS U1163 ( .A0(n4093), .A1(n4092), .B0(n4844), .Y(n4091) );
OAI21X1TS U1164 ( .A0(n4116), .A1(n4115), .B0(n4674), .Y(n4114) );
OAI21X1TS U1165 ( .A0(n4144), .A1(n4143), .B0(n4699), .Y(n4142) );
OAI21X1TS U1166 ( .A0(n4150), .A1(n4149), .B0(n4699), .Y(n4148) );
OAI21X1TS U1167 ( .A0(n3199), .A1(n3198), .B0(n3402), .Y(n3197) );
OAI21X1TS U1168 ( .A0(n4625), .A1(n4624), .B0(n4844), .Y(n4623) );
XNOR2X1TS U1169 ( .A(n1516), .B(n1515), .Y(n3691) );
OAI21X1TS U1170 ( .A0(n3961), .A1(n3960), .B0(n4674), .Y(n3959) );
OAI21X1TS U1171 ( .A0(n4633), .A1(n4632), .B0(n4656), .Y(n4631) );
OAI21X1TS U1172 ( .A0(n2705), .A1(n2704), .B0(n3402), .Y(n2703) );
XNOR2X1TS U1173 ( .A(n1524), .B(n1523), .Y(n5116) );
OAI21X1TS U1174 ( .A0(n4113), .A1(n4112), .B0(n4656), .Y(n4111) );
OAI21X1TS U1175 ( .A0(n4643), .A1(n4642), .B0(n4656), .Y(n4641) );
XNOR2X1TS U1176 ( .A(n1548), .B(n1547), .Y(n5132) );
ADDFX1TS U1177 ( .A(n5172), .B(Sgf_operation_ODD1_Q_right[34]), .CI(n5171),
.CO(n5168), .S(n5173) );
ADDFHX2TS U1178 ( .A(n5175), .B(Sgf_operation_ODD1_Q_right[33]), .CI(n5174),
.CO(n5171), .S(n5176) );
XOR2X1TS U1179 ( .A(n1944), .B(n1943), .Y(n774) );
XOR2X1TS U1180 ( .A(n1924), .B(n1923), .Y(n783) );
XOR2X1TS U1181 ( .A(n1954), .B(n1953), .Y(n778) );
XOR2X1TS U1182 ( .A(n1994), .B(n1993), .Y(n775) );
XOR2X1TS U1183 ( .A(n2055), .B(n2054), .Y(n772) );
XOR2X1TS U1184 ( .A(n1972), .B(n1971), .Y(n777) );
XOR2X1TS U1185 ( .A(n2128), .B(n2127), .Y(n776) );
XOR2X1TS U1186 ( .A(n2008), .B(n2007), .Y(n773) );
XOR2X1TS U1187 ( .A(n2247), .B(n2246), .Y(n781) );
ADDHXLTS U1188 ( .A(n2073), .B(n2072), .CO(n2070), .S(
DP_OP_169J45_123_4229_n514) );
XOR2X1TS U1189 ( .A(n2239), .B(n2238), .Y(n782) );
XOR2X1TS U1190 ( .A(n2095), .B(n2094), .Y(n770) );
XOR2X1TS U1191 ( .A(n1873), .B(n1872), .Y(n780) );
OAI21X1TS U1192 ( .A0(n4201), .A1(n4200), .B0(n4656), .Y(n4199) );
ADDFHX2TS U1193 ( .A(n5182), .B(Sgf_operation_ODD1_Q_right[31]), .CI(n5181),
.CO(n5177), .S(n5183) );
XOR2X1TS U1194 ( .A(n1998), .B(n1997), .Y(n779) );
ADDFHX2TS U1195 ( .A(n5185), .B(Sgf_operation_ODD1_Q_right[30]), .CI(n5184),
.CO(n5181), .S(n5186) );
ADDHXLTS U1196 ( .A(n2208), .B(n2207), .CO(n2205), .S(
DP_OP_169J45_123_4229_n726) );
ADDHXLTS U1197 ( .A(n2192), .B(n2191), .CO(n2189), .S(
DP_OP_169J45_123_4229_n691) );
ADDHXLTS U1198 ( .A(n2224), .B(n2223), .CO(n2221), .S(
DP_OP_169J45_123_4229_n749) );
CLKBUFX3TS U1199 ( .A(n2601), .Y(n800) );
CLKBUFX3TS U1200 ( .A(n2305), .Y(n801) );
INVX6TS U1201 ( .A(n4818), .Y(n735) );
CLKBUFX3TS U1202 ( .A(n2334), .Y(n812) );
OR3X4TS U1203 ( .A(underflow_flag), .B(overflow_flag), .C(n5201), .Y(n5200)
);
AOI21X1TS U1204 ( .A0(n1621), .A1(n1628), .B0(n1620), .Y(n1626) );
BUFX3TS U1205 ( .A(n3780), .Y(n736) );
NAND3X1TS U1206 ( .A(n4005), .B(n4754), .C(n4004), .Y(n4006) );
INVX6TS U1207 ( .A(n4824), .Y(n737) );
NOR2X2TS U1208 ( .A(FSM_selector_C), .B(n3774), .Y(n3775) );
OAI21X1TS U1209 ( .A0(n1669), .A1(n1665), .B0(n1666), .Y(n1664) );
BUFX6TS U1210 ( .A(n2602), .Y(n871) );
CLKBUFX3TS U1211 ( .A(n2450), .Y(n803) );
INVX6TS U1212 ( .A(n4032), .Y(n4773) );
CLKBUFX3TS U1213 ( .A(n2482), .Y(n807) );
CLKBUFX3TS U1214 ( .A(n2391), .Y(n802) );
CLKBUFX3TS U1215 ( .A(n2510), .Y(n804) );
CLKBUFX3TS U1216 ( .A(n2364), .Y(n808) );
INVX6TS U1217 ( .A(n4830), .Y(n738) );
BUFX3TS U1218 ( .A(n4037), .Y(n4778) );
INVX6TS U1219 ( .A(n4806), .Y(n739) );
NAND3X1TS U1220 ( .A(n3973), .B(n4076), .C(n3972), .Y(n3974) );
INVX6TS U1221 ( .A(n4059), .Y(n4097) );
INVX6TS U1222 ( .A(n4847), .Y(n740) );
INVX3TS U1223 ( .A(n2758), .Y(n3291) );
INVX6TS U1224 ( .A(n4705), .Y(n4697) );
BUFX6TS U1225 ( .A(n2272), .Y(n741) );
CLKAND2X2TS U1226 ( .A(n856), .B(n857), .Y(n855) );
NAND3X1TS U1227 ( .A(n3916), .B(n4062), .C(n3915), .Y(n3917) );
NAND3X1TS U1228 ( .A(n4036), .B(n4035), .C(n4034), .Y(n4037) );
INVX3TS U1229 ( .A(n2934), .Y(n3299) );
NAND2BX4TS U1230 ( .AN(n3770), .B(n1246), .Y(n3465) );
INVX3TS U1231 ( .A(n3251), .Y(n3321) );
INVX6TS U1232 ( .A(n3588), .Y(n4351) );
INVX6TS U1233 ( .A(n4812), .Y(n742) );
NAND3X1TS U1234 ( .A(n3948), .B(n4708), .C(n3947), .Y(n3949) );
INVX6TS U1235 ( .A(n3616), .Y(n4443) );
BUFX6TS U1236 ( .A(n3683), .Y(n5473) );
NAND3X1TS U1237 ( .A(n3901), .B(n4665), .C(n3470), .Y(n3468) );
INVX3TS U1238 ( .A(n2738), .Y(n3389) );
BUFX6TS U1239 ( .A(n3683), .Y(n744) );
INVX3TS U1240 ( .A(n2887), .Y(n3010) );
INVX6TS U1241 ( .A(n2811), .Y(n3314) );
BUFX3TS U1242 ( .A(n3473), .Y(n4506) );
BUFX3TS U1243 ( .A(n3578), .Y(n4515) );
INVX3TS U1244 ( .A(n2791), .Y(n3396) );
OR2X4TS U1245 ( .A(n4946), .B(FSM_selector_C), .Y(n3783) );
INVX2TS U1246 ( .A(n1458), .Y(n1358) );
INVX6TS U1247 ( .A(n3663), .Y(n3504) );
INVX2TS U1248 ( .A(n1410), .Y(n1407) );
AOI222X1TS U1249 ( .A0(n914), .A1(n3267), .B0(n1210), .B1(Op_MY[28]), .C0(
n1209), .C1(n848), .Y(n1211) );
INVX6TS U1250 ( .A(n2825), .Y(n2930) );
INVX6TS U1251 ( .A(n2820), .Y(n3056) );
INVX6TS U1252 ( .A(n2806), .Y(n3331) );
NAND2X1TS U1253 ( .A(n1608), .B(n1607), .Y(n1609) );
AOI222X1TS U1254 ( .A0(n1164), .A1(n3267), .B0(n918), .B1(Op_MY[28]), .C0(
n2830), .C1(n848), .Y(n1165) );
NAND2X1TS U1255 ( .A(n1656), .B(n1655), .Y(n1657) );
INVX3TS U1256 ( .A(n1164), .Y(n2891) );
INVX6TS U1257 ( .A(n1003), .Y(n3342) );
INVX6TS U1258 ( .A(n2757), .Y(n746) );
NAND2X1TS U1259 ( .A(n1624), .B(n1623), .Y(n1625) );
NAND2X1TS U1260 ( .A(n1645), .B(n1644), .Y(n1646) );
INVX2TS U1261 ( .A(n1442), .Y(n1374) );
INVX6TS U1262 ( .A(n2831), .Y(n2828) );
INVX6TS U1263 ( .A(n2816), .Y(n3298) );
INVX2TS U1264 ( .A(n1434), .Y(n1383) );
AND2X4TS U1265 ( .A(n3770), .B(n3896), .Y(DP_OP_36J45_124_1029_n42) );
INVX2TS U1266 ( .A(n1474), .Y(n1345) );
INVX2TS U1267 ( .A(n1482), .Y(n1340) );
INVX2TS U1268 ( .A(n1648), .Y(n1656) );
INVX6TS U1269 ( .A(n2771), .Y(n747) );
INVX6TS U1270 ( .A(n2810), .Y(n748) );
INVX2TS U1271 ( .A(n1490), .Y(n1335) );
INVX6TS U1272 ( .A(n2790), .Y(n749) );
INVX6TS U1273 ( .A(n3250), .Y(n750) );
NAND2X1TS U1274 ( .A(n1373), .B(n1372), .Y(n1442) );
NAND2X1TS U1275 ( .A(n1357), .B(n1356), .Y(n1458) );
ADDHX2TS U1276 ( .A(Op_MY[28]), .B(n848), .CO(n1134), .S(n3267) );
INVX3TS U1277 ( .A(n4516), .Y(n4914) );
INVX1TS U1278 ( .A(n1501), .Y(n1503) );
INVX6TS U1279 ( .A(n1139), .Y(n752) );
NAND2X1TS U1280 ( .A(n1406), .B(Sgf_operation_ODD1_Q_middle[54]), .Y(n1410)
);
NAND2X1TS U1281 ( .A(n1382), .B(n1381), .Y(n1434) );
INVX1TS U1282 ( .A(n1493), .Y(n1495) );
INVX6TS U1283 ( .A(n2805), .Y(n754) );
AOI21X1TS U1284 ( .A0(n919), .A1(n1676), .B0(n1247), .Y(n1673) );
INVX6TS U1285 ( .A(n2737), .Y(n755) );
NAND2X1TS U1286 ( .A(n1344), .B(n1343), .Y(n1474) );
INVX6TS U1287 ( .A(n3249), .Y(n756) );
INVX3TS U1288 ( .A(n3664), .Y(n3648) );
INVX6TS U1289 ( .A(n2824), .Y(n757) );
OR2X2TS U1290 ( .A(n1329), .B(n1328), .Y(n904) );
BUFX6TS U1291 ( .A(n2701), .Y(n758) );
AFHCINX2TS U1292 ( .CIN(n1684), .B(Op_MX[28]), .A(Op_MX[1]), .S(n2299), .CO(
n1760) );
INVX6TS U1293 ( .A(n1056), .Y(n1057) );
BUFX4TS U1294 ( .A(n931), .Y(n5453) );
INVX6TS U1295 ( .A(n2815), .Y(n759) );
INVX3TS U1296 ( .A(n4278), .Y(n4915) );
INVX2TS U1297 ( .A(n3263), .Y(n846) );
INVX3TS U1298 ( .A(n3488), .Y(n4893) );
NAND2X1TS U1299 ( .A(n1257), .B(n1256), .Y(n1651) );
NAND2X1TS U1300 ( .A(n1259), .B(n1258), .Y(n1644) );
ADDFX1TS U1301 ( .A(Sgf_operation_ODD1_Q_middle[12]), .B(
DP_OP_168J45_122_1342_n537), .CI(DP_OP_168J45_122_1342_n589), .CO(
n1278), .S(n1277) );
ADDFX1TS U1302 ( .A(Sgf_operation_ODD1_Q_middle[11]), .B(
DP_OP_168J45_122_1342_n538), .CI(DP_OP_168J45_122_1342_n590), .CO(
n1276), .S(n1273) );
INVX2TS U1303 ( .A(Sgf_operation_ODD1_Q_left[0]), .Y(n1676) );
OR2X2TS U1304 ( .A(DP_OP_168J45_122_1342_n549), .B(
Sgf_operation_ODD1_Q_middle[0]), .Y(n919) );
ADDFX1TS U1305 ( .A(Sgf_operation_ODD1_Q_middle[13]), .B(
DP_OP_168J45_122_1342_n536), .CI(DP_OP_168J45_122_1342_n588), .CO(
n1280), .S(n1279) );
NOR2X2TS U1306 ( .A(Op_MX[50]), .B(Op_MX[51]), .Y(n3258) );
OR2X1TS U1307 ( .A(Op_MX[21]), .B(Op_MX[48]), .Y(n1708) );
ADDFX1TS U1308 ( .A(Sgf_operation_ODD1_Q_middle[14]), .B(
DP_OP_168J45_122_1342_n535), .CI(DP_OP_168J45_122_1342_n587), .CO(
n1282), .S(n1281) );
INVX6TS U1309 ( .A(n1209), .Y(n760) );
INVX3TS U1310 ( .A(DP_OP_169J45_123_4229_n2458), .Y(n4174) );
BUFX6TS U1311 ( .A(n5478), .Y(n761) );
ADDFHX4TS U1312 ( .A(n5147), .B(Sgf_operation_ODD1_Q_right[42]), .CI(n5146),
.CO(n5143), .S(n5148) );
ADDFHX4TS U1313 ( .A(n3708), .B(Sgf_operation_ODD1_Q_left[16]), .CI(n3707),
.CO(n3710), .S(n3709) );
ADDFHX4TS U1314 ( .A(n3705), .B(Sgf_operation_ODD1_Q_left[15]), .CI(n3704),
.CO(n3707), .S(n3706) );
ADDFHX2TS U1315 ( .A(n5113), .B(Sgf_operation_ODD1_Q_left[0]), .CI(n5112),
.CO(n3690), .S(n5114) );
ADDFHX4TS U1316 ( .A(n5088), .B(Sgf_operation_ODD1_Q_left[9]), .CI(n5087),
.CO(n5084), .S(n5089) );
ADDFHX4TS U1317 ( .A(n5091), .B(Sgf_operation_ODD1_Q_left[8]), .CI(n5090),
.CO(n5087), .S(n5092) );
ADDFHX4TS U1318 ( .A(n3699), .B(Sgf_operation_ODD1_Q_left[13]), .CI(n3698),
.CO(n3701), .S(n3700) );
ADDFHX4TS U1319 ( .A(n3729), .B(Sgf_operation_ODD1_Q_left[23]), .CI(n3728),
.CO(n3731), .S(n3730) );
XOR2X4TS U1320 ( .A(n1678), .B(Sgf_operation_ODD1_Q_left[51]), .Y(n1679) );
INVX2TS U1321 ( .A(n3615), .Y(n4458) );
INVX2TS U1322 ( .A(n1631), .Y(n1658) );
OAI21XLTS U1323 ( .A0(n4357), .A1(n4356), .B0(n4516), .Y(n4355) );
NAND3XLTS U1324 ( .A(n3595), .B(n3619), .C(n3475), .Y(n3473) );
INVX2TS U1325 ( .A(n1151), .Y(n3262) );
OAI21XLTS U1326 ( .A0(n4363), .A1(n4362), .B0(n4516), .Y(n4361) );
OAI21XLTS U1327 ( .A0(n4360), .A1(n4359), .B0(n4516), .Y(n4358) );
OAI21XLTS U1328 ( .A0(n4406), .A1(n4405), .B0(n4516), .Y(n4404) );
BUFX4TS U1329 ( .A(n3482), .Y(n3657) );
XNOR2X1TS U1330 ( .A(n1564), .B(n1563), .Y(n5144) );
NAND2X1TS U1331 ( .A(n966), .B(n1562), .Y(n1563) );
XNOR2X1TS U1332 ( .A(n1532), .B(n1531), .Y(n5119) );
ADDFHX2TS U1333 ( .A(n3717), .B(Sgf_operation_ODD1_Q_left[19]), .CI(n3716),
.CO(n3719), .S(n3718) );
XOR2X1TS U1334 ( .A(n1425), .B(n1424), .Y(n3732) );
BUFX3TS U1335 ( .A(n980), .Y(n1054) );
OAI21XLTS U1336 ( .A0(n4477), .A1(n4476), .B0(n4744), .Y(n4475) );
OAI21XLTS U1337 ( .A0(n4748), .A1(n4746), .B0(n4744), .Y(n4745) );
NAND3XLTS U1338 ( .A(n3581), .B(n3592), .C(n3583), .Y(n3578) );
AOI2BB2X2TS U1339 ( .B0(Op_MX[6]), .B1(n4513), .A0N(n4878), .A1N(Op_MX[6]),
.Y(n3592) );
OAI21XLTS U1340 ( .A0(n2886), .A1(n2885), .B0(n2898), .Y(n2884) );
OAI21XLTS U1341 ( .A0(n2868), .A1(n2867), .B0(n2898), .Y(n2866) );
OAI21XLTS U1342 ( .A0(n4250), .A1(n4249), .B0(n4744), .Y(n4248) );
OAI21XLTS U1343 ( .A0(n2862), .A1(n2861), .B0(n2898), .Y(n2860) );
OAI21XLTS U1344 ( .A0(n4266), .A1(n4265), .B0(n4744), .Y(n4264) );
OAI21XLTS U1345 ( .A0(n4427), .A1(n4426), .B0(n4510), .Y(n4425) );
OAI21XLTS U1346 ( .A0(n4291), .A1(n4290), .B0(n4744), .Y(n4289) );
OAI21XLTS U1347 ( .A0(n4350), .A1(n4349), .B0(n4744), .Y(n4348) );
OAI21XLTS U1348 ( .A0(n4409), .A1(n4408), .B0(n4510), .Y(n4407) );
OAI21XLTS U1349 ( .A0(n4465), .A1(n4464), .B0(n4782), .Y(n4463) );
OAI21XLTS U1350 ( .A0(n4451), .A1(n4450), .B0(n4513), .Y(n4449) );
OAI21XLTS U1351 ( .A0(n4768), .A1(n4767), .B0(n4782), .Y(n4766) );
INVX2TS U1352 ( .A(n1144), .Y(n3254) );
OAI21XLTS U1353 ( .A0(n4785), .A1(n4784), .B0(n4782), .Y(n4783) );
OAI21XLTS U1354 ( .A0(n4501), .A1(n4500), .B0(n4510), .Y(n4499) );
INVX2TS U1355 ( .A(n1659), .Y(n1669) );
INVX2TS U1356 ( .A(n1655), .Y(n1649) );
INVX2TS U1357 ( .A(n1650), .Y(n1652) );
OAI21X1TS U1358 ( .A0(n1633), .A1(n1643), .B0(n1644), .Y(n1634) );
INVX2TS U1359 ( .A(n1641), .Y(n1633) );
NOR2X1TS U1360 ( .A(n1632), .B(n1643), .Y(n1635) );
OAI21XLTS U1361 ( .A0(n3006), .A1(n3005), .B0(n976), .Y(n3004) );
OAI21XLTS U1362 ( .A0(n2980), .A1(n2979), .B0(n976), .Y(n2978) );
INVX2TS U1363 ( .A(n985), .Y(n3229) );
OAI21XLTS U1364 ( .A0(n2949), .A1(n2948), .B0(n976), .Y(n2947) );
INVX2TS U1365 ( .A(n1065), .Y(n3368) );
INVX2TS U1366 ( .A(n1075), .Y(n3365) );
OAI21XLTS U1367 ( .A0(n2929), .A1(n2928), .B0(n976), .Y(n2927) );
INVX2TS U1368 ( .A(n1085), .Y(n3348) );
INVX2TS U1369 ( .A(n3498), .Y(n4080) );
INVX2TS U1370 ( .A(n3509), .Y(n4442) );
INVX2TS U1371 ( .A(n1110), .Y(n3355) );
INVX2TS U1372 ( .A(n3519), .Y(n4424) );
OAI21XLTS U1373 ( .A0(n4354), .A1(n4353), .B0(n4516), .Y(n4352) );
INVX2TS U1374 ( .A(n1120), .Y(n3172) );
OAI21XLTS U1375 ( .A0(n4384), .A1(n4383), .B0(n4516), .Y(n4382) );
INVX2TS U1376 ( .A(n1130), .Y(n3388) );
INVX2TS U1377 ( .A(n3544), .Y(n4629) );
INVX2TS U1378 ( .A(n1177), .Y(n3112) );
INVX2TS U1379 ( .A(n1156), .Y(n3280) );
OAI21XLTS U1380 ( .A0(n4496), .A1(n4495), .B0(n4516), .Y(n4494) );
OAI21XLTS U1381 ( .A0(n3598), .A1(n3597), .B0(n4510), .Y(n3596) );
OAI21XLTS U1382 ( .A0(n3610), .A1(n3609), .B0(n4510), .Y(n3608) );
XOR2X1TS U1383 ( .A(n1674), .B(n1673), .Y(n5192) );
XOR2X1TS U1384 ( .A(n1647), .B(n1646), .Y(n5175) );
AOI21X1TS U1385 ( .A0(n1658), .A1(n1642), .B0(n1641), .Y(n1647) );
XNOR2X1TS U1386 ( .A(n1556), .B(n1555), .Y(n5138) );
NAND2X1TS U1387 ( .A(n960), .B(n1554), .Y(n1555) );
XNOR2X1TS U1388 ( .A(n1540), .B(n1539), .Y(n5125) );
NOR2X4TS U1389 ( .A(n2832), .B(n982), .Y(n3395) );
OAI21XLTS U1390 ( .A0(n1128), .A1(n1127), .B0(n2981), .Y(n1126) );
OAI21XLTS U1391 ( .A0(n1198), .A1(n1197), .B0(n2981), .Y(n1196) );
OAI21XLTS U1392 ( .A0(n1203), .A1(n1054), .B0(n1053), .Y(n1055) );
OAI21XLTS U1393 ( .A0(n1063), .A1(n1062), .B0(n2981), .Y(n1061) );
OAI21XLTS U1394 ( .A0(n1073), .A1(n1072), .B0(n2981), .Y(n1071) );
OAI21XLTS U1395 ( .A0(n1083), .A1(n1082), .B0(n2981), .Y(n1081) );
OAI21XLTS U1396 ( .A0(n3507), .A1(n3506), .B0(n3659), .Y(n3505) );
OAI21XLTS U1397 ( .A0(n3517), .A1(n3516), .B0(n3659), .Y(n3515) );
OAI21XLTS U1398 ( .A0(n1118), .A1(n1117), .B0(n2981), .Y(n1116) );
OAI21XLTS U1399 ( .A0(n3542), .A1(n3541), .B0(n3659), .Y(n3540) );
OAI21XLTS U1400 ( .A0(n1172), .A1(n1171), .B0(n2981), .Y(n1170) );
OAI21XLTS U1401 ( .A0(n3552), .A1(n3551), .B0(n3659), .Y(n3550) );
OAI21XLTS U1402 ( .A0(n1188), .A1(n1187), .B0(n2981), .Y(n1186) );
OAI21XLTS U1403 ( .A0(n3572), .A1(n3571), .B0(n931), .Y(n3570) );
OAI21XLTS U1404 ( .A0(n3645), .A1(n3644), .B0(n3659), .Y(n3643) );
OAI21XLTS U1405 ( .A0(n3656), .A1(n3654), .B0(n3659), .Y(n3653) );
XNOR2X1TS U1406 ( .A(n1214), .B(n1213), .Y(Sgf_operation_ODD1_left_N51) );
NAND3XLTS U1407 ( .A(Op_MX[50]), .B(n2832), .C(Op_MX[51]), .Y(n1213) );
INVX2TS U1408 ( .A(n2088), .Y(n2002) );
INVX2TS U1409 ( .A(n2085), .Y(n2003) );
AOI21X1TS U1410 ( .A0(n2050), .A1(n956), .B0(n1989), .Y(n1990) );
OAI21X1TS U1411 ( .A0(n2042), .A1(n2044), .B0(n2045), .Y(n2050) );
OAI21X1TS U1412 ( .A0(n1737), .A1(n1765), .B0(n1738), .Y(n1743) );
NAND2X1TS U1413 ( .A(n2111), .B(n1961), .Y(n1963) );
NOR2X1TS U1414 ( .A(n2112), .B(n1963), .Y(n1965) );
INVX2TS U1415 ( .A(n1947), .Y(n2111) );
AOI21X1TS U1416 ( .A0(n2122), .A1(n1945), .B0(n1946), .Y(n1941) );
NOR2X1TS U1417 ( .A(n2085), .B(n2087), .Y(n2090) );
AOI21X1TS U1418 ( .A0(n2122), .A1(n2090), .B0(n2089), .Y(n2091) );
OAI21XLTS U1419 ( .A0(n2088), .A1(n2087), .B0(n2086), .Y(n2089) );
OAI21XLTS U1420 ( .A0(n3278), .A1(n3277), .B0(n3402), .Y(n3276) );
OAI21XLTS U1421 ( .A0(n2731), .A1(n2730), .B0(n3402), .Y(n2729) );
OAI21XLTS U1422 ( .A0(n3257), .A1(n3256), .B0(n3402), .Y(n3255) );
NOR2X1TS U1423 ( .A(n838), .B(n852), .Y(n2058) );
NAND2BXLTS U1424 ( .AN(n854), .B(Op_MY[26]), .Y(n2062) );
OAI21XLTS U1425 ( .A0(n4019), .A1(n4018), .B0(n4674), .Y(n4017) );
OAI21XLTS U1426 ( .A0(n4235), .A1(n4234), .B0(n4656), .Y(n4233) );
OAI21XLTS U1427 ( .A0(n4210), .A1(n4209), .B0(n4674), .Y(n4208) );
OAI21XLTS U1428 ( .A0(n4282), .A1(n4281), .B0(n4656), .Y(n4280) );
OAI21XLTS U1429 ( .A0(n4257), .A1(n4256), .B0(n4674), .Y(n4255) );
NAND2BXLTS U1430 ( .AN(n854), .B(n2389), .Y(n2151) );
OAI21XLTS U1431 ( .A0(n4665), .A1(n4755), .B0(Op_MX[26]), .Y(n4664) );
NAND2BXLTS U1432 ( .AN(n854), .B(n2420), .Y(n2177) );
OAI21X1TS U1433 ( .A0(n2125), .A1(n1991), .B0(n1990), .Y(n1994) );
NAND2X1TS U1434 ( .A(n2049), .B(n956), .Y(n1991) );
NOR2X1TS U1435 ( .A(n2043), .B(n2044), .Y(n2049) );
INVX2TS U1436 ( .A(n2050), .Y(n2051) );
INVX2TS U1437 ( .A(n1988), .Y(n2042) );
INVX2TS U1438 ( .A(n1987), .Y(n2043) );
AOI21X1TS U1439 ( .A0(n2030), .A1(n953), .B0(n2029), .Y(n2031) );
NAND2X1TS U1440 ( .A(Op_MX[32]), .B(n4913), .Y(n1746) );
OR2X1TS U1441 ( .A(Op_MX[32]), .B(n4913), .Y(n969) );
NOR2X1TS U1442 ( .A(n1737), .B(n1764), .Y(n1742) );
NAND2X1TS U1443 ( .A(Op_MX[34]), .B(Op_MX[7]), .Y(n2033) );
INVX2TS U1444 ( .A(n2023), .Y(n2029) );
OR2X1TS U1445 ( .A(Op_MX[34]), .B(Op_MX[7]), .Y(n795) );
AOI21X2TS U1446 ( .A0(n969), .A1(n1743), .B0(n1686), .Y(n2028) );
INVX2TS U1447 ( .A(n1746), .Y(n1686) );
NAND2X2TS U1448 ( .A(Op_MX[38]), .B(n4915), .Y(n2088) );
NAND2X1TS U1449 ( .A(n795), .B(n953), .Y(n1689) );
NAND2X1TS U1450 ( .A(n969), .B(n1742), .Y(n2026) );
NOR2X2TS U1451 ( .A(Op_MX[35]), .B(n4914), .Y(n2044) );
INVX2TS U1452 ( .A(n1945), .Y(n2112) );
INVX2TS U1453 ( .A(n1958), .Y(n2116) );
INVX2TS U1454 ( .A(n1946), .Y(n2118) );
NOR2X2TS U1455 ( .A(n1952), .B(n1968), .Y(n2115) );
NAND2X1TS U1456 ( .A(n2111), .B(n2115), .Y(n2119) );
AOI21X1TS U1457 ( .A0(n2122), .A1(n1965), .B0(n1964), .Y(n1966) );
OAI21XLTS U1458 ( .A0(n1963), .A1(n2118), .B0(n1962), .Y(n1964) );
AOI21X1TS U1459 ( .A0(n2116), .A1(n1961), .B0(n1960), .Y(n1962) );
NAND2X1TS U1460 ( .A(n1965), .B(n2113), .Y(n1967) );
INVX2TS U1461 ( .A(n1952), .Y(n1961) );
NOR2X1TS U1462 ( .A(n2112), .B(n1947), .Y(n1949) );
INVX2TS U1463 ( .A(n1996), .Y(n2113) );
AOI21X1TS U1464 ( .A0(n2122), .A1(n1949), .B0(n1948), .Y(n1950) );
OAI21XLTS U1465 ( .A0(n2118), .A1(n1947), .B0(n1958), .Y(n1948) );
OAI21XLTS U1466 ( .A0(Op_MY[43]), .A1(Op_MY[16]), .B0(Op_MY[15]), .Y(n1906)
);
OAI21XLTS U1467 ( .A0(n3327), .A1(n3325), .B0(n3402), .Y(n3324) );
OAI21X1TS U1468 ( .A0(n2125), .A1(n2092), .B0(n2091), .Y(n2095) );
NAND2X1TS U1469 ( .A(n2113), .B(n2090), .Y(n2092) );
OAI21XLTS U1470 ( .A0(n3186), .A1(n3185), .B0(n3402), .Y(n3184) );
OAI21XLTS U1471 ( .A0(n3312), .A1(n3311), .B0(n3391), .Y(n3310) );
OAI21XLTS U1472 ( .A0(n3305), .A1(n3304), .B0(n3391), .Y(n3303) );
OAI21XLTS U1473 ( .A0(n3087), .A1(n3086), .B0(n3363), .Y(n3085) );
XNOR2X1TS U1474 ( .A(n832), .B(n850), .Y(n2324) );
XNOR2X1TS U1475 ( .A(n830), .B(n850), .Y(n2323) );
NOR2XLTS U1476 ( .A(n813), .B(n853), .Y(n2057) );
OAI22X1TS U1477 ( .A0(n2325), .A1(n2334), .B0(n2324), .B1(n873), .Y(n2056)
);
OAI21XLTS U1478 ( .A0(n3078), .A1(n3077), .B0(n3363), .Y(n3076) );
OAI21XLTS U1479 ( .A0(n3987), .A1(n3986), .B0(n4656), .Y(n3985) );
XNOR2X1TS U1480 ( .A(n835), .B(n850), .Y(n2325) );
NOR2XLTS U1481 ( .A(n768), .B(n853), .Y(n2060) );
OAI21XLTS U1482 ( .A0(n3072), .A1(n3071), .B0(n968), .Y(n3070) );
OAI21XLTS U1483 ( .A0(n3266), .A1(n3265), .B0(n3402), .Y(n3264) );
XNOR2X1TS U1484 ( .A(n833), .B(n850), .Y(n2326) );
OAI21XLTS U1485 ( .A0(n4002), .A1(n4001), .B0(n4656), .Y(n4000) );
OAI21XLTS U1486 ( .A0(n4162), .A1(n4161), .B0(n4699), .Y(n4160) );
OAI21XLTS U1487 ( .A0(n3075), .A1(n3074), .B0(n968), .Y(n3073) );
OAI21XLTS U1488 ( .A0(n3244), .A1(n3243), .B0(n3402), .Y(n3242) );
XNOR2X1TS U1489 ( .A(n837), .B(n850), .Y(n2327) );
INVX2TS U1490 ( .A(n897), .Y(DP_OP_169J45_123_4229_n1180) );
XNOR2X1TS U1491 ( .A(n840), .B(n2301), .Y(n2297) );
OAI22X1TS U1492 ( .A0(n2063), .A1(n798), .B0(n2064), .B1(n863), .Y(n2072) );
OAI22X1TS U1493 ( .A0(n2062), .A1(n863), .B0(n798), .B1(n853), .Y(n2073) );
XNOR2X1TS U1494 ( .A(n836), .B(n2331), .Y(n2328) );
XNOR2X1TS U1495 ( .A(n814), .B(n2301), .Y(n2298) );
XNOR2X1TS U1496 ( .A(n840), .B(n850), .Y(n2330) );
XNOR2X1TS U1497 ( .A(n814), .B(n850), .Y(n2329) );
NAND2BXLTS U1498 ( .AN(n854), .B(n2301), .Y(n2096) );
OAI21XLTS U1499 ( .A0(n4012), .A1(n4011), .B0(n4656), .Y(n4010) );
OAI21XLTS U1500 ( .A0(n4165), .A1(n4164), .B0(n4699), .Y(n4163) );
OAI21XLTS U1501 ( .A0(n3069), .A1(n3068), .B0(n968), .Y(n3067) );
OAI21XLTS U1502 ( .A0(n3248), .A1(n3247), .B0(n3402), .Y(n3246) );
OAI21XLTS U1503 ( .A0(n3065), .A1(n3064), .B0(n968), .Y(n3063) );
XNOR2X1TS U1504 ( .A(n819), .B(n897), .Y(n2635) );
ADDHXLTS U1505 ( .A(n2130), .B(n2129), .CO(DP_OP_169J45_123_4229_n550), .S(
DP_OP_169J45_123_4229_n551) );
OAI22X1TS U1506 ( .A0(n2329), .A1(n2335), .B0(n812), .B1(n2131), .Y(n2130)
);
OAI21XLTS U1507 ( .A0(n3040), .A1(n3039), .B0(n968), .Y(n3038) );
XNOR2X1TS U1508 ( .A(n850), .B(n834), .Y(n2131) );
OAI21XLTS U1509 ( .A0(n4207), .A1(n4206), .B0(n959), .Y(n4205) );
ADDHXLTS U1510 ( .A(n2147), .B(DP_OP_169J45_123_4229_n598), .CO(
DP_OP_169J45_123_4229_n584), .S(DP_OP_169J45_123_4229_n585) );
OAI22X1TS U1511 ( .A0(n812), .A1(n849), .B0(n2146), .B1(n2335), .Y(n2147) );
NAND2BXLTS U1512 ( .AN(n854), .B(n2331), .Y(n2146) );
XNOR2X1TS U1513 ( .A(n2331), .B(n854), .Y(n2333) );
XNOR2X1TS U1514 ( .A(n2331), .B(n2299), .Y(n2332) );
OAI22X1TS U1515 ( .A0(n2362), .A1(n2365), .B0(n2366), .B1(n808), .Y(
DP_OP_169J45_123_4229_n906) );
OAI21XLTS U1516 ( .A0(n4213), .A1(n4212), .B0(n4726), .Y(n4211) );
OAI21XLTS U1517 ( .A0(n2736), .A1(n2735), .B0(n5334), .Y(n2734) );
ADDHXLTS U1518 ( .A(n2159), .B(n2158), .CO(DP_OP_169J45_123_4229_n615), .S(
n2157) );
OAI22X1TS U1519 ( .A0(n808), .A1(n2336), .B0(n2149), .B1(n2365), .Y(n2158)
);
OAI22X1TS U1520 ( .A0(n808), .A1(n2148), .B0(n2365), .B1(n2363), .Y(n2159)
);
NAND2BXLTS U1521 ( .AN(n854), .B(n2361), .Y(n2149) );
OAI21XLTS U1522 ( .A0(n4216), .A1(n4215), .B0(n4726), .Y(n4214) );
XNOR2X1TS U1523 ( .A(n2389), .B(n2299), .Y(n2153) );
ADDHXLTS U1524 ( .A(n2164), .B(n2163), .CO(n2161), .S(
DP_OP_169J45_123_4229_n644) );
OAI22X1TS U1525 ( .A0(n802), .A1(n2150), .B0(n2394), .B1(n2153), .Y(n2164)
);
OAI22X1TS U1526 ( .A0(n802), .A1(n2152), .B0(n2394), .B1(n2151), .Y(n2163)
);
OAI21XLTS U1527 ( .A0(n4225), .A1(n4224), .B0(n4726), .Y(n4223) );
OAI21XLTS U1528 ( .A0(n4685), .A1(n4684), .B0(n4682), .Y(n4683) );
XNOR2X1TS U1529 ( .A(n2420), .B(n2299), .Y(n2422) );
XNOR2X1TS U1530 ( .A(n834), .B(n2420), .Y(n2425) );
OAI21XLTS U1531 ( .A0(n4219), .A1(n4218), .B0(n959), .Y(n4217) );
OAI21XLTS U1532 ( .A0(n4668), .A1(n4667), .B0(n4674), .Y(n4666) );
CLKINVX6TS U1533 ( .A(n2485), .Y(n891) );
XNOR2X1TS U1534 ( .A(n814), .B(n2448), .Y(n2451) );
ADDHXLTS U1535 ( .A(n2187), .B(n2186), .CO(DP_OP_169J45_123_4229_n668), .S(
n2185) );
OAI22X1TS U1536 ( .A0(n809), .A1(n2176), .B0(n2424), .B1(n2422), .Y(n2187)
);
XNOR2X1TS U1537 ( .A(n834), .B(n2448), .Y(n2182) );
OAI21XLTS U1538 ( .A0(n4263), .A1(n4262), .B0(n4726), .Y(n4261) );
OAI21XLTS U1539 ( .A0(n4065), .A1(n4064), .B0(n4674), .Y(n4063) );
NAND2BXLTS U1540 ( .AN(n2660), .B(n2448), .Y(n2179) );
XNOR2X1TS U1541 ( .A(n2448), .B(n2299), .Y(n2181) );
CLKINVX6TS U1542 ( .A(n2514), .Y(n894) );
XOR2X1TS U1543 ( .A(Op_MY[41]), .B(Op_MY[14]), .Y(n1935) );
NAND2X2TS U1544 ( .A(n1932), .B(n1931), .Y(n2074) );
XOR2X1TS U1545 ( .A(Op_MY[39]), .B(Op_MY[12]), .Y(n2080) );
XNOR2X2TS U1546 ( .A(Op_MY[38]), .B(Op_MY[11]), .Y(n2076) );
OAI21XLTS U1547 ( .A0(n4327), .A1(n4326), .B0(n4699), .Y(n4325) );
XNOR2X1TS U1548 ( .A(n831), .B(n897), .Y(n2648) );
NAND2BXLTS U1549 ( .AN(n2660), .B(n2479), .Y(n2193) );
NAND2BXLTS U1550 ( .AN(n2660), .B(n2508), .Y(n2195) );
INVX2TS U1551 ( .A(n2508), .Y(n2485) );
XNOR2X1TS U1552 ( .A(n2508), .B(n839), .Y(n2197) );
OAI21XLTS U1553 ( .A0(n4703), .A1(n4701), .B0(n4699), .Y(n4700) );
NAND2X1TS U1554 ( .A(n1981), .B(n1980), .Y(n2100) );
OAI21XLTS U1555 ( .A0(Op_MY[35]), .A1(Op_MY[8]), .B0(Op_MY[7]), .Y(n1981) );
INVX2TS U1556 ( .A(n2539), .Y(n2514) );
OAI21XLTS U1557 ( .A0(n4755), .A1(n4708), .B0(n730), .Y(n4707) );
NAND2X2TS U1558 ( .A(n2022), .B(n2021), .Y(n2103) );
NAND2X1TS U1559 ( .A(n953), .B(n2023), .Y(n2024) );
OAI21X1TS U1560 ( .A0(n2125), .A1(n2026), .B0(n2028), .Y(n2025) );
NAND2X1TS U1561 ( .A(n1766), .B(n1765), .Y(n1767) );
XNOR2X1TS U1562 ( .A(Op_MX[10]), .B(Op_MX[9]), .Y(n4034) );
NAND2X1TS U1563 ( .A(n2006), .B(n928), .Y(n1698) );
NOR2X1TS U1564 ( .A(Op_MX[29]), .B(n731), .Y(n1757) );
NAND2X1TS U1565 ( .A(Op_MX[29]), .B(n731), .Y(n1758) );
OAI21X1TS U1566 ( .A0(n2028), .A1(n1689), .B0(n1688), .Y(n1988) );
AOI21X1TS U1567 ( .A0(n795), .A1(n2029), .B0(n1687), .Y(n1688) );
NAND2X1TS U1568 ( .A(n956), .B(n933), .Y(n1692) );
NAND2X1TS U1569 ( .A(Op_MX[35]), .B(n4914), .Y(n2045) );
OAI21X2TS U1570 ( .A0(n2088), .A1(n1698), .B0(n1697), .Y(n1946) );
AOI21X1TS U1571 ( .A0(n928), .A1(n1696), .B0(n1695), .Y(n1697) );
NAND2X1TS U1572 ( .A(n967), .B(n2115), .Y(n1701) );
NAND2X1TS U1573 ( .A(Op_MX[41]), .B(n763), .Y(n1958) );
NOR2X1TS U1574 ( .A(n2026), .B(n1689), .Y(n1987) );
NOR2X1TS U1575 ( .A(n2044), .B(n1692), .Y(n1694) );
NOR2X2TS U1576 ( .A(Op_MX[50]), .B(n729), .Y(n1885) );
NAND2X1TS U1577 ( .A(n1865), .B(n1864), .Y(n1896) );
OAI21XLTS U1578 ( .A0(Op_MY[49]), .A1(Op_MY[22]), .B0(Op_MY[21]), .Y(n1865)
);
INVX2TS U1579 ( .A(n1995), .Y(n2122) );
NOR2X1TS U1580 ( .A(n2112), .B(n2119), .Y(n2121) );
OAI21XLTS U1581 ( .A0(n2119), .A1(n2118), .B0(n2117), .Y(n2120) );
INVX4TS U1582 ( .A(n1736), .Y(n2125) );
OAI21X1TS U1583 ( .A0(n2125), .A1(n1967), .B0(n1966), .Y(n1972) );
NOR2X1TS U1584 ( .A(n774), .B(n852), .Y(n1957) );
NAND2X1TS U1585 ( .A(n2175), .B(n2174), .Y(n1907) );
XNOR2X2TS U1586 ( .A(Op_MY[50]), .B(Op_MY[23]), .Y(n1897) );
NAND2X1TS U1587 ( .A(n2132), .B(n2140), .Y(n1861) );
NOR2XLTS U1588 ( .A(n845), .B(Op_MY[21]), .Y(n1857) );
INVX6TS U1589 ( .A(n849), .Y(n850) );
XOR2X1TS U1590 ( .A(Op_MY[47]), .B(Op_MY[20]), .Y(n2138) );
NAND2X1TS U1591 ( .A(n2135), .B(n2134), .Y(n2136) );
CMPR42X1TS U1592 ( .A(DP_OP_169J45_123_4229_n1000), .B(
DP_OP_169J45_123_4229_n274), .C(DP_OP_169J45_123_4229_n782), .D(
DP_OP_169J45_123_4229_n804), .ICI(DP_OP_169J45_123_4229_n832), .S(
DP_OP_169J45_123_4229_n261), .ICO(DP_OP_169J45_123_4229_n259), .CO(
DP_OP_169J45_123_4229_n260) );
CLKAND2X2TS U1593 ( .A(n4005), .B(n4003), .Y(n4824) );
OAI21XLTS U1594 ( .A0(n3175), .A1(n3174), .B0(n3402), .Y(n3173) );
CMPR42X1TS U1595 ( .A(DP_OP_169J45_123_4229_n275), .B(
DP_OP_169J45_123_4229_n805), .C(DP_OP_169J45_123_4229_n1001), .D(
DP_OP_169J45_123_4229_n833), .ICI(DP_OP_169J45_123_4229_n285), .S(
DP_OP_169J45_123_4229_n273), .ICO(DP_OP_169J45_123_4229_n271), .CO(
DP_OP_169J45_123_4229_n272) );
CMPR42X1TS U1596 ( .A(DP_OP_169J45_123_4229_n861), .B(
DP_OP_169J45_123_4229_n288), .C(DP_OP_169J45_123_4229_n973), .D(
DP_OP_169J45_123_4229_n945), .ICI(DP_OP_169J45_123_4229_n282), .S(
DP_OP_169J45_123_4229_n270), .ICO(DP_OP_169J45_123_4229_n268), .CO(
DP_OP_169J45_123_4229_n269) );
OAI22X1TS U1597 ( .A0(n2318), .A1(n2334), .B0(n2317), .B1(n873), .Y(n2010)
);
CMPR42X1TS U1598 ( .A(DP_OP_169J45_123_4229_n1031), .B(
DP_OP_169J45_123_4229_n835), .C(DP_OP_169J45_123_4229_n318), .D(
DP_OP_169J45_123_4229_n891), .ICI(DP_OP_169J45_123_4229_n312), .S(
DP_OP_169J45_123_4229_n301), .ICO(DP_OP_169J45_123_4229_n299), .CO(
DP_OP_169J45_123_4229_n300) );
CMPR42X1TS U1599 ( .A(DP_OP_169J45_123_4229_n1060), .B(
DP_OP_169J45_123_4229_n336), .C(DP_OP_169J45_123_4229_n784), .D(
DP_OP_169J45_123_4229_n892), .ICI(DP_OP_169J45_123_4229_n808), .S(
DP_OP_169J45_123_4229_n320), .ICO(DP_OP_169J45_123_4229_n318), .CO(
DP_OP_169J45_123_4229_n319) );
CMPR42X1TS U1600 ( .A(DP_OP_169J45_123_4229_n864), .B(
DP_OP_169J45_123_4229_n836), .C(DP_OP_169J45_123_4229_n1032), .D(
DP_OP_169J45_123_4229_n920), .ICI(DP_OP_169J45_123_4229_n327), .S(
DP_OP_169J45_123_4229_n317), .ICO(DP_OP_169J45_123_4229_n315), .CO(
DP_OP_169J45_123_4229_n316) );
OAI21XLTS U1601 ( .A0(n3945), .A1(n3944), .B0(n4656), .Y(n3943) );
OAI21XLTS U1602 ( .A0(n3151), .A1(n3150), .B0(n3391), .Y(n3149) );
CMPR42X1TS U1603 ( .A(DP_OP_169J45_123_4229_n337), .B(
DP_OP_169J45_123_4229_n865), .C(DP_OP_169J45_123_4229_n809), .D(
DP_OP_169J45_123_4229_n1061), .ICI(DP_OP_169J45_123_4229_n350), .S(
DP_OP_169J45_123_4229_n335), .ICO(DP_OP_169J45_123_4229_n333), .CO(
DP_OP_169J45_123_4229_n334) );
CMPR42X1TS U1604 ( .A(DP_OP_169J45_123_4229_n893), .B(
DP_OP_169J45_123_4229_n837), .C(DP_OP_169J45_123_4229_n921), .D(
DP_OP_169J45_123_4229_n353), .ICI(DP_OP_169J45_123_4229_n344), .S(
DP_OP_169J45_123_4229_n332), .ICO(DP_OP_169J45_123_4229_n330), .CO(
DP_OP_169J45_123_4229_n331) );
CMPR42X1TS U1605 ( .A(DP_OP_169J45_123_4229_n894), .B(
DP_OP_169J45_123_4229_n810), .C(DP_OP_169J45_123_4229_n838), .D(
DP_OP_169J45_123_4229_n354), .ICI(DP_OP_169J45_123_4229_n364), .S(
DP_OP_169J45_123_4229_n352), .ICO(DP_OP_169J45_123_4229_n350), .CO(
DP_OP_169J45_123_4229_n351) );
CMPR42X1TS U1606 ( .A(DP_OP_169J45_123_4229_n866), .B(
DP_OP_169J45_123_4229_n922), .C(DP_OP_169J45_123_4229_n1062), .D(
DP_OP_169J45_123_4229_n950), .ICI(DP_OP_169J45_123_4229_n367), .S(
DP_OP_169J45_123_4229_n349), .ICO(DP_OP_169J45_123_4229_n347), .CO(
DP_OP_169J45_123_4229_n348) );
OAI22X1TS U1607 ( .A0(n2379), .A1(n2391), .B0(n2378), .B1(n865), .Y(n2040)
);
OAI21XLTS U1608 ( .A0(n3139), .A1(n3138), .B0(n3391), .Y(n3137) );
OAI21XLTS U1609 ( .A0(n3090), .A1(n3089), .B0(n3384), .Y(n3088) );
CMPR42X1TS U1610 ( .A(DP_OP_169J45_123_4229_n895), .B(
DP_OP_169J45_123_4229_n1091), .C(DP_OP_169J45_123_4229_n389), .D(
DP_OP_169J45_123_4229_n951), .ICI(DP_OP_169J45_123_4229_n380), .S(
DP_OP_169J45_123_4229_n369), .ICO(DP_OP_169J45_123_4229_n367), .CO(
DP_OP_169J45_123_4229_n368) );
CMPR42X1TS U1611 ( .A(DP_OP_169J45_123_4229_n811), .B(
DP_OP_169J45_123_4229_n839), .C(DP_OP_169J45_123_4229_n979), .D(
DP_OP_169J45_123_4229_n1063), .ICI(DP_OP_169J45_123_4229_n371), .S(
DP_OP_169J45_123_4229_n366), .ICO(DP_OP_169J45_123_4229_n364), .CO(
DP_OP_169J45_123_4229_n365) );
OAI22X1TS U1612 ( .A0(n2305), .A1(n2292), .B0(n2291), .B1(n868), .Y(
DP_OP_169J45_123_4229_n839) );
CMPR42X1TS U1613 ( .A(DP_OP_169J45_123_4229_n1120), .B(
DP_OP_169J45_123_4229_n410), .C(DP_OP_169J45_123_4229_n786), .D(
DP_OP_169J45_123_4229_n924), .ICI(DP_OP_169J45_123_4229_n952), .S(
DP_OP_169J45_123_4229_n391), .ICO(DP_OP_169J45_123_4229_n389), .CO(
DP_OP_169J45_123_4229_n390) );
OAI21XLTS U1614 ( .A0(n4132), .A1(n4131), .B0(n5451), .Y(n4130) );
OAI21XLTS U1615 ( .A0(n3009), .A1(n3008), .B0(n977), .Y(n3007) );
OAI21XLTS U1616 ( .A0(n3394), .A1(n3393), .B0(n3391), .Y(n3392) );
OAI21XLTS U1617 ( .A0(n3130), .A1(n3129), .B0(n3391), .Y(n3128) );
OAI21XLTS U1618 ( .A0(n3290), .A1(n3289), .B0(n977), .Y(n3288) );
CMPR42X1TS U1619 ( .A(DP_OP_169J45_123_4229_n868), .B(
DP_OP_169J45_123_4229_n812), .C(DP_OP_169J45_123_4229_n896), .D(
DP_OP_169J45_123_4229_n840), .ICI(DP_OP_169J45_123_4229_n401), .S(
DP_OP_169J45_123_4229_n388), .ICO(DP_OP_169J45_123_4229_n386), .CO(
DP_OP_169J45_123_4229_n387) );
OAI21XLTS U1620 ( .A0(n4129), .A1(n4128), .B0(n4674), .Y(n4127) );
CMPR42X1TS U1621 ( .A(DP_OP_169J45_123_4229_n411), .B(
DP_OP_169J45_123_4229_n869), .C(DP_OP_169J45_123_4229_n897), .D(
DP_OP_169J45_123_4229_n1121), .ICI(DP_OP_169J45_123_4229_n427), .S(
DP_OP_169J45_123_4229_n409), .ICO(DP_OP_169J45_123_4229_n407), .CO(
DP_OP_169J45_123_4229_n408) );
OAI22X1TS U1622 ( .A0(n2324), .A1(n2334), .B0(n2323), .B1(n873), .Y(
DP_OP_169J45_123_4229_n869) );
CMPR42X1TS U1623 ( .A(DP_OP_169J45_123_4229_n953), .B(
DP_OP_169J45_123_4229_n813), .C(DP_OP_169J45_123_4229_n841), .D(
DP_OP_169J45_123_4229_n981), .ICI(DP_OP_169J45_123_4229_n418), .S(
DP_OP_169J45_123_4229_n406), .ICO(DP_OP_169J45_123_4229_n404), .CO(
DP_OP_169J45_123_4229_n405) );
OAI22X1TS U1624 ( .A0(n2305), .A1(n2294), .B0(n2293), .B1(n868), .Y(
DP_OP_169J45_123_4229_n841) );
CMPR42X1TS U1625 ( .A(DP_OP_169J45_123_4229_n925), .B(
DP_OP_169J45_123_4229_n430), .C(DP_OP_169J45_123_4229_n1093), .D(
DP_OP_169J45_123_4229_n1065), .ICI(DP_OP_169J45_123_4229_n424), .S(
DP_OP_169J45_123_4229_n403), .ICO(DP_OP_169J45_123_4229_n401), .CO(
DP_OP_169J45_123_4229_n402) );
CMPR42X1TS U1626 ( .A(DP_OP_169J45_123_4229_n982), .B(
DP_OP_169J45_123_4229_n898), .C(DP_OP_169J45_123_4229_n842), .D(
DP_OP_169J45_123_4229_n1150), .ICI(DP_OP_169J45_123_4229_n441), .S(
DP_OP_169J45_123_4229_n429), .ICO(DP_OP_169J45_123_4229_n427), .CO(
DP_OP_169J45_123_4229_n428) );
AO21XLTS U1627 ( .A0(n861), .A1(n887), .B0(n2604), .Y(
DP_OP_169J45_123_4229_n1150) );
CMPR42X1TS U1628 ( .A(DP_OP_169J45_123_4229_n954), .B(
DP_OP_169J45_123_4229_n814), .C(DP_OP_169J45_123_4229_n926), .D(
DP_OP_169J45_123_4229_n450), .ICI(DP_OP_169J45_123_4229_n438), .S(
DP_OP_169J45_123_4229_n426), .ICO(DP_OP_169J45_123_4229_n424), .CO(
DP_OP_169J45_123_4229_n425) );
OAI21XLTS U1629 ( .A0(n3118), .A1(n3117), .B0(n3391), .Y(n3116) );
OAI21XLTS U1630 ( .A0(n3003), .A1(n3002), .B0(n977), .Y(n3001) );
CMPR42X1TS U1631 ( .A(DP_OP_169J45_123_4229_n983), .B(
DP_OP_169J45_123_4229_n1151), .C(DP_OP_169J45_123_4229_n843), .D(
DP_OP_169J45_123_4229_n1011), .ICI(DP_OP_169J45_123_4229_n463), .S(
DP_OP_169J45_123_4229_n449), .ICO(DP_OP_169J45_123_4229_n447), .CO(
DP_OP_169J45_123_4229_n448) );
CMPR42X1TS U1632 ( .A(DP_OP_169J45_123_4229_n899), .B(
DP_OP_169J45_123_4229_n955), .C(DP_OP_169J45_123_4229_n871), .D(
DP_OP_169J45_123_4229_n927), .ICI(DP_OP_169J45_123_4229_n460), .S(
DP_OP_169J45_123_4229_n446), .ICO(DP_OP_169J45_123_4229_n444), .CO(
DP_OP_169J45_123_4229_n445) );
OAI22X1TS U1633 ( .A0(n2326), .A1(n2334), .B0(n2325), .B1(n873), .Y(
DP_OP_169J45_123_4229_n871) );
CMPR42X1TS U1634 ( .A(DP_OP_169J45_123_4229_n472), .B(
DP_OP_169J45_123_4229_n1039), .C(DP_OP_169J45_123_4229_n451), .D(
DP_OP_169J45_123_4229_n469), .ICI(DP_OP_169J45_123_4229_n466), .S(
DP_OP_169J45_123_4229_n443), .ICO(DP_OP_169J45_123_4229_n441), .CO(
DP_OP_169J45_123_4229_n442) );
OAI21XLTS U1635 ( .A0(n3115), .A1(n3114), .B0(n3391), .Y(n3113) );
OAI21XLTS U1636 ( .A0(n3000), .A1(n2999), .B0(n977), .Y(n2998) );
CMPR42X1TS U1637 ( .A(DP_OP_169J45_123_4229_n984), .B(
DP_OP_169J45_123_4229_n928), .C(DP_OP_169J45_123_4229_n956), .D(
DP_OP_169J45_123_4229_n844), .ICI(DP_OP_169J45_123_4229_n484), .S(
DP_OP_169J45_123_4229_n468), .ICO(DP_OP_169J45_123_4229_n466), .CO(
DP_OP_169J45_123_4229_n467) );
CMPR42X1TS U1638 ( .A(DP_OP_169J45_123_4229_n1152), .B(
DP_OP_169J45_123_4229_n1124), .C(DP_OP_169J45_123_4229_n1068), .D(
DP_OP_169J45_123_4229_n487), .ICI(DP_OP_169J45_123_4229_n481), .S(
DP_OP_169J45_123_4229_n465), .ICO(DP_OP_169J45_123_4229_n463), .CO(
DP_OP_169J45_123_4229_n464) );
OAI21XLTS U1639 ( .A0(n4147), .A1(n4146), .B0(n4674), .Y(n4145) );
OAI21XLTS U1640 ( .A0(n3111), .A1(n3110), .B0(n3391), .Y(n3109) );
OAI21XLTS U1641 ( .A0(n2994), .A1(n2993), .B0(n3407), .Y(n2992) );
XNOR2X1TS U1642 ( .A(n815), .B(n897), .Y(n2633) );
XNOR2X1TS U1643 ( .A(n818), .B(n897), .Y(n2634) );
CMPR42X1TS U1644 ( .A(DP_OP_169J45_123_4229_n957), .B(
DP_OP_169J45_123_4229_n873), .C(DP_OP_169J45_123_4229_n901), .D(
DP_OP_169J45_123_4229_n1181), .ICI(DP_OP_169J45_123_4229_n504), .S(
DP_OP_169J45_123_4229_n489), .ICO(DP_OP_169J45_123_4229_n487), .CO(
DP_OP_169J45_123_4229_n488) );
OAI22X1TS U1645 ( .A0(n2328), .A1(n812), .B0(n2327), .B1(n873), .Y(
DP_OP_169J45_123_4229_n873) );
CMPR42X1TS U1646 ( .A(DP_OP_169J45_123_4229_n494), .B(
DP_OP_169J45_123_4229_n985), .C(DP_OP_169J45_123_4229_n845), .D(
DP_OP_169J45_123_4229_n1041), .ICI(DP_OP_169J45_123_4229_n510), .S(
DP_OP_169J45_123_4229_n492), .ICO(DP_OP_169J45_123_4229_n490), .CO(
DP_OP_169J45_123_4229_n491) );
OAI22X1TS U1647 ( .A0(n801), .A1(n2298), .B0(n2297), .B1(n2303), .Y(
DP_OP_169J45_123_4229_n845) );
CMPR42X1TS U1648 ( .A(DP_OP_169J45_123_4229_n1013), .B(
DP_OP_169J45_123_4229_n929), .C(DP_OP_169J45_123_4229_n1097), .D(
DP_OP_169J45_123_4229_n1153), .ICI(DP_OP_169J45_123_4229_n501), .S(
DP_OP_169J45_123_4229_n486), .ICO(DP_OP_169J45_123_4229_n484), .CO(
DP_OP_169J45_123_4229_n485) );
CMPR42X1TS U1649 ( .A(DP_OP_169J45_123_4229_n514), .B(
DP_OP_169J45_123_4229_n930), .C(DP_OP_169J45_123_4229_n1042), .D(
DP_OP_169J45_123_4229_n986), .ICI(DP_OP_169J45_123_4229_n874), .S(
DP_OP_169J45_123_4229_n512), .ICO(DP_OP_169J45_123_4229_n510), .CO(
DP_OP_169J45_123_4229_n511) );
OAI22X1TS U1650 ( .A0(n2330), .A1(n2334), .B0(n2328), .B1(n873), .Y(
DP_OP_169J45_123_4229_n874) );
CMPR42X1TS U1651 ( .A(DP_OP_169J45_123_4229_n958), .B(
DP_OP_169J45_123_4229_n902), .C(DP_OP_169J45_123_4229_n1014), .D(
DP_OP_169J45_123_4229_n846), .ICI(DP_OP_169J45_123_4229_n524), .S(
DP_OP_169J45_123_4229_n509), .ICO(DP_OP_169J45_123_4229_n507), .CO(
DP_OP_169J45_123_4229_n508) );
OAI22X1TS U1652 ( .A0(n2330), .A1(n2335), .B0(n2329), .B1(n812), .Y(
DP_OP_169J45_123_4229_n875) );
OAI22X1TS U1653 ( .A0(n801), .A1(n2273), .B0(n2303), .B1(n2096), .Y(n2097)
);
OAI22X1TS U1654 ( .A0(n2499), .A1(n2510), .B0(n2498), .B1(n872), .Y(n2098)
);
CMPR42X1TS U1655 ( .A(DP_OP_169J45_123_4229_n987), .B(
DP_OP_169J45_123_4229_n1015), .C(DP_OP_169J45_123_4229_n1071), .D(
DP_OP_169J45_123_4229_n550), .ICI(DP_OP_169J45_123_4229_n539), .S(
DP_OP_169J45_123_4229_n529), .ICO(DP_OP_169J45_123_4229_n527), .CO(
DP_OP_169J45_123_4229_n528) );
CMPR42X1TS U1656 ( .A(DP_OP_169J45_123_4229_n903), .B(
DP_OP_169J45_123_4229_n847), .C(DP_OP_169J45_123_4229_n1183), .D(
DP_OP_169J45_123_4229_n1155), .ICI(DP_OP_169J45_123_4229_n542), .S(
DP_OP_169J45_123_4229_n526), .ICO(DP_OP_169J45_123_4229_n524), .CO(
DP_OP_169J45_123_4229_n525) );
OAI21XLTS U1657 ( .A0(n3108), .A1(n3107), .B0(n3391), .Y(n3106) );
OAI21XLTS U1658 ( .A0(n2988), .A1(n2987), .B0(n3098), .Y(n2986) );
OAI21XLTS U1659 ( .A0(n3096), .A1(n3095), .B0(n3391), .Y(n3094) );
OAI21XLTS U1660 ( .A0(n2985), .A1(n2984), .B0(n3098), .Y(n2983) );
CMPR42X1TS U1661 ( .A(DP_OP_169J45_123_4229_n988), .B(
DP_OP_169J45_123_4229_n932), .C(DP_OP_169J45_123_4229_n1100), .D(
DP_OP_169J45_123_4229_n1184), .ICI(DP_OP_169J45_123_4229_n549), .S(
DP_OP_169J45_123_4229_n544), .ICO(DP_OP_169J45_123_4229_n542), .CO(
DP_OP_169J45_123_4229_n543) );
CMPR42X1TS U1662 ( .A(DP_OP_169J45_123_4229_n960), .B(
DP_OP_169J45_123_4229_n904), .C(DP_OP_169J45_123_4229_n848), .D(
DP_OP_169J45_123_4229_n551), .ICI(DP_OP_169J45_123_4229_n558), .S(
DP_OP_169J45_123_4229_n547), .ICO(DP_OP_169J45_123_4229_n545), .CO(
DP_OP_169J45_123_4229_n546) );
XNOR2X1TS U1663 ( .A(n821), .B(n895), .Y(n2609) );
OAI21XLTS U1664 ( .A0(n3052), .A1(n3051), .B0(n3391), .Y(n3050) );
OAI21XLTS U1665 ( .A0(n2977), .A1(n2976), .B0(n3098), .Y(n2975) );
XNOR2X1TS U1666 ( .A(n820), .B(n895), .Y(n2610) );
CMPR42X1TS U1667 ( .A(DP_OP_169J45_123_4229_n961), .B(
DP_OP_169J45_123_4229_n1045), .C(DP_OP_169J45_123_4229_n933), .D(
DP_OP_169J45_123_4229_n989), .ICI(DP_OP_169J45_123_4229_n578), .S(
DP_OP_169J45_123_4229_n563), .ICO(DP_OP_169J45_123_4229_n561), .CO(
DP_OP_169J45_123_4229_n562) );
CMPR42X1TS U1668 ( .A(DP_OP_169J45_123_4229_n1017), .B(
DP_OP_169J45_123_4229_n1073), .C(DP_OP_169J45_123_4229_n584), .D(
DP_OP_169J45_123_4229_n1101), .ICI(DP_OP_169J45_123_4229_n575), .S(
DP_OP_169J45_123_4229_n566), .ICO(DP_OP_169J45_123_4229_n564), .CO(
DP_OP_169J45_123_4229_n565) );
XNOR2X1TS U1669 ( .A(n816), .B(n897), .Y(n2636) );
NOR2BX1TS U1670 ( .AN(n854), .B(n2303), .Y(n2144) );
OAI22X1TS U1671 ( .A0(n812), .A1(n2332), .B0(n2131), .B1(n2335), .Y(n2145)
);
OAI21XLTS U1672 ( .A0(n4181), .A1(n4180), .B0(n4699), .Y(n4179) );
XNOR2X1TS U1673 ( .A(n821), .B(n897), .Y(n2637) );
XNOR2X1TS U1674 ( .A(n822), .B(n895), .Y(n2611) );
CMPR42X1TS U1675 ( .A(DP_OP_169J45_123_4229_n1074), .B(
DP_OP_169J45_123_4229_n934), .C(DP_OP_169J45_123_4229_n1102), .D(
DP_OP_169J45_123_4229_n585), .ICI(DP_OP_169J45_123_4229_n599), .S(
DP_OP_169J45_123_4229_n580), .ICO(DP_OP_169J45_123_4229_n578), .CO(
DP_OP_169J45_123_4229_n579) );
CMPR42X1TS U1676 ( .A(DP_OP_169J45_123_4229_n878), .B(
DP_OP_169J45_123_4229_n906), .C(DP_OP_169J45_123_4229_n962), .D(
DP_OP_169J45_123_4229_n990), .ICI(DP_OP_169J45_123_4229_n595), .S(
DP_OP_169J45_123_4229_n583), .ICO(DP_OP_169J45_123_4229_n581), .CO(
DP_OP_169J45_123_4229_n582) );
OAI22X1TS U1677 ( .A0(n2417), .A1(n2423), .B0(n2416), .B1(n866), .Y(
DP_OP_169J45_123_4229_n962) );
OAI22X1TS U1678 ( .A0(n812), .A1(n2333), .B0(n2332), .B1(n2335), .Y(
DP_OP_169J45_123_4229_n878) );
OAI21XLTS U1679 ( .A0(n4198), .A1(n4197), .B0(n4702), .Y(n4196) );
OAI21XLTS U1680 ( .A0(n2971), .A1(n2970), .B0(n3098), .Y(n2969) );
XNOR2X1TS U1681 ( .A(n820), .B(n897), .Y(n2638) );
XNOR2X1TS U1682 ( .A(n831), .B(n894), .Y(n2529) );
CMPR42X1TS U1683 ( .A(DP_OP_169J45_123_4229_n879), .B(
DP_OP_169J45_123_4229_n615), .C(DP_OP_169J45_123_4229_n907), .D(
DP_OP_169J45_123_4229_n935), .ICI(DP_OP_169J45_123_4229_n963), .S(
DP_OP_169J45_123_4229_n600), .ICO(DP_OP_169J45_123_4229_n598), .CO(
DP_OP_169J45_123_4229_n599) );
XNOR2X1TS U1684 ( .A(n826), .B(n895), .Y(n2612) );
CMPR42X1TS U1685 ( .A(DP_OP_169J45_123_4229_n1047), .B(
DP_OP_169J45_123_4229_n1103), .C(DP_OP_169J45_123_4229_n1019), .D(
DP_OP_169J45_123_4229_n1131), .ICI(DP_OP_169J45_123_4229_n607), .S(
DP_OP_169J45_123_4229_n597), .ICO(DP_OP_169J45_123_4229_n595), .CO(
DP_OP_169J45_123_4229_n596) );
XNOR2X1TS U1686 ( .A(n829), .B(n895), .Y(n2613) );
XOR2X1TS U1687 ( .A(n1937), .B(n2166), .Y(n1938) );
NOR2XLTS U1688 ( .A(n1936), .B(n1935), .Y(n1937) );
XNOR2X1TS U1689 ( .A(n822), .B(n897), .Y(n2639) );
XNOR2X1TS U1690 ( .A(n826), .B(n897), .Y(n2640) );
OAI22X1TS U1691 ( .A0(n2392), .A1(n2394), .B0(n2154), .B1(n802), .Y(n2156)
);
OAI21XLTS U1692 ( .A0(n2961), .A1(n2960), .B0(n3098), .Y(n2959) );
OAI21XLTS U1693 ( .A0(n4204), .A1(n4203), .B0(n4699), .Y(n4202) );
OAI21XLTS U1694 ( .A0(n4312), .A1(n4311), .B0(n4782), .Y(n4310) );
NOR2BX1TS U1695 ( .AN(n854), .B(n2365), .Y(n2162) );
XNOR2X1TS U1696 ( .A(n817), .B(n894), .Y(n2530) );
XNOR2X1TS U1697 ( .A(n840), .B(n2420), .Y(n2419) );
XNOR2X1TS U1698 ( .A(n830), .B(n891), .Y(n2503) );
NAND2X1TS U1699 ( .A(n2167), .B(n2166), .Y(n2168) );
NOR2XLTS U1700 ( .A(n847), .B(Op_MY[15]), .Y(n2165) );
XNOR2X1TS U1701 ( .A(n814), .B(n2420), .Y(n2421) );
XNOR2X1TS U1702 ( .A(n827), .B(n895), .Y(n2615) );
XNOR2X1TS U1703 ( .A(n832), .B(n891), .Y(n2504) );
XOR2X1TS U1704 ( .A(n2083), .B(n2082), .Y(n2084) );
NOR2XLTS U1705 ( .A(n2081), .B(n2080), .Y(n2083) );
XNOR2X1TS U1706 ( .A(n829), .B(n897), .Y(n2642) );
CMPR42X1TS U1707 ( .A(DP_OP_169J45_123_4229_n644), .B(
DP_OP_169J45_123_4229_n966), .C(DP_OP_169J45_123_4229_n654), .D(
DP_OP_169J45_123_4229_n994), .ICI(DP_OP_169J45_123_4229_n1078), .S(
DP_OP_169J45_123_4229_n642), .ICO(DP_OP_169J45_123_4229_n640), .CO(
DP_OP_169J45_123_4229_n641) );
OAI22X1TS U1708 ( .A0(n2421), .A1(n2424), .B0(n2425), .B1(n809), .Y(
DP_OP_169J45_123_4229_n966) );
OAI21XLTS U1709 ( .A0(n2752), .A1(n2751), .B0(n968), .Y(n2750) );
OAI21XLTS U1710 ( .A0(n4238), .A1(n4237), .B0(n4699), .Y(n4236) );
OAI21XLTS U1711 ( .A0(n4309), .A1(n4308), .B0(n4782), .Y(n4307) );
XNOR2X1TS U1712 ( .A(n837), .B(n889), .Y(n2476) );
XNOR2X1TS U1713 ( .A(n835), .B(n891), .Y(n2505) );
CMPR42X1TS U1714 ( .A(DP_OP_169J45_123_4229_n939), .B(
DP_OP_169J45_123_4229_n668), .C(DP_OP_169J45_123_4229_n967), .D(
DP_OP_169J45_123_4229_n995), .ICI(DP_OP_169J45_123_4229_n1107), .S(
DP_OP_169J45_123_4229_n656), .ICO(DP_OP_169J45_123_4229_n654), .CO(
DP_OP_169J45_123_4229_n655) );
NOR2BX1TS U1715 ( .AN(n854), .B(n2394), .Y(DP_OP_169J45_123_4229_n939) );
OAI22X1TS U1716 ( .A0(n2425), .A1(n2424), .B0(n809), .B1(n2422), .Y(
DP_OP_169J45_123_4229_n967) );
OAI22X1TS U1717 ( .A0(n2452), .A1(n2453), .B0(n2451), .B1(n803), .Y(
DP_OP_169J45_123_4229_n995) );
XNOR2X1TS U1718 ( .A(n824), .B(n895), .Y(n2616) );
XNOR2X1TS U1719 ( .A(n830), .B(n894), .Y(n2532) );
OAI21XLTS U1720 ( .A0(n2756), .A1(n2755), .B0(n968), .Y(n2754) );
OAI21XLTS U1721 ( .A0(n2958), .A1(n2957), .B0(n3098), .Y(n2956) );
OAI21XLTS U1722 ( .A0(n4285), .A1(n4284), .B0(n4699), .Y(n4283) );
OAI21XLTS U1723 ( .A0(n4306), .A1(n4305), .B0(n4782), .Y(n4304) );
XNOR2X1TS U1724 ( .A(n827), .B(n897), .Y(n2644) );
XNOR2X1TS U1725 ( .A(n823), .B(n895), .Y(n2617) );
XNOR2X1TS U1726 ( .A(n832), .B(n894), .Y(n2533) );
XNOR2X1TS U1727 ( .A(n824), .B(n897), .Y(n2645) );
NAND2X6TS U1728 ( .A(n1984), .B(n2513), .Y(n2510) );
XOR2X1TS U1729 ( .A(n1977), .B(n2076), .Y(n1984) );
NOR2XLTS U1730 ( .A(n1976), .B(n1979), .Y(n1977) );
XOR2XLTS U1731 ( .A(Op_MY[36]), .B(Op_MY[37]), .Y(n1976) );
XNOR2X1TS U1732 ( .A(n836), .B(n888), .Y(n2477) );
XNOR2X1TS U1733 ( .A(n833), .B(n891), .Y(n2506) );
OAI22X1TS U1734 ( .A0(n2451), .A1(n2453), .B0(n2182), .B1(n803), .Y(n2184)
);
NOR2BX1TS U1735 ( .AN(n854), .B(n2424), .Y(n2190) );
OAI22X1TS U1736 ( .A0(n2182), .A1(n2453), .B0(n803), .B1(n2181), .Y(n2188)
);
XNOR2X1TS U1737 ( .A(n825), .B(n895), .Y(n2618) );
XNOR2X1TS U1738 ( .A(n835), .B(n894), .Y(n2534) );
XNOR2X1TS U1739 ( .A(n831), .B(n895), .Y(n2619) );
XNOR2X1TS U1740 ( .A(n840), .B(n2479), .Y(n2478) );
XNOR2X1TS U1741 ( .A(n837), .B(n2508), .Y(n2507) );
XNOR2X1TS U1742 ( .A(n830), .B(n811), .Y(n2562) );
OAI21XLTS U1743 ( .A0(n2952), .A1(n2951), .B0(n3098), .Y(n2950) );
OAI21XLTS U1744 ( .A0(n4294), .A1(n4293), .B0(n4699), .Y(n4292) );
XNOR2X1TS U1745 ( .A(n823), .B(n897), .Y(n2646) );
XNOR2X1TS U1746 ( .A(n825), .B(n897), .Y(n2647) );
XNOR2X1TS U1747 ( .A(n832), .B(n811), .Y(n2563) );
XNOR2X1TS U1748 ( .A(n836), .B(n2508), .Y(n2509) );
OAI22X1TS U1749 ( .A0(n803), .A1(n2178), .B0(n2453), .B1(n2181), .Y(n2192)
);
OAI22X1TS U1750 ( .A0(n803), .A1(n2180), .B0(n2453), .B1(n2179), .Y(n2191)
);
XNOR2X1TS U1751 ( .A(n814), .B(n889), .Y(n2480) );
XNOR2X1TS U1752 ( .A(n833), .B(n894), .Y(n2535) );
OAI31X1TS U1753 ( .A0(n2761), .A1(Op_MX[44]), .A2(n3245), .B0(n2760), .Y(
n3105) );
OAI21XLTS U1754 ( .A0(n2770), .A1(n2769), .B0(n5335), .Y(n2768) );
OAI21XLTS U1755 ( .A0(n2946), .A1(n2945), .B0(n3098), .Y(n2944) );
XNOR2X1TS U1756 ( .A(n889), .B(n2299), .Y(n2481) );
XNOR2X1TS U1757 ( .A(n1935), .B(n1930), .Y(n1934) );
NOR2XLTS U1758 ( .A(Op_MY[40]), .B(Op_MY[13]), .Y(n1930) );
XNOR2X1TS U1759 ( .A(n840), .B(n2508), .Y(n2512) );
XNOR2X1TS U1760 ( .A(n834), .B(n888), .Y(n2484) );
XNOR2X1TS U1761 ( .A(n2080), .B(n2075), .Y(n2079) );
NAND2X1TS U1762 ( .A(n2077), .B(n2076), .Y(n2078) );
NOR2XLTS U1763 ( .A(Op_MY[38]), .B(Op_MY[11]), .Y(n2075) );
XNOR2X1TS U1764 ( .A(n837), .B(n2539), .Y(n2536) );
XNOR2X1TS U1765 ( .A(n835), .B(n811), .Y(n2564) );
XNOR2X1TS U1766 ( .A(n830), .B(n2598), .Y(n2590) );
OAI21XLTS U1767 ( .A0(n4288), .A1(n4287), .B0(n4726), .Y(n4286) );
OAI21XLTS U1768 ( .A0(n4318), .A1(n4317), .B0(n5452), .Y(n4316) );
XNOR2X1TS U1769 ( .A(n828), .B(n895), .Y(n2621) );
XNOR2X1TS U1770 ( .A(n836), .B(n2539), .Y(n2537) );
XNOR2X1TS U1771 ( .A(n832), .B(n2598), .Y(n2591) );
XNOR2X1TS U1772 ( .A(n814), .B(n2508), .Y(n2511) );
ADDHXLTS U1773 ( .A(n2203), .B(n2202), .CO(DP_OP_169J45_123_4229_n709), .S(
n2201) );
OAI22X1TS U1774 ( .A0(n807), .A1(n2194), .B0(n2483), .B1(n2481), .Y(n2202)
);
OAI22X1TS U1775 ( .A0(n807), .A1(n2454), .B0(n2483), .B1(n2193), .Y(n2203)
);
XNOR2X1TS U1776 ( .A(n834), .B(n2508), .Y(n2198) );
OAI21XLTS U1777 ( .A0(n4297), .A1(n4296), .B0(n4726), .Y(n4295) );
OAI21XLTS U1778 ( .A0(n4324), .A1(n4323), .B0(n4782), .Y(n4322) );
XNOR2X1TS U1779 ( .A(n2106), .B(n2101), .Y(n2105) );
NAND2X1TS U1780 ( .A(n2103), .B(n2102), .Y(n2104) );
NOR2XLTS U1781 ( .A(Op_MY[34]), .B(Op_MY[7]), .Y(n2101) );
XOR2X1TS U1782 ( .A(Op_MY[35]), .B(Op_MY[8]), .Y(n2106) );
XNOR2X2TS U1783 ( .A(Op_MY[36]), .B(Op_MY[9]), .Y(n2108) );
XNOR2X1TS U1784 ( .A(n817), .B(n897), .Y(n2649) );
XNOR2X1TS U1785 ( .A(n835), .B(n892), .Y(n2592) );
XNOR2X1TS U1786 ( .A(n830), .B(n895), .Y(n2622) );
NOR2BX1TS U1787 ( .AN(n2660), .B(n2483), .Y(n2206) );
OAI22X1TS U1788 ( .A0(n2198), .A1(n2513), .B0(n804), .B1(n2197), .Y(n2204)
);
CLKAND2X2TS U1789 ( .A(n2571), .B(n2020), .Y(n794) );
XOR2XLTS U1790 ( .A(n2019), .B(n2102), .Y(n2020) );
NOR2XLTS U1791 ( .A(n2018), .B(n2017), .Y(n2019) );
OAI22X1TS U1792 ( .A0(n804), .A1(n2196), .B0(n2513), .B1(n2197), .Y(n2207)
);
OAI22X1TS U1793 ( .A0(n804), .A1(n2485), .B0(n2513), .B1(n2195), .Y(n2208)
);
XNOR2X1TS U1794 ( .A(n833), .B(n893), .Y(n2593) );
XNOR2X1TS U1795 ( .A(n828), .B(n897), .Y(n2650) );
OAI21XLTS U1796 ( .A0(n4718), .A1(n4717), .B0(n4726), .Y(n4716) );
OAI21XLTS U1797 ( .A0(n4330), .A1(n4329), .B0(n4782), .Y(n4328) );
XNOR2X1TS U1798 ( .A(n834), .B(n2539), .Y(n2544) );
XNOR2X1TS U1799 ( .A(n2539), .B(n839), .Y(n2541) );
XNOR2X1TS U1800 ( .A(n830), .B(n897), .Y(n2651) );
NAND2X1TS U1801 ( .A(n2100), .B(n2108), .Y(n1982) );
NOR2XLTS U1802 ( .A(Op_MY[36]), .B(Op_MY[9]), .Y(n1978) );
OAI22X1TS U1803 ( .A0(n2570), .A1(n2571), .B0(n2569), .B1(n805), .Y(
DP_OP_169J45_123_4229_n1115) );
ADDHXLTS U1804 ( .A(n2219), .B(n2218), .CO(DP_OP_169J45_123_4229_n738), .S(
n2217) );
OAI22X1TS U1805 ( .A0(n2542), .A1(n2514), .B0(n874), .B1(n2209), .Y(n2219)
);
NAND2BXLTS U1806 ( .AN(n2660), .B(n2539), .Y(n2209) );
OAI21XLTS U1807 ( .A0(n4723), .A1(n4722), .B0(n4726), .Y(n4721) );
OAI21XLTS U1808 ( .A0(n4347), .A1(n4346), .B0(n4782), .Y(n4345) );
XNOR2X1TS U1809 ( .A(n834), .B(n811), .Y(n2214) );
OAI21XLTS U1810 ( .A0(n4729), .A1(n4728), .B0(n4726), .Y(n4727) );
OAI21XLTS U1811 ( .A0(n4390), .A1(n4389), .B0(n5452), .Y(n4388) );
CLKINVX6TS U1812 ( .A(n2604), .Y(n895) );
NAND2X6TS U1813 ( .A(n2602), .B(n1731), .Y(n2601) );
XOR2X1TS U1814 ( .A(n1730), .B(n2013), .Y(n1731) );
NOR2XLTS U1815 ( .A(n1729), .B(n1728), .Y(n1730) );
XOR2X1TS U1816 ( .A(Op_MY[33]), .B(Op_MY[6]), .Y(n2017) );
NAND2X2TS U1817 ( .A(n1733), .B(n1732), .Y(n2014) );
OAI21XLTS U1818 ( .A0(n4711), .A1(n4710), .B0(n4726), .Y(n4709) );
OAI21XLTS U1819 ( .A0(n4399), .A1(n4398), .B0(n4782), .Y(n4397) );
NAND2BXLTS U1820 ( .AN(n2660), .B(n893), .Y(n1734) );
OAI21XLTS U1821 ( .A0(n4403), .A1(n4402), .B0(n4744), .Y(n4401) );
OAI21XLTS U1822 ( .A0(n4755), .A1(n4076), .B0(DP_OP_169J45_123_4229_n2458),
.Y(n4075) );
NOR2X1TS U1823 ( .A(n4035), .B(n4036), .Y(n4032) );
CLKAND2X2TS U1824 ( .A(n4036), .B(n3747), .Y(n4830) );
NOR2X1TS U1825 ( .A(n4034), .B(n3747), .Y(n4033) );
NOR2X1TS U1826 ( .A(n3583), .B(n3582), .Y(n3587) );
NOR2X1TS U1827 ( .A(n3592), .B(n3581), .Y(n3588) );
CLKAND2X2TS U1828 ( .A(n3581), .B(n3582), .Y(n4838) );
XNOR2X1TS U1829 ( .A(Op_MX[4]), .B(Op_MX[3]), .Y(n3475) );
OAI21X2TS U1830 ( .A0(n1670), .A1(n1673), .B0(n1671), .Y(n1659) );
OR2X1TS U1831 ( .A(DP_OP_168J45_122_1342_n548), .B(
Sgf_operation_ODD1_Q_middle[1]), .Y(n1248) );
NOR2X2TS U1832 ( .A(n1251), .B(n1250), .Y(n1660) );
NOR2X2TS U1833 ( .A(n1257), .B(n1256), .Y(n1650) );
AOI21X2TS U1834 ( .A0(n1659), .A1(n1253), .B0(n1252), .Y(n1631) );
OAI21X1TS U1835 ( .A0(n1660), .A1(n1666), .B0(n1661), .Y(n1252) );
NOR2X2TS U1836 ( .A(n1259), .B(n1258), .Y(n1643) );
NOR2X2TS U1837 ( .A(n1261), .B(n1260), .Y(n1636) );
OAI21XLTS U1838 ( .A0(n1636), .A1(n1644), .B0(n1637), .Y(n1262) );
NOR2X1TS U1839 ( .A(n1267), .B(n1266), .Y(n1619) );
NOR2X2TS U1840 ( .A(n1269), .B(n1268), .Y(n1622) );
NOR2X1TS U1841 ( .A(n1271), .B(n1270), .Y(n1602) );
NOR2X1TS U1842 ( .A(n1277), .B(n1276), .Y(n1585) );
OAI21X2TS U1843 ( .A0(n1622), .A1(n1627), .B0(n1623), .Y(n1612) );
NOR2X2TS U1844 ( .A(n1273), .B(n1272), .Y(n1606) );
NOR2X2TS U1845 ( .A(n1619), .B(n1622), .Y(n1611) );
NOR2X1TS U1846 ( .A(n1602), .B(n1606), .Y(n1275) );
NOR2X2TS U1847 ( .A(n1279), .B(n1278), .Y(n1591) );
INVX2TS U1848 ( .A(n1596), .Y(n1588) );
OAI21X2TS U1849 ( .A0(n1591), .A1(n1598), .B0(n1592), .Y(n1576) );
NOR2X2TS U1850 ( .A(n1281), .B(n1280), .Y(n1580) );
NOR2X1TS U1851 ( .A(n1565), .B(n1580), .Y(n1568) );
NOR2X2TS U1852 ( .A(n1283), .B(n1282), .Y(n1571) );
NOR2X2TS U1853 ( .A(n1585), .B(n1591), .Y(n1577) );
NOR2X1TS U1854 ( .A(n1580), .B(n1571), .Y(n1285) );
AOI21X1TS U1855 ( .A0(n1576), .A1(n1285), .B0(n1284), .Y(n1286) );
OAI21XLTS U1856 ( .A0(n1571), .A1(n1581), .B0(n1572), .Y(n1284) );
NOR2X1TS U1857 ( .A(n1885), .B(n1883), .Y(n1716) );
NOR2X2TS U1858 ( .A(n2085), .B(n1698), .Y(n1945) );
NOR2X1TS U1859 ( .A(n1947), .B(n1701), .Y(n1703) );
OAI21X2TS U1860 ( .A0(n1757), .A1(n1685), .B0(n1758), .Y(n1736) );
AOI21X2TS U1861 ( .A0(n1988), .A1(n1694), .B0(n1693), .Y(n1995) );
OAI21X1TS U1862 ( .A0(n2045), .A1(n1692), .B0(n1691), .Y(n1693) );
AOI21X1TS U1863 ( .A0(n933), .A1(n1989), .B0(n1690), .Y(n1691) );
AOI21X1TS U1864 ( .A0(n1703), .A1(n1946), .B0(n1702), .Y(n1704) );
OAI21XLTS U1865 ( .A0(n1701), .A1(n1958), .B0(n1700), .Y(n1702) );
AOI21X1TS U1866 ( .A0(n967), .A1(n2114), .B0(n1699), .Y(n1700) );
NOR2X1TS U1867 ( .A(n1882), .B(n1885), .Y(n2227) );
XOR2X1TS U1868 ( .A(n1878), .B(n1877), .Y(n786) );
OAI21XLTS U1869 ( .A0(n2244), .A1(n1882), .B0(n1886), .Y(n1878) );
INVX2TS U1870 ( .A(n1885), .Y(n1876) );
NOR2X1TS U1871 ( .A(n780), .B(n853), .Y(n1881) );
NAND2X2TS U1872 ( .A(n1718), .B(n1717), .Y(n1891) );
XOR2X1TS U1873 ( .A(Op_MY[51]), .B(n4893), .Y(n1894) );
NAND2X1TS U1874 ( .A(n1897), .B(n1896), .Y(n1898) );
XNOR2X1TS U1875 ( .A(n1895), .B(n1894), .Y(n1899) );
NOR2XLTS U1876 ( .A(Op_MY[50]), .B(Op_MY[23]), .Y(n1895) );
CLKAND2X2TS U1877 ( .A(n932), .B(n863), .Y(n796) );
NOR2X1TS U1878 ( .A(n1917), .B(n853), .Y(n1927) );
OAI21X1TS U1879 ( .A0(n2125), .A1(n2124), .B0(n2123), .Y(n2128) );
AOI21X1TS U1880 ( .A0(n2122), .A1(n2121), .B0(n2120), .Y(n2123) );
NAND2X6TS U1881 ( .A(n2424), .B(n2173), .Y(n2423) );
XOR2X1TS U1882 ( .A(n2172), .B(n2174), .Y(n2173) );
NOR2XLTS U1883 ( .A(n2171), .B(n2170), .Y(n2172) );
XOR2X1TS U1884 ( .A(n1911), .B(n2135), .Y(n1912) );
NOR2XLTS U1885 ( .A(n1910), .B(n1909), .Y(n1911) );
XOR2X1TS U1886 ( .A(n1897), .B(n1856), .Y(n1863) );
NOR2XLTS U1887 ( .A(n1855), .B(n1858), .Y(n1856) );
XOR2X1TS U1888 ( .A(n2141), .B(n2140), .Y(n2142) );
NOR2XLTS U1889 ( .A(n2139), .B(n2138), .Y(n2141) );
CLKAND2X2TS U1890 ( .A(n3916), .B(n3914), .Y(n4806) );
CLKAND2X2TS U1891 ( .A(n3948), .B(n3946), .Y(n4812) );
CLKAND2X2TS U1892 ( .A(n3973), .B(n3971), .Y(n4818) );
CLKAND2X2TS U1893 ( .A(n992), .B(n3156), .Y(n3249) );
CLKAND2X2TS U1894 ( .A(n1001), .B(n1000), .Y(n3250) );
CLKAND2X2TS U1895 ( .A(n1007), .B(n2741), .Y(n2805) );
CLKAND2X2TS U1896 ( .A(n1009), .B(n1008), .Y(n2737) );
CLKAND2X2TS U1897 ( .A(n1016), .B(n1015), .Y(n2757) );
CLKAND2X2TS U1898 ( .A(n1014), .B(n2761), .Y(n2810) );
OAI21XLTS U1899 ( .A0(n3405), .A1(n3404), .B0(n3402), .Y(n3403) );
OAI21XLTS U1900 ( .A0(n3212), .A1(n3211), .B0(n3402), .Y(n3210) );
OAI21XLTS U1901 ( .A0(n2902), .A1(n2900), .B0(n2898), .Y(n2899) );
OAI21XLTS U1902 ( .A0(n2997), .A1(n2996), .B0(n976), .Y(n2995) );
OAI21XLTS U1903 ( .A0(n2853), .A1(n2852), .B0(n2898), .Y(n2851) );
INVX2TS U1904 ( .A(n1105), .Y(n3357) );
OAI21XLTS U1905 ( .A0(n2841), .A1(n2840), .B0(n2898), .Y(n2839) );
OAI21XLTS U1906 ( .A0(n3923), .A1(n3922), .B0(n4844), .Y(n3921) );
CLKAND2X2TS U1907 ( .A(n1020), .B(n1023), .Y(n2934) );
CMPR42X1TS U1908 ( .A(DP_OP_169J45_123_4229_n802), .B(
DP_OP_169J45_123_4229_n236), .C(DP_OP_169J45_123_4229_n942), .D(
DP_OP_169J45_123_4229_n830), .ICI(DP_OP_169J45_123_4229_n243), .S(
DP_OP_169J45_123_4229_n234), .ICO(DP_OP_169J45_123_4229_n232), .CO(
DP_OP_169J45_123_4229_n233) );
CMPR42X1TS U1909 ( .A(DP_OP_169J45_123_4229_n887), .B(
DP_OP_169J45_123_4229_n859), .C(DP_OP_169J45_123_4229_n247), .D(
DP_OP_169J45_123_4229_n256), .ICI(DP_OP_169J45_123_4229_n253), .S(
DP_OP_169J45_123_4229_n242), .ICO(DP_OP_169J45_123_4229_n240), .CO(
DP_OP_169J45_123_4229_n241) );
CMPR42X1TS U1910 ( .A(DP_OP_169J45_123_4229_n259), .B(
DP_OP_169J45_123_4229_n831), .C(DP_OP_169J45_123_4229_n943), .D(
DP_OP_169J45_123_4229_n915), .ICI(DP_OP_169J45_123_4229_n260), .S(
DP_OP_169J45_123_4229_n245), .ICO(DP_OP_169J45_123_4229_n243), .CO(
DP_OP_169J45_123_4229_n244) );
AOI2BB2XLTS U1911 ( .B0(n4824), .B1(n4846), .A0N(DP_OP_169J45_123_4229_n86),
.A1N(n4822), .Y(n4820) );
OAI21XLTS U1912 ( .A0(n3178), .A1(n3177), .B0(n3391), .Y(n3176) );
CMPR42X1TS U1913 ( .A(DP_OP_169J45_123_4229_n860), .B(
DP_OP_169J45_123_4229_n888), .C(DP_OP_169J45_123_4229_n268), .D(
DP_OP_169J45_123_4229_n272), .ICI(DP_OP_169J45_123_4229_n269), .S(
DP_OP_169J45_123_4229_n255), .ICO(DP_OP_169J45_123_4229_n253), .CO(
DP_OP_169J45_123_4229_n254) );
CMPR42X1TS U1914 ( .A(DP_OP_169J45_123_4229_n972), .B(
DP_OP_169J45_123_4229_n916), .C(DP_OP_169J45_123_4229_n944), .D(
DP_OP_169J45_123_4229_n271), .ICI(DP_OP_169J45_123_4229_n261), .S(
DP_OP_169J45_123_4229_n258), .ICO(DP_OP_169J45_123_4229_n256), .CO(
DP_OP_169J45_123_4229_n257) );
OAI21XLTS U1915 ( .A0(n4107), .A1(n4106), .B0(n4674), .Y(n4105) );
OAI21XLTS U1916 ( .A0(n3142), .A1(n3141), .B0(n968), .Y(n3140) );
CMPR42X1TS U1917 ( .A(DP_OP_169J45_123_4229_n1002), .B(
DP_OP_169J45_123_4229_n974), .C(DP_OP_169J45_123_4229_n946), .D(
DP_OP_169J45_123_4229_n302), .ICI(DP_OP_169J45_123_4229_n299), .S(
DP_OP_169J45_123_4229_n284), .ICO(DP_OP_169J45_123_4229_n282), .CO(
DP_OP_169J45_123_4229_n283) );
CMPR42X1TS U1918 ( .A(DP_OP_169J45_123_4229_n890), .B(
DP_OP_169J45_123_4229_n918), .C(DP_OP_169J45_123_4229_n300), .D(
DP_OP_169J45_123_4229_n287), .ICI(DP_OP_169J45_123_4229_n297), .S(
DP_OP_169J45_123_4229_n281), .ICO(DP_OP_169J45_123_4229_n279), .CO(
DP_OP_169J45_123_4229_n280) );
AOI2BB2XLTS U1919 ( .B0(n4830), .B1(n4846), .A0N(n853), .A1N(n4828), .Y(
n4826) );
CMPR42X1TS U1920 ( .A(DP_OP_169J45_123_4229_n947), .B(
DP_OP_169J45_123_4229_n315), .C(DP_OP_169J45_123_4229_n316), .D(
DP_OP_169J45_123_4229_n301), .ICI(DP_OP_169J45_123_4229_n313), .S(
DP_OP_169J45_123_4229_n295), .ICO(DP_OP_169J45_123_4229_n293), .CO(
DP_OP_169J45_123_4229_n294) );
CMPR42X1TS U1921 ( .A(DP_OP_169J45_123_4229_n1004), .B(
DP_OP_169J45_123_4229_n948), .C(DP_OP_169J45_123_4229_n333), .D(
DP_OP_169J45_123_4229_n330), .ICI(DP_OP_169J45_123_4229_n334), .S(
DP_OP_169J45_123_4229_n314), .ICO(DP_OP_169J45_123_4229_n312), .CO(
DP_OP_169J45_123_4229_n313) );
CMPR42X1TS U1922 ( .A(DP_OP_169J45_123_4229_n976), .B(
DP_OP_169J45_123_4229_n320), .C(DP_OP_169J45_123_4229_n331), .D(
DP_OP_169J45_123_4229_n317), .ICI(DP_OP_169J45_123_4229_n328), .S(
DP_OP_169J45_123_4229_n311), .ICO(DP_OP_169J45_123_4229_n309), .CO(
DP_OP_169J45_123_4229_n310) );
OAI21XLTS U1923 ( .A0(n2891), .A1(n3395), .B0(n2828), .Y(n2829) );
OAI21XLTS U1924 ( .A0(n3124), .A1(n3123), .B0(n968), .Y(n3122) );
CMPR42X1TS U1925 ( .A(DP_OP_169J45_123_4229_n351), .B(
DP_OP_169J45_123_4229_n335), .C(DP_OP_169J45_123_4229_n348), .D(
DP_OP_169J45_123_4229_n332), .ICI(DP_OP_169J45_123_4229_n341), .S(
DP_OP_169J45_123_4229_n326), .ICO(DP_OP_169J45_123_4229_n324), .CO(
DP_OP_169J45_123_4229_n325) );
CMPR42X1TS U1926 ( .A(DP_OP_169J45_123_4229_n368), .B(
DP_OP_169J45_123_4229_n352), .C(DP_OP_169J45_123_4229_n365), .D(
DP_OP_169J45_123_4229_n349), .ICI(DP_OP_169J45_123_4229_n358), .S(
DP_OP_169J45_123_4229_n343), .ICO(DP_OP_169J45_123_4229_n341), .CO(
DP_OP_169J45_123_4229_n342) );
CMPR42X1TS U1927 ( .A(DP_OP_169J45_123_4229_n1034), .B(
DP_OP_169J45_123_4229_n978), .C(DP_OP_169J45_123_4229_n1006), .D(
DP_OP_169J45_123_4229_n370), .ICI(DP_OP_169J45_123_4229_n361), .S(
DP_OP_169J45_123_4229_n346), .ICO(DP_OP_169J45_123_4229_n344), .CO(
DP_OP_169J45_123_4229_n345) );
OAI21XLTS U1928 ( .A0(n3121), .A1(n3120), .B0(n3318), .Y(n3119) );
CMPR42X1TS U1929 ( .A(DP_OP_169J45_123_4229_n387), .B(
DP_OP_169J45_123_4229_n369), .C(DP_OP_169J45_123_4229_n366), .D(
DP_OP_169J45_123_4229_n384), .ICI(DP_OP_169J45_123_4229_n381), .S(
DP_OP_169J45_123_4229_n360), .ICO(DP_OP_169J45_123_4229_n358), .CO(
DP_OP_169J45_123_4229_n359) );
CMPR42X1TS U1930 ( .A(DP_OP_169J45_123_4229_n1035), .B(
DP_OP_169J45_123_4229_n1007), .C(DP_OP_169J45_123_4229_n386), .D(
DP_OP_169J45_123_4229_n390), .ICI(DP_OP_169J45_123_4229_n383), .S(
DP_OP_169J45_123_4229_n363), .ICO(DP_OP_169J45_123_4229_n361), .CO(
DP_OP_169J45_123_4229_n362) );
OAI21XLTS U1931 ( .A0(n3062), .A1(n3061), .B0(n3384), .Y(n3060) );
CMPR42X1TS U1932 ( .A(DP_OP_169J45_123_4229_n1092), .B(
DP_OP_169J45_123_4229_n1036), .C(DP_OP_169J45_123_4229_n1064), .D(
DP_OP_169J45_123_4229_n408), .ICI(DP_OP_169J45_123_4229_n405), .S(
DP_OP_169J45_123_4229_n382), .ICO(DP_OP_169J45_123_4229_n380), .CO(
DP_OP_169J45_123_4229_n381) );
CMPR42X1TS U1933 ( .A(DP_OP_169J45_123_4229_n398), .B(
DP_OP_169J45_123_4229_n388), .C(DP_OP_169J45_123_4229_n402), .D(
DP_OP_169J45_123_4229_n385), .ICI(DP_OP_169J45_123_4229_n399), .S(
DP_OP_169J45_123_4229_n379), .ICO(DP_OP_169J45_123_4229_n377), .CO(
DP_OP_169J45_123_4229_n378) );
CMPR42X1TS U1934 ( .A(DP_OP_169J45_123_4229_n409), .B(
DP_OP_169J45_123_4229_n406), .C(DP_OP_169J45_123_4229_n422), .D(
DP_OP_169J45_123_4229_n403), .ICI(DP_OP_169J45_123_4229_n419), .S(
DP_OP_169J45_123_4229_n397), .ICO(DP_OP_169J45_123_4229_n395), .CO(
DP_OP_169J45_123_4229_n396) );
CMPR42X1TS U1935 ( .A(DP_OP_169J45_123_4229_n1010), .B(
DP_OP_169J45_123_4229_n1066), .C(DP_OP_169J45_123_4229_n1094), .D(
DP_OP_169J45_123_4229_n448), .ICI(DP_OP_169J45_123_4229_n445), .S(
DP_OP_169J45_123_4229_n420), .ICO(DP_OP_169J45_123_4229_n418), .CO(
DP_OP_169J45_123_4229_n419) );
CMPR42X1TS U1936 ( .A(DP_OP_169J45_123_4229_n429), .B(
DP_OP_169J45_123_4229_n426), .C(DP_OP_169J45_123_4229_n442), .D(
DP_OP_169J45_123_4229_n423), .ICI(DP_OP_169J45_123_4229_n439), .S(
DP_OP_169J45_123_4229_n417), .ICO(DP_OP_169J45_123_4229_n415), .CO(
DP_OP_169J45_123_4229_n416) );
OAI21XLTS U1937 ( .A0(n3049), .A1(n3048), .B0(n3384), .Y(n3047) );
OAI21XLTS U1938 ( .A0(n2894), .A1(n2893), .B0(n2898), .Y(n2892) );
CMPR42X1TS U1939 ( .A(DP_OP_169J45_123_4229_n1123), .B(
DP_OP_169J45_123_4229_n1067), .C(DP_OP_169J45_123_4229_n1095), .D(
DP_OP_169J45_123_4229_n470), .ICI(DP_OP_169J45_123_4229_n467), .S(
DP_OP_169J45_123_4229_n440), .ICO(DP_OP_169J45_123_4229_n438), .CO(
DP_OP_169J45_123_4229_n439) );
CMPR42X1TS U1940 ( .A(DP_OP_169J45_123_4229_n446), .B(
DP_OP_169J45_123_4229_n449), .C(DP_OP_169J45_123_4229_n464), .D(
DP_OP_169J45_123_4229_n443), .ICI(DP_OP_169J45_123_4229_n461), .S(
DP_OP_169J45_123_4229_n437), .ICO(DP_OP_169J45_123_4229_n435), .CO(
DP_OP_169J45_123_4229_n436) );
OAI21XLTS U1941 ( .A0(n3046), .A1(n3045), .B0(n3384), .Y(n3044) );
CMPR42X1TS U1942 ( .A(DP_OP_169J45_123_4229_n1040), .B(
DP_OP_169J45_123_4229_n473), .C(DP_OP_169J45_123_4229_n1096), .D(
DP_OP_169J45_123_4229_n491), .ICI(DP_OP_169J45_123_4229_n488), .S(
DP_OP_169J45_123_4229_n462), .ICO(DP_OP_169J45_123_4229_n460), .CO(
DP_OP_169J45_123_4229_n461) );
CMPR42X1TS U1943 ( .A(DP_OP_169J45_123_4229_n471), .B(
DP_OP_169J45_123_4229_n468), .C(DP_OP_169J45_123_4229_n485), .D(
DP_OP_169J45_123_4229_n465), .ICI(DP_OP_169J45_123_4229_n482), .S(
DP_OP_169J45_123_4229_n459), .ICO(DP_OP_169J45_123_4229_n457), .CO(
DP_OP_169J45_123_4229_n458) );
OAI21XLTS U1944 ( .A0(n3043), .A1(n3042), .B0(n3384), .Y(n3041) );
OAI21XLTS U1945 ( .A0(n2883), .A1(n2882), .B0(n2898), .Y(n2881) );
CMPR42X1TS U1946 ( .A(DP_OP_169J45_123_4229_n1182), .B(
DP_OP_169J45_123_4229_n1126), .C(DP_OP_169J45_123_4229_n1154), .D(
DP_OP_169J45_123_4229_n521), .ICI(DP_OP_169J45_123_4229_n528), .S(
DP_OP_169J45_123_4229_n503), .ICO(DP_OP_169J45_123_4229_n501), .CO(
DP_OP_169J45_123_4229_n502) );
CMPR42X1TS U1947 ( .A(DP_OP_169J45_123_4229_n492), .B(
DP_OP_169J45_123_4229_n489), .C(DP_OP_169J45_123_4229_n486), .D(
DP_OP_169J45_123_4229_n505), .ICI(DP_OP_169J45_123_4229_n498), .S(
DP_OP_169J45_123_4229_n480), .ICO(DP_OP_169J45_123_4229_n478), .CO(
DP_OP_169J45_123_4229_n479) );
CMPR42X1TS U1948 ( .A(DP_OP_169J45_123_4229_n1070), .B(
DP_OP_169J45_123_4229_n1098), .C(DP_OP_169J45_123_4229_n530), .D(
DP_OP_169J45_123_4229_n527), .ICI(DP_OP_169J45_123_4229_n531), .S(
DP_OP_169J45_123_4229_n506), .ICO(DP_OP_169J45_123_4229_n504), .CO(
DP_OP_169J45_123_4229_n505) );
CMPR42X1TS U1949 ( .A(DP_OP_169J45_123_4229_n512), .B(
DP_OP_169J45_123_4229_n509), .C(DP_OP_169J45_123_4229_n525), .D(
DP_OP_169J45_123_4229_n522), .ICI(DP_OP_169J45_123_4229_n503), .S(
DP_OP_169J45_123_4229_n500), .ICO(DP_OP_169J45_123_4229_n498), .CO(
DP_OP_169J45_123_4229_n499) );
CMPR42X1TS U1950 ( .A(DP_OP_169J45_123_4229_n546), .B(
DP_OP_169J45_123_4229_n543), .C(DP_OP_169J45_123_4229_n529), .D(
DP_OP_169J45_123_4229_n526), .ICI(DP_OP_169J45_123_4229_n536), .S(
DP_OP_169J45_123_4229_n520), .ICO(DP_OP_169J45_123_4229_n518), .CO(
DP_OP_169J45_123_4229_n519) );
OAI21XLTS U1951 ( .A0(n3037), .A1(n3036), .B0(n3384), .Y(n3035) );
OAI21XLTS U1952 ( .A0(n2880), .A1(n2879), .B0(n2898), .Y(n2878) );
OAI21XLTS U1953 ( .A0(n2877), .A1(n2876), .B0(n2898), .Y(n2875) );
CMPR42X1TS U1954 ( .A(DP_OP_169J45_123_4229_n565), .B(
DP_OP_169J45_123_4229_n562), .C(DP_OP_169J45_123_4229_n547), .D(
DP_OP_169J45_123_4229_n544), .ICI(DP_OP_169J45_123_4229_n555), .S(
DP_OP_169J45_123_4229_n538), .ICO(DP_OP_169J45_123_4229_n536), .CO(
DP_OP_169J45_123_4229_n537) );
CMPR42X1TS U1955 ( .A(DP_OP_169J45_123_4229_n1156), .B(
DP_OP_169J45_123_4229_n1128), .C(DP_OP_169J45_123_4229_n567), .D(
DP_OP_169J45_123_4229_n561), .ICI(DP_OP_169J45_123_4229_n564), .S(
DP_OP_169J45_123_4229_n541), .ICO(DP_OP_169J45_123_4229_n539), .CO(
DP_OP_169J45_123_4229_n540) );
OAI21XLTS U1956 ( .A0(n2874), .A1(n2873), .B0(n2898), .Y(n2872) );
CMPR42X1TS U1957 ( .A(DP_OP_169J45_123_4229_n1157), .B(
DP_OP_169J45_123_4229_n579), .C(DP_OP_169J45_123_4229_n576), .D(
DP_OP_169J45_123_4229_n563), .ICI(DP_OP_169J45_123_4229_n566), .S(
DP_OP_169J45_123_4229_n557), .ICO(DP_OP_169J45_123_4229_n555), .CO(
DP_OP_169J45_123_4229_n556) );
CMPR42X1TS U1958 ( .A(DP_OP_169J45_123_4229_n1185), .B(
DP_OP_169J45_123_4229_n1129), .C(DP_OP_169J45_123_4229_n568), .D(
DP_OP_169J45_123_4229_n581), .ICI(DP_OP_169J45_123_4229_n582), .S(
DP_OP_169J45_123_4229_n560), .ICO(DP_OP_169J45_123_4229_n558), .CO(
DP_OP_169J45_123_4229_n559) );
CMPR42X1TS U1959 ( .A(DP_OP_169J45_123_4229_n1046), .B(
DP_OP_169J45_123_4229_n1018), .C(DP_OP_169J45_123_4229_n1130), .D(
DP_OP_169J45_123_4229_n1186), .ICI(DP_OP_169J45_123_4229_n592), .S(
DP_OP_169J45_123_4229_n577), .ICO(DP_OP_169J45_123_4229_n575), .CO(
DP_OP_169J45_123_4229_n576) );
OAI22X1TS U1960 ( .A0(n2472), .A1(n2482), .B0(n2471), .B1(n870), .Y(
DP_OP_169J45_123_4229_n1018) );
CMPR42X1TS U1961 ( .A(DP_OP_169J45_123_4229_n1158), .B(
DP_OP_169J45_123_4229_n583), .C(DP_OP_169J45_123_4229_n596), .D(
DP_OP_169J45_123_4229_n593), .ICI(DP_OP_169J45_123_4229_n580), .S(
DP_OP_169J45_123_4229_n574), .ICO(DP_OP_169J45_123_4229_n572), .CO(
DP_OP_169J45_123_4229_n573) );
OAI21XLTS U1962 ( .A0(n2871), .A1(n2870), .B0(n2898), .Y(n2869) );
CMPR42X1TS U1963 ( .A(DP_OP_169J45_123_4229_n991), .B(
DP_OP_169J45_123_4229_n1075), .C(DP_OP_169J45_123_4229_n613), .D(
DP_OP_169J45_123_4229_n1187), .ICI(DP_OP_169J45_123_4229_n610), .S(
DP_OP_169J45_123_4229_n594), .ICO(DP_OP_169J45_123_4229_n592), .CO(
DP_OP_169J45_123_4229_n593) );
OAI22X1TS U1964 ( .A0(n2446), .A1(n2450), .B0(n2445), .B1(n867), .Y(
DP_OP_169J45_123_4229_n991) );
CMPR42X1TS U1965 ( .A(DP_OP_169J45_123_4229_n1159), .B(
DP_OP_169J45_123_4229_n600), .C(DP_OP_169J45_123_4229_n611), .D(
DP_OP_169J45_123_4229_n608), .ICI(DP_OP_169J45_123_4229_n597), .S(
DP_OP_169J45_123_4229_n591), .ICO(DP_OP_169J45_123_4229_n589), .CO(
DP_OP_169J45_123_4229_n590) );
CMPR42X1TS U1966 ( .A(DP_OP_169J45_123_4229_n1076), .B(
DP_OP_169J45_123_4229_n1132), .C(DP_OP_169J45_123_4229_n992), .D(
DP_OP_169J45_123_4229_n1160), .ICI(DP_OP_169J45_123_4229_n623), .S(
DP_OP_169J45_123_4229_n609), .ICO(DP_OP_169J45_123_4229_n607), .CO(
DP_OP_169J45_123_4229_n608) );
OAI22X1TS U1967 ( .A0(n2584), .A1(n2601), .B0(n2583), .B1(n871), .Y(
DP_OP_169J45_123_4229_n1132) );
CMPR42X1TS U1968 ( .A(DP_OP_169J45_123_4229_n1048), .B(
DP_OP_169J45_123_4229_n964), .C(DP_OP_169J45_123_4229_n1020), .D(
DP_OP_169J45_123_4229_n1104), .ICI(DP_OP_169J45_123_4229_n626), .S(
DP_OP_169J45_123_4229_n612), .ICO(DP_OP_169J45_123_4229_n610), .CO(
DP_OP_169J45_123_4229_n611) );
OAI22X1TS U1969 ( .A0(n2419), .A1(n809), .B0(n2418), .B1(n866), .Y(
DP_OP_169J45_123_4229_n964) );
OAI22X1TS U1970 ( .A0(n2503), .A1(n2510), .B0(n2502), .B1(n872), .Y(
DP_OP_169J45_123_4229_n1048) );
CMPR42X1TS U1971 ( .A(DP_OP_169J45_123_4229_n614), .B(
DP_OP_169J45_123_4229_n1188), .C(DP_OP_169J45_123_4229_n627), .D(
DP_OP_169J45_123_4229_n624), .ICI(DP_OP_169J45_123_4229_n620), .S(
DP_OP_169J45_123_4229_n606), .ICO(DP_OP_169J45_123_4229_n604), .CO(
DP_OP_169J45_123_4229_n605) );
INVX2TS U1972 ( .A(n3487), .Y(n4068) );
CMPR42X1TS U1973 ( .A(DP_OP_169J45_123_4229_n630), .B(
DP_OP_169J45_123_4229_n1105), .C(DP_OP_169J45_123_4229_n1077), .D(
DP_OP_169J45_123_4229_n1161), .ICI(DP_OP_169J45_123_4229_n637), .S(
DP_OP_169J45_123_4229_n628), .ICO(DP_OP_169J45_123_4229_n626), .CO(
DP_OP_169J45_123_4229_n627) );
OAI22X1TS U1974 ( .A0(n2559), .A1(n806), .B0(n2558), .B1(n869), .Y(
DP_OP_169J45_123_4229_n1105) );
CMPR42X1TS U1975 ( .A(DP_OP_169J45_123_4229_n965), .B(
DP_OP_169J45_123_4229_n993), .C(DP_OP_169J45_123_4229_n1049), .D(
DP_OP_169J45_123_4229_n1133), .ICI(DP_OP_169J45_123_4229_n1189), .S(
DP_OP_169J45_123_4229_n625), .ICO(DP_OP_169J45_123_4229_n623), .CO(
DP_OP_169J45_123_4229_n624) );
OAI22X1TS U1976 ( .A0(n2504), .A1(n2510), .B0(n2503), .B1(n872), .Y(
DP_OP_169J45_123_4229_n1049) );
OAI22X1TS U1977 ( .A0(n2419), .A1(n2424), .B0(n2421), .B1(n809), .Y(
DP_OP_169J45_123_4229_n965) );
CMPR42X1TS U1978 ( .A(DP_OP_169J45_123_4229_n1021), .B(
DP_OP_169J45_123_4229_n640), .C(DP_OP_169J45_123_4229_n634), .D(
DP_OP_169J45_123_4229_n641), .ICI(DP_OP_169J45_123_4229_n638), .S(
DP_OP_169J45_123_4229_n622), .ICO(DP_OP_169J45_123_4229_n620), .CO(
DP_OP_169J45_123_4229_n621) );
CMPR42X1TS U1979 ( .A(DP_OP_169J45_123_4229_n1106), .B(
DP_OP_169J45_123_4229_n1050), .C(DP_OP_169J45_123_4229_n1022), .D(
DP_OP_169J45_123_4229_n1162), .ICI(DP_OP_169J45_123_4229_n655), .S(
DP_OP_169J45_123_4229_n639), .ICO(DP_OP_169J45_123_4229_n637), .CO(
DP_OP_169J45_123_4229_n638) );
OAI22X1TS U1980 ( .A0(n2505), .A1(n2510), .B0(n2504), .B1(n872), .Y(
DP_OP_169J45_123_4229_n1050) );
OAI22X1TS U1981 ( .A0(n2476), .A1(n2482), .B0(n2475), .B1(n870), .Y(
DP_OP_169J45_123_4229_n1022) );
CMPR42X1TS U1982 ( .A(DP_OP_169J45_123_4229_n1134), .B(
DP_OP_169J45_123_4229_n1190), .C(DP_OP_169J45_123_4229_n651), .D(
DP_OP_169J45_123_4229_n648), .ICI(DP_OP_169J45_123_4229_n642), .S(
DP_OP_169J45_123_4229_n636), .ICO(DP_OP_169J45_123_4229_n634), .CO(
DP_OP_169J45_123_4229_n635) );
OAI22X1TS U1983 ( .A0(n2586), .A1(n2601), .B0(n2585), .B1(n871), .Y(
DP_OP_169J45_123_4229_n1134) );
OAI21XLTS U1984 ( .A0(n3025), .A1(n3024), .B0(n3384), .Y(n3023) );
OAI21XLTS U1985 ( .A0(n2865), .A1(n2864), .B0(n2898), .Y(n2863) );
OAI21XLTS U1986 ( .A0(n4244), .A1(n4243), .B0(n4744), .Y(n4242) );
OAI21XLTS U1987 ( .A0(n4447), .A1(n4446), .B0(n4510), .Y(n4445) );
CMPR42X1TS U1988 ( .A(DP_OP_169J45_123_4229_n1023), .B(
DP_OP_169J45_123_4229_n1051), .C(DP_OP_169J45_123_4229_n666), .D(
DP_OP_169J45_123_4229_n663), .ICI(DP_OP_169J45_123_4229_n656), .S(
DP_OP_169J45_123_4229_n650), .ICO(DP_OP_169J45_123_4229_n648), .CO(
DP_OP_169J45_123_4229_n649) );
OAI22X1TS U1989 ( .A0(n2506), .A1(n2510), .B0(n2505), .B1(n872), .Y(
DP_OP_169J45_123_4229_n1051) );
OAI22X1TS U1990 ( .A0(n2477), .A1(n807), .B0(n2476), .B1(n870), .Y(
DP_OP_169J45_123_4229_n1023) );
CMPR42X1TS U1991 ( .A(DP_OP_169J45_123_4229_n1079), .B(
DP_OP_169J45_123_4229_n1135), .C(DP_OP_169J45_123_4229_n1163), .D(
DP_OP_169J45_123_4229_n1191), .ICI(DP_OP_169J45_123_4229_n660), .S(
DP_OP_169J45_123_4229_n653), .ICO(DP_OP_169J45_123_4229_n651), .CO(
DP_OP_169J45_123_4229_n652) );
OAI21XLTS U1992 ( .A0(n3022), .A1(n3021), .B0(n3384), .Y(n3020) );
INVX2TS U1993 ( .A(n1090), .Y(n3341) );
OAI21XLTS U1994 ( .A0(n4432), .A1(n4431), .B0(n4510), .Y(n4430) );
CMPR42X1TS U1995 ( .A(DP_OP_169J45_123_4229_n1080), .B(
DP_OP_169J45_123_4229_n1192), .C(DP_OP_169J45_123_4229_n1136), .D(
DP_OP_169J45_123_4229_n1164), .ICI(DP_OP_169J45_123_4229_n676), .S(
DP_OP_169J45_123_4229_n665), .ICO(DP_OP_169J45_123_4229_n663), .CO(
DP_OP_169J45_123_4229_n664) );
CMPR42X1TS U1996 ( .A(DP_OP_169J45_123_4229_n1024), .B(
DP_OP_169J45_123_4229_n1108), .C(DP_OP_169J45_123_4229_n1052), .D(
DP_OP_169J45_123_4229_n667), .ICI(DP_OP_169J45_123_4229_n673), .S(
DP_OP_169J45_123_4229_n662), .ICO(DP_OP_169J45_123_4229_n660), .CO(
DP_OP_169J45_123_4229_n661) );
OAI22X1TS U1997 ( .A0(n2507), .A1(n2510), .B0(n2506), .B1(n872), .Y(
DP_OP_169J45_123_4229_n1052) );
OAI22X1TS U1998 ( .A0(n2478), .A1(n807), .B0(n2477), .B1(n870), .Y(
DP_OP_169J45_123_4229_n1024) );
OAI22X1TS U1999 ( .A0(n2562), .A1(n806), .B0(n2561), .B1(n869), .Y(
DP_OP_169J45_123_4229_n1108) );
CMPR42X1TS U2000 ( .A(DP_OP_169J45_123_4229_n680), .B(
DP_OP_169J45_123_4229_n1137), .C(DP_OP_169J45_123_4229_n1081), .D(
DP_OP_169J45_123_4229_n1165), .ICI(DP_OP_169J45_123_4229_n684), .S(
DP_OP_169J45_123_4229_n678), .ICO(DP_OP_169J45_123_4229_n676), .CO(
DP_OP_169J45_123_4229_n677) );
OAI22X1TS U2001 ( .A0(n2589), .A1(n2601), .B0(n2588), .B1(n871), .Y(
DP_OP_169J45_123_4229_n1137) );
CMPR42X1TS U2002 ( .A(DP_OP_169J45_123_4229_n1025), .B(
DP_OP_169J45_123_4229_n1193), .C(DP_OP_169J45_123_4229_n1053), .D(
DP_OP_169J45_123_4229_n1109), .ICI(DP_OP_169J45_123_4229_n687), .S(
DP_OP_169J45_123_4229_n675), .ICO(DP_OP_169J45_123_4229_n673), .CO(
DP_OP_169J45_123_4229_n674) );
OAI22X1TS U2003 ( .A0(n2563), .A1(n806), .B0(n2562), .B1(n869), .Y(
DP_OP_169J45_123_4229_n1109) );
OAI22X1TS U2004 ( .A0(n2509), .A1(n804), .B0(n2507), .B1(n872), .Y(
DP_OP_169J45_123_4229_n1053) );
OAI22X1TS U2005 ( .A0(n2478), .A1(n2483), .B0(n2480), .B1(n807), .Y(
DP_OP_169J45_123_4229_n1025) );
OAI21XLTS U2006 ( .A0(n2991), .A1(n2990), .B0(n3384), .Y(n2989) );
OAI21XLTS U2007 ( .A0(n2859), .A1(n2858), .B0(n2898), .Y(n2857) );
INVX2TS U2008 ( .A(n1095), .Y(n3360) );
CMPR42X1TS U2009 ( .A(DP_OP_169J45_123_4229_n1110), .B(
DP_OP_169J45_123_4229_n1194), .C(DP_OP_169J45_123_4229_n1054), .D(
DP_OP_169J45_123_4229_n1166), .ICI(DP_OP_169J45_123_4229_n699), .S(
DP_OP_169J45_123_4229_n686), .ICO(DP_OP_169J45_123_4229_n684), .CO(
DP_OP_169J45_123_4229_n685) );
OAI22X1TS U2010 ( .A0(n2512), .A1(n804), .B0(n2509), .B1(n872), .Y(
DP_OP_169J45_123_4229_n1054) );
OAI22X1TS U2011 ( .A0(n2564), .A1(n806), .B0(n2563), .B1(n869), .Y(
DP_OP_169J45_123_4229_n1110) );
CMPR42X1TS U2012 ( .A(DP_OP_169J45_123_4229_n691), .B(
DP_OP_169J45_123_4229_n1026), .C(DP_OP_169J45_123_4229_n698), .D(
DP_OP_169J45_123_4229_n1082), .ICI(DP_OP_169J45_123_4229_n1138), .S(
DP_OP_169J45_123_4229_n689), .ICO(DP_OP_169J45_123_4229_n687), .CO(
DP_OP_169J45_123_4229_n688) );
OAI22X1TS U2013 ( .A0(n2480), .A1(n2483), .B0(n2484), .B1(n807), .Y(
DP_OP_169J45_123_4229_n1026) );
OAI21XLTS U2014 ( .A0(n2937), .A1(n2936), .B0(n3384), .Y(n2935) );
OAI21XLTS U2015 ( .A0(n2856), .A1(n2855), .B0(n2898), .Y(n2854) );
INVX2TS U2016 ( .A(n1100), .Y(n3235) );
CMPR42X1TS U2017 ( .A(DP_OP_169J45_123_4229_n999), .B(
DP_OP_169J45_123_4229_n709), .C(DP_OP_169J45_123_4229_n1027), .D(
DP_OP_169J45_123_4229_n1055), .ICI(DP_OP_169J45_123_4229_n1195), .S(
DP_OP_169J45_123_4229_n700), .ICO(DP_OP_169J45_123_4229_n698), .CO(
DP_OP_169J45_123_4229_n699) );
NOR2BX1TS U2018 ( .AN(n2660), .B(n2453), .Y(DP_OP_169J45_123_4229_n999) );
OAI22X1TS U2019 ( .A0(n2484), .A1(n2483), .B0(n807), .B1(n2481), .Y(
DP_OP_169J45_123_4229_n1027) );
OAI22X1TS U2020 ( .A0(n2512), .A1(n2513), .B0(n2511), .B1(n804), .Y(
DP_OP_169J45_123_4229_n1055) );
CMPR42X1TS U2021 ( .A(DP_OP_169J45_123_4229_n1111), .B(
DP_OP_169J45_123_4229_n1139), .C(DP_OP_169J45_123_4229_n1083), .D(
DP_OP_169J45_123_4229_n1167), .ICI(DP_OP_169J45_123_4229_n704), .S(
DP_OP_169J45_123_4229_n697), .ICO(DP_OP_169J45_123_4229_n695), .CO(
DP_OP_169J45_123_4229_n696) );
OAI22X1TS U2022 ( .A0(n2591), .A1(n2601), .B0(n2590), .B1(n871), .Y(
DP_OP_169J45_123_4229_n1139) );
OAI22X1TS U2023 ( .A0(n2565), .A1(n806), .B0(n2564), .B1(n869), .Y(
DP_OP_169J45_123_4229_n1111) );
CMPR42X1TS U2024 ( .A(DP_OP_169J45_123_4229_n1140), .B(
DP_OP_169J45_123_4229_n1196), .C(DP_OP_169J45_123_4229_n1084), .D(
DP_OP_169J45_123_4229_n1168), .ICI(DP_OP_169J45_123_4229_n714), .S(
DP_OP_169J45_123_4229_n706), .ICO(DP_OP_169J45_123_4229_n704), .CO(
DP_OP_169J45_123_4229_n705) );
OAI22X1TS U2025 ( .A0(n2592), .A1(n2601), .B0(n2591), .B1(n871), .Y(
DP_OP_169J45_123_4229_n1140) );
OAI21XLTS U2026 ( .A0(n4272), .A1(n4271), .B0(n4747), .Y(n4270) );
OAI21XLTS U2027 ( .A0(n4418), .A1(n4417), .B0(n4510), .Y(n4416) );
XNOR2X1TS U2028 ( .A(n840), .B(n2539), .Y(n2538) );
XNOR2X1TS U2029 ( .A(n814), .B(n2539), .Y(n2540) );
XOR2X1TS U2030 ( .A(n2109), .B(n2108), .Y(n2110) );
NOR2XLTS U2031 ( .A(n2107), .B(n2106), .Y(n2109) );
XNOR2X1TS U2032 ( .A(n837), .B(n890), .Y(n2566) );
CMPR42X1TS U2033 ( .A(DP_OP_169J45_123_4229_n718), .B(
DP_OP_169J45_123_4229_n1141), .C(DP_OP_169J45_123_4229_n1197), .D(
DP_OP_169J45_123_4229_n1169), .ICI(DP_OP_169J45_123_4229_n722), .S(
DP_OP_169J45_123_4229_n716), .ICO(DP_OP_169J45_123_4229_n714), .CO(
DP_OP_169J45_123_4229_n715) );
OAI22X1TS U2034 ( .A0(n2593), .A1(n2601), .B0(n2592), .B1(n871), .Y(
DP_OP_169J45_123_4229_n1141) );
XNOR2X1TS U2035 ( .A(n832), .B(n895), .Y(n2623) );
XNOR2X1TS U2036 ( .A(n836), .B(n2567), .Y(n2568) );
CMPR42X1TS U2037 ( .A(DP_OP_169J45_123_4229_n726), .B(
DP_OP_169J45_123_4229_n1086), .C(DP_OP_169J45_123_4229_n730), .D(
DP_OP_169J45_123_4229_n1142), .ICI(DP_OP_169J45_123_4229_n1198), .S(
DP_OP_169J45_123_4229_n724), .ICO(DP_OP_169J45_123_4229_n722), .CO(
DP_OP_169J45_123_4229_n723) );
OAI22X1TS U2038 ( .A0(n2594), .A1(n2601), .B0(n2593), .B1(n871), .Y(
DP_OP_169J45_123_4229_n1142) );
OAI21XLTS U2039 ( .A0(n2782), .A1(n2781), .B0(n3098), .Y(n2780) );
OAI21XLTS U2040 ( .A0(n2850), .A1(n2849), .B0(n2898), .Y(n2848) );
OAI21XLTS U2041 ( .A0(n4413), .A1(n4412), .B0(n4510), .Y(n4411) );
XNOR2X1TS U2042 ( .A(n835), .B(n2627), .Y(n2624) );
CMPR42X1TS U2043 ( .A(DP_OP_169J45_123_4229_n1059), .B(
DP_OP_169J45_123_4229_n738), .C(DP_OP_169J45_123_4229_n1087), .D(
DP_OP_169J45_123_4229_n1115), .ICI(DP_OP_169J45_123_4229_n1199), .S(
DP_OP_169J45_123_4229_n732), .ICO(DP_OP_169J45_123_4229_n730), .CO(
DP_OP_169J45_123_4229_n731) );
NOR2BX1TS U2044 ( .AN(n2660), .B(n2513), .Y(DP_OP_169J45_123_4229_n1059) );
OAI21XLTS U2045 ( .A0(n2785), .A1(n2784), .B0(n3098), .Y(n2783) );
OAI21XLTS U2046 ( .A0(n2847), .A1(n2846), .B0(n2898), .Y(n2845) );
XNOR2X1TS U2047 ( .A(n836), .B(n892), .Y(n2595) );
XNOR2X1TS U2048 ( .A(n832), .B(n897), .Y(n2652) );
XNOR2X1TS U2049 ( .A(n833), .B(n895), .Y(n2625) );
OAI22X1TS U2050 ( .A0(n2569), .A1(n2571), .B0(n2214), .B1(n805), .Y(n2216)
);
OAI21XLTS U2051 ( .A0(n4300), .A1(n4299), .B0(n4744), .Y(n4298) );
OAI21XLTS U2052 ( .A0(n4441), .A1(n4440), .B0(n4510), .Y(n4439) );
INVX2TS U2053 ( .A(n3524), .Y(n4419) );
XNOR2X1TS U2054 ( .A(n840), .B(n2598), .Y(n2597) );
XNOR2X1TS U2055 ( .A(n835), .B(n897), .Y(n2653) );
XNOR2X1TS U2056 ( .A(n837), .B(n2627), .Y(n2626) );
NOR2BX1TS U2057 ( .AN(n2660), .B(n874), .Y(n2222) );
OAI21XLTS U2058 ( .A0(n2844), .A1(n2843), .B0(n2898), .Y(n2842) );
OAI22X1TS U2059 ( .A0(n805), .A1(n733), .B0(n2571), .B1(n2211), .Y(n2224) );
NAND2BXLTS U2060 ( .AN(n2660), .B(n2567), .Y(n2211) );
XNOR2X1TS U2061 ( .A(n814), .B(n893), .Y(n2599) );
XNOR2X1TS U2062 ( .A(n833), .B(n896), .Y(n2655) );
XNOR2X1TS U2063 ( .A(n836), .B(n895), .Y(n2628) );
BUFX6TS U2064 ( .A(n2629), .Y(n887) );
XNOR2X1TS U2065 ( .A(n837), .B(n896), .Y(n2656) );
XNOR2X1TS U2066 ( .A(n840), .B(n2627), .Y(n2630) );
XNOR2X1TS U2067 ( .A(n2017), .B(n2012), .Y(n2016) );
NOR2XLTS U2068 ( .A(Op_MY[32]), .B(Op_MY[5]), .Y(n2012) );
OAI21XLTS U2069 ( .A0(n4456), .A1(n4455), .B0(n4513), .Y(n4454) );
INVX2TS U2070 ( .A(n3534), .Y(n4410) );
XNOR2X1TS U2071 ( .A(n836), .B(n896), .Y(n2658) );
ADDHXLTS U2072 ( .A(n2226), .B(n2225), .CO(DP_OP_169J45_123_4229_n755), .S(
n1772) );
OAI22X1TS U2073 ( .A0(n800), .A1(n1735), .B0(n2602), .B1(n2600), .Y(n2225)
);
OAI22X1TS U2074 ( .A0(n800), .A1(n2572), .B0(n1734), .B1(n2602), .Y(n2226)
);
OAI21XLTS U2075 ( .A0(n2838), .A1(n2837), .B0(n2898), .Y(n2836) );
XNOR2X1TS U2076 ( .A(n840), .B(n896), .Y(n1768) );
NAND2X1TS U2077 ( .A(n1763), .B(n1762), .Y(n1726) );
XNOR2X1TS U2078 ( .A(n1728), .B(n1723), .Y(n1727) );
NOR2XLTS U2079 ( .A(n846), .B(Op_MY[3]), .Y(n1723) );
NAND2X1TS U2080 ( .A(n1725), .B(n1724), .Y(n1763) );
OAI21XLTS U2081 ( .A0(Op_MY[29]), .A1(Op_MY[2]), .B0(n4892), .Y(n1725) );
XNOR2X1TS U2082 ( .A(n814), .B(n896), .Y(n1773) );
ADDHXLTS U2083 ( .A(n3443), .B(n3442), .CO(mult_x_23_n518), .S(n2803) );
OAI21XLTS U2084 ( .A0(n1138), .A1(n1137), .B0(n3015), .Y(n1136) );
OAI21XLTS U2085 ( .A0(n4486), .A1(n4485), .B0(n4782), .Y(n4484) );
OAI21XLTS U2086 ( .A0(n4462), .A1(n4461), .B0(n4510), .Y(n4460) );
OAI31X1TS U2087 ( .A0(n1142), .A1(Op_MX[35]), .A2(n3245), .B0(n1141), .Y(
n1160) );
XOR2X1TS U2088 ( .A(Op_MY[29]), .B(Op_MY[2]), .Y(n1751) );
CLKAND2X2TS U2089 ( .A(n848), .B(Op_MY[0]), .Y(n910) );
OAI21XLTS U2090 ( .A0(n4776), .A1(n4775), .B0(n4782), .Y(n4774) );
OAI21XLTS U2091 ( .A0(n4474), .A1(n4473), .B0(n4510), .Y(n4472) );
OAI21XLTS U2092 ( .A0(n4483), .A1(n4482), .B0(n4513), .Y(n4481) );
INVX2TS U2093 ( .A(n1135), .Y(n3260) );
OAI21XLTS U2094 ( .A0(n4759), .A1(n4758), .B0(n4782), .Y(n4757) );
OAI21XLTS U2095 ( .A0(n4493), .A1(n4492), .B0(n4510), .Y(n4491) );
OAI21XLTS U2096 ( .A0(n3590), .A1(n4035), .B0(n4915), .Y(n3749) );
OAI21XLTS U2097 ( .A0(n4514), .A1(n4512), .B0(n4510), .Y(n4511) );
OAI21XLTS U2098 ( .A0(n3586), .A1(n3585), .B0(n4516), .Y(n3584) );
OAI21XLTS U2099 ( .A0(n3590), .A1(n3592), .B0(n4914), .Y(n3591) );
NOR2X1TS U2100 ( .A(n3619), .B(n3595), .Y(n3616) );
NOR2X1TS U2101 ( .A(n3475), .B(n3474), .Y(n3615) );
NOR2X2TS U2102 ( .A(n732), .B(DP_OP_168J45_122_1342_n600), .Y(n1670) );
INVX2TS U2103 ( .A(n1675), .Y(n1247) );
NAND2X1TS U2104 ( .A(DP_OP_168J45_122_1342_n600), .B(n732), .Y(n1671) );
NAND2X1TS U2105 ( .A(n1251), .B(n1250), .Y(n1661) );
INVX2TS U2106 ( .A(n1643), .Y(n1645) );
OAI21X2TS U2107 ( .A0(n1650), .A1(n1655), .B0(n1651), .Y(n1641) );
NOR2X2TS U2108 ( .A(n1648), .B(n1650), .Y(n1642) );
INVX2TS U2109 ( .A(n1636), .Y(n1638) );
NAND2X1TS U2110 ( .A(n1261), .B(n1260), .Y(n1637) );
NAND2X1TS U2111 ( .A(n1642), .B(n1263), .Y(n1265) );
AOI21X1TS U2112 ( .A0(n1641), .A1(n1263), .B0(n1262), .Y(n1264) );
NOR2X1TS U2113 ( .A(n1643), .B(n1636), .Y(n1263) );
INVX2TS U2114 ( .A(n1619), .Y(n1628) );
INVX2TS U2115 ( .A(n1627), .Y(n1620) );
INVX2TS U2116 ( .A(n1622), .Y(n1624) );
INVX2TS U2117 ( .A(n1612), .Y(n1613) );
NAND2X1TS U2118 ( .A(n1271), .B(n1270), .Y(n1615) );
INVX2TS U2119 ( .A(n1602), .Y(n1616) );
AOI21X1TS U2120 ( .A0(n1612), .A1(n1616), .B0(n1603), .Y(n1604) );
INVX2TS U2121 ( .A(n1615), .Y(n1603) );
NAND2X1TS U2122 ( .A(n1611), .B(n1616), .Y(n1605) );
NAND2X1TS U2123 ( .A(n1273), .B(n1272), .Y(n1607) );
NAND2X1TS U2124 ( .A(n1277), .B(n1276), .Y(n1598) );
INVX2TS U2125 ( .A(n1585), .Y(n1599) );
AOI21X2TS U2126 ( .A0(n1612), .A1(n1275), .B0(n1274), .Y(n1596) );
OAI21X1TS U2127 ( .A0(n1606), .A1(n1615), .B0(n1607), .Y(n1274) );
NAND2X1TS U2128 ( .A(n1611), .B(n1275), .Y(n1597) );
AOI21X1TS U2129 ( .A0(n1588), .A1(n1599), .B0(n1587), .Y(n1589) );
NAND2X1TS U2130 ( .A(n1586), .B(n1599), .Y(n1590) );
NAND2X1TS U2131 ( .A(n1279), .B(n1278), .Y(n1592) );
AOI21X1TS U2132 ( .A0(n1588), .A1(n1577), .B0(n1576), .Y(n1578) );
NAND2X1TS U2133 ( .A(n1281), .B(n1280), .Y(n1581) );
AOI21X1TS U2134 ( .A0(n1588), .A1(n1568), .B0(n1567), .Y(n1569) );
OAI21XLTS U2135 ( .A0(n1566), .A1(n1580), .B0(n1581), .Y(n1567) );
NAND2X1TS U2136 ( .A(n1283), .B(n1282), .Y(n1572) );
NAND2X1TS U2137 ( .A(n1289), .B(n1288), .Y(n1562) );
OAI21X1TS U2138 ( .A0(n1630), .A1(n965), .B0(n964), .Y(n1564) );
NAND2X1TS U2139 ( .A(n1577), .B(n1285), .Y(n1287) );
NOR2X1TS U2140 ( .A(n1292), .B(n1291), .Y(n1557) );
NAND2X1TS U2141 ( .A(n1292), .B(n1291), .Y(n1558) );
AOI21X1TS U2142 ( .A0(n1564), .A1(n966), .B0(n1290), .Y(n1561) );
INVX2TS U2143 ( .A(n1562), .Y(n1290) );
NAND2X1TS U2144 ( .A(n1294), .B(n1293), .Y(n1554) );
OAI21X1TS U2145 ( .A0(n1561), .A1(n1557), .B0(n1558), .Y(n1556) );
NOR2X1TS U2146 ( .A(n1297), .B(n1296), .Y(n1549) );
NAND2X1TS U2147 ( .A(n1297), .B(n1296), .Y(n1550) );
INVX2TS U2148 ( .A(n1554), .Y(n1295) );
NAND2X1TS U2149 ( .A(n1299), .B(n1298), .Y(n1546) );
NOR2X1TS U2150 ( .A(n1302), .B(n1301), .Y(n1541) );
NAND2X1TS U2151 ( .A(n1302), .B(n1301), .Y(n1542) );
AOI21X1TS U2152 ( .A0(n1548), .A1(n961), .B0(n1300), .Y(n1545) );
NAND2X1TS U2153 ( .A(n1304), .B(n1303), .Y(n1538) );
OAI21X1TS U2154 ( .A0(n1545), .A1(n1541), .B0(n1542), .Y(n1540) );
NOR2X1TS U2155 ( .A(n1307), .B(n1306), .Y(n1533) );
NAND2X1TS U2156 ( .A(n1307), .B(n1306), .Y(n1534) );
AOI21X1TS U2157 ( .A0(n1540), .A1(n973), .B0(n1305), .Y(n1537) );
INVX2TS U2158 ( .A(n1538), .Y(n1305) );
NAND2X1TS U2159 ( .A(n1309), .B(n1308), .Y(n1530) );
OAI21X1TS U2160 ( .A0(n1537), .A1(n1533), .B0(n1534), .Y(n1532) );
NOR2X1TS U2161 ( .A(n1312), .B(n1311), .Y(n1525) );
NAND2X1TS U2162 ( .A(n1314), .B(n1313), .Y(n1522) );
NAND2X1TS U2163 ( .A(n1317), .B(n1316), .Y(n1518) );
NAND2X1TS U2164 ( .A(n1319), .B(n1318), .Y(n1514) );
NAND2X1TS U2165 ( .A(n1322), .B(n1321), .Y(n1510) );
AOI21X1TS U2166 ( .A0(n1412), .A1(n920), .B0(n1407), .Y(n1409) );
OAI21XLTS U2167 ( .A0(n1884), .A1(n1883), .B0(n1714), .Y(n1715) );
NOR2X1TS U2168 ( .A(n1705), .B(n1996), .Y(n1707) );
OAI21X1TS U2169 ( .A0(n1995), .A1(n1705), .B0(n1704), .Y(n1706) );
NAND2X1TS U2170 ( .A(n1945), .B(n1703), .Y(n1705) );
NOR2XLTS U2171 ( .A(n786), .B(n853), .Y(n1879) );
INVX2TS U2172 ( .A(n1881), .Y(n1902) );
CMPR42X1TS U2173 ( .A(DP_OP_169J45_123_4229_n880), .B(
DP_OP_169J45_123_4229_n186), .C(DP_OP_169J45_123_4229_n778), .D(
DP_OP_169J45_123_4229_n852), .ICI(DP_OP_169J45_123_4229_n824), .S(
DP_OP_169J45_123_4229_n179), .ICO(DP_OP_169J45_123_4229_n177), .CO(
DP_OP_169J45_123_4229_n178) );
XOR2X1TS U2174 ( .A(n1893), .B(Op_MY[25]), .Y(n1900) );
NOR2XLTS U2175 ( .A(n1892), .B(n1894), .Y(n1893) );
CMPR42X1TS U2176 ( .A(DP_OP_169J45_123_4229_n881), .B(
DP_OP_169J45_123_4229_n187), .C(DP_OP_169J45_123_4229_n853), .D(
DP_OP_169J45_123_4229_n797), .ICI(DP_OP_169J45_123_4229_n191), .S(
DP_OP_169J45_123_4229_n185), .ICO(DP_OP_169J45_123_4229_n183), .CO(
DP_OP_169J45_123_4229_n184) );
CMPR42X1TS U2177 ( .A(DP_OP_169J45_123_4229_n882), .B(
DP_OP_169J45_123_4229_n854), .C(DP_OP_169J45_123_4229_n826), .D(
DP_OP_169J45_123_4229_n195), .ICI(DP_OP_169J45_123_4229_n199), .S(
DP_OP_169J45_123_4229_n193), .ICO(DP_OP_169J45_123_4229_n191), .CO(
DP_OP_169J45_123_4229_n192) );
CMPR42X1TS U2178 ( .A(DP_OP_169J45_123_4229_n827), .B(
DP_OP_169J45_123_4229_n883), .C(DP_OP_169J45_123_4229_n855), .D(
DP_OP_169J45_123_4229_n799), .ICI(DP_OP_169J45_123_4229_n213), .S(
DP_OP_169J45_123_4229_n201), .ICO(DP_OP_169J45_123_4229_n199), .CO(
DP_OP_169J45_123_4229_n200) );
OAI22X1TS U2179 ( .A0(n2367), .A1(n2391), .B0(n865), .B1(n2152), .Y(n1928)
);
CMPR42X1TS U2180 ( .A(DP_OP_169J45_123_4229_n940), .B(
DP_OP_169J45_123_4229_n224), .C(DP_OP_169J45_123_4229_n780), .D(
DP_OP_169J45_123_4229_n912), .ICI(DP_OP_169J45_123_4229_n800), .S(
DP_OP_169J45_123_4229_n214), .ICO(DP_OP_169J45_123_4229_n212), .CO(
DP_OP_169J45_123_4229_n213) );
CMPR42X1TS U2181 ( .A(DP_OP_169J45_123_4229_n884), .B(
DP_OP_169J45_123_4229_n828), .C(DP_OP_169J45_123_4229_n856), .D(
DP_OP_169J45_123_4229_n221), .ICI(DP_OP_169J45_123_4229_n218), .S(
DP_OP_169J45_123_4229_n211), .ICO(DP_OP_169J45_123_4229_n209), .CO(
DP_OP_169J45_123_4229_n210) );
CMPR42X1TS U2182 ( .A(DP_OP_169J45_123_4229_n225), .B(
DP_OP_169J45_123_4229_n941), .C(DP_OP_169J45_123_4229_n801), .D(
DP_OP_169J45_123_4229_n235), .ICI(DP_OP_169J45_123_4229_n829), .S(
DP_OP_169J45_123_4229_n223), .ICO(DP_OP_169J45_123_4229_n221), .CO(
DP_OP_169J45_123_4229_n222) );
CMPR42X1TS U2183 ( .A(DP_OP_169J45_123_4229_n913), .B(
DP_OP_169J45_123_4229_n857), .C(DP_OP_169J45_123_4229_n885), .D(
DP_OP_169J45_123_4229_n232), .ICI(DP_OP_169J45_123_4229_n229), .S(
DP_OP_169J45_123_4229_n220), .ICO(DP_OP_169J45_123_4229_n218), .CO(
DP_OP_169J45_123_4229_n219) );
CLKAND2X2TS U2184 ( .A(n3901), .B(n3469), .Y(n4847) );
OAI21XLTS U2185 ( .A0(n3926), .A1(n3925), .B0(n4844), .Y(n3924) );
OAI21XLTS U2186 ( .A0(n3400), .A1(n3395), .B0(n3342), .Y(n988) );
INVX2TS U2187 ( .A(n990), .Y(n3225) );
CLKAND2X2TS U2188 ( .A(n987), .B(n1001), .Y(n3251) );
OAI21XLTS U2189 ( .A0(n3233), .A1(n3232), .B0(n3402), .Y(n3231) );
OAI21XLTS U2190 ( .A0(n3332), .A1(n3395), .B0(n3331), .Y(n2804) );
CLKAND2X2TS U2191 ( .A(n1006), .B(n1009), .Y(n2738) );
BUFX6TS U2192 ( .A(n3326), .Y(n3402) );
OAI21XLTS U2193 ( .A0(n3315), .A1(n3395), .B0(n3314), .Y(n2809) );
OAI21XLTS U2194 ( .A0(n3219), .A1(n3218), .B0(n3402), .Y(n3217) );
CLKAND2X2TS U2195 ( .A(n1013), .B(n1016), .Y(n2758) );
OAI21XLTS U2196 ( .A0(n3299), .A1(n3395), .B0(n3298), .Y(n2814) );
INVX2TS U2197 ( .A(n1125), .Y(n3339) );
NAND2BXLTS U2198 ( .AN(n2660), .B(n896), .Y(n1683) );
CMPR42X1TS U2199 ( .A(DP_OP_169J45_123_4229_n223), .B(
DP_OP_169J45_123_4229_n233), .C(DP_OP_169J45_123_4229_n230), .D(
DP_OP_169J45_123_4229_n220), .ICI(DP_OP_169J45_123_4229_n226), .S(
DP_OP_169J45_123_4229_n217), .ICO(DP_OP_169J45_123_4229_n215), .CO(
DP_OP_169J45_123_4229_n216) );
OAI21XLTS U2200 ( .A0(n3230), .A1(n759), .B0(n747), .Y(n1024) );
CMPR42X1TS U2201 ( .A(DP_OP_169J45_123_4229_n245), .B(
DP_OP_169J45_123_4229_n257), .C(DP_OP_169J45_123_4229_n242), .D(
DP_OP_169J45_123_4229_n254), .ICI(DP_OP_169J45_123_4229_n250), .S(
DP_OP_169J45_123_4229_n239), .ICO(DP_OP_169J45_123_4229_n237), .CO(
DP_OP_169J45_123_4229_n238) );
OAI21XLTS U2202 ( .A0(n3230), .A1(n3287), .B0(n749), .Y(n1031) );
CMPR42X1TS U2203 ( .A(DP_OP_169J45_123_4229_n258), .B(
DP_OP_169J45_123_4229_n265), .C(DP_OP_169J45_123_4229_n255), .D(
DP_OP_169J45_123_4229_n266), .ICI(DP_OP_169J45_123_4229_n262), .S(
DP_OP_169J45_123_4229_n252), .ICO(DP_OP_169J45_123_4229_n250), .CO(
DP_OP_169J45_123_4229_n251) );
CMPR42X1TS U2204 ( .A(DP_OP_169J45_123_4229_n283), .B(
DP_OP_169J45_123_4229_n279), .C(DP_OP_169J45_123_4229_n280), .D(
DP_OP_169J45_123_4229_n267), .ICI(DP_OP_169J45_123_4229_n276), .S(
DP_OP_169J45_123_4229_n264), .ICO(DP_OP_169J45_123_4229_n262), .CO(
DP_OP_169J45_123_4229_n263) );
CMPR42X1TS U2205 ( .A(DP_OP_169J45_123_4229_n284), .B(
DP_OP_169J45_123_4229_n293), .C(DP_OP_169J45_123_4229_n294), .D(
DP_OP_169J45_123_4229_n281), .ICI(DP_OP_169J45_123_4229_n290), .S(
DP_OP_169J45_123_4229_n278), .ICO(DP_OP_169J45_123_4229_n276), .CO(
DP_OP_169J45_123_4229_n277) );
OAI21XLTS U2206 ( .A0(n3230), .A1(n757), .B0(n752), .Y(n1038) );
CMPR42X1TS U2207 ( .A(DP_OP_169J45_123_4229_n314), .B(
DP_OP_169J45_123_4229_n324), .C(DP_OP_169J45_123_4229_n325), .D(
DP_OP_169J45_123_4229_n311), .ICI(DP_OP_169J45_123_4229_n321), .S(
DP_OP_169J45_123_4229_n308), .ICO(DP_OP_169J45_123_4229_n306), .CO(
DP_OP_169J45_123_4229_n307) );
CMPR42X1TS U2208 ( .A(DP_OP_169J45_123_4229_n345), .B(
DP_OP_169J45_123_4229_n329), .C(DP_OP_169J45_123_4229_n342), .D(
DP_OP_169J45_123_4229_n326), .ICI(DP_OP_169J45_123_4229_n338), .S(
DP_OP_169J45_123_4229_n323), .ICO(DP_OP_169J45_123_4229_n321), .CO(
DP_OP_169J45_123_4229_n322) );
CMPR42X1TS U2209 ( .A(DP_OP_169J45_123_4229_n362), .B(
DP_OP_169J45_123_4229_n346), .C(DP_OP_169J45_123_4229_n359), .D(
DP_OP_169J45_123_4229_n343), .ICI(DP_OP_169J45_123_4229_n355), .S(
DP_OP_169J45_123_4229_n340), .ICO(DP_OP_169J45_123_4229_n338), .CO(
DP_OP_169J45_123_4229_n339) );
CMPR42X1TS U2210 ( .A(DP_OP_169J45_123_4229_n377), .B(
DP_OP_169J45_123_4229_n363), .C(DP_OP_169J45_123_4229_n378), .D(
DP_OP_169J45_123_4229_n360), .ICI(DP_OP_169J45_123_4229_n374), .S(
DP_OP_169J45_123_4229_n357), .ICO(DP_OP_169J45_123_4229_n355), .CO(
DP_OP_169J45_123_4229_n356) );
BUFX6TS U2211 ( .A(n970), .Y(n2898) );
OAI21XLTS U2212 ( .A0(n3230), .A1(n2897), .B0(n2896), .Y(n1045) );
CMPR42X1TS U2213 ( .A(DP_OP_169J45_123_4229_n415), .B(
DP_OP_169J45_123_4229_n400), .C(DP_OP_169J45_123_4229_n416), .D(
DP_OP_169J45_123_4229_n397), .ICI(DP_OP_169J45_123_4229_n412), .S(
DP_OP_169J45_123_4229_n394), .ICO(DP_OP_169J45_123_4229_n392), .CO(
DP_OP_169J45_123_4229_n393) );
CMPR42X1TS U2214 ( .A(DP_OP_169J45_123_4229_n435), .B(
DP_OP_169J45_123_4229_n420), .C(DP_OP_169J45_123_4229_n436), .D(
DP_OP_169J45_123_4229_n417), .ICI(DP_OP_169J45_123_4229_n432), .S(
DP_OP_169J45_123_4229_n414), .ICO(DP_OP_169J45_123_4229_n412), .CO(
DP_OP_169J45_123_4229_n413) );
CMPR42X1TS U2215 ( .A(DP_OP_169J45_123_4229_n457), .B(
DP_OP_169J45_123_4229_n440), .C(DP_OP_169J45_123_4229_n458), .D(
DP_OP_169J45_123_4229_n437), .ICI(DP_OP_169J45_123_4229_n454), .S(
DP_OP_169J45_123_4229_n434), .ICO(DP_OP_169J45_123_4229_n432), .CO(
DP_OP_169J45_123_4229_n433) );
OAI21XLTS U2216 ( .A0(n3230), .A1(n760), .B0(n1204), .Y(n1052) );
OAI21XLTS U2217 ( .A0(n2974), .A1(n2973), .B0(n976), .Y(n2972) );
CMPR42X1TS U2218 ( .A(DP_OP_169J45_123_4229_n478), .B(
DP_OP_169J45_123_4229_n462), .C(DP_OP_169J45_123_4229_n479), .D(
DP_OP_169J45_123_4229_n459), .ICI(DP_OP_169J45_123_4229_n475), .S(
DP_OP_169J45_123_4229_n456), .ICO(DP_OP_169J45_123_4229_n454), .CO(
DP_OP_169J45_123_4229_n455) );
CMPR42X1TS U2219 ( .A(DP_OP_169J45_123_4229_n506), .B(
DP_OP_169J45_123_4229_n518), .C(DP_OP_169J45_123_4229_n519), .D(
DP_OP_169J45_123_4229_n500), .ICI(DP_OP_169J45_123_4229_n515), .S(
DP_OP_169J45_123_4229_n497), .ICO(DP_OP_169J45_123_4229_n495), .CO(
DP_OP_169J45_123_4229_n496) );
CMPR42X1TS U2220 ( .A(DP_OP_169J45_123_4229_n540), .B(
DP_OP_169J45_123_4229_n523), .C(DP_OP_169J45_123_4229_n537), .D(
DP_OP_169J45_123_4229_n520), .ICI(DP_OP_169J45_123_4229_n533), .S(
DP_OP_169J45_123_4229_n517), .ICO(DP_OP_169J45_123_4229_n515), .CO(
DP_OP_169J45_123_4229_n516) );
CLKAND2X2TS U2221 ( .A(n3595), .B(n3474), .Y(n4841) );
OAI21XLTS U2222 ( .A0(n2955), .A1(n2954), .B0(n976), .Y(n2953) );
CMPR42X1TS U2223 ( .A(DP_OP_169J45_123_4229_n559), .B(
DP_OP_169J45_123_4229_n541), .C(DP_OP_169J45_123_4229_n556), .D(
DP_OP_169J45_123_4229_n538), .ICI(DP_OP_169J45_123_4229_n552), .S(
DP_OP_169J45_123_4229_n535), .ICO(DP_OP_169J45_123_4229_n533), .CO(
DP_OP_169J45_123_4229_n534) );
INVX2TS U2224 ( .A(n1070), .Y(n3237) );
CMPR42X1TS U2225 ( .A(DP_OP_169J45_123_4229_n572), .B(
DP_OP_169J45_123_4229_n560), .C(DP_OP_169J45_123_4229_n573), .D(
DP_OP_169J45_123_4229_n557), .ICI(DP_OP_169J45_123_4229_n569), .S(
DP_OP_169J45_123_4229_n554), .ICO(DP_OP_169J45_123_4229_n552), .CO(
DP_OP_169J45_123_4229_n553) );
BUFX3TS U2226 ( .A(n3479), .Y(n4846) );
CMPR42X1TS U2227 ( .A(DP_OP_169J45_123_4229_n594), .B(
DP_OP_169J45_123_4229_n604), .C(DP_OP_169J45_123_4229_n605), .D(
DP_OP_169J45_123_4229_n601), .ICI(DP_OP_169J45_123_4229_n591), .S(
DP_OP_169J45_123_4229_n588), .ICO(DP_OP_169J45_123_4229_n586), .CO(
DP_OP_169J45_123_4229_n587) );
CMPR42X1TS U2228 ( .A(DP_OP_169J45_123_4229_n612), .B(
DP_OP_169J45_123_4229_n609), .C(DP_OP_169J45_123_4229_n621), .D(
DP_OP_169J45_123_4229_n617), .ICI(DP_OP_169J45_123_4229_n606), .S(
DP_OP_169J45_123_4229_n603), .ICO(DP_OP_169J45_123_4229_n601), .CO(
DP_OP_169J45_123_4229_n602) );
OAI21XLTS U2229 ( .A0(n2933), .A1(n2932), .B0(n976), .Y(n2931) );
INVX2TS U2230 ( .A(n1080), .Y(n3399) );
CMPR42X1TS U2231 ( .A(DP_OP_169J45_123_4229_n628), .B(
DP_OP_169J45_123_4229_n625), .C(DP_OP_169J45_123_4229_n635), .D(
DP_OP_169J45_123_4229_n631), .ICI(DP_OP_169J45_123_4229_n622), .S(
DP_OP_169J45_123_4229_n619), .ICO(DP_OP_169J45_123_4229_n617), .CO(
DP_OP_169J45_123_4229_n618) );
CMPR42X1TS U2232 ( .A(DP_OP_169J45_123_4229_n652), .B(
DP_OP_169J45_123_4229_n639), .C(DP_OP_169J45_123_4229_n649), .D(
DP_OP_169J45_123_4229_n645), .ICI(DP_OP_169J45_123_4229_n636), .S(
DP_OP_169J45_123_4229_n633), .ICO(DP_OP_169J45_123_4229_n631), .CO(
DP_OP_169J45_123_4229_n632) );
INVX2TS U2233 ( .A(n3493), .Y(n4334) );
OAI21XLTS U2234 ( .A0(n2926), .A1(n2925), .B0(n976), .Y(n2924) );
CMPR42X1TS U2235 ( .A(DP_OP_169J45_123_4229_n677), .B(
DP_OP_169J45_123_4229_n674), .C(DP_OP_169J45_123_4229_n665), .D(
DP_OP_169J45_123_4229_n662), .ICI(DP_OP_169J45_123_4229_n670), .S(
DP_OP_169J45_123_4229_n659), .ICO(DP_OP_169J45_123_4229_n657), .CO(
DP_OP_169J45_123_4229_n658) );
CMPR42X1TS U2236 ( .A(DP_OP_169J45_123_4229_n688), .B(
DP_OP_169J45_123_4229_n685), .C(DP_OP_169J45_123_4229_n678), .D(
DP_OP_169J45_123_4229_n675), .ICI(DP_OP_169J45_123_4229_n681), .S(
DP_OP_169J45_123_4229_n672), .ICO(DP_OP_169J45_123_4229_n670), .CO(
DP_OP_169J45_123_4229_n671) );
OAI21XLTS U2237 ( .A0(n4366), .A1(n4365), .B0(n4516), .Y(n4364) );
CMPR42X1TS U2238 ( .A(DP_OP_169J45_123_4229_n695), .B(
DP_OP_169J45_123_4229_n689), .C(DP_OP_169J45_123_4229_n696), .D(
DP_OP_169J45_123_4229_n686), .ICI(DP_OP_169J45_123_4229_n692), .S(
DP_OP_169J45_123_4229_n683), .ICO(DP_OP_169J45_123_4229_n681), .CO(
DP_OP_169J45_123_4229_n682) );
CMPR42X1TS U2239 ( .A(DP_OP_169J45_123_4229_n1112), .B(
DP_OP_169J45_123_4229_n708), .C(DP_OP_169J45_123_4229_n715), .D(
DP_OP_169J45_123_4229_n706), .ICI(DP_OP_169J45_123_4229_n711), .S(
DP_OP_169J45_123_4229_n703), .ICO(DP_OP_169J45_123_4229_n701), .CO(
DP_OP_169J45_123_4229_n702) );
OAI22X1TS U2240 ( .A0(n2566), .A1(n806), .B0(n2565), .B1(n869), .Y(
DP_OP_169J45_123_4229_n1112) );
INVX2TS U2241 ( .A(n3514), .Y(n4611) );
CMPR42X1TS U2242 ( .A(DP_OP_169J45_123_4229_n1085), .B(
DP_OP_169J45_123_4229_n1113), .C(DP_OP_169J45_123_4229_n723), .D(
DP_OP_169J45_123_4229_n719), .ICI(DP_OP_169J45_123_4229_n716), .S(
DP_OP_169J45_123_4229_n713), .ICO(DP_OP_169J45_123_4229_n711), .CO(
DP_OP_169J45_123_4229_n712) );
OAI22X1TS U2243 ( .A0(n2568), .A1(n806), .B0(n2566), .B1(n869), .Y(
DP_OP_169J45_123_4229_n1113) );
CMPR42X1TS U2244 ( .A(DP_OP_169J45_123_4229_n1114), .B(
DP_OP_169J45_123_4229_n1170), .C(DP_OP_169J45_123_4229_n727), .D(
DP_OP_169J45_123_4229_n731), .ICI(DP_OP_169J45_123_4229_n724), .S(
DP_OP_169J45_123_4229_n721), .ICO(DP_OP_169J45_123_4229_n719), .CO(
DP_OP_169J45_123_4229_n720) );
OAI22X1TS U2245 ( .A0(n2570), .A1(n805), .B0(n2568), .B1(n869), .Y(
DP_OP_169J45_123_4229_n1114) );
OAI22X1TS U2246 ( .A0(n2595), .A1(n800), .B0(n2594), .B1(n871), .Y(
DP_OP_169J45_123_4229_n1143) );
INVX2TS U2247 ( .A(n1115), .Y(n3183) );
CMPR42X1TS U2248 ( .A(DP_OP_169J45_123_4229_n1200), .B(
DP_OP_169J45_123_4229_n1144), .C(DP_OP_169J45_123_4229_n1172), .D(
DP_OP_169J45_123_4229_n737), .ICI(DP_OP_169J45_123_4229_n740), .S(
DP_OP_169J45_123_4229_n735), .ICO(DP_OP_169J45_123_4229_n733), .CO(
DP_OP_169J45_123_4229_n734) );
OAI22X1TS U2249 ( .A0(n2597), .A1(n800), .B0(n2595), .B1(n871), .Y(
DP_OP_169J45_123_4229_n1144) );
CMPR42X1TS U2250 ( .A(DP_OP_169J45_123_4229_n744), .B(
DP_OP_169J45_123_4229_n1145), .C(DP_OP_169J45_123_4229_n1201), .D(
DP_OP_169J45_123_4229_n1173), .ICI(DP_OP_169J45_123_4229_n745), .S(
DP_OP_169J45_123_4229_n742), .ICO(DP_OP_169J45_123_4229_n740), .CO(
DP_OP_169J45_123_4229_n741) );
OAI22X1TS U2251 ( .A0(n2597), .A1(n2602), .B0(n2599), .B1(n800), .Y(
DP_OP_169J45_123_4229_n1145) );
OAI21XLTS U2252 ( .A0(n4381), .A1(n4380), .B0(n4516), .Y(n4379) );
CMPR42X1TS U2253 ( .A(DP_OP_169J45_123_4229_n749), .B(
DP_OP_169J45_123_4229_n1146), .C(DP_OP_169J45_123_4229_n750), .D(
DP_OP_169J45_123_4229_n1202), .ICI(DP_OP_169J45_123_4229_n1174), .S(
DP_OP_169J45_123_4229_n747), .ICO(DP_OP_169J45_123_4229_n745), .CO(
DP_OP_169J45_123_4229_n746) );
OAI22X1TS U2254 ( .A0(n2599), .A1(n2602), .B0(n2603), .B1(n800), .Y(
DP_OP_169J45_123_4229_n1146) );
CMPR42X1TS U2255 ( .A(DP_OP_169J45_123_4229_n1119), .B(
DP_OP_169J45_123_4229_n755), .C(DP_OP_169J45_123_4229_n1147), .D(
DP_OP_169J45_123_4229_n1203), .ICI(DP_OP_169J45_123_4229_n1175), .S(
DP_OP_169J45_123_4229_n752), .ICO(DP_OP_169J45_123_4229_n750), .CO(
DP_OP_169J45_123_4229_n751) );
OAI22X1TS U2256 ( .A0(n1768), .A1(n810), .B0(n1773), .B1(n2657), .Y(n1777)
);
OAI21XLTS U2257 ( .A0(n4387), .A1(n4386), .B0(n4516), .Y(n4385) );
INVX2TS U2258 ( .A(n3539), .Y(n4622) );
ADDHX1TS U2259 ( .A(n1781), .B(n1780), .CO(n1848), .S(n1850) );
OAI22X1TS U2260 ( .A0(n1773), .A1(n810), .B0(n2657), .B1(n1782), .Y(n1781)
);
OAI21XLTS U2261 ( .A0(n1147), .A1(n1146), .B0(n2898), .Y(n1145) );
INVX2TS U2262 ( .A(n1169), .Y(n3337) );
OAI21XLTS U2263 ( .A0(n1154), .A1(n1153), .B0(n2898), .Y(n1152) );
INVX2TS U2264 ( .A(n3549), .Y(n4452) );
OAI21XLTS U2265 ( .A0(n1159), .A1(n1158), .B0(n2898), .Y(n1157) );
INVX2TS U2266 ( .A(n1185), .Y(n3273) );
XNOR2X1TS U2267 ( .A(n896), .B(n839), .Y(n1783) );
XOR2X1TS U2268 ( .A(n1753), .B(n911), .Y(n1681) );
CLKXOR2X4TS U2269 ( .A(n1755), .B(n1754), .Y(n2629) );
XNOR2X1TS U2270 ( .A(n1752), .B(n1751), .Y(n1755) );
NAND2X1TS U2271 ( .A(n1753), .B(n910), .Y(n1754) );
NOR2XLTS U2272 ( .A(Op_MY[28]), .B(n4892), .Y(n1752) );
OAI21XLTS U2273 ( .A0(n1163), .A1(n1162), .B0(n2898), .Y(n1161) );
OAI21XLTS U2274 ( .A0(n4504), .A1(n4503), .B0(n4516), .Y(n4502) );
OAI21XLTS U2275 ( .A0(n3590), .A1(n3619), .B0(n4913), .Y(n3618) );
XNOR2X1TS U2276 ( .A(n1677), .B(n1676), .Y(n5194) );
NAND2X1TS U2277 ( .A(n919), .B(n1675), .Y(n1677) );
XOR2X1TS U2278 ( .A(n1669), .B(n1668), .Y(n5188) );
NAND2X1TS U2279 ( .A(n1667), .B(n1666), .Y(n1668) );
NAND2X1TS U2280 ( .A(n1662), .B(n1661), .Y(n1663) );
XOR2X1TS U2281 ( .A(n1654), .B(n1653), .Y(n5178) );
NAND2X1TS U2282 ( .A(n1652), .B(n1651), .Y(n1653) );
AOI21X1TS U2283 ( .A0(n1658), .A1(n1656), .B0(n1649), .Y(n1654) );
XOR2X1TS U2284 ( .A(n1640), .B(n1639), .Y(n5172) );
AOI21X1TS U2285 ( .A0(n1658), .A1(n1635), .B0(n1634), .Y(n1640) );
XOR2X1TS U2286 ( .A(n1630), .B(n1629), .Y(n5169) );
NAND2X1TS U2287 ( .A(n1628), .B(n1627), .Y(n1629) );
XNOR2X1TS U2288 ( .A(n1618), .B(n1617), .Y(n5163) );
NAND2X1TS U2289 ( .A(n1616), .B(n1615), .Y(n1617) );
OAI21XLTS U2290 ( .A0(n1630), .A1(n1614), .B0(n1613), .Y(n1618) );
XNOR2X1TS U2291 ( .A(n1601), .B(n1600), .Y(n5157) );
NAND2X1TS U2292 ( .A(n1599), .B(n1598), .Y(n1600) );
OAI21XLTS U2293 ( .A0(n1630), .A1(n1597), .B0(n1596), .Y(n1601) );
XNOR2X1TS U2294 ( .A(n1595), .B(n1594), .Y(n5153) );
NAND2X1TS U2295 ( .A(n1593), .B(n1592), .Y(n1594) );
OAI21XLTS U2296 ( .A0(n1630), .A1(n1590), .B0(n1589), .Y(n1595) );
XNOR2X1TS U2297 ( .A(n1584), .B(n1583), .Y(n5150) );
NAND2X1TS U2298 ( .A(n1582), .B(n1581), .Y(n1583) );
OAI21XLTS U2299 ( .A0(n1630), .A1(n1579), .B0(n1578), .Y(n1584) );
XNOR2X1TS U2300 ( .A(n1575), .B(n1574), .Y(n5147) );
NAND2X1TS U2301 ( .A(n1573), .B(n1572), .Y(n1574) );
OAI21XLTS U2302 ( .A0(n1630), .A1(n1570), .B0(n1569), .Y(n1575) );
XOR2X1TS U2303 ( .A(n1561), .B(n1560), .Y(n5141) );
NAND2X1TS U2304 ( .A(n1559), .B(n1558), .Y(n1560) );
XOR2X1TS U2305 ( .A(n1545), .B(n1544), .Y(n5129) );
XOR2X1TS U2306 ( .A(n1537), .B(n1536), .Y(n5122) );
XOR2X1TS U2307 ( .A(n1529), .B(n1528), .Y(n3688) );
XOR2X1TS U2308 ( .A(n1521), .B(n1520), .Y(n5113) );
XOR2X1TS U2309 ( .A(n1513), .B(n1512), .Y(n5109) );
XOR2X1TS U2310 ( .A(n1505), .B(n1504), .Y(n5103) );
XOR2X1TS U2311 ( .A(n1497), .B(n1496), .Y(n5097) );
XOR2X1TS U2312 ( .A(n1489), .B(n1488), .Y(n5091) );
XOR2X1TS U2313 ( .A(n1481), .B(n1480), .Y(n5085) );
XOR2X1TS U2314 ( .A(n1473), .B(n1472), .Y(n3696) );
XOR2X1TS U2315 ( .A(n1465), .B(n1464), .Y(n3702) );
XOR2X1TS U2316 ( .A(n1457), .B(n1456), .Y(n3708) );
XOR2X1TS U2317 ( .A(n1449), .B(n1448), .Y(n3714) );
XOR2X1TS U2318 ( .A(n1441), .B(n1440), .Y(n3720) );
XNOR2X1TS U2319 ( .A(n1420), .B(n1419), .Y(n3735) );
XNOR2X1TS U2320 ( .A(n1412), .B(n1411), .Y(n3741) );
INVX2TS U2321 ( .A(n1786), .Y(n1784) );
CMPR42X1TS U2322 ( .A(DP_OP_169J45_123_4229_n160), .B(
DP_OP_169J45_123_4229_n776), .C(DP_OP_169J45_123_4229_n820), .D(
DP_OP_169J45_123_4229_n792), .ICI(DP_OP_169J45_123_4229_n157), .S(
DP_OP_169J45_123_4229_n156), .ICO(DP_OP_169J45_123_4229_n154), .CO(
DP_OP_169J45_123_4229_n155) );
CMPR42X1TS U2323 ( .A(DP_OP_169J45_123_4229_n821), .B(
DP_OP_169J45_123_4229_n161), .C(DP_OP_169J45_123_4229_n793), .D(
DP_OP_169J45_123_4229_n165), .ICI(DP_OP_169J45_123_4229_n162), .S(
DP_OP_169J45_123_4229_n159), .ICO(DP_OP_169J45_123_4229_n157), .CO(
DP_OP_169J45_123_4229_n158) );
CMPR42X1TS U2324 ( .A(DP_OP_169J45_123_4229_n822), .B(
DP_OP_169J45_123_4229_n794), .C(DP_OP_169J45_123_4229_n166), .D(
DP_OP_169J45_123_4229_n170), .ICI(DP_OP_169J45_123_4229_n167), .S(
DP_OP_169J45_123_4229_n164), .ICO(DP_OP_169J45_123_4229_n162), .CO(
DP_OP_169J45_123_4229_n163) );
CMPR42X1TS U2325 ( .A(DP_OP_169J45_123_4229_n795), .B(
DP_OP_169J45_123_4229_n177), .C(DP_OP_169J45_123_4229_n171), .D(
DP_OP_169J45_123_4229_n178), .ICI(DP_OP_169J45_123_4229_n174), .S(
DP_OP_169J45_123_4229_n169), .ICO(DP_OP_169J45_123_4229_n167), .CO(
DP_OP_169J45_123_4229_n168) );
CMPR42X1TS U2326 ( .A(DP_OP_169J45_123_4229_n796), .B(
DP_OP_169J45_123_4229_n183), .C(DP_OP_169J45_123_4229_n184), .D(
DP_OP_169J45_123_4229_n179), .ICI(DP_OP_169J45_123_4229_n180), .S(
DP_OP_169J45_123_4229_n176), .ICO(DP_OP_169J45_123_4229_n174), .CO(
DP_OP_169J45_123_4229_n175) );
CMPR42X1TS U2327 ( .A(DP_OP_169J45_123_4229_n825), .B(
DP_OP_169J45_123_4229_n194), .C(DP_OP_169J45_123_4229_n185), .D(
DP_OP_169J45_123_4229_n192), .ICI(DP_OP_169J45_123_4229_n188), .S(
DP_OP_169J45_123_4229_n182), .ICO(DP_OP_169J45_123_4229_n180), .CO(
DP_OP_169J45_123_4229_n181) );
CMPR42X1TS U2328 ( .A(DP_OP_169J45_123_4229_n798), .B(
DP_OP_169J45_123_4229_n202), .C(DP_OP_169J45_123_4229_n200), .D(
DP_OP_169J45_123_4229_n193), .ICI(DP_OP_169J45_123_4229_n196), .S(
DP_OP_169J45_123_4229_n190), .ICO(DP_OP_169J45_123_4229_n188), .CO(
DP_OP_169J45_123_4229_n189) );
CMPR42X1TS U2329 ( .A(DP_OP_169J45_123_4229_n203), .B(
DP_OP_169J45_123_4229_n209), .C(DP_OP_169J45_123_4229_n210), .D(
DP_OP_169J45_123_4229_n201), .ICI(DP_OP_169J45_123_4229_n206), .S(
DP_OP_169J45_123_4229_n198), .ICO(DP_OP_169J45_123_4229_n196), .CO(
DP_OP_169J45_123_4229_n197) );
CMPR42X1TS U2330 ( .A(DP_OP_169J45_123_4229_n222), .B(
DP_OP_169J45_123_4229_n214), .C(DP_OP_169J45_123_4229_n219), .D(
DP_OP_169J45_123_4229_n211), .ICI(DP_OP_169J45_123_4229_n215), .S(
DP_OP_169J45_123_4229_n208), .ICO(DP_OP_169J45_123_4229_n206), .CO(
DP_OP_169J45_123_4229_n207) );
AO22XLTS U2331 ( .A0(n4881), .A1(Data_MY[40]), .B0(n4882), .B1(Op_MY[40]),
.Y(n622) );
AO22XLTS U2332 ( .A0(n4890), .A1(Data_MY[34]), .B0(n4885), .B1(Op_MY[34]),
.Y(n616) );
AO22XLTS U2333 ( .A0(n5047), .A1(n4956), .B0(n5043), .B1(Add_result[7]), .Y(
n572) );
AO22XLTS U2334 ( .A0(n5047), .A1(n4960), .B0(n5043), .B1(Add_result[9]), .Y(
n570) );
AO22XLTS U2335 ( .A0(n5047), .A1(n4964), .B0(n5043), .B1(Add_result[11]),
.Y(n568) );
AO22XLTS U2336 ( .A0(n5047), .A1(n4968), .B0(n5043), .B1(Add_result[13]),
.Y(n566) );
AO22XLTS U2337 ( .A0(n5047), .A1(n4972), .B0(n5043), .B1(Add_result[15]),
.Y(n564) );
AO22XLTS U2338 ( .A0(n5047), .A1(n4976), .B0(n5043), .B1(Add_result[17]),
.Y(n562) );
AO22XLTS U2339 ( .A0(n5047), .A1(n4980), .B0(n5043), .B1(Add_result[19]),
.Y(n560) );
AO22XLTS U2340 ( .A0(n5047), .A1(n4984), .B0(n5043), .B1(Add_result[21]),
.Y(n558) );
AO22XLTS U2341 ( .A0(n5047), .A1(n4988), .B0(n5043), .B1(Add_result[23]),
.Y(n556) );
AO22XLTS U2342 ( .A0(n5024), .A1(n3693), .B0(n753), .B1(Add_result[25]), .Y(
n554) );
AO22XLTS U2343 ( .A0(n5024), .A1(n3694), .B0(n753), .B1(Add_result[27]), .Y(
n552) );
AO22XLTS U2344 ( .A0(n5024), .A1(n4998), .B0(n753), .B1(Add_result[29]), .Y(
n550) );
AO22XLTS U2345 ( .A0(n5024), .A1(n5002), .B0(n753), .B1(Add_result[31]), .Y(
n548) );
AO22XLTS U2346 ( .A0(n5024), .A1(n5006), .B0(n753), .B1(Add_result[33]), .Y(
n546) );
AO22XLTS U2347 ( .A0(n5024), .A1(n5010), .B0(n753), .B1(Add_result[35]), .Y(
n544) );
AO22XLTS U2348 ( .A0(n5024), .A1(n5015), .B0(n753), .B1(Add_result[37]), .Y(
n542) );
AO22XLTS U2349 ( .A0(n5024), .A1(n5019), .B0(n753), .B1(Add_result[39]), .Y(
n540) );
AO22XLTS U2350 ( .A0(n5024), .A1(n5023), .B0(n5043), .B1(Add_result[41]),
.Y(n538) );
AO22XLTS U2351 ( .A0(n5024), .A1(n3750), .B0(n753), .B1(Add_result[43]), .Y(
n536) );
AO22XLTS U2352 ( .A0(n5024), .A1(n3764), .B0(n753), .B1(Add_result[45]), .Y(
n534) );
AO22XLTS U2353 ( .A0(n5024), .A1(n3765), .B0(n753), .B1(Add_result[47]), .Y(
n532) );
AO22XLTS U2354 ( .A0(n4887), .A1(Data_MY[18]), .B0(n4888), .B1(Op_MY[18]),
.Y(n600) );
AO22XLTS U2355 ( .A0(n4890), .A1(Data_MX[36]), .B0(n4877), .B1(Op_MX[36]),
.Y(n682) );
AO22XLTS U2356 ( .A0(n4884), .A1(Data_MX[33]), .B0(n4877), .B1(Op_MX[33]),
.Y(n679) );
AO22XLTS U2357 ( .A0(n4881), .A1(Data_MX[40]), .B0(n4877), .B1(Op_MX[40]),
.Y(n686) );
AO22XLTS U2358 ( .A0(n4881), .A1(Data_MX[45]), .B0(n4888), .B1(Op_MX[45]),
.Y(n691) );
AO22XLTS U2359 ( .A0(n4884), .A1(Data_MX[10]), .B0(n4882), .B1(Op_MX[10]),
.Y(n656) );
AO22XLTS U2360 ( .A0(n4881), .A1(Data_MX[51]), .B0(n4888), .B1(Op_MX[51]),
.Y(n697) );
AO22XLTS U2361 ( .A0(n4887), .A1(Data_MY[5]), .B0(n4888), .B1(Op_MY[5]), .Y(
n587) );
AO22XLTS U2362 ( .A0(n4881), .A1(Data_MY[51]), .B0(n4885), .B1(Op_MY[51]),
.Y(n633) );
AO22XLTS U2363 ( .A0(n4883), .A1(Data_MX[21]), .B0(n4879), .B1(Op_MX[21]),
.Y(n667) );
AO22XLTS U2364 ( .A0(n4887), .A1(Data_MY[13]), .B0(n4886), .B1(Op_MY[13]),
.Y(n595) );
AO22XLTS U2365 ( .A0(n4887), .A1(Data_MY[11]), .B0(n4886), .B1(Op_MY[11]),
.Y(n593) );
AO22XLTS U2366 ( .A0(n4890), .A1(Data_MY[2]), .B0(n4888), .B1(Op_MY[2]), .Y(
n584) );
AO22XLTS U2367 ( .A0(n4881), .A1(Data_MX[39]), .B0(n4877), .B1(Op_MX[39]),
.Y(n685) );
AO22XLTS U2368 ( .A0(n4883), .A1(Data_MX[3]), .B0(n4885), .B1(Op_MX[3]), .Y(
n649) );
AO22XLTS U2369 ( .A0(n4890), .A1(Data_MX[31]), .B0(n4877), .B1(Op_MX[31]),
.Y(n677) );
AO22XLTS U2370 ( .A0(n4881), .A1(Data_MX[37]), .B0(n4877), .B1(Op_MX[37]),
.Y(n683) );
AO22XLTS U2371 ( .A0(n4890), .A1(Data_MX[9]), .B0(n4882), .B1(Op_MX[9]), .Y(
n655) );
AO22XLTS U2372 ( .A0(n4884), .A1(Data_MX[24]), .B0(n4879), .B1(Op_MX[24]),
.Y(n670) );
AO22XLTS U2373 ( .A0(n4887), .A1(Data_MY[17]), .B0(n979), .B1(Op_MY[17]),
.Y(n599) );
AO22XLTS U2374 ( .A0(n4887), .A1(Data_MY[7]), .B0(n4886), .B1(Op_MY[7]), .Y(
n589) );
AO22XLTS U2375 ( .A0(n4887), .A1(Data_MY[19]), .B0(n4888), .B1(Op_MY[19]),
.Y(n601) );
AO22XLTS U2376 ( .A0(n4884), .A1(Data_MX[28]), .B0(n4879), .B1(Op_MX[28]),
.Y(n674) );
AO22XLTS U2377 ( .A0(n4883), .A1(Data_MX[30]), .B0(n4877), .B1(Op_MX[30]),
.Y(n676) );
AO22XLTS U2378 ( .A0(n4890), .A1(Data_MY[31]), .B0(n4885), .B1(Op_MY[31]),
.Y(n613) );
AO22XLTS U2379 ( .A0(n4890), .A1(Data_MY[49]), .B0(n4882), .B1(Op_MY[49]),
.Y(n631) );
AO22XLTS U2380 ( .A0(n4890), .A1(Data_MY[45]), .B0(n4882), .B1(Op_MY[45]),
.Y(n627) );
AO22XLTS U2381 ( .A0(n4883), .A1(Data_MY[29]), .B0(n4885), .B1(Op_MY[29]),
.Y(n611) );
AO22XLTS U2382 ( .A0(n4887), .A1(Data_MY[27]), .B0(n4888), .B1(n848), .Y(
n609) );
AO22XLTS U2383 ( .A0(n4880), .A1(Data_MX[63]), .B0(n4885), .B1(Op_MX[63]),
.Y(n645) );
AO22XLTS U2384 ( .A0(n4883), .A1(Data_MY[41]), .B0(n4882), .B1(Op_MY[41]),
.Y(n623) );
AO22XLTS U2385 ( .A0(n4890), .A1(Data_MY[36]), .B0(n4885), .B1(Op_MY[36]),
.Y(n618) );
AO22XLTS U2386 ( .A0(n4883), .A1(Data_MY[37]), .B0(n4885), .B1(Op_MY[37]),
.Y(n619) );
AO22XLTS U2387 ( .A0(n4883), .A1(Data_MX[34]), .B0(n4877), .B1(Op_MX[34]),
.Y(n680) );
AO22XLTS U2388 ( .A0(n4890), .A1(Data_MX[22]), .B0(n4879), .B1(Op_MX[22]),
.Y(n668) );
AO22XLTS U2389 ( .A0(n4890), .A1(Data_MX[13]), .B0(n4882), .B1(Op_MX[13]),
.Y(n659) );
AO22XLTS U2390 ( .A0(n4883), .A1(Data_MX[16]), .B0(n4882), .B1(Op_MX[16]),
.Y(n662) );
AO22XLTS U2391 ( .A0(n4884), .A1(Data_MX[19]), .B0(n4879), .B1(Op_MX[19]),
.Y(n665) );
AO22XLTS U2392 ( .A0(n4883), .A1(Data_MX[7]), .B0(n4885), .B1(Op_MX[7]), .Y(
n653) );
AO22XLTS U2393 ( .A0(n4881), .A1(Data_MX[49]), .B0(n4888), .B1(Op_MX[49]),
.Y(n695) );
AO22XLTS U2394 ( .A0(n5047), .A1(n4952), .B0(n5043), .B1(Add_result[5]), .Y(
n574) );
AO22XLTS U2395 ( .A0(n4881), .A1(Data_MX[1]), .B0(n4879), .B1(Op_MX[1]), .Y(
n647) );
AO22XLTS U2396 ( .A0(n4884), .A1(Data_MX[15]), .B0(n4877), .B1(Op_MX[15]),
.Y(n661) );
AO22XLTS U2397 ( .A0(n4884), .A1(Data_MX[6]), .B0(n4879), .B1(Op_MX[6]), .Y(
n652) );
AO22XLTS U2398 ( .A0(n4887), .A1(Data_MY[22]), .B0(n979), .B1(Op_MY[22]),
.Y(n604) );
AO22XLTS U2399 ( .A0(n4883), .A1(Data_MX[25]), .B0(n4879), .B1(Op_MX[25]),
.Y(n671) );
AO22XLTS U2400 ( .A0(n4890), .A1(Data_MX[18]), .B0(n4877), .B1(Op_MX[18]),
.Y(n664) );
AO22XLTS U2401 ( .A0(n4883), .A1(Data_MX[12]), .B0(n4882), .B1(Op_MX[12]),
.Y(n658) );
AO22XLTS U2402 ( .A0(n4890), .A1(Data_MX[4]), .B0(n4885), .B1(Op_MX[4]), .Y(
n650) );
AO22XLTS U2403 ( .A0(n4883), .A1(Data_MY[4]), .B0(n4888), .B1(Op_MY[4]), .Y(
n586) );
AO22XLTS U2404 ( .A0(n4890), .A1(Data_MX[27]), .B0(n4879), .B1(Op_MX[27]),
.Y(n673) );
AO22XLTS U2405 ( .A0(n4887), .A1(Data_MY[10]), .B0(n4886), .B1(Op_MY[10]),
.Y(n592) );
AO22XLTS U2406 ( .A0(n4883), .A1(Data_MX[32]), .B0(n4877), .B1(Op_MX[32]),
.Y(n678) );
AO22XLTS U2407 ( .A0(n4881), .A1(Data_MX[44]), .B0(n4888), .B1(Op_MX[44]),
.Y(n690) );
AO22XLTS U2408 ( .A0(n4881), .A1(Data_MX[47]), .B0(n4888), .B1(Op_MX[47]),
.Y(n693) );
AO22XLTS U2409 ( .A0(n4884), .A1(Data_MY[43]), .B0(n4882), .B1(Op_MY[43]),
.Y(n625) );
AO22XLTS U2410 ( .A0(n4883), .A1(Data_MY[47]), .B0(n4882), .B1(Op_MY[47]),
.Y(n629) );
AO22XLTS U2411 ( .A0(n4884), .A1(Data_MY[39]), .B0(n4882), .B1(Op_MY[39]),
.Y(n621) );
AO22XLTS U2412 ( .A0(n4890), .A1(Data_MY[35]), .B0(n4885), .B1(Op_MY[35]),
.Y(n617) );
AO22XLTS U2413 ( .A0(n4884), .A1(Data_MY[33]), .B0(n4885), .B1(Op_MY[33]),
.Y(n615) );
AO22XLTS U2414 ( .A0(n4884), .A1(Data_MX[35]), .B0(n4877), .B1(Op_MX[35]),
.Y(n681) );
AO22XLTS U2415 ( .A0(n4884), .A1(Data_MY[25]), .B0(n4888), .B1(Op_MY[25]),
.Y(n607) );
AO22XLTS U2416 ( .A0(n4887), .A1(Data_MY[26]), .B0(n4886), .B1(n898), .Y(
n608) );
AO22XLTS U2417 ( .A0(n4887), .A1(Data_MY[50]), .B0(n4885), .B1(Op_MY[50]),
.Y(n632) );
AO22XLTS U2418 ( .A0(n4887), .A1(Data_MY[28]), .B0(n4885), .B1(Op_MY[28]),
.Y(n610) );
NAND2X1TS U2419 ( .A(n2662), .B(n2661), .Y(DP_OP_169J45_123_4229_n147) );
OAI21XLTS U2420 ( .A0(n2891), .A1(n1054), .B0(n1046), .Y(n1047) );
OAI21XLTS U2421 ( .A0(n2834), .A1(n1203), .B0(n1049), .Y(n1050) );
OAI21XLTS U2422 ( .A0(n1060), .A1(n1059), .B0(n2981), .Y(n1058) );
OAI21XLTS U2423 ( .A0(n1068), .A1(n1067), .B0(n2981), .Y(n1066) );
OAI21XLTS U2424 ( .A0(n1078), .A1(n1077), .B0(n2981), .Y(n1076) );
OAI21XLTS U2425 ( .A0(n1088), .A1(n1087), .B0(n2981), .Y(n1086) );
OAI21XLTS U2426 ( .A0(n3501), .A1(n3500), .B0(n3659), .Y(n3499) );
OAI21XLTS U2427 ( .A0(n3512), .A1(n3511), .B0(n3659), .Y(n3510) );
OAI21XLTS U2428 ( .A0(n1113), .A1(n1112), .B0(n2981), .Y(n1111) );
OAI21XLTS U2429 ( .A0(n3522), .A1(n3521), .B0(n3659), .Y(n3520) );
OAI21XLTS U2430 ( .A0(n1123), .A1(n1122), .B0(n2981), .Y(n1121) );
OAI21XLTS U2431 ( .A0(n1133), .A1(n1132), .B0(n2981), .Y(n1131) );
OAI21XLTS U2432 ( .A0(n3547), .A1(n3546), .B0(n3659), .Y(n3545) );
OAI21XLTS U2433 ( .A0(n1180), .A1(n1179), .B0(n2981), .Y(n1178) );
OAI21XLTS U2434 ( .A0(n1193), .A1(n1192), .B0(n2981), .Y(n1191) );
OAI21XLTS U2435 ( .A0(n3557), .A1(n3556), .B0(n931), .Y(n3555) );
OAI21XLTS U2436 ( .A0(n1202), .A1(n1201), .B0(n2981), .Y(n1200) );
OAI21XLTS U2437 ( .A0(n3577), .A1(n3576), .B0(n3659), .Y(n3575) );
OAI21XLTS U2438 ( .A0(n3632), .A1(n3631), .B0(n3659), .Y(n3630) );
OAI21XLTS U2439 ( .A0(n3651), .A1(n3650), .B0(n3659), .Y(n3649) );
OAI21XLTS U2440 ( .A0(n3662), .A1(n3661), .B0(n3659), .Y(n3660) );
AO22XLTS U2441 ( .A0(n5080), .A1(P_Sgf[83]), .B0(n3465), .B1(n5079), .Y(n504) );
AO22XLTS U2442 ( .A0(n5080), .A1(P_Sgf[84]), .B0(n3465), .B1(n5077), .Y(n505) );
AO22XLTS U2443 ( .A0(n5080), .A1(P_Sgf[85]), .B0(n3465), .B1(n5075), .Y(n506) );
AO22XLTS U2444 ( .A0(n5080), .A1(P_Sgf[86]), .B0(n3465), .B1(n5073), .Y(n507) );
AO22X1TS U2445 ( .A0(n5127), .A1(P_Sgf[104]), .B0(n734), .B1(n3681), .Y(n520) );
AO22XLTS U2446 ( .A0(n4884), .A1(Data_MY[30]), .B0(n4885), .B1(n846), .Y(
n612) );
AO22XLTS U2447 ( .A0(n4883), .A1(Data_MY[42]), .B0(n4882), .B1(n847), .Y(
n624) );
AO22XLTS U2448 ( .A0(n4883), .A1(Data_MY[48]), .B0(n4882), .B1(n845), .Y(
n630) );
AO22XLTS U2449 ( .A0(n4881), .A1(Data_MX[46]), .B0(n4888), .B1(n844), .Y(
n692) );
XOR2X1TS U2450 ( .A(n1791), .B(n1790), .Y(Sgf_operation_ODD1_middle_N55) );
OAI21XLTS U2451 ( .A0(n3400), .A1(n1054), .B0(n1004), .Y(n1005) );
XOR2X1TS U2452 ( .A(n1748), .B(n1747), .Y(n765) );
XOR2X1TS U2453 ( .A(n1741), .B(n1740), .Y(n766) );
XOR2X1TS U2454 ( .A(n2025), .B(n2024), .Y(n767) );
XOR2X1TS U2455 ( .A(n1761), .B(n1760), .Y(n768) );
XOR2X1TS U2456 ( .A(n2035), .B(n2034), .Y(n769) );
XOR2X1TS U2457 ( .A(n2048), .B(n2047), .Y(n771) );
CLKXOR2X2TS U2458 ( .A(n848), .B(Op_MY[0]), .Y(n1680) );
XOR2X1TS U2459 ( .A(n1890), .B(Op_MX[25]), .Y(n784) );
XOR2X1TS U2460 ( .A(n2234), .B(n2233), .Y(n785) );
XOR2X1TS U2461 ( .A(n1722), .B(n935), .Y(n787) );
OA21XLTS U2462 ( .A0(n2244), .A1(n900), .B0(n899), .Y(n788) );
INVX6TS U2463 ( .A(n1680), .Y(n2659) );
NAND2X6TS U2464 ( .A(n2483), .B(n2084), .Y(n2482) );
NAND2X6TS U2465 ( .A(n2453), .B(n1938), .Y(n2450) );
NAND2X6TS U2466 ( .A(n2394), .B(n1912), .Y(n2391) );
NAND2X6TS U2467 ( .A(n2365), .B(n2142), .Y(n2364) );
NAND2X6TS U2468 ( .A(n1900), .B(n2303), .Y(n2305) );
NOR2X1TS U2469 ( .A(n788), .B(n852), .Y(n797) );
CLKINVX6TS U2470 ( .A(n762), .Y(n4892) );
INVX2TS U2471 ( .A(n796), .Y(n798) );
INVX6TS U2472 ( .A(n796), .Y(n799) );
INVX2TS U2473 ( .A(n794), .Y(n805) );
INVX6TS U2474 ( .A(n794), .Y(n806) );
INVX2TS U2475 ( .A(n1680), .Y(n810) );
NOR2X1TS U2476 ( .A(n4844), .B(n4434), .Y(mult_x_24_n602) );
ADDHX1TS U2477 ( .A(n4761), .B(n4760), .CO(n4787), .S(mult_x_24_n575) );
ADDHX1TS U2478 ( .A(n3441), .B(n3440), .CO(n3408), .S(mult_x_23_n414) );
ADDHX1TS U2479 ( .A(n4713), .B(n4712), .CO(n4731), .S(mult_x_24_n536) );
ADDHX1TS U2480 ( .A(n3433), .B(n3432), .CO(n3444), .S(mult_x_23_n510) );
ADDHX1TS U2481 ( .A(n3409), .B(n3408), .CO(n3269), .S(mult_x_23_n403) );
ADDHX1TS U2482 ( .A(n3418), .B(n3417), .CO(n3423), .S(mult_x_23_n463) );
ADDHX1TS U2483 ( .A(n4671), .B(n4670), .CO(n4686), .S(mult_x_24_n468) );
ADDHX1TS U2484 ( .A(n4732), .B(n4731), .CO(n4739), .S(mult_x_24_n528) );
ADDHX1TS U2485 ( .A(n4788), .B(n4787), .CO(n4795), .S(mult_x_24_n570) );
ADDHX1TS U2486 ( .A(n3439), .B(n3438), .CO(n3417), .S(mult_x_23_n471) );
ADDHX1TS U2487 ( .A(n4067), .B(n4066), .CO(n4670), .S(mult_x_24_n479) );
OR2X4TS U2488 ( .A(FSM_selector_B[1]), .B(n5388), .Y(n4531) );
XOR2X1TS U2489 ( .A(n1750), .B(n1762), .Y(n1756) );
OAI22X1TS U2490 ( .A0(n2214), .A1(n2571), .B0(n805), .B1(n2213), .Y(n2220)
);
OAI22X1TS U2491 ( .A0(n805), .A1(n2212), .B0(n2571), .B1(n2213), .Y(n2223)
);
OAI22X1TS U2492 ( .A0(n2449), .A1(n803), .B0(n2447), .B1(n867), .Y(
DP_OP_169J45_123_4229_n993) );
OAI22X1TS U2493 ( .A0(n2447), .A1(n2450), .B0(n2446), .B1(n867), .Y(
DP_OP_169J45_123_4229_n992) );
OAI22X1TS U2494 ( .A0(n2154), .A1(n2394), .B0(n802), .B1(n2153), .Y(n2160)
);
OAI22X1TS U2495 ( .A0(n2366), .A1(n2365), .B0(n808), .B1(n2363), .Y(
DP_OP_169J45_123_4229_n907) );
CLKINVX3TS U2496 ( .A(n733), .Y(n811) );
OAI22X1TS U2497 ( .A0(n801), .A1(n2297), .B0(n2296), .B1(n868), .Y(
DP_OP_169J45_123_4229_n844) );
OAI22X1TS U2498 ( .A0(n801), .A1(n2296), .B0(n2295), .B1(n868), .Y(
DP_OP_169J45_123_4229_n843) );
BUFX6TS U2499 ( .A(n915), .Y(n3343) );
BUFX6TS U2500 ( .A(n942), .Y(n3313) );
BUFX6TS U2501 ( .A(n943), .Y(n3196) );
BUFX6TS U2502 ( .A(n938), .Y(n3309) );
XNOR2X1TS U2503 ( .A(n1979), .B(n1978), .Y(n1983) );
OAI31X1TS U2504 ( .A0(n913), .A1(Op_MX[29]), .A2(n3245), .B0(n1212), .Y(
n3238) );
ADDHX4TS U2505 ( .A(n4892), .B(Op_MY[0]), .CO(n3579), .S(n4749) );
BUFX4TS U2506 ( .A(n5478), .Y(n5456) );
BUFX4TS U2507 ( .A(n5478), .Y(n5458) );
NOR4X1TS U2508 ( .A(n847), .B(Op_MY[43]), .C(Op_MY[44]), .D(Op_MY[45]), .Y(
n4898) );
NOR4X1TS U2509 ( .A(n898), .B(n848), .C(Op_MY[28]), .D(Op_MY[29]), .Y(n4894)
);
NOR4X1TS U2510 ( .A(Op_MY[38]), .B(Op_MY[39]), .C(Op_MY[40]), .D(Op_MY[41]),
.Y(n4899) );
NOR4X1TS U2511 ( .A(Op_MY[34]), .B(Op_MY[35]), .C(Op_MY[36]), .D(Op_MY[37]),
.Y(n4900) );
NOR4X1TS U2512 ( .A(n846), .B(Op_MY[31]), .C(Op_MY[32]), .D(Op_MY[33]), .Y(
n4901) );
NOR4X1TS U2513 ( .A(Op_MY[46]), .B(Op_MY[47]), .C(n845), .D(Op_MY[49]), .Y(
n4905) );
NOR4X1TS U2514 ( .A(n763), .B(Op_MX[15]), .C(Op_MX[16]), .D(
DP_OP_169J45_123_4229_n2458), .Y(n4923) );
OAI22X1TS U2515 ( .A0(n801), .A1(n2302), .B0(n2303), .B1(n2300), .Y(
DP_OP_169J45_123_4229_n847) );
OAI22X1TS U2516 ( .A0(n801), .A1(n2304), .B0(n2303), .B1(n2302), .Y(
DP_OP_169J45_123_4229_n848) );
BUFX4TS U2517 ( .A(n5470), .Y(n5477) );
BUFX4TS U2518 ( .A(n744), .Y(n5459) );
XNOR2X1TS U2519 ( .A(n2641), .B(n897), .Y(n2643) );
XNOR2X1TS U2520 ( .A(n2641), .B(n895), .Y(n2614) );
NOR2X4TS U2521 ( .A(FS_Module_state_reg[3]), .B(n4875), .Y(n4941) );
BUFX4TS U2522 ( .A(n3683), .Y(n5470) );
BUFX4TS U2523 ( .A(n3683), .Y(n5465) );
NAND2X1TS U2524 ( .A(n1986), .B(n1985), .Y(n2077) );
BUFX4TS U2525 ( .A(n5473), .Y(n5469) );
NOR3X2TS U2526 ( .A(n5359), .B(FS_Module_state_reg[0]), .C(
FS_Module_state_reg[3]), .Y(n3770) );
BUFX4TS U2527 ( .A(n5473), .Y(n5472) );
BUFX4TS U2528 ( .A(n5473), .Y(n5468) );
BUFX4TS U2529 ( .A(n5473), .Y(n5474) );
BUFX4TS U2530 ( .A(n5473), .Y(n5467) );
BUFX3TS U2531 ( .A(n3683), .Y(n3684) );
BUFX6TS U2532 ( .A(n5348), .Y(n4438) );
BUFX6TS U2533 ( .A(n5347), .Y(n4471) );
INVX6TS U2534 ( .A(n4888), .Y(n4883) );
CLKINVX6TS U2535 ( .A(n4888), .Y(n4890) );
INVX6TS U2536 ( .A(n4888), .Y(n4884) );
BUFX4TS U2537 ( .A(n5473), .Y(n5460) );
BUFX4TS U2538 ( .A(n5473), .Y(n5471) );
BUFX4TS U2539 ( .A(n5473), .Y(n5461) );
CLKINVX6TS U2540 ( .A(n5200), .Y(n5206) );
CLKINVX6TS U2541 ( .A(n5200), .Y(n5204) );
CLKINVX6TS U2542 ( .A(n979), .Y(n4881) );
OAI21XLTS U2543 ( .A0(n2905), .A1(n2904), .B0(n3015), .Y(n2903) );
OAI21XLTS U2544 ( .A0(n2917), .A1(n2916), .B0(n976), .Y(n2915) );
INVX2TS U2545 ( .A(n2596), .Y(n813) );
INVX4TS U2546 ( .A(n813), .Y(n814) );
XOR2X1TS U2547 ( .A(n2125), .B(n1767), .Y(n2596) );
BUFX6TS U2548 ( .A(n5335), .Y(n3384) );
BUFX6TS U2549 ( .A(n978), .Y(n5335) );
BUFX6TS U2550 ( .A(n5345), .Y(n4508) );
BUFX6TS U2551 ( .A(n5343), .Y(n4765) );
BUFX6TS U2552 ( .A(n5334), .Y(n3391) );
BUFX6TS U2553 ( .A(n963), .Y(n5334) );
BUFX6TS U2554 ( .A(n3784), .Y(n3871) );
INVX2TS U2555 ( .A(n729), .Y(n4682) );
OAI21XLTS U2556 ( .A0(n4755), .A1(n4062), .B0(n729), .Y(n4061) );
BUFX6TS U2557 ( .A(n736), .Y(n3865) );
OAI21XLTS U2558 ( .A0(n3590), .A1(n4754), .B0(n763), .Y(n4753) );
INVX3TS U2559 ( .A(n5200), .Y(n5202) );
BUFX6TS U2560 ( .A(n951), .Y(n3220) );
BUFX4TS U2561 ( .A(n4888), .Y(n4886) );
INVX4TS U2562 ( .A(n788), .Y(n815) );
INVX4TS U2563 ( .A(n785), .Y(n816) );
INVX4TS U2564 ( .A(n773), .Y(n817) );
INVX4TS U2565 ( .A(n787), .Y(n818) );
INVX4TS U2566 ( .A(n784), .Y(n819) );
INVX4TS U2567 ( .A(n780), .Y(n820) );
INVX4TS U2568 ( .A(n786), .Y(n821) );
INVX4TS U2569 ( .A(n782), .Y(n822) );
INVX4TS U2570 ( .A(n778), .Y(n823) );
INVX4TS U2571 ( .A(n777), .Y(n824) );
INVX4TS U2572 ( .A(n774), .Y(n825) );
INVX4TS U2573 ( .A(n781), .Y(n826) );
INVX4TS U2574 ( .A(n776), .Y(n827) );
INVX4TS U2575 ( .A(n779), .Y(n828) );
INVX4TS U2576 ( .A(n783), .Y(n829) );
INVX4TS U2577 ( .A(n775), .Y(n830) );
INVX4TS U2578 ( .A(n770), .Y(n831) );
INVX4TS U2579 ( .A(n772), .Y(n832) );
INVX4TS U2580 ( .A(n769), .Y(n833) );
INVX4TS U2581 ( .A(n768), .Y(n834) );
INVX4TS U2582 ( .A(n771), .Y(n835) );
INVX4TS U2583 ( .A(n765), .Y(n836) );
INVX4TS U2584 ( .A(n767), .Y(n837) );
INVX2TS U2585 ( .A(n2299), .Y(n838) );
INVX2TS U2586 ( .A(n838), .Y(n839) );
INVX4TS U2587 ( .A(n766), .Y(n840) );
AOI21X2TS U2588 ( .A0(n841), .A1(Sgf_normalized_result[2]), .B0(
Sgf_normalized_result[4]), .Y(n4951) );
NAND2X1TS U2589 ( .A(Sgf_normalized_result[30]), .B(n4999), .Y(n5001) );
NAND2X1TS U2590 ( .A(Sgf_normalized_result[32]), .B(n5003), .Y(n5005) );
NAND2X1TS U2591 ( .A(Sgf_normalized_result[34]), .B(n5007), .Y(n5009) );
NAND2X1TS U2592 ( .A(Sgf_normalized_result[36]), .B(n5012), .Y(n5014) );
NAND2X1TS U2593 ( .A(Sgf_normalized_result[38]), .B(n5016), .Y(n5018) );
NAND2X1TS U2594 ( .A(Sgf_normalized_result[42]), .B(n5026), .Y(n5025) );
NAND2X1TS U2595 ( .A(Sgf_normalized_result[44]), .B(n5029), .Y(n5028) );
BUFX4TS U2596 ( .A(n5346), .Y(n4638) );
BUFX4TS U2597 ( .A(n5353), .Y(n4607) );
BUFX4TS U2598 ( .A(n5369), .Y(n4509) );
BUFX4TS U2599 ( .A(n5371), .Y(n4648) );
BUFX4TS U2600 ( .A(n5372), .Y(n4459) );
BUFX4TS U2601 ( .A(n5374), .Y(n4630) );
BUFX4TS U2602 ( .A(n5377), .Y(n4415) );
BUFX4TS U2603 ( .A(n5379), .Y(n4429) );
INVX2TS U2604 ( .A(n790), .Y(n841) );
ADDHXLTS U2605 ( .A(Op_MY[26]), .B(n3478), .CO(n3479), .S(n4837) );
OAI2BB2X2TS U2606 ( .B0(Op_MX[36]), .B1(Op_MX[35]), .A0N(Op_MX[35]), .A1N(
Op_MX[36]), .Y(n2794) );
NOR4X1TS U2607 ( .A(Op_MX[34]), .B(Op_MX[35]), .C(Op_MX[36]), .D(Op_MX[37]),
.Y(n4926) );
OAI2BB2X2TS U2608 ( .B0(Op_MX[33]), .B1(Op_MX[32]), .A0N(Op_MX[32]), .A1N(
Op_MX[33]), .Y(n1142) );
NOR4X1TS U2609 ( .A(Op_MX[30]), .B(Op_MX[31]), .C(Op_MX[32]), .D(Op_MX[33]),
.Y(n4927) );
OAI2BB2X2TS U2610 ( .B0(Op_MX[48]), .B1(Op_MX[47]), .A0N(Op_MX[47]), .A1N(
Op_MX[48]), .Y(n3156) );
NOR4X1TS U2611 ( .A(n844), .B(Op_MX[47]), .C(Op_MX[48]), .D(Op_MX[49]), .Y(
n4931) );
AOI2BB2X2TS U2612 ( .B0(Op_MX[40]), .B1(n5335), .A0N(n978), .A1N(Op_MX[40]),
.Y(n1022) );
NOR4X1TS U2613 ( .A(Op_MX[38]), .B(Op_MX[39]), .C(Op_MX[40]), .D(Op_MX[41]),
.Y(n4925) );
NOR2X2TS U2614 ( .A(Op_MX[45]), .B(Op_MX[18]), .Y(n1919) );
OAI2BB2X2TS U2615 ( .B0(Op_MX[45]), .B1(Op_MX[44]), .A0N(Op_MX[44]), .A1N(
Op_MX[45]), .Y(n2741) );
NOR4X1TS U2616 ( .A(Op_MX[42]), .B(n843), .C(Op_MX[44]), .D(Op_MX[45]), .Y(
n4924) );
OAI2BB2X2TS U2617 ( .B0(Op_MX[42]), .B1(Op_MX[41]), .A0N(Op_MX[41]), .A1N(
Op_MX[42]), .Y(n2761) );
NOR2X1TS U2618 ( .A(Op_MX[15]), .B(Op_MX[42]), .Y(n1952) );
OAI2BB2X2TS U2619 ( .B0(n5452), .B1(Op_MX[10]), .A0N(Op_MX[10]), .A1N(n4782),
.Y(n4036) );
AO22X2TS U2620 ( .A0(Op_MX[50]), .A1(n908), .B0(Op_MX[51]), .B1(n3402), .Y(
n3268) );
NOR2X2TS U2621 ( .A(Op_MX[51]), .B(Op_MX[24]), .Y(n1883) );
NOR4X1TS U2622 ( .A(Op_MX[50]), .B(Op_MX[51]), .C(Op_MX[62]), .D(Op_MX[61]),
.Y(n4930) );
XNOR2X4TS U2623 ( .A(Op_MY[32]), .B(Op_MY[5]), .Y(n2013) );
OAI21XLTS U2624 ( .A0(Op_MY[33]), .A1(Op_MY[6]), .B0(Op_MY[5]), .Y(n2022) );
NOR4X1TS U2625 ( .A(Op_MY[2]), .B(Op_MY[3]), .C(Op_MY[4]), .D(Op_MY[5]), .Y(
n4912) );
NOR4X1TS U2626 ( .A(Op_MY[50]), .B(Op_MY[51]), .C(Op_MY[52]), .D(Op_MY[61]),
.Y(n4904) );
NOR4X1TS U2627 ( .A(Op_MX[18]), .B(Op_MX[19]), .C(n730), .D(Op_MX[21]), .Y(
n4922) );
XNOR2X4TS U2628 ( .A(Op_MY[40]), .B(Op_MY[13]), .Y(n2082) );
OAI21XLTS U2629 ( .A0(Op_MY[41]), .A1(Op_MY[14]), .B0(Op_MY[13]), .Y(n1940)
);
OAI21XLTS U2630 ( .A0(Op_MY[39]), .A1(Op_MY[12]), .B0(Op_MY[11]), .Y(n1932)
);
NOR2X2TS U2631 ( .A(Op_MX[12]), .B(Op_MX[39]), .Y(n2087) );
NOR2X2TS U2632 ( .A(Op_MX[3]), .B(Op_MX[30]), .Y(n1764) );
NOR4X1TS U2633 ( .A(n731), .B(Op_MX[3]), .C(Op_MX[4]), .D(n4913), .Y(n4938)
);
NOR2X2TS U2634 ( .A(Op_MX[31]), .B(Op_MX[4]), .Y(n1737) );
NAND2X1TS U2635 ( .A(Op_MX[37]), .B(Op_MX[10]), .Y(n1992) );
NAND2X1TS U2636 ( .A(Op_MX[9]), .B(Op_MX[36]), .Y(n2053) );
NOR4X1TS U2637 ( .A(Op_MX[6]), .B(Op_MX[7]), .C(n4914), .D(Op_MX[9]), .Y(
n4937) );
NOR4X1TS U2638 ( .A(Op_MX[22]), .B(n729), .C(Op_MX[24]), .D(Op_MX[25]), .Y(
n4921) );
INVX2TS U2639 ( .A(n793), .Y(n843) );
XNOR2X4TS U2640 ( .A(Op_MY[44]), .B(Op_MY[17]), .Y(n2174) );
OAI21XLTS U2641 ( .A0(Op_MY[45]), .A1(Op_MY[18]), .B0(Op_MY[17]), .Y(n1914)
);
INVX2TS U2642 ( .A(n792), .Y(n844) );
XNOR2X4TS U2643 ( .A(Op_MY[34]), .B(Op_MY[7]), .Y(n2102) );
XNOR2X4TS U2644 ( .A(Op_MY[46]), .B(Op_MY[19]), .Y(n2135) );
NOR3X2TS U2645 ( .A(Op_MX[28]), .B(Op_MX[27]), .C(mult_x_23_n871), .Y(n1056)
);
NOR4X1TS U2646 ( .A(Op_MX[26]), .B(Op_MX[27]), .C(Op_MX[28]), .D(Op_MX[29]),
.Y(n4920) );
NAND2X1TS U2647 ( .A(Op_MX[3]), .B(Op_MX[30]), .Y(n1765) );
XOR2XLTS U2648 ( .A(Op_MY[41]), .B(Op_MY[40]), .Y(n1936) );
INVX2TS U2649 ( .A(n3224), .Y(n845) );
NOR2XLTS U2650 ( .A(Op_MY[44]), .B(Op_MY[17]), .Y(n1904) );
INVX2TS U2651 ( .A(n3203), .Y(n847) );
NOR2XLTS U2652 ( .A(Op_MY[46]), .B(Op_MY[19]), .Y(n2133) );
XOR2X1TS U2653 ( .A(Op_MY[31]), .B(Op_MY[4]), .Y(n1728) );
OAI21XLTS U2654 ( .A0(Op_MY[31]), .A1(Op_MY[4]), .B0(Op_MY[3]), .Y(n1733) );
XOR2XLTS U2655 ( .A(Op_MY[49]), .B(n845), .Y(n1855) );
XOR2X1TS U2656 ( .A(Op_MY[45]), .B(Op_MY[18]), .Y(n1909) );
XOR2XLTS U2657 ( .A(Op_MY[44]), .B(Op_MY[45]), .Y(n1910) );
INVX4TS U2658 ( .A(n3245), .Y(n848) );
INVX2TS U2659 ( .A(n2331), .Y(n849) );
INVX2TS U2660 ( .A(DP_OP_169J45_123_4229_n86), .Y(n851) );
CLKINVX6TS U2661 ( .A(n851), .Y(n852) );
CLKINVX6TS U2662 ( .A(n851), .Y(n853) );
INVX6TS U2663 ( .A(n1682), .Y(n854) );
NAND2X1TS U2664 ( .A(n912), .B(n1684), .Y(n1682) );
INVX4TS U2665 ( .A(n1682), .Y(n2660) );
NAND2X1TS U2666 ( .A(Op_MY[37]), .B(n3366), .Y(n856) );
NAND2X1TS U2667 ( .A(Op_MY[36]), .B(n758), .Y(n857) );
NOR4X1TS U2668 ( .A(Op_MY[14]), .B(Op_MY[15]), .C(Op_MY[16]), .D(Op_MY[17]),
.Y(n4897) );
OAI21X1TS U2669 ( .A0(n2244), .A1(n1919), .B0(n1918), .Y(n1924) );
OAI21X1TS U2670 ( .A0(n2244), .A1(n2243), .B0(n2242), .Y(n2247) );
OAI2BB2X2TS U2671 ( .B0(n4682), .B1(Op_MX[22]), .A0N(Op_MX[22]), .A1N(n4674),
.Y(n3916) );
NAND2X1TS U2672 ( .A(n858), .B(n859), .Y(n4005) );
NAND2X1TS U2673 ( .A(Op_MX[13]), .B(n4744), .Y(n858) );
NAND2X1TS U2674 ( .A(n791), .B(n763), .Y(n859) );
OAI2BB2X2TS U2675 ( .B0(n4174), .B1(Op_MX[16]), .A0N(Op_MX[16]), .A1N(n4726),
.Y(n3973) );
OAI2BB2X2TS U2676 ( .B0(n4125), .B1(Op_MX[19]), .A0N(Op_MX[19]), .A1N(n4699),
.Y(n3948) );
BUFX4TS U2677 ( .A(n5478), .Y(n5454) );
OAI22X2TS U2678 ( .A0(beg_FSM), .A1(n5473), .B0(ack_FSM), .B1(n3898), .Y(
n4873) );
NOR2X2TS U2679 ( .A(Op_MX[38]), .B(n4915), .Y(n2085) );
OAI2BB2X2TS U2680 ( .B0(n929), .B1(Op_MX[7]), .A0N(Op_MX[7]), .A1N(n4516),
.Y(n3581) );
CLKBUFX2TS U2681 ( .A(n2542), .Y(n860) );
OAI22X1TS U2682 ( .A0(n2530), .A1(n2542), .B0(n2529), .B1(n875), .Y(
DP_OP_169J45_123_4229_n1076) );
OAI22X1TS U2683 ( .A0(n2529), .A1(n2542), .B0(n2528), .B1(n876), .Y(
DP_OP_169J45_123_4229_n1075) );
OAI22X1TS U2684 ( .A0(n2531), .A1(n2542), .B0(n2530), .B1(n875), .Y(
DP_OP_169J45_123_4229_n1077) );
OAI22X1TS U2685 ( .A0(n2533), .A1(n2542), .B0(n2532), .B1(n876), .Y(
DP_OP_169J45_123_4229_n1079) );
OAI22X1TS U2686 ( .A0(n2534), .A1(n2542), .B0(n2533), .B1(n875), .Y(
DP_OP_169J45_123_4229_n1080) );
OAI22X1TS U2687 ( .A0(n2535), .A1(n2542), .B0(n2534), .B1(n876), .Y(
DP_OP_169J45_123_4229_n1081) );
OAI22X1TS U2688 ( .A0(n2536), .A1(n2542), .B0(n2535), .B1(n875), .Y(
DP_OP_169J45_123_4229_n1082) );
OAI22X1TS U2689 ( .A0(n2538), .A1(n876), .B0(n2540), .B1(n2542), .Y(
DP_OP_169J45_123_4229_n1085) );
OAI22X1TS U2690 ( .A0(n2537), .A1(n2542), .B0(n2536), .B1(n875), .Y(
DP_OP_169J45_123_4229_n1083) );
OAI22X1TS U2691 ( .A0(n2538), .A1(n2542), .B0(n2537), .B1(n876), .Y(
DP_OP_169J45_123_4229_n1084) );
OAI22X1TS U2692 ( .A0(n2540), .A1(n875), .B0(n2544), .B1(n2542), .Y(
DP_OP_169J45_123_4229_n1086) );
OAI22X1TS U2693 ( .A0(n2544), .A1(n874), .B0(n2542), .B1(n2541), .Y(
DP_OP_169J45_123_4229_n1087) );
OAI22X1TS U2694 ( .A0(n2542), .A1(n2210), .B0(n874), .B1(n2541), .Y(n2218)
);
NAND2X6TS U2695 ( .A(n874), .B(n2110), .Y(n2542) );
AOI2BB2X2TS U2696 ( .B0(Op_MX[49]), .B1(n3326), .A0N(n975), .A1N(Op_MX[49]),
.Y(n1000) );
CLKINVX6TS U2697 ( .A(n734), .Y(n5127) );
BUFX4TS U2698 ( .A(n5354), .Y(n4434) );
BUFX4TS U2699 ( .A(n5349), .Y(n4621) );
BUFX4TS U2700 ( .A(n5344), .Y(n4781) );
CLKINVX6TS U2701 ( .A(n4892), .Y(n4779) );
BUFX6TS U2702 ( .A(n736), .Y(n3884) );
BUFX6TS U2703 ( .A(n5453), .Y(n3659) );
NAND2X1TS U2704 ( .A(Sgf_normalized_result[46]), .B(n5032), .Y(n5031) );
NAND2X1TS U2705 ( .A(Sgf_normalized_result[40]), .B(n5020), .Y(n5022) );
CLKBUFX2TS U2706 ( .A(n2632), .Y(n861) );
OAI22X1TS U2707 ( .A0(n2606), .A1(n861), .B0(n2605), .B1(n887), .Y(
DP_OP_169J45_123_4229_n1152) );
OAI22X1TS U2708 ( .A0(n2608), .A1(n861), .B0(n2607), .B1(n887), .Y(
DP_OP_169J45_123_4229_n1154) );
OAI22X1TS U2709 ( .A0(n2607), .A1(n861), .B0(n2606), .B1(n887), .Y(
DP_OP_169J45_123_4229_n1153) );
OAI22X1TS U2710 ( .A0(n2610), .A1(n861), .B0(n2609), .B1(n887), .Y(
DP_OP_169J45_123_4229_n1156) );
OAI22X1TS U2711 ( .A0(n2611), .A1(n2632), .B0(n2610), .B1(n887), .Y(
DP_OP_169J45_123_4229_n1157) );
OAI22X1TS U2712 ( .A0(n2609), .A1(n2632), .B0(n2608), .B1(n887), .Y(
DP_OP_169J45_123_4229_n1155) );
OAI22X1TS U2713 ( .A0(n2612), .A1(n2632), .B0(n2611), .B1(n887), .Y(
DP_OP_169J45_123_4229_n1158) );
OAI22X1TS U2714 ( .A0(n2613), .A1(n2632), .B0(n2612), .B1(n887), .Y(
DP_OP_169J45_123_4229_n1159) );
OAI22X1TS U2715 ( .A0(n2614), .A1(n887), .B0(n2632), .B1(n2615), .Y(
DP_OP_169J45_123_4229_n1161) );
OAI22X1TS U2716 ( .A0(n2632), .A1(n2616), .B0(n2615), .B1(n887), .Y(
DP_OP_169J45_123_4229_n1162) );
OAI22X1TS U2717 ( .A0(n2632), .A1(n2617), .B0(n2616), .B1(n887), .Y(
DP_OP_169J45_123_4229_n1163) );
OAI22X1TS U2718 ( .A0(n2632), .A1(n2618), .B0(n2617), .B1(n887), .Y(
DP_OP_169J45_123_4229_n1164) );
OAI22X1TS U2719 ( .A0(n2632), .A1(n2619), .B0(n2618), .B1(n887), .Y(
DP_OP_169J45_123_4229_n1165) );
OAI22X1TS U2720 ( .A0(n2632), .A1(n2620), .B0(n2619), .B1(n887), .Y(
DP_OP_169J45_123_4229_n1166) );
OAI22X1TS U2721 ( .A0(n2632), .A1(n2623), .B0(n2622), .B1(n887), .Y(
DP_OP_169J45_123_4229_n1169) );
OAI22X1TS U2722 ( .A0(n2632), .A1(n2621), .B0(n2620), .B1(n887), .Y(
DP_OP_169J45_123_4229_n1167) );
OAI22X1TS U2723 ( .A0(n2632), .A1(n2622), .B0(n2621), .B1(n887), .Y(
DP_OP_169J45_123_4229_n1168) );
OAI22X1TS U2724 ( .A0(n2632), .A1(n2630), .B0(n2628), .B1(n887), .Y(
DP_OP_169J45_123_4229_n1174) );
OAI22X1TS U2725 ( .A0(n2632), .A1(n2626), .B0(n2625), .B1(n887), .Y(
DP_OP_169J45_123_4229_n1172) );
OAI22X1TS U2726 ( .A0(n2632), .A1(n2628), .B0(n2626), .B1(n887), .Y(
DP_OP_169J45_123_4229_n1173) );
NAND2X6TS U2727 ( .A(n1756), .B(n2629), .Y(n2632) );
CLKBUFX2TS U2728 ( .A(n2657), .Y(n862) );
OAI22X1TS U2729 ( .A0(n2634), .A1(n862), .B0(n2633), .B1(n2659), .Y(
DP_OP_169J45_123_4229_n1182) );
OAI22X1TS U2730 ( .A0(n2633), .A1(n862), .B0(DP_OP_169J45_123_4229_n1180),
.B1(n2659), .Y(DP_OP_169J45_123_4229_n1181) );
OAI22X1TS U2731 ( .A0(n2635), .A1(n862), .B0(n2634), .B1(n2659), .Y(
DP_OP_169J45_123_4229_n1183) );
OAI22X1TS U2732 ( .A0(n2637), .A1(n862), .B0(n2636), .B1(n2659), .Y(
DP_OP_169J45_123_4229_n1185) );
OAI22X1TS U2733 ( .A0(n2638), .A1(n2657), .B0(n2637), .B1(n2659), .Y(
DP_OP_169J45_123_4229_n1186) );
OAI22X1TS U2734 ( .A0(n2640), .A1(n2657), .B0(n2639), .B1(n2659), .Y(
DP_OP_169J45_123_4229_n1188) );
OAI22X1TS U2735 ( .A0(n2639), .A1(n2657), .B0(n2638), .B1(n2659), .Y(
DP_OP_169J45_123_4229_n1187) );
OAI22X1TS U2736 ( .A0(n2642), .A1(n2659), .B0(n2643), .B1(n2657), .Y(
DP_OP_169J45_123_4229_n1190) );
OAI22X1TS U2737 ( .A0(n2643), .A1(n2659), .B0(n2644), .B1(n2657), .Y(
DP_OP_169J45_123_4229_n1191) );
OAI22X1TS U2738 ( .A0(n2645), .A1(n2657), .B0(n2644), .B1(n2659), .Y(
DP_OP_169J45_123_4229_n1192) );
OAI22X1TS U2739 ( .A0(n2646), .A1(n2657), .B0(n2645), .B1(n2659), .Y(
DP_OP_169J45_123_4229_n1193) );
OAI22X1TS U2740 ( .A0(n2647), .A1(n2657), .B0(n2646), .B1(n2659), .Y(
DP_OP_169J45_123_4229_n1194) );
OAI22X1TS U2741 ( .A0(n2648), .A1(n2657), .B0(n2647), .B1(n2659), .Y(
DP_OP_169J45_123_4229_n1195) );
OAI22X1TS U2742 ( .A0(n2651), .A1(n2657), .B0(n2650), .B1(n2659), .Y(
DP_OP_169J45_123_4229_n1198) );
OAI22X1TS U2743 ( .A0(n2650), .A1(n2657), .B0(n2649), .B1(n2659), .Y(
DP_OP_169J45_123_4229_n1197) );
OAI22X1TS U2744 ( .A0(n2649), .A1(n2657), .B0(n2648), .B1(n2659), .Y(
DP_OP_169J45_123_4229_n1196) );
OAI22X1TS U2745 ( .A0(n2652), .A1(n2657), .B0(n2651), .B1(n2659), .Y(
DP_OP_169J45_123_4229_n1199) );
OAI22X1TS U2746 ( .A0(n2653), .A1(n2657), .B0(n2652), .B1(n2659), .Y(
DP_OP_169J45_123_4229_n1200) );
OAI22X1TS U2747 ( .A0(n2655), .A1(n2657), .B0(n2653), .B1(n2659), .Y(
DP_OP_169J45_123_4229_n1201) );
OAI22X1TS U2748 ( .A0(n2656), .A1(n2657), .B0(n2655), .B1(n2659), .Y(
DP_OP_169J45_123_4229_n1202) );
OAI22X1TS U2749 ( .A0(n2658), .A1(n2657), .B0(n2656), .B1(n810), .Y(
DP_OP_169J45_123_4229_n1203) );
OAI22X1TS U2750 ( .A0(n1768), .A1(n2657), .B0(n2658), .B1(n810), .Y(n1771)
);
OAI22X1TS U2751 ( .A0(n2657), .A1(n1783), .B0(n1782), .B1(n810), .Y(n1854)
);
OAI22X1TS U2752 ( .A0(n2657), .A1(n854), .B0(n1783), .B1(n810), .Y(n2662) );
NAND2X6TS U2753 ( .A(n1681), .B(n810), .Y(n2657) );
OAI21XLTS U2754 ( .A0(n1208), .A1(n1207), .B0(n1205), .Y(n1206) );
OAI21XLTS U2755 ( .A0(n1108), .A1(n1107), .B0(n1205), .Y(n1106) );
OAI21XLTS U2756 ( .A0(n1103), .A1(n1102), .B0(n1205), .Y(n1101) );
OAI21XLTS U2757 ( .A0(n1098), .A1(n1097), .B0(n1205), .Y(n1096) );
OAI21XLTS U2758 ( .A0(n1093), .A1(n1092), .B0(n1205), .Y(n1091) );
BUFX3TS U2759 ( .A(mult_x_23_n871), .Y(n1205) );
BUFX6TS U2760 ( .A(n3831), .Y(n3890) );
INVX6TS U2761 ( .A(n2819), .Y(n3287) );
NOR4X1TS U2762 ( .A(Op_MX[0]), .B(Op_MX[1]), .C(Op_MX[53]), .D(n4916), .Y(
n4936) );
NAND2X1TS U2763 ( .A(Op_MX[15]), .B(Op_MX[42]), .Y(n1959) );
NAND2X1TS U2764 ( .A(Op_MX[6]), .B(Op_MX[33]), .Y(n2023) );
XOR2X1TS U2765 ( .A(Op_MY[49]), .B(Op_MY[22]), .Y(n1858) );
NOR2XLTS U2766 ( .A(n1887), .B(Op_MX[25]), .Y(n1714) );
OAI2BB2X2TS U2767 ( .B0(n4103), .B1(Op_MX[25]), .A0N(Op_MX[25]), .A1N(n4103),
.Y(n3901) );
NAND2X1TS U2768 ( .A(Op_MX[45]), .B(Op_MX[18]), .Y(n1918) );
NAND2X1TS U2769 ( .A(Op_MX[12]), .B(Op_MX[39]), .Y(n2086) );
NAND2X1TS U2770 ( .A(Op_MX[31]), .B(Op_MX[4]), .Y(n1738) );
OAI2BB2X2TS U2771 ( .B0(n4878), .B1(Op_MX[4]), .A0N(Op_MX[4]), .A1N(n4510),
.Y(n3595) );
NAND2X1TS U2772 ( .A(Op_MX[27]), .B(Op_MX[0]), .Y(n1684) );
XOR2X1TS U2773 ( .A(Op_MY[37]), .B(Op_MY[10]), .Y(n1979) );
OAI21XLTS U2774 ( .A0(Op_MY[37]), .A1(Op_MY[10]), .B0(Op_MY[9]), .Y(n1986)
);
OAI31X1TS U2775 ( .A0(n1167), .A1(Op_MX[32]), .A2(n3245), .B0(n1166), .Y(
n1199) );
CLKBUFX2TS U2776 ( .A(n2272), .Y(n863) );
CLKXOR2X2TS U2777 ( .A(n1719), .B(DP_OP_169J45_123_4229_n86), .Y(n2272) );
BUFX6TS U2778 ( .A(n2365), .Y(n864) );
XNOR2X1TS U2779 ( .A(n2138), .B(n2133), .Y(n2137) );
XOR2XLTS U2780 ( .A(n847), .B(Op_MY[43]), .Y(n2171) );
BUFX6TS U2781 ( .A(n2394), .Y(n865) );
XNOR2X1TS U2782 ( .A(n1909), .B(n1904), .Y(n1908) );
XOR2XLTS U2783 ( .A(Op_MY[46]), .B(Op_MY[47]), .Y(n2139) );
BUFX6TS U2784 ( .A(n2424), .Y(n866) );
XNOR2X1TS U2785 ( .A(n2170), .B(n2165), .Y(n2169) );
XOR2XLTS U2786 ( .A(Op_MY[38]), .B(Op_MY[39]), .Y(n2081) );
XOR2XLTS U2787 ( .A(Op_MY[35]), .B(Op_MY[34]), .Y(n2107) );
BUFX6TS U2788 ( .A(n2453), .Y(n867) );
NAND2X1TS U2789 ( .A(n2074), .B(n2082), .Y(n1933) );
XOR2XLTS U2790 ( .A(Op_MY[33]), .B(Op_MY[32]), .Y(n2018) );
BUFX6TS U2791 ( .A(n2303), .Y(n868) );
BUFX6TS U2792 ( .A(n2571), .Y(n869) );
NAND2X1TS U2793 ( .A(n2014), .B(n2013), .Y(n2015) );
NOR2X2TS U2794 ( .A(Op_MX[41]), .B(n763), .Y(n1947) );
BUFX6TS U2795 ( .A(n2483), .Y(n870) );
BUFX6TS U2796 ( .A(n2513), .Y(n872) );
OAI31X1TS U2797 ( .A0(n3156), .A1(Op_MX[50]), .A2(n3245), .B0(n3155), .Y(
n3253) );
BUFX6TS U2798 ( .A(n2335), .Y(n873) );
XNOR2X1TS U2799 ( .A(n1858), .B(n1857), .Y(n1862) );
XNOR2X2TS U2800 ( .A(n2105), .B(n2104), .Y(n2543) );
INVX2TS U2801 ( .A(n2543), .Y(n874) );
INVX4TS U2802 ( .A(n2543), .Y(n875) );
INVX3TS U2803 ( .A(n2543), .Y(n876) );
XNOR2X4TS U2804 ( .A(n2135), .B(n2134), .Y(n877) );
XNOR2X4TS U2805 ( .A(n2135), .B(n2134), .Y(n878) );
NAND2X2TS U2806 ( .A(n1914), .B(n1913), .Y(n2134) );
XNOR2X4TS U2807 ( .A(Op_MY[25]), .B(n1891), .Y(n879) );
XNOR2X4TS U2808 ( .A(Op_MY[25]), .B(n1891), .Y(n880) );
XNOR2X4TS U2809 ( .A(n2132), .B(n2140), .Y(n881) );
XNOR2X4TS U2810 ( .A(n2132), .B(n2140), .Y(n882) );
XNOR2X1TS U2811 ( .A(n2299), .B(n2361), .Y(n2363) );
INVX2TS U2812 ( .A(n2361), .Y(n2336) );
XNOR2X1TS U2813 ( .A(n834), .B(n2361), .Y(n2366) );
NAND2X2TS U2814 ( .A(n1860), .B(n1859), .Y(n2132) );
XNOR2X4TS U2815 ( .A(n2175), .B(n2174), .Y(n883) );
XNOR2X4TS U2816 ( .A(n2175), .B(n2174), .Y(n884) );
INVX2TS U2817 ( .A(n2420), .Y(n2395) );
XNOR2X1TS U2818 ( .A(n854), .B(n2420), .Y(n2176) );
NAND2X2TS U2819 ( .A(n1906), .B(n1905), .Y(n2175) );
XNOR2X4TS U2820 ( .A(n2167), .B(n2166), .Y(n885) );
XNOR2X4TS U2821 ( .A(n2167), .B(n2166), .Y(n886) );
XNOR2X1TS U2822 ( .A(n833), .B(n885), .Y(n2446) );
XNOR2X1TS U2823 ( .A(n837), .B(n886), .Y(n2447) );
XNOR2X1TS U2824 ( .A(n836), .B(n2448), .Y(n2449) );
XNOR2X1TS U2825 ( .A(n854), .B(n2448), .Y(n2178) );
INVX2TS U2826 ( .A(n2448), .Y(n2180) );
NAND2X2TS U2827 ( .A(n1940), .B(n1939), .Y(n2167) );
XNOR2X4TS U2828 ( .A(n2074), .B(n2082), .Y(n888) );
XNOR2X4TS U2829 ( .A(n2074), .B(n2082), .Y(n889) );
XNOR2X1TS U2830 ( .A(n833), .B(n2479), .Y(n2475) );
XNOR2X1TS U2831 ( .A(n854), .B(n2479), .Y(n2194) );
XNOR2X4TS U2832 ( .A(n2103), .B(n2102), .Y(n890) );
XNOR2X1TS U2833 ( .A(n825), .B(n2567), .Y(n2558) );
XNOR2X1TS U2834 ( .A(n831), .B(n2567), .Y(n2559) );
XNOR2X1TS U2835 ( .A(n817), .B(n890), .Y(n2560) );
XNOR2X1TS U2836 ( .A(n828), .B(n2567), .Y(n2561) );
XNOR2X1TS U2837 ( .A(n2567), .B(n839), .Y(n2213) );
XNOR2X1TS U2838 ( .A(n854), .B(n2508), .Y(n2196) );
XNOR2X4TS U2839 ( .A(n2014), .B(n2013), .Y(n892) );
XNOR2X4TS U2840 ( .A(n2014), .B(n2013), .Y(n893) );
XNOR2X1TS U2841 ( .A(n831), .B(n2598), .Y(n2587) );
XNOR2X1TS U2842 ( .A(n825), .B(n892), .Y(n2586) );
XNOR2X1TS U2843 ( .A(n828), .B(n893), .Y(n2589) );
XNOR2X1TS U2844 ( .A(n817), .B(n892), .Y(n2588) );
XNOR2X1TS U2845 ( .A(n837), .B(n893), .Y(n2594) );
XNOR2X1TS U2846 ( .A(n834), .B(n892), .Y(n2603) );
XNOR2X1TS U2847 ( .A(n839), .B(n2598), .Y(n2600) );
XNOR2X1TS U2848 ( .A(n2539), .B(n854), .Y(n2210) );
XNOR2X1TS U2849 ( .A(n814), .B(n2627), .Y(n2631) );
CLKBUFX3TS U2850 ( .A(n2654), .Y(n896) );
BUFX6TS U2851 ( .A(n2654), .Y(n897) );
XNOR2X1TS U2852 ( .A(n1753), .B(n910), .Y(n2654) );
INVX4TS U2853 ( .A(n852), .Y(n898) );
XOR2XLTS U2854 ( .A(Op_MY[50]), .B(Op_MY[51]), .Y(n1892) );
XNOR2X2TS U2855 ( .A(Op_MY[28]), .B(n4892), .Y(n1753) );
AOI222X4TS U2856 ( .A0(n2758), .A1(n3267), .B0(n2757), .B1(Op_MY[28]), .C0(
n2810), .C1(n848), .Y(n2759) );
AOI222X4TS U2857 ( .A0(n2791), .A1(n3267), .B0(n2790), .B1(Op_MY[28]), .C0(
n2819), .C1(n848), .Y(n2792) );
XOR2XLTS U2858 ( .A(Op_MY[28]), .B(Op_MY[29]), .Y(n1749) );
OR2X1TS U2859 ( .A(n1720), .B(n4103), .Y(n899) );
OR2X1TS U2860 ( .A(n1721), .B(n4659), .Y(n900) );
OR2X1TS U2861 ( .A(n1334), .B(n1333), .Y(n905) );
OR2X1TS U2862 ( .A(n1339), .B(n1338), .Y(n906) );
OR2X1TS U2863 ( .A(n1344), .B(n1343), .Y(n907) );
OR2X1TS U2864 ( .A(Op_MX[27]), .B(Op_MX[0]), .Y(n912) );
CLKAND2X2TS U2865 ( .A(n1048), .B(Op_MX[27]), .Y(n914) );
CLKAND2X2TS U2866 ( .A(n1044), .B(n1043), .Y(n918) );
OR2X1TS U2867 ( .A(n1406), .B(Sgf_operation_ODD1_Q_middle[54]), .Y(n920) );
OR2X1TS U2868 ( .A(n1391), .B(n1390), .Y(n921) );
OR2X1TS U2869 ( .A(n1350), .B(n1349), .Y(n922) );
OR2X1TS U2870 ( .A(n1357), .B(n1356), .Y(n923) );
OR2X1TS U2871 ( .A(n1364), .B(n1363), .Y(n924) );
OR2X1TS U2872 ( .A(n1373), .B(n1372), .Y(n925) );
OR2X1TS U2873 ( .A(n1382), .B(n1381), .Y(n926) );
OR2X1TS U2874 ( .A(n1400), .B(n1399), .Y(n927) );
OR2X1TS U2875 ( .A(Op_MX[40]), .B(Op_MX[13]), .Y(n928) );
OR2X1TS U2876 ( .A(Op_MY[25]), .B(Op_MY[26]), .Y(n932) );
OR2X1TS U2877 ( .A(Op_MX[37]), .B(Op_MX[10]), .Y(n933) );
INVX2TS U2878 ( .A(Op_MX[5]), .Y(n4878) );
CLKINVX3TS U2879 ( .A(n4878), .Y(n4913) );
OR2X1TS U2880 ( .A(Op_MX[49]), .B(Op_MX[22]), .Y(n936) );
AOI22X1TS U2881 ( .A0(n4883), .A1(Data_MX[29]), .B0(n4879), .B1(Op_MX[29]),
.Y(n941) );
OR2X1TS U2882 ( .A(n1294), .B(n1293), .Y(n960) );
OR2X1TS U2883 ( .A(n1299), .B(n1298), .Y(n961) );
OR2X1TS U2884 ( .A(Op_MX[47]), .B(n730), .Y(n962) );
OA21XLTS U2885 ( .A0(n1596), .A1(n1287), .B0(n1286), .Y(n964) );
OR2X1TS U2886 ( .A(n1597), .B(n1287), .Y(n965) );
OR2X1TS U2887 ( .A(n1289), .B(n1288), .Y(n966) );
OR2X1TS U2888 ( .A(Op_MX[44]), .B(DP_OP_169J45_123_4229_n2458), .Y(n967) );
BUFX6TS U2889 ( .A(n3318), .Y(n3363) );
OR2X1TS U2890 ( .A(n2662), .B(n2661), .Y(n971) );
BUFX6TS U2891 ( .A(n977), .Y(n3098) );
BUFX6TS U2892 ( .A(n977), .Y(n3407) );
OR4X2TS U2893 ( .A(FS_Module_state_reg[2]), .B(n728), .C(
FS_Module_state_reg[3]), .D(n5360), .Y(n979) );
INVX2TS U2894 ( .A(n2126), .Y(n1699) );
INVX2TS U2895 ( .A(n2033), .Y(n1687) );
OAI21XLTS U2896 ( .A0(n4660), .A1(n4658), .B0(n4656), .Y(n4657) );
AOI21X1TS U2897 ( .A0(n2122), .A1(n2003), .B0(n2002), .Y(n2004) );
NAND2X1TS U2898 ( .A(n1694), .B(n1987), .Y(n1996) );
OAI21XLTS U2899 ( .A0(n2725), .A1(n2724), .B0(n3402), .Y(n2723) );
OAI21XLTS U2900 ( .A0(n4677), .A1(n4676), .B0(n4674), .Y(n4675) );
XOR2XLTS U2901 ( .A(n846), .B(Op_MY[31]), .Y(n1729) );
INVX2TS U2902 ( .A(Sgf_operation_ODD1_Q_right[44]), .Y(n1366) );
INVX2TS U2903 ( .A(Sgf_operation_ODD1_Q_left[51]), .Y(n1398) );
NAND2X1TS U2904 ( .A(n1866), .B(n1708), .Y(n1870) );
XOR2X1TS U2905 ( .A(Op_MY[43]), .B(Op_MY[16]), .Y(n2170) );
XNOR2X1TS U2906 ( .A(n823), .B(n898), .Y(n2260) );
OAI21XLTS U2907 ( .A0(n3936), .A1(n3935), .B0(n4656), .Y(n3934) );
OAI21XLTS U2908 ( .A0(n4104), .A1(n4102), .B0(n4656), .Y(n4101) );
OAI21XLTS U2909 ( .A0(n3159), .A1(n3158), .B0(n3402), .Y(n3157) );
XNOR2X1TS U2910 ( .A(n825), .B(n850), .Y(n2319) );
XNOR2X1TS U2911 ( .A(n832), .B(Op_MY[26]), .Y(n2266) );
XNOR2X1TS U2912 ( .A(n2641), .B(n883), .Y(n2405) );
OAI21XLTS U2913 ( .A0(n3294), .A1(n3293), .B0(n3318), .Y(n3292) );
XNOR2X1TS U2914 ( .A(n825), .B(n878), .Y(n2380) );
XNOR2X1TS U2915 ( .A(n823), .B(n883), .Y(n2408) );
XNOR2X1TS U2916 ( .A(n834), .B(Op_MY[26]), .Y(n2065) );
NOR2XLTS U2917 ( .A(n3245), .B(n3369), .Y(n3270) );
OAI21XLTS U2918 ( .A0(n4159), .A1(n4158), .B0(n5451), .Y(n4157) );
XNOR2X1TS U2919 ( .A(n817), .B(n886), .Y(n2441) );
OAI21XLTS U2920 ( .A0(n4025), .A1(n4024), .B0(n959), .Y(n4023) );
XNOR2X1TS U2921 ( .A(n839), .B(n2301), .Y(n2302) );
XNOR2X1TS U2922 ( .A(n837), .B(n2389), .Y(n2388) );
XNOR2X1TS U2923 ( .A(n827), .B(n811), .Y(n2555) );
OAI21XLTS U2924 ( .A0(n2744), .A1(n2743), .B0(n968), .Y(n2742) );
OAI21XLTS U2925 ( .A0(n2749), .A1(n2748), .B0(n968), .Y(n2747) );
XNOR2X1TS U2926 ( .A(n834), .B(n2389), .Y(n2154) );
XNOR2X1TS U2927 ( .A(n840), .B(n2448), .Y(n2452) );
OAI22X1TS U2928 ( .A0(n809), .A1(n2395), .B0(n2424), .B1(n2177), .Y(n2186)
);
OAI21XLTS U2929 ( .A0(n4378), .A1(n4377), .B0(n4699), .Y(n4376) );
OAI21X1TS U2930 ( .A0(n2244), .A1(n2236), .B0(n2235), .Y(n2239) );
OAI22X1TS U2931 ( .A0(n2426), .A1(n2450), .B0(n867), .B1(n2180), .Y(n1973)
);
NOR2X1TS U2932 ( .A(n773), .B(n852), .Y(DP_OP_169J45_123_4229_n274) );
OAI22X1TS U2933 ( .A0(n2400), .A1(n2423), .B0(n2399), .B1(n866), .Y(
DP_OP_169J45_123_4229_n945) );
INVX2TS U2934 ( .A(n2001), .Y(n2011) );
XNOR2X1TS U2935 ( .A(n826), .B(n884), .Y(n2403) );
OAI22X1TS U2936 ( .A0(n2378), .A1(n2391), .B0(n2377), .B1(n865), .Y(
DP_OP_169J45_123_4229_n922) );
OAI22X1TS U2937 ( .A0(n2405), .A1(n866), .B0(n2406), .B1(n2423), .Y(
DP_OP_169J45_123_4229_n951) );
XNOR2X1TS U2938 ( .A(n815), .B(n890), .Y(n2545) );
OAI22X1TS U2939 ( .A0(n2408), .A1(n2423), .B0(n2407), .B1(n866), .Y(
DP_OP_169J45_123_4229_n953) );
OAI22X1TS U2940 ( .A0(n801), .A1(n2295), .B0(n2294), .B1(n868), .Y(
DP_OP_169J45_123_4229_n842) );
OAI22X1TS U2941 ( .A0(n861), .A1(n2605), .B0(n887), .B1(n2604), .Y(
DP_OP_169J45_123_4229_n1151) );
OAI22X1TS U2942 ( .A0(n2327), .A1(n812), .B0(n2326), .B1(n873), .Y(
DP_OP_169J45_123_4229_n872) );
OAI22X1TS U2943 ( .A0(n2385), .A1(n2391), .B0(n2384), .B1(n865), .Y(
DP_OP_169J45_123_4229_n929) );
OAI22X1TS U2944 ( .A0(n2469), .A1(n2482), .B0(n2468), .B1(n870), .Y(
DP_OP_169J45_123_4229_n1015) );
OAI21XLTS U2945 ( .A0(n3034), .A1(n3033), .B0(n3384), .Y(n3032) );
OAI22X1TS U2946 ( .A0(n2636), .A1(n862), .B0(n2635), .B1(n2659), .Y(
DP_OP_169J45_123_4229_n1184) );
OAI21XLTS U2947 ( .A0(n3387), .A1(n3386), .B0(n3384), .Y(n3385) );
OAI22X1TS U2948 ( .A0(n2360), .A1(n2365), .B0(n2362), .B1(n808), .Y(n2143)
);
OAI22X1TS U2949 ( .A0(n2556), .A1(n806), .B0(n2555), .B1(n869), .Y(
DP_OP_169J45_123_4229_n1102) );
OAI21XLTS U2950 ( .A0(n3031), .A1(n3030), .B0(n3384), .Y(n3029) );
XNOR2X1TS U2951 ( .A(n835), .B(n2448), .Y(n2445) );
OAI21XLTS U2952 ( .A0(n3028), .A1(n3027), .B0(n3384), .Y(n3026) );
XNOR2X1TS U2953 ( .A(n828), .B(n894), .Y(n2531) );
OAI21XLTS U2954 ( .A0(n2968), .A1(n2967), .B0(n3098), .Y(n2966) );
OAI21XLTS U2955 ( .A0(n4254), .A1(n4253), .B0(n4744), .Y(n4252) );
OAI21XLTS U2956 ( .A0(n4321), .A1(n4320), .B0(n5452), .Y(n4319) );
XNOR2X1TS U2957 ( .A(n817), .B(n895), .Y(n2620) );
OAI21XLTS U2958 ( .A0(n4269), .A1(n4268), .B0(n4744), .Y(n4267) );
OAI21XLTS U2959 ( .A0(n2777), .A1(n2776), .B0(n3098), .Y(n2775) );
OAI21XLTS U2960 ( .A0(n2789), .A1(n2788), .B0(n3098), .Y(n2787) );
OAI21XLTS U2961 ( .A0(n4393), .A1(n4392), .B0(n4744), .Y(n4391) );
NOR2XLTS U2962 ( .A(n1749), .B(n1751), .Y(n1750) );
NAND2X1TS U2963 ( .A(n1269), .B(n1268), .Y(n1623) );
INVX2TS U2964 ( .A(n1546), .Y(n1300) );
NAND2X1TS U2965 ( .A(n1312), .B(n1311), .Y(n1526) );
INVX2TS U2966 ( .A(n1506), .Y(n1325) );
NAND2X1TS U2967 ( .A(n1337), .B(n1336), .Y(n1486) );
INVX2TS U2968 ( .A(n1466), .Y(n1351) );
NAND2X1TS U2969 ( .A(n1369), .B(n1368), .Y(n1446) );
INVX2TS U2970 ( .A(n1426), .Y(n1392) );
INVX2TS U2971 ( .A(n2641), .Y(n1917) );
XNOR2X1TS U2972 ( .A(n819), .B(n878), .Y(n2369) );
XNOR2X1TS U2973 ( .A(n816), .B(n850), .Y(n2309) );
OAI21XLTS U2974 ( .A0(n3230), .A1(n748), .B0(n746), .Y(n1017) );
OAI21XLTS U2975 ( .A0(n3206), .A1(n3205), .B0(n3402), .Y(n3204) );
OAI22X1TS U2976 ( .A0(n2342), .A1(n2364), .B0(n2341), .B1(n864), .Y(
DP_OP_169J45_123_4229_n886) );
OAI22X1TS U2977 ( .A0(n2283), .A1(n868), .B0(n2305), .B1(n2284), .Y(
DP_OP_169J45_123_4229_n831) );
OAI22X1TS U2978 ( .A0(n2427), .A1(n2450), .B0(n2426), .B1(n867), .Y(
DP_OP_169J45_123_4229_n972) );
CMPR42X1TS U2979 ( .A(DP_OP_169J45_123_4229_n862), .B(
DP_OP_169J45_123_4229_n806), .C(DP_OP_169J45_123_4229_n834), .D(
DP_OP_169J45_123_4229_n289), .ICI(DP_OP_169J45_123_4229_n296), .S(
DP_OP_169J45_123_4229_n287), .ICO(DP_OP_169J45_123_4229_n285), .CO(
DP_OP_169J45_123_4229_n286) );
OAI22X1TS U2980 ( .A0(n2430), .A1(n2450), .B0(n2429), .B1(n867), .Y(
DP_OP_169J45_123_4229_n975) );
OAI22X1TS U2981 ( .A0(n2403), .A1(n2423), .B0(n2402), .B1(n866), .Y(
DP_OP_169J45_123_4229_n948) );
CMPR42X1TS U2982 ( .A(DP_OP_169J45_123_4229_n980), .B(
DP_OP_169J45_123_4229_n1008), .C(DP_OP_169J45_123_4229_n407), .D(
DP_OP_169J45_123_4229_n404), .ICI(DP_OP_169J45_123_4229_n391), .S(
DP_OP_169J45_123_4229_n385), .ICO(DP_OP_169J45_123_4229_n383), .CO(
DP_OP_169J45_123_4229_n384) );
CMPR42X1TS U2983 ( .A(DP_OP_169J45_123_4229_n1122), .B(
DP_OP_169J45_123_4229_n1038), .C(DP_OP_169J45_123_4229_n431), .D(
DP_OP_169J45_123_4229_n444), .ICI(DP_OP_169J45_123_4229_n447), .S(
DP_OP_169J45_123_4229_n423), .ICO(DP_OP_169J45_123_4229_n421), .CO(
DP_OP_169J45_123_4229_n422) );
INVX2TS U2984 ( .A(n3395), .Y(n2834) );
OAI22X1TS U2985 ( .A0(n2549), .A1(n806), .B0(n2548), .B1(n869), .Y(
DP_OP_169J45_123_4229_n1095) );
CMPR42X1TS U2986 ( .A(DP_OP_169J45_123_4229_n1180), .B(
DP_OP_169J45_123_4229_n1012), .C(DP_OP_169J45_123_4229_n872), .D(
DP_OP_169J45_123_4229_n900), .ICI(DP_OP_169J45_123_4229_n490), .S(
DP_OP_169J45_123_4229_n471), .ICO(DP_OP_169J45_123_4229_n469), .CO(
DP_OP_169J45_123_4229_n470) );
OAI21XLTS U2987 ( .A0(n2964), .A1(n2963), .B0(n976), .Y(n2962) );
OAI22X1TS U2988 ( .A0(n2578), .A1(n2601), .B0(n2577), .B1(n871), .Y(
DP_OP_169J45_123_4229_n1126) );
CMPR42X1TS U2989 ( .A(DP_OP_169J45_123_4229_n819), .B(
DP_OP_169J45_123_4229_n875), .C(DP_OP_169J45_123_4229_n959), .D(
DP_OP_169J45_123_4229_n931), .ICI(DP_OP_169J45_123_4229_n1043), .S(
DP_OP_169J45_123_4229_n532), .ICO(DP_OP_169J45_123_4229_n530), .CO(
DP_OP_169J45_123_4229_n531) );
OAI21XLTS U2990 ( .A0(n2943), .A1(n2942), .B0(n976), .Y(n2941) );
OAI22X1TS U2991 ( .A0(n2501), .A1(n2510), .B0(n2500), .B1(n872), .Y(
DP_OP_169J45_123_4229_n1046) );
OAI21XLTS U2992 ( .A0(n2940), .A1(n2939), .B0(n976), .Y(n2938) );
OAI22X1TS U2993 ( .A0(n2613), .A1(n887), .B0(n2614), .B1(n2632), .Y(
DP_OP_169J45_123_4229_n1160) );
OAI22X1TS U2994 ( .A0(n2642), .A1(n2657), .B0(n2640), .B1(n2659), .Y(
DP_OP_169J45_123_4229_n1189) );
OAI22X1TS U2995 ( .A0(n2560), .A1(n806), .B0(n2559), .B1(n869), .Y(
DP_OP_169J45_123_4229_n1106) );
OAI21XLTS U2996 ( .A0(n4372), .A1(n4371), .B0(n4516), .Y(n4370) );
OAI22X1TS U2997 ( .A0(n2587), .A1(n2601), .B0(n2586), .B1(n871), .Y(
DP_OP_169J45_123_4229_n1135) );
OAI21XLTS U2998 ( .A0(n4369), .A1(n4368), .B0(n4516), .Y(n4367) );
OAI22X1TS U2999 ( .A0(n2588), .A1(n2601), .B0(n2587), .B1(n871), .Y(
DP_OP_169J45_123_4229_n1136) );
OAI21XLTS U3000 ( .A0(n2923), .A1(n2922), .B0(n976), .Y(n2921) );
INVX2TS U3001 ( .A(n3503), .Y(n4433) );
OAI21XLTS U3002 ( .A0(n2920), .A1(n2919), .B0(n976), .Y(n2918) );
OAI21XLTS U3003 ( .A0(n4423), .A1(n4422), .B0(n4510), .Y(n4421) );
OAI22X1TS U3004 ( .A0(n2511), .A1(n2513), .B0(n2198), .B1(n804), .Y(n2200)
);
OAI21XLTS U3005 ( .A0(n2914), .A1(n2913), .B0(n976), .Y(n2912) );
OAI21XLTS U3006 ( .A0(n2911), .A1(n2910), .B0(n976), .Y(n2909) );
OAI21XLTS U3007 ( .A0(n2908), .A1(n2907), .B0(n3015), .Y(n2906) );
INVX2TS U3008 ( .A(n3529), .Y(n4414) );
OAI21XLTS U3009 ( .A0(n2890), .A1(n2889), .B0(n3015), .Y(n2888) );
OAI21XLTS U3010 ( .A0(n4396), .A1(n4395), .B0(n4519), .Y(n4394) );
OAI21XLTS U3011 ( .A0(n4470), .A1(n4469), .B0(n4510), .Y(n4468) );
OAI21XLTS U3012 ( .A0(n4480), .A1(n4479), .B0(n4516), .Y(n4478) );
OAI21XLTS U3013 ( .A0(n4489), .A1(n4488), .B0(n4516), .Y(n4487) );
OAI21XLTS U3014 ( .A0(n4520), .A1(n4518), .B0(n4516), .Y(n4517) );
OAI21XLTS U3015 ( .A0(n3605), .A1(n3604), .B0(n4510), .Y(n3603) );
OAI21XLTS U3016 ( .A0(n3614), .A1(n3613), .B0(n4510), .Y(n3612) );
NAND2X1TS U3017 ( .A(n1638), .B(n1637), .Y(n1639) );
NAND2X1TS U3018 ( .A(n1479), .B(n1478), .Y(n1480) );
NAND2X1TS U3019 ( .A(n927), .B(n1418), .Y(n1419) );
OAI22X1TS U3020 ( .A0(n2307), .A1(n2334), .B0(n2306), .B1(n873), .Y(
DP_OP_169J45_123_4229_n852) );
NOR2X1TS U3021 ( .A(n777), .B(n853), .Y(DP_OP_169J45_123_4229_n224) );
INVX2TS U3022 ( .A(n1927), .Y(n1929) );
NOR2XLTS U3023 ( .A(n4656), .B(n4607), .Y(n4609) );
OAI21XLTS U3024 ( .A0(n3228), .A1(n3227), .B0(n3402), .Y(n3226) );
CMPR42X1TS U3025 ( .A(DP_OP_169J45_123_4229_n858), .B(
DP_OP_169J45_123_4229_n914), .C(DP_OP_169J45_123_4229_n886), .D(
DP_OP_169J45_123_4229_n246), .ICI(DP_OP_169J45_123_4229_n240), .S(
DP_OP_169J45_123_4229_n231), .ICO(DP_OP_169J45_123_4229_n229), .CO(
DP_OP_169J45_123_4229_n230) );
CMPR42X1TS U3026 ( .A(DP_OP_169J45_123_4229_n917), .B(
DP_OP_169J45_123_4229_n889), .C(DP_OP_169J45_123_4229_n286), .D(
DP_OP_169J45_123_4229_n273), .ICI(DP_OP_169J45_123_4229_n270), .S(
DP_OP_169J45_123_4229_n267), .ICO(DP_OP_169J45_123_4229_n265), .CO(
DP_OP_169J45_123_4229_n266) );
CMPR42X1TS U3027 ( .A(DP_OP_169J45_123_4229_n1003), .B(
DP_OP_169J45_123_4229_n919), .C(DP_OP_169J45_123_4229_n975), .D(
DP_OP_169J45_123_4229_n303), .ICI(DP_OP_169J45_123_4229_n319), .S(
DP_OP_169J45_123_4229_n298), .ICO(DP_OP_169J45_123_4229_n296), .CO(
DP_OP_169J45_123_4229_n297) );
CMPR42X1TS U3028 ( .A(DP_OP_169J45_123_4229_n1033), .B(
DP_OP_169J45_123_4229_n949), .C(DP_OP_169J45_123_4229_n977), .D(
DP_OP_169J45_123_4229_n1005), .ICI(DP_OP_169J45_123_4229_n347), .S(
DP_OP_169J45_123_4229_n329), .ICO(DP_OP_169J45_123_4229_n327), .CO(
DP_OP_169J45_123_4229_n328) );
CMPR42X1TS U3029 ( .A(DP_OP_169J45_123_4229_n1037), .B(
DP_OP_169J45_123_4229_n1009), .C(DP_OP_169J45_123_4229_n421), .D(
DP_OP_169J45_123_4229_n428), .ICI(DP_OP_169J45_123_4229_n425), .S(
DP_OP_169J45_123_4229_n400), .ICO(DP_OP_169J45_123_4229_n398), .CO(
DP_OP_169J45_123_4229_n399) );
CMPR42X1TS U3030 ( .A(DP_OP_169J45_123_4229_n1125), .B(
DP_OP_169J45_123_4229_n1069), .C(DP_OP_169J45_123_4229_n507), .D(
DP_OP_169J45_123_4229_n511), .ICI(DP_OP_169J45_123_4229_n508), .S(
DP_OP_169J45_123_4229_n483), .ICO(DP_OP_169J45_123_4229_n481), .CO(
DP_OP_169J45_123_4229_n482) );
CMPR42X1TS U3031 ( .A(DP_OP_169J45_123_4229_n1127), .B(
DP_OP_169J45_123_4229_n1099), .C(DP_OP_169J45_123_4229_n545), .D(
DP_OP_169J45_123_4229_n548), .ICI(DP_OP_169J45_123_4229_n532), .S(
DP_OP_169J45_123_4229_n523), .ICO(DP_OP_169J45_123_4229_n521), .CO(
DP_OP_169J45_123_4229_n522) );
OAI22X1TS U3032 ( .A0(n2632), .A1(n2624), .B0(n2623), .B1(n887), .Y(
DP_OP_169J45_123_4229_n1170) );
OAI22X1TS U3033 ( .A0(n2632), .A1(n2625), .B0(n2624), .B1(n887), .Y(
DP_OP_169J45_123_4229_n1171) );
OAI21XLTS U3034 ( .A0(n3527), .A1(n3526), .B0(n3659), .Y(n3525) );
OAI21XLTS U3035 ( .A0(n3532), .A1(n3531), .B0(n3659), .Y(n3530) );
OAI21XLTS U3036 ( .A0(n3537), .A1(n3536), .B0(n3659), .Y(n3535) );
OAI22X1TS U3037 ( .A0(n2632), .A1(n1774), .B0(n2629), .B1(n1769), .Y(n1776)
);
OAI22X1TS U3038 ( .A0(n2632), .A1(n1775), .B0(n2629), .B1(n1774), .Y(n1780)
);
XNOR2X1TS U3039 ( .A(n896), .B(n834), .Y(n1782) );
OAI21XLTS U3040 ( .A0(n3562), .A1(n3561), .B0(n931), .Y(n3560) );
OAI21XLTS U3041 ( .A0(n3567), .A1(n3566), .B0(n3659), .Y(n3565) );
OAI21XLTS U3042 ( .A0(n3624), .A1(n3623), .B0(n3659), .Y(n3622) );
OAI21XLTS U3043 ( .A0(n3640), .A1(n3639), .B0(n3659), .Y(n3638) );
XNOR2X1TS U3044 ( .A(n1658), .B(n1657), .Y(n5182) );
XOR2X1TS U3045 ( .A(n1553), .B(n1552), .Y(n5135) );
XNOR2X1TS U3046 ( .A(n1492), .B(n1491), .Y(n5094) );
XOR2X1TS U3047 ( .A(n1433), .B(n1432), .Y(n3726) );
NAND2X1TS U3048 ( .A(n4951), .B(n5363), .Y(n4953) );
NAND2X1TS U3049 ( .A(Sgf_normalized_result[20]), .B(n4981), .Y(n4983) );
NOR2X2TS U3050 ( .A(n5384), .B(n5009), .Y(n5012) );
AO21XLTS U3051 ( .A0(n2305), .A1(n868), .B0(n2273), .Y(
DP_OP_169J45_123_4229_n820) );
OAI22X1TS U3052 ( .A0(n2278), .A1(n2305), .B0(n2277), .B1(n868), .Y(
DP_OP_169J45_123_4229_n825) );
CMPR42X1TS U3053 ( .A(DP_OP_169J45_123_4229_n244), .B(
DP_OP_169J45_123_4229_n234), .C(DP_OP_169J45_123_4229_n241), .D(
DP_OP_169J45_123_4229_n231), .ICI(DP_OP_169J45_123_4229_n237), .S(
DP_OP_169J45_123_4229_n228), .ICO(DP_OP_169J45_123_4229_n226), .CO(
DP_OP_169J45_123_4229_n227) );
CMPR42X1TS U3054 ( .A(DP_OP_169J45_123_4229_n309), .B(
DP_OP_169J45_123_4229_n298), .C(DP_OP_169J45_123_4229_n310), .D(
DP_OP_169J45_123_4229_n295), .ICI(DP_OP_169J45_123_4229_n306), .S(
DP_OP_169J45_123_4229_n292), .ICO(DP_OP_169J45_123_4229_n290), .CO(
DP_OP_169J45_123_4229_n291) );
CMPR42X1TS U3055 ( .A(DP_OP_169J45_123_4229_n395), .B(
DP_OP_169J45_123_4229_n382), .C(DP_OP_169J45_123_4229_n396), .D(
DP_OP_169J45_123_4229_n379), .ICI(DP_OP_169J45_123_4229_n392), .S(
DP_OP_169J45_123_4229_n376), .ICO(DP_OP_169J45_123_4229_n374), .CO(
DP_OP_169J45_123_4229_n375) );
CMPR42X1TS U3056 ( .A(DP_OP_169J45_123_4229_n502), .B(
DP_OP_169J45_123_4229_n483), .C(DP_OP_169J45_123_4229_n499), .D(
DP_OP_169J45_123_4229_n480), .ICI(DP_OP_169J45_123_4229_n495), .S(
DP_OP_169J45_123_4229_n477), .ICO(DP_OP_169J45_123_4229_n475), .CO(
DP_OP_169J45_123_4229_n476) );
CMPR42X1TS U3057 ( .A(DP_OP_169J45_123_4229_n577), .B(
DP_OP_169J45_123_4229_n589), .C(DP_OP_169J45_123_4229_n590), .D(
DP_OP_169J45_123_4229_n574), .ICI(DP_OP_169J45_123_4229_n586), .S(
DP_OP_169J45_123_4229_n571), .ICO(DP_OP_169J45_123_4229_n569), .CO(
DP_OP_169J45_123_4229_n570) );
CMPR42X1TS U3058 ( .A(DP_OP_169J45_123_4229_n664), .B(
DP_OP_169J45_123_4229_n661), .C(DP_OP_169J45_123_4229_n653), .D(
DP_OP_169J45_123_4229_n650), .ICI(DP_OP_169J45_123_4229_n657), .S(
DP_OP_169J45_123_4229_n647), .ICO(DP_OP_169J45_123_4229_n645), .CO(
DP_OP_169J45_123_4229_n646) );
CMPR42X1TS U3059 ( .A(DP_OP_169J45_123_4229_n707), .B(
DP_OP_169J45_123_4229_n700), .C(DP_OP_169J45_123_4229_n705), .D(
DP_OP_169J45_123_4229_n697), .ICI(DP_OP_169J45_123_4229_n701), .S(
DP_OP_169J45_123_4229_n694), .ICO(DP_OP_169J45_123_4229_n692), .CO(
DP_OP_169J45_123_4229_n693) );
CMPR42X1TS U3060 ( .A(DP_OP_169J45_123_4229_n1143), .B(
DP_OP_169J45_123_4229_n1171), .C(DP_OP_169J45_123_4229_n736), .D(
DP_OP_169J45_123_4229_n733), .ICI(DP_OP_169J45_123_4229_n732), .S(
DP_OP_169J45_123_4229_n729), .ICO(DP_OP_169J45_123_4229_n727), .CO(
DP_OP_169J45_123_4229_n728) );
OAI21XLTS U3061 ( .A0(n5044), .A1(Sgf_normalized_result[52]), .B0(n5046),
.Y(n5045) );
OAI211XLTS U3062 ( .A0(n3783), .A1(n5401), .B0(n3802), .C0(n3801), .Y(n358)
);
OAI211XLTS U3063 ( .A0(n3895), .A1(n5421), .B0(n3889), .C0(n3888), .Y(n388)
);
OAI211XLTS U3064 ( .A0(n3876), .A1(n5418), .B0(n3858), .C0(n3857), .Y(n391)
);
BUFX3TS U3191 ( .A(n4888), .Y(n4879) );
BUFX4TS U3192 ( .A(n976), .Y(n5336) );
BUFX6TS U3193 ( .A(n975), .Y(n3326) );
BUFX4TS U3194 ( .A(Op_MY[51]), .Y(n2832) );
INVX3TS U3195 ( .A(n3268), .Y(n3369) );
BUFX6TS U3196 ( .A(n3258), .Y(n3366) );
NOR2X1TS U3197 ( .A(n3326), .B(n908), .Y(n2701) );
AOI22X1TS U3198 ( .A0(n2832), .A1(n3366), .B0(Op_MY[50]), .B1(n758), .Y(n981) );
OAI21XLTS U3199 ( .A0(n1054), .A1(n3369), .B0(n981), .Y(n983) );
INVX3TS U3200 ( .A(n3268), .Y(n3358) );
OAI32X1TS U3201 ( .A0(n3268), .A1(n2832), .A2(n908), .B0(n3395), .B1(n3358),
.Y(n3240) );
CMPR32X2TS U3202 ( .A(mult_x_23_n197), .B(n3326), .C(n983), .CO(n3241), .S(
n3428) );
AOI22X1TS U3203 ( .A0(Op_MY[50]), .A1(n3366), .B0(Op_MY[49]), .B1(n758), .Y(
n986) );
OAI21XLTS U3204 ( .A0(n3369), .A1(n3229), .B0(n986), .Y(n996) );
INVX2TS U3205 ( .A(mult_x_23_n197), .Y(n999) );
INVX2TS U3206 ( .A(n1000), .Y(n987) );
INVX2TS U3207 ( .A(n3156), .Y(n1001) );
INVX3TS U3208 ( .A(n3251), .Y(n3400) );
XOR2X1TS U3209 ( .A(Op_MX[49]), .B(Op_MX[48]), .Y(n992) );
NOR3X2TS U3210 ( .A(n1001), .B(n992), .C(n1000), .Y(n1003) );
XNOR2X1TS U3211 ( .A(n3402), .B(n988), .Y(n995) );
AOI22X1TS U3212 ( .A0(Op_MY[49]), .A1(n3366), .B0(n845), .B1(n758), .Y(n991)
);
OAI21XLTS U3213 ( .A0(n3369), .A1(n3225), .B0(n991), .Y(n998) );
AOI21X1TS U3214 ( .A0(n2832), .A1(n1003), .B0(n3249), .Y(n993) );
XNOR2X1TS U3215 ( .A(n3326), .B(n994), .Y(n997) );
CMPR32X2TS U3216 ( .A(n996), .B(n999), .C(n995), .CO(n3427), .S(n3430) );
CMPR32X2TS U3217 ( .A(n999), .B(n998), .C(n997), .CO(n3431), .S(n2664) );
INVX4TS U3218 ( .A(n2832), .Y(n3230) );
OAI21XLTS U3219 ( .A0(n3230), .A1(n756), .B0(n750), .Y(n1002) );
AOI21X1TS U3220 ( .A0(Op_MY[50]), .A1(n1003), .B0(n1002), .Y(n1004) );
XNOR2X1TS U3221 ( .A(n3326), .B(n1005), .Y(n1222) );
AOI2BB2X2TS U3222 ( .B0(n844), .B1(n5334), .A0N(n963), .A1N(n844), .Y(n1008)
);
INVX2TS U3223 ( .A(n1008), .Y(n1006) );
INVX2TS U3224 ( .A(n2741), .Y(n1009) );
INVX3TS U3225 ( .A(n2738), .Y(n3332) );
XOR2X1TS U3226 ( .A(n844), .B(Op_MX[45]), .Y(n1007) );
NOR3X2TS U3227 ( .A(n1009), .B(n1007), .C(n1008), .Y(n2806) );
OAI21XLTS U3228 ( .A0(n3230), .A1(n754), .B0(n755), .Y(n1010) );
AOI21X1TS U3229 ( .A0(Op_MY[50]), .A1(n2806), .B0(n1010), .Y(n1011) );
XNOR2X1TS U3230 ( .A(n5334), .B(n1012), .Y(n1238) );
BUFX3TS U3231 ( .A(n968), .Y(n3318) );
AOI2BB2X2TS U3232 ( .B0(n843), .B1(n3363), .A0N(n968), .A1N(n843), .Y(n1015)
);
INVX2TS U3233 ( .A(n1015), .Y(n1013) );
INVX2TS U3234 ( .A(n2761), .Y(n1016) );
INVX3TS U3235 ( .A(n2758), .Y(n3315) );
XOR2X1TS U3236 ( .A(n843), .B(Op_MX[42]), .Y(n1014) );
NOR3X2TS U3237 ( .A(n1016), .B(n1014), .C(n1015), .Y(n2811) );
AOI21X1TS U3238 ( .A0(Op_MY[50]), .A1(n2811), .B0(n1017), .Y(n1018) );
XNOR2X1TS U3239 ( .A(n3363), .B(n1019), .Y(n1234) );
INVX2TS U3240 ( .A(n1022), .Y(n1020) );
OAI2BB2X2TS U3241 ( .B0(Op_MX[39]), .B1(Op_MX[38]), .A0N(Op_MX[38]), .A1N(
Op_MX[39]), .Y(n2774) );
INVX2TS U3242 ( .A(n2774), .Y(n1023) );
XOR2X1TS U3243 ( .A(Op_MX[40]), .B(Op_MX[39]), .Y(n1021) );
NOR3X2TS U3244 ( .A(n1023), .B(n1021), .C(n1022), .Y(n2816) );
CLKAND2X2TS U3245 ( .A(n1021), .B(n2774), .Y(n2815) );
CLKAND2X2TS U3246 ( .A(n1023), .B(n1022), .Y(n2771) );
AOI21X1TS U3247 ( .A0(Op_MY[50]), .A1(n2816), .B0(n1024), .Y(n1025) );
XNOR2X1TS U3248 ( .A(n5335), .B(n1026), .Y(n1240) );
AOI2BB2X2TS U3249 ( .B0(Op_MX[37]), .B1(n3407), .A0N(n3098), .A1N(Op_MX[37]),
.Y(n1029) );
INVX2TS U3250 ( .A(n1029), .Y(n1027) );
INVX2TS U3251 ( .A(n2794), .Y(n1030) );
CLKAND2X2TS U3252 ( .A(n1027), .B(n1030), .Y(n2791) );
XOR2X1TS U3253 ( .A(Op_MX[37]), .B(Op_MX[36]), .Y(n1028) );
NOR3X2TS U3254 ( .A(n1030), .B(n1028), .C(n1029), .Y(n2820) );
CLKAND2X2TS U3255 ( .A(n1028), .B(n2794), .Y(n2819) );
CLKAND2X2TS U3256 ( .A(n1030), .B(n1029), .Y(n2790) );
AOI21X1TS U3257 ( .A0(Op_MY[50]), .A1(n2820), .B0(n1031), .Y(n1032) );
XNOR2X1TS U3258 ( .A(n3407), .B(n1033), .Y(n1236) );
BUFX4TS U3259 ( .A(n976), .Y(n3015) );
AOI2BB2X2TS U3260 ( .B0(Op_MX[34]), .B1(n3015), .A0N(n5336), .A1N(Op_MX[34]),
.Y(n1036) );
INVX2TS U3261 ( .A(n1036), .Y(n1034) );
INVX2TS U3262 ( .A(n1142), .Y(n1037) );
CLKAND2X2TS U3263 ( .A(n1034), .B(n1037), .Y(n2887) );
XOR2X1TS U3264 ( .A(Op_MX[34]), .B(Op_MX[33]), .Y(n1035) );
NOR3X2TS U3265 ( .A(n1037), .B(n1035), .C(n1036), .Y(n2825) );
CLKAND2X2TS U3266 ( .A(n1035), .B(n1142), .Y(n2824) );
CLKAND2X2TS U3267 ( .A(n1037), .B(n1036), .Y(n1139) );
AOI21X1TS U3268 ( .A0(Op_MY[50]), .A1(n2825), .B0(n1038), .Y(n1039) );
XNOR2X1TS U3269 ( .A(n3015), .B(n1040), .Y(n1245) );
AOI2BB2X2TS U3270 ( .B0(Op_MX[31]), .B1(n970), .A0N(n970), .A1N(Op_MX[31]),
.Y(n1043) );
INVX2TS U3271 ( .A(n1043), .Y(n1041) );
OAI2BB2X2TS U3272 ( .B0(Op_MX[30]), .B1(Op_MX[29]), .A0N(Op_MX[29]), .A1N(
Op_MX[30]), .Y(n1167) );
INVX2TS U3273 ( .A(n1167), .Y(n1044) );
CLKAND2X2TS U3274 ( .A(n1041), .B(n1044), .Y(n1164) );
XOR2X1TS U3275 ( .A(Op_MX[31]), .B(Op_MX[30]), .Y(n1042) );
NOR3X2TS U3276 ( .A(n1044), .B(n1042), .C(n1043), .Y(n2831) );
CLKAND2X2TS U3277 ( .A(n1042), .B(n1167), .Y(n2830) );
INVX6TS U3278 ( .A(n2830), .Y(n2897) );
INVX6TS U3279 ( .A(n918), .Y(n2896) );
AOI21X1TS U3280 ( .A0(Op_MY[50]), .A1(n2831), .B0(n1045), .Y(n1046) );
XNOR2X1TS U3281 ( .A(n2898), .B(n1047), .Y(n1220) );
BUFX6TS U3282 ( .A(n1205), .Y(n2981) );
AOI22X1TS U3283 ( .A0(Op_MX[29]), .A1(n972), .B0(Op_MX[28]), .B1(
mult_x_23_n871), .Y(n1051) );
INVX2TS U3284 ( .A(n1051), .Y(n1048) );
INVX6TS U3285 ( .A(n914), .Y(n1203) );
CLKAND2X2TS U3286 ( .A(Op_MX[28]), .B(n913), .Y(n1209) );
AOI21X1TS U3287 ( .A0(n2832), .A1(n1056), .B0(n1209), .Y(n1049) );
XNOR2X1TS U3288 ( .A(n2981), .B(n1050), .Y(n2678) );
CLKAND2X2TS U3289 ( .A(Op_MX[27]), .B(n1051), .Y(n1210) );
INVX6TS U3290 ( .A(n1210), .Y(n1204) );
AOI21X1TS U3291 ( .A0(Op_MY[50]), .A1(n1056), .B0(n1052), .Y(n1053) );
XNOR2X1TS U3292 ( .A(n1205), .B(n1055), .Y(n1218) );
OAI22X1TS U3293 ( .A0(n3230), .A1(n1204), .B0(n1203), .B1(n3229), .Y(n1060)
);
OAI22X1TS U3294 ( .A0(n789), .A1(n760), .B0(n1057), .B1(n3220), .Y(n1059) );
OAI31X1TS U3295 ( .A0(n1060), .A1(n1205), .A2(n1059), .B0(n1058), .Y(n2680)
);
BUFX6TS U3296 ( .A(n944), .Y(n3224) );
OAI22X1TS U3297 ( .A0(n1203), .A1(n3225), .B0(n1057), .B1(n3224), .Y(n1063)
);
OAI22X1TS U3298 ( .A0(n789), .A1(n1204), .B0(n760), .B1(n3220), .Y(n1062) );
OAI31X1TS U3299 ( .A0(n1063), .A1(n1205), .A2(n1062), .B0(n1061), .Y(n2682)
);
OAI22X1TS U3300 ( .A0(n1203), .A1(n3368), .B0(n1057), .B1(n3343), .Y(n1068)
);
OAI22X1TS U3301 ( .A0(n1204), .A1(n3220), .B0(n760), .B1(n3224), .Y(n1067)
);
OAI31X1TS U3302 ( .A0(n1068), .A1(n1205), .A2(n1067), .B0(n1066), .Y(n2684)
);
BUFX6TS U3303 ( .A(n916), .Y(n3401) );
OAI22X1TS U3304 ( .A0(n1203), .A1(n3237), .B0(n1057), .B1(n3401), .Y(n1073)
);
OAI22X1TS U3305 ( .A0(n1204), .A1(n3224), .B0(n760), .B1(n3343), .Y(n1072)
);
OAI31X1TS U3306 ( .A0(n1073), .A1(mult_x_23_n871), .A2(n1072), .B0(n1071),
.Y(n2686) );
OAI22X1TS U3307 ( .A0(n1203), .A1(n3365), .B0(n1057), .B1(n3313), .Y(n1078)
);
OAI22X1TS U3308 ( .A0(n1204), .A1(n3343), .B0(n760), .B1(n3401), .Y(n1077)
);
OAI31X1TS U3309 ( .A0(n1078), .A1(mult_x_23_n871), .A2(n1077), .B0(n1076),
.Y(n2688) );
BUFX6TS U3310 ( .A(n937), .Y(n3398) );
OAI22X1TS U3311 ( .A0(n1203), .A1(n3399), .B0(n1057), .B1(n3398), .Y(n1083)
);
OAI22X1TS U3312 ( .A0(n1204), .A1(n3401), .B0(n760), .B1(n3313), .Y(n1082)
);
OAI31X1TS U3313 ( .A0(n1083), .A1(mult_x_23_n871), .A2(n1082), .B0(n1081),
.Y(n2690) );
OAI22X1TS U3314 ( .A0(n1203), .A1(n3348), .B0(n1057), .B1(n3196), .Y(n1088)
);
OAI22X1TS U3315 ( .A0(n1204), .A1(n3313), .B0(n760), .B1(n3398), .Y(n1087)
);
OAI31X1TS U3316 ( .A0(n1088), .A1(mult_x_23_n871), .A2(n1087), .B0(n1086),
.Y(n2692) );
BUFX6TS U3317 ( .A(n947), .Y(n3203) );
OAI22X1TS U3318 ( .A0(n1203), .A1(n3341), .B0(n1057), .B1(n3203), .Y(n1093)
);
OAI22X1TS U3319 ( .A0(n1204), .A1(n3398), .B0(n760), .B1(n3196), .Y(n1092)
);
OAI31X1TS U3320 ( .A0(n1093), .A1(mult_x_23_n871), .A2(n1092), .B0(n1091),
.Y(n2694) );
OAI22X1TS U3321 ( .A0(n1203), .A1(n3360), .B0(n1057), .B1(n3309), .Y(n1098)
);
OAI22X1TS U3322 ( .A0(n1204), .A1(n3196), .B0(n760), .B1(n3203), .Y(n1097)
);
OAI31X1TS U3323 ( .A0(n1098), .A1(mult_x_23_n871), .A2(n1097), .B0(n1096),
.Y(n2696) );
BUFX6TS U3324 ( .A(n940), .Y(n3323) );
OAI22X1TS U3325 ( .A0(n1203), .A1(n3235), .B0(n1057), .B1(n3323), .Y(n1103)
);
OAI22X1TS U3326 ( .A0(n1204), .A1(n3203), .B0(n760), .B1(n3309), .Y(n1102)
);
OAI31X1TS U3327 ( .A0(n1103), .A1(mult_x_23_n871), .A2(n1102), .B0(n1101),
.Y(n1216) );
BUFX6TS U3328 ( .A(n957), .Y(n3322) );
OAI22X1TS U3329 ( .A0(n1203), .A1(n3357), .B0(n1057), .B1(n3322), .Y(n1108)
);
OAI22X1TS U3330 ( .A0(n1204), .A1(n3309), .B0(n760), .B1(n3323), .Y(n1107)
);
OAI31X1TS U3331 ( .A0(n1108), .A1(mult_x_23_n871), .A2(n1107), .B0(n1106),
.Y(n2698) );
BUFX6TS U3332 ( .A(n948), .Y(n3320) );
OAI22X1TS U3333 ( .A0(n1203), .A1(n3355), .B0(n1057), .B1(n3320), .Y(n1113)
);
OAI22X1TS U3334 ( .A0(n1204), .A1(n3323), .B0(n760), .B1(n3322), .Y(n1112)
);
OAI31X1TS U3335 ( .A0(n1113), .A1(mult_x_23_n871), .A2(n1112), .B0(n1111),
.Y(n2700) );
BUFX6TS U3336 ( .A(n958), .Y(n3182) );
OAI22X1TS U3337 ( .A0(n1203), .A1(n3183), .B0(n1057), .B1(n3182), .Y(n1118)
);
OAI22X1TS U3338 ( .A0(n1204), .A1(n3322), .B0(n760), .B1(n3320), .Y(n1117)
);
OAI31X1TS U3339 ( .A0(n1118), .A1(mult_x_23_n871), .A2(n1117), .B0(n1116),
.Y(n1226) );
BUFX6TS U3340 ( .A(n950), .Y(n3390) );
OAI22X1TS U3341 ( .A0(n1203), .A1(n3172), .B0(n1057), .B1(n3390), .Y(n1123)
);
OAI22X1TS U3342 ( .A0(n1204), .A1(n3320), .B0(n760), .B1(n3182), .Y(n1122)
);
OAI31X1TS U3343 ( .A0(n1123), .A1(mult_x_23_n871), .A2(n1122), .B0(n1121),
.Y(n3379) );
CMPR32X2TS U3344 ( .A(Op_MY[36]), .B(Op_MY[37]), .C(n1124), .CO(n1119), .S(
n1125) );
BUFX3TS U3345 ( .A(n939), .Y(n2965) );
OAI22X1TS U3346 ( .A0(n1203), .A1(n3339), .B0(n1057), .B1(n2965), .Y(n1128)
);
OAI22X1TS U3347 ( .A0(n1204), .A1(n3182), .B0(n760), .B1(n3390), .Y(n1127)
);
OAI31X1TS U3348 ( .A0(n1128), .A1(mult_x_23_n871), .A2(n1127), .B0(n1126),
.Y(n1224) );
CMPR32X2TS U3349 ( .A(Op_MY[35]), .B(Op_MY[36]), .C(n1129), .CO(n1124), .S(
n1130) );
OAI22X1TS U3350 ( .A0(n1203), .A1(n3388), .B0(n760), .B1(n2965), .Y(n1133)
);
OAI22X1TS U3351 ( .A0(n1204), .A1(n3390), .B0(n1057), .B1(n917), .Y(n1132)
);
OAI31X1TS U3352 ( .A0(n1133), .A1(mult_x_23_n871), .A2(n1132), .B0(n1131),
.Y(n3377) );
BUFX6TS U3353 ( .A(n911), .Y(n3245) );
OAI22X1TS U3354 ( .A0(n3010), .A1(n3260), .B0(n2930), .B1(n3245), .Y(n1138)
);
BUFX6TS U3355 ( .A(n952), .Y(n3261) );
OAI22X1TS U3356 ( .A0(n752), .A1(n3261), .B0(n757), .B1(n764), .Y(n1137) );
OAI31X1TS U3357 ( .A0(n1138), .A1(n5336), .A2(n1137), .B0(n1136), .Y(n3443)
);
AOI222X4TS U3358 ( .A0(n2887), .A1(n3267), .B0(n1139), .B1(Op_MY[28]), .C0(
n2824), .C1(n848), .Y(n1140) );
XNOR2X1TS U3359 ( .A(Op_MX[35]), .B(n1140), .Y(n1149) );
OAI21XLTS U3360 ( .A0(n1142), .A1(n3245), .B0(Op_MX[35]), .Y(n1141) );
INVX3TS U3361 ( .A(n1164), .Y(n2895) );
BUFX6TS U3362 ( .A(n945), .Y(n3263) );
OAI22X1TS U3363 ( .A0(n2895), .A1(n3254), .B0(n2828), .B1(n3263), .Y(n1147)
);
BUFX6TS U3364 ( .A(n2898), .Y(n2901) );
BUFX6TS U3365 ( .A(n946), .Y(n3274) );
BUFX6TS U3366 ( .A(n954), .Y(n3272) );
OAI22X1TS U3367 ( .A0(n2896), .A1(n3274), .B0(n2897), .B1(n3272), .Y(n1146)
);
OAI31X1TS U3368 ( .A0(n1147), .A1(n2901), .A2(n1146), .B0(n1145), .Y(n2802)
);
ADDHXLTS U3369 ( .A(n1149), .B(n1148), .CO(n3442), .S(n1175) );
OAI22X1TS U3370 ( .A0(n2895), .A1(n3262), .B0(n2828), .B1(n3261), .Y(n1154)
);
OAI22X1TS U3371 ( .A0(n2896), .A1(n3272), .B0(n2897), .B1(n3263), .Y(n1153)
);
OAI31X1TS U3372 ( .A0(n1154), .A1(n2901), .A2(n1153), .B0(n1152), .Y(n1174)
);
CMPR32X2TS U3373 ( .A(Op_MY[29]), .B(n846), .C(n1155), .CO(n1150), .S(n1156)
);
OAI22X1TS U3374 ( .A0(n2895), .A1(n3280), .B0(n2828), .B1(n764), .Y(n1159)
);
OAI22X1TS U3375 ( .A0(n2896), .A1(n3263), .B0(n2897), .B1(n3261), .Y(n1158)
);
OAI31X1TS U3376 ( .A0(n1159), .A1(n2901), .A2(n1158), .B0(n1157), .Y(n1183)
);
ADDHXLTS U3377 ( .A(Op_MX[35]), .B(n1160), .CO(n1148), .S(n1182) );
OAI22X1TS U3378 ( .A0(n2891), .A1(n3260), .B0(n2828), .B1(n3245), .Y(n1163)
);
OAI22X1TS U3379 ( .A0(n2896), .A1(n3261), .B0(n2897), .B1(n764), .Y(n1162)
);
OAI31X1TS U3380 ( .A0(n1163), .A1(n2901), .A2(n1162), .B0(n1161), .Y(n1190)
);
XNOR2X1TS U3381 ( .A(Op_MX[32]), .B(n1165), .Y(n1195) );
OAI21XLTS U3382 ( .A0(n1167), .A1(n3245), .B0(Op_MX[32]), .Y(n1166) );
OAI22X1TS U3383 ( .A0(n1203), .A1(n3337), .B0(n1204), .B1(n2965), .Y(n1172)
);
BUFX3TS U3384 ( .A(n917), .Y(n3066) );
BUFX6TS U3385 ( .A(n955), .Y(n3275) );
OAI22X1TS U3386 ( .A0(n760), .A1(n3066), .B0(n1057), .B1(n3275), .Y(n1171)
);
OAI31X1TS U3387 ( .A0(n1172), .A1(mult_x_23_n871), .A2(n1171), .B0(n1170),
.Y(n1231) );
CMPR32X2TS U3388 ( .A(n1175), .B(n1174), .C(n1173), .CO(n2801), .S(n3416) );
OAI22X1TS U3389 ( .A0(n1203), .A1(n3112), .B0(n1057), .B1(n3274), .Y(n1180)
);
OAI22X1TS U3390 ( .A0(n1204), .A1(n3066), .B0(n760), .B1(n3275), .Y(n1179)
);
OAI31X1TS U3391 ( .A0(n1180), .A1(mult_x_23_n871), .A2(n1179), .B0(n1178),
.Y(n3415) );
CMPR32X2TS U3392 ( .A(n1183), .B(n1182), .C(n1181), .CO(n1173), .S(n1229) );
OAI22X1TS U3393 ( .A0(n1203), .A1(n3273), .B0(n1057), .B1(n3272), .Y(n1188)
);
OAI22X1TS U3394 ( .A0(n1204), .A1(n3275), .B0(n760), .B1(n3274), .Y(n1187)
);
OAI31X1TS U3395 ( .A0(n1188), .A1(n2981), .A2(n1187), .B0(n1186), .Y(n1228)
);
ADDHXLTS U3396 ( .A(n1190), .B(n1189), .CO(n1181), .S(n3375) );
OAI22X1TS U3397 ( .A0(n1203), .A1(n3254), .B0(n1057), .B1(n3263), .Y(n1193)
);
OAI22X1TS U3398 ( .A0(n1204), .A1(n3274), .B0(n760), .B1(n3272), .Y(n1192)
);
OAI31X1TS U3399 ( .A0(n1193), .A1(n2981), .A2(n1192), .B0(n1191), .Y(n3374)
);
ADDHXLTS U3400 ( .A(n1195), .B(n1194), .CO(n1189), .S(n1243) );
OAI22X1TS U3401 ( .A0(n1203), .A1(n3262), .B0(n1057), .B1(n3261), .Y(n1198)
);
OAI22X1TS U3402 ( .A0(n1204), .A1(n3272), .B0(n760), .B1(n3263), .Y(n1197)
);
OAI31X1TS U3403 ( .A0(n1198), .A1(n2981), .A2(n1197), .B0(n1196), .Y(n1242)
);
ADDHXLTS U3404 ( .A(Op_MX[32]), .B(n1199), .CO(n1194), .S(n3372) );
OAI22X1TS U3405 ( .A0(n1203), .A1(n3280), .B0(n1057), .B1(n764), .Y(n1202)
);
OAI22X1TS U3406 ( .A0(n1204), .A1(n3263), .B0(n760), .B1(n3261), .Y(n1201)
);
OAI31X1TS U3407 ( .A0(n1202), .A1(n2981), .A2(n1201), .B0(n1200), .Y(n3371)
);
OAI22X1TS U3408 ( .A0(n1203), .A1(n3260), .B0(n1057), .B1(n3245), .Y(n1208)
);
OAI22X1TS U3409 ( .A0(n1204), .A1(n3261), .B0(n760), .B1(n764), .Y(n1207) );
OAI31X1TS U3410 ( .A0(n1208), .A1(n2981), .A2(n1207), .B0(n1206), .Y(n3413)
);
XNOR2X1TS U3411 ( .A(Op_MX[29]), .B(n1211), .Y(n3411) );
OAI21XLTS U3412 ( .A0(n913), .A1(n911), .B0(Op_MX[29]), .Y(n1212) );
NOR2X2TS U3413 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[0]), .Y(
n4872) );
NAND2X1TS U3414 ( .A(FS_Module_state_reg[3]), .B(n4872), .Y(n3671) );
INVX2TS U3415 ( .A(n3671), .Y(n3771) );
NAND3XLTS U3416 ( .A(n728), .B(FSM_add_overflow_flag), .C(n3771), .Y(n1246)
);
INVX4TS U3417 ( .A(n734), .Y(n5199) );
INVX2TS U3418 ( .A(n1530), .Y(n1310) );
INVX2TS U3419 ( .A(n1522), .Y(n1315) );
NOR2X1TS U3420 ( .A(n1317), .B(n1316), .Y(n1517) );
INVX2TS U3421 ( .A(n1514), .Y(n1320) );
NOR2X1TS U3422 ( .A(n1322), .B(n1321), .Y(n1509) );
NAND2X1TS U3423 ( .A(n1324), .B(n1323), .Y(n1506) );
NOR2X1TS U3424 ( .A(n1327), .B(n1326), .Y(n1501) );
NAND2X1TS U3425 ( .A(n1327), .B(n1326), .Y(n1502) );
NAND2X1TS U3426 ( .A(n1329), .B(n1328), .Y(n1498) );
INVX2TS U3427 ( .A(n1498), .Y(n1330) );
NOR2X1TS U3428 ( .A(n1332), .B(n1331), .Y(n1493) );
NAND2X1TS U3429 ( .A(n1332), .B(n1331), .Y(n1494) );
NAND2X1TS U3430 ( .A(n1334), .B(n1333), .Y(n1490) );
NOR2X1TS U3431 ( .A(n1337), .B(n1336), .Y(n1485) );
NAND2X1TS U3432 ( .A(n1339), .B(n1338), .Y(n1482) );
NOR2X1TS U3433 ( .A(n1342), .B(n1341), .Y(n1477) );
NAND2X1TS U3434 ( .A(n1342), .B(n1341), .Y(n1478) );
INVX2TS U3435 ( .A(Sgf_operation_ODD1_Q_left[39]), .Y(n1348) );
NOR2X1TS U3436 ( .A(n1347), .B(n1346), .Y(n1469) );
NAND2X1TS U3437 ( .A(n1347), .B(n1346), .Y(n1470) );
INVX2TS U3438 ( .A(Sgf_operation_ODD1_Q_left[40]), .Y(n1352) );
NAND2X1TS U3439 ( .A(n1350), .B(n1349), .Y(n1466) );
INVX2TS U3440 ( .A(Sgf_operation_ODD1_Q_left[41]), .Y(n1355) );
NOR2X1TS U3441 ( .A(n1354), .B(n1353), .Y(n1461) );
NAND2X1TS U3442 ( .A(n1354), .B(n1353), .Y(n1462) );
INVX2TS U3443 ( .A(Sgf_operation_ODD1_Q_left[42]), .Y(n1359) );
INVX2TS U3444 ( .A(Sgf_operation_ODD1_Q_left[43]), .Y(n1362) );
NOR2X1TS U3445 ( .A(n1361), .B(n1360), .Y(n1453) );
NAND2X1TS U3446 ( .A(n1361), .B(n1360), .Y(n1454) );
INVX2TS U3447 ( .A(Sgf_operation_ODD1_Q_left[44]), .Y(n1367) );
NAND2X1TS U3448 ( .A(n1364), .B(n1363), .Y(n1450) );
INVX2TS U3449 ( .A(n1450), .Y(n1365) );
INVX2TS U3450 ( .A(Sgf_operation_ODD1_Q_right[45]), .Y(n1371) );
INVX2TS U3451 ( .A(Sgf_operation_ODD1_Q_left[45]), .Y(n1370) );
NOR2X1TS U3452 ( .A(n1369), .B(n1368), .Y(n1445) );
INVX2TS U3453 ( .A(Sgf_operation_ODD1_Q_right[46]), .Y(n1376) );
INVX2TS U3454 ( .A(Sgf_operation_ODD1_Q_left[46]), .Y(n1375) );
INVX2TS U3455 ( .A(Sgf_operation_ODD1_Q_right[47]), .Y(n1380) );
INVX2TS U3456 ( .A(Sgf_operation_ODD1_Q_left[47]), .Y(n1379) );
NOR2X1TS U3457 ( .A(n1378), .B(n1377), .Y(n1437) );
NAND2X1TS U3458 ( .A(n1378), .B(n1377), .Y(n1438) );
INVX2TS U3459 ( .A(Sgf_operation_ODD1_Q_right[48]), .Y(n1385) );
INVX2TS U3460 ( .A(Sgf_operation_ODD1_Q_left[48]), .Y(n1384) );
INVX2TS U3461 ( .A(Sgf_operation_ODD1_Q_right[49]), .Y(n1389) );
INVX2TS U3462 ( .A(Sgf_operation_ODD1_Q_left[49]), .Y(n1388) );
NOR2X1TS U3463 ( .A(n1387), .B(n1386), .Y(n1429) );
NAND2X1TS U3464 ( .A(n1387), .B(n1386), .Y(n1430) );
INVX2TS U3465 ( .A(Sgf_operation_ODD1_Q_right[50]), .Y(n1394) );
INVX2TS U3466 ( .A(Sgf_operation_ODD1_Q_left[50]), .Y(n1393) );
NAND2X1TS U3467 ( .A(n1391), .B(n1390), .Y(n1426) );
INVX2TS U3468 ( .A(Sgf_operation_ODD1_Q_right[51]), .Y(n1397) );
NOR2X1TS U3469 ( .A(n1396), .B(n1395), .Y(n1421) );
NAND2X1TS U3470 ( .A(n1396), .B(n1395), .Y(n1422) );
INVX2TS U3471 ( .A(Sgf_operation_ODD1_Q_right[52]), .Y(n1402) );
XNOR2X1TS U3472 ( .A(n1402), .B(Sgf_operation_ODD1_Q_middle[52]), .Y(n1400)
);
NAND2X1TS U3473 ( .A(n1400), .B(n1399), .Y(n1418) );
INVX2TS U3474 ( .A(n1418), .Y(n1401) );
INVX2TS U3475 ( .A(Sgf_operation_ODD1_Q_right[53]), .Y(n1405) );
XNOR2X1TS U3476 ( .A(n1405), .B(Sgf_operation_ODD1_Q_middle[53]), .Y(n1404)
);
OR2X1TS U3477 ( .A(n1402), .B(Sgf_operation_ODD1_Q_middle[52]), .Y(n1403) );
NOR2X1TS U3478 ( .A(n1404), .B(n1403), .Y(n1413) );
NAND2X1TS U3479 ( .A(n1404), .B(n1403), .Y(n1414) );
OR2X1TS U3480 ( .A(n1405), .B(Sgf_operation_ODD1_Q_middle[53]), .Y(n1406) );
INVX2TS U3481 ( .A(Sgf_operation_ODD1_Q_middle[55]), .Y(n1408) );
XOR2X1TS U3482 ( .A(n1409), .B(Sgf_operation_ODD1_Q_middle[55]), .Y(n3744)
);
NAND2X1TS U3483 ( .A(n920), .B(n1410), .Y(n1411) );
INVX2TS U3484 ( .A(n1413), .Y(n1415) );
NAND2X1TS U3485 ( .A(n1415), .B(n1414), .Y(n1416) );
INVX2TS U3486 ( .A(n1421), .Y(n1423) );
NAND2X1TS U3487 ( .A(n1423), .B(n1422), .Y(n1424) );
NAND2X1TS U3488 ( .A(n921), .B(n1426), .Y(n1427) );
XNOR2X1TS U3489 ( .A(n1428), .B(n1427), .Y(n3729) );
INVX2TS U3490 ( .A(n1429), .Y(n1431) );
NAND2X1TS U3491 ( .A(n1431), .B(n1430), .Y(n1432) );
NAND2X1TS U3492 ( .A(n926), .B(n1434), .Y(n1435) );
XNOR2X1TS U3493 ( .A(n1436), .B(n1435), .Y(n3723) );
INVX2TS U3494 ( .A(n1437), .Y(n1439) );
NAND2X1TS U3495 ( .A(n1439), .B(n1438), .Y(n1440) );
NAND2X1TS U3496 ( .A(n925), .B(n1442), .Y(n1443) );
INVX2TS U3497 ( .A(n1445), .Y(n1447) );
NAND2X1TS U3498 ( .A(n1447), .B(n1446), .Y(n1448) );
NAND2X1TS U3499 ( .A(n924), .B(n1450), .Y(n1451) );
XNOR2X1TS U3500 ( .A(n1452), .B(n1451), .Y(n3711) );
INVX2TS U3501 ( .A(n1453), .Y(n1455) );
NAND2X1TS U3502 ( .A(n1455), .B(n1454), .Y(n1456) );
NAND2X1TS U3503 ( .A(n923), .B(n1458), .Y(n1459) );
XNOR2X1TS U3504 ( .A(n1460), .B(n1459), .Y(n3705) );
INVX2TS U3505 ( .A(n1461), .Y(n1463) );
NAND2X1TS U3506 ( .A(n1463), .B(n1462), .Y(n1464) );
NAND2X1TS U3507 ( .A(n922), .B(n1466), .Y(n1467) );
XNOR2X1TS U3508 ( .A(n1468), .B(n1467), .Y(n3699) );
INVX2TS U3509 ( .A(n1469), .Y(n1471) );
NAND2X1TS U3510 ( .A(n1471), .B(n1470), .Y(n1472) );
NAND2X1TS U3511 ( .A(n907), .B(n1474), .Y(n1475) );
XNOR2X1TS U3512 ( .A(n1476), .B(n1475), .Y(n5082) );
INVX2TS U3513 ( .A(n1477), .Y(n1479) );
NAND2X1TS U3514 ( .A(n906), .B(n1482), .Y(n1483) );
XNOR2X1TS U3515 ( .A(n1484), .B(n1483), .Y(n5088) );
INVX2TS U3516 ( .A(n1485), .Y(n1487) );
NAND2X1TS U3517 ( .A(n1487), .B(n1486), .Y(n1488) );
NAND2X1TS U3518 ( .A(n905), .B(n1490), .Y(n1491) );
NAND2X1TS U3519 ( .A(n904), .B(n1498), .Y(n1499) );
XNOR2X1TS U3520 ( .A(n1500), .B(n1499), .Y(n5100) );
NAND2X1TS U3521 ( .A(n1543), .B(n1542), .Y(n1544) );
NAND2X1TS U3522 ( .A(n961), .B(n1546), .Y(n1547) );
INVX2TS U3523 ( .A(n1549), .Y(n1551) );
NAND2X1TS U3524 ( .A(n1551), .B(n1550), .Y(n1552) );
INVX2TS U3525 ( .A(n1557), .Y(n1559) );
INVX2TS U3526 ( .A(n1577), .Y(n1565) );
INVX2TS U3527 ( .A(n1597), .Y(n1586) );
NAND2X1TS U3528 ( .A(n1568), .B(n1586), .Y(n1570) );
INVX2TS U3529 ( .A(n1576), .Y(n1566) );
INVX2TS U3530 ( .A(n1571), .Y(n1573) );
NAND2X1TS U3531 ( .A(n1586), .B(n1577), .Y(n1579) );
INVX2TS U3532 ( .A(n1580), .Y(n1582) );
INVX2TS U3533 ( .A(n1598), .Y(n1587) );
INVX2TS U3534 ( .A(n1591), .Y(n1593) );
INVX2TS U3535 ( .A(n1606), .Y(n1608) );
INVX2TS U3536 ( .A(n1611), .Y(n1614) );
INVX2TS U3537 ( .A(n1642), .Y(n1632) );
INVX2TS U3538 ( .A(n1660), .Y(n1662) );
INVX2TS U3539 ( .A(n1665), .Y(n1667) );
INVX2TS U3540 ( .A(n1670), .Y(n1672) );
NAND2X2TS U3541 ( .A(n1672), .B(n1671), .Y(n1674) );
NAND2X1TS U3542 ( .A(n1683), .B(n2657), .Y(n2661) );
INVX2TS U3543 ( .A(n1760), .Y(n1685) );
INVX2TS U3544 ( .A(Op_MX[11]), .Y(n4278) );
INVX2TS U3545 ( .A(n2087), .Y(n2006) );
NOR2X2TS U3546 ( .A(n843), .B(Op_MX[16]), .Y(n1968) );
INVX2TS U3547 ( .A(n2053), .Y(n1989) );
INVX2TS U3548 ( .A(n1992), .Y(n1690) );
INVX2TS U3549 ( .A(n2086), .Y(n1696) );
NAND2X1TS U3550 ( .A(Op_MX[40]), .B(Op_MX[13]), .Y(n2093) );
INVX2TS U3551 ( .A(n2093), .Y(n1695) );
NAND2X1TS U3552 ( .A(n843), .B(Op_MX[16]), .Y(n1969) );
OAI21X1TS U3553 ( .A0(n1968), .A1(n1959), .B0(n1969), .Y(n2114) );
NAND2X1TS U3554 ( .A(Op_MX[44]), .B(DP_OP_169J45_123_4229_n2458), .Y(n2126)
);
AOI21X4TS U3555 ( .A0(n1736), .A1(n1707), .B0(n1706), .Y(n2244) );
NOR2X2TS U3556 ( .A(n844), .B(Op_MX[19]), .Y(n1920) );
NOR2X1TS U3557 ( .A(n1919), .B(n1920), .Y(n2240) );
NAND2X1TS U3558 ( .A(n962), .B(n2240), .Y(n2236) );
NAND2X1TS U3559 ( .A(n1708), .B(n936), .Y(n1713) );
NOR2X1TS U3560 ( .A(n2236), .B(n1713), .Y(n1874) );
NAND2X1TS U3561 ( .A(n1716), .B(n1874), .Y(n1721) );
NAND2X1TS U3562 ( .A(n844), .B(Op_MX[19]), .Y(n1921) );
OAI21X1TS U3563 ( .A0(n1920), .A1(n1918), .B0(n1921), .Y(n2241) );
NAND2X1TS U3564 ( .A(Op_MX[47]), .B(n730), .Y(n2245) );
INVX2TS U3565 ( .A(n2245), .Y(n1710) );
AOI21X2TS U3566 ( .A0(n962), .A1(n2241), .B0(n1710), .Y(n2235) );
NAND2X1TS U3567 ( .A(Op_MX[21]), .B(Op_MX[48]), .Y(n2237) );
INVX2TS U3568 ( .A(n2237), .Y(n1867) );
NAND2X1TS U3569 ( .A(Op_MX[49]), .B(Op_MX[22]), .Y(n1871) );
INVX2TS U3570 ( .A(n1871), .Y(n1711) );
AOI21X1TS U3571 ( .A0(n936), .A1(n1867), .B0(n1711), .Y(n1712) );
OAI21X1TS U3572 ( .A0(n2235), .A1(n1713), .B0(n1712), .Y(n1875) );
NAND2X1TS U3573 ( .A(Op_MX[50]), .B(n729), .Y(n1884) );
NAND2X1TS U3574 ( .A(Op_MX[51]), .B(Op_MX[24]), .Y(n2231) );
INVX2TS U3575 ( .A(n2231), .Y(n1887) );
AOI21X1TS U3576 ( .A0(n1875), .A1(n1716), .B0(n1715), .Y(n1720) );
XNOR2X1TS U3577 ( .A(n815), .B(n898), .Y(n2248) );
INVX2TS U3578 ( .A(Op_MY[24]), .Y(n3488) );
OAI21XLTS U3579 ( .A0(Op_MY[51]), .A1(n4893), .B0(Op_MY[23]), .Y(n1718) );
NAND2X1TS U3580 ( .A(Op_MY[51]), .B(n4893), .Y(n1717) );
NAND2X1TS U3581 ( .A(Op_MY[25]), .B(n1891), .Y(n1719) );
OAI22X1TS U3582 ( .A0(n2248), .A1(n799), .B0(n741), .B1(n853), .Y(n1785) );
OAI21X1TS U3583 ( .A0(n2244), .A1(n1721), .B0(n1720), .Y(n1722) );
NOR2X1TS U3584 ( .A(n787), .B(n853), .Y(n1786) );
NAND2X1TS U3585 ( .A(Op_MY[29]), .B(Op_MY[2]), .Y(n1724) );
XNOR2X2TS U3586 ( .A(n846), .B(Op_MY[3]), .Y(n1762) );
CLKXOR2X4TS U3587 ( .A(n1727), .B(n1726), .Y(n2602) );
NAND2X1TS U3588 ( .A(Op_MY[31]), .B(Op_MY[4]), .Y(n1732) );
XNOR2X4TS U3589 ( .A(n2014), .B(n2013), .Y(n2598) );
INVX2TS U3590 ( .A(n892), .Y(n2572) );
XNOR2X1TS U3591 ( .A(n2660), .B(n2598), .Y(n1735) );
OAI21X1TS U3592 ( .A0(n2125), .A1(n1764), .B0(n1765), .Y(n1741) );
INVX2TS U3593 ( .A(n1737), .Y(n1739) );
NAND2X1TS U3594 ( .A(n1739), .B(n1738), .Y(n1740) );
INVX2TS U3595 ( .A(n1742), .Y(n1745) );
INVX2TS U3596 ( .A(n1743), .Y(n1744) );
OAI21X1TS U3597 ( .A0(n2125), .A1(n1745), .B0(n1744), .Y(n1748) );
NAND2X1TS U3598 ( .A(n969), .B(n1746), .Y(n1747) );
INVX2TS U3599 ( .A(n1757), .Y(n1759) );
NAND2X1TS U3600 ( .A(n1759), .B(n1758), .Y(n1761) );
XNOR2X4TS U3601 ( .A(n1763), .B(n1762), .Y(n2627) );
XNOR2X1TS U3602 ( .A(n834), .B(n2627), .Y(n1769) );
INVX2TS U3603 ( .A(n1764), .Y(n1766) );
OAI22X1TS U3604 ( .A0(n2632), .A1(n1769), .B0(n2631), .B1(n2629), .Y(n1770)
);
NOR2BX1TS U3605 ( .AN(n2660), .B(n2602), .Y(n1778) );
XNOR2X1TS U3606 ( .A(n839), .B(n2627), .Y(n1774) );
XNOR2X1TS U3607 ( .A(n2660), .B(n2627), .Y(n1775) );
INVX2TS U3608 ( .A(n2627), .Y(n2604) );
NAND2BXLTS U3609 ( .AN(n2660), .B(n2627), .Y(n1779) );
OAI22X1TS U3610 ( .A0(n2632), .A1(n2604), .B0(n2629), .B1(n1779), .Y(n1851)
);
NOR2BX1TS U3611 ( .AN(n2660), .B(n2629), .Y(n1853) );
INVX2TS U3612 ( .A(DP_OP_169J45_123_4229_n147), .Y(n1852) );
AO21XLTS U3613 ( .A0(n799), .A1(n741), .B0(n852), .Y(n1787) );
XOR3X1TS U3614 ( .A(n1787), .B(n797), .C(n1786), .Y(n1788) );
XOR2XLTS U3615 ( .A(n1789), .B(n1788), .Y(n1790) );
CMPR32X2TS U3616 ( .A(DP_OP_169J45_123_4229_n155), .B(n1793), .C(n1792),
.CO(n1791), .S(Sgf_operation_ODD1_middle_N54) );
CMPR32X2TS U3617 ( .A(DP_OP_169J45_123_4229_n156), .B(
DP_OP_169J45_123_4229_n158), .C(n1794), .CO(n1792), .S(
Sgf_operation_ODD1_middle_N53) );
CMPR32X2TS U3618 ( .A(DP_OP_169J45_123_4229_n159), .B(
DP_OP_169J45_123_4229_n163), .C(n1795), .CO(n1794), .S(
Sgf_operation_ODD1_middle_N52) );
CMPR32X2TS U3619 ( .A(DP_OP_169J45_123_4229_n168), .B(
DP_OP_169J45_123_4229_n164), .C(n1796), .CO(n1795), .S(
Sgf_operation_ODD1_middle_N51) );
CMPR32X2TS U3620 ( .A(DP_OP_169J45_123_4229_n175), .B(
DP_OP_169J45_123_4229_n169), .C(n1797), .CO(n1796), .S(
Sgf_operation_ODD1_middle_N50) );
CMPR32X2TS U3621 ( .A(DP_OP_169J45_123_4229_n176), .B(
DP_OP_169J45_123_4229_n181), .C(n1798), .CO(n1797), .S(
Sgf_operation_ODD1_middle_N49) );
CMPR32X2TS U3622 ( .A(DP_OP_169J45_123_4229_n182), .B(
DP_OP_169J45_123_4229_n189), .C(n1799), .CO(n1798), .S(
Sgf_operation_ODD1_middle_N48) );
CMPR32X2TS U3623 ( .A(DP_OP_169J45_123_4229_n190), .B(
DP_OP_169J45_123_4229_n197), .C(n1800), .CO(n1799), .S(
Sgf_operation_ODD1_middle_N47) );
CMPR32X2TS U3624 ( .A(DP_OP_169J45_123_4229_n198), .B(
DP_OP_169J45_123_4229_n207), .C(n1801), .CO(n1800), .S(
Sgf_operation_ODD1_middle_N46) );
CMPR32X2TS U3625 ( .A(DP_OP_169J45_123_4229_n208), .B(
DP_OP_169J45_123_4229_n216), .C(n1802), .CO(n1801), .S(
Sgf_operation_ODD1_middle_N45) );
CMPR32X2TS U3626 ( .A(DP_OP_169J45_123_4229_n217), .B(
DP_OP_169J45_123_4229_n227), .C(n1803), .CO(n1802), .S(
Sgf_operation_ODD1_middle_N44) );
CMPR32X2TS U3627 ( .A(DP_OP_169J45_123_4229_n238), .B(
DP_OP_169J45_123_4229_n228), .C(n1804), .CO(n1803), .S(
Sgf_operation_ODD1_middle_N43) );
CMPR32X2TS U3628 ( .A(DP_OP_169J45_123_4229_n251), .B(
DP_OP_169J45_123_4229_n239), .C(n1805), .CO(n1804), .S(
Sgf_operation_ODD1_middle_N42) );
CMPR32X2TS U3629 ( .A(DP_OP_169J45_123_4229_n252), .B(
DP_OP_169J45_123_4229_n263), .C(n1806), .CO(n1805), .S(
Sgf_operation_ODD1_middle_N41) );
CMPR32X2TS U3630 ( .A(DP_OP_169J45_123_4229_n264), .B(
DP_OP_169J45_123_4229_n277), .C(n1807), .CO(n1806), .S(
Sgf_operation_ODD1_middle_N40) );
AFHCINX2TS U3631 ( .CIN(n1808), .B(DP_OP_169J45_123_4229_n278), .A(
DP_OP_169J45_123_4229_n291), .S(Sgf_operation_ODD1_middle_N39), .CO(
n1807) );
AFHCONX2TS U3632 ( .A(DP_OP_169J45_123_4229_n307), .B(
DP_OP_169J45_123_4229_n292), .CI(n1809), .CON(n1808), .S(
Sgf_operation_ODD1_middle_N38) );
AFHCINX2TS U3633 ( .CIN(n1810), .B(DP_OP_169J45_123_4229_n308), .A(
DP_OP_169J45_123_4229_n322), .S(Sgf_operation_ODD1_middle_N37), .CO(
n1809) );
AFHCONX2TS U3634 ( .A(DP_OP_169J45_123_4229_n339), .B(
DP_OP_169J45_123_4229_n323), .CI(n1811), .CON(n1810), .S(
Sgf_operation_ODD1_middle_N36) );
AFHCINX2TS U3635 ( .CIN(n1812), .B(DP_OP_169J45_123_4229_n340), .A(
DP_OP_169J45_123_4229_n356), .S(Sgf_operation_ODD1_middle_N35), .CO(
n1811) );
AFHCONX2TS U3636 ( .A(DP_OP_169J45_123_4229_n375), .B(
DP_OP_169J45_123_4229_n357), .CI(n1813), .CON(n1812), .S(
Sgf_operation_ODD1_middle_N34) );
AFHCINX2TS U3637 ( .CIN(n1814), .B(DP_OP_169J45_123_4229_n376), .A(
DP_OP_169J45_123_4229_n393), .S(Sgf_operation_ODD1_middle_N33), .CO(
n1813) );
AFHCONX2TS U3638 ( .A(DP_OP_169J45_123_4229_n413), .B(
DP_OP_169J45_123_4229_n394), .CI(n1815), .CON(n1814), .S(
Sgf_operation_ODD1_middle_N32) );
AFHCINX2TS U3639 ( .CIN(n1816), .B(DP_OP_169J45_123_4229_n414), .A(
DP_OP_169J45_123_4229_n433), .S(Sgf_operation_ODD1_middle_N31), .CO(
n1815) );
AFHCONX2TS U3640 ( .A(DP_OP_169J45_123_4229_n455), .B(
DP_OP_169J45_123_4229_n434), .CI(n1817), .CON(n1816), .S(
Sgf_operation_ODD1_middle_N30) );
AFHCINX2TS U3641 ( .CIN(n1818), .B(DP_OP_169J45_123_4229_n456), .A(
DP_OP_169J45_123_4229_n476), .S(Sgf_operation_ODD1_middle_N29), .CO(
n1817) );
AFHCONX2TS U3642 ( .A(DP_OP_169J45_123_4229_n496), .B(
DP_OP_169J45_123_4229_n477), .CI(n1819), .CON(n1818), .S(
Sgf_operation_ODD1_middle_N28) );
AFHCINX2TS U3643 ( .CIN(n1820), .B(DP_OP_169J45_123_4229_n497), .A(
DP_OP_169J45_123_4229_n516), .S(Sgf_operation_ODD1_middle_N27), .CO(
n1819) );
AFHCONX2TS U3644 ( .A(DP_OP_169J45_123_4229_n534), .B(
DP_OP_169J45_123_4229_n517), .CI(n1821), .CON(n1820), .S(
Sgf_operation_ODD1_middle_N26) );
AFHCINX2TS U3645 ( .CIN(n1822), .B(DP_OP_169J45_123_4229_n535), .A(
DP_OP_169J45_123_4229_n553), .S(Sgf_operation_ODD1_middle_N25), .CO(
n1821) );
AFHCONX2TS U3646 ( .A(DP_OP_169J45_123_4229_n570), .B(
DP_OP_169J45_123_4229_n554), .CI(n1823), .CON(n1822), .S(
Sgf_operation_ODD1_middle_N24) );
AFHCINX2TS U3647 ( .CIN(n1824), .B(DP_OP_169J45_123_4229_n571), .A(
DP_OP_169J45_123_4229_n587), .S(Sgf_operation_ODD1_middle_N23), .CO(
n1823) );
AFHCONX2TS U3648 ( .A(DP_OP_169J45_123_4229_n602), .B(
DP_OP_169J45_123_4229_n588), .CI(n1825), .CON(n1824), .S(
Sgf_operation_ODD1_middle_N22) );
AFHCINX2TS U3649 ( .CIN(n1826), .B(DP_OP_169J45_123_4229_n603), .A(
DP_OP_169J45_123_4229_n618), .S(Sgf_operation_ODD1_middle_N21), .CO(
n1825) );
AFHCONX2TS U3650 ( .A(DP_OP_169J45_123_4229_n632), .B(
DP_OP_169J45_123_4229_n619), .CI(n1827), .CON(n1826), .S(
Sgf_operation_ODD1_middle_N20) );
AFHCINX2TS U3651 ( .CIN(n1828), .B(DP_OP_169J45_123_4229_n633), .A(
DP_OP_169J45_123_4229_n646), .S(Sgf_operation_ODD1_middle_N19), .CO(
n1827) );
AFHCONX2TS U3652 ( .A(DP_OP_169J45_123_4229_n658), .B(
DP_OP_169J45_123_4229_n647), .CI(n1829), .CON(n1828), .S(
Sgf_operation_ODD1_middle_N18) );
AFHCINX2TS U3653 ( .CIN(n1830), .B(DP_OP_169J45_123_4229_n659), .A(
DP_OP_169J45_123_4229_n671), .S(Sgf_operation_ODD1_middle_N17), .CO(
n1829) );
AFHCONX2TS U3654 ( .A(DP_OP_169J45_123_4229_n682), .B(
DP_OP_169J45_123_4229_n672), .CI(n1831), .CON(n1830), .S(
Sgf_operation_ODD1_middle_N16) );
AFHCINX2TS U3655 ( .CIN(n1832), .B(DP_OP_169J45_123_4229_n683), .A(
DP_OP_169J45_123_4229_n693), .S(Sgf_operation_ODD1_middle_N15), .CO(
n1831) );
AFHCONX2TS U3656 ( .A(DP_OP_169J45_123_4229_n702), .B(
DP_OP_169J45_123_4229_n694), .CI(n1833), .CON(n1832), .S(
Sgf_operation_ODD1_middle_N14) );
AFHCINX2TS U3657 ( .CIN(n1834), .B(DP_OP_169J45_123_4229_n703), .A(
DP_OP_169J45_123_4229_n712), .S(Sgf_operation_ODD1_middle_N13), .CO(
n1833) );
AFHCONX2TS U3658 ( .A(DP_OP_169J45_123_4229_n720), .B(
DP_OP_169J45_123_4229_n713), .CI(n1835), .CON(n1834), .S(
Sgf_operation_ODD1_middle_N12) );
AFHCINX2TS U3659 ( .CIN(n1836), .B(DP_OP_169J45_123_4229_n721), .A(
DP_OP_169J45_123_4229_n728), .S(Sgf_operation_ODD1_middle_N11), .CO(
n1835) );
AFHCONX2TS U3660 ( .A(DP_OP_169J45_123_4229_n734), .B(
DP_OP_169J45_123_4229_n729), .CI(n1837), .CON(n1836), .S(
Sgf_operation_ODD1_middle_N10) );
AFHCINX2TS U3661 ( .CIN(n1838), .B(DP_OP_169J45_123_4229_n735), .A(
DP_OP_169J45_123_4229_n741), .S(Sgf_operation_ODD1_middle_N9), .CO(
n1837) );
AFHCONX2TS U3662 ( .A(DP_OP_169J45_123_4229_n746), .B(
DP_OP_169J45_123_4229_n742), .CI(n1839), .CON(n1838), .S(
Sgf_operation_ODD1_middle_N8) );
AFHCINX2TS U3663 ( .CIN(n1840), .B(DP_OP_169J45_123_4229_n747), .A(
DP_OP_169J45_123_4229_n751), .S(Sgf_operation_ODD1_middle_N7), .CO(
n1839) );
AFHCONX2TS U3664 ( .A(n1842), .B(DP_OP_169J45_123_4229_n752), .CI(n1841),
.CON(n1840), .S(Sgf_operation_ODD1_middle_N6) );
AFHCINX2TS U3665 ( .CIN(n1843), .B(n1844), .A(n1845), .S(
Sgf_operation_ODD1_middle_N5), .CO(n1841) );
AFHCONX2TS U3666 ( .A(n1848), .B(n1847), .CI(n1846), .CON(n1843), .S(
Sgf_operation_ODD1_middle_N4) );
AFHCINX2TS U3667 ( .CIN(n1849), .B(n1850), .A(n1851), .S(
Sgf_operation_ODD1_middle_N3), .CO(n1846) );
AFHCONX2TS U3668 ( .A(n1854), .B(n1853), .CI(n1852), .CON(n1849), .S(
Sgf_operation_ODD1_middle_N2) );
OAI21XLTS U3669 ( .A0(Op_MY[47]), .A1(Op_MY[20]), .B0(Op_MY[19]), .Y(n1860)
);
NAND2X1TS U3670 ( .A(Op_MY[47]), .B(Op_MY[20]), .Y(n1859) );
XNOR2X4TS U3671 ( .A(n845), .B(Op_MY[21]), .Y(n2140) );
CLKXOR2X4TS U3672 ( .A(n1862), .B(n1861), .Y(n2335) );
NAND2X6TS U3673 ( .A(n1863), .B(n2335), .Y(n2334) );
NAND2X1TS U3674 ( .A(Op_MY[49]), .B(Op_MY[22]), .Y(n1864) );
XNOR2X4TS U3675 ( .A(n1897), .B(n1896), .Y(n2331) );
AO21XLTS U3676 ( .A0(n2334), .A1(n873), .B0(n849), .Y(n1880) );
INVX2TS U3677 ( .A(n2236), .Y(n1866) );
INVX2TS U3678 ( .A(n2235), .Y(n1868) );
AOI21X1TS U3679 ( .A0(n1868), .A1(n1708), .B0(n1867), .Y(n1869) );
OAI21X1TS U3680 ( .A0(n2244), .A1(n1870), .B0(n1869), .Y(n1873) );
NAND2X1TS U3681 ( .A(n936), .B(n1871), .Y(n1872) );
INVX2TS U3682 ( .A(n1874), .Y(n1882) );
INVX2TS U3683 ( .A(n1875), .Y(n1886) );
NAND2X1TS U3684 ( .A(n1876), .B(n1884), .Y(n1877) );
XNOR2X1TS U3685 ( .A(n815), .B(n850), .Y(n2306) );
OAI22X1TS U3686 ( .A0(n2306), .A1(n2334), .B0(n849), .B1(n873), .Y(n1903) );
INVX2TS U3687 ( .A(n1883), .Y(n2232) );
NAND2X1TS U3688 ( .A(n2227), .B(n2232), .Y(n1889) );
OAI21X1TS U3689 ( .A0(n1886), .A1(n1885), .B0(n1884), .Y(n2228) );
AOI21X1TS U3690 ( .A0(n2228), .A1(n2232), .B0(n1887), .Y(n1888) );
XNOR2X4TS U3691 ( .A(Op_MY[25]), .B(n1891), .Y(n2301) );
XNOR2X1TS U3692 ( .A(n819), .B(n880), .Y(n2276) );
CLKXOR2X4TS U3693 ( .A(n1899), .B(n1898), .Y(n2303) );
XNOR2X1TS U3694 ( .A(n818), .B(n879), .Y(n2275) );
OAI22X1TS U3695 ( .A0(n2276), .A1(n2305), .B0(n2275), .B1(n868), .Y(n1901)
);
NAND2X1TS U3696 ( .A(Op_MY[43]), .B(Op_MY[16]), .Y(n1905) );
CLKXOR2X4TS U3697 ( .A(n1908), .B(n1907), .Y(n2394) );
NAND2X1TS U3698 ( .A(Op_MY[45]), .B(Op_MY[18]), .Y(n1913) );
XNOR2X4TS U3699 ( .A(n2135), .B(n2134), .Y(n2389) );
INVX2TS U3700 ( .A(n2389), .Y(n2152) );
AO21XLTS U3701 ( .A0(n2391), .A1(n865), .B0(n2152), .Y(n1926) );
INVX2TS U3702 ( .A(n1919), .Y(n1915) );
NAND2X1TS U3703 ( .A(n1915), .B(n1918), .Y(n1916) );
CLKXOR2X4TS U3704 ( .A(n2244), .B(n1916), .Y(n2641) );
INVX2TS U3705 ( .A(n1920), .Y(n1922) );
NAND2X1TS U3706 ( .A(n1922), .B(n1921), .Y(n1923) );
NOR2XLTS U3707 ( .A(n783), .B(n852), .Y(n1925) );
XNOR2X1TS U3708 ( .A(n815), .B(n878), .Y(n2367) );
NAND2X1TS U3709 ( .A(Op_MY[39]), .B(Op_MY[12]), .Y(n1931) );
CLKXOR2X4TS U3710 ( .A(n1934), .B(n1933), .Y(n2453) );
XNOR2X4TS U3711 ( .A(n847), .B(Op_MY[15]), .Y(n2166) );
NAND2X1TS U3712 ( .A(Op_MY[41]), .B(Op_MY[14]), .Y(n1939) );
XNOR2X4TS U3713 ( .A(n2167), .B(n2166), .Y(n2448) );
AO21XLTS U3714 ( .A0(n2450), .A1(n867), .B0(n2180), .Y(n1956) );
NAND2X1TS U3715 ( .A(n2113), .B(n1945), .Y(n1942) );
OAI21X1TS U3716 ( .A0(n2125), .A1(n1942), .B0(n1941), .Y(n1944) );
NAND2X1TS U3717 ( .A(n2111), .B(n1958), .Y(n1943) );
NAND2X1TS U3718 ( .A(n1949), .B(n2113), .Y(n1951) );
NAND2X1TS U3719 ( .A(n1961), .B(n1959), .Y(n1953) );
NOR2XLTS U3720 ( .A(n778), .B(n852), .Y(n1955) );
INVX2TS U3721 ( .A(n1957), .Y(n1975) );
INVX2TS U3722 ( .A(n1959), .Y(n1960) );
INVX2TS U3723 ( .A(n1968), .Y(n1970) );
NAND2X1TS U3724 ( .A(n1970), .B(n1969), .Y(n1971) );
XNOR2X1TS U3725 ( .A(n824), .B(n898), .Y(n2259) );
OAI22X1TS U3726 ( .A0(n2260), .A1(n799), .B0(n2259), .B1(n741), .Y(n1974) );
XNOR2X1TS U3727 ( .A(n815), .B(n885), .Y(n2426) );
NAND2X1TS U3728 ( .A(Op_MY[35]), .B(Op_MY[8]), .Y(n1980) );
CLKXOR2X4TS U3729 ( .A(n1983), .B(n1982), .Y(n2513) );
NAND2X1TS U3730 ( .A(Op_MY[37]), .B(Op_MY[10]), .Y(n1985) );
XNOR2X4TS U3731 ( .A(n2077), .B(n2076), .Y(n2508) );
AO21XLTS U3732 ( .A0(n2510), .A1(n872), .B0(n2485), .Y(n2000) );
NAND2X1TS U3733 ( .A(n933), .B(n1992), .Y(n1993) );
NOR2X1TS U3734 ( .A(n775), .B(n852), .Y(n2001) );
NAND2X1TS U3735 ( .A(n2003), .B(n2088), .Y(n1997) );
NOR2XLTS U3736 ( .A(n779), .B(n853), .Y(n1999) );
XNOR2X1TS U3737 ( .A(n823), .B(n850), .Y(n2318) );
XNOR2X1TS U3738 ( .A(n824), .B(n850), .Y(n2317) );
XNOR2X1TS U3739 ( .A(n828), .B(Op_MY[26]), .Y(n2264) );
NAND2X1TS U3740 ( .A(n2113), .B(n2003), .Y(n2005) );
OAI21X1TS U3741 ( .A0(n2125), .A1(n2005), .B0(n2004), .Y(n2008) );
NAND2X1TS U3742 ( .A(n2006), .B(n2086), .Y(n2007) );
XNOR2X1TS U3743 ( .A(n817), .B(Op_MY[26]), .Y(n2263) );
OAI22X1TS U3744 ( .A0(n2264), .A1(n799), .B0(n2263), .B1(n741), .Y(n2009) );
CLKXOR2X4TS U3745 ( .A(n2016), .B(n2015), .Y(n2571) );
NAND2X1TS U3746 ( .A(Op_MY[33]), .B(Op_MY[6]), .Y(n2021) );
XNOR2X4TS U3747 ( .A(n2103), .B(n2102), .Y(n2567) );
AO21XLTS U3748 ( .A0(n806), .A1(n869), .B0(n733), .Y(n2037) );
NOR2X1TS U3749 ( .A(n767), .B(n853), .Y(n2038) );
INVX2TS U3750 ( .A(n2026), .Y(n2027) );
NAND2X1TS U3751 ( .A(n2027), .B(n953), .Y(n2032) );
INVX2TS U3752 ( .A(n2028), .Y(n2030) );
OAI21X1TS U3753 ( .A0(n2125), .A1(n2032), .B0(n2031), .Y(n2035) );
NAND2X1TS U3754 ( .A(n795), .B(n2033), .Y(n2034) );
NOR2XLTS U3755 ( .A(n769), .B(n852), .Y(n2036) );
INVX2TS U3756 ( .A(n2038), .Y(n2041) );
XNOR2X1TS U3757 ( .A(n823), .B(n877), .Y(n2379) );
XNOR2X1TS U3758 ( .A(n824), .B(n877), .Y(n2378) );
XNOR2X1TS U3759 ( .A(n828), .B(n850), .Y(n2322) );
XNOR2X1TS U3760 ( .A(n817), .B(n850), .Y(n2321) );
OAI22X1TS U3761 ( .A0(n2322), .A1(n2334), .B0(n2321), .B1(n873), .Y(n2039)
);
OAI21X1TS U3762 ( .A0(n2125), .A1(n2043), .B0(n2042), .Y(n2048) );
INVX2TS U3763 ( .A(n2044), .Y(n2046) );
NAND2X1TS U3764 ( .A(n2046), .B(n2045), .Y(n2047) );
INVX2TS U3765 ( .A(n2049), .Y(n2052) );
OAI21X1TS U3766 ( .A0(n2125), .A1(n2052), .B0(n2051), .Y(n2055) );
NAND2X1TS U3767 ( .A(n956), .B(n2053), .Y(n2054) );
INVX2TS U3768 ( .A(n2058), .Y(n2068) );
XNOR2X1TS U3769 ( .A(n840), .B(Op_MY[26]), .Y(n2271) );
XNOR2X1TS U3770 ( .A(n814), .B(Op_MY[26]), .Y(n2061) );
OAI22X1TS U3771 ( .A0(n2271), .A1(n741), .B0(n2061), .B1(n798), .Y(n2059) );
OAI22X1TS U3772 ( .A0(n2061), .A1(n741), .B0(n2065), .B1(n798), .Y(n2067) );
NOR2BX1TS U3773 ( .AN(n854), .B(n853), .Y(n2071) );
XNOR2X1TS U3774 ( .A(n854), .B(Op_MY[26]), .Y(n2063) );
XNOR2X1TS U3775 ( .A(n839), .B(Op_MY[26]), .Y(n2064) );
OAI22X1TS U3776 ( .A0(n2065), .A1(n863), .B0(n2064), .B1(n798), .Y(n2069) );
XNOR2X4TS U3777 ( .A(n2074), .B(n2082), .Y(n2479) );
XNOR2X1TS U3778 ( .A(n817), .B(n889), .Y(n2470) );
CLKXOR2X4TS U3779 ( .A(n2079), .B(n2078), .Y(n2483) );
NAND2X1TS U3780 ( .A(n928), .B(n2093), .Y(n2094) );
XNOR2X1TS U3781 ( .A(n831), .B(n2479), .Y(n2469) );
OAI22X1TS U3782 ( .A0(n2470), .A1(n2482), .B0(n2469), .B1(n870), .Y(n2099)
);
XNOR2X1TS U3783 ( .A(n825), .B(n891), .Y(n2499) );
XNOR2X1TS U3784 ( .A(n823), .B(n891), .Y(n2498) );
INVX2TS U3785 ( .A(n2301), .Y(n2273) );
XNOR2X4TS U3786 ( .A(n2100), .B(n2108), .Y(n2539) );
XNOR2X1TS U3787 ( .A(n824), .B(n894), .Y(n2526) );
NAND2X1TS U3788 ( .A(n2121), .B(n2113), .Y(n2124) );
AOI21X1TS U3789 ( .A0(n2116), .A1(n2115), .B0(n2114), .Y(n2117) );
NAND2X1TS U3790 ( .A(n967), .B(n2126), .Y(n2127) );
XNOR2X1TS U3791 ( .A(n827), .B(n894), .Y(n2524) );
OAI22X1TS U3792 ( .A0(n2526), .A1(n2542), .B0(n2524), .B1(n876), .Y(n2129)
);
XNOR2X4TS U3793 ( .A(n2132), .B(n2140), .Y(n2361) );
XNOR2X1TS U3794 ( .A(n840), .B(n2361), .Y(n2360) );
CLKXOR2X4TS U3795 ( .A(n2137), .B(n2136), .Y(n2365) );
XNOR2X1TS U3796 ( .A(n814), .B(n2361), .Y(n2362) );
XNOR2X1TS U3797 ( .A(n854), .B(n2361), .Y(n2148) );
XNOR2X1TS U3798 ( .A(n814), .B(n2389), .Y(n2392) );
XNOR2X1TS U3799 ( .A(n854), .B(n2389), .Y(n2150) );
CLKXOR2X4TS U3800 ( .A(n2169), .B(n2168), .Y(n2424) );
XNOR2X4TS U3801 ( .A(n2175), .B(n2174), .Y(n2420) );
INVX2TS U3802 ( .A(n888), .Y(n2454) );
XNOR2X1TS U3803 ( .A(n814), .B(n890), .Y(n2569) );
XNOR2X1TS U3804 ( .A(n2660), .B(n811), .Y(n2212) );
NOR2X1TS U3805 ( .A(n784), .B(n853), .Y(DP_OP_169J45_123_4229_n776) );
INVX2TS U3806 ( .A(n2227), .Y(n2230) );
INVX2TS U3807 ( .A(n2228), .Y(n2229) );
OAI21X1TS U3808 ( .A0(n2244), .A1(n2230), .B0(n2229), .Y(n2234) );
NAND2X1TS U3809 ( .A(n2232), .B(n2231), .Y(n2233) );
NOR2X1TS U3810 ( .A(n785), .B(n852), .Y(DP_OP_169J45_123_4229_n160) );
NAND2X1TS U3811 ( .A(n1708), .B(n2237), .Y(n2238) );
NOR2X1TS U3812 ( .A(n782), .B(n852), .Y(DP_OP_169J45_123_4229_n778) );
INVX2TS U3813 ( .A(n2240), .Y(n2243) );
INVX2TS U3814 ( .A(n2241), .Y(n2242) );
NAND2X1TS U3815 ( .A(n962), .B(n2245), .Y(n2246) );
NOR2X1TS U3816 ( .A(n781), .B(n853), .Y(DP_OP_169J45_123_4229_n186) );
NOR2X1TS U3817 ( .A(n776), .B(n852), .Y(DP_OP_169J45_123_4229_n780) );
NOR2X1TS U3818 ( .A(n770), .B(n853), .Y(DP_OP_169J45_123_4229_n782) );
NOR2X1TS U3819 ( .A(n772), .B(n853), .Y(DP_OP_169J45_123_4229_n784) );
NOR2X1TS U3820 ( .A(n771), .B(n853), .Y(DP_OP_169J45_123_4229_n336) );
NOR2X1TS U3821 ( .A(n765), .B(n852), .Y(DP_OP_169J45_123_4229_n786) );
NOR2X1TS U3822 ( .A(n766), .B(n852), .Y(DP_OP_169J45_123_4229_n410) );
XNOR2X1TS U3823 ( .A(n818), .B(n898), .Y(n2249) );
OAI22X1TS U3824 ( .A0(n2249), .A1(n799), .B0(n2248), .B1(n741), .Y(
DP_OP_169J45_123_4229_n792) );
XNOR2X1TS U3825 ( .A(n819), .B(n898), .Y(n2250) );
OAI22X1TS U3826 ( .A0(n2250), .A1(n799), .B0(n2249), .B1(n2272), .Y(
DP_OP_169J45_123_4229_n793) );
XNOR2X1TS U3827 ( .A(n816), .B(n898), .Y(n2251) );
OAI22X1TS U3828 ( .A0(n2251), .A1(n799), .B0(n2250), .B1(n741), .Y(
DP_OP_169J45_123_4229_n794) );
XNOR2X1TS U3829 ( .A(n821), .B(n898), .Y(n2252) );
OAI22X1TS U3830 ( .A0(n2252), .A1(n799), .B0(n2251), .B1(n741), .Y(
DP_OP_169J45_123_4229_n795) );
XNOR2X1TS U3831 ( .A(n820), .B(n898), .Y(n2253) );
OAI22X1TS U3832 ( .A0(n2253), .A1(n799), .B0(n2252), .B1(n2272), .Y(
DP_OP_169J45_123_4229_n796) );
XNOR2X1TS U3833 ( .A(n822), .B(n898), .Y(n2254) );
OAI22X1TS U3834 ( .A0(n2254), .A1(n799), .B0(n2253), .B1(n741), .Y(
DP_OP_169J45_123_4229_n797) );
XNOR2X1TS U3835 ( .A(n826), .B(n898), .Y(n2255) );
OAI22X1TS U3836 ( .A0(n2255), .A1(n799), .B0(n2254), .B1(n741), .Y(
DP_OP_169J45_123_4229_n798) );
XNOR2X1TS U3837 ( .A(n829), .B(n898), .Y(n2256) );
OAI22X1TS U3838 ( .A0(n2256), .A1(n799), .B0(n2255), .B1(n741), .Y(
DP_OP_169J45_123_4229_n799) );
XNOR2X1TS U3839 ( .A(n2641), .B(n898), .Y(n2257) );
OAI22X1TS U3840 ( .A0(n2256), .A1(n741), .B0(n2257), .B1(n799), .Y(
DP_OP_169J45_123_4229_n800) );
XNOR2X1TS U3841 ( .A(n827), .B(n898), .Y(n2258) );
OAI22X1TS U3842 ( .A0(n2257), .A1(n741), .B0(n2258), .B1(n799), .Y(
DP_OP_169J45_123_4229_n801) );
OAI22X1TS U3843 ( .A0(n2259), .A1(n799), .B0(n2258), .B1(n741), .Y(
DP_OP_169J45_123_4229_n802) );
XNOR2X1TS U3844 ( .A(n825), .B(n898), .Y(n2261) );
OAI22X1TS U3845 ( .A0(n2261), .A1(n799), .B0(n2260), .B1(n741), .Y(
DP_OP_169J45_123_4229_n804) );
XNOR2X1TS U3846 ( .A(n831), .B(n898), .Y(n2262) );
OAI22X1TS U3847 ( .A0(n2262), .A1(n799), .B0(n2261), .B1(n741), .Y(
DP_OP_169J45_123_4229_n805) );
OAI22X1TS U3848 ( .A0(n2263), .A1(n799), .B0(n2262), .B1(n741), .Y(
DP_OP_169J45_123_4229_n806) );
XNOR2X1TS U3849 ( .A(n830), .B(Op_MY[26]), .Y(n2265) );
OAI22X1TS U3850 ( .A0(n2265), .A1(n799), .B0(n2264), .B1(n741), .Y(
DP_OP_169J45_123_4229_n808) );
OAI22X1TS U3851 ( .A0(n2266), .A1(n799), .B0(n2265), .B1(n741), .Y(
DP_OP_169J45_123_4229_n809) );
XNOR2X1TS U3852 ( .A(n835), .B(Op_MY[26]), .Y(n2267) );
OAI22X1TS U3853 ( .A0(n2267), .A1(n799), .B0(n2266), .B1(n741), .Y(
DP_OP_169J45_123_4229_n810) );
XNOR2X1TS U3854 ( .A(n833), .B(Op_MY[26]), .Y(n2268) );
OAI22X1TS U3855 ( .A0(n2268), .A1(n799), .B0(n2267), .B1(n741), .Y(
DP_OP_169J45_123_4229_n811) );
XNOR2X1TS U3856 ( .A(n837), .B(Op_MY[26]), .Y(n2269) );
OAI22X1TS U3857 ( .A0(n2269), .A1(n799), .B0(n2268), .B1(n741), .Y(
DP_OP_169J45_123_4229_n812) );
XNOR2X1TS U3858 ( .A(n836), .B(Op_MY[26]), .Y(n2270) );
OAI22X1TS U3859 ( .A0(n2270), .A1(n798), .B0(n2269), .B1(n741), .Y(
DP_OP_169J45_123_4229_n813) );
OAI22X1TS U3860 ( .A0(n2271), .A1(n798), .B0(n2270), .B1(n741), .Y(
DP_OP_169J45_123_4229_n814) );
NOR2BX1TS U3861 ( .AN(n854), .B(n863), .Y(DP_OP_169J45_123_4229_n819) );
XNOR2X1TS U3862 ( .A(n815), .B(n880), .Y(n2274) );
OAI22X1TS U3863 ( .A0(n2305), .A1(n2274), .B0(n868), .B1(n2273), .Y(
DP_OP_169J45_123_4229_n821) );
OAI22X1TS U3864 ( .A0(n2275), .A1(n2305), .B0(n2274), .B1(n868), .Y(
DP_OP_169J45_123_4229_n822) );
XNOR2X1TS U3865 ( .A(n816), .B(n879), .Y(n2277) );
OAI22X1TS U3866 ( .A0(n2277), .A1(n2305), .B0(n2276), .B1(n868), .Y(
DP_OP_169J45_123_4229_n824) );
XNOR2X1TS U3867 ( .A(n821), .B(n880), .Y(n2278) );
XNOR2X1TS U3868 ( .A(n820), .B(n879), .Y(n2279) );
OAI22X1TS U3869 ( .A0(n2279), .A1(n2305), .B0(n2278), .B1(n868), .Y(
DP_OP_169J45_123_4229_n826) );
XNOR2X1TS U3870 ( .A(n822), .B(n879), .Y(n2280) );
OAI22X1TS U3871 ( .A0(n2280), .A1(n2305), .B0(n2279), .B1(n868), .Y(
DP_OP_169J45_123_4229_n827) );
XNOR2X1TS U3872 ( .A(n826), .B(n880), .Y(n2281) );
OAI22X1TS U3873 ( .A0(n2281), .A1(n2305), .B0(n2280), .B1(n868), .Y(
DP_OP_169J45_123_4229_n828) );
XNOR2X1TS U3874 ( .A(n829), .B(n879), .Y(n2282) );
OAI22X1TS U3875 ( .A0(n2282), .A1(n2305), .B0(n2281), .B1(n868), .Y(
DP_OP_169J45_123_4229_n829) );
XNOR2X1TS U3876 ( .A(n2641), .B(n880), .Y(n2283) );
OAI22X1TS U3877 ( .A0(n2282), .A1(n868), .B0(n2283), .B1(n2305), .Y(
DP_OP_169J45_123_4229_n830) );
XNOR2X1TS U3878 ( .A(n827), .B(n880), .Y(n2284) );
XNOR2X1TS U3879 ( .A(n824), .B(n879), .Y(n2285) );
OAI22X1TS U3880 ( .A0(n2305), .A1(n2285), .B0(n2284), .B1(n868), .Y(
DP_OP_169J45_123_4229_n832) );
XNOR2X1TS U3881 ( .A(n823), .B(n880), .Y(n2286) );
OAI22X1TS U3882 ( .A0(n2305), .A1(n2286), .B0(n2285), .B1(n868), .Y(
DP_OP_169J45_123_4229_n833) );
XNOR2X1TS U3883 ( .A(n825), .B(n880), .Y(n2287) );
OAI22X1TS U3884 ( .A0(n2305), .A1(n2287), .B0(n2286), .B1(n868), .Y(
DP_OP_169J45_123_4229_n834) );
XNOR2X1TS U3885 ( .A(n831), .B(n880), .Y(n2288) );
OAI22X1TS U3886 ( .A0(n2305), .A1(n2288), .B0(n2287), .B1(n868), .Y(
DP_OP_169J45_123_4229_n835) );
XNOR2X1TS U3887 ( .A(n817), .B(n880), .Y(n2289) );
OAI22X1TS U3888 ( .A0(n2305), .A1(n2289), .B0(n2288), .B1(n868), .Y(
DP_OP_169J45_123_4229_n836) );
XNOR2X1TS U3889 ( .A(n828), .B(n879), .Y(n2290) );
OAI22X1TS U3890 ( .A0(n2305), .A1(n2290), .B0(n2289), .B1(n868), .Y(
DP_OP_169J45_123_4229_n837) );
XNOR2X1TS U3891 ( .A(n830), .B(n879), .Y(n2291) );
OAI22X1TS U3892 ( .A0(n2305), .A1(n2291), .B0(n2290), .B1(n868), .Y(
DP_OP_169J45_123_4229_n838) );
XNOR2X1TS U3893 ( .A(n832), .B(n2301), .Y(n2292) );
XNOR2X1TS U3894 ( .A(n835), .B(n879), .Y(n2293) );
OAI22X1TS U3895 ( .A0(n2305), .A1(n2293), .B0(n2292), .B1(n868), .Y(
DP_OP_169J45_123_4229_n840) );
XNOR2X1TS U3896 ( .A(n833), .B(n879), .Y(n2294) );
XNOR2X1TS U3897 ( .A(n837), .B(n2301), .Y(n2295) );
XNOR2X1TS U3898 ( .A(n836), .B(n2301), .Y(n2296) );
XNOR2X1TS U3899 ( .A(n834), .B(n2301), .Y(n2300) );
OAI22X1TS U3900 ( .A0(n801), .A1(n2300), .B0(n2303), .B1(n2298), .Y(
DP_OP_169J45_123_4229_n846) );
XNOR2X1TS U3901 ( .A(n854), .B(n2301), .Y(n2304) );
XNOR2X1TS U3902 ( .A(n818), .B(n850), .Y(n2307) );
XNOR2X1TS U3903 ( .A(n819), .B(n850), .Y(n2308) );
OAI22X1TS U3904 ( .A0(n2308), .A1(n2334), .B0(n2307), .B1(n873), .Y(
DP_OP_169J45_123_4229_n853) );
OAI22X1TS U3905 ( .A0(n2309), .A1(n2334), .B0(n2308), .B1(n873), .Y(
DP_OP_169J45_123_4229_n854) );
XNOR2X1TS U3906 ( .A(n821), .B(n850), .Y(n2310) );
OAI22X1TS U3907 ( .A0(n2310), .A1(n2334), .B0(n2309), .B1(n873), .Y(
DP_OP_169J45_123_4229_n855) );
XNOR2X1TS U3908 ( .A(n820), .B(n850), .Y(n2311) );
OAI22X1TS U3909 ( .A0(n2311), .A1(n2334), .B0(n2310), .B1(n873), .Y(
DP_OP_169J45_123_4229_n856) );
XNOR2X1TS U3910 ( .A(n822), .B(n850), .Y(n2312) );
OAI22X1TS U3911 ( .A0(n2312), .A1(n2334), .B0(n2311), .B1(n873), .Y(
DP_OP_169J45_123_4229_n857) );
XNOR2X1TS U3912 ( .A(n826), .B(n850), .Y(n2313) );
OAI22X1TS U3913 ( .A0(n2313), .A1(n2334), .B0(n2312), .B1(n873), .Y(
DP_OP_169J45_123_4229_n858) );
XNOR2X1TS U3914 ( .A(n829), .B(n850), .Y(n2314) );
OAI22X1TS U3915 ( .A0(n2314), .A1(n2334), .B0(n2313), .B1(n873), .Y(
DP_OP_169J45_123_4229_n859) );
XNOR2X1TS U3916 ( .A(n2641), .B(n850), .Y(n2315) );
OAI22X1TS U3917 ( .A0(n2314), .A1(n873), .B0(n2315), .B1(n2334), .Y(
DP_OP_169J45_123_4229_n860) );
XNOR2X1TS U3918 ( .A(n827), .B(n850), .Y(n2316) );
OAI22X1TS U3919 ( .A0(n2315), .A1(n873), .B0(n2316), .B1(n2334), .Y(
DP_OP_169J45_123_4229_n861) );
OAI22X1TS U3920 ( .A0(n2317), .A1(n2334), .B0(n2316), .B1(n873), .Y(
DP_OP_169J45_123_4229_n862) );
OAI22X1TS U3921 ( .A0(n2319), .A1(n2334), .B0(n2318), .B1(n873), .Y(
DP_OP_169J45_123_4229_n864) );
XNOR2X1TS U3922 ( .A(n831), .B(n850), .Y(n2320) );
OAI22X1TS U3923 ( .A0(n2320), .A1(n2334), .B0(n2319), .B1(n873), .Y(
DP_OP_169J45_123_4229_n865) );
OAI22X1TS U3924 ( .A0(n2321), .A1(n2334), .B0(n2320), .B1(n873), .Y(
DP_OP_169J45_123_4229_n866) );
OAI22X1TS U3925 ( .A0(n2323), .A1(n2334), .B0(n2322), .B1(n873), .Y(
DP_OP_169J45_123_4229_n868) );
NOR2BX1TS U3926 ( .AN(n854), .B(n2335), .Y(DP_OP_169J45_123_4229_n879) );
AO21XLTS U3927 ( .A0(n2364), .A1(n864), .B0(n2336), .Y(
DP_OP_169J45_123_4229_n880) );
XNOR2X1TS U3928 ( .A(n815), .B(n881), .Y(n2337) );
OAI22X1TS U3929 ( .A0(n2337), .A1(n2364), .B0(n864), .B1(n2336), .Y(
DP_OP_169J45_123_4229_n881) );
XNOR2X1TS U3930 ( .A(n818), .B(n882), .Y(n2338) );
OAI22X1TS U3931 ( .A0(n2338), .A1(n2364), .B0(n2337), .B1(n864), .Y(
DP_OP_169J45_123_4229_n882) );
XNOR2X1TS U3932 ( .A(n819), .B(n881), .Y(n2339) );
OAI22X1TS U3933 ( .A0(n2339), .A1(n2364), .B0(n2338), .B1(n864), .Y(
DP_OP_169J45_123_4229_n883) );
XNOR2X1TS U3934 ( .A(n816), .B(n882), .Y(n2340) );
OAI22X1TS U3935 ( .A0(n2340), .A1(n2364), .B0(n2339), .B1(n864), .Y(
DP_OP_169J45_123_4229_n884) );
XNOR2X1TS U3936 ( .A(n821), .B(n881), .Y(n2341) );
OAI22X1TS U3937 ( .A0(n2341), .A1(n2364), .B0(n2340), .B1(n864), .Y(
DP_OP_169J45_123_4229_n885) );
XNOR2X1TS U3938 ( .A(n820), .B(n882), .Y(n2342) );
XNOR2X1TS U3939 ( .A(n822), .B(n881), .Y(n2343) );
OAI22X1TS U3940 ( .A0(n2343), .A1(n2364), .B0(n2342), .B1(n864), .Y(
DP_OP_169J45_123_4229_n887) );
XNOR2X1TS U3941 ( .A(n826), .B(n882), .Y(n2344) );
OAI22X1TS U3942 ( .A0(n2344), .A1(n2364), .B0(n2343), .B1(n864), .Y(
DP_OP_169J45_123_4229_n888) );
XNOR2X1TS U3943 ( .A(n829), .B(n881), .Y(n2345) );
OAI22X1TS U3944 ( .A0(n2345), .A1(n2364), .B0(n2344), .B1(n864), .Y(
DP_OP_169J45_123_4229_n889) );
XNOR2X1TS U3945 ( .A(n2641), .B(n882), .Y(n2346) );
OAI22X1TS U3946 ( .A0(n2345), .A1(n864), .B0(n2346), .B1(n2364), .Y(
DP_OP_169J45_123_4229_n890) );
XNOR2X1TS U3947 ( .A(n827), .B(n881), .Y(n2347) );
OAI22X1TS U3948 ( .A0(n2346), .A1(n864), .B0(n2347), .B1(n2364), .Y(
DP_OP_169J45_123_4229_n891) );
XNOR2X1TS U3949 ( .A(n824), .B(n882), .Y(n2348) );
OAI22X1TS U3950 ( .A0(n2348), .A1(n2364), .B0(n2347), .B1(n864), .Y(
DP_OP_169J45_123_4229_n892) );
XNOR2X1TS U3951 ( .A(n823), .B(n881), .Y(n2349) );
OAI22X1TS U3952 ( .A0(n2349), .A1(n2364), .B0(n2348), .B1(n864), .Y(
DP_OP_169J45_123_4229_n893) );
XNOR2X1TS U3953 ( .A(n825), .B(n882), .Y(n2350) );
OAI22X1TS U3954 ( .A0(n2350), .A1(n2364), .B0(n2349), .B1(n864), .Y(
DP_OP_169J45_123_4229_n894) );
XNOR2X1TS U3955 ( .A(n831), .B(n881), .Y(n2351) );
OAI22X1TS U3956 ( .A0(n2351), .A1(n2364), .B0(n2350), .B1(n864), .Y(
DP_OP_169J45_123_4229_n895) );
XNOR2X1TS U3957 ( .A(n817), .B(n882), .Y(n2352) );
OAI22X1TS U3958 ( .A0(n2352), .A1(n2364), .B0(n2351), .B1(n864), .Y(
DP_OP_169J45_123_4229_n896) );
XNOR2X1TS U3959 ( .A(n828), .B(n881), .Y(n2353) );
OAI22X1TS U3960 ( .A0(n2353), .A1(n2364), .B0(n2352), .B1(n864), .Y(
DP_OP_169J45_123_4229_n897) );
XNOR2X1TS U3961 ( .A(n830), .B(n882), .Y(n2354) );
OAI22X1TS U3962 ( .A0(n2354), .A1(n2364), .B0(n2353), .B1(n864), .Y(
DP_OP_169J45_123_4229_n898) );
XNOR2X1TS U3963 ( .A(n832), .B(n881), .Y(n2355) );
OAI22X1TS U3964 ( .A0(n2355), .A1(n2364), .B0(n2354), .B1(n864), .Y(
DP_OP_169J45_123_4229_n899) );
XNOR2X1TS U3965 ( .A(n835), .B(n882), .Y(n2356) );
OAI22X1TS U3966 ( .A0(n2356), .A1(n2364), .B0(n2355), .B1(n864), .Y(
DP_OP_169J45_123_4229_n900) );
XNOR2X1TS U3967 ( .A(n833), .B(n2361), .Y(n2357) );
OAI22X1TS U3968 ( .A0(n2357), .A1(n2364), .B0(n2356), .B1(n2365), .Y(
DP_OP_169J45_123_4229_n901) );
XNOR2X1TS U3969 ( .A(n837), .B(n2361), .Y(n2358) );
OAI22X1TS U3970 ( .A0(n2358), .A1(n808), .B0(n2357), .B1(n2365), .Y(
DP_OP_169J45_123_4229_n902) );
XNOR2X1TS U3971 ( .A(n836), .B(n2361), .Y(n2359) );
OAI22X1TS U3972 ( .A0(n2359), .A1(n808), .B0(n2358), .B1(n2365), .Y(
DP_OP_169J45_123_4229_n903) );
OAI22X1TS U3973 ( .A0(n2360), .A1(n808), .B0(n2359), .B1(n2365), .Y(
DP_OP_169J45_123_4229_n904) );
XNOR2X1TS U3974 ( .A(n818), .B(n877), .Y(n2368) );
OAI22X1TS U3975 ( .A0(n2368), .A1(n2391), .B0(n2367), .B1(n865), .Y(
DP_OP_169J45_123_4229_n912) );
OAI22X1TS U3976 ( .A0(n2369), .A1(n2391), .B0(n2368), .B1(n865), .Y(
DP_OP_169J45_123_4229_n913) );
XNOR2X1TS U3977 ( .A(n816), .B(n877), .Y(n2370) );
OAI22X1TS U3978 ( .A0(n2370), .A1(n2391), .B0(n2369), .B1(n865), .Y(
DP_OP_169J45_123_4229_n914) );
XNOR2X1TS U3979 ( .A(n821), .B(n878), .Y(n2371) );
OAI22X1TS U3980 ( .A0(n2371), .A1(n2391), .B0(n2370), .B1(n865), .Y(
DP_OP_169J45_123_4229_n915) );
XNOR2X1TS U3981 ( .A(n820), .B(n877), .Y(n2372) );
OAI22X1TS U3982 ( .A0(n2372), .A1(n2391), .B0(n2371), .B1(n865), .Y(
DP_OP_169J45_123_4229_n916) );
XNOR2X1TS U3983 ( .A(n822), .B(n877), .Y(n2373) );
OAI22X1TS U3984 ( .A0(n2373), .A1(n2391), .B0(n2372), .B1(n865), .Y(
DP_OP_169J45_123_4229_n917) );
XNOR2X1TS U3985 ( .A(n826), .B(n878), .Y(n2374) );
OAI22X1TS U3986 ( .A0(n2374), .A1(n2391), .B0(n2373), .B1(n865), .Y(
DP_OP_169J45_123_4229_n918) );
XNOR2X1TS U3987 ( .A(n829), .B(n877), .Y(n2375) );
OAI22X1TS U3988 ( .A0(n2375), .A1(n2391), .B0(n2374), .B1(n865), .Y(
DP_OP_169J45_123_4229_n919) );
XNOR2X1TS U3989 ( .A(n2641), .B(n878), .Y(n2376) );
OAI22X1TS U3990 ( .A0(n2375), .A1(n865), .B0(n2376), .B1(n2391), .Y(
DP_OP_169J45_123_4229_n920) );
XNOR2X1TS U3991 ( .A(n827), .B(n878), .Y(n2377) );
OAI22X1TS U3992 ( .A0(n2376), .A1(n865), .B0(n2377), .B1(n2391), .Y(
DP_OP_169J45_123_4229_n921) );
OAI22X1TS U3993 ( .A0(n2380), .A1(n2391), .B0(n2379), .B1(n865), .Y(
DP_OP_169J45_123_4229_n924) );
XNOR2X1TS U3994 ( .A(n831), .B(n877), .Y(n2381) );
OAI22X1TS U3995 ( .A0(n2381), .A1(n2391), .B0(n2380), .B1(n865), .Y(
DP_OP_169J45_123_4229_n925) );
XNOR2X1TS U3996 ( .A(n817), .B(n878), .Y(n2382) );
OAI22X1TS U3997 ( .A0(n2382), .A1(n2391), .B0(n2381), .B1(n865), .Y(
DP_OP_169J45_123_4229_n926) );
XNOR2X1TS U3998 ( .A(n828), .B(n877), .Y(n2383) );
OAI22X1TS U3999 ( .A0(n2383), .A1(n2391), .B0(n2382), .B1(n865), .Y(
DP_OP_169J45_123_4229_n927) );
XNOR2X1TS U4000 ( .A(n830), .B(n878), .Y(n2384) );
OAI22X1TS U4001 ( .A0(n2384), .A1(n2391), .B0(n2383), .B1(n865), .Y(
DP_OP_169J45_123_4229_n928) );
XNOR2X1TS U4002 ( .A(n832), .B(n877), .Y(n2385) );
XNOR2X1TS U4003 ( .A(n835), .B(n878), .Y(n2386) );
OAI22X1TS U4004 ( .A0(n2386), .A1(n2391), .B0(n2385), .B1(n865), .Y(
DP_OP_169J45_123_4229_n930) );
XNOR2X1TS U4005 ( .A(n833), .B(n2389), .Y(n2387) );
OAI22X1TS U4006 ( .A0(n2387), .A1(n2391), .B0(n2386), .B1(n865), .Y(
DP_OP_169J45_123_4229_n931) );
OAI22X1TS U4007 ( .A0(n2388), .A1(n802), .B0(n2387), .B1(n865), .Y(
DP_OP_169J45_123_4229_n932) );
XNOR2X1TS U4008 ( .A(n836), .B(n2389), .Y(n2390) );
OAI22X1TS U4009 ( .A0(n2390), .A1(n802), .B0(n2388), .B1(n865), .Y(
DP_OP_169J45_123_4229_n933) );
XNOR2X1TS U4010 ( .A(n840), .B(n2389), .Y(n2393) );
OAI22X1TS U4011 ( .A0(n2393), .A1(n802), .B0(n2390), .B1(n865), .Y(
DP_OP_169J45_123_4229_n934) );
OAI22X1TS U4012 ( .A0(n2393), .A1(n2394), .B0(n2392), .B1(n802), .Y(
DP_OP_169J45_123_4229_n935) );
AO21XLTS U4013 ( .A0(n2423), .A1(n866), .B0(n2395), .Y(
DP_OP_169J45_123_4229_n940) );
XNOR2X1TS U4014 ( .A(n815), .B(n884), .Y(n2396) );
OAI22X1TS U4015 ( .A0(n2396), .A1(n2423), .B0(n866), .B1(n2395), .Y(
DP_OP_169J45_123_4229_n941) );
XNOR2X1TS U4016 ( .A(n818), .B(n883), .Y(n2397) );
OAI22X1TS U4017 ( .A0(n2397), .A1(n2423), .B0(n2396), .B1(n866), .Y(
DP_OP_169J45_123_4229_n942) );
XNOR2X1TS U4018 ( .A(n819), .B(n884), .Y(n2398) );
OAI22X1TS U4019 ( .A0(n2398), .A1(n2423), .B0(n2397), .B1(n866), .Y(
DP_OP_169J45_123_4229_n943) );
XNOR2X1TS U4020 ( .A(n816), .B(n883), .Y(n2399) );
OAI22X1TS U4021 ( .A0(n2399), .A1(n2423), .B0(n2398), .B1(n866), .Y(
DP_OP_169J45_123_4229_n944) );
XNOR2X1TS U4022 ( .A(n821), .B(n883), .Y(n2400) );
XNOR2X1TS U4023 ( .A(n820), .B(n884), .Y(n2401) );
OAI22X1TS U4024 ( .A0(n2401), .A1(n2423), .B0(n2400), .B1(n866), .Y(
DP_OP_169J45_123_4229_n946) );
XNOR2X1TS U4025 ( .A(n822), .B(n883), .Y(n2402) );
OAI22X1TS U4026 ( .A0(n2402), .A1(n2423), .B0(n2401), .B1(n866), .Y(
DP_OP_169J45_123_4229_n947) );
XNOR2X1TS U4027 ( .A(n829), .B(n884), .Y(n2404) );
OAI22X1TS U4028 ( .A0(n2404), .A1(n2423), .B0(n2403), .B1(n866), .Y(
DP_OP_169J45_123_4229_n949) );
OAI22X1TS U4029 ( .A0(n2404), .A1(n866), .B0(n2405), .B1(n2423), .Y(
DP_OP_169J45_123_4229_n950) );
XNOR2X1TS U4030 ( .A(n827), .B(n883), .Y(n2406) );
XNOR2X1TS U4031 ( .A(n824), .B(n884), .Y(n2407) );
OAI22X1TS U4032 ( .A0(n2407), .A1(n2423), .B0(n2406), .B1(n866), .Y(
DP_OP_169J45_123_4229_n952) );
XNOR2X1TS U4033 ( .A(n825), .B(n884), .Y(n2409) );
OAI22X1TS U4034 ( .A0(n2409), .A1(n2423), .B0(n2408), .B1(n866), .Y(
DP_OP_169J45_123_4229_n954) );
XNOR2X1TS U4035 ( .A(n831), .B(n883), .Y(n2410) );
OAI22X1TS U4036 ( .A0(n2410), .A1(n2423), .B0(n2409), .B1(n866), .Y(
DP_OP_169J45_123_4229_n955) );
XNOR2X1TS U4037 ( .A(n817), .B(n884), .Y(n2411) );
OAI22X1TS U4038 ( .A0(n2411), .A1(n2423), .B0(n2410), .B1(n866), .Y(
DP_OP_169J45_123_4229_n956) );
XNOR2X1TS U4039 ( .A(n828), .B(n884), .Y(n2412) );
OAI22X1TS U4040 ( .A0(n2412), .A1(n2423), .B0(n2411), .B1(n866), .Y(
DP_OP_169J45_123_4229_n957) );
XNOR2X1TS U4041 ( .A(n830), .B(n883), .Y(n2413) );
OAI22X1TS U4042 ( .A0(n2413), .A1(n2423), .B0(n2412), .B1(n866), .Y(
DP_OP_169J45_123_4229_n958) );
XNOR2X1TS U4043 ( .A(n832), .B(n884), .Y(n2414) );
OAI22X1TS U4044 ( .A0(n2414), .A1(n2423), .B0(n2413), .B1(n866), .Y(
DP_OP_169J45_123_4229_n959) );
XNOR2X1TS U4045 ( .A(n835), .B(n883), .Y(n2415) );
OAI22X1TS U4046 ( .A0(n2415), .A1(n2423), .B0(n2414), .B1(n866), .Y(
DP_OP_169J45_123_4229_n960) );
XNOR2X1TS U4047 ( .A(n833), .B(n2420), .Y(n2416) );
OAI22X1TS U4048 ( .A0(n2416), .A1(n2423), .B0(n2415), .B1(n866), .Y(
DP_OP_169J45_123_4229_n961) );
XNOR2X1TS U4049 ( .A(n837), .B(n2420), .Y(n2417) );
XNOR2X1TS U4050 ( .A(n836), .B(n2420), .Y(n2418) );
OAI22X1TS U4051 ( .A0(n2418), .A1(n2423), .B0(n2417), .B1(n866), .Y(
DP_OP_169J45_123_4229_n963) );
XNOR2X1TS U4052 ( .A(n818), .B(n886), .Y(n2427) );
XNOR2X1TS U4053 ( .A(n819), .B(n885), .Y(n2428) );
OAI22X1TS U4054 ( .A0(n2428), .A1(n2450), .B0(n2427), .B1(n867), .Y(
DP_OP_169J45_123_4229_n973) );
XNOR2X1TS U4055 ( .A(n816), .B(n885), .Y(n2429) );
OAI22X1TS U4056 ( .A0(n2429), .A1(n2450), .B0(n2428), .B1(n867), .Y(
DP_OP_169J45_123_4229_n974) );
XNOR2X1TS U4057 ( .A(n821), .B(n886), .Y(n2430) );
XNOR2X1TS U4058 ( .A(n820), .B(n886), .Y(n2431) );
OAI22X1TS U4059 ( .A0(n2431), .A1(n2450), .B0(n2430), .B1(n867), .Y(
DP_OP_169J45_123_4229_n976) );
XNOR2X1TS U4060 ( .A(n822), .B(n885), .Y(n2432) );
OAI22X1TS U4061 ( .A0(n2432), .A1(n2450), .B0(n2431), .B1(n867), .Y(
DP_OP_169J45_123_4229_n977) );
XNOR2X1TS U4062 ( .A(n826), .B(n886), .Y(n2433) );
OAI22X1TS U4063 ( .A0(n2433), .A1(n2450), .B0(n2432), .B1(n867), .Y(
DP_OP_169J45_123_4229_n978) );
XNOR2X1TS U4064 ( .A(n829), .B(n885), .Y(n2434) );
OAI22X1TS U4065 ( .A0(n2434), .A1(n2450), .B0(n2433), .B1(n867), .Y(
DP_OP_169J45_123_4229_n979) );
XNOR2X1TS U4066 ( .A(n2641), .B(n886), .Y(n2435) );
OAI22X1TS U4067 ( .A0(n2434), .A1(n867), .B0(n2435), .B1(n2450), .Y(
DP_OP_169J45_123_4229_n980) );
XNOR2X1TS U4068 ( .A(n827), .B(n885), .Y(n2436) );
OAI22X1TS U4069 ( .A0(n2435), .A1(n867), .B0(n2436), .B1(n2450), .Y(
DP_OP_169J45_123_4229_n981) );
XNOR2X1TS U4070 ( .A(n824), .B(n886), .Y(n2437) );
OAI22X1TS U4071 ( .A0(n2437), .A1(n2450), .B0(n2436), .B1(n867), .Y(
DP_OP_169J45_123_4229_n982) );
XNOR2X1TS U4072 ( .A(n823), .B(n885), .Y(n2438) );
OAI22X1TS U4073 ( .A0(n2438), .A1(n2450), .B0(n2437), .B1(n867), .Y(
DP_OP_169J45_123_4229_n983) );
XNOR2X1TS U4074 ( .A(n825), .B(n885), .Y(n2439) );
OAI22X1TS U4075 ( .A0(n2439), .A1(n2450), .B0(n2438), .B1(n867), .Y(
DP_OP_169J45_123_4229_n984) );
XNOR2X1TS U4076 ( .A(n831), .B(n886), .Y(n2440) );
OAI22X1TS U4077 ( .A0(n2440), .A1(n2450), .B0(n2439), .B1(n867), .Y(
DP_OP_169J45_123_4229_n985) );
OAI22X1TS U4078 ( .A0(n2441), .A1(n2450), .B0(n2440), .B1(n867), .Y(
DP_OP_169J45_123_4229_n986) );
XNOR2X1TS U4079 ( .A(n828), .B(n885), .Y(n2442) );
OAI22X1TS U4080 ( .A0(n2442), .A1(n2450), .B0(n2441), .B1(n867), .Y(
DP_OP_169J45_123_4229_n987) );
XNOR2X1TS U4081 ( .A(n830), .B(n886), .Y(n2443) );
OAI22X1TS U4082 ( .A0(n2443), .A1(n2450), .B0(n2442), .B1(n867), .Y(
DP_OP_169J45_123_4229_n988) );
XNOR2X1TS U4083 ( .A(n832), .B(n2448), .Y(n2444) );
OAI22X1TS U4084 ( .A0(n2444), .A1(n2450), .B0(n2443), .B1(n867), .Y(
DP_OP_169J45_123_4229_n989) );
OAI22X1TS U4085 ( .A0(n2445), .A1(n2450), .B0(n2444), .B1(n867), .Y(
DP_OP_169J45_123_4229_n990) );
OAI22X1TS U4086 ( .A0(n2452), .A1(n803), .B0(n2449), .B1(n867), .Y(
DP_OP_169J45_123_4229_n994) );
AO21XLTS U4087 ( .A0(n2482), .A1(n870), .B0(n2454), .Y(
DP_OP_169J45_123_4229_n1000) );
XNOR2X1TS U4088 ( .A(n815), .B(n889), .Y(n2455) );
OAI22X1TS U4089 ( .A0(n2455), .A1(n2482), .B0(n870), .B1(n2454), .Y(
DP_OP_169J45_123_4229_n1001) );
XNOR2X1TS U4090 ( .A(n818), .B(n888), .Y(n2456) );
OAI22X1TS U4091 ( .A0(n2456), .A1(n2482), .B0(n2455), .B1(n870), .Y(
DP_OP_169J45_123_4229_n1002) );
XNOR2X1TS U4092 ( .A(n819), .B(n889), .Y(n2457) );
OAI22X1TS U4093 ( .A0(n2457), .A1(n2482), .B0(n2456), .B1(n870), .Y(
DP_OP_169J45_123_4229_n1003) );
XNOR2X1TS U4094 ( .A(n816), .B(n2479), .Y(n2458) );
OAI22X1TS U4095 ( .A0(n2458), .A1(n2482), .B0(n2457), .B1(n870), .Y(
DP_OP_169J45_123_4229_n1004) );
XNOR2X1TS U4096 ( .A(n821), .B(n888), .Y(n2459) );
OAI22X1TS U4097 ( .A0(n2459), .A1(n2482), .B0(n2458), .B1(n870), .Y(
DP_OP_169J45_123_4229_n1005) );
XNOR2X1TS U4098 ( .A(n820), .B(n2479), .Y(n2460) );
OAI22X1TS U4099 ( .A0(n2460), .A1(n2482), .B0(n2459), .B1(n870), .Y(
DP_OP_169J45_123_4229_n1006) );
XNOR2X1TS U4100 ( .A(n822), .B(n2479), .Y(n2461) );
OAI22X1TS U4101 ( .A0(n2461), .A1(n2482), .B0(n2460), .B1(n870), .Y(
DP_OP_169J45_123_4229_n1007) );
XNOR2X1TS U4102 ( .A(n826), .B(n888), .Y(n2462) );
OAI22X1TS U4103 ( .A0(n2462), .A1(n2482), .B0(n2461), .B1(n870), .Y(
DP_OP_169J45_123_4229_n1008) );
XNOR2X1TS U4104 ( .A(n829), .B(n889), .Y(n2463) );
OAI22X1TS U4105 ( .A0(n2463), .A1(n2482), .B0(n2462), .B1(n870), .Y(
DP_OP_169J45_123_4229_n1009) );
XNOR2X1TS U4106 ( .A(n2641), .B(n889), .Y(n2464) );
OAI22X1TS U4107 ( .A0(n2463), .A1(n870), .B0(n2464), .B1(n2482), .Y(
DP_OP_169J45_123_4229_n1010) );
XNOR2X1TS U4108 ( .A(n827), .B(n888), .Y(n2465) );
OAI22X1TS U4109 ( .A0(n2464), .A1(n870), .B0(n2465), .B1(n2482), .Y(
DP_OP_169J45_123_4229_n1011) );
XNOR2X1TS U4110 ( .A(n824), .B(n2479), .Y(n2466) );
OAI22X1TS U4111 ( .A0(n2466), .A1(n2482), .B0(n2465), .B1(n870), .Y(
DP_OP_169J45_123_4229_n1012) );
XNOR2X1TS U4112 ( .A(n823), .B(n889), .Y(n2467) );
OAI22X1TS U4113 ( .A0(n2467), .A1(n2482), .B0(n2466), .B1(n870), .Y(
DP_OP_169J45_123_4229_n1013) );
XNOR2X1TS U4114 ( .A(n825), .B(n888), .Y(n2468) );
OAI22X1TS U4115 ( .A0(n2468), .A1(n2482), .B0(n2467), .B1(n870), .Y(
DP_OP_169J45_123_4229_n1014) );
XNOR2X1TS U4116 ( .A(n828), .B(n888), .Y(n2471) );
OAI22X1TS U4117 ( .A0(n2471), .A1(n2482), .B0(n2470), .B1(n870), .Y(
DP_OP_169J45_123_4229_n1017) );
XNOR2X1TS U4118 ( .A(n830), .B(n888), .Y(n2472) );
XNOR2X1TS U4119 ( .A(n832), .B(n889), .Y(n2473) );
OAI22X1TS U4120 ( .A0(n2473), .A1(n2482), .B0(n2472), .B1(n870), .Y(
DP_OP_169J45_123_4229_n1019) );
XNOR2X1TS U4121 ( .A(n835), .B(n2479), .Y(n2474) );
OAI22X1TS U4122 ( .A0(n2474), .A1(n2482), .B0(n2473), .B1(n870), .Y(
DP_OP_169J45_123_4229_n1020) );
OAI22X1TS U4123 ( .A0(n2475), .A1(n2482), .B0(n2474), .B1(n870), .Y(
DP_OP_169J45_123_4229_n1021) );
XNOR2X1TS U4124 ( .A(n815), .B(n891), .Y(n2486) );
OAI22X1TS U4125 ( .A0(n2486), .A1(n2510), .B0(n872), .B1(n2485), .Y(
DP_OP_169J45_123_4229_n1031) );
XNOR2X1TS U4126 ( .A(n818), .B(n891), .Y(n2487) );
OAI22X1TS U4127 ( .A0(n2487), .A1(n2510), .B0(n2486), .B1(n872), .Y(
DP_OP_169J45_123_4229_n1032) );
XNOR2X1TS U4128 ( .A(n819), .B(n891), .Y(n2488) );
OAI22X1TS U4129 ( .A0(n2488), .A1(n2510), .B0(n2487), .B1(n872), .Y(
DP_OP_169J45_123_4229_n1033) );
XNOR2X1TS U4130 ( .A(n816), .B(n891), .Y(n2489) );
OAI22X1TS U4131 ( .A0(n2489), .A1(n2510), .B0(n2488), .B1(n872), .Y(
DP_OP_169J45_123_4229_n1034) );
XNOR2X1TS U4132 ( .A(n821), .B(n891), .Y(n2490) );
OAI22X1TS U4133 ( .A0(n2490), .A1(n2510), .B0(n2489), .B1(n872), .Y(
DP_OP_169J45_123_4229_n1035) );
XNOR2X1TS U4134 ( .A(n820), .B(n891), .Y(n2491) );
OAI22X1TS U4135 ( .A0(n2491), .A1(n2510), .B0(n2490), .B1(n872), .Y(
DP_OP_169J45_123_4229_n1036) );
XNOR2X1TS U4136 ( .A(n822), .B(n891), .Y(n2492) );
OAI22X1TS U4137 ( .A0(n2492), .A1(n2510), .B0(n2491), .B1(n872), .Y(
DP_OP_169J45_123_4229_n1037) );
XNOR2X1TS U4138 ( .A(n826), .B(n891), .Y(n2493) );
OAI22X1TS U4139 ( .A0(n2493), .A1(n2510), .B0(n2492), .B1(n872), .Y(
DP_OP_169J45_123_4229_n1038) );
XNOR2X1TS U4140 ( .A(n829), .B(n891), .Y(n2494) );
OAI22X1TS U4141 ( .A0(n2494), .A1(n2510), .B0(n2493), .B1(n872), .Y(
DP_OP_169J45_123_4229_n1039) );
XNOR2X1TS U4142 ( .A(n2641), .B(n891), .Y(n2495) );
OAI22X1TS U4143 ( .A0(n2494), .A1(n872), .B0(n2495), .B1(n2510), .Y(
DP_OP_169J45_123_4229_n1040) );
XNOR2X1TS U4144 ( .A(n827), .B(n891), .Y(n2496) );
OAI22X1TS U4145 ( .A0(n2495), .A1(n872), .B0(n2496), .B1(n2510), .Y(
DP_OP_169J45_123_4229_n1041) );
XNOR2X1TS U4146 ( .A(n824), .B(n891), .Y(n2497) );
OAI22X1TS U4147 ( .A0(n2497), .A1(n2510), .B0(n2496), .B1(n872), .Y(
DP_OP_169J45_123_4229_n1042) );
OAI22X1TS U4148 ( .A0(n2498), .A1(n2510), .B0(n2497), .B1(n872), .Y(
DP_OP_169J45_123_4229_n1043) );
XNOR2X1TS U4149 ( .A(n831), .B(n891), .Y(n2500) );
OAI22X1TS U4150 ( .A0(n2500), .A1(n2510), .B0(n2499), .B1(n872), .Y(
DP_OP_169J45_123_4229_n1045) );
XNOR2X1TS U4151 ( .A(n817), .B(n891), .Y(n2501) );
XNOR2X1TS U4152 ( .A(n828), .B(n891), .Y(n2502) );
OAI22X1TS U4153 ( .A0(n2502), .A1(n2510), .B0(n2501), .B1(n872), .Y(
DP_OP_169J45_123_4229_n1047) );
AO21XLTS U4154 ( .A0(n860), .A1(n875), .B0(n2514), .Y(
DP_OP_169J45_123_4229_n1060) );
XNOR2X1TS U4155 ( .A(n815), .B(n894), .Y(n2515) );
OAI22X1TS U4156 ( .A0(n2515), .A1(n860), .B0(n876), .B1(n2514), .Y(
DP_OP_169J45_123_4229_n1061) );
XNOR2X1TS U4157 ( .A(n818), .B(n894), .Y(n2516) );
OAI22X1TS U4158 ( .A0(n2516), .A1(n860), .B0(n2515), .B1(n875), .Y(
DP_OP_169J45_123_4229_n1062) );
XNOR2X1TS U4159 ( .A(n819), .B(n894), .Y(n2517) );
OAI22X1TS U4160 ( .A0(n2517), .A1(n860), .B0(n2516), .B1(n875), .Y(
DP_OP_169J45_123_4229_n1063) );
XNOR2X1TS U4161 ( .A(n816), .B(n894), .Y(n2518) );
OAI22X1TS U4162 ( .A0(n2518), .A1(n860), .B0(n2517), .B1(n876), .Y(
DP_OP_169J45_123_4229_n1064) );
XNOR2X1TS U4163 ( .A(n821), .B(n894), .Y(n2519) );
OAI22X1TS U4164 ( .A0(n2519), .A1(n860), .B0(n2518), .B1(n876), .Y(
DP_OP_169J45_123_4229_n1065) );
XNOR2X1TS U4165 ( .A(n820), .B(n894), .Y(n2520) );
OAI22X1TS U4166 ( .A0(n2520), .A1(n2542), .B0(n2519), .B1(n875), .Y(
DP_OP_169J45_123_4229_n1066) );
XNOR2X1TS U4167 ( .A(n822), .B(n894), .Y(n2521) );
OAI22X1TS U4168 ( .A0(n2521), .A1(n2542), .B0(n2520), .B1(n876), .Y(
DP_OP_169J45_123_4229_n1067) );
XNOR2X1TS U4169 ( .A(n826), .B(n894), .Y(n2522) );
OAI22X1TS U4170 ( .A0(n2522), .A1(n2542), .B0(n2521), .B1(n875), .Y(
DP_OP_169J45_123_4229_n1068) );
XNOR2X1TS U4171 ( .A(n829), .B(n894), .Y(n2523) );
OAI22X1TS U4172 ( .A0(n2523), .A1(n2542), .B0(n2522), .B1(n876), .Y(
DP_OP_169J45_123_4229_n1069) );
XNOR2X1TS U4173 ( .A(n2641), .B(n894), .Y(n2525) );
OAI22X1TS U4174 ( .A0(n2523), .A1(n875), .B0(n2525), .B1(n2542), .Y(
DP_OP_169J45_123_4229_n1070) );
OAI22X1TS U4175 ( .A0(n2525), .A1(n876), .B0(n2524), .B1(n2542), .Y(
DP_OP_169J45_123_4229_n1071) );
XNOR2X1TS U4176 ( .A(n823), .B(n894), .Y(n2527) );
OAI22X1TS U4177 ( .A0(n2527), .A1(n2542), .B0(n2526), .B1(n875), .Y(
DP_OP_169J45_123_4229_n1073) );
XNOR2X1TS U4178 ( .A(n825), .B(n894), .Y(n2528) );
OAI22X1TS U4179 ( .A0(n2528), .A1(n2542), .B0(n2527), .B1(n876), .Y(
DP_OP_169J45_123_4229_n1074) );
OAI22X1TS U4180 ( .A0(n2532), .A1(n2542), .B0(n2531), .B1(n875), .Y(
DP_OP_169J45_123_4229_n1078) );
OAI22X1TS U4181 ( .A0(n2545), .A1(n806), .B0(n869), .B1(n733), .Y(
DP_OP_169J45_123_4229_n1091) );
XNOR2X1TS U4182 ( .A(n818), .B(n2567), .Y(n2546) );
OAI22X1TS U4183 ( .A0(n2546), .A1(n806), .B0(n2545), .B1(n869), .Y(
DP_OP_169J45_123_4229_n1092) );
XNOR2X1TS U4184 ( .A(n819), .B(n811), .Y(n2547) );
OAI22X1TS U4185 ( .A0(n2547), .A1(n806), .B0(n2546), .B1(n869), .Y(
DP_OP_169J45_123_4229_n1093) );
XNOR2X1TS U4186 ( .A(n816), .B(n890), .Y(n2548) );
OAI22X1TS U4187 ( .A0(n2548), .A1(n806), .B0(n2547), .B1(n869), .Y(
DP_OP_169J45_123_4229_n1094) );
XNOR2X1TS U4188 ( .A(n821), .B(n811), .Y(n2549) );
XNOR2X1TS U4189 ( .A(n820), .B(n2567), .Y(n2550) );
OAI22X1TS U4190 ( .A0(n2550), .A1(n806), .B0(n2549), .B1(n869), .Y(
DP_OP_169J45_123_4229_n1096) );
XNOR2X1TS U4191 ( .A(n822), .B(n890), .Y(n2551) );
OAI22X1TS U4192 ( .A0(n2551), .A1(n806), .B0(n2550), .B1(n869), .Y(
DP_OP_169J45_123_4229_n1097) );
XNOR2X1TS U4193 ( .A(n826), .B(n811), .Y(n2552) );
OAI22X1TS U4194 ( .A0(n2552), .A1(n806), .B0(n2551), .B1(n869), .Y(
DP_OP_169J45_123_4229_n1098) );
XNOR2X1TS U4195 ( .A(n829), .B(n2567), .Y(n2553) );
OAI22X1TS U4196 ( .A0(n2553), .A1(n806), .B0(n2552), .B1(n869), .Y(
DP_OP_169J45_123_4229_n1099) );
XNOR2X1TS U4197 ( .A(n2641), .B(n890), .Y(n2554) );
OAI22X1TS U4198 ( .A0(n2553), .A1(n869), .B0(n2554), .B1(n806), .Y(
DP_OP_169J45_123_4229_n1100) );
OAI22X1TS U4199 ( .A0(n2554), .A1(n869), .B0(n2555), .B1(n806), .Y(
DP_OP_169J45_123_4229_n1101) );
XNOR2X1TS U4200 ( .A(n824), .B(n811), .Y(n2556) );
XNOR2X1TS U4201 ( .A(n823), .B(n890), .Y(n2557) );
OAI22X1TS U4202 ( .A0(n2557), .A1(n806), .B0(n2556), .B1(n869), .Y(
DP_OP_169J45_123_4229_n1103) );
OAI22X1TS U4203 ( .A0(n2558), .A1(n806), .B0(n2557), .B1(n869), .Y(
DP_OP_169J45_123_4229_n1104) );
OAI22X1TS U4204 ( .A0(n2561), .A1(n806), .B0(n2560), .B1(n869), .Y(
DP_OP_169J45_123_4229_n1107) );
XNOR2X1TS U4205 ( .A(n833), .B(n890), .Y(n2565) );
XNOR2X1TS U4206 ( .A(n840), .B(n2567), .Y(n2570) );
NOR2BX1TS U4207 ( .AN(n2660), .B(n2571), .Y(DP_OP_169J45_123_4229_n1119) );
AO21XLTS U4208 ( .A0(n2601), .A1(n871), .B0(n2572), .Y(
DP_OP_169J45_123_4229_n1120) );
XNOR2X1TS U4209 ( .A(n815), .B(n892), .Y(n2573) );
OAI22X1TS U4210 ( .A0(n2573), .A1(n2601), .B0(n871), .B1(n2572), .Y(
DP_OP_169J45_123_4229_n1121) );
XNOR2X1TS U4211 ( .A(n818), .B(n893), .Y(n2574) );
OAI22X1TS U4212 ( .A0(n2574), .A1(n2601), .B0(n2573), .B1(n871), .Y(
DP_OP_169J45_123_4229_n1122) );
XNOR2X1TS U4213 ( .A(n819), .B(n2598), .Y(n2575) );
OAI22X1TS U4214 ( .A0(n2575), .A1(n2601), .B0(n2574), .B1(n871), .Y(
DP_OP_169J45_123_4229_n1123) );
XNOR2X1TS U4215 ( .A(n816), .B(n893), .Y(n2576) );
OAI22X1TS U4216 ( .A0(n2576), .A1(n2601), .B0(n2575), .B1(n871), .Y(
DP_OP_169J45_123_4229_n1124) );
XNOR2X1TS U4217 ( .A(n821), .B(n892), .Y(n2577) );
OAI22X1TS U4218 ( .A0(n2577), .A1(n2601), .B0(n2576), .B1(n871), .Y(
DP_OP_169J45_123_4229_n1125) );
XNOR2X1TS U4219 ( .A(n820), .B(n893), .Y(n2578) );
XNOR2X1TS U4220 ( .A(n822), .B(n2598), .Y(n2579) );
OAI22X1TS U4221 ( .A0(n2579), .A1(n2601), .B0(n2578), .B1(n871), .Y(
DP_OP_169J45_123_4229_n1127) );
XNOR2X1TS U4222 ( .A(n826), .B(n892), .Y(n2580) );
OAI22X1TS U4223 ( .A0(n2580), .A1(n2601), .B0(n2579), .B1(n871), .Y(
DP_OP_169J45_123_4229_n1128) );
XNOR2X1TS U4224 ( .A(n829), .B(n2598), .Y(n2581) );
OAI22X1TS U4225 ( .A0(n2581), .A1(n2601), .B0(n2580), .B1(n871), .Y(
DP_OP_169J45_123_4229_n1129) );
XNOR2X1TS U4226 ( .A(n2641), .B(n893), .Y(n2582) );
OAI22X1TS U4227 ( .A0(n2581), .A1(n871), .B0(n2582), .B1(n2601), .Y(
DP_OP_169J45_123_4229_n1130) );
XNOR2X1TS U4228 ( .A(n827), .B(n892), .Y(n2583) );
OAI22X1TS U4229 ( .A0(n2582), .A1(n871), .B0(n2583), .B1(n2601), .Y(
DP_OP_169J45_123_4229_n1131) );
XNOR2X1TS U4230 ( .A(n824), .B(n893), .Y(n2584) );
XNOR2X1TS U4231 ( .A(n823), .B(n2598), .Y(n2585) );
OAI22X1TS U4232 ( .A0(n2585), .A1(n2601), .B0(n2584), .B1(n871), .Y(
DP_OP_169J45_123_4229_n1133) );
OAI22X1TS U4233 ( .A0(n2590), .A1(n2601), .B0(n2589), .B1(n871), .Y(
DP_OP_169J45_123_4229_n1138) );
OAI22X1TS U4234 ( .A0(n2603), .A1(n2602), .B0(n800), .B1(n2600), .Y(
DP_OP_169J45_123_4229_n1147) );
XNOR2X1TS U4235 ( .A(n815), .B(n895), .Y(n2605) );
XNOR2X1TS U4236 ( .A(n818), .B(n895), .Y(n2606) );
XNOR2X1TS U4237 ( .A(n819), .B(n895), .Y(n2607) );
XNOR2X1TS U4238 ( .A(n816), .B(n895), .Y(n2608) );
OAI22X1TS U4239 ( .A0(n2632), .A1(n2631), .B0(n2630), .B1(n2629), .Y(
DP_OP_169J45_123_4229_n1175) );
NOR2BX1TS U4240 ( .AN(n854), .B(n2659), .Y(Sgf_operation_ODD1_middle_N0) );
INVX2TS U4241 ( .A(DP_OP_169J45_123_4229_n160), .Y(
DP_OP_169J45_123_4229_n161) );
INVX2TS U4242 ( .A(DP_OP_169J45_123_4229_n186), .Y(
DP_OP_169J45_123_4229_n187) );
INVX2TS U4243 ( .A(DP_OP_169J45_123_4229_n224), .Y(
DP_OP_169J45_123_4229_n225) );
INVX2TS U4244 ( .A(DP_OP_169J45_123_4229_n274), .Y(
DP_OP_169J45_123_4229_n275) );
INVX2TS U4245 ( .A(DP_OP_169J45_123_4229_n336), .Y(
DP_OP_169J45_123_4229_n337) );
INVX2TS U4246 ( .A(DP_OP_169J45_123_4229_n410), .Y(
DP_OP_169J45_123_4229_n411) );
CMPR32X2TS U4247 ( .A(mult_x_23_n202), .B(n2664), .C(n2663), .CO(n3429), .S(
Sgf_operation_ODD1_left_N47) );
CMPR32X2TS U4248 ( .A(mult_x_23_n214), .B(mult_x_23_n211), .C(n2665), .CO(
n3437), .S(Sgf_operation_ODD1_left_N44) );
CMPR32X2TS U4249 ( .A(mult_x_23_n225), .B(mult_x_23_n219), .C(n2666), .CO(
n1237), .S(Sgf_operation_ODD1_left_N42) );
CMPR32X2TS U4250 ( .A(mult_x_23_n231), .B(mult_x_23_n226), .C(n2667), .CO(
n2666), .S(Sgf_operation_ODD1_left_N41) );
CMPR32X2TS U4251 ( .A(mult_x_23_n244), .B(mult_x_23_n237), .C(n2668), .CO(
n1233), .S(Sgf_operation_ODD1_left_N39) );
CMPR32X2TS U4252 ( .A(mult_x_23_n251), .B(mult_x_23_n245), .C(n2669), .CO(
n2668), .S(Sgf_operation_ODD1_left_N38) );
CMPR32X2TS U4253 ( .A(mult_x_23_n268), .B(mult_x_23_n259), .C(n2670), .CO(
n1239), .S(Sgf_operation_ODD1_left_N36) );
CMPR32X2TS U4254 ( .A(mult_x_23_n277), .B(mult_x_23_n269), .C(n2671), .CO(
n2670), .S(Sgf_operation_ODD1_left_N35) );
CMPR32X2TS U4255 ( .A(mult_x_23_n296), .B(mult_x_23_n286), .C(n2672), .CO(
n1235), .S(Sgf_operation_ODD1_left_N33) );
CMPR32X2TS U4256 ( .A(mult_x_23_n306), .B(mult_x_23_n297), .C(n2673), .CO(
n2672), .S(Sgf_operation_ODD1_left_N32) );
CMPR32X2TS U4257 ( .A(mult_x_23_n328), .B(mult_x_23_n318), .C(n2674), .CO(
n1244), .S(Sgf_operation_ODD1_left_N30) );
CMPR32X2TS U4258 ( .A(mult_x_23_n339), .B(mult_x_23_n329), .C(n2675), .CO(
n2674), .S(Sgf_operation_ODD1_left_N29) );
CMPR32X2TS U4259 ( .A(mult_x_23_n351), .B(mult_x_23_n361), .C(n2676), .CO(
n1219), .S(Sgf_operation_ODD1_left_N27) );
CMPR32X2TS U4260 ( .A(n2678), .B(mult_x_23_n362), .C(n2677), .CO(n2676), .S(
Sgf_operation_ODD1_left_N26) );
CMPR32X2TS U4261 ( .A(n2680), .B(mult_x_23_n384), .C(n2679), .CO(n1217), .S(
Sgf_operation_ODD1_left_N24) );
CMPR32X2TS U4262 ( .A(n2682), .B(mult_x_23_n395), .C(n2681), .CO(n2679), .S(
Sgf_operation_ODD1_left_N23) );
CMPR32X2TS U4263 ( .A(n2684), .B(mult_x_23_n406), .C(n2683), .CO(n2681), .S(
Sgf_operation_ODD1_left_N22) );
CMPR32X2TS U4264 ( .A(n2686), .B(mult_x_23_n417), .C(n2685), .CO(n2683), .S(
Sgf_operation_ODD1_left_N21) );
CMPR32X2TS U4265 ( .A(n2688), .B(mult_x_23_n428), .C(n2687), .CO(n2685), .S(
Sgf_operation_ODD1_left_N20) );
CMPR32X2TS U4266 ( .A(n2690), .B(mult_x_23_n438), .C(n2689), .CO(n2687), .S(
Sgf_operation_ODD1_left_N19) );
CMPR32X2TS U4267 ( .A(n2692), .B(mult_x_23_n448), .C(n2691), .CO(n2689), .S(
Sgf_operation_ODD1_left_N18) );
CMPR32X2TS U4268 ( .A(n2694), .B(mult_x_23_n458), .C(n2693), .CO(n2691), .S(
Sgf_operation_ODD1_left_N17) );
CMPR32X2TS U4269 ( .A(n2696), .B(mult_x_23_n466), .C(n2695), .CO(n2693), .S(
Sgf_operation_ODD1_left_N16) );
CMPR32X2TS U4270 ( .A(n2698), .B(mult_x_23_n482), .C(n2697), .CO(n1215), .S(
Sgf_operation_ODD1_left_N14) );
CMPR32X2TS U4271 ( .A(n2700), .B(mult_x_23_n489), .C(n2699), .CO(n2697), .S(
Sgf_operation_ODD1_left_N13) );
AOI22X1TS U4272 ( .A0(Op_MY[38]), .A1(n3366), .B0(Op_MY[37]), .B1(n758), .Y(
n2702) );
OAI21X1TS U4273 ( .A0(n3358), .A1(n3183), .B0(n2702), .Y(n2707) );
INVX2TS U4274 ( .A(mult_x_23_n265), .Y(n2713) );
OAI22X1TS U4275 ( .A0(n3400), .A1(n3235), .B0(n3342), .B1(n3323), .Y(n2705)
);
OAI22X1TS U4276 ( .A0(n750), .A1(n3203), .B0(n756), .B1(n938), .Y(n2704) );
OAI31X1TS U4277 ( .A0(n2705), .A1(n3326), .A2(n2704), .B0(n2703), .Y(n2706)
);
CMPR32X2TS U4278 ( .A(n2707), .B(n2713), .C(n2706), .CO(mult_x_23_n263), .S(
mult_x_23_n264) );
OAI21X1TS U4279 ( .A0(n3358), .A1(n3172), .B0(n855), .Y(n2712) );
OAI22X1TS U4280 ( .A0(n3321), .A1(n3357), .B0(n3342), .B1(n3322), .Y(n2710)
);
OAI22X1TS U4281 ( .A0(n750), .A1(n3309), .B0(n756), .B1(n3323), .Y(n2709) );
OAI31X1TS U4282 ( .A0(n2710), .A1(n3326), .A2(n2709), .B0(n2708), .Y(n2711)
);
CMPR32X2TS U4283 ( .A(n2713), .B(n2712), .C(n2711), .CO(mult_x_23_n273), .S(
mult_x_23_n274) );
AOI22X1TS U4284 ( .A0(Op_MY[33]), .A1(n3366), .B0(Op_MY[32]), .B1(n758), .Y(
n2714) );
CMPR32X2TS U4285 ( .A(n2901), .B(n1205), .C(n2715), .CO(mult_x_23_n314), .S(
mult_x_23_n315) );
AOI22X1TS U4286 ( .A0(Op_MY[32]), .A1(n3366), .B0(Op_MY[31]), .B1(n758), .Y(
n2716) );
OAI21X1TS U4287 ( .A0(n3358), .A1(n3273), .B0(n2716), .Y(n2721) );
OAI22X1TS U4288 ( .A0(n3321), .A1(n3388), .B0(n756), .B1(n939), .Y(n2719) );
OAI22X1TS U4289 ( .A0(n750), .A1(n3390), .B0(n3342), .B1(n917), .Y(n2718) );
OAI31X1TS U4290 ( .A0(n2719), .A1(n3326), .A2(n2718), .B0(n2717), .Y(n2720)
);
CMPR32X2TS U4291 ( .A(n2721), .B(Op_MX[29]), .C(n2720), .CO(mult_x_23_n325),
.S(mult_x_23_n326) );
AOI22X1TS U4292 ( .A0(Op_MY[31]), .A1(n3366), .B0(n846), .B1(n758), .Y(n2722) );
OAI22X1TS U4293 ( .A0(n3321), .A1(n3337), .B0(n750), .B1(n939), .Y(n2725) );
OAI22X1TS U4294 ( .A0(n756), .A1(n917), .B0(n3342), .B1(n3275), .Y(n2724) );
OAI31X1TS U4295 ( .A0(n2725), .A1(n3326), .A2(n2724), .B0(n2723), .Y(n2726)
);
CMPR32X2TS U4296 ( .A(n2727), .B(Op_MX[29]), .C(n2726), .CO(mult_x_23_n336),
.S(mult_x_23_n337) );
AOI22X1TS U4297 ( .A0(n846), .A1(n3366), .B0(Op_MY[29]), .B1(n758), .Y(n2728) );
OAI22X1TS U4298 ( .A0(n3321), .A1(n3112), .B0(n3342), .B1(n3274), .Y(n2731)
);
OAI22X1TS U4299 ( .A0(n750), .A1(n917), .B0(n756), .B1(n3275), .Y(n2730) );
OAI31X1TS U4300 ( .A0(n2731), .A1(n3326), .A2(n2730), .B0(n2729), .Y(n2732)
);
CMPR32X2TS U4301 ( .A(n2733), .B(Op_MX[29]), .C(n2732), .CO(mult_x_23_n347),
.S(mult_x_23_n348) );
OAI22X1TS U4302 ( .A0(n3389), .A1(n3260), .B0(n3331), .B1(n3245), .Y(n2736)
);
OAI22X1TS U4303 ( .A0(n755), .A1(n3261), .B0(n754), .B1(n764), .Y(n2735) );
OAI31X1TS U4304 ( .A0(n2736), .A1(n5334), .A2(n2735), .B0(n2734), .Y(n3420)
);
AOI222X4TS U4305 ( .A0(n2738), .A1(n3267), .B0(n2737), .B1(Op_MY[28]), .C0(
n2805), .C1(n848), .Y(n2739) );
XNOR2X1TS U4306 ( .A(Op_MX[47]), .B(n2739), .Y(n2746) );
OAI21XLTS U4307 ( .A0(n2741), .A1(n3245), .B0(Op_MX[47]), .Y(n2740) );
OAI31X1TS U4308 ( .A0(n2741), .A1(Op_MX[47]), .A2(n3245), .B0(n2740), .Y(
n2753) );
OAI22X1TS U4309 ( .A0(n3291), .A1(n3254), .B0(n3314), .B1(n3263), .Y(n2744)
);
OAI22X1TS U4310 ( .A0(n746), .A1(n3274), .B0(n748), .B1(n3272), .Y(n2743) );
OAI31X1TS U4311 ( .A0(n2744), .A1(n3363), .A2(n2743), .B0(n2742), .Y(n2763)
);
ADDHXLTS U4312 ( .A(n2746), .B(n2745), .CO(n3419), .S(n2767) );
OAI22X1TS U4313 ( .A0(n3291), .A1(n3262), .B0(n3314), .B1(n3261), .Y(n2749)
);
OAI22X1TS U4314 ( .A0(n746), .A1(n3272), .B0(n748), .B1(n3263), .Y(n2748) );
OAI31X1TS U4315 ( .A0(n2749), .A1(n3363), .A2(n2748), .B0(n2747), .Y(n2766)
);
OAI22X1TS U4316 ( .A0(n3291), .A1(n3280), .B0(n3314), .B1(n764), .Y(n2752)
);
OAI22X1TS U4317 ( .A0(n746), .A1(n3263), .B0(n748), .B1(n3261), .Y(n2751) );
OAI31X1TS U4318 ( .A0(n2752), .A1(n3363), .A2(n2751), .B0(n2750), .Y(n3425)
);
ADDHXLTS U4319 ( .A(Op_MX[47]), .B(n2753), .CO(n2745), .S(n3424) );
OAI22X1TS U4320 ( .A0(n3291), .A1(n3260), .B0(n3314), .B1(n3245), .Y(n2756)
);
OAI22X1TS U4321 ( .A0(n746), .A1(n3261), .B0(n748), .B1(n764), .Y(n2755) );
OAI31X1TS U4322 ( .A0(n2756), .A1(n3363), .A2(n2755), .B0(n2754), .Y(n3418)
);
XNOR2X1TS U4323 ( .A(Op_MX[44]), .B(n2759), .Y(n3439) );
OAI21XLTS U4324 ( .A0(n2761), .A1(n3245), .B0(Op_MX[44]), .Y(n2760) );
CMPR32X2TS U4325 ( .A(n2764), .B(n2763), .C(n2762), .CO(mult_x_23_n432), .S(
mult_x_23_n433) );
CMPR32X2TS U4326 ( .A(n2767), .B(n2766), .C(n2765), .CO(n2762), .S(
mult_x_23_n443) );
OAI22X1TS U4327 ( .A0(n3299), .A1(n3260), .B0(n3298), .B1(n3245), .Y(n2770)
);
OAI22X1TS U4328 ( .A0(n747), .A1(n3261), .B0(n759), .B1(n764), .Y(n2769) );
OAI31X1TS U4329 ( .A0(n2770), .A1(n5335), .A2(n2769), .B0(n2768), .Y(n3422)
);
AOI222X4TS U4330 ( .A0(n2934), .A1(n3267), .B0(n2771), .B1(Op_MY[28]), .C0(
n2815), .C1(n848), .Y(n2772) );
XNOR2X1TS U4331 ( .A(Op_MX[41]), .B(n2772), .Y(n2779) );
OAI21XLTS U4332 ( .A0(n2774), .A1(n3245), .B0(Op_MX[41]), .Y(n2773) );
OAI31X1TS U4333 ( .A0(n2774), .A1(Op_MX[41]), .A2(n3245), .B0(n2773), .Y(
n2786) );
INVX3TS U4334 ( .A(n2791), .Y(n3097) );
OAI22X1TS U4335 ( .A0(n3097), .A1(n3254), .B0(n3056), .B1(n3263), .Y(n2777)
);
OAI22X1TS U4336 ( .A0(n749), .A1(n3274), .B0(n3287), .B1(n3272), .Y(n2776)
);
OAI31X1TS U4337 ( .A0(n2777), .A1(n3407), .A2(n2776), .B0(n2775), .Y(n2796)
);
ADDHXLTS U4338 ( .A(n2779), .B(n2778), .CO(n3421), .S(n2800) );
OAI22X1TS U4339 ( .A0(n3097), .A1(n3262), .B0(n3056), .B1(n3261), .Y(n2782)
);
OAI22X1TS U4340 ( .A0(n749), .A1(n3272), .B0(n3287), .B1(n3263), .Y(n2781)
);
OAI31X1TS U4341 ( .A0(n2782), .A1(n3407), .A2(n2781), .B0(n2780), .Y(n2799)
);
OAI22X1TS U4342 ( .A0(n3097), .A1(n3280), .B0(n3056), .B1(n764), .Y(n2785)
);
OAI22X1TS U4343 ( .A0(n749), .A1(n3263), .B0(n3287), .B1(n3261), .Y(n2784)
);
OAI31X1TS U4344 ( .A0(n2785), .A1(n3407), .A2(n2784), .B0(n2783), .Y(n3436)
);
ADDHXLTS U4345 ( .A(Op_MX[41]), .B(n2786), .CO(n2778), .S(n3435) );
OAI22X1TS U4346 ( .A0(n3396), .A1(n3260), .B0(n3056), .B1(n3245), .Y(n2789)
);
OAI22X1TS U4347 ( .A0(n749), .A1(n3261), .B0(n3287), .B1(n764), .Y(n2788) );
OAI31X1TS U4348 ( .A0(n2789), .A1(n3407), .A2(n2788), .B0(n2787), .Y(n3445)
);
XNOR2X1TS U4349 ( .A(Op_MX[38]), .B(n2792), .Y(n3433) );
OAI21XLTS U4350 ( .A0(n2794), .A1(n3245), .B0(Op_MX[38]), .Y(n2793) );
OAI31X1TS U4351 ( .A0(n2794), .A1(Op_MX[38]), .A2(n3245), .B0(n2793), .Y(
n3019) );
CMPR32X2TS U4352 ( .A(n2797), .B(n2796), .C(n2795), .CO(mult_x_23_n483), .S(
mult_x_23_n484) );
CMPR32X2TS U4353 ( .A(n2800), .B(n2799), .C(n2798), .CO(n2795), .S(
mult_x_23_n491) );
CMPR32X2TS U4354 ( .A(n2803), .B(n2802), .C(n2801), .CO(mult_x_23_n516), .S(
n1232) );
XNOR2X1TS U4355 ( .A(n5334), .B(n2804), .Y(mult_x_23_n698) );
AOI21X1TS U4356 ( .A0(n2832), .A1(n2806), .B0(n2805), .Y(n2807) );
XNOR2X1TS U4357 ( .A(n5334), .B(n2808), .Y(mult_x_23_n699) );
XNOR2X1TS U4358 ( .A(n3363), .B(n2809), .Y(mult_x_23_n727) );
AOI21X1TS U4359 ( .A0(n2832), .A1(n2811), .B0(n2810), .Y(n2812) );
XNOR2X1TS U4360 ( .A(n3363), .B(n2813), .Y(mult_x_23_n728) );
XNOR2X1TS U4361 ( .A(n5335), .B(n2814), .Y(mult_x_23_n756) );
AOI21X1TS U4362 ( .A0(n2832), .A1(n2816), .B0(n2815), .Y(n2817) );
XNOR2X1TS U4363 ( .A(n5335), .B(n2818), .Y(mult_x_23_n757) );
AOI21X1TS U4364 ( .A0(n2832), .A1(n2820), .B0(n2819), .Y(n2821) );
XNOR2X1TS U4365 ( .A(n3407), .B(n2822), .Y(mult_x_23_n786) );
XNOR2X1TS U4366 ( .A(n3015), .B(n2823), .Y(mult_x_23_n814) );
AOI21X1TS U4367 ( .A0(n2832), .A1(n2825), .B0(n2824), .Y(n2826) );
XNOR2X1TS U4368 ( .A(n3015), .B(n2827), .Y(mult_x_23_n815) );
XNOR2X1TS U4369 ( .A(n970), .B(n2829), .Y(mult_x_23_n843) );
AOI21X1TS U4370 ( .A0(n2832), .A1(n2831), .B0(n2830), .Y(n2833) );
XNOR2X1TS U4371 ( .A(n2901), .B(n2835), .Y(mult_x_23_n844) );
OAI22X1TS U4372 ( .A0(n2895), .A1(n3273), .B0(n2828), .B1(n3272), .Y(n2838)
);
OAI22X1TS U4373 ( .A0(n2896), .A1(n3275), .B0(n2897), .B1(n3274), .Y(n2837)
);
OAI31X1TS U4374 ( .A0(n2838), .A1(n2901), .A2(n2837), .B0(n2836), .Y(
mult_x_23_n864) );
OAI22X1TS U4375 ( .A0(n2895), .A1(n3112), .B0(n2828), .B1(n3274), .Y(n2841)
);
OAI22X1TS U4376 ( .A0(n2896), .A1(n3066), .B0(n2897), .B1(n3275), .Y(n2840)
);
OAI31X1TS U4377 ( .A0(n2841), .A1(n2901), .A2(n2840), .B0(n2839), .Y(
mult_x_23_n863) );
OAI22X1TS U4378 ( .A0(n2895), .A1(n3337), .B0(n2896), .B1(n2965), .Y(n2844)
);
OAI22X1TS U4379 ( .A0(n2897), .A1(n3066), .B0(n2828), .B1(n3275), .Y(n2843)
);
OAI31X1TS U4380 ( .A0(n2844), .A1(n2901), .A2(n2843), .B0(n2842), .Y(
mult_x_23_n862) );
OAI22X1TS U4381 ( .A0(n2895), .A1(n3388), .B0(n2897), .B1(n2965), .Y(n2847)
);
OAI22X1TS U4382 ( .A0(n2896), .A1(n3390), .B0(n2828), .B1(n917), .Y(n2846)
);
OAI31X1TS U4383 ( .A0(n2847), .A1(n2901), .A2(n2846), .B0(n2845), .Y(
mult_x_23_n861) );
OAI22X1TS U4384 ( .A0(n2895), .A1(n3339), .B0(n2828), .B1(n2965), .Y(n2850)
);
OAI22X1TS U4385 ( .A0(n2896), .A1(n3182), .B0(n2897), .B1(n3390), .Y(n2849)
);
OAI31X1TS U4386 ( .A0(n2850), .A1(n2901), .A2(n2849), .B0(n2848), .Y(
mult_x_23_n860) );
OAI22X1TS U4387 ( .A0(n2895), .A1(n3172), .B0(n2828), .B1(n3390), .Y(n2853)
);
OAI22X1TS U4388 ( .A0(n2896), .A1(n3320), .B0(n2897), .B1(n3182), .Y(n2852)
);
OAI31X1TS U4389 ( .A0(n2853), .A1(n2901), .A2(n2852), .B0(n2851), .Y(
mult_x_23_n859) );
OAI22X1TS U4390 ( .A0(n2895), .A1(n3183), .B0(n2828), .B1(n3182), .Y(n2856)
);
OAI22X1TS U4391 ( .A0(n2896), .A1(n3322), .B0(n2897), .B1(n3320), .Y(n2855)
);
OAI31X1TS U4392 ( .A0(n2856), .A1(n2901), .A2(n2855), .B0(n2854), .Y(
mult_x_23_n858) );
OAI22X1TS U4393 ( .A0(n2895), .A1(n3355), .B0(n2828), .B1(n3320), .Y(n2859)
);
OAI22X1TS U4394 ( .A0(n2896), .A1(n3323), .B0(n2897), .B1(n3322), .Y(n2858)
);
OAI31X1TS U4395 ( .A0(n2859), .A1(n2901), .A2(n2858), .B0(n2857), .Y(
mult_x_23_n857) );
OAI22X1TS U4396 ( .A0(n2895), .A1(n3357), .B0(n2828), .B1(n3322), .Y(n2862)
);
OAI22X1TS U4397 ( .A0(n2896), .A1(n3309), .B0(n2897), .B1(n3323), .Y(n2861)
);
OAI31X1TS U4398 ( .A0(n2862), .A1(n2901), .A2(n2861), .B0(n2860), .Y(
mult_x_23_n856) );
OAI22X1TS U4399 ( .A0(n2891), .A1(n3235), .B0(n2828), .B1(n3323), .Y(n2865)
);
OAI22X1TS U4400 ( .A0(n2896), .A1(n3203), .B0(n2897), .B1(n3309), .Y(n2864)
);
OAI31X1TS U4401 ( .A0(n2865), .A1(n2901), .A2(n2864), .B0(n2863), .Y(
mult_x_23_n855) );
OAI22X1TS U4402 ( .A0(n2891), .A1(n3360), .B0(n2828), .B1(n3309), .Y(n2868)
);
OAI22X1TS U4403 ( .A0(n2896), .A1(n3196), .B0(n2897), .B1(n3203), .Y(n2867)
);
OAI31X1TS U4404 ( .A0(n2868), .A1(n2901), .A2(n2867), .B0(n2866), .Y(
mult_x_23_n854) );
OAI22X1TS U4405 ( .A0(n2891), .A1(n3341), .B0(n2828), .B1(n3203), .Y(n2871)
);
OAI22X1TS U4406 ( .A0(n2896), .A1(n3398), .B0(n2897), .B1(n3196), .Y(n2870)
);
OAI31X1TS U4407 ( .A0(n2871), .A1(n2901), .A2(n2870), .B0(n2869), .Y(
mult_x_23_n853) );
OAI22X1TS U4408 ( .A0(n2891), .A1(n3348), .B0(n2828), .B1(n3196), .Y(n2874)
);
OAI22X1TS U4409 ( .A0(n2896), .A1(n3313), .B0(n2897), .B1(n3398), .Y(n2873)
);
OAI31X1TS U4410 ( .A0(n2874), .A1(n2901), .A2(n2873), .B0(n2872), .Y(
mult_x_23_n852) );
OAI22X1TS U4411 ( .A0(n2891), .A1(n3399), .B0(n2828), .B1(n3398), .Y(n2877)
);
OAI22X1TS U4412 ( .A0(n2896), .A1(n3401), .B0(n2897), .B1(n3313), .Y(n2876)
);
OAI31X1TS U4413 ( .A0(n2877), .A1(n2901), .A2(n2876), .B0(n2875), .Y(
mult_x_23_n851) );
OAI22X1TS U4414 ( .A0(n2891), .A1(n3365), .B0(n2828), .B1(n3313), .Y(n2880)
);
OAI22X1TS U4415 ( .A0(n2896), .A1(n3343), .B0(n2897), .B1(n3401), .Y(n2879)
);
OAI31X1TS U4416 ( .A0(n2880), .A1(n2901), .A2(n2879), .B0(n2878), .Y(
mult_x_23_n850) );
OAI22X1TS U4417 ( .A0(n2891), .A1(n3237), .B0(n2828), .B1(n3401), .Y(n2883)
);
OAI22X1TS U4418 ( .A0(n2896), .A1(n3224), .B0(n2897), .B1(n3343), .Y(n2882)
);
OAI31X1TS U4419 ( .A0(n2883), .A1(n2901), .A2(n2882), .B0(n2881), .Y(
mult_x_23_n849) );
OAI22X1TS U4420 ( .A0(n2891), .A1(n3368), .B0(n2828), .B1(n3343), .Y(n2886)
);
OAI22X1TS U4421 ( .A0(n2896), .A1(n3220), .B0(n2897), .B1(n3224), .Y(n2885)
);
OAI31X1TS U4422 ( .A0(n2886), .A1(n2901), .A2(n2885), .B0(n2884), .Y(
mult_x_23_n848) );
INVX3TS U4423 ( .A(n2887), .Y(n3014) );
OAI22X1TS U4424 ( .A0(n3014), .A1(n3262), .B0(n2930), .B1(n3261), .Y(n2890)
);
OAI22X1TS U4425 ( .A0(n752), .A1(n3272), .B0(n757), .B1(n3263), .Y(n2889) );
OAI31X1TS U4426 ( .A0(n2890), .A1(n5336), .A2(n2889), .B0(n2888), .Y(
mult_x_23_n837) );
OAI22X1TS U4427 ( .A0(n2891), .A1(n3225), .B0(n2828), .B1(n3224), .Y(n2894)
);
OAI22X1TS U4428 ( .A0(n789), .A1(n2896), .B0(n2897), .B1(n3220), .Y(n2893)
);
OAI31X1TS U4429 ( .A0(n2894), .A1(n2901), .A2(n2893), .B0(n2892), .Y(
mult_x_23_n847) );
OAI22X1TS U4430 ( .A0(n3230), .A1(n2896), .B0(n2895), .B1(n3229), .Y(n2902)
);
OAI22X1TS U4431 ( .A0(n789), .A1(n2897), .B0(n2828), .B1(n3220), .Y(n2900)
);
OAI31X1TS U4432 ( .A0(n2902), .A1(n2901), .A2(n2900), .B0(n2899), .Y(
mult_x_23_n846) );
OAI22X1TS U4433 ( .A0(n3014), .A1(n3280), .B0(n2930), .B1(n764), .Y(n2905)
);
OAI22X1TS U4434 ( .A0(n752), .A1(n3263), .B0(n757), .B1(n3261), .Y(n2904) );
OAI31X1TS U4435 ( .A0(n2905), .A1(n5336), .A2(n2904), .B0(n2903), .Y(
mult_x_23_n838) );
OAI22X1TS U4436 ( .A0(n3014), .A1(n3254), .B0(n2930), .B1(n3263), .Y(n2908)
);
OAI22X1TS U4437 ( .A0(n752), .A1(n3274), .B0(n757), .B1(n3272), .Y(n2907) );
OAI31X1TS U4438 ( .A0(n2908), .A1(n5336), .A2(n2907), .B0(n2906), .Y(
mult_x_23_n836) );
OAI22X1TS U4439 ( .A0(n3014), .A1(n3273), .B0(n2930), .B1(n3272), .Y(n2911)
);
OAI22X1TS U4440 ( .A0(n752), .A1(n3275), .B0(n757), .B1(n3274), .Y(n2910) );
OAI31X1TS U4441 ( .A0(n2911), .A1(n5336), .A2(n2910), .B0(n2909), .Y(
mult_x_23_n835) );
OAI22X1TS U4442 ( .A0(n3014), .A1(n3112), .B0(n2930), .B1(n3274), .Y(n2914)
);
OAI22X1TS U4443 ( .A0(n752), .A1(n3066), .B0(n757), .B1(n3275), .Y(n2913) );
OAI31X1TS U4444 ( .A0(n2914), .A1(n5336), .A2(n2913), .B0(n2912), .Y(
mult_x_23_n834) );
OAI22X1TS U4445 ( .A0(n3014), .A1(n3337), .B0(n752), .B1(n2965), .Y(n2917)
);
OAI22X1TS U4446 ( .A0(n757), .A1(n3066), .B0(n2930), .B1(n3275), .Y(n2916)
);
OAI31X1TS U4447 ( .A0(n2917), .A1(n5336), .A2(n2916), .B0(n2915), .Y(
mult_x_23_n833) );
OAI22X1TS U4448 ( .A0(n3014), .A1(n3388), .B0(n757), .B1(n2965), .Y(n2920)
);
OAI22X1TS U4449 ( .A0(n752), .A1(n3390), .B0(n2930), .B1(n917), .Y(n2919) );
OAI31X1TS U4450 ( .A0(n2920), .A1(n5336), .A2(n2919), .B0(n2918), .Y(
mult_x_23_n832) );
OAI22X1TS U4451 ( .A0(n3014), .A1(n3339), .B0(n2930), .B1(n2965), .Y(n2923)
);
OAI22X1TS U4452 ( .A0(n752), .A1(n3182), .B0(n757), .B1(n3390), .Y(n2922) );
OAI31X1TS U4453 ( .A0(n2923), .A1(n3015), .A2(n2922), .B0(n2921), .Y(
mult_x_23_n831) );
OAI22X1TS U4454 ( .A0(n3014), .A1(n3172), .B0(n2930), .B1(n3390), .Y(n2926)
);
OAI22X1TS U4455 ( .A0(n752), .A1(n3320), .B0(n757), .B1(n3182), .Y(n2925) );
OAI31X1TS U4456 ( .A0(n2926), .A1(n5336), .A2(n2925), .B0(n2924), .Y(
mult_x_23_n830) );
OAI22X1TS U4457 ( .A0(n3014), .A1(n3183), .B0(n2930), .B1(n3182), .Y(n2929)
);
OAI22X1TS U4458 ( .A0(n752), .A1(n3322), .B0(n757), .B1(n3320), .Y(n2928) );
OAI31X1TS U4459 ( .A0(n2929), .A1(n3015), .A2(n2928), .B0(n2927), .Y(
mult_x_23_n829) );
OAI22X1TS U4460 ( .A0(n3014), .A1(n3355), .B0(n2930), .B1(n3320), .Y(n2933)
);
OAI22X1TS U4461 ( .A0(n752), .A1(n3323), .B0(n757), .B1(n3322), .Y(n2932) );
OAI31X1TS U4462 ( .A0(n2933), .A1(n3015), .A2(n2932), .B0(n2931), .Y(
mult_x_23_n828) );
INVX3TS U4463 ( .A(n2934), .Y(n3383) );
OAI22X1TS U4464 ( .A0(n3383), .A1(n3280), .B0(n3298), .B1(n764), .Y(n2937)
);
OAI22X1TS U4465 ( .A0(n747), .A1(n3263), .B0(n759), .B1(n3261), .Y(n2936) );
OAI31X1TS U4466 ( .A0(n2937), .A1(n5335), .A2(n2936), .B0(n2935), .Y(
mult_x_23_n780) );
OAI22X1TS U4467 ( .A0(n3014), .A1(n3357), .B0(n2930), .B1(n3322), .Y(n2940)
);
OAI22X1TS U4468 ( .A0(n752), .A1(n3309), .B0(n757), .B1(n3323), .Y(n2939) );
OAI31X1TS U4469 ( .A0(n2940), .A1(n3015), .A2(n2939), .B0(n2938), .Y(
mult_x_23_n827) );
OAI22X1TS U4470 ( .A0(n3010), .A1(n3235), .B0(n2930), .B1(n3323), .Y(n2943)
);
OAI22X1TS U4471 ( .A0(n752), .A1(n3203), .B0(n757), .B1(n3309), .Y(n2942) );
OAI31X1TS U4472 ( .A0(n2943), .A1(n3015), .A2(n2942), .B0(n2941), .Y(
mult_x_23_n826) );
OAI22X1TS U4473 ( .A0(n3097), .A1(n3273), .B0(n3056), .B1(n3272), .Y(n2946)
);
OAI22X1TS U4474 ( .A0(n749), .A1(n3275), .B0(n3287), .B1(n3274), .Y(n2945)
);
OAI31X1TS U4475 ( .A0(n2946), .A1(n3407), .A2(n2945), .B0(n2944), .Y(
mult_x_23_n806) );
OAI22X1TS U4476 ( .A0(n3010), .A1(n3360), .B0(n2930), .B1(n938), .Y(n2949)
);
OAI22X1TS U4477 ( .A0(n752), .A1(n3196), .B0(n757), .B1(n3203), .Y(n2948) );
OAI31X1TS U4478 ( .A0(n2949), .A1(n3015), .A2(n2948), .B0(n2947), .Y(
mult_x_23_n825) );
OAI22X1TS U4479 ( .A0(n3097), .A1(n3112), .B0(n3056), .B1(n3274), .Y(n2952)
);
OAI22X1TS U4480 ( .A0(n749), .A1(n3066), .B0(n3287), .B1(n3275), .Y(n2951)
);
OAI31X1TS U4481 ( .A0(n2952), .A1(n3407), .A2(n2951), .B0(n2950), .Y(
mult_x_23_n805) );
OAI22X1TS U4482 ( .A0(n3010), .A1(n3341), .B0(n2930), .B1(n3203), .Y(n2955)
);
OAI22X1TS U4483 ( .A0(n752), .A1(n3398), .B0(n757), .B1(n3196), .Y(n2954) );
OAI31X1TS U4484 ( .A0(n2955), .A1(n3015), .A2(n2954), .B0(n2953), .Y(
mult_x_23_n824) );
OAI22X1TS U4485 ( .A0(n3097), .A1(n3337), .B0(n749), .B1(n2965), .Y(n2958)
);
OAI22X1TS U4486 ( .A0(n3287), .A1(n3066), .B0(n3056), .B1(n3275), .Y(n2957)
);
OAI31X1TS U4487 ( .A0(n2958), .A1(n3098), .A2(n2957), .B0(n2956), .Y(
mult_x_23_n804) );
OAI22X1TS U4488 ( .A0(n3097), .A1(n3339), .B0(n3056), .B1(n2965), .Y(n2961)
);
OAI22X1TS U4489 ( .A0(n749), .A1(n3182), .B0(n3287), .B1(n3390), .Y(n2960)
);
OAI31X1TS U4490 ( .A0(n2961), .A1(n3407), .A2(n2960), .B0(n2959), .Y(
mult_x_23_n802) );
OAI22X1TS U4491 ( .A0(n3010), .A1(n3348), .B0(n2930), .B1(n943), .Y(n2964)
);
OAI22X1TS U4492 ( .A0(n752), .A1(n3313), .B0(n757), .B1(n3398), .Y(n2963) );
OAI31X1TS U4493 ( .A0(n2964), .A1(n3015), .A2(n2963), .B0(n2962), .Y(
mult_x_23_n823) );
OAI22X1TS U4494 ( .A0(n3097), .A1(n3388), .B0(n3287), .B1(n2965), .Y(n2968)
);
OAI22X1TS U4495 ( .A0(n749), .A1(n3390), .B0(n3056), .B1(n917), .Y(n2967) );
OAI31X1TS U4496 ( .A0(n2968), .A1(n3407), .A2(n2967), .B0(n2966), .Y(
mult_x_23_n803) );
OAI22X1TS U4497 ( .A0(n3097), .A1(n3172), .B0(n3056), .B1(n3390), .Y(n2971)
);
OAI22X1TS U4498 ( .A0(n749), .A1(n3320), .B0(n3287), .B1(n3182), .Y(n2970)
);
OAI31X1TS U4499 ( .A0(n2971), .A1(n3098), .A2(n2970), .B0(n2969), .Y(
mult_x_23_n801) );
OAI22X1TS U4500 ( .A0(n3010), .A1(n3399), .B0(n2930), .B1(n3398), .Y(n2974)
);
OAI22X1TS U4501 ( .A0(n752), .A1(n3401), .B0(n757), .B1(n3313), .Y(n2973) );
OAI31X1TS U4502 ( .A0(n2974), .A1(n3015), .A2(n2973), .B0(n2972), .Y(
mult_x_23_n822) );
OAI22X1TS U4503 ( .A0(n3097), .A1(n3183), .B0(n3056), .B1(n3182), .Y(n2977)
);
OAI22X1TS U4504 ( .A0(n749), .A1(n3322), .B0(n3287), .B1(n3320), .Y(n2976)
);
OAI31X1TS U4505 ( .A0(n2977), .A1(n3407), .A2(n2976), .B0(n2975), .Y(
mult_x_23_n800) );
OAI22X1TS U4506 ( .A0(n3010), .A1(n3365), .B0(n2930), .B1(n3313), .Y(n2980)
);
OAI22X1TS U4507 ( .A0(n752), .A1(n3343), .B0(n757), .B1(n3401), .Y(n2979) );
OAI31X1TS U4508 ( .A0(n2980), .A1(n5336), .A2(n2979), .B0(n2978), .Y(
mult_x_23_n821) );
AOI21X1TS U4509 ( .A0(Op_MX[27]), .A1(n3395), .B0(Op_MX[28]), .Y(n2982) );
OAI32X1TS U4510 ( .A0(n913), .A1(n972), .A2(n3395), .B0(n2982), .B1(n2981),
.Y(mult_x_23_n872) );
OAI22X1TS U4511 ( .A0(n3097), .A1(n3355), .B0(n3056), .B1(n3320), .Y(n2985)
);
OAI22X1TS U4512 ( .A0(n749), .A1(n3323), .B0(n3287), .B1(n3322), .Y(n2984)
);
OAI31X1TS U4513 ( .A0(n2985), .A1(n3407), .A2(n2984), .B0(n2983), .Y(
mult_x_23_n799) );
OAI22X1TS U4514 ( .A0(n3097), .A1(n3357), .B0(n3056), .B1(n3322), .Y(n2988)
);
OAI22X1TS U4515 ( .A0(n749), .A1(n3309), .B0(n3287), .B1(n3323), .Y(n2987)
);
OAI31X1TS U4516 ( .A0(n2988), .A1(n3407), .A2(n2987), .B0(n2986), .Y(
mult_x_23_n798) );
OAI22X1TS U4517 ( .A0(n3383), .A1(n3262), .B0(n3298), .B1(n3261), .Y(n2991)
);
OAI22X1TS U4518 ( .A0(n747), .A1(n3272), .B0(n759), .B1(n3263), .Y(n2990) );
OAI31X1TS U4519 ( .A0(n2991), .A1(n5335), .A2(n2990), .B0(n2989), .Y(
mult_x_23_n779) );
OAI22X1TS U4520 ( .A0(n3396), .A1(n3235), .B0(n3056), .B1(n3323), .Y(n2994)
);
OAI22X1TS U4521 ( .A0(n749), .A1(n3203), .B0(n3287), .B1(n3309), .Y(n2993)
);
OAI31X1TS U4522 ( .A0(n2994), .A1(n3407), .A2(n2993), .B0(n2992), .Y(
mult_x_23_n797) );
OAI22X1TS U4523 ( .A0(n3010), .A1(n3237), .B0(n2930), .B1(n3401), .Y(n2997)
);
OAI22X1TS U4524 ( .A0(n752), .A1(n3224), .B0(n757), .B1(n3343), .Y(n2996) );
OAI31X1TS U4525 ( .A0(n2997), .A1(n5336), .A2(n2996), .B0(n2995), .Y(
mult_x_23_n820) );
OAI22X1TS U4526 ( .A0(n3396), .A1(n3360), .B0(n3056), .B1(n3309), .Y(n3000)
);
OAI22X1TS U4527 ( .A0(n749), .A1(n3196), .B0(n3287), .B1(n3203), .Y(n2999)
);
OAI31X1TS U4528 ( .A0(n3000), .A1(n3407), .A2(n2999), .B0(n2998), .Y(
mult_x_23_n796) );
OAI22X1TS U4529 ( .A0(n3396), .A1(n3341), .B0(n3056), .B1(n3203), .Y(n3003)
);
OAI22X1TS U4530 ( .A0(n749), .A1(n3398), .B0(n3287), .B1(n3196), .Y(n3002)
);
OAI31X1TS U4531 ( .A0(n3003), .A1(n3407), .A2(n3002), .B0(n3001), .Y(
mult_x_23_n795) );
OAI22X1TS U4532 ( .A0(n3010), .A1(n3368), .B0(n2930), .B1(n3343), .Y(n3006)
);
OAI22X1TS U4533 ( .A0(n752), .A1(n3220), .B0(n757), .B1(n3224), .Y(n3005) );
OAI31X1TS U4534 ( .A0(n3006), .A1(n5336), .A2(n3005), .B0(n3004), .Y(
mult_x_23_n819) );
OAI22X1TS U4535 ( .A0(n3396), .A1(n3348), .B0(n3056), .B1(n3196), .Y(n3009)
);
OAI22X1TS U4536 ( .A0(n749), .A1(n3313), .B0(n3287), .B1(n3398), .Y(n3008)
);
OAI31X1TS U4537 ( .A0(n3009), .A1(n3407), .A2(n3008), .B0(n3007), .Y(
mult_x_23_n794) );
OAI22X1TS U4538 ( .A0(n3010), .A1(n3225), .B0(n2930), .B1(n3224), .Y(n3013)
);
OAI22X1TS U4539 ( .A0(n789), .A1(n752), .B0(n757), .B1(n3220), .Y(n3012) );
OAI31X1TS U4540 ( .A0(n3013), .A1(n5336), .A2(n3012), .B0(n3011), .Y(
mult_x_23_n818) );
OAI22X1TS U4541 ( .A0(n3230), .A1(n752), .B0(n3014), .B1(n3229), .Y(n3018)
);
OAI22X1TS U4542 ( .A0(n789), .A1(n757), .B0(n2930), .B1(n3220), .Y(n3017) );
OAI31X1TS U4543 ( .A0(n3018), .A1(n5336), .A2(n3017), .B0(n3016), .Y(
mult_x_23_n817) );
ADDHXLTS U4544 ( .A(Op_MX[38]), .B(n3019), .CO(n3432), .S(mult_x_23_n515) );
OAI22X1TS U4545 ( .A0(n3383), .A1(n3254), .B0(n3298), .B1(n3263), .Y(n3022)
);
OAI22X1TS U4546 ( .A0(n747), .A1(n3274), .B0(n759), .B1(n3272), .Y(n3021) );
OAI31X1TS U4547 ( .A0(n3022), .A1(n5335), .A2(n3021), .B0(n3020), .Y(
mult_x_23_n778) );
OAI22X1TS U4548 ( .A0(n3383), .A1(n3273), .B0(n3298), .B1(n3272), .Y(n3025)
);
OAI22X1TS U4549 ( .A0(n747), .A1(n3275), .B0(n759), .B1(n3274), .Y(n3024) );
OAI31X1TS U4550 ( .A0(n3025), .A1(n5335), .A2(n3024), .B0(n3023), .Y(
mult_x_23_n777) );
OAI22X1TS U4551 ( .A0(n3383), .A1(n3112), .B0(n3298), .B1(n3274), .Y(n3028)
);
OAI22X1TS U4552 ( .A0(n747), .A1(n3066), .B0(n759), .B1(n3275), .Y(n3027) );
OAI31X1TS U4553 ( .A0(n3028), .A1(n5335), .A2(n3027), .B0(n3026), .Y(
mult_x_23_n776) );
OAI22X1TS U4554 ( .A0(n3383), .A1(n3337), .B0(n747), .B1(n939), .Y(n3031) );
OAI22X1TS U4555 ( .A0(n759), .A1(n3066), .B0(n3298), .B1(n3275), .Y(n3030)
);
OAI31X1TS U4556 ( .A0(n3031), .A1(n978), .A2(n3030), .B0(n3029), .Y(
mult_x_23_n775) );
OAI22X1TS U4557 ( .A0(n3383), .A1(n3339), .B0(n3298), .B1(n939), .Y(n3034)
);
OAI22X1TS U4558 ( .A0(n747), .A1(n3182), .B0(n759), .B1(n3390), .Y(n3033) );
OAI31X1TS U4559 ( .A0(n3034), .A1(n5335), .A2(n3033), .B0(n3032), .Y(
mult_x_23_n773) );
OAI22X1TS U4560 ( .A0(n3383), .A1(n3172), .B0(n3298), .B1(n3390), .Y(n3037)
);
OAI22X1TS U4561 ( .A0(n747), .A1(n3320), .B0(n759), .B1(n3182), .Y(n3036) );
OAI31X1TS U4562 ( .A0(n3037), .A1(n978), .A2(n3036), .B0(n3035), .Y(
mult_x_23_n772) );
OAI22X1TS U4563 ( .A0(n3291), .A1(n3273), .B0(n3314), .B1(n3272), .Y(n3040)
);
OAI22X1TS U4564 ( .A0(n746), .A1(n3275), .B0(n748), .B1(n3274), .Y(n3039) );
OAI31X1TS U4565 ( .A0(n3040), .A1(n3363), .A2(n3039), .B0(n3038), .Y(
mult_x_23_n748) );
OAI22X1TS U4566 ( .A0(n3383), .A1(n3183), .B0(n3298), .B1(n3182), .Y(n3043)
);
OAI22X1TS U4567 ( .A0(n747), .A1(n3322), .B0(n759), .B1(n3320), .Y(n3042) );
OAI31X1TS U4568 ( .A0(n3043), .A1(n5335), .A2(n3042), .B0(n3041), .Y(
mult_x_23_n771) );
OAI22X1TS U4569 ( .A0(n3383), .A1(n3355), .B0(n3298), .B1(n3320), .Y(n3046)
);
OAI22X1TS U4570 ( .A0(n747), .A1(n3323), .B0(n759), .B1(n3322), .Y(n3045) );
OAI31X1TS U4571 ( .A0(n3046), .A1(n5335), .A2(n3045), .B0(n3044), .Y(
mult_x_23_n770) );
OAI22X1TS U4572 ( .A0(n3383), .A1(n3357), .B0(n3298), .B1(n3322), .Y(n3049)
);
OAI22X1TS U4573 ( .A0(n747), .A1(n3309), .B0(n759), .B1(n3323), .Y(n3048) );
OAI31X1TS U4574 ( .A0(n3049), .A1(n5335), .A2(n3048), .B0(n3047), .Y(
mult_x_23_n769) );
OAI22X1TS U4575 ( .A0(n3389), .A1(n3280), .B0(n3331), .B1(n764), .Y(n3052)
);
OAI22X1TS U4576 ( .A0(n755), .A1(n3263), .B0(n754), .B1(n3261), .Y(n3051) );
OAI31X1TS U4577 ( .A0(n3052), .A1(n5334), .A2(n3051), .B0(n3050), .Y(
mult_x_23_n722) );
OAI22X1TS U4578 ( .A0(n3396), .A1(n3365), .B0(n3056), .B1(n3313), .Y(n3055)
);
OAI22X1TS U4579 ( .A0(n749), .A1(n3343), .B0(n3287), .B1(n3401), .Y(n3054)
);
OAI31X1TS U4580 ( .A0(n3055), .A1(n977), .A2(n3054), .B0(n3053), .Y(
mult_x_23_n792) );
OAI22X1TS U4581 ( .A0(n3396), .A1(n3237), .B0(n3056), .B1(n3401), .Y(n3059)
);
OAI22X1TS U4582 ( .A0(n749), .A1(n3224), .B0(n3287), .B1(n915), .Y(n3058) );
OAI31X1TS U4583 ( .A0(n3059), .A1(n977), .A2(n3058), .B0(n3057), .Y(
mult_x_23_n791) );
OAI22X1TS U4584 ( .A0(n3299), .A1(n3235), .B0(n3298), .B1(n3323), .Y(n3062)
);
OAI22X1TS U4585 ( .A0(n747), .A1(n3203), .B0(n759), .B1(n3309), .Y(n3061) );
OAI31X1TS U4586 ( .A0(n3062), .A1(n5335), .A2(n3061), .B0(n3060), .Y(
mult_x_23_n768) );
OAI22X1TS U4587 ( .A0(n3291), .A1(n3112), .B0(n3314), .B1(n3274), .Y(n3065)
);
OAI22X1TS U4588 ( .A0(n746), .A1(n3066), .B0(n748), .B1(n3275), .Y(n3064) );
OAI31X1TS U4589 ( .A0(n3065), .A1(n3363), .A2(n3064), .B0(n3063), .Y(
mult_x_23_n747) );
OAI22X1TS U4590 ( .A0(n3291), .A1(n3337), .B0(n746), .B1(n939), .Y(n3069) );
OAI22X1TS U4591 ( .A0(n748), .A1(n3066), .B0(n3314), .B1(n3275), .Y(n3068)
);
OAI31X1TS U4592 ( .A0(n3069), .A1(n3318), .A2(n3068), .B0(n3067), .Y(
mult_x_23_n746) );
OAI22X1TS U4593 ( .A0(n3291), .A1(n3339), .B0(n3314), .B1(n939), .Y(n3072)
);
OAI22X1TS U4594 ( .A0(n746), .A1(n3182), .B0(n748), .B1(n3390), .Y(n3071) );
OAI31X1TS U4595 ( .A0(n3072), .A1(n3363), .A2(n3071), .B0(n3070), .Y(
mult_x_23_n744) );
OAI22X1TS U4596 ( .A0(n3291), .A1(n3388), .B0(n748), .B1(n939), .Y(n3075) );
OAI22X1TS U4597 ( .A0(n746), .A1(n3390), .B0(n3314), .B1(n917), .Y(n3074) );
OAI31X1TS U4598 ( .A0(n3075), .A1(n3363), .A2(n3074), .B0(n3073), .Y(
mult_x_23_n745) );
OAI22X1TS U4599 ( .A0(n3291), .A1(n3172), .B0(n3314), .B1(n3390), .Y(n3078)
);
OAI22X1TS U4600 ( .A0(n746), .A1(n3320), .B0(n748), .B1(n3182), .Y(n3077) );
OAI31X1TS U4601 ( .A0(n3078), .A1(n3318), .A2(n3077), .B0(n3076), .Y(
mult_x_23_n743) );
OAI22X1TS U4602 ( .A0(n3299), .A1(n3360), .B0(n3298), .B1(n3309), .Y(n3081)
);
OAI22X1TS U4603 ( .A0(n747), .A1(n3196), .B0(n759), .B1(n3203), .Y(n3080) );
OAI31X1TS U4604 ( .A0(n3081), .A1(n5335), .A2(n3080), .B0(n3079), .Y(
mult_x_23_n767) );
OAI22X1TS U4605 ( .A0(n3396), .A1(n3368), .B0(n3056), .B1(n3343), .Y(n3084)
);
OAI22X1TS U4606 ( .A0(n749), .A1(n3220), .B0(n3287), .B1(n3224), .Y(n3083)
);
OAI31X1TS U4607 ( .A0(n3084), .A1(n977), .A2(n3083), .B0(n3082), .Y(
mult_x_23_n790) );
OAI22X1TS U4608 ( .A0(n3291), .A1(n3183), .B0(n3314), .B1(n3182), .Y(n3087)
);
OAI22X1TS U4609 ( .A0(n746), .A1(n3322), .B0(n748), .B1(n3320), .Y(n3086) );
OAI31X1TS U4610 ( .A0(n3087), .A1(n3363), .A2(n3086), .B0(n3085), .Y(
mult_x_23_n742) );
OAI22X1TS U4611 ( .A0(n3299), .A1(n3341), .B0(n3298), .B1(n3203), .Y(n3090)
);
OAI22X1TS U4612 ( .A0(n747), .A1(n3398), .B0(n759), .B1(n3196), .Y(n3089) );
OAI31X1TS U4613 ( .A0(n3090), .A1(n5335), .A2(n3089), .B0(n3088), .Y(
mult_x_23_n766) );
OAI22X1TS U4614 ( .A0(n3396), .A1(n3225), .B0(n3056), .B1(n3224), .Y(n3093)
);
OAI22X1TS U4615 ( .A0(n789), .A1(n749), .B0(n3287), .B1(n3220), .Y(n3092) );
OAI31X1TS U4616 ( .A0(n3093), .A1(n3407), .A2(n3092), .B0(n3091), .Y(
mult_x_23_n789) );
OAI22X1TS U4617 ( .A0(n3389), .A1(n3262), .B0(n3331), .B1(n3261), .Y(n3096)
);
OAI22X1TS U4618 ( .A0(n755), .A1(n3272), .B0(n754), .B1(n3263), .Y(n3095) );
OAI31X1TS U4619 ( .A0(n3096), .A1(n5334), .A2(n3095), .B0(n3094), .Y(
mult_x_23_n721) );
OAI22X1TS U4620 ( .A0(n3230), .A1(n749), .B0(n3097), .B1(n3229), .Y(n3101)
);
OAI22X1TS U4621 ( .A0(n789), .A1(n3287), .B0(n3056), .B1(n3220), .Y(n3100)
);
OAI31X1TS U4622 ( .A0(n3101), .A1(n3407), .A2(n3100), .B0(n3099), .Y(
mult_x_23_n788) );
OAI22X1TS U4623 ( .A0(n3299), .A1(n3348), .B0(n3298), .B1(n3196), .Y(n3104)
);
OAI22X1TS U4624 ( .A0(n747), .A1(n3313), .B0(n759), .B1(n3398), .Y(n3103) );
OAI31X1TS U4625 ( .A0(n3104), .A1(n5335), .A2(n3103), .B0(n3102), .Y(
mult_x_23_n765) );
ADDHXLTS U4626 ( .A(Op_MX[44]), .B(n3105), .CO(n3438), .S(mult_x_23_n479) );
OAI22X1TS U4627 ( .A0(n3389), .A1(n3254), .B0(n3331), .B1(n3263), .Y(n3108)
);
OAI22X1TS U4628 ( .A0(n755), .A1(n3274), .B0(n754), .B1(n3272), .Y(n3107) );
OAI31X1TS U4629 ( .A0(n3108), .A1(n5334), .A2(n3107), .B0(n3106), .Y(
mult_x_23_n720) );
OAI22X1TS U4630 ( .A0(n3389), .A1(n3273), .B0(n3331), .B1(n3272), .Y(n3111)
);
OAI22X1TS U4631 ( .A0(n755), .A1(n3275), .B0(n754), .B1(n3274), .Y(n3110) );
OAI31X1TS U4632 ( .A0(n3111), .A1(n5334), .A2(n3110), .B0(n3109), .Y(
mult_x_23_n719) );
OAI22X1TS U4633 ( .A0(n3389), .A1(n3112), .B0(n3331), .B1(n3274), .Y(n3115)
);
OAI22X1TS U4634 ( .A0(n755), .A1(n917), .B0(n754), .B1(n3275), .Y(n3114) );
OAI31X1TS U4635 ( .A0(n3115), .A1(n5334), .A2(n3114), .B0(n3113), .Y(
mult_x_23_n718) );
OAI22X1TS U4636 ( .A0(n3389), .A1(n3337), .B0(n755), .B1(n939), .Y(n3118) );
OAI22X1TS U4637 ( .A0(n754), .A1(n917), .B0(n3331), .B1(n3275), .Y(n3117) );
OAI31X1TS U4638 ( .A0(n3118), .A1(n963), .A2(n3117), .B0(n3116), .Y(
mult_x_23_n717) );
OAI22X1TS U4639 ( .A0(n3291), .A1(n3357), .B0(n3314), .B1(n3322), .Y(n3121)
);
OAI22X1TS U4640 ( .A0(n746), .A1(n3309), .B0(n748), .B1(n3323), .Y(n3120) );
OAI31X1TS U4641 ( .A0(n3121), .A1(n3363), .A2(n3120), .B0(n3119), .Y(
mult_x_23_n740) );
OAI22X1TS U4642 ( .A0(n3315), .A1(n3235), .B0(n3314), .B1(n3323), .Y(n3124)
);
OAI22X1TS U4643 ( .A0(n746), .A1(n3203), .B0(n748), .B1(n3309), .Y(n3123) );
OAI31X1TS U4644 ( .A0(n3124), .A1(n3363), .A2(n3123), .B0(n3122), .Y(
mult_x_23_n739) );
OAI22X1TS U4645 ( .A0(n3299), .A1(n3237), .B0(n3298), .B1(n3401), .Y(n3127)
);
OAI22X1TS U4646 ( .A0(n747), .A1(n3224), .B0(n759), .B1(n3343), .Y(n3126) );
OAI31X1TS U4647 ( .A0(n3127), .A1(n978), .A2(n3126), .B0(n3125), .Y(
mult_x_23_n762) );
OAI22X1TS U4648 ( .A0(n3389), .A1(n3339), .B0(n3331), .B1(n939), .Y(n3130)
);
OAI22X1TS U4649 ( .A0(n755), .A1(n3182), .B0(n754), .B1(n3390), .Y(n3129) );
OAI31X1TS U4650 ( .A0(n3130), .A1(n5334), .A2(n3129), .B0(n3128), .Y(
mult_x_23_n715) );
OAI22X1TS U4651 ( .A0(n3315), .A1(n3360), .B0(n3314), .B1(n3309), .Y(n3133)
);
OAI22X1TS U4652 ( .A0(n746), .A1(n3196), .B0(n748), .B1(n3203), .Y(n3132) );
OAI31X1TS U4653 ( .A0(n3133), .A1(n3363), .A2(n3132), .B0(n3131), .Y(
mult_x_23_n738) );
OAI22X1TS U4654 ( .A0(n3299), .A1(n3368), .B0(n3298), .B1(n3343), .Y(n3136)
);
OAI22X1TS U4655 ( .A0(n747), .A1(n3220), .B0(n759), .B1(n3224), .Y(n3135) );
OAI31X1TS U4656 ( .A0(n3136), .A1(n978), .A2(n3135), .B0(n3134), .Y(
mult_x_23_n761) );
OAI22X1TS U4657 ( .A0(n3389), .A1(n3172), .B0(n3331), .B1(n3390), .Y(n3139)
);
OAI22X1TS U4658 ( .A0(n755), .A1(n3320), .B0(n754), .B1(n3182), .Y(n3138) );
OAI31X1TS U4659 ( .A0(n3139), .A1(n963), .A2(n3138), .B0(n3137), .Y(
mult_x_23_n714) );
OAI22X1TS U4660 ( .A0(n3315), .A1(n3341), .B0(n3314), .B1(n3203), .Y(n3142)
);
OAI22X1TS U4661 ( .A0(n746), .A1(n3398), .B0(n748), .B1(n3196), .Y(n3141) );
OAI31X1TS U4662 ( .A0(n3142), .A1(n3363), .A2(n3141), .B0(n3140), .Y(
mult_x_23_n737) );
OAI22X1TS U4663 ( .A0(n3299), .A1(n3225), .B0(n3298), .B1(n3224), .Y(n3145)
);
OAI22X1TS U4664 ( .A0(n789), .A1(n747), .B0(n759), .B1(n3220), .Y(n3144) );
OAI31X1TS U4665 ( .A0(n3145), .A1(n5335), .A2(n3144), .B0(n3143), .Y(
mult_x_23_n760) );
OAI22X1TS U4666 ( .A0(n3230), .A1(n747), .B0(n3383), .B1(n3229), .Y(n3148)
);
OAI22X1TS U4667 ( .A0(n789), .A1(n759), .B0(n3298), .B1(n3220), .Y(n3147) );
OAI31X1TS U4668 ( .A0(n3148), .A1(n5335), .A2(n3147), .B0(n3146), .Y(
mult_x_23_n759) );
OAI22X1TS U4669 ( .A0(n3389), .A1(n3183), .B0(n3331), .B1(n3182), .Y(n3151)
);
OAI22X1TS U4670 ( .A0(n755), .A1(n3322), .B0(n754), .B1(n3320), .Y(n3150) );
OAI31X1TS U4671 ( .A0(n3151), .A1(n5334), .A2(n3150), .B0(n3149), .Y(
mult_x_23_n713) );
OAI22X1TS U4672 ( .A0(n3315), .A1(n3348), .B0(n3314), .B1(n3196), .Y(n3154)
);
OAI22X1TS U4673 ( .A0(n746), .A1(n3313), .B0(n748), .B1(n3398), .Y(n3153) );
OAI31X1TS U4674 ( .A0(n3154), .A1(n3363), .A2(n3153), .B0(n3152), .Y(
mult_x_23_n736) );
OAI21XLTS U4675 ( .A0(n3156), .A1(n3245), .B0(Op_MX[50]), .Y(n3155) );
OAI22X1TS U4676 ( .A0(n3321), .A1(n3339), .B0(n3342), .B1(n939), .Y(n3159)
);
OAI22X1TS U4677 ( .A0(n750), .A1(n3182), .B0(n756), .B1(n3390), .Y(n3158) );
OAI31X1TS U4678 ( .A0(n3159), .A1(n3326), .A2(n3158), .B0(n3157), .Y(
mult_x_23_n686) );
OAI22X1TS U4679 ( .A0(n3332), .A1(n3235), .B0(n3331), .B1(n3323), .Y(n3162)
);
OAI22X1TS U4680 ( .A0(n755), .A1(n3203), .B0(n754), .B1(n938), .Y(n3161) );
OAI31X1TS U4681 ( .A0(n3162), .A1(n5334), .A2(n3161), .B0(n3160), .Y(
mult_x_23_n710) );
OAI22X1TS U4682 ( .A0(n3315), .A1(n3237), .B0(n3314), .B1(n3401), .Y(n3165)
);
OAI22X1TS U4683 ( .A0(n746), .A1(n3224), .B0(n748), .B1(n3343), .Y(n3164) );
OAI31X1TS U4684 ( .A0(n3165), .A1(n3318), .A2(n3164), .B0(n3163), .Y(
mult_x_23_n733) );
OAI22X1TS U4685 ( .A0(n3332), .A1(n3360), .B0(n3331), .B1(n938), .Y(n3168)
);
OAI22X1TS U4686 ( .A0(n755), .A1(n3196), .B0(n754), .B1(n3203), .Y(n3167) );
OAI31X1TS U4687 ( .A0(n3168), .A1(n5334), .A2(n3167), .B0(n3166), .Y(
mult_x_23_n709) );
OAI22X1TS U4688 ( .A0(n3315), .A1(n3368), .B0(n3314), .B1(n3343), .Y(n3171)
);
OAI22X1TS U4689 ( .A0(n746), .A1(n3220), .B0(n748), .B1(n3224), .Y(n3170) );
OAI31X1TS U4690 ( .A0(n3171), .A1(n3318), .A2(n3170), .B0(n3169), .Y(
mult_x_23_n732) );
OAI22X1TS U4691 ( .A0(n3321), .A1(n3172), .B0(n3342), .B1(n3390), .Y(n3175)
);
OAI22X1TS U4692 ( .A0(n750), .A1(n3320), .B0(n756), .B1(n3182), .Y(n3174) );
OAI31X1TS U4693 ( .A0(n3175), .A1(n3326), .A2(n3174), .B0(n3173), .Y(
mult_x_23_n685) );
OAI22X1TS U4694 ( .A0(n3332), .A1(n3341), .B0(n3331), .B1(n3203), .Y(n3178)
);
OAI22X1TS U4695 ( .A0(n755), .A1(n3398), .B0(n754), .B1(n943), .Y(n3177) );
OAI31X1TS U4696 ( .A0(n3178), .A1(n5334), .A2(n3177), .B0(n3176), .Y(
mult_x_23_n708) );
OAI22X1TS U4697 ( .A0(n3315), .A1(n3225), .B0(n3314), .B1(n3224), .Y(n3181)
);
OAI22X1TS U4698 ( .A0(n789), .A1(n746), .B0(n748), .B1(n3220), .Y(n3180) );
OAI31X1TS U4699 ( .A0(n3181), .A1(n3363), .A2(n3180), .B0(n3179), .Y(
mult_x_23_n731) );
OAI22X1TS U4700 ( .A0(n3321), .A1(n3183), .B0(n3342), .B1(n3182), .Y(n3186)
);
OAI22X1TS U4701 ( .A0(n750), .A1(n3322), .B0(n756), .B1(n3320), .Y(n3185) );
OAI31X1TS U4702 ( .A0(n3186), .A1(n3326), .A2(n3185), .B0(n3184), .Y(
mult_x_23_n684) );
OAI22X1TS U4703 ( .A0(n3332), .A1(n3348), .B0(n3331), .B1(n943), .Y(n3189)
);
OAI22X1TS U4704 ( .A0(n755), .A1(n3313), .B0(n754), .B1(n3398), .Y(n3188) );
OAI31X1TS U4705 ( .A0(n3189), .A1(n5334), .A2(n3188), .B0(n3187), .Y(
mult_x_23_n707) );
OAI22X1TS U4706 ( .A0(n3315), .A1(n3229), .B0(n3314), .B1(n3220), .Y(n3192)
);
OAI22X1TS U4707 ( .A0(n3230), .A1(n746), .B0(n789), .B1(n748), .Y(n3191) );
OAI31X1TS U4708 ( .A0(n3192), .A1(n3363), .A2(n3191), .B0(n3190), .Y(
mult_x_23_n730) );
OAI22X1TS U4709 ( .A0(n3332), .A1(n3237), .B0(n3331), .B1(n3401), .Y(n3195)
);
OAI22X1TS U4710 ( .A0(n755), .A1(n3224), .B0(n754), .B1(n915), .Y(n3194) );
OAI31X1TS U4711 ( .A0(n3195), .A1(n963), .A2(n3194), .B0(n3193), .Y(
mult_x_23_n704) );
OAI22X1TS U4712 ( .A0(n3400), .A1(n3360), .B0(n3342), .B1(n938), .Y(n3199)
);
OAI22X1TS U4713 ( .A0(n750), .A1(n3196), .B0(n756), .B1(n3203), .Y(n3198) );
OAI31X1TS U4714 ( .A0(n3199), .A1(n3326), .A2(n3198), .B0(n3197), .Y(
mult_x_23_n680) );
OAI22X1TS U4715 ( .A0(n3332), .A1(n3368), .B0(n3331), .B1(n915), .Y(n3202)
);
OAI22X1TS U4716 ( .A0(n755), .A1(n3220), .B0(n754), .B1(n3224), .Y(n3201) );
OAI31X1TS U4717 ( .A0(n3202), .A1(n963), .A2(n3201), .B0(n3200), .Y(
mult_x_23_n703) );
OAI22X1TS U4718 ( .A0(n3400), .A1(n3341), .B0(n3342), .B1(n3203), .Y(n3206)
);
OAI22X1TS U4719 ( .A0(n750), .A1(n3398), .B0(n756), .B1(n943), .Y(n3205) );
OAI31X1TS U4720 ( .A0(n3206), .A1(n3326), .A2(n3205), .B0(n3204), .Y(
mult_x_23_n679) );
OAI22X1TS U4721 ( .A0(n3332), .A1(n3225), .B0(n3331), .B1(n3224), .Y(n3209)
);
OAI22X1TS U4722 ( .A0(n789), .A1(n755), .B0(n754), .B1(n951), .Y(n3208) );
OAI31X1TS U4723 ( .A0(n3209), .A1(n5334), .A2(n3208), .B0(n3207), .Y(
mult_x_23_n702) );
OAI22X1TS U4724 ( .A0(n3400), .A1(n3348), .B0(n3342), .B1(n943), .Y(n3212)
);
OAI22X1TS U4725 ( .A0(n750), .A1(n3313), .B0(n756), .B1(n3398), .Y(n3211) );
OAI31X1TS U4726 ( .A0(n3212), .A1(n975), .A2(n3211), .B0(n3210), .Y(
mult_x_23_n678) );
OAI22X1TS U4727 ( .A0(n3332), .A1(n3229), .B0(n3331), .B1(n3220), .Y(n3215)
);
OAI22X1TS U4728 ( .A0(n3230), .A1(n755), .B0(n789), .B1(n754), .Y(n3214) );
OAI31X1TS U4729 ( .A0(n3215), .A1(n5334), .A2(n3214), .B0(n3213), .Y(
mult_x_23_n701) );
AOI22X1TS U4730 ( .A0(Op_MY[35]), .A1(n3366), .B0(Op_MY[34]), .B1(n758), .Y(
n3216) );
OAI21X1TS U4731 ( .A0(n3358), .A1(n3388), .B0(n3216), .Y(mult_x_23_n659) );
OAI22X1TS U4732 ( .A0(n3400), .A1(n3237), .B0(n3342), .B1(n3401), .Y(n3219)
);
OAI22X1TS U4733 ( .A0(n750), .A1(n3224), .B0(n756), .B1(n915), .Y(n3218) );
OAI31X1TS U4734 ( .A0(n3219), .A1(n975), .A2(n3218), .B0(n3217), .Y(
mult_x_23_n675) );
OAI22X1TS U4735 ( .A0(n3400), .A1(n3368), .B0(n3342), .B1(n915), .Y(n3223)
);
OAI22X1TS U4736 ( .A0(n750), .A1(n3220), .B0(n756), .B1(n3224), .Y(n3222) );
OAI31X1TS U4737 ( .A0(n3223), .A1(n975), .A2(n3222), .B0(n3221), .Y(
mult_x_23_n674) );
OAI22X1TS U4738 ( .A0(n3400), .A1(n3225), .B0(n3342), .B1(n3224), .Y(n3228)
);
OAI22X1TS U4739 ( .A0(n789), .A1(n750), .B0(n756), .B1(n3220), .Y(n3227) );
OAI31X1TS U4740 ( .A0(n3228), .A1(n975), .A2(n3227), .B0(n3226), .Y(
mult_x_23_n673) );
OAI22X1TS U4741 ( .A0(n3400), .A1(n3229), .B0(n3342), .B1(n951), .Y(n3233)
);
OAI22X1TS U4742 ( .A0(n3230), .A1(n750), .B0(n789), .B1(n756), .Y(n3232) );
OAI31X1TS U4743 ( .A0(n3233), .A1(n3326), .A2(n3232), .B0(n3231), .Y(
mult_x_23_n672) );
AOI22X1TS U4744 ( .A0(Op_MY[41]), .A1(n3366), .B0(Op_MY[40]), .B1(n758), .Y(
n3234) );
OAI21X1TS U4745 ( .A0(n3369), .A1(n3235), .B0(n3234), .Y(mult_x_23_n653) );
AOI22X1TS U4746 ( .A0(Op_MY[47]), .A1(n3366), .B0(Op_MY[46]), .B1(n758), .Y(
n3236) );
OAI21X1TS U4747 ( .A0(n3369), .A1(n3237), .B0(n3236), .Y(mult_x_23_n647) );
ADDHXLTS U4748 ( .A(Op_MX[29]), .B(n3238), .CO(n3410), .S(
Sgf_operation_ODD1_left_N0) );
OAI22X1TS U4749 ( .A0(n3321), .A1(n3280), .B0(n3342), .B1(n764), .Y(n3244)
);
OAI22X1TS U4750 ( .A0(n750), .A1(n3263), .B0(n756), .B1(n3261), .Y(n3243) );
OAI31X1TS U4751 ( .A0(n3244), .A1(n3326), .A2(n3243), .B0(n3242), .Y(n3271)
);
OAI22X1TS U4752 ( .A0(n3321), .A1(n3260), .B0(n3342), .B1(n3245), .Y(n3248)
);
OAI22X1TS U4753 ( .A0(n750), .A1(n3261), .B0(n756), .B1(n764), .Y(n3247) );
OAI31X1TS U4754 ( .A0(n3248), .A1(n3326), .A2(n3247), .B0(n3246), .Y(n3409)
);
AOI222X4TS U4755 ( .A0(n3251), .A1(n3267), .B0(n3250), .B1(Op_MY[28]), .C0(
n3249), .C1(n848), .Y(n3252) );
XNOR2X1TS U4756 ( .A(Op_MX[50]), .B(n3252), .Y(n3441) );
ADDHXLTS U4757 ( .A(Op_MX[50]), .B(n3253), .CO(n3440), .S(mult_x_23_n425) );
OAI22X1TS U4758 ( .A0(n3321), .A1(n3254), .B0(n3342), .B1(n3263), .Y(n3257)
);
OAI22X1TS U4759 ( .A0(n750), .A1(n3274), .B0(n756), .B1(n3272), .Y(n3256) );
OAI31X1TS U4760 ( .A0(n3257), .A1(n3326), .A2(n3256), .B0(n3255), .Y(n3283)
);
AOI22X1TS U4761 ( .A0(Op_MY[28]), .A1(n3258), .B0(n848), .B1(n758), .Y(n3259) );
OAI21X1TS U4762 ( .A0(n3358), .A1(n3260), .B0(n3259), .Y(n3282) );
OAI22X1TS U4763 ( .A0(n3321), .A1(n3262), .B0(n3342), .B1(n3261), .Y(n3266)
);
OAI22X1TS U4764 ( .A0(n750), .A1(n3272), .B0(n756), .B1(n3263), .Y(n3265) );
OAI31X1TS U4765 ( .A0(n3266), .A1(n3326), .A2(n3265), .B0(n3264), .Y(n3382)
);
AO22XLTS U4766 ( .A0(n848), .A1(n3258), .B0(n3268), .B1(n3267), .Y(n3381) );
CMPR32X2TS U4767 ( .A(n3271), .B(n3270), .C(n3269), .CO(n3380), .S(
mult_x_23_n392) );
OAI22X1TS U4768 ( .A0(n3321), .A1(n3273), .B0(n3342), .B1(n3272), .Y(n3278)
);
OAI22X1TS U4769 ( .A0(n750), .A1(n3275), .B0(n756), .B1(n3274), .Y(n3277) );
OAI31X1TS U4770 ( .A0(n3278), .A1(n3326), .A2(n3277), .B0(n3276), .Y(n3286)
);
AOI22X1TS U4771 ( .A0(Op_MY[29]), .A1(n3366), .B0(Op_MY[28]), .B1(n758), .Y(
n3279) );
OAI21X1TS U4772 ( .A0(n3358), .A1(n3280), .B0(n3279), .Y(n3285) );
CMPR32X2TS U4773 ( .A(n3283), .B(n3282), .C(n3281), .CO(n3284), .S(
mult_x_23_n370) );
CMPR32X2TS U4774 ( .A(n3286), .B(n3285), .C(n3284), .CO(mult_x_23_n358), .S(
mult_x_23_n359) );
OAI22X1TS U4775 ( .A0(n3396), .A1(n3399), .B0(n3056), .B1(n3398), .Y(n3290)
);
OAI22X1TS U4776 ( .A0(n749), .A1(n3401), .B0(n3287), .B1(n942), .Y(n3289) );
OAI31X1TS U4777 ( .A0(n3290), .A1(n3407), .A2(n3289), .B0(n3288), .Y(
mult_x_23_n793) );
OAI22X1TS U4778 ( .A0(n3291), .A1(n3355), .B0(n3314), .B1(n3320), .Y(n3294)
);
OAI22X1TS U4779 ( .A0(n746), .A1(n3323), .B0(n748), .B1(n3322), .Y(n3293) );
OAI31X1TS U4780 ( .A0(n3294), .A1(n3363), .A2(n3293), .B0(n3292), .Y(
mult_x_23_n741) );
OAI22X1TS U4781 ( .A0(n3299), .A1(n3399), .B0(n3298), .B1(n3398), .Y(n3297)
);
OAI22X1TS U4782 ( .A0(n747), .A1(n3401), .B0(n759), .B1(n3313), .Y(n3296) );
OAI31X1TS U4783 ( .A0(n3297), .A1(n5335), .A2(n3296), .B0(n3295), .Y(
mult_x_23_n764) );
OAI22X1TS U4784 ( .A0(n3299), .A1(n3365), .B0(n3298), .B1(n3313), .Y(n3302)
);
OAI22X1TS U4785 ( .A0(n747), .A1(n3343), .B0(n759), .B1(n3401), .Y(n3301) );
OAI31X1TS U4786 ( .A0(n3302), .A1(n978), .A2(n3301), .B0(n3300), .Y(
mult_x_23_n763) );
OAI22X1TS U4787 ( .A0(n3389), .A1(n3355), .B0(n3331), .B1(n3320), .Y(n3305)
);
OAI22X1TS U4788 ( .A0(n755), .A1(n3323), .B0(n754), .B1(n3322), .Y(n3304) );
OAI31X1TS U4789 ( .A0(n3305), .A1(n5334), .A2(n3304), .B0(n3303), .Y(
mult_x_23_n712) );
OAI22X1TS U4790 ( .A0(n3315), .A1(n3399), .B0(n3314), .B1(n3398), .Y(n3308)
);
OAI22X1TS U4791 ( .A0(n746), .A1(n3401), .B0(n748), .B1(n3313), .Y(n3307) );
OAI31X1TS U4792 ( .A0(n3308), .A1(n3363), .A2(n3307), .B0(n3306), .Y(
mult_x_23_n735) );
OAI22X1TS U4793 ( .A0(n3389), .A1(n3357), .B0(n3331), .B1(n3322), .Y(n3312)
);
OAI22X1TS U4794 ( .A0(n755), .A1(n3309), .B0(n754), .B1(n3323), .Y(n3311) );
OAI31X1TS U4795 ( .A0(n3312), .A1(n5334), .A2(n3311), .B0(n3310), .Y(
mult_x_23_n711) );
OAI22X1TS U4796 ( .A0(n3315), .A1(n3365), .B0(n3314), .B1(n3313), .Y(n3319)
);
OAI22X1TS U4797 ( .A0(n746), .A1(n3343), .B0(n748), .B1(n3401), .Y(n3317) );
OAI31X1TS U4798 ( .A0(n3319), .A1(n3318), .A2(n3317), .B0(n3316), .Y(
mult_x_23_n734) );
OAI22X1TS U4799 ( .A0(n3321), .A1(n3355), .B0(n3342), .B1(n3320), .Y(n3327)
);
OAI22X1TS U4800 ( .A0(n750), .A1(n3323), .B0(n756), .B1(n3322), .Y(n3325) );
OAI31X1TS U4801 ( .A0(n3327), .A1(n3326), .A2(n3325), .B0(n3324), .Y(
mult_x_23_n683) );
OAI22X1TS U4802 ( .A0(n3332), .A1(n3399), .B0(n3331), .B1(n3398), .Y(n3330)
);
OAI22X1TS U4803 ( .A0(n755), .A1(n3401), .B0(n754), .B1(n942), .Y(n3329) );
OAI31X1TS U4804 ( .A0(n3330), .A1(n5334), .A2(n3329), .B0(n3328), .Y(
mult_x_23_n706) );
OAI22X1TS U4805 ( .A0(n3332), .A1(n3365), .B0(n3331), .B1(n942), .Y(n3335)
);
OAI22X1TS U4806 ( .A0(n755), .A1(n3343), .B0(n754), .B1(n3401), .Y(n3334) );
OAI31X1TS U4807 ( .A0(n3335), .A1(n963), .A2(n3334), .B0(n3333), .Y(
mult_x_23_n705) );
AOI22X1TS U4808 ( .A0(Op_MY[34]), .A1(n3366), .B0(Op_MY[33]), .B1(n758), .Y(
n3336) );
OAI21X1TS U4809 ( .A0(n3358), .A1(n3337), .B0(n3336), .Y(mult_x_23_n293) );
INVX2TS U4810 ( .A(mult_x_23_n293), .Y(mult_x_23_n304) );
AOI22X1TS U4811 ( .A0(Op_MY[36]), .A1(n3366), .B0(Op_MY[35]), .B1(n758), .Y(
n3338) );
OAI21X1TS U4812 ( .A0(n3358), .A1(n3339), .B0(n3338), .Y(mult_x_23_n658) );
INVX2TS U4813 ( .A(mult_x_23_n222), .Y(n3352) );
AOI22X1TS U4814 ( .A0(Op_MY[43]), .A1(n3366), .B0(n847), .B1(n758), .Y(n3340) );
OAI21XLTS U4815 ( .A0(n3369), .A1(n3341), .B0(n3340), .Y(n3350) );
OAI22X1TS U4816 ( .A0(n3400), .A1(n3365), .B0(n3342), .B1(n942), .Y(n3346)
);
OAI22X1TS U4817 ( .A0(n750), .A1(n3343), .B0(n756), .B1(n3401), .Y(n3345) );
OAI31X1TS U4818 ( .A0(n3346), .A1(n975), .A2(n3345), .B0(n3344), .Y(n3349)
);
AOI22X1TS U4819 ( .A0(Op_MY[44]), .A1(n3366), .B0(Op_MY[43]), .B1(n758), .Y(
n3347) );
OAI21XLTS U4820 ( .A0(n3369), .A1(n3348), .B0(n3347), .Y(n3353) );
CMPR32X2TS U4821 ( .A(n3352), .B(n3350), .C(n3349), .CO(n3351), .S(
mult_x_23_n228) );
CMPR32X2TS U4822 ( .A(n3353), .B(n3352), .C(n3351), .CO(mult_x_23_n220), .S(
mult_x_23_n221) );
AOI22X1TS U4823 ( .A0(Op_MY[39]), .A1(n3366), .B0(Op_MY[38]), .B1(n758), .Y(
n3354) );
OAI21X1TS U4824 ( .A0(n3358), .A1(n3355), .B0(n3354), .Y(n3406) );
INVX2TS U4825 ( .A(mult_x_23_n241), .Y(mult_x_23_n249) );
AOI22X1TS U4826 ( .A0(Op_MY[40]), .A1(n3366), .B0(Op_MY[39]), .B1(n758), .Y(
n3356) );
OAI21X1TS U4827 ( .A0(n3358), .A1(n3357), .B0(n3356), .Y(mult_x_23_n654) );
AOI22X1TS U4828 ( .A0(n847), .A1(n3366), .B0(Op_MY[41]), .B1(n758), .Y(n3359) );
OAI21X1TS U4829 ( .A0(n3369), .A1(n3360), .B0(n3359), .Y(mult_x_23_n652) );
AOI22X1TS U4830 ( .A0(Op_MY[45]), .A1(n3366), .B0(Op_MY[44]), .B1(n758), .Y(
n3361) );
INVX2TS U4831 ( .A(mult_x_23_n207), .Y(mult_x_23_n212) );
CMPR32X2TS U4832 ( .A(mult_x_23_n222), .B(n3363), .C(n3362), .CO(
mult_x_23_n207), .S(mult_x_23_n216) );
AOI22X1TS U4833 ( .A0(Op_MY[46]), .A1(n3366), .B0(Op_MY[45]), .B1(n758), .Y(
n3364) );
OAI21X1TS U4834 ( .A0(n3369), .A1(n3365), .B0(n3364), .Y(mult_x_23_n648) );
AOI22X1TS U4835 ( .A0(n845), .A1(n3366), .B0(Op_MY[47]), .B1(n758), .Y(n3367) );
OAI21X1TS U4836 ( .A0(n3369), .A1(n3368), .B0(n3367), .Y(mult_x_23_n646) );
CMPR32X2TS U4837 ( .A(n3372), .B(n3371), .C(n3370), .CO(n1241), .S(
Sgf_operation_ODD1_left_N3) );
CMPR32X2TS U4838 ( .A(n3375), .B(n3374), .C(n3373), .CO(n1227), .S(
Sgf_operation_ODD1_left_N5) );
CMPR32X2TS U4839 ( .A(mult_x_23_n513), .B(n3377), .C(n3376), .CO(n1223), .S(
Sgf_operation_ODD1_left_N9) );
CMPR32X2TS U4840 ( .A(mult_x_23_n503), .B(n3379), .C(n3378), .CO(n1225), .S(
Sgf_operation_ODD1_left_N11) );
CMPR32X2TS U4841 ( .A(n3382), .B(n3381), .C(n3380), .CO(n3281), .S(
mult_x_23_n381) );
OAI22X1TS U4842 ( .A0(n3383), .A1(n3388), .B0(n759), .B1(n939), .Y(n3387) );
OAI22X1TS U4843 ( .A0(n747), .A1(n3390), .B0(n3298), .B1(n917), .Y(n3386) );
OAI31X1TS U4844 ( .A0(n3387), .A1(n978), .A2(n3386), .B0(n3385), .Y(
mult_x_23_n774) );
OAI22X1TS U4845 ( .A0(n3389), .A1(n3388), .B0(n754), .B1(n939), .Y(n3394) );
OAI22X1TS U4846 ( .A0(n755), .A1(n3390), .B0(n3331), .B1(n917), .Y(n3393) );
OAI31X1TS U4847 ( .A0(n3394), .A1(n963), .A2(n3393), .B0(n3392), .Y(
mult_x_23_n716) );
XNOR2X1TS U4848 ( .A(n3407), .B(n3397), .Y(mult_x_23_n785) );
OAI22X1TS U4849 ( .A0(n3400), .A1(n3399), .B0(n3342), .B1(n3398), .Y(n3405)
);
OAI22X1TS U4850 ( .A0(n750), .A1(n3401), .B0(n756), .B1(n942), .Y(n3404) );
OAI31X1TS U4851 ( .A0(n3405), .A1(n975), .A2(n3404), .B0(n3403), .Y(
mult_x_23_n677) );
CMPR32X2TS U4852 ( .A(mult_x_23_n265), .B(n3407), .C(n3406), .CO(
mult_x_23_n241), .S(mult_x_23_n256) );
ADDHXLTS U4853 ( .A(n3411), .B(n3410), .CO(n3412), .S(
Sgf_operation_ODD1_left_N1) );
ADDHXLTS U4854 ( .A(n3413), .B(n3412), .CO(n3370), .S(
Sgf_operation_ODD1_left_N2) );
CMPR32X2TS U4855 ( .A(n3416), .B(n3415), .C(n3414), .CO(n1230), .S(
Sgf_operation_ODD1_left_N7) );
ADDHXLTS U4856 ( .A(n3420), .B(n3419), .CO(mult_x_23_n434), .S(n2764) );
ADDHXLTS U4857 ( .A(n3422), .B(n3421), .CO(mult_x_23_n485), .S(n2797) );
CMPR32X2TS U4858 ( .A(n3425), .B(n3424), .C(n3423), .CO(n2765), .S(
mult_x_23_n453) );
CMPR32X2TS U4859 ( .A(n3436), .B(n3435), .C(n3434), .CO(n2798), .S(
mult_x_23_n498) );
CMPR32X2TS U4860 ( .A(mult_x_23_n210), .B(mult_x_23_n206), .C(n3437), .CO(
n1221), .S(Sgf_operation_ODD1_left_N45) );
ADDHX1TS U4861 ( .A(n3445), .B(n3444), .CO(n3434), .S(mult_x_23_n505) );
NOR2X1TS U4862 ( .A(n5359), .B(n5340), .Y(n3897) );
CLKXOR2X2TS U4863 ( .A(Op_MX[63]), .B(Op_MY[63]), .Y(n3768) );
NOR4X1TS U4864 ( .A(P_Sgf[0]), .B(P_Sgf[1]), .C(P_Sgf[2]), .D(P_Sgf[3]), .Y(
n3461) );
NOR4X1TS U4865 ( .A(P_Sgf[4]), .B(P_Sgf[5]), .C(P_Sgf[6]), .D(P_Sgf[7]), .Y(
n3460) );
NOR4X1TS U4866 ( .A(P_Sgf[48]), .B(P_Sgf[49]), .C(P_Sgf[50]), .D(P_Sgf[51]),
.Y(n3459) );
OR4X2TS U4867 ( .A(P_Sgf[44]), .B(P_Sgf[45]), .C(P_Sgf[46]), .D(P_Sgf[47]),
.Y(n3457) );
OR4X2TS U4868 ( .A(P_Sgf[40]), .B(P_Sgf[41]), .C(P_Sgf[42]), .D(P_Sgf[43]),
.Y(n3456) );
NOR4X1TS U4869 ( .A(P_Sgf[8]), .B(P_Sgf[9]), .C(P_Sgf[10]), .D(P_Sgf[11]),
.Y(n3449) );
NOR4X1TS U4870 ( .A(P_Sgf[12]), .B(P_Sgf[13]), .C(P_Sgf[14]), .D(P_Sgf[15]),
.Y(n3448) );
NOR4X1TS U4871 ( .A(P_Sgf[16]), .B(P_Sgf[17]), .C(P_Sgf[18]), .D(P_Sgf[19]),
.Y(n3447) );
NOR4X1TS U4872 ( .A(P_Sgf[20]), .B(P_Sgf[21]), .C(P_Sgf[22]), .D(P_Sgf[23]),
.Y(n3446) );
NAND4XLTS U4873 ( .A(n3449), .B(n3448), .C(n3447), .D(n3446), .Y(n3455) );
NOR4X1TS U4874 ( .A(P_Sgf[24]), .B(P_Sgf[25]), .C(P_Sgf[26]), .D(P_Sgf[27]),
.Y(n3453) );
NOR4X1TS U4875 ( .A(P_Sgf[28]), .B(P_Sgf[29]), .C(P_Sgf[30]), .D(P_Sgf[31]),
.Y(n3452) );
NOR4X1TS U4876 ( .A(P_Sgf[32]), .B(P_Sgf[33]), .C(P_Sgf[34]), .D(P_Sgf[35]),
.Y(n3451) );
NOR4X1TS U4877 ( .A(P_Sgf[36]), .B(P_Sgf[37]), .C(P_Sgf[38]), .D(P_Sgf[39]),
.Y(n3450) );
NAND4XLTS U4878 ( .A(n3453), .B(n3452), .C(n3451), .D(n3450), .Y(n3454) );
NOR4X1TS U4879 ( .A(n3457), .B(n3456), .C(n3455), .D(n3454), .Y(n3458) );
NAND4XLTS U4880 ( .A(n3461), .B(n3460), .C(n3459), .D(n3458), .Y(n3463) );
MXI2X1TS U4881 ( .A(n3768), .B(round_mode[1]), .S0(round_mode[0]), .Y(n3462)
);
OAI211X1TS U4882 ( .A0(n3768), .A1(round_mode[1]), .B0(n3463), .C0(n3462),
.Y(n3670) );
AOI32X1TS U4883 ( .A0(FS_Module_state_reg[3]), .A1(n4872), .A2(n3670), .B0(
n728), .B1(n4872), .Y(n3464) );
OAI31X1TS U4884 ( .A0(n728), .A1(n3897), .A2(n5360), .B0(n3464), .Y(n712) );
INVX4TS U4885 ( .A(n734), .Y(n5080) );
BUFX6TS U4886 ( .A(n4682), .Y(n5451) );
NAND2X1TS U4887 ( .A(Op_MX[26]), .B(n4893), .Y(n4856) );
INVX2TS U4888 ( .A(Op_MX[26]), .Y(n4103) );
BUFX6TS U4889 ( .A(n4682), .Y(n4674) );
AOI2BB2X2TS U4890 ( .B0(Op_MX[24]), .B1(n5451), .A0N(n4674), .A1N(Op_MX[24]),
.Y(n4665) );
INVX2TS U4891 ( .A(n4665), .Y(n3469) );
XNOR2X1TS U4892 ( .A(Op_MX[25]), .B(Op_MX[24]), .Y(n3470) );
BUFX3TS U4893 ( .A(n3468), .Y(n4654) );
BUFX4TS U4894 ( .A(n4654), .Y(n4845) );
NOR2X1TS U4895 ( .A(n3470), .B(n3469), .Y(n4662) );
INVX2TS U4896 ( .A(n4662), .Y(n4640) );
BUFX4TS U4897 ( .A(n4640), .Y(n4655) );
OAI22X1TS U4898 ( .A0(n5358), .A1(n4845), .B0(DP_OP_169J45_123_4229_n86),
.B1(n4655), .Y(n3471) );
AOI21X1TS U4899 ( .A0(n4847), .A1(n842), .B0(n3471), .Y(n3472) );
XNOR2X1TS U4900 ( .A(Op_MX[26]), .B(n3472), .Y(n4843) );
BUFX6TS U4901 ( .A(n934), .Y(n4510) );
AOI2BB2X2TS U4902 ( .B0(Op_MX[3]), .B1(n931), .A0N(n5453), .A1N(Op_MX[3]),
.Y(n3619) );
INVX2TS U4903 ( .A(n3619), .Y(n3474) );
BUFX3TS U4904 ( .A(n5358), .Y(n4835) );
BUFX4TS U4905 ( .A(n4506), .Y(n4840) );
OAI22X1TS U4906 ( .A0(n4835), .A1(n4840), .B0(n853), .B1(n4458), .Y(n3476)
);
AOI21X1TS U4907 ( .A0(n4841), .A1(n842), .B0(n3476), .Y(n3477) );
XNOR2X1TS U4908 ( .A(n4913), .B(n3477), .Y(n4555) );
NOR3X1TS U4909 ( .A(Op_MX[1]), .B(Op_MX[0]), .C(n931), .Y(n3481) );
AOI2BB2X1TS U4910 ( .B0(Op_MX[1]), .B1(n931), .A0N(n931), .A1N(Op_MX[1]),
.Y(n3485) );
NOR2X2TS U4911 ( .A(n3485), .B(n5341), .Y(n3663) );
AOI22X1TS U4912 ( .A0(Op_MY[26]), .A1(n3481), .B0(n3663), .B1(n4846), .Y(
n3480) );
XNOR2X1TS U4913 ( .A(n731), .B(n3480), .Y(n4558) );
INVX2TS U4914 ( .A(n3481), .Y(n3482) );
CLKAND2X2TS U4915 ( .A(Op_MX[1]), .B(n5341), .Y(n3664) );
OAI22X1TS U4916 ( .A0(n4835), .A1(n3657), .B0(n852), .B1(n3648), .Y(n3483)
);
AOI21X1TS U4917 ( .A0(n3663), .A1(n842), .B0(n3483), .Y(n3484) );
XNOR2X1TS U4918 ( .A(n731), .B(n3484), .Y(n4560) );
CLKAND2X2TS U4919 ( .A(Op_MX[0]), .B(n3485), .Y(n3665) );
CMPR32X2TS U4920 ( .A(Op_MY[25]), .B(Op_MY[26]), .C(n3486), .CO(n3478), .S(
n3487) );
OAI22X1TS U4921 ( .A0(n852), .A1(n751), .B0(n4068), .B1(n3504), .Y(n3491) );
BUFX4TS U4922 ( .A(n3488), .Y(n4081) );
OAI22X1TS U4923 ( .A0(n4835), .A1(n3648), .B0(n4081), .B1(n3657), .Y(n3490)
);
OAI31X1TS U4924 ( .A0(n3491), .A1(n931), .A2(n3490), .B0(n3489), .Y(n4562)
);
CMPR32X2TS U4925 ( .A(n4893), .B(Op_MY[25]), .C(n3492), .CO(n3486), .S(n3493) );
OAI22X1TS U4926 ( .A0(n5354), .A1(n3657), .B0(n4334), .B1(n3504), .Y(n3496)
);
INVX3TS U4927 ( .A(n3664), .Y(n3658) );
OAI22X1TS U4928 ( .A0(n4835), .A1(n751), .B0(n949), .B1(n3658), .Y(n3495) );
OAI31X1TS U4929 ( .A0(n3496), .A1(n5453), .A2(n3495), .B0(n3494), .Y(n4564)
);
BUFX3TS U4930 ( .A(n5357), .Y(n4444) );
CMPR32X2TS U4931 ( .A(Op_MY[23]), .B(n4893), .C(n3497), .CO(n3492), .S(n3498) );
OAI22X1TS U4932 ( .A0(n4444), .A1(n3657), .B0(n4080), .B1(n3504), .Y(n3501)
);
OAI22X1TS U4933 ( .A0(n4081), .A1(n751), .B0(n5354), .B1(n3658), .Y(n3500)
);
OAI31X1TS U4934 ( .A0(n3501), .A1(n5453), .A2(n3500), .B0(n3499), .Y(n4566)
);
OAI22X1TS U4935 ( .A0(n4444), .A1(n3648), .B0(n4433), .B1(n3504), .Y(n3507)
);
OAI22X1TS U4936 ( .A0(n4434), .A1(n751), .B0(n5379), .B1(n3482), .Y(n3506)
);
OAI31X1TS U4937 ( .A0(n3507), .A1(n5453), .A2(n3506), .B0(n3505), .Y(n4568)
);
OAI22X1TS U4938 ( .A0(n5353), .A1(n3482), .B0(n4442), .B1(n3504), .Y(n3512)
);
OAI22X1TS U4939 ( .A0(n4444), .A1(n751), .B0(n5379), .B1(n3658), .Y(n3511)
);
OAI31X1TS U4940 ( .A0(n3512), .A1(n5453), .A2(n3511), .B0(n3510), .Y(n4570)
);
BUFX3TS U4941 ( .A(n5356), .Y(n4428) );
CMPR32X2TS U4942 ( .A(Op_MY[20]), .B(Op_MY[21]), .C(n3513), .CO(n3508), .S(
n3514) );
OAI22X1TS U4943 ( .A0(n4428), .A1(n3482), .B0(n4611), .B1(n3504), .Y(n3517)
);
OAI22X1TS U4944 ( .A0(n4429), .A1(n751), .B0(n5353), .B1(n3658), .Y(n3516)
);
OAI31X1TS U4945 ( .A0(n3517), .A1(n5453), .A2(n3516), .B0(n3515), .Y(n4572)
);
OAI22X1TS U4946 ( .A0(n4428), .A1(n3648), .B0(n4424), .B1(n3504), .Y(n3522)
);
OAI22X1TS U4947 ( .A0(n4607), .A1(n751), .B0(n5377), .B1(n3482), .Y(n3521)
);
OAI31X1TS U4948 ( .A0(n3522), .A1(n5453), .A2(n3521), .B0(n3520), .Y(n4574)
);
BUFX3TS U4949 ( .A(n5355), .Y(n4420) );
OAI22X1TS U4950 ( .A0(n4420), .A1(n3482), .B0(n4419), .B1(n3504), .Y(n3527)
);
OAI22X1TS U4951 ( .A0(n4428), .A1(n751), .B0(n5377), .B1(n3658), .Y(n3526)
);
OAI31X1TS U4952 ( .A0(n3527), .A1(n5453), .A2(n3526), .B0(n3525), .Y(n4576)
);
OAI22X1TS U4953 ( .A0(n4420), .A1(n3648), .B0(n4414), .B1(n3504), .Y(n3532)
);
OAI22X1TS U4954 ( .A0(n4415), .A1(n751), .B0(n4438), .B1(n3482), .Y(n3531)
);
OAI31X1TS U4955 ( .A0(n3532), .A1(n5453), .A2(n3531), .B0(n3530), .Y(n4578)
);
OAI22X1TS U4956 ( .A0(n4420), .A1(n751), .B0(n4410), .B1(n3504), .Y(n3537)
);
OAI22X1TS U4957 ( .A0(n4438), .A1(n3648), .B0(n5374), .B1(n3482), .Y(n3536)
);
OAI31X1TS U4958 ( .A0(n3537), .A1(n5453), .A2(n3536), .B0(n3535), .Y(n4580)
);
CMPR32X2TS U4959 ( .A(Op_MY[15]), .B(Op_MY[16]), .C(n3538), .CO(n3533), .S(
n3539) );
OAI22X1TS U4960 ( .A0(n5349), .A1(n3657), .B0(n4622), .B1(n3504), .Y(n3542)
);
OAI22X1TS U4961 ( .A0(n5348), .A1(n751), .B0(n5374), .B1(n3658), .Y(n3541)
);
OAI31X1TS U4962 ( .A0(n3542), .A1(n5453), .A2(n3541), .B0(n3540), .Y(n4582)
);
BUFX3TS U4963 ( .A(n5352), .Y(n4453) );
CMPR32X2TS U4964 ( .A(Op_MY[14]), .B(Op_MY[15]), .C(n3543), .CO(n3538), .S(
n3544) );
OAI22X1TS U4965 ( .A0(n4453), .A1(n3657), .B0(n4629), .B1(n3504), .Y(n3547)
);
OAI22X1TS U4966 ( .A0(n4630), .A1(n751), .B0(n5349), .B1(n3658), .Y(n3546)
);
OAI31X1TS U4967 ( .A0(n3547), .A1(n5453), .A2(n3546), .B0(n3545), .Y(n4584)
);
OAI22X1TS U4968 ( .A0(n4453), .A1(n3648), .B0(n4452), .B1(n3504), .Y(n3552)
);
OAI22X1TS U4969 ( .A0(n4621), .A1(n751), .B0(n5372), .B1(n3482), .Y(n3551)
);
OAI31X1TS U4970 ( .A0(n3552), .A1(n5453), .A2(n3551), .B0(n3550), .Y(n4586)
);
BUFX3TS U4971 ( .A(n5351), .Y(n4467) );
INVX2TS U4972 ( .A(n3554), .Y(n4448) );
OAI22X1TS U4973 ( .A0(n4467), .A1(n3657), .B0(n4448), .B1(n3504), .Y(n3557)
);
OAI22X1TS U4974 ( .A0(n4453), .A1(n751), .B0(n5372), .B1(n3658), .Y(n3556)
);
OAI31X1TS U4975 ( .A0(n3557), .A1(n5453), .A2(n3556), .B0(n3555), .Y(n4588)
);
INVX2TS U4976 ( .A(n3559), .Y(n4457) );
OAI22X1TS U4977 ( .A0(n4467), .A1(n3648), .B0(n4457), .B1(n3504), .Y(n3562)
);
OAI22X1TS U4978 ( .A0(n4459), .A1(n751), .B0(n4471), .B1(n3657), .Y(n3561)
);
OAI31X1TS U4979 ( .A0(n3562), .A1(n5453), .A2(n3561), .B0(n3560), .Y(n4590)
);
INVX2TS U4980 ( .A(n3564), .Y(n4466) );
OAI22X1TS U4981 ( .A0(n4467), .A1(n751), .B0(n4466), .B1(n3504), .Y(n3567)
);
OAI22X1TS U4982 ( .A0(n4471), .A1(n3648), .B0(n5371), .B1(n3657), .Y(n3566)
);
OAI31X1TS U4983 ( .A0(n3567), .A1(n931), .A2(n3566), .B0(n3565), .Y(n4592)
);
INVX2TS U4984 ( .A(n3569), .Y(n4639) );
OAI22X1TS U4985 ( .A0(n5346), .A1(n3657), .B0(n4639), .B1(n3504), .Y(n3572)
);
OAI22X1TS U4986 ( .A0(n5347), .A1(n751), .B0(n5371), .B1(n3658), .Y(n3571)
);
OAI31X1TS U4987 ( .A0(n3572), .A1(n931), .A2(n3571), .B0(n3570), .Y(n4594)
);
BUFX3TS U4988 ( .A(n5350), .Y(n4498) );
CMPR32X2TS U4989 ( .A(Op_MY[8]), .B(Op_MY[9]), .C(n3573), .CO(n3568), .S(
n3574) );
INVX2TS U4990 ( .A(n3574), .Y(n4647) );
OAI22X1TS U4991 ( .A0(n4498), .A1(n3657), .B0(n4647), .B1(n3504), .Y(n3577)
);
OAI22X1TS U4992 ( .A0(n4648), .A1(n751), .B0(n5346), .B1(n3658), .Y(n3576)
);
OAI31X1TS U4993 ( .A0(n3577), .A1(n931), .A2(n3576), .B0(n3575), .Y(n4596)
);
INVX2TS U4994 ( .A(Op_MY[0]), .Y(n3590) );
BUFX4TS U4995 ( .A(n3590), .Y(n4755) );
BUFX6TS U4996 ( .A(n929), .Y(n4516) );
BUFX6TS U4997 ( .A(n4878), .Y(n4513) );
XNOR2X1TS U4998 ( .A(Op_MX[7]), .B(Op_MX[6]), .Y(n3583) );
INVX2TS U4999 ( .A(n3580), .Y(n4756) );
INVX2TS U5000 ( .A(n3592), .Y(n3582) );
OAI22X1TS U5001 ( .A0(n4755), .A1(n4515), .B0(n4756), .B1(n743), .Y(n3586)
);
BUFX6TS U5002 ( .A(n4516), .Y(n4519) );
OAI22X1TS U5003 ( .A0(n5342), .A1(n4351), .B0(n4779), .B1(n4051), .Y(n3585)
);
OAI31X1TS U5004 ( .A0(n3586), .A1(n4519), .A2(n3585), .B0(n3584), .Y(n3669)
);
AOI222X1TS U5005 ( .A0(n4892), .A1(n3588), .B0(Op_MY[0]), .B1(n3587), .C0(
n4838), .C1(n4749), .Y(n3589) );
XNOR2X1TS U5006 ( .A(n4914), .B(n3589), .Y(n3600) );
OAI31X1TS U5007 ( .A0(n4755), .A1(n4914), .A2(n3592), .B0(n3591), .Y(n3611)
);
INVX2TS U5008 ( .A(n3594), .Y(n4764) );
OAI22X1TS U5009 ( .A0(n5344), .A1(n4506), .B0(n4764), .B1(n745), .Y(n3598)
);
BUFX4TS U5010 ( .A(n4458), .Y(n4507) );
OAI22X1TS U5011 ( .A0(n5345), .A1(n4443), .B0(n4765), .B1(n4507), .Y(n3597)
);
OAI31X1TS U5012 ( .A0(n3598), .A1(n4513), .A2(n3597), .B0(n3596), .Y(n4800)
);
ADDHXLTS U5013 ( .A(n3600), .B(n3599), .CO(n3668), .S(n3627) );
INVX2TS U5014 ( .A(n3602), .Y(n4771) );
OAI22X1TS U5015 ( .A0(n5342), .A1(n4506), .B0(n4771), .B1(n745), .Y(n3605)
);
OAI22X1TS U5016 ( .A0(n5343), .A1(n4443), .B0(n5344), .B1(n4507), .Y(n3604)
);
OAI31X1TS U5017 ( .A0(n3605), .A1(n4513), .A2(n3604), .B0(n3603), .Y(n3626)
);
INVX2TS U5018 ( .A(n3607), .Y(n4777) );
OAI22X1TS U5019 ( .A0(n4779), .A1(n4506), .B0(n4777), .B1(n745), .Y(n3610)
);
OAI22X1TS U5020 ( .A0(n4781), .A1(n4443), .B0(n5342), .B1(n4507), .Y(n3609)
);
OAI31X1TS U5021 ( .A0(n3610), .A1(n4513), .A2(n3609), .B0(n3608), .Y(n3635)
);
ADDHXLTS U5022 ( .A(n4914), .B(n3611), .CO(n3599), .S(n3634) );
OAI22X1TS U5023 ( .A0(n3590), .A1(n4506), .B0(n4756), .B1(n745), .Y(n3614)
);
BUFX4TS U5024 ( .A(n5342), .Y(n4772) );
OAI22X1TS U5025 ( .A0(n4772), .A1(n4443), .B0(n4779), .B1(n4507), .Y(n3613)
);
OAI31X1TS U5026 ( .A0(n3614), .A1(n4513), .A2(n3613), .B0(n3612), .Y(n3642)
);
AOI222X1TS U5027 ( .A0(n4892), .A1(n3616), .B0(Op_MY[0]), .B1(n3615), .C0(
n4841), .C1(n4749), .Y(n3617) );
XNOR2X1TS U5028 ( .A(n4913), .B(n3617), .Y(n3647) );
OAI31X1TS U5029 ( .A0(n4755), .A1(n4913), .A2(n3619), .B0(n3618), .Y(n3652)
);
INVX2TS U5030 ( .A(n3621), .Y(n4490) );
OAI22X1TS U5031 ( .A0(n4498), .A1(n3648), .B0(n4490), .B1(n3504), .Y(n3624)
);
OAI22X1TS U5032 ( .A0(n4638), .A1(n751), .B0(n5369), .B1(n3657), .Y(n3623)
);
OAI31X1TS U5033 ( .A0(n3624), .A1(n931), .A2(n3623), .B0(n3622), .Y(n3752)
);
CMPR32X2TS U5034 ( .A(n3627), .B(n3626), .C(n3625), .CO(n4799), .S(n3756) );
INVX2TS U5035 ( .A(n3629), .Y(n4497) );
OAI22X1TS U5036 ( .A0(n4508), .A1(n3657), .B0(n4497), .B1(n3504), .Y(n3632)
);
OAI22X1TS U5037 ( .A0(n4498), .A1(n751), .B0(n5369), .B1(n3658), .Y(n3631)
);
OAI31X1TS U5038 ( .A0(n3632), .A1(n931), .A2(n3631), .B0(n3630), .Y(n3755)
);
CMPR32X2TS U5039 ( .A(n3635), .B(n3634), .C(n3633), .CO(n3625), .S(n3759) );
INVX2TS U5040 ( .A(n3637), .Y(n4505) );
OAI22X1TS U5041 ( .A0(n4765), .A1(n3657), .B0(n4505), .B1(n3504), .Y(n3640)
);
OAI22X1TS U5042 ( .A0(n4509), .A1(n751), .B0(n4508), .B1(n3648), .Y(n3639)
);
OAI31X1TS U5043 ( .A0(n3640), .A1(n931), .A2(n3639), .B0(n3638), .Y(n3758)
);
ADDHXLTS U5044 ( .A(n3642), .B(n3641), .CO(n3633), .S(n4599) );
OAI22X1TS U5045 ( .A0(n5344), .A1(n3657), .B0(n4764), .B1(n3504), .Y(n3645)
);
OAI22X1TS U5046 ( .A0(n5345), .A1(n751), .B0(n4765), .B1(n3648), .Y(n3644)
);
OAI31X1TS U5047 ( .A0(n3645), .A1(n931), .A2(n3644), .B0(n3643), .Y(n4598)
);
ADDHXLTS U5048 ( .A(n3647), .B(n3646), .CO(n3641), .S(n4602) );
OAI22X1TS U5049 ( .A0(n5342), .A1(n3657), .B0(n4771), .B1(n3504), .Y(n3651)
);
OAI22X1TS U5050 ( .A0(n5343), .A1(n751), .B0(n5344), .B1(n3648), .Y(n3650)
);
OAI31X1TS U5051 ( .A0(n3651), .A1(n931), .A2(n3650), .B0(n3649), .Y(n4601)
);
ADDHXLTS U5052 ( .A(n4913), .B(n3652), .CO(n3646), .S(n4605) );
OAI22X1TS U5053 ( .A0(n4779), .A1(n3657), .B0(n4777), .B1(n3504), .Y(n3656)
);
OAI22X1TS U5054 ( .A0(n4781), .A1(n751), .B0(n5342), .B1(n3658), .Y(n3654)
);
OAI31X1TS U5055 ( .A0(n3656), .A1(n931), .A2(n3654), .B0(n3653), .Y(n4604)
);
OAI22X1TS U5056 ( .A0(n3590), .A1(n3657), .B0(n4756), .B1(n3504), .Y(n3662)
);
OAI22X1TS U5057 ( .A0(n4772), .A1(n751), .B0(n4779), .B1(n3658), .Y(n3661)
);
OAI31X1TS U5058 ( .A0(n3662), .A1(n5453), .A2(n3661), .B0(n3660), .Y(n3761)
);
AOI222X1TS U5059 ( .A0(n4892), .A1(n3665), .B0(Op_MY[0]), .B1(n3664), .C0(
n3663), .C1(n4749), .Y(n3666) );
XNOR2X1TS U5060 ( .A(n731), .B(n3666), .Y(n3763) );
OAI21XLTS U5061 ( .A0(n930), .A1(n5341), .B0(n731), .Y(n3667) );
OAI31X1TS U5062 ( .A0(n4755), .A1(n731), .A2(n5341), .B0(n3667), .Y(n4606)
);
BUFX6TS U5063 ( .A(n4278), .Y(n5452) );
ADDHXLTS U5064 ( .A(n3669), .B(n3668), .CO(mult_x_24_n583), .S(n4801) );
OR2X1TS U5065 ( .A(exp_oper_result[11]), .B(Exp_module_Overflow_flag_A), .Y(
overflow_flag) );
OAI31X1TS U5066 ( .A0(n728), .A1(n3671), .A2(n3670), .B0(n5362), .Y(n709) );
BUFX3TS U5067 ( .A(n5478), .Y(n5457) );
BUFX3TS U5068 ( .A(n5478), .Y(n5455) );
NAND2X1TS U5069 ( .A(n5340), .B(n4872), .Y(n3682) );
BUFX3TS U5070 ( .A(n3683), .Y(n5463) );
INVX2TS U5071 ( .A(n728), .Y(n3896) );
NAND4X1TS U5072 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[2]),
.C(n3896), .D(n5340), .Y(n4874) );
NAND2BXLTS U5073 ( .AN(n4874), .B(P_Sgf[105]), .Y(n3767) );
NAND4X1TS U5074 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[3]),
.C(n5359), .D(n3896), .Y(n4947) );
NAND3X1TS U5075 ( .A(FS_Module_state_reg[0]), .B(n728), .C(n5359), .Y(n4875)
);
INVX2TS U5076 ( .A(n4941), .Y(n4939) );
NAND2X1TS U5077 ( .A(n753), .B(n4939), .Y(n3685) );
AO21XLTS U5078 ( .A0(n3767), .A1(FSM_selector_B[0]), .B0(n3685), .Y(n419) );
NOR2XLTS U5079 ( .A(n4875), .B(n5340), .Y(n3686) );
BUFX3TS U5080 ( .A(n3686), .Y(n5207) );
AO22XLTS U5081 ( .A0(Sgf_normalized_result[45]), .A1(n5206), .B0(
final_result_ieee[45]), .B1(n5201), .Y(n306) );
BUFX4TS U5082 ( .A(n5201), .Y(n5205) );
AO22XLTS U5083 ( .A0(Sgf_normalized_result[39]), .A1(n5206), .B0(
final_result_ieee[39]), .B1(n5205), .Y(n312) );
AO22XLTS U5084 ( .A0(Sgf_normalized_result[47]), .A1(n5206), .B0(
final_result_ieee[47]), .B1(n5201), .Y(n304) );
AO22XLTS U5085 ( .A0(Sgf_normalized_result[41]), .A1(n5206), .B0(
final_result_ieee[41]), .B1(n5201), .Y(n310) );
AO22XLTS U5086 ( .A0(Sgf_normalized_result[49]), .A1(n5206), .B0(
final_result_ieee[49]), .B1(n5201), .Y(n302) );
AO22XLTS U5087 ( .A0(Sgf_normalized_result[51]), .A1(n5206), .B0(
final_result_ieee[51]), .B1(n5201), .Y(n300) );
AO22XLTS U5088 ( .A0(Sgf_normalized_result[43]), .A1(n5206), .B0(
final_result_ieee[43]), .B1(n5201), .Y(n308) );
NAND2X1TS U5089 ( .A(Op_MX[26]), .B(Op_MY[21]), .Y(mult_x_24_n219) );
NAND2X1TS U5090 ( .A(Op_MX[26]), .B(Op_MY[15]), .Y(mult_x_24_n256) );
NAND2X1TS U5091 ( .A(Op_MX[26]), .B(Op_MY[16]), .Y(mult_x_24_n249) );
NAND2X1TS U5092 ( .A(Op_MX[26]), .B(Op_MY[9]), .Y(mult_x_24_n311) );
BUFX4TS U5093 ( .A(n734), .Y(n5198) );
CMPR32X2TS U5094 ( .A(n3688), .B(Sgf_operation_ODD1_Q_right[52]), .C(n3687),
.CO(n5115), .S(n3689) );
AO22XLTS U5095 ( .A0(n5127), .A1(P_Sgf[52]), .B0(n5198), .B1(n3689), .Y(n473) );
NAND2X1TS U5096 ( .A(Op_MX[26]), .B(Op_MY[10]), .Y(mult_x_24_n301) );
AO22XLTS U5097 ( .A0(n5127), .A1(P_Sgf[55]), .B0(n5198), .B1(n3692), .Y(n476) );
BUFX3TS U5098 ( .A(n753), .Y(n5037) );
INVX3TS U5099 ( .A(n5037), .Y(n5024) );
NAND2X1TS U5100 ( .A(Sgf_normalized_result[6]), .B(n4953), .Y(n4955) );
NOR2X2TS U5101 ( .A(n5364), .B(n4955), .Y(n4957) );
NAND2X1TS U5102 ( .A(Sgf_normalized_result[8]), .B(n4957), .Y(n4959) );
NOR2X2TS U5103 ( .A(n5365), .B(n4959), .Y(n4961) );
NAND2X1TS U5104 ( .A(Sgf_normalized_result[10]), .B(n4961), .Y(n4963) );
NOR2X2TS U5105 ( .A(n5366), .B(n4963), .Y(n4965) );
NAND2X1TS U5106 ( .A(Sgf_normalized_result[12]), .B(n4965), .Y(n4967) );
NOR2X2TS U5107 ( .A(n5367), .B(n4967), .Y(n4969) );
NAND2X1TS U5108 ( .A(Sgf_normalized_result[14]), .B(n4969), .Y(n4971) );
NOR2X2TS U5109 ( .A(n5368), .B(n4971), .Y(n4973) );
NAND2X1TS U5110 ( .A(Sgf_normalized_result[16]), .B(n4973), .Y(n4975) );
NOR2X2TS U5111 ( .A(n5370), .B(n4975), .Y(n4977) );
NAND2X1TS U5112 ( .A(Sgf_normalized_result[18]), .B(n4977), .Y(n4979) );
NOR2X2TS U5113 ( .A(n5373), .B(n4979), .Y(n4981) );
NOR2X2TS U5114 ( .A(n5375), .B(n4983), .Y(n4985) );
NAND2X1TS U5115 ( .A(Sgf_normalized_result[22]), .B(n4985), .Y(n4987) );
NOR2X2TS U5116 ( .A(n5376), .B(n4987), .Y(n4990) );
NAND2X1TS U5117 ( .A(Sgf_normalized_result[24]), .B(n4990), .Y(n4989) );
NOR2X2TS U5118 ( .A(n5378), .B(n4989), .Y(n4993) );
AOI21X1TS U5119 ( .A0(n5378), .A1(n4989), .B0(n4993), .Y(n3693) );
NAND2X1TS U5120 ( .A(Sgf_normalized_result[26]), .B(n4993), .Y(n4992) );
NOR2X2TS U5121 ( .A(n5380), .B(n4992), .Y(n4995) );
AOI21X1TS U5122 ( .A0(n5380), .A1(n4992), .B0(n4995), .Y(n3694) );
INVX4TS U5123 ( .A(n734), .Y(n3746) );
BUFX4TS U5124 ( .A(n5198), .Y(n5111) );
AO22XLTS U5125 ( .A0(n3746), .A1(P_Sgf[66]), .B0(n5111), .B1(n3697), .Y(n487) );
AO22XLTS U5126 ( .A0(n3746), .A1(P_Sgf[67]), .B0(n5111), .B1(n3700), .Y(n488) );
AO22XLTS U5127 ( .A0(n3746), .A1(P_Sgf[68]), .B0(n5111), .B1(n3703), .Y(n489) );
AO22XLTS U5128 ( .A0(n3746), .A1(P_Sgf[69]), .B0(n5111), .B1(n3706), .Y(n490) );
AO22XLTS U5129 ( .A0(n3746), .A1(P_Sgf[70]), .B0(n5111), .B1(n3709), .Y(n491) );
CMPR32X2TS U5130 ( .A(n3711), .B(Sgf_operation_ODD1_Q_left[17]), .C(n3710),
.CO(n3713), .S(n3712) );
AO22XLTS U5131 ( .A0(n3746), .A1(P_Sgf[71]), .B0(n5111), .B1(n3712), .Y(n492) );
AO22XLTS U5132 ( .A0(n3746), .A1(P_Sgf[72]), .B0(n5111), .B1(n3715), .Y(n493) );
AO22XLTS U5133 ( .A0(n3746), .A1(P_Sgf[73]), .B0(n5111), .B1(n3718), .Y(n494) );
CMPR32X2TS U5134 ( .A(n3720), .B(Sgf_operation_ODD1_Q_left[20]), .C(n3719),
.CO(n3722), .S(n3721) );
AO22XLTS U5135 ( .A0(n3746), .A1(P_Sgf[74]), .B0(n5111), .B1(n3721), .Y(n495) );
CMPR32X2TS U5136 ( .A(n3723), .B(Sgf_operation_ODD1_Q_left[21]), .C(n3722),
.CO(n3725), .S(n3724) );
AO22XLTS U5137 ( .A0(n3746), .A1(P_Sgf[75]), .B0(n5111), .B1(n3724), .Y(n496) );
CMPR32X2TS U5138 ( .A(n3726), .B(Sgf_operation_ODD1_Q_left[22]), .C(n3725),
.CO(n3728), .S(n3727) );
AO22XLTS U5139 ( .A0(n3746), .A1(P_Sgf[76]), .B0(n5111), .B1(n3727), .Y(n497) );
AO22XLTS U5140 ( .A0(n3746), .A1(P_Sgf[77]), .B0(n5111), .B1(n3730), .Y(n498) );
CMPR32X2TS U5141 ( .A(n3732), .B(Sgf_operation_ODD1_Q_left[24]), .C(n3731),
.CO(n3734), .S(n3733) );
AO22XLTS U5142 ( .A0(n3746), .A1(P_Sgf[78]), .B0(n5111), .B1(n3733), .Y(n499) );
AO22XLTS U5143 ( .A0(n3746), .A1(P_Sgf[79]), .B0(n5111), .B1(n3736), .Y(n500) );
ADDFHX4TS U5144 ( .A(n3738), .B(Sgf_operation_ODD1_Q_left[26]), .CI(n3737),
.CO(n3740), .S(n3739) );
AO22XLTS U5145 ( .A0(n3746), .A1(P_Sgf[80]), .B0(n5111), .B1(n3739), .Y(n501) );
AO22XLTS U5146 ( .A0(n3746), .A1(P_Sgf[81]), .B0(n5111), .B1(n3742), .Y(n502) );
CMPR32X2TS U5147 ( .A(n3744), .B(Sgf_operation_ODD1_Q_left[28]), .C(n3743),
.CO(n5078), .S(n3745) );
AO22XLTS U5148 ( .A0(n3746), .A1(P_Sgf[82]), .B0(n5111), .B1(n3745), .Y(n503) );
AOI2BB2X2TS U5149 ( .B0(Op_MX[9]), .B1(n4519), .A0N(n929), .A1N(Op_MX[9]),
.Y(n4035) );
BUFX6TS U5150 ( .A(n4278), .Y(n4782) );
INVX2TS U5151 ( .A(n4035), .Y(n3747) );
AOI222X1TS U5152 ( .A0(n4892), .A1(n4032), .B0(Op_MY[0]), .B1(n4033), .C0(
n4830), .C1(n4749), .Y(n3748) );
XNOR2X1TS U5153 ( .A(n4915), .B(n3748), .Y(n4761) );
OAI31X1TS U5154 ( .A0(n4755), .A1(n4915), .A2(n4035), .B0(n3749), .Y(n4798)
);
NAND2X1TS U5155 ( .A(Sgf_normalized_result[28]), .B(n4995), .Y(n4997) );
NOR2X2TS U5156 ( .A(n5381), .B(n4997), .Y(n4999) );
NOR2X2TS U5157 ( .A(n5382), .B(n5001), .Y(n5003) );
NOR2X2TS U5158 ( .A(n5383), .B(n5005), .Y(n5007) );
NOR2X2TS U5159 ( .A(n5385), .B(n5014), .Y(n5016) );
NOR2X2TS U5160 ( .A(n5386), .B(n5018), .Y(n5020) );
NOR2X2TS U5161 ( .A(n5387), .B(n5022), .Y(n5026) );
NOR2X2TS U5162 ( .A(n5390), .B(n5025), .Y(n5029) );
AOI21X1TS U5163 ( .A0(n5390), .A1(n5025), .B0(n5029), .Y(n3750) );
CMPR32X2TS U5164 ( .A(n3753), .B(n3752), .C(n3751), .CO(n4595), .S(
Sgf_operation_ODD1_right_N8) );
CMPR32X2TS U5165 ( .A(n3756), .B(n3755), .C(n3754), .CO(n3751), .S(
Sgf_operation_ODD1_right_N7) );
CMPR32X2TS U5166 ( .A(n3759), .B(n3758), .C(n3757), .CO(n3754), .S(
Sgf_operation_ODD1_right_N6) );
ADDHXLTS U5167 ( .A(n3761), .B(n3760), .CO(n4603), .S(
Sgf_operation_ODD1_right_N2) );
ADDHXLTS U5168 ( .A(n3763), .B(n3762), .CO(n3760), .S(
Sgf_operation_ODD1_right_N1) );
NOR2X2TS U5169 ( .A(n5391), .B(n5028), .Y(n5032) );
AOI21X1TS U5170 ( .A0(n5391), .A1(n5028), .B0(n5032), .Y(n3764) );
NOR2X2TS U5171 ( .A(n5392), .B(n5031), .Y(n5035) );
AOI21X1TS U5172 ( .A0(n5392), .A1(n5031), .B0(n5035), .Y(n3765) );
NAND2X1TS U5173 ( .A(Sgf_normalized_result[48]), .B(n5035), .Y(n5034) );
NOR2X2TS U5174 ( .A(n5393), .B(n5034), .Y(n5039) );
AOI21X1TS U5175 ( .A0(n5393), .A1(n5034), .B0(n5039), .Y(n3766) );
BUFX3TS U5176 ( .A(n3683), .Y(n5466) );
BUFX3TS U5177 ( .A(n3683), .Y(n5462) );
BUFX3TS U5178 ( .A(n3683), .Y(n5464) );
BUFX3TS U5179 ( .A(n3683), .Y(n5475) );
BUFX3TS U5180 ( .A(n3683), .Y(n5476) );
INVX4TS U5181 ( .A(n4947), .Y(n5047) );
OAI31X1TS U5182 ( .A0(n4941), .A1(n5047), .A2(n5389), .B0(n3767), .Y(n418)
);
NOR2XLTS U5183 ( .A(n3768), .B(underflow_flag), .Y(n3769) );
OAI32X1TS U5184 ( .A0(n5201), .A1(n3769), .A2(overflow_flag), .B0(n5207),
.B1(n5450), .Y(n287) );
INVX2TS U5185 ( .A(mult_x_24_n219), .Y(mult_x_24_n604) );
BUFX4TS U5186 ( .A(n4103), .Y(n4656) );
BUFX6TS U5187 ( .A(n4656), .Y(n4844) );
AOI32X4TS U5188 ( .A0(FSM_add_overflow_flag), .A1(n728), .A2(n3771), .B0(
n3770), .B1(n728), .Y(n4946) );
BUFX3TS U5189 ( .A(n3783), .Y(n3876) );
AOI32X1TS U5190 ( .A0(FS_Module_state_reg[2]), .A1(n728), .A2(n5340), .B0(
n3771), .B1(n728), .Y(n3773) );
INVX2TS U5191 ( .A(n3773), .Y(n4945) );
INVX4TS U5192 ( .A(n4945), .Y(n3899) );
NOR2X1TS U5193 ( .A(n4946), .B(n5362), .Y(n3784) );
CLKBUFX2TS U5194 ( .A(n3784), .Y(n3831) );
AOI22X1TS U5195 ( .A0(Sgf_normalized_result[46]), .A1(n3899), .B0(
Add_result[47]), .B1(n3831), .Y(n3777) );
NAND2X1TS U5196 ( .A(n4945), .B(n4946), .Y(n3774) );
NOR2XLTS U5197 ( .A(n5362), .B(n3774), .Y(n3780) );
BUFX4TS U5198 ( .A(n3775), .Y(n3866) );
AOI22X1TS U5199 ( .A0(Add_result[46]), .A1(n736), .B0(n3866), .B1(P_Sgf[98]),
.Y(n3776) );
OAI211XLTS U5200 ( .A0(n3876), .A1(n5410), .B0(n3777), .C0(n3776), .Y(n399)
);
AOI22X1TS U5201 ( .A0(Sgf_normalized_result[41]), .A1(n3899), .B0(
Add_result[42]), .B1(n3890), .Y(n3779) );
AOI22X1TS U5202 ( .A0(Add_result[41]), .A1(n736), .B0(n3866), .B1(P_Sgf[93]),
.Y(n3778) );
OAI211XLTS U5203 ( .A0(n3876), .A1(n5415), .B0(n3779), .C0(n3778), .Y(n394)
);
BUFX3TS U5204 ( .A(n3783), .Y(n3887) );
INVX3TS U5205 ( .A(n4945), .Y(n3883) );
AOI22X1TS U5206 ( .A0(Sgf_normalized_result[21]), .A1(n3883), .B0(
Add_result[22]), .B1(n3890), .Y(n3782) );
AOI22X1TS U5207 ( .A0(Add_result[21]), .A1(n736), .B0(n3866), .B1(P_Sgf[73]),
.Y(n3781) );
OAI211XLTS U5208 ( .A0(n3887), .A1(n5435), .B0(n3782), .C0(n3781), .Y(n374)
);
INVX4TS U5209 ( .A(n4945), .Y(n3891) );
AOI22X1TS U5210 ( .A0(Add_result[1]), .A1(n3871), .B0(
Sgf_normalized_result[0]), .B1(n3891), .Y(n3786) );
BUFX4TS U5211 ( .A(n3775), .Y(n3844) );
AOI22X1TS U5212 ( .A0(n3844), .A1(P_Sgf[52]), .B0(n3865), .B1(Add_result[0]),
.Y(n3785) );
OAI211XLTS U5213 ( .A0(n3783), .A1(n5406), .B0(n3786), .C0(n3785), .Y(n353)
);
INVX3TS U5214 ( .A(n4945), .Y(n4943) );
AOI22X1TS U5215 ( .A0(n841), .A1(n4943), .B0(n3871), .B1(Add_result[4]), .Y(
n3788) );
AOI22X1TS U5216 ( .A0(n3844), .A1(P_Sgf[55]), .B0(n3865), .B1(Add_result[3]),
.Y(n3787) );
OAI211XLTS U5217 ( .A0(n3783), .A1(n5403), .B0(n3788), .C0(n3787), .Y(n356)
);
AOI22X1TS U5218 ( .A0(Add_result[2]), .A1(n3871), .B0(
Sgf_normalized_result[1]), .B1(n3899), .Y(n3790) );
AOI22X1TS U5219 ( .A0(n3844), .A1(P_Sgf[53]), .B0(n3865), .B1(Add_result[1]),
.Y(n3789) );
OAI211XLTS U5220 ( .A0(n3783), .A1(n5405), .B0(n3790), .C0(n3789), .Y(n354)
);
AOI22X1TS U5221 ( .A0(Sgf_normalized_result[2]), .A1(n4943), .B0(n3871),
.B1(Add_result[3]), .Y(n3792) );
AOI22X1TS U5222 ( .A0(n3844), .A1(P_Sgf[54]), .B0(n3865), .B1(Add_result[2]),
.Y(n3791) );
OAI211XLTS U5223 ( .A0(n3783), .A1(n5404), .B0(n3792), .C0(n3791), .Y(n355)
);
AOI22X1TS U5224 ( .A0(Sgf_normalized_result[4]), .A1(n4943), .B0(n3871),
.B1(Add_result[5]), .Y(n3794) );
AOI22X1TS U5225 ( .A0(n3844), .A1(P_Sgf[56]), .B0(n3865), .B1(Add_result[4]),
.Y(n3793) );
OAI211XLTS U5226 ( .A0(n3783), .A1(n5402), .B0(n3794), .C0(n3793), .Y(n357)
);
AOI22X1TS U5227 ( .A0(Sgf_normalized_result[6]), .A1(n4943), .B0(n3871),
.B1(Add_result[7]), .Y(n3796) );
AOI22X1TS U5228 ( .A0(n3844), .A1(P_Sgf[58]), .B0(n3865), .B1(Add_result[6]),
.Y(n3795) );
OAI211XLTS U5229 ( .A0(n3783), .A1(n5400), .B0(n3796), .C0(n3795), .Y(n359)
);
AOI22X1TS U5230 ( .A0(Sgf_normalized_result[23]), .A1(n3883), .B0(
Add_result[24]), .B1(n3890), .Y(n3798) );
AOI22X1TS U5231 ( .A0(Add_result[23]), .A1(n736), .B0(n3844), .B1(P_Sgf[75]),
.Y(n3797) );
OAI211XLTS U5232 ( .A0(n3887), .A1(n5433), .B0(n3798), .C0(n3797), .Y(n376)
);
AOI22X1TS U5233 ( .A0(Sgf_normalized_result[7]), .A1(n4943), .B0(
Add_result[8]), .B1(n3871), .Y(n3800) );
AOI22X1TS U5234 ( .A0(n3844), .A1(P_Sgf[59]), .B0(n3865), .B1(Add_result[7]),
.Y(n3799) );
OAI211XLTS U5235 ( .A0(n3783), .A1(n5449), .B0(n3800), .C0(n3799), .Y(n360)
);
AOI22X1TS U5236 ( .A0(Sgf_normalized_result[5]), .A1(n4943), .B0(n3871),
.B1(Add_result[6]), .Y(n3802) );
AOI22X1TS U5237 ( .A0(n3844), .A1(P_Sgf[57]), .B0(n3865), .B1(Add_result[5]),
.Y(n3801) );
AOI22X1TS U5238 ( .A0(Sgf_normalized_result[42]), .A1(n3899), .B0(
Add_result[43]), .B1(n3890), .Y(n3804) );
AOI22X1TS U5239 ( .A0(Add_result[42]), .A1(n3865), .B0(n3866), .B1(P_Sgf[94]), .Y(n3803) );
OAI211XLTS U5240 ( .A0(n3876), .A1(n5414), .B0(n3804), .C0(n3803), .Y(n395)
);
AOI22X1TS U5241 ( .A0(Sgf_normalized_result[40]), .A1(n3899), .B0(
Add_result[41]), .B1(n3831), .Y(n3806) );
AOI22X1TS U5242 ( .A0(Add_result[40]), .A1(n3865), .B0(n3866), .B1(P_Sgf[92]), .Y(n3805) );
OAI211XLTS U5243 ( .A0(n3876), .A1(n5416), .B0(n3806), .C0(n3805), .Y(n393)
);
AOI22X1TS U5244 ( .A0(Sgf_normalized_result[50]), .A1(n3899), .B0(
Add_result[51]), .B1(n3890), .Y(n3808) );
AOI22X1TS U5245 ( .A0(Add_result[50]), .A1(n3865), .B0(n3866), .B1(
P_Sgf[102]), .Y(n3807) );
OAI211XLTS U5246 ( .A0(n5407), .A1(n3876), .B0(n3808), .C0(n3807), .Y(n403)
);
AOI22X1TS U5247 ( .A0(Sgf_normalized_result[48]), .A1(n3899), .B0(
Add_result[49]), .B1(n3831), .Y(n3810) );
AOI22X1TS U5248 ( .A0(Add_result[48]), .A1(n3865), .B0(n3866), .B1(
P_Sgf[100]), .Y(n3809) );
OAI211XLTS U5249 ( .A0(n3887), .A1(n5408), .B0(n3810), .C0(n3809), .Y(n401)
);
AOI22X1TS U5250 ( .A0(Sgf_normalized_result[44]), .A1(n3899), .B0(
Add_result[45]), .B1(n3890), .Y(n3812) );
AOI22X1TS U5251 ( .A0(Add_result[44]), .A1(n3865), .B0(n3866), .B1(P_Sgf[96]), .Y(n3811) );
OAI211XLTS U5252 ( .A0(n3876), .A1(n5412), .B0(n3812), .C0(n3811), .Y(n397)
);
AOI22X1TS U5253 ( .A0(Sgf_normalized_result[22]), .A1(n3883), .B0(
Add_result[23]), .B1(n3871), .Y(n3814) );
AOI22X1TS U5254 ( .A0(Add_result[22]), .A1(n3884), .B0(n3866), .B1(P_Sgf[74]), .Y(n3813) );
OAI211XLTS U5255 ( .A0(n3887), .A1(n5434), .B0(n3814), .C0(n3813), .Y(n375)
);
AOI22X1TS U5256 ( .A0(Sgf_normalized_result[10]), .A1(n4943), .B0(
Add_result[11]), .B1(n3871), .Y(n3816) );
AOI22X1TS U5257 ( .A0(Add_result[10]), .A1(n3884), .B0(n3844), .B1(P_Sgf[62]), .Y(n3815) );
OAI211XLTS U5258 ( .A0(n3783), .A1(n5446), .B0(n3816), .C0(n3815), .Y(n363)
);
AOI22X1TS U5259 ( .A0(Sgf_normalized_result[8]), .A1(n4943), .B0(
Add_result[9]), .B1(n3871), .Y(n3818) );
AOI22X1TS U5260 ( .A0(Add_result[8]), .A1(n3884), .B0(n3844), .B1(P_Sgf[60]),
.Y(n3817) );
OAI211XLTS U5261 ( .A0(n3783), .A1(n5448), .B0(n3818), .C0(n3817), .Y(n361)
);
AOI22X1TS U5262 ( .A0(Sgf_normalized_result[18]), .A1(n3883), .B0(
Add_result[19]), .B1(n3871), .Y(n3820) );
AOI22X1TS U5263 ( .A0(Add_result[18]), .A1(n3884), .B0(n3844), .B1(P_Sgf[70]), .Y(n3819) );
OAI211XLTS U5264 ( .A0(n3887), .A1(n5438), .B0(n3820), .C0(n3819), .Y(n371)
);
BUFX3TS U5265 ( .A(n3783), .Y(n3895) );
AOI22X1TS U5266 ( .A0(Sgf_normalized_result[24]), .A1(n3883), .B0(
Add_result[25]), .B1(n3871), .Y(n3822) );
AOI22X1TS U5267 ( .A0(Add_result[24]), .A1(n3884), .B0(n3844), .B1(P_Sgf[76]), .Y(n3821) );
OAI211XLTS U5268 ( .A0(n3895), .A1(n5432), .B0(n3822), .C0(n3821), .Y(n377)
);
AOI22X1TS U5269 ( .A0(Sgf_normalized_result[12]), .A1(n3891), .B0(
Add_result[13]), .B1(n3871), .Y(n3824) );
AOI22X1TS U5270 ( .A0(Add_result[12]), .A1(n3884), .B0(n3844), .B1(P_Sgf[64]), .Y(n3823) );
OAI211XLTS U5271 ( .A0(n3887), .A1(n5444), .B0(n3824), .C0(n3823), .Y(n365)
);
AOI22X1TS U5272 ( .A0(Sgf_normalized_result[16]), .A1(n3883), .B0(
Add_result[17]), .B1(n3871), .Y(n3826) );
AOI22X1TS U5273 ( .A0(Add_result[16]), .A1(n3884), .B0(n3866), .B1(P_Sgf[68]), .Y(n3825) );
OAI211XLTS U5274 ( .A0(n3887), .A1(n5440), .B0(n3826), .C0(n3825), .Y(n369)
);
AOI22X1TS U5275 ( .A0(Sgf_normalized_result[49]), .A1(n3899), .B0(
Add_result[50]), .B1(n3890), .Y(n3828) );
AOI22X1TS U5276 ( .A0(Add_result[49]), .A1(n3865), .B0(n3866), .B1(
P_Sgf[101]), .Y(n3827) );
OAI211XLTS U5277 ( .A0(n5399), .A1(n3895), .B0(n3828), .C0(n3827), .Y(n402)
);
AOI22X1TS U5278 ( .A0(Sgf_normalized_result[45]), .A1(n3899), .B0(
Add_result[46]), .B1(n3831), .Y(n3830) );
AOI22X1TS U5279 ( .A0(Add_result[45]), .A1(n3865), .B0(n3866), .B1(P_Sgf[97]), .Y(n3829) );
OAI211XLTS U5280 ( .A0(n3876), .A1(n5411), .B0(n3830), .C0(n3829), .Y(n398)
);
AOI22X1TS U5281 ( .A0(Sgf_normalized_result[47]), .A1(n3899), .B0(
Add_result[48]), .B1(n3831), .Y(n3833) );
AOI22X1TS U5282 ( .A0(Add_result[47]), .A1(n3865), .B0(n3866), .B1(P_Sgf[99]), .Y(n3832) );
OAI211XLTS U5283 ( .A0(n3876), .A1(n5409), .B0(n3833), .C0(n3832), .Y(n400)
);
AOI22X1TS U5284 ( .A0(Sgf_normalized_result[43]), .A1(n3899), .B0(
Add_result[44]), .B1(n3890), .Y(n3835) );
AOI22X1TS U5285 ( .A0(Add_result[43]), .A1(n3865), .B0(n3866), .B1(P_Sgf[95]), .Y(n3834) );
OAI211XLTS U5286 ( .A0(n3876), .A1(n5413), .B0(n3835), .C0(n3834), .Y(n396)
);
AOI22X1TS U5287 ( .A0(Sgf_normalized_result[9]), .A1(n4943), .B0(
Add_result[10]), .B1(n3871), .Y(n3837) );
AOI22X1TS U5288 ( .A0(Add_result[9]), .A1(n3884), .B0(n3844), .B1(P_Sgf[61]),
.Y(n3836) );
OAI211XLTS U5289 ( .A0(n3783), .A1(n5447), .B0(n3837), .C0(n3836), .Y(n362)
);
AOI22X1TS U5290 ( .A0(Sgf_normalized_result[39]), .A1(n3891), .B0(
Add_result[40]), .B1(n3890), .Y(n3839) );
AOI22X1TS U5291 ( .A0(Add_result[39]), .A1(n3884), .B0(n3866), .B1(P_Sgf[91]), .Y(n3838) );
OAI211XLTS U5292 ( .A0(n3876), .A1(n5417), .B0(n3839), .C0(n3838), .Y(n392)
);
AOI22X1TS U5293 ( .A0(Sgf_normalized_result[15]), .A1(n3883), .B0(
Add_result[16]), .B1(n3871), .Y(n3841) );
AOI22X1TS U5294 ( .A0(Add_result[15]), .A1(n3884), .B0(n3866), .B1(P_Sgf[67]), .Y(n3840) );
OAI211XLTS U5295 ( .A0(n3887), .A1(n5441), .B0(n3841), .C0(n3840), .Y(n368)
);
AOI22X1TS U5296 ( .A0(Sgf_normalized_result[11]), .A1(n4943), .B0(
Add_result[12]), .B1(n3871), .Y(n3843) );
AOI22X1TS U5297 ( .A0(Add_result[11]), .A1(n3884), .B0(n3844), .B1(P_Sgf[63]), .Y(n3842) );
OAI211XLTS U5298 ( .A0(n3783), .A1(n5445), .B0(n3843), .C0(n3842), .Y(n364)
);
AOI22X1TS U5299 ( .A0(Sgf_normalized_result[17]), .A1(n3883), .B0(
Add_result[18]), .B1(n3890), .Y(n3846) );
AOI22X1TS U5300 ( .A0(Add_result[17]), .A1(n3884), .B0(n3844), .B1(P_Sgf[69]), .Y(n3845) );
OAI211XLTS U5301 ( .A0(n3887), .A1(n5439), .B0(n3846), .C0(n3845), .Y(n370)
);
AOI22X1TS U5302 ( .A0(Sgf_normalized_result[30]), .A1(n3891), .B0(
Add_result[31]), .B1(n3890), .Y(n3848) );
BUFX4TS U5303 ( .A(n3775), .Y(n3892) );
AOI22X1TS U5304 ( .A0(Add_result[30]), .A1(n3884), .B0(n3892), .B1(P_Sgf[82]), .Y(n3847) );
OAI211XLTS U5305 ( .A0(n3895), .A1(n5426), .B0(n3848), .C0(n3847), .Y(n383)
);
AOI22X1TS U5306 ( .A0(Sgf_normalized_result[28]), .A1(n3891), .B0(
Add_result[29]), .B1(n3890), .Y(n3850) );
AOI22X1TS U5307 ( .A0(Add_result[28]), .A1(n3884), .B0(n3892), .B1(P_Sgf[80]), .Y(n3849) );
OAI211XLTS U5308 ( .A0(n3895), .A1(n5428), .B0(n3850), .C0(n3849), .Y(n381)
);
AOI22X1TS U5309 ( .A0(Sgf_normalized_result[36]), .A1(n3891), .B0(
Add_result[37]), .B1(n3890), .Y(n3852) );
AOI22X1TS U5310 ( .A0(Add_result[36]), .A1(n3865), .B0(n3892), .B1(P_Sgf[88]), .Y(n3851) );
OAI211XLTS U5311 ( .A0(n3876), .A1(n5420), .B0(n3852), .C0(n3851), .Y(n389)
);
AOI22X1TS U5312 ( .A0(Sgf_normalized_result[32]), .A1(n3891), .B0(
Add_result[33]), .B1(n3890), .Y(n3854) );
AOI22X1TS U5313 ( .A0(Add_result[32]), .A1(n3884), .B0(n3892), .B1(P_Sgf[84]), .Y(n3853) );
OAI211XLTS U5314 ( .A0(n3895), .A1(n5424), .B0(n3854), .C0(n3853), .Y(n385)
);
AOI22X1TS U5315 ( .A0(Sgf_normalized_result[34]), .A1(n3891), .B0(
Add_result[35]), .B1(n3890), .Y(n3856) );
AOI22X1TS U5316 ( .A0(Add_result[34]), .A1(n3865), .B0(n3892), .B1(P_Sgf[86]), .Y(n3855) );
OAI211XLTS U5317 ( .A0(n3895), .A1(n5422), .B0(n3856), .C0(n3855), .Y(n387)
);
AOI22X1TS U5318 ( .A0(Sgf_normalized_result[38]), .A1(n3891), .B0(
Add_result[39]), .B1(n3890), .Y(n3858) );
AOI22X1TS U5319 ( .A0(Add_result[38]), .A1(n3865), .B0(n3892), .B1(P_Sgf[90]), .Y(n3857) );
AOI22X1TS U5320 ( .A0(Sgf_normalized_result[20]), .A1(n3883), .B0(
Add_result[21]), .B1(n3871), .Y(n3860) );
AOI22X1TS U5321 ( .A0(Add_result[20]), .A1(n3884), .B0(n3892), .B1(P_Sgf[72]), .Y(n3859) );
OAI211XLTS U5322 ( .A0(n3887), .A1(n5436), .B0(n3860), .C0(n3859), .Y(n373)
);
AOI22X1TS U5323 ( .A0(Sgf_normalized_result[26]), .A1(n3883), .B0(
Add_result[27]), .B1(n3890), .Y(n3862) );
AOI22X1TS U5324 ( .A0(Add_result[26]), .A1(n3884), .B0(n3892), .B1(P_Sgf[78]), .Y(n3861) );
OAI211XLTS U5325 ( .A0(n3895), .A1(n5430), .B0(n3862), .C0(n3861), .Y(n379)
);
AOI22X1TS U5326 ( .A0(Sgf_normalized_result[14]), .A1(n4943), .B0(
Add_result[15]), .B1(n3871), .Y(n3864) );
AOI22X1TS U5327 ( .A0(Add_result[14]), .A1(n3884), .B0(n3892), .B1(P_Sgf[66]), .Y(n3863) );
OAI211XLTS U5328 ( .A0(n3887), .A1(n5442), .B0(n3864), .C0(n3863), .Y(n367)
);
AOI22X1TS U5329 ( .A0(FSM_selector_C), .A1(Add_result[52]), .B0(P_Sgf[104]),
.B1(n5362), .Y(n4944) );
AOI22X1TS U5330 ( .A0(Sgf_normalized_result[51]), .A1(n3899), .B0(
Add_result[51]), .B1(n3865), .Y(n3868) );
NAND2X1TS U5331 ( .A(n3866), .B(P_Sgf[103]), .Y(n3867) );
OAI211XLTS U5332 ( .A0(n4946), .A1(n4944), .B0(n3868), .C0(n3867), .Y(n404)
);
AOI22X1TS U5333 ( .A0(Sgf_normalized_result[31]), .A1(n3891), .B0(
Add_result[32]), .B1(n3890), .Y(n3870) );
AOI22X1TS U5334 ( .A0(Add_result[31]), .A1(n3884), .B0(n3892), .B1(P_Sgf[83]), .Y(n3869) );
OAI211XLTS U5335 ( .A0(n3895), .A1(n5425), .B0(n3870), .C0(n3869), .Y(n384)
);
AOI22X1TS U5336 ( .A0(Sgf_normalized_result[13]), .A1(n4943), .B0(
Add_result[14]), .B1(n3871), .Y(n3873) );
AOI22X1TS U5337 ( .A0(Add_result[13]), .A1(n3884), .B0(n3892), .B1(P_Sgf[65]), .Y(n3872) );
OAI211XLTS U5338 ( .A0(n3887), .A1(n5443), .B0(n3873), .C0(n3872), .Y(n366)
);
AOI22X1TS U5339 ( .A0(Sgf_normalized_result[37]), .A1(n3891), .B0(
Add_result[38]), .B1(n3890), .Y(n3875) );
AOI22X1TS U5340 ( .A0(Add_result[37]), .A1(n736), .B0(n3892), .B1(P_Sgf[89]),
.Y(n3874) );
OAI211XLTS U5341 ( .A0(n3876), .A1(n5419), .B0(n3875), .C0(n3874), .Y(n390)
);
AOI22X1TS U5342 ( .A0(Sgf_normalized_result[29]), .A1(n3891), .B0(
Add_result[30]), .B1(n3890), .Y(n3878) );
AOI22X1TS U5343 ( .A0(Add_result[29]), .A1(n736), .B0(n3892), .B1(P_Sgf[81]),
.Y(n3877) );
OAI211XLTS U5344 ( .A0(n3895), .A1(n5427), .B0(n3878), .C0(n3877), .Y(n382)
);
AOI22X1TS U5345 ( .A0(Sgf_normalized_result[27]), .A1(n3883), .B0(
Add_result[28]), .B1(n3890), .Y(n3880) );
AOI22X1TS U5346 ( .A0(Add_result[27]), .A1(n736), .B0(n3892), .B1(P_Sgf[79]),
.Y(n3879) );
OAI211XLTS U5347 ( .A0(n3895), .A1(n5429), .B0(n3880), .C0(n3879), .Y(n380)
);
AOI22X1TS U5348 ( .A0(Sgf_normalized_result[25]), .A1(n3883), .B0(
Add_result[26]), .B1(n3890), .Y(n3882) );
AOI22X1TS U5349 ( .A0(Add_result[25]), .A1(n736), .B0(n3892), .B1(P_Sgf[77]),
.Y(n3881) );
OAI211XLTS U5350 ( .A0(n3895), .A1(n5431), .B0(n3882), .C0(n3881), .Y(n378)
);
AOI22X1TS U5351 ( .A0(Sgf_normalized_result[19]), .A1(n3883), .B0(
Add_result[20]), .B1(n3890), .Y(n3886) );
AOI22X1TS U5352 ( .A0(Add_result[19]), .A1(n3884), .B0(n3892), .B1(P_Sgf[71]), .Y(n3885) );
OAI211XLTS U5353 ( .A0(n3887), .A1(n5437), .B0(n3886), .C0(n3885), .Y(n372)
);
AOI22X1TS U5354 ( .A0(Sgf_normalized_result[35]), .A1(n3891), .B0(
Add_result[36]), .B1(n3890), .Y(n3889) );
AOI22X1TS U5355 ( .A0(Add_result[35]), .A1(n736), .B0(n3892), .B1(P_Sgf[87]),
.Y(n3888) );
AOI22X1TS U5356 ( .A0(Sgf_normalized_result[33]), .A1(n3891), .B0(
Add_result[34]), .B1(n3890), .Y(n3894) );
AOI22X1TS U5357 ( .A0(Add_result[33]), .A1(n736), .B0(n3892), .B1(P_Sgf[85]),
.Y(n3893) );
OAI211XLTS U5358 ( .A0(n3895), .A1(n5423), .B0(n3894), .C0(n3893), .Y(n386)
);
BUFX6TS U5359 ( .A(n4844), .Y(n4659) );
NOR2X1TS U5360 ( .A(n4659), .B(n5357), .Y(mult_x_24_n603) );
NAND3XLTS U5361 ( .A(n3897), .B(n5360), .C(n3896), .Y(n3898) );
INVX2TS U5362 ( .A(n3898), .Y(ready) );
INVX2TS U5363 ( .A(mult_x_24_n256), .Y(mult_x_24_n610) );
INVX2TS U5364 ( .A(mult_x_24_n249), .Y(mult_x_24_n609) );
NOR2X1TS U5365 ( .A(n4844), .B(n5355), .Y(mult_x_24_n608) );
INVX2TS U5366 ( .A(DP_OP_36J45_124_1029_n42), .Y(n4870) );
OAI21XLTS U5367 ( .A0(n5359), .A1(n4873), .B0(FS_Module_state_reg[3]), .Y(
n3900) );
OAI211XLTS U5368 ( .A0(n5396), .A1(n4870), .B0(n3900), .C0(n3899), .Y(n714)
);
INVX2TS U5369 ( .A(mult_x_24_n311), .Y(mult_x_24_n616) );
INVX2TS U5370 ( .A(mult_x_24_n301), .Y(mult_x_24_n615) );
NOR2X1TS U5371 ( .A(n4844), .B(n5351), .Y(mult_x_24_n614) );
NOR2X1TS U5372 ( .A(n4665), .B(n3901), .Y(n4661) );
OAI22X1TS U5373 ( .A0(n740), .A1(n4068), .B0(DP_OP_169J45_123_4229_n86),
.B1(n3933), .Y(n3904) );
OAI22X1TS U5374 ( .A0(n5358), .A1(n4640), .B0(n4845), .B1(n4081), .Y(n3903)
);
OAI21XLTS U5375 ( .A0(n3904), .A1(n3903), .B0(n4844), .Y(n3902) );
OAI31X1TS U5376 ( .A0(n3904), .A1(n4659), .A2(n3903), .B0(n3902), .Y(
mult_x_24_n710) );
OAI22X1TS U5377 ( .A0(n740), .A1(n4080), .B0(n4845), .B1(n5357), .Y(n3907)
);
OAI22X1TS U5378 ( .A0(n4655), .A1(n5354), .B0(n4081), .B1(n3933), .Y(n3906)
);
OAI21XLTS U5379 ( .A0(n3907), .A1(n3906), .B0(n4656), .Y(n3905) );
OAI31X1TS U5380 ( .A0(n3907), .A1(n4659), .A2(n3906), .B0(n3905), .Y(
mult_x_24_n712) );
OAI22X1TS U5381 ( .A0(n740), .A1(n4334), .B0(n4845), .B1(n4434), .Y(n3910)
);
OAI22X1TS U5382 ( .A0(n5358), .A1(n3933), .B0(n4640), .B1(n4081), .Y(n3909)
);
OAI21XLTS U5383 ( .A0(n3910), .A1(n3909), .B0(n4659), .Y(n3908) );
OAI31X1TS U5384 ( .A0(n3910), .A1(n4659), .A2(n3909), .B0(n3908), .Y(
mult_x_24_n711) );
NOR2X1TS U5385 ( .A(n4844), .B(n4508), .Y(mult_x_24_n620) );
OAI22X1TS U5386 ( .A0(n740), .A1(n4424), .B0(n4640), .B1(n5356), .Y(n3913)
);
OAI22X1TS U5387 ( .A0(n4845), .A1(n4415), .B0(n3933), .B1(n4607), .Y(n3912)
);
OAI31X1TS U5388 ( .A0(n3913), .A1(n4659), .A2(n3912), .B0(n3911), .Y(
mult_x_24_n716) );
INVX2TS U5389 ( .A(n730), .Y(n4125) );
BUFX6TS U5390 ( .A(n4125), .Y(n4702) );
AOI2BB2X2TS U5391 ( .B0(Op_MX[21]), .B1(n4702), .A0N(n4125), .A1N(Op_MX[21]),
.Y(n4062) );
NOR2X1TS U5392 ( .A(n4062), .B(n3916), .Y(n4059) );
INVX2TS U5393 ( .A(n4062), .Y(n3914) );
OAI22X1TS U5394 ( .A0(DP_OP_169J45_123_4229_n86), .A1(n4097), .B0(n4068),
.B1(n739), .Y(n3920) );
XNOR2X1TS U5395 ( .A(Op_MX[22]), .B(Op_MX[21]), .Y(n3915) );
NOR2X1TS U5396 ( .A(n3915), .B(n3914), .Y(n4058) );
INVX2TS U5397 ( .A(n4058), .Y(n4803) );
BUFX3TS U5398 ( .A(n3917), .Y(n4680) );
BUFX4TS U5399 ( .A(n4680), .Y(n4804) );
OAI22X1TS U5400 ( .A0(n5358), .A1(n4803), .B0(n4081), .B1(n4804), .Y(n3919)
);
OAI21XLTS U5401 ( .A0(n3920), .A1(n3919), .B0(n4674), .Y(n3918) );
OAI31X1TS U5402 ( .A0(n3920), .A1(n5451), .A2(n3919), .B0(n3918), .Y(
mult_x_24_n740) );
NOR2X1TS U5403 ( .A(n4844), .B(n5343), .Y(mult_x_24_n621) );
OAI22X1TS U5404 ( .A0(n740), .A1(n4414), .B0(n4640), .B1(n5355), .Y(n3923)
);
OAI22X1TS U5405 ( .A0(n4845), .A1(n4438), .B0(n3933), .B1(n5377), .Y(n3922)
);
OAI31X1TS U5406 ( .A0(n3923), .A1(n4659), .A2(n3922), .B0(n3921), .Y(
mult_x_24_n718) );
OAI22X1TS U5407 ( .A0(n740), .A1(n4419), .B0(n4845), .B1(n5355), .Y(n3926)
);
OAI22X1TS U5408 ( .A0(n4655), .A1(n4415), .B0(n3933), .B1(n5356), .Y(n3925)
);
OAI31X1TS U5409 ( .A0(n3926), .A1(n4659), .A2(n3925), .B0(n3924), .Y(
mult_x_24_n717) );
NOR2X1TS U5410 ( .A(n4844), .B(n4781), .Y(mult_x_24_n622) );
OAI22X1TS U5411 ( .A0(n5357), .A1(n4804), .B0(n4080), .B1(n739), .Y(n3929)
);
BUFX4TS U5412 ( .A(n4803), .Y(n4681) );
OAI22X1TS U5413 ( .A0(n4081), .A1(n4097), .B0(n5354), .B1(n4681), .Y(n3928)
);
OAI21XLTS U5414 ( .A0(n3929), .A1(n3928), .B0(n4674), .Y(n3927) );
OAI31X1TS U5415 ( .A0(n3929), .A1(n5451), .A2(n3928), .B0(n3927), .Y(
mult_x_24_n742) );
OAI22X1TS U5416 ( .A0(n4434), .A1(n4680), .B0(n4334), .B1(n739), .Y(n3932)
);
OAI22X1TS U5417 ( .A0(n5358), .A1(n4097), .B0(n4081), .B1(n4681), .Y(n3931)
);
OAI21XLTS U5418 ( .A0(n3932), .A1(n3931), .B0(n4674), .Y(n3930) );
OAI31X1TS U5419 ( .A0(n3932), .A1(n5451), .A2(n3931), .B0(n3930), .Y(
mult_x_24_n741) );
OAI22X1TS U5420 ( .A0(n740), .A1(n4452), .B0(n4640), .B1(n5352), .Y(n3936)
);
OAI22X1TS U5421 ( .A0(n4845), .A1(n4459), .B0(n3933), .B1(n4621), .Y(n3935)
);
OAI31X1TS U5422 ( .A0(n3936), .A1(n4659), .A2(n3935), .B0(n3934), .Y(
mult_x_24_n722) );
NOR2X1TS U5423 ( .A(n4844), .B(n4772), .Y(mult_x_24_n623) );
OAI22X1TS U5424 ( .A0(n5356), .A1(n4804), .B0(n4611), .B1(n739), .Y(n3939)
);
OAI22X1TS U5425 ( .A0(n4429), .A1(n4097), .B0(n5353), .B1(n4681), .Y(n3938)
);
OAI31X1TS U5426 ( .A0(n3939), .A1(n4682), .A2(n3938), .B0(n3937), .Y(
mult_x_24_n745) );
OAI22X1TS U5427 ( .A0(n5356), .A1(n4803), .B0(n4424), .B1(n739), .Y(n3942)
);
OAI22X1TS U5428 ( .A0(n4607), .A1(n4097), .B0(n4415), .B1(n4804), .Y(n3941)
);
OAI31X1TS U5429 ( .A0(n3942), .A1(n4682), .A2(n3941), .B0(n3940), .Y(
mult_x_24_n746) );
OAI22X1TS U5430 ( .A0(n740), .A1(n4457), .B0(n4640), .B1(n5351), .Y(n3945)
);
OAI22X1TS U5431 ( .A0(n4845), .A1(n4471), .B0(n3933), .B1(n5372), .Y(n3944)
);
OAI31X1TS U5432 ( .A0(n3945), .A1(n4103), .A2(n3944), .B0(n3943), .Y(
mult_x_24_n724) );
AOI2BB2X2TS U5433 ( .B0(Op_MX[18]), .B1(n959), .A0N(n4174), .A1N(Op_MX[18]),
.Y(n4708) );
BUFX6TS U5434 ( .A(n4125), .Y(n4699) );
NOR2X1TS U5435 ( .A(n4708), .B(n3948), .Y(n4705) );
INVX2TS U5436 ( .A(n4708), .Y(n3946) );
OAI22X1TS U5437 ( .A0(DP_OP_169J45_123_4229_n86), .A1(n4697), .B0(n4068),
.B1(n742), .Y(n3952) );
XNOR2X1TS U5438 ( .A(Op_MX[19]), .B(Op_MX[18]), .Y(n3947) );
NOR2X1TS U5439 ( .A(n3947), .B(n3946), .Y(n4704) );
INVX2TS U5440 ( .A(n4704), .Y(n4809) );
BUFX3TS U5441 ( .A(n3949), .Y(n4696) );
BUFX4TS U5442 ( .A(n4696), .Y(n4810) );
OAI22X1TS U5443 ( .A0(n5358), .A1(n4809), .B0(n949), .B1(n4810), .Y(n3951)
);
OAI31X1TS U5444 ( .A0(n3952), .A1(n4702), .A2(n3951), .B0(n3950), .Y(
mult_x_24_n770) );
NOR2X1TS U5445 ( .A(n4844), .B(n4779), .Y(mult_x_24_n624) );
OAI22X1TS U5446 ( .A0(n5357), .A1(n4810), .B0(n4080), .B1(n742), .Y(n3955)
);
BUFX4TS U5447 ( .A(n4809), .Y(n4698) );
OAI22X1TS U5448 ( .A0(n4081), .A1(n4697), .B0(n5354), .B1(n4698), .Y(n3954)
);
OAI31X1TS U5449 ( .A0(n3955), .A1(n4125), .A2(n3954), .B0(n3953), .Y(
mult_x_24_n772) );
OAI22X1TS U5450 ( .A0(n4434), .A1(n4696), .B0(n4334), .B1(n742), .Y(n3958)
);
OAI22X1TS U5451 ( .A0(n5358), .A1(n4697), .B0(n4081), .B1(n4698), .Y(n3957)
);
OAI31X1TS U5452 ( .A0(n3958), .A1(n4125), .A2(n3957), .B0(n3956), .Y(
mult_x_24_n771) );
NOR2X1TS U5453 ( .A(n4844), .B(n4755), .Y(mult_x_24_n625) );
OAI22X1TS U5454 ( .A0(n5352), .A1(n4680), .B0(n4629), .B1(n739), .Y(n3961)
);
OAI22X1TS U5455 ( .A0(n4630), .A1(n4097), .B0(n5349), .B1(n4681), .Y(n3960)
);
OAI31X1TS U5456 ( .A0(n3961), .A1(n5451), .A2(n3960), .B0(n3959), .Y(
mult_x_24_n751) );
OAI22X1TS U5457 ( .A0(n5352), .A1(n4803), .B0(n4452), .B1(n739), .Y(n3964)
);
OAI22X1TS U5458 ( .A0(n4621), .A1(n4097), .B0(n4459), .B1(n4804), .Y(n3963)
);
OAI31X1TS U5459 ( .A0(n3964), .A1(n5451), .A2(n3963), .B0(n3962), .Y(
mult_x_24_n752) );
OAI22X1TS U5460 ( .A0(n5356), .A1(n4810), .B0(n4611), .B1(n742), .Y(n3967)
);
OAI22X1TS U5461 ( .A0(n4429), .A1(n4697), .B0(n5353), .B1(n4698), .Y(n3966)
);
OAI31X1TS U5462 ( .A0(n3967), .A1(n4699), .A2(n3966), .B0(n3965), .Y(
mult_x_24_n775) );
OAI22X1TS U5463 ( .A0(n5356), .A1(n4809), .B0(n4424), .B1(n742), .Y(n3970)
);
OAI22X1TS U5464 ( .A0(n4607), .A1(n4697), .B0(n5377), .B1(n4810), .Y(n3969)
);
OAI31X1TS U5465 ( .A0(n3970), .A1(n4125), .A2(n3969), .B0(n3968), .Y(
mult_x_24_n776) );
BUFX6TS U5466 ( .A(n4194), .Y(n4747) );
AOI2BB2X2TS U5467 ( .B0(Op_MX[15]), .B1(n4747), .A0N(n4194), .A1N(Op_MX[15]),
.Y(n4076) );
BUFX6TS U5468 ( .A(n4174), .Y(n4726) );
NOR2X1TS U5469 ( .A(n4076), .B(n3973), .Y(n4073) );
INVX2TS U5470 ( .A(n4076), .Y(n3971) );
OAI22X1TS U5471 ( .A0(DP_OP_169J45_123_4229_n86), .A1(n4725), .B0(n4068),
.B1(n735), .Y(n3977) );
XNOR2X1TS U5472 ( .A(Op_MX[16]), .B(Op_MX[15]), .Y(n3972) );
NOR2X1TS U5473 ( .A(n3972), .B(n3971), .Y(n4072) );
BUFX3TS U5474 ( .A(n3978), .Y(n4815) );
BUFX3TS U5475 ( .A(n3974), .Y(n4724) );
BUFX4TS U5476 ( .A(n4724), .Y(n4816) );
OAI22X1TS U5477 ( .A0(n5358), .A1(n4815), .B0(n4081), .B1(n4816), .Y(n3976)
);
OAI31X1TS U5478 ( .A0(n3977), .A1(n4174), .A2(n3976), .B0(n3975), .Y(
mult_x_24_n800) );
OAI22X1TS U5479 ( .A0(n5357), .A1(n4816), .B0(n4080), .B1(n735), .Y(n3981)
);
OAI22X1TS U5480 ( .A0(n4081), .A1(n4725), .B0(n5354), .B1(n3978), .Y(n3980)
);
OAI31X1TS U5481 ( .A0(n3981), .A1(n4726), .A2(n3980), .B0(n3979), .Y(
mult_x_24_n802) );
OAI22X1TS U5482 ( .A0(n4434), .A1(n4724), .B0(n4334), .B1(n735), .Y(n3984)
);
OAI22X1TS U5483 ( .A0(n5358), .A1(n4725), .B0(n3488), .B1(n3978), .Y(n3983)
);
OAI31X1TS U5484 ( .A0(n3984), .A1(n4174), .A2(n3983), .B0(n3982), .Y(
mult_x_24_n801) );
OAI22X1TS U5485 ( .A0(n740), .A1(n4490), .B0(n4655), .B1(n5350), .Y(n3987)
);
OAI22X1TS U5486 ( .A0(n4845), .A1(n4509), .B0(n3933), .B1(n4638), .Y(n3986)
);
OAI31X1TS U5487 ( .A0(n3987), .A1(n4659), .A2(n3986), .B0(n3985), .Y(
mult_x_24_n728) );
OAI22X1TS U5488 ( .A0(n5352), .A1(n4696), .B0(n4629), .B1(n742), .Y(n3990)
);
OAI22X1TS U5489 ( .A0(n4630), .A1(n4697), .B0(n5349), .B1(n4698), .Y(n3989)
);
OAI31X1TS U5490 ( .A0(n3990), .A1(n4702), .A2(n3989), .B0(n3988), .Y(
mult_x_24_n781) );
OAI22X1TS U5491 ( .A0(n5352), .A1(n4809), .B0(n4452), .B1(n742), .Y(n3993)
);
OAI22X1TS U5492 ( .A0(n4621), .A1(n4697), .B0(n5372), .B1(n4810), .Y(n3992)
);
OAI31X1TS U5493 ( .A0(n3993), .A1(n4702), .A2(n3992), .B0(n3991), .Y(
mult_x_24_n782) );
OAI22X1TS U5494 ( .A0(n5356), .A1(n4816), .B0(n4611), .B1(n735), .Y(n3996)
);
OAI22X1TS U5495 ( .A0(n4429), .A1(n4725), .B0(n5353), .B1(n3978), .Y(n3995)
);
OAI31X1TS U5496 ( .A0(n3996), .A1(n4726), .A2(n3995), .B0(n3994), .Y(
mult_x_24_n805) );
OAI22X1TS U5497 ( .A0(n5356), .A1(n4815), .B0(n4424), .B1(n735), .Y(n3999)
);
OAI22X1TS U5498 ( .A0(n4607), .A1(n4725), .B0(n4415), .B1(n4816), .Y(n3998)
);
OAI31X1TS U5499 ( .A0(n3999), .A1(n4726), .A2(n3998), .B0(n3997), .Y(
mult_x_24_n806) );
OAI22X1TS U5500 ( .A0(n740), .A1(n4497), .B0(n4654), .B1(n4508), .Y(n4002)
);
OAI22X1TS U5501 ( .A0(n4655), .A1(n4509), .B0(n3933), .B1(n5350), .Y(n4001)
);
OAI31X1TS U5502 ( .A0(n4002), .A1(n4659), .A2(n4001), .B0(n4000), .Y(
mult_x_24_n729) );
AOI2BB2X2TS U5503 ( .B0(Op_MX[12]), .B1(n5452), .A0N(n4278), .A1N(Op_MX[12]),
.Y(n4754) );
BUFX6TS U5504 ( .A(n4194), .Y(n4744) );
NOR2X1TS U5505 ( .A(n4754), .B(n4005), .Y(n4751) );
INVX2TS U5506 ( .A(n4754), .Y(n4003) );
OAI22X1TS U5507 ( .A0(DP_OP_169J45_123_4229_n86), .A1(n4400), .B0(n4068),
.B1(n737), .Y(n4009) );
XNOR2X1TS U5508 ( .A(Op_MX[13]), .B(Op_MX[12]), .Y(n4004) );
NOR2X1TS U5509 ( .A(n4004), .B(n4003), .Y(n4750) );
BUFX3TS U5510 ( .A(n4013), .Y(n4821) );
BUFX3TS U5511 ( .A(n4006), .Y(n4743) );
BUFX4TS U5512 ( .A(n4743), .Y(n4822) );
OAI22X1TS U5513 ( .A0(n5358), .A1(n4821), .B0(n3488), .B1(n4822), .Y(n4008)
);
OAI31X1TS U5514 ( .A0(n4009), .A1(n4747), .A2(n4008), .B0(n4007), .Y(
mult_x_24_n830) );
OAI22X1TS U5515 ( .A0(n740), .A1(n4505), .B0(n4654), .B1(n5343), .Y(n4012)
);
OAI22X1TS U5516 ( .A0(n4655), .A1(n4508), .B0(n3933), .B1(n5369), .Y(n4011)
);
OAI31X1TS U5517 ( .A0(n4012), .A1(n4659), .A2(n4011), .B0(n4010), .Y(
mult_x_24_n730) );
OAI22X1TS U5518 ( .A0(n5357), .A1(n4822), .B0(n4080), .B1(n737), .Y(n4016)
);
OAI22X1TS U5519 ( .A0(n4081), .A1(n4400), .B0(n5354), .B1(n4013), .Y(n4015)
);
OAI31X1TS U5520 ( .A0(n4016), .A1(n4194), .A2(n4015), .B0(n4014), .Y(
mult_x_24_n832) );
OAI22X1TS U5521 ( .A0(n5350), .A1(n4681), .B0(n4490), .B1(n739), .Y(n4019)
);
OAI22X1TS U5522 ( .A0(n4638), .A1(n4097), .B0(n4509), .B1(n4804), .Y(n4018)
);
OAI31X1TS U5523 ( .A0(n4019), .A1(n5451), .A2(n4018), .B0(n4017), .Y(
mult_x_24_n758) );
OAI22X1TS U5524 ( .A0(n4434), .A1(n4743), .B0(n4334), .B1(n737), .Y(n4022)
);
OAI22X1TS U5525 ( .A0(n4835), .A1(n4400), .B0(n3488), .B1(n4013), .Y(n4021)
);
OAI31X1TS U5526 ( .A0(n4022), .A1(n4194), .A2(n4021), .B0(n4020), .Y(
mult_x_24_n831) );
OAI22X1TS U5527 ( .A0(n5352), .A1(n4815), .B0(n4452), .B1(n735), .Y(n4025)
);
OAI22X1TS U5528 ( .A0(n4621), .A1(n4725), .B0(n4459), .B1(n4816), .Y(n4024)
);
OAI31X1TS U5529 ( .A0(n4025), .A1(n959), .A2(n4024), .B0(n4023), .Y(
mult_x_24_n812) );
OAI22X1TS U5530 ( .A0(n5356), .A1(n4822), .B0(n4611), .B1(n737), .Y(n4028)
);
OAI22X1TS U5531 ( .A0(n4429), .A1(n4400), .B0(n5353), .B1(n4013), .Y(n4027)
);
OAI31X1TS U5532 ( .A0(n4028), .A1(n4744), .A2(n4027), .B0(n4026), .Y(
mult_x_24_n835) );
OAI22X1TS U5533 ( .A0(n5356), .A1(n4821), .B0(n4424), .B1(n737), .Y(n4031)
);
OAI22X1TS U5534 ( .A0(n4607), .A1(n4400), .B0(n5377), .B1(n4822), .Y(n4030)
);
OAI31X1TS U5535 ( .A0(n4031), .A1(n4194), .A2(n4030), .B0(n4029), .Y(
mult_x_24_n836) );
OAI22X1TS U5536 ( .A0(n852), .A1(n4773), .B0(n4068), .B1(n738), .Y(n4040) );
BUFX3TS U5537 ( .A(n4041), .Y(n4827) );
BUFX4TS U5538 ( .A(n4778), .Y(n4828) );
OAI22X1TS U5539 ( .A0(n4835), .A1(n4827), .B0(n3488), .B1(n4828), .Y(n4039)
);
OAI31X1TS U5540 ( .A0(n4040), .A1(n5452), .A2(n4039), .B0(n4038), .Y(
mult_x_24_n860) );
OAI22X1TS U5541 ( .A0(n4444), .A1(n4828), .B0(n4080), .B1(n738), .Y(n4044)
);
OAI22X1TS U5542 ( .A0(n4081), .A1(n4773), .B0(n5354), .B1(n4041), .Y(n4043)
);
OAI31X1TS U5543 ( .A0(n4044), .A1(n4278), .A2(n4043), .B0(n4042), .Y(
mult_x_24_n862) );
OAI22X1TS U5544 ( .A0(n4434), .A1(n4778), .B0(n4334), .B1(n738), .Y(n4047)
);
OAI22X1TS U5545 ( .A0(n4835), .A1(n4773), .B0(n3488), .B1(n4041), .Y(n4046)
);
OAI31X1TS U5546 ( .A0(n4047), .A1(n5452), .A2(n4046), .B0(n4045), .Y(
mult_x_24_n861) );
OAI22X1TS U5547 ( .A0(n4428), .A1(n4827), .B0(n4424), .B1(n738), .Y(n4050)
);
OAI22X1TS U5548 ( .A0(n4607), .A1(n4773), .B0(n5377), .B1(n4828), .Y(n4049)
);
OAI31X1TS U5549 ( .A0(n4050), .A1(n4278), .A2(n4049), .B0(n4048), .Y(
mult_x_24_n866) );
OAI22X1TS U5550 ( .A0(n852), .A1(n4351), .B0(n4068), .B1(n743), .Y(n4054) );
BUFX3TS U5551 ( .A(n4051), .Y(n4833) );
BUFX4TS U5552 ( .A(n4515), .Y(n4834) );
OAI22X1TS U5553 ( .A0(n4835), .A1(n4833), .B0(n3488), .B1(n4834), .Y(n4053)
);
OAI31X1TS U5554 ( .A0(n4054), .A1(n4519), .A2(n4053), .B0(n4052), .Y(
mult_x_24_n890) );
OAI22X1TS U5555 ( .A0(n4444), .A1(n4834), .B0(n4080), .B1(n743), .Y(n4057)
);
OAI22X1TS U5556 ( .A0(n4081), .A1(n4351), .B0(n5354), .B1(n4051), .Y(n4056)
);
OAI31X1TS U5557 ( .A0(n4057), .A1(n929), .A2(n4056), .B0(n4055), .Y(
mult_x_24_n892) );
AOI222X1TS U5558 ( .A0(n4892), .A1(n4059), .B0(Op_MY[0]), .B1(n4058), .C0(
n4806), .C1(n4749), .Y(n4060) );
XNOR2X1TS U5559 ( .A(n729), .B(n4060), .Y(n4067) );
OAI31X1TS U5560 ( .A0(n4755), .A1(n729), .A2(n4062), .B0(n4061), .Y(n4695)
);
OAI22X1TS U5561 ( .A0(n4755), .A1(n4680), .B0(n4756), .B1(n739), .Y(n4065)
);
OAI22X1TS U5562 ( .A0(n4772), .A1(n4097), .B0(n4779), .B1(n4681), .Y(n4064)
);
OAI31X1TS U5563 ( .A0(n4065), .A1(n5451), .A2(n4064), .B0(n4063), .Y(n4671)
);
OAI22X1TS U5564 ( .A0(n852), .A1(n4443), .B0(n4068), .B1(n745), .Y(n4071) );
OAI22X1TS U5565 ( .A0(n4835), .A1(n4458), .B0(n4081), .B1(n4840), .Y(n4070)
);
OAI31X1TS U5566 ( .A0(n4071), .A1(n4513), .A2(n4070), .B0(n4069), .Y(
mult_x_24_n920) );
AOI222X1TS U5567 ( .A0(n4892), .A1(n4073), .B0(Op_MY[0]), .B1(n4072), .C0(
n4818), .C1(n4749), .Y(n4074) );
XNOR2X1TS U5568 ( .A(DP_OP_169J45_123_4229_n2458), .B(n4074), .Y(n4713) );
OAI31X1TS U5569 ( .A0(n4755), .A1(DP_OP_169J45_123_4229_n2458), .A2(n4076),
.B0(n4075), .Y(n4742) );
OAI22X1TS U5570 ( .A0(n5354), .A1(n4506), .B0(n4334), .B1(n745), .Y(n4079)
);
OAI22X1TS U5571 ( .A0(n4835), .A1(n4443), .B0(n4081), .B1(n4507), .Y(n4078)
);
OAI31X1TS U5572 ( .A0(n4079), .A1(n4513), .A2(n4078), .B0(n4077), .Y(
mult_x_24_n921) );
OAI22X1TS U5573 ( .A0(n4444), .A1(n4840), .B0(n4080), .B1(n745), .Y(n4084)
);
OAI22X1TS U5574 ( .A0(n4081), .A1(n4443), .B0(n5354), .B1(n4507), .Y(n4083)
);
OAI31X1TS U5575 ( .A0(n4084), .A1(n4513), .A2(n4083), .B0(n4082), .Y(
mult_x_24_n922) );
OAI22X1TS U5576 ( .A0(n740), .A1(n4433), .B0(n4640), .B1(n5357), .Y(n4087)
);
OAI22X1TS U5577 ( .A0(n4845), .A1(n4429), .B0(n3933), .B1(n4434), .Y(n4086)
);
OAI31X1TS U5578 ( .A0(n4087), .A1(n4659), .A2(n4086), .B0(n4085), .Y(
mult_x_24_n713) );
OAI22X1TS U5579 ( .A0(n740), .A1(n4442), .B0(n4845), .B1(n4607), .Y(n4090)
);
OAI22X1TS U5580 ( .A0(n4655), .A1(n4429), .B0(n3933), .B1(n5357), .Y(n4089)
);
OAI21XLTS U5581 ( .A0(n4090), .A1(n4089), .B0(n4656), .Y(n4088) );
OAI31X1TS U5582 ( .A0(n4090), .A1(n4659), .A2(n4089), .B0(n4088), .Y(
mult_x_24_n714) );
OAI22X1TS U5583 ( .A0(n740), .A1(n4410), .B0(n3933), .B1(n5355), .Y(n4093)
);
OAI22X1TS U5584 ( .A0(n4655), .A1(n4438), .B0(n4845), .B1(n5374), .Y(n4092)
);
OAI31X1TS U5585 ( .A0(n4093), .A1(n4659), .A2(n4092), .B0(n4091), .Y(
mult_x_24_n719) );
OAI22X1TS U5586 ( .A0(n5357), .A1(n4803), .B0(n4433), .B1(n739), .Y(n4096)
);
OAI22X1TS U5587 ( .A0(n4434), .A1(n4097), .B0(n4429), .B1(n4804), .Y(n4095)
);
OAI31X1TS U5588 ( .A0(n4096), .A1(n5451), .A2(n4095), .B0(n4094), .Y(
mult_x_24_n743) );
OAI22X1TS U5589 ( .A0(n4607), .A1(n4804), .B0(n4442), .B1(n739), .Y(n4100)
);
OAI22X1TS U5590 ( .A0(n5357), .A1(n4097), .B0(n4429), .B1(n4681), .Y(n4099)
);
OAI31X1TS U5591 ( .A0(n4100), .A1(n4674), .A2(n4099), .B0(n4098), .Y(
mult_x_24_n744) );
OAI22X1TS U5592 ( .A0(n740), .A1(n4448), .B0(n4654), .B1(n5351), .Y(n4104)
);
OAI22X1TS U5593 ( .A0(n4655), .A1(n4459), .B0(n3933), .B1(n5352), .Y(n4102)
);
OAI31X1TS U5594 ( .A0(n4104), .A1(n4103), .A2(n4102), .B0(n4101), .Y(
mult_x_24_n723) );
OAI22X1TS U5595 ( .A0(n5355), .A1(n4803), .B0(n4414), .B1(n739), .Y(n4107)
);
OAI22X1TS U5596 ( .A0(n4415), .A1(n4097), .B0(n4438), .B1(n4804), .Y(n4106)
);
OAI31X1TS U5597 ( .A0(n4107), .A1(n4682), .A2(n4106), .B0(n4105), .Y(
mult_x_24_n748) );
OAI22X1TS U5598 ( .A0(n5355), .A1(n4804), .B0(n4419), .B1(n739), .Y(n4110)
);
OAI22X1TS U5599 ( .A0(n5356), .A1(n4097), .B0(n4415), .B1(n4681), .Y(n4109)
);
OAI31X1TS U5600 ( .A0(n4110), .A1(n4682), .A2(n4109), .B0(n4108), .Y(
mult_x_24_n747) );
OAI22X1TS U5601 ( .A0(n740), .A1(n4466), .B0(n3933), .B1(n5351), .Y(n4113)
);
OAI22X1TS U5602 ( .A0(n4655), .A1(n4471), .B0(n4654), .B1(n5371), .Y(n4112)
);
OAI31X1TS U5603 ( .A0(n4113), .A1(n4844), .A2(n4112), .B0(n4111), .Y(
mult_x_24_n725) );
OAI22X1TS U5604 ( .A0(n5355), .A1(n4097), .B0(n4410), .B1(n739), .Y(n4116)
);
OAI22X1TS U5605 ( .A0(n4438), .A1(n4803), .B0(n4630), .B1(n4804), .Y(n4115)
);
OAI31X1TS U5606 ( .A0(n4116), .A1(n5451), .A2(n4115), .B0(n4114), .Y(
mult_x_24_n749) );
OAI22X1TS U5607 ( .A0(n4621), .A1(n4680), .B0(n4622), .B1(n739), .Y(n4119)
);
OAI22X1TS U5608 ( .A0(n4438), .A1(n4097), .B0(n4630), .B1(n4681), .Y(n4118)
);
OAI31X1TS U5609 ( .A0(n4119), .A1(n5451), .A2(n4118), .B0(n4117), .Y(
mult_x_24_n750) );
OAI22X1TS U5610 ( .A0(n5357), .A1(n4809), .B0(n4433), .B1(n742), .Y(n4122)
);
OAI22X1TS U5611 ( .A0(n4434), .A1(n4697), .B0(n5379), .B1(n4810), .Y(n4121)
);
OAI31X1TS U5612 ( .A0(n4122), .A1(n4702), .A2(n4121), .B0(n4120), .Y(
mult_x_24_n773) );
OAI22X1TS U5613 ( .A0(n4607), .A1(n4810), .B0(n4442), .B1(n742), .Y(n4126)
);
OAI22X1TS U5614 ( .A0(n5357), .A1(n4697), .B0(n4429), .B1(n4698), .Y(n4124)
);
OAI31X1TS U5615 ( .A0(n4126), .A1(n4125), .A2(n4124), .B0(n4123), .Y(
mult_x_24_n774) );
OAI22X1TS U5616 ( .A0(n5351), .A1(n4803), .B0(n4457), .B1(n739), .Y(n4129)
);
OAI22X1TS U5617 ( .A0(n4459), .A1(n4097), .B0(n4471), .B1(n4804), .Y(n4128)
);
OAI31X1TS U5618 ( .A0(n4129), .A1(n5451), .A2(n4128), .B0(n4127), .Y(
mult_x_24_n754) );
OAI22X1TS U5619 ( .A0(n5351), .A1(n4680), .B0(n4448), .B1(n739), .Y(n4132)
);
OAI22X1TS U5620 ( .A0(n5352), .A1(n4097), .B0(n4459), .B1(n4681), .Y(n4131)
);
OAI31X1TS U5621 ( .A0(n4132), .A1(n5451), .A2(n4131), .B0(n4130), .Y(
mult_x_24_n753) );
OAI22X1TS U5622 ( .A0(n5355), .A1(n4809), .B0(n4414), .B1(n742), .Y(n4135)
);
OAI22X1TS U5623 ( .A0(n4415), .A1(n4697), .B0(n4438), .B1(n4810), .Y(n4134)
);
OAI31X1TS U5624 ( .A0(n4135), .A1(n4702), .A2(n4134), .B0(n4133), .Y(
mult_x_24_n778) );
OAI22X1TS U5625 ( .A0(n5351), .A1(n4097), .B0(n4466), .B1(n739), .Y(n4138)
);
OAI22X1TS U5626 ( .A0(n4471), .A1(n4681), .B0(n4648), .B1(n4804), .Y(n4137)
);
OAI31X1TS U5627 ( .A0(n4138), .A1(n5451), .A2(n4137), .B0(n4136), .Y(
mult_x_24_n755) );
OAI22X1TS U5628 ( .A0(n5355), .A1(n4810), .B0(n4419), .B1(n742), .Y(n4141)
);
OAI22X1TS U5629 ( .A0(n5356), .A1(n4697), .B0(n4415), .B1(n4698), .Y(n4140)
);
OAI31X1TS U5630 ( .A0(n4141), .A1(n5338), .A2(n4140), .B0(n4139), .Y(
mult_x_24_n777) );
OAI22X1TS U5631 ( .A0(n5355), .A1(n4697), .B0(n4410), .B1(n742), .Y(n4144)
);
OAI22X1TS U5632 ( .A0(n4438), .A1(n4809), .B0(n5374), .B1(n4810), .Y(n4143)
);
OAI31X1TS U5633 ( .A0(n4144), .A1(n4702), .A2(n4143), .B0(n4142), .Y(
mult_x_24_n779) );
OAI22X1TS U5634 ( .A0(n4638), .A1(n4680), .B0(n4639), .B1(n739), .Y(n4147)
);
OAI22X1TS U5635 ( .A0(n4471), .A1(n4097), .B0(n4648), .B1(n4681), .Y(n4146)
);
OAI31X1TS U5636 ( .A0(n4147), .A1(n5451), .A2(n4146), .B0(n4145), .Y(
mult_x_24_n756) );
OAI22X1TS U5637 ( .A0(n4621), .A1(n4696), .B0(n4622), .B1(n742), .Y(n4150)
);
OAI22X1TS U5638 ( .A0(n4438), .A1(n4697), .B0(n4630), .B1(n4698), .Y(n4149)
);
OAI31X1TS U5639 ( .A0(n4150), .A1(n4702), .A2(n4149), .B0(n4148), .Y(
mult_x_24_n780) );
OAI22X1TS U5640 ( .A0(n5357), .A1(n4815), .B0(n4433), .B1(n735), .Y(n4153)
);
OAI22X1TS U5641 ( .A0(n4434), .A1(n4725), .B0(n4429), .B1(n4816), .Y(n4152)
);
OAI31X1TS U5642 ( .A0(n4153), .A1(n4174), .A2(n4152), .B0(n4151), .Y(
mult_x_24_n803) );
OAI22X1TS U5643 ( .A0(n4607), .A1(n4816), .B0(n4442), .B1(n735), .Y(n4156)
);
OAI22X1TS U5644 ( .A0(n5357), .A1(n4725), .B0(n5379), .B1(n3978), .Y(n4155)
);
OAI31X1TS U5645 ( .A0(n4156), .A1(n4174), .A2(n4155), .B0(n4154), .Y(
mult_x_24_n804) );
OAI22X1TS U5646 ( .A0(n5350), .A1(n4680), .B0(n4647), .B1(n739), .Y(n4159)
);
OAI22X1TS U5647 ( .A0(n4648), .A1(n4097), .B0(n5346), .B1(n4681), .Y(n4158)
);
OAI31X1TS U5648 ( .A0(n4159), .A1(n5451), .A2(n4158), .B0(n4157), .Y(
mult_x_24_n757) );
OAI22X1TS U5649 ( .A0(n5351), .A1(n4696), .B0(n4448), .B1(n742), .Y(n4162)
);
OAI22X1TS U5650 ( .A0(n5352), .A1(n4697), .B0(n4459), .B1(n4698), .Y(n4161)
);
OAI31X1TS U5651 ( .A0(n4162), .A1(n4702), .A2(n4161), .B0(n4160), .Y(
mult_x_24_n783) );
OAI22X1TS U5652 ( .A0(n5351), .A1(n4809), .B0(n4457), .B1(n742), .Y(n4165)
);
OAI22X1TS U5653 ( .A0(n4459), .A1(n4697), .B0(n4471), .B1(n4810), .Y(n4164)
);
OAI31X1TS U5654 ( .A0(n4165), .A1(n4702), .A2(n4164), .B0(n4163), .Y(
mult_x_24_n784) );
OAI22X1TS U5655 ( .A0(n5351), .A1(n4697), .B0(n4466), .B1(n742), .Y(n4168)
);
OAI22X1TS U5656 ( .A0(n4471), .A1(n4698), .B0(n5371), .B1(n4810), .Y(n4167)
);
OAI31X1TS U5657 ( .A0(n4168), .A1(n4702), .A2(n4167), .B0(n4166), .Y(
mult_x_24_n785) );
OAI22X1TS U5658 ( .A0(n5355), .A1(n4815), .B0(n4414), .B1(n735), .Y(n4171)
);
OAI22X1TS U5659 ( .A0(n4415), .A1(n4725), .B0(n4438), .B1(n4816), .Y(n4170)
);
OAI31X1TS U5660 ( .A0(n4171), .A1(n4174), .A2(n4170), .B0(n4169), .Y(
mult_x_24_n808) );
OAI22X1TS U5661 ( .A0(n5355), .A1(n4816), .B0(n4419), .B1(n735), .Y(n4175)
);
OAI22X1TS U5662 ( .A0(n5356), .A1(n4725), .B0(n5377), .B1(n3978), .Y(n4173)
);
OAI31X1TS U5663 ( .A0(n4175), .A1(n4174), .A2(n4173), .B0(n4172), .Y(
mult_x_24_n807) );
OAI22X1TS U5664 ( .A0(n5355), .A1(n4725), .B0(n4410), .B1(n735), .Y(n4178)
);
OAI22X1TS U5665 ( .A0(n4438), .A1(n4815), .B0(n4630), .B1(n4816), .Y(n4177)
);
OAI31X1TS U5666 ( .A0(n4178), .A1(n4174), .A2(n4177), .B0(n4176), .Y(
mult_x_24_n809) );
OAI22X1TS U5667 ( .A0(n4638), .A1(n4696), .B0(n4639), .B1(n742), .Y(n4181)
);
OAI22X1TS U5668 ( .A0(n4471), .A1(n4697), .B0(n4648), .B1(n4698), .Y(n4180)
);
OAI31X1TS U5669 ( .A0(n4181), .A1(n4702), .A2(n4180), .B0(n4179), .Y(
mult_x_24_n786) );
OAI22X1TS U5670 ( .A0(n4621), .A1(n4724), .B0(n4622), .B1(n735), .Y(n4184)
);
OAI22X1TS U5671 ( .A0(n5348), .A1(n4725), .B0(n5374), .B1(n3978), .Y(n4183)
);
OAI31X1TS U5672 ( .A0(n4184), .A1(n959), .A2(n4183), .B0(n4182), .Y(
mult_x_24_n810) );
OAI22X1TS U5673 ( .A0(n5352), .A1(n4724), .B0(n4629), .B1(n735), .Y(n4187)
);
OAI22X1TS U5674 ( .A0(n4630), .A1(n4725), .B0(n5349), .B1(n3978), .Y(n4186)
);
OAI31X1TS U5675 ( .A0(n4187), .A1(n959), .A2(n4186), .B0(n4185), .Y(
mult_x_24_n811) );
OAI22X1TS U5676 ( .A0(n5357), .A1(n4821), .B0(n4433), .B1(n737), .Y(n4191)
);
OAI22X1TS U5677 ( .A0(n4434), .A1(n4400), .B0(n5379), .B1(n4822), .Y(n4190)
);
OAI31X1TS U5678 ( .A0(n4191), .A1(n4747), .A2(n4190), .B0(n4189), .Y(
mult_x_24_n833) );
OAI22X1TS U5679 ( .A0(n4607), .A1(n4822), .B0(n4442), .B1(n737), .Y(n4195)
);
OAI22X1TS U5680 ( .A0(n4444), .A1(n4400), .B0(n5379), .B1(n4013), .Y(n4193)
);
OAI31X1TS U5681 ( .A0(n4195), .A1(n4194), .A2(n4193), .B0(n4192), .Y(
mult_x_24_n834) );
OAI22X1TS U5682 ( .A0(n5350), .A1(n4696), .B0(n4647), .B1(n742), .Y(n4198)
);
OAI22X1TS U5683 ( .A0(n4648), .A1(n4697), .B0(n5346), .B1(n4698), .Y(n4197)
);
OAI31X1TS U5684 ( .A0(n4198), .A1(n4702), .A2(n4197), .B0(n4196), .Y(
mult_x_24_n787) );
OAI22X1TS U5685 ( .A0(n740), .A1(n4764), .B0(n4654), .B1(n4781), .Y(n4201)
);
OAI22X1TS U5686 ( .A0(n4655), .A1(n4765), .B0(n3933), .B1(n4508), .Y(n4200)
);
OAI31X1TS U5687 ( .A0(n4201), .A1(n4659), .A2(n4200), .B0(n4199), .Y(
mult_x_24_n731) );
OAI22X1TS U5688 ( .A0(n5350), .A1(n4698), .B0(n4490), .B1(n742), .Y(n4204)
);
OAI22X1TS U5689 ( .A0(n4638), .A1(n4697), .B0(n5369), .B1(n4810), .Y(n4203)
);
OAI31X1TS U5690 ( .A0(n4204), .A1(n4702), .A2(n4203), .B0(n4202), .Y(
mult_x_24_n788) );
OAI22X1TS U5691 ( .A0(n5351), .A1(n4724), .B0(n4448), .B1(n735), .Y(n4207)
);
OAI22X1TS U5692 ( .A0(n5352), .A1(n4725), .B0(n5372), .B1(n3978), .Y(n4206)
);
OAI31X1TS U5693 ( .A0(n4207), .A1(n959), .A2(n4206), .B0(n4205), .Y(
mult_x_24_n813) );
OAI22X1TS U5694 ( .A0(n4508), .A1(n4680), .B0(n4497), .B1(n739), .Y(n4210)
);
OAI22X1TS U5695 ( .A0(n5350), .A1(n4097), .B0(n4509), .B1(n4681), .Y(n4209)
);
OAI31X1TS U5696 ( .A0(n4210), .A1(n5451), .A2(n4209), .B0(n4208), .Y(
mult_x_24_n759) );
OAI22X1TS U5697 ( .A0(n5351), .A1(n4815), .B0(n4457), .B1(n735), .Y(n4213)
);
OAI22X1TS U5698 ( .A0(n4459), .A1(n4725), .B0(n4471), .B1(n4816), .Y(n4212)
);
OAI31X1TS U5699 ( .A0(n4213), .A1(n959), .A2(n4212), .B0(n4211), .Y(
mult_x_24_n814) );
OAI22X1TS U5700 ( .A0(n5351), .A1(n4725), .B0(n4466), .B1(n735), .Y(n4216)
);
OAI22X1TS U5701 ( .A0(n4471), .A1(n4815), .B0(n4648), .B1(n4816), .Y(n4215)
);
OAI31X1TS U5702 ( .A0(n4216), .A1(n959), .A2(n4215), .B0(n4214), .Y(
mult_x_24_n815) );
OAI22X1TS U5703 ( .A0(n5350), .A1(n4724), .B0(n4647), .B1(n735), .Y(n4219)
);
OAI22X1TS U5704 ( .A0(n4648), .A1(n4725), .B0(n5346), .B1(n3978), .Y(n4218)
);
OAI31X1TS U5705 ( .A0(n4219), .A1(n959), .A2(n4218), .B0(n4217), .Y(
mult_x_24_n817) );
OAI22X1TS U5706 ( .A0(n5355), .A1(n4821), .B0(n4414), .B1(n737), .Y(n4222)
);
OAI22X1TS U5707 ( .A0(n4415), .A1(n4400), .B0(n4438), .B1(n4822), .Y(n4221)
);
OAI31X1TS U5708 ( .A0(n4222), .A1(n4747), .A2(n4221), .B0(n4220), .Y(
mult_x_24_n838) );
OAI22X1TS U5709 ( .A0(n4638), .A1(n4724), .B0(n4639), .B1(n735), .Y(n4225)
);
OAI22X1TS U5710 ( .A0(n5347), .A1(n4725), .B0(n5371), .B1(n3978), .Y(n4224)
);
OAI31X1TS U5711 ( .A0(n4225), .A1(n959), .A2(n4224), .B0(n4223), .Y(
mult_x_24_n816) );
OAI22X1TS U5712 ( .A0(n5355), .A1(n4822), .B0(n4419), .B1(n737), .Y(n4229)
);
OAI22X1TS U5713 ( .A0(n4428), .A1(n4400), .B0(n5377), .B1(n4013), .Y(n4228)
);
OAI31X1TS U5714 ( .A0(n4229), .A1(n4194), .A2(n4228), .B0(n4227), .Y(
mult_x_24_n837) );
OAI22X1TS U5715 ( .A0(n4420), .A1(n4400), .B0(n4410), .B1(n737), .Y(n4232)
);
OAI22X1TS U5716 ( .A0(n5348), .A1(n4821), .B0(n5374), .B1(n4822), .Y(n4231)
);
OAI31X1TS U5717 ( .A0(n4232), .A1(n4747), .A2(n4231), .B0(n4230), .Y(
mult_x_24_n839) );
OAI22X1TS U5718 ( .A0(n740), .A1(n4771), .B0(n4654), .B1(n4772), .Y(n4235)
);
OAI22X1TS U5719 ( .A0(n4655), .A1(n5344), .B0(n3933), .B1(n5343), .Y(n4234)
);
OAI31X1TS U5720 ( .A0(n4235), .A1(n4659), .A2(n4234), .B0(n4233), .Y(
mult_x_24_n732) );
OAI22X1TS U5721 ( .A0(n4508), .A1(n4696), .B0(n4497), .B1(n742), .Y(n4238)
);
OAI22X1TS U5722 ( .A0(n5350), .A1(n4697), .B0(n4509), .B1(n4698), .Y(n4237)
);
OAI31X1TS U5723 ( .A0(n4238), .A1(n4702), .A2(n4237), .B0(n4236), .Y(
mult_x_24_n789) );
OAI22X1TS U5724 ( .A0(n4621), .A1(n4743), .B0(n4622), .B1(n737), .Y(n4241)
);
OAI22X1TS U5725 ( .A0(n5348), .A1(n4400), .B0(n5374), .B1(n4013), .Y(n4240)
);
OAI31X1TS U5726 ( .A0(n4241), .A1(n4747), .A2(n4240), .B0(n4239), .Y(
mult_x_24_n840) );
OAI22X1TS U5727 ( .A0(n5351), .A1(n4743), .B0(n4448), .B1(n737), .Y(n4244)
);
OAI22X1TS U5728 ( .A0(n4453), .A1(n4400), .B0(n5372), .B1(n4013), .Y(n4243)
);
OAI31X1TS U5729 ( .A0(n4244), .A1(n4747), .A2(n4243), .B0(n4242), .Y(
mult_x_24_n843) );
OAI22X1TS U5730 ( .A0(n5352), .A1(n4743), .B0(n4629), .B1(n737), .Y(n4247)
);
OAI22X1TS U5731 ( .A0(n4630), .A1(n4400), .B0(n5349), .B1(n4013), .Y(n4246)
);
OAI31X1TS U5732 ( .A0(n4247), .A1(n4747), .A2(n4246), .B0(n4245), .Y(
mult_x_24_n841) );
OAI22X1TS U5733 ( .A0(n5352), .A1(n4821), .B0(n4452), .B1(n737), .Y(n4250)
);
OAI22X1TS U5734 ( .A0(n4621), .A1(n4400), .B0(n5372), .B1(n4822), .Y(n4249)
);
OAI31X1TS U5735 ( .A0(n4250), .A1(n4747), .A2(n4249), .B0(n4248), .Y(
mult_x_24_n842) );
OAI22X1TS U5736 ( .A0(n5351), .A1(n4821), .B0(n4457), .B1(n737), .Y(n4254)
);
OAI22X1TS U5737 ( .A0(n4459), .A1(n4400), .B0(n4471), .B1(n4822), .Y(n4253)
);
OAI31X1TS U5738 ( .A0(n4254), .A1(n4747), .A2(n4253), .B0(n4252), .Y(
mult_x_24_n844) );
OAI22X1TS U5739 ( .A0(n4765), .A1(n4680), .B0(n4505), .B1(n739), .Y(n4257)
);
OAI22X1TS U5740 ( .A0(n4509), .A1(n4097), .B0(n4508), .B1(n4681), .Y(n4256)
);
OAI31X1TS U5741 ( .A0(n4257), .A1(n5451), .A2(n4256), .B0(n4255), .Y(
mult_x_24_n760) );
OAI22X1TS U5742 ( .A0(n4444), .A1(n4827), .B0(n4433), .B1(n738), .Y(n4260)
);
OAI22X1TS U5743 ( .A0(n4434), .A1(n4773), .B0(n5379), .B1(n4828), .Y(n4259)
);
OAI31X1TS U5744 ( .A0(n4260), .A1(n5452), .A2(n4259), .B0(n4258), .Y(
mult_x_24_n863) );
OAI22X1TS U5745 ( .A0(n5350), .A1(n4815), .B0(n4490), .B1(n735), .Y(n4263)
);
OAI22X1TS U5746 ( .A0(n4638), .A1(n4725), .B0(n4509), .B1(n4816), .Y(n4262)
);
OAI31X1TS U5747 ( .A0(n4263), .A1(n959), .A2(n4262), .B0(n4261), .Y(
mult_x_24_n818) );
OAI22X1TS U5748 ( .A0(n4467), .A1(n4400), .B0(n4466), .B1(n737), .Y(n4266)
);
OAI22X1TS U5749 ( .A0(n5347), .A1(n4821), .B0(n5371), .B1(n4822), .Y(n4265)
);
OAI31X1TS U5750 ( .A0(n4266), .A1(n4747), .A2(n4265), .B0(n4264), .Y(
mult_x_24_n845) );
OAI22X1TS U5751 ( .A0(n4638), .A1(n4743), .B0(n4639), .B1(n737), .Y(n4269)
);
OAI22X1TS U5752 ( .A0(n5347), .A1(n4400), .B0(n5371), .B1(n4013), .Y(n4268)
);
OAI31X1TS U5753 ( .A0(n4269), .A1(n4747), .A2(n4268), .B0(n4267), .Y(
mult_x_24_n846) );
OAI22X1TS U5754 ( .A0(n5350), .A1(n4743), .B0(n4647), .B1(n737), .Y(n4272)
);
OAI22X1TS U5755 ( .A0(n4648), .A1(n4400), .B0(n5346), .B1(n4013), .Y(n4271)
);
OAI31X1TS U5756 ( .A0(n4272), .A1(n4747), .A2(n4271), .B0(n4270), .Y(
mult_x_24_n847) );
OAI22X1TS U5757 ( .A0(n4428), .A1(n4828), .B0(n4611), .B1(n738), .Y(n4275)
);
OAI22X1TS U5758 ( .A0(n4429), .A1(n4773), .B0(n5353), .B1(n4041), .Y(n4274)
);
OAI31X1TS U5759 ( .A0(n4275), .A1(n4278), .A2(n4274), .B0(n4273), .Y(
mult_x_24_n865) );
OAI22X1TS U5760 ( .A0(n4607), .A1(n4828), .B0(n4442), .B1(n738), .Y(n4279)
);
OAI22X1TS U5761 ( .A0(n4444), .A1(n4773), .B0(n5379), .B1(n4041), .Y(n4277)
);
OAI31X1TS U5762 ( .A0(n4279), .A1(n4278), .A2(n4277), .B0(n4276), .Y(
mult_x_24_n864) );
OAI22X1TS U5763 ( .A0(n740), .A1(n4777), .B0(n4654), .B1(n4779), .Y(n4282)
);
OAI22X1TS U5764 ( .A0(n4655), .A1(n5342), .B0(n3933), .B1(n4781), .Y(n4281)
);
OAI31X1TS U5765 ( .A0(n4282), .A1(n4659), .A2(n4281), .B0(n4280), .Y(
mult_x_24_n733) );
OAI22X1TS U5766 ( .A0(n4765), .A1(n4696), .B0(n4505), .B1(n742), .Y(n4285)
);
OAI22X1TS U5767 ( .A0(n4509), .A1(n4697), .B0(n4508), .B1(n4698), .Y(n4284)
);
OAI31X1TS U5768 ( .A0(n4285), .A1(n4702), .A2(n4284), .B0(n4283), .Y(
mult_x_24_n790) );
OAI22X1TS U5769 ( .A0(n5345), .A1(n4724), .B0(n4497), .B1(n735), .Y(n4288)
);
OAI22X1TS U5770 ( .A0(n5350), .A1(n4725), .B0(n5369), .B1(n3978), .Y(n4287)
);
OAI31X1TS U5771 ( .A0(n4288), .A1(n959), .A2(n4287), .B0(n4286), .Y(
mult_x_24_n819) );
OAI22X1TS U5772 ( .A0(n5350), .A1(n4821), .B0(n4490), .B1(n737), .Y(n4291)
);
OAI22X1TS U5773 ( .A0(n4638), .A1(n4400), .B0(n5369), .B1(n4822), .Y(n4290)
);
OAI31X1TS U5774 ( .A0(n4291), .A1(n4747), .A2(n4290), .B0(n4289), .Y(
mult_x_24_n848) );
OAI22X1TS U5775 ( .A0(n4781), .A1(n4696), .B0(n4764), .B1(n742), .Y(n4294)
);
OAI22X1TS U5776 ( .A0(n4508), .A1(n4697), .B0(n4765), .B1(n4698), .Y(n4293)
);
OAI31X1TS U5777 ( .A0(n4294), .A1(n4702), .A2(n4293), .B0(n4292), .Y(
mult_x_24_n791) );
OAI22X1TS U5778 ( .A0(n4765), .A1(n4724), .B0(n4505), .B1(n735), .Y(n4297)
);
OAI22X1TS U5779 ( .A0(n4509), .A1(n4725), .B0(n4508), .B1(n4815), .Y(n4296)
);
OAI31X1TS U5780 ( .A0(n4297), .A1(n959), .A2(n4296), .B0(n4295), .Y(
mult_x_24_n820) );
OAI22X1TS U5781 ( .A0(n5345), .A1(n4743), .B0(n4497), .B1(n737), .Y(n4300)
);
OAI22X1TS U5782 ( .A0(n4498), .A1(n4400), .B0(n5369), .B1(n4013), .Y(n4299)
);
OAI31X1TS U5783 ( .A0(n4300), .A1(n4747), .A2(n4299), .B0(n4298), .Y(
mult_x_24_n849) );
OAI22X1TS U5784 ( .A0(n4420), .A1(n4828), .B0(n4419), .B1(n738), .Y(n4303)
);
OAI22X1TS U5785 ( .A0(n4428), .A1(n4773), .B0(n5377), .B1(n4041), .Y(n4302)
);
OAI31X1TS U5786 ( .A0(n4303), .A1(n4782), .A2(n4302), .B0(n4301), .Y(
mult_x_24_n867) );
OAI22X1TS U5787 ( .A0(n4453), .A1(n4778), .B0(n4629), .B1(n738), .Y(n4306)
);
OAI22X1TS U5788 ( .A0(n4630), .A1(n4773), .B0(n5349), .B1(n4041), .Y(n4305)
);
OAI31X1TS U5789 ( .A0(n4306), .A1(n5452), .A2(n4305), .B0(n4304), .Y(
mult_x_24_n871) );
OAI22X1TS U5790 ( .A0(n4621), .A1(n4778), .B0(n4622), .B1(n738), .Y(n4309)
);
OAI22X1TS U5791 ( .A0(n5348), .A1(n4773), .B0(n5374), .B1(n4041), .Y(n4308)
);
OAI31X1TS U5792 ( .A0(n4309), .A1(n5452), .A2(n4308), .B0(n4307), .Y(
mult_x_24_n870) );
OAI22X1TS U5793 ( .A0(n4420), .A1(n4773), .B0(n4410), .B1(n738), .Y(n4312)
);
OAI22X1TS U5794 ( .A0(n5348), .A1(n4827), .B0(n5374), .B1(n4828), .Y(n4311)
);
OAI31X1TS U5795 ( .A0(n4312), .A1(n5452), .A2(n4311), .B0(n4310), .Y(
mult_x_24_n869) );
OAI22X1TS U5796 ( .A0(n4420), .A1(n4827), .B0(n4414), .B1(n738), .Y(n4315)
);
OAI22X1TS U5797 ( .A0(n4415), .A1(n4773), .B0(n4438), .B1(n4828), .Y(n4314)
);
OAI31X1TS U5798 ( .A0(n4315), .A1(n4782), .A2(n4314), .B0(n4313), .Y(
mult_x_24_n868) );
OAI22X1TS U5799 ( .A0(n4467), .A1(n4778), .B0(n4448), .B1(n738), .Y(n4318)
);
OAI22X1TS U5800 ( .A0(n4453), .A1(n4773), .B0(n5372), .B1(n4041), .Y(n4317)
);
OAI31X1TS U5801 ( .A0(n4318), .A1(n5452), .A2(n4317), .B0(n4316), .Y(
mult_x_24_n873) );
OAI22X1TS U5802 ( .A0(n4453), .A1(n4827), .B0(n4452), .B1(n738), .Y(n4321)
);
OAI22X1TS U5803 ( .A0(n4621), .A1(n4773), .B0(n5372), .B1(n4828), .Y(n4320)
);
OAI31X1TS U5804 ( .A0(n4321), .A1(n5452), .A2(n4320), .B0(n4319), .Y(
mult_x_24_n872) );
OAI22X1TS U5805 ( .A0(n4467), .A1(n4827), .B0(n4457), .B1(n738), .Y(n4324)
);
OAI22X1TS U5806 ( .A0(n4459), .A1(n4773), .B0(n4471), .B1(n4828), .Y(n4323)
);
OAI31X1TS U5807 ( .A0(n4324), .A1(n5452), .A2(n4323), .B0(n4322), .Y(
mult_x_24_n874) );
OAI22X1TS U5808 ( .A0(n4772), .A1(n4696), .B0(n4771), .B1(n742), .Y(n4327)
);
OAI22X1TS U5809 ( .A0(n4765), .A1(n4697), .B0(n5344), .B1(n4698), .Y(n4326)
);
OAI31X1TS U5810 ( .A0(n4327), .A1(n4702), .A2(n4326), .B0(n4325), .Y(
mult_x_24_n792) );
OAI22X1TS U5811 ( .A0(n4467), .A1(n4773), .B0(n4466), .B1(n738), .Y(n4330)
);
OAI22X1TS U5812 ( .A0(n5347), .A1(n4827), .B0(n5371), .B1(n4828), .Y(n4329)
);
OAI31X1TS U5813 ( .A0(n4330), .A1(n5452), .A2(n4329), .B0(n4328), .Y(
mult_x_24_n875) );
OAI22X1TS U5814 ( .A0(n4444), .A1(n4833), .B0(n4433), .B1(n743), .Y(n4333)
);
OAI22X1TS U5815 ( .A0(n5354), .A1(n4351), .B0(n5379), .B1(n4834), .Y(n4332)
);
OAI31X1TS U5816 ( .A0(n4333), .A1(n4519), .A2(n4332), .B0(n4331), .Y(
mult_x_24_n893) );
OAI22X1TS U5817 ( .A0(n5354), .A1(n4515), .B0(n4334), .B1(n743), .Y(n4338)
);
OAI22X1TS U5818 ( .A0(n4835), .A1(n4351), .B0(n3488), .B1(n4051), .Y(n4337)
);
OAI31X1TS U5819 ( .A0(n4338), .A1(n4519), .A2(n4337), .B0(n4336), .Y(
mult_x_24_n891) );
OAI22X1TS U5820 ( .A0(n5353), .A1(n4834), .B0(n4442), .B1(n743), .Y(n4341)
);
OAI22X1TS U5821 ( .A0(n4444), .A1(n4351), .B0(n5379), .B1(n4051), .Y(n4340)
);
OAI31X1TS U5822 ( .A0(n4341), .A1(n929), .A2(n4340), .B0(n4339), .Y(
mult_x_24_n894) );
OAI22X1TS U5823 ( .A0(n4428), .A1(n4834), .B0(n4611), .B1(n743), .Y(n4344)
);
OAI22X1TS U5824 ( .A0(n4429), .A1(n4351), .B0(n5353), .B1(n4051), .Y(n4343)
);
OAI31X1TS U5825 ( .A0(n4344), .A1(n929), .A2(n4343), .B0(n4342), .Y(
mult_x_24_n895) );
OAI22X1TS U5826 ( .A0(n4638), .A1(n4778), .B0(n4639), .B1(n738), .Y(n4347)
);
OAI22X1TS U5827 ( .A0(n5347), .A1(n4773), .B0(n5371), .B1(n4041), .Y(n4346)
);
OAI31X1TS U5828 ( .A0(n4347), .A1(n5452), .A2(n4346), .B0(n4345), .Y(
mult_x_24_n876) );
OAI22X1TS U5829 ( .A0(n4765), .A1(n4743), .B0(n4505), .B1(n737), .Y(n4350)
);
OAI22X1TS U5830 ( .A0(n4509), .A1(n4400), .B0(n4508), .B1(n4821), .Y(n4349)
);
OAI31X1TS U5831 ( .A0(n4350), .A1(n4747), .A2(n4349), .B0(n4348), .Y(
mult_x_24_n850) );
OAI22X1TS U5832 ( .A0(n4467), .A1(n4515), .B0(n4448), .B1(n743), .Y(n4354)
);
OAI22X1TS U5833 ( .A0(n4453), .A1(n4351), .B0(n5372), .B1(n4051), .Y(n4353)
);
OAI31X1TS U5834 ( .A0(n4354), .A1(n4519), .A2(n4353), .B0(n4352), .Y(
mult_x_24_n903) );
OAI22X1TS U5835 ( .A0(n4453), .A1(n4515), .B0(n4629), .B1(n743), .Y(n4357)
);
OAI22X1TS U5836 ( .A0(n4630), .A1(n4351), .B0(n5349), .B1(n4051), .Y(n4356)
);
OAI31X1TS U5837 ( .A0(n4357), .A1(n4519), .A2(n4356), .B0(n4355), .Y(
mult_x_24_n901) );
OAI22X1TS U5838 ( .A0(n4453), .A1(n4833), .B0(n4452), .B1(n743), .Y(n4360)
);
OAI22X1TS U5839 ( .A0(n5349), .A1(n4351), .B0(n5372), .B1(n4834), .Y(n4359)
);
OAI31X1TS U5840 ( .A0(n4360), .A1(n4519), .A2(n4359), .B0(n4358), .Y(
mult_x_24_n902) );
OAI22X1TS U5841 ( .A0(n5349), .A1(n4515), .B0(n4622), .B1(n743), .Y(n4363)
);
OAI22X1TS U5842 ( .A0(n4438), .A1(n4351), .B0(n5374), .B1(n4051), .Y(n4362)
);
OAI31X1TS U5843 ( .A0(n4363), .A1(n4519), .A2(n4362), .B0(n4361), .Y(
mult_x_24_n900) );
OAI22X1TS U5844 ( .A0(n4420), .A1(n4351), .B0(n4410), .B1(n743), .Y(n4366)
);
OAI22X1TS U5845 ( .A0(n5348), .A1(n4833), .B0(n5374), .B1(n4834), .Y(n4365)
);
OAI31X1TS U5846 ( .A0(n4366), .A1(n4519), .A2(n4365), .B0(n4364), .Y(
mult_x_24_n899) );
OAI22X1TS U5847 ( .A0(n4420), .A1(n4833), .B0(n4414), .B1(n743), .Y(n4369)
);
OAI22X1TS U5848 ( .A0(n4415), .A1(n4351), .B0(n4438), .B1(n4834), .Y(n4368)
);
OAI31X1TS U5849 ( .A0(n4369), .A1(n4519), .A2(n4368), .B0(n4367), .Y(
mult_x_24_n898) );
OAI22X1TS U5850 ( .A0(n4420), .A1(n4834), .B0(n4419), .B1(n743), .Y(n4372)
);
OAI22X1TS U5851 ( .A0(n4428), .A1(n4351), .B0(n5377), .B1(n4051), .Y(n4371)
);
OAI31X1TS U5852 ( .A0(n4372), .A1(n929), .A2(n4371), .B0(n4370), .Y(
mult_x_24_n897) );
OAI22X1TS U5853 ( .A0(n4428), .A1(n4833), .B0(n4424), .B1(n743), .Y(n4375)
);
OAI22X1TS U5854 ( .A0(n5353), .A1(n4351), .B0(n5377), .B1(n4834), .Y(n4374)
);
OAI31X1TS U5855 ( .A0(n4375), .A1(n929), .A2(n4374), .B0(n4373), .Y(
mult_x_24_n896) );
OAI22X1TS U5856 ( .A0(n4779), .A1(n4696), .B0(n4777), .B1(n742), .Y(n4378)
);
OAI22X1TS U5857 ( .A0(n4781), .A1(n4697), .B0(n5342), .B1(n4698), .Y(n4377)
);
OAI31X1TS U5858 ( .A0(n4378), .A1(n4702), .A2(n4377), .B0(n4376), .Y(
mult_x_24_n793) );
OAI22X1TS U5859 ( .A0(n4467), .A1(n4833), .B0(n4457), .B1(n743), .Y(n4381)
);
OAI22X1TS U5860 ( .A0(n4459), .A1(n4351), .B0(n4471), .B1(n4834), .Y(n4380)
);
OAI31X1TS U5861 ( .A0(n4381), .A1(n4519), .A2(n4380), .B0(n4379), .Y(
mult_x_24_n904) );
OAI22X1TS U5862 ( .A0(n4467), .A1(n4351), .B0(n4466), .B1(n743), .Y(n4384)
);
OAI22X1TS U5863 ( .A0(n5347), .A1(n4833), .B0(n5371), .B1(n4834), .Y(n4383)
);
OAI31X1TS U5864 ( .A0(n4384), .A1(n4519), .A2(n4383), .B0(n4382), .Y(
mult_x_24_n905) );
OAI22X1TS U5865 ( .A0(n5346), .A1(n4515), .B0(n4639), .B1(n743), .Y(n4387)
);
OAI22X1TS U5866 ( .A0(n4471), .A1(n4351), .B0(n5371), .B1(n4051), .Y(n4386)
);
OAI31X1TS U5867 ( .A0(n4387), .A1(n4519), .A2(n4386), .B0(n4385), .Y(
mult_x_24_n906) );
OAI22X1TS U5868 ( .A0(n4498), .A1(n4778), .B0(n4647), .B1(n738), .Y(n4390)
);
OAI22X1TS U5869 ( .A0(n4648), .A1(n4773), .B0(n5346), .B1(n4041), .Y(n4389)
);
OAI31X1TS U5870 ( .A0(n4390), .A1(n5452), .A2(n4389), .B0(n4388), .Y(
mult_x_24_n877) );
OAI22X1TS U5871 ( .A0(n4781), .A1(n4743), .B0(n4764), .B1(n737), .Y(n4393)
);
OAI22X1TS U5872 ( .A0(n5345), .A1(n4400), .B0(n4765), .B1(n4821), .Y(n4392)
);
OAI31X1TS U5873 ( .A0(n4393), .A1(n4747), .A2(n4392), .B0(n4391), .Y(
mult_x_24_n851) );
OAI22X1TS U5874 ( .A0(n4498), .A1(n4515), .B0(n4647), .B1(n743), .Y(n4396)
);
OAI22X1TS U5875 ( .A0(n4648), .A1(n4351), .B0(n5346), .B1(n4051), .Y(n4395)
);
OAI31X1TS U5876 ( .A0(n4396), .A1(n4519), .A2(n4395), .B0(n4394), .Y(
mult_x_24_n907) );
OAI22X1TS U5877 ( .A0(n4498), .A1(n4827), .B0(n4490), .B1(n738), .Y(n4399)
);
OAI22X1TS U5878 ( .A0(n4638), .A1(n4773), .B0(n5369), .B1(n4828), .Y(n4398)
);
OAI31X1TS U5879 ( .A0(n4399), .A1(n5452), .A2(n4398), .B0(n4397), .Y(
mult_x_24_n878) );
OAI22X1TS U5880 ( .A0(n4772), .A1(n4743), .B0(n4771), .B1(n737), .Y(n4403)
);
OAI22X1TS U5881 ( .A0(n4765), .A1(n4400), .B0(n5344), .B1(n4821), .Y(n4402)
);
OAI31X1TS U5882 ( .A0(n4403), .A1(n4747), .A2(n4402), .B0(n4401), .Y(
mult_x_24_n852) );
OAI22X1TS U5883 ( .A0(n4498), .A1(n4833), .B0(n4490), .B1(n743), .Y(n4406)
);
OAI22X1TS U5884 ( .A0(n5346), .A1(n4351), .B0(n5369), .B1(n4834), .Y(n4405)
);
OAI31X1TS U5885 ( .A0(n4406), .A1(n4519), .A2(n4405), .B0(n4404), .Y(
mult_x_24_n908) );
OAI22X1TS U5886 ( .A0(n4453), .A1(n4506), .B0(n4629), .B1(n745), .Y(n4409)
);
OAI22X1TS U5887 ( .A0(n4630), .A1(n4443), .B0(n5349), .B1(n4507), .Y(n4408)
);
OAI31X1TS U5888 ( .A0(n4409), .A1(n4513), .A2(n4408), .B0(n4407), .Y(
mult_x_24_n931) );
OAI22X1TS U5889 ( .A0(n4420), .A1(n4443), .B0(n4410), .B1(n745), .Y(n4413)
);
OAI22X1TS U5890 ( .A0(n5348), .A1(n4458), .B0(n5374), .B1(n4840), .Y(n4412)
);
OAI31X1TS U5891 ( .A0(n4413), .A1(n4513), .A2(n4412), .B0(n4411), .Y(
mult_x_24_n929) );
OAI22X1TS U5892 ( .A0(n4420), .A1(n4458), .B0(n4414), .B1(n745), .Y(n4418)
);
OAI22X1TS U5893 ( .A0(n4415), .A1(n4443), .B0(n4438), .B1(n4840), .Y(n4417)
);
OAI31X1TS U5894 ( .A0(n4418), .A1(n4878), .A2(n4417), .B0(n4416), .Y(
mult_x_24_n928) );
OAI22X1TS U5895 ( .A0(n4420), .A1(n4840), .B0(n4419), .B1(n745), .Y(n4423)
);
OAI22X1TS U5896 ( .A0(n4428), .A1(n4443), .B0(n5377), .B1(n4507), .Y(n4422)
);
OAI31X1TS U5897 ( .A0(n4423), .A1(n4878), .A2(n4422), .B0(n4421), .Y(
mult_x_24_n927) );
OAI22X1TS U5898 ( .A0(n4428), .A1(n4458), .B0(n4424), .B1(n745), .Y(n4427)
);
OAI22X1TS U5899 ( .A0(n4607), .A1(n4443), .B0(n5377), .B1(n4840), .Y(n4426)
);
OAI31X1TS U5900 ( .A0(n4427), .A1(n4878), .A2(n4426), .B0(n4425), .Y(
mult_x_24_n926) );
OAI22X1TS U5901 ( .A0(n4428), .A1(n4840), .B0(n4611), .B1(n745), .Y(n4432)
);
OAI22X1TS U5902 ( .A0(n4429), .A1(n4443), .B0(n5353), .B1(n4507), .Y(n4431)
);
OAI31X1TS U5903 ( .A0(n4432), .A1(n4513), .A2(n4431), .B0(n4430), .Y(
mult_x_24_n925) );
OAI22X1TS U5904 ( .A0(n4444), .A1(n4458), .B0(n4433), .B1(n745), .Y(n4437)
);
OAI22X1TS U5905 ( .A0(n4434), .A1(n4443), .B0(n5379), .B1(n4840), .Y(n4436)
);
OAI31X1TS U5906 ( .A0(n4437), .A1(n4513), .A2(n4436), .B0(n4435), .Y(
mult_x_24_n923) );
OAI22X1TS U5907 ( .A0(n5349), .A1(n4506), .B0(n4622), .B1(n745), .Y(n4441)
);
OAI22X1TS U5908 ( .A0(n4438), .A1(n4443), .B0(n5374), .B1(n4507), .Y(n4440)
);
OAI31X1TS U5909 ( .A0(n4441), .A1(n4513), .A2(n4440), .B0(n4439), .Y(
mult_x_24_n930) );
OAI22X1TS U5910 ( .A0(n5353), .A1(n4840), .B0(n4442), .B1(n745), .Y(n4447)
);
OAI22X1TS U5911 ( .A0(n4444), .A1(n4443), .B0(n5379), .B1(n4507), .Y(n4446)
);
OAI31X1TS U5912 ( .A0(n4447), .A1(n4510), .A2(n4446), .B0(n4445), .Y(
mult_x_24_n924) );
OAI22X1TS U5913 ( .A0(n4467), .A1(n4506), .B0(n4448), .B1(n745), .Y(n4451)
);
OAI22X1TS U5914 ( .A0(n4453), .A1(n4443), .B0(n5372), .B1(n4507), .Y(n4450)
);
OAI31X1TS U5915 ( .A0(n4451), .A1(n4513), .A2(n4450), .B0(n4449), .Y(
mult_x_24_n933) );
OAI22X1TS U5916 ( .A0(n4453), .A1(n4458), .B0(n4452), .B1(n745), .Y(n4456)
);
OAI22X1TS U5917 ( .A0(n4621), .A1(n4443), .B0(n5372), .B1(n4840), .Y(n4455)
);
OAI31X1TS U5918 ( .A0(n4456), .A1(n4513), .A2(n4455), .B0(n4454), .Y(
mult_x_24_n932) );
OAI22X1TS U5919 ( .A0(n4467), .A1(n4458), .B0(n4457), .B1(n745), .Y(n4462)
);
OAI22X1TS U5920 ( .A0(n4459), .A1(n4443), .B0(n4471), .B1(n4840), .Y(n4461)
);
OAI31X1TS U5921 ( .A0(n4462), .A1(n4513), .A2(n4461), .B0(n4460), .Y(
mult_x_24_n934) );
OAI22X1TS U5922 ( .A0(n5345), .A1(n4778), .B0(n4497), .B1(n738), .Y(n4465)
);
OAI22X1TS U5923 ( .A0(n4498), .A1(n4773), .B0(n5369), .B1(n4041), .Y(n4464)
);
OAI31X1TS U5924 ( .A0(n4465), .A1(n5452), .A2(n4464), .B0(n4463), .Y(
mult_x_24_n879) );
OAI22X1TS U5925 ( .A0(n4467), .A1(n4443), .B0(n4466), .B1(n745), .Y(n4470)
);
OAI22X1TS U5926 ( .A0(n5347), .A1(n4507), .B0(n5371), .B1(n4840), .Y(n4469)
);
OAI31X1TS U5927 ( .A0(n4470), .A1(n4513), .A2(n4469), .B0(n4468), .Y(
mult_x_24_n935) );
OAI22X1TS U5928 ( .A0(n5346), .A1(n4506), .B0(n4639), .B1(n745), .Y(n4474)
);
OAI22X1TS U5929 ( .A0(n4471), .A1(n4443), .B0(n5371), .B1(n4507), .Y(n4473)
);
OAI31X1TS U5930 ( .A0(n4474), .A1(n4513), .A2(n4473), .B0(n4472), .Y(
mult_x_24_n936) );
OAI22X1TS U5931 ( .A0(n4779), .A1(n4743), .B0(n4777), .B1(n737), .Y(n4477)
);
OAI22X1TS U5932 ( .A0(n4781), .A1(n4400), .B0(n5342), .B1(n4013), .Y(n4476)
);
OAI31X1TS U5933 ( .A0(n4477), .A1(n4747), .A2(n4476), .B0(n4475), .Y(
mult_x_24_n853) );
OAI22X1TS U5934 ( .A0(n4508), .A1(n4515), .B0(n4497), .B1(n743), .Y(n4480)
);
OAI22X1TS U5935 ( .A0(n4498), .A1(n4351), .B0(n5369), .B1(n4051), .Y(n4479)
);
OAI31X1TS U5936 ( .A0(n4480), .A1(n4519), .A2(n4479), .B0(n4478), .Y(
mult_x_24_n909) );
OAI22X1TS U5937 ( .A0(n4498), .A1(n4506), .B0(n4647), .B1(n745), .Y(n4483)
);
OAI22X1TS U5938 ( .A0(n4648), .A1(n4443), .B0(n5346), .B1(n4507), .Y(n4482)
);
OAI31X1TS U5939 ( .A0(n4483), .A1(n4513), .A2(n4482), .B0(n4481), .Y(
mult_x_24_n937) );
OAI22X1TS U5940 ( .A0(n4765), .A1(n4778), .B0(n4505), .B1(n738), .Y(n4486)
);
OAI22X1TS U5941 ( .A0(n4509), .A1(n4773), .B0(n4508), .B1(n4827), .Y(n4485)
);
OAI31X1TS U5942 ( .A0(n4486), .A1(n5452), .A2(n4485), .B0(n4484), .Y(
mult_x_24_n880) );
OAI22X1TS U5943 ( .A0(n4765), .A1(n4515), .B0(n4505), .B1(n743), .Y(n4489)
);
OAI22X1TS U5944 ( .A0(n4509), .A1(n4351), .B0(n4508), .B1(n4833), .Y(n4488)
);
OAI31X1TS U5945 ( .A0(n4489), .A1(n4519), .A2(n4488), .B0(n4487), .Y(
mult_x_24_n910) );
OAI22X1TS U5946 ( .A0(n4498), .A1(n4507), .B0(n4490), .B1(n745), .Y(n4493)
);
OAI22X1TS U5947 ( .A0(n4638), .A1(n4443), .B0(n5369), .B1(n4840), .Y(n4492)
);
OAI31X1TS U5948 ( .A0(n4493), .A1(n4513), .A2(n4492), .B0(n4491), .Y(
mult_x_24_n938) );
OAI22X1TS U5949 ( .A0(n5344), .A1(n4515), .B0(n4764), .B1(n743), .Y(n4496)
);
OAI22X1TS U5950 ( .A0(n4508), .A1(n4351), .B0(n4765), .B1(n4833), .Y(n4495)
);
OAI31X1TS U5951 ( .A0(n4496), .A1(n4519), .A2(n4495), .B0(n4494), .Y(
mult_x_24_n911) );
OAI22X1TS U5952 ( .A0(n4508), .A1(n4506), .B0(n4497), .B1(n745), .Y(n4501)
);
OAI22X1TS U5953 ( .A0(n4498), .A1(n4443), .B0(n5369), .B1(n4507), .Y(n4500)
);
OAI31X1TS U5954 ( .A0(n4501), .A1(n4513), .A2(n4500), .B0(n4499), .Y(
mult_x_24_n939) );
OAI22X1TS U5955 ( .A0(n5342), .A1(n4515), .B0(n4771), .B1(n743), .Y(n4504)
);
OAI22X1TS U5956 ( .A0(n4765), .A1(n4351), .B0(n5344), .B1(n4833), .Y(n4503)
);
OAI31X1TS U5957 ( .A0(n4504), .A1(n4519), .A2(n4503), .B0(n4502), .Y(
mult_x_24_n912) );
OAI22X1TS U5958 ( .A0(n4765), .A1(n4506), .B0(n4505), .B1(n745), .Y(n4514)
);
OAI22X1TS U5959 ( .A0(n4509), .A1(n4443), .B0(n4508), .B1(n4507), .Y(n4512)
);
OAI31X1TS U5960 ( .A0(n4514), .A1(n4513), .A2(n4512), .B0(n4511), .Y(
mult_x_24_n940) );
OAI22X1TS U5961 ( .A0(n4779), .A1(n4515), .B0(n4777), .B1(n743), .Y(n4520)
);
OAI22X1TS U5962 ( .A0(n5344), .A1(n4351), .B0(n5342), .B1(n4051), .Y(n4518)
);
OAI31X1TS U5963 ( .A0(n4520), .A1(n4519), .A2(n4518), .B0(n4517), .Y(
mult_x_24_n913) );
NOR3BX1TS U5964 ( .AN(Op_MY[62]), .B(FSM_selector_B[1]), .C(
FSM_selector_B[0]), .Y(n4521) );
XOR2X1TS U5965 ( .A(DP_OP_36J45_124_1029_n42), .B(n4521), .Y(
DP_OP_36J45_124_1029_n18) );
OAI2BB1X1TS U5966 ( .A0N(Op_MY[61]), .A1N(n5389), .B0(n4531), .Y(n4522) );
XOR2X1TS U5967 ( .A(DP_OP_36J45_124_1029_n42), .B(n4522), .Y(
DP_OP_36J45_124_1029_n19) );
OAI2BB1X1TS U5968 ( .A0N(Op_MY[60]), .A1N(n5389), .B0(n4531), .Y(n4523) );
XOR2X1TS U5969 ( .A(DP_OP_36J45_124_1029_n42), .B(n4523), .Y(
DP_OP_36J45_124_1029_n20) );
OAI2BB1X1TS U5970 ( .A0N(Op_MY[59]), .A1N(n5389), .B0(n4531), .Y(n4524) );
XOR2X1TS U5971 ( .A(DP_OP_36J45_124_1029_n42), .B(n4524), .Y(
DP_OP_36J45_124_1029_n21) );
OAI2BB1X1TS U5972 ( .A0N(Op_MY[58]), .A1N(n5389), .B0(n4531), .Y(n4525) );
XOR2X1TS U5973 ( .A(DP_OP_36J45_124_1029_n42), .B(n4525), .Y(
DP_OP_36J45_124_1029_n22) );
OAI2BB1X1TS U5974 ( .A0N(Op_MY[57]), .A1N(n5389), .B0(n4531), .Y(n4526) );
XOR2X1TS U5975 ( .A(DP_OP_36J45_124_1029_n42), .B(n4526), .Y(
DP_OP_36J45_124_1029_n23) );
OAI2BB1X1TS U5976 ( .A0N(Op_MY[56]), .A1N(n5389), .B0(n4531), .Y(n4527) );
XOR2X1TS U5977 ( .A(DP_OP_36J45_124_1029_n42), .B(n4527), .Y(
DP_OP_36J45_124_1029_n24) );
OAI2BB1X1TS U5978 ( .A0N(Op_MY[55]), .A1N(n5389), .B0(n4531), .Y(n4528) );
XOR2X1TS U5979 ( .A(DP_OP_36J45_124_1029_n42), .B(n4528), .Y(
DP_OP_36J45_124_1029_n25) );
OAI2BB1X1TS U5980 ( .A0N(Op_MY[54]), .A1N(n5389), .B0(n4531), .Y(n4529) );
XOR2X1TS U5981 ( .A(DP_OP_36J45_124_1029_n42), .B(n4529), .Y(
DP_OP_36J45_124_1029_n26) );
OAI2BB1X1TS U5982 ( .A0N(Op_MY[53]), .A1N(n5389), .B0(n4531), .Y(n4530) );
XOR2X1TS U5983 ( .A(DP_OP_36J45_124_1029_n42), .B(n4530), .Y(
DP_OP_36J45_124_1029_n27) );
NOR2XLTS U5984 ( .A(FSM_selector_B[1]), .B(Op_MY[52]), .Y(n4532) );
OAI21XLTS U5985 ( .A0(FSM_selector_B[0]), .A1(n4532), .B0(n4531), .Y(n4533)
);
XOR2X1TS U5986 ( .A(DP_OP_36J45_124_1029_n42), .B(n4533), .Y(
DP_OP_36J45_124_1029_n28) );
CMPR32X2TS U5987 ( .A(mult_x_24_n211), .B(mult_x_24_n213), .C(n4534), .CO(
n4849), .S(Sgf_operation_ODD1_right_N50) );
CMPR32X2TS U5988 ( .A(mult_x_24_n217), .B(mult_x_24_n214), .C(n4535), .CO(
n4534), .S(Sgf_operation_ODD1_right_N49) );
CMPR32X2TS U5989 ( .A(mult_x_24_n218), .B(mult_x_24_n221), .C(n4536), .CO(
n4535), .S(Sgf_operation_ODD1_right_N48) );
CMPR32X2TS U5990 ( .A(mult_x_24_n226), .B(mult_x_24_n222), .C(n4537), .CO(
n4536), .S(Sgf_operation_ODD1_right_N47) );
CMPR32X2TS U5991 ( .A(mult_x_24_n232), .B(mult_x_24_n227), .C(n4538), .CO(
n4537), .S(Sgf_operation_ODD1_right_N46) );
CMPR32X2TS U5992 ( .A(mult_x_24_n233), .B(mult_x_24_n238), .C(n4539), .CO(
n4538), .S(Sgf_operation_ODD1_right_N45) );
CMPR32X2TS U5993 ( .A(mult_x_24_n244), .B(mult_x_24_n239), .C(n4540), .CO(
n4539), .S(Sgf_operation_ODD1_right_N44) );
CMPR32X2TS U5994 ( .A(mult_x_24_n251), .B(mult_x_24_n245), .C(n4541), .CO(
n4540), .S(Sgf_operation_ODD1_right_N43) );
CMPR32X2TS U5995 ( .A(mult_x_24_n252), .B(mult_x_24_n258), .C(n4542), .CO(
n4541), .S(Sgf_operation_ODD1_right_N42) );
CMPR32X2TS U5996 ( .A(mult_x_24_n266), .B(mult_x_24_n259), .C(n4543), .CO(
n4542), .S(Sgf_operation_ODD1_right_N41) );
CMPR32X2TS U5997 ( .A(mult_x_24_n275), .B(mult_x_24_n267), .C(n4544), .CO(
n4543), .S(Sgf_operation_ODD1_right_N40) );
CMPR32X2TS U5998 ( .A(mult_x_24_n276), .B(mult_x_24_n284), .C(n4545), .CO(
n4544), .S(Sgf_operation_ODD1_right_N39) );
CMPR32X2TS U5999 ( .A(mult_x_24_n293), .B(mult_x_24_n285), .C(n4546), .CO(
n4545), .S(Sgf_operation_ODD1_right_N38) );
CMPR32X2TS U6000 ( .A(mult_x_24_n303), .B(mult_x_24_n294), .C(n4547), .CO(
n4546), .S(Sgf_operation_ODD1_right_N37) );
CMPR32X2TS U6001 ( .A(mult_x_24_n304), .B(mult_x_24_n313), .C(n4548), .CO(
n4547), .S(Sgf_operation_ODD1_right_N36) );
CMPR32X2TS U6002 ( .A(mult_x_24_n324), .B(mult_x_24_n314), .C(n4549), .CO(
n4548), .S(Sgf_operation_ODD1_right_N35) );
CMPR32X2TS U6003 ( .A(mult_x_24_n336), .B(mult_x_24_n325), .C(n4550), .CO(
n4549), .S(Sgf_operation_ODD1_right_N34) );
CMPR32X2TS U6004 ( .A(mult_x_24_n337), .B(mult_x_24_n348), .C(n4551), .CO(
n4550), .S(Sgf_operation_ODD1_right_N33) );
CMPR32X2TS U6005 ( .A(mult_x_24_n360), .B(mult_x_24_n349), .C(n4552), .CO(
n4551), .S(Sgf_operation_ODD1_right_N32) );
CMPR32X2TS U6006 ( .A(mult_x_24_n361), .B(mult_x_24_n372), .C(n4553), .CO(
n4552), .S(Sgf_operation_ODD1_right_N31) );
CMPR32X2TS U6007 ( .A(mult_x_24_n373), .B(n4555), .C(n4554), .CO(n4553), .S(
Sgf_operation_ODD1_right_N30) );
CMPR32X2TS U6008 ( .A(mult_x_24_n385), .B(mult_x_24_n396), .C(n4556), .CO(
n4554), .S(Sgf_operation_ODD1_right_N29) );
CMPR32X2TS U6009 ( .A(mult_x_24_n397), .B(n4558), .C(n4557), .CO(n4556), .S(
Sgf_operation_ODD1_right_N28) );
CMPR32X2TS U6010 ( .A(n4560), .B(mult_x_24_n409), .C(n4559), .CO(n4557), .S(
Sgf_operation_ODD1_right_N27) );
CMPR32X2TS U6011 ( .A(n4562), .B(mult_x_24_n421), .C(n4561), .CO(n4559), .S(
Sgf_operation_ODD1_right_N26) );
CMPR32X2TS U6012 ( .A(n4564), .B(mult_x_24_n434), .C(n4563), .CO(n4561), .S(
Sgf_operation_ODD1_right_N25) );
CMPR32X2TS U6013 ( .A(n4566), .B(mult_x_24_n447), .C(n4565), .CO(n4563), .S(
Sgf_operation_ODD1_right_N24) );
CMPR32X2TS U6014 ( .A(n4568), .B(mult_x_24_n460), .C(n4567), .CO(n4565), .S(
Sgf_operation_ODD1_right_N23) );
CMPR32X2TS U6015 ( .A(n4570), .B(mult_x_24_n471), .C(n4569), .CO(n4567), .S(
Sgf_operation_ODD1_right_N22) );
CMPR32X2TS U6016 ( .A(n4572), .B(mult_x_24_n482), .C(n4571), .CO(n4569), .S(
Sgf_operation_ODD1_right_N21) );
CMPR32X2TS U6017 ( .A(n4574), .B(mult_x_24_n493), .C(n4573), .CO(n4571), .S(
Sgf_operation_ODD1_right_N20) );
CMPR32X2TS U6018 ( .A(n4576), .B(mult_x_24_n503), .C(n4575), .CO(n4573), .S(
Sgf_operation_ODD1_right_N19) );
CMPR32X2TS U6019 ( .A(n4578), .B(mult_x_24_n513), .C(n4577), .CO(n4575), .S(
Sgf_operation_ODD1_right_N18) );
CMPR32X2TS U6020 ( .A(n4580), .B(mult_x_24_n523), .C(n4579), .CO(n4577), .S(
Sgf_operation_ODD1_right_N17) );
CMPR32X2TS U6021 ( .A(n4582), .B(mult_x_24_n531), .C(n4581), .CO(n4579), .S(
Sgf_operation_ODD1_right_N16) );
CMPR32X2TS U6022 ( .A(n4584), .B(mult_x_24_n539), .C(n4583), .CO(n4581), .S(
Sgf_operation_ODD1_right_N15) );
CMPR32X2TS U6023 ( .A(n4586), .B(mult_x_24_n547), .C(n4585), .CO(n4583), .S(
Sgf_operation_ODD1_right_N14) );
CMPR32X2TS U6024 ( .A(n4588), .B(mult_x_24_n554), .C(n4587), .CO(n4585), .S(
Sgf_operation_ODD1_right_N13) );
CMPR32X2TS U6025 ( .A(mult_x_24_n561), .B(n4590), .C(n4589), .CO(n4587), .S(
Sgf_operation_ODD1_right_N12) );
CMPR32X2TS U6026 ( .A(mult_x_24_n568), .B(n4592), .C(n4591), .CO(n4589), .S(
Sgf_operation_ODD1_right_N11) );
CMPR32X2TS U6027 ( .A(mult_x_24_n573), .B(n4594), .C(n4593), .CO(n4591), .S(
Sgf_operation_ODD1_right_N10) );
CMPR32X2TS U6028 ( .A(mult_x_24_n578), .B(n4596), .C(n4595), .CO(n4593), .S(
Sgf_operation_ODD1_right_N9) );
CMPR32X2TS U6029 ( .A(n4599), .B(n4598), .C(n4597), .CO(n3757), .S(
Sgf_operation_ODD1_right_N5) );
CMPR32X2TS U6030 ( .A(n4602), .B(n4601), .C(n4600), .CO(n4597), .S(
Sgf_operation_ODD1_right_N4) );
CMPR32X2TS U6031 ( .A(n4605), .B(n4604), .C(n4603), .CO(n4600), .S(
Sgf_operation_ODD1_right_N3) );
ADDHXLTS U6032 ( .A(n731), .B(n4606), .CO(n3762), .S(
Sgf_operation_ODD1_right_N0) );
NAND2X1TS U6033 ( .A(Op_MX[26]), .B(Op_MY[18]), .Y(n4618) );
INVX2TS U6034 ( .A(n4618), .Y(n4608) );
CMPR32X2TS U6035 ( .A(n4609), .B(n4702), .C(n4608), .CO(mult_x_24_n223), .S(
mult_x_24_n224) );
NOR2XLTS U6036 ( .A(n4844), .B(n5356), .Y(n4616) );
OAI22X1TS U6037 ( .A0(n740), .A1(n4611), .B0(n4845), .B1(n5356), .Y(n4614)
);
OAI22X1TS U6038 ( .A0(n4655), .A1(n5353), .B0(n3933), .B1(n5379), .Y(n4613)
);
OAI31X1TS U6039 ( .A0(n4614), .A1(n4659), .A2(n4613), .B0(n4612), .Y(n4617)
);
CMPR32X2TS U6040 ( .A(n4618), .B(n4616), .C(n4615), .CO(mult_x_24_n228), .S(
mult_x_24_n229) );
CMPR32X2TS U6041 ( .A(mult_x_24_n240), .B(n4618), .C(n4617), .CO(n4615), .S(
mult_x_24_n235) );
NOR2XLTS U6042 ( .A(n4844), .B(n4621), .Y(n4620) );
NAND2X1TS U6043 ( .A(Op_MX[26]), .B(Op_MY[12]), .Y(n4635) );
INVX2TS U6044 ( .A(n4635), .Y(n4619) );
CMPR32X2TS U6045 ( .A(n4620), .B(n4747), .C(n4619), .CO(mult_x_24_n263), .S(
mult_x_24_n264) );
NOR2XLTS U6046 ( .A(n4844), .B(n5352), .Y(n4627) );
OAI22X1TS U6047 ( .A0(n740), .A1(n4622), .B0(n4654), .B1(n4621), .Y(n4625)
);
OAI22X1TS U6048 ( .A0(n4655), .A1(n4630), .B0(n3933), .B1(n4438), .Y(n4624)
);
OAI31X1TS U6049 ( .A0(n4625), .A1(n4659), .A2(n4624), .B0(n4623), .Y(n4626)
);
CMPR32X2TS U6050 ( .A(n4635), .B(n4627), .C(n4626), .CO(mult_x_24_n271), .S(
mult_x_24_n272) );
OAI22X1TS U6051 ( .A0(n740), .A1(n4629), .B0(n4654), .B1(n5352), .Y(n4633)
);
OAI22X1TS U6052 ( .A0(n4655), .A1(n5349), .B0(n3933), .B1(n4630), .Y(n4632)
);
OAI31X1TS U6053 ( .A0(n4633), .A1(n4659), .A2(n4632), .B0(n4631), .Y(n4634)
);
CMPR32X2TS U6054 ( .A(mult_x_24_n289), .B(n4635), .C(n4634), .CO(
mult_x_24_n280), .S(mult_x_24_n281) );
NAND2X1TS U6055 ( .A(Op_MX[26]), .B(Op_MY[6]), .Y(n4653) );
INVX2TS U6056 ( .A(n4653), .Y(n4637) );
NOR2XLTS U6057 ( .A(n4659), .B(n4638), .Y(n4636) );
CMPR32X2TS U6058 ( .A(n4637), .B(n929), .C(n4636), .CO(mult_x_24_n321), .S(
mult_x_24_n322) );
NOR2XLTS U6059 ( .A(n4844), .B(n5350), .Y(n4645) );
OAI22X1TS U6060 ( .A0(n740), .A1(n4639), .B0(n4654), .B1(n4638), .Y(n4643)
);
OAI22X1TS U6061 ( .A0(n4640), .A1(n4648), .B0(n3933), .B1(n4471), .Y(n4642)
);
OAI31X1TS U6062 ( .A0(n4643), .A1(n4844), .A2(n4642), .B0(n4641), .Y(n4644)
);
CMPR32X2TS U6063 ( .A(n4653), .B(n4645), .C(n4644), .CO(mult_x_24_n332), .S(
mult_x_24_n333) );
OAI22X1TS U6064 ( .A0(n740), .A1(n4647), .B0(n4654), .B1(n5350), .Y(n4651)
);
OAI22X1TS U6065 ( .A0(n4655), .A1(n5346), .B0(n3933), .B1(n4648), .Y(n4650)
);
OAI31X1TS U6066 ( .A0(n4651), .A1(n4844), .A2(n4650), .B0(n4649), .Y(n4652)
);
CMPR32X2TS U6067 ( .A(mult_x_24_n356), .B(n4653), .C(n4652), .CO(
mult_x_24_n344), .S(mult_x_24_n345) );
OAI22X1TS U6068 ( .A0(n740), .A1(n4756), .B0(n4654), .B1(n930), .Y(n4660) );
OAI22X1TS U6069 ( .A0(n4655), .A1(n4779), .B0(n3933), .B1(n4772), .Y(n4658)
);
OAI31X1TS U6070 ( .A0(n4660), .A1(n4659), .A2(n4658), .B0(n4657), .Y(n4673)
);
AOI222X1TS U6071 ( .A0(n4847), .A1(n4749), .B0(n4662), .B1(Op_MY[0]), .C0(
n4661), .C1(n4892), .Y(n4663) );
XNOR2X1TS U6072 ( .A(Op_MX[26]), .B(n4663), .Y(n4679) );
OAI31X1TS U6073 ( .A0(n4665), .A1(Op_MX[26]), .A2(n4755), .B0(n4664), .Y(
n4669) );
OAI22X1TS U6074 ( .A0(n4779), .A1(n4680), .B0(n4777), .B1(n739), .Y(n4668)
);
OAI22X1TS U6075 ( .A0(n4781), .A1(n4097), .B0(n5342), .B1(n4681), .Y(n4667)
);
OAI31X1TS U6076 ( .A0(n4668), .A1(n5451), .A2(n4667), .B0(n4666), .Y(n4688)
);
ADDHXLTS U6077 ( .A(Op_MX[26]), .B(n4669), .CO(n4678), .S(n4687) );
ADDHXLTS U6078 ( .A(n4673), .B(n4672), .CO(mult_x_24_n430), .S(n4691) );
OAI22X1TS U6079 ( .A0(n4781), .A1(n4680), .B0(n4764), .B1(n739), .Y(n4677)
);
OAI22X1TS U6080 ( .A0(n4508), .A1(n4097), .B0(n4765), .B1(n4681), .Y(n4676)
);
OAI31X1TS U6081 ( .A0(n4677), .A1(n5451), .A2(n4676), .B0(n4675), .Y(n4690)
);
ADDHXLTS U6082 ( .A(n4679), .B(n4678), .CO(n4672), .S(n4694) );
OAI22X1TS U6083 ( .A0(n4772), .A1(n4680), .B0(n4771), .B1(n739), .Y(n4685)
);
OAI22X1TS U6084 ( .A0(n4765), .A1(n4097), .B0(n5344), .B1(n4681), .Y(n4684)
);
OAI31X1TS U6085 ( .A0(n4685), .A1(n5451), .A2(n4684), .B0(n4683), .Y(n4693)
);
CMPR32X2TS U6086 ( .A(n4688), .B(n4687), .C(n4686), .CO(n4692), .S(
mult_x_24_n455) );
CMPR32X2TS U6087 ( .A(n4691), .B(n4690), .C(n4689), .CO(mult_x_24_n428), .S(
mult_x_24_n429) );
CMPR32X2TS U6088 ( .A(n4694), .B(n4693), .C(n4692), .CO(n4689), .S(
mult_x_24_n442) );
ADDHXLTS U6089 ( .A(n729), .B(n4695), .CO(n4066), .S(mult_x_24_n490) );
OAI22X1TS U6090 ( .A0(n4755), .A1(n4696), .B0(n4756), .B1(n742), .Y(n4703)
);
OAI22X1TS U6091 ( .A0(n4772), .A1(n4697), .B0(n4779), .B1(n4698), .Y(n4701)
);
OAI31X1TS U6092 ( .A0(n4703), .A1(n4702), .A2(n4701), .B0(n4700), .Y(n4715)
);
AOI222X1TS U6093 ( .A0(n4892), .A1(n4705), .B0(Op_MY[0]), .B1(n4704), .C0(
n4812), .C1(n4749), .Y(n4706) );
XNOR2X1TS U6094 ( .A(n730), .B(n4706), .Y(n4720) );
OAI31X1TS U6095 ( .A0(n4755), .A1(n730), .A2(n4708), .B0(n4707), .Y(n4730)
);
OAI22X1TS U6096 ( .A0(n4755), .A1(n4724), .B0(n4756), .B1(n735), .Y(n4711)
);
OAI22X1TS U6097 ( .A0(n4772), .A1(n4725), .B0(n4779), .B1(n3978), .Y(n4710)
);
OAI31X1TS U6098 ( .A0(n4711), .A1(n959), .A2(n4710), .B0(n4709), .Y(n4732)
);
ADDHXLTS U6099 ( .A(n4715), .B(n4714), .CO(mult_x_24_n499), .S(n4735) );
OAI22X1TS U6100 ( .A0(n4781), .A1(n4724), .B0(n4764), .B1(n735), .Y(n4718)
);
OAI22X1TS U6101 ( .A0(n5345), .A1(n4725), .B0(n4765), .B1(n4815), .Y(n4717)
);
OAI31X1TS U6102 ( .A0(n4718), .A1(n959), .A2(n4717), .B0(n4716), .Y(n4734)
);
ADDHXLTS U6103 ( .A(n4720), .B(n4719), .CO(n4714), .S(n4738) );
OAI22X1TS U6104 ( .A0(n4772), .A1(n4724), .B0(n4771), .B1(n735), .Y(n4723)
);
OAI22X1TS U6105 ( .A0(n4765), .A1(n4725), .B0(n5344), .B1(n4815), .Y(n4722)
);
OAI31X1TS U6106 ( .A0(n4723), .A1(n959), .A2(n4722), .B0(n4721), .Y(n4737)
);
OAI22X1TS U6107 ( .A0(n4779), .A1(n4724), .B0(n4777), .B1(n735), .Y(n4729)
);
OAI22X1TS U6108 ( .A0(n4781), .A1(n4725), .B0(n5342), .B1(n3978), .Y(n4728)
);
OAI31X1TS U6109 ( .A0(n4729), .A1(n959), .A2(n4728), .B0(n4727), .Y(n4741)
);
ADDHXLTS U6110 ( .A(n730), .B(n4730), .CO(n4719), .S(n4740) );
CMPR32X2TS U6111 ( .A(n4735), .B(n4734), .C(n4733), .CO(mult_x_24_n497), .S(
mult_x_24_n498) );
CMPR32X2TS U6112 ( .A(n4738), .B(n4737), .C(n4736), .CO(n4733), .S(
mult_x_24_n508) );
CMPR32X2TS U6113 ( .A(n4741), .B(n4740), .C(n4739), .CO(n4736), .S(
mult_x_24_n518) );
ADDHXLTS U6114 ( .A(DP_OP_169J45_123_4229_n2458), .B(n4742), .CO(n4712), .S(
mult_x_24_n544) );
OAI22X1TS U6115 ( .A0(n3590), .A1(n4743), .B0(n4756), .B1(n737), .Y(n4748)
);
OAI22X1TS U6116 ( .A0(n4772), .A1(n4400), .B0(n4779), .B1(n4013), .Y(n4746)
);
OAI31X1TS U6117 ( .A0(n4748), .A1(n4747), .A2(n4746), .B0(n4745), .Y(n4763)
);
AOI222X1TS U6118 ( .A0(n4892), .A1(n4751), .B0(Op_MY[0]), .B1(n4750), .C0(
n4824), .C1(n4749), .Y(n4752) );
XNOR2X1TS U6119 ( .A(n763), .B(n4752), .Y(n4770) );
OAI31X1TS U6120 ( .A0(n4755), .A1(n763), .A2(n4754), .B0(n4753), .Y(n4786)
);
OAI22X1TS U6121 ( .A0(n3590), .A1(n4778), .B0(n4756), .B1(n738), .Y(n4759)
);
OAI22X1TS U6122 ( .A0(n4772), .A1(n4773), .B0(n4779), .B1(n4041), .Y(n4758)
);
OAI31X1TS U6123 ( .A0(n4759), .A1(n5452), .A2(n4758), .B0(n4757), .Y(n4788)
);
ADDHXLTS U6124 ( .A(n4763), .B(n4762), .CO(mult_x_24_n550), .S(n4791) );
OAI22X1TS U6125 ( .A0(n4781), .A1(n4778), .B0(n4764), .B1(n738), .Y(n4768)
);
OAI22X1TS U6126 ( .A0(n5345), .A1(n4773), .B0(n4765), .B1(n4827), .Y(n4767)
);
OAI31X1TS U6127 ( .A0(n4768), .A1(n5452), .A2(n4767), .B0(n4766), .Y(n4790)
);
ADDHXLTS U6128 ( .A(n4770), .B(n4769), .CO(n4762), .S(n4794) );
OAI22X1TS U6129 ( .A0(n4772), .A1(n4778), .B0(n4771), .B1(n738), .Y(n4776)
);
OAI22X1TS U6130 ( .A0(n4765), .A1(n4773), .B0(n5344), .B1(n4827), .Y(n4775)
);
OAI31X1TS U6131 ( .A0(n4776), .A1(n5452), .A2(n4775), .B0(n4774), .Y(n4793)
);
OAI22X1TS U6132 ( .A0(n4779), .A1(n4778), .B0(n4777), .B1(n738), .Y(n4785)
);
OAI22X1TS U6133 ( .A0(n4781), .A1(n4773), .B0(n5342), .B1(n4041), .Y(n4784)
);
OAI31X1TS U6134 ( .A0(n4785), .A1(n5452), .A2(n4784), .B0(n4783), .Y(n4797)
);
ADDHXLTS U6135 ( .A(n763), .B(n4786), .CO(n4769), .S(n4796) );
CMPR32X2TS U6136 ( .A(n4791), .B(n4790), .C(n4789), .CO(mult_x_24_n548), .S(
mult_x_24_n549) );
CMPR32X2TS U6137 ( .A(n4794), .B(n4793), .C(n4792), .CO(n4789), .S(
mult_x_24_n556) );
CMPR32X2TS U6138 ( .A(n4797), .B(n4796), .C(n4795), .CO(n4792), .S(
mult_x_24_n563) );
ADDHXLTS U6139 ( .A(n4915), .B(n4798), .CO(n4760), .S(mult_x_24_n580) );
CMPR32X2TS U6140 ( .A(n4801), .B(n4800), .C(n4799), .CO(mult_x_24_n581), .S(
n3753) );
AOI2BB2XLTS U6141 ( .B0(n4806), .B1(n4846), .A0N(n852), .A1N(n4804), .Y(
n4802) );
XNOR2X1TS U6142 ( .A(n729), .B(n4802), .Y(mult_x_24_n738) );
OAI22X1TS U6143 ( .A0(n5358), .A1(n4804), .B0(DP_OP_169J45_123_4229_n86),
.B1(n4803), .Y(n4805) );
AOI21X1TS U6144 ( .A0(n4806), .A1(n842), .B0(n4805), .Y(n4807) );
XNOR2X1TS U6145 ( .A(n729), .B(n4807), .Y(mult_x_24_n739) );
AOI2BB2XLTS U6146 ( .B0(n4812), .B1(n4846), .A0N(DP_OP_169J45_123_4229_n86),
.A1N(n4810), .Y(n4808) );
XNOR2X1TS U6147 ( .A(n730), .B(n4808), .Y(mult_x_24_n768) );
OAI22X1TS U6148 ( .A0(n5358), .A1(n4810), .B0(DP_OP_169J45_123_4229_n86),
.B1(n4809), .Y(n4811) );
AOI21X1TS U6149 ( .A0(n4812), .A1(n842), .B0(n4811), .Y(n4813) );
XNOR2X1TS U6150 ( .A(n730), .B(n4813), .Y(mult_x_24_n769) );
AOI2BB2XLTS U6151 ( .B0(n4818), .B1(n4846), .A0N(DP_OP_169J45_123_4229_n86),
.A1N(n4816), .Y(n4814) );
XNOR2X1TS U6152 ( .A(DP_OP_169J45_123_4229_n2458), .B(n4814), .Y(
mult_x_24_n798) );
OAI22X1TS U6153 ( .A0(n5358), .A1(n4816), .B0(DP_OP_169J45_123_4229_n86),
.B1(n4815), .Y(n4817) );
AOI21X1TS U6154 ( .A0(n4818), .A1(n842), .B0(n4817), .Y(n4819) );
XNOR2X1TS U6155 ( .A(DP_OP_169J45_123_4229_n2458), .B(n4819), .Y(
mult_x_24_n799) );
XNOR2X1TS U6156 ( .A(n763), .B(n4820), .Y(mult_x_24_n828) );
OAI22X1TS U6157 ( .A0(n5358), .A1(n4822), .B0(DP_OP_169J45_123_4229_n86),
.B1(n4821), .Y(n4823) );
AOI21X1TS U6158 ( .A0(n4824), .A1(n842), .B0(n4823), .Y(n4825) );
XNOR2X1TS U6159 ( .A(n763), .B(n4825), .Y(mult_x_24_n829) );
XNOR2X1TS U6160 ( .A(n4915), .B(n4826), .Y(mult_x_24_n858) );
OAI22X1TS U6161 ( .A0(n4835), .A1(n4828), .B0(DP_OP_169J45_123_4229_n86),
.B1(n4827), .Y(n4829) );
AOI21X1TS U6162 ( .A0(n4830), .A1(n842), .B0(n4829), .Y(n4831) );
XNOR2X1TS U6163 ( .A(n4915), .B(n4831), .Y(mult_x_24_n859) );
XNOR2X1TS U6164 ( .A(n4914), .B(n4832), .Y(mult_x_24_n888) );
OAI22X1TS U6165 ( .A0(n4835), .A1(n4834), .B0(n853), .B1(n4833), .Y(n4836)
);
AOI21X1TS U6166 ( .A0(n4838), .A1(n842), .B0(n4836), .Y(n4839) );
XNOR2X1TS U6167 ( .A(n4914), .B(n4839), .Y(mult_x_24_n889) );
XNOR2X1TS U6168 ( .A(n4913), .B(n4842), .Y(mult_x_24_n918) );
NOR2XLTS U6169 ( .A(n4844), .B(n5358), .Y(n4855) );
AOI2BB2XLTS U6170 ( .B0(n4847), .B1(n4846), .A0N(n852), .A1N(n4845), .Y(
n4848) );
XNOR2X1TS U6171 ( .A(Op_MX[26]), .B(n4848), .Y(n4854) );
CMPR32X2TS U6172 ( .A(n4850), .B(mult_x_24_n210), .C(n4849), .CO(n4851), .S(
Sgf_operation_ODD1_right_N51) );
CMPR32X2TS U6173 ( .A(n4856), .B(n4855), .C(n4854), .CO(n4859), .S(n4852) );
OAI21XLTS U6174 ( .A0(DP_OP_169J45_123_4229_n86), .A1(n4893), .B0(Op_MX[26]),
.Y(n4857) );
AOI21X1TS U6175 ( .A0(DP_OP_169J45_123_4229_n86), .A1(n4893), .B0(n4857),
.Y(n4858) );
XOR2X1TS U6176 ( .A(n4859), .B(n4858), .Y(n4860) );
XNOR2X1TS U6177 ( .A(n4861), .B(n4860), .Y(Sgf_operation_ODD1_right_N53) );
INVX4TS U6178 ( .A(n979), .Y(n4880) );
MX2X1TS U6179 ( .A(Op_MY[53]), .B(Data_MY[53]), .S0(n4880), .Y(n635) );
MX2X1TS U6180 ( .A(Op_MY[52]), .B(Data_MY[52]), .S0(n4880), .Y(n634) );
MX2X1TS U6181 ( .A(Op_MY[61]), .B(Data_MY[61]), .S0(n4880), .Y(n643) );
MX2X1TS U6182 ( .A(Op_MY[60]), .B(Data_MY[60]), .S0(n4880), .Y(n642) );
MX2X1TS U6183 ( .A(Op_MY[59]), .B(Data_MY[59]), .S0(n4880), .Y(n641) );
MX2X1TS U6184 ( .A(Op_MY[58]), .B(Data_MY[58]), .S0(n4880), .Y(n640) );
MX2X1TS U6185 ( .A(Op_MY[57]), .B(Data_MY[57]), .S0(n4880), .Y(n639) );
MX2X1TS U6186 ( .A(Op_MY[56]), .B(Data_MY[56]), .S0(n4880), .Y(n638) );
MX2X1TS U6187 ( .A(Op_MY[55]), .B(Data_MY[55]), .S0(n4880), .Y(n637) );
MX2X1TS U6188 ( .A(Op_MY[62]), .B(Data_MY[62]), .S0(n4880), .Y(n644) );
MX2X1TS U6189 ( .A(Op_MY[54]), .B(Data_MY[54]), .S0(n4880), .Y(n636) );
MX2X1TS U6190 ( .A(Op_MX[53]), .B(Data_MX[53]), .S0(n4880), .Y(n699) );
MX2X1TS U6191 ( .A(Op_MX[62]), .B(Data_MX[62]), .S0(n4880), .Y(n708) );
MX2X1TS U6192 ( .A(Op_MX[61]), .B(Data_MX[61]), .S0(n4890), .Y(n707) );
MX2X1TS U6193 ( .A(Op_MX[60]), .B(Data_MX[60]), .S0(n4884), .Y(n706) );
MX2X1TS U6194 ( .A(Op_MX[59]), .B(Data_MX[59]), .S0(n4883), .Y(n705) );
MX2X1TS U6195 ( .A(Op_MX[58]), .B(Data_MX[58]), .S0(n4890), .Y(n704) );
MX2X1TS U6196 ( .A(Op_MX[57]), .B(Data_MX[57]), .S0(n4884), .Y(n703) );
MX2X1TS U6197 ( .A(Op_MX[56]), .B(Data_MX[56]), .S0(n4883), .Y(n702) );
MX2X1TS U6198 ( .A(Op_MX[55]), .B(Data_MX[55]), .S0(n4890), .Y(n701) );
MX2X1TS U6199 ( .A(Op_MX[52]), .B(Data_MX[52]), .S0(n4884), .Y(n698) );
MX2X1TS U6200 ( .A(Op_MX[54]), .B(Data_MX[54]), .S0(n4883), .Y(n700) );
NAND2X1TS U6201 ( .A(n4939), .B(n5395), .Y(n710) );
NOR2BX1TS U6202 ( .AN(exp_oper_result[11]), .B(n5395), .Y(S_Oper_A_exp[11])
);
NOR2XLTS U6203 ( .A(n4941), .B(n3465), .Y(n4862) );
BUFX3TS U6204 ( .A(n4862), .Y(n4864) );
MX2X1TS U6205 ( .A(Exp_module_Data_S[10]), .B(exp_oper_result[10]), .S0(
n4864), .Y(n407) );
MX2X1TS U6206 ( .A(Op_MX[62]), .B(exp_oper_result[10]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[10]) );
MX2X1TS U6207 ( .A(Exp_module_Data_S[9]), .B(exp_oper_result[9]), .S0(n4864),
.Y(n408) );
MX2X1TS U6208 ( .A(Op_MX[61]), .B(exp_oper_result[9]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[9]) );
MX2X1TS U6209 ( .A(Exp_module_Data_S[8]), .B(exp_oper_result[8]), .S0(n4864),
.Y(n409) );
MX2X1TS U6210 ( .A(Op_MX[60]), .B(exp_oper_result[8]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[8]) );
MX2X1TS U6211 ( .A(Exp_module_Data_S[7]), .B(exp_oper_result[7]), .S0(n4864),
.Y(n410) );
MX2X1TS U6212 ( .A(Op_MX[59]), .B(exp_oper_result[7]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[7]) );
MX2X1TS U6213 ( .A(Exp_module_Data_S[6]), .B(exp_oper_result[6]), .S0(n4864),
.Y(n411) );
MX2X1TS U6214 ( .A(Op_MX[58]), .B(exp_oper_result[6]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[6]) );
MX2X1TS U6215 ( .A(Exp_module_Data_S[5]), .B(exp_oper_result[5]), .S0(n4864),
.Y(n412) );
MX2X1TS U6216 ( .A(Op_MX[57]), .B(exp_oper_result[5]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[5]) );
MX2X1TS U6217 ( .A(Exp_module_Data_S[4]), .B(exp_oper_result[4]), .S0(n4864),
.Y(n413) );
MX2X1TS U6218 ( .A(Op_MX[56]), .B(exp_oper_result[4]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[4]) );
MX2X1TS U6219 ( .A(Exp_module_Data_S[3]), .B(exp_oper_result[3]), .S0(n4864),
.Y(n414) );
MX2X1TS U6220 ( .A(Op_MX[55]), .B(exp_oper_result[3]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[3]) );
MX2X1TS U6221 ( .A(Exp_module_Data_S[2]), .B(exp_oper_result[2]), .S0(n4864),
.Y(n415) );
MX2X1TS U6222 ( .A(Op_MX[54]), .B(exp_oper_result[2]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[2]) );
MX2X1TS U6223 ( .A(Exp_module_Data_S[1]), .B(exp_oper_result[1]), .S0(n4864),
.Y(n416) );
MX2X1TS U6224 ( .A(Op_MX[53]), .B(exp_oper_result[1]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[1]) );
MX2X1TS U6225 ( .A(Exp_module_Data_S[0]), .B(exp_oper_result[0]), .S0(n4864),
.Y(n417) );
MX2X1TS U6226 ( .A(Op_MX[52]), .B(exp_oper_result[0]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[0]) );
MX2X1TS U6227 ( .A(Exp_module_Data_S[11]), .B(exp_oper_result[11]), .S0(
n4864), .Y(n406) );
XNOR2X1TS U6228 ( .A(DP_OP_36J45_124_1029_n1), .B(n4870), .Y(n4865) );
MX2X1TS U6229 ( .A(n4865), .B(Exp_module_Overflow_flag_A), .S0(n5199), .Y(
n405) );
NAND4XLTS U6230 ( .A(Exp_module_Data_S[3]), .B(Exp_module_Data_S[2]), .C(
Exp_module_Data_S[1]), .D(Exp_module_Data_S[0]), .Y(n4866) );
NAND4BXLTS U6231 ( .AN(n4866), .B(Exp_module_Data_S[6]), .C(
Exp_module_Data_S[5]), .D(Exp_module_Data_S[4]), .Y(n4867) );
NAND4BXLTS U6232 ( .AN(n4867), .B(Exp_module_Data_S[9]), .C(
Exp_module_Data_S[8]), .D(Exp_module_Data_S[7]), .Y(n4868) );
NAND3BXLTS U6233 ( .AN(Exp_module_Data_S[10]), .B(n4941), .C(n4868), .Y(
n4869) );
OAI22X1TS U6234 ( .A0(Exp_module_Data_S[11]), .A1(n4869), .B0(n4941), .B1(
n5398), .Y(n352) );
AO22XLTS U6235 ( .A0(n4881), .A1(Data_MY[63]), .B0(n4886), .B1(Op_MY[63]),
.Y(n715) );
OAI22X1TS U6236 ( .A0(zero_flag), .A1(n4870), .B0(P_Sgf[105]), .B1(n4874),
.Y(n4871) );
AOI2BB1XLTS U6237 ( .A0N(n4872), .A1N(n4871), .B0(n4873), .Y(n713) );
AOI21X1TS U6238 ( .A0(FS_Module_state_reg[2]), .A1(n4873), .B0(
DP_OP_36J45_124_1029_n42), .Y(n4876) );
NAND3XLTS U6239 ( .A(n4876), .B(n4875), .C(n4874), .Y(n711) );
AO22XLTS U6240 ( .A0(n4881), .A1(Data_MX[50]), .B0(n4888), .B1(Op_MX[50]),
.Y(n696) );
AO22XLTS U6241 ( .A0(n4881), .A1(Data_MX[48]), .B0(n4886), .B1(Op_MX[48]),
.Y(n694) );
AO22XLTS U6242 ( .A0(n4881), .A1(Data_MX[43]), .B0(n4886), .B1(n843), .Y(
n689) );
AO22XLTS U6243 ( .A0(n4881), .A1(Data_MX[42]), .B0(n4886), .B1(Op_MX[42]),
.Y(n688) );
AO22XLTS U6244 ( .A0(n4881), .A1(Data_MX[41]), .B0(n4888), .B1(Op_MX[41]),
.Y(n687) );
BUFX3TS U6245 ( .A(n4888), .Y(n4877) );
AO22XLTS U6246 ( .A0(n4881), .A1(Data_MX[38]), .B0(n4877), .B1(Op_MX[38]),
.Y(n684) );
AO22XLTS U6247 ( .A0(n4884), .A1(Data_MX[26]), .B0(n4879), .B1(Op_MX[26]),
.Y(n672) );
AO22XLTS U6248 ( .A0(n4883), .A1(Data_MX[23]), .B0(n4879), .B1(n729), .Y(
n669) );
AO22XLTS U6249 ( .A0(n4884), .A1(Data_MX[20]), .B0(n4879), .B1(n730), .Y(
n666) );
BUFX4TS U6250 ( .A(n4877), .Y(n4882) );
AO22XLTS U6251 ( .A0(n4890), .A1(Data_MX[17]), .B0(n4882), .B1(
DP_OP_169J45_123_4229_n2458), .Y(n663) );
AO22XLTS U6252 ( .A0(n4890), .A1(Data_MX[14]), .B0(n4882), .B1(n763), .Y(
n660) );
AO22XLTS U6253 ( .A0(n4884), .A1(Data_MX[11]), .B0(n4882), .B1(n4915), .Y(
n657) );
AO22XLTS U6254 ( .A0(n4883), .A1(Data_MX[8]), .B0(n4882), .B1(n4914), .Y(
n654) );
BUFX4TS U6255 ( .A(n4879), .Y(n4885) );
AO22XLTS U6256 ( .A0(n4890), .A1(Data_MX[5]), .B0(n4885), .B1(n4913), .Y(
n651) );
AO22XLTS U6257 ( .A0(n4881), .A1(Data_MX[2]), .B0(n4885), .B1(n731), .Y(n648) );
AO22XLTS U6258 ( .A0(n4884), .A1(Data_MX[0]), .B0(n4885), .B1(Op_MX[0]), .Y(
n646) );
CLKINVX6TS U6259 ( .A(n979), .Y(n4887) );
AO22XLTS U6260 ( .A0(n4884), .A1(Data_MY[46]), .B0(n4882), .B1(Op_MY[46]),
.Y(n628) );
AO22XLTS U6261 ( .A0(n4884), .A1(Data_MY[44]), .B0(n4882), .B1(Op_MY[44]),
.Y(n626) );
AO22XLTS U6262 ( .A0(n4890), .A1(Data_MY[38]), .B0(n4885), .B1(Op_MY[38]),
.Y(n620) );
AO22XLTS U6263 ( .A0(n4884), .A1(Data_MY[32]), .B0(n4885), .B1(Op_MY[32]),
.Y(n614) );
AO22XLTS U6264 ( .A0(n4887), .A1(Data_MY[24]), .B0(n979), .B1(n4893), .Y(
n606) );
AO22XLTS U6265 ( .A0(n4883), .A1(Data_MY[23]), .B0(n4888), .B1(Op_MY[23]),
.Y(n605) );
AO22XLTS U6266 ( .A0(n4887), .A1(Data_MY[21]), .B0(n4886), .B1(Op_MY[21]),
.Y(n603) );
AO22XLTS U6267 ( .A0(n4887), .A1(Data_MY[20]), .B0(n4886), .B1(Op_MY[20]),
.Y(n602) );
AO22XLTS U6268 ( .A0(n4887), .A1(Data_MY[16]), .B0(n4886), .B1(Op_MY[16]),
.Y(n598) );
AO22XLTS U6269 ( .A0(n4887), .A1(Data_MY[15]), .B0(n4886), .B1(Op_MY[15]),
.Y(n597) );
AO22XLTS U6270 ( .A0(n4887), .A1(Data_MY[14]), .B0(n4886), .B1(Op_MY[14]),
.Y(n596) );
AO22XLTS U6271 ( .A0(n4887), .A1(Data_MY[12]), .B0(n4886), .B1(Op_MY[12]),
.Y(n594) );
AO22XLTS U6272 ( .A0(n4887), .A1(Data_MY[9]), .B0(n4886), .B1(Op_MY[9]), .Y(
n591) );
AO22XLTS U6273 ( .A0(n4887), .A1(Data_MY[8]), .B0(n4886), .B1(Op_MY[8]), .Y(
n590) );
AO22XLTS U6274 ( .A0(n4887), .A1(Data_MY[6]), .B0(n4886), .B1(Op_MY[6]), .Y(
n588) );
AO22XLTS U6275 ( .A0(n4890), .A1(Data_MY[3]), .B0(n4888), .B1(Op_MY[3]), .Y(
n585) );
AO22XLTS U6276 ( .A0(n4883), .A1(Data_MY[1]), .B0(n4888), .B1(n4892), .Y(
n583) );
AO22XLTS U6277 ( .A0(n4884), .A1(Data_MY[0]), .B0(n979), .B1(Op_MY[0]), .Y(
n582) );
NOR4X1TS U6278 ( .A(Op_MY[6]), .B(Op_MY[7]), .C(Op_MY[8]), .D(Op_MY[9]), .Y(
n4911) );
OR4X2TS U6279 ( .A(Op_MY[10]), .B(Op_MY[11]), .C(Op_MY[12]), .D(Op_MY[13]),
.Y(n4891) );
NOR4X1TS U6280 ( .A(Op_MY[0]), .B(n4892), .C(Op_MY[53]), .D(n4891), .Y(n4910) );
NOR4X1TS U6281 ( .A(Op_MY[18]), .B(Op_MY[19]), .C(Op_MY[20]), .D(Op_MY[21]),
.Y(n4896) );
NOR4X1TS U6282 ( .A(Op_MY[22]), .B(Op_MY[23]), .C(n4893), .D(Op_MY[25]), .Y(
n4895) );
NAND4XLTS U6283 ( .A(n4897), .B(n4896), .C(n4895), .D(n4894), .Y(n4908) );
NAND4XLTS U6284 ( .A(n4901), .B(n4900), .C(n4899), .D(n4898), .Y(n4907) );
NOR4X1TS U6285 ( .A(Op_MY[60]), .B(Op_MY[59]), .C(Op_MY[58]), .D(Op_MY[57]),
.Y(n4903) );
NOR4X1TS U6286 ( .A(Op_MY[56]), .B(Op_MY[55]), .C(Op_MY[62]), .D(Op_MY[54]),
.Y(n4902) );
NAND4XLTS U6287 ( .A(n4905), .B(n4904), .C(n4903), .D(n4902), .Y(n4906) );
NOR3XLTS U6288 ( .A(n4908), .B(n4907), .C(n4906), .Y(n4909) );
NAND4XLTS U6289 ( .A(n4912), .B(n4911), .C(n4910), .D(n4909), .Y(n4942) );
OR4X2TS U6290 ( .A(Op_MX[10]), .B(n4915), .C(Op_MX[12]), .D(Op_MX[13]), .Y(
n4916) );
NAND4XLTS U6291 ( .A(n4923), .B(n4922), .C(n4921), .D(n4920), .Y(n4934) );
NAND4XLTS U6292 ( .A(n4927), .B(n4926), .C(n4925), .D(n4924), .Y(n4933) );
NOR4X1TS U6293 ( .A(Op_MX[60]), .B(Op_MX[59]), .C(Op_MX[58]), .D(Op_MX[57]),
.Y(n4929) );
NOR4X1TS U6294 ( .A(Op_MX[56]), .B(Op_MX[55]), .C(Op_MX[52]), .D(Op_MX[54]),
.Y(n4928) );
NAND4XLTS U6295 ( .A(n4931), .B(n4930), .C(n4929), .D(n4928), .Y(n4932) );
NOR3XLTS U6296 ( .A(n4934), .B(n4933), .C(n4932), .Y(n4935) );
NAND4XLTS U6297 ( .A(n4938), .B(n4937), .C(n4936), .D(n4935), .Y(n4940) );
AOI32X1TS U6298 ( .A0(n4942), .A1(n4941), .A2(n4940), .B0(n5396), .B1(n4939),
.Y(n581) );
AOI32X1TS U6299 ( .A0(n4946), .A1(n4945), .A2(n4944), .B0(n5397), .B1(n4943),
.Y(n580) );
AO22XLTS U6300 ( .A0(n5047), .A1(Sgf_normalized_result[0]), .B0(n5037), .B1(
Add_result[0]), .Y(n579) );
BUFX4TS U6301 ( .A(n753), .Y(n5043) );
AO22XLTS U6302 ( .A0(n5047), .A1(Sgf_normalized_result[1]), .B0(n5043), .B1(
Add_result[1]), .Y(n578) );
INVX3TS U6303 ( .A(n753), .Y(n5011) );
AOI2BB2XLTS U6304 ( .B0(n5011), .B1(Sgf_normalized_result[2]), .A0N(
Add_result[2]), .A1N(n5024), .Y(n577) );
INVX3TS U6305 ( .A(n753), .Y(n5038) );
NAND2X1TS U6306 ( .A(n841), .B(Sgf_normalized_result[2]), .Y(n4948) );
OAI211XLTS U6307 ( .A0(n841), .A1(Sgf_normalized_result[2]), .B0(n5038),
.C0(n4948), .Y(n4949) );
OAI2BB1X1TS U6308 ( .A0N(Add_result[3]), .A1N(n753), .B0(n4949), .Y(n576) );
AOI31XLTS U6309 ( .A0(n841), .A1(Sgf_normalized_result[4]), .A2(
Sgf_normalized_result[2]), .B0(n4951), .Y(n4950) );
AOI2BB2XLTS U6310 ( .B0(n5011), .B1(n4950), .A0N(Add_result[4]), .A1N(n5047),
.Y(n575) );
OAI21XLTS U6311 ( .A0(n4951), .A1(n5363), .B0(n4953), .Y(n4952) );
OAI211XLTS U6312 ( .A0(Sgf_normalized_result[6]), .A1(n4953), .B0(n5038),
.C0(n4955), .Y(n4954) );
OAI2BB1X1TS U6313 ( .A0N(Add_result[6]), .A1N(n753), .B0(n4954), .Y(n573) );
AOI21X1TS U6314 ( .A0(n5364), .A1(n4955), .B0(n4957), .Y(n4956) );
OAI211XLTS U6315 ( .A0(Sgf_normalized_result[8]), .A1(n4957), .B0(n5038),
.C0(n4959), .Y(n4958) );
OAI2BB1X1TS U6316 ( .A0N(Add_result[8]), .A1N(n5037), .B0(n4958), .Y(n571)
);
AOI21X1TS U6317 ( .A0(n5365), .A1(n4959), .B0(n4961), .Y(n4960) );
OAI211XLTS U6318 ( .A0(Sgf_normalized_result[10]), .A1(n4961), .B0(n5038),
.C0(n4963), .Y(n4962) );
OAI2BB1X1TS U6319 ( .A0N(Add_result[10]), .A1N(n5037), .B0(n4962), .Y(n569)
);
AOI21X1TS U6320 ( .A0(n5366), .A1(n4963), .B0(n4965), .Y(n4964) );
OAI211XLTS U6321 ( .A0(Sgf_normalized_result[12]), .A1(n4965), .B0(n5038),
.C0(n4967), .Y(n4966) );
OAI2BB1X1TS U6322 ( .A0N(Add_result[12]), .A1N(n5037), .B0(n4966), .Y(n567)
);
AOI21X1TS U6323 ( .A0(n5367), .A1(n4967), .B0(n4969), .Y(n4968) );
OAI211XLTS U6324 ( .A0(Sgf_normalized_result[14]), .A1(n4969), .B0(n5038),
.C0(n4971), .Y(n4970) );
OAI2BB1X1TS U6325 ( .A0N(Add_result[14]), .A1N(n5037), .B0(n4970), .Y(n565)
);
AOI21X1TS U6326 ( .A0(n5368), .A1(n4971), .B0(n4973), .Y(n4972) );
OAI211XLTS U6327 ( .A0(Sgf_normalized_result[16]), .A1(n4973), .B0(n5011),
.C0(n4975), .Y(n4974) );
OAI2BB1X1TS U6328 ( .A0N(Add_result[16]), .A1N(n5037), .B0(n4974), .Y(n563)
);
AOI21X1TS U6329 ( .A0(n5370), .A1(n4975), .B0(n4977), .Y(n4976) );
OAI211XLTS U6330 ( .A0(Sgf_normalized_result[18]), .A1(n4977), .B0(n5011),
.C0(n4979), .Y(n4978) );
OAI2BB1X1TS U6331 ( .A0N(Add_result[18]), .A1N(n5037), .B0(n4978), .Y(n561)
);
AOI21X1TS U6332 ( .A0(n5373), .A1(n4979), .B0(n4981), .Y(n4980) );
OAI211XLTS U6333 ( .A0(Sgf_normalized_result[20]), .A1(n4981), .B0(n5011),
.C0(n4983), .Y(n4982) );
OAI2BB1X1TS U6334 ( .A0N(Add_result[20]), .A1N(n5037), .B0(n4982), .Y(n559)
);
AOI21X1TS U6335 ( .A0(n5375), .A1(n4983), .B0(n4985), .Y(n4984) );
OAI211XLTS U6336 ( .A0(Sgf_normalized_result[22]), .A1(n4985), .B0(n5011),
.C0(n4987), .Y(n4986) );
OAI2BB1X1TS U6337 ( .A0N(Add_result[22]), .A1N(n5043), .B0(n4986), .Y(n557)
);
AOI21X1TS U6338 ( .A0(n5376), .A1(n4987), .B0(n4990), .Y(n4988) );
OAI211XLTS U6339 ( .A0(Sgf_normalized_result[24]), .A1(n4990), .B0(n5011),
.C0(n4989), .Y(n4991) );
OAI2BB1X1TS U6340 ( .A0N(Add_result[24]), .A1N(n5043), .B0(n4991), .Y(n555)
);
OAI211XLTS U6341 ( .A0(Sgf_normalized_result[26]), .A1(n4993), .B0(n5011),
.C0(n4992), .Y(n4994) );
OAI2BB1X1TS U6342 ( .A0N(Add_result[26]), .A1N(n5037), .B0(n4994), .Y(n553)
);
OAI211XLTS U6343 ( .A0(Sgf_normalized_result[28]), .A1(n4995), .B0(n5011),
.C0(n4997), .Y(n4996) );
OAI2BB1X1TS U6344 ( .A0N(Add_result[28]), .A1N(n753), .B0(n4996), .Y(n551)
);
AOI21X1TS U6345 ( .A0(n5381), .A1(n4997), .B0(n4999), .Y(n4998) );
OAI211XLTS U6346 ( .A0(Sgf_normalized_result[30]), .A1(n4999), .B0(n5011),
.C0(n5001), .Y(n5000) );
OAI2BB1X1TS U6347 ( .A0N(Add_result[30]), .A1N(n5043), .B0(n5000), .Y(n549)
);
AOI21X1TS U6348 ( .A0(n5382), .A1(n5001), .B0(n5003), .Y(n5002) );
OAI211XLTS U6349 ( .A0(Sgf_normalized_result[32]), .A1(n5003), .B0(n5011),
.C0(n5005), .Y(n5004) );
OAI2BB1X1TS U6350 ( .A0N(Add_result[32]), .A1N(n5043), .B0(n5004), .Y(n547)
);
AOI21X1TS U6351 ( .A0(n5383), .A1(n5005), .B0(n5007), .Y(n5006) );
OAI211XLTS U6352 ( .A0(Sgf_normalized_result[34]), .A1(n5007), .B0(n5011),
.C0(n5009), .Y(n5008) );
OAI2BB1X1TS U6353 ( .A0N(Add_result[34]), .A1N(n5043), .B0(n5008), .Y(n545)
);
AOI21X1TS U6354 ( .A0(n5384), .A1(n5009), .B0(n5012), .Y(n5010) );
OAI211XLTS U6355 ( .A0(Sgf_normalized_result[36]), .A1(n5012), .B0(n5011),
.C0(n5014), .Y(n5013) );
OAI2BB1X1TS U6356 ( .A0N(Add_result[36]), .A1N(n5043), .B0(n5013), .Y(n543)
);
AOI21X1TS U6357 ( .A0(n5385), .A1(n5014), .B0(n5016), .Y(n5015) );
OAI211XLTS U6358 ( .A0(Sgf_normalized_result[38]), .A1(n5016), .B0(n5038),
.C0(n5018), .Y(n5017) );
OAI2BB1X1TS U6359 ( .A0N(Add_result[38]), .A1N(n5043), .B0(n5017), .Y(n541)
);
AOI21X1TS U6360 ( .A0(n5386), .A1(n5018), .B0(n5020), .Y(n5019) );
OAI211XLTS U6361 ( .A0(Sgf_normalized_result[40]), .A1(n5020), .B0(n5038),
.C0(n5022), .Y(n5021) );
OAI2BB1X1TS U6362 ( .A0N(Add_result[40]), .A1N(n753), .B0(n5021), .Y(n539)
);
AOI21X1TS U6363 ( .A0(n5387), .A1(n5022), .B0(n5026), .Y(n5023) );
OAI211XLTS U6364 ( .A0(Sgf_normalized_result[42]), .A1(n5026), .B0(n5038),
.C0(n5025), .Y(n5027) );
OAI2BB1X1TS U6365 ( .A0N(Add_result[42]), .A1N(n5037), .B0(n5027), .Y(n537)
);
OAI211XLTS U6366 ( .A0(Sgf_normalized_result[44]), .A1(n5029), .B0(n5038),
.C0(n5028), .Y(n5030) );
OAI2BB1X1TS U6367 ( .A0N(Add_result[44]), .A1N(n5037), .B0(n5030), .Y(n535)
);
OAI211XLTS U6368 ( .A0(Sgf_normalized_result[46]), .A1(n5032), .B0(n5038),
.C0(n5031), .Y(n5033) );
OAI2BB1X1TS U6369 ( .A0N(Add_result[46]), .A1N(n5037), .B0(n5033), .Y(n533)
);
OAI211XLTS U6370 ( .A0(Sgf_normalized_result[48]), .A1(n5035), .B0(n5038),
.C0(n5034), .Y(n5036) );
OAI2BB1X1TS U6371 ( .A0N(Add_result[48]), .A1N(n5037), .B0(n5036), .Y(n531)
);
NAND2X1TS U6372 ( .A(Sgf_normalized_result[50]), .B(n5039), .Y(n5041) );
OAI2BB1X1TS U6373 ( .A0N(Add_result[50]), .A1N(n753), .B0(n5040), .Y(n529)
);
NOR2X2TS U6374 ( .A(n5394), .B(n5041), .Y(n5044) );
AOI211X1TS U6375 ( .A0(n5394), .A1(n5041), .B0(n5044), .C0(n753), .Y(n5042)
);
AO21XLTS U6376 ( .A0(Add_result[51]), .A1(n5043), .B0(n5042), .Y(n528) );
AOI21X1TS U6377 ( .A0(n5044), .A1(Sgf_normalized_result[52]), .B0(n753), .Y(
n5046) );
OAI2BB1X1TS U6378 ( .A0N(Add_result[52]), .A1N(n753), .B0(n5045), .Y(n527)
);
CMPR32X2TS U6379 ( .A(n909), .B(Sgf_operation_ODD1_Q_left[29]), .C(n5078),
.CO(n5076), .S(n5079) );
BUFX3TS U6380 ( .A(n5198), .Y(n5190) );
ADDFHX4TS U6381 ( .A(n5082), .B(Sgf_operation_ODD1_Q_left[11]), .CI(n5081),
.CO(n3695), .S(n5083) );
AO22XLTS U6382 ( .A0(n5127), .A1(P_Sgf[65]), .B0(n5190), .B1(n5083), .Y(n486) );
BUFX3TS U6383 ( .A(n5198), .Y(n5155) );
AO22XLTS U6384 ( .A0(n5127), .A1(P_Sgf[64]), .B0(n5155), .B1(n5086), .Y(n485) );
AO22XLTS U6385 ( .A0(n5127), .A1(P_Sgf[63]), .B0(n5111), .B1(n5089), .Y(n484) );
AO22XLTS U6386 ( .A0(n5127), .A1(P_Sgf[62]), .B0(n5190), .B1(n5092), .Y(n483) );
ADDFHX4TS U6387 ( .A(n5094), .B(Sgf_operation_ODD1_Q_left[7]), .CI(n5093),
.CO(n5090), .S(n5095) );
AO22XLTS U6388 ( .A0(n5127), .A1(P_Sgf[61]), .B0(n5155), .B1(n5095), .Y(n482) );
AO22XLTS U6389 ( .A0(n5127), .A1(P_Sgf[60]), .B0(n734), .B1(n5098), .Y(n481)
);
CMPR32X2TS U6390 ( .A(n5100), .B(Sgf_operation_ODD1_Q_left[5]), .C(n5099),
.CO(n5096), .S(n5101) );
AO22XLTS U6391 ( .A0(n5127), .A1(P_Sgf[59]), .B0(n734), .B1(n5101), .Y(n480)
);
BUFX3TS U6392 ( .A(n5198), .Y(n5196) );
AO22XLTS U6393 ( .A0(n5127), .A1(P_Sgf[58]), .B0(n5196), .B1(n5104), .Y(n479) );
ADDFHX4TS U6394 ( .A(n5106), .B(Sgf_operation_ODD1_Q_left[3]), .CI(n5105),
.CO(n5102), .S(n5107) );
AO22XLTS U6395 ( .A0(n5127), .A1(P_Sgf[57]), .B0(n5111), .B1(n5107), .Y(n478) );
CMPR32X2TS U6396 ( .A(n5109), .B(Sgf_operation_ODD1_Q_left[2]), .C(n5108),
.CO(n5105), .S(n5110) );
AO22XLTS U6397 ( .A0(n5127), .A1(P_Sgf[56]), .B0(n5111), .B1(n5110), .Y(n477) );
AO22XLTS U6398 ( .A0(n5127), .A1(P_Sgf[54]), .B0(n5190), .B1(n5114), .Y(n475) );
AO22XLTS U6399 ( .A0(n5127), .A1(P_Sgf[53]), .B0(n5155), .B1(n5117), .Y(n474) );
AO22XLTS U6400 ( .A0(n5127), .A1(P_Sgf[51]), .B0(n734), .B1(n5120), .Y(n472)
);
AO22XLTS U6401 ( .A0(n5127), .A1(P_Sgf[50]), .B0(n5155), .B1(n5123), .Y(n471) );
CMPR32X2TS U6402 ( .A(n5125), .B(Sgf_operation_ODD1_Q_right[49]), .C(n5124),
.CO(n5121), .S(n5126) );
AO22XLTS U6403 ( .A0(n5127), .A1(P_Sgf[49]), .B0(n5155), .B1(n5126), .Y(n470) );
INVX4TS U6404 ( .A(n734), .Y(n5180) );
AO22XLTS U6405 ( .A0(n5180), .A1(P_Sgf[48]), .B0(n5155), .B1(n5130), .Y(n469) );
AO22XLTS U6406 ( .A0(n5180), .A1(P_Sgf[47]), .B0(n5155), .B1(n5133), .Y(n468) );
AO22XLTS U6407 ( .A0(n5180), .A1(P_Sgf[46]), .B0(n5155), .B1(n5136), .Y(n467) );
CMPR32X2TS U6408 ( .A(n5138), .B(Sgf_operation_ODD1_Q_right[45]), .C(n5137),
.CO(n5134), .S(n5139) );
AO22XLTS U6409 ( .A0(n5180), .A1(P_Sgf[45]), .B0(n5155), .B1(n5139), .Y(n466) );
AO22XLTS U6410 ( .A0(n5180), .A1(P_Sgf[44]), .B0(n5155), .B1(n5142), .Y(n465) );
ADDFHX4TS U6411 ( .A(n5144), .B(Sgf_operation_ODD1_Q_right[43]), .CI(n5143),
.CO(n5140), .S(n5145) );
AO22XLTS U6412 ( .A0(n5180), .A1(P_Sgf[43]), .B0(n5155), .B1(n5145), .Y(n464) );
AO22XLTS U6413 ( .A0(n5180), .A1(P_Sgf[42]), .B0(n5155), .B1(n5148), .Y(n463) );
AO22XLTS U6414 ( .A0(n5180), .A1(P_Sgf[41]), .B0(n5155), .B1(n5151), .Y(n462) );
AO22XLTS U6415 ( .A0(n5180), .A1(P_Sgf[40]), .B0(n5155), .B1(n5154), .Y(n461) );
CMPR32X2TS U6416 ( .A(n5157), .B(Sgf_operation_ODD1_Q_right[39]), .C(n5156),
.CO(n5152), .S(n5158) );
AO22XLTS U6417 ( .A0(n5180), .A1(P_Sgf[39]), .B0(n5190), .B1(n5158), .Y(n460) );
AO22XLTS U6418 ( .A0(n5180), .A1(P_Sgf[38]), .B0(n5190), .B1(n5161), .Y(n459) );
AO22XLTS U6419 ( .A0(n5180), .A1(P_Sgf[37]), .B0(n5190), .B1(n5164), .Y(n458) );
CMPR32X2TS U6420 ( .A(n5166), .B(Sgf_operation_ODD1_Q_right[36]), .C(n5165),
.CO(n5162), .S(n5167) );
AO22XLTS U6421 ( .A0(n5180), .A1(P_Sgf[36]), .B0(n5190), .B1(n5167), .Y(n457) );
AO22XLTS U6422 ( .A0(n5180), .A1(P_Sgf[35]), .B0(n5190), .B1(n5170), .Y(n456) );
AO22XLTS U6423 ( .A0(n5180), .A1(P_Sgf[34]), .B0(n5190), .B1(n5173), .Y(n455) );
AO22XLTS U6424 ( .A0(n5180), .A1(P_Sgf[33]), .B0(n5190), .B1(n5176), .Y(n454) );
CMPR32X2TS U6425 ( .A(n5178), .B(Sgf_operation_ODD1_Q_right[32]), .C(n5177),
.CO(n5174), .S(n5179) );
AO22XLTS U6426 ( .A0(n5180), .A1(P_Sgf[32]), .B0(n5190), .B1(n5179), .Y(n453) );
INVX4TS U6427 ( .A(n734), .Y(n5197) );
AO22XLTS U6428 ( .A0(n5197), .A1(P_Sgf[31]), .B0(n5190), .B1(n5183), .Y(n452) );
AO22XLTS U6429 ( .A0(n5197), .A1(P_Sgf[30]), .B0(n5190), .B1(n5186), .Y(n451) );
AO22XLTS U6430 ( .A0(n5197), .A1(P_Sgf[29]), .B0(n5190), .B1(n5189), .Y(n450) );
CMPR32X2TS U6431 ( .A(n5192), .B(Sgf_operation_ODD1_Q_right[28]), .C(n5191),
.CO(n5187), .S(n5193) );
AO22XLTS U6432 ( .A0(n5197), .A1(P_Sgf[28]), .B0(n5196), .B1(n5193), .Y(n449) );
ADDHXLTS U6433 ( .A(Sgf_operation_ODD1_Q_right[27]), .B(n5194), .CO(n5191),
.S(n5195) );
AO22XLTS U6434 ( .A0(n5197), .A1(P_Sgf[27]), .B0(n5196), .B1(n5195), .Y(n448) );
AO22XLTS U6435 ( .A0(n5197), .A1(P_Sgf[26]), .B0(n5198), .B1(
Sgf_operation_Result[26]), .Y(n447) );
AO22XLTS U6436 ( .A0(n5197), .A1(P_Sgf[25]), .B0(n5196), .B1(
Sgf_operation_Result[25]), .Y(n446) );
AO22XLTS U6437 ( .A0(n5197), .A1(P_Sgf[24]), .B0(n5196), .B1(
Sgf_operation_Result[24]), .Y(n445) );
AO22XLTS U6438 ( .A0(n5197), .A1(P_Sgf[23]), .B0(n5196), .B1(
Sgf_operation_Result[23]), .Y(n444) );
AO22XLTS U6439 ( .A0(n5197), .A1(P_Sgf[22]), .B0(n5196), .B1(
Sgf_operation_Result[22]), .Y(n443) );
AO22XLTS U6440 ( .A0(n5197), .A1(P_Sgf[21]), .B0(n5196), .B1(
Sgf_operation_Result[21]), .Y(n442) );
AO22XLTS U6441 ( .A0(n5197), .A1(P_Sgf[20]), .B0(n5196), .B1(
Sgf_operation_Result[20]), .Y(n441) );
AO22XLTS U6442 ( .A0(n5197), .A1(P_Sgf[19]), .B0(n5196), .B1(
Sgf_operation_Result[19]), .Y(n440) );
AO22XLTS U6443 ( .A0(n5197), .A1(P_Sgf[18]), .B0(n5196), .B1(
Sgf_operation_Result[18]), .Y(n439) );
AO22XLTS U6444 ( .A0(n5197), .A1(P_Sgf[17]), .B0(n5198), .B1(
Sgf_operation_Result[17]), .Y(n438) );
AO22XLTS U6445 ( .A0(n5197), .A1(P_Sgf[16]), .B0(n5196), .B1(
Sgf_operation_Result[16]), .Y(n437) );
AO22XLTS U6446 ( .A0(n5197), .A1(P_Sgf[15]), .B0(n5198), .B1(
Sgf_operation_Result[15]), .Y(n436) );
AO22XLTS U6447 ( .A0(n5199), .A1(P_Sgf[14]), .B0(n5198), .B1(
Sgf_operation_Result[14]), .Y(n435) );
AO22XLTS U6448 ( .A0(n5199), .A1(P_Sgf[13]), .B0(n5198), .B1(
Sgf_operation_Result[13]), .Y(n434) );
AO22XLTS U6449 ( .A0(n5199), .A1(P_Sgf[12]), .B0(n5198), .B1(
Sgf_operation_Result[12]), .Y(n433) );
AO22XLTS U6450 ( .A0(n5199), .A1(P_Sgf[11]), .B0(n5198), .B1(
Sgf_operation_Result[11]), .Y(n432) );
AO22XLTS U6451 ( .A0(n5199), .A1(P_Sgf[10]), .B0(n5198), .B1(
Sgf_operation_Result[10]), .Y(n431) );
AO22XLTS U6452 ( .A0(n5199), .A1(P_Sgf[9]), .B0(n5198), .B1(
Sgf_operation_Result[9]), .Y(n430) );
AO22XLTS U6453 ( .A0(n5199), .A1(P_Sgf[8]), .B0(n5198), .B1(
Sgf_operation_Result[8]), .Y(n429) );
AO22XLTS U6454 ( .A0(n5199), .A1(P_Sgf[7]), .B0(n5198), .B1(
Sgf_operation_Result[7]), .Y(n428) );
AO22XLTS U6455 ( .A0(n5199), .A1(P_Sgf[6]), .B0(n5198), .B1(
Sgf_operation_Result[6]), .Y(n427) );
AO22XLTS U6456 ( .A0(n5199), .A1(P_Sgf[5]), .B0(n734), .B1(
Sgf_operation_Result[5]), .Y(n426) );
AO22XLTS U6457 ( .A0(n5199), .A1(P_Sgf[4]), .B0(n734), .B1(
Sgf_operation_Result[4]), .Y(n425) );
AO22XLTS U6458 ( .A0(n5199), .A1(P_Sgf[3]), .B0(n734), .B1(
Sgf_operation_Result[3]), .Y(n424) );
AO22XLTS U6459 ( .A0(n5199), .A1(P_Sgf[2]), .B0(n5196), .B1(
Sgf_operation_Result[2]), .Y(n423) );
AO22XLTS U6460 ( .A0(n5199), .A1(P_Sgf[1]), .B0(n5196), .B1(
Sgf_operation_Result[1]), .Y(n422) );
AO22XLTS U6461 ( .A0(n5199), .A1(P_Sgf[0]), .B0(n734), .B1(
Sgf_operation_Result[0]), .Y(n421) );
AO22XLTS U6462 ( .A0(Sgf_normalized_result[0]), .A1(n5202), .B0(
final_result_ieee[0]), .B1(n5201), .Y(n351) );
BUFX4TS U6463 ( .A(n5205), .Y(n5203) );
AO22XLTS U6464 ( .A0(Sgf_normalized_result[1]), .A1(n5202), .B0(
final_result_ieee[1]), .B1(n5203), .Y(n350) );
AO22XLTS U6465 ( .A0(Sgf_normalized_result[2]), .A1(n5202), .B0(
final_result_ieee[2]), .B1(n5203), .Y(n349) );
AO22XLTS U6466 ( .A0(n841), .A1(n5202), .B0(final_result_ieee[3]), .B1(n5205), .Y(n348) );
AO22XLTS U6467 ( .A0(Sgf_normalized_result[4]), .A1(n5202), .B0(
final_result_ieee[4]), .B1(n5203), .Y(n347) );
AO22XLTS U6468 ( .A0(Sgf_normalized_result[5]), .A1(n5202), .B0(
final_result_ieee[5]), .B1(n5203), .Y(n346) );
AO22XLTS U6469 ( .A0(Sgf_normalized_result[6]), .A1(n5202), .B0(
final_result_ieee[6]), .B1(n5205), .Y(n345) );
AO22XLTS U6470 ( .A0(Sgf_normalized_result[7]), .A1(n5202), .B0(
final_result_ieee[7]), .B1(n5203), .Y(n344) );
AO22XLTS U6471 ( .A0(Sgf_normalized_result[8]), .A1(n5202), .B0(
final_result_ieee[8]), .B1(n5205), .Y(n343) );
AO22XLTS U6472 ( .A0(Sgf_normalized_result[9]), .A1(n5202), .B0(
final_result_ieee[9]), .B1(n5203), .Y(n342) );
AO22XLTS U6473 ( .A0(Sgf_normalized_result[10]), .A1(n5202), .B0(
final_result_ieee[10]), .B1(n5205), .Y(n341) );
AO22XLTS U6474 ( .A0(Sgf_normalized_result[11]), .A1(n5202), .B0(
final_result_ieee[11]), .B1(n5201), .Y(n340) );
AO22XLTS U6475 ( .A0(Sgf_normalized_result[12]), .A1(n5202), .B0(
final_result_ieee[12]), .B1(n5205), .Y(n339) );
AO22XLTS U6476 ( .A0(Sgf_normalized_result[13]), .A1(n5204), .B0(
final_result_ieee[13]), .B1(n5203), .Y(n338) );
AO22XLTS U6477 ( .A0(Sgf_normalized_result[14]), .A1(n5204), .B0(
final_result_ieee[14]), .B1(n5203), .Y(n337) );
AO22XLTS U6478 ( .A0(Sgf_normalized_result[15]), .A1(n5204), .B0(
final_result_ieee[15]), .B1(n5203), .Y(n336) );
AO22XLTS U6479 ( .A0(Sgf_normalized_result[16]), .A1(n5204), .B0(
final_result_ieee[16]), .B1(n5203), .Y(n335) );
AO22XLTS U6480 ( .A0(Sgf_normalized_result[17]), .A1(n5204), .B0(
final_result_ieee[17]), .B1(n5203), .Y(n334) );
AO22XLTS U6481 ( .A0(Sgf_normalized_result[18]), .A1(n5204), .B0(
final_result_ieee[18]), .B1(n5203), .Y(n333) );
AO22XLTS U6482 ( .A0(Sgf_normalized_result[19]), .A1(n5204), .B0(
final_result_ieee[19]), .B1(n5203), .Y(n332) );
AO22XLTS U6483 ( .A0(Sgf_normalized_result[20]), .A1(n5204), .B0(
final_result_ieee[20]), .B1(n5203), .Y(n331) );
AO22XLTS U6484 ( .A0(Sgf_normalized_result[21]), .A1(n5204), .B0(
final_result_ieee[21]), .B1(n5203), .Y(n330) );
AO22XLTS U6485 ( .A0(Sgf_normalized_result[22]), .A1(n5204), .B0(
final_result_ieee[22]), .B1(n5203), .Y(n329) );
AO22XLTS U6486 ( .A0(Sgf_normalized_result[23]), .A1(n5204), .B0(
final_result_ieee[23]), .B1(n5203), .Y(n328) );
AO22XLTS U6487 ( .A0(Sgf_normalized_result[24]), .A1(n5204), .B0(
final_result_ieee[24]), .B1(n5203), .Y(n327) );
AO22XLTS U6488 ( .A0(Sgf_normalized_result[25]), .A1(n5204), .B0(
final_result_ieee[25]), .B1(n5203), .Y(n326) );
AO22XLTS U6489 ( .A0(Sgf_normalized_result[26]), .A1(n5206), .B0(
final_result_ieee[26]), .B1(n5203), .Y(n325) );
AO22XLTS U6490 ( .A0(Sgf_normalized_result[27]), .A1(n5204), .B0(
final_result_ieee[27]), .B1(n5205), .Y(n324) );
AO22XLTS U6491 ( .A0(Sgf_normalized_result[28]), .A1(n5206), .B0(
final_result_ieee[28]), .B1(n5205), .Y(n323) );
AO22XLTS U6492 ( .A0(Sgf_normalized_result[29]), .A1(n5204), .B0(
final_result_ieee[29]), .B1(n5205), .Y(n322) );
AO22XLTS U6493 ( .A0(Sgf_normalized_result[30]), .A1(n5206), .B0(
final_result_ieee[30]), .B1(n5205), .Y(n321) );
AO22XLTS U6494 ( .A0(Sgf_normalized_result[31]), .A1(n5204), .B0(
final_result_ieee[31]), .B1(n5205), .Y(n320) );
AO22XLTS U6495 ( .A0(Sgf_normalized_result[32]), .A1(n5206), .B0(
final_result_ieee[32]), .B1(n5205), .Y(n319) );
AO22XLTS U6496 ( .A0(Sgf_normalized_result[33]), .A1(n5204), .B0(
final_result_ieee[33]), .B1(n5205), .Y(n318) );
AO22XLTS U6497 ( .A0(Sgf_normalized_result[34]), .A1(n5206), .B0(
final_result_ieee[34]), .B1(n5205), .Y(n317) );
AO22XLTS U6498 ( .A0(Sgf_normalized_result[35]), .A1(n5204), .B0(
final_result_ieee[35]), .B1(n5205), .Y(n316) );
AO22XLTS U6499 ( .A0(Sgf_normalized_result[36]), .A1(n5206), .B0(
final_result_ieee[36]), .B1(n5205), .Y(n315) );
AO22XLTS U6500 ( .A0(Sgf_normalized_result[37]), .A1(n5204), .B0(
final_result_ieee[37]), .B1(n5205), .Y(n314) );
AO22XLTS U6501 ( .A0(Sgf_normalized_result[38]), .A1(n5206), .B0(
final_result_ieee[38]), .B1(n5205), .Y(n313) );
AO22XLTS U6502 ( .A0(Sgf_normalized_result[40]), .A1(n5206), .B0(
final_result_ieee[40]), .B1(n5205), .Y(n311) );
AO22XLTS U6503 ( .A0(Sgf_normalized_result[42]), .A1(n5206), .B0(
final_result_ieee[42]), .B1(n5201), .Y(n309) );
AO22XLTS U6504 ( .A0(Sgf_normalized_result[44]), .A1(n5206), .B0(
final_result_ieee[44]), .B1(n5201), .Y(n307) );
AO22XLTS U6505 ( .A0(Sgf_normalized_result[46]), .A1(n5206), .B0(
final_result_ieee[46]), .B1(n5201), .Y(n305) );
AO22XLTS U6506 ( .A0(Sgf_normalized_result[48]), .A1(n5206), .B0(
final_result_ieee[48]), .B1(n5201), .Y(n303) );
AO22XLTS U6507 ( .A0(Sgf_normalized_result[50]), .A1(n5206), .B0(
final_result_ieee[50]), .B1(n5201), .Y(n301) );
OA22X1TS U6508 ( .A0(n5207), .A1(final_result_ieee[52]), .B0(
exp_oper_result[0]), .B1(n5200), .Y(n299) );
OA22X1TS U6509 ( .A0(n5207), .A1(final_result_ieee[53]), .B0(
exp_oper_result[1]), .B1(n5200), .Y(n298) );
OA22X1TS U6510 ( .A0(n5207), .A1(final_result_ieee[54]), .B0(
exp_oper_result[2]), .B1(n5200), .Y(n297) );
OA22X1TS U6511 ( .A0(n5207), .A1(final_result_ieee[55]), .B0(
exp_oper_result[3]), .B1(n5200), .Y(n296) );
OA22X1TS U6512 ( .A0(n5207), .A1(final_result_ieee[56]), .B0(
exp_oper_result[4]), .B1(n5200), .Y(n295) );
OA22X1TS U6513 ( .A0(n5207), .A1(final_result_ieee[57]), .B0(
exp_oper_result[5]), .B1(n5200), .Y(n294) );
OA22X1TS U6514 ( .A0(n5207), .A1(final_result_ieee[58]), .B0(
exp_oper_result[6]), .B1(n5200), .Y(n293) );
OA22X1TS U6515 ( .A0(n5207), .A1(final_result_ieee[59]), .B0(
exp_oper_result[7]), .B1(n5200), .Y(n292) );
OA22X1TS U6516 ( .A0(n5207), .A1(final_result_ieee[60]), .B0(
exp_oper_result[8]), .B1(n5200), .Y(n291) );
OA22X1TS U6517 ( .A0(n5207), .A1(final_result_ieee[61]), .B0(
exp_oper_result[9]), .B1(n5200), .Y(n290) );
OA22X1TS U6518 ( .A0(n5207), .A1(final_result_ieee[62]), .B0(
exp_oper_result[10]), .B1(n5200), .Y(n289) );
initial $sdf_annotate("FPU_Multiplication_Function_ASIC_fpu_syn_constraints_clk40.tcl_KOA_2STAGE_syn.sdf");
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: rx_port_channel_gate.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Provides cross domain synchronization for the CHNL_RX*
// signals between the CHNL_CLK and CLK domains.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module rx_port_channel_gate #(
parameter C_DATA_WIDTH = 9'd64
)
(
input RST,
input CLK,
input RX, // Channel read signal (CLK)
output RX_RECVD, // Channel read received signal (CLK)
output RX_ACK_RECVD, // Channel read acknowledgment received signal (CLK)
input RX_LAST, // Channel last read (CLK)
input [31:0] RX_LEN, // Channel read length (CLK)
input [30:0] RX_OFF, // Channel read offset (CLK)
output [31:0] RX_CONSUMED, // Channel words consumed (CLK)
input [C_DATA_WIDTH-1:0] RD_DATA, // FIFO read data (CHNL_CLK)
input RD_EMPTY, // FIFO is empty (CHNL_CLK)
output RD_EN, // FIFO read enable (CHNL_CLK)
input CHNL_CLK, // Channel read clock
output CHNL_RX, // Channel read receive signal (CHNL_CLK)
input CHNL_RX_ACK, // Channle read received signal (CHNL_CLK)
output CHNL_RX_LAST, // Channel last read (CHNL_CLK)
output [31:0] CHNL_RX_LEN, // Channel read length (CHNL_CLK)
output [30:0] CHNL_RX_OFF, // Channel read offset (CHNL_CLK)
output [C_DATA_WIDTH-1:0] CHNL_RX_DATA, // Channel read data (CHNL_CLK)
output CHNL_RX_DATA_VALID, // Channel read data valid (CHNL_CLK)
input CHNL_RX_DATA_REN // Channel read data has been recieved (CHNL_CLK)
);
reg rAckd=0, _rAckd=0;
reg rChnlRxAck=0, _rChnlRxAck=0;
reg [31:0] rConsumed=0, _rConsumed=0;
reg [31:0] rConsumedStable=0, _rConsumedStable=0;
reg [31:0] rConsumedSample=0, _rConsumedSample=0;
reg rCountRead=0, _rCountRead=0;
wire wCountRead;
wire wCountStable;
wire wDataRead = (CHNL_RX_DATA_REN & CHNL_RX_DATA_VALID);
assign RX_CONSUMED = rConsumedSample;
assign RD_EN = CHNL_RX_DATA_REN;
assign CHNL_RX_LAST = RX_LAST;
assign CHNL_RX_LEN = RX_LEN;
assign CHNL_RX_OFF = RX_OFF;
assign CHNL_RX_DATA = RD_DATA;
assign CHNL_RX_DATA_VALID = !RD_EMPTY;
// Buffer the input signals that come from outside the rx_port.
always @ (posedge CHNL_CLK) begin
rChnlRxAck <= #1 (RST ? 1'd0 : _rChnlRxAck);
end
always @ (*) begin
_rChnlRxAck = CHNL_RX_ACK;
end
// Signal receive into the channel domain.
cross_domain_signal rxSig (
.CLK_A(CLK),
.CLK_A_SEND(RX),
.CLK_A_RECV(RX_RECVD),
.CLK_B(CHNL_CLK),
.CLK_B_RECV(CHNL_RX),
.CLK_B_SEND(CHNL_RX)
);
// Signal acknowledgment of receive into the CLK domain.
syncff rxAckSig (.CLK(CLK), .IN_ASYNC(rAckd), .OUT_SYNC(RX_ACK_RECVD));
// Capture CHNL_RX_ACK and reset only after the CHNL_RX drops.
always @ (posedge CHNL_CLK) begin
rAckd <= #1 (RST ? 1'd0 : _rAckd);
end
always @ (*) begin
_rAckd = (CHNL_RX & (rAckd | rChnlRxAck));
end
// Count the words consumed by the channel and pass it into the CLK domain.
always @ (posedge CHNL_CLK) begin
rConsumed <= #1 _rConsumed;
rConsumedStable <= #1 _rConsumedStable;
rCountRead <= #1 (RST ? 1'd0 : _rCountRead);
end
always @ (*) begin
_rConsumed = (!CHNL_RX ? 0 : rConsumed + (wDataRead*(C_DATA_WIDTH/32)));
_rConsumedStable = (wCountRead | rCountRead ? rConsumedStable : rConsumed);
_rCountRead = !wCountRead;
end
always @ (posedge CLK) begin
rConsumedSample <= #1 _rConsumedSample;
end
always @ (*) begin
_rConsumedSample = (wCountStable ? rConsumedStable : rConsumedSample);
end
// Determine when it's safe to update the count in the CLK domain.
cross_domain_signal countSync (
.CLK_A(CHNL_CLK),
.CLK_A_SEND(rCountRead),
.CLK_A_RECV(wCountRead),
.CLK_B(CLK),
.CLK_B_RECV(wCountStable),
.CLK_B_SEND(wCountStable)
);
endmodule
|
(******************************************************************************)
(* Copyright (c) 2015 Daniel Lustig & Yatin Manerkar, Princeton University *)
(* *)
(* Permission is hereby granted, free of charge, to any person obtaining a *)
(* copy of this software and associated documentation files (the "Software"), *)
(* to deal in the Software without restriction, including without limitation *)
(* the rights to use, copy, modify, merge, publish, distribute, sublicense, *)
(* and/or sell copies of the Software, and to permit persons to whom the *)
(* Software is furnished to do so, subject to the following conditions: *)
(* *)
(* The above copyright notice and this permission notice shall be included in *)
(* all copies or substantial portions of the Software. *)
(* *)
(* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *)
(* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *)
(* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *)
(* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *)
(* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *)
(* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *)
(* DEALINGS IN THE SOFTWARE. *)
(******************************************************************************)
Require Import List.
Require Import Arith.
Require Import String.
Require Import PipeGraph.Util.
Require Import PipeGraph.StringUtil.
Require Import PipeGraph.Instruction.
Require Import PipeGraph.Processor.
Require Import PipeGraph.Graph.
Require Import PipeGraph.Debug.
Import ListNotations.
Open Scope string_scope.
(** For [SameData], the argument order matters! If [x] is a [RMW] [Microop],
then look at the written data. If [y] is a [RMW] [Microop], look at the read
data. *)
Definition SameData
(x y : Microop)
: bool :=
let xd := match x with
| mkMicroop _ _ _ (Read _ d) => Some d
| mkMicroop _ _ _ (Write _ d) => Some d
| mkMicroop _ _ _ (RMWRead _ d) => Some d
| mkMicroop _ _ _ (RMWWrite _ d) => Some d
| _ => None
end in
let yd := match y with
| mkMicroop _ _ _ (Read _ d) => Some d
| mkMicroop _ _ _ (Write _ d) => Some d
| mkMicroop _ _ _ (RMWRead _ d) => Some d
| mkMicroop _ _ _ (RMWWrite _ d) => Some d
| _ => None
end in
match (xd, yd) with
| (Some d1, Some d2) => beq_nat d1 d2
| _ => false
end.
Definition ReadsBetweenFilter
(uop : Microop)
(loc : Location)
(x : GraphNode)
: bool :=
(* the [SameData] order matters: (fst x) is the source, and uop is the dest. *)
andb
(andb (beq_loc loc (snd x)) (negb (beq_uop uop (fst x))))
(andb (SameAddress uop (fst x)) (SameData (fst x) uop)).
Definition ReadsBetween
(a b c : Location)
(name : string)
(vicls : list (Microop * ViCL))
(nodes : list GraphNode)
(edges : list GraphEdge)
(uop : Microop)
: option (list (list GraphEdge)) :=
let candidates_a := filter (ReadsBetweenFilter uop a) nodes in
let candidates_c := filter (ReadsBetweenFilter uop c) nodes in
let candidates := PairNodesByMicroop candidates_a candidates_c [] in
let f x := [(fst x, (uop, b), name); ((uop, b), snd x, name)] in
Some (Map f candidates).
Definition ReadsBetweenSLRFilter
(a b : Microop)
(loc : Location)
(x : GraphNode)
: bool :=
let valid :=
andb (beq_loc loc (snd x))
(andb (blt_nat (globalID a) (globalID (fst x)))
(blt_nat (globalID (fst x)) (globalID b))) in
let valid := Println valid ["RBSLRFilter: "; stringOfNat (globalID a);
" < "; stringOfNat (globalID (fst x)); " < "; stringOfNat (globalID b);
"?"] in
match fst x with
| mkMicroop _ _ _ (Read _ _) => valid
| mkMicroop _ _ _ (Write _ _) => valid
| mkMicroop _ _ _ (RMWRead _ _) => valid
| mkMicroop _ _ _ (RMWWrite _ _) => valid
| _ => false
end.
Definition ReadsBetweenSLRHelper
(a b c : Location)
(name : string)
(nodes : list GraphNode)
(uop : Microop)
(r : list GraphEdge)
: option (list (list GraphEdge)) :=
let candidates_a := filter (ReadsBetweenFilter uop a) nodes in
let candidates_c := filter (ReadsBetweenFilter uop c) nodes in
let candidates := PairNodesByMicroop candidates_a candidates_c [] in
let candidates := Println candidates ["RBSLR: ";
stringOfNat (List.length candidates); " candidates"] in
let f x :=
let nodes_in_between :=
filter (ReadsBetweenSLRFilter (fst (snd x)) uop b) nodes in
let nodes_in_between := Println nodes_in_between ["RBSLR: ";
stringOfNat (List.length nodes_in_between); " nodes in between"] in
let g y := (y, snd x, name) in
(fst x, (uop, b), name) :: ((uop, b), snd x, name) ::
Map g nodes_in_between in
Some (Map f candidates).
Definition ReadsBetweenSLR
(a b c : Location)
(name : string)
(vicls : list (Microop * ViCL))
(nodes : list GraphNode)
(edges : list GraphEdge)
(uop : Microop)
: option (list (list GraphEdge)) :=
ReadsBetweenSLRHelper a b c name nodes uop [].
Definition SourcedFromFilter
(uop : Microop)
(loc : Location)
(x : GraphNode)
: bool :=
(* the [SameData] order matters: (fst x) is the source, and uop is the dest. *)
andb
(andb (beq_loc loc (snd x)) (negb (beq_uop uop (fst x))))
(andb (SameAddress uop (fst x)) (SameData (fst x) uop)).
Definition SourcedFromHelper
(a b : Location)
(name : string)
(nodes : list GraphNode)
(uop : Microop)
(r : list GraphEdge)
: option (list (list GraphEdge)) :=
let candidates := filter (SourcedFromFilter uop a) nodes in
let f x := [(x, (uop, b), name)] in
Some (Map f candidates).
Definition SourcedFrom
(a b : Location)
(name : string)
(vicls : list (Microop * ViCL))
(nodes : list GraphNode)
(edges : list GraphEdge)
(uop : Microop)
: option (list (list GraphEdge)) :=
SourcedFromHelper a b name nodes uop [].
Definition SourcedAtLevelFilter
(uop : Microop)
(stage : nat)
(x : GraphNode)
: bool :=
(* the [SameData] order matters: (fst x) is the source, and uop is the dest. *)
andb
(andb (beq_nat stage (snd (snd x))) (negb (beq_uop uop (fst x))))
(andb (SameAddress uop (fst x)) (SameData (fst x) uop)).
Definition SourcedAtLevelHelper
(a : nat)
(b : Location)
(name : string)
(nodes : list GraphNode)
(uop : Microop)
(r : list GraphEdge)
: option (list (list GraphEdge)) :=
let candidates := filter (SourcedAtLevelFilter uop a) nodes in
let f x := [(x, (uop, b), name)] in
Some (Map f candidates).
Definition SourcedAtLevel
(a : nat)
(b : Location)
(name : string)
(vicls : list (Microop * ViCL))
(nodes : list GraphNode)
(edges : list GraphEdge)
(uop : Microop)
: option (list (list GraphEdge)) :=
SourcedAtLevelHelper a b name nodes uop [].
(* A rearrangement of the parameters of SourcedAtLevel for easier partial application. *)
Definition SourcedAtLevel2
(b : Location)
(name : string)
(nodes : list GraphNode)
(uop : Microop)
(a : nat)
: option (list (list GraphEdge)) :=
SourcedAtLevelHelper a b name nodes uop [].
Fixpoint ConvertToOptList
(a : list GraphEdge)
(a' : list (list GraphEdge))
: option (list (list GraphEdge)) :=
match a with
| [] => Some a'
| h::t => ConvertToOptList t ([h]::a')
end.
Fixpoint KeepFirstHelper
(a : list GraphEdge)
(b : list GraphEdge)
: list GraphEdge :=
let f x y := match y with
| ((uop, loc), n2, str) => beq_uop x uop
end in
match a with
| [] => b
| h::t => match h with
| ((uop, _), _, _) => match (find (f uop) b) with
| None => KeepFirstHelper t (h::b)
| _ => KeepFirstHelper t b
end
end
end.
Fixpoint KeepFirst
(a : list (list GraphEdge))
(b : list GraphEdge)
: list GraphEdge :=
match a with
| [] => b
| h::t => match h with
| [] => KeepFirst t b
| _ => KeepFirst t (KeepFirstHelper h b)
end
end.
Definition SourcedAtLevels
(a : list nat)
(b : Location)
(name : string)
(nodes : list GraphNode)
(uop : Microop)
: list GraphEdge :=
let le := Map (SourcedAtLevel2 b name nodes uop) a in
let f x := match x with
| Some x' => fold_left (app_rev (A:=_)) x' []
(* This should never happen, as SourcedAtLevel2 always returns Some <list>.*)
| _ => Warning ([]) ["SourcedAtLevel2 didn't return Some <list>."]
end in
let le' := Map f le in
KeepFirst le' [].
Definition FlushAllAddressesFilter
(uop : Microop)
(loc : Location)
(x : GraphNode)
: bool :=
let valid :=
andb (beq_loc loc (snd x)) (blt_nat (globalID (fst x)) (globalID uop)) in
match fst x with
| mkMicroop _ _ _ (Read _ _) => valid
| mkMicroop _ _ _ (Write _ _) => valid
| mkMicroop _ _ _ (RMWRead _ _) => valid
| mkMicroop _ _ _ (RMWWrite _ _) => valid
| _ => false
end.
Definition FlushAllAddressesHelper
(a b : Location)
(name : string)
(nodes : list GraphNode)
(uop : Microop)
(r : list GraphEdge)
: option (list (list GraphEdge)) :=
let candidates := filter (FlushAllAddressesFilter uop a) nodes in
let f x := (x, (uop, b), name) in
match candidates with
| [] => None
| _ => Some [(Map f candidates)]
end.
Definition FlushAllAddresses
(a b : Location)
(name : string)
(vicls : list (Microop * ViCL))
(nodes : list GraphNode)
(edges : list GraphEdge)
(uop : Microop)
: option (list (list GraphEdge)) :=
FlushAllAddressesHelper a b name nodes uop [].
Definition FlushSameAddressFilter
(uop : Microop)
(loc : Location)
(x : GraphNode)
: bool :=
andb (andb (beq_loc loc (snd x)) (SameAddress uop (fst x)))
(blt_nat (globalID (fst x)) (globalID uop)).
Definition FlushSameAddressHelper
(a b : Location)
(name : string)
(nodes : list GraphNode)
(uop : Microop)
(r : list GraphEdge)
: option (list (list GraphEdge)) :=
let candidates := filter (FlushSameAddressFilter uop a) nodes in
let f x := [(x, (uop, b), name)] in
match candidates with
| [] => None
| _ => Some (Map f candidates)
end.
Definition FlushSameAddress
(a b : Location)
(name : string)
(vicls : list (Microop * ViCL))
(nodes : list GraphNode)
(edges : list GraphEdge)
(uop : Microop)
: option (list (list GraphEdge)) :=
FlushSameAddressHelper a b name nodes uop [].
Definition FlushBeforeLaterFilter
(uop : Microop)
(loc : Location)
(x : GraphNode)
: bool :=
let valid :=
andb (beq_loc loc (snd x)) (blt_nat (globalID uop) (globalID (fst x))) in
match fst x with
| mkMicroop _ _ _ (Read _ _) => valid
| mkMicroop _ _ _ (Write _ _) => valid
| mkMicroop _ _ _ (RMWRead _ _) => valid
| mkMicroop _ _ _ (RMWWrite _ _) => valid
| _ => false
end.
Definition FlushBeforeLaterHelper
(a b : Location)
(name : string)
(nodes : list GraphNode)
(uop : Microop)
(r : list GraphEdge)
: option (list (list GraphEdge)) :=
let candidates := filter (FlushBeforeLaterFilter uop b) nodes in
let f x := ((uop, a), x, name) in
match candidates with
| [] => None
| _ => Some [(Map f candidates)]
end.
Definition FlushBeforeLater
(a b : Location)
(name : string)
(vicls : list (Microop * ViCL))
(nodes : list GraphNode)
(edges : list GraphEdge)
(uop : Microop)
: option (list (list GraphEdge)) :=
FlushBeforeLaterHelper a b name nodes uop [].
Fixpoint ReadsBeforeAllHelper
(vicls : list (Microop * ViCL))
(node : GraphNode)
(adj : AdjacencyList)
: option (list GraphEdge) :=
match vicls with
| (h, SWViCL _ c _ _)::t =>
if andb (SameAddress h (fst node)) (negb (beq_uop h (fst node)))
then match AdjacencyListFind adj (h, c) node with
| Some _ => Println (Some []) ["Store "; stringOfNat (globalID h);
" is visible to instruction "; stringOfNat (globalID (fst node));
" even though it should read from the initial condition"]
| None => ReadsBeforeAllHelper t node adj
end
else ReadsBeforeAllHelper t node adj
| _::t => ReadsBeforeAllHelper t node adj
| [] => None
end.
Definition ReadsBeforeAll
(vicl_c : Location)
(name : string)
(vicls : list (Microop * ViCL))
(nodes : list GraphNode)
(edges : list GraphEdge)
(uop : Microop)
: option (list GraphEdge) :=
match TransitiveClosure edges with
| TC adj => ReadsBeforeAllHelper vicls (uop, vicl_c) adj
| TCError _ => Println None ["ReadsBeforeAll: already cyclic"]
end.
Definition ReadsZero
(name : string)
(vicls : list (Microop * ViCL))
(nodes : list GraphNode)
(edges : list GraphEdge)
(uop : Microop)
: option (list (list GraphEdge)) :=
match uop with
| mkMicroop _ _ _ (Read _ 0) => None
| mkMicroop _ _ _ (RMWRead _ 0) => None
| _ => Println (Some [])
["Read returns non-zero; doesn't read from initial state"]
end.
Fixpoint LaterSWViCLsForOtherViCL
(uop : Microop)
(c : Location)
(adj : AdjacencyList)
(vicls : list (Microop * ViCL))
(latest : option GraphNode)
(later : list GraphNode)
: option (list GraphNode) :=
match vicls with
| h::t =>
let h := Println h
["LaterSWViCLsForOtherViCL: "; stringOfNat (globalID uop); " @ ";
stringOfNat (snd c); ", "; stringOfNat (globalID (fst h)); " @ ";
stringOfNat (snd (ViCLCreate (snd h)))] in
if andb (SameAddress uop (fst h))
(orb (negb (beq_uop uop (fst h))) (negb (beq_loc c (ViCLCreate (snd h)))))
then
match snd h with
| SWViCL _ h_c _ _ =>
let h_c := (fst h, h_c) in
match AdjacencyListFind adj h_c (uop, c) with
| Some _ =>
match latest with
| Some l =>
match AdjacencyListFind adj h_c l with
| Some _ =>
let uop := Println uop [tab; "earlier than previous latest"] in
LaterSWViCLsForOtherViCL uop c adj t latest later
| None =>
let uop := Println uop [tab; "new latest"] in
LaterSWViCLsForOtherViCL uop c adj t (Some h_c) later
end
| None =>
let uop := Println uop [tab; "no previous latest; now this is latest"] in
LaterSWViCLsForOtherViCL uop c adj t (Some h_c) later
end
| None =>
let uop := Println uop [tab; "not earlier"] in
LaterSWViCLsForOtherViCL uop c adj t latest (h_c :: later)
end
| _ =>
let uop := Println uop [tab; "Not a SWViCL"] in
LaterSWViCLsForOtherViCL uop c adj t latest later
end
else
let uop := Println uop [tab; "Different address and/or same ViCL"] in
LaterSWViCLsForOtherViCL uop c adj t latest later
| [] =>
(* Get latest value *)
match latest with
| Some l =>
(* the [SameData] order matters: (fst l) is the source, and uop is
the dest. *)
if SameData (fst l) uop
then Println (Some later) ["Same data"]
else Println None ["Different data!"]
| None =>
match uop with
| mkMicroop _ _ _ (Read _ 0) => Println (Some later) ["Reads zero"]
| mkMicroop _ _ _ (RMWRead _ 0) => Println (Some later) ["Reads zero"]
| _ => Println None ["Doesn't read zero"]
end
end
end.
Definition InvalidateOtherViCLBeforeNextWriters
(self_c self_i : Location)
(name : string)
(vicls : list (Microop * ViCL))
(nodes : list GraphNode)
(edges : list GraphEdge)
(uop : Microop)
: option (list GraphEdge) :=
match AdjacencyListTransitiveClosure (AdjacencyListFromEdges edges) with
| TC adj =>
match LaterSWViCLsForOtherViCL uop self_c adj vicls None [] with
| Some later_vicls =>
match later_vicls with
| [] => None
| _ => Some (Map (fun x => ((uop, self_i), x, name)) later_vicls)
end
| None =>
Println (Some []) ["Get Latest Value constraint not satisfied"]
end
| _ => Println None ["Input to InvalidateBeforeNextWriters is cyclic"]
end.
Definition SourceOtherViCLBeforeNextWriters
(self_c : Location)
(name : string)
(vicls : list (Microop * ViCL))
(nodes : list GraphNode)
(edges : list GraphEdge)
(uop : Microop)
: option (list GraphEdge) :=
match AdjacencyListTransitiveClosure (AdjacencyListFromEdges edges) with
| TC adj =>
match LaterSWViCLsForOtherViCL uop self_c adj vicls None [] with
| Some later_vicls =>
match later_vicls with
| [] => None
| _ => Some (Map (fun x => ((uop, self_c), x, name)) later_vicls)
end
| None =>
Println (Some []) ["Get Latest Value constraint not satisfied"]
end
| _ => Println None ["Input to SourceOtherViCLBeforeNextWriters is cyclic"]
end.
Fixpoint LaterSWViCLsForSWViCL
(uop : Microop)
(c : Location)
(adj : AdjacencyList)
(vicls : list (Microop * ViCL))
(later : list GraphNode)
: option (list GraphNode) :=
match vicls with
| h::t =>
match snd h with
| SWViCL _ h_c _ _ =>
if andb (SameAddress uop (fst h)) (negb (beq_uop uop (fst h)))
then
let h_c := (fst h, h_c) in
match AdjacencyListFind adj h_c (uop, c) with
| Some _ => LaterSWViCLsForSWViCL uop c adj t later
| None => LaterSWViCLsForSWViCL uop c adj t (h_c :: later)
end
else LaterSWViCLsForSWViCL uop c adj t later
| _ => LaterSWViCLsForSWViCL uop c adj t later
end
| [] => Some later
end.
Definition InvalidateSWViCLBeforeNextWriters
(self_c self_i : Location)
(name : string)
(vicls : list (Microop * ViCL))
(nodes : list GraphNode)
(edges : list GraphEdge)
(uop : Microop)
: option (list GraphEdge) :=
match AdjacencyListTransitiveClosure (AdjacencyListFromEdges edges) with
| TC adj =>
match LaterSWViCLsForSWViCL uop self_c adj vicls [] with
| Some later_vicls =>
match later_vicls with
| [] => None
| _ => Some (Map (fun x => ((uop, self_i), x, name)) later_vicls)
end
| None =>
Println (Some []) ["Get Latest Value constraint not satisfied"]
end
| _ => Println None ["Input to InvalidateBeforeNextWriters is cyclic"]
end.
Definition IsStore
(uop : Microop)
: bool :=
match uop with
| mkMicroop _ _ _ (Write _ _) => true
| mkMicroop _ _ _ (RMWWrite _ _) => true
| _ => false
end.
Fixpoint ParallelViCLOptions
(name : string)
(uop : Microop)
(self_c self_i : Location)
(parallel : list (Microop * ViCL))
(choices : list (list (list GraphEdge)))
: option (list (list GraphEdge)) :=
match parallel with
| h::t =>
if IsStore (fst h) then
(* Either this store ViCL is downgraded (and thus evicted) before the
fence/missing instr's ViCL, or it's downgraded after the fence/missing
instr's ViCL. *)
match ViCLDowngrade (snd h) with
| None => Warning None ["Store without downgrade in ParallelViCLOptions"]
| Some d =>
let new_edges := [[((fst h, ViCLEvict (snd h)), (uop, self_c), name)];
[((uop, self_c), (fst h, d), name)]] in
ParallelViCLOptions name uop self_c self_i t (new_edges :: choices)
end
else
let new_edges := [[((fst h, ViCLEvict (snd h)), (uop, self_c), name)];
[((uop, self_c), (fst h, ViCLCreate (snd h)), name)]] in
ParallelViCLOptions name uop self_c self_i t (new_edges :: choices)
| [] =>
Some (Map (fun x => fold_left (app_rev (A:=_)) x []) (CrossProduct choices))
end.
Fixpoint SortViCLsBeforeOrAfter
(name : string)
(uop : Microop)
(self_c self_i : Location)
(adj : AdjacencyList)
(vicls : list (Microop * ViCL))
(nodes : list GraphNode)
(earlier parallel later : list (Microop * ViCL))
: option (list (list GraphEdge)) :=
match vicls with
| h::t =>
let h_c := ViCLCreate (snd h) in
let h_i := ViCLEvict (snd h) in
if andb (beq_loc h_c self_c) (negb (beq_uop uop (fst h)))
then
if IsStore (fst h) then
(* Does the store have a downgrade? *)
match ViCLDowngrade (snd h) with
| None => SortViCLsBeforeOrAfter name uop self_c self_i adj t nodes
earlier parallel later (* No DG - immune to invalidation, ignore *)
| Some d => match (AdjacencyListFind adj (fst h, d) (uop, self_c),
AdjacencyListFind adj (uop, self_c) (fst h, d)) with
| (Some _, Some _) =>
Println
(SortViCLsBeforeOrAfter name uop self_c self_i adj t nodes
(h::earlier) parallel later )
["Already cyclic at SortViCLsBeforeOrAfter"]
(* DG before missing ViCL created - treat it just like any shared ViCL
that was created beforehand *)
| (Some _, None) =>
SortViCLsBeforeOrAfter name uop self_c self_i adj t nodes
(h::earlier) parallel later
| (None, None) => (* Could be downgraded before or after *)
SortViCLsBeforeOrAfter name uop self_c self_i adj t nodes
earlier (h::parallel) later
(* DG after missing ViCL created - immune to this invalidation, ignore *)
| (None, Some _) =>
SortViCLsBeforeOrAfter name uop self_c self_i adj t nodes
earlier parallel later
end
end
else
let h_c := (fst h, h_c) in
match (AdjacencyListFind adj h_c (uop, self_c),
AdjacencyListFind adj (uop, self_c) h_c) with
| (Some _, Some _) =>
Println
(SortViCLsBeforeOrAfter name uop self_c self_i adj t nodes
(h::earlier) parallel later)
["Already cyclic at SortViCLsBeforeOrAfter"]
| (Some _, None) =>
SortViCLsBeforeOrAfter name uop self_c self_i adj t nodes
(h::earlier) parallel later
| (None, None) =>
SortViCLsBeforeOrAfter name uop self_c self_i adj t nodes
earlier (h::parallel) later
| (None, Some _) =>
SortViCLsBeforeOrAfter name uop self_c self_i adj t nodes
earlier parallel (h::later)
end
else SortViCLsBeforeOrAfter name uop self_c self_i adj t nodes earlier parallel later
| [] =>
let f_earlier x := ((fst x, ViCLEvict (snd x)), (uop, self_c), name) in
let f_later x := ((uop, self_c), (fst x, ViCLCreate (snd x)), name) in
let f_known := app_rev (Map f_earlier earlier) (Map f_later later) in
let f_known := Println f_known
["SortViCLsBeforeOrAfter "; stringOfNat (globalID uop); ": ";
stringOfNat (List.length earlier); " earlier, ";
stringOfNat (List.length parallel); " parallel, ";
stringOfNat (List.length later); " later"] in
ParallelViCLOptions name uop self_c self_i parallel [[f_known]]
end.
Fixpoint SortViCLsForFence
(name : string)
(uop : Microop)
(self_c self_i sort_loc : Location)
(adj : AdjacencyList)
(vicls : list (Microop * ViCL))
(nodes : list GraphNode)
(earlier parallel : list (Microop * ViCL))
: option (list (list GraphEdge)) :=
match vicls with
| h::t =>
let h_c := ViCLCreate (snd h) in
let h_i := ViCLEvict (snd h) in
if (beq_loc h_c sort_loc) then
if IsStore (fst h) then
(* Does the store have a downgrade? *)
match ViCLDowngrade (snd h) with
| None => SortViCLsForFence name uop self_c self_i sort_loc adj t nodes
earlier parallel (* No DG - immune to invalidation, ignore *)
| Some d => match (AdjacencyListFind adj (fst h, d) (uop, self_c),
AdjacencyListFind adj (uop, self_c) (fst h, d)) with
| (Some _, Some _) =>
Println
(SortViCLsForFence name uop self_c self_i sort_loc adj t nodes
(h::earlier) parallel)
["Already cyclic at SortViCLsForFence"]
(* DG before fence at memory - treat it just like any shared ViCL
that was created beforehand *)
| (Some _, None) =>
SortViCLsForFence name uop self_c self_i sort_loc adj t nodes
(h::earlier) parallel
| (None, None) => (* Could be downgraded before or after *)
SortViCLsForFence name uop self_c self_i sort_loc adj t nodes
earlier (h::parallel)
(* DG after fence at memory - immune to this invalidation, ignore *)
| (None, Some _) =>
SortViCLsForFence name uop self_c self_i sort_loc adj t nodes
earlier parallel
end
end
(* All load ViCLs from prior instructions must expire before the fence reaches the memory stage. *)
else SortViCLsForFence name uop self_c self_i sort_loc adj t nodes (h::earlier) parallel
(* Not a ViCL we should be ordering here, so skip it. *)
else SortViCLsForFence name uop self_c self_i sort_loc adj t nodes earlier parallel
| [] =>
let f_earlier x := ((fst x, ViCLEvict (snd x)), (uop, self_c), name) in
let f_known := Map f_earlier earlier in
ParallelViCLOptions name uop self_c self_i parallel [[f_known]]
end.
Definition InvalidateCache
(self_c self_i : Location)
(name : string)
(vicls : list (Microop * ViCL))
(nodes : list GraphNode)
(edges : list GraphEdge)
(uop : Microop)
: option (list (list GraphEdge)) :=
match AdjacencyListTransitiveClosure (AdjacencyListFromEdges edges) with
| TC adj =>
match SortViCLsBeforeOrAfter name uop self_c self_i adj vicls nodes [] [] [] with
| Some new_edges =>
match new_edges with
| [] => None
| _ => Some new_edges
end
| None => Warning (Some []) ["InvalidateCache returned None"]
end
| _ => Println (Some []) ["Input to InvalidateCache is cyclic"]
end.
Definition InvalidateCacheForPriorInsts
(self_c self_i sort_loc : Location)
(name : string)
(vicls : list (Microop * ViCL))
(nodes : list GraphNode)
(edges : list GraphEdge)
(uop : Microop)
: option (list (list GraphEdge)) :=
let f x := match x with
| (u, v) => blt_nat (globalID uop) (globalID u)
end in
match AdjacencyListTransitiveClosure (AdjacencyListFromEdges edges) with
| TC adj =>
match SortViCLsForFence name uop self_c self_i sort_loc adj (removeb f vicls) nodes [] [] with
| Some new_edges =>
match new_edges with
| [] => None
| _ => Some new_edges
end
| None => Warning (Some []) ["InvalidateCacheForPriorInsts returned None"]
end
| _ => Println (Some []) ["Input to InvalidateCacheForPriorInsts is cyclic"]
end.
Definition InvalidateCacheIfNotLastWriter
(self_c self_i : Location)
(vicls : list (Microop * ViCL))
(nodes : list GraphNode)
(edges : list GraphEdge)
(uop : Microop)
(src_edge : GraphEdge)
: list (list GraphEdge) :=
match src_edge with
| ((src_uop, (src_proc, st1)), (cur_uop, (cur_proc, st2)), n) =>
match beq_nat cur_proc src_proc with
(* The constraint is satisfied: there's no need to inv the cache as we were the last owner *)
| true => [[src_edge]]
(* We need to add edges; invalidate the cache as appropriate, and add in the sourcing edge to each possibility. *)
| false => let new_edges := InvalidateCache self_c self_i "InvCache" vicls nodes edges uop in
match new_edges with
| None => [[src_edge]] (* no edges to add *)
| Some actual_edges => let f x y := (x::y) in
Map (f src_edge) actual_edges
end
end
end.
Definition SourceAtAndInvIfNotLastOwner
(self_c self_i : Location)
(a : list nat)
(b : Location)
(name : string)
(vicls : list (Microop * ViCL))
(nodes : list GraphNode)
(edges : list GraphEdge)
(uop : Microop)
: option (list (list GraphEdge)) :=
let srcs := SourcedAtLevels a b name nodes uop in
Some (fold_left (app_rev (A:=_)) (Map (InvalidateCacheIfNotLastWriter self_c self_i vicls nodes edges uop) srcs) []).
Definition SourceFromAndInvIfNotLastOwner
(self_c self_i a b : Location)
(name : string)
(vicls : list (Microop * ViCL))
(nodes : list GraphNode)
(edges : list GraphEdge)
(uop : Microop)
: option (list (list GraphEdge)) :=
let srcs := SourcedFrom a b name vicls nodes edges uop in
match srcs with
| None => Warning (Some []) ["No SourceFrom possibilities for this ViCL!"]
| Some srcs' => let srcs'' := fold_left (app_rev (A:=_)) srcs' [] in
Some (fold_left (app_rev (A:=_)) (Map (InvalidateCacheIfNotLastWriter self_c self_i vicls nodes edges uop) srcs'') [])
end.
Fixpoint FindRMWPartner
(uop_id : nat)
(vicl_c : Location)
(vicls : list (Microop * ViCL))
: option GraphNode :=
match vicls with
| h::t =>
if andb
(beq_nat uop_id (globalID (fst h)))
(beq_loc vicl_c (ViCLCreate (snd h)))
then Some (fst h, ViCLCreate (snd h))
else FindRMWPartner uop_id vicl_c t
| [] => Println None ["Could not find write paired with RMWRead!"]
end.
Fixpoint AtomicBeforeAfterHelper
(r_c w_c : GraphNode)
(name : string)
(vicls : list (Microop * ViCL))
(adj : AdjacencyList)
(edges : list GraphEdge)
: option (list GraphEdge) :=
match vicls with
| h::t =>
let vicl_node := (fst h, ViCLCreate (snd h)) in
if orb
(beq_uop (fst vicl_node) (fst r_c))
(beq_uop (fst vicl_node) (fst w_c))
then AtomicBeforeAfterHelper r_c w_c name t adj edges
else
(* if the ViCL is before the W, it must be before the R too *)
let edges :=
if AdjacencyListFind adj vicl_node w_c
then
Println ((vicl_node, r_c, name) :: edges)
["Found node before W: adding edge to make node before R: ";
GraphvizShortStringOfGraphNode vicl_node; " --> ";
GraphvizShortStringOfGraphNode r_c]
else edges
in
(* if the ViCL is after the R, it must be after the W too *)
let edges :=
if AdjacencyListFind adj r_c vicl_node
then Println ((w_c, vicl_node, name) :: edges)
["Found node after R: adding edge to make node after W: ";
GraphvizShortStringOfGraphNode w_c; " --> ";
GraphvizShortStringOfGraphNode vicl_node]
else edges
in
AtomicBeforeAfterHelper r_c w_c name t adj edges
| [] => Some edges
end.
Definition AtomicBeforeAfter
(r_loc w_loc : Location)
(name : string)
(vicls : list (Microop * ViCL))
(nodes : list GraphNode)
(edges : list GraphEdge)
(uop : Microop)
: option (list GraphEdge) :=
match FindRMWPartner (S (globalID uop)) w_loc vicls with
| Some w =>
let a := AdjacencyListFromEdges edges in
match AdjacencyListTransitiveClosure a with
| TC adj => AtomicBeforeAfterHelper (uop, r_loc) w name vicls adj []
| _ => Println None ["AtomicBeforeAfter: already cyclic"]
end
| None => Println (Some []) ["AtomicBeforeAfter: Unpaired atomic"]
end.
Definition AtomicReadsBetweenHelper
(a b c : Location)
(w : GraphNode)
(name : string)
(nodes : list GraphNode)
(uop : Microop)
(r : list GraphEdge)
: option (list (list GraphEdge)) :=
let candidates_a := filter (ReadsBetweenFilter uop a) nodes in
let candidates_c := filter (ReadsBetweenFilter uop c) nodes in
let candidates := PairNodesByMicroop candidates_a candidates_c [] in
let f x := [(fst x, (uop, b), name); ((uop, b), snd x, name);
(* paired with rmw partner *)
(snd x, w, "RMWPair");
(* stb: redundant via transitivity, but visually helpful *)
((uop, b), w, "RMWStore")
] in
Some (Map f candidates).
Definition AtomicReadsBetween
(a b c : Location)
(name : string)
(vicls : list (Microop * ViCL))
(nodes : list GraphNode)
(edges : list GraphEdge)
(uop : Microop)
: option (list (list GraphEdge)) :=
match FindRMWPartner (S (globalID uop)) a vicls with
| Some w => AtomicReadsBetweenHelper a b c w name nodes uop []
| None => Println (Some []) ["AtomicReadsBetween: unpaired atomic"]
end.
Definition AtomicityEdges
(a b c : Location)
(name : string)
(vicls : list (Microop * ViCL))
(nodes : list GraphNode)
(edges : list GraphEdge)
(uop : Microop)
: option (list (list GraphEdge)) :=
match FindRMWPartner (S (globalID uop)) b vicls with
| Some w => Some [[((uop, a), w, name); ((uop, c), w, name)]]
| None => Println (Some []) ["AtomicityEdges: unpaired atomic"]
end.
Definition CreateAllSubsequentAfterFilter
(uop : Microop)
(loc : Location)
(x : GraphNode)
: bool :=
andb (beq_loc loc (snd x)) (blt_nat (globalID uop) (globalID (fst x))).
Definition CreateAllSubsequentAfterHelper
(a b : Location)
(name : string)
(nodes : list GraphNode)
(uop : Microop)
(r : list GraphEdge)
: option (list (list GraphEdge)) :=
let candidates := filter (CreateAllSubsequentAfterFilter uop b) nodes in
let f x := ((uop, a), x, name) in
match candidates with
| [] => None
| _ => Some [(Map f candidates)]
end.
Definition CreateAllSubsequentAfter
(a b : Location)
(name : string)
(vicls : list (Microop * ViCL))
(nodes : list GraphNode)
(edges : list GraphEdge)
(uop : Microop)
: option (list (list GraphEdge)) :=
CreateAllSubsequentAfterHelper a b name nodes uop [].
Definition ExecAllSubsequentLoadsAfterFilter
(uop : Microop)
(loc : Location)
(x : GraphNode)
: bool :=
let is_ld := match uop, x with
| mkMicroop _ _ _ (Fence _), (mkMicroop _ _ _ (Read _ _), _) => true
| mkMicroop _ _ _ (Fence _), (mkMicroop _ _ _ (RMWRead _ _), _) => true
| _, _ => false
end in
andb is_ld (andb (beq_loc loc (snd x)) (blt_nat (globalID uop) (globalID (fst x)))).
Definition ExecAllSubsequentLoadsAfterHelper
(a b : Location)
(name : string)
(nodes : list GraphNode)
(uop : Microop)
: option (list (list GraphEdge)) :=
let candidates := filter (ExecAllSubsequentLoadsAfterFilter uop b) nodes in
let f x := ((uop, a), x, name) in
match candidates with
| [] => None
| _ => Some [(Map f candidates)]
end.
Definition ExecAllSubsequentLoadsAfter
(a b : Location)
(name : string)
(vicls : list (Microop * ViCL))
(nodes : list GraphNode)
(edges : list GraphEdge)
(uop : Microop)
: option (list (list GraphEdge)) :=
ExecAllSubsequentLoadsAfterHelper a b name nodes uop.
|
// Copyright (C) 1991-2011 Altera Corporation
// This simulation model contains highly confidential and
// proprietary information of Altera and is being provided
// in accordance with and subject to the protections of the
// applicable Altera Program License Subscription Agreement
// which governs its use and disclosure. Your use of Altera
// Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions,
// and any output files any of the foregoing (including device
// programming or simulation files), and any associated
// documentation or information are expressly subject to the
// terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of simulating designs for
// use exclusively in logic devices manufactured by Altera and sold
// by Altera or its authorized distributors. Please refer to the
// applicable agreement for further details. Altera products and
// services are protected under numerous U.S. and foreign patents,
// maskwork rights, copyrights and other intellectual property laws.
// Altera assumes no responsibility or liability arising out of the
// application or use of this simulation model.
// Quartus II 11.0 Build 157 04/27/2011
`timescale 1 ps/1 ps
module stratixv_hssi_gen3_pcie_hip (
dpriostatus,
lmidout,
lmiack,
lmirden,
lmiwren,
lmiaddr,
lmidin,
flrreset,
flrsts,
resetstatus,
l2exit,
hotrstexit,
hiphardreset,
dlupexit,
coreclkout,
pldclk,
pldsrst,
pldrst,
pclkch0,
pclkch1,
pclkcentral,
pllfixedclkch0,
pllfixedclkch1,
pllfixedclkcentral,
phyrst,
physrst,
coreclkin,
corerst,
corepor,
corecrst,
coresrst,
swdnout,
swupout,
swdnin,
swupin,
swctmod,
rxstdata,
rxstparity,
rxstbe,
rxsterr,
rxstsop,
rxsteop,
rxstempty,
rxstvalid,
rxstbardec1,
rxstbardec2,
rxstmask,
rxstready,
txstready,
txcredfchipcons,
txcredfcinfinite,
txcredhdrfcp,
txcreddatafcp,
txcredhdrfcnp,
txcreddatafcnp,
txcredhdrfccp,
txcreddatafccp,
txstdata,
txstparity,
txsterr,
txstsop,
txsteop,
txstempty,
txstvalid,
r2cuncecc,
rxcorrecc,
retryuncecc,
retrycorrecc,
rxparerr,
txparerr,
r2cparerr,
pmetosr,
pmetocr,
pmevent,
pmdata,
pmauxpwr,
tlcfgsts,
tlcfgctl,
tlcfgadd,
appintaack,
appintasts,
intstatus,
appmsiack,
appmsireq,
appmsitc,
appmsinum,
aermsinum,
pexmsinum,
hpgctrler,
cfglink2csrpld,
cfgprmbuspld,
csebisshadow,
csebwrdata,
csebwrdataparity,
csebbe,
csebaddr,
csebaddrparity,
csebwren,
csebrden,
csebwrrespreq,
csebrddata,
csebrddataparity,
csebwaitrequest,
csebwrrespvalid,
csebwrresponse,
csebrdresponse,
dlup,
testouthip,
testout1hip,
ev1us,
ev128ns,
wakeoen,
serrout,
ltssmstate,
laneact,
currentspeed,
slotclkcfg,
mode,
testinhip,
testin1hip,
cplpending,
cplerr,
appinterr,
egressblkerr,
pmexitd0ack,
pmexitd0req,
currentcoeff0,
currentcoeff1,
currentcoeff2,
currentcoeff3,
currentcoeff4,
currentcoeff5,
currentcoeff6,
currentcoeff7,
currentrxpreset0,
currentrxpreset1,
currentrxpreset2,
currentrxpreset3,
currentrxpreset4,
currentrxpreset5,
currentrxpreset6,
currentrxpreset7,
rate0,
rate1,
rate2,
rate3,
rate4,
rate5,
rate6,
rate7,
ratectrl,
ratetiedtognd,
eidleinfersel0,
eidleinfersel1,
eidleinfersel2,
eidleinfersel3,
eidleinfersel4,
eidleinfersel5,
eidleinfersel6,
eidleinfersel7,
txdata0,
txdatak0,
txdetectrx0,
txelecidle0,
txcompl0,
rxpolarity0,
powerdown0,
txdataskip0,
txblkst0,
txsynchd0,
txdeemph0,
txmargin0,
rxdata0,
rxdatak0,
rxvalid0,
phystatus0,
rxelecidle0,
rxstatus0,
rxdataskip0,
rxblkst0,
rxsynchd0,
rxfreqlocked0,
txdata1,
txdatak1,
txdetectrx1,
txelecidle1,
txcompl1,
rxpolarity1,
powerdown1,
txdataskip1,
txblkst1,
txsynchd1,
txdeemph1,
txmargin1,
rxdata1,
rxdatak1,
rxvalid1,
phystatus1,
rxelecidle1,
rxstatus1,
rxdataskip1,
rxblkst1,
rxsynchd1,
rxfreqlocked1,
txdata2,
txdatak2,
txdetectrx2,
txelecidle2,
txcompl2,
rxpolarity2,
powerdown2,
txdataskip2,
txblkst2,
txsynchd2,
txdeemph2,
txmargin2,
rxdata2,
rxdatak2,
rxvalid2,
phystatus2,
rxelecidle2,
rxstatus2,
rxdataskip2,
rxblkst2,
rxsynchd2,
rxfreqlocked2,
txdata3,
txdatak3,
txdetectrx3,
txelecidle3,
txcompl3,
rxpolarity3,
powerdown3,
txdataskip3,
txblkst3,
txsynchd3,
txdeemph3,
txmargin3,
rxdata3,
rxdatak3,
rxvalid3,
phystatus3,
rxelecidle3,
rxstatus3,
rxdataskip3,
rxblkst3,
rxsynchd3,
rxfreqlocked3,
txdata4,
txdatak4,
txdetectrx4,
txelecidle4,
txcompl4,
rxpolarity4,
powerdown4,
txdataskip4,
txblkst4,
txsynchd4,
txdeemph4,
txmargin4,
rxdata4,
rxdatak4,
rxvalid4,
phystatus4,
rxelecidle4,
rxstatus4,
rxdataskip4,
rxblkst4,
rxsynchd4,
rxfreqlocked4,
txdata5,
txdatak5,
txdetectrx5,
txelecidle5,
txcompl5,
rxpolarity5,
powerdown5,
txdataskip5,
txblkst5,
txsynchd5,
txdeemph5,
txmargin5,
rxdata5,
rxdatak5,
rxvalid5,
phystatus5,
rxelecidle5,
rxstatus5,
rxdataskip5,
rxblkst5,
rxsynchd5,
rxfreqlocked5,
txdata6,
txdatak6,
txdetectrx6,
txelecidle6,
txcompl6,
rxpolarity6,
powerdown6,
txdataskip6,
txblkst6,
txsynchd6,
txdeemph6,
txmargin6,
rxdata6,
rxdatak6,
rxvalid6,
phystatus6,
rxelecidle6,
rxstatus6,
rxdataskip6,
rxblkst6,
rxsynchd6,
rxfreqlocked6,
txdata7,
txdatak7,
txdetectrx7,
txelecidle7,
txcompl7,
rxpolarity7,
powerdown7,
txdataskip7,
txblkst7,
txsynchd7,
txdeemph7,
txmargin7,
rxdata7,
rxdatak7,
rxvalid7,
phystatus7,
rxelecidle7,
rxstatus7,
rxdataskip7,
rxblkst7,
rxsynchd7,
rxfreqlocked7,
dbgpipex1rx,
memredsclk,
memredenscan,
memredscen,
memredscin,
memredscsel,
memredscrst,
memredscout,
memregscanen,
memregscanin,
memhiptestenable,
memregscanout,
bisttesten,
bistenrpl,
bistscanin,
bistscanen,
bistenrcv,
bistscanoutrpl,
bistdonearpl,
bistdonebrpl,
bistpassrpl,
derrrpl,
derrcorextrpl,
bistscanoutrcv,
bistdonearcv,
bistdonebrcv,
bistpassrcv,
derrcorextrcv,
bistscanoutrcv1,
bistdonearcv1,
bistdonebrcv1,
bistpassrcv1,
derrcorextrcv1,
scanmoden,
scanshiftn,
nfrzdrv,
frzreg,
frzlogic,
idrpl,
idrcv,
plniotri,
entest,
npor,
usermode,
cvpclk,
cvpdata,
cvpstartxfer,
cvpconfig,
cvpfullconfig,
cvpconfigready,
cvpen,
cvpconfigerror,
cvpconfigdone,
pinperstn,
pldperstn,
iocsrrdydly,
softaltpe3rstn,
softaltpe3srstn,
softaltpe3crstn,
pldclrpmapcshipn,
pldclrpcshipn,
pldclrhipn,
s0ch0emsiptieoff,
s0ch1emsiptieoff,
s0ch2emsiptieoff,
s1ch0emsiptieoff,
s1ch1emsiptieoff,
s1ch2emsiptieoff,
s2ch0emsiptieoff,
s2ch1emsiptieoff,
s2ch2emsiptieoff,
s3ch0emsiptieoff,
s3ch1emsiptieoff,
s3ch2emsiptieoff,
emsiptieofftop,
emsiptieoffbot,
txpcsrstn0,
rxpcsrstn0,
g3txpcsrstn0,
g3rxpcsrstn0,
txpmasyncp0,
rxpmarstb0,
txlcpllrstb0,
offcalen0,
frefclk0,
offcaldone0,
txlcplllock0,
rxfreqtxcmuplllock0,
rxpllphaselock0,
masktxplllock0,
txpcsrstn1,
rxpcsrstn1,
g3txpcsrstn1,
g3rxpcsrstn1,
txpmasyncp1,
rxpmarstb1,
txlcpllrstb1,
offcalen1,
frefclk1,
offcaldone1,
txlcplllock1,
rxfreqtxcmuplllock1,
rxpllphaselock1,
masktxplllock1,
txpcsrstn2,
rxpcsrstn2,
g3txpcsrstn2,
g3rxpcsrstn2,
txpmasyncp2,
rxpmarstb2,
txlcpllrstb2,
offcalen2,
frefclk2,
offcaldone2,
txlcplllock2,
rxfreqtxcmuplllock2,
rxpllphaselock2,
masktxplllock2,
txpcsrstn3,
rxpcsrstn3,
g3txpcsrstn3,
g3rxpcsrstn3,
txpmasyncp3,
rxpmarstb3,
txlcpllrstb3,
offcalen3,
frefclk3,
offcaldone3,
txlcplllock3,
rxfreqtxcmuplllock3,
rxpllphaselock3,
masktxplllock3,
txpcsrstn4,
rxpcsrstn4,
g3txpcsrstn4,
g3rxpcsrstn4,
txpmasyncp4,
rxpmarstb4,
txlcpllrstb4,
offcalen4,
frefclk4,
offcaldone4,
txlcplllock4,
rxfreqtxcmuplllock4,
rxpllphaselock4,
masktxplllock4,
txpcsrstn5,
rxpcsrstn5,
g3txpcsrstn5,
g3rxpcsrstn5,
txpmasyncp5,
rxpmarstb5,
txlcpllrstb5,
offcalen5,
frefclk5,
offcaldone5,
txlcplllock5,
rxfreqtxcmuplllock5,
rxpllphaselock5,
masktxplllock5,
txpcsrstn6,
rxpcsrstn6,
g3txpcsrstn6,
g3rxpcsrstn6,
txpmasyncp6,
rxpmarstb6,
txlcpllrstb6,
offcalen6,
frefclk6,
offcaldone6,
txlcplllock6,
rxfreqtxcmuplllock6,
rxpllphaselock6,
masktxplllock6,
txpcsrstn7,
rxpcsrstn7,
g3txpcsrstn7,
g3rxpcsrstn7,
txpmasyncp7,
rxpmarstb7,
txlcpllrstb7,
offcalen7,
frefclk7,
offcaldone7,
txlcplllock7,
rxfreqtxcmuplllock7,
rxpllphaselock7,
masktxplllock7,
txpcsrstn8,
rxpcsrstn8,
g3txpcsrstn8,
g3rxpcsrstn8,
txpmasyncp8,
rxpmarstb8,
txlcpllrstb8,
offcalen8,
frefclk8,
offcaldone8,
txlcplllock8,
rxfreqtxcmuplllock8,
rxpllphaselock8,
masktxplllock8,
txpcsrstn9,
rxpcsrstn9,
g3txpcsrstn9,
g3rxpcsrstn9,
txpmasyncp9,
rxpmarstb9,
txlcpllrstb9,
offcalen9,
frefclk9,
offcaldone9,
txlcplllock9,
rxfreqtxcmuplllock9,
rxpllphaselock9,
masktxplllock9,
txpcsrstn10,
rxpcsrstn10,
g3txpcsrstn10,
g3rxpcsrstn10,
txpmasyncp10,
rxpmarstb10,
txlcpllrstb10,
offcalen10,
frefclk10,
offcaldone10,
txlcplllock10,
rxfreqtxcmuplllock10,
rxpllphaselock10,
masktxplllock10,
txpcsrstn11,
rxpcsrstn11,
g3txpcsrstn11,
g3rxpcsrstn11,
txpmasyncp11,
rxpmarstb11,
txlcpllrstb11,
offcalen11,
frefclk11,
offcaldone11,
txlcplllock11,
rxfreqtxcmuplllock11,
rxpllphaselock11,
masktxplllock11,
reservedin,
reservedclkin,
reservedout,
reservedclkout);
parameter func_mode = "disable";
parameter in_cvp_mode = "not_cvp_mode"; // Enable CVP
parameter bonding_mode = "bond_disable";
parameter prot_mode = "disabled_prot_mode";
parameter pcie_spec_1p0_compliance = "spec_1p1";
parameter vc_enable = "single_vc";
parameter enable_slot_register = "false";
parameter pcie_mode = "shared_mode";
parameter bypass_cdc = "false";
parameter enable_rx_reordering = "true";
parameter enable_rx_buffer_checking = "false";
parameter single_rx_detect_data = 4'b0;
parameter single_rx_detect = "single_rx_detect";
parameter use_crc_forwarding = "false";
parameter bypass_tl = "false";
parameter gen123_lane_rate_mode = "gen1";
parameter lane_mask = "x4";
parameter disable_link_x2_support = "false";
parameter national_inst_thru_enhance = "true";
parameter hip_hard_reset = "enable";
parameter dis_paritychk = "enable";
parameter wrong_device_id = "disable";
parameter data_pack_rx = "disable";
parameter ast_width = "rx_tx_64";
parameter rx_sop_ctrl = "boundary_64";
parameter rx_ast_parity = "disable";
parameter tx_ast_parity = "disable";
parameter ltssm_1ms_timeout = "disable";
parameter ltssm_freqlocked_check = "disable";
parameter deskew_comma = "skp_eieos_deskw";
parameter dl_tx_check_parity_edb = "disable";
parameter tl_tx_check_parity_msg = "disable";
parameter port_link_number_data = 8'b1;
parameter port_link_number = "port_link_number";
parameter device_number_data = 5'b0;
parameter device_number = "device_number";
parameter bypass_clk_switch = "false";
parameter core_clk_out_sel = "div_1";
parameter core_clk_divider = "div_1";
parameter core_clk_source = "pll_fixed_clk";
parameter core_clk_sel = "pld_clk";
parameter enable_ch0_pclk_out = "pclk_ch01";
parameter enable_ch01_pclk_out = "pclk_ch0";
parameter pipex1_debug_sel = "disable";
parameter pclk_out_sel = "pclk";
parameter vendor_id_data = 16'b1000101110010;
parameter vendor_id = "vendor_id";
parameter device_id_data = 16'b1;
parameter device_id = "device_id";
parameter revision_id_data = 8'b1;
parameter revision_id = "revision_id";
parameter class_code_data = 24'b111111110000000000000000;
parameter class_code = "class_code";
parameter subsystem_vendor_id_data = 16'b1000101110010;
parameter subsystem_vendor_id = "subsystem_vendor_id";
parameter subsystem_device_id_data = 16'b1;
parameter subsystem_device_id = "subsystem_device_id";
parameter no_soft_reset = "false";
parameter maximum_current_data = 3'b0;
parameter maximum_current = "maximum_current";
parameter d1_support = "false";
parameter d2_support = "false";
parameter d0_pme = "false";
parameter d1_pme = "false";
parameter d2_pme = "false";
parameter d3_hot_pme = "false";
parameter d3_cold_pme = "false";
parameter use_aer = "false";
parameter low_priority_vc = "single_vc";
parameter vc_arbitration = "single_vc";
parameter disable_snoop_packet = "false";
parameter max_payload_size = "payload_512";
parameter surprise_down_error_support = "false";
parameter dll_active_report_support = "false";
parameter extend_tag_field = "false";
parameter endpoint_l0_latency_data = 3'b0;
parameter endpoint_l0_latency = "endpoint_l0_latency";
parameter endpoint_l1_latency_data = 3'b0;
parameter endpoint_l1_latency = "endpoint_l1_latency";
parameter indicator_data = 3'b111;
parameter indicator = "indicator";
parameter role_based_error_reporting = "false";
parameter slot_power_scale_data = 2'b0;
parameter slot_power_scale = "slot_power_scale";
parameter max_link_width = "x4";
parameter enable_l1_aspm = "false";
parameter enable_l0s_aspm = "false";
parameter l1_exit_latency_sameclock_data = 3'b0;
parameter l1_exit_latency_sameclock = "l1_exit_latency_sameclock";
parameter l1_exit_latency_diffclock_data = 3'b0;
parameter l1_exit_latency_diffclock = "l1_exit_latency_diffclock";
parameter hot_plug_support_data = 7'b0;
parameter hot_plug_support = "hot_plug_support";
parameter slot_power_limit_data = 8'b0;
parameter slot_power_limit = "slot_power_limit";
parameter slot_number_data = 13'b0;
parameter slot_number = "slot_number";
parameter diffclock_nfts_count_data = 8'b0;
parameter diffclock_nfts_count = "diffclock_nfts_count";
parameter sameclock_nfts_count_data = 8'b0;
parameter sameclock_nfts_count = "sameclock_nfts_count";
parameter completion_timeout = "abcd";
parameter enable_completion_timeout_disable = "true";
parameter extended_tag_reset = "false";
parameter ecrc_check_capable = "true";
parameter ecrc_gen_capable = "true";
parameter no_command_completed = "true";
parameter msi_multi_message_capable = "count_4";
parameter msi_64bit_addressing_capable = "true";
parameter msi_masking_capable = "false";
parameter msi_support = "true";
parameter interrupt_pin = "inta";
parameter ena_ido_req = "false";
parameter ena_ido_cpl = "false";
parameter enable_function_msix_support = "true";
parameter msix_table_size_data = 11'b0;
parameter msix_table_size = "msix_table_size";
parameter msix_table_bir_data = 3'b0;
parameter msix_table_bir = "msix_table_bir";
parameter msix_table_offset_data = 29'b0;
parameter msix_table_offset = "msix_table_offset";
parameter msix_pba_bir_data = 3'b0;
parameter msix_pba_bir = "msix_pba_bir";
parameter msix_pba_offset_data = 29'b0;
parameter msix_pba_offset = "msix_pba_offset";
parameter bridge_port_vga_enable = "false";
parameter bridge_port_ssid_support = "false";
parameter ssvid_data = 16'b0;
parameter ssvid = "ssvid";
parameter ssid_data = 16'b0;
parameter ssid = "ssid";
parameter eie_before_nfts_count_data = 4'b100;
parameter eie_before_nfts_count = "eie_before_nfts_count";
parameter gen2_diffclock_nfts_count_data = 8'b11111111;
parameter gen2_diffclock_nfts_count = "gen2_diffclock_nfts_count";
parameter gen2_sameclock_nfts_count_data = 8'b11111111;
parameter gen2_sameclock_nfts_count = "gen2_sameclock_nfts_count";
parameter deemphasis_enable = "false";
parameter pcie_spec_version = "v2";
parameter l0_exit_latency_sameclock_data = 3'b110;
parameter l0_exit_latency_sameclock = "l0_exit_latency_sameclock";
parameter l0_exit_latency_diffclock_data = 3'b110;
parameter l0_exit_latency_diffclock = "l0_exit_latency_diffclock";
parameter rx_ei_l0s = "disable";
parameter l2_async_logic = "enable";
parameter aspm_config_management = "true";
parameter atomic_op_routing = "false";
parameter atomic_op_completer_32bit = "false";
parameter atomic_op_completer_64bit = "false";
parameter cas_completer_128bit = "false";
parameter ltr_mechanism = "false";
parameter tph_completer = "false";
parameter extended_format_field = "true";
parameter atomic_malformed = "false";
parameter flr_capability = "true";
parameter enable_adapter_half_rate_mode = "false";
parameter vc0_clk_enable = "true";
parameter vc1_clk_enable = "false";
parameter register_pipe_signals = "false";
parameter bar0_io_space = "false";
parameter bar0_64bit_mem_space = "true";
parameter bar0_prefetchable = "true";
parameter bar0_size_mask_data = 28'b1111111111111111111111111111;
parameter bar0_size_mask = "bar0_size_mask";
parameter bar1_io_space = "false";
parameter bar1_64bit_mem_space = "false";
parameter bar1_prefetchable = "false";
parameter bar1_size_mask_data = 28'b0;
parameter bar1_size_mask = "bar1_size_mask";
parameter bar2_io_space = "false";
parameter bar2_64bit_mem_space = "false";
parameter bar2_prefetchable = "false";
parameter bar2_size_mask_data = 28'b0;
parameter bar2_size_mask = "bar2_size_mask";
parameter bar3_io_space = "false";
parameter bar3_64bit_mem_space = "false";
parameter bar3_prefetchable = "false";
parameter bar3_size_mask_data = 28'b0;
parameter bar3_size_mask = "bar3_size_mask";
parameter bar4_io_space = "false";
parameter bar4_64bit_mem_space = "false";
parameter bar4_prefetchable = "false";
parameter bar4_size_mask_data = 28'b0;
parameter bar4_size_mask = "bar4_size_mask";
parameter bar5_io_space = "false";
parameter bar5_64bit_mem_space = "false";
parameter bar5_prefetchable = "false";
parameter bar5_size_mask_data = 28'b0;
parameter bar5_size_mask = "bar5_size_mask";
parameter expansion_base_address_register_data = 32'b0;
parameter expansion_base_address_register = "expansion_base_address_register";
parameter io_window_addr_width = "window_32_bit";
parameter prefetchable_mem_window_addr_width = "prefetch_32";
parameter skp_os_gen3_count_data = 11'b0;
parameter skp_os_gen3_count = "skp_os_gen3_count";
parameter rx_cdc_almost_empty_data = 4'h0;
parameter rx_cdc_almost_empty = "rx_cdc_almost_empty";
parameter tx_cdc_almost_empty_data = 4'h0;
parameter tx_cdc_almost_empty = "tx_cdc_almost_empty";
parameter rx_cdc_almost_full_data = 4'h0;
parameter rx_cdc_almost_full = "rx_cdc_almost_full";
parameter tx_cdc_almost_full_data = 4'h0;
parameter tx_cdc_almost_full = "tx_cdc_almost_full";
parameter rx_l0s_count_idl_data = 8'b0;
parameter rx_l0s_count_idl = "rx_l0s_count_idl";
parameter cdc_dummy_insert_limit_data = 4'h0;
parameter cdc_dummy_insert_limit = "cdc_dummy_insert_limit";
parameter ei_delay_powerdown_count_data = 8'b1010;
parameter ei_delay_powerdown_count = "ei_delay_powerdown_count";
parameter millisecond_cycle_count_data = 20'b0;
parameter millisecond_cycle_count = "millisecond_cycle_count";
parameter skp_os_schedule_count_data = 11'b0;
parameter skp_os_schedule_count = "skp_os_schedule_count";
parameter fc_init_timer_data = 11'b10000000000;
parameter fc_init_timer = "fc_init_timer";
parameter l01_entry_latency_data = 5'b11111;
parameter l01_entry_latency = "l01_entry_latency";
parameter flow_control_update_count_data = 5'b11110;
parameter flow_control_update_count = "flow_control_update_count";
parameter flow_control_timeout_count_data = 8'b11001000;
parameter flow_control_timeout_count = "flow_control_timeout_count";
parameter vc0_rx_flow_ctrl_posted_header_data = 8'b110010;
parameter vc0_rx_flow_ctrl_posted_header = "vc0_rx_flow_ctrl_posted_header";
parameter vc0_rx_flow_ctrl_posted_data_data = 12'b101101000;
parameter vc0_rx_flow_ctrl_posted_data = "vc0_rx_flow_ctrl_posted_data";
parameter vc0_rx_flow_ctrl_nonposted_header_data = 8'b110110;
parameter vc0_rx_flow_ctrl_nonposted_header = "vc0_rx_flow_ctrl_nonposted_header";
parameter vc0_rx_flow_ctrl_nonposted_data_data = 8'b0;
parameter vc0_rx_flow_ctrl_nonposted_data = "vc0_rx_flow_ctrl_nonposted_data";
parameter vc0_rx_flow_ctrl_compl_header_data = 8'b1110000;
parameter vc0_rx_flow_ctrl_compl_header = "vc0_rx_flow_ctrl_compl_header";
parameter vc0_rx_flow_ctrl_compl_data_data = 12'b111000000;
parameter vc0_rx_flow_ctrl_compl_data = "vc0_rx_flow_ctrl_compl_data";
parameter rx_ptr0_posted_dpram_min_data = 11'b0;
parameter rx_ptr0_posted_dpram_min = "rx_ptr0_posted_dpram_min";
parameter rx_ptr0_posted_dpram_max_data = 11'b0;
parameter rx_ptr0_posted_dpram_max = "rx_ptr0_posted_dpram_max";
parameter rx_ptr0_nonposted_dpram_min_data = 11'b0;
parameter rx_ptr0_nonposted_dpram_min = "rx_ptr0_nonposted_dpram_min";
parameter rx_ptr0_nonposted_dpram_max_data = 11'b0;
parameter rx_ptr0_nonposted_dpram_max = "rx_ptr0_nonposted_dpram_max";
parameter retry_buffer_last_active_address_data = 10'b1111111111;
parameter retry_buffer_last_active_address = "retry_buffer_last_active_address";
parameter retry_buffer_memory_settings_data = 30'b0;
parameter retry_buffer_memory_settings = "retry_buffer_memory_settings";
parameter vc0_rx_buffer_memory_settings_data = 30'b0;
parameter vc0_rx_buffer_memory_settings = "vc0_rx_buffer_memory_settings";
parameter bist_memory_settings_data = 75'b0;
parameter bist_memory_settings = "bist_memory_settings";
parameter credit_buffer_allocation_aux = "balanced";
parameter iei_enable_settings = "gen2_infei_infsd_gen1_infei_sd";
parameter vsec_id_data = 16'b1000101110010;
parameter vsec_id = "vsec_id";
parameter cvp_rate_sel = "full_rate";
parameter hard_reset_bypass = "false";
parameter cvp_data_compressed = "false";
parameter cvp_data_encrypted = "false";
parameter cvp_mode_reset = "false";
parameter cvp_clk_reset = "false";
parameter vsec_cap_data = 4'b0;
parameter vsec_cap = "vsec_cap";
parameter jtag_id_data = 32'b0;
parameter jtag_id = "jtag_id";
parameter user_id_data = 16'b0;
parameter user_id = "user_id";
parameter cseb_extend_pci = "false";
parameter cseb_extend_pcie = "false";
parameter cseb_cpl_status_during_cvp = "config_retry_status";
parameter cseb_route_to_avl_rx_st = "cseb";
parameter cseb_config_bypass = "disable";
parameter cseb_cpl_tag_checking = "enable";
parameter cseb_bar_match_checking = "enable";
parameter cseb_min_error_checking = "false";
parameter cseb_temp_busy_crs = "completer_abort";
parameter cseb_disable_auto_crs = "false";
parameter gen3_diffclock_nfts_count_data = 8'b10000000;
parameter gen3_diffclock_nfts_count = "g3_diffclock_nfts_count";
parameter gen3_sameclock_nfts_count_data = 8'b10000000;
parameter gen3_sameclock_nfts_count = "g3_sameclock_nfts_count";
parameter gen3_coeff_errchk = "enable";
parameter gen3_paritychk = "enable";
parameter gen3_coeff_delay_count_data = 7'b1111101;
parameter gen3_coeff_delay_count = "g3_coeff_dly_count";
parameter gen3_coeff_1_data = 18'b0;
parameter gen3_coeff_1 = "g3_coeff_1";
parameter gen3_coeff_1_sel = "coeff_1";
parameter gen3_coeff_1_preset_hint_data = 3'b0;
parameter gen3_coeff_1_preset_hint = "g3_coeff_1_prst_hint";
parameter gen3_coeff_1_nxtber_more_ptr = 4'b0;
parameter gen3_coeff_1_nxtber_more = "g3_coeff_1_nxtber_more";
parameter gen3_coeff_1_nxtber_less_ptr = 4'b0;
parameter gen3_coeff_1_nxtber_less = "g3_coeff_1_nxtber_less";
parameter gen3_coeff_1_reqber_data = 5'b0;
parameter gen3_coeff_1_reqber = "g3_coeff_1_reqber";
parameter gen3_coeff_1_ber_meas_data = 6'b0;
parameter gen3_coeff_1_ber_meas = "g3_coeff_1_ber_meas";
parameter gen3_coeff_2_data = 18'b0;
parameter gen3_coeff_2 = "g3_coeff_2";
parameter gen3_coeff_2_sel = "coeff_2";
parameter gen3_coeff_2_preset_hint_data = 3'b0;
parameter gen3_coeff_2_preset_hint = "g3_coeff_2_prst_hint";
parameter gen3_coeff_2_nxtber_more_ptr = 4'b0;
parameter gen3_coeff_2_nxtber_more = "g3_coeff_2_nxtber_more";
parameter gen3_coeff_2_nxtber_less_ptr = 4'b0;
parameter gen3_coeff_2_nxtber_less = "g3_coeff_2_nxtber_less";
parameter gen3_coeff_2_reqber_data = 5'b0;
parameter gen3_coeff_2_reqber = "g3_coeff_2_reqber";
parameter gen3_coeff_2_ber_meas_data = 6'b0;
parameter gen3_coeff_2_ber_meas = "g3_coeff_1_ber_meas";
parameter gen3_coeff_3_data = 18'b0;
parameter gen3_coeff_3 = "g3_coeff_3";
parameter gen3_coeff_3_sel = "coeff_3";
parameter gen3_coeff_3_preset_hint_data = 3'b0;
parameter gen3_coeff_3_preset_hint = "g3_coeff_3_prst_hint";
parameter gen3_coeff_3_nxtber_more_ptr = 4'b0;
parameter gen3_coeff_3_nxtber_more = "g3_coeff_3_nxtber_more";
parameter gen3_coeff_3_nxtber_less_ptr = 4'b0;
parameter gen3_coeff_3_nxtber_less = "g3_coeff_3_nxtber_less";
parameter gen3_coeff_3_reqber_data = 5'b0;
parameter gen3_coeff_3_reqber = "g3_coeff_3_reqber";
parameter gen3_coeff_3_ber_meas_data = 6'b0;
parameter gen3_coeff_3_ber_meas = "g3_coeff_3_ber_meas";
parameter gen3_coeff_4_data = 18'b0;
parameter gen3_coeff_4 = "g3_coeff_4";
parameter gen3_coeff_4_sel = "coeff_4";
parameter gen3_coeff_4_preset_hint_data = 3'b0;
parameter gen3_coeff_4_preset_hint = "g3_coeff_4_prst_hint";
parameter gen3_coeff_4_nxtber_more_ptr = 4'b0;
parameter gen3_coeff_4_nxtber_more = "g3_coeff_4_nxtber_more";
parameter gen3_coeff_4_nxtber_less_ptr = 4'b0;
parameter gen3_coeff_4_nxtber_less = "g3_coeff_4_nxtber_less";
parameter gen3_coeff_4_reqber_data = 5'b0;
parameter gen3_coeff_4_reqber = "g3_coeff_4_reqber";
parameter gen3_coeff_4_ber_meas_data = 6'b0;
parameter gen3_coeff_4_ber_meas = "g3_coeff_4_ber_meas";
parameter gen3_coeff_5_data = 18'b0;
parameter gen3_coeff_5 = "g3_coeff_5";
parameter gen3_coeff_5_sel = "coeff_5";
parameter gen3_coeff_5_preset_hint_data = 3'b0;
parameter gen3_coeff_5_preset_hint = "g3_coeff_5_prst_hint";
parameter gen3_coeff_5_nxtber_more_ptr = 4'b0;
parameter gen3_coeff_5_nxtber_more = "g3_coeff_5_nxtber_more";
parameter gen3_coeff_5_nxtber_less_ptr = 4'b0;
parameter gen3_coeff_5_nxtber_less = "g3_coeff_5_nxtber_less";
parameter gen3_coeff_5_reqber_data = 5'b0;
parameter gen3_coeff_5_reqber = "g3_coeff_5_reqber";
parameter gen3_coeff_5_ber_meas_data = 6'b0;
parameter gen3_coeff_5_ber_meas = "g3_coeff_5_ber_meas";
parameter gen3_coeff_6_data = 18'b0;
parameter gen3_coeff_6 = "g3_coeff_6";
parameter gen3_coeff_6_sel = "coeff_6";
parameter gen3_coeff_6_preset_hint_data = 3'b0;
parameter gen3_coeff_6_preset_hint = "g3_coeff_6_prst_hint";
parameter gen3_coeff_6_nxtber_more_ptr = 4'b0;
parameter gen3_coeff_6_nxtber_more = "g3_coeff_6_nxtber_more";
parameter gen3_coeff_6_nxtber_less_ptr = 4'b0;
parameter gen3_coeff_6_nxtber_less = "g3_coeff_6_nxtber_less";
parameter gen3_coeff_6_reqber_data = 5'b0;
parameter gen3_coeff_6_reqber = "g3_coeff_6_reqber";
parameter gen3_coeff_6_ber_meas_data = 6'b0;
parameter gen3_coeff_6_ber_meas = "g3_coeff_6_ber_meas";
parameter gen3_coeff_7_data = 18'b0;
parameter gen3_coeff_7 = "g3_coeff_7";
parameter gen3_coeff_7_sel = "coeff_7";
parameter gen3_coeff_7_preset_hint_data = 3'b0;
parameter gen3_coeff_7_preset_hint = "g3_coeff_7_prst_hint";
parameter gen3_coeff_7_nxtber_more_ptr = 4'b0;
parameter gen3_coeff_7_nxtber_more = "g3_coeff_7_nxtber_more";
parameter gen3_coeff_7_nxtber_less_ptr = 4'b0;
parameter gen3_coeff_7_nxtber_less = "g3_coeff_7_nxtber_less";
parameter gen3_coeff_7_reqber_data = 5'b0;
parameter gen3_coeff_7_reqber = "g3_coeff_7_reqber";
parameter gen3_coeff_7_ber_meas_data = 6'b0;
parameter gen3_coeff_7_ber_meas = "g3_coeff_7_ber_meas";
parameter gen3_coeff_8_data = 18'b0;
parameter gen3_coeff_8 = "g3_coeff_8";
parameter gen3_coeff_8_sel = "coeff_8";
parameter gen3_coeff_8_preset_hint_data = 3'b0;
parameter gen3_coeff_8_preset_hint = "g3_coeff_8_prst_hint";
parameter gen3_coeff_8_nxtber_more_ptr = 4'b0;
parameter gen3_coeff_8_nxtber_more = "g3_coeff_8_nxtber_more";
parameter gen3_coeff_8_nxtber_less_ptr = 4'b0;
parameter gen3_coeff_8_nxtber_less = "g3_coeff_8_nxtber_less";
parameter gen3_coeff_8_reqber_data = 5'b0;
parameter gen3_coeff_8_reqber = "g3_coeff_8_reqber";
parameter gen3_coeff_8_ber_meas_data = 6'b0;
parameter gen3_coeff_8_ber_meas = "g3_coeff_8_ber_meas";
parameter gen3_coeff_9_data = 18'b0;
parameter gen3_coeff_9 = "g3_coeff_9";
parameter gen3_coeff_9_sel = "coeff_9";
parameter gen3_coeff_9_preset_hint_data = 3'b0;
parameter gen3_coeff_9_preset_hint = "g3_coeff_9_prst_hint";
parameter gen3_coeff_9_nxtber_more_ptr = 4'b0;
parameter gen3_coeff_9_nxtber_more = "g3_coeff_9_nxtber_more";
parameter gen3_coeff_9_nxtber_less_ptr = 4'b0;
parameter gen3_coeff_9_nxtber_less = "g3_coeff_9_nxtber_less";
parameter gen3_coeff_9_reqber_data = 5'b0;
parameter gen3_coeff_9_reqber = "g3_coeff_9_reqber";
parameter gen3_coeff_9_ber_meas_data = 6'b0;
parameter gen3_coeff_9_ber_meas = "g3_coeff_9_ber_meas";
parameter gen3_coeff_10_data = 18'b0;
parameter gen3_coeff_10 = "g3_coeff_10";
parameter gen3_coeff_10_sel = "coeff_10";
parameter gen3_coeff_10_preset_hint_data = 3'b0;
parameter gen3_coeff_10_preset_hint = "g3_coeff_10_prst_hint";
parameter gen3_coeff_10_nxtber_more_ptr = 4'b0;
parameter gen3_coeff_10_nxtber_more = "g3_coeff_10_nxtber_more";
parameter gen3_coeff_10_nxtber_less_ptr = 4'b0;
parameter gen3_coeff_10_nxtber_less = "g3_coeff_10_nxtber_less";
parameter gen3_coeff_10_reqber_data = 5'b0;
parameter gen3_coeff_10_reqber = "g3_coeff_10_reqber";
parameter gen3_coeff_10_ber_meas_data = 6'b0;
parameter gen3_coeff_10_ber_meas = "g3_coeff_10_ber_meas";
parameter gen3_coeff_11_data = 18'b0;
parameter gen3_coeff_11 = "g3_coeff_11";
parameter gen3_coeff_11_sel = "coeff_11";
parameter gen3_coeff_11_preset_hint_data = 3'b0;
parameter gen3_coeff_11_preset_hint = "g3_coeff_11_prst_hint";
parameter gen3_coeff_11_nxtber_more_ptr = 4'b0;
parameter gen3_coeff_11_nxtber_more = "g3_coeff_11_nxtber_more";
parameter gen3_coeff_11_nxtber_less_ptr = 4'b0;
parameter gen3_coeff_11_nxtber_less = "g3_coeff_11_nxtber_less";
parameter gen3_coeff_11_reqber_data = 5'b0;
parameter gen3_coeff_11_reqber = "g3_coeff_11_reqber";
parameter gen3_coeff_11_ber_meas_data = 6'b0;
parameter gen3_coeff_11_ber_meas = "g3_coeff_11_ber_meas";
parameter gen3_coeff_12_data = 18'b0;
parameter gen3_coeff_12 = "g3_coeff_12";
parameter gen3_coeff_12_sel = "coeff_12";
parameter gen3_coeff_12_preset_hint_data = 3'b0;
parameter gen3_coeff_12_preset_hint = "g3_coeff_12_prst_hint";
parameter gen3_coeff_12_nxtber_more_ptr = 4'b0;
parameter gen3_coeff_12_nxtber_more = "g3_coeff_12_nxtber_more";
parameter gen3_coeff_12_nxtber_less_ptr = 4'b0;
parameter gen3_coeff_12_nxtber_less = "g3_coeff_12_nxtber_less";
parameter gen3_coeff_12_reqber_data = 5'b0;
parameter gen3_coeff_12_reqber = "g3_coeff_12_reqber";
parameter gen3_coeff_12_ber_meas_data = 6'b0;
parameter gen3_coeff_12_ber_meas = "g3_coeff_12_ber_meas";
parameter gen3_coeff_13_data = 18'b0;
parameter gen3_coeff_13 = "g3_coeff_13";
parameter gen3_coeff_13_sel = "coeff_13";
parameter gen3_coeff_13_preset_hint_data = 3'b0;
parameter gen3_coeff_13_preset_hint = "g3_coeff_13_prst_hint";
parameter gen3_coeff_13_nxtber_more_ptr = 4'b0;
parameter gen3_coeff_13_nxtber_more = "g3_coeff_13_nxtber_more";
parameter gen3_coeff_13_nxtber_less_ptr = 4'b0;
parameter gen3_coeff_13_nxtber_less = "g3_coeff_13_nxtber_less";
parameter gen3_coeff_13_reqber_data = 5'b0;
parameter gen3_coeff_13_reqber = "g3_coeff_13_reqber";
parameter gen3_coeff_13_ber_meas_data = 6'b0;
parameter gen3_coeff_13_ber_meas = "g3_coeff_13_ber_meas";
parameter gen3_coeff_14_data = 18'b0;
parameter gen3_coeff_14 = "g3_coeff_14";
parameter gen3_coeff_14_sel = "coeff_14";
parameter gen3_coeff_14_preset_hint_data = 3'b0;
parameter gen3_coeff_14_preset_hint = "g3_coeff_14_prst_hint";
parameter gen3_coeff_14_nxtber_more_ptr = 4'b0;
parameter gen3_coeff_14_nxtber_more = "g3_coeff_14_nxtber_more";
parameter gen3_coeff_14_nxtber_less_ptr = 4'b0;
parameter gen3_coeff_14_nxtber_less = "g3_coeff_14_nxtber_less";
parameter gen3_coeff_14_reqber_data = 5'b0;
parameter gen3_coeff_14_reqber = "g3_coeff_14_reqber";
parameter gen3_coeff_14_ber_meas_data = 6'b0;
parameter gen3_coeff_14_ber_meas = "g3_coeff_14_ber_meas";
parameter gen3_coeff_15_data = 18'b0;
parameter gen3_coeff_15 = "g3_coeff_15";
parameter gen3_coeff_15_sel = "coeff_15";
parameter gen3_coeff_15_preset_hint_data = 3'b0;
parameter gen3_coeff_15_preset_hint = "g3_coeff_15_prst_hint";
parameter gen3_coeff_15_nxtber_more_ptr = 4'b0;
parameter gen3_coeff_15_nxtber_more = "g3_coeff_15_nxtber_more";
parameter gen3_coeff_15_nxtber_less_ptr = 4'b0;
parameter gen3_coeff_15_nxtber_less = "g3_coeff_15_nxtber_less";
parameter gen3_coeff_15_reqber_data = 5'b0;
parameter gen3_coeff_15_reqber = "g3_coeff_15_reqber";
parameter gen3_coeff_15_ber_meas_data = 6'b0;
parameter gen3_coeff_15_ber_meas = "g3_coeff_15_ber_meas";
parameter gen3_coeff_16_data = 18'b0;
parameter gen3_coeff_16 = "g3_coeff_16";
parameter gen3_coeff_16_sel = "coeff_16";
parameter gen3_coeff_16_preset_hint_data = 3'b0;
parameter gen3_coeff_16_preset_hint = "g3_coeff_16_prst_hint";
parameter gen3_coeff_16_nxtber_more_ptr = 4'b0;
parameter gen3_coeff_16_nxtber_more = "g3_coeff_16_nxtber_more";
parameter gen3_coeff_16_nxtber_less_ptr = 4'b0;
parameter gen3_coeff_16_nxtber_less = "g3_coeff_16_nxtber_less";
parameter gen3_coeff_16_reqber_data = 5'b0;
parameter gen3_coeff_16_reqber = "g3_coeff_16_reqber";
parameter gen3_coeff_16_ber_meas_data = 6'b0;
parameter gen3_coeff_16_ber_meas = "g3_coeff_16_ber_meas";
parameter gen3_preset_coeff_1_data = 18'b0;
parameter gen3_preset_coeff_1 = "g3_prst_coeff_1";
parameter gen3_preset_coeff_2_data = 18'b0;
parameter gen3_preset_coeff_2 = "g3_prst_coeff_2";
parameter gen3_preset_coeff_3_data = 18'b0;
parameter gen3_preset_coeff_3 = "g3_prst_coeff_3";
parameter gen3_preset_coeff_4_data = 18'b0;
parameter gen3_preset_coeff_4 = "g3_prst_coeff_4";
parameter gen3_preset_coeff_5_data = 18'b0;
parameter gen3_preset_coeff_5 = "g3_prst_coeff_5";
parameter gen3_preset_coeff_6_data = 18'b0;
parameter gen3_preset_coeff_6 = "g3_prst_coeff_6";
parameter gen3_preset_coeff_7_data = 18'b0;
parameter gen3_preset_coeff_7 = "g3_prst_coeff_7";
parameter gen3_preset_coeff_8_data = 18'b0;
parameter gen3_preset_coeff_8 = "g3_prst_coeff_8";
parameter gen3_preset_coeff_9_data = 18'b0;
parameter gen3_preset_coeff_9 = "g3_prst_coeff_9";
parameter gen3_preset_coeff_10_data = 18'b0;
parameter gen3_preset_coeff_10 = "g3_prst_coeff_10";
parameter gen3_rxfreqlock_counter_data = 20'b0;
parameter gen3_rxfreqlock_counter = "g3_rxfreqlock_count";
parameter rstctrl_pld_clr = "false";// "false", "true".
parameter rstctrl_debug_en = "false";// "false", "true".
parameter rstctrl_force_inactive_rst = "false";// "false", "true".
parameter rstctrl_perst_enable = "level";// "level", "neg_edge", "not_used".
parameter hrdrstctrl_en = "hrdrstctrl_dis";//"hrdrstctrl_dis", "hrdrstctrl_en".
parameter rstctrl_hip_ep = "hip_ep"; //"hip_ep", "hip_not_ep".
parameter rstctrl_hard_block_enable = "hard_rst_ctl";//"hard_rst_ctl", "pld_rst_ctl".
parameter rstctrl_rx_pma_rstb_inv = "false";//"false", "true".
parameter rstctrl_tx_pma_rstb_inv = "false";//"false", "true".
parameter rstctrl_rx_pcs_rst_n_inv = "false";//"false", "true".
parameter rstctrl_tx_pcs_rst_n_inv = "false";//"false", "true".
parameter rstctrl_altpe3_crst_n_inv = "false";//"false", "true".
parameter rstctrl_altpe3_srst_n_inv = "false";//"false", "true".
parameter rstctrl_altpe3_rst_n_inv = "false";//"false", "true".
parameter rstctrl_tx_pma_syncp_inv = "false";//"false", "true".
parameter rstctrl_1us_count_fref_clk = "rstctrl_1us_cnt";//
parameter rstctrl_1us_count_fref_clk_value = 20'b00000000000000111111;//
parameter rstctrl_1ms_count_fref_clk = "rstctrl_1ms_cnt";//
parameter rstctrl_1ms_count_fref_clk_value = 20'b00001111010000100100;//
parameter rstctrl_off_cal_done_select = "not_active";// "ch0_sel", "ch01_sel", "ch0123_sel", "ch0123_5678_sel", "not_active".
parameter rstctrl_rx_pma_rstb_cmu_select = "not_active";// "ch1cmu_sel", "ch4cmu_sel", "ch4_10cmu_sel", "not_active".
parameter rstctrl_rx_pll_freq_lock_select = "not_active";// "ch0_sel", "ch01_sel", "ch0123_sel", "ch0123_5678_sel", "not_active", "ch0_phs_sel", "ch01_phs_sel", "ch0123_phs_sel", "ch0123_5678_phs_sel".
parameter rstctrl_mask_tx_pll_lock_select = "not_active";// "ch1_sel", "ch4_sel", "ch4_10_sel", "not_active".
parameter rstctrl_rx_pll_lock_select = "not_active";// "ch0_sel", "ch01_sel", "ch0123_sel", "ch0123_5678_sel", "not_active".
parameter rstctrl_perstn_select = "perstn_pin";// "perstn_pin", "perstn_pld".
parameter rstctrl_tx_lc_pll_rstb_select = "not_active";// "ch1_out", "ch7_out", "not_active".
parameter rstctrl_fref_clk_select = "ch0_sel";// "ch0_sel", "ch1_sel", "ch2_sel", "ch3_sel", "ch4_sel", "ch5_sel", "ch6_sel", "ch7_sel", "ch8_sel", "ch9_sel", "ch10_sel", "ch11_sel".
parameter rstctrl_off_cal_en_select = "not_active";// "ch0_out", "ch01_out", "ch0123_out", "ch0123_5678_out", "not_active".
parameter rstctrl_tx_pma_syncp_select = "not_active";// "ch1_out", "ch4_out", "ch4_10_out", "not_active".
parameter rstctrl_rx_pcs_rst_n_select = "not_active";// "ch0_out", "ch01_out", "ch0123_out", "ch012345678_out", "ch012345678_10_out", "not_active".
parameter rstctrl_tx_cmu_pll_lock_select = "not_active";// "ch1_sel", "ch4_sel", "ch4_10_sel", "not_active".
parameter rstctrl_tx_pcs_rst_n_select = "not_active";// "ch0_out", "ch01_out", "ch0123_out", "ch012345678_out", "ch012345678_10_out", "not_active".
parameter rstctrl_tx_lc_pll_lock_select = "not_active";// "ch1_sel", "ch7_sel", "not_active".
parameter rstctrl_timer_a = "rstctrl_timer_a";
parameter rstctrl_timer_a_type = "milli_secs";//possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
parameter rstctrl_timer_a_value = 8'h1;
parameter rstctrl_timer_b = "rstctrl_timer_b";
parameter rstctrl_timer_b_type = "milli_secs";//possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
parameter rstctrl_timer_b_value = 8'h1;
parameter rstctrl_timer_c = "rstctrl_timer_c";
parameter rstctrl_timer_c_type = "milli_secs";//possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
parameter rstctrl_timer_c_value = 8'h1;
parameter rstctrl_timer_d = "rstctrl_timer_d";
parameter rstctrl_timer_d_type = "milli_secs";//possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
parameter rstctrl_timer_d_value = 8'h1;
parameter rstctrl_timer_e = "rstctrl_timer_e";
parameter rstctrl_timer_e_type = "milli_secs";//possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
parameter rstctrl_timer_e_value = 8'h1;
parameter rstctrl_timer_f = "rstctrl_timer_f";
parameter rstctrl_timer_f_type = "milli_secs";//possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
parameter rstctrl_timer_f_value = 8'h1;
parameter rstctrl_timer_g = "rstctrl_timer_g";
parameter rstctrl_timer_g_type = "milli_secs";//possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
parameter rstctrl_timer_g_value = 8'h1;
parameter rstctrl_timer_h = "rstctrl_timer_h";
parameter rstctrl_timer_h_type = "milli_secs";//possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
parameter rstctrl_timer_h_value = 8'h1;
parameter rstctrl_timer_i = "rstctrl_timer_i";
parameter rstctrl_timer_i_type = "milli_secs";//possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
parameter rstctrl_timer_i_value = 8'h1;
parameter rstctrl_timer_j = "rstctrl_timer_j";
parameter rstctrl_timer_j_type = "milli_secs";//possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
parameter rstctrl_timer_j_value = 8'h1;
output [15:0] dpriostatus;
output [31:0] lmidout;
output [0:0] lmiack;
input [0:0] lmirden;
input [0:0] lmiwren;
input [11:0] lmiaddr;
input [31:0] lmidin;
input [0:0] flrreset;
output [0:0] flrsts;
output [0:0] resetstatus;
output [0:0] l2exit;
output [0:0] hotrstexit;
input [0:0] hiphardreset;
output [0:0] dlupexit;
output [0:0] coreclkout;
input [0:0] pldclk;
input [0:0] pldsrst;
input [0:0] pldrst;
input [0:0] pclkch0;
input [0:0] pclkch1;
input [0:0] pclkcentral;
input [0:0] pllfixedclkch0;
input [0:0] pllfixedclkch1;
input [0:0] pllfixedclkcentral;
input [0:0] phyrst;
input [0:0] physrst;
input [0:0] coreclkin;
input [0:0] corerst;
input [0:0] corepor;
input [0:0] corecrst;
input [0:0] coresrst;
output [6:0] swdnout;
output [2:0] swupout;
input [2:0] swdnin;
input [6:0] swupin;
input [1:0] swctmod;
output [255:0] rxstdata;
output [31:0] rxstparity;
output [31:0] rxstbe;
output [3:0] rxsterr;
output [3:0] rxstsop;
output [3:0] rxsteop;
output [1:0] rxstempty;
output [3:0] rxstvalid;
output [7:0] rxstbardec1;
output [7:0] rxstbardec2;
input [0:0] rxstmask;
input [0:0] rxstready;
output [0:0] txstready;
output [5:0] txcredfchipcons;
output [5:0] txcredfcinfinite;
output [7:0] txcredhdrfcp;
output [11:0] txcreddatafcp;
output [7:0] txcredhdrfcnp;
output [11:0] txcreddatafcnp;
output [7:0] txcredhdrfccp;
output [11:0] txcreddatafccp;
input [255:0] txstdata;
input [31:0] txstparity;
input [3:0] txsterr;
input [3:0] txstsop;
input [3:0] txsteop;
input [1:0] txstempty;
input [0:0] txstvalid;
output [0:0] r2cuncecc;
output [0:0] rxcorrecc;
output [0:0] retryuncecc;
output [0:0] retrycorrecc;
output [0:0] rxparerr;
output [1:0] txparerr;
output [0:0] r2cparerr;
output [0:0] pmetosr;
input [0:0] pmetocr;
input [0:0] pmevent;
input [9:0] pmdata;
input [0:0] pmauxpwr;
output [52:0] tlcfgsts;
output [31:0] tlcfgctl;
output [3:0] tlcfgadd;
output [0:0] appintaack;
input [0:0] appintasts;
output [3:0] intstatus;
output [0:0] appmsiack;
input [0:0] appmsireq;
input [2:0] appmsitc;
input [4:0] appmsinum;
input [4:0] aermsinum;
input [4:0] pexmsinum;
input [4:0] hpgctrler;
input [12:0] cfglink2csrpld;
input [7:0] cfgprmbuspld;
output [0:0] csebisshadow;
output [31:0] csebwrdata;
output [3:0] csebwrdataparity;
output [3:0] csebbe;
output [32:0] csebaddr;
output [4:0] csebaddrparity;
output [0:0] csebwren;
output [0:0] csebrden;
output [0:0] csebwrrespreq;
input [31:0] csebrddata;
input [3:0] csebrddataparity;
input [0:0] csebwaitrequest;
input [0:0] csebwrrespvalid;
input [4:0] csebwrresponse;
input [4:0] csebrdresponse;
output [0:0] dlup;
output [255:0] testouthip;
output [63:0] testout1hip;
output [0:0] ev1us;
output [0:0] ev128ns;
output [0:0] wakeoen;
output [0:0] serrout;
output [4:0] ltssmstate;
output [3:0] laneact;
output [1:0] currentspeed;
input [0:0] slotclkcfg;
input [1:0] mode;
input [31:0] testinhip;
input [31:0] testin1hip;
input [0:0] cplpending;
input [6:0] cplerr;
input [1:0] appinterr;
input [0:0] egressblkerr;
input [0:0] pmexitd0ack;
output [0:0] pmexitd0req;
output [17:0] currentcoeff0;
output [17:0] currentcoeff1;
output [17:0] currentcoeff2;
output [17:0] currentcoeff3;
output [17:0] currentcoeff4;
output [17:0] currentcoeff5;
output [17:0] currentcoeff6;
output [17:0] currentcoeff7;
output [2:0] currentrxpreset0;
output [2:0] currentrxpreset1;
output [2:0] currentrxpreset2;
output [2:0] currentrxpreset3;
output [2:0] currentrxpreset4;
output [2:0] currentrxpreset5;
output [2:0] currentrxpreset6;
output [2:0] currentrxpreset7;
output [1:0] rate0;
output [1:0] rate1;
output [1:0] rate2;
output [1:0] rate3;
output [1:0] rate4;
output [1:0] rate5;
output [1:0] rate6;
output [1:0] rate7;
output [0:0] ratetiedtognd;
output [1:0] ratectrl;
output [2:0] eidleinfersel0;
output [2:0] eidleinfersel1;
output [2:0] eidleinfersel2;
output [2:0] eidleinfersel3;
output [2:0] eidleinfersel4;
output [2:0] eidleinfersel5;
output [2:0] eidleinfersel6;
output [2:0] eidleinfersel7;
output [31:0] txdata0;
output [3:0] txdatak0;
output [0:0] txdetectrx0;
output [0:0] txelecidle0;
output [0:0] txcompl0;
output [0:0] rxpolarity0;
output [1:0] powerdown0;
output [0:0] txdataskip0;
output [0:0] txblkst0;
output [1:0] txsynchd0;
output [0:0] txdeemph0;
output [2:0] txmargin0;
input [31:0] rxdata0;
input [3:0] rxdatak0;
input [0:0] rxvalid0;
input [0:0] phystatus0;
input [0:0] rxelecidle0;
input [2:0] rxstatus0;
input [0:0] rxdataskip0;
input [0:0] rxblkst0;
input [1:0] rxsynchd0;
input [0:0] rxfreqlocked0;
output [31:0] txdata1;
output [3:0] txdatak1;
output [0:0] txdetectrx1;
output [0:0] txelecidle1;
output [0:0] txcompl1;
output [0:0] rxpolarity1;
output [1:0] powerdown1;
output [0:0] txdataskip1;
output [0:0] txblkst1;
output [1:0] txsynchd1;
output [0:0] txdeemph1;
output [2:0] txmargin1;
input [31:0] rxdata1;
input [3:0] rxdatak1;
input [0:0] rxvalid1;
input [0:0] phystatus1;
input [0:0] rxelecidle1;
input [2:0] rxstatus1;
input [0:0] rxdataskip1;
input [0:0] rxblkst1;
input [1:0] rxsynchd1;
input [0:0] rxfreqlocked1;
output [31:0] txdata2;
output [3:0] txdatak2;
output [0:0] txdetectrx2;
output [0:0] txelecidle2;
output [0:0] txcompl2;
output [0:0] rxpolarity2;
output [1:0] powerdown2;
output [0:0] txdataskip2;
output [0:0] txblkst2;
output [1:0] txsynchd2;
output [0:0] txdeemph2;
output [2:0] txmargin2;
input [31:0] rxdata2;
input [3:0] rxdatak2;
input [0:0] rxvalid2;
input [0:0] phystatus2;
input [0:0] rxelecidle2;
input [2:0] rxstatus2;
input [0:0] rxdataskip2;
input [0:0] rxblkst2;
input [1:0] rxsynchd2;
input [0:0] rxfreqlocked2;
output [31:0] txdata3;
output [3:0] txdatak3;
output [0:0] txdetectrx3;
output [0:0] txelecidle3;
output [0:0] txcompl3;
output [0:0] rxpolarity3;
output [1:0] powerdown3;
output [0:0] txdataskip3;
output [0:0] txblkst3;
output [1:0] txsynchd3;
output [0:0] txdeemph3;
output [2:0] txmargin3;
input [31:0] rxdata3;
input [3:0] rxdatak3;
input [0:0] rxvalid3;
input [0:0] phystatus3;
input [0:0] rxelecidle3;
input [2:0] rxstatus3;
input [0:0] rxdataskip3;
input [0:0] rxblkst3;
input [1:0] rxsynchd3;
input [0:0] rxfreqlocked3;
output [31:0] txdata4;
output [3:0] txdatak4;
output [0:0] txdetectrx4;
output [0:0] txelecidle4;
output [0:0] txcompl4;
output [0:0] rxpolarity4;
output [1:0] powerdown4;
output [0:0] txdataskip4;
output [0:0] txblkst4;
output [1:0] txsynchd4;
output [0:0] txdeemph4;
output [2:0] txmargin4;
input [31:0] rxdata4;
input [3:0] rxdatak4;
input [0:0] rxvalid4;
input [0:0] phystatus4;
input [0:0] rxelecidle4;
input [2:0] rxstatus4;
input [0:0] rxdataskip4;
input [0:0] rxblkst4;
input [1:0] rxsynchd4;
input [0:0] rxfreqlocked4;
output [31:0] txdata5;
output [3:0] txdatak5;
output [0:0] txdetectrx5;
output [0:0] txelecidle5;
output [0:0] txcompl5;
output [0:0] rxpolarity5;
output [1:0] powerdown5;
output [0:0] txdataskip5;
output [0:0] txblkst5;
output [1:0] txsynchd5;
output [0:0] txdeemph5;
output [2:0] txmargin5;
input [31:0] rxdata5;
input [3:0] rxdatak5;
input [0:0] rxvalid5;
input [0:0] phystatus5;
input [0:0] rxelecidle5;
input [2:0] rxstatus5;
input [0:0] rxdataskip5;
input [0:0] rxblkst5;
input [1:0] rxsynchd5;
input [0:0] rxfreqlocked5;
output [31:0] txdata6;
output [3:0] txdatak6;
output [0:0] txdetectrx6;
output [0:0] txelecidle6;
output [0:0] txcompl6;
output [0:0] rxpolarity6;
output [1:0] powerdown6;
output [0:0] txdataskip6;
output [0:0] txblkst6;
output [1:0] txsynchd6;
output [0:0] txdeemph6;
output [2:0] txmargin6;
input [31:0] rxdata6;
input [3:0] rxdatak6;
input [0:0] rxvalid6;
input [0:0] phystatus6;
input [0:0] rxelecidle6;
input [2:0] rxstatus6;
input [0:0] rxdataskip6;
input [0:0] rxblkst6;
input [1:0] rxsynchd6;
input [0:0] rxfreqlocked6;
output [31:0] txdata7;
output [3:0] txdatak7;
output [0:0] txdetectrx7;
output [0:0] txelecidle7;
output [0:0] txcompl7;
output [0:0] rxpolarity7;
output [1:0] powerdown7;
output [0:0] txdataskip7;
output [0:0] txblkst7;
output [1:0] txsynchd7;
output [0:0] txdeemph7;
output [2:0] txmargin7;
input [31:0] rxdata7;
input [3:0] rxdatak7;
input [0:0] rxvalid7;
input [0:0] phystatus7;
input [0:0] rxelecidle7;
input [2:0] rxstatus7;
input [0:0] rxdataskip7;
input [0:0] rxblkst7;
input [1:0] rxsynchd7;
input [0:0] rxfreqlocked7;
input [43:0] dbgpipex1rx;
input [0:0] memredsclk;
input [0:0] memredenscan;
input [0:0] memredscen;
input [0:0] memredscin;
input [0:0] memredscsel;
input [0:0] memredscrst;
output [0:0] memredscout;
input [0:0] memregscanen;
input [0:0] memregscanin;
input [0:0] memhiptestenable;
output [0:0] memregscanout;
input [0:0] bisttesten;
input [0:0] bistenrpl;
input [0:0] bistscanin;
input [0:0] bistscanen;
input [0:0] bistenrcv;
output [0:0] bistscanoutrpl;
output [0:0] bistdonearpl;
output [0:0] bistdonebrpl;
output [0:0] bistpassrpl;
output [0:0] derrrpl;
output [0:0] derrcorextrpl;
output [0:0] bistscanoutrcv;
output [0:0] bistdonearcv;
output [0:0] bistdonebrcv;
output [0:0] bistpassrcv;
output [0:0] derrcorextrcv;
output [0:0] bistscanoutrcv1;
output [0:0] bistdonearcv1;
output [0:0] bistdonebrcv1;
output [0:0] bistpassrcv1;
output [0:0] derrcorextrcv1;
input [0:0] scanmoden;
input [0:0] scanshiftn;
input [0:0] nfrzdrv;
input [0:0] frzreg;
input [0:0] frzlogic;
input [7:0] idrpl;
input [7:0] idrcv;
input [0:0] plniotri;
input [0:0] entest;
input [0:0] npor;
input [0:0] usermode;
output [0:0] cvpclk;
output [31:0] cvpdata;
output [0:0] cvpstartxfer;
output [0:0] cvpconfig;
output [0:0] cvpfullconfig;
input [0:0] cvpconfigready;
input [0:0] cvpen;
input [0:0] cvpconfigerror;
input [0:0] cvpconfigdone;
input [0:0] pinperstn;
input [0:0] pldperstn;
input [0:0] iocsrrdydly;
input [0:0] softaltpe3rstn;
input [0:0] softaltpe3srstn;
input [0:0] softaltpe3crstn;
input [0:0] pldclrpmapcshipn;
input [0:0] pldclrpcshipn;
input [0:0] pldclrhipn;
output [100:0] s0ch0emsiptieoff;
output [100:0] s0ch1emsiptieoff;
output [100:0] s0ch2emsiptieoff;
output [100:0] s1ch0emsiptieoff;
output [188:0] s1ch1emsiptieoff;
output [100:0] s1ch2emsiptieoff;
output [100:0] s2ch0emsiptieoff;
output [100:0] s2ch1emsiptieoff;
output [100:0] s2ch2emsiptieoff;
output [188:0] s3ch0emsiptieoff;
output [188:0] s3ch1emsiptieoff;
output [188:0] s3ch2emsiptieoff;
output [299:0] emsiptieofftop;
output [299:0] emsiptieoffbot;
// Reset Control Interface Ch0
output [0:0] txpcsrstn0;
output [0:0] rxpcsrstn0;
output [0:0] g3txpcsrstn0;
output [0:0] g3rxpcsrstn0;
output [0:0] txpmasyncp0;
output [0:0] rxpmarstb0;
output [0:0] txlcpllrstb0;
output [0:0] offcalen0;
input [0:0] frefclk0;
input [0:0] offcaldone0;
input [0:0] txlcplllock0;
input [0:0] rxfreqtxcmuplllock0;
input [0:0] rxpllphaselock0;
input [0:0] masktxplllock0;
// Reset Control Interface Ch1
output [0:0] txpcsrstn1;
output [0:0] rxpcsrstn1;
output [0:0] g3txpcsrstn1;
output [0:0] g3rxpcsrstn1;
output [0:0] txpmasyncp1;
output [0:0] rxpmarstb1;
output [0:0] txlcpllrstb1;
output [0:0] offcalen1;
input [0:0] frefclk1;
input [0:0] offcaldone1;
input [0:0] txlcplllock1;
input [0:0] rxfreqtxcmuplllock1;
input [0:0] rxpllphaselock1;
input [0:0] masktxplllock1;
// Reset Control Interface Ch2
output [0:0] txpcsrstn2;
output [0:0] rxpcsrstn2;
output [0:0] g3txpcsrstn2;
output [0:0] g3rxpcsrstn2;
output [0:0] txpmasyncp2;
output [0:0] rxpmarstb2;
output [0:0] txlcpllrstb2;
output [0:0] offcalen2;
input [0:0] frefclk2;
input [0:0] offcaldone2;
input [0:0] txlcplllock2;
input [0:0] rxfreqtxcmuplllock2;
input [0:0] rxpllphaselock2;
input [0:0] masktxplllock2;
// Reset Control Interface Ch3
output [0:0] txpcsrstn3;
output [0:0] rxpcsrstn3;
output [0:0] g3txpcsrstn3;
output [0:0] g3rxpcsrstn3;
output [0:0] txpmasyncp3;
output [0:0] rxpmarstb3;
output [0:0] txlcpllrstb3;
output [0:0] offcalen3;
input [0:0] frefclk3;
input [0:0] offcaldone3;
input [0:0] txlcplllock3;
input [0:0] rxfreqtxcmuplllock3;
input [0:0] rxpllphaselock3;
input [0:0] masktxplllock3;
// Reset Control Interface Ch4
output [0:0] txpcsrstn4;
output [0:0] rxpcsrstn4;
output [0:0] g3txpcsrstn4;
output [0:0] g3rxpcsrstn4;
output [0:0] txpmasyncp4;
output [0:0] rxpmarstb4;
output [0:0] txlcpllrstb4;
output [0:0] offcalen4;
input [0:0] frefclk4;
input [0:0] offcaldone4;
input [0:0] txlcplllock4;
input [0:0] rxfreqtxcmuplllock4;
input [0:0] rxpllphaselock4;
input [0:0] masktxplllock4;
// Reset Control Interface Ch5
output [0:0] txpcsrstn5;
output [0:0] rxpcsrstn5;
output [0:0] g3txpcsrstn5;
output [0:0] g3rxpcsrstn5;
output [0:0] txpmasyncp5;
output [0:0] rxpmarstb5;
output [0:0] txlcpllrstb5;
output [0:0] offcalen5;
input [0:0] frefclk5;
input [0:0] offcaldone5;
input [0:0] txlcplllock5;
input [0:0] rxfreqtxcmuplllock5;
input [0:0] rxpllphaselock5;
input [0:0] masktxplllock5;
// Reset Control Interface Ch6
output [0:0] txpcsrstn6;
output [0:0] rxpcsrstn6;
output [0:0] g3txpcsrstn6;
output [0:0] g3rxpcsrstn6;
output [0:0] txpmasyncp6;
output [0:0] rxpmarstb6;
output [0:0] txlcpllrstb6;
output [0:0] offcalen6;
input [0:0] frefclk6;
input [0:0] offcaldone6;
input [0:0] txlcplllock6;
input [0:0] rxfreqtxcmuplllock6;
input [0:0] rxpllphaselock6;
input [0:0] masktxplllock6;
// Reset Control Interface Ch7
output [0:0] txpcsrstn7;
output [0:0] rxpcsrstn7;
output [0:0] g3txpcsrstn7;
output [0:0] g3rxpcsrstn7;
output [0:0] txpmasyncp7;
output [0:0] rxpmarstb7;
output [0:0] txlcpllrstb7;
output [0:0] offcalen7;
input [0:0] frefclk7;
input [0:0] offcaldone7;
input [0:0] txlcplllock7;
input [0:0] rxfreqtxcmuplllock7;
input [0:0] rxpllphaselock7;
input [0:0] masktxplllock7;
// Reset Control Interface Ch8
output [0:0] txpcsrstn8;
output [0:0] rxpcsrstn8;
output [0:0] g3txpcsrstn8;
output [0:0] g3rxpcsrstn8;
output [0:0] txpmasyncp8;
output [0:0] rxpmarstb8;
output [0:0] txlcpllrstb8;
output [0:0] offcalen8;
input [0:0] frefclk8;
input [0:0] offcaldone8;
input [0:0] txlcplllock8;
input [0:0] rxfreqtxcmuplllock8;
input [0:0] rxpllphaselock8;
input [0:0] masktxplllock8;
// Reset Control Interface Ch9
output [0:0] txpcsrstn9;
output [0:0] rxpcsrstn9;
output [0:0] g3txpcsrstn9;
output [0:0] g3rxpcsrstn9;
output [0:0] txpmasyncp9;
output [0:0] rxpmarstb9;
output [0:0] txlcpllrstb9;
output [0:0] offcalen9;
input [0:0] frefclk9;
input [0:0] offcaldone9;
input [0:0] txlcplllock9;
input [0:0] rxfreqtxcmuplllock9;
input [0:0] rxpllphaselock9;
input [0:0] masktxplllock9;
// Reset Control Interface Ch10
output [0:0] txpcsrstn10;
output [0:0] rxpcsrstn10;
output [0:0] g3txpcsrstn10;
output [0:0] g3rxpcsrstn10;
output [0:0] txpmasyncp10;
output [0:0] rxpmarstb10;
output [0:0] txlcpllrstb10;
output [0:0] offcalen10;
input [0:0] frefclk10;
input [0:0] offcaldone10;
input [0:0] txlcplllock10;
input [0:0] rxfreqtxcmuplllock10;
input [0:0] rxpllphaselock10;
input [0:0] masktxplllock10;
// Reset Control Interface Ch11
output [0:0] txpcsrstn11;
output [0:0] rxpcsrstn11;
output [0:0] g3txpcsrstn11;
output [0:0] g3rxpcsrstn11;
output [0:0] txpmasyncp11;
output [0:0] rxpmarstb11;
output [0:0] txlcpllrstb11;
output [0:0] offcalen11;
input [0:0] frefclk11;
input [0:0] offcaldone11;
input [0:0] txlcplllock11;
input [0:0] rxfreqtxcmuplllock11;
input [0:0] rxpllphaselock11;
input [0:0] masktxplllock11;
input [31:0] reservedin;
input [0:0] reservedclkin;
output [31:0] reservedout;
output [0:0] reservedclkout;
stratixv_hssi_gen3_pcie_hip_encrypted inst (
.dpriostatus(dpriostatus),
.lmidout(lmidout),
.lmiack(lmiack),
.lmirden(lmirden),
.lmiwren(lmiwren),
.lmiaddr(lmiaddr),
.lmidin(lmidin),
.flrreset(flrreset),
.flrsts(flrsts),
.resetstatus(resetstatus),
.l2exit(l2exit),
.hotrstexit(hotrstexit),
.dlupexit(dlupexit),
.coreclkout(coreclkout),
.pldclk(pldclk),
.pldsrst(pldsrst),
.pldrst(pldrst),
.pclkch0(pclkch0),
.pclkch1(pclkch1),
.pclkcentral(pclkcentral),
.pllfixedclkch0(pllfixedclkch0),
.pllfixedclkch1(pllfixedclkch1),
.pllfixedclkcentral(pllfixedclkcentral),
.phyrst(phyrst),
.physrst(physrst),
.coreclkin(coreclkin),
.corerst(corerst),
.corepor(corepor),
.corecrst(corecrst),
.coresrst(coresrst),
.swdnout(swdnout),
.swupout(swupout),
.swdnin(swdnin),
.swupin(swupin),
.swctmod(swctmod),
.rxstdata(rxstdata),
.rxstparity(rxstparity),
.rxstbe(rxstbe),
.rxsterr(rxsterr),
.rxstsop(rxstsop),
.rxsteop(rxsteop),
.rxstempty(rxstempty),
.rxstvalid(rxstvalid),
.rxstbardec1(rxstbardec1),
.rxstbardec2(rxstbardec2),
.rxstmask(rxstmask),
.rxstready(rxstready),
.txstready(txstready),
.txcredfchipcons(txcredfchipcons),
.txcredfcinfinite(txcredfcinfinite),
.txcredhdrfcp(txcredhdrfcp),
.txcreddatafcp(txcreddatafcp),
.txcredhdrfcnp(txcredhdrfcnp),
.txcreddatafcnp(txcreddatafcnp),
.txcredhdrfccp(txcredhdrfccp),
.txcreddatafccp(txcreddatafccp),
.txstdata(txstdata),
.txstparity(txstparity),
.txsterr(txsterr),
.txstsop(txstsop),
.txsteop(txsteop),
.txstempty(txstempty),
.txstvalid(txstvalid),
.r2cuncecc(r2cuncecc),
.rxcorrecc(rxcorrecc),
.retryuncecc(retryuncecc),
.retrycorrecc(retrycorrecc),
.rxparerr(rxparerr),
.txparerr(txparerr),
.r2cparerr(r2cparerr),
.pmetosr(pmetosr),
.pmetocr(pmetocr),
.pmevent(pmevent),
.pmdata(pmdata),
.pmauxpwr(pmauxpwr),
.tlcfgsts(tlcfgsts),
.tlcfgctl(tlcfgctl),
.tlcfgadd(tlcfgadd),
.appintaack(appintaack),
.appintasts(appintasts),
.intstatus(intstatus),
.appmsiack(appmsiack),
.appmsireq(appmsireq),
.appmsitc(appmsitc),
.appmsinum(appmsinum),
.aermsinum(aermsinum),
.pexmsinum(pexmsinum),
.hpgctrler(hpgctrler),
.cfglink2csrpld(cfglink2csrpld),
.cfgprmbuspld(cfgprmbuspld),
.csebisshadow(csebisshadow),
.csebwrdata(csebwrdata),
.csebwrdataparity(csebwrdataparity),
.csebbe(csebbe),
.csebaddr(csebaddr),
.csebaddrparity(csebaddrparity),
.csebwren(csebwren),
.csebrden(csebrden),
.csebwrrespreq(csebwrrespreq),
.csebrddata(csebrddata),
.csebrddataparity(csebrddataparity),
.csebwaitrequest(csebwaitrequest),
.csebwrrespvalid(csebwrrespvalid),
.csebwrresponse(csebwrresponse),
.csebrdresponse(csebrdresponse),
.dlup(dlup),
.testouthip(testouthip),
.testout1hip(testout1hip),
.ev1us(ev1us),
.ev128ns(ev128ns),
.wakeoen(wakeoen),
.serrout(serrout),
.ltssmstate(ltssmstate),
.laneact(laneact),
.currentspeed(currentspeed),
.slotclkcfg(slotclkcfg),
.mode(mode),
.testinhip(testinhip),
.testin1hip(testin1hip),
.cplpending(cplpending),
.cplerr(cplerr),
.appinterr(appinterr),
.egressblkerr(egressblkerr),
.pmexitd0ack(pmexitd0ack),
.pmexitd0req(pmexitd0req),
.currentcoeff0(currentcoeff0),
.currentcoeff1(currentcoeff1),
.currentcoeff2(currentcoeff2),
.currentcoeff3(currentcoeff3),
.currentcoeff4(currentcoeff4),
.currentcoeff5(currentcoeff5),
.currentcoeff6(currentcoeff6),
.currentcoeff7(currentcoeff7),
.currentrxpreset0(currentrxpreset0),
.currentrxpreset1(currentrxpreset1),
.currentrxpreset2(currentrxpreset2),
.currentrxpreset3(currentrxpreset3),
.currentrxpreset4(currentrxpreset4),
.currentrxpreset5(currentrxpreset5),
.currentrxpreset6(currentrxpreset6),
.currentrxpreset7(currentrxpreset7),
.rate0(rate0),
.rate1(rate1),
.rate2(rate2),
.rate3(rate3),
.rate4(rate4),
.rate5(rate5),
.rate6(rate6),
.rate7(rate7),
.ratectrl(ratectrl),
.eidleinfersel0(eidleinfersel0),
.eidleinfersel1(eidleinfersel1),
.eidleinfersel2(eidleinfersel2),
.eidleinfersel3(eidleinfersel3),
.eidleinfersel4(eidleinfersel4),
.eidleinfersel5(eidleinfersel5),
.eidleinfersel6(eidleinfersel6),
.eidleinfersel7(eidleinfersel7),
.txdata0(txdata0),
.txdatak0(txdatak0),
.txdetectrx0(txdetectrx0),
.txelecidle0(txelecidle0),
.txcompl0(txcompl0),
.rxpolarity0(rxpolarity0),
.powerdown0(powerdown0),
.txdataskip0(txdataskip0),
.txblkst0(txblkst0),
.txsynchd0(txsynchd0),
.txdeemph0(txdeemph0),
.txmargin0(txmargin0),
.rxdata0(rxdata0),
.rxdatak0(rxdatak0),
.rxvalid0(rxvalid0),
.phystatus0(phystatus0),
.rxelecidle0(rxelecidle0),
.rxstatus0(rxstatus0),
.rxdataskip0(rxdataskip0),
.rxblkst0(rxblkst0),
.rxsynchd0(rxsynchd0),
.rxfreqlocked0(rxfreqlocked0),
.txdata1(txdata1),
.txdatak1(txdatak1),
.txdetectrx1(txdetectrx1),
.txelecidle1(txelecidle1),
.txcompl1(txcompl1),
.rxpolarity1(rxpolarity1),
.powerdown1(powerdown1),
.txdataskip1(txdataskip1),
.txblkst1(txblkst1),
.txsynchd1(txsynchd1),
.txdeemph1(txdeemph1),
.txmargin1(txmargin1),
.rxdata1(rxdata1),
.rxdatak1(rxdatak1),
.rxvalid1(rxvalid1),
.phystatus1(phystatus1),
.rxelecidle1(rxelecidle1),
.rxstatus1(rxstatus1),
.rxdataskip1(rxdataskip1),
.rxblkst1(rxblkst1),
.rxsynchd1(rxsynchd1),
.rxfreqlocked1(rxfreqlocked1),
.txdata2(txdata2),
.txdatak2(txdatak2),
.txdetectrx2(txdetectrx2),
.txelecidle2(txelecidle2),
.txcompl2(txcompl2),
.rxpolarity2(rxpolarity2),
.powerdown2(powerdown2),
.txdataskip2(txdataskip2),
.txblkst2(txblkst2),
.txsynchd2(txsynchd2),
.txdeemph2(txdeemph2),
.txmargin2(txmargin2),
.rxdata2(rxdata2),
.rxdatak2(rxdatak2),
.rxvalid2(rxvalid2),
.phystatus2(phystatus2),
.rxelecidle2(rxelecidle2),
.rxstatus2(rxstatus2),
.rxdataskip2(rxdataskip2),
.rxblkst2(rxblkst2),
.rxsynchd2(rxsynchd2),
.rxfreqlocked2(rxfreqlocked2),
.txdata3(txdata3),
.txdatak3(txdatak3),
.txdetectrx3(txdetectrx3),
.txelecidle3(txelecidle3),
.txcompl3(txcompl3),
.rxpolarity3(rxpolarity3),
.powerdown3(powerdown3),
.txdataskip3(txdataskip3),
.txblkst3(txblkst3),
.txsynchd3(txsynchd3),
.txdeemph3(txdeemph3),
.txmargin3(txmargin3),
.rxdata3(rxdata3),
.rxdatak3(rxdatak3),
.rxvalid3(rxvalid3),
.phystatus3(phystatus3),
.rxelecidle3(rxelecidle3),
.rxstatus3(rxstatus3),
.rxdataskip3(rxdataskip3),
.rxblkst3(rxblkst3),
.rxsynchd3(rxsynchd3),
.rxfreqlocked3(rxfreqlocked3),
.txdata4(txdata4),
.txdatak4(txdatak4),
.txdetectrx4(txdetectrx4),
.txelecidle4(txelecidle4),
.txcompl4(txcompl4),
.rxpolarity4(rxpolarity4),
.powerdown4(powerdown4),
.txdataskip4(txdataskip4),
.txblkst4(txblkst4),
.txsynchd4(txsynchd4),
.txdeemph4(txdeemph4),
.txmargin4(txmargin4),
.rxdata4(rxdata4),
.rxdatak4(rxdatak4),
.rxvalid4(rxvalid4),
.phystatus4(phystatus4),
.rxelecidle4(rxelecidle4),
.rxstatus4(rxstatus4),
.rxdataskip4(rxdataskip4),
.rxblkst4(rxblkst4),
.rxsynchd4(rxsynchd4),
.rxfreqlocked4(rxfreqlocked4),
.txdata5(txdata5),
.txdatak5(txdatak5),
.txdetectrx5(txdetectrx5),
.txelecidle5(txelecidle5),
.txcompl5(txcompl5),
.rxpolarity5(rxpolarity5),
.powerdown5(powerdown5),
.txdataskip5(txdataskip5),
.txblkst5(txblkst5),
.txsynchd5(txsynchd5),
.txdeemph5(txdeemph5),
.txmargin5(txmargin5),
.rxdata5(rxdata5),
.rxdatak5(rxdatak5),
.rxvalid5(rxvalid5),
.phystatus5(phystatus5),
.rxelecidle5(rxelecidle5),
.rxstatus5(rxstatus5),
.rxdataskip5(rxdataskip5),
.rxblkst5(rxblkst5),
.rxsynchd5(rxsynchd5),
.rxfreqlocked5(rxfreqlocked5),
.txdata6(txdata6),
.txdatak6(txdatak6),
.txdetectrx6(txdetectrx6),
.txelecidle6(txelecidle6),
.txcompl6(txcompl6),
.rxpolarity6(rxpolarity6),
.powerdown6(powerdown6),
.txdataskip6(txdataskip6),
.txblkst6(txblkst6),
.txsynchd6(txsynchd6),
.txdeemph6(txdeemph6),
.txmargin6(txmargin6),
.rxdata6(rxdata6),
.rxdatak6(rxdatak6),
.rxvalid6(rxvalid6),
.phystatus6(phystatus6),
.rxelecidle6(rxelecidle6),
.rxstatus6(rxstatus6),
.rxdataskip6(rxdataskip6),
.rxblkst6(rxblkst6),
.rxsynchd6(rxsynchd6),
.rxfreqlocked6(rxfreqlocked6),
.txdata7(txdata7),
.txdatak7(txdatak7),
.txdetectrx7(txdetectrx7),
.txelecidle7(txelecidle7),
.txcompl7(txcompl7),
.rxpolarity7(rxpolarity7),
.powerdown7(powerdown7),
.txdataskip7(txdataskip7),
.txblkst7(txblkst7),
.txsynchd7(txsynchd7),
.txdeemph7(txdeemph7),
.txmargin7(txmargin7),
.rxdata7(rxdata7),
.rxdatak7(rxdatak7),
.rxvalid7(rxvalid7),
.phystatus7(phystatus7),
.rxelecidle7(rxelecidle7),
.rxstatus7(rxstatus7),
.rxdataskip7(rxdataskip7),
.rxblkst7(rxblkst7),
.rxsynchd7(rxsynchd7),
.rxfreqlocked7(rxfreqlocked7),
.dbgpipex1rx(dbgpipex1rx),
.memredsclk(memredsclk),
.memredenscan(memredenscan),
.memredscen(memredscen),
.memredscin(memredscin),
.memredscsel(memredscsel),
.memredscrst(memredscrst),
.memredscout(memredscout),
.memregscanen(memregscanen),
.memregscanin(memregscanin),
.memhiptestenable(memhiptestenable),
.memregscanout(memregscanout),
.bisttesten(bisttesten),
.bistenrpl(bistenrpl),
.bistscanin(bistscanin),
.bistscanen(bistscanen),
.bistenrcv(bistenrcv),
.bistscanoutrpl(bistscanoutrpl),
.bistdonearpl(bistdonearpl),
.bistdonebrpl(bistdonebrpl),
.bistpassrpl(bistpassrpl),
.derrrpl(derrrpl),
.derrcorextrpl(derrcorextrpl),
.bistscanoutrcv(bistscanoutrcv),
.bistdonearcv(bistdonearcv),
.bistdonebrcv(bistdonebrcv),
.bistpassrcv(bistpassrcv),
.derrcorextrcv(derrcorextrcv),
.bistscanoutrcv1(bistscanoutrcv1),
.bistdonearcv1(bistdonearcv1),
.bistdonebrcv1(bistdonebrcv1),
.bistpassrcv1(bistpassrcv1),
.derrcorextrcv1(derrcorextrcv1),
.scanmoden(scanmoden),
.scanshiftn(scanshiftn),
.nfrzdrv(nfrzdrv),
.frzreg(frzreg),
.frzlogic(frzlogic),
.idrpl(idrpl),
.idrcv(idrcv),
.plniotri(plniotri),
.entest(entest),
.npor(npor),
.usermode(usermode),
.cvpclk(cvpclk),
.cvpdata(cvpdata),
.cvpstartxfer(cvpstartxfer),
.cvpconfig(cvpconfig),
.cvpfullconfig(cvpfullconfig),
.cvpconfigready(cvpconfigready),
.cvpen(cvpen),
.cvpconfigerror(cvpconfigerror),
.cvpconfigdone(cvpconfigdone),
.pinperstn(pinperstn),
.pldperstn(pldperstn),
.iocsrrdydly(iocsrrdydly),
.softaltpe3rstn(softaltpe3rstn),
.softaltpe3srstn(softaltpe3srstn),
.softaltpe3crstn(softaltpe3crstn),
.pldclrpmapcshipn(pldclrpmapcshipn),
.pldclrpcshipn(pldclrpcshipn),
.pldclrhipn(pldclrhipn),
.s0ch0emsiptieoff(s0ch0emsiptieoff),
.s0ch1emsiptieoff(s0ch1emsiptieoff),
.s0ch2emsiptieoff(s0ch2emsiptieoff),
.s1ch0emsiptieoff(s1ch0emsiptieoff),
.s1ch1emsiptieoff(s1ch1emsiptieoff),
.s1ch2emsiptieoff(s1ch2emsiptieoff),
.s2ch0emsiptieoff(s2ch0emsiptieoff),
.s2ch1emsiptieoff(s2ch1emsiptieoff),
.s2ch2emsiptieoff(s2ch2emsiptieoff),
.s3ch0emsiptieoff(s3ch0emsiptieoff),
.s3ch1emsiptieoff(s3ch1emsiptieoff),
.s3ch2emsiptieoff(s3ch2emsiptieoff),
.emsiptieofftop(emsiptieofftop),
.emsiptieoffbot(emsiptieoffbot),
.txpcsrstn0 (txpcsrstn0 ),
.rxpcsrstn0 (rxpcsrstn0 ),
.g3txpcsrstn0 (g3txpcsrstn0 ),
.g3rxpcsrstn0 (g3rxpcsrstn0 ),
.txpmasyncp0 (txpmasyncp0 ),
.rxpmarstb0 (rxpmarstb0 ),
.txlcpllrstb0 (txlcpllrstb0 ),
.offcalen0 (offcalen0 ),
.frefclk0 (frefclk0 ),
.offcaldone0 (offcaldone0 ),
.txlcplllock0 (txlcplllock0 ),
.rxfreqtxcmuplllock0 (rxfreqtxcmuplllock0 ),
.rxpllphaselock0 (rxpllphaselock0 ),
.masktxplllock0 (masktxplllock0 ),
.txpcsrstn1 (txpcsrstn1 ),
.rxpcsrstn1 (rxpcsrstn1 ),
.g3txpcsrstn1 (g3txpcsrstn1 ),
.g3rxpcsrstn1 (g3rxpcsrstn1 ),
.txpmasyncp1 (txpmasyncp1 ),
.rxpmarstb1 (rxpmarstb1 ),
.txlcpllrstb1 (txlcpllrstb1 ),
.offcalen1 (offcalen1 ),
.frefclk1 (frefclk1 ),
.offcaldone1 (offcaldone1 ),
.txlcplllock1 (txlcplllock1 ),
.rxfreqtxcmuplllock1 (rxfreqtxcmuplllock1 ),
.rxpllphaselock1 (rxpllphaselock1 ),
.masktxplllock1 (masktxplllock1 ),
.txpcsrstn2 (txpcsrstn2 ),
.rxpcsrstn2 (rxpcsrstn2 ),
.g3txpcsrstn2 (g3txpcsrstn2 ),
.g3rxpcsrstn2 (g3rxpcsrstn2 ),
.txpmasyncp2 (txpmasyncp2 ),
.rxpmarstb2 (rxpmarstb2 ),
.txlcpllrstb2 (txlcpllrstb2 ),
.offcalen2 (offcalen2 ),
.frefclk2 (frefclk2 ),
.offcaldone2 (offcaldone2 ),
.txlcplllock2 (txlcplllock2 ),
.rxfreqtxcmuplllock2 (rxfreqtxcmuplllock2 ),
.rxpllphaselock2 (rxpllphaselock2 ),
.masktxplllock2 (masktxplllock2 ),
.txpcsrstn3 (txpcsrstn3 ),
.rxpcsrstn3 (rxpcsrstn3 ),
.g3txpcsrstn3 (g3txpcsrstn3 ),
.g3rxpcsrstn3 (g3rxpcsrstn3 ),
.txpmasyncp3 (txpmasyncp3 ),
.rxpmarstb3 (rxpmarstb3 ),
.txlcpllrstb3 (txlcpllrstb3 ),
.offcalen3 (offcalen3 ),
.frefclk3 (frefclk3 ),
.offcaldone3 (offcaldone3 ),
.txlcplllock3 (txlcplllock3 ),
.rxfreqtxcmuplllock3 (rxfreqtxcmuplllock3 ),
.rxpllphaselock3 (rxpllphaselock3 ),
.masktxplllock3 (masktxplllock3 ),
.txpcsrstn4 (txpcsrstn4 ),
.rxpcsrstn4 (rxpcsrstn4 ),
.g3txpcsrstn4 (g3txpcsrstn4 ),
.g3rxpcsrstn4 (g3rxpcsrstn4 ),
.txpmasyncp4 (txpmasyncp4 ),
.rxpmarstb4 (rxpmarstb4 ),
.txlcpllrstb4 (txlcpllrstb4 ),
.offcalen4 (offcalen4 ),
.frefclk4 (frefclk4 ),
.offcaldone4 (offcaldone4 ),
.txlcplllock4 (txlcplllock4 ),
.rxfreqtxcmuplllock4 (rxfreqtxcmuplllock4 ),
.rxpllphaselock4 (rxpllphaselock4 ),
.masktxplllock4 (masktxplllock4 ),
.txpcsrstn5 (txpcsrstn5 ),
.rxpcsrstn5 (rxpcsrstn5 ),
.g3txpcsrstn5 (g3txpcsrstn5 ),
.g3rxpcsrstn5 (g3rxpcsrstn5 ),
.txpmasyncp5 (txpmasyncp5 ),
.rxpmarstb5 (rxpmarstb5 ),
.txlcpllrstb5 (txlcpllrstb5 ),
.offcalen5 (offcalen5 ),
.frefclk5 (frefclk5 ),
.offcaldone5 (offcaldone5 ),
.txlcplllock5 (txlcplllock5 ),
.rxfreqtxcmuplllock5 (rxfreqtxcmuplllock5 ),
.rxpllphaselock5 (rxpllphaselock5 ),
.masktxplllock5 (masktxplllock5 ),
.txpcsrstn6 (txpcsrstn6 ),
.rxpcsrstn6 (rxpcsrstn6 ),
.g3txpcsrstn6 (g3txpcsrstn6 ),
.g3rxpcsrstn6 (g3rxpcsrstn6 ),
.txpmasyncp6 (txpmasyncp6 ),
.rxpmarstb6 (rxpmarstb6 ),
.txlcpllrstb6 (txlcpllrstb6 ),
.offcalen6 (offcalen6 ),
.frefclk6 (frefclk6 ),
.offcaldone6 (offcaldone6 ),
.txlcplllock6 (txlcplllock6 ),
.rxfreqtxcmuplllock6 (rxfreqtxcmuplllock6 ),
.rxpllphaselock6 (rxpllphaselock6 ),
.masktxplllock6 (masktxplllock6 ),
.txpcsrstn7 (txpcsrstn7 ),
.rxpcsrstn7 (rxpcsrstn7 ),
.g3txpcsrstn7 (g3txpcsrstn7 ),
.g3rxpcsrstn7 (g3rxpcsrstn7 ),
.txpmasyncp7 (txpmasyncp7 ),
.rxpmarstb7 (rxpmarstb7 ),
.txlcpllrstb7 (txlcpllrstb7 ),
.offcalen7 (offcalen7 ),
.frefclk7 (frefclk7 ),
.offcaldone7 (offcaldone7 ),
.txlcplllock7 (txlcplllock7 ),
.rxfreqtxcmuplllock7 (rxfreqtxcmuplllock7 ),
.rxpllphaselock7 (rxpllphaselock7 ),
.masktxplllock7 (masktxplllock7 ),
.txpcsrstn8 (txpcsrstn8 ),
.rxpcsrstn8 (rxpcsrstn8 ),
.g3txpcsrstn8 (g3txpcsrstn8 ),
.g3rxpcsrstn8 (g3rxpcsrstn8 ),
.txpmasyncp8 (txpmasyncp8 ),
.rxpmarstb8 (rxpmarstb8 ),
.txlcpllrstb8 (txlcpllrstb8 ),
.offcalen8 (offcalen8 ),
.frefclk8 (frefclk8 ),
.offcaldone8 (offcaldone8 ),
.txlcplllock8 (txlcplllock8 ),
.rxfreqtxcmuplllock8 (rxfreqtxcmuplllock8 ),
.rxpllphaselock8 (rxpllphaselock8 ),
.masktxplllock8 (masktxplllock8 ),
.txpcsrstn9 (txpcsrstn9 ),
.rxpcsrstn9 (rxpcsrstn9 ),
.g3txpcsrstn9 (g3txpcsrstn9 ),
.g3rxpcsrstn9 (g3rxpcsrstn9 ),
.txpmasyncp9 (txpmasyncp9 ),
.rxpmarstb9 (rxpmarstb9 ),
.txlcpllrstb9 (txlcpllrstb9 ),
.offcalen9 (offcalen9 ),
.frefclk9 (frefclk9 ),
.offcaldone9 (offcaldone9 ),
.txlcplllock9 (txlcplllock9 ),
.rxfreqtxcmuplllock9 (rxfreqtxcmuplllock9 ),
.rxpllphaselock9 (rxpllphaselock9 ),
.masktxplllock9 (masktxplllock9 ),
.txpcsrstn10 (txpcsrstn10 ),
.rxpcsrstn10 (rxpcsrstn10 ),
.g3txpcsrstn10 (g3txpcsrstn10 ),
.g3rxpcsrstn10 (g3rxpcsrstn10 ),
.txpmasyncp10 (txpmasyncp10 ),
.rxpmarstb10 (rxpmarstb10 ),
.txlcpllrstb10 (txlcpllrstb10 ),
.offcalen10 (offcalen10 ),
.frefclk10 (frefclk10 ),
.offcaldone10 (offcaldone10 ),
.txlcplllock10 (txlcplllock10 ),
.rxfreqtxcmuplllock10 (rxfreqtxcmuplllock10 ),
.rxpllphaselock10 (rxpllphaselock10 ),
.masktxplllock10 (masktxplllock10 ),
.txpcsrstn11 (txpcsrstn11 ),
.rxpcsrstn11 (rxpcsrstn11 ),
.g3txpcsrstn11 (g3txpcsrstn11 ),
.g3rxpcsrstn11 (g3rxpcsrstn11 ),
.txpmasyncp11 (txpmasyncp11 ),
.rxpmarstb11 (rxpmarstb11 ),
.txlcpllrstb11 (txlcpllrstb11 ),
.offcalen11 (offcalen11 ),
.frefclk11 (frefclk11 ),
.offcaldone11 (offcaldone11 ),
.txlcplllock11 (txlcplllock11 ),
.rxfreqtxcmuplllock11 (rxfreqtxcmuplllock11 ),
.rxpllphaselock11 (rxpllphaselock11 ),
.masktxplllock11 (masktxplllock11 ),
.reservedin(reservedin),
.reservedclkin(reservedclkin),
.reservedout(reservedout),
.reservedclkout(reservedclkout) );
defparam inst.func_mode = func_mode;
defparam inst.bonding_mode = bonding_mode;
defparam inst.prot_mode = prot_mode;
defparam inst.pcie_spec_1p0_compliance = pcie_spec_1p0_compliance;
defparam inst.vc_enable = vc_enable;
defparam inst.enable_slot_register = enable_slot_register;
defparam inst.pcie_mode = pcie_mode;
defparam inst.bypass_cdc = bypass_cdc;
defparam inst.enable_rx_reordering = enable_rx_reordering;
defparam inst.enable_rx_buffer_checking = enable_rx_buffer_checking;
defparam inst.single_rx_detect_data = single_rx_detect_data;
defparam inst.single_rx_detect = single_rx_detect;
defparam inst.use_crc_forwarding = use_crc_forwarding;
defparam inst.bypass_tl = bypass_tl;
defparam inst.gen123_lane_rate_mode = gen123_lane_rate_mode;
defparam inst.lane_mask = lane_mask;
defparam inst.disable_link_x2_support = disable_link_x2_support;
defparam inst.national_inst_thru_enhance = national_inst_thru_enhance;
defparam inst.hip_hard_reset = hip_hard_reset;
defparam inst.dis_paritychk = dis_paritychk;
defparam inst.wrong_device_id = wrong_device_id;
defparam inst.data_pack_rx = data_pack_rx;
defparam inst.ast_width = ast_width;
defparam inst.rx_sop_ctrl = rx_sop_ctrl;
defparam inst.rx_ast_parity = rx_ast_parity;
defparam inst.tx_ast_parity = tx_ast_parity;
defparam inst.ltssm_1ms_timeout = ltssm_1ms_timeout;
defparam inst.ltssm_freqlocked_check = ltssm_freqlocked_check;
defparam inst.deskew_comma = deskew_comma;
defparam inst.dl_tx_check_parity_edb = dl_tx_check_parity_edb;
defparam inst.tl_tx_check_parity_msg = tl_tx_check_parity_msg;
defparam inst.port_link_number_data = port_link_number_data;
defparam inst.port_link_number = port_link_number;
defparam inst.device_number_data = device_number_data;
defparam inst.device_number = device_number;
defparam inst.bypass_clk_switch = bypass_clk_switch;
defparam inst.core_clk_out_sel = core_clk_out_sel;
defparam inst.core_clk_divider = core_clk_divider;
defparam inst.core_clk_source = core_clk_source;
defparam inst.core_clk_sel = core_clk_sel;
defparam inst.enable_ch0_pclk_out = enable_ch0_pclk_out;
defparam inst.enable_ch01_pclk_out = enable_ch01_pclk_out;
defparam inst.pipex1_debug_sel = pipex1_debug_sel;
defparam inst.pclk_out_sel = pclk_out_sel;
defparam inst.vendor_id_data = vendor_id_data;
defparam inst.vendor_id = vendor_id;
defparam inst.device_id_data = device_id_data;
defparam inst.device_id = device_id;
defparam inst.revision_id_data = revision_id_data;
defparam inst.revision_id = revision_id;
defparam inst.class_code_data = class_code_data;
defparam inst.class_code = class_code;
defparam inst.subsystem_vendor_id_data = subsystem_vendor_id_data;
defparam inst.subsystem_vendor_id = subsystem_vendor_id;
defparam inst.subsystem_device_id_data = subsystem_device_id_data;
defparam inst.subsystem_device_id = subsystem_device_id;
defparam inst.no_soft_reset = no_soft_reset;
defparam inst.maximum_current_data = maximum_current_data;
defparam inst.maximum_current = maximum_current;
defparam inst.d1_support = d1_support;
defparam inst.d2_support = d2_support;
defparam inst.d0_pme = d0_pme;
defparam inst.d1_pme = d1_pme;
defparam inst.d2_pme = d2_pme;
defparam inst.d3_hot_pme = d3_hot_pme;
defparam inst.d3_cold_pme = d3_cold_pme;
defparam inst.use_aer = use_aer;
defparam inst.low_priority_vc = low_priority_vc;
defparam inst.vc_arbitration = vc_arbitration;
defparam inst.disable_snoop_packet = disable_snoop_packet;
defparam inst.max_payload_size = max_payload_size;
defparam inst.surprise_down_error_support = surprise_down_error_support;
defparam inst.dll_active_report_support = dll_active_report_support;
defparam inst.extend_tag_field = extend_tag_field;
defparam inst.endpoint_l0_latency_data = endpoint_l0_latency_data;
defparam inst.endpoint_l0_latency = endpoint_l0_latency;
defparam inst.endpoint_l1_latency_data = endpoint_l1_latency_data;
defparam inst.endpoint_l1_latency = endpoint_l1_latency;
defparam inst.indicator_data = indicator_data;
defparam inst.indicator = indicator;
defparam inst.role_based_error_reporting = role_based_error_reporting;
defparam inst.slot_power_scale_data = slot_power_scale_data;
defparam inst.slot_power_scale = slot_power_scale;
defparam inst.max_link_width = max_link_width;
defparam inst.enable_l1_aspm = enable_l1_aspm;
defparam inst.enable_l0s_aspm = enable_l0s_aspm;
defparam inst.l1_exit_latency_sameclock_data = l1_exit_latency_sameclock_data;
defparam inst.l1_exit_latency_sameclock = l1_exit_latency_sameclock;
defparam inst.l1_exit_latency_diffclock_data = l1_exit_latency_diffclock_data;
defparam inst.l1_exit_latency_diffclock = l1_exit_latency_diffclock;
defparam inst.hot_plug_support_data = hot_plug_support_data;
defparam inst.hot_plug_support = hot_plug_support;
defparam inst.slot_power_limit_data = slot_power_limit_data;
defparam inst.slot_power_limit = slot_power_limit;
defparam inst.slot_number_data = slot_number_data;
defparam inst.slot_number = slot_number;
defparam inst.diffclock_nfts_count_data = diffclock_nfts_count_data;
defparam inst.diffclock_nfts_count = diffclock_nfts_count;
defparam inst.sameclock_nfts_count_data = sameclock_nfts_count_data;
defparam inst.sameclock_nfts_count = sameclock_nfts_count;
defparam inst.completion_timeout = completion_timeout;
defparam inst.enable_completion_timeout_disable = enable_completion_timeout_disable;
defparam inst.extended_tag_reset = extended_tag_reset;
defparam inst.ecrc_check_capable = ecrc_check_capable;
defparam inst.ecrc_gen_capable = ecrc_gen_capable;
defparam inst.no_command_completed = no_command_completed;
defparam inst.msi_multi_message_capable = msi_multi_message_capable;
defparam inst.msi_64bit_addressing_capable = msi_64bit_addressing_capable;
defparam inst.msi_masking_capable = msi_masking_capable;
defparam inst.msi_support = msi_support;
defparam inst.interrupt_pin = interrupt_pin;
defparam inst.ena_ido_req = ena_ido_req;
defparam inst.ena_ido_cpl = ena_ido_cpl;
defparam inst.enable_function_msix_support = enable_function_msix_support;
defparam inst.msix_table_size_data = msix_table_size_data;
defparam inst.msix_table_size = msix_table_size;
defparam inst.msix_table_bir_data = msix_table_bir_data;
defparam inst.msix_table_bir = msix_table_bir;
defparam inst.msix_table_offset_data = msix_table_offset_data;
defparam inst.msix_table_offset = msix_table_offset;
defparam inst.msix_pba_bir_data = msix_pba_bir_data;
defparam inst.msix_pba_bir = msix_pba_bir;
defparam inst.msix_pba_offset_data = msix_pba_offset_data;
defparam inst.msix_pba_offset = msix_pba_offset;
defparam inst.bridge_port_vga_enable = bridge_port_vga_enable;
defparam inst.bridge_port_ssid_support = bridge_port_ssid_support;
defparam inst.ssvid_data = ssvid_data;
defparam inst.ssvid = ssvid;
defparam inst.ssid_data = ssid_data;
defparam inst.ssid = ssid;
defparam inst.eie_before_nfts_count_data = eie_before_nfts_count_data;
defparam inst.eie_before_nfts_count = eie_before_nfts_count;
defparam inst.gen2_diffclock_nfts_count_data = gen2_diffclock_nfts_count_data;
defparam inst.gen2_diffclock_nfts_count = gen2_diffclock_nfts_count;
defparam inst.gen2_sameclock_nfts_count_data = gen2_sameclock_nfts_count_data;
defparam inst.gen2_sameclock_nfts_count = gen2_sameclock_nfts_count;
defparam inst.deemphasis_enable = deemphasis_enable;
defparam inst.pcie_spec_version = pcie_spec_version;
defparam inst.l0_exit_latency_sameclock_data = l0_exit_latency_sameclock_data;
defparam inst.l0_exit_latency_sameclock = l0_exit_latency_sameclock;
defparam inst.l0_exit_latency_diffclock_data = l0_exit_latency_diffclock_data;
defparam inst.l0_exit_latency_diffclock = l0_exit_latency_diffclock;
defparam inst.rx_ei_l0s = rx_ei_l0s;
defparam inst.l2_async_logic = l2_async_logic;
defparam inst.aspm_config_management = aspm_config_management;
defparam inst.atomic_op_routing = atomic_op_routing;
defparam inst.atomic_op_completer_32bit = atomic_op_completer_32bit;
defparam inst.atomic_op_completer_64bit = atomic_op_completer_64bit;
defparam inst.cas_completer_128bit = cas_completer_128bit;
defparam inst.ltr_mechanism = ltr_mechanism;
defparam inst.tph_completer = tph_completer;
defparam inst.extended_format_field = extended_format_field;
defparam inst.atomic_malformed = atomic_malformed;
defparam inst.flr_capability = flr_capability;
defparam inst.enable_adapter_half_rate_mode = enable_adapter_half_rate_mode;
defparam inst.vc0_clk_enable = vc0_clk_enable;
defparam inst.vc1_clk_enable = vc1_clk_enable;
defparam inst.register_pipe_signals = register_pipe_signals;
defparam inst.bar0_io_space = bar0_io_space;
defparam inst.bar0_64bit_mem_space = bar0_64bit_mem_space;
defparam inst.bar0_prefetchable = bar0_prefetchable;
defparam inst.bar0_size_mask_data = bar0_size_mask_data;
defparam inst.bar0_size_mask = bar0_size_mask;
defparam inst.bar1_io_space = bar1_io_space;
defparam inst.bar1_64bit_mem_space = bar1_64bit_mem_space;
defparam inst.bar1_prefetchable = bar1_prefetchable;
defparam inst.bar1_size_mask_data = bar1_size_mask_data;
defparam inst.bar1_size_mask = bar1_size_mask;
defparam inst.bar2_io_space = bar2_io_space;
defparam inst.bar2_64bit_mem_space = bar2_64bit_mem_space;
defparam inst.bar2_prefetchable = bar2_prefetchable;
defparam inst.bar2_size_mask_data = bar2_size_mask_data;
defparam inst.bar2_size_mask = bar2_size_mask;
defparam inst.bar3_io_space = bar3_io_space;
defparam inst.bar3_64bit_mem_space = bar3_64bit_mem_space;
defparam inst.bar3_prefetchable = bar3_prefetchable;
defparam inst.bar3_size_mask_data = bar3_size_mask_data;
defparam inst.bar3_size_mask = bar3_size_mask;
defparam inst.bar4_io_space = bar4_io_space;
defparam inst.bar4_64bit_mem_space = bar4_64bit_mem_space;
defparam inst.bar4_prefetchable = bar4_prefetchable;
defparam inst.bar4_size_mask_data = bar4_size_mask_data;
defparam inst.bar4_size_mask = bar4_size_mask;
defparam inst.bar5_io_space = bar5_io_space;
defparam inst.bar5_64bit_mem_space = bar5_64bit_mem_space;
defparam inst.bar5_prefetchable = bar5_prefetchable;
defparam inst.bar5_size_mask_data = bar5_size_mask_data;
defparam inst.bar5_size_mask = bar5_size_mask;
defparam inst.expansion_base_address_register_data = expansion_base_address_register_data;
defparam inst.expansion_base_address_register = expansion_base_address_register;
defparam inst.io_window_addr_width = io_window_addr_width;
defparam inst.prefetchable_mem_window_addr_width = prefetchable_mem_window_addr_width;
defparam inst.skp_os_gen3_count_data = skp_os_gen3_count_data;
defparam inst.skp_os_gen3_count = skp_os_gen3_count;
defparam inst.rx_cdc_almost_empty_data = rx_cdc_almost_empty_data;
defparam inst.rx_cdc_almost_empty = rx_cdc_almost_empty;
defparam inst.tx_cdc_almost_empty_data = tx_cdc_almost_empty_data;
defparam inst.tx_cdc_almost_empty = tx_cdc_almost_empty;
defparam inst.rx_cdc_almost_full_data = rx_cdc_almost_full_data;
defparam inst.rx_cdc_almost_full = rx_cdc_almost_full;
defparam inst.tx_cdc_almost_full_data = tx_cdc_almost_full_data;
defparam inst.tx_cdc_almost_full = tx_cdc_almost_full;
defparam inst.rx_l0s_count_idl_data = rx_l0s_count_idl_data;
defparam inst.rx_l0s_count_idl = rx_l0s_count_idl;
defparam inst.cdc_dummy_insert_limit_data = cdc_dummy_insert_limit_data;
defparam inst.cdc_dummy_insert_limit = cdc_dummy_insert_limit;
defparam inst.ei_delay_powerdown_count_data = ei_delay_powerdown_count_data;
defparam inst.ei_delay_powerdown_count = ei_delay_powerdown_count;
defparam inst.millisecond_cycle_count_data = millisecond_cycle_count_data;
defparam inst.millisecond_cycle_count = millisecond_cycle_count;
defparam inst.skp_os_schedule_count_data = skp_os_schedule_count_data;
defparam inst.skp_os_schedule_count = skp_os_schedule_count;
defparam inst.fc_init_timer_data = fc_init_timer_data;
defparam inst.fc_init_timer = fc_init_timer;
defparam inst.l01_entry_latency_data = l01_entry_latency_data;
defparam inst.l01_entry_latency = l01_entry_latency;
defparam inst.flow_control_update_count_data = flow_control_update_count_data;
defparam inst.flow_control_update_count = flow_control_update_count;
defparam inst.flow_control_timeout_count_data = flow_control_timeout_count_data;
defparam inst.flow_control_timeout_count = flow_control_timeout_count;
defparam inst.vc0_rx_flow_ctrl_posted_header_data = vc0_rx_flow_ctrl_posted_header_data;
defparam inst.vc0_rx_flow_ctrl_posted_header = vc0_rx_flow_ctrl_posted_header;
defparam inst.vc0_rx_flow_ctrl_posted_data_data = vc0_rx_flow_ctrl_posted_data_data;
defparam inst.vc0_rx_flow_ctrl_posted_data = vc0_rx_flow_ctrl_posted_data;
defparam inst.vc0_rx_flow_ctrl_nonposted_header_data = vc0_rx_flow_ctrl_nonposted_header_data;
defparam inst.vc0_rx_flow_ctrl_nonposted_header = vc0_rx_flow_ctrl_nonposted_header;
defparam inst.vc0_rx_flow_ctrl_nonposted_data_data = vc0_rx_flow_ctrl_nonposted_data_data;
defparam inst.vc0_rx_flow_ctrl_nonposted_data = vc0_rx_flow_ctrl_nonposted_data;
defparam inst.vc0_rx_flow_ctrl_compl_header_data = vc0_rx_flow_ctrl_compl_header_data;
defparam inst.vc0_rx_flow_ctrl_compl_header = vc0_rx_flow_ctrl_compl_header;
defparam inst.vc0_rx_flow_ctrl_compl_data_data = vc0_rx_flow_ctrl_compl_data_data;
defparam inst.vc0_rx_flow_ctrl_compl_data = vc0_rx_flow_ctrl_compl_data;
defparam inst.rx_ptr0_posted_dpram_min_data = rx_ptr0_posted_dpram_min_data;
defparam inst.rx_ptr0_posted_dpram_min = rx_ptr0_posted_dpram_min;
defparam inst.rx_ptr0_posted_dpram_max_data = rx_ptr0_posted_dpram_max_data;
defparam inst.rx_ptr0_posted_dpram_max = rx_ptr0_posted_dpram_max;
defparam inst.rx_ptr0_nonposted_dpram_min_data = rx_ptr0_nonposted_dpram_min_data;
defparam inst.rx_ptr0_nonposted_dpram_min = rx_ptr0_nonposted_dpram_min;
defparam inst.rx_ptr0_nonposted_dpram_max_data = rx_ptr0_nonposted_dpram_max_data;
defparam inst.rx_ptr0_nonposted_dpram_max = rx_ptr0_nonposted_dpram_max;
defparam inst.retry_buffer_last_active_address_data = retry_buffer_last_active_address_data;
defparam inst.retry_buffer_last_active_address = retry_buffer_last_active_address;
defparam inst.retry_buffer_memory_settings_data = retry_buffer_memory_settings_data;
defparam inst.retry_buffer_memory_settings = retry_buffer_memory_settings;
defparam inst.vc0_rx_buffer_memory_settings_data = vc0_rx_buffer_memory_settings_data;
defparam inst.vc0_rx_buffer_memory_settings = vc0_rx_buffer_memory_settings;
defparam inst.bist_memory_settings_data = bist_memory_settings_data;
defparam inst.bist_memory_settings = bist_memory_settings;
defparam inst.credit_buffer_allocation_aux = credit_buffer_allocation_aux;
defparam inst.iei_enable_settings = iei_enable_settings;
defparam inst.vsec_id_data = vsec_id_data;
defparam inst.vsec_id = vsec_id;
defparam inst.cvp_rate_sel = cvp_rate_sel;
defparam inst.hard_reset_bypass = hard_reset_bypass;
defparam inst.cvp_data_compressed = cvp_data_compressed;
defparam inst.cvp_data_encrypted = cvp_data_encrypted;
defparam inst.cvp_mode_reset = cvp_mode_reset;
defparam inst.cvp_clk_reset = cvp_clk_reset;
defparam inst.vsec_cap_data = vsec_cap_data;
defparam inst.vsec_cap = vsec_cap;
defparam inst.jtag_id_data = jtag_id_data;
defparam inst.jtag_id = jtag_id;
defparam inst.user_id_data = user_id_data;
defparam inst.user_id = user_id;
defparam inst.cseb_extend_pci = cseb_extend_pci;
defparam inst.cseb_extend_pcie = cseb_extend_pcie;
defparam inst.cseb_cpl_status_during_cvp = cseb_cpl_status_during_cvp;
defparam inst.cseb_route_to_avl_rx_st = cseb_route_to_avl_rx_st;
defparam inst.cseb_config_bypass = cseb_config_bypass;
defparam inst.cseb_cpl_tag_checking = cseb_cpl_tag_checking;
defparam inst.cseb_bar_match_checking = cseb_bar_match_checking;
defparam inst.cseb_min_error_checking = cseb_min_error_checking;
defparam inst.cseb_temp_busy_crs = cseb_temp_busy_crs;
defparam inst.cseb_disable_auto_crs = cseb_disable_auto_crs;
defparam inst.gen3_diffclock_nfts_count_data = gen3_diffclock_nfts_count_data;
defparam inst.gen3_diffclock_nfts_count = gen3_diffclock_nfts_count;
defparam inst.gen3_sameclock_nfts_count_data = gen3_sameclock_nfts_count_data;
defparam inst.gen3_sameclock_nfts_count = gen3_sameclock_nfts_count;
defparam inst.gen3_coeff_errchk = gen3_coeff_errchk;
defparam inst.gen3_paritychk = gen3_paritychk;
defparam inst.gen3_coeff_delay_count_data = gen3_coeff_delay_count_data;
defparam inst.gen3_coeff_delay_count = gen3_coeff_delay_count;
defparam inst.gen3_coeff_1_data = gen3_coeff_1_data;
defparam inst.gen3_coeff_1 = gen3_coeff_1;
defparam inst.gen3_coeff_1_sel = gen3_coeff_1_sel;
defparam inst.gen3_coeff_1_preset_hint_data = gen3_coeff_1_preset_hint_data;
defparam inst.gen3_coeff_1_preset_hint = gen3_coeff_1_preset_hint;
defparam inst.gen3_coeff_1_nxtber_more_ptr = gen3_coeff_1_nxtber_more_ptr;
defparam inst.gen3_coeff_1_nxtber_more = gen3_coeff_1_nxtber_more;
defparam inst.gen3_coeff_1_nxtber_less_ptr = gen3_coeff_1_nxtber_less_ptr;
defparam inst.gen3_coeff_1_nxtber_less = gen3_coeff_1_nxtber_less;
defparam inst.gen3_coeff_1_reqber_data = gen3_coeff_1_reqber_data;
defparam inst.gen3_coeff_1_reqber = gen3_coeff_1_reqber;
defparam inst.gen3_coeff_1_ber_meas_data = gen3_coeff_1_ber_meas_data;
defparam inst.gen3_coeff_1_ber_meas = gen3_coeff_1_ber_meas;
defparam inst.gen3_coeff_2_data = gen3_coeff_2_data;
defparam inst.gen3_coeff_2 = gen3_coeff_2;
defparam inst.gen3_coeff_2_sel = gen3_coeff_2_sel;
defparam inst.gen3_coeff_2_preset_hint_data = gen3_coeff_2_preset_hint_data;
defparam inst.gen3_coeff_2_preset_hint = gen3_coeff_2_preset_hint;
defparam inst.gen3_coeff_2_nxtber_more_ptr = gen3_coeff_2_nxtber_more_ptr;
defparam inst.gen3_coeff_2_nxtber_more = gen3_coeff_2_nxtber_more;
defparam inst.gen3_coeff_2_nxtber_less_ptr = gen3_coeff_2_nxtber_less_ptr;
defparam inst.gen3_coeff_2_nxtber_less = gen3_coeff_2_nxtber_less;
defparam inst.gen3_coeff_2_reqber_data = gen3_coeff_2_reqber_data;
defparam inst.gen3_coeff_2_reqber = gen3_coeff_2_reqber;
defparam inst.gen3_coeff_2_ber_meas_data = gen3_coeff_2_ber_meas_data;
defparam inst.gen3_coeff_2_ber_meas = gen3_coeff_2_ber_meas;
defparam inst.gen3_coeff_3_data = gen3_coeff_3_data;
defparam inst.gen3_coeff_3 = gen3_coeff_3;
defparam inst.gen3_coeff_3_sel = gen3_coeff_3_sel;
defparam inst.gen3_coeff_3_preset_hint_data = gen3_coeff_3_preset_hint_data;
defparam inst.gen3_coeff_3_preset_hint = gen3_coeff_3_preset_hint;
defparam inst.gen3_coeff_3_nxtber_more_ptr = gen3_coeff_3_nxtber_more_ptr;
defparam inst.gen3_coeff_3_nxtber_more = gen3_coeff_3_nxtber_more;
defparam inst.gen3_coeff_3_nxtber_less_ptr = gen3_coeff_3_nxtber_less_ptr;
defparam inst.gen3_coeff_3_nxtber_less = gen3_coeff_3_nxtber_less;
defparam inst.gen3_coeff_3_reqber_data = gen3_coeff_3_reqber_data;
defparam inst.gen3_coeff_3_reqber = gen3_coeff_3_reqber;
defparam inst.gen3_coeff_3_ber_meas_data = gen3_coeff_3_ber_meas_data;
defparam inst.gen3_coeff_3_ber_meas = gen3_coeff_3_ber_meas;
defparam inst.gen3_coeff_4_data = gen3_coeff_4_data;
defparam inst.gen3_coeff_4 = gen3_coeff_4;
defparam inst.gen3_coeff_4_sel = gen3_coeff_4_sel;
defparam inst.gen3_coeff_4_preset_hint_data = gen3_coeff_4_preset_hint_data;
defparam inst.gen3_coeff_4_preset_hint = gen3_coeff_4_preset_hint;
defparam inst.gen3_coeff_4_nxtber_more_ptr = gen3_coeff_4_nxtber_more_ptr;
defparam inst.gen3_coeff_4_nxtber_more = gen3_coeff_4_nxtber_more;
defparam inst.gen3_coeff_4_nxtber_less_ptr = gen3_coeff_4_nxtber_less_ptr;
defparam inst.gen3_coeff_4_nxtber_less = gen3_coeff_4_nxtber_less;
defparam inst.gen3_coeff_4_reqber_data = gen3_coeff_4_reqber_data;
defparam inst.gen3_coeff_4_reqber = gen3_coeff_4_reqber;
defparam inst.gen3_coeff_4_ber_meas_data = gen3_coeff_4_ber_meas_data;
defparam inst.gen3_coeff_4_ber_meas = gen3_coeff_4_ber_meas;
defparam inst.gen3_coeff_5_data = gen3_coeff_5_data;
defparam inst.gen3_coeff_5 = gen3_coeff_5;
defparam inst.gen3_coeff_5_sel = gen3_coeff_5_sel;
defparam inst.gen3_coeff_5_preset_hint_data = gen3_coeff_5_preset_hint_data;
defparam inst.gen3_coeff_5_preset_hint = gen3_coeff_5_preset_hint;
defparam inst.gen3_coeff_5_nxtber_more_ptr = gen3_coeff_5_nxtber_more_ptr;
defparam inst.gen3_coeff_5_nxtber_more = gen3_coeff_5_nxtber_more;
defparam inst.gen3_coeff_5_nxtber_less_ptr = gen3_coeff_5_nxtber_less_ptr;
defparam inst.gen3_coeff_5_nxtber_less = gen3_coeff_5_nxtber_less;
defparam inst.gen3_coeff_5_reqber_data = gen3_coeff_5_reqber_data;
defparam inst.gen3_coeff_5_reqber = gen3_coeff_5_reqber;
defparam inst.gen3_coeff_5_ber_meas_data = gen3_coeff_5_ber_meas_data;
defparam inst.gen3_coeff_5_ber_meas = gen3_coeff_5_ber_meas;
defparam inst.gen3_coeff_6_data = gen3_coeff_6_data;
defparam inst.gen3_coeff_6 = gen3_coeff_6;
defparam inst.gen3_coeff_6_sel = gen3_coeff_6_sel;
defparam inst.gen3_coeff_6_preset_hint_data = gen3_coeff_6_preset_hint_data;
defparam inst.gen3_coeff_6_preset_hint = gen3_coeff_6_preset_hint;
defparam inst.gen3_coeff_6_nxtber_more_ptr = gen3_coeff_6_nxtber_more_ptr;
defparam inst.gen3_coeff_6_nxtber_more = gen3_coeff_6_nxtber_more;
defparam inst.gen3_coeff_6_nxtber_less_ptr = gen3_coeff_6_nxtber_less_ptr;
defparam inst.gen3_coeff_6_nxtber_less = gen3_coeff_6_nxtber_less;
defparam inst.gen3_coeff_6_reqber_data = gen3_coeff_6_reqber_data;
defparam inst.gen3_coeff_6_reqber = gen3_coeff_6_reqber;
defparam inst.gen3_coeff_6_ber_meas_data = gen3_coeff_6_ber_meas_data;
defparam inst.gen3_coeff_6_ber_meas = gen3_coeff_6_ber_meas;
defparam inst.gen3_coeff_7_data = gen3_coeff_7_data;
defparam inst.gen3_coeff_7 = gen3_coeff_7;
defparam inst.gen3_coeff_7_sel = gen3_coeff_7_sel;
defparam inst.gen3_coeff_7_preset_hint_data = gen3_coeff_7_preset_hint_data;
defparam inst.gen3_coeff_7_preset_hint = gen3_coeff_7_preset_hint;
defparam inst.gen3_coeff_7_nxtber_more_ptr = gen3_coeff_7_nxtber_more_ptr;
defparam inst.gen3_coeff_7_nxtber_more = gen3_coeff_7_nxtber_more;
defparam inst.gen3_coeff_7_nxtber_less_ptr = gen3_coeff_7_nxtber_less_ptr;
defparam inst.gen3_coeff_7_nxtber_less = gen3_coeff_7_nxtber_less;
defparam inst.gen3_coeff_7_reqber_data = gen3_coeff_7_reqber_data;
defparam inst.gen3_coeff_7_reqber = gen3_coeff_7_reqber;
defparam inst.gen3_coeff_7_ber_meas_data = gen3_coeff_7_ber_meas_data;
defparam inst.gen3_coeff_7_ber_meas = gen3_coeff_7_ber_meas;
defparam inst.gen3_coeff_8_data = gen3_coeff_8_data;
defparam inst.gen3_coeff_8 = gen3_coeff_8;
defparam inst.gen3_coeff_8_sel = gen3_coeff_8_sel;
defparam inst.gen3_coeff_8_preset_hint_data = gen3_coeff_8_preset_hint_data;
defparam inst.gen3_coeff_8_preset_hint = gen3_coeff_8_preset_hint;
defparam inst.gen3_coeff_8_nxtber_more_ptr = gen3_coeff_8_nxtber_more_ptr;
defparam inst.gen3_coeff_8_nxtber_more = gen3_coeff_8_nxtber_more;
defparam inst.gen3_coeff_8_nxtber_less_ptr = gen3_coeff_8_nxtber_less_ptr;
defparam inst.gen3_coeff_8_nxtber_less = gen3_coeff_8_nxtber_less;
defparam inst.gen3_coeff_8_reqber_data = gen3_coeff_8_reqber_data;
defparam inst.gen3_coeff_8_reqber = gen3_coeff_8_reqber;
defparam inst.gen3_coeff_8_ber_meas_data = gen3_coeff_8_ber_meas_data;
defparam inst.gen3_coeff_8_ber_meas = gen3_coeff_8_ber_meas;
defparam inst.gen3_coeff_9_data = gen3_coeff_9_data;
defparam inst.gen3_coeff_9 = gen3_coeff_9;
defparam inst.gen3_coeff_9_sel = gen3_coeff_9_sel;
defparam inst.gen3_coeff_9_preset_hint_data = gen3_coeff_9_preset_hint_data;
defparam inst.gen3_coeff_9_preset_hint = gen3_coeff_9_preset_hint;
defparam inst.gen3_coeff_9_nxtber_more_ptr = gen3_coeff_9_nxtber_more_ptr;
defparam inst.gen3_coeff_9_nxtber_more = gen3_coeff_9_nxtber_more;
defparam inst.gen3_coeff_9_nxtber_less_ptr = gen3_coeff_9_nxtber_less_ptr;
defparam inst.gen3_coeff_9_nxtber_less = gen3_coeff_9_nxtber_less;
defparam inst.gen3_coeff_9_reqber_data = gen3_coeff_9_reqber_data;
defparam inst.gen3_coeff_9_reqber = gen3_coeff_9_reqber;
defparam inst.gen3_coeff_9_ber_meas_data = gen3_coeff_9_ber_meas_data;
defparam inst.gen3_coeff_9_ber_meas = gen3_coeff_9_ber_meas;
defparam inst.gen3_coeff_10_data = gen3_coeff_10_data;
defparam inst.gen3_coeff_10 = gen3_coeff_10;
defparam inst.gen3_coeff_10_sel = gen3_coeff_10_sel;
defparam inst.gen3_coeff_10_preset_hint_data = gen3_coeff_10_preset_hint_data;
defparam inst.gen3_coeff_10_preset_hint = gen3_coeff_10_preset_hint;
defparam inst.gen3_coeff_10_nxtber_more_ptr = gen3_coeff_10_nxtber_more_ptr;
defparam inst.gen3_coeff_10_nxtber_more = gen3_coeff_10_nxtber_more;
defparam inst.gen3_coeff_10_nxtber_less_ptr = gen3_coeff_10_nxtber_less_ptr;
defparam inst.gen3_coeff_10_nxtber_less = gen3_coeff_10_nxtber_less;
defparam inst.gen3_coeff_10_reqber_data = gen3_coeff_10_reqber_data;
defparam inst.gen3_coeff_10_reqber = gen3_coeff_10_reqber;
defparam inst.gen3_coeff_10_ber_meas_data = gen3_coeff_10_ber_meas_data;
defparam inst.gen3_coeff_10_ber_meas = gen3_coeff_10_ber_meas;
defparam inst.gen3_coeff_11_data = gen3_coeff_11_data;
defparam inst.gen3_coeff_11 = gen3_coeff_11;
defparam inst.gen3_coeff_11_sel = gen3_coeff_11_sel;
defparam inst.gen3_coeff_11_preset_hint_data = gen3_coeff_11_preset_hint_data;
defparam inst.gen3_coeff_11_preset_hint = gen3_coeff_11_preset_hint;
defparam inst.gen3_coeff_11_nxtber_more_ptr = gen3_coeff_11_nxtber_more_ptr;
defparam inst.gen3_coeff_11_nxtber_more = gen3_coeff_11_nxtber_more;
defparam inst.gen3_coeff_11_nxtber_less_ptr = gen3_coeff_11_nxtber_less_ptr;
defparam inst.gen3_coeff_11_nxtber_less = gen3_coeff_11_nxtber_less;
defparam inst.gen3_coeff_11_reqber_data = gen3_coeff_11_reqber_data;
defparam inst.gen3_coeff_11_reqber = gen3_coeff_11_reqber;
defparam inst.gen3_coeff_11_ber_meas_data = gen3_coeff_11_ber_meas_data;
defparam inst.gen3_coeff_11_ber_meas = gen3_coeff_11_ber_meas;
defparam inst.gen3_coeff_12_data = gen3_coeff_12_data;
defparam inst.gen3_coeff_12 = gen3_coeff_12;
defparam inst.gen3_coeff_12_sel = gen3_coeff_12_sel;
defparam inst.gen3_coeff_12_preset_hint_data = gen3_coeff_12_preset_hint_data;
defparam inst.gen3_coeff_12_preset_hint = gen3_coeff_12_preset_hint;
defparam inst.gen3_coeff_12_nxtber_more_ptr = gen3_coeff_12_nxtber_more_ptr;
defparam inst.gen3_coeff_12_nxtber_more = gen3_coeff_12_nxtber_more;
defparam inst.gen3_coeff_12_nxtber_less_ptr = gen3_coeff_12_nxtber_less_ptr;
defparam inst.gen3_coeff_12_nxtber_less = gen3_coeff_12_nxtber_less;
defparam inst.gen3_coeff_12_reqber_data = gen3_coeff_12_reqber_data;
defparam inst.gen3_coeff_12_reqber = gen3_coeff_12_reqber;
defparam inst.gen3_coeff_12_ber_meas_data = gen3_coeff_12_ber_meas_data;
defparam inst.gen3_coeff_12_ber_meas = gen3_coeff_12_ber_meas;
defparam inst.gen3_coeff_13_data = gen3_coeff_13_data;
defparam inst.gen3_coeff_13 = gen3_coeff_13;
defparam inst.gen3_coeff_13_sel = gen3_coeff_13_sel;
defparam inst.gen3_coeff_13_preset_hint_data = gen3_coeff_13_preset_hint_data;
defparam inst.gen3_coeff_13_preset_hint = gen3_coeff_13_preset_hint;
defparam inst.gen3_coeff_13_nxtber_more_ptr = gen3_coeff_13_nxtber_more_ptr;
defparam inst.gen3_coeff_13_nxtber_more = gen3_coeff_13_nxtber_more;
defparam inst.gen3_coeff_13_nxtber_less_ptr = gen3_coeff_13_nxtber_less_ptr;
defparam inst.gen3_coeff_13_nxtber_less = gen3_coeff_13_nxtber_less;
defparam inst.gen3_coeff_13_reqber_data = gen3_coeff_13_reqber_data;
defparam inst.gen3_coeff_13_reqber = gen3_coeff_13_reqber;
defparam inst.gen3_coeff_13_ber_meas_data = gen3_coeff_13_ber_meas_data;
defparam inst.gen3_coeff_13_ber_meas = gen3_coeff_13_ber_meas;
defparam inst.gen3_coeff_14_data = gen3_coeff_14_data;
defparam inst.gen3_coeff_14 = gen3_coeff_14;
defparam inst.gen3_coeff_14_sel = gen3_coeff_14_sel;
defparam inst.gen3_coeff_14_preset_hint_data = gen3_coeff_14_preset_hint_data;
defparam inst.gen3_coeff_14_preset_hint = gen3_coeff_14_preset_hint;
defparam inst.gen3_coeff_14_nxtber_more_ptr = gen3_coeff_14_nxtber_more_ptr;
defparam inst.gen3_coeff_14_nxtber_more = gen3_coeff_14_nxtber_more;
defparam inst.gen3_coeff_14_nxtber_less_ptr = gen3_coeff_14_nxtber_less_ptr;
defparam inst.gen3_coeff_14_nxtber_less = gen3_coeff_14_nxtber_less;
defparam inst.gen3_coeff_14_reqber_data = gen3_coeff_14_reqber_data;
defparam inst.gen3_coeff_14_reqber = gen3_coeff_14_reqber;
defparam inst.gen3_coeff_14_ber_meas_data = gen3_coeff_14_ber_meas_data;
defparam inst.gen3_coeff_14_ber_meas = gen3_coeff_14_ber_meas;
defparam inst.gen3_coeff_15_data = gen3_coeff_15_data;
defparam inst.gen3_coeff_15 = gen3_coeff_15;
defparam inst.gen3_coeff_15_sel = gen3_coeff_15_sel;
defparam inst.gen3_coeff_15_preset_hint_data = gen3_coeff_15_preset_hint_data;
defparam inst.gen3_coeff_15_preset_hint = gen3_coeff_15_preset_hint;
defparam inst.gen3_coeff_15_nxtber_more_ptr = gen3_coeff_15_nxtber_more_ptr;
defparam inst.gen3_coeff_15_nxtber_more = gen3_coeff_15_nxtber_more;
defparam inst.gen3_coeff_15_nxtber_less_ptr = gen3_coeff_15_nxtber_less_ptr;
defparam inst.gen3_coeff_15_nxtber_less = gen3_coeff_15_nxtber_less;
defparam inst.gen3_coeff_15_reqber_data = gen3_coeff_15_reqber_data;
defparam inst.gen3_coeff_15_reqber = gen3_coeff_15_reqber;
defparam inst.gen3_coeff_15_ber_meas_data = gen3_coeff_15_ber_meas_data;
defparam inst.gen3_coeff_15_ber_meas = gen3_coeff_15_ber_meas;
defparam inst.gen3_coeff_16_data = gen3_coeff_16_data;
defparam inst.gen3_coeff_16 = gen3_coeff_16;
defparam inst.gen3_coeff_16_sel = gen3_coeff_16_sel;
defparam inst.gen3_coeff_16_preset_hint_data = gen3_coeff_16_preset_hint_data;
defparam inst.gen3_coeff_16_preset_hint = gen3_coeff_16_preset_hint;
defparam inst.gen3_coeff_16_nxtber_more_ptr = gen3_coeff_16_nxtber_more_ptr;
defparam inst.gen3_coeff_16_nxtber_more = gen3_coeff_16_nxtber_more;
defparam inst.gen3_coeff_16_nxtber_less_ptr = gen3_coeff_16_nxtber_less_ptr;
defparam inst.gen3_coeff_16_nxtber_less = gen3_coeff_16_nxtber_less;
defparam inst.gen3_coeff_16_reqber_data = gen3_coeff_16_reqber_data;
defparam inst.gen3_coeff_16_reqber = gen3_coeff_16_reqber;
defparam inst.gen3_coeff_16_ber_meas_data = gen3_coeff_16_ber_meas_data;
defparam inst.gen3_coeff_16_ber_meas = gen3_coeff_16_ber_meas;
defparam inst.gen3_preset_coeff_1_data = gen3_preset_coeff_1_data;
defparam inst.gen3_preset_coeff_1 = gen3_preset_coeff_1;
defparam inst.gen3_preset_coeff_2_data = gen3_preset_coeff_2_data;
defparam inst.gen3_preset_coeff_2 = gen3_preset_coeff_2;
defparam inst.gen3_preset_coeff_3_data = gen3_preset_coeff_3_data;
defparam inst.gen3_preset_coeff_3 = gen3_preset_coeff_3;
defparam inst.gen3_preset_coeff_4_data = gen3_preset_coeff_4_data;
defparam inst.gen3_preset_coeff_4 = gen3_preset_coeff_4;
defparam inst.gen3_preset_coeff_5_data = gen3_preset_coeff_5_data;
defparam inst.gen3_preset_coeff_5 = gen3_preset_coeff_5;
defparam inst.gen3_preset_coeff_6_data = gen3_preset_coeff_6_data;
defparam inst.gen3_preset_coeff_6 = gen3_preset_coeff_6;
defparam inst.gen3_preset_coeff_7_data = gen3_preset_coeff_7_data;
defparam inst.gen3_preset_coeff_7 = gen3_preset_coeff_7;
defparam inst.gen3_preset_coeff_8_data = gen3_preset_coeff_8_data;
defparam inst.gen3_preset_coeff_8 = gen3_preset_coeff_8;
defparam inst.gen3_preset_coeff_9_data = gen3_preset_coeff_9_data;
defparam inst.gen3_preset_coeff_9 = gen3_preset_coeff_9;
defparam inst.gen3_preset_coeff_10_data = gen3_preset_coeff_10_data;
defparam inst.gen3_preset_coeff_10 = gen3_preset_coeff_10;
defparam inst.gen3_rxfreqlock_counter_data = gen3_rxfreqlock_counter_data;
defparam inst.gen3_rxfreqlock_counter = gen3_rxfreqlock_counter;
defparam inst.rstctrl_pld_clr = rstctrl_pld_clr ;
defparam inst.rstctrl_debug_en = rstctrl_debug_en ;
defparam inst.rstctrl_force_inactive_rst = rstctrl_force_inactive_rst ;
defparam inst.rstctrl_perst_enable = rstctrl_perst_enable ;
defparam inst.hrdrstctrl_en = hrdrstctrl_en ;
defparam inst.rstctrl_hip_ep = rstctrl_hip_ep ;
defparam inst.rstctrl_hard_block_enable = rstctrl_hard_block_enable ;
defparam inst.rstctrl_rx_pma_rstb_inv = rstctrl_rx_pma_rstb_inv ;
defparam inst.rstctrl_tx_pma_rstb_inv = rstctrl_tx_pma_rstb_inv ;
defparam inst.rstctrl_rx_pcs_rst_n_inv = rstctrl_rx_pcs_rst_n_inv ;
defparam inst.rstctrl_tx_pcs_rst_n_inv = rstctrl_tx_pcs_rst_n_inv ;
defparam inst.rstctrl_altpe3_crst_n_inv = rstctrl_altpe3_crst_n_inv ;
defparam inst.rstctrl_altpe3_srst_n_inv = rstctrl_altpe3_srst_n_inv ;
defparam inst.rstctrl_altpe3_rst_n_inv = rstctrl_altpe3_rst_n_inv ;
defparam inst.rstctrl_tx_pma_syncp_inv = rstctrl_tx_pma_syncp_inv ;
defparam inst.rstctrl_1us_count_fref_clk = rstctrl_1us_count_fref_clk ;
defparam inst.rstctrl_1us_count_fref_clk_value = rstctrl_1us_count_fref_clk_value ;
defparam inst.rstctrl_1ms_count_fref_clk = rstctrl_1ms_count_fref_clk ;
defparam inst.rstctrl_1ms_count_fref_clk_value = rstctrl_1ms_count_fref_clk_value ;
defparam inst.rstctrl_off_cal_done_select = rstctrl_off_cal_done_select ;
defparam inst.rstctrl_rx_pma_rstb_cmu_select = rstctrl_rx_pma_rstb_cmu_select ;
defparam inst.rstctrl_rx_pll_freq_lock_select = rstctrl_rx_pll_freq_lock_select ;
defparam inst.rstctrl_mask_tx_pll_lock_select = rstctrl_mask_tx_pll_lock_select ;
defparam inst.rstctrl_rx_pll_lock_select = rstctrl_rx_pll_lock_select ;
defparam inst.rstctrl_perstn_select = rstctrl_perstn_select ;
defparam inst.rstctrl_tx_lc_pll_rstb_select = rstctrl_tx_lc_pll_rstb_select ;
defparam inst.rstctrl_fref_clk_select = rstctrl_fref_clk_select ;
defparam inst.rstctrl_off_cal_en_select = rstctrl_off_cal_en_select ;
defparam inst.rstctrl_tx_pma_syncp_select = rstctrl_tx_pma_syncp_select ;
defparam inst.rstctrl_rx_pcs_rst_n_select = rstctrl_rx_pcs_rst_n_select ;
defparam inst.rstctrl_tx_cmu_pll_lock_select = rstctrl_tx_cmu_pll_lock_select ;
defparam inst.rstctrl_tx_pcs_rst_n_select = rstctrl_tx_pcs_rst_n_select ;
defparam inst.rstctrl_tx_lc_pll_lock_select = rstctrl_tx_lc_pll_lock_select ;
defparam inst.rstctrl_timer_a = rstctrl_timer_a ;
defparam inst.rstctrl_timer_a_type = rstctrl_timer_a_type ;
defparam inst.rstctrl_timer_a_value = rstctrl_timer_a_value ;
defparam inst.rstctrl_timer_b = rstctrl_timer_b ;
defparam inst.rstctrl_timer_b_type = rstctrl_timer_b_type ;
defparam inst.rstctrl_timer_b_value = rstctrl_timer_b_value ;
defparam inst.rstctrl_timer_c = rstctrl_timer_c ;
defparam inst.rstctrl_timer_c_type = rstctrl_timer_c_type ;
defparam inst.rstctrl_timer_c_value = rstctrl_timer_c_value ;
defparam inst.rstctrl_timer_d = rstctrl_timer_d ;
defparam inst.rstctrl_timer_d_type = rstctrl_timer_d_type ;
defparam inst.rstctrl_timer_d_value = rstctrl_timer_d_value ;
defparam inst.rstctrl_timer_e = rstctrl_timer_e ;
defparam inst.rstctrl_timer_e_type = rstctrl_timer_e_type ;
defparam inst.rstctrl_timer_e_value = rstctrl_timer_e_value ;
defparam inst.rstctrl_timer_f = rstctrl_timer_f ;
defparam inst.rstctrl_timer_f_type = rstctrl_timer_f_type ;
defparam inst.rstctrl_timer_f_value = rstctrl_timer_f_value ;
defparam inst.rstctrl_timer_g = rstctrl_timer_g ;
defparam inst.rstctrl_timer_g_type = rstctrl_timer_g_type ;
defparam inst.rstctrl_timer_g_value = rstctrl_timer_g_value ;
defparam inst.rstctrl_timer_h = rstctrl_timer_h ;
defparam inst.rstctrl_timer_h_type = rstctrl_timer_h_type ;
defparam inst.rstctrl_timer_h_value = rstctrl_timer_h_value ;
defparam inst.rstctrl_timer_i = rstctrl_timer_i ;
defparam inst.rstctrl_timer_i_type = rstctrl_timer_i_type ;
defparam inst.rstctrl_timer_i_value = rstctrl_timer_i_value ;
defparam inst.rstctrl_timer_j = rstctrl_timer_j ;
defparam inst.rstctrl_timer_j_type = rstctrl_timer_j_type ;
defparam inst.rstctrl_timer_j_value = rstctrl_timer_j_value ;
endmodule //stratixv_hssi_gen3_pcie_hip
|
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module sub32 (
dataa,
datab,
clock,
aclr,
clken,
result)/* synthesis synthesis_clearbox = 1 */;
input [31:0] dataa;
input [31:0] datab;
input clock;
input aclr;
input clken;
output [31:0] result;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPVGND_SYMBOL_V
`define SKY130_FD_SC_MS__TAPVGND_SYMBOL_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__tapvgnd ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPVGND_SYMBOL_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIEBus_pcie_bram_top_7x.v
// Version : 1.11
// Description : bram wrapper for Tx and Rx
// given the pcie block attributes calculate the number of brams
// and pipeline stages and instantiate the brams
//
// Hierarchy:
// pcie_bram_top top level
// pcie_brams pcie_bram instantiations,
// pipeline stages (if any),
// address decode logic (if any),
// datapath muxing (if any)
// pcie_bram bram library cell wrapper
// the pcie_bram module can have a paramter that
// specifies the family (V6, V5, V4)
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
module PCIEBus_pcie_bram_top_7x
#(
parameter IMPL_TARGET = "HARD", // the implementation target : HARD, SOFT
parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 0, // MPS Supported : 0 - 128 B, 1 - 256 B, 2 - 512 B, 3 - 1024 B
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1, // PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08, // PCIe Link Width : 1 / 2 / 4 / 8
parameter VC0_TX_LASTPACKET = 31, // Number of Packets in Transmit
parameter TLM_TX_OVERHEAD = 24, // Overhead Bytes for Packets (Transmit)
parameter TL_TX_RAM_RADDR_LATENCY = 1, // BRAM Read Address Latency (Transmit)
parameter TL_TX_RAM_RDATA_LATENCY = 2, // BRAM Read Data Latency (Transmit)
parameter TL_TX_RAM_WRITE_LATENCY = 1, // BRAM Write Latency (Transmit)
parameter VC0_RX_RAM_LIMIT = 'h1FFF, // RAM Size (Receive)
parameter TL_RX_RAM_RADDR_LATENCY = 1, // BRAM Read Address Latency (Receive)
parameter TL_RX_RAM_RDATA_LATENCY = 2, // BRAM Read Data Latency (Receive)
parameter TL_RX_RAM_WRITE_LATENCY = 1 // BRAM Write Latency (Receive)
)
(
input user_clk_i, // Clock input
input reset_i, // Reset input
input mim_tx_wen, // Write Enable for Transmit path BRAM
input [12:0] mim_tx_waddr, // Write Address for Transmit path BRAM
input [71:0] mim_tx_wdata, // Write Data for Transmit path BRAM
input mim_tx_ren, // Read Enable for Transmit path BRAM
input mim_tx_rce, // Read Output Register Clock Enable for Transmit path BRAM
input [12:0] mim_tx_raddr, // Read Address for Transmit path BRAM
output [71:0] mim_tx_rdata, // Read Data for Transmit path BRAM
input mim_rx_wen, // Write Enable for Receive path BRAM
input [12:0] mim_rx_waddr, // Write Enable for Receive path BRAM
input [71:0] mim_rx_wdata, // Write Enable for Receive path BRAM
input mim_rx_ren, // Read Enable for Receive path BRAM
input mim_rx_rce, // Read Output Register Clock Enable for Receive path BRAM
input [12:0] mim_rx_raddr, // Read Address for Receive path BRAM
output [71:0] mim_rx_rdata // Read Data for Receive path BRAM
);
// TX calculations
localparam MPS_BYTES = ((DEV_CAP_MAX_PAYLOAD_SUPPORTED == 0) ? 128 :
(DEV_CAP_MAX_PAYLOAD_SUPPORTED == 1) ? 256 :
(DEV_CAP_MAX_PAYLOAD_SUPPORTED == 2) ? 512 :
1024 );
localparam BYTES_TX = (VC0_TX_LASTPACKET + 1) * (MPS_BYTES + TLM_TX_OVERHEAD);
localparam ROWS_TX = 1;
localparam COLS_TX = ((BYTES_TX <= 4096) ? 1 :
(BYTES_TX <= 8192) ? 2 :
(BYTES_TX <= 16384) ? 4 :
(BYTES_TX <= 32768) ? 8 :
18
);
// RX calculations
localparam ROWS_RX = 1;
localparam COLS_RX = ((VC0_RX_RAM_LIMIT < 'h0200) ? 1 :
(VC0_RX_RAM_LIMIT < 'h0400) ? 2 :
(VC0_RX_RAM_LIMIT < 'h0800) ? 4 :
(VC0_RX_RAM_LIMIT < 'h1000) ? 8 :
18
);
initial begin
$display("[%t] %m ROWS_TX %0d COLS_TX %0d", $time, ROWS_TX, COLS_TX);
$display("[%t] %m ROWS_RX %0d COLS_RX %0d", $time, ROWS_RX, COLS_RX);
end
PCIEBus_pcie_brams_7x #(
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
.IMPL_TARGET ( IMPL_TARGET ),
.NUM_BRAMS ( COLS_TX ),
.RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ),
.RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ),
.RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY )
)
pcie_brams_tx (
.user_clk_i ( user_clk_i ),
.reset_i ( reset_i ),
.waddr ( mim_tx_waddr ),
.wen ( mim_tx_wen ),
.ren ( mim_tx_ren ),
.rce ( mim_tx_rce ),
.wdata ( mim_tx_wdata ),
.raddr ( mim_tx_raddr ),
.rdata ( mim_tx_rdata )
);
PCIEBus_pcie_brams_7x #(
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
.IMPL_TARGET ( IMPL_TARGET ),
.NUM_BRAMS ( COLS_RX ),
.RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ),
.RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ),
.RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY )
) pcie_brams_rx (
.user_clk_i ( user_clk_i ),
.reset_i ( reset_i ),
.waddr ( mim_rx_waddr ),
.wen ( mim_rx_wen ),
.ren ( mim_rx_ren ),
.rce ( mim_rx_rce ),
.wdata ( mim_rx_wdata ),
.raddr ( mim_rx_raddr ),
.rdata ( mim_rx_rdata )
);
endmodule // pcie_bram_top
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: rxr_engine_classic.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The RXR Engine (Ultrascale) takes a single stream of
// AXI packets and provides the completion packets on the RXR Interface.
// This Engine is capable of operating at "line rate".
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh"
`include "ultrascale.vh"
module rxr_engine_ultrascale
#(parameter C_PCI_DATA_WIDTH = 128,
parameter C_RX_PIPELINE_DEPTH=10)
(// Interface: Clocks
input CLK,
// Interface: Resets
input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_RXR_RST,
// Interface: CQ
input M_AXIS_CQ_TVALID,
input M_AXIS_CQ_TLAST,
input [C_PCI_DATA_WIDTH-1:0] M_AXIS_CQ_TDATA,
input [(C_PCI_DATA_WIDTH/32)-1:0] M_AXIS_CQ_TKEEP,
input [`SIG_CQ_TUSER_W-1:0] M_AXIS_CQ_TUSER,
output M_AXIS_CQ_TREADY,
// Interface: RXR Engine
output [C_PCI_DATA_WIDTH-1:0] RXR_DATA,
output RXR_DATA_VALID,
output [(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_WORD_ENABLE,
output RXR_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_START_OFFSET,
output RXR_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_END_OFFSET,
output [`SIG_FBE_W-1:0] RXR_META_FDWBE,
output [`SIG_LBE_W-1:0] RXR_META_LDWBE,
output [`SIG_TC_W-1:0] RXR_META_TC,
output [`SIG_ATTR_W-1:0] RXR_META_ATTR,
output [`SIG_TAG_W-1:0] RXR_META_TAG,
output [`SIG_TYPE_W-1:0] RXR_META_TYPE,
output [`SIG_ADDR_W-1:0] RXR_META_ADDR,
output [`SIG_BARDECODE_W-1:0] RXR_META_BAR_DECODED,
output [`SIG_REQID_W-1:0] RXR_META_REQUESTER_ID,
output [`SIG_LEN_W-1:0] RXR_META_LENGTH,
output RXR_META_EP
);
// Width of the Byte Enable Shift register
localparam C_RX_BE_W = (`SIG_FBE_W + `SIG_LBE_W);
localparam C_RX_INPUT_STAGES = 0;
localparam C_RX_OUTPUT_STAGES = 2; // Should always be at least one
localparam C_RX_COMPUTATION_STAGES = 1;
localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES;
// CYCLE = LOW ORDER BIT (INDEX) / C_PCI_DATA_WIDTH
localparam C_RX_ADDRDW0_CYCLE = (`UPKT_RXR_ADDRDW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_ADDRDW1_CYCLE = (`UPKT_RXR_ADDRDW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_METADW0_CYCLE = (`UPKT_RXR_METADW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_METADW1_CYCLE = (`UPKT_RXR_METADW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_PAYLOAD_CYCLE = (`UPKT_RXR_PAYLOAD_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_BE_CYCLE = C_RX_INPUT_STAGES; // Available on the first cycle (as per the spec)
localparam C_RX_ADDRDW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXR_ADDRDW0_I%C_PCI_DATA_WIDTH);
localparam C_RX_ADDRDW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXR_ADDRDW1_I%C_PCI_DATA_WIDTH);
localparam C_RX_METADW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXR_METADW0_I%C_PCI_DATA_WIDTH);
localparam C_RX_METADW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXR_METADW1_I%C_PCI_DATA_WIDTH);
localparam C_RX_BE_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES;
// Mask width of the calculated SOF/EOF fields
localparam C_OFFSET_WIDTH = clog2s(C_PCI_DATA_WIDTH/32);
wire wMAxisCqSop;
wire wMAxisCqTlast;
wire [C_RX_PIPELINE_DEPTH:0] wRxSrSop;
wire [C_RX_PIPELINE_DEPTH:0] wRxSrEop;
wire [C_RX_PIPELINE_DEPTH:0] wRxSrDataValid;
wire [(C_RX_PIPELINE_DEPTH+1)*C_RX_BE_W-1:0] wRxSrBe;
wire [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] wRxSrData;
wire wRxrDataValid;
wire wRxrDataReady; // Pinned High
wire wRxrDataEndFlag;
wire [C_OFFSET_WIDTH-1:0] wRxrDataEndOffset;
wire wRxrDataStartFlag;
wire [C_OFFSET_WIDTH-1:0] wRxrDataStartOffset;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wRxrDataWordEnable;
wire [127:0] wRxrHdr;
wire [`SIG_TYPE_W-1:0] wRxrType;
wire [`SIG_FBE_W-1:0] wRxrMetaFdwbe;
wire [`SIG_LBE_W-1:0] wRxrMetaLdwbe;
wire [C_RX_BE_W-1:0] wRxrBe;
wire [`SIG_BARDECODE_W-1:0] wRxrBarDecoded;
wire [127:0] wHdr;
wire wEndFlag;
wire wEndFlagLastCycle;
wire _wEndFlag;
wire [C_OFFSET_WIDTH-1:0] wEndOffset;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wEndMask;
wire _wStartFlag;
wire wStartFlag;
wire [1:0] wStartFlags;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wStartMask;
wire [C_OFFSET_WIDTH-1:0] wStartOffset;
wire [C_RX_BE_W-1:0] wByteEnables;
wire [`SIG_BARDECODE_W-1:0] wBarDecoded;
wire wHasPayload;
wire [`SIG_TYPE_W-1:0] wType;
reg rValid,_rValid;
reg rRST;
assign DONE_RXR_RST = ~rRST;
assign wMAxisCqSop = M_AXIS_CQ_TUSER[`UPKT_CQ_TUSER_SOP_R];
assign wMAxisCqTlast = M_AXIS_CQ_TLAST;
assign wBarDecoded = (8'b0000_0001 << wHdr[`UPKT_RXR_BARID_R]);
// We assert the end flag on the last cycle of a packet, however on single
// cycle packets we need to check that there wasn't an end flag last cycle
// (because wStartFlag will take priority when setting rValid) so we can
// deassert rValid if necessary.
assign wEndFlag = wRxSrEop[C_RX_INPUT_STAGES + C_RX_COMPUTATION_STAGES];
assign wEndFlagLastCycle = wRxSrEop[C_RX_INPUT_STAGES + C_RX_COMPUTATION_STAGES + 1];
/* verilator lint_off WIDTH */
assign wStartOffset = 4;
assign wEndOffset = wHdr[`UPKT_RXR_LENGTH_I +: C_OFFSET_WIDTH] + ((`UPKT_RXR_MAXHDR_W-32)/32);
/* verilator lint_on WIDTH */
// Output assignments. See the header file derived from the user
// guide for indices.
assign RXR_META_EP = wRxrHdr[`UPKT_RXR_EP_R];
assign RXR_META_LENGTH = wRxrHdr[`UPKT_RXR_LENGTH_I+:`SIG_LEN_W];// The top three bits are ignored (fine)
assign RXR_META_ATTR = wRxrHdr[`UPKT_RXR_ATTR_R];
assign RXR_META_TC = wRxrHdr[`UPKT_RXR_TC_R];
assign RXR_META_TYPE = wRxrType;
assign RXR_META_REQUESTER_ID = wRxrHdr[`UPKT_RXR_REQID_R];
assign RXR_META_TAG = wRxrHdr[`UPKT_RXR_TAG_R];
assign RXR_META_FDWBE = wRxrMetaFdwbe;
assign RXR_META_LDWBE = wRxrMetaLdwbe;
assign RXR_META_ADDR = {wRxrHdr[`UPKT_RXR_ADDR_R],2'b0};
assign RXR_DATA_START_FLAG = wRxrDataStartFlag;
assign RXR_DATA_START_OFFSET = 0;
assign RXR_DATA_END_FLAG = wRxrDataEndFlag;
assign RXR_DATA_END_OFFSET = wEndOffset;
assign RXR_META_BAR_DECODED = wRxrBarDecoded;
assign RXR_DATA_VALID = wRxrDataValid;
assign RXR_DATA = wRxSrData[(C_TOTAL_STAGES)*C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH];
assign M_AXIS_CQ_TREADY = 1'b1;
assign wType = upkt_to_trellis_type({wHdr[`UPKT_RXR_TYPE_R], wHdr[`UPKT_RXR_LENGTH_R] != 0});
assign _wEndFlag = wRxSrEop[C_RX_INPUT_STAGES];
assign wEndFlag = wRxSrEop[C_RX_INPUT_STAGES+1];
assign _wStartFlag = wStartFlags != 0;
assign wHasPayload = ~wType[`TRLS_TYPE_PAY_I];
assign wStartMask = {C_PCI_DATA_WIDTH/32{1'b1}} << ({C_OFFSET_WIDTH{wStartFlag}}& wStartOffset[C_OFFSET_WIDTH-1:0]);
generate
if(C_PCI_DATA_WIDTH == 64) begin
assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 2] & ~rValid;
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wRxSrEop[C_RX_INPUT_STAGES]; // No Payload
end else if (C_PCI_DATA_WIDTH == 128) begin
assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 1] & ~rValid;
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES] & wRxSrEop[C_RX_INPUT_STAGES]; // No Payload
end else begin // 256
assign wStartFlags[1] = 0;
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES];
end // else: !if(C_PCI_DATA_WIDTH == 128)
endgenerate
always @(*) begin
_rValid = rValid;
if(_wStartFlag) begin
_rValid = 1'b1;
end else if (wEndFlag) begin
_rValid = 1'b0;
end
end
always @(posedge CLK) begin
if(rRST) begin
rValid <= 1'b0;
end else begin
rValid <= _rValid;
end
end
always @(posedge CLK) begin
rRST <= RST_BUS | RST_LOGIC;
end
register
#(// Parameters
.C_WIDTH (32),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
meta_DW1_register
(// Outputs
.RD_DATA (wHdr[127:96]),
// Inputs
.RST_IN (0),
.WR_DATA (wRxSrData[C_RX_METADW1_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_METADW1_CYCLE]),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (32),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
metadata_DW0_register
(// Outputs
.RD_DATA (wHdr[95:64]),
// Inputs
.RST_IN (0),
.WR_DATA (wRxSrData[C_RX_METADW0_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_METADW0_CYCLE]),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (32),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
addr_DW1_register
(// Outputs
.RD_DATA (wHdr[63:32]),
// Inputs
.RST_IN (0),
.WR_DATA (wRxSrData[C_RX_ADDRDW1_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_ADDRDW1_CYCLE]),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (32),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
addr_DW0_register
(// Outputs
.RD_DATA (wHdr[31:0]),
// Inputs
.RST_IN (0),
.WR_DATA (wRxSrData[C_RX_ADDRDW0_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_ADDRDW0_CYCLE]),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (C_RX_BE_W),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
be_register
(// Outputs
.RD_DATA (wByteEnables),
// Inputs
.RST_IN (0),
.WR_DATA (wRxSrBe[C_RX_BE_INDEX +: C_RX_BE_W]),
.WR_EN (wRxSrSop[C_RX_BE_CYCLE]),
/*AUTOINST*/
// Inputs
.CLK (CLK));
// Shift register for input data with output taps for each delayed
// cycle.
shiftreg
#(// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (C_PCI_DATA_WIDTH),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
data_shiftreg_inst
(// Outputs
.RD_DATA (wRxSrData),
// Inputs
.WR_DATA (M_AXIS_CQ_TDATA),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
// Start Flag Shift Register. Data enables are derived from the
// taps on this shift register.
shiftreg
#(// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (1'b1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
sop_shiftreg_inst
(// Outputs
.RD_DATA (wRxSrSop),
// Inputs
.WR_DATA (wMAxisCqSop & M_AXIS_CQ_TVALID),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
// End Flag Shift Register.
shiftreg
#(// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (1'b1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
eop_shiftreg_inst
(// Outputs
.RD_DATA (wRxSrEop),
// Inputs
.WR_DATA (wMAxisCqTlast),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
// Data Valid Shift Register. Data enables are derived from the
// taps on this shift register.
shiftreg
#(// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (1'b1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
valid_shiftreg_inst
(// Outputs
.RD_DATA (wRxSrDataValid),
// Inputs
.WR_DATA (M_AXIS_CQ_TVALID),
.RST_IN (rRst),
/*AUTOINST*/
// Inputs
.CLK (CLK));
// Shift register for input data with output taps for each delayed
// cycle.
shiftreg
#(// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (C_RX_BE_W),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
be_shiftreg_inst
(// Outputs
.RD_DATA (wRxSrBe),
// Inputs
.WR_DATA (M_AXIS_CQ_TUSER[`UPKT_CQ_TUSER_BE_R]),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (1),
.C_VALUE (1'b0)
/*AUTOINSTPARAM*/)
start_flag_register
(// Outputs
.RD_DATA (wStartFlag),
// Inputs
.WR_DATA (_wStartFlag),
.WR_EN (1),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
offset_to_mask
#(// Parameters
.C_MASK_SWAP (0),
.C_MASK_WIDTH (C_PCI_DATA_WIDTH/32)
/*AUTOINSTPARAM*/)
o2m_ef
(// Outputs
.MASK (wEndMask),
// Inputs
.OFFSET_ENABLE (wEndFlag),
.OFFSET (wEndOffset)
/*AUTOINST*/);
generate
if(C_RX_OUTPUT_STAGES == 0) begin
assign RXR_DATA_WORD_ENABLE = {wEndMask & wStartMask} & {C_PCI_DATA_WIDTH/32{~rValid | wHasPayload}};
end else begin
register
#(// Parameters
.C_WIDTH (C_PCI_DATA_WIDTH/32),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
dw_enable
(// Outputs
.RD_DATA (wRxrDataWordEnable),
// Inputs
.RST_IN (~rValid | wHasPayload),
.WR_DATA (wEndMask & wStartMask),
.WR_EN (1),
/*AUTOINST*/
// Inputs
.CLK (CLK));
pipeline
#(// Parameters
.C_DEPTH (C_RX_OUTPUT_STAGES-1),
.C_WIDTH (C_PCI_DATA_WIDTH/32),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
dw_pipeline
(// Outputs
.WR_DATA_READY (), // Pinned to 1
.RD_DATA (RXR_DATA_WORD_ENABLE),
.RD_DATA_VALID (),
// Inputs
.WR_DATA (wRxrDataWordEnable),
.WR_DATA_VALID (1),
.RD_DATA_READY (1'b1),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
end
endgenerate
pipeline
#(// Parameters
.C_DEPTH (C_RX_OUTPUT_STAGES),
.C_WIDTH (`UPKT_RXR_MAXHDR_W + 2*(1 + C_OFFSET_WIDTH) +
`SIG_LBE_W + `SIG_FBE_W + `SIG_BARDECODE_W +
`SIG_TYPE_W),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_pipeline
(// Outputs
.WR_DATA_READY (), // Pinned to 1
.RD_DATA ({wRxrHdr,wRxrBarDecoded,wRxrType,wRxrDataStartFlag,wRxrDataStartOffset,wRxrDataEndFlag,wRxrDataEndOffset,wRxrMetaLdwbe,wRxrMetaFdwbe}),
.RD_DATA_VALID (wRxrDataValid),
// Inputs
.WR_DATA ({wHdr,wBarDecoded,wType,wStartFlag,wStartOffset[C_OFFSET_WIDTH-1:0],wEndFlag,wEndOffset[C_OFFSET_WIDTH-1:0],wByteEnables}),
.WR_DATA_VALID (rValid),
.RD_DATA_READY (1'b1),
.RST_IN (rRST),
/*AUTOINST*/
// Inputs
.CLK (CLK));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common/")
// End:
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// verilator lint_off BLKANDNBLK
// verilator lint_off COMBDLY
// verilator lint_off UNOPT
// verilator lint_off UNOPTFLAT
// verilator lint_off MULTIDRIVEN
reg [31:0] runnerm1, runner; initial runner = 0;
reg [31:0] runcount; initial runcount = 0;
reg [31:0] clkrun; initial clkrun = 0;
reg [31:0] clkcount; initial clkcount = 0;
always @ (/*AS*/runner) begin
runnerm1 = runner - 32'd1;
end
reg run0;
always @ (/*AS*/runnerm1) begin
if ((runner & 32'hf)!=0) begin
runcount = runcount + 1;
runner = runnerm1;
$write (" seq runcount=%0d runner =%0x\n",runcount, runnerm1);
end
run0 = (runner[8:4]!=0 && runner[3:0]==0);
end
always @ (posedge run0) begin
// Do something that forces another combo run
clkcount <= clkcount + 1;
runner[8:4] <= runner[8:4] - 1;
runner[3:0] <= 3;
$write ("[%0t] posedge runner=%0x\n", $time, runner);
end
reg [7:0] cyc; initial cyc=0;
always @ (posedge clk) begin
$write("[%0t] %x counts %0x %0x\n",$time,cyc,runcount,clkcount);
cyc <= cyc + 8'd1;
case (cyc)
8'd00: begin
runner <= 0;
end
8'd01: begin
runner <= 32'h35;
end
default: ;
endcase
case (cyc)
8'd02: begin
if (runcount!=32'he) $stop;
if (clkcount!=32'h3) $stop;
end
8'd03: begin
$write("*-* All Finished *-*\n");
$finish;
end
default: ;
endcase
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIeGen2x8If128_pipe_eq.v
// Version : 3.2
//------------------------------------------------------------------------------
// Filename : pipe_eq.v
// Description : PIPE Equalization Module for 7 Series Transceiver
// Version : 20.1
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE Equalization Module ------------------------------------------
(* DowngradeIPIdentifiedWarnings = "yes" *)
module PCIeGen2x8If128_pipe_eq #
(
parameter PCIE_SIM_MODE = "FALSE",
parameter PCIE_GT_DEVICE = "GTX",
parameter PCIE_RXEQ_MODE_GEN3 = 1
)
(
//---------- Input -------------------------------------
input EQ_CLK,
input EQ_RST_N,
input EQ_GEN3,
input [ 1:0] EQ_TXEQ_CONTROL,
input [ 3:0] EQ_TXEQ_PRESET,
input [ 3:0] EQ_TXEQ_PRESET_DEFAULT,
input [ 5:0] EQ_TXEQ_DEEMPH_IN,
input [ 1:0] EQ_RXEQ_CONTROL,
input [ 2:0] EQ_RXEQ_PRESET,
input [ 5:0] EQ_RXEQ_LFFS,
input [ 3:0] EQ_RXEQ_TXPRESET,
input EQ_RXEQ_USER_EN,
input [17:0] EQ_RXEQ_USER_TXCOEFF,
input EQ_RXEQ_USER_MODE,
//---------- Output ------------------------------------
output EQ_TXEQ_DEEMPH,
output [ 4:0] EQ_TXEQ_PRECURSOR,
output [ 6:0] EQ_TXEQ_MAINCURSOR,
output [ 4:0] EQ_TXEQ_POSTCURSOR,
output [17:0] EQ_TXEQ_DEEMPH_OUT,
output EQ_TXEQ_DONE,
output [ 5:0] EQ_TXEQ_FSM,
output [17:0] EQ_RXEQ_NEW_TXCOEFF,
output EQ_RXEQ_LFFS_SEL,
output EQ_RXEQ_ADAPT_DONE,
output EQ_RXEQ_DONE,
output [ 5:0] EQ_RXEQ_FSM
);
//---------- Input Registers ---------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] txeq_control_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txeq_preset_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] txeq_deemph_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] txeq_control_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txeq_preset_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] txeq_deemph_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rxeq_control_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] rxeq_preset_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] rxeq_lffs_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] rxeq_txpreset_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_en_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] rxeq_user_txcoeff_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_mode_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rxeq_control_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] rxeq_preset_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] rxeq_lffs_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] rxeq_txpreset_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_en_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] rxeq_user_txcoeff_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_mode_reg2;
//---------- Internal Signals --------------------------
reg [18:0] txeq_preset = 19'd0;
reg txeq_preset_done = 1'd0;
reg [ 1:0] txeq_txcoeff_cnt = 2'd0;
reg [ 2:0] rxeq_preset = 3'd0;
reg rxeq_preset_valid = 1'd0;
reg [ 3:0] rxeq_txpreset = 4'd0;
reg [17:0] rxeq_txcoeff = 18'd0;
reg [ 2:0] rxeq_cnt = 3'd0;
reg [ 5:0] rxeq_fs = 6'd0;
reg [ 5:0] rxeq_lf = 6'd0;
reg rxeq_new_txcoeff_req = 1'd0;
//---------- Output Registers --------------------------
reg [18:0] txeq_txcoeff = 19'd0;
reg txeq_done = 1'd0;
reg [ 5:0] fsm_tx = 6'd0;
reg [17:0] rxeq_new_txcoeff = 18'd0;
reg rxeq_lffs_sel = 1'd0;
reg rxeq_adapt_done_reg = 1'd0;
reg rxeq_adapt_done = 1'd0;
reg rxeq_done = 1'd0;
reg [ 5:0] fsm_rx = 6'd0;
//---------- RXEQ Eye Scan Module Output ---------------
wire rxeqscan_lffs_sel;
wire rxeqscan_preset_done;
wire [17:0] rxeqscan_new_txcoeff;
wire rxeqscan_new_txcoeff_done;
wire rxeqscan_adapt_done;
//---------- FSM ---------------------------------------
localparam FSM_TXEQ_IDLE = 6'b000001;
localparam FSM_TXEQ_PRESET = 6'b000010;
localparam FSM_TXEQ_TXCOEFF = 6'b000100;
localparam FSM_TXEQ_REMAP = 6'b001000;
localparam FSM_TXEQ_QUERY = 6'b010000;
localparam FSM_TXEQ_DONE = 6'b100000;
localparam FSM_RXEQ_IDLE = 6'b000001;
localparam FSM_RXEQ_PRESET = 6'b000010;
localparam FSM_RXEQ_TXCOEFF = 6'b000100;
localparam FSM_RXEQ_LF = 6'b001000;
localparam FSM_RXEQ_NEW_TXCOEFF_REQ = 6'b010000;
localparam FSM_RXEQ_DONE = 6'b100000;
//---------- TXEQ Presets Look-up Table ----------------
// TXPRECURSOR = Coefficient range between 0 and 20 units
// TXMAINCURSOR = Coefficient range between 29 and 80 units
// TXPOSTCURSOR = Coefficient range between 0 and 31 units
//------------------------------------------------------
// Actual Full Swing (FS) = 80
// Actual Low Frequency (LF) = 29
// Advertise Full Swing (FS) = 40
// Advertise Low Frequency (LF) = 15
//------------------------------------------------------
// Pre-emphasis = 20 log [80 - (2 * TXPRECURSOR)] / 80], assuming no de-emphasis
// Main-emphasis = 80 - (TXPRECURSOR + TXPOSTCURSOR)
// De-emphasis = 20 log [80 - (2 * TXPOSTCURSOR)] / 80], assuming no pre-emphasis
//------------------------------------------------------
// Note: TXMAINCURSOR calculated internally in GT
//------------------------------------------------------
localparam TXPRECURSOR_00 = 6'd0; // 0.0 dB
localparam TXMAINCURSOR_00 = 7'd60;
localparam TXPOSTCURSOR_00 = 6'd20; // -6.0 +/- 1 dB
localparam TXPRECURSOR_01 = 6'd0; // 0.0 dB
localparam TXMAINCURSOR_01 = 7'd68; // added 1 to compensate decimal
localparam TXPOSTCURSOR_01 = 6'd13; // -3.5 +/- 1 dB
localparam TXPRECURSOR_02 = 6'd0; // 0.0 dB
localparam TXMAINCURSOR_02 = 7'd64;
localparam TXPOSTCURSOR_02 = 6'd16; // -4.4 +/- 1.5 dB
localparam TXPRECURSOR_03 = 6'd0; // 0.0 dB
localparam TXMAINCURSOR_03 = 7'd70;
localparam TXPOSTCURSOR_03 = 6'd10; // -2.5 +/- 1 dB
localparam TXPRECURSOR_04 = 6'd0; // 0.0 dB
localparam TXMAINCURSOR_04 = 7'd80;
localparam TXPOSTCURSOR_04 = 6'd0; // 0.0 dB
localparam TXPRECURSOR_05 = 6'd8; // -1.9 +/- 1 dB
localparam TXMAINCURSOR_05 = 7'd72;
localparam TXPOSTCURSOR_05 = 6'd0; // 0.0 dB
localparam TXPRECURSOR_06 = 6'd10; // -2.5 +/- 1 dB
localparam TXMAINCURSOR_06 = 7'd70;
localparam TXPOSTCURSOR_06 = 6'd0; // 0.0 dB
localparam TXPRECURSOR_07 = 6'd8; // -3.5 +/- 1 dB
localparam TXMAINCURSOR_07 = 7'd56;
localparam TXPOSTCURSOR_07 = 6'd16; // -6.0 +/- 1 dB
localparam TXPRECURSOR_08 = 6'd10; // -3.5 +/- 1 dB
localparam TXMAINCURSOR_08 = 7'd60;
localparam TXPOSTCURSOR_08 = 6'd10; // -3.5 +/- 1 dB
localparam TXPRECURSOR_09 = 6'd13; // -3.5 +/- 1 dB
localparam TXMAINCURSOR_09 = 7'd68; // added 1 to compensate decimal
localparam TXPOSTCURSOR_09 = 6'd0; // 0.0 dB
localparam TXPRECURSOR_10 = 6'd0; // 0.0 dB
localparam TXMAINCURSOR_10 = 7'd56; // added 1 to compensate decimal
localparam TXPOSTCURSOR_10 = 6'd25; // 9.5 +/- 1 dB, updated for coefficient rules
//---------- Input FF ----------------------------------------------------------
always @ (posedge EQ_CLK)
begin
if (!EQ_RST_N)
begin
//---------- 1st Stage FF --------------------------
gen3_reg1 <= 1'd0;
txeq_control_reg1 <= 2'd0;
txeq_preset_reg1 <= 4'd0;
txeq_deemph_reg1 <= 6'd1;
rxeq_control_reg1 <= 2'd0;
rxeq_preset_reg1 <= 3'd0;
rxeq_lffs_reg1 <= 6'd0;
rxeq_txpreset_reg1 <= 4'd0;
rxeq_user_en_reg1 <= 1'd0;
rxeq_user_txcoeff_reg1 <= 18'd0;
rxeq_user_mode_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
gen3_reg2 <= 1'd0;
txeq_control_reg2 <= 2'd0;
txeq_preset_reg2 <= 4'd0;
txeq_deemph_reg2 <= 6'd1;
rxeq_control_reg2 <= 2'd0;
rxeq_preset_reg2 <= 3'd0;
rxeq_lffs_reg2 <= 6'd0;
rxeq_txpreset_reg2 <= 4'd0;
rxeq_user_en_reg2 <= 1'd0;
rxeq_user_txcoeff_reg2 <= 18'd0;
rxeq_user_mode_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
gen3_reg1 <= EQ_GEN3;
txeq_control_reg1 <= EQ_TXEQ_CONTROL;
txeq_preset_reg1 <= EQ_TXEQ_PRESET;
txeq_deemph_reg1 <= EQ_TXEQ_DEEMPH_IN;
rxeq_control_reg1 <= EQ_RXEQ_CONTROL;
rxeq_preset_reg1 <= EQ_RXEQ_PRESET;
rxeq_lffs_reg1 <= EQ_RXEQ_LFFS;
rxeq_txpreset_reg1 <= EQ_RXEQ_TXPRESET;
rxeq_user_en_reg1 <= EQ_RXEQ_USER_EN;
rxeq_user_txcoeff_reg1 <= EQ_RXEQ_USER_TXCOEFF;
rxeq_user_mode_reg1 <= EQ_RXEQ_USER_MODE;
//---------- 2nd Stage FF --------------------------
gen3_reg2 <= gen3_reg1;
txeq_control_reg2 <= txeq_control_reg1;
txeq_preset_reg2 <= txeq_preset_reg1;
txeq_deemph_reg2 <= txeq_deemph_reg1;
rxeq_control_reg2 <= rxeq_control_reg1;
rxeq_preset_reg2 <= rxeq_preset_reg1;
rxeq_lffs_reg2 <= rxeq_lffs_reg1;
rxeq_txpreset_reg2 <= rxeq_txpreset_reg1;
rxeq_user_en_reg2 <= rxeq_user_en_reg1;
rxeq_user_txcoeff_reg2 <= rxeq_user_txcoeff_reg1;
rxeq_user_mode_reg2 <= rxeq_user_mode_reg1;
end
end
//---------- TXEQ Preset -------------------------------------------------------
always @ (posedge EQ_CLK)
begin
if (!EQ_RST_N)
begin
//---------- Select TXEQ Preset ----------------
case (EQ_TXEQ_PRESET_DEFAULT)
4'd0 : txeq_preset <= {TXPOSTCURSOR_00, TXMAINCURSOR_00, TXPRECURSOR_00};
4'd1 : txeq_preset <= {TXPOSTCURSOR_01, TXMAINCURSOR_01, TXPRECURSOR_01};
4'd2 : txeq_preset <= {TXPOSTCURSOR_02, TXMAINCURSOR_02, TXPRECURSOR_02};
4'd3 : txeq_preset <= {TXPOSTCURSOR_03, TXMAINCURSOR_03, TXPRECURSOR_03};
4'd4 : txeq_preset <= {TXPOSTCURSOR_04, TXMAINCURSOR_04, TXPRECURSOR_04};
4'd5 : txeq_preset <= {TXPOSTCURSOR_05, TXMAINCURSOR_05, TXPRECURSOR_05};
4'd6 : txeq_preset <= {TXPOSTCURSOR_06, TXMAINCURSOR_06, TXPRECURSOR_06};
4'd7 : txeq_preset <= {TXPOSTCURSOR_07, TXMAINCURSOR_07, TXPRECURSOR_07};
4'd8 : txeq_preset <= {TXPOSTCURSOR_08, TXMAINCURSOR_08, TXPRECURSOR_08};
4'd9 : txeq_preset <= {TXPOSTCURSOR_09, TXMAINCURSOR_09, TXPRECURSOR_09};
4'd10 : txeq_preset <= {TXPOSTCURSOR_10, TXMAINCURSOR_10, TXPRECURSOR_10};
default : txeq_preset <= 19'd4;
endcase
txeq_preset_done <= 1'd0;
end
else
begin
if (fsm_tx == FSM_TXEQ_PRESET)
begin
//---------- Select TXEQ Preset ----------------
case (txeq_preset_reg2)
4'd0 : txeq_preset <= {TXPOSTCURSOR_00, TXMAINCURSOR_00, TXPRECURSOR_00};
4'd1 : txeq_preset <= {TXPOSTCURSOR_01, TXMAINCURSOR_01, TXPRECURSOR_01};
4'd2 : txeq_preset <= {TXPOSTCURSOR_02, TXMAINCURSOR_02, TXPRECURSOR_02};
4'd3 : txeq_preset <= {TXPOSTCURSOR_03, TXMAINCURSOR_03, TXPRECURSOR_03};
4'd4 : txeq_preset <= {TXPOSTCURSOR_04, TXMAINCURSOR_04, TXPRECURSOR_04};
4'd5 : txeq_preset <= {TXPOSTCURSOR_05, TXMAINCURSOR_05, TXPRECURSOR_05};
4'd6 : txeq_preset <= {TXPOSTCURSOR_06, TXMAINCURSOR_06, TXPRECURSOR_06};
4'd7 : txeq_preset <= {TXPOSTCURSOR_07, TXMAINCURSOR_07, TXPRECURSOR_07};
4'd8 : txeq_preset <= {TXPOSTCURSOR_08, TXMAINCURSOR_08, TXPRECURSOR_08};
4'd9 : txeq_preset <= {TXPOSTCURSOR_09, TXMAINCURSOR_09, TXPRECURSOR_09};
4'd10 : txeq_preset <= {TXPOSTCURSOR_10, TXMAINCURSOR_10, TXPRECURSOR_10};
default : txeq_preset <= 19'd4;
endcase
txeq_preset_done <= 1'd1;
end
else
begin
txeq_preset <= txeq_preset;
txeq_preset_done <= 1'd0;
end
end
end
//---------- TXEQ FSM ----------------------------------------------------------
always @ (posedge EQ_CLK)
begin
if (!EQ_RST_N)
begin
fsm_tx <= FSM_TXEQ_IDLE;
txeq_txcoeff <= 19'd0;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
else
begin
case (fsm_tx)
//---------- Idle State ----------------------------
FSM_TXEQ_IDLE :
begin
case (txeq_control_reg2)
//---------- Idle ------------------------------
2'd0 :
begin
fsm_tx <= FSM_TXEQ_IDLE;
txeq_txcoeff <= txeq_txcoeff;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
//---------- Process TXEQ Preset ---------------
2'd1 :
begin
fsm_tx <= FSM_TXEQ_PRESET;
txeq_txcoeff <= txeq_txcoeff;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
//---------- Coefficient -----------------------
2'd2 :
begin
fsm_tx <= FSM_TXEQ_TXCOEFF;
txeq_txcoeff <= {txeq_deemph_reg2, txeq_txcoeff[18:6]};
txeq_txcoeff_cnt <= 2'd1;
txeq_done <= 1'd0;
end
//---------- Query -----------------------------
2'd3 :
begin
fsm_tx <= FSM_TXEQ_QUERY;
txeq_txcoeff <= txeq_txcoeff;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
//---------- Default ---------------------------
default :
begin
fsm_tx <= FSM_TXEQ_IDLE;
txeq_txcoeff <= txeq_txcoeff;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
endcase
end
//---------- Process TXEQ Preset -------------------
FSM_TXEQ_PRESET :
begin
fsm_tx <= (txeq_preset_done ? FSM_TXEQ_DONE : FSM_TXEQ_PRESET);
txeq_txcoeff <= txeq_preset;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
//---------- Latch Link Partner TX Coefficient -----
FSM_TXEQ_TXCOEFF :
begin
fsm_tx <= ((txeq_txcoeff_cnt == 2'd2) ? FSM_TXEQ_REMAP : FSM_TXEQ_TXCOEFF);
//---------- Shift in extra bit for TXMAINCURSOR
if (txeq_txcoeff_cnt == 2'd1)
txeq_txcoeff <= {1'd0, txeq_deemph_reg2, txeq_txcoeff[18:7]};
else
txeq_txcoeff <= {txeq_deemph_reg2, txeq_txcoeff[18:6]};
txeq_txcoeff_cnt <= txeq_txcoeff_cnt + 2'd1;
txeq_done <= 1'd0;
end
//---------- Remap to GT TX Coefficient ------------
FSM_TXEQ_REMAP :
begin
fsm_tx <= FSM_TXEQ_DONE;
txeq_txcoeff <= txeq_txcoeff << 1; // Multiply by 2x
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
//---------- Query TXEQ Coefficient ----------------
FSM_TXEQ_QUERY:
begin
fsm_tx <= FSM_TXEQ_DONE;
txeq_txcoeff <= txeq_txcoeff;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
//---------- Done ----------------------------------
FSM_TXEQ_DONE :
begin
fsm_tx <= ((txeq_control_reg2 == 2'd0) ? FSM_TXEQ_IDLE : FSM_TXEQ_DONE);
txeq_txcoeff <= txeq_txcoeff;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd1;
end
//---------- Default State -------------------------
default :
begin
fsm_tx <= FSM_TXEQ_IDLE;
txeq_txcoeff <= 19'd0;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
endcase
end
end
//---------- RXEQ FSM ----------------------------------------------------------
always @ (posedge EQ_CLK)
begin
if (!EQ_RST_N)
begin
fsm_rx <= FSM_RXEQ_IDLE;
rxeq_preset <= 3'd0;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= 4'd0;
rxeq_txcoeff <= 18'd0;
rxeq_cnt <= 3'd0;
rxeq_fs <= 6'd0;
rxeq_lf <= 6'd0;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= 18'd0;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= 1'd0;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
else
begin
case (fsm_rx)
//---------- Idle State ----------------------------
FSM_RXEQ_IDLE :
begin
case (rxeq_control_reg2)
//---------- Process RXEQ Preset ---------------
2'd1 :
begin
fsm_rx <= FSM_RXEQ_PRESET;
rxeq_preset <= rxeq_preset_reg2;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset;
rxeq_txcoeff <= rxeq_txcoeff;
rxeq_cnt <= 3'd0;
rxeq_fs <= rxeq_fs;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= 1'd0;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
//---------- Request New TX Coefficient --------
2'd2 :
begin
fsm_rx <= FSM_RXEQ_TXCOEFF;
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset_reg2;
rxeq_txcoeff <= {txeq_deemph_reg2, rxeq_txcoeff[17:6]};
rxeq_cnt <= 3'd1;
rxeq_fs <= rxeq_lffs_reg2;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
//---------- Phase2/3 Bypass (reuse logic from rxeq_control = 2 ----
2'd3 :
begin
fsm_rx <= FSM_RXEQ_TXCOEFF;
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset_reg2;
rxeq_txcoeff <= {txeq_deemph_reg2, rxeq_txcoeff[17:6]};
rxeq_cnt <= 3'd1;
rxeq_fs <= rxeq_lffs_reg2;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
//---------- Default ---------------------------
default :
begin
fsm_rx <= FSM_RXEQ_IDLE;
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset;
rxeq_txcoeff <= rxeq_txcoeff;
rxeq_cnt <= 3'd0;
rxeq_fs <= rxeq_fs;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
endcase
end
//---------- Process RXEQ Preset -------------------
FSM_RXEQ_PRESET :
begin
fsm_rx <= (rxeqscan_preset_done ? FSM_RXEQ_DONE : FSM_RXEQ_PRESET);
rxeq_preset <= rxeq_preset_reg2;
rxeq_preset_valid <= 1'd1;
rxeq_txpreset <= rxeq_txpreset;
rxeq_txcoeff <= rxeq_txcoeff;
rxeq_cnt <= 3'd0;
rxeq_fs <= rxeq_fs;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
//---------- Shift-in Link Partner TX Coefficient and Preset
FSM_RXEQ_TXCOEFF :
begin
fsm_rx <= ((rxeq_cnt == 3'd2) ? FSM_RXEQ_LF : FSM_RXEQ_TXCOEFF);
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset_reg2;
rxeq_txcoeff <= {txeq_deemph_reg2, rxeq_txcoeff[17:6]};
rxeq_cnt <= rxeq_cnt + 2'd1;
rxeq_fs <= rxeq_fs;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd1;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
//---------- Read Low Frequency (LF) Value ---------
FSM_RXEQ_LF :
begin
fsm_rx <= ((rxeq_cnt == 3'd7) ? FSM_RXEQ_NEW_TXCOEFF_REQ : FSM_RXEQ_LF);
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset;
rxeq_txcoeff <= rxeq_txcoeff;
rxeq_cnt <= rxeq_cnt + 2'd1;
rxeq_fs <= rxeq_fs;
rxeq_lf <= ((rxeq_cnt == 3'd7) ? rxeq_lffs_reg2 : rxeq_lf);
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd1;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
//---------- Request New TX Coefficient ------------
FSM_RXEQ_NEW_TXCOEFF_REQ :
begin
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset;
rxeq_txcoeff <= rxeq_txcoeff;
rxeq_cnt <= 3'd0;
rxeq_fs <= rxeq_fs;
rxeq_lf <= rxeq_lf;
if (rxeqscan_new_txcoeff_done)
begin
fsm_rx <= FSM_RXEQ_DONE;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeqscan_lffs_sel ? {14'd0, rxeqscan_new_txcoeff[3:0]} : rxeqscan_new_txcoeff;
rxeq_lffs_sel <= rxeqscan_lffs_sel;
rxeq_adapt_done_reg <= rxeqscan_adapt_done || rxeq_adapt_done_reg;
rxeq_adapt_done <= rxeqscan_adapt_done || rxeq_adapt_done_reg;
rxeq_done <= 1'd1;
end
else
begin
fsm_rx <= FSM_RXEQ_NEW_TXCOEFF_REQ;
rxeq_new_txcoeff_req <= 1'd1;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
end
//---------- RXEQ Done -----------------------------
FSM_RXEQ_DONE :
begin
fsm_rx <= ((rxeq_control_reg2 == 2'd0) ? FSM_RXEQ_IDLE : FSM_RXEQ_DONE);
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset;
rxeq_txcoeff <= rxeq_txcoeff;
rxeq_cnt <= 3'd0;
rxeq_fs <= rxeq_fs;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= rxeq_lffs_sel;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= rxeq_adapt_done;
rxeq_done <= 1'd1;
end
//---------- Default State -------------------------
default :
begin
fsm_rx <= FSM_RXEQ_IDLE;
rxeq_preset <= 3'd0;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= 4'd0;
rxeq_txcoeff <= 18'd0;
rxeq_cnt <= 3'd0;
rxeq_fs <= 6'd0;
rxeq_lf <= 6'd0;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= 18'd0;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= 1'd0;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
endcase
end
end
//---------- RXEQ Eye Scan Module ----------------------------------------------
PCIeGen2x8If128_rxeq_scan #
(
.PCIE_SIM_MODE (PCIE_SIM_MODE),
.PCIE_GT_DEVICE (PCIE_GT_DEVICE),
.PCIE_RXEQ_MODE_GEN3 (PCIE_RXEQ_MODE_GEN3)
)
rxeq_scan_i
(
//---------- Input -------------------------------------
.RXEQSCAN_CLK (EQ_CLK),
.RXEQSCAN_RST_N (EQ_RST_N),
.RXEQSCAN_CONTROL (rxeq_control_reg2),
.RXEQSCAN_FS (rxeq_fs),
.RXEQSCAN_LF (rxeq_lf),
.RXEQSCAN_PRESET (rxeq_preset),
.RXEQSCAN_PRESET_VALID (rxeq_preset_valid),
.RXEQSCAN_TXPRESET (rxeq_txpreset),
.RXEQSCAN_TXCOEFF (rxeq_txcoeff),
.RXEQSCAN_NEW_TXCOEFF_REQ (rxeq_new_txcoeff_req),
//---------- Output ------------------------------------
.RXEQSCAN_PRESET_DONE (rxeqscan_preset_done),
.RXEQSCAN_NEW_TXCOEFF (rxeqscan_new_txcoeff),
.RXEQSCAN_NEW_TXCOEFF_DONE (rxeqscan_new_txcoeff_done),
.RXEQSCAN_LFFS_SEL (rxeqscan_lffs_sel),
.RXEQSCAN_ADAPT_DONE (rxeqscan_adapt_done)
);
//---------- PIPE EQ Output ----------------------------------------------------
assign EQ_TXEQ_DEEMPH = txeq_txcoeff[0];
assign EQ_TXEQ_PRECURSOR = gen3_reg2 ? txeq_txcoeff[ 4: 0] : 5'h00;
assign EQ_TXEQ_MAINCURSOR = gen3_reg2 ? txeq_txcoeff[12: 6] : 7'h00;
assign EQ_TXEQ_POSTCURSOR = gen3_reg2 ? txeq_txcoeff[17:13] : 5'h00;
assign EQ_TXEQ_DEEMPH_OUT = {1'd0, txeq_txcoeff[18:14], txeq_txcoeff[12:7], 1'd0, txeq_txcoeff[5:1]}; // Divide by 2x
assign EQ_TXEQ_DONE = txeq_done;
assign EQ_TXEQ_FSM = fsm_tx;
assign EQ_RXEQ_NEW_TXCOEFF = rxeq_user_en_reg2 ? rxeq_user_txcoeff_reg2 : rxeq_new_txcoeff;
assign EQ_RXEQ_LFFS_SEL = rxeq_user_en_reg2 ? rxeq_user_mode_reg2 : rxeq_lffs_sel;
assign EQ_RXEQ_ADAPT_DONE = rxeq_adapt_done;
assign EQ_RXEQ_DONE = rxeq_done;
assign EQ_RXEQ_FSM = fsm_rx;
endmodule
|
// ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014
//
// top module for video output.
/*
This file is part of ZX-Evo Base Configuration firmware.
ZX-Evo Base Configuration firmware is free software:
you can redistribute it and/or modify it under the terms of
the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
ZX-Evo Base Configuration firmware is distributed in the hope that
it will be useful, but WITHOUT ANY WARRANTY; without even
the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with ZX-Evo Base Configuration firmware.
If not, see <http://www.gnu.org/licenses/>.
*/
// note: the only bandwidths currently in use are 1/8 and 1/4.
`include "../include/tune.v"
module video_top(
input wire clk, // 28 MHz clock
// external video outputs
output wire [ 1:0] vred,
output wire [ 1:0] vgrn,
output wire [ 1:0] vblu,
output wire vhsync,
output wire vvsync,
output wire vcsync,
// aux video inputs
input wire [ 3:0] zxborder, // border zxcolor
// config inputs
input wire [ 1:0] pent_vmode, // 2'b00 - standard ZX
// 2'b01 - hardware multicolor
// 2'b10 - pentagon 16 colors
// 2'b11 - not defined yet
input wire [ 2:0] atm_vmode, // 3'b011 - zx modes (pent_vmode is active)
// 3'b010 - 640x200 hardware multicolor
// 3'b000 - 320x200 16 colors
// 3'b110 - 80x25 text mode
// 3'b??? (others) - not defined yet
input wire scr_page, // screen page (bit 3 of 7FFD)
input wire vga_on, // vga mode ON - scandoubler activated
input wire [ 1:0] modes_raster, // 2'b00 - pentagon raster (71680 clocks)
// 2'b01 - 60Hz raster
// 2'b10 - 48k raster (69888 clocks)
// 2'b11 - 128k raster (70908 clocks)
input wire mode_contend_type, // 2'b0 - 48k/128k/+2 contend type (6 5 4 3 2 1 0 0)
// 2'b1 - +2a/+3 contend type (1 0 7 6 5 4 3 2)
// memory synchronization inputs
input wire cbeg,
input wire post_cbeg,
input wire pre_cend,
input wire cend,
// memory arbiter video port connection
input wire video_strobe,
input wire video_next,
output wire [20:0] video_addr,
input wire [15:0] video_data,
output wire [ 1:0] video_bw,
output wire video_go,
// atm palette write strobe adn data
input wire atm_palwr,
input wire [ 5:0] atm_paldata,
input wire up_ena,
input wire up_palwr,
input wire [ 5:0] up_paladdr,
input wire [ 7:0] up_paldata,
output wire int_start,
input wire [10:0] fnt_a,
input wire [ 7:0] fnt_d,
input wire fnt_wr,
output wire [ 5:0] palcolor, // for palette readback
output wire [ 7:0] fontrom_readback,
output wire contend // for 48k/128k contended memory emulation
);
// these decoded in video_modedecode.v
wire mode_atm_n_pent;
wire mode_zx;
wire mode_p_16c;
wire mode_p_hmclr;
wire mode_a_hmclr;
wire mode_a_16c;
wire mode_a_text;
wire mode_a_txt_1page;
wire mode_pixf_14;
// synchronization
wire hsync_start;
wire line_start;
wire hint_start;
wire vblank;
wire hblank;
wire vpix;
wire hpix;
wire vsync;
wire hsync;
wire vga_hsync;
wire scanin_start;
wire scanout_start;
wire fetch_start;
wire fetch_end;
wire fetch_sync;
wire [63:0] pic_bits;
wire [3:0] pixels;
wire [5:0] color;
wire [5:0] vga_color;
wire [2:0] typos;
// ulaplus related
wire [ 1:0] up_palsel;
wire [ 2:0] up_paper;
wire [ 2:0] up_ink;
wire up_pixel;
// border sync for 48k/128k emulation
wire border_sync;
// decode video modes
video_modedecode video_modedecode(
.clk(clk),
.pent_vmode(pent_vmode),
.atm_vmode (atm_vmode),
.mode_atm_n_pent (mode_atm_n_pent ),
.mode_zx (mode_zx ),
.mode_p_16c (mode_p_16c ),
.mode_p_hmclr (mode_p_hmclr ),
.mode_a_hmclr (mode_a_hmclr ),
.mode_a_16c (mode_a_16c ),
.mode_a_text (mode_a_text ),
.mode_a_txt_1page(mode_a_txt_1page),
.mode_pixf_14(mode_pixf_14),
.mode_bw(video_bw)
);
// vertical sync generator
video_sync_v video_sync_v(
.clk(clk),
.mode_atm_n_pent(mode_atm_n_pent),
.modes_raster(modes_raster),
.hsync_start(hsync_start),
.line_start(line_start),
.hint_start(hint_start),
.vblank(vblank),
.vsync(vsync),
.vpix(vpix),
.int_start(int_start)
);
// horizontal sync generator
video_sync_h video_sync_h(
.clk(clk),
.mode_atm_n_pent(mode_atm_n_pent),
.mode_a_text (mode_a_text),
.modes_raster (modes_raster ),
.mode_contend_type(mode_contend_type),
.init(1'b0),
.pre_cend(pre_cend),
.cend (cend ),
.hblank(hblank),
.hsync(hsync),
.vpix(vpix),
.hpix(hpix),
.line_start(line_start),
.hsync_start(hsync_start),
.hint_start(hint_start),
.scanin_start(scanin_start),
.fetch_start(fetch_start),
.fetch_end (fetch_end ),
.contend(contend),
.border_sync(border_sync)
);
// address generation
video_addrgen video_addrgen(
.clk(clk),
.video_addr(video_addr),
.video_next(video_next),
.line_start(hsync_start),
.int_start (int_start ),
.vpix (vpix ),
.scr_page(scr_page),
.typos(typos),
.mode_atm_n_pent (mode_atm_n_pent ),
.mode_zx (mode_zx ),
.mode_p_16c (mode_p_16c ),
.mode_p_hmclr (mode_p_hmclr ),
.mode_a_hmclr (mode_a_hmclr ),
.mode_a_16c (mode_a_16c ),
.mode_a_text (mode_a_text ),
.mode_a_txt_1page(mode_a_txt_1page)
);
// data fetch
video_fetch video_fetch(
.clk(clk),
.pre_cend (pre_cend),
.cend (cend ),
.vpix(vpix),
.fetch_start(fetch_start),
.fetch_end (fetch_end ),
.fetch_sync (fetch_sync ),
.video_data (video_data ),
.video_strobe(video_strobe),
.video_go (video_go ),
.pic_bits(pic_bits)
);
// render fetched data to pixels
video_render video_render(
.clk(clk),
.pic_bits(pic_bits),
.fetch_sync(fetch_sync),
.cbeg (cbeg ),
.post_cbeg(post_cbeg),
.pre_cend (pre_cend ),
.cend (cend ),
.int_start(int_start),
.mode_atm_n_pent(mode_atm_n_pent),
.mode_zx (mode_zx ),
.mode_p_16c (mode_p_16c ),
.mode_p_hmclr (mode_p_hmclr ),
.mode_a_hmclr (mode_a_hmclr ),
.mode_a_16c (mode_a_16c ),
.mode_a_text (mode_a_text ),
.mode_pixf_14 (mode_pixf_14 ),
.typos(typos),
.pixels(pixels),
.up_palsel(up_palsel),
.up_paper (up_paper ),
.up_ink (up_ink ),
.up_pixel (up_pixel ),
.fnt_a (fnt_a ),
.fnt_d (fnt_d ),
.fnt_wr(fnt_wr),
.fontrom_readback(fontrom_readback)
);
// combine border and pixels, apply palette
video_palframe video_palframe(
.clk(clk),
.hblank(hblank),
.vblank(vblank),
.hsync_start(hsync_start),
.vsync (vsync ),
.hpix(hpix),
.vpix(vpix),
.pixels(pixels),
.border(zxborder),
.border_sync (border_sync ),
.border_sync_ena(modes_raster[1]),
.atm_palwr (atm_palwr ),
.atm_paldata(atm_paldata),
.up_palsel(up_palsel),
.up_paper (up_paper ),
.up_ink (up_ink ),
.up_pixel (up_pixel ),
.up_ena (up_ena ),
.up_paladdr(up_paladdr),
.up_paldata(up_paldata),
.up_palwr (up_palwr ),
.color(color),
.palcolor(palcolor) // palette readback
);
// VGA hsync doubling
video_vga_sync_h video_vga_sync_h(
.clk(clk),
.hsync_start(hsync_start),
.modes_raster(modes_raster),
.scanout_start(scanout_start),
.vga_hsync(vga_hsync)
);
// VGA scandoubling
video_vga_double video_vga_double(
.clk(clk),
.hsync_start (hsync_start ),
.scanout_start(scanout_start),
.scanin_start (scanin_start ),
.pix_in(color),
.pix_out(vga_color)
);
// final MUXing of VGA and TV signals
video_outmux video_outmux(
.clk(clk),
.vga_on(vga_on),
.tvcolor(color),
.vgacolor(vga_color),
.vga_hsync(vga_hsync),
.hsync (hsync ),
.vsync (vsync ),
.vred(vred),
.vgrn(vgrn),
.vblu(vblu),
.vhsync(vhsync),
.vvsync(vvsync),
.vcsync(vcsync)
);
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate constant multiplication in array define.
//
//
module main ();
reg [5 * 2: 0] val1;
reg [10'h1 * 10: 0 ] val2 ;
initial
begin
val1 = 11'h1 * 5;
val2 = 11'h2 * 4;
if((val1 === 11'h5) && (val2 === 11'h8))
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
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//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : arb_row_col.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// This block receives request to send row and column commands. These requests
// come the individual bank machines. The arbitration winner is selected
// and driven back to the bank machines.
//
// The CS enables are generated. For 2:1 mode, row commands are sent
// in the "0" phase, and column commands are sent in the "1" phase.
//
// In 2T mode, a further arbitration is performed between the row
// and column commands. The winner of this arbitration inhibits
// arbitration by the loser. The winner is allowed to arbitrate, the loser is
// blocked until the next state. The winning address command
// is repeated on both the "0" and the "1" phases and the CS
// is asserted for just the "1" phase.
`timescale 1 ps / 1 ps
module mig_7series_v2_3_arb_row_col #
(
parameter TCQ = 100,
parameter ADDR_CMD_MODE = "1T",
parameter CWL = 5,
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nRAS = 37500, // ACT->PRE cmd period (CKs)
parameter nRCD = 12500, // ACT->R/W delay (CKs)
parameter nWR = 6 // Write recovery (CKs)
)
(/*AUTOARG*/
// Outputs
grant_row_r, grant_pre_r, sent_row, sending_row, sending_pre, grant_config_r,
rnk_config_strobe, rnk_config_valid_r, grant_col_r,
sending_col, sent_col, sent_col_r, grant_col_wr, send_cmd0_row, send_cmd0_col,
send_cmd1_row, send_cmd1_col, send_cmd2_row, send_cmd2_col, send_cmd2_pre,
send_cmd3_col, col_channel_offset, cs_en0, cs_en1, cs_en2, cs_en3,
insert_maint_r1, rnk_config_kill_rts_col,
// Inputs
clk, rst, rts_row, rts_pre, insert_maint_r, rts_col, rtc, col_rdy_wr
);
// Create a delay when switching ranks
localparam RNK2RNK_DLY = 12;
localparam RNK2RNK_DLY_CLKS =
(RNK2RNK_DLY / nCK_PER_CLK) + (RNK2RNK_DLY % nCK_PER_CLK ? 1 : 0);
input clk;
input rst;
input [nBANK_MACHS-1:0] rts_row;
input insert_maint_r;
input [nBANK_MACHS-1:0] rts_col;
reg [RNK2RNK_DLY_CLKS-1:0] rnk_config_strobe_r;
wire block_grant_row;
wire block_grant_col;
wire rnk_config_kill_rts_col_lcl =
RNK2RNK_DLY_CLKS > 0 ? |rnk_config_strobe_r : 1'b0;
output rnk_config_kill_rts_col;
assign rnk_config_kill_rts_col = rnk_config_kill_rts_col_lcl;
wire [nBANK_MACHS-1:0] col_request;
wire granted_col_ns = |col_request;
wire [nBANK_MACHS-1:0] row_request =
rts_row & {nBANK_MACHS{~insert_maint_r}};
wire granted_row_ns = |row_request;
generate
if (ADDR_CMD_MODE == "2T" && nCK_PER_CLK != 4) begin : row_col_2T_arb
assign col_request =
rts_col & {nBANK_MACHS{~(rnk_config_kill_rts_col_lcl || insert_maint_r)}};
// Give column command priority whenever previous state has no row request.
wire [1:0] row_col_grant;
wire [1:0] current_master = ~granted_row_ns ? 2'b10 : row_col_grant;
wire upd_last_master = ~granted_row_ns || |row_col_grant;
mig_7series_v2_3_round_robin_arb #
(.WIDTH (2))
row_col_arb0
(.grant_ns (),
.grant_r (row_col_grant),
.upd_last_master (upd_last_master),
.current_master (current_master),
.clk (clk),
.rst (rst),
.req ({granted_row_ns, granted_col_ns}),
.disable_grant (1'b0));
assign {block_grant_col, block_grant_row} = row_col_grant;
end
else begin : row_col_1T_arb
assign col_request = rts_col & {nBANK_MACHS{~rnk_config_kill_rts_col_lcl}};
assign block_grant_row = 1'b0;
assign block_grant_col = 1'b0;
end
endgenerate
// Row address/command arbitration.
wire[nBANK_MACHS-1:0] grant_row_r_lcl;
output wire[nBANK_MACHS-1:0] grant_row_r;
assign grant_row_r = grant_row_r_lcl;
reg granted_row_r;
always @(posedge clk) granted_row_r <= #TCQ granted_row_ns;
wire sent_row_lcl = granted_row_r && ~block_grant_row;
output wire sent_row;
assign sent_row = sent_row_lcl;
mig_7series_v2_3_round_robin_arb #
(.WIDTH (nBANK_MACHS))
row_arb0
(.grant_ns (),
.grant_r (grant_row_r_lcl[nBANK_MACHS-1:0]),
.upd_last_master (sent_row_lcl),
.current_master (grant_row_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (row_request),
.disable_grant (1'b0));
output wire [nBANK_MACHS-1:0] sending_row;
assign sending_row = grant_row_r_lcl & {nBANK_MACHS{~block_grant_row}};
// Precharge arbitration for 4:1 mode
input [nBANK_MACHS-1:0] rts_pre;
output wire[nBANK_MACHS-1:0] grant_pre_r;
output wire [nBANK_MACHS-1:0] sending_pre;
wire sent_pre_lcl;
generate
if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T")) begin : pre_4_1_1T_arb
reg granted_pre_r;
wire[nBANK_MACHS-1:0] grant_pre_r_lcl;
wire granted_pre_ns = |rts_pre;
assign grant_pre_r = grant_pre_r_lcl;
always @(posedge clk) granted_pre_r <= #TCQ granted_pre_ns;
assign sent_pre_lcl = granted_pre_r;
assign sending_pre = grant_pre_r_lcl;
mig_7series_v2_3_round_robin_arb #
(.WIDTH (nBANK_MACHS))
pre_arb0
(.grant_ns (),
.grant_r (grant_pre_r_lcl[nBANK_MACHS-1:0]),
.upd_last_master (sent_pre_lcl),
.current_master (grant_pre_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (rts_pre),
.disable_grant (1'b0));
end
endgenerate
`ifdef MC_SVA
all_bank_machines_row_arb:
cover property (@(posedge clk) (~rst && &rts_row));
`endif
// Rank config arbitration.
input [nBANK_MACHS-1:0] rtc;
wire [nBANK_MACHS-1:0] grant_config_r_lcl;
output wire [nBANK_MACHS-1:0] grant_config_r;
assign grant_config_r = grant_config_r_lcl;
wire upd_rnk_config_last_master;
mig_7series_v2_3_round_robin_arb #
(.WIDTH (nBANK_MACHS))
config_arb0
(.grant_ns (),
.grant_r (grant_config_r_lcl[nBANK_MACHS-1:0]),
.upd_last_master (upd_rnk_config_last_master),
.current_master (grant_config_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (rtc[nBANK_MACHS-1:0]),
.disable_grant (1'b0));
`ifdef MC_SVA
all_bank_machines_config_arb: cover property (@(posedge clk) (~rst && &rtc));
`endif
wire rnk_config_strobe_ns = ~rnk_config_strobe_r[0] && |rtc && ~granted_col_ns;
always @(posedge clk) rnk_config_strobe_r[0] <= #TCQ rnk_config_strobe_ns;
genvar i;
generate
for(i = 1; i < RNK2RNK_DLY_CLKS; i = i + 1)
always @(posedge clk)
rnk_config_strobe_r[i] <= #TCQ rnk_config_strobe_r[i-1];
endgenerate
output wire rnk_config_strobe;
assign rnk_config_strobe = rnk_config_strobe_r[0];
assign upd_rnk_config_last_master = rnk_config_strobe_r[0];
// Generate rnk_config_valid.
reg rnk_config_valid_r_lcl;
wire rnk_config_valid_ns;
assign rnk_config_valid_ns =
~rst && (rnk_config_valid_r_lcl || rnk_config_strobe_ns);
always @(posedge clk) rnk_config_valid_r_lcl <= #TCQ rnk_config_valid_ns;
output wire rnk_config_valid_r;
assign rnk_config_valid_r = rnk_config_valid_r_lcl;
// Column address/command arbitration.
wire [nBANK_MACHS-1:0] grant_col_r_lcl;
output wire [nBANK_MACHS-1:0] grant_col_r;
assign grant_col_r = grant_col_r_lcl;
reg granted_col_r;
always @(posedge clk) granted_col_r <= #TCQ granted_col_ns;
wire sent_col_lcl;
mig_7series_v2_3_round_robin_arb #
(.WIDTH (nBANK_MACHS))
col_arb0
(.grant_ns (),
.grant_r (grant_col_r_lcl[nBANK_MACHS-1:0]),
.upd_last_master (sent_col_lcl),
.current_master (grant_col_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (col_request),
.disable_grant (1'b0));
`ifdef MC_SVA
all_bank_machines_col_arb:
cover property (@(posedge clk) (~rst && &rts_col));
`endif
output wire [nBANK_MACHS-1:0] sending_col;
assign sending_col = grant_col_r_lcl & {nBANK_MACHS{~block_grant_col}};
assign sent_col_lcl = granted_col_r && ~block_grant_col;
reg sent_col_lcl_r = 1'b0;
always @(posedge clk) sent_col_lcl_r <= #TCQ sent_col_lcl;
output wire sent_col;
assign sent_col = sent_col_lcl;
output wire sent_col_r;
assign sent_col_r = sent_col_lcl_r;
// If we need early wr_data_addr because ECC is on, arbitrate
// to see which bank machine might sent the next wr_data_addr;
input [nBANK_MACHS-1:0] col_rdy_wr;
output wire [nBANK_MACHS-1:0] grant_col_wr;
generate
if (EARLY_WR_DATA_ADDR == "OFF") begin : early_wr_addr_arb_off
assign grant_col_wr = {nBANK_MACHS{1'b0}};
end
else begin : early_wr_addr_arb_on
wire [nBANK_MACHS-1:0] grant_col_wr_raw;
mig_7series_v2_3_round_robin_arb #
(.WIDTH (nBANK_MACHS))
col_arb0
(.grant_ns (grant_col_wr_raw),
.grant_r (),
.upd_last_master (sent_col_lcl),
.current_master (grant_col_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (col_rdy_wr),
.disable_grant (1'b0));
reg [nBANK_MACHS-1:0] grant_col_wr_r;
wire [nBANK_MACHS-1:0] grant_col_wr_ns = granted_col_ns
? grant_col_wr_raw
: grant_col_wr_r;
always @(posedge clk) grant_col_wr_r <= #TCQ grant_col_wr_ns;
assign grant_col_wr = grant_col_wr_ns;
end // block: early_wr_addr_arb_on
endgenerate
output reg send_cmd0_row = 1'b0;
output reg send_cmd0_col = 1'b0;
output reg send_cmd1_row = 1'b0;
output reg send_cmd1_col = 1'b0;
output reg send_cmd2_row = 1'b0;
output reg send_cmd2_col = 1'b0;
output reg send_cmd2_pre = 1'b0;
output reg send_cmd3_col = 1'b0;
output reg cs_en0 = 1'b0;
output reg cs_en1 = 1'b0;
output reg cs_en2 = 1'b0;
output reg cs_en3 = 1'b0;
output wire [5:0] col_channel_offset;
reg insert_maint_r1_lcl;
always @(posedge clk) insert_maint_r1_lcl <= #TCQ insert_maint_r;
output wire insert_maint_r1;
assign insert_maint_r1 = insert_maint_r1_lcl;
wire sent_row_or_maint = sent_row_lcl || insert_maint_r1_lcl;
reg sent_row_or_maint_r = 1'b0;
always @(posedge clk) sent_row_or_maint_r <= #TCQ sent_row_or_maint;
generate
case ({(nCK_PER_CLK == 4), (nCK_PER_CLK == 2), (ADDR_CMD_MODE == "2T")})
3'b000 : begin : one_one_not2T
end
3'b001 : begin : one_one_2T
end
3'b010 : begin : two_one_not2T
if(!(CWL % 2)) begin // Place column commands on slot 0 for even CWL
always @(sent_col_lcl) begin
cs_en0 = sent_col_lcl;
send_cmd0_col = sent_col_lcl;
end
always @(sent_row_or_maint) begin
cs_en1 = sent_row_or_maint;
send_cmd1_row = sent_row_or_maint;
end
assign col_channel_offset = 0;
end
else begin // Place column commands on slot 1 for odd CWL
always @(sent_row_or_maint) begin
cs_en0 = sent_row_or_maint;
send_cmd0_row = sent_row_or_maint;
end
always @(sent_col_lcl) begin
cs_en1 = sent_col_lcl;
send_cmd1_col = sent_col_lcl;
end
assign col_channel_offset = 1;
end
end
3'b011 : begin : two_one_2T
if(!(CWL % 2)) begin // Place column commands on slot 1->0 for even CWL
always @(sent_row_or_maint_r or sent_col_lcl_r)
cs_en0 = sent_row_or_maint_r || sent_col_lcl_r;
always @(sent_row_or_maint or sent_row_or_maint_r) begin
send_cmd0_row = sent_row_or_maint_r;
send_cmd1_row = sent_row_or_maint;
end
always @(sent_col_lcl or sent_col_lcl_r) begin
send_cmd0_col = sent_col_lcl_r;
send_cmd1_col = sent_col_lcl;
end
assign col_channel_offset = 0;
end
else begin // Place column commands on slot 0->1 for odd CWL
always @(sent_col_lcl or sent_row_or_maint)
cs_en1 = sent_row_or_maint || sent_col_lcl;
always @(sent_row_or_maint) begin
send_cmd0_row = sent_row_or_maint;
send_cmd1_row = sent_row_or_maint;
end
always @(sent_col_lcl) begin
send_cmd0_col = sent_col_lcl;
send_cmd1_col = sent_col_lcl;
end
assign col_channel_offset = 1;
end
end
3'b100 : begin : four_one_not2T
if(!(CWL % 2)) begin // Place column commands on slot 0 for even CWL
always @(sent_col_lcl) begin
cs_en0 = sent_col_lcl;
send_cmd0_col = sent_col_lcl;
end
always @(sent_row_or_maint) begin
cs_en1 = sent_row_or_maint;
send_cmd1_row = sent_row_or_maint;
end
assign col_channel_offset = 0;
end
else begin // Place column commands on slot 1 for odd CWL
always @(sent_row_or_maint) begin
cs_en0 = sent_row_or_maint;
send_cmd0_row = sent_row_or_maint;
end
always @(sent_col_lcl) begin
cs_en1 = sent_col_lcl;
send_cmd1_col = sent_col_lcl;
end
assign col_channel_offset = 1;
end
always @(sent_pre_lcl) begin
cs_en2 = sent_pre_lcl;
send_cmd2_pre = sent_pre_lcl;
end
end
3'b101 : begin : four_one_2T
if(!(CWL % 2)) begin // Place column commands on slot 3->0 for even CWL
always @(sent_col_lcl or sent_col_lcl_r) begin
cs_en0 = sent_col_lcl_r;
send_cmd0_col = sent_col_lcl_r;
send_cmd3_col = sent_col_lcl;
end
always @(sent_row_or_maint) begin
cs_en2 = sent_row_or_maint;
send_cmd1_row = sent_row_or_maint;
send_cmd2_row = sent_row_or_maint;
end
assign col_channel_offset = 0;
end
else begin // Place column commands on slot 2->3 for odd CWL
always @(sent_row_or_maint) begin
cs_en1 = sent_row_or_maint;
send_cmd0_row = sent_row_or_maint;
send_cmd1_row = sent_row_or_maint;
end
always @(sent_col_lcl) begin
cs_en3 = sent_col_lcl;
send_cmd2_col = sent_col_lcl;
send_cmd3_col = sent_col_lcl;
end
assign col_channel_offset = 3;
end
end
endcase
endgenerate
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: fifo_packer_32.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Packs 32 bit received data into a 32 bit wide FIFO.
// Assumes the FIFO always has room to accommodate the data.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
// Additional Comments:
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module fifo_packer_32 (
input CLK,
input RST,
input [31:0] DATA_IN, // Incoming data
input DATA_IN_EN, // Incoming data enable
input DATA_IN_DONE, // Incoming data packet end
input DATA_IN_ERR, // Incoming data error
input DATA_IN_FLUSH, // End of incoming data
output [31:0] PACKED_DATA, // Outgoing data
output PACKED_WEN, // Outgoing data write enable
output PACKED_DATA_DONE, // End of outgoing data packet
output PACKED_DATA_ERR, // Error in outgoing data
output PACKED_DATA_FLUSHED // End of outgoing data
);
reg rPackedDone=0, _rPackedDone=0;
reg rPackedErr=0, _rPackedErr=0;
reg rPackedFlush=0, _rPackedFlush=0;
reg rPackedFlushed=0, _rPackedFlushed=0;
reg [31:0] rDataIn=64'd0, _rDataIn=64'd0;
reg rDataInEn=0, _rDataInEn=0;
assign PACKED_DATA = rDataIn;
assign PACKED_WEN = rDataInEn;
assign PACKED_DATA_DONE = rPackedDone;
assign PACKED_DATA_ERR = rPackedErr;
assign PACKED_DATA_FLUSHED = rPackedFlushed;
// Buffers input data to ease timing.
always @ (posedge CLK) begin
rPackedDone <= #1 (RST ? 1'd0 : _rPackedDone);
rPackedErr <= #1 (RST ? 1'd0 : _rPackedErr);
rPackedFlush <= #1 (RST ? 1'd0 : _rPackedFlush);
rPackedFlushed <= #1 (RST ? 1'd0 : _rPackedFlushed);
rDataIn <= #1 _rDataIn;
rDataInEn <= #1 (RST ? 1'd0 : _rDataInEn);
end
always @ (*) begin
// Buffer and mask the input data.
_rDataIn = DATA_IN;
_rDataInEn = DATA_IN_EN;
// Track done/error/flush signals.
_rPackedDone = DATA_IN_DONE;
_rPackedErr = DATA_IN_ERR;
_rPackedFlush = DATA_IN_FLUSH;
_rPackedFlushed = rPackedFlush;
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_monitor_32.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Detects transaction open/close events from the stream
// of data from the tx_port_channel_gate. Filters out events and passes data
// onto the tx_port_buffer.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_TXPORTMON32_NEXT 6'b00_0001
`define S_TXPORTMON32_EVT_2 6'b00_0010
`define S_TXPORTMON32_TXN 6'b00_0100
`define S_TXPORTMON32_READ 6'b00_1000
`define S_TXPORTMON32_END_0 6'b01_0000
`define S_TXPORTMON32_END_1 6'b10_0000
`timescale 1ns/1ns
module tx_port_monitor_32 #(
parameter C_DATA_WIDTH = 9'd32,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_THRESH = (C_FIFO_DEPTH - 4),
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),
parameter C_VALID_HIST = 1
)
(
input RST,
input CLK,
input [C_DATA_WIDTH:0] EVT_DATA, // Event data from tx_port_channel_gate
input EVT_DATA_EMPTY, // Event data FIFO is empty
output EVT_DATA_RD_EN, // Event data FIFO read enable
output [C_DATA_WIDTH-1:0] WR_DATA, // Output data
output WR_EN, // Write enable for output data
input [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT, // Output FIFO count
output TXN, // Transaction parameters are valid
input ACK, // Transaction parameter read, continue
output LAST, // Channel last write
output [31:0] LEN, // Channel write length (in 32 bit words)
output [30:0] OFF, // Channel write offset
output [31:0] WORDS_RECVD, // Count of data words received in transaction
output DONE, // Transaction is closed
input TX_ERR // Transaction encountered an error
);
`include "functions.vh"
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [5:0] rState=`S_TXPORTMON32_NEXT, _rState=`S_TXPORTMON32_NEXT;
reg rRead=0, _rRead=0;
reg [C_VALID_HIST-1:0] rDataValid={C_VALID_HIST{1'd0}}, _rDataValid={C_VALID_HIST{1'd0}};
reg rEvent=0, _rEvent=0;
reg [31:0] rReadOffLast=0, _rReadOffLast=0;
reg [31:0] rReadLen=0, _rReadLen=0;
reg rReadCount=0, _rReadCount=0;
reg [31:0] rWordsRecvd=0, _rWordsRecvd=0;
reg [31:0] rWordsRecvdAdv=0, _rWordsRecvdAdv=0;
reg rAlmostAllRecvd=0, _rAlmostAllRecvd=0;
reg rAlmostFull=0, _rAlmostFull=0;
reg rLenEQ0Hi=0, _rLenEQ0Hi=0;
reg rLenEQ0Lo=0, _rLenEQ0Lo=0;
reg rLenLE1Lo=0, _rLenLE1Lo=0;
reg rTxErr=0, _rTxErr=0;
wire wEventData = (rDataValid[0] & EVT_DATA[C_DATA_WIDTH]);
wire wPayloadData = (rDataValid[0] & !EVT_DATA[C_DATA_WIDTH] & rState[3]); // S_TXPORTMON32_READ
wire wAllWordsRecvd = ((rAlmostAllRecvd | (rLenEQ0Hi & rLenLE1Lo)) & wPayloadData);
assign EVT_DATA_RD_EN = rRead;
assign WR_DATA = EVT_DATA[C_DATA_WIDTH-1:0];
assign WR_EN = wPayloadData;
assign TXN = rState[2]; // S_TXPORTMON32_TXN
assign LAST = rReadOffLast[0];
assign OFF = rReadOffLast[31:1];
assign LEN = rReadLen;
assign WORDS_RECVD = rWordsRecvd;
assign DONE = !rState[3]; // !S_TXPORTMON32_READ
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CLK) begin
rTxErr <= #1 (RST ? 1'd0 : _rTxErr);
end
always @ (*) begin
_rTxErr = TX_ERR;
end
// Transaction monitoring FSM.
always @ (posedge CLK) begin
rState <= #1 (RST ? `S_TXPORTMON32_NEXT : _rState);
end
always @ (*) begin
_rState = rState;
case (rState)
`S_TXPORTMON32_NEXT: begin // Read, wait for start of transaction event
if (rEvent)
_rState = `S_TXPORTMON32_TXN;
end
`S_TXPORTMON32_EVT_2: begin // Read, wait for start of transaction event
if (rEvent)
_rState = `S_TXPORTMON32_TXN;
end
`S_TXPORTMON32_TXN: begin // Don't read, wait until transaction has been acknowledged
if (ACK)
_rState = ((rLenEQ0Hi && rLenEQ0Lo) ? `S_TXPORTMON32_END_0 : `S_TXPORTMON32_READ);
end
`S_TXPORTMON32_READ: begin // Continue reading, wait for end of transaction event or all expected data
if (rEvent)
_rState = `S_TXPORTMON32_END_1;
else if (wAllWordsRecvd | rTxErr)
_rState = `S_TXPORTMON32_END_0;
end
`S_TXPORTMON32_END_0: begin // Continue reading, wait for first end of transaction event
if (rEvent)
_rState = `S_TXPORTMON32_END_1;
end
`S_TXPORTMON32_END_1: begin // Continue reading, wait for second end of transaction event
if (rEvent)
_rState = `S_TXPORTMON32_NEXT;
end
default: begin
_rState = `S_TXPORTMON32_NEXT;
end
endcase
end
// Manage reading from the FIFO and tracking amounts read.
always @ (posedge CLK) begin
rRead <= #1 (RST ? 1'd0 : _rRead);
rDataValid <= #1 (RST ? {C_VALID_HIST{1'd0}} : _rDataValid);
rEvent <= #1 (RST ? 1'd0 : _rEvent);
rReadOffLast <= #1 _rReadOffLast;
rReadLen <= #1 _rReadLen;
rReadCount <= #1 (RST ? 1'd0 : _rReadCount);
rWordsRecvd <= #1 _rWordsRecvd;
rWordsRecvdAdv <= #1 _rWordsRecvdAdv;
rAlmostAllRecvd <= #1 _rAlmostAllRecvd;
rAlmostFull <= #1 _rAlmostFull;
rLenEQ0Hi <= #1 _rLenEQ0Hi;
rLenEQ0Lo <= #1 _rLenEQ0Lo;
rLenLE1Lo <= #1 _rLenLE1Lo;
end
always @ (*) begin
// Don't get to the full point in the output FIFO
_rAlmostFull = (WR_COUNT >= C_FIFO_DEPTH_THRESH);
// Track read history so we know when data is valid
_rDataValid = ((rDataValid<<1) | (rRead & !EVT_DATA_EMPTY));
// Read until we get a (valid) event
_rRead = (!rState[2] & !(rState[1] & rEvent) & !wEventData & !rAlmostFull); // !S_TXPORTMON32_TXN
// Track detected events
_rEvent = wEventData;
// Save event data when valid
if (wEventData) begin
_rReadOffLast = (rReadCount ? EVT_DATA[C_DATA_WIDTH-1:0] : rReadOffLast);
_rReadLen = (!rReadCount ? EVT_DATA[C_DATA_WIDTH-1:0] : rReadLen);
_rReadCount = rReadCount + 1'd1;
end
else begin
_rReadOffLast = rReadOffLast;
_rReadLen = rReadLen;
_rReadCount = rReadCount;
end
// If LEN == 0, we don't want to send any data to the output
_rLenEQ0Hi = (LEN[31:16] == 16'd0);
_rLenEQ0Lo = (LEN[15:0] == 16'd0);
// If LEN <= 1, we want to trigger the almost all received flag
_rLenLE1Lo = (LEN[15:0] <= 16'd1);
// Count received non-event data
_rWordsRecvd = (ACK ? 0 : rWordsRecvd + wPayloadData);
_rWordsRecvdAdv = (ACK ? 2*(C_DATA_WIDTH/32) : rWordsRecvdAdv + wPayloadData);
_rAlmostAllRecvd = ((rWordsRecvdAdv >= LEN) && wPayloadData);
end
/*
wire [35:0] wControl0;
chipscope_icon_1 cs_icon(
.CONTROL0(wControl0)
);
chipscope_ila_t8_512 a0(
.CLK(CLK),
.CONTROL(wControl0),
.TRIG0({TXN, wPayloadData, wEventData, rState}),
.DATA({297'd0,
WR_COUNT, // 10
wPayloadData, // 1
EVT_DATA_RD_EN, // 1
RST, // 1
rTxErr, // 1
wEventData, // 1
rReadData, // 64
OFF, // 31
LEN, // 32
LAST, // 1
TXN, // 1
EVT_DATA_EMPTY, // 1
EVT_DATA, // 65
rState}) // 5
);
*/
endmodule
|
/*
* Sound module
* Copyright (C) 2010 Donna Polehn <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
// --------------------------------------------------------------------
// Description: Sound module. This is NOT a sound blaster emulator.
// This module produces simple sounds by implementing a simple interface,
// The user simply writes a byte of data to the left and/or right channels.
// Then poll the status register which will raise a flag when ready for the
// next byte of data. Alternatively, it can generate an interupt to request
// the next byte.
//
// Sound uses 16 I/O addresses 0x0nn0 to 0x0nnF, nn can be anything
//
// I/O Address Description
// ----------- ------------------
// 0x0210 Left Channel
// 0x0211 Right Channel
// 0x0212 High byte of timing increment
// 0x0213 Low byte of timing increment
// 0x0215 Control, 0x01 to enable interupt, 0x00 for polled mode
// 0x0217 Status, 0x80 when ready for next data, else 0x00
//
// --------------------------------------------------------------------
module sound (
input wb_clk_i,
input wb_rst_i,
input [ 2:0] wb_adr_i,
input [ 1:0] wb_sel_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input wb_cyc_i,
input wb_stb_i,
input wb_we_i,
output reg wb_ack_o,
output audio_l,
output audio_r
);
// --------------------------------------------------------------------
// Wishbone Handling
// --------------------------------------------------------------------
reg [7:0] sb_dat_o;
wire [3:0] sb_adr_i = {wb_adr_i, wb_sel_i[1]};
wire [7:0] sb_dat_i = wb_sel_i[0] ? wb_dat_i[7:0] : wb_dat_i[15:8]; // 16 to 8 bit
assign wb_dat_o = {sb_dat_o, sb_dat_o};
wire wb_ack_i = wb_stb_i & wb_cyc_i; // Immediate ack
wire wr_command = wb_ack_i & wb_we_i; // Wishbone write access, Singal to send
wire rd_command = wb_ack_i & ~wb_we_i; // Wishbone write access, Singal to send
always @(posedge wb_clk_i or posedge wb_rst_i) begin // Synchrounous
if(wb_rst_i) wb_ack_o <= 1'b0;
else wb_ack_o <= wb_ack_i & ~wb_ack_o; // one clock delay on acknowledge output
end
// --------------------------------------------------------------------
// The following table lists the functions of the I/O ports:
// I/O Address Description Access
// ----------- -------------------
// Base + 0 Left channel data, write only
// Base + 1 Right channel data, write only
// Base + 2 High byte for timer, write only
// Base + 3 Low byte for timer, write only
// Base + 5 Control, write only
// Base + 7 Status, read only
// --------------------------------------------------------------------
`define REG_CHAN01 4'h0 // W - Channel 1
`define REG_CHAN02 4'h1 // W - Channel 1
`define REG_TIMERH 4'h2 // W - Timer increment high byte
`define REG_TIMERL 4'h3 // W - Timer increment low byte
`define REG_CONTRL 4'h5 // W - Control
`define REG_STATUS 4'h7 // R - Status
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// DefaultTime Constant
// --------------------------------------------------------------------
`define DSP_DEFAULT_RATE 16'd671 // Default sampling rate is 8Khz
// --------------------------------------------------------------------
// Sound Blaster Register behavior
// --------------------------------------------------------------------
reg start; // Start the timer
reg timeout; // Timer has timed out
reg [19:0] timer; // DAC output timer register
reg [15:0] time_inc; // DAC output time increment
wire [7:0] TMR_STATUS = {timeout, 7'h00};
always @(posedge wb_clk_i) begin // Synchrounous Logic
if(wb_rst_i) begin
sb_dat_o <= 8'h00; // Default value
end
else begin
if(rd_command) begin
case(sb_adr_i) // Determine which register was read
`REG_STATUS: sb_dat_o <= TMR_STATUS; // DSP Read status
`REG_TIMERH: sb_dat_o <= time_inc[15:8]; // Read back the timing register
`REG_TIMERL: sb_dat_o <= time_inc[ 7:0]; // Read back the timing register
default: sb_dat_o <= 8'h00; // Default
endcase // End of case
end
end // End of Reset if
end // End Synchrounous always
always @(posedge wb_clk_i) begin // Synchrounous Logic
if(wb_rst_i) begin
dsp_audio_l <= 8'h80; // default is equivalent to 1/2
dsp_audio_r <= 8'h80; // default is equivalent to 1/2
start <= 1'b0; // Timer not on
timeout <= 1'b0; // Not timed out
time_inc <= `DSP_DEFAULT_RATE; // Default value
end
else begin
if(wr_command) begin // If a write was requested
case(sb_adr_i) // Determine which register was writen to
`REG_CHAN01: begin
dsp_audio_l <= sb_dat_i; // Get the user data or data
start <= 1'b1;
timeout <= 1'b0;
end
`REG_CHAN02: begin
dsp_audio_r <= sb_dat_i; // Get the user data or data
start <= 1'b1;
timeout <= 1'b0;
end
`REG_TIMERH: time_inc[15:8] <= sb_dat_i; // Get the user data or data
`REG_TIMERL: time_inc[ 7:0] <= sb_dat_i; // Get the user data or data
default: ; // Default value
endcase // End of case
end // End of Write Command if
if(timed_out) begin
start <= 1'b0;
timeout <= 1'b1;
end
end // End of Reset if
end // End Synchrounous always
// --------------------------------------------------------------------
// Audio Timer interrupt Generation Section
// DAC Clock set to system clock which is 12,500,000Hz
// Interval = DAC_ClK / Incr = 12,500,000 / (1048576 / X ) = 8000Hz
// X = 1048576 / (12,500,000 / 8000) = 1048576 / 1562.5
// X = 671
// --------------------------------------------------------------------
wire timed_out = timer[19];
always @(posedge wb_clk_i) begin
if(wb_rst_i) begin
timer <= 20'd0;
end
else begin
if(start) timer <= timer + time_inc;
else timer <= 20'd0;
end
end
// --------------------------------------------------------------------
// PWM CLock Generation Section:
// We need to divide down the clock for PWM, dac_clk = 12.5Mhz
// then 12,500,000 / 512 = 24,414Hz which is a good sampling rate for audio
// 0 = 2
// 1 = 4
// 2 = 8 1,562,500Hz
// 3 = 16
// 4 = 32
// 5 = 64
// 6 = 128
// 7 = 256
// 8 = 512 24,414Hz
// --------------------------------------------------------------------
wire pwm_clk;
assign pwm_clk = wb_clk_i; // Because it's already at 12.5 Mhz
// --------------------------------------------------------------------
// Audio Generation Section
// --------------------------------------------------------------------
reg [7:0] dsp_audio_l;
reg [7:0] dsp_audio_r;
sound_dac8 left (pwm_clk, dsp_audio_l, audio_l); // 8 bit pwm DAC
sound_dac8 right(pwm_clk, dsp_audio_r, audio_r); // 8 bit pwm DAC
endmodule
|
(***********************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA-Rocquencourt & LRI-CNRS-Orsay *)
(* \VV/ *************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(***********************************************************************)
(** * Finite set library *)
(** Set interfaces, inspired by the one of Ocaml. When compared with
Ocaml, the main differences are:
- the lack of [iter] function, useless since Coq is purely functional
- the use of [option] types instead of [Not_found] exceptions
- the use of [nat] instead of [int] for the [cardinal] function
Several variants of the set interfaces are available:
- [WSetsOn] : functorial signature for weak sets
- [WSets] : self-contained version of [WSets]
- [SetsOn] : functorial signature for ordered sets
- [Sets] : self-contained version of [Sets]
- [WRawSets] : a signature for weak sets that may be ill-formed
- [RawSets] : same for ordered sets
If unsure, [S = Sets] is probably what you're looking for: most other
signatures are subsets of it, while [Sets] can be obtained from
[RawSets] via the use of a subset type (see (W)Raw2Sets below).
*)
Require Export Bool SetoidList RelationClasses Morphisms
RelationPairs Equalities Orders OrdersFacts.
Set Implicit Arguments.
Unset Strict Implicit.
Module Type TypElt.
Parameters t elt : Type.
End TypElt.
Module Type HasWOps (Import T:TypElt).
Parameter empty : t.
(** The empty set. *)
Parameter is_empty : t -> bool.
(** Test whether a set is empty or not. *)
Parameter mem : elt -> t -> bool.
(** [mem x s] tests whether [x] belongs to the set [s]. *)
Parameter add : elt -> t -> t.
(** [add x s] returns a set containing all elements of [s],
plus [x]. If [x] was already in [s], [s] is returned unchanged. *)
Parameter singleton : elt -> t.
(** [singleton x] returns the one-element set containing only [x]. *)
Parameter remove : elt -> t -> t.
(** [remove x s] returns a set containing all elements of [s],
except [x]. If [x] was not in [s], [s] is returned unchanged. *)
Parameter union : t -> t -> t.
(** Set union. *)
Parameter inter : t -> t -> t.
(** Set intersection. *)
Parameter diff : t -> t -> t.
(** Set difference. *)
Parameter equal : t -> t -> bool.
(** [equal s1 s2] tests whether the sets [s1] and [s2] are
equal, that is, contain equal elements. *)
Parameter subset : t -> t -> bool.
(** [subset s1 s2] tests whether the set [s1] is a subset of
the set [s2]. *)
Parameter fold : forall A : Type, (elt -> A -> A) -> t -> A -> A.
(** [fold f s a] computes [(f xN ... (f x2 (f x1 a))...)],
where [x1 ... xN] are the elements of [s].
The order in which elements of [s] are presented to [f] is
unspecified. *)
Parameter for_all : (elt -> bool) -> t -> bool.
(** [for_all p s] checks if all elements of the set
satisfy the predicate [p]. *)
Parameter exists_ : (elt -> bool) -> t -> bool.
(** [exists p s] checks if at least one element of
the set satisfies the predicate [p]. *)
Parameter filter : (elt -> bool) -> t -> t.
(** [filter p s] returns the set of all elements in [s]
that satisfy predicate [p]. *)
Parameter partition : (elt -> bool) -> t -> t * t.
(** [partition p s] returns a pair of sets [(s1, s2)], where
[s1] is the set of all the elements of [s] that satisfy the
predicate [p], and [s2] is the set of all the elements of
[s] that do not satisfy [p]. *)
Parameter cardinal : t -> nat.
(** Return the number of elements of a set. *)
Parameter elements : t -> list elt.
(** Return the list of all elements of the given set, in any order. *)
Parameter choose : t -> option elt.
(** Return one element of the given set, or [None] if
the set is empty. Which element is chosen is unspecified.
Equal sets could return different elements. *)
End HasWOps.
Module Type WOps (E : DecidableType).
Definition elt := E.t.
Parameter t : Type. (** the abstract type of sets *)
Include HasWOps.
End WOps.
(** ** Functorial signature for weak sets
Weak sets are sets without ordering on base elements, only
a decidable equality. *)
Module Type WSetsOn (E : DecidableType).
(** First, we ask for all the functions *)
Include WOps E.
(** Logical predicates *)
Parameter In : elt -> t -> Prop.
Declare Instance In_compat : Proper (E.eq==>eq==>iff) In.
Definition Equal s s' := forall a : elt, In a s <-> In a s'.
Definition Subset s s' := forall a : elt, In a s -> In a s'.
Definition Empty s := forall a : elt, ~ In a s.
Definition For_all (P : elt -> Prop) s := forall x, In x s -> P x.
Definition Exists (P : elt -> Prop) s := exists x, In x s /\ P x.
Notation "s [=] t" := (Equal s t) (at level 70, no associativity).
Notation "s [<=] t" := (Subset s t) (at level 70, no associativity).
Definition eq : t -> t -> Prop := Equal.
Include IsEq. (** [eq] is obviously an equivalence, for subtyping only *)
Include HasEqDec.
(** Specifications of set operators *)
Section Spec.
Variable s s': t.
Variable x y : elt.
Variable f : elt -> bool.
Notation compatb := (Proper (E.eq==>Logic.eq)) (only parsing).
Parameter mem_spec : mem x s = true <-> In x s.
Parameter equal_spec : equal s s' = true <-> s[=]s'.
Parameter subset_spec : subset s s' = true <-> s[<=]s'.
Parameter empty_spec : Empty empty.
Parameter is_empty_spec : is_empty s = true <-> Empty s.
Parameter add_spec : In y (add x s) <-> E.eq y x \/ In y s.
Parameter remove_spec : In y (remove x s) <-> In y s /\ ~E.eq y x.
Parameter singleton_spec : In y (singleton x) <-> E.eq y x.
Parameter union_spec : In x (union s s') <-> In x s \/ In x s'.
Parameter inter_spec : In x (inter s s') <-> In x s /\ In x s'.
Parameter diff_spec : In x (diff s s') <-> In x s /\ ~In x s'.
Parameter fold_spec : forall (A : Type) (i : A) (f : elt -> A -> A),
fold f s i = fold_left (flip f) (elements s) i.
Parameter cardinal_spec : cardinal s = length (elements s).
Parameter filter_spec : compatb f ->
(In x (filter f s) <-> In x s /\ f x = true).
Parameter for_all_spec : compatb f ->
(for_all f s = true <-> For_all (fun x => f x = true) s).
Parameter exists_spec : compatb f ->
(exists_ f s = true <-> Exists (fun x => f x = true) s).
Parameter partition_spec1 : compatb f ->
fst (partition f s) [=] filter f s.
Parameter partition_spec2 : compatb f ->
snd (partition f s) [=] filter (fun x => negb (f x)) s.
Parameter elements_spec1 : InA E.eq x (elements s) <-> In x s.
(** When compared with ordered sets, here comes the only
property that is really weaker: *)
Parameter elements_spec2w : NoDupA E.eq (elements s).
Parameter choose_spec1 : choose s = Some x -> In x s.
Parameter choose_spec2 : choose s = None -> Empty s.
End Spec.
End WSetsOn.
(** ** Static signature for weak sets
Similar to the functorial signature [WSetsOn], except that the
module [E] of base elements is incorporated in the signature. *)
Module Type WSets.
Declare Module E : DecidableType.
Include WSetsOn E.
End WSets.
(** ** Functorial signature for sets on ordered elements
Based on [WSetsOn], plus ordering on sets and [min_elt] and [max_elt]
and some stronger specifications for other functions. *)
Module Type HasOrdOps (Import T:TypElt).
Parameter compare : t -> t -> comparison.
(** Total ordering between sets. Can be used as the ordering function
for doing sets of sets. *)
Parameter min_elt : t -> option elt.
(** Return the smallest element of the given set
(with respect to the [E.compare] ordering),
or [None] if the set is empty. *)
Parameter max_elt : t -> option elt.
(** Same as [min_elt], but returns the largest element of the
given set. *)
End HasOrdOps.
Module Type Ops (E : OrderedType) := WOps E <+ HasOrdOps.
Module Type SetsOn (E : OrderedType).
Include WSetsOn E <+ HasOrdOps <+ HasLt <+ IsStrOrder.
Section Spec.
Variable s s': t.
Variable x y : elt.
Parameter compare_spec : CompSpec eq lt s s' (compare s s').
(** Additional specification of [elements] *)
Parameter elements_spec2 : sort E.lt (elements s).
(** Remark: since [fold] is specified via [elements], this stronger
specification of [elements] has an indirect impact on [fold],
which can now be proved to receive elements in increasing order.
*)
Parameter min_elt_spec1 : min_elt s = Some x -> In x s.
Parameter min_elt_spec2 : min_elt s = Some x -> In y s -> ~ E.lt y x.
Parameter min_elt_spec3 : min_elt s = None -> Empty s.
Parameter max_elt_spec1 : max_elt s = Some x -> In x s.
Parameter max_elt_spec2 : max_elt s = Some x -> In y s -> ~ E.lt x y.
Parameter max_elt_spec3 : max_elt s = None -> Empty s.
(** Additional specification of [choose] *)
Parameter choose_spec3 : choose s = Some x -> choose s' = Some y ->
Equal s s' -> E.eq x y.
End Spec.
End SetsOn.
(** ** Static signature for sets on ordered elements
Similar to the functorial signature [SetsOn], except that the
module [E] of base elements is incorporated in the signature. *)
Module Type Sets.
Declare Module E : OrderedType.
Include SetsOn E.
End Sets.
Module Type S := Sets.
(** ** Some subtyping tests
<<
WSetsOn ---> WSets
| |
| |
V V
SetsOn ---> Sets
Module S_WS (M : Sets) <: WSets := M.
Module Sfun_WSfun (E:OrderedType)(M : SetsOn E) <: WSetsOn E := M.
Module S_Sfun (M : Sets) <: SetsOn M.E := M.
Module WS_WSfun (M : WSets) <: WSetsOn M.E := M.
>>
*)
(** ** Signatures for set representations with ill-formed values.
Motivation:
For many implementation of finite sets (AVL trees, sorted
lists, lists without duplicates), we use the same two-layer
approach:
- A first module deals with the datatype (eg. list or tree) without
any restriction on the values we consider. In this module (named
"Raw" in the past), some results are stated under the assumption
that some invariant (e.g. sortedness) holds for the input sets. We
also prove that this invariant is preserved by set operators.
- A second module implements the exact Sets interface by
using a subtype, for instance [{ l : list A | sorted l }].
This module is a mere wrapper around the first Raw module.
With the interfaces below, we give some respectability to
the "Raw" modules. This allows the interested users to directly
access them via the interfaces. Even better, we can build once
and for all a functor doing the transition between Raw and usual Sets.
Description:
The type [t] of sets may contain ill-formed values on which our
set operators may give wrong answers. In particular, [mem]
may not see a element in a ill-formed set (think for instance of a
unsorted list being given to an optimized [mem] that stops
its search as soon as a strictly larger element is encountered).
Unlike optimized operators, the [In] predicate is supposed to
always be correct, even on ill-formed sets. Same for [Equal] and
other logical predicates.
A predicate parameter [Ok] is used to discriminate between
well-formed and ill-formed values. Some lemmas hold only on sets
validating [Ok]. This predicate [Ok] is required to be
preserved by set operators. Moreover, a boolean function [isok]
should exist for identifying (at least some of) the well-formed sets.
*)
Module Type WRawSets (E : DecidableType).
(** First, we ask for all the functions *)
Include WOps E.
(** Is a set well-formed or ill-formed ? *)
Parameter IsOk : t -> Prop.
Class Ok (s:t) : Prop := ok : IsOk s.
(** In order to be able to validate (at least some) particular sets as
well-formed, we ask for a boolean function for (semi-)deciding
predicate [Ok]. If [Ok] isn't decidable, [isok] may be the
always-false function. *)
Parameter isok : t -> bool.
Declare Instance isok_Ok s `(isok s = true) : Ok s | 10.
(** Logical predicates *)
Parameter In : elt -> t -> Prop.
Declare Instance In_compat : Proper (E.eq==>eq==>iff) In.
Definition Equal s s' := forall a : elt, In a s <-> In a s'.
Definition Subset s s' := forall a : elt, In a s -> In a s'.
Definition Empty s := forall a : elt, ~ In a s.
Definition For_all (P : elt -> Prop) s := forall x, In x s -> P x.
Definition Exists (P : elt -> Prop) s := exists x, In x s /\ P x.
Notation "s [=] t" := (Equal s t) (at level 70, no associativity).
Notation "s [<=] t" := (Subset s t) (at level 70, no associativity).
Definition eq : t -> t -> Prop := Equal.
Declare Instance eq_equiv : Equivalence eq.
(** First, all operations are compatible with the well-formed predicate. *)
Declare Instance empty_ok : Ok empty.
Declare Instance add_ok s x `(Ok s) : Ok (add x s).
Declare Instance remove_ok s x `(Ok s) : Ok (remove x s).
Declare Instance singleton_ok x : Ok (singleton x).
Declare Instance union_ok s s' `(Ok s, Ok s') : Ok (union s s').
Declare Instance inter_ok s s' `(Ok s, Ok s') : Ok (inter s s').
Declare Instance diff_ok s s' `(Ok s, Ok s') : Ok (diff s s').
Declare Instance filter_ok s f `(Ok s) : Ok (filter f s).
Declare Instance partition_ok1 s f `(Ok s) : Ok (fst (partition f s)).
Declare Instance partition_ok2 s f `(Ok s) : Ok (snd (partition f s)).
(** Now, the specifications, with constraints on the input sets. *)
Section Spec.
Variable s s': t.
Variable x y : elt.
Variable f : elt -> bool.
Notation compatb := (Proper (E.eq==>Logic.eq)) (only parsing).
Parameter mem_spec : forall `{Ok s}, mem x s = true <-> In x s.
Parameter equal_spec : forall `{Ok s, Ok s'},
equal s s' = true <-> s[=]s'.
Parameter subset_spec : forall `{Ok s, Ok s'},
subset s s' = true <-> s[<=]s'.
Parameter empty_spec : Empty empty.
Parameter is_empty_spec : is_empty s = true <-> Empty s.
Parameter add_spec : forall `{Ok s},
In y (add x s) <-> E.eq y x \/ In y s.
Parameter remove_spec : forall `{Ok s},
In y (remove x s) <-> In y s /\ ~E.eq y x.
Parameter singleton_spec : In y (singleton x) <-> E.eq y x.
Parameter union_spec : forall `{Ok s, Ok s'},
In x (union s s') <-> In x s \/ In x s'.
Parameter inter_spec : forall `{Ok s, Ok s'},
In x (inter s s') <-> In x s /\ In x s'.
Parameter diff_spec : forall `{Ok s, Ok s'},
In x (diff s s') <-> In x s /\ ~In x s'.
Parameter fold_spec : forall (A : Type) (i : A) (f : elt -> A -> A),
fold f s i = fold_left (flip f) (elements s) i.
Parameter cardinal_spec : forall `{Ok s},
cardinal s = length (elements s).
Parameter filter_spec : compatb f ->
(In x (filter f s) <-> In x s /\ f x = true).
Parameter for_all_spec : compatb f ->
(for_all f s = true <-> For_all (fun x => f x = true) s).
Parameter exists_spec : compatb f ->
(exists_ f s = true <-> Exists (fun x => f x = true) s).
Parameter partition_spec1 : compatb f ->
fst (partition f s) [=] filter f s.
Parameter partition_spec2 : compatb f ->
snd (partition f s) [=] filter (fun x => negb (f x)) s.
Parameter elements_spec1 : InA E.eq x (elements s) <-> In x s.
Parameter elements_spec2w : forall `{Ok s}, NoDupA E.eq (elements s).
Parameter choose_spec1 : choose s = Some x -> In x s.
Parameter choose_spec2 : choose s = None -> Empty s.
End Spec.
End WRawSets.
(** From weak raw sets to weak usual sets *)
Module WRaw2SetsOn (E:DecidableType)(M:WRawSets E) <: WSetsOn E.
(** We avoid creating induction principles for the Record *)
Local Unset Elimination Schemes.
Definition elt := E.t.
Record t_ := Mkt {this :> M.t; is_ok : M.Ok this}.
Definition t := t_.
Arguments Mkt this {is_ok}.
Hint Resolve is_ok : typeclass_instances.
Definition In (x : elt)(s : t) := M.In x s.(this).
Definition Equal (s s' : t) := forall a : elt, In a s <-> In a s'.
Definition Subset (s s' : t) := forall a : elt, In a s -> In a s'.
Definition Empty (s : t) := forall a : elt, ~ In a s.
Definition For_all (P : elt -> Prop)(s : t) := forall x, In x s -> P x.
Definition Exists (P : elt -> Prop)(s : t) := exists x, In x s /\ P x.
Definition mem (x : elt)(s : t) := M.mem x s.
Definition add (x : elt)(s : t) : t := Mkt (M.add x s).
Definition remove (x : elt)(s : t) : t := Mkt (M.remove x s).
Definition singleton (x : elt) : t := Mkt (M.singleton x).
Definition union (s s' : t) : t := Mkt (M.union s s').
Definition inter (s s' : t) : t := Mkt (M.inter s s').
Definition diff (s s' : t) : t := Mkt (M.diff s s').
Definition equal (s s' : t) := M.equal s s'.
Definition subset (s s' : t) := M.subset s s'.
Definition empty : t := Mkt M.empty.
Definition is_empty (s : t) := M.is_empty s.
Definition elements (s : t) : list elt := M.elements s.
Definition choose (s : t) : option elt := M.choose s.
Definition fold (A : Type)(f : elt -> A -> A)(s : t) : A -> A := M.fold f s.
Definition cardinal (s : t) := M.cardinal s.
Definition filter (f : elt -> bool)(s : t) : t := Mkt (M.filter f s).
Definition for_all (f : elt -> bool)(s : t) := M.for_all f s.
Definition exists_ (f : elt -> bool)(s : t) := M.exists_ f s.
Definition partition (f : elt -> bool)(s : t) : t * t :=
let p := M.partition f s in (Mkt (fst p), Mkt (snd p)).
Instance In_compat : Proper (E.eq==>eq==>iff) In.
Proof. repeat red. intros; apply M.In_compat; congruence. Qed.
Definition eq : t -> t -> Prop := Equal.
Instance eq_equiv : Equivalence eq.
Proof. firstorder. Qed.
Definition eq_dec : forall (s s':t), { eq s s' }+{ ~eq s s' }.
Proof.
intros (s,Hs) (s',Hs').
change ({M.Equal s s'}+{~M.Equal s s'}).
destruct (M.equal s s') eqn:H; [left|right];
rewrite <- M.equal_spec; congruence.
Defined.
Section Spec.
Variable s s' : t.
Variable x y : elt.
Variable f : elt -> bool.
Notation compatb := (Proper (E.eq==>Logic.eq)) (only parsing).
Lemma mem_spec : mem x s = true <-> In x s.
Proof. exact (@M.mem_spec _ _ _). Qed.
Lemma equal_spec : equal s s' = true <-> Equal s s'.
Proof. exact (@M.equal_spec _ _ _ _). Qed.
Lemma subset_spec : subset s s' = true <-> Subset s s'.
Proof. exact (@M.subset_spec _ _ _ _). Qed.
Lemma empty_spec : Empty empty.
Proof. exact M.empty_spec. Qed.
Lemma is_empty_spec : is_empty s = true <-> Empty s.
Proof. exact (@M.is_empty_spec _). Qed.
Lemma add_spec : In y (add x s) <-> E.eq y x \/ In y s.
Proof. exact (@M.add_spec _ _ _ _). Qed.
Lemma remove_spec : In y (remove x s) <-> In y s /\ ~E.eq y x.
Proof. exact (@M.remove_spec _ _ _ _). Qed.
Lemma singleton_spec : In y (singleton x) <-> E.eq y x.
Proof. exact (@M.singleton_spec _ _). Qed.
Lemma union_spec : In x (union s s') <-> In x s \/ In x s'.
Proof. exact (@M.union_spec _ _ _ _ _). Qed.
Lemma inter_spec : In x (inter s s') <-> In x s /\ In x s'.
Proof. exact (@M.inter_spec _ _ _ _ _). Qed.
Lemma diff_spec : In x (diff s s') <-> In x s /\ ~In x s'.
Proof. exact (@M.diff_spec _ _ _ _ _). Qed.
Lemma fold_spec : forall (A : Type) (i : A) (f : elt -> A -> A),
fold f s i = fold_left (fun a e => f e a) (elements s) i.
Proof. exact (@M.fold_spec _). Qed.
Lemma cardinal_spec : cardinal s = length (elements s).
Proof. exact (@M.cardinal_spec s _). Qed.
Lemma filter_spec : compatb f ->
(In x (filter f s) <-> In x s /\ f x = true).
Proof. exact (@M.filter_spec _ _ _). Qed.
Lemma for_all_spec : compatb f ->
(for_all f s = true <-> For_all (fun x => f x = true) s).
Proof. exact (@M.for_all_spec _ _). Qed.
Lemma exists_spec : compatb f ->
(exists_ f s = true <-> Exists (fun x => f x = true) s).
Proof. exact (@M.exists_spec _ _). Qed.
Lemma partition_spec1 : compatb f -> Equal (fst (partition f s)) (filter f s).
Proof. exact (@M.partition_spec1 _ _). Qed.
Lemma partition_spec2 : compatb f ->
Equal (snd (partition f s)) (filter (fun x => negb (f x)) s).
Proof. exact (@M.partition_spec2 _ _). Qed.
Lemma elements_spec1 : InA E.eq x (elements s) <-> In x s.
Proof. exact (@M.elements_spec1 _ _). Qed.
Lemma elements_spec2w : NoDupA E.eq (elements s).
Proof. exact (@M.elements_spec2w _ _). Qed.
Lemma choose_spec1 : choose s = Some x -> In x s.
Proof. exact (@M.choose_spec1 _ _). Qed.
Lemma choose_spec2 : choose s = None -> Empty s.
Proof. exact (@M.choose_spec2 _). Qed.
End Spec.
End WRaw2SetsOn.
Module WRaw2Sets (D:DecidableType)(M:WRawSets D) <: WSets with Module E := D.
Module E := D.
Include WRaw2SetsOn D M.
End WRaw2Sets.
(** Same approach for ordered sets *)
Module Type RawSets (E : OrderedType).
Include WRawSets E <+ HasOrdOps <+ HasLt <+ IsStrOrder.
Section Spec.
Variable s s': t.
Variable x y : elt.
(** Specification of [compare] *)
Parameter compare_spec : forall `{Ok s, Ok s'}, CompSpec eq lt s s' (compare s s').
(** Additional specification of [elements] *)
Parameter elements_spec2 : forall `{Ok s}, sort E.lt (elements s).
(** Specification of [min_elt] *)
Parameter min_elt_spec1 : min_elt s = Some x -> In x s.
Parameter min_elt_spec2 : forall `{Ok s}, min_elt s = Some x -> In y s -> ~ E.lt y x.
Parameter min_elt_spec3 : min_elt s = None -> Empty s.
(** Specification of [max_elt] *)
Parameter max_elt_spec1 : max_elt s = Some x -> In x s.
Parameter max_elt_spec2 : forall `{Ok s}, max_elt s = Some x -> In y s -> ~ E.lt x y.
Parameter max_elt_spec3 : max_elt s = None -> Empty s.
(** Additional specification of [choose] *)
Parameter choose_spec3 : forall `{Ok s, Ok s'},
choose s = Some x -> choose s' = Some y -> Equal s s' -> E.eq x y.
End Spec.
End RawSets.
(** From Raw to usual sets *)
Module Raw2SetsOn (O:OrderedType)(M:RawSets O) <: SetsOn O.
Include WRaw2SetsOn O M.
Definition compare (s s':t) := M.compare s s'.
Definition min_elt (s:t) : option elt := M.min_elt s.
Definition max_elt (s:t) : option elt := M.max_elt s.
Definition lt (s s':t) := M.lt s s'.
(** Specification of [lt] *)
Instance lt_strorder : StrictOrder lt.
Proof. constructor ; unfold lt; red.
unfold complement. red. intros. apply (irreflexivity H).
intros. transitivity y; auto.
Qed.
Instance lt_compat : Proper (eq==>eq==>iff) lt.
Proof.
repeat red. unfold eq, lt.
intros (s1,p1) (s2,p2) E (s1',p1') (s2',p2') E'; simpl.
change (M.eq s1 s2) in E.
change (M.eq s1' s2') in E'.
rewrite E,E'; intuition.
Qed.
Section Spec.
Variable s s' s'' : t.
Variable x y : elt.
Lemma compare_spec : CompSpec eq lt s s' (compare s s').
Proof. unfold compare; destruct (@M.compare_spec s s' _ _); auto. Qed.
(** Additional specification of [elements] *)
Lemma elements_spec2 : sort O.lt (elements s).
Proof. exact (@M.elements_spec2 _ _). Qed.
(** Specification of [min_elt] *)
Lemma min_elt_spec1 : min_elt s = Some x -> In x s.
Proof. exact (@M.min_elt_spec1 _ _). Qed.
Lemma min_elt_spec2 : min_elt s = Some x -> In y s -> ~ O.lt y x.
Proof. exact (@M.min_elt_spec2 _ _ _ _). Qed.
Lemma min_elt_spec3 : min_elt s = None -> Empty s.
Proof. exact (@M.min_elt_spec3 _). Qed.
(** Specification of [max_elt] *)
Lemma max_elt_spec1 : max_elt s = Some x -> In x s.
Proof. exact (@M.max_elt_spec1 _ _). Qed.
Lemma max_elt_spec2 : max_elt s = Some x -> In y s -> ~ O.lt x y.
Proof. exact (@M.max_elt_spec2 _ _ _ _). Qed.
Lemma max_elt_spec3 : max_elt s = None -> Empty s.
Proof. exact (@M.max_elt_spec3 _). Qed.
(** Additional specification of [choose] *)
Lemma choose_spec3 :
choose s = Some x -> choose s' = Some y -> Equal s s' -> O.eq x y.
Proof. exact (@M.choose_spec3 _ _ _ _ _ _). Qed.
End Spec.
End Raw2SetsOn.
Module Raw2Sets (O:OrderedType)(M:RawSets O) <: Sets with Module E := O.
Module E := O.
Include Raw2SetsOn O M.
End Raw2Sets.
(** It is in fact possible to provide an ordering on sets with
very little information on them (more or less only the [In]
predicate). This generic build of ordering is in fact not
used for the moment, we rather use a simplier version
dedicated to sets-as-sorted-lists, see [MakeListOrdering].
*)
Module Type IN (O:OrderedType).
Parameter Inline t : Type.
Parameter Inline In : O.t -> t -> Prop.
Declare Instance In_compat : Proper (O.eq==>eq==>iff) In.
Definition Equal s s' := forall x, In x s <-> In x s'.
Definition Empty s := forall x, ~In x s.
End IN.
Module MakeSetOrdering (O:OrderedType)(Import M:IN O).
Module Import MO := OrderedTypeFacts O.
Definition eq : t -> t -> Prop := Equal.
Instance eq_equiv : Equivalence eq.
Proof. firstorder. Qed.
Instance : Proper (O.eq==>eq==>iff) In.
Proof.
intros x x' Ex s s' Es. rewrite Ex. apply Es.
Qed.
Definition Below x s := forall y, In y s -> O.lt y x.
Definition Above x s := forall y, In y s -> O.lt x y.
Definition EquivBefore x s s' :=
forall y, O.lt y x -> (In y s <-> In y s').
Definition EmptyBetween x y s :=
forall z, In z s -> O.lt z y -> O.lt z x.
Definition lt s s' := exists x, EquivBefore x s s' /\
((In x s' /\ Below x s) \/
(In x s /\ exists y, In y s' /\ O.lt x y /\ EmptyBetween x y s')).
Instance : Proper (O.eq==>eq==>eq==>iff) EquivBefore.
Proof.
unfold EquivBefore. intros x x' E s1 s1' E1 s2 s2' E2.
setoid_rewrite E; setoid_rewrite E1; setoid_rewrite E2; intuition.
Qed.
Instance : Proper (O.eq==>eq==>iff) Below.
Proof.
unfold Below. intros x x' Ex s s' Es.
setoid_rewrite Ex; setoid_rewrite Es; intuition.
Qed.
Instance : Proper (O.eq==>eq==>iff) Above.
Proof.
unfold Above. intros x x' Ex s s' Es.
setoid_rewrite Ex; setoid_rewrite Es; intuition.
Qed.
Instance : Proper (O.eq==>O.eq==>eq==>iff) EmptyBetween.
Proof.
unfold EmptyBetween. intros x x' Ex y y' Ey s s' Es.
setoid_rewrite Ex; setoid_rewrite Ey; setoid_rewrite Es; intuition.
Qed.
Instance lt_compat : Proper (eq==>eq==>iff) lt.
Proof.
unfold lt. intros s1 s1' E1 s2 s2' E2.
setoid_rewrite E1; setoid_rewrite E2; intuition.
Qed.
Instance lt_strorder : StrictOrder lt.
Proof.
split.
(* irreflexive *)
intros s (x & _ & [(IN,Em)|(IN & y & IN' & LT & Be)]).
specialize (Em x IN); order.
specialize (Be x IN LT); order.
(* transitive *)
intros s1 s2 s3 (x & EQ & [(IN,Pre)|(IN,Lex)])
(x' & EQ' & [(IN',Pre')|(IN',Lex')]).
(* 1) Pre / Pre --> Pre *)
assert (O.lt x x') by (specialize (Pre' x IN); auto).
exists x; split.
intros y Hy; rewrite <- (EQ' y); auto; order.
left; split; auto.
rewrite <- (EQ' x); auto.
(* 2) Pre / Lex *)
elim_compare x x'.
(* 2a) x=x' --> Pre *)
destruct Lex' as (y & INy & LT & Be).
exists y; split.
intros z Hz. split; intros INz.
specialize (Pre z INz). rewrite <- (EQ' z), <- (EQ z); auto; order.
specialize (Be z INz Hz). rewrite (EQ z), (EQ' z); auto; order.
left; split; auto.
intros z Hz. transitivity x; auto; order.
(* 2b) x<x' --> Pre *)
exists x; split.
intros z Hz. rewrite <- (EQ' z) by order; auto.
left; split; auto.
rewrite <- (EQ' x); auto.
(* 2c) x>x' --> Lex *)
exists x'; split.
intros z Hz. rewrite (EQ z) by order; auto.
right; split; auto.
rewrite (EQ x'); auto.
(* 3) Lex / Pre --> Lex *)
destruct Lex as (y & INy & LT & Be).
specialize (Pre' y INy).
exists x; split.
intros z Hz. rewrite <- (EQ' z) by order; auto.
right; split; auto.
exists y; repeat split; auto.
rewrite <- (EQ' y); auto.
intros z Hz LTz; apply Be; auto. rewrite (EQ' z); auto; order.
(* 4) Lex / Lex *)
elim_compare x x'.
(* 4a) x=x' --> impossible *)
destruct Lex as (y & INy & LT & Be).
setoid_replace x with x' in LT; auto.
specialize (Be x' IN' LT); order.
(* 4b) x<x' --> Lex *)
exists x; split.
intros z Hz. rewrite <- (EQ' z) by order; auto.
right; split; auto.
destruct Lex as (y & INy & LT & Be).
elim_compare y x'.
(* 4ba *)
destruct Lex' as (y' & Iny' & LT' & Be').
exists y'; repeat split; auto. order.
intros z Hz LTz. specialize (Be' z Hz LTz).
rewrite <- (EQ' z) in Hz by order.
apply Be; auto. order.
(* 4bb *)
exists y; repeat split; auto.
rewrite <- (EQ' y); auto.
intros z Hz LTz. apply Be; auto. rewrite (EQ' z); auto; order.
(* 4bc*)
assert (O.lt x' x) by auto. order.
(* 4c) x>x' --> Lex *)
exists x'; split.
intros z Hz. rewrite (EQ z) by order; auto.
right; split; auto.
rewrite (EQ x'); auto.
Qed.
Lemma lt_empty_r : forall s s', Empty s' -> ~ lt s s'.
Proof.
intros s s' Hs' (x & _ & [(IN,_)|(_ & y & IN & _)]).
elim (Hs' x IN).
elim (Hs' y IN).
Qed.
Definition Add x s s' := forall y, In y s' <-> O.eq x y \/ In y s.
Lemma lt_empty_l : forall x s1 s2 s2',
Empty s1 -> Above x s2 -> Add x s2 s2' -> lt s1 s2'.
Proof.
intros x s1 s2 s2' Em Ab Ad.
exists x; split.
intros y Hy; split; intros IN.
elim (Em y IN).
rewrite (Ad y) in IN; destruct IN as [EQ|IN]. order.
specialize (Ab y IN). order.
left; split.
rewrite (Ad x). now left.
intros y Hy. elim (Em y Hy).
Qed.
Lemma lt_add_lt : forall x1 x2 s1 s1' s2 s2',
Above x1 s1 -> Above x2 s2 -> Add x1 s1 s1' -> Add x2 s2 s2' ->
O.lt x1 x2 -> lt s1' s2'.
Proof.
intros x1 x2 s1 s1' s2 s2' Ab1 Ab2 Ad1 Ad2 LT.
exists x1; split; [ | right; split]; auto.
intros y Hy. rewrite (Ad1 y), (Ad2 y).
split; intros [U|U]; try order.
specialize (Ab1 y U). order.
specialize (Ab2 y U). order.
rewrite (Ad1 x1); auto with *.
exists x2; repeat split; auto.
rewrite (Ad2 x2); now left.
intros y. rewrite (Ad2 y). intros [U|U]. order.
specialize (Ab2 y U). order.
Qed.
Lemma lt_add_eq : forall x1 x2 s1 s1' s2 s2',
Above x1 s1 -> Above x2 s2 -> Add x1 s1 s1' -> Add x2 s2 s2' ->
O.eq x1 x2 -> lt s1 s2 -> lt s1' s2'.
Proof.
intros x1 x2 s1 s1' s2 s2' Ab1 Ab2 Ad1 Ad2 Hx (x & EQ & Disj).
assert (O.lt x1 x).
destruct Disj as [(IN,_)|(IN,_)]; auto. rewrite Hx; auto.
exists x; split.
intros z Hz. rewrite (Ad1 z), (Ad2 z).
split; intros [U|U]; try (left; order); right.
rewrite <- (EQ z); auto.
rewrite (EQ z); auto.
destruct Disj as [(IN,Em)|(IN & y & INy & LTy & Be)].
left; split; auto.
rewrite (Ad2 x); auto.
intros z. rewrite (Ad1 z); intros [U|U]; try specialize (Ab1 z U); auto; order.
right; split; auto.
rewrite (Ad1 x); auto.
exists y; repeat split; auto.
rewrite (Ad2 y); auto.
intros z. rewrite (Ad2 z). intros [U|U]; try specialize (Ab2 z U); auto; order.
Qed.
End MakeSetOrdering.
Module MakeListOrdering (O:OrderedType).
Module MO:=OrderedTypeFacts O.
Local Notation t := (list O.t).
Local Notation In := (InA O.eq).
Definition eq s s' := forall x, In x s <-> In x s'.
Instance eq_equiv : Equivalence eq := _.
Inductive lt_list : t -> t -> Prop :=
| lt_nil : forall x s, lt_list nil (x :: s)
| lt_cons_lt : forall x y s s',
O.lt x y -> lt_list (x :: s) (y :: s')
| lt_cons_eq : forall x y s s',
O.eq x y -> lt_list s s' -> lt_list (x :: s) (y :: s').
Hint Constructors lt_list.
Definition lt := lt_list.
Hint Unfold lt.
Instance lt_strorder : StrictOrder lt.
Proof.
split.
(* irreflexive *)
assert (forall s s', s=s' -> ~lt s s').
red; induction 2.
discriminate.
inversion H; subst.
apply (StrictOrder_Irreflexive y); auto.
inversion H; subst; auto.
intros s Hs; exact (H s s (eq_refl s) Hs).
(* transitive *)
intros s s' s'' H; generalize s''; clear s''; elim H.
intros x l s'' H'; inversion_clear H'; auto.
intros x x' l l' E s'' H'; inversion_clear H'; auto.
constructor 2. transitivity x'; auto.
constructor 2. rewrite <- H0; auto.
intros.
inversion_clear H3.
constructor 2. rewrite H0; auto.
constructor 3; auto. transitivity y; auto. unfold lt in *; auto.
Qed.
Instance lt_compat' :
Proper (eqlistA O.eq==>eqlistA O.eq==>iff) lt.
Proof.
apply proper_sym_impl_iff_2; auto with *.
intros s1 s1' E1 s2 s2' E2 H.
revert s1' E1 s2' E2.
induction H; intros; inversion_clear E1; inversion_clear E2.
constructor 1.
constructor 2. MO.order.
constructor 3. MO.order. unfold lt in *; auto.
Qed.
Lemma eq_cons :
forall l1 l2 x y,
O.eq x y -> eq l1 l2 -> eq (x :: l1) (y :: l2).
Proof.
unfold eq; intros l1 l2 x y Exy E12 z.
split; inversion_clear 1.
left; MO.order. right; rewrite <- E12; auto.
left; MO.order. right; rewrite E12; auto.
Qed.
Hint Resolve eq_cons.
Lemma cons_CompSpec : forall c x1 x2 l1 l2, O.eq x1 x2 ->
CompSpec eq lt l1 l2 c -> CompSpec eq lt (x1::l1) (x2::l2) c.
Proof.
destruct c; simpl; inversion_clear 2; auto with relations.
Qed.
Hint Resolve cons_CompSpec.
End MakeListOrdering.
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jorge Sequeira
//
// Create Date: 08/31/2016 03:34:58 PM
// Design Name:
// Module Name: KOA_c
// Project Name:
// Target Devices:
// Tool Versions:
// Description: Recursive Karasuba Parameterized Algorithm
//
// Dependencies:
//
// Revision:
// Revision 0.03 - File Created
// Additional Comments: La primera version de este modulo se puede encontrar en la misma carpeta madre.
// The reason for a second version is the way the numbers with lenght lower than 8 are treated. Here, we change that
// by using an at the start before the case, so a multiplier below l = 7 is never instatiated.
//
// Revision 0.04
//
// 1. Width of KOA multipliers in the even case was fixed from the original version
// 2. Zero padding in the adders was fixed.
// 3. Changed the adder-sub description
//////////////////////////////////////////////////////////////////////////////////
module KOA_c_2
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 54, parameter precision = 1)
(
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] sgf_result_o
);
wire [SW/2+1:0] result_A_adder;
wire [SW/2+1:0] result_B_adder;
wire [2*(SW/2)-1:0] Q_left;
wire [2*(SW/2+1)-1:0] Q_right;
wire [2*(SW/2+2)-1:0] Q_middle;
wire [2*(SW/2+2)-1:0] S_A;
wire [2*(SW/2+2)-1:0] S_B;
wire [4*(SW/2)+2:0] Result;
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 =2'b00;
assign zero2 =4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
wire [4*(SW/2)-1:0] sgf_r;
assign rightside1 = (SW/2) *1'b0;
assign rightside2 = (SW/2+1)*1'b0;
assign leftside1 = (SW/2-2) *1'b0; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = (SW/2-3)*1'b0;
localparam half = SW/2;
//localparam level1=4;
//localparam level2=5;
////////////////////////////////////
generate
if ((SW<=18) && (precision == 0)) begin
assign sgf_result_o = Data_A_i * Data_B_i;
end else if ((SW<=7) && (precision == 1)) begin
assign sgf_result_o = Data_A_i * Data_B_i;
end else begin
case (SW%2)
0:begin
//////////////////////////////////even//////////////////////////////////
//Multiplier for left side and right side
KOA_c_2 #(.SW(SW/2), .precision(precision) /*,.level(level1)*/) left(
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.sgf_result_o(/*result_left_mult*/Q_left)
);
KOA_c_2 #(.SW(SW/2), .precision(precision)/*,.level(level1)*/) right(
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.sgf_result_o(/*result_right_mult[2*(SW/2)-1:0]*/Q_right[2*(SW/2)-1:0])
);
//Adders for middle
adder #(.W(SW/2)) A_operation (
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder[SW/2:0])
);
adder #(.W(SW/2)) B_operation (
.Data_A_i(Data_B_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder[SW/2:0])
);
KOA_c_2 #(.SW(SW/2+1), .precision(precision)/*,.level(level1)*/) middle (
.Data_A_i(/*Q_result_A_adder[SW/2:0]*/result_A_adder[SW/2:0]),
.Data_B_i(/*Q_result_B_adder[SW/2:0]*/result_B_adder[SW/2:0]),
.sgf_result_o(/*result_middle_mult[2*(SW/2)+1:0]*/Q_middle[2*(SW/2)+1:0])
);
assign S_A[2*(SW/2)+1:0] = Q_middle[2*(SW/2)+1:0] - {zero1, Q_left};
assign S_B[2*(SW/2)+1:0] = S_A[2*(SW/2)+1:0] - {zero1, Q_right[2*(SW/2)-1:0]};
assign Result[4*(SW/2):0] = {Q_left,Q_right[2*(SW/2)-1:0]} + {leftside1,S_B[2*(SW/2)+1:0],rightside1};
//Final assignation
assign sgf_result_o = Result[2*SW-1:0];
end
1:begin
//////////////////////////////////odd//////////////////////////////////
//Multiplier for left side and right side
KOA_c_2 #(.SW(SW/2), .precision(precision)/*,.level(level2)*/) left_high(
.Data_A_i(Data_A_i[SW-1:SW/2+1]),
.Data_B_i(Data_B_i[SW-1:SW/2+1]),
.sgf_result_o(/*result_left_mult*/Q_left)
);
KOA_c_2 #(.SW((SW/2)+1), .precision(precision)/*,.level(level2)*/) right_lower(
/// Modificacion: Tamaño de puerto cambia de SW/2+1 a SW/2+2. El compilador lo pide por alguna razon.
.Data_A_i(Data_A_i[SW/2:0]),
.Data_B_i(Data_B_i[SW/2:0]),
.sgf_result_o(/*result_right_mult*/Q_right)
);
//Adders for middle
adder #(.W(SW/2+1)) A_operation (
.Data_A_i({1'b0,Data_A_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder)
);
adder #(.W(SW/2+1)) B_operation (
.Data_A_i({1'b0,Data_B_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder)
);
//multiplication for middle
KOA_c_2 #(.SW(SW/2+2), .precision(precision)/*,.level(level2)*/) middle (
.Data_A_i(/*Q_result_A_adder*/result_A_adder),
.Data_B_i(/*Q_result_B_adder*/result_B_adder),
.sgf_result_o(/*result_middle_mult*/Q_middle)
);
//segmentation registers array
assign S_A = Q_middle - Q_left;
assign S_B = S_A - Q_right;
assign Result[4*(SW/2)+2:0] = {Q_left,Q_right} - {leftside2,S_B,rightside2};
//Final assignation
assign sgf_result_o = Result[2*SW-1:0];
end
endcase
end
endgenerate
endmodule
|
/**
* bsg_cache_non_blocking_miss_fifo.v
*
* Special Miss FIFO
*
* @author tommy
*
*/
`include "bsg_defines.v"
module bsg_cache_non_blocking_miss_fifo
import bsg_cache_non_blocking_pkg::*;
#(parameter `BSG_INV_PARAM(width_p)
,parameter `BSG_INV_PARAM(els_p)
)
(
input clk_i
, input reset_i
, input [width_p-1:0] data_i
, input v_i
, output logic ready_o
, output logic v_o
, output logic [width_p-1:0] data_o
, input yumi_i
, input bsg_cache_non_blocking_miss_fifo_op_e yumi_op_i
, input scan_not_dq_i // SCAN or DEQUEUE mode
, output logic empty_o
, input rollback_i
);
// localparam
//
localparam lg_els_lp = `BSG_SAFE_CLOG2(els_p);
localparam rptr_inc_width_lp = $clog2(els_p);
// valid bits array
//
logic [els_p-1:0] valid_r, valid_n;
bsg_dff_reset #(
.width_p(els_p)
) valid_dff (
.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i(valid_n)
,.data_o(valid_r)
);
// read pointer
//
logic [rptr_inc_width_lp-1:0] rptr_inc;
logic [lg_els_lp-1:0] rptr_r, rptr_n;
bsg_circular_ptr #(
.slots_p(els_p)
,.max_add_p(els_p-1)
) read_ptr0 (
.clk(clk_i)
,.reset_i(reset_i)
,.add_i(rptr_inc)
,.o(rptr_r)
,.n_o(rptr_n)
);
wire [lg_els_lp-1:0] rptr_plus1 = (els_p-1 == rptr_r)
? (lg_els_lp)'(0)
: (lg_els_lp)'(rptr_r+1);
wire [lg_els_lp-1:0] rptr_plus2 = (els_p-1 == rptr_plus1)
? (lg_els_lp)'(0)
: (lg_els_lp)'(rptr_plus1+1);
// write pointer
//
logic wptr_inc;
logic [lg_els_lp-1:0] wptr_r;
bsg_circular_ptr #(
.slots_p(els_p)
,.max_add_p(1)
) write_ptr0 (
.clk(clk_i)
,.reset_i(reset_i)
,.add_i(wptr_inc)
,.o(wptr_r)
,.n_o()
);
// checkpoint pointer
//
logic cptr_inc;
logic [lg_els_lp-1:0] cptr_r;
bsg_circular_ptr #(
.slots_p(els_p)
,.max_add_p(1)
) cp_ptr0 (
.clk(clk_i)
,.reset_i(reset_i)
,.add_i(cptr_inc)
,.o(cptr_r)
,.n_o()
);
wire rptr_valid = valid_r[rptr_r];
wire rptr_plus1_valid = valid_r[rptr_plus1];
wire rptr_plus2_valid = valid_r[rptr_plus2];
wire cptr_valid = valid_r[cptr_r];
wire read_write_same_addr = (rptr_n == wptr_r);
// 1r1w mem
//
logic enque, deque;
logic mem_read_en;
logic [width_p-1:0] mem_data_lo;
logic [lg_els_lp-1:0] mem_read_addr;
bsg_mem_1r1w_sync #(
.width_p(width_p)
,.els_p(els_p)
,.harden_p(1)
,.read_write_same_addr_p(0)
,.disable_collision_warning_p(0)
) mem_1r1w (
.clk_i(clk_i)
,.reset_i(reset_i)
,.w_v_i(enque)
,.w_addr_i(wptr_r)
,.w_data_i(data_i)
,.r_v_i(mem_read_en)
,.r_addr_i(mem_read_addr)
,.r_data_o(mem_data_lo)
);
logic mem_read_en_r;
logic [lg_els_lp-1:0] mem_read_addr_r;
always_ff @ (posedge clk_i) begin
if (reset_i) begin
mem_read_en_r <= 1'b0;
mem_read_addr_r <= '0;
end
else begin
mem_read_en_r <= mem_read_en;
if (mem_read_en)
mem_read_addr_r <= mem_read_addr;
end
end
logic [width_p-1:0] data_r, data_n;
logic v_r, v_n;
always_ff @ (posedge clk_i) begin
if (reset_i) begin
data_r <= '0;
v_r <= 1'b0;
end
else begin
data_r <= data_n;
v_r <= v_n;
end
end
assign v_o = v_r;
assign data_o = data_r;
// next state logic for valid bit array
//
logic inval;
logic [els_p-1:0] inval_decode;
logic [els_p-1:0] enque_decode;
bsg_decode_with_v #(
.num_out_p(els_p)
) enque_dec (
.i(wptr_r)
,.v_i(enque)
,.o(enque_decode)
);
bsg_decode_with_v #(
.num_out_p(els_p)
) inval_dec (
.i(rptr_r)
,.v_i(inval)
,.o(inval_decode)
);
always_comb begin
for (integer i = 0; i < els_p; i++) begin
if (inval_decode[i])
valid_n[i] = 1'b0;
else if (enque_decode[i])
valid_n[i] = 1'b1;
else
valid_n[i] = valid_r[i];
end
end
// FIFO logic
//
logic enque_r;
logic deque_r;
always_ff @ (posedge clk_i) begin
if (reset_i) begin
enque_r <= 1'b0;
deque_r <= 1'b1;
end
else begin
if (cptr_inc | enque) begin
enque_r <= enque;
end
if (rollback_i) begin
deque_r <= ~cptr_valid;
end
else begin
if (enque | deque) begin
deque_r <= deque;
end
end
end
end
wire full = enque_r & (cptr_r == wptr_r);
wire empty = deque_r & (rptr_r == wptr_r);
assign empty_o = empty;
assign ready_o = ~full;
assign enque = ready_o & v_i;
assign wptr_inc = enque;
always_comb begin
if (rollback_i) begin
// only rollback when empty_o=1
deque = 1'b0;
cptr_inc = 1'b0;
inval = 1'b0;
rptr_inc = (cptr_r >= rptr_r)
? (rptr_inc_width_lp)'(cptr_r - rptr_r)
: (rptr_inc_width_lp)'(els_p + cptr_r - rptr_r);
mem_read_en = cptr_valid;
mem_read_addr = rptr_n;
v_n = v_r;
data_n = data_r;
end
else begin
// output valid
if (v_r) begin
// output taken
if (yumi_i) begin
mem_read_addr = ((rptr_n == mem_read_addr_r) & mem_read_en_r)
? rptr_plus2
: rptr_plus1;
mem_read_en = ~read_write_same_addr & ((rptr_n == mem_read_addr_r) & mem_read_en_r
? rptr_plus2_valid
: rptr_plus1_valid);
v_n = read_write_same_addr
? enque
: mem_read_en_r;
data_n = read_write_same_addr
? (enque ? data_i : data_r)
: (mem_read_en_r ? mem_data_lo : data_r);
case (yumi_op_i)
e_miss_fifo_dequeue: begin
deque = 1'b1;
inval = 1'b1;
cptr_inc = 1'b1;
rptr_inc = (rptr_inc_width_lp)'(1);
end
e_miss_fifo_skip: begin
deque = 1'b1;
inval = 1'b0;
cptr_inc = 1'b0;
rptr_inc = (rptr_inc_width_lp)'(1);
end
e_miss_fifo_invalidate: begin
deque = 1'b1;
inval = 1'b1;
cptr_inc = 1'b0;
rptr_inc = (rptr_inc_width_lp)'(1);
end
default: begin
// this should never happen.
deque = 1'b0;
inval = 1'b0;
cptr_inc = 1'b0;
rptr_inc = (rptr_inc_width_lp)'(0);
mem_read_en = 1'b0;
mem_read_addr = (lg_els_lp)'(0);
v_n = v_r;
data_n = data_r;
end
endcase
end
// output valid, but not taken.
else begin
deque = 1'b0;
inval = 1'b0;
cptr_inc = 1'b0;
rptr_inc = (rptr_inc_width_lp)'(0);
mem_read_en = rptr_plus1_valid;
mem_read_addr = rptr_plus1;
v_n = v_r;
data_n = data_r;
end
end
// output not valid.
else begin
deque = empty
? 1'b0
: ~rptr_valid;
inval = 1'b0;
cptr_inc = empty
? 1'b0
: (rptr_valid
? 1'b0
: ~scan_not_dq_i);
rptr_inc = empty
? (rptr_inc_width_lp)'(0)
: (rptr_valid
? 1'b0
: (rptr_inc_width_lp)'(1));
mem_read_en = mem_read_en_r
? rptr_plus1_valid
: rptr_valid;
mem_read_addr = mem_read_en_r
? rptr_plus1
: rptr_r;
v_n = empty
? enque
: mem_read_en_r;
data_n = empty
? (enque ? data_i : data_r)
: (mem_read_en_r ? mem_data_lo : data_r);
end
end
end
// synopsys translate_off
always_ff @ (negedge clk_i) begin
if (~reset_i) begin
if (rollback_i) assert(empty_o) else $error("[BSG_ERROR] rollback_i called when fifo is not empty_o.");
end
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_cache_non_blocking_miss_fifo)
|
module wb_intercon
(input wb_clk_i,
input wb_rst_i,
input [31:0] wb_dbg_adr_i,
input [31:0] wb_dbg_dat_i,
input [3:0] wb_dbg_sel_i,
input wb_dbg_we_i,
input wb_dbg_cyc_i,
input wb_dbg_stb_i,
input [2:0] wb_dbg_cti_i,
input [1:0] wb_dbg_bte_i,
output [31:0] wb_dbg_dat_o,
output wb_dbg_ack_o,
output wb_dbg_err_o,
output wb_dbg_rty_o,
input [31:0] wb_or1k_i_adr_i,
input [31:0] wb_or1k_i_dat_i,
input [3:0] wb_or1k_i_sel_i,
input wb_or1k_i_we_i,
input wb_or1k_i_cyc_i,
input wb_or1k_i_stb_i,
input [2:0] wb_or1k_i_cti_i,
input [1:0] wb_or1k_i_bte_i,
output [31:0] wb_or1k_i_dat_o,
output wb_or1k_i_ack_o,
output wb_or1k_i_err_o,
output wb_or1k_i_rty_o,
input [31:0] wb_or1k_d_adr_i,
input [31:0] wb_or1k_d_dat_i,
input [3:0] wb_or1k_d_sel_i,
input wb_or1k_d_we_i,
input wb_or1k_d_cyc_i,
input wb_or1k_d_stb_i,
input [2:0] wb_or1k_d_cti_i,
input [1:0] wb_or1k_d_bte_i,
output [31:0] wb_or1k_d_dat_o,
output wb_or1k_d_ack_o,
output wb_or1k_d_err_o,
output wb_or1k_d_rty_o,
output [31:0] wb_uart0_adr_o,
output [7:0] wb_uart0_dat_o,
output [3:0] wb_uart0_sel_o,
output wb_uart0_we_o,
output wb_uart0_cyc_o,
output wb_uart0_stb_o,
output [2:0] wb_uart0_cti_o,
output [1:0] wb_uart0_bte_o,
input [7:0] wb_uart0_dat_i,
input wb_uart0_ack_i,
input wb_uart0_err_i,
input wb_uart0_rty_i,
output [31:0] wb_sdram_dbus_adr_o,
output [31:0] wb_sdram_dbus_dat_o,
output [3:0] wb_sdram_dbus_sel_o,
output wb_sdram_dbus_we_o,
output wb_sdram_dbus_cyc_o,
output wb_sdram_dbus_stb_o,
output [2:0] wb_sdram_dbus_cti_o,
output [1:0] wb_sdram_dbus_bte_o,
input [31:0] wb_sdram_dbus_dat_i,
input wb_sdram_dbus_ack_i,
input wb_sdram_dbus_err_i,
input wb_sdram_dbus_rty_i,
output [31:0] wb_gpio0_adr_o,
output [7:0] wb_gpio0_dat_o,
output [3:0] wb_gpio0_sel_o,
output wb_gpio0_we_o,
output wb_gpio0_cyc_o,
output wb_gpio0_stb_o,
output [2:0] wb_gpio0_cti_o,
output [1:0] wb_gpio0_bte_o,
input [7:0] wb_gpio0_dat_i,
input wb_gpio0_ack_i,
input wb_gpio0_err_i,
input wb_gpio0_rty_i,
output [31:0] wb_rom0_adr_o,
output [31:0] wb_rom0_dat_o,
output [3:0] wb_rom0_sel_o,
output wb_rom0_we_o,
output wb_rom0_cyc_o,
output wb_rom0_stb_o,
output [2:0] wb_rom0_cti_o,
output [1:0] wb_rom0_bte_o,
input [31:0] wb_rom0_dat_i,
input wb_rom0_ack_i,
input wb_rom0_err_i,
input wb_rom0_rty_i,
output [31:0] wb_sdram_ibus_adr_o,
output [31:0] wb_sdram_ibus_dat_o,
output [3:0] wb_sdram_ibus_sel_o,
output wb_sdram_ibus_we_o,
output wb_sdram_ibus_cyc_o,
output wb_sdram_ibus_stb_o,
output [2:0] wb_sdram_ibus_cti_o,
output [1:0] wb_sdram_ibus_bte_o,
input [31:0] wb_sdram_ibus_dat_i,
input wb_sdram_ibus_ack_i,
input wb_sdram_ibus_err_i,
input wb_sdram_ibus_rty_i);
wire [31:0] wb_m2s_dbg_sdram_dbus_adr;
wire [31:0] wb_m2s_dbg_sdram_dbus_dat;
wire [3:0] wb_m2s_dbg_sdram_dbus_sel;
wire wb_m2s_dbg_sdram_dbus_we;
wire wb_m2s_dbg_sdram_dbus_cyc;
wire wb_m2s_dbg_sdram_dbus_stb;
wire [2:0] wb_m2s_dbg_sdram_dbus_cti;
wire [1:0] wb_m2s_dbg_sdram_dbus_bte;
wire [31:0] wb_s2m_dbg_sdram_dbus_dat;
wire wb_s2m_dbg_sdram_dbus_ack;
wire wb_s2m_dbg_sdram_dbus_err;
wire wb_s2m_dbg_sdram_dbus_rty;
wire [31:0] wb_m2s_dbg_uart0_adr;
wire [31:0] wb_m2s_dbg_uart0_dat;
wire [3:0] wb_m2s_dbg_uart0_sel;
wire wb_m2s_dbg_uart0_we;
wire wb_m2s_dbg_uart0_cyc;
wire wb_m2s_dbg_uart0_stb;
wire [2:0] wb_m2s_dbg_uart0_cti;
wire [1:0] wb_m2s_dbg_uart0_bte;
wire [31:0] wb_s2m_dbg_uart0_dat;
wire wb_s2m_dbg_uart0_ack;
wire wb_s2m_dbg_uart0_err;
wire wb_s2m_dbg_uart0_rty;
wire [31:0] wb_m2s_dbg_gpio0_adr;
wire [31:0] wb_m2s_dbg_gpio0_dat;
wire [3:0] wb_m2s_dbg_gpio0_sel;
wire wb_m2s_dbg_gpio0_we;
wire wb_m2s_dbg_gpio0_cyc;
wire wb_m2s_dbg_gpio0_stb;
wire [2:0] wb_m2s_dbg_gpio0_cti;
wire [1:0] wb_m2s_dbg_gpio0_bte;
wire [31:0] wb_s2m_dbg_gpio0_dat;
wire wb_s2m_dbg_gpio0_ack;
wire wb_s2m_dbg_gpio0_err;
wire wb_s2m_dbg_gpio0_rty;
wire [31:0] wb_m2s_or1k_d_sdram_dbus_adr;
wire [31:0] wb_m2s_or1k_d_sdram_dbus_dat;
wire [3:0] wb_m2s_or1k_d_sdram_dbus_sel;
wire wb_m2s_or1k_d_sdram_dbus_we;
wire wb_m2s_or1k_d_sdram_dbus_cyc;
wire wb_m2s_or1k_d_sdram_dbus_stb;
wire [2:0] wb_m2s_or1k_d_sdram_dbus_cti;
wire [1:0] wb_m2s_or1k_d_sdram_dbus_bte;
wire [31:0] wb_s2m_or1k_d_sdram_dbus_dat;
wire wb_s2m_or1k_d_sdram_dbus_ack;
wire wb_s2m_or1k_d_sdram_dbus_err;
wire wb_s2m_or1k_d_sdram_dbus_rty;
wire [31:0] wb_m2s_or1k_d_uart0_adr;
wire [31:0] wb_m2s_or1k_d_uart0_dat;
wire [3:0] wb_m2s_or1k_d_uart0_sel;
wire wb_m2s_or1k_d_uart0_we;
wire wb_m2s_or1k_d_uart0_cyc;
wire wb_m2s_or1k_d_uart0_stb;
wire [2:0] wb_m2s_or1k_d_uart0_cti;
wire [1:0] wb_m2s_or1k_d_uart0_bte;
wire [31:0] wb_s2m_or1k_d_uart0_dat;
wire wb_s2m_or1k_d_uart0_ack;
wire wb_s2m_or1k_d_uart0_err;
wire wb_s2m_or1k_d_uart0_rty;
wire [31:0] wb_m2s_or1k_d_gpio0_adr;
wire [31:0] wb_m2s_or1k_d_gpio0_dat;
wire [3:0] wb_m2s_or1k_d_gpio0_sel;
wire wb_m2s_or1k_d_gpio0_we;
wire wb_m2s_or1k_d_gpio0_cyc;
wire wb_m2s_or1k_d_gpio0_stb;
wire [2:0] wb_m2s_or1k_d_gpio0_cti;
wire [1:0] wb_m2s_or1k_d_gpio0_bte;
wire [31:0] wb_s2m_or1k_d_gpio0_dat;
wire wb_s2m_or1k_d_gpio0_ack;
wire wb_s2m_or1k_d_gpio0_err;
wire wb_s2m_or1k_d_gpio0_rty;
wire [31:0] wb_m2s_resize_uart0_adr;
wire [31:0] wb_m2s_resize_uart0_dat;
wire [3:0] wb_m2s_resize_uart0_sel;
wire wb_m2s_resize_uart0_we;
wire wb_m2s_resize_uart0_cyc;
wire wb_m2s_resize_uart0_stb;
wire [2:0] wb_m2s_resize_uart0_cti;
wire [1:0] wb_m2s_resize_uart0_bte;
wire [31:0] wb_s2m_resize_uart0_dat;
wire wb_s2m_resize_uart0_ack;
wire wb_s2m_resize_uart0_err;
wire wb_s2m_resize_uart0_rty;
wire [31:0] wb_m2s_resize_gpio0_adr;
wire [31:0] wb_m2s_resize_gpio0_dat;
wire [3:0] wb_m2s_resize_gpio0_sel;
wire wb_m2s_resize_gpio0_we;
wire wb_m2s_resize_gpio0_cyc;
wire wb_m2s_resize_gpio0_stb;
wire [2:0] wb_m2s_resize_gpio0_cti;
wire [1:0] wb_m2s_resize_gpio0_bte;
wire [31:0] wb_s2m_resize_gpio0_dat;
wire wb_s2m_resize_gpio0_ack;
wire wb_s2m_resize_gpio0_err;
wire wb_s2m_resize_gpio0_rty;
wb_mux
#(.num_slaves (3),
.MATCH_ADDR ({32'h00000000, 32'h90000000, 32'h91000000}),
.MATCH_MASK ({32'hfe000000, 32'hffffffe0, 32'hfffffffe}))
wb_mux_dbg
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i (wb_dbg_adr_i),
.wbm_dat_i (wb_dbg_dat_i),
.wbm_sel_i (wb_dbg_sel_i),
.wbm_we_i (wb_dbg_we_i),
.wbm_cyc_i (wb_dbg_cyc_i),
.wbm_stb_i (wb_dbg_stb_i),
.wbm_cti_i (wb_dbg_cti_i),
.wbm_bte_i (wb_dbg_bte_i),
.wbm_dat_o (wb_dbg_dat_o),
.wbm_ack_o (wb_dbg_ack_o),
.wbm_err_o (wb_dbg_err_o),
.wbm_rty_o (wb_dbg_rty_o),
.wbs_adr_o ({wb_m2s_dbg_sdram_dbus_adr, wb_m2s_dbg_uart0_adr, wb_m2s_dbg_gpio0_adr}),
.wbs_dat_o ({wb_m2s_dbg_sdram_dbus_dat, wb_m2s_dbg_uart0_dat, wb_m2s_dbg_gpio0_dat}),
.wbs_sel_o ({wb_m2s_dbg_sdram_dbus_sel, wb_m2s_dbg_uart0_sel, wb_m2s_dbg_gpio0_sel}),
.wbs_we_o ({wb_m2s_dbg_sdram_dbus_we, wb_m2s_dbg_uart0_we, wb_m2s_dbg_gpio0_we}),
.wbs_cyc_o ({wb_m2s_dbg_sdram_dbus_cyc, wb_m2s_dbg_uart0_cyc, wb_m2s_dbg_gpio0_cyc}),
.wbs_stb_o ({wb_m2s_dbg_sdram_dbus_stb, wb_m2s_dbg_uart0_stb, wb_m2s_dbg_gpio0_stb}),
.wbs_cti_o ({wb_m2s_dbg_sdram_dbus_cti, wb_m2s_dbg_uart0_cti, wb_m2s_dbg_gpio0_cti}),
.wbs_bte_o ({wb_m2s_dbg_sdram_dbus_bte, wb_m2s_dbg_uart0_bte, wb_m2s_dbg_gpio0_bte}),
.wbs_dat_i ({wb_s2m_dbg_sdram_dbus_dat, wb_s2m_dbg_uart0_dat, wb_s2m_dbg_gpio0_dat}),
.wbs_ack_i ({wb_s2m_dbg_sdram_dbus_ack, wb_s2m_dbg_uart0_ack, wb_s2m_dbg_gpio0_ack}),
.wbs_err_i ({wb_s2m_dbg_sdram_dbus_err, wb_s2m_dbg_uart0_err, wb_s2m_dbg_gpio0_err}),
.wbs_rty_i ({wb_s2m_dbg_sdram_dbus_rty, wb_s2m_dbg_uart0_rty, wb_s2m_dbg_gpio0_rty}));
wb_mux
#(.num_slaves (2),
.MATCH_ADDR ({32'h00000000, 32'hf0000100}),
.MATCH_MASK ({32'hfe000000, 32'hffffffc0}))
wb_mux_or1k_i
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i (wb_or1k_i_adr_i),
.wbm_dat_i (wb_or1k_i_dat_i),
.wbm_sel_i (wb_or1k_i_sel_i),
.wbm_we_i (wb_or1k_i_we_i),
.wbm_cyc_i (wb_or1k_i_cyc_i),
.wbm_stb_i (wb_or1k_i_stb_i),
.wbm_cti_i (wb_or1k_i_cti_i),
.wbm_bte_i (wb_or1k_i_bte_i),
.wbm_dat_o (wb_or1k_i_dat_o),
.wbm_ack_o (wb_or1k_i_ack_o),
.wbm_err_o (wb_or1k_i_err_o),
.wbm_rty_o (wb_or1k_i_rty_o),
.wbs_adr_o ({wb_sdram_ibus_adr_o, wb_rom0_adr_o}),
.wbs_dat_o ({wb_sdram_ibus_dat_o, wb_rom0_dat_o}),
.wbs_sel_o ({wb_sdram_ibus_sel_o, wb_rom0_sel_o}),
.wbs_we_o ({wb_sdram_ibus_we_o, wb_rom0_we_o}),
.wbs_cyc_o ({wb_sdram_ibus_cyc_o, wb_rom0_cyc_o}),
.wbs_stb_o ({wb_sdram_ibus_stb_o, wb_rom0_stb_o}),
.wbs_cti_o ({wb_sdram_ibus_cti_o, wb_rom0_cti_o}),
.wbs_bte_o ({wb_sdram_ibus_bte_o, wb_rom0_bte_o}),
.wbs_dat_i ({wb_sdram_ibus_dat_i, wb_rom0_dat_i}),
.wbs_ack_i ({wb_sdram_ibus_ack_i, wb_rom0_ack_i}),
.wbs_err_i ({wb_sdram_ibus_err_i, wb_rom0_err_i}),
.wbs_rty_i ({wb_sdram_ibus_rty_i, wb_rom0_rty_i}));
wb_mux
#(.num_slaves (3),
.MATCH_ADDR ({32'h00000000, 32'h90000000, 32'h91000000}),
.MATCH_MASK ({32'hfe000000, 32'hffffffe0, 32'hfffffffe}))
wb_mux_or1k_d
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i (wb_or1k_d_adr_i),
.wbm_dat_i (wb_or1k_d_dat_i),
.wbm_sel_i (wb_or1k_d_sel_i),
.wbm_we_i (wb_or1k_d_we_i),
.wbm_cyc_i (wb_or1k_d_cyc_i),
.wbm_stb_i (wb_or1k_d_stb_i),
.wbm_cti_i (wb_or1k_d_cti_i),
.wbm_bte_i (wb_or1k_d_bte_i),
.wbm_dat_o (wb_or1k_d_dat_o),
.wbm_ack_o (wb_or1k_d_ack_o),
.wbm_err_o (wb_or1k_d_err_o),
.wbm_rty_o (wb_or1k_d_rty_o),
.wbs_adr_o ({wb_m2s_or1k_d_sdram_dbus_adr, wb_m2s_or1k_d_uart0_adr, wb_m2s_or1k_d_gpio0_adr}),
.wbs_dat_o ({wb_m2s_or1k_d_sdram_dbus_dat, wb_m2s_or1k_d_uart0_dat, wb_m2s_or1k_d_gpio0_dat}),
.wbs_sel_o ({wb_m2s_or1k_d_sdram_dbus_sel, wb_m2s_or1k_d_uart0_sel, wb_m2s_or1k_d_gpio0_sel}),
.wbs_we_o ({wb_m2s_or1k_d_sdram_dbus_we, wb_m2s_or1k_d_uart0_we, wb_m2s_or1k_d_gpio0_we}),
.wbs_cyc_o ({wb_m2s_or1k_d_sdram_dbus_cyc, wb_m2s_or1k_d_uart0_cyc, wb_m2s_or1k_d_gpio0_cyc}),
.wbs_stb_o ({wb_m2s_or1k_d_sdram_dbus_stb, wb_m2s_or1k_d_uart0_stb, wb_m2s_or1k_d_gpio0_stb}),
.wbs_cti_o ({wb_m2s_or1k_d_sdram_dbus_cti, wb_m2s_or1k_d_uart0_cti, wb_m2s_or1k_d_gpio0_cti}),
.wbs_bte_o ({wb_m2s_or1k_d_sdram_dbus_bte, wb_m2s_or1k_d_uart0_bte, wb_m2s_or1k_d_gpio0_bte}),
.wbs_dat_i ({wb_s2m_or1k_d_sdram_dbus_dat, wb_s2m_or1k_d_uart0_dat, wb_s2m_or1k_d_gpio0_dat}),
.wbs_ack_i ({wb_s2m_or1k_d_sdram_dbus_ack, wb_s2m_or1k_d_uart0_ack, wb_s2m_or1k_d_gpio0_ack}),
.wbs_err_i ({wb_s2m_or1k_d_sdram_dbus_err, wb_s2m_or1k_d_uart0_err, wb_s2m_or1k_d_gpio0_err}),
.wbs_rty_i ({wb_s2m_or1k_d_sdram_dbus_rty, wb_s2m_or1k_d_uart0_rty, wb_s2m_or1k_d_gpio0_rty}));
wb_arbiter
#(.num_masters (2))
wb_arbiter_uart0
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i ({wb_m2s_or1k_d_uart0_adr, wb_m2s_dbg_uart0_adr}),
.wbm_dat_i ({wb_m2s_or1k_d_uart0_dat, wb_m2s_dbg_uart0_dat}),
.wbm_sel_i ({wb_m2s_or1k_d_uart0_sel, wb_m2s_dbg_uart0_sel}),
.wbm_we_i ({wb_m2s_or1k_d_uart0_we, wb_m2s_dbg_uart0_we}),
.wbm_cyc_i ({wb_m2s_or1k_d_uart0_cyc, wb_m2s_dbg_uart0_cyc}),
.wbm_stb_i ({wb_m2s_or1k_d_uart0_stb, wb_m2s_dbg_uart0_stb}),
.wbm_cti_i ({wb_m2s_or1k_d_uart0_cti, wb_m2s_dbg_uart0_cti}),
.wbm_bte_i ({wb_m2s_or1k_d_uart0_bte, wb_m2s_dbg_uart0_bte}),
.wbm_dat_o ({wb_s2m_or1k_d_uart0_dat, wb_s2m_dbg_uart0_dat}),
.wbm_ack_o ({wb_s2m_or1k_d_uart0_ack, wb_s2m_dbg_uart0_ack}),
.wbm_err_o ({wb_s2m_or1k_d_uart0_err, wb_s2m_dbg_uart0_err}),
.wbm_rty_o ({wb_s2m_or1k_d_uart0_rty, wb_s2m_dbg_uart0_rty}),
.wbs_adr_o (wb_m2s_resize_uart0_adr),
.wbs_dat_o (wb_m2s_resize_uart0_dat),
.wbs_sel_o (wb_m2s_resize_uart0_sel),
.wbs_we_o (wb_m2s_resize_uart0_we),
.wbs_cyc_o (wb_m2s_resize_uart0_cyc),
.wbs_stb_o (wb_m2s_resize_uart0_stb),
.wbs_cti_o (wb_m2s_resize_uart0_cti),
.wbs_bte_o (wb_m2s_resize_uart0_bte),
.wbs_dat_i (wb_s2m_resize_uart0_dat),
.wbs_ack_i (wb_s2m_resize_uart0_ack),
.wbs_err_i (wb_s2m_resize_uart0_err),
.wbs_rty_i (wb_s2m_resize_uart0_rty));
wb_data_resize
#(.aw (32),
.mdw (32),
.sdw (8))
wb_data_resize_uart0
(.wbm_adr_i (wb_m2s_resize_uart0_adr),
.wbm_dat_i (wb_m2s_resize_uart0_dat),
.wbm_sel_i (wb_m2s_resize_uart0_sel),
.wbm_we_i (wb_m2s_resize_uart0_we),
.wbm_cyc_i (wb_m2s_resize_uart0_cyc),
.wbm_stb_i (wb_m2s_resize_uart0_stb),
.wbm_cti_i (wb_m2s_resize_uart0_cti),
.wbm_bte_i (wb_m2s_resize_uart0_bte),
.wbm_dat_o (wb_s2m_resize_uart0_dat),
.wbm_ack_o (wb_s2m_resize_uart0_ack),
.wbm_err_o (wb_s2m_resize_uart0_err),
.wbm_rty_o (wb_s2m_resize_uart0_rty),
.wbs_adr_o (wb_uart0_adr_o),
.wbs_dat_o (wb_uart0_dat_o),
.wbs_we_o (wb_uart0_we_o),
.wbs_cyc_o (wb_uart0_cyc_o),
.wbs_stb_o (wb_uart0_stb_o),
.wbs_cti_o (wb_uart0_cti_o),
.wbs_bte_o (wb_uart0_bte_o),
.wbs_dat_i (wb_uart0_dat_i),
.wbs_ack_i (wb_uart0_ack_i),
.wbs_err_i (wb_uart0_err_i),
.wbs_rty_i (wb_uart0_rty_i));
wb_arbiter
#(.num_masters (2))
wb_arbiter_sdram_dbus
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i ({wb_m2s_or1k_d_sdram_dbus_adr, wb_m2s_dbg_sdram_dbus_adr}),
.wbm_dat_i ({wb_m2s_or1k_d_sdram_dbus_dat, wb_m2s_dbg_sdram_dbus_dat}),
.wbm_sel_i ({wb_m2s_or1k_d_sdram_dbus_sel, wb_m2s_dbg_sdram_dbus_sel}),
.wbm_we_i ({wb_m2s_or1k_d_sdram_dbus_we, wb_m2s_dbg_sdram_dbus_we}),
.wbm_cyc_i ({wb_m2s_or1k_d_sdram_dbus_cyc, wb_m2s_dbg_sdram_dbus_cyc}),
.wbm_stb_i ({wb_m2s_or1k_d_sdram_dbus_stb, wb_m2s_dbg_sdram_dbus_stb}),
.wbm_cti_i ({wb_m2s_or1k_d_sdram_dbus_cti, wb_m2s_dbg_sdram_dbus_cti}),
.wbm_bte_i ({wb_m2s_or1k_d_sdram_dbus_bte, wb_m2s_dbg_sdram_dbus_bte}),
.wbm_dat_o ({wb_s2m_or1k_d_sdram_dbus_dat, wb_s2m_dbg_sdram_dbus_dat}),
.wbm_ack_o ({wb_s2m_or1k_d_sdram_dbus_ack, wb_s2m_dbg_sdram_dbus_ack}),
.wbm_err_o ({wb_s2m_or1k_d_sdram_dbus_err, wb_s2m_dbg_sdram_dbus_err}),
.wbm_rty_o ({wb_s2m_or1k_d_sdram_dbus_rty, wb_s2m_dbg_sdram_dbus_rty}),
.wbs_adr_o (wb_sdram_dbus_adr_o),
.wbs_dat_o (wb_sdram_dbus_dat_o),
.wbs_sel_o (wb_sdram_dbus_sel_o),
.wbs_we_o (wb_sdram_dbus_we_o),
.wbs_cyc_o (wb_sdram_dbus_cyc_o),
.wbs_stb_o (wb_sdram_dbus_stb_o),
.wbs_cti_o (wb_sdram_dbus_cti_o),
.wbs_bte_o (wb_sdram_dbus_bte_o),
.wbs_dat_i (wb_sdram_dbus_dat_i),
.wbs_ack_i (wb_sdram_dbus_ack_i),
.wbs_err_i (wb_sdram_dbus_err_i),
.wbs_rty_i (wb_sdram_dbus_rty_i));
wb_arbiter
#(.num_masters (2))
wb_arbiter_gpio0
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i ({wb_m2s_or1k_d_gpio0_adr, wb_m2s_dbg_gpio0_adr}),
.wbm_dat_i ({wb_m2s_or1k_d_gpio0_dat, wb_m2s_dbg_gpio0_dat}),
.wbm_sel_i ({wb_m2s_or1k_d_gpio0_sel, wb_m2s_dbg_gpio0_sel}),
.wbm_we_i ({wb_m2s_or1k_d_gpio0_we, wb_m2s_dbg_gpio0_we}),
.wbm_cyc_i ({wb_m2s_or1k_d_gpio0_cyc, wb_m2s_dbg_gpio0_cyc}),
.wbm_stb_i ({wb_m2s_or1k_d_gpio0_stb, wb_m2s_dbg_gpio0_stb}),
.wbm_cti_i ({wb_m2s_or1k_d_gpio0_cti, wb_m2s_dbg_gpio0_cti}),
.wbm_bte_i ({wb_m2s_or1k_d_gpio0_bte, wb_m2s_dbg_gpio0_bte}),
.wbm_dat_o ({wb_s2m_or1k_d_gpio0_dat, wb_s2m_dbg_gpio0_dat}),
.wbm_ack_o ({wb_s2m_or1k_d_gpio0_ack, wb_s2m_dbg_gpio0_ack}),
.wbm_err_o ({wb_s2m_or1k_d_gpio0_err, wb_s2m_dbg_gpio0_err}),
.wbm_rty_o ({wb_s2m_or1k_d_gpio0_rty, wb_s2m_dbg_gpio0_rty}),
.wbs_adr_o (wb_m2s_resize_gpio0_adr),
.wbs_dat_o (wb_m2s_resize_gpio0_dat),
.wbs_sel_o (wb_m2s_resize_gpio0_sel),
.wbs_we_o (wb_m2s_resize_gpio0_we),
.wbs_cyc_o (wb_m2s_resize_gpio0_cyc),
.wbs_stb_o (wb_m2s_resize_gpio0_stb),
.wbs_cti_o (wb_m2s_resize_gpio0_cti),
.wbs_bte_o (wb_m2s_resize_gpio0_bte),
.wbs_dat_i (wb_s2m_resize_gpio0_dat),
.wbs_ack_i (wb_s2m_resize_gpio0_ack),
.wbs_err_i (wb_s2m_resize_gpio0_err),
.wbs_rty_i (wb_s2m_resize_gpio0_rty));
wb_data_resize
#(.aw (32),
.mdw (32),
.sdw (8))
wb_data_resize_gpio0
(.wbm_adr_i (wb_m2s_resize_gpio0_adr),
.wbm_dat_i (wb_m2s_resize_gpio0_dat),
.wbm_sel_i (wb_m2s_resize_gpio0_sel),
.wbm_we_i (wb_m2s_resize_gpio0_we),
.wbm_cyc_i (wb_m2s_resize_gpio0_cyc),
.wbm_stb_i (wb_m2s_resize_gpio0_stb),
.wbm_cti_i (wb_m2s_resize_gpio0_cti),
.wbm_bte_i (wb_m2s_resize_gpio0_bte),
.wbm_dat_o (wb_s2m_resize_gpio0_dat),
.wbm_ack_o (wb_s2m_resize_gpio0_ack),
.wbm_err_o (wb_s2m_resize_gpio0_err),
.wbm_rty_o (wb_s2m_resize_gpio0_rty),
.wbs_adr_o (wb_gpio0_adr_o),
.wbs_dat_o (wb_gpio0_dat_o),
.wbs_we_o (wb_gpio0_we_o),
.wbs_cyc_o (wb_gpio0_cyc_o),
.wbs_stb_o (wb_gpio0_stb_o),
.wbs_cti_o (wb_gpio0_cti_o),
.wbs_bte_o (wb_gpio0_bte_o),
.wbs_dat_i (wb_gpio0_dat_i),
.wbs_ack_i (wb_gpio0_ack_i),
.wbs_err_i (wb_gpio0_err_i),
.wbs_rty_i (wb_gpio0_rty_i));
endmodule
|
// -- (c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: N-deep SRL pipeline element with generic single-channel AXI interfaces.
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
// Structure:
// axic_srl_fifo
// ndeep_srl
// nto1_mux
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_data_fifo_v2_1_7_axic_srl_fifo #
(
parameter C_FAMILY = "none", // FPGA Family
parameter integer C_FIFO_WIDTH = 1, // Width of S_MESG/M_MESG.
parameter integer C_MAX_CTRL_FANOUT = 33, // Maximum number of mesg bits
// the control logic can be used
// on before the control logic
// needs to be replicated.
parameter integer C_FIFO_DEPTH_LOG = 2, // Depth of FIFO is 2**C_FIFO_DEPTH_LOG.
// The minimum size fifo generated is 4-deep.
parameter C_USE_FULL = 1 // Prevent overwrite by throttling S_READY.
)
(
input wire ACLK, // Clock
input wire ARESET, // Reset
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Input data
input wire S_VALID, // Input data valid
output wire S_READY, // Input data ready
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Output data
output wire M_VALID, // Output data valid
input wire M_READY // Output data ready
);
localparam P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG>1) ? C_FIFO_DEPTH_LOG : 2;
localparam P_EMPTY = {P_FIFO_DEPTH_LOG{1'b1}};
localparam P_ALMOSTEMPTY = {P_FIFO_DEPTH_LOG{1'b0}};
localparam P_ALMOSTFULL_TEMP = {P_EMPTY, 1'b0};
localparam P_ALMOSTFULL = P_ALMOSTFULL_TEMP[0+:P_FIFO_DEPTH_LOG];
localparam P_NUM_REPS = (((C_FIFO_WIDTH+1)%C_MAX_CTRL_FANOUT) == 0) ?
(C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT :
((C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT)+1;
(* syn_keep = "1" *) reg [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr;
(* syn_keep = "1" *) wire [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr_i;
genvar i;
genvar j;
reg M_VALID_i;
reg S_READY_i;
wire push; // FIFO push
wire pop; // FIFO pop
reg areset_d1; // Reset delay register
wire [C_FIFO_WIDTH-1:0] m_axi_mesg_i; // Intermediate SRL data
assign M_VALID = M_VALID_i;
assign S_READY = C_USE_FULL ? S_READY_i : 1'b1;
assign M_MESG = m_axi_mesg_i;
assign push = S_VALID & (C_USE_FULL ? S_READY_i : 1'b1);
assign pop = M_VALID_i & M_READY;
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
generate
//---------------------------------------------------------------------------
// Create count of number of elements in FIFOs
//---------------------------------------------------------------------------
for (i=0;i<P_NUM_REPS;i=i+1) begin : gen_rep
assign fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] =
push ? fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] + 1 :
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] - 1;
always @(posedge ACLK) begin
if (ARESET)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
{P_FIFO_DEPTH_LOG{1'b1}};
else if (push ^ pop)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i];
end
end
//---------------------------------------------------------------------------
// When FIFO is empty, reset master valid bit. When not empty set valid bit.
// When FIFO is full, reset slave ready bit. When not full set ready bit.
//---------------------------------------------------------------------------
always @(posedge ACLK) begin
if (ARESET) begin
M_VALID_i <= 1'b0;
end else if ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTEMPTY) && pop && ~push) begin
M_VALID_i <= 1'b0;
end else if (push) begin
M_VALID_i <= 1'b1;
end
end
always @(posedge ACLK) begin
if (ARESET) begin
S_READY_i <= 1'b0;
end else if (areset_d1) begin
S_READY_i <= 1'b1;
end else if (C_USE_FULL &&
((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTFULL) && push && ~pop)) begin
S_READY_i <= 1'b0;
end else if (C_USE_FULL && pop) begin
S_READY_i <= 1'b1;
end
end
//---------------------------------------------------------------------------
// Instantiate SRLs
//---------------------------------------------------------------------------
for (i=0;i<(C_FIFO_WIDTH/C_MAX_CTRL_FANOUT)+((C_FIFO_WIDTH%C_MAX_CTRL_FANOUT)>0);i=i+1) begin : gen_srls
for (j=0;((j<C_MAX_CTRL_FANOUT)&&(i*C_MAX_CTRL_FANOUT+j<C_FIFO_WIDTH));j=j+1) begin : gen_rep
axi_data_fifo_v2_1_7_ndeep_srl #
(
.C_FAMILY (C_FAMILY),
.C_A_WIDTH (P_FIFO_DEPTH_LOG)
)
srl_nx1
(
.CLK (ACLK),
.A (fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:
P_FIFO_DEPTH_LOG*(i)]),
.CE (push),
.D (S_MESG[i*C_MAX_CTRL_FANOUT+j]),
.Q (m_axi_mesg_i[i*C_MAX_CTRL_FANOUT+j])
);
end
end
endgenerate
endmodule
`default_nettype wire
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: fpu_cnt_lead0_lvl4.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////////////
//
// 4th level of lead 0 counters. Lead 0 count for 32 bits.
//
///////////////////////////////////////////////////////////////////////////////
module fpu_cnt_lead0_lvl4 (
din_31_16_eq_0,
din_31_24_eq_0,
lead0_16b_2_hi,
lead0_16b_1_hi,
lead0_16b_0_hi,
din_15_0_eq_0,
din_15_8_eq_0,
lead0_16b_2_lo,
lead0_16b_1_lo,
lead0_16b_0_lo,
din_31_0_eq_0,
lead0_32b_3,
lead0_32b_2,
lead0_32b_1,
lead0_32b_0
);
input din_31_16_eq_0; // data in[31:16] is zero
input din_31_24_eq_0; // data in[31:24] is zero
input lead0_16b_2_hi; // bit[2] of lead 0 count- din[31:16]
input lead0_16b_1_hi; // bit[1] of lead 0 count- din[31:16]
input lead0_16b_0_hi; // bit[0] of lead 0 count- din[31:16]
input din_15_0_eq_0; // data in[15:0] is zero
input din_15_8_eq_0; // data in[15:8] is zero
input lead0_16b_2_lo; // bit[2] of lead 0 count- din[15:0]
input lead0_16b_1_lo; // bit[1] of lead 0 count- din[15:0]
input lead0_16b_0_lo; // bit[0] of lead 0 count- din[15:0]
output din_31_0_eq_0; // data in[31:0] is zero
output lead0_32b_3; // bit[3] of lead 0 count
output lead0_32b_2; // bit[2] of lead 0 count
output lead0_32b_1; // bit[1] of lead 0 count
output lead0_32b_0; // bit[0] of lead 0 count
wire din_31_0_eq_0;
wire lead0_32b_3;
wire lead0_32b_2;
wire lead0_32b_1;
wire lead0_32b_0;
assign din_31_0_eq_0= din_15_0_eq_0 && din_31_16_eq_0;
assign lead0_32b_3= ((!din_31_16_eq_0) && din_31_24_eq_0)
|| (din_31_16_eq_0 && din_15_8_eq_0);
assign lead0_32b_2= ((!din_31_16_eq_0) && lead0_16b_2_hi)
|| (din_31_16_eq_0 && lead0_16b_2_lo);
assign lead0_32b_1= ((!din_31_16_eq_0) && lead0_16b_1_hi)
|| (din_31_16_eq_0 && lead0_16b_1_lo);
assign lead0_32b_0= ((!din_31_16_eq_0) && lead0_16b_0_hi)
|| (din_31_16_eq_0 && lead0_16b_0_lo);
endmodule
|
//------------------------------------------------------------------------------
// (c) Copyright 2013-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
// *********************************************************************************************************************
// IMPORTANT
// This helper block was chosen for exclusion from the IP core, and is therefore delivered within the example design.
// However, it is still customized for the chosen core configuration. If you wish to modify its behavior, refer to this
// core's Product Guide for possible guidance and be careful to understand the existing behavior and the effects of any
// modifications you may choose to make.
// *********************************************************************************************************************
(* DowngradeIPIdentifiedWarnings="yes" *)
module aurora_64b66b_25p4G_ultrascale_tx_userclk #(
parameter integer P_CONTENTS = 0,
parameter integer P_FREQ_RATIO_SOURCE_TO_USRCLK = 1,
parameter integer P_FREQ_RATIO_USRCLK_TO_USRCLK2 = 1
)(
input wire gtwiz_userclk_tx_srcclk_in,
input wire gtwiz_userclk_tx_reset_in,
output wire gtwiz_userclk_tx_usrclk_out,
output wire gtwiz_userclk_tx_usrclk2_out,
output reg gtwiz_userclk_tx_active_out = 1'b0
);
// -------------------------------------------------------------------------------------------------------------------
// Local parameters
// -------------------------------------------------------------------------------------------------------------------
// Convert integer parameters with known, limited legal range to a 3-bit local parameter values
localparam integer P_USRCLK_INT_DIV = P_FREQ_RATIO_SOURCE_TO_USRCLK - 1;
localparam [2:0] P_USRCLK_DIV = P_USRCLK_INT_DIV[2:0];
localparam integer P_USRCLK2_INT_DIV = (P_FREQ_RATIO_SOURCE_TO_USRCLK * P_FREQ_RATIO_USRCLK_TO_USRCLK2) - 1;
localparam [2:0] P_USRCLK2_DIV = P_USRCLK2_INT_DIV[2:0];
// -------------------------------------------------------------------------------------------------------------------
// Transmitter user clocking network conditional generation, based on parameter values in module instantiation
// -------------------------------------------------------------------------------------------------------------------
generate if (1) begin: gen_gtwiz_userclk_tx_main
// Use BUFG_GT instance(s) to drive TXUSRCLK and TXUSRCLK2, inferred for integral source to TXUSRCLK frequency ratio
if (P_CONTENTS == 0) begin
// Drive TXUSRCLK with BUFG_GT-buffered source clock, dividing the input by the integral source clock to TXUSRCLK
// frequency ratio
BUFG_GT bufg_gt_usrclk_inst (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (gtwiz_userclk_tx_reset_in),
.CLRMASK (1'b0),
.DIV (P_USRCLK_DIV),
.I (gtwiz_userclk_tx_srcclk_in),
.O (gtwiz_userclk_tx_usrclk_out)
);
// If TXUSRCLK and TXUSRCLK2 frequencies are identical, drive both from the same BUFG_GT. Otherwise, drive
// TXUSRCLK2 from a second BUFG_GT instance, dividing the source clock down to the TXUSRCLK2 frequency.
if (P_FREQ_RATIO_USRCLK_TO_USRCLK2 == 1)
assign gtwiz_userclk_tx_usrclk2_out = gtwiz_userclk_tx_usrclk_out;
else begin
BUFG_GT bufg_gt_usrclk2_inst (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (gtwiz_userclk_tx_reset_in),
.CLRMASK (1'b0),
.DIV (P_USRCLK2_DIV),
.I (gtwiz_userclk_tx_srcclk_in),
.O (gtwiz_userclk_tx_usrclk2_out)
);
end
// Indicate active helper block functionality when the BUFG_GT divider is not held in reset
always @(posedge gtwiz_userclk_tx_usrclk2_out, posedge gtwiz_userclk_tx_reset_in) begin
if (gtwiz_userclk_tx_reset_in)
gtwiz_userclk_tx_active_out <= 1'b0;
else
gtwiz_userclk_tx_active_out <= 1'b1;
end
end
end
endgenerate
endmodule
|
/******************************************************************************
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
*****************************************************************************
*
* Filename: blk_mem_gen_v8_3_5.v
*
* Description:
* This file is the Verilog behvarial model for the
* Block Memory Generator Core.
*
*****************************************************************************
* Author: Xilinx
*
* History: Jan 11, 2006 Initial revision
* Jun 11, 2007 Added independent register stages for
* Port A and Port B (IP1_Jm/v2.5)
* Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)
* Mar 13, 2008 Behavioral model optimizations
* April 07, 2009 : Added support for Spartan-6 and Virtex-6
* features, including the following:
* (i) error injection, detection and/or correction
* (ii) reset priority
* (iii) special reset behavior
*
*****************************************************************************/
`timescale 1ps/1ps
module STATE_LOGIC_v8_3 (O, I0, I1, I2, I3, I4, I5);
parameter INIT = 64'h0000000000000000;
input I0, I1, I2, I3, I4, I5;
output O;
reg O;
reg tmp;
always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin
tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5;
if ( tmp == 0 || tmp == 1)
O = INIT[{I5, I4, I3, I2, I1, I0}];
end
endmodule
module beh_vlog_muxf7_v8_3 (O, I0, I1, S);
output O;
reg O;
input I0, I1, S;
always @(I0 or I1 or S)
if (S)
O = I1;
else
O = I0;
endmodule
module beh_vlog_ff_clr_v8_3 (Q, C, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q<= 1'b0;
else
Q<= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_pre_v8_3 (Q, C, D, PRE);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, D, PRE;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (PRE)
Q <= 1'b1;
else
Q <= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_ce_clr_v8_3 (Q, C, CE, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CE, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q <= 1'b0;
else if (CE)
Q <= #FLOP_DELAY D;
endmodule
module write_netlist_v8_3
#(
parameter C_AXI_TYPE = 0
)
(
S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,
w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,
S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c
);
input S_ACLK;
input S_ARESETN;
input S_AXI_AWVALID;
input S_AXI_WVALID;
input S_AXI_BREADY;
input w_last_c;
input bready_timeout_c;
output aw_ready_r;
output S_AXI_WREADY;
output S_AXI_BVALID;
output S_AXI_WR_EN;
output addr_en_c;
output incr_addr_c;
output bvalid_c;
//-------------------------------------------------------------------------
//AXI LITE
//-------------------------------------------------------------------------
generate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm
wire w_ready_r_7;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSignal_bvalid_c;
wire NlwRenamedSignal_incr_addr_c;
wire present_state_FSM_FFd3_13;
wire present_state_FSM_FFd2_14;
wire present_state_FSM_FFd1_15;
wire present_state_FSM_FFd4_16;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd4_In1_21;
wire [0:0] Mmux_aw_ready_c ;
begin
assign
S_AXI_WREADY = w_ready_r_7,
S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,
S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,
incr_addr_c = NlwRenamedSignal_incr_addr_c,
bvalid_c = NlwRenamedSignal_bvalid_c;
assign NlwRenamedSignal_incr_addr_c = 1'b0;
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
aw_ready_r_2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
w_ready_r (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_7)
);
beh_vlog_ff_pre_v8_3 #(
.INIT (1'b1))
present_state_FSM_FFd4 (
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_16)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd3 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_13)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_15)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000055554440))
present_state_FSM_FFd3_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000088880800))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_AWVALID),
.I1 ( S_AXI_WVALID),
.I2 ( bready_timeout_c),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000AAAA2000))
Mmux_addr_en_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_WVALID),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( addr_en_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hF5F07570F5F05500))
Mmux_w_ready_c_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( w_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd3_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd1_15),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( present_state_FSM_FFd3_13),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSignal_bvalid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h2F0F27072F0F2200))
present_state_FSM_FFd4_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( present_state_FSM_FFd4_In1_21)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000F8))
present_state_FSM_FFd4_In2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_In1_21),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h7535753575305500))
Mmux_aw_ready_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_WVALID),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 ( present_state_FSM_FFd2_14),
.O ( Mmux_aw_ready_c[0])
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000F8))
Mmux_aw_ready_c_0_2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( Mmux_aw_ready_c[0]),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( aw_ready_c)
);
end
end
endgenerate
//---------------------------------------------------------------------
// AXI FULL
//---------------------------------------------------------------------
generate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm
wire w_ready_r_8;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSig_OI_bvalid_c;
wire present_state_FSM_FFd1_16;
wire present_state_FSM_FFd4_17;
wire present_state_FSM_FFd3_18;
wire present_state_FSM_FFd2_19;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd2_In1_24;
wire present_state_FSM_FFd4_In1_25;
wire N2;
wire N4;
begin
assign
S_AXI_WREADY = w_ready_r_8,
bvalid_c = NlwRenamedSig_OI_bvalid_c,
S_AXI_BVALID = 1'b0;
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
aw_ready_r_2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
w_ready_r
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_8)
);
beh_vlog_ff_pre_v8_3 #(
.INIT (1'b1))
present_state_FSM_FFd4
(
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_17)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd3
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_18)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_19)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd1
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_16)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000005540))
present_state_FSM_FFd3_In1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd4_17),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hBF3FBB33AF0FAA00))
Mmux_aw_ready_c_0_2
(
.I0 ( S_AXI_BREADY),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd1_16),
.I4 ( present_state_FSM_FFd4_17),
.I5 ( NlwRenamedSig_OI_bvalid_c),
.O ( aw_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hAAAAAAAA20000000))
Mmux_addr_en_c_0_1
(
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( S_AXI_WVALID),
.I4 ( w_last_c),
.I5 ( present_state_FSM_FFd4_17),
.O ( addr_en_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_19),
.I2 ( present_state_FSM_FFd3_18),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( S_AXI_WR_EN)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000002220))
Mmux_incr_addr_c_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( incr_addr_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000008880))
Mmux_aw_ready_c_0_11
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSig_OI_bvalid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000000000D5C0))
present_state_FSM_FFd2_In1
(
.I0 ( w_last_c),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In1_24)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hFFFFAAAA08AAAAAA))
present_state_FSM_FFd2_In2
(
.I0 ( present_state_FSM_FFd2_19),
.I1 ( S_AXI_AWVALID),
.I2 ( bready_timeout_c),
.I3 ( w_last_c),
.I4 ( S_AXI_WVALID),
.I5 ( present_state_FSM_FFd2_In1_24),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00C0004000C00000))
present_state_FSM_FFd4_In1
(
.I0 ( S_AXI_AWVALID),
.I1 ( w_last_c),
.I2 ( S_AXI_WVALID),
.I3 ( bready_timeout_c),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( present_state_FSM_FFd4_In1_25)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000FFFF88F8))
present_state_FSM_FFd4_In2
(
.I0 ( present_state_FSM_FFd1_16),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( S_AXI_AWVALID),
.I4 ( present_state_FSM_FFd4_In1_25),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000007))
Mmux_w_ready_c_0_SW0
(
.I0 ( w_last_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N2)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hFABAFABAFAAAF000))
Mmux_w_ready_c_0_Q
(
.I0 ( N2),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd4_17),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( w_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000008))
Mmux_aw_ready_c_0_11_SW0
(
.I0 ( bready_timeout_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N4)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1
(
.I0 ( w_last_c),
.I1 ( N4),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 ( present_state_FSM_FFd1_16),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
end
end
endgenerate
endmodule
module read_netlist_v8_3 #(
parameter C_AXI_TYPE = 1,
parameter C_ADDRB_WIDTH = 12
) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,
S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,
S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,
S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);
input S_AXI_R_LAST_INT;
input S_ACLK;
input S_ARESETN;
input S_AXI_ARVALID;
input S_AXI_RREADY;
output S_AXI_INCR_ADDR;
output S_AXI_ADDR_EN;
output S_AXI_SINGLE_TRANS;
output S_AXI_MUX_SEL;
output S_AXI_R_LAST;
output S_AXI_ARREADY;
output S_AXI_RLAST;
output S_AXI_RVALID;
output S_AXI_RD_EN;
input [7:0] S_AXI_ARLEN;
wire present_state_FSM_FFd1_13 ;
wire present_state_FSM_FFd2_14 ;
wire gaxi_full_sm_outstanding_read_r_15 ;
wire gaxi_full_sm_ar_ready_r_16 ;
wire gaxi_full_sm_r_last_r_17 ;
wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ;
wire gaxi_full_sm_r_valid_c ;
wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ;
wire gaxi_full_sm_ar_ready_c ;
wire gaxi_full_sm_outstanding_read_c ;
wire NlwRenamedSig_OI_S_AXI_R_LAST ;
wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ;
wire present_state_FSM_FFd2_In ;
wire present_state_FSM_FFd1_In ;
wire Mmux_S_AXI_R_LAST13 ;
wire N01 ;
wire N2 ;
wire Mmux_gaxi_full_sm_ar_ready_c11 ;
wire N4 ;
wire N8 ;
wire N9 ;
wire N10 ;
wire N11 ;
wire N12 ;
wire N13 ;
assign
S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,
S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,
S_AXI_RLAST = gaxi_full_sm_r_last_r_17,
S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
gaxi_full_sm_outstanding_read_r (
.C (S_ACLK),
.CLR(S_ARESETN),
.D(gaxi_full_sm_outstanding_read_c),
.Q(gaxi_full_sm_outstanding_read_r_15)
);
beh_vlog_ff_ce_clr_v8_3 #(
.INIT (1'b0))
gaxi_full_sm_r_valid_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (gaxi_full_sm_r_valid_c),
.Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
gaxi_full_sm_ar_ready_r (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (gaxi_full_sm_ar_ready_c),
.Q (gaxi_full_sm_ar_ready_r_16)
);
beh_vlog_ff_ce_clr_v8_3 #(
.INIT(1'b0))
gaxi_full_sm_r_last_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (NlwRenamedSig_OI_S_AXI_R_LAST),
.Q (gaxi_full_sm_r_last_r_17)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (present_state_FSM_FFd1_In),
.Q (present_state_FSM_FFd1_13)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000000000000B))
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (
.I0 ( S_AXI_RREADY),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000008))
Mmux_S_AXI_SINGLE_TRANS11 (
.I0 (S_AXI_ARVALID),
.I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_SINGLE_TRANS)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000004))
Mmux_S_AXI_ADDR_EN11 (
.I0 (present_state_FSM_FFd1_13),
.I1 (S_AXI_ARVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_ADDR_EN)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hECEE2022EEEE2022))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_ARVALID),
.I1 ( present_state_FSM_FFd1_13),
.I2 ( S_AXI_RREADY),
.I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000044440444))
Mmux_S_AXI_R_LAST131 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_RREADY),
.I5 (1'b0),
.O ( Mmux_S_AXI_R_LAST13)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h4000FFFF40004000))
Mmux_S_AXI_INCR_ADDR11 (
.I0 ( S_AXI_R_LAST_INT),
.I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( Mmux_S_AXI_R_LAST13),
.O ( S_AXI_INCR_ADDR)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000FE))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (
.I0 ( S_AXI_ARLEN[2]),
.I1 ( S_AXI_ARLEN[1]),
.I2 ( S_AXI_ARLEN[0]),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N01)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000001))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (
.I0 ( S_AXI_ARLEN[7]),
.I1 ( S_AXI_ARLEN[6]),
.I2 ( S_AXI_ARLEN[5]),
.I3 ( S_AXI_ARLEN[4]),
.I4 ( S_AXI_ARLEN[3]),
.I5 ( N01),
.O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000007))
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 ( 1'b0),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N2)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0020000002200200))
Mmux_gaxi_full_sm_outstanding_read_c1 (
.I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd1_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( gaxi_full_sm_outstanding_read_r_15),
.I5 ( N2),
.O ( gaxi_full_sm_outstanding_read_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000004555))
Mmux_gaxi_full_sm_ar_ready_c12 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( Mmux_gaxi_full_sm_ar_ready_c11)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000EF))
Mmux_S_AXI_R_LAST11_SW0 (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N4)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hFCAAFC0A00AA000A))
Mmux_S_AXI_R_LAST11 (
.I0 ( S_AXI_ARVALID),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( N4),
.I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.O ( gaxi_full_sm_r_valid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000AAAAAA08))
S_AXI_MUX_SEL1 (
.I0 (present_state_FSM_FFd1_13),
.I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (S_AXI_RREADY),
.I3 (present_state_FSM_FFd2_14),
.I4 (gaxi_full_sm_outstanding_read_r_15),
.I5 (1'b0),
.O (S_AXI_MUX_SEL)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hF3F3F755A2A2A200))
Mmux_S_AXI_RD_EN11 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 ( S_AXI_RREADY),
.I3 ( gaxi_full_sm_outstanding_read_r_15),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( S_AXI_ARVALID),
.O ( S_AXI_RD_EN)
);
beh_vlog_muxf7_v8_3 present_state_FSM_FFd1_In3 (
.I0 ( N8),
.I1 ( N9),
.S ( present_state_FSM_FFd1_13),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000005410F4F0))
present_state_FSM_FFd1_In3_F (
.I0 ( S_AXI_RREADY),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( S_AXI_ARVALID),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( 1'b0),
.O ( N8)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000072FF7272))
present_state_FSM_FFd1_In3_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N9)
);
beh_vlog_muxf7_v8_3 Mmux_gaxi_full_sm_ar_ready_c14 (
.I0 ( N10),
.I1 ( N11),
.S ( present_state_FSM_FFd1_13),
.O ( gaxi_full_sm_ar_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000FFFF88A8))
Mmux_gaxi_full_sm_ar_ready_c14_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( Mmux_gaxi_full_sm_ar_ready_c11),
.I5 ( 1'b0),
.O ( N10)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000008D008D8D))
Mmux_gaxi_full_sm_ar_ready_c14_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N11)
);
beh_vlog_muxf7_v8_3 Mmux_S_AXI_R_LAST1 (
.I0 ( N12),
.I1 ( N13),
.S ( present_state_FSM_FFd1_13),
.O ( NlwRenamedSig_OI_S_AXI_R_LAST)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000088088888))
Mmux_S_AXI_R_LAST1_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N12)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000E400E4E4))
Mmux_S_AXI_R_LAST1_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( S_AXI_R_LAST_INT),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N13)
);
endmodule
module blk_mem_axi_write_wrapper_beh_v8_3
# (
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface; 1: AXI Interface
parameter C_AXI_TYPE = 0, // 0: AXI Lite; 1: AXI Full;
parameter C_AXI_SLAVE_TYPE = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
parameter C_MEMORY_TYPE = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
parameter C_WRITE_DEPTH_A = 0,
parameter C_AXI_AWADDR_WIDTH = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_WDATA_WIDTH = 32,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
// AXI OUTSTANDING WRITES
parameter C_AXI_OS_WR = 2
)
(
// AXI Global Signals
input S_ACLK,
input S_ARESETN,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,
input [8-1:0] S_AXI_AWLEN,
input [2:0] S_AXI_AWSIZE,
input [1:0] S_AXI_AWBURST,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
input S_AXI_WVALID,
output S_AXI_WREADY,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,
output S_AXI_BVALID,
input S_AXI_BREADY,
// Signals for BMG interface
output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,
output S_AXI_WR_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:
((C_AXI_WDATA_WIDTH==16)?1:
((C_AXI_WDATA_WIDTH==32)?2:
((C_AXI_WDATA_WIDTH==64)?3:
((C_AXI_WDATA_WIDTH==128)?4:
((C_AXI_WDATA_WIDTH==256)?5:0))))));
wire bvalid_c ;
reg bready_timeout_c = 0;
wire [1:0] bvalid_rd_cnt_c;
reg bvalid_r = 0;
reg [2:0] bvalid_count_r = 0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;
reg [1:0] bvalid_wr_cnt_r = 0;
reg [1:0] bvalid_rd_cnt_r = 0;
wire w_last_c ;
wire addr_en_c ;
wire incr_addr_c ;
wire aw_ready_r ;
wire dec_alen_c ;
reg bvalid_d1_c = 0;
reg [7:0] awlen_cntr_r = 0;
reg [7:0] awlen_int = 0;
reg [1:0] awburst_int = 0;
integer total_bytes = 0;
integer wrap_boundary = 0;
integer wrap_base_addr = 0;
integer num_of_bytes_c = 0;
integer num_of_bytes_r = 0;
// Array to store BIDs
reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;
wire S_AXI_BVALID_axi_wr_fsm;
//-------------------------------------
//AXI WRITE FSM COMPONENT INSTANTIATION
//-------------------------------------
write_netlist_v8_3 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm
(
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
.S_AXI_AWVALID(S_AXI_AWVALID),
.aw_ready_r(aw_ready_r),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_WR_EN(S_AXI_WR_EN),
.w_last_c(w_last_c),
.bready_timeout_c(bready_timeout_c),
.addr_en_c(addr_en_c),
.incr_addr_c(incr_addr_c),
.bvalid_c(bvalid_c),
.S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm)
);
//Wrap Address boundary calculation
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);
total_bytes = (num_of_bytes_r)*(awlen_int+1);
wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);
wrap_boundary = wrap_base_addr+total_bytes;
end
//-------------------------------------------------------------------------
// BMG address generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awaddr_reg <= 0;
num_of_bytes_r <= 0;
awburst_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awaddr_reg <= #FLOP_DELAY S_AXI_AWADDR ;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);
end else if (incr_addr_c == 1'b1) begin
if (awburst_int == 2'b10) begin
if(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin
awaddr_reg <= wrap_base_addr;
end else begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end
end
end
assign S_AXI_AWADDR_OUT = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);
//-------------------------------------------------------------------------
// AXI wlast generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awlen_cntr_r <= 0;
awlen_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awlen_int <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
awlen_cntr_r <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
end else if (dec_alen_c == 1'b1) begin
awlen_cntr_r <= #FLOP_DELAY awlen_cntr_r - 1 ;
end
end
end
assign w_last_c = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;
assign dec_alen_c = (incr_addr_c | w_last_c);
//-------------------------------------------------------------------------
// Generation of bvalid counter for outstanding transactions
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_count_r <= 0;
end else begin
// bvalid_count_r generation
if (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r ;
end else if (bvalid_c == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r + 1 ;
end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r - 1 ;
end
end
end
//-------------------------------------------------------------------------
// Generation of bvalid when BID is used
//-------------------------------------------------------------------------
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
bvalid_d1_c <= 0;
end else begin
// Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
//external bvalid signal generation
if (bvalid_d1_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of bvalid when BID is not used
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
end else begin
//external bvalid signal generation
if (bvalid_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of Bready timeout
//-------------------------------------------------------------------------
always @(bvalid_count_r) begin
// bready_timeout_c generation
if(bvalid_count_r == C_AXI_OS_WR-1) begin
bready_timeout_c <= 1'b1;
end else begin
bready_timeout_c <= 1'b0;
end
end
//-------------------------------------------------------------------------
// Generation of BID
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_wr_cnt_r <= 0;
bvalid_rd_cnt_r <= 0;
end else begin
// STORE AWID IN AN ARRAY
if(bvalid_c == 1'b1) begin
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + 1;
end
// generate BID FROM AWID ARRAY
bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;
S_AXI_BID <= axi_bid_array[bvalid_rd_cnt_c];
end
end
assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;
//-------------------------------------------------------------------------
// Storing AWID for generation of BID
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if(S_ARESETN == 1'b1) begin
axi_bid_array[0] = 0;
axi_bid_array[1] = 0;
axi_bid_array[2] = 0;
axi_bid_array[3] = 0;
end else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin
axi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;
end
end
end
endgenerate
assign S_AXI_BVALID = bvalid_r;
assign S_AXI_AWREADY = aw_ready_r;
endmodule
module blk_mem_axi_read_wrapper_beh_v8_3
# (
//// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_WRITE_WIDTH_A = 4,
parameter C_WRITE_DEPTH_A = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_PIPELINE_STAGES = 0,
parameter C_AXI_ARADDR_WIDTH = 12,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_ADDRB_WIDTH = 12
)
(
//// AXI Global Signals
input S_ACLK,
input S_ARESETN,
//// AXI Full/Lite Slave Read (Read side)
input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,
input [7:0] S_AXI_ARLEN,
input [2:0] S_AXI_ARSIZE,
input [1:0] S_AXI_ARBURST,
input S_AXI_ARVALID,
output S_AXI_ARREADY,
output S_AXI_RLAST,
output S_AXI_RVALID,
input S_AXI_RREADY,
input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,
//// AXI Full/Lite Read Address Signals to BRAM
output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,
output S_AXI_RD_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:
((C_WRITE_WIDTH_A==16)?1:
((C_WRITE_WIDTH_A==32)?2:
((C_WRITE_WIDTH_A==64)?3:
((C_WRITE_WIDTH_A==128)?4:
((C_WRITE_WIDTH_A==256)?5:0))))));
reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;
wire addr_en_c;
wire rd_en_c;
wire incr_addr_c;
wire single_trans_c;
wire dec_alen_c;
wire mux_sel_c;
wire r_last_c;
wire r_last_int_c;
wire [C_ADDRB_WIDTH-1 : 0] araddr_out;
reg [7:0] arlen_int_r=0;
reg [7:0] arlen_cntr=8'h01;
reg [1:0] arburst_int_c=0;
reg [1:0] arburst_int_r=0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;
integer num_of_bytes_c = 0;
integer total_bytes = 0;
integer num_of_bytes_r = 0;
integer wrap_base_addr_r = 0;
integer wrap_boundary_r = 0;
reg [7:0] arlen_int_c=0;
integer total_bytes_c = 0;
integer wrap_base_addr_c = 0;
integer wrap_boundary_c = 0;
assign dec_alen_c = incr_addr_c | r_last_int_c;
read_netlist_v8_3
#(.C_AXI_TYPE (1),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_read_fsm (
.S_AXI_INCR_ADDR(incr_addr_c),
.S_AXI_ADDR_EN(addr_en_c),
.S_AXI_SINGLE_TRANS(single_trans_c),
.S_AXI_MUX_SEL(mux_sel_c),
.S_AXI_R_LAST(r_last_c),
.S_AXI_R_LAST_INT(r_last_int_c),
//// AXI Global Signals
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
//// AXI Full/Lite Slave Read (Read side)
.S_AXI_ARLEN(S_AXI_ARLEN),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RLAST(S_AXI_RLAST),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY),
//// AXI Full/Lite Read Address Signals to BRAM
.S_AXI_RD_EN(rd_en_c)
);
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);
total_bytes = (num_of_bytes_r)*(arlen_int_r+1);
wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);
wrap_boundary_r = wrap_base_addr_r+total_bytes;
//////// combinatorial from interface
arlen_int_c = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);
total_bytes_c = (num_of_bytes_c)*(arlen_int_c+1);
wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);
wrap_boundary_c = wrap_base_addr_c+total_bytes_c;
arburst_int_c = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);
end
////-------------------------------------------------------------------------
//// BMG address generation
////-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
araddr_reg <= 0;
arburst_int_r <= 0;
num_of_bytes_r <= 0;
end else begin
if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
if (arburst_int_c == 2'b10) begin
if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin
araddr_reg <= wrap_base_addr_c;
end else begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (addr_en_c == 1'b1) begin
araddr_reg <= S_AXI_ARADDR;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
end else if (incr_addr_c == 1'b1) begin
if (arburst_int_r == 2'b10) begin
if(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin
araddr_reg <= wrap_base_addr_r;
end else begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end
end
end
assign araddr_out = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);
////-----------------------------------------------------------------------
//// Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
////-----------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
arlen_cntr <= 8'h01;
arlen_int_r <= 0;
end else begin
if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= S_AXI_ARLEN - 1'b1;
end else if (addr_en_c == 1'b1) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
end else if (dec_alen_c == 1'b1) begin
arlen_cntr <= arlen_cntr - 1'b1 ;
end
else begin
arlen_cntr <= arlen_cntr;
end
end
end
assign r_last_int_c = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;
////------------------------------------------------------------------------
//// AXI FULL FSM
//// Mux Selection of ARADDR
//// ARADDR is driven out from the read fsm based on the mux_sel_c
//// Based on mux_sel either ARADDR is given out or the latched ARADDR is
//// given out to BRAM
////------------------------------------------------------------------------
assign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;
////------------------------------------------------------------------------
//// Assign output signals - AXI FULL FSM
////------------------------------------------------------------------------
assign S_AXI_RD_EN = rd_en_c;
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
S_AXI_RID <= 0;
ar_id_r <= 0;
end else begin
if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin
ar_id_r <= S_AXI_ARID;
end else if (rd_en_c == 1'b1) begin
S_AXI_RID <= ar_id_r;
end
end
end
end
endgenerate
endmodule
module blk_mem_axi_regs_fwd_v8_3
#(parameter C_DATA_WIDTH = 8
)(
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
wire S_READY_I;
reg M_VALID_I;
reg [1:0] ARESET_D;
//assign local signal to its output signal
assign S_READY = S_READY_I;
assign M_VALID = M_VALID_I;
always @(posedge ACLK) begin
ARESET_D <= {ARESET_D[0], ARESET};
end
//Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK or ARESET) begin
if (ARESET == 1'b1) begin
STORAGE_DATA <= 0;
end else begin
if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin
STORAGE_DATA <= S_PAYLOAD_DATA;
end
end
end
always @(posedge ACLK) begin
M_PAYLOAD_DATA = STORAGE_DATA;
end
//M_Valid set to high when we have a completed transfer on slave side
//Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK or ARESET_D) begin
if (ARESET_D != 2'b00) begin
M_VALID_I <= 1'b0;
end else begin
if (S_VALID == 1'b1) begin
//Always set M_VALID_I when slave side is valid
M_VALID_I <= 1'b1;
end else if (M_READY == 1'b1 ) begin
//Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= 1'b0;
end
end
end
//Slave Ready is either when Master side drives M_READY or we have space in our storage data
assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));
endmodule
//*****************************************************************************
// Output Register Stage module
//
// This module builds the output register stages of the memory. This module is
// instantiated in the main memory module (blk_mem_gen_v8_3_5) which is
// declared/implemented further down in this file.
//*****************************************************************************
module blk_mem_gen_v8_3_5_output_stage
#(parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RST = 0,
parameter C_RSTRAM = 0,
parameter C_RST_PRIORITY = "CE",
parameter C_INIT_VAL = "0",
parameter C_HAS_EN = 0,
parameter C_HAS_REGCE = 0,
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_MEM_OUTPUT_REGS = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter NUM_STAGES = 1,
parameter C_EN_ECC_PIPE = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input RST,
input EN,
input REGCE,
input [C_DATA_WIDTH-1:0] DIN_I,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN_I,
input DBITERR_IN_I,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN_I,
input ECCPIPECE,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RST : Determines the presence of the RST port
// C_RSTRAM : Determines if special reset behavior is used
// C_RST_PRIORITY : Determines the priority between CE and SR
// C_INIT_VAL : Initialization value
// C_HAS_EN : Determines the presence of the EN port
// C_HAS_REGCE : Determines the presence of the REGCE port
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// NUM_STAGES : Determines the number of output stages
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// RST : Reset input to reset memory outputs to a user-defined
// reset state
// EN : Enable all read and write operations
// REGCE : Register Clock Enable to control each pipeline output
// register stages
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
// Fix for CR-509792
localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;
// Declare the pipeline registers
// (includes mem output reg, mux pipeline stages, and mux output reg)
reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;
reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;
reg [REG_STAGES-1:0] sbiterr_regs;
reg [REG_STAGES-1:0] dbiterr_regs;
reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL;
reg [C_DATA_WIDTH-1:0] init_val ;
//*********************************************
// Wire off optional inputs based on parameters
//*********************************************
wire en_i;
wire regce_i;
wire rst_i;
// Internal signals
reg [C_DATA_WIDTH-1:0] DIN;
reg [C_ADDRB_WIDTH-1:0] RDADDRECC_IN;
reg SBITERR_IN;
reg DBITERR_IN;
// Internal enable for output registers is tied to user EN or '1' depending
// on parameters
assign en_i = (C_HAS_EN==0 || EN);
// Internal register enable for output registers is tied to user REGCE, EN or
// '1' depending on parameters
// For V4 ECC, REGCE is always 1
// Virtex-4 ECC Not Yet Supported
assign regce_i = ((C_HAS_REGCE==1) && REGCE) ||
((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));
//Internal SRR is tied to user RST or '0' depending on parameters
assign rst_i = (C_HAS_RST==1) && RST;
//****************************************************
// Power on: load up the output registers and latches
//****************************************************
initial begin
if (!($sscanf(init_str, "%h", init_val))) begin
init_val = 0;
end
DOUT = init_val;
RDADDRECC = 0;
SBITERR = 1'b0;
DBITERR = 1'b0;
DIN = {(C_DATA_WIDTH){1'b0}};
RDADDRECC_IN = 0;
SBITERR_IN = 0;
DBITERR_IN = 0;
// This will be one wider than need, but 0 is an error
out_regs = {(REG_STAGES+1){init_val}};
rdaddrecc_regs = 0;
sbiterr_regs = {(REG_STAGES+1){1'b0}};
dbiterr_regs = {(REG_STAGES+1){1'b0}};
end
//***********************************************
// NUM_STAGES = 0 (No output registers. RAM only)
//***********************************************
generate if (NUM_STAGES == 0) begin : zero_stages
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg
always @* begin
DIN = DIN_I;
SBITERR_IN = SBITERR_IN_I;
DBITERR_IN = DBITERR_IN_I;
RDADDRECC_IN = RDADDRECC_IN_I;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg
always @(posedge CLK) begin
if(ECCPIPECE == 1) begin
DIN <= #FLOP_DELAY DIN_I;
SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;
DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;
RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;
end
end
end
endgenerate
//***********************************************
// NUM_STAGES = 1
// (Mem Output Reg only or Mux Output Reg only)
//***********************************************
// Possible valid combinations:
// Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
// +-----------------------------------------+
// | C_RSTRAM_* | Reset Behavior |
// +----------------+------------------------+
// | 0 | Normal Behavior |
// +----------------+------------------------+
// | 1 | Special Behavior |
// +----------------+------------------------+
//
// Normal = REGCE gates reset, as in the case of all families except S3ADSP.
// Special = EN gates reset, as in the case of S3ADSP.
generate if (NUM_STAGES == 1 &&
(C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != "spartan3adsp" && C_XDEVICEFAMILY != "aspartan3adsp" )) ||
C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))
begin : one_stages_norm
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end //end Priority conditions
end //end RST Type conditions
end //end one_stages_norm generate statement
endgenerate
// Special Reset Behavior for S3ADSP
generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY =="spartan3adsp" || C_XDEVICEFAMILY =="aspartan3adsp"))
begin : one_stage_splbhv
always @(posedge CLK) begin
if (en_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
end else if (regce_i && !rst_i) begin
DOUT <= #FLOP_DELAY DIN;
end //Output signal assignments
end //end CLK
end //end one_stage_splbhv generate statement
endgenerate
//************************************************************
// NUM_STAGES > 1
// Mem Output Reg + Mux Output Reg
// or
// Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
// or
// Mux Pipeline Stages (>0) + Mux Output Reg
//*************************************************************
generate if (NUM_STAGES > 1) begin : multi_stage
//Asynchronous Reset
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end //end Priority conditions
// Shift the data through the output stages
if (en_i) begin
out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;
rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;
sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;
dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;
end
end //end CLK
end //end multi_stage generate statement
endgenerate
endmodule
module blk_mem_gen_v8_3_5_softecc_output_reg_stage
#(parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input [C_DATA_WIDTH-1:0] DIN,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
reg [C_DATA_WIDTH-1:0] dout_i = 0;
reg sbiterr_i = 0;
reg dbiterr_i = 0;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;
//***********************************************
// NO OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// WITH OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage
always @(posedge CLK) begin
dout_i <= #FLOP_DELAY DIN;
rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;
sbiterr_i <= #FLOP_DELAY SBITERR_IN;
dbiterr_i <= #FLOP_DELAY DBITERR_IN;
end
always @* begin
DOUT = dout_i;
RDADDRECC = rdaddrecc_i;
SBITERR = sbiterr_i;
DBITERR = dbiterr_i;
end //end always
end //end in_or_out_stage generate statement
endgenerate
endmodule
//*****************************************************************************
// Main Memory module
//
// This module is the top-level behavioral model and this implements the RAM
//*****************************************************************************
module blk_mem_gen_v8_3_5_mem_module
#(parameter C_CORENAME = "blk_mem_gen_v8_3_5",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter FLOP_DELAY = 100,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_DISABLE_WARN_BHV_RANGE = 0
)
(input CLKA,
input RSTA,
input ENA,
input REGCEA,
input [C_WEA_WIDTH-1:0] WEA,
input [C_ADDRA_WIDTH-1:0] ADDRA,
input [C_WRITE_WIDTH_A-1:0] DINA,
output [C_READ_WIDTH_A-1:0] DOUTA,
input CLKB,
input RSTB,
input ENB,
input REGCEB,
input [C_WEB_WIDTH-1:0] WEB,
input [C_ADDRB_WIDTH-1:0] ADDRB,
input [C_WRITE_WIDTH_B-1:0] DINB,
output [C_READ_WIDTH_B-1:0] DOUTB,
input INJECTSBITERR,
input INJECTDBITERR,
input ECCPIPECE,
input SLEEP,
output SBITERR,
output DBITERR,
output [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
// Note: C_CORENAME parameter is hard-coded to "blk_mem_gen_v8_3_5" and it is
// only used by this module to print warning messages. It is neither passed
// down from blk_mem_gen_v8_3_5_xst.v nor present in the instantiation template
// coregen generates
//***************************************************************************
// constants for the core behavior
//***************************************************************************
// file handles for logging
//--------------------------------------------------
localparam ADDRFILE = 32'h8000_0001; //stdout for addr out of range
localparam COLLFILE = 32'h8000_0001; //stdout for coll detection
localparam ERRFILE = 32'h8000_0001; //stdout for file I/O errors
// other constants
//--------------------------------------------------
localparam COLL_DELAY = 100; // 100 ps
// locally derived parameters to determine memory shape
//-----------------------------------------------------
localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0)))));
localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?
C_WRITE_WIDTH_A : C_READ_WIDTH_A;
localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?
C_WRITE_WIDTH_B : C_READ_WIDTH_B;
localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?
MIN_WIDTH_A : MIN_WIDTH_B;
localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?
C_WRITE_DEPTH_A : C_READ_DEPTH_A;
localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?
C_WRITE_DEPTH_B : C_READ_DEPTH_B;
localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?
MAX_DEPTH_A : MAX_DEPTH_B;
// locally derived parameters to assist memory access
//----------------------------------------------------
// Calculate the width ratios of each port with respect to the narrowest
// port
localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;
localparam READ_WIDTH_RATIO_A = C_READ_WIDTH_A/MIN_WIDTH;
localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;
localparam READ_WIDTH_RATIO_B = C_READ_WIDTH_B/MIN_WIDTH;
// To modify the LSBs of the 'wider' data to the actual
// address value
//----------------------------------------------------
localparam WRITE_ADDR_A_DIV = C_WRITE_WIDTH_A/MIN_WIDTH_A;
localparam READ_ADDR_A_DIV = C_READ_WIDTH_A/MIN_WIDTH_A;
localparam WRITE_ADDR_B_DIV = C_WRITE_WIDTH_B/MIN_WIDTH_B;
localparam READ_ADDR_B_DIV = C_READ_WIDTH_B/MIN_WIDTH_B;
// If byte writes aren't being used, make sure BYTE_SIZE is not
// wider than the memory elements to avoid compilation warnings
localparam BYTE_SIZE = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;
// The memory
reg [MIN_WIDTH-1:0] memory [0:MAX_DEPTH-1];
reg [MIN_WIDTH-1:0] temp_mem_array [0:MAX_DEPTH-1];
reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;
// ECC error arrays
reg sbiterr_arr [0:MAX_DEPTH-1];
reg dbiterr_arr [0:MAX_DEPTH-1];
reg softecc_sbiterr_arr [0:MAX_DEPTH-1];
reg softecc_dbiterr_arr [0:MAX_DEPTH-1];
// Memory output 'latches'
reg [C_READ_WIDTH_A-1:0] memory_out_a;
reg [C_READ_WIDTH_B-1:0] memory_out_b;
// ECC error inputs and outputs from output_stage module:
reg sbiterr_in;
wire sbiterr_sdp;
reg dbiterr_in;
wire dbiterr_sdp;
wire [C_READ_WIDTH_B-1:0] dout_i;
wire dbiterr_i;
wire sbiterr_i;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_i;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_in;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sdp;
// Reset values
reg [C_READ_WIDTH_A-1:0] inita_val;
reg [C_READ_WIDTH_B-1:0] initb_val;
// Collision detect
reg is_collision;
reg is_collision_a, is_collision_delay_a;
reg is_collision_b, is_collision_delay_b;
// Temporary variables for initialization
//---------------------------------------
integer status;
integer initfile;
integer meminitfile;
// data input buffer
reg [C_WRITE_WIDTH_A-1:0] mif_data;
reg [C_WRITE_WIDTH_A-1:0] mem_data;
// string values in hex
reg [C_READ_WIDTH_A*8-1:0] inita_str = C_INITA_VAL;
reg [C_READ_WIDTH_B*8-1:0] initb_str = C_INITB_VAL;
reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA;
// initialization filename
reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME;
reg [1023*8-1:0] mem_init_file_str = C_INIT_FILE;
//Constants used to calculate the effective address widths for each of the
//four ports.
integer cnt = 1;
integer write_addr_a_width, read_addr_a_width;
integer write_addr_b_width, read_addr_b_width;
localparam C_FAMILY_LOCALPARAM = (C_FAMILY=="zynquplus"?"virtex7":(C_FAMILY=="kintexuplus"?"virtex7":(C_FAMILY=="virtexuplus"?"virtex7":(C_FAMILY=="virtexu"?"virtex7":(C_FAMILY=="kintexu" ? "virtex7":(C_FAMILY=="virtex7" ? "virtex7" : (C_FAMILY=="virtex7l" ? "virtex7" : (C_FAMILY=="qvirtex7" ? "virtex7" : (C_FAMILY=="qvirtex7l" ? "virtex7" : (C_FAMILY=="kintex7" ? "virtex7" : (C_FAMILY=="kintex7l" ? "virtex7" : (C_FAMILY=="qkintex7" ? "virtex7" : (C_FAMILY=="qkintex7l" ? "virtex7" : (C_FAMILY=="artix7" ? "virtex7" : (C_FAMILY=="artix7l" ? "virtex7" : (C_FAMILY=="qartix7" ? "virtex7" : (C_FAMILY=="qartix7l" ? "virtex7" : (C_FAMILY=="aartix7" ? "virtex7" : (C_FAMILY=="zynq" ? "virtex7" : (C_FAMILY=="azynq" ? "virtex7" : (C_FAMILY=="qzynq" ? "virtex7" : C_FAMILY)))))))))))))))))))));
// Internal configuration parameters
//---------------------------------------------
localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);
localparam IS_ROM = (C_MEM_TYPE==3 || C_MEM_TYPE==4);
localparam HAS_A_WRITE = (!IS_ROM);
localparam HAS_B_WRITE = (C_MEM_TYPE==2);
localparam HAS_A_READ = (C_MEM_TYPE!=1);
localparam HAS_B_READ = (!SINGLE_PORT);
localparam HAS_B_PORT = (HAS_B_READ || HAS_B_WRITE);
// Calculate the mux pipeline register stages for Port A and Port B
//------------------------------------------------------------------
localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?
C_MUX_PIPELINE_STAGES : 0;
localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?
C_MUX_PIPELINE_STAGES : 0;
// Calculate total number of register stages in the core
// -----------------------------------------------------
localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);
localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);
wire ena_i;
wire enb_i;
wire reseta_i;
wire resetb_i;
wire [C_WEA_WIDTH-1:0] wea_i;
wire [C_WEB_WIDTH-1:0] web_i;
wire rea_i;
wire reb_i;
wire rsta_outp_stage;
wire rstb_outp_stage;
// ECC SBITERR/DBITERR Outputs
// The ECC Behavior is modeled by the behavioral models only for Virtex-6.
// For Virtex-5, these outputs will be tied to 0.
assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;
assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;
assign RDADDRECC = (((C_FAMILY_LOCALPARAM == "virtex7") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;
// This effectively wires off optional inputs
assign ena_i = (C_HAS_ENA==0) || ENA;
assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;
// To match RTL : In RTL, write enable of the primitive is tied to all 1's and
// the enable of the primitive is ANDing of wea(0) and ena. so eventually, the
// write operation depends on both enable and write enable. So, the below code
// which is actually doing the write operation only on enable ignoring the wea
// is removed to be in consistent with RTL.
// To Fix CR855535 (The fix to this CR is reverted to match RTL)
//assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;
assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;
assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;
assign rea_i = (HAS_A_READ) ? ena_i : 'b0;
assign reb_i = (HAS_B_READ) ? enb_i : 'b0;
// These signals reset the memory latches
assign reseta_i =
((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||
(C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));
assign resetb_i =
((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||
(C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));
// Tasks to access the memory
//---------------------------
//**************
// write_a
//**************
task write_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg [C_WEA_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_A-1:0] data,
input inj_sbiterr,
input inj_dbiterr);
reg [C_WRITE_WIDTH_A-1:0] current_contents;
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_A_DIV);
if (address >= C_WRITE_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEA) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_A + i];
end
end
// Apply incoming bytes
if (C_WEA_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Insert double bit errors:
if (C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
// Modified for Implementing CR_859399
current_contents[0] = !(current_contents[30]);
current_contents[1] = !(current_contents[62]);
/*current_contents[0] = !(current_contents[0]);
current_contents[1] = !(current_contents[1]);*/
end
end
// Insert softecc double bit errors:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];
doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];
doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];
current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];
end
end
// Write data to memory
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_A] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_A + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
// Store the address at which error is injected:
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
sbiterr_arr[addr] = 1;
end else begin
sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
dbiterr_arr[addr] = 1;
end else begin
dbiterr_arr[addr] = 0;
end
end
// Store the address at which softecc error is injected:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
softecc_sbiterr_arr[addr] = 1;
end else begin
softecc_sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
softecc_dbiterr_arr[addr] = 1;
end else begin
softecc_dbiterr_arr[addr] = 0;
end
end
end
end
endtask
//**************
// write_b
//**************
task write_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg [C_WEB_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_B-1:0] data);
reg [C_WRITE_WIDTH_B-1:0] current_contents;
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_B_DIV);
if (address >= C_WRITE_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEB) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_B + i];
end
end
// Apply incoming bytes
if (C_WEB_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Write data to memory
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_B] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_B + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
end
end
endtask
//**************
// read_a
//**************
task read_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_a <= #FLOP_DELAY inita_val;
end else begin
// Shift the address by the ratio
address = (addr/READ_ADDR_A_DIV);
if (address >= C_READ_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Read",
C_CORENAME, addr);
end
memory_out_a <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_A==1) begin
memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin
memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];
end
end //end READ_WIDTH_RATIO_A==1 loop
end //end valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// read_b
//**************
task read_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_b <= #FLOP_DELAY initb_val;
sbiterr_in <= #FLOP_DELAY 1'b0;
dbiterr_in <= #FLOP_DELAY 1'b0;
rdaddrecc_in <= #FLOP_DELAY 0;
end else begin
// Shift the address
address = (addr/READ_ADDR_B_DIV);
if (address >= C_READ_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Read",
C_CORENAME, addr);
end
memory_out_b <= #FLOP_DELAY 'bX;
sbiterr_in <= #FLOP_DELAY 1'bX;
dbiterr_in <= #FLOP_DELAY 1'bX;
rdaddrecc_in <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_B==1) begin
memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin
memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];
end
end
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else if (C_USE_SOFTECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (softecc_sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (softecc_dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else begin
rdaddrecc_in <= #FLOP_DELAY 0;
dbiterr_in <= #FLOP_DELAY 1'b0;
sbiterr_in <= #FLOP_DELAY 1'b0;
end //end SOFTECC Loop
end //end Valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// reset_a
//**************
task reset_a (input reg reset);
begin
if (reset) memory_out_a <= #FLOP_DELAY inita_val;
end
endtask
//**************
// reset_b
//**************
task reset_b (input reg reset);
begin
if (reset) memory_out_b <= #FLOP_DELAY initb_val;
end
endtask
//**************
// init_memory
//**************
task init_memory;
integer i, j, addr_step;
integer status;
reg [C_WRITE_WIDTH_A-1:0] default_data;
begin
default_data = 0;
//Display output message indicating that the behavioral model is being
//initialized
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator module loading initial data...");
// Convert the default to hex
if (C_USE_DEFAULT_DATA) begin
if (default_data_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME);
$finish;
end else begin
status = $sscanf(default_data_str, "%h", default_data);
if (status == 0) begin
$fdisplay(ERRFILE, {"%0s ERROR: Unsuccessful hexadecimal read",
"from C_DEFAULT_DATA: %0s"},
C_CORENAME, C_DEFAULT_DATA);
$finish;
end
end
end
// Step by WRITE_ADDR_A_DIV through the memory via the
// Port A write interface to hit every location once
addr_step = WRITE_ADDR_A_DIV;
// 'write' to every location with default (or 0)
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);
end
// Get specialized data from the MIF file
if (C_LOAD_INIT_FILE) begin
if (init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE_NAME is empty!",
C_CORENAME);
$finish;
end else begin
initfile = $fopen(init_file_str, "r");
if (initfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE_NAME: %0s!"},
C_CORENAME, init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
status = $fscanf(initfile, "%b", mif_data);
if (status > 0) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);
end
end
$fclose(initfile);
end //initfile
end //init_file_str
end //C_LOAD_INIT_FILE
if (C_USE_BRAM_BLOCK) begin
// Get specialized data from the MIF file
if (C_INIT_FILE != "NONE") begin
if (mem_init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE is empty!",
C_CORENAME);
$finish;
end else begin
meminitfile = $fopen(mem_init_file_str, "r");
if (meminitfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE: %0s!"},
C_CORENAME, mem_init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
$readmemh(mem_init_file_str, memory );
for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin
end
$fclose(meminitfile);
end //meminitfile
end //mem_init_file_str
end //C_INIT_FILE
end //C_USE_BRAM_BLOCK
//Display output message indicating that the behavioral model is done
//initializing
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE)
$display(" Block Memory Generator data initialization complete.");
end
endtask
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//*******************
// collision_check
//*******************
function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,
input integer iswrite_a,
input reg [C_ADDRB_WIDTH-1:0] addr_b,
input integer iswrite_b);
reg c_aw_bw, c_aw_br, c_ar_bw;
integer scaled_addra_to_waddrb_width;
integer scaled_addrb_to_waddrb_width;
integer scaled_addra_to_waddra_width;
integer scaled_addrb_to_waddra_width;
integer scaled_addra_to_raddrb_width;
integer scaled_addrb_to_raddrb_width;
integer scaled_addra_to_raddra_width;
integer scaled_addrb_to_raddra_width;
begin
c_aw_bw = 0;
c_aw_br = 0;
c_ar_bw = 0;
//If write_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_b_width. Once both are scaled to
//write_addr_b_width, compare.
scaled_addra_to_waddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_b_width));
scaled_addrb_to_waddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_b_width));
//If write_addr_a_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_a_width. Once both are scaled to
//write_addr_a_width, compare.
scaled_addra_to_waddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_a_width));
scaled_addrb_to_waddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_a_width));
//If read_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_b_width. Once both are scaled to
//read_addr_b_width, compare.
scaled_addra_to_raddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_b_width));
scaled_addrb_to_raddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_b_width));
//If read_addr_a_width is smaller, scale both addresses to that width for
//comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_a_width. Once both are scaled to
//read_addr_a_width, compare.
scaled_addra_to_raddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_a_width));
scaled_addrb_to_raddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_a_width));
//Look for a write-write collision. In order for a write-write
//collision to exist, both ports must have a write transaction.
if (iswrite_a && iswrite_b) begin
if (write_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end //width
end //iswrite_a and iswrite_b
//If the B port is reading (which means it is enabled - so could be
//a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
//to asymmetric write/read ports.
if (iswrite_a) begin
if (write_addr_a_width > read_addr_b_width) begin
if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end //width
end //iswrite_a
//If the A port is reading (which means it is enabled - so could be
// a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
// to asymmetric write/read ports.
if (iswrite_b) begin
if (read_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end else begin
if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end //width
end //iswrite_b
collision_check = c_aw_bw | c_aw_br | c_ar_bw;
end
endfunction
//*******************************
// power on values
//*******************************
initial begin
// Load up the memory
init_memory;
// Load up the output registers and latches
if ($sscanf(inita_str, "%h", inita_val)) begin
memory_out_a = inita_val;
end else begin
memory_out_a = 0;
end
if ($sscanf(initb_str, "%h", initb_val)) begin
memory_out_b = initb_val;
end else begin
memory_out_b = 0;
end
sbiterr_in = 1'b0;
dbiterr_in = 1'b0;
rdaddrecc_in = 0;
// Determine the effective address widths for each of the 4 ports
write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);
write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);
$display("Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.");
end
//***************************************************************************
// These are the main blocks which schedule read and write operations
// Note that the reset priority feature at the latch stage is only supported
// for Spartan-6. For other families, the default priority at the latch stage
// is "CE"
//***************************************************************************
// Synchronous clocks: schedule port operations with respect to
// both write operating modes
generate
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_wf_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_rf_wf
always @(posedge CLKA) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_wf_rf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_rf_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="WRITE_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_wf_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="READ_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_rf_nc
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_nc_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_nc_rf
always @(posedge CLKA) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_nc_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK) begin: com_clk_sched_default
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
endgenerate
// Asynchronous clocks: port operation is independent
generate
if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "WRITE_FIRST")) begin : async_clk_sched_clka_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "READ_FIRST")) begin : async_clk_sched_clka_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "NO_CHANGE")) begin : async_clk_sched_clka_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
end
end
endgenerate
generate
if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "WRITE_FIRST")) begin: async_clk_sched_clkb_wf
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "READ_FIRST")) begin: async_clk_sched_clkb_rf
always @(posedge CLKB) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "NO_CHANGE")) begin: async_clk_sched_clkb_nc
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
endgenerate
//***************************************************************
// Instantiate the variable depth output register stage module
//***************************************************************
// Port A
assign rsta_outp_stage = RSTA & (~SLEEP);
blk_mem_gen_v8_3_5_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTA),
.C_RSTRAM (C_RSTRAM_A),
.C_RST_PRIORITY (C_RST_PRIORITY_A),
.C_INIT_VAL (C_INITA_VAL),
.C_HAS_EN (C_HAS_ENA),
.C_HAS_REGCE (C_HAS_REGCEA),
.C_DATA_WIDTH (C_READ_WIDTH_A),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_A),
.C_EN_ECC_PIPE (0),
.FLOP_DELAY (FLOP_DELAY))
reg_a
(.CLK (CLKA),
.RST (rsta_outp_stage),//(RSTA),
.EN (ENA),
.REGCE (REGCEA),
.DIN_I (memory_out_a),
.DOUT (DOUTA),
.SBITERR_IN_I (1'b0),
.DBITERR_IN_I (1'b0),
.SBITERR (),
.DBITERR (),
.RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),
.ECCPIPECE (1'b0),
.RDADDRECC ()
);
assign rstb_outp_stage = RSTB & (~SLEEP);
// Port B
blk_mem_gen_v8_3_5_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTB),
.C_RSTRAM (C_RSTRAM_B),
.C_RST_PRIORITY (C_RST_PRIORITY_B),
.C_INIT_VAL (C_INITB_VAL),
.C_HAS_EN (C_HAS_ENB),
.C_HAS_REGCE (C_HAS_REGCEB),
.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_B),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.FLOP_DELAY (FLOP_DELAY))
reg_b
(.CLK (CLKB),
.RST (rstb_outp_stage),//(RSTB),
.EN (ENB),
.REGCE (REGCEB),
.DIN_I (memory_out_b),
.DOUT (dout_i),
.SBITERR_IN_I (sbiterr_in),
.DBITERR_IN_I (dbiterr_in),
.SBITERR (sbiterr_i),
.DBITERR (dbiterr_i),
.RDADDRECC_IN_I (rdaddrecc_in),
.ECCPIPECE (ECCPIPECE),
.RDADDRECC (rdaddrecc_i)
);
//***************************************************************
// Instantiate the Input and Output register stages
//***************************************************************
blk_mem_gen_v8_3_5_softecc_output_reg_stage
#(.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.FLOP_DELAY (FLOP_DELAY))
has_softecc_output_reg_stage
(.CLK (CLKB),
.DIN (dout_i),
.DOUT (DOUTB),
.SBITERR_IN (sbiterr_i),
.DBITERR_IN (dbiterr_i),
.SBITERR (sbiterr_sdp),
.DBITERR (dbiterr_sdp),
.RDADDRECC_IN (rdaddrecc_i),
.RDADDRECC (rdaddrecc_sdp)
);
//****************************************************
// Synchronous collision checks
//****************************************************
// CR 780544 : To make verilog model's collison warnings in consistant with
// vhdl model, the non-blocking assignments are replaced with blocking
// assignments.
generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision = 0;
end
end else begin
is_collision = 0;
end
// If the write port is in READ_FIRST mode, there is no collision
if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin
is_collision = 0;
end
if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin
is_collision = 0;
end
// Only flag if one of the accesses is a write
if (is_collision && (wea_i || web_i)) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B %0s address: %0h\n",
wea_i ? "write" : "read", ADDRA,
web_i ? "write" : "read", ADDRB);
end
end
//****************************************************
// Asynchronous collision checks
//****************************************************
end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll
// Delay A and B addresses in order to mimic setup/hold times
wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA;
wire [0:0] #COLL_DELAY wea_delay = wea_i;
wire #COLL_DELAY ena_delay = ena_i;
wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB;
wire [0:0] #COLL_DELAY web_delay = web_i;
wire #COLL_DELAY enb_delay = enb_i;
// Do the checks w/rt A
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_a = 0;
end
end else begin
is_collision_a = 0;
end
if (ena_i && enb_delay) begin
if(wea_i || web_delay) begin
is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,
web_delay);
end else begin
is_collision_delay_a = 0;
end
end else begin
is_collision_delay_a = 0;
end
// Only flag if B access is a write
if (is_collision_a && web_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, ADDRB);
end else if (is_collision_delay_a && web_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, addrb_delay);
end
end
// Do the checks w/rt B
always @(posedge CLKB) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_b = 0;
end
end else begin
is_collision_b = 0;
end
if (ena_delay && enb_i) begin
if (wea_delay || web_i) begin
is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,
web_i);
end else begin
is_collision_delay_b = 0;
end
end else begin
is_collision_delay_b = 0;
end
// Only flag if A access is a write
if (is_collision_b && wea_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
ADDRA, web_i ? "write" : "read", ADDRB);
end else if (is_collision_delay_b && wea_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
addra_delay, web_i ? "write" : "read", ADDRB);
end
end
end
endgenerate
endmodule
//*****************************************************************************
// Top module wraps Input register and Memory module
//
// This module is the top-level behavioral model and this implements the memory
// module and the input registers
//*****************************************************************************
module blk_mem_gen_v8_3_5
#(parameter C_CORENAME = "blk_mem_gen_v8_3_5",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_ELABORATION_DIR = "",
parameter C_INTERFACE_TYPE = 0,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_CTRL_ECC_ALGO = "NONE",
parameter C_ENABLE_32BIT_ADDRESS = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
//parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_SLEEP_PIN = 0,
parameter C_USE_URAM = 0,
parameter C_EN_RDADDRA_CHG = 0,
parameter C_EN_RDADDRB_CHG = 0,
parameter C_EN_DEEPSLEEP_PIN = 0,
parameter C_EN_SHUTDOWN_PIN = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_COUNT_36K_BRAM = "",
parameter C_COUNT_18K_BRAM = "",
parameter C_EST_POWER_SUMMARY = "",
parameter C_DISABLE_WARN_BHV_RANGE = 0
)
(input clka,
input rsta,
input ena,
input regcea,
input [C_WEA_WIDTH-1:0] wea,
input [C_ADDRA_WIDTH-1:0] addra,
input [C_WRITE_WIDTH_A-1:0] dina,
output [C_READ_WIDTH_A-1:0] douta,
input clkb,
input rstb,
input enb,
input regceb,
input [C_WEB_WIDTH-1:0] web,
input [C_ADDRB_WIDTH-1:0] addrb,
input [C_WRITE_WIDTH_B-1:0] dinb,
output [C_READ_WIDTH_B-1:0] doutb,
input injectsbiterr,
input injectdbiterr,
output sbiterr,
output dbiterr,
output [C_ADDRB_WIDTH-1:0] rdaddrecc,
input eccpipece,
input sleep,
input deepsleep,
input shutdown,
output rsta_busy,
output rstb_busy,
//AXI BMG Input and Output Port Declarations
//AXI Global Signals
input s_aclk,
input s_aresetn,
//AXI Full/lite slave write (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [31:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input s_axi_awvalid,
output s_axi_awready,
input [C_WRITE_WIDTH_A-1:0] s_axi_wdata,
input [C_WEA_WIDTH-1:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
input s_axi_bready,
//AXI Full/lite slave read (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [31:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_WRITE_WIDTH_B-1:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
input s_axi_rready,
//AXI Full/lite sideband signals
input s_axi_injectsbiterr,
input s_axi_injectdbiterr,
output s_axi_sbiterr,
output s_axi_dbiterr,
output [C_ADDRB_WIDTH-1:0] s_axi_rdaddrecc
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_HAS_SOFTECC_INPUT_REGS_A :
// C_HAS_SOFTECC_OUTPUT_REGS_B :
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
wire SBITERR;
wire DBITERR;
wire S_AXI_AWREADY;
wire S_AXI_WREADY;
wire S_AXI_BVALID;
wire S_AXI_ARREADY;
wire S_AXI_RLAST;
wire S_AXI_RVALID;
wire S_AXI_SBITERR;
wire S_AXI_DBITERR;
wire [C_WEA_WIDTH-1:0] WEA = wea;
wire [C_ADDRA_WIDTH-1:0] ADDRA = addra;
wire [C_WRITE_WIDTH_A-1:0] DINA = dina;
wire [C_READ_WIDTH_A-1:0] DOUTA;
wire [C_WEB_WIDTH-1:0] WEB = web;
wire [C_ADDRB_WIDTH-1:0] ADDRB = addrb;
wire [C_WRITE_WIDTH_B-1:0] DINB = dinb;
wire [C_READ_WIDTH_B-1:0] DOUTB;
wire [C_ADDRB_WIDTH-1:0] RDADDRECC;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID = s_axi_awid;
wire [31:0] S_AXI_AWADDR = s_axi_awaddr;
wire [7:0] S_AXI_AWLEN = s_axi_awlen;
wire [2:0] S_AXI_AWSIZE = s_axi_awsize;
wire [1:0] S_AXI_AWBURST = s_axi_awburst;
wire [C_WRITE_WIDTH_A-1:0] S_AXI_WDATA = s_axi_wdata;
wire [C_WEA_WIDTH-1:0] S_AXI_WSTRB = s_axi_wstrb;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [1:0] S_AXI_BRESP;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID = s_axi_arid;
wire [31:0] S_AXI_ARADDR = s_axi_araddr;
wire [7:0] S_AXI_ARLEN = s_axi_arlen;
wire [2:0] S_AXI_ARSIZE = s_axi_arsize;
wire [1:0] S_AXI_ARBURST = s_axi_arburst;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_WRITE_WIDTH_B-1:0] S_AXI_RDATA;
wire [1:0] S_AXI_RRESP;
wire [C_ADDRB_WIDTH-1:0] S_AXI_RDADDRECC;
// Added to fix the simulation warning #CR731605
wire [C_WEB_WIDTH-1:0] WEB_parameterized = 0;
wire ECCPIPECE;
wire SLEEP;
reg RSTA_BUSY = 0;
reg RSTB_BUSY = 0;
// Declaration of internal signals to avoid warnings #927399
wire CLKA;
wire RSTA;
wire ENA;
wire REGCEA;
wire CLKB;
wire RSTB;
wire ENB;
wire REGCEB;
wire INJECTSBITERR;
wire INJECTDBITERR;
wire S_ACLK;
wire S_ARESETN;
wire S_AXI_AWVALID;
wire S_AXI_WLAST;
wire S_AXI_WVALID;
wire S_AXI_BREADY;
wire S_AXI_ARVALID;
wire S_AXI_RREADY;
wire S_AXI_INJECTSBITERR;
wire S_AXI_INJECTDBITERR;
assign CLKA = clka;
assign RSTA = rsta;
assign ENA = ena;
assign REGCEA = regcea;
assign CLKB = clkb;
assign RSTB = rstb;
assign ENB = enb;
assign REGCEB = regceb;
assign INJECTSBITERR = injectsbiterr;
assign INJECTDBITERR = injectdbiterr;
assign ECCPIPECE = eccpipece;
assign SLEEP = sleep;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign S_AXI_INJECTSBITERR = s_axi_injectsbiterr;
assign S_AXI_INJECTDBITERR = s_axi_injectdbiterr;
assign s_axi_sbiterr = S_AXI_SBITERR;
assign s_axi_dbiterr = S_AXI_DBITERR;
assign rsta_busy = RSTA_BUSY;
assign rstb_busy = RSTB_BUSY;
assign doutb = DOUTB;
assign douta = DOUTA;
assign rdaddrecc = RDADDRECC;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_rdaddrecc = S_AXI_RDADDRECC;
localparam FLOP_DELAY = 100; // 100 ps
reg injectsbiterr_in;
reg injectdbiterr_in;
reg rsta_in;
reg ena_in;
reg regcea_in;
reg [C_WEA_WIDTH-1:0] wea_in;
reg [C_ADDRA_WIDTH-1:0] addra_in;
reg [C_WRITE_WIDTH_A-1:0] dina_in;
wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;
wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;
wire s_axi_wr_en_c;
wire s_axi_rd_en_c;
wire s_aresetn_a_c;
wire [7:0] s_axi_arlen_c ;
wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;
wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;
wire [1:0] s_axi_rresp_c;
wire s_axi_rlast_c;
wire s_axi_rvalid_c;
wire s_axi_rready_c;
wire regceb_c;
localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;
wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;
wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;
// Safety logic related signals
reg [4:0] RSTA_SHFT_REG = 0;
reg POR_A = 0;
reg [4:0] RSTB_SHFT_REG = 0;
reg POR_B = 0;
reg ENA_dly = 0;
reg ENA_dly_D = 0;
reg ENB_dly = 0;
reg ENB_dly_D = 0;
wire RSTA_I_SAFE;
wire RSTB_I_SAFE;
wire ENA_I_SAFE;
wire ENB_I_SAFE;
reg ram_rstram_a_busy = 0;
reg ram_rstreg_a_busy = 0;
reg ram_rstram_b_busy = 0;
reg ram_rstreg_b_busy = 0;
reg ENA_dly_reg = 0;
reg ENB_dly_reg = 0;
reg ENA_dly_reg_D = 0;
reg ENB_dly_reg_D = 0;
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//**************
// log2int
//**************
function integer log2int (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
cnt= data_value;
for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin
width = width + 1;
end //loop
log2int = width;
end //log2int
endfunction
//**************************************************************************
// FUNCTION : divroundup
// Returns the ceiling value of the division
// Data_value - the quantity to be divided, dividend
// Divisor - the value to divide the data_value by
//**************************************************************************
function integer divroundup (input integer data_value,input integer divisor);
integer div;
begin
div = data_value/divisor;
if ((data_value % divisor) != 0) begin
div = div+1;
end //if
divroundup = div;
end //if
endfunction
localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);
localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
localparam C_AXI_ADDR_WIDTH = C_AXI_ADDR_WIDTH_MSB;
//Data Width Number of LSB address bits to be discarded
//1 to 16 1
//17 to 32 2
//33 to 64 3
//65 to 128 4
//129 to 256 5
//257 to 512 6
//513 to 1024 7
// The following two constants determine this.
localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);
localparam C_AXI_OS_WR = 2;
//***********************************************
// INPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage
always @* begin
injectsbiterr_in = INJECTSBITERR;
injectdbiterr_in = INJECTDBITERR;
rsta_in = RSTA;
ena_in = ENA;
regcea_in = REGCEA;
wea_in = WEA;
addra_in = ADDRA;
dina_in = DINA;
end //end always
end //end no_softecc_input_reg_stage
endgenerate
generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage
always @(posedge CLKA) begin
injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;
injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;
rsta_in <= #FLOP_DELAY RSTA;
ena_in <= #FLOP_DELAY ENA;
regcea_in <= #FLOP_DELAY REGCEA;
wea_in <= #FLOP_DELAY WEA;
addra_in <= #FLOP_DELAY ADDRA;
dina_in <= #FLOP_DELAY DINA;
end //end always
end //end input_reg_stages generate statement
endgenerate
//**************************************************************************
// NO SAFETY LOGIC
//**************************************************************************
generate
if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN
assign ENA_I_SAFE = ena_in;
assign ENB_I_SAFE = ENB;
assign RSTA_I_SAFE = rsta_in;
assign RSTB_I_SAFE = RSTB;
end
endgenerate
//***************************************************************************
// SAFETY LOGIC
// Power-ON Reset Generation
//***************************************************************************
generate
if (C_EN_SAFETY_CKT == 1) begin
always @(posedge clka) RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;
always @(posedge clka) POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];
always @(posedge clkb) RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;
always @(posedge clkb) POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0];
assign RSTA_I_SAFE = rsta_in | POR_A;
assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);
end
endgenerate
//-----------------------------------------------------------------------------
// -- RSTA/B_BUSY Generation
//-----------------------------------------------------------------------------
generate
if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG
always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;
always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG
always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;
always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;
end
endgenerate
generate
if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY
always @(*) RSTB_BUSY = 1'b0;
end
endgenerate
generate
if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_NO_REG
always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;
always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG
always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;
always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;
end
endgenerate
//-----------------------------------------------------------------------------
// -- ENA/ENB Generation
//-----------------------------------------------------------------------------
generate
if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG
always @(posedge clka) begin
ENA_dly <= #FLOP_DELAY RSTA_I_SAFE;
ENA_dly_D <= #FLOP_DELAY ENA_dly;
end
assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);
end
endgenerate
generate
if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG
always @(posedge clka) begin
ENA_dly_reg <= #FLOP_DELAY RSTA_I_SAFE;
ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;
end
assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);
end
endgenerate
generate
if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB
assign ENB_I_SAFE = 1'b0;
end
endgenerate
generate
if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG
always @(posedge clkb) begin : PROC_ENB_GEN
ENB_dly <= #FLOP_DELAY RSTB_I_SAFE;
ENB_dly_D <= #FLOP_DELAY ENB_dly;
end
assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG
always @(posedge clkb) begin : PROC_ENB_GEN
ENB_dly_reg <= #FLOP_DELAY RSTB_I_SAFE;
ENB_dly_reg_D <= #FLOP_DELAY ENB_dly_reg;
end
assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);
end
endgenerate
generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module
blk_mem_gen_v8_3_5_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_ALGORITHM (C_ALGORITHM),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_5_inst
(.CLKA (CLKA),
.RSTA (RSTA_I_SAFE),//(rsta_in),
.ENA (ENA_I_SAFE),//(ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB_I_SAFE),//(RSTB),
.ENB (ENB_I_SAFE),//(ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module
localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);
localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);
localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
// localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);
// localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);
localparam C_MEM_MAP_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_MSB;
localparam C_MEM_MAP_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_MSB;
// Data Width Number of LSB address bits to be discarded
// 1 to 16 1
// 17 to 32 2
// 33 to 64 3
// 65 to 128 4
// 129 to 256 5
// 257 to 512 6
// 513 to 1024 7
// The following two constants determine this.
localparam MEM_MAP_LOWER_BOUND_VAL_A = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam MEM_MAP_LOWER_BOUND_VAL_B = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;
localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;
wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;
wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;
wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;
assign msb_zero_i = 0;
assign lsb_zero_i = 0;
assign RDADDRECC = {msb_zero_i,rdaddrecc_i,lsb_zero_i};
blk_mem_gen_v8_3_5_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH_ACTUAL),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH_ACTUAL),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_5_inst
(.CLKA (CLKA),
.RSTA (RSTA_I_SAFE),//(rsta_in),
.ENA (ENA_I_SAFE),//(ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB_I_SAFE),//(RSTB),
.ENB (ENB_I_SAFE),//(ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (rdaddrecc_i)
);
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RLAST = s_axi_rlast_c;
assign S_AXI_RVALID = s_axi_rvalid_c;
assign S_AXI_RID = s_axi_rid_c;
assign S_AXI_RRESP = s_axi_rresp_c;
assign s_axi_rready_c = S_AXI_RREADY;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb
assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb
assign regceb_c = REGCEB;
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RDATA = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd
blk_mem_axi_regs_fwd_v8_3
#(.C_DATA_WIDTH (C_AXI_PAYLOAD))
axi_regs_inst (
.ACLK (S_ACLK),
.ARESET (s_aresetn_a_c),
.S_VALID (s_axi_rvalid_c),
.S_READY (s_axi_rready_c),
.S_PAYLOAD_DATA (s_axi_payload_c),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY),
.M_PAYLOAD_DATA (m_axi_payload_c)
);
end
endgenerate
generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module
assign s_aresetn_a_c = !S_ARESETN;
assign S_AXI_BRESP = 2'b00;
assign s_axi_rresp_c = 2'b00;
assign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;
blk_mem_axi_write_wrapper_beh_v8_3
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_AXI_AWADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_WDATA_WIDTH (C_WRITE_WIDTH_A),
.C_AXI_OS_WR (C_AXI_OS_WR))
axi_wr_fsm (
// AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
// AXI Full/Lite Slave Write interface
.S_AXI_AWADDR (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
.S_AXI_BID (S_AXI_BID),
// Signals for BRAM interfac(
.S_AXI_AWADDR_OUT (s_axi_awaddr_out_c),
.S_AXI_WR_EN (s_axi_wr_en_c)
);
blk_mem_axi_read_wrapper_beh_v8_3
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_PIPELINE_STAGES (1),
.C_AXI_ARADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_rd_sm(
//AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
//AXI Full/Lite Read Side
.S_AXI_ARADDR (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_ARLEN (s_axi_arlen_c),
.S_AXI_ARSIZE (S_AXI_ARSIZE),
.S_AXI_ARBURST (S_AXI_ARBURST),
.S_AXI_ARVALID (S_AXI_ARVALID),
.S_AXI_ARREADY (S_AXI_ARREADY),
.S_AXI_RLAST (s_axi_rlast_c),
.S_AXI_RVALID (s_axi_rvalid_c),
.S_AXI_RREADY (s_axi_rready_c),
.S_AXI_ARID (S_AXI_ARID),
.S_AXI_RID (s_axi_rid_c),
//AXI Full/Lite Read FSM Outputs
.S_AXI_ARADDR_OUT (s_axi_araddr_out_c),
.S_AXI_RD_EN (s_axi_rd_en_c)
);
blk_mem_gen_v8_3_5_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (1),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (1),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (1),
.C_HAS_REGCEB (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_BYTE_WEB (1),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (0),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (0),
.C_HAS_MUX_OUTPUT_REGS_B (0),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (0),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_5_inst
(.CLKA (S_ACLK),
.RSTA (s_aresetn_a_c),
.ENA (s_axi_wr_en_c),
.REGCEA (regcea_in),
.WEA (S_AXI_WSTRB),
.ADDRA (s_axi_awaddr_out_c),
.DINA (S_AXI_WDATA),
.DOUTA (DOUTA),
.CLKB (S_ACLK),
.RSTB (s_aresetn_a_c),
.ENB (s_axi_rd_en_c),
.REGCEB (regceb_c),
.WEB (WEB_parameterized),
.ADDRB (s_axi_araddr_out_c),
.DINB (DINB),
.DOUTB (s_axi_rdata_c),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.ECCPIPECE (1'b0),
.SLEEP (1'b0),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
endmodule
|
//
///////////////////////////////////////////////////////////////////////////////////////////
// Copyright © 2010-2013, Xilinx, Inc.
// This file contains confidential and proprietary information of Xilinx, Inc. and is
// protected under U.S. and international copyright and other intellectual property laws.
///////////////////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to
// you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
// MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
// DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
// OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
// (whether in contract or tort, including negligence, or under any other theory
// of liability) for any loss or damage of any kind or nature related to, arising
// under or in connection with these materials, including for any direct, or any
// indirect, special, incidental, or consequential loss or damage (including loss
// of data, profits, goodwill, or any type of loss or damage suffered as a result
// of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-safe, or for use in any
// application requiring fail-safe performance, such as life-support or safety
// devices or systems, Class III medical devices, nuclear facilities, applications
// related to the deployment of airbags, or any other applications that could lead
// to death, personal injury, or severe property or environmental damage
// (individually and collectively, "Critical Applications"). Customer assumes the
// sole risk and liability of any use of Xilinx products in Critical Applications,
// subject only to applicable laws and regulations governing limitations on product
// liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////////////////
//
ROM_form.v
Template for a 1K program for KCPSM6 in a Spartan-6 device using a RAMB18WER primitive.
Includes generic parameters to allow for the inclusion of Jtag Loader hardware for
software development.
Nick Sawyer (Xilinx Ltd)
Ken Chapman (Xilinx Ltd)
Kris Chaplin (Xilinx Ltd)
3rd March 2011 - Initial Verilog Release
16th August 2011 - Additions and adjustments for support of 7-Series in ISE v13.2.
Simplification of JTAG Loader definition.
20th April 2012 - Correction to copyright year range.
26th November 2012 - 4K program for Spartan-6.
14th March 2013 - Unused address inputs on Virtex-6 and 7-Series BRAMs connected
High to reflect descriptions in UG363 and UG473.
This is a Verilog template file for the KCPSM6 assembler.
This Verilog file is not valid as input directly into a synthesis or a simulation tool.
The assembler will read this template and insert the information required to complete
the definition of program ROM and write it out to a new '.v' file that is ready for
synthesis and simulation.
This template can be modified to define alternative memory definitions. However, you are
responsible for ensuring the template is correct as the assembler does not perform any
checking of the VHDL.
The assembler identifies all text enclosed by {} characters, and replaces these
character strings. All templates should include these {} character strings for
the assembler to work correctly.
The next line is used to determine where the template actually starts.
{begin template}
//
///////////////////////////////////////////////////////////////////////////////////////////
// Copyright © 2010-2013, Xilinx, Inc.
// This file contains confidential and proprietary information of Xilinx, Inc. and is
// protected under U.S. and international copyright and other intellectual property laws.
///////////////////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to
// you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
// MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
// DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
// OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
// (whether in contract or tort, including negligence, or under any other theory
// of liability) for any loss or damage of any kind or nature related to, arising
// under or in connection with these materials, including for any direct, or any
// indirect, special, incidental, or consequential loss or damage (including loss
// of data, profits, goodwill, or any type of loss or damage suffered as a result
// of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-safe, or for use in any
// application requiring fail-safe performance, such as life-support or safety
// devices or systems, Class III medical devices, nuclear facilities, applications
// related to the deployment of airbags, or any other applications that could lead
// to death, personal injury, or severe property or environmental damage
// (individually and collectively, "Critical Applications"). Customer assumes the
// sole risk and liability of any use of Xilinx products in Critical Applications,
// subject only to applicable laws and regulations governing limitations on product
// liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////////////////
//
//
// Definition of a program memory for KCPSM6 including generic parameters for the
// convenient selection of device family, program memory size and the ability to include
// the JTAG Loader hardware for rapid software development.
//
// This file is primarily for use during code development and it is recommended that the
// appropriate simplified program memory definition be used in a final production design.
//
//
// Generic Values Comments
// Parameter Supported
//
// C_FAMILY "S6" Spartan-6 device
// "V6" Virtex-6 device
// "7S" 7-Series device
// (Artix-7, Kintex-7, Virtex-7 or Zynq)
//
// C_RAM_SIZE_KWORDS 1, 2 or 4 Size of program memory in K-instructions
//
// C_JTAG_LOADER_ENABLE 0 or 1 Set to '1' to include JTAG Loader
//
// Notes
//
// If your design contains MULTIPLE KCPSM6 instances then only one should have the
// JTAG Loader enabled at a time (i.e. make sure that C_JTAG_LOADER_ENABLE is only set to
// '1' on one instance of the program memory). Advanced users may be interested to know
// that it is possible to connect JTAG Loader to multiple memories and then to use the
// JTAG Loader utility to specify which memory contents are to be modified. However,
// this scheme does require some effort to set up and the additional connectivity of the
// multiple BRAMs can impact the placement, routing and performance of the complete
// design. Please contact the author at Xilinx for more detailed information.
//
// Regardless of the size of program memory specified by C_RAM_SIZE_KWORDS, the complete
// 12-bit address bus is connected to KCPSM6. This enables the generic to be modified
// without requiring changes to the fundamental hardware definition. However, when the
// program memory is 1K then only the lower 10-bits of the address are actually used and
// the valid address range is 000 to 3FF hex. Likewise, for a 2K program only the lower
// 11-bits of the address are actually used and the valid address range is 000 to 7FF hex.
//
// Programs are stored in Block Memory (BRAM) and the number of BRAM used depends on the
// size of the program and the device family.
//
// In a Spartan-6 device a BRAM is capable of holding 1K instructions. Hence a 2K program
// will require 2 BRAMs to be used and a 4K program will require 4 BRAMs to be used. It
// should be noted that a 4K program is not such a natural fit in a Spartan-6 device and
// the implementation also requires a small amount of logic resulting in slightly lower
// performance. A Spartan-6 BRAM can also be split into two 9k-bit memories suggesting
// that a program containing up to 512 instructions could be implemented. However, there
// is a silicon errata which makes this unsuitable and therefore it is not supported by
// this file.
//
// In a Virtex-6 or any 7-Series device a BRAM is capable of holding 2K instructions so
// obviously a 2K program requires only a single BRAM. Each BRAM can also be divided into
// 2 smaller memories supporting programs of 1K in half of a 36k-bit BRAM (generally
// reported as being an 18k-bit BRAM). For a program of 4K instructions, 2 BRAMs are used.
//
//
// Program defined by '{psmname}.psm'.
//
// Generated by KCPSM6 Assembler: {timestamp}.
//
// Assembler used ROM_form template: ROM_form_JTAGLoader_14March13.v
//
//
`timescale 1ps/1ps
module {name} (address, instruction, enable, rdl, clk);
//
parameter integer C_JTAG_LOADER_ENABLE = 1;
parameter C_FAMILY = "7S";
parameter integer C_RAM_SIZE_KWORDS = 1;
//
input clk;
input [11:0] address;
input enable;
output [17:0] instruction;
output rdl;
//
//
wire [15:0] address_a;
wire pipe_a11;
wire [35:0] data_in_a;
wire [35:0] data_out_a;
wire [35:0] data_out_a_l;
wire [35:0] data_out_a_h;
wire [35:0] data_out_a_ll;
wire [35:0] data_out_a_lh;
wire [35:0] data_out_a_hl;
wire [35:0] data_out_a_hh;
wire [15:0] address_b;
wire [35:0] data_in_b;
wire [35:0] data_in_b_l;
wire [35:0] data_in_b_ll;
wire [35:0] data_in_b_hl;
wire [35:0] data_out_b;
wire [35:0] data_out_b_l;
wire [35:0] data_out_b_ll;
wire [35:0] data_out_b_hl;
wire [35:0] data_in_b_h;
wire [35:0] data_in_b_lh;
wire [35:0] data_in_b_hh;
wire [35:0] data_out_b_h;
wire [35:0] data_out_b_lh;
wire [35:0] data_out_b_hh;
wire enable_b;
wire clk_b;
wire [7:0] we_b;
wire [3:0] we_b_l;
wire [3:0] we_b_h;
//
wire [11:0] jtag_addr;
wire jtag_we;
wire jtag_clk;
wire [17:0] jtag_din;
wire [17:0] jtag_dout;
wire [17:0] jtag_dout_1;
wire [0:0] jtag_en;
//
wire [0:0] picoblaze_reset;
wire [0:0] rdl_bus;
//
parameter integer BRAM_ADDRESS_WIDTH = addr_width_calc(C_RAM_SIZE_KWORDS);
//
//
function integer addr_width_calc;
input integer size_in_k;
if (size_in_k == 1) begin addr_width_calc = 10; end
else if (size_in_k == 2) begin addr_width_calc = 11; end
else if (size_in_k == 4) begin addr_width_calc = 12; end
else begin
if (C_RAM_SIZE_KWORDS != 1 && C_RAM_SIZE_KWORDS != 2 && C_RAM_SIZE_KWORDS != 4) begin
//#0;
$display("Invalid BlockRAM size. Please set to 1, 2 or 4 K words..\n");
$finish;
end
end
endfunction
//
//
generate
if (C_RAM_SIZE_KWORDS == 1) begin : ram_1k_generate
//
//
//
if (C_FAMILY == "7S") begin: akv7
//
assign address_a[13:0] = {address[9:0], 4'b1111};
assign instruction = data_out_a[17:0];
assign data_in_a[17:0] = {16'b0000000000000000, address[11:10]};
assign jtag_dout = data_out_b[17:0];
//
if (C_JTAG_LOADER_ENABLE == 0) begin : no_loader
assign data_in_b[17:0] = data_out_b[17:0];
assign address_b[13:0] = 14'b11111111111111;
assign we_b[3:0] = 4'b0000;
assign enable_b = 1'b0;
assign rdl = 1'b0;
assign clk_b = 1'b0;
end // no_loader;
//
if (C_JTAG_LOADER_ENABLE == 1) begin : loader
assign data_in_b[17:0] = jtag_din[17:0];
assign address_b[13:0] = {jtag_addr[9:0], 4'b1111};
assign we_b[3:0] = {jtag_we, jtag_we, jtag_we, jtag_we};
assign enable_b = jtag_en[0];
assign rdl = rdl_bus[0];
assign clk_b = jtag_clk;
end // loader;
//
RAMB18E1 #(.READ_WIDTH_A (18),
.WRITE_WIDTH_A (18),
.DOA_REG (0),
.INIT_A (18'b000000000000000000),
.RSTREG_PRIORITY_A ("REGCE"),
.SRVAL_A (18'b000000000000000000),
.WRITE_MODE_A ("WRITE_FIRST"),
.READ_WIDTH_B (18),
.WRITE_WIDTH_B (18),
.DOB_REG (0),
.INIT_B (18'b000000000000000000),
.RSTREG_PRIORITY_B ("REGCE"),
.SRVAL_B (18'b000000000000000000),
.WRITE_MODE_B ("WRITE_FIRST"),
.INIT_FILE ("NONE"),
.SIM_COLLISION_CHECK ("ALL"),
.RAM_MODE ("TDP"),
.RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),
.SIM_DEVICE ("7SERIES"),
.INIT_00 (256'h{INIT_00}),
.INIT_01 (256'h{INIT_01}),
.INIT_02 (256'h{INIT_02}),
.INIT_03 (256'h{INIT_03}),
.INIT_04 (256'h{INIT_04}),
.INIT_05 (256'h{INIT_05}),
.INIT_06 (256'h{INIT_06}),
.INIT_07 (256'h{INIT_07}),
.INIT_08 (256'h{INIT_08}),
.INIT_09 (256'h{INIT_09}),
.INIT_0A (256'h{INIT_0A}),
.INIT_0B (256'h{INIT_0B}),
.INIT_0C (256'h{INIT_0C}),
.INIT_0D (256'h{INIT_0D}),
.INIT_0E (256'h{INIT_0E}),
.INIT_0F (256'h{INIT_0F}),
.INIT_10 (256'h{INIT_10}),
.INIT_11 (256'h{INIT_11}),
.INIT_12 (256'h{INIT_12}),
.INIT_13 (256'h{INIT_13}),
.INIT_14 (256'h{INIT_14}),
.INIT_15 (256'h{INIT_15}),
.INIT_16 (256'h{INIT_16}),
.INIT_17 (256'h{INIT_17}),
.INIT_18 (256'h{INIT_18}),
.INIT_19 (256'h{INIT_19}),
.INIT_1A (256'h{INIT_1A}),
.INIT_1B (256'h{INIT_1B}),
.INIT_1C (256'h{INIT_1C}),
.INIT_1D (256'h{INIT_1D}),
.INIT_1E (256'h{INIT_1E}),
.INIT_1F (256'h{INIT_1F}),
.INIT_20 (256'h{INIT_20}),
.INIT_21 (256'h{INIT_21}),
.INIT_22 (256'h{INIT_22}),
.INIT_23 (256'h{INIT_23}),
.INIT_24 (256'h{INIT_24}),
.INIT_25 (256'h{INIT_25}),
.INIT_26 (256'h{INIT_26}),
.INIT_27 (256'h{INIT_27}),
.INIT_28 (256'h{INIT_28}),
.INIT_29 (256'h{INIT_29}),
.INIT_2A (256'h{INIT_2A}),
.INIT_2B (256'h{INIT_2B}),
.INIT_2C (256'h{INIT_2C}),
.INIT_2D (256'h{INIT_2D}),
.INIT_2E (256'h{INIT_2E}),
.INIT_2F (256'h{INIT_2F}),
.INIT_30 (256'h{INIT_30}),
.INIT_31 (256'h{INIT_31}),
.INIT_32 (256'h{INIT_32}),
.INIT_33 (256'h{INIT_33}),
.INIT_34 (256'h{INIT_34}),
.INIT_35 (256'h{INIT_35}),
.INIT_36 (256'h{INIT_36}),
.INIT_37 (256'h{INIT_37}),
.INIT_38 (256'h{INIT_38}),
.INIT_39 (256'h{INIT_39}),
.INIT_3A (256'h{INIT_3A}),
.INIT_3B (256'h{INIT_3B}),
.INIT_3C (256'h{INIT_3C}),
.INIT_3D (256'h{INIT_3D}),
.INIT_3E (256'h{INIT_3E}),
.INIT_3F (256'h{INIT_3F}),
.INITP_00 (256'h{INITP_00}),
.INITP_01 (256'h{INITP_01}),
.INITP_02 (256'h{INITP_02}),
.INITP_03 (256'h{INITP_03}),
.INITP_04 (256'h{INITP_04}),
.INITP_05 (256'h{INITP_05}),
.INITP_06 (256'h{INITP_06}),
.INITP_07 (256'h{INITP_07}))
kcpsm6_rom( .ADDRARDADDR (address_a[13:0]),
.ENARDEN (enable),
.CLKARDCLK (clk),
.DOADO (data_out_a[15:0]),
.DOPADOP (data_out_a[17:16]),
.DIADI (data_in_a[15:0]),
.DIPADIP (data_in_a[17:16]),
.WEA (2'b00),
.REGCEAREGCE (1'b0),
.RSTRAMARSTRAM (1'b0),
.RSTREGARSTREG (1'b0),
.ADDRBWRADDR (address_b[13:0]),
.ENBWREN (enable_b),
.CLKBWRCLK (clk_b),
.DOBDO (data_out_b[15:0]),
.DOPBDOP (data_out_b[17:16]),
.DIBDI (data_in_b[15:0]),
.DIPBDIP (data_in_b[17:16]),
.WEBWE (we_b[3:0]),
.REGCEB (1'b0),
.RSTRAMB (1'b0),
.RSTREGB (1'b0));
end // akv7;
//
end // ram_1k_generate;
endgenerate
//
generate
if (C_RAM_SIZE_KWORDS == 2) begin : ram_2k_generate
//
//
//
if (C_FAMILY == "7S") begin: akv7
//
assign address_a = {1'b1, address[10:0], 4'b1111};
assign instruction = {data_out_a[33:32], data_out_a[15:0]};
assign data_in_a = {35'b00000000000000000000000000000000000, address[11]};
assign jtag_dout = {data_out_b[33:32], data_out_b[15:0]};
//
if (C_JTAG_LOADER_ENABLE == 0) begin : no_loader
assign data_in_b = {2'b00, data_out_b[33:32], 16'b0000000000000000, data_out_b[15:0]};
assign address_b = 16'b1111111111111111;
assign we_b = 8'b00000000;
assign enable_b = 1'b0;
assign rdl = 1'b0;
assign clk_b = 1'b0;
end // no_loader;
//
if (C_JTAG_LOADER_ENABLE == 1) begin : loader
assign data_in_b = {2'b00, jtag_din[17:16], 16'b0000000000000000, jtag_din[15:0]};
assign address_b = {1'b1, jtag_addr[10:0], 4'b1111};
assign we_b = {jtag_we, jtag_we, jtag_we, jtag_we, jtag_we, jtag_we, jtag_we, jtag_we};
assign enable_b = jtag_en[0];
assign rdl = rdl_bus[0];
assign clk_b = jtag_clk;
end // loader;
//
RAMB36E1 #(.READ_WIDTH_A (18),
.WRITE_WIDTH_A (18),
.DOA_REG (0),
.INIT_A (36'h000000000),
.RSTREG_PRIORITY_A ("REGCE"),
.SRVAL_A (36'h000000000),
.WRITE_MODE_A ("WRITE_FIRST"),
.READ_WIDTH_B (18),
.WRITE_WIDTH_B (18),
.DOB_REG (0),
.INIT_B (36'h000000000),
.RSTREG_PRIORITY_B ("REGCE"),
.SRVAL_B (36'h000000000),
.WRITE_MODE_B ("WRITE_FIRST"),
.INIT_FILE ("NONE"),
.SIM_COLLISION_CHECK ("ALL"),
.RAM_MODE ("TDP"),
.RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),
.EN_ECC_READ ("FALSE"),
.EN_ECC_WRITE ("FALSE"),
.RAM_EXTENSION_A ("NONE"),
.RAM_EXTENSION_B ("NONE"),
.SIM_DEVICE ("7SERIES"),
.INIT_00 (256'h{INIT_00}),
.INIT_01 (256'h{INIT_01}),
.INIT_02 (256'h{INIT_02}),
.INIT_03 (256'h{INIT_03}),
.INIT_04 (256'h{INIT_04}),
.INIT_05 (256'h{INIT_05}),
.INIT_06 (256'h{INIT_06}),
.INIT_07 (256'h{INIT_07}),
.INIT_08 (256'h{INIT_08}),
.INIT_09 (256'h{INIT_09}),
.INIT_0A (256'h{INIT_0A}),
.INIT_0B (256'h{INIT_0B}),
.INIT_0C (256'h{INIT_0C}),
.INIT_0D (256'h{INIT_0D}),
.INIT_0E (256'h{INIT_0E}),
.INIT_0F (256'h{INIT_0F}),
.INIT_10 (256'h{INIT_10}),
.INIT_11 (256'h{INIT_11}),
.INIT_12 (256'h{INIT_12}),
.INIT_13 (256'h{INIT_13}),
.INIT_14 (256'h{INIT_14}),
.INIT_15 (256'h{INIT_15}),
.INIT_16 (256'h{INIT_16}),
.INIT_17 (256'h{INIT_17}),
.INIT_18 (256'h{INIT_18}),
.INIT_19 (256'h{INIT_19}),
.INIT_1A (256'h{INIT_1A}),
.INIT_1B (256'h{INIT_1B}),
.INIT_1C (256'h{INIT_1C}),
.INIT_1D (256'h{INIT_1D}),
.INIT_1E (256'h{INIT_1E}),
.INIT_1F (256'h{INIT_1F}),
.INIT_20 (256'h{INIT_20}),
.INIT_21 (256'h{INIT_21}),
.INIT_22 (256'h{INIT_22}),
.INIT_23 (256'h{INIT_23}),
.INIT_24 (256'h{INIT_24}),
.INIT_25 (256'h{INIT_25}),
.INIT_26 (256'h{INIT_26}),
.INIT_27 (256'h{INIT_27}),
.INIT_28 (256'h{INIT_28}),
.INIT_29 (256'h{INIT_29}),
.INIT_2A (256'h{INIT_2A}),
.INIT_2B (256'h{INIT_2B}),
.INIT_2C (256'h{INIT_2C}),
.INIT_2D (256'h{INIT_2D}),
.INIT_2E (256'h{INIT_2E}),
.INIT_2F (256'h{INIT_2F}),
.INIT_30 (256'h{INIT_30}),
.INIT_31 (256'h{INIT_31}),
.INIT_32 (256'h{INIT_32}),
.INIT_33 (256'h{INIT_33}),
.INIT_34 (256'h{INIT_34}),
.INIT_35 (256'h{INIT_35}),
.INIT_36 (256'h{INIT_36}),
.INIT_37 (256'h{INIT_37}),
.INIT_38 (256'h{INIT_38}),
.INIT_39 (256'h{INIT_39}),
.INIT_3A (256'h{INIT_3A}),
.INIT_3B (256'h{INIT_3B}),
.INIT_3C (256'h{INIT_3C}),
.INIT_3D (256'h{INIT_3D}),
.INIT_3E (256'h{INIT_3E}),
.INIT_3F (256'h{INIT_3F}),
.INIT_40 (256'h{INIT_40}),
.INIT_41 (256'h{INIT_41}),
.INIT_42 (256'h{INIT_42}),
.INIT_43 (256'h{INIT_43}),
.INIT_44 (256'h{INIT_44}),
.INIT_45 (256'h{INIT_45}),
.INIT_46 (256'h{INIT_46}),
.INIT_47 (256'h{INIT_47}),
.INIT_48 (256'h{INIT_48}),
.INIT_49 (256'h{INIT_49}),
.INIT_4A (256'h{INIT_4A}),
.INIT_4B (256'h{INIT_4B}),
.INIT_4C (256'h{INIT_4C}),
.INIT_4D (256'h{INIT_4D}),
.INIT_4E (256'h{INIT_4E}),
.INIT_4F (256'h{INIT_4F}),
.INIT_50 (256'h{INIT_50}),
.INIT_51 (256'h{INIT_51}),
.INIT_52 (256'h{INIT_52}),
.INIT_53 (256'h{INIT_53}),
.INIT_54 (256'h{INIT_54}),
.INIT_55 (256'h{INIT_55}),
.INIT_56 (256'h{INIT_56}),
.INIT_57 (256'h{INIT_57}),
.INIT_58 (256'h{INIT_58}),
.INIT_59 (256'h{INIT_59}),
.INIT_5A (256'h{INIT_5A}),
.INIT_5B (256'h{INIT_5B}),
.INIT_5C (256'h{INIT_5C}),
.INIT_5D (256'h{INIT_5D}),
.INIT_5E (256'h{INIT_5E}),
.INIT_5F (256'h{INIT_5F}),
.INIT_60 (256'h{INIT_60}),
.INIT_61 (256'h{INIT_61}),
.INIT_62 (256'h{INIT_62}),
.INIT_63 (256'h{INIT_63}),
.INIT_64 (256'h{INIT_64}),
.INIT_65 (256'h{INIT_65}),
.INIT_66 (256'h{INIT_66}),
.INIT_67 (256'h{INIT_67}),
.INIT_68 (256'h{INIT_68}),
.INIT_69 (256'h{INIT_69}),
.INIT_6A (256'h{INIT_6A}),
.INIT_6B (256'h{INIT_6B}),
.INIT_6C (256'h{INIT_6C}),
.INIT_6D (256'h{INIT_6D}),
.INIT_6E (256'h{INIT_6E}),
.INIT_6F (256'h{INIT_6F}),
.INIT_70 (256'h{INIT_70}),
.INIT_71 (256'h{INIT_71}),
.INIT_72 (256'h{INIT_72}),
.INIT_73 (256'h{INIT_73}),
.INIT_74 (256'h{INIT_74}),
.INIT_75 (256'h{INIT_75}),
.INIT_76 (256'h{INIT_76}),
.INIT_77 (256'h{INIT_77}),
.INIT_78 (256'h{INIT_78}),
.INIT_79 (256'h{INIT_79}),
.INIT_7A (256'h{INIT_7A}),
.INIT_7B (256'h{INIT_7B}),
.INIT_7C (256'h{INIT_7C}),
.INIT_7D (256'h{INIT_7D}),
.INIT_7E (256'h{INIT_7E}),
.INIT_7F (256'h{INIT_7F}),
.INITP_00 (256'h{INITP_00}),
.INITP_01 (256'h{INITP_01}),
.INITP_02 (256'h{INITP_02}),
.INITP_03 (256'h{INITP_03}),
.INITP_04 (256'h{INITP_04}),
.INITP_05 (256'h{INITP_05}),
.INITP_06 (256'h{INITP_06}),
.INITP_07 (256'h{INITP_07}),
.INITP_08 (256'h{INITP_08}),
.INITP_09 (256'h{INITP_09}),
.INITP_0A (256'h{INITP_0A}),
.INITP_0B (256'h{INITP_0B}),
.INITP_0C (256'h{INITP_0C}),
.INITP_0D (256'h{INITP_0D}),
.INITP_0E (256'h{INITP_0E}),
.INITP_0F (256'h{INITP_0F}))
kcpsm6_rom( .ADDRARDADDR (address_a),
.ENARDEN (enable),
.CLKARDCLK (clk),
.DOADO (data_out_a[31:0]),
.DOPADOP (data_out_a[35:32]),
.DIADI (data_in_a[31:0]),
.DIPADIP (data_in_a[35:32]),
.WEA (4'b0000),
.REGCEAREGCE (1'b0),
.RSTRAMARSTRAM (1'b0),
.RSTREGARSTREG (1'b0),
.ADDRBWRADDR (address_b),
.ENBWREN (enable_b),
.CLKBWRCLK (clk_b),
.DOBDO (data_out_b[31:0]),
.DOPBDOP (data_out_b[35:32]),
.DIBDI (data_in_b[31:0]),
.DIPBDIP (data_in_b[35:32]),
.WEBWE (we_b),
.REGCEB (1'b0),
.RSTRAMB (1'b0),
.RSTREGB (1'b0),
.CASCADEINA (1'b0),
.CASCADEINB (1'b0),
.CASCADEOUTA (),
.CASCADEOUTB (),
.DBITERR (),
.ECCPARITY (),
.RDADDRECC (),
.SBITERR (),
.INJECTDBITERR (1'b0),
.INJECTSBITERR (1'b0));
end // akv7;
//
end // ram_2k_generate;
endgenerate
//
//
// JTAG Loader
//
generate
if (C_JTAG_LOADER_ENABLE == 1) begin: instantiate_loader
jtag_loader_6 #( .C_FAMILY (C_FAMILY),
.C_NUM_PICOBLAZE (1),
.C_JTAG_LOADER_ENABLE (C_JTAG_LOADER_ENABLE),
.C_BRAM_MAX_ADDR_WIDTH (BRAM_ADDRESS_WIDTH),
.C_ADDR_WIDTH_0 (BRAM_ADDRESS_WIDTH))
jtag_loader_6_inst(.picoblaze_reset (rdl_bus),
.jtag_en (jtag_en),
.jtag_din (jtag_din),
.jtag_addr (jtag_addr[BRAM_ADDRESS_WIDTH-1 : 0]),
.jtag_clk (jtag_clk),
.jtag_we (jtag_we),
.jtag_dout_0 (jtag_dout),
.jtag_dout_1 (jtag_dout), // ports 1-7 are not used
.jtag_dout_2 (jtag_dout), // in a 1 device debug
.jtag_dout_3 (jtag_dout), // session. However, Synplify
.jtag_dout_4 (jtag_dout), // etc require all ports are
.jtag_dout_5 (jtag_dout), // connected
.jtag_dout_6 (jtag_dout),
.jtag_dout_7 (jtag_dout));
end //instantiate_loader
endgenerate
//
//
endmodule
//
//
//
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// JTAG Loader
//
///////////////////////////////////////////////////////////////////////////////////////////
//
//
// JTAG Loader 6 - Version 6.00
//
// Kris Chaplin - 4th February 2010
// Nick Sawyer - 3rd March 2011 - Initial conversion to Verilog
// Ken Chapman - 16th August 2011 - Revised coding style
//
`timescale 1ps/1ps
module jtag_loader_6 (picoblaze_reset, jtag_en, jtag_din, jtag_addr, jtag_clk, jtag_we, jtag_dout_0, jtag_dout_1, jtag_dout_2, jtag_dout_3, jtag_dout_4, jtag_dout_5, jtag_dout_6, jtag_dout_7);
//
parameter integer C_JTAG_LOADER_ENABLE = 1;
parameter C_FAMILY = "V6";
parameter integer C_NUM_PICOBLAZE = 1;
parameter integer C_BRAM_MAX_ADDR_WIDTH = 10;
parameter integer C_PICOBLAZE_INSTRUCTION_DATA_WIDTH = 18;
parameter integer C_JTAG_CHAIN = 2;
parameter [4:0] C_ADDR_WIDTH_0 = 10;
parameter [4:0] C_ADDR_WIDTH_1 = 10;
parameter [4:0] C_ADDR_WIDTH_2 = 10;
parameter [4:0] C_ADDR_WIDTH_3 = 10;
parameter [4:0] C_ADDR_WIDTH_4 = 10;
parameter [4:0] C_ADDR_WIDTH_5 = 10;
parameter [4:0] C_ADDR_WIDTH_6 = 10;
parameter [4:0] C_ADDR_WIDTH_7 = 10;
//
output [C_NUM_PICOBLAZE-1:0] picoblaze_reset;
output [C_NUM_PICOBLAZE-1:0] jtag_en;
output [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_din;
output [C_BRAM_MAX_ADDR_WIDTH-1:0] jtag_addr;
output jtag_clk ;
output jtag_we;
input [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_0;
input [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_1;
input [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_2;
input [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_3;
input [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_4;
input [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_5;
input [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_6;
input [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_7;
//
//
wire [2:0] num_picoblaze;
wire [4:0] picoblaze_instruction_data_width;
//
wire drck;
wire shift_clk;
wire shift_din;
wire shift_dout;
wire shift;
wire capture;
//
reg control_reg_ce;
reg [C_NUM_PICOBLAZE-1:0] bram_ce;
wire [C_NUM_PICOBLAZE-1:0] bus_zero;
wire [C_NUM_PICOBLAZE-1:0] jtag_en_int;
wire [7:0] jtag_en_expanded;
reg [C_BRAM_MAX_ADDR_WIDTH-1:0] jtag_addr_int;
reg [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_din_int;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] control_din;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] control_dout;
reg [7:0] control_dout_int;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] bram_dout_int;
reg jtag_we_int;
wire jtag_clk_int;
wire bram_ce_valid;
reg din_load;
//
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_0_masked;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_1_masked;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_2_masked;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_3_masked;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_4_masked;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_5_masked;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_6_masked;
wire [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_7_masked;
reg [C_NUM_PICOBLAZE-1:0] picoblaze_reset_int;
//
initial picoblaze_reset_int = 0;
//
genvar i;
//
generate
for (i = 0; i <= C_NUM_PICOBLAZE-1; i = i+1)
begin : npzero_loop
assign bus_zero[i] = 1'b0;
end
endgenerate
//
generate
//
if (C_JTAG_LOADER_ENABLE == 1)
begin : jtag_loader_gen
//
// Insert BSCAN primitive for target device architecture.
//
if (C_FAMILY == "S6")
begin : BSCAN_SPARTAN6_gen
BSCAN_SPARTAN6 # (.JTAG_CHAIN (C_JTAG_CHAIN))
BSCAN_BLOCK_inst (.CAPTURE (capture),
.DRCK (drck),
.RESET (),
.RUNTEST (),
.SEL (bram_ce_valid),
.SHIFT (shift),
.TCK (),
.TDI (shift_din),
.TMS (),
.UPDATE (jtag_clk_int),
.TDO (shift_dout));
end
//
if (C_FAMILY == "V6")
begin : BSCAN_VIRTEX6_gen
BSCAN_VIRTEX6 # ( .JTAG_CHAIN (C_JTAG_CHAIN),
.DISABLE_JTAG ("FALSE"))
BSCAN_BLOCK_inst (.CAPTURE (capture),
.DRCK (drck),
.RESET (),
.RUNTEST (),
.SEL (bram_ce_valid),
.SHIFT (shift),
.TCK (),
.TDI (shift_din),
.TMS (),
.UPDATE (jtag_clk_int),
.TDO (shift_dout));
end
//
if (C_FAMILY == "7S")
begin : BSCAN_7SERIES_gen
BSCANE2 # ( .JTAG_CHAIN (C_JTAG_CHAIN),
.DISABLE_JTAG ("FALSE"))
BSCAN_BLOCK_inst (.CAPTURE (capture),
.DRCK (drck),
.RESET (),
.RUNTEST (),
.SEL (bram_ce_valid),
.SHIFT (shift),
.TCK (),
.TDI (shift_din),
.TMS (),
.UPDATE (jtag_clk_int),
.TDO (shift_dout));
end
//
// Insert clock buffer to ensure reliable shift operations.
//
BUFG upload_clock (.I (drck), .O (shift_clk));
//
//
// Shift Register
//
always @ (posedge shift_clk) begin
if (shift == 1'b1) begin
control_reg_ce <= shift_din;
end
end
//
always @ (posedge shift_clk) begin
if (shift == 1'b1) begin
bram_ce[0] <= control_reg_ce;
end
end
//
for (i = 0; i <= C_NUM_PICOBLAZE-2; i = i+1)
begin : loop0
if (C_NUM_PICOBLAZE > 1) begin
always @ (posedge shift_clk) begin
if (shift == 1'b1) begin
bram_ce[i+1] <= bram_ce[i];
end
end
end
end
//
always @ (posedge shift_clk) begin
if (shift == 1'b1) begin
jtag_we_int <= bram_ce[C_NUM_PICOBLAZE-1];
end
end
//
always @ (posedge shift_clk) begin
if (shift == 1'b1) begin
jtag_addr_int[0] <= jtag_we_int;
end
end
//
for (i = 0; i <= C_BRAM_MAX_ADDR_WIDTH-2; i = i+1)
begin : loop1
always @ (posedge shift_clk) begin
if (shift == 1'b1) begin
jtag_addr_int[i+1] <= jtag_addr_int[i];
end
end
end
//
always @ (posedge shift_clk) begin
if (din_load == 1'b1) begin
jtag_din_int[0] <= bram_dout_int[0];
end
else if (shift == 1'b1) begin
jtag_din_int[0] <= jtag_addr_int[C_BRAM_MAX_ADDR_WIDTH-1];
end
end
//
for (i = 0; i <= C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-2; i = i+1)
begin : loop2
always @ (posedge shift_clk) begin
if (din_load == 1'b1) begin
jtag_din_int[i+1] <= bram_dout_int[i+1];
end
if (shift == 1'b1) begin
jtag_din_int[i+1] <= jtag_din_int[i];
end
end
end
//
assign shift_dout = jtag_din_int[C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1];
//
//
always @ (bram_ce or din_load or capture or bus_zero or control_reg_ce) begin
if ( bram_ce == bus_zero ) begin
din_load <= capture & control_reg_ce;
end else begin
din_load <= capture;
end
end
//
//
// Control Registers
//
assign num_picoblaze = C_NUM_PICOBLAZE-3'h1;
assign picoblaze_instruction_data_width = C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-5'h01;
//
always @ (posedge jtag_clk_int) begin
if (bram_ce_valid == 1'b1 && jtag_we_int == 1'b0 && control_reg_ce == 1'b1) begin
case (jtag_addr_int[3:0])
0 : // 0 = version - returns (7:4) illustrating number of PB
// and [3:0] picoblaze instruction data width
control_dout_int <= {num_picoblaze, picoblaze_instruction_data_width};
1 : // 1 = PicoBlaze 0 reset / status
if (C_NUM_PICOBLAZE >= 1) begin
control_dout_int <= {picoblaze_reset_int[0], 2'b00, C_ADDR_WIDTH_0-5'h01};
end else begin
control_dout_int <= 8'h00;
end
2 : // 2 = PicoBlaze 1 reset / status
if (C_NUM_PICOBLAZE >= 2) begin
control_dout_int <= {picoblaze_reset_int[1], 2'b00, C_ADDR_WIDTH_1-5'h01};
end else begin
control_dout_int <= 8'h00;
end
3 : // 3 = PicoBlaze 2 reset / status
if (C_NUM_PICOBLAZE >= 3) begin
control_dout_int <= {picoblaze_reset_int[2], 2'b00, C_ADDR_WIDTH_2-5'h01};
end else begin
control_dout_int <= 8'h00;
end
4 : // 4 = PicoBlaze 3 reset / status
if (C_NUM_PICOBLAZE >= 4) begin
control_dout_int <= {picoblaze_reset_int[3], 2'b00, C_ADDR_WIDTH_3-5'h01};
end else begin
control_dout_int <= 8'h00;
end
5: // 5 = PicoBlaze 4 reset / status
if (C_NUM_PICOBLAZE >= 5) begin
control_dout_int <= {picoblaze_reset_int[4], 2'b00, C_ADDR_WIDTH_4-5'h01};
end else begin
control_dout_int <= 8'h00;
end
6 : // 6 = PicoBlaze 5 reset / status
if (C_NUM_PICOBLAZE >= 6) begin
control_dout_int <= {picoblaze_reset_int[5], 2'b00, C_ADDR_WIDTH_5-5'h01};
end else begin
control_dout_int <= 8'h00;
end
7 : // 7 = PicoBlaze 6 reset / status
if (C_NUM_PICOBLAZE >= 7) begin
control_dout_int <= {picoblaze_reset_int[6], 2'b00, C_ADDR_WIDTH_6-5'h01};
end else begin
control_dout_int <= 8'h00;
end
8 : // 8 = PicoBlaze 7 reset / status
if (C_NUM_PICOBLAZE >= 8) begin
control_dout_int <= {picoblaze_reset_int[7], 2'b00, C_ADDR_WIDTH_7-5'h01};
end else begin
control_dout_int <= 8'h00;
end
15 : control_dout_int <= C_BRAM_MAX_ADDR_WIDTH -1;
default : control_dout_int <= 8'h00;
//
endcase
end else begin
control_dout_int <= 8'h00;
end
end
//
assign control_dout[C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-8] = control_dout_int;
//
always @ (posedge jtag_clk_int) begin
if (bram_ce_valid == 1'b1 && jtag_we_int == 1'b1 && control_reg_ce == 1'b1) begin
picoblaze_reset_int[C_NUM_PICOBLAZE-1:0] <= control_din[C_NUM_PICOBLAZE-1:0];
end
end
//
//
// Assignments
//
if (C_PICOBLAZE_INSTRUCTION_DATA_WIDTH > 8) begin
assign control_dout[C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-9:0] = 10'h000;
end
//
// Qualify the blockram CS signal with bscan select output
assign jtag_en_int = (bram_ce_valid) ? bram_ce : bus_zero;
//
assign jtag_en_expanded[C_NUM_PICOBLAZE-1:0] = jtag_en_int;
//
for (i = 7; i >= C_NUM_PICOBLAZE; i = i-1)
begin : loop4
if (C_NUM_PICOBLAZE < 8) begin : jtag_en_expanded_gen
assign jtag_en_expanded[i] = 1'b0;
end
end
//
assign bram_dout_int = control_dout | jtag_dout_0_masked | jtag_dout_1_masked | jtag_dout_2_masked | jtag_dout_3_masked | jtag_dout_4_masked | jtag_dout_5_masked | jtag_dout_6_masked | jtag_dout_7_masked;
//
assign control_din = jtag_din_int;
//
assign jtag_dout_0_masked = (jtag_en_expanded[0]) ? jtag_dout_0 : 18'h00000;
assign jtag_dout_1_masked = (jtag_en_expanded[1]) ? jtag_dout_1 : 18'h00000;
assign jtag_dout_2_masked = (jtag_en_expanded[2]) ? jtag_dout_2 : 18'h00000;
assign jtag_dout_3_masked = (jtag_en_expanded[3]) ? jtag_dout_3 : 18'h00000;
assign jtag_dout_4_masked = (jtag_en_expanded[4]) ? jtag_dout_4 : 18'h00000;
assign jtag_dout_5_masked = (jtag_en_expanded[5]) ? jtag_dout_5 : 18'h00000;
assign jtag_dout_6_masked = (jtag_en_expanded[6]) ? jtag_dout_6 : 18'h00000;
assign jtag_dout_7_masked = (jtag_en_expanded[7]) ? jtag_dout_7 : 18'h00000;
//
assign jtag_en = jtag_en_int;
assign jtag_din = jtag_din_int;
assign jtag_addr = jtag_addr_int;
assign jtag_clk = jtag_clk_int;
assign jtag_we = jtag_we_int;
assign picoblaze_reset = picoblaze_reset_int;
//
end
endgenerate
//
endmodule
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// END OF FILE {name}.v
//
///////////////////////////////////////////////////////////////////////////////////////////
//
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* FIFO
* ====
*
* Implementation notes:
*
* - Read and write pointers are simple ring counters
*
* - Number of items held in FIFO is recorded in shift register
* (Full/empty flags are most and least-significant bits of register)
*
* - Supports input and/or output registers on FIFO
*
* Examples:
*
* fifo_v #(.fifo_elements_t(int), .size(8)) myfifo (.*);
*
* Instantiates a FIFO that can hold up to 8 integers.
*
* fifo_v #(.fifo_elements_t(int), .size(8), .output_reg(1)) myfifo (.*);
*
* Instantiates a FIFO that can hold up to 8 integers with output register
*
* Output Register
* ===============
*
* Instantiate a FIFO of length (size-1) + an output register and bypass logic
*
* output_reg = 0 (default) - no output register
* output_reg = 1 - instantiate a single output register
*
* _
* ______ |\ | |
* _|-[_FIFO_]-->| |__| |__ Out
* |----------->| | |_|
* bypass |/ Reg.
*
*
* Input Register
* ==============
*
* input_reg = 0 (default) - no input register, FIFO receives data directly
* input_reg = 1 - assume **external** input register and bypass logic
* input_reg = 2 - instantiate input register and bypass logic
*
* In case 1. the FIFO is still of length 'size' as it is assumed the external
* input register is always enabled (used when building VC buffers).
*
* _ ______ |\
* | | |-[_FIFO_]-->| |___ Out
* | |__|___________>| |
* |_| |/
* Reg.
*
* Input and Output Registers
* ==========================
*
* Can set input_reg=2, output_reg=1 to create FIFO with both input and output
* registers. FIFO behaviour remains identical at the cycle-level with the
* addition of input/output registers.
*
* InReg OutReg
* _ ______ _
* | |---[_FIFO_]---| |
* | | |____________| |___|\
* |_| | |_| | |__ Out
* |__________________| |
* |/
* FIFO Initialisation
* ===================
*
* init_fifo_contents = 0 - FIFO is empty on reset
* init_fifo_contents = 1 - FIFO is nearly_full on reset (mem[i]=1'b1<<i, mem[size]=0)
* init_fifo_contents = 2 - FIFO is nearly empty on reset (mem[0]=1)
*
*
* ===============================================================================
*/
// other FIFO types: double buffered, two slower FIFOs + output register
// FIFOs with second entry outputs (as required by router)
// pending write input register
//
// - second output with output registers [two output registers?]
//
//`ifdef VCS
//import fifo_package::*;
//`endif
/************************************************************************************
*
* FIFO
*
************************************************************************************/
typedef struct packed
{
logic full, empty, nearly_full, nearly_empty;
logic fast_empty;
} fifov_flags_t;
typedef flit_t fifo_elements_t;
module NW_fifo_v (push, pop, data_in, data_out, second_data_out, flags, clk, rst_n);
// initialise FIFO contents? (usually no initialisation, set to 0)
parameter init_fifo_contents = 0;
// Type of FIFO elements
//parameter type fifo_elements_t = integer ;
//parameter fifo_elements_t = integer ;
// max no. of entries
parameter size = 8;
// opt. delay between clk+ and data becoming valid on output of FIFO?
parameter output_reg = 1;
// external input register and bypass logic? or (2) internal input register
parameter input_reg = 0;
// trade performance for power savings? (may degrade performance in some cases!) - rename late_pop?
parameter low_power = 0;
// need second data out?
parameter generate_second_data_out = 1;
input push, pop;
output fifov_flags_t flags;
input fifo_elements_t data_in;
output fifo_elements_t data_out, second_data_out;
input clk, rst_n;
fifo_elements_t second;
logic is_push, select_bypass, fifo_push, fifo_pop;
fifo_elements_t in_reg, fifo_data_out;
generate
if (input_reg==0) begin
fifo_r #(.init_fifo_contents(init_fifo_contents),
//.fifo_elements_t(fifo_elements_t),
.size(size),
.output_reg(output_reg),
.low_power(low_power)) fifo_r
(push, pop, data_in, data_out, second, clk, rst_n);
end else if (input_reg==1) begin
//
// instantiate FIFO which can be used with *external* input register and bypass
//
fifo_r #(.init_fifo_contents(init_fifo_contents),
//.fifo_elements_t(fifo_elements_t),
.size(size),
.output_reg(output_reg),
.low_power(low_power)) fifo_r
(fifo_push, fifo_pop, data_in, data_out, second, clk, rst_n);
end else if (input_reg==2) begin
//
// instantiate FIFO and input register and bypass
//
fifo_r #(.init_fifo_contents(init_fifo_contents),
// .fifo_elements_t(fifo_elements_t),
.size(size),
.output_reg(output_reg),
.low_power(low_power)) fifo_r
(fifo_push, fifo_pop, in_reg, fifo_data_out, second, clk, rst_n);
//
// instantiate input register and bypass (input_reg==2)
//
always@(posedge clk)
begin
if (!rst_n) begin
in_reg<='0;
end else begin
if (push) begin
in_reg<=data_in;
end else
in_reg<='0; // rdm34
end
end
assign data_out = (select_bypass) ? in_reg : fifo_data_out;
end
endgenerate
generate
//
// if input_reg==0, push and pop are used directly
//
if (!low_power && !(output_reg && input_reg!=0)) begin
/* Always write even if data bypassed FIFO altogether. May reduce router
cycle time in cases where 'fifo_push' is generated late in the clock
cycle. Downside - this wastes energy */
assign fifo_push = is_push;
assign fifo_pop = pop;
end else begin
// only copy input register contents to FIFO if there was a push operation
// and contents didn't bypass FIFO altogether
assign fifo_push = is_push && !(select_bypass && pop);
// similarly for pop, only pop if we aren't bypasses the FIFO
assign fifo_pop = pop && !select_bypass;
end
endgenerate
always@(posedge clk) begin
if (!rst_n) begin
is_push <= 1'b0;
select_bypass <= 1'b1;
end else begin
is_push <= push;
select_bypass <= flags.empty || (flags.nearly_empty && pop);
end
end
/************************************************************************************
* Generate Flags for FIFO (flags are always generated for a FIFO of length 'size')
************************************************************************************/
fifo_flags #(.size(size),
.init_fifo_contents(init_fifo_contents)) genflags
(push, pop, flags, clk, rst_n);
/************************************************************************************
* Need second data out?
************************************************************************************/
generate
if (generate_second_data_out) begin
assign second_data_out = second;
end else begin
assign second_data_out = 'x;
end
endgenerate
endmodule // fifo_v
/************************************************************************************
*
* FIFO + Output Register (if requested)
*
************************************************************************************/
module fifo_r (push, pop, data_in, data_out, second_data_out, clk, rst_n);
// initialise FIFO
parameter init_fifo_contents = 0;
// what does FIFO hold?
//parameter type fifo_elements_t = int ;
// max no. of entries
parameter size = 8;
// opt. delay between clk+ and data becoming valid on output of FIFO?
parameter output_reg = 1;
// trade power for performance
parameter low_power = 0;
// 'always_write'
// regardless of 'push' always write input data to FIFO slot pointed to by write
// pointer (one extra entry is added to FIFO to ensure FIFO data is not overwritten).
parameter always_write = 1'b0; //!low_power;
//==========
input push, pop;
input fifo_elements_t data_in;
output fifo_elements_t data_out, second_data_out;
input clk, rst_n;
fifov_flags_t local_flags;
fifo_elements_t fifo_data_out, second_data;
fifo_elements_t fifo_out_reg;
fifo_elements_t to_reg;
logic bypass, fifo_push, fifo_pop;
generate
if (!output_reg) begin
fifo_buffer #(.init_fifo_contents(init_fifo_contents),
//.fifo_elements_t(fifo_elements_t),
.size(always_write+size), .output_reg(0),
.low_power(low_power), .always_write(always_write))
fifo_buf (push, pop, data_in, data_out, second_data, clk, rst_n);
assign second_data_out = second_data;
end else begin
//
// FIFO + output register
//
fifo_buffer #(.init_fifo_contents(init_fifo_contents),
//.fifo_elements_t(fifo_elements_t),
.size(always_write+size), .output_reg(0), .low_power(low_power),
.always_write(always_write))
fifo_buf (push, pop, data_in, fifo_data_out, second_data, clk, rst_n);
//
// local flags to determine when to bypass, read and write FIFO
//
// *rdm34, better if we could use global flags, are these flags ever on critical path?
//
fifo_flags #(.size(always_write+size),
.init_fifo_contents(init_fifo_contents)) gen_localflags
(push, pop, local_flags, clk, rst_n);
always@(posedge clk) begin
if (!rst_n) begin
// initialise FIFO contents?
if (init_fifo_contents!=0) begin
fifo_out_reg<=1;
end
end else begin
fifo_out_reg<=to_reg;
/*
if (local_flags.empty || (local_flags.nearly_empty && pop)) begin
if (push) begin
fifo_out_reg<=data_in;
end else begin
// fifo_out_reg<='0; // FIFO is empty
end
end else if (pop) begin
fifo_out_reg<=second_data;
end else begin
fifo_out_reg<=fifo_data_out;
end
*/
end // else: !if(!rst_n)
end // always@ (posedge clk)
// select data to write to fifo_out_reg
always_comb
begin
if (local_flags.empty || (local_flags.nearly_empty && pop)) begin
if (push) begin
to_reg = data_in;
end else begin
// FIFO is empty
//if (init_fifo_contents!=0) to_reg='0; else to_reg='x;
to_reg = '0;
end
end else if (pop) begin
to_reg = second_data;
end else begin
to_reg = fifo_data_out;
end
end
assign data_out = fifo_out_reg;
assign second_data_out = second_data;
end
endgenerate
endmodule // fifo_r
/************************************************************************************
*
* Maintain FIFO flags (full, nearly_full, nearly_empty and empty)
*
* This design uses a shift register to ensure flags are available quickly.
*
************************************************************************************/
module fifo_flags (push, pop, flags, clk, rst_n);
input push, pop;
output fifov_flags_t flags;
input clk, rst_n;
parameter size = 8;
parameter init_fifo_contents = 0;
reg [size:0] counter; // counter must hold 1..size + empty state
logic was_push, was_pop;
fifov_flags_t flags_reg;
logic add, sub, same;
logic fast_empty;
/*
* maintain flags
*
*
* maintain shift register as counter to determine if FIFO is full or empty
* full=counter[size-1], empty=counter[0], etc..
* init: counter=1'b1;
* (push & !pop): shift left
* (pop & !push): shift right
*/
always@(posedge clk) begin
if (!rst_n) begin
//
// initialise flags counter on reset
//
if (init_fifo_contents==2) begin
// nearly_empty
counter<={{(size-1){1'b0}},2'b10};
end else if (init_fifo_contents==1) begin
// nearly_full
counter<={2'b01,{(size-1){1'b0}}};
end else begin
// empty
counter<={{size{1'b0}},1'b1};
end
was_push<=1'b0;
was_pop<=1'b0;
fast_empty <=1'b1;
end else begin
if (add) begin
assert (counter!={1'b1,{size{1'b0}}}) else $fatal;
counter <= {counter[size-1:0], 1'b0};
end else if (sub) begin
assert (counter!={{size{1'b0}},1'b1}) else $fatal;
counter <= {1'b0, counter[size:1]};
end
assert (counter!=0) else $fatal;
was_push<=push;
was_pop<=pop;
assert (push!==1'bx) else $fatal;
assert (pop!==1'bx) else $fatal;
fast_empty <= (flags.empty && !push && !pop) || (flags.nearly_empty && pop && !push);
end // else: !if(!rst_n)
end
assign add = was_push && !was_pop;
assign sub = was_pop && !was_push;
assign same = !(add || sub);
assign flags.full = (counter[size] && !sub) || (counter[size-1] && add);
assign flags.empty = (counter[0] && !add) || (counter[1] && sub);
assign flags.nearly_full = (counter[size-1:0] && same) || (counter[size] && sub) || (counter[size-2] && add);
assign flags.nearly_empty = (counter[1] && same) || (counter[0] && add) || (counter[2] && sub);
assign flags.fast_empty = fast_empty;
/*
always@(posedge clk) begin
if (size>3) begin
if (rst_n) begin
if ((flags.full && flags.empty)||
(flags.full && flags.nearly_empty)||
(flags.full && flags.nearly_full)||
(flags.nearly_full && flags.nearly_empty) ||
(flags.nearly_full && flags.empty) ||
(flags.nearly_empty && flags.empty)) begin
$display ("%d: %m", $time);
$display ("flags.full =%b", flags.full);
$display ("flags.nfull=%b (counter[size, -1, -2]=%b, %b, %b)",
flags.nearly_full, counter[size], counter[size-1], counter[size-2]);
$display ("flags.nempt=%b", flags.nearly_empty);
$display ("flags.empt =%b", flags.empty);
$display ("Counter=%b", counter);
end
end
end
end
*/
endmodule // fifo_flags
/************************************************************************************
*
* Simple core FIFO module
*
************************************************************************************/
module fifo_buffer (push, pop, data_in, data_out, second_data_out, clk, rst_n);
// initialise FIFO
parameter init_fifo_contents = 0;
// what does FIFO hold?
//parameter type fifo_elements_t = logic ;
// max no. of entries
parameter int unsigned size = 4;
// part of fast read FIFO?
parameter output_reg = 0;
// trade power for performance
parameter low_power = 0;
// write input data to FIFO[wt_ptr] every clock cycle regardless of 'push'
parameter always_write = 0;
input push, pop;
input fifo_elements_t data_in;
output fifo_elements_t data_out;
output fifo_elements_t second_data_out;
input clk, rst_n;
// reg [size-1:0] rd_ptr, wt_ptr;
logic unsigned [size-1:0] rd_ptr, wt_ptr;
fifo_elements_t fifo_mem[0:size-1];
logic select_bypass;
integer i,j;
always@(posedge clk) begin
assert (size>=2) else $fatal();
if (!rst_n) begin
//
// reset read and write pointers
//
if ((init_fifo_contents==2)&&(output_reg==0)) begin
// initialise with single entry set to 1
fifo_mem[0]<=1;
rd_ptr<={{size-1{1'b0}},1'b1};
wt_ptr <= {{size-2{1'b0}},2'b10};
end else if (init_fifo_contents==1) begin
// initialise FIFO full (contents 1'b1<<(i+output_reg))
for (i=0; i<size-1; i=i+1) begin
fifo_mem[i]<=1'b1<<(i+output_reg);
end
rd_ptr<={{size-1{1'b0}},1'b1};
wt_ptr<={1'b1,{size-1{1'b0}}};
end else begin
//
// initialise empty FIFO
//
rd_ptr<={{size-1{1'b0}},1'b1};
wt_ptr<={{size-1{1'b0}},1'b1};
end
end else begin
if (push || always_write) begin
// enqueue new data
for (i=0; i<size; i++) begin
if (wt_ptr[i]==1'b1) begin
fifo_mem[i] <= data_in;
end
end
end
if (push) begin
// rotate write pointer
wt_ptr <= {wt_ptr[size-2:0], wt_ptr[size-1]};
end
if (pop) begin
// rotate read pointer
rd_ptr <= {rd_ptr[size-2:0], rd_ptr[size-1]};
end
end // else: !if(!rst_n)
end // always@ (posedge clk)
/*
*
* FIFO output is item pointed to by read pointer
*
*/
always_comb begin
//
// one bit of read pointer is always set, ensure synthesis tool
// doesn't add logic to force a default
//
data_out = 'x;
second_data_out ='x;
for (j=0; j<size; j++) begin
if (rd_ptr[j]==1'b1) begin
// output entry pointed to by read pointer
data_out = fifo_mem[j];
// output next entry after head
if ((j+1)==size) begin
second_data_out = fifo_mem[0];
end else begin
second_data_out = fifo_mem[j+1];
end
end
end
end
endmodule // fifo_buffer
|
(* This program is free software; you can redistribute it and/or *)
(* modify it under the terms of the GNU Lesser General Public License *)
(* as published by the Free Software Foundation; either version 2.1 *)
(* of the License, or (at your option) any later version. *)
(* *)
(* This program is distributed in the hope that it will be useful, *)
(* but WITHOUT ANY WARRANTY; without even the implied warranty of *)
(* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *)
(* GNU General Public License for more details. *)
(* *)
(* You should have received a copy of the GNU Lesser General Public *)
(* License along with this program; if not, write to the Free *)
(* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA *)
(* 02110-1301 USA *)
(** This file includes random facts about Integers (and natural numbers) which are not found in the standard library. Some of the lemma here are not used in the QArith developement but are rather useful.
*)
Require Export ZArith.
Require Export ZArithRing.
Tactic Notation "ElimCompare" constr(c) constr(d) := elim_compare c d.
Ltac Flip :=
apply Zgt_lt || apply Zlt_gt || apply Zle_ge || apply Zge_le; assumption.
Ltac Falsum :=
try intro; apply False_ind;
repeat
match goal with
| id1:(~ ?X1) |- ?X2 =>
(apply id1; assumption || reflexivity) || clear id1
end.
Ltac Step_l a :=
match goal with
| |- (?X1 < ?X2)%Z => replace X1 with a; [ idtac | try ring ]
end.
Ltac Step_r a :=
match goal with
| |- (?X1 < ?X2)%Z => replace X2 with a; [ idtac | try ring ]
end.
Ltac CaseEq formula :=
generalize (refl_equal formula); pattern formula at -1 in |- *;
case formula.
Lemma pair_1 : forall (A B : Set) (H : A * B), H = pair (fst H) (snd H).
Proof.
intros.
case H.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma pair_2 :
forall (A B : Set) (H1 H2 : A * B),
fst H1 = fst H2 -> snd H1 = snd H2 -> H1 = H2.
Proof.
intros A B H1 H2.
case H1.
case H2.
simpl in |- *.
intros.
rewrite H.
rewrite H0.
reflexivity.
Qed.
Section projection.
Variable A : Set.
Variable P : A -> Prop.
Definition projP1 (H : sig P) := let (x, h) := H in x.
Definition projP2 (H : sig P) :=
let (x, h) as H return (P (projP1 H)) := H in h.
End projection.
(*###########################################################################*)
(* Declaring some realtions on natural numbers for stepl and stepr tactics. *)
(*###########################################################################*)
Lemma le_stepl: forall x y z, le x y -> x=z -> le z y.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma le_stepr: forall x y z, le x y -> y=z -> le x z.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma lt_stepl: forall x y z, lt x y -> x=z -> lt z y.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma lt_stepr: forall x y z, lt x y -> y=z -> lt x z.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma neq_stepl:forall (x y z:nat), x<>y -> x=z -> z<>y.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Lemma neq_stepr:forall (x y z:nat), x<>y -> y=z -> x<>z.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Declare Left Step le_stepl.
Declare Right Step le_stepr.
Declare Left Step lt_stepl.
Declare Right Step lt_stepr.
Declare Left Step neq_stepl.
Declare Right Step neq_stepr.
(*###########################################################################*)
(** Some random facts about natural numbers, positive numbers and integers *)
(*###########################################################################*)
Lemma not_O_S : forall n : nat, n <> 0 -> {p : nat | n = S p}.
Proof.
intros [| np] Hn; [ exists 0; apply False_ind; apply Hn | exists np ];
reflexivity.
Qed.
Lemma lt_minus_neq : forall m n : nat, m < n -> n - m <> 0.
Proof.
intros.
omega.
Qed.
Lemma lt_minus_eq_0 : forall m n : nat, m < n -> m - n = 0.
Proof.
intros.
omega.
Qed.
Lemma le_plus_Sn_1_SSn : forall n : nat, S n + 1 <= S (S n).
Proof.
intros.
omega.
Qed.
Lemma le_plus_O_l : forall p q : nat, p + q <= 0 -> p = 0.
Proof.
intros; omega.
Qed.
Lemma le_plus_O_r : forall p q : nat, p + q <= 0 -> q = 0.
Proof.
intros; omega.
Qed.
Lemma minus_pred : forall m n : nat, 0 < n -> pred m - pred n = m - n.
Proof.
intros.
omega.
Qed.
(*###########################################################################*)
(* Declaring some realtions on integers for stepl and stepr tactics. *)
(*###########################################################################*)
Lemma Zle_stepl: forall x y z, (x<=y)%Z -> x=z -> (z<=y)%Z.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma Zle_stepr: forall x y z, (x<=y)%Z -> y=z -> (x<=z)%Z.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma Zlt_stepl: forall x y z, (x<y)%Z -> x=z -> (z<y)%Z.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma Zlt_stepr: forall x y z, (x<y)%Z -> y=z -> (x<z)%Z.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma Zneq_stepl:forall (x y z:Z), (x<>y)%Z -> x=z -> (z<>y)%Z.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Lemma Zneq_stepr:forall (x y z:Z), (x<>y)%Z -> y=z -> (x<>z)%Z.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Declare Left Step Zle_stepl.
Declare Right Step Zle_stepr.
Declare Left Step Zlt_stepl.
Declare Right Step Zlt_stepr.
Declare Left Step Zneq_stepl.
Declare Right Step Zneq_stepr.
(*###########################################################################*)
(** Informative case analysis *)
(*###########################################################################*)
Lemma Zlt_cotrans :
forall x y : Z, (x < y)%Z -> forall z : Z, {(x < z)%Z} + {(z < y)%Z}.
Proof.
intros.
case (Z_lt_ge_dec x z).
intro.
left.
assumption.
intro.
right.
apply Zle_lt_trans with (m := x).
apply Zge_le.
assumption.
assumption.
Qed.
Lemma Zlt_cotrans_pos :
forall x y : Z, (0 < x + y)%Z -> {(0 < x)%Z} + {(0 < y)%Z}.
Proof.
intros.
case (Zlt_cotrans 0 (x + y) H x).
intro.
left.
assumption.
intro.
right.
apply Zplus_lt_reg_l with (p := x).
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zlt_cotrans_neg :
forall x y : Z, (x + y < 0)%Z -> {(x < 0)%Z} + {(y < 0)%Z}.
Proof.
intros x y H; case (Zlt_cotrans (x + y) 0 H x); intro Hxy;
[ right; apply Zplus_lt_reg_l with (p := x); rewrite Zplus_0_r | left ];
assumption.
Qed.
Lemma not_Zeq_inf : forall x y : Z, x <> y -> {(x < y)%Z} + {(y < x)%Z}.
Proof.
intros.
case Z_lt_ge_dec with x y.
intro.
left.
assumption.
intro H0.
generalize (Zge_le _ _ H0).
intro.
case (Z_le_lt_eq_dec _ _ H1).
intro.
right.
assumption.
intro.
apply False_rec.
apply H.
symmetry in |- *.
assumption.
Qed.
Lemma Z_dec : forall x y : Z, {(x < y)%Z} + {(x > y)%Z} + {x = y}.
Proof.
intros.
case (Z_lt_ge_dec x y).
intro H.
left.
left.
assumption.
intro H.
generalize (Zge_le _ _ H).
intro H0.
case (Z_le_lt_eq_dec y x H0).
intro H1.
left.
right.
apply Zlt_gt.
assumption.
intro.
right.
symmetry in |- *.
assumption.
Qed.
Lemma Z_dec' : forall x y : Z, {(x < y)%Z} + {(y < x)%Z} + {x = y}.
Proof.
intros x y.
case (Z_eq_dec x y); intro H;
[ right; assumption | left; apply (not_Zeq_inf _ _ H) ].
Qed.
Lemma Z_lt_le_dec : forall x y : Z, {(x < y)%Z} + {(y <= x)%Z}.
Proof.
intros.
case (Z_lt_ge_dec x y).
intro.
left.
assumption.
intro.
right.
apply Zge_le.
assumption.
Qed.
Lemma Z_le_lt_dec : forall x y : Z, {(x <= y)%Z} + {(y < x)%Z}.
Proof.
intros; case (Z_lt_le_dec y x); [ right | left ]; assumption.
Qed.
Lemma Z_lt_lt_S_eq_dec :
forall x y : Z, (x < y)%Z -> {(x + 1 < y)%Z} + {(x + 1)%Z = y}.
Proof.
intros.
generalize (Zlt_le_succ _ _ H).
unfold Zsucc in |- *.
apply Z_le_lt_eq_dec.
Qed.
Lemma quadro_leq_inf :
forall a b c d : Z,
{(c <= a)%Z /\ (d <= b)%Z} + {~ ((c <= a)%Z /\ (d <= b)%Z)}.
Proof.
intros.
case (Z_lt_le_dec a c).
intro z.
right.
intro.
elim H.
intros.
generalize z.
apply Zle_not_lt.
assumption.
intro.
case (Z_lt_le_dec b d).
intro z0.
right.
intro.
elim H.
intros.
generalize z0.
apply Zle_not_lt.
assumption.
intro.
left.
split.
assumption.
assumption.
Qed.
(*###########################################################################*)
(** General auxiliary lemmata *)
(*###########################################################################*)
Lemma Zminus_eq : forall x y : Z, (x - y)%Z = 0%Z -> x = y.
Proof.
intros.
apply Zplus_reg_l with (- y)%Z.
rewrite Zplus_opp_l.
unfold Zminus in H.
rewrite Zplus_comm.
assumption.
Qed.
Lemma Zlt_minus : forall a b : Z, (b < a)%Z -> (0 < a - b)%Z.
Proof.
intros a b.
intros.
apply Zplus_lt_reg_l with b.
unfold Zminus in |- *.
rewrite (Zplus_comm a).
rewrite (Zplus_assoc b (- b)).
rewrite Zplus_opp_r.
simpl in |- *.
rewrite <- Zplus_0_r_reverse.
assumption.
Qed.
Lemma Zle_minus : forall a b : Z, (b <= a)%Z -> (0 <= a - b)%Z.
Proof.
intros a b.
intros.
apply Zplus_le_reg_l with b.
unfold Zminus in |- *.
rewrite (Zplus_comm a).
rewrite (Zplus_assoc b (- b)).
rewrite Zplus_opp_r.
simpl in |- *.
rewrite <- Zplus_0_r_reverse.
assumption.
Qed.
Lemma Zlt_plus_plus :
forall m n p q : Z, (m < n)%Z -> (p < q)%Z -> (m + p < n + q)%Z.
Proof.
intros.
apply Zlt_trans with (m := (n + p)%Z).
rewrite Zplus_comm.
rewrite Zplus_comm with (n := n).
apply Zplus_lt_compat_l.
assumption.
apply Zplus_lt_compat_l.
assumption.
Qed.
Lemma Zgt_plus_plus :
forall m n p q : Z, (m > n)%Z -> (p > q)%Z -> (m + p > n + q)%Z.
intros.
apply Zgt_trans with (m := (n + p)%Z).
rewrite Zplus_comm.
rewrite Zplus_comm with (n := n).
apply Zplus_gt_compat_l.
assumption.
apply Zplus_gt_compat_l.
assumption.
Qed.
Lemma Zle_lt_plus_plus :
forall m n p q : Z, (m <= n)%Z -> (p < q)%Z -> (m + p < n + q)%Z.
Proof.
intros.
case (Zle_lt_or_eq m n).
assumption.
intro.
apply Zlt_plus_plus.
assumption.
assumption.
intro.
rewrite H1.
apply Zplus_lt_compat_l.
assumption.
Qed.
Lemma Zge_gt_plus_plus :
forall m n p q : Z, (m >= n)%Z -> (p > q)%Z -> (m + p > n + q)%Z.
Proof.
intros.
case (Zle_lt_or_eq n m).
apply Zge_le.
assumption.
intro.
apply Zgt_plus_plus.
apply Zlt_gt.
assumption.
assumption.
intro.
rewrite H1.
apply Zplus_gt_compat_l.
assumption.
Qed.
Lemma Zgt_ge_plus_plus :
forall m n p q : Z, (m > n)%Z -> (p >= q)%Z -> (m + p > n + q)%Z.
Proof.
intros.
rewrite Zplus_comm.
replace (n + q)%Z with (q + n)%Z.
apply Zge_gt_plus_plus.
assumption.
assumption.
apply Zplus_comm.
Qed.
Lemma Zlt_resp_pos : forall x y : Z, (0 < x)%Z -> (0 < y)%Z -> (0 < x + y)%Z.
Proof.
intros.
rewrite <- Zplus_0_r with 0%Z.
apply Zlt_plus_plus; assumption.
Qed.
Lemma Zle_resp_neg :
forall x y : Z, (x <= 0)%Z -> (y <= 0)%Z -> (x + y <= 0)%Z.
Proof.
intros.
rewrite <- Zplus_0_r with 0%Z.
apply Zplus_le_compat; assumption.
Qed.
Lemma Zlt_pos_opp : forall x : Z, (0 < x)%Z -> (- x < 0)%Z.
Proof.
intros.
apply Zplus_lt_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zlt_neg_opp : forall x : Z, (x < 0)%Z -> (0 < - x)%Z.
Proof.
intros.
apply Zplus_lt_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zle_neg_opp : forall x : Z, (x <= 0)%Z -> (0 <= - x)%Z.
Proof.
intros.
apply Zplus_le_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zle_pos_opp : forall x : Z, (0 <= x)%Z -> (- x <= 0)%Z.
Proof.
intros.
apply Zplus_le_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zge_opp : forall x y : Z, (x <= y)%Z -> (- x >= - y)%Z.
Proof.
intros.
apply Zle_ge.
apply Zplus_le_reg_l with (p := (x + y)%Z).
ring_simplify (x + y + - y)%Z (x + y + - x)%Z.
assumption.
Qed.
(* Omega can't solve this *)
Lemma Zmult_pos_pos : forall x y : Z, (0 < x)%Z -> (0 < y)%Z -> (0 < x * y)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Lemma Zmult_neg_neg : forall x y : Z, (x < 0)%Z -> (y < 0)%Z -> (0 < x * y)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Lemma Zmult_neg_pos : forall x y : Z, (x < 0)%Z -> (0 < y)%Z -> (x * y < 0)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Lemma Zmult_pos_neg : forall x y : Z, (0 < x)%Z -> (y < 0)%Z -> (x * y < 0)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Hint Resolve Zmult_pos_pos Zmult_neg_neg Zmult_neg_pos Zmult_pos_neg: zarith.
Lemma Zle_reg_mult_l :
forall x y a : Z, (0 < a)%Z -> (x <= y)%Z -> (a * x <= a * y)%Z.
Proof.
intros.
apply Zplus_le_reg_l with (p := (- a * x)%Z).
ring_simplify (- a * x + a * x)%Z.
replace (- a * x + a * y)%Z with ((y - x) * a)%Z.
apply Zmult_gt_0_le_0_compat.
apply Zlt_gt.
assumption.
unfold Zminus in |- *.
apply Zle_left.
assumption.
ring.
Qed.
Lemma Zsimpl_plus_l_dep :
forall x y m n : Z, (x + m)%Z = (y + n)%Z -> x = y -> m = n.
Proof.
intros.
apply Zplus_reg_l with x.
rewrite <- H0 in H.
assumption.
Qed.
Lemma Zsimpl_plus_r_dep :
forall x y m n : Z, (m + x)%Z = (n + y)%Z -> x = y -> m = n.
Proof.
intros.
apply Zplus_reg_l with x.
rewrite Zplus_comm.
rewrite Zplus_comm with x n.
rewrite <- H0 in H.
assumption.
Qed.
Lemma Zmult_simpl :
forall n m p q : Z, n = m -> p = q -> (n * p)%Z = (m * q)%Z.
Proof.
intros.
rewrite H.
rewrite H0.
reflexivity.
Qed.
Lemma Zsimpl_mult_l :
forall n m p : Z, n <> 0%Z -> (n * m)%Z = (n * p)%Z -> m = p.
Proof.
intros.
apply Zplus_reg_l with (n := (- p)%Z).
replace (- p + p)%Z with 0%Z.
apply Zmult_integral_l with (n := n).
assumption.
replace ((- p + m) * n)%Z with (n * m + - (n * p))%Z.
apply Zegal_left.
assumption.
ring.
ring.
Qed.
Lemma Zlt_reg_mult_l :
forall x y z : Z, (x > 0)%Z -> (y < z)%Z -> (x * y < x * z)%Z. (*QA*)
Proof.
intros.
case (Zcompare_Gt_spec x 0).
unfold Zgt in H.
assumption.
intros.
cut (x = Zpos x0).
intro.
rewrite H2.
unfold Zlt in H0.
unfold Zlt in |- *.
cut ((Zpos x0 * y ?= Zpos x0 * z)%Z = (y ?= z)%Z).
intro.
exact (trans_eq H3 H0).
apply Zcompare_mult_compat.
cut (x = (x + - (0))%Z).
intro.
exact (trans_eq H2 H1).
simpl in |- *.
apply (sym_eq (A:=Z)).
exact (Zplus_0_r x).
Qed.
Lemma Zlt_opp : forall x y : Z, (x < y)%Z -> (- x > - y)%Z. (*QA*)
Proof.
intros.
red in |- *.
apply sym_eq.
cut (Datatypes.Gt = (y ?= x)%Z).
intro.
cut ((y ?= x)%Z = (- x ?= - y)%Z).
intro.
exact (trans_eq H0 H1).
exact (Zcompare_opp y x).
apply sym_eq.
exact (Zlt_gt x y H).
Qed.
Lemma Zlt_conv_mult_l :
forall x y z : Z, (x < 0)%Z -> (y < z)%Z -> (x * y > x * z)%Z. (*QA*)
Proof.
intros.
cut (- x > 0)%Z.
intro.
cut (- x * y < - x * z)%Z.
intro.
cut (- (- x * y) > - (- x * z))%Z.
intro.
cut (- - (x * y) > - - (x * z))%Z.
intro.
cut ((- - (x * y))%Z = (x * y)%Z).
intro.
rewrite H5 in H4.
cut ((- - (x * z))%Z = (x * z)%Z).
intro.
rewrite H6 in H4.
assumption.
exact (Zopp_involutive (x * z)).
exact (Zopp_involutive (x * y)).
cut ((- (- x * y))%Z = (- - (x * y))%Z).
intro.
rewrite H4 in H3.
cut ((- (- x * z))%Z = (- - (x * z))%Z).
intro.
rewrite H5 in H3.
assumption.
cut ((- x * z)%Z = (- (x * z))%Z).
intro.
exact (f_equal Zopp H5).
exact (Zopp_mult_distr_l_reverse x z).
cut ((- x * y)%Z = (- (x * y))%Z).
intro.
exact (f_equal Zopp H4).
exact (Zopp_mult_distr_l_reverse x y).
exact (Zlt_opp (- x * y) (- x * z) H2).
exact (Zlt_reg_mult_l (- x) y z H1 H0).
exact (Zlt_opp x 0 H).
Qed.
Lemma Zgt_not_eq : forall x y : Z, (x > y)%Z -> x <> y. (*QA*)
Proof.
intros.
cut (y < x)%Z.
intro.
cut (y <> x).
intro.
red in |- *.
intros.
cut (y = x).
intros.
apply H1.
assumption.
exact (sym_eq H2).
exact (Zorder.Zlt_not_eq y x H0).
exact (Zgt_lt x y H).
Qed.
Lemma Zmult_resp_nonzero :
forall x y : Z, x <> 0%Z -> y <> 0%Z -> (x * y)%Z <> 0%Z.
Proof.
intros x y Hx Hy Hxy.
apply Hx.
apply Zmult_integral_l with y; assumption.
Qed.
Lemma Zopp_app : forall y : Z, y <> 0%Z -> (- y)%Z <> 0%Z.
Proof.
intros.
intro.
apply H.
apply Zplus_reg_l with (- y)%Z.
rewrite Zplus_opp_l.
rewrite H0.
simpl in |- *.
reflexivity.
Qed.
Lemma Zle_neq_Zlt : forall a b : Z, (a <= b)%Z -> b <> a -> (a < b)%Z.
Proof.
intros a b H H0.
case (Z_le_lt_eq_dec _ _ H); trivial.
intro; apply False_ind; apply H0; symmetry in |- *; assumption.
Qed.
Lemma not_Zle_lt : forall x y : Z, ~ (y <= x)%Z -> (x < y)%Z.
Proof.
intros; apply Zgt_lt; apply Znot_le_gt; assumption.
Qed.
Lemma not_Zlt : forall x y : Z, ~ (y < x)%Z -> (x <= y)%Z.
Proof.
intros x y H1 H2; apply H1; apply Zgt_lt; assumption.
Qed.
Lemma Zmult_absorb :
forall x y z : Z, x <> 0%Z -> (x * y)%Z = (x * z)%Z -> y = z. (*QA*)
Proof.
intros.
case (dec_eq y z).
intro.
assumption.
intro.
case (not_Zeq y z).
assumption.
intro.
case (not_Zeq x 0).
assumption.
intro.
apply False_ind.
cut (x * y > x * z)%Z.
intro.
cut ((x * y)%Z <> (x * z)%Z).
intro.
apply H5.
assumption.
exact (Zgt_not_eq (x * y) (x * z) H4).
exact (Zlt_conv_mult_l x y z H3 H2).
intro.
apply False_ind.
cut (x * y < x * z)%Z.
intro.
cut ((x * y)%Z <> (x * z)%Z).
intro.
apply H5.
assumption.
exact (Zorder.Zlt_not_eq (x * y) (x * z) H4).
cut (x > 0)%Z.
intro.
exact (Zlt_reg_mult_l x y z H4 H2).
exact (Zlt_gt 0 x H3).
intro.
apply False_ind.
cut (x * z < x * y)%Z.
intro.
cut ((x * z)%Z <> (x * y)%Z).
intro.
apply H4.
apply (sym_eq (A:=Z)).
assumption.
exact (Zorder.Zlt_not_eq (x * z) (x * y) H3).
apply False_ind.
case (not_Zeq x 0).
assumption.
intro.
cut (x * z > x * y)%Z.
intro.
cut ((x * z)%Z <> (x * y)%Z).
intro.
apply H5.
apply (sym_eq (A:=Z)).
assumption.
exact (Zgt_not_eq (x * z) (x * y) H4).
exact (Zlt_conv_mult_l x z y H3 H2).
intro.
cut (x * z < x * y)%Z.
intro.
cut ((x * z)%Z <> (x * y)%Z).
intro.
apply H5.
apply (sym_eq (A:=Z)).
assumption.
exact (Zorder.Zlt_not_eq (x * z) (x * y) H4).
cut (x > 0)%Z.
intro.
exact (Zlt_reg_mult_l x z y H4 H2).
exact (Zlt_gt 0 x H3).
Qed.
Lemma Zlt_mult_mult :
forall a b c d : Z,
(0 < a)%Z -> (0 < d)%Z -> (a < b)%Z -> (c < d)%Z -> (a * c < b * d)%Z.
Proof.
intros.
apply Zlt_trans with (a * d)%Z.
apply Zlt_reg_mult_l.
Flip.
assumption.
rewrite Zmult_comm.
rewrite Zmult_comm with b d.
apply Zlt_reg_mult_l.
Flip.
assumption.
Qed.
Lemma Zgt_mult_conv_absorb_l :
forall a x y : Z, (a < 0)%Z -> (a * x > a * y)%Z -> (x < y)%Z. (*QC*)
Proof.
intros.
case (dec_eq x y).
intro.
apply False_ind.
rewrite H1 in H0.
cut ((a * y)%Z = (a * y)%Z).
change ((a * y)%Z <> (a * y)%Z) in |- *.
apply Zgt_not_eq.
assumption.
trivial.
intro.
case (not_Zeq x y H1).
trivial.
intro.
apply False_ind.
cut (a * y > a * x)%Z.
apply Zgt_asym with (m := (a * y)%Z) (n := (a * x)%Z).
assumption.
apply Zlt_conv_mult_l.
assumption.
assumption.
Qed.
Lemma Zgt_mult_reg_absorb_l :
forall a x y : Z, (a > 0)%Z -> (a * x > a * y)%Z -> (x > y)%Z. (*QC*)
Proof.
intros.
cut (- - a > - - (0))%Z.
intro.
cut (- a < - (0))%Z.
simpl in |- *.
intro.
replace x with (- - x)%Z.
replace y with (- - y)%Z.
apply Zlt_opp.
apply Zgt_mult_conv_absorb_l with (a := (- a)%Z) (x := (- x)%Z).
assumption.
rewrite Zmult_opp_opp.
rewrite Zmult_opp_opp.
assumption.
apply Zopp_involutive.
apply Zopp_involutive.
apply Zgt_lt.
apply Zlt_opp.
apply Zgt_lt.
assumption.
simpl in |- *.
rewrite Zopp_involutive.
assumption.
Qed.
Lemma Zopp_Zlt : forall x y : Z, (y < x)%Z -> (- x < - y)%Z.
Proof.
intros x y Hyx.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
replace (-1 * - y)%Z with y.
replace (-1 * - x)%Z with x.
Flip.
ring.
ring.
Qed.
Lemma Zmin_cancel_Zlt : forall x y : Z, (- x < - y)%Z -> (y < x)%Z.
Proof.
intros.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
replace (-1 * y)%Z with (- y)%Z.
replace (-1 * x)%Z with (- x)%Z.
apply Zlt_gt.
assumption.
ring.
ring.
Qed.
Lemma Zmult_cancel_Zle :
forall a x y : Z, (a < 0)%Z -> (a * x <= a * y)%Z -> (y <= x)%Z.
Proof.
intros.
case (Z_le_gt_dec y x).
trivial.
intro.
apply False_ind.
apply (Zlt_irrefl (a * x)).
apply Zle_lt_trans with (m := (a * y)%Z).
assumption.
apply Zgt_lt.
apply Zlt_conv_mult_l.
assumption.
apply Zgt_lt.
assumption.
Qed.
Lemma Zlt_mult_cancel_l :
forall x y z : Z, (0 < x)%Z -> (x * y < x * z)%Z -> (y < z)%Z.
Proof.
intros.
apply Zgt_lt.
apply Zgt_mult_reg_absorb_l with x.
apply Zlt_gt.
assumption.
apply Zlt_gt.
assumption.
Qed.
Lemma Zmin_cancel_Zle : forall x y : Z, (- x <= - y)%Z -> (y <= x)%Z.
Proof.
intros.
apply Zmult_cancel_Zle with (a := (-1)%Z).
constructor.
replace (-1 * y)%Z with (- y)%Z.
replace (-1 * x)%Z with (- x)%Z.
assumption.
ring.
ring.
Qed.
Lemma Zmult_resp_Zle :
forall a x y : Z, (0 < a)%Z -> (a * y <= a * x)%Z -> (y <= x)%Z.
Proof.
intros.
case (Z_le_gt_dec y x).
trivial.
intro.
apply False_ind.
apply (Zlt_irrefl (a * y)).
apply Zle_lt_trans with (m := (a * x)%Z).
assumption.
apply Zlt_reg_mult_l.
apply Zlt_gt.
assumption.
apply Zgt_lt.
assumption.
Qed.
Lemma Zopp_Zle : forall x y : Z, (y <= x)%Z -> (- x <= - y)%Z.
Proof.
intros.
apply Zmult_cancel_Zle with (a := (-1)%Z).
constructor.
replace (-1 * - y)%Z with y.
replace (-1 * - x)%Z with x.
assumption.
clear y H; ring.
clear x H; ring.
Qed.
Lemma Zle_lt_eq_S : forall x y : Z, (x <= y)%Z -> (y < x + 1)%Z -> y = x.
Proof.
intros.
case (Z_le_lt_eq_dec x y H).
intro H1.
apply False_ind.
generalize (Zlt_le_succ x y H1).
intro.
apply (Zlt_not_le y (x + 1) H0).
replace (x + 1)%Z with (Zsucc x).
assumption.
reflexivity.
intro H1.
symmetry in |- *.
assumption.
Qed.
Lemma Zlt_le_eq_S :
forall x y : Z, (x < y)%Z -> (y <= x + 1)%Z -> y = (x + 1)%Z.
Proof.
intros.
case (Z_le_lt_eq_dec y (x + 1) H0).
intro H1.
apply False_ind.
generalize (Zlt_le_succ x y H).
intro.
apply (Zlt_not_le y (x + 1) H1).
replace (x + 1)%Z with (Zsucc x).
assumption.
reflexivity.
trivial.
Qed.
Lemma double_not_equal_zero :
forall c d : Z, ~ (c = 0%Z /\ d = 0%Z) -> c <> d \/ c <> 0%Z.
Proof.
intros.
case (Z_zerop c).
intro.
rewrite e.
left.
apply sym_not_eq.
intro.
apply H; repeat split; assumption.
intro; right; assumption.
Qed.
Lemma triple_not_equal_zero :
forall a b c : Z,
~ (a = 0%Z /\ b = 0%Z /\ c = 0%Z) -> a <> 0%Z \/ b <> 0%Z \/ c <> 0%Z.
Proof.
intros a b c H; case (Z_zerop a); intro Ha;
[ case (Z_zerop b); intro Hb;
[ case (Z_zerop c); intro Hc;
[ apply False_ind; apply H; repeat split | right; right ]
| right; left ]
| left ]; assumption.
Qed.
Lemma mediant_1 :
forall m n m' n' : Z, (m' * n < m * n')%Z -> ((m + m') * n < m * (n + n'))%Z.
Proof.
intros.
rewrite Zmult_plus_distr_r.
rewrite Zmult_plus_distr_l.
apply Zplus_lt_compat_l.
assumption.
Qed.
Lemma mediant_2 :
forall m n m' n' : Z,
(m' * n < m * n')%Z -> (m' * (n + n') < (m + m') * n')%Z.
Proof.
intros.
rewrite Zmult_plus_distr_l.
rewrite Zmult_plus_distr_r.
apply Zplus_lt_compat_r.
assumption.
Qed.
Lemma mediant_3 :
forall a b m n m' n' : Z,
(0 <= a * m + b * n)%Z ->
(0 <= a * m' + b * n')%Z -> (0 <= a * (m + m') + b * (n + n'))%Z.
Proof.
intros.
replace (a * (m + m') + b * (n + n'))%Z with
(a * m + b * n + (a * m' + b * n'))%Z.
apply Zplus_le_0_compat.
assumption.
assumption.
ring.
Qed.
Lemma fraction_lt_trans :
forall a b c d e f : Z,
(0 < b)%Z ->
(0 < d)%Z ->
(0 < f)%Z -> (a * d < c * b)%Z -> (c * f < e * d)%Z -> (a * f < e * b)%Z.
Proof.
intros.
apply Zgt_lt.
apply Zgt_mult_reg_absorb_l with d.
Flip.
apply Zgt_trans with (c * b * f)%Z.
replace (d * (e * b))%Z with (b * (e * d))%Z.
replace (c * b * f)%Z with (b * (c * f))%Z.
apply Zlt_gt.
apply Zlt_reg_mult_l.
Flip.
assumption.
ring.
ring.
replace (c * b * f)%Z with (f * (c * b))%Z.
replace (d * (a * f))%Z with (f * (a * d))%Z.
apply Zlt_gt.
apply Zlt_reg_mult_l.
Flip.
assumption.
ring.
ring.
Qed.
Lemma square_pos : forall a : Z, a <> 0%Z -> (0 < a * a)%Z.
Proof.
intros [| p| p]; intros; [ Falsum | constructor | constructor ].
Qed.
Hint Resolve square_pos: zarith.
(*###########################################################################*)
(** Properties of positive numbers, mapping between Z and nat *)
(*###########################################################################*)
Definition Z2positive (z : Z) :=
match z with
| Zpos p => p
| Zneg p => p
| Z0 => 1%positive
end.
Lemma ZL9 : forall p : positive, Z_of_nat (nat_of_P p) = Zpos p. (*QF*)
Proof.
intro.
cut (exists h : nat, nat_of_P p = S h).
intro.
case H.
intros.
unfold Z_of_nat in |- *.
rewrite H0.
apply f_equal with (A := positive) (B := Z) (f := Zpos).
cut (P_of_succ_nat (nat_of_P p) = P_of_succ_nat (S x)).
intro.
rewrite P_of_succ_nat_o_nat_of_P_eq_succ in H1.
cut (Ppred (Psucc p) = Ppred (P_of_succ_nat (S x))).
intro.
rewrite Ppred_succ in H2.
simpl in H2.
rewrite Ppred_succ in H2.
apply sym_eq.
assumption.
apply f_equal with (A := positive) (B := positive) (f := Ppred).
assumption.
apply f_equal with (f := P_of_succ_nat).
assumption.
apply ZL4.
Qed.
Coercion Z_of_nat : nat >-> Z.
Lemma ZERO_lt_POS : forall p : positive, (0 < Zpos p)%Z.
Proof.
intros.
constructor.
Qed.
Lemma POS_neq_ZERO : forall p : positive, Zpos p <> 0%Z.
Proof.
intros.
apply sym_not_eq.
apply Zorder.Zlt_not_eq.
apply ZERO_lt_POS.
Qed.
Lemma NEG_neq_ZERO : forall p : positive, Zneg p <> 0%Z.
Proof.
intros.
apply Zorder.Zlt_not_eq.
unfold Zlt in |- *.
constructor.
Qed.
Lemma POS_resp_eq : forall p0 p1 : positive, Zpos p0 = Zpos p1 -> p0 = p1.
Proof.
intros.
injection H.
trivial.
Qed.
Lemma nat_nat_pos : forall m n : nat, ((m + 1) * (n + 1) > 0)%Z. (*QF*)
Proof.
intros.
apply Zlt_gt.
cut (Z_of_nat m + 1 > 0)%Z.
intro.
cut (0 < Z_of_nat n + 1)%Z.
intro.
cut ((Z_of_nat m + 1) * 0 < (Z_of_nat m + 1) * (Z_of_nat n + 1))%Z.
rewrite Zmult_0_r.
intro.
assumption.
apply Zlt_reg_mult_l.
assumption.
assumption.
change (0 < Zsucc (Z_of_nat n))%Z in |- *.
apply Zle_lt_succ.
change (Z_of_nat 0 <= Z_of_nat n)%Z in |- *.
apply Znat.inj_le.
apply le_O_n.
apply Zlt_gt.
change (0 < Zsucc (Z_of_nat m))%Z in |- *.
apply Zle_lt_succ.
change (Z_of_nat 0 <= Z_of_nat m)%Z in |- *.
apply Znat.inj_le.
apply le_O_n.
Qed.
Theorem S_predn : forall m : nat, m <> 0 -> S (pred m) = m. (*QF*)
Proof.
intros.
case (O_or_S m).
intro.
case s.
intros.
rewrite <- e.
rewrite <- pred_Sn with (n := x).
trivial.
intro.
apply False_ind.
apply H.
apply sym_eq.
assumption.
Qed.
Lemma absolu_1 : forall x : Z, Zabs_nat x = 0 -> x = 0%Z. (*QF*)
Proof.
intros.
case (dec_eq x 0).
intro.
assumption.
intro.
apply False_ind.
cut ((x < 0)%Z \/ (x > 0)%Z).
intro.
ElimCompare x 0%Z.
intro.
cut (x = 0%Z).
assumption.
cut ((x ?= 0)%Z = Datatypes.Eq -> x = 0%Z).
intro.
apply H3.
assumption.
apply proj1 with (B := x = 0%Z -> (x ?= 0)%Z = Datatypes.Eq).
change ((x ?= 0)%Z = Datatypes.Eq <-> x = 0%Z) in |- *.
apply Zcompare_Eq_iff_eq.
(***)
intro.
cut (exists h : nat, Zabs_nat x = S h).
intro.
case H3.
rewrite H.
exact O_S.
change (x < 0)%Z in H2.
cut (0 > x)%Z.
intro.
cut (exists p : positive, (0 + - x)%Z = Zpos p).
simpl in |- *.
intro.
case H4.
intros.
cut (exists q : positive, x = Zneg q).
intro.
case H6.
intros.
rewrite H7.
unfold Zabs_nat in |- *.
generalize x1.
exact ZL4.
cut (x = (- Zpos x0)%Z).
simpl in |- *.
intro.
exists x0.
assumption.
cut ((- - x)%Z = x).
intro.
rewrite <- H6.
exact (f_equal Zopp H5).
apply Zopp_involutive.
apply Zcompare_Gt_spec.
assumption.
apply Zlt_gt.
assumption.
(***)
intro.
cut (exists h : nat, Zabs_nat x = S h).
intro.
case H3.
rewrite H.
exact O_S.
cut (exists p : positive, (x + - (0))%Z = Zpos p).
simpl in |- *.
rewrite Zplus_0_r.
intro.
case H3.
intros.
rewrite H4.
unfold Zabs_nat in |- *.
generalize x0.
exact ZL4.
apply Zcompare_Gt_spec.
assumption.
(***)
cut ((x < 0)%Z \/ (0 < x)%Z).
intro.
apply
or_ind with (A := (x < 0)%Z) (B := (0 < x)%Z) (P := (x < 0)%Z \/ (x > 0)%Z).
intro.
left.
assumption.
intro.
right.
apply Zlt_gt.
assumption.
assumption.
apply not_Zeq.
assumption.
Qed.
Lemma absolu_2 : forall x : Z, x <> 0%Z -> Zabs_nat x <> 0. (*QF*)
Proof.
intros.
intro.
apply H.
apply absolu_1.
assumption.
Qed.
Lemma absolu_inject_nat : forall n : nat, Zabs_nat (Z_of_nat n) = n.
Proof.
simple induction n; simpl in |- *.
reflexivity.
intros.
apply nat_of_P_o_P_of_succ_nat_eq_succ.
Qed.
Lemma eq_inj : forall m n : nat, m = n :>Z -> m = n.
Proof.
intros.
generalize (f_equal Zabs_nat H).
intro.
rewrite (absolu_inject_nat m) in H0.
rewrite (absolu_inject_nat n) in H0.
assumption.
Qed.
Lemma lt_inj : forall m n : nat, (m < n)%Z -> m < n.
Proof.
intros.
omega.
Qed.
Lemma le_inj : forall m n : nat, (m <= n)%Z -> m <= n.
Proof.
intros.
omega.
Qed.
Lemma inject_nat_S_inf : forall x : Z, (0 < x)%Z -> {n : nat | x = S n}.
Proof.
intros [| p| p] Hp; try discriminate Hp.
exists (pred (nat_of_P p)).
rewrite S_predn.
symmetry in |- *; apply ZL9.
clear Hp;
apply sym_not_equal; apply lt_O_neq; apply lt_O_nat_of_P.
Qed.
Lemma le_absolu :
forall x y : Z,
(0 <= x)%Z -> (0 <= y)%Z -> (x <= y)%Z -> Zabs_nat x <= Zabs_nat y.
Proof.
intros [| x| x] [| y| y] Hx Hy Hxy;
apply le_O_n ||
(try
match goal with
| id1:(0 <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= 0)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
end).
simpl in |- *.
apply le_inj.
do 2 rewrite ZL9.
assumption.
Qed.
Lemma lt_absolu :
forall x y : Z,
(0 <= x)%Z -> (0 <= y)%Z -> (x < y)%Z -> Zabs_nat x < Zabs_nat y.
Proof.
intros [| x| x] [| y| y] Hx Hy Hxy; inversion Hxy;
try
match goal with
| id1:(0 <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= 0)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
end; simpl in |- *; apply lt_inj; repeat rewrite ZL9;
assumption.
Qed.
Lemma absolu_plus :
forall x y : Z,
(0 <= x)%Z -> (0 <= y)%Z -> Zabs_nat (x + y) = Zabs_nat x + Zabs_nat y.
Proof.
intros [| x| x] [| y| y] Hx Hy; trivial;
try
match goal with
| id1:(0 <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= 0)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
end.
rewrite <- BinInt.Zpos_plus_distr.
unfold Zabs_nat in |- *.
apply nat_of_P_plus_morphism.
Qed.
Lemma pred_absolu :
forall x : Z, (0 < x)%Z -> pred (Zabs_nat x) = Zabs_nat (x - 1).
Proof.
intros x Hx.
generalize (Z_lt_lt_S_eq_dec 0 x Hx); simpl in |- *; intros [H1| H1];
[ replace (Zabs_nat x) with (Zabs_nat (x - 1 + 1));
[ idtac | apply f_equal with Z; auto with zarith ];
rewrite absolu_plus;
[ unfold Zabs_nat at 2, nat_of_P, Piter_op in |- *; omega
| auto with zarith
| intro; discriminate ]
| rewrite <- H1; reflexivity ].
Qed.
Definition pred_nat : forall (x : Z) (Hx : (0 < x)%Z), nat.
intros [| px| px] Hx; try abstract (discriminate Hx).
exact (pred (nat_of_P px)).
Defined.
Lemma pred_nat_equal :
forall (x : Z) (Hx1 Hx2 : (0 < x)%Z), pred_nat x Hx1 = pred_nat x Hx2.
Proof.
intros [| px| px] Hx1 Hx2; try (discriminate Hx1); trivial.
Qed.
Let pred_nat_unfolded_subproof px :
Pos.to_nat px <> 0.
Proof.
apply sym_not_equal; apply lt_O_neq; apply lt_O_nat_of_P.
Qed.
Lemma pred_nat_unfolded :
forall (x : Z) (Hx : (0 < x)%Z), x = S (pred_nat x Hx).
Proof.
intros [| px| px] Hx; try discriminate Hx.
unfold pred_nat in |- *.
rewrite S_predn.
symmetry in |- *; apply ZL9.
clear Hx; apply pred_nat_unfolded_subproof.
Qed.
Lemma absolu_pred_nat :
forall (m : Z) (Hm : (0 < m)%Z), S (pred_nat m Hm) = Zabs_nat m.
Proof.
intros [| px| px] Hx; try discriminate Hx.
unfold pred_nat in |- *.
rewrite S_predn.
reflexivity.
apply pred_nat_unfolded_subproof.
Qed.
Lemma pred_nat_absolu :
forall (m : Z) (Hm : (0 < m)%Z), pred_nat m Hm = Zabs_nat (m - 1).
Proof.
intros [| px| px] Hx; try discriminate Hx.
unfold pred_nat in |- *.
rewrite <- pred_absolu; reflexivity || assumption.
Qed.
Lemma minus_pred_nat :
forall (n m : Z) (Hn : (0 < n)%Z) (Hm : (0 < m)%Z) (Hnm : (0 < n - m)%Z),
S (pred_nat n Hn) - S (pred_nat m Hm) = S (pred_nat (n - m) Hnm).
Proof.
intros.
simpl in |- *.
destruct n; try discriminate Hn.
destruct m; try discriminate Hm.
unfold pred_nat at 1 2 in |- *.
rewrite minus_pred; try apply lt_O_nat_of_P.
apply eq_inj.
rewrite <- pred_nat_unfolded.
rewrite Znat.inj_minus1.
repeat rewrite ZL9.
reflexivity.
apply le_inj.
apply Zlt_le_weak.
repeat rewrite ZL9.
apply Zlt_O_minus_lt.
assumption.
Qed.
(*###########################################################################*)
(** Properties of Zsgn *)
(*###########################################################################*)
Lemma Zsgn_1 :
forall x : Z, {Zsgn x = 0%Z} + {Zsgn x = 1%Z} + {Zsgn x = (-1)%Z}. (*QF*)
Proof.
intros.
case x.
left.
left.
unfold Zsgn in |- *.
reflexivity.
intro.
simpl in |- *.
left.
right.
reflexivity.
intro.
right.
simpl in |- *.
reflexivity.
Qed.
Lemma Zsgn_2 : forall x : Z, Zsgn x = 0%Z -> x = 0%Z. (*QF*)
Proof.
intros [| p1| p1]; simpl in |- *; intro H; constructor || discriminate H.
Qed.
Lemma Zsgn_3 : forall x : Z, x <> 0%Z -> Zsgn x <> 0%Z. (*QF*)
Proof.
intro.
case x.
intros.
apply False_ind.
apply H.
reflexivity.
intros.
simpl in |- *.
discriminate.
intros.
simpl in |- *.
discriminate.
Qed.
Theorem Zsgn_4 : forall a : Z, a = (Zsgn a * Zabs_nat a)%Z. (*QF*)
Proof.
intro.
case a.
simpl in |- *.
reflexivity.
intro.
unfold Zsgn in |- *.
unfold Zabs_nat in |- *.
rewrite Zmult_1_l.
symmetry in |- *.
apply ZL9.
intros.
unfold Zsgn in |- *.
unfold Zabs_nat in |- *.
rewrite ZL9.
constructor.
Qed.
Theorem Zsgn_5 :
forall a b x y : Z,
x <> 0%Z ->
y <> 0%Z ->
(Zsgn a * x)%Z = (Zsgn b * y)%Z -> (Zsgn a * y)%Z = (Zsgn b * x)%Z. (*QF*)
Proof.
intros a b x y H H0.
case a.
case b.
simpl in |- *.
trivial.
intro.
unfold Zsgn in |- *.
intro.
rewrite Zmult_1_l in H1.
simpl in H1.
apply False_ind.
apply H0.
symmetry in |- *.
assumption.
intro.
unfold Zsgn in |- *.
intro.
apply False_ind.
apply H0.
apply Zopp_inj.
simpl in |- *.
transitivity (-1 * y)%Z.
constructor.
transitivity (0 * x)%Z.
symmetry in |- *.
assumption.
simpl in |- *.
reflexivity.
intro.
unfold Zsgn at 1 in |- *.
unfold Zsgn at 2 in |- *.
intro.
transitivity y.
rewrite Zmult_1_l.
reflexivity.
transitivity (Zsgn b * (Zsgn b * y))%Z.
case (Zsgn_1 b).
intro.
case s.
intro.
apply False_ind.
apply H.
rewrite e in H1.
change ((1 * x)%Z = 0%Z) in H1.
rewrite Zmult_1_l in H1.
assumption.
intro.
rewrite e.
rewrite Zmult_1_l.
rewrite Zmult_1_l.
reflexivity.
intro.
rewrite e.
ring.
rewrite Zmult_1_l in H1.
rewrite H1.
reflexivity.
intro.
unfold Zsgn at 1 in |- *.
unfold Zsgn at 2 in |- *.
intro.
transitivity (Zsgn b * (-1 * (Zsgn b * y)))%Z.
case (Zsgn_1 b).
intros.
case s.
intro.
apply False_ind.
apply H.
apply Zopp_inj.
transitivity (-1 * x)%Z.
ring.
unfold Zopp in |- *.
rewrite e in H1.
transitivity (0 * y)%Z.
assumption.
simpl in |- *.
reflexivity.
intro.
rewrite e.
ring.
intro.
rewrite e.
ring.
rewrite <- H1.
ring.
Qed.
Lemma Zsgn_6 : forall x : Z, x = 0%Z -> Zsgn x = 0%Z.
Proof.
intros.
rewrite H.
simpl in |- *.
reflexivity.
Qed.
Lemma Zsgn_7 : forall x : Z, (x > 0)%Z -> Zsgn x = 1%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
apply (Zlt_irrefl 0).
Flip.
intros.
simpl in |- *.
reflexivity.
intros.
apply False_ind.
apply (Zlt_irrefl (Zneg p)).
apply Zlt_trans with 0%Z.
constructor.
Flip.
Qed.
Lemma Zsgn_7' : forall x : Z, (0 < x)%Z -> Zsgn x = 1%Z.
Proof.
intros; apply Zsgn_7; Flip.
Qed.
Lemma Zsgn_8 : forall x : Z, (x < 0)%Z -> Zsgn x = (-1)%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
apply (Zlt_irrefl 0).
assumption.
intros.
apply False_ind.
apply (Zlt_irrefl 0).
apply Zlt_trans with (Zpos p).
constructor.
assumption.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma Zsgn_9 : forall x : Z, Zsgn x = 1%Z -> (0 < x)%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
simpl in H.
discriminate.
intros.
constructor.
intros.
apply False_ind.
discriminate.
Qed.
Lemma Zsgn_10 : forall x : Z, Zsgn x = (-1)%Z -> (x < 0)%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
discriminate.
intros.
apply False_ind.
discriminate.
intros.
constructor.
Qed.
Lemma Zsgn_11 : forall x : Z, (Zsgn x < 0)%Z -> (x < 0)%Z.
Proof.
intros.
apply Zsgn_10.
case (Zsgn_1 x).
intro.
apply False_ind.
case s.
intro.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
apply (H0 e).
intro.
rewrite e in H.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
discriminate.
trivial.
Qed.
Lemma Zsgn_12 : forall x : Z, (0 < Zsgn x)%Z -> (0 < x)%Z.
Proof.
intros.
apply Zsgn_9.
case (Zsgn_1 x).
intro.
case s.
intro.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
generalize (sym_eq e).
intro.
apply False_ind.
apply (H0 H1).
trivial.
intro.
rewrite e in H.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
apply False_ind.
discriminate.
Qed.
Lemma Zsgn_13 : forall x : Z, (0 <= Zsgn x)%Z -> (0 <= x)%Z.
Proof.
intros.
case (Z_le_lt_eq_dec 0 (Zsgn x) H).
intro.
apply Zlt_le_weak.
apply Zsgn_12.
assumption.
intro.
assert (x = 0%Z).
apply Zsgn_2.
symmetry in |- *.
assumption.
rewrite H0.
apply Zle_refl.
Qed.
Lemma Zsgn_14 : forall x : Z, (Zsgn x <= 0)%Z -> (x <= 0)%Z.
Proof.
intros.
case (Z_le_lt_eq_dec (Zsgn x) 0 H).
intro.
apply Zlt_le_weak.
apply Zsgn_11.
assumption.
intro.
assert (x = 0%Z).
apply Zsgn_2.
assumption.
rewrite H0.
apply Zle_refl.
Qed.
Lemma Zsgn_15 : forall x y : Z, Zsgn (x * y) = (Zsgn x * Zsgn y)%Z.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; constructor.
Qed.
Lemma Zsgn_16 :
forall x y : Z,
Zsgn (x * y) = 1%Z -> {(0 < x)%Z /\ (0 < y)%Z} + {(x < 0)%Z /\ (y < 0)%Z}.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
try discriminate H; [ left | right ]; repeat split.
Qed.
Lemma Zsgn_17 :
forall x y : Z,
Zsgn (x * y) = (-1)%Z -> {(0 < x)%Z /\ (y < 0)%Z} + {(x < 0)%Z /\ (0 < y)%Z}.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
try discriminate H; [ left | right ]; repeat split.
Qed.
Lemma Zsgn_18 : forall x y : Z, Zsgn (x * y) = 0%Z -> {x = 0%Z} + {y = 0%Z}.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
try discriminate H; [ left | right | right ]; constructor.
Qed.
Lemma Zsgn_19 : forall x y : Z, (0 < Zsgn x + Zsgn y)%Z -> (0 < x + y)%Z.
Proof.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
discriminate H || (constructor || apply Zsgn_12; assumption).
Qed.
Lemma Zsgn_20 : forall x y : Z, (Zsgn x + Zsgn y < 0)%Z -> (x + y < 0)%Z.
Proof.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
discriminate H || (constructor || apply Zsgn_11; assumption).
Qed.
Lemma Zsgn_21 : forall x y : Z, (0 < Zsgn x + Zsgn y)%Z -> (0 <= x)%Z.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intros H H0;
discriminate H || discriminate H0.
Qed.
Lemma Zsgn_22 : forall x y : Z, (Zsgn x + Zsgn y < 0)%Z -> (x <= 0)%Z.
Proof.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intros H H0;
discriminate H || discriminate H0.
Qed.
Lemma Zsgn_23 : forall x y : Z, (0 < Zsgn x + Zsgn y)%Z -> (0 <= y)%Z.
Proof.
intros [[| p2| p2]| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *;
intros H H0; discriminate H || discriminate H0.
Qed.
Lemma Zsgn_24 : forall x y : Z, (Zsgn x + Zsgn y < 0)%Z -> (y <= 0)%Z.
Proof.
intros [[| p2| p2]| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *;
intros H H0; discriminate H || discriminate H0.
Qed.
Lemma Zsgn_25 : forall x : Z, Zsgn (- x) = (- Zsgn x)%Z.
Proof.
intros [| p1| p1]; simpl in |- *; reflexivity.
Qed.
Lemma Zsgn_26 : forall x : Z, (0 < x)%Z -> (0 < Zsgn x)%Z.
Proof.
intros [| p| p] Hp; trivial.
Qed.
Lemma Zsgn_27 : forall x : Z, (x < 0)%Z -> (Zsgn x < 0)%Z.
Proof.
intros [| p| p] Hp; trivial.
Qed.
Hint Resolve Zsgn_1 Zsgn_2 Zsgn_3 Zsgn_4 Zsgn_5 Zsgn_6 Zsgn_7 Zsgn_7' Zsgn_8
Zsgn_9 Zsgn_10 Zsgn_11 Zsgn_12 Zsgn_13 Zsgn_14 Zsgn_15 Zsgn_16 Zsgn_17
Zsgn_18 Zsgn_19 Zsgn_20 Zsgn_21 Zsgn_22 Zsgn_23 Zsgn_24 Zsgn_25 Zsgn_26
Zsgn_27: zarith.
(*###########################################################################*)
(** Properties of Zabs *)
(*###########################################################################*)
Lemma Zabs_1 : forall z p : Z, (Zabs z < p)%Z -> (z < p)%Z /\ (- p < z)%Z.
Proof.
intros z p.
case z.
intros.
simpl in H.
split.
assumption.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
replace (-1)%Z with (Zpred 0).
apply Zlt_pred.
simpl; trivial.
ring_simplify (-1 * - p)%Z (-1 * 0)%Z.
apply Zlt_gt.
assumption.
intros.
simpl in H.
split.
assumption.
apply Zlt_trans with (m := 0%Z).
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
replace (-1)%Z with (Zpred 0).
apply Zlt_pred.
simpl; trivial.
ring_simplify (-1 * - p)%Z (-1 * 0)%Z.
apply Zlt_gt.
apply Zlt_trans with (m := Zpos p0).
constructor.
assumption.
constructor.
intros.
simpl in H.
split.
apply Zlt_trans with (m := Zpos p0).
constructor.
assumption.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
replace (-1)%Z with (Zpred 0).
apply Zlt_pred.
simpl;trivial.
ring_simplify (-1 * - p)%Z.
replace (-1 * Zneg p0)%Z with (- Zneg p0)%Z.
replace (- Zneg p0)%Z with (Zpos p0).
apply Zlt_gt.
assumption.
symmetry in |- *.
apply Zopp_neg.
rewrite Zopp_mult_distr_l_reverse with (n := 1%Z).
simpl in |- *.
constructor.
Qed.
Lemma Zabs_2 : forall z p : Z, (Zabs z > p)%Z -> (z > p)%Z \/ (- p > z)%Z.
Proof.
intros z p.
case z.
intros.
simpl in H.
left.
assumption.
intros.
simpl in H.
left.
assumption.
intros.
simpl in H.
right.
apply Zlt_gt.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
ring_simplify (-1 * - p)%Z.
replace (-1 * Zneg p0)%Z with (Zpos p0).
assumption.
reflexivity.
Qed.
Lemma Zabs_3 : forall z p : Z, (z < p)%Z /\ (- p < z)%Z -> (Zabs z < p)%Z.
Proof.
intros z p.
case z.
intro.
simpl in |- *.
elim H.
intros.
assumption.
intros.
elim H.
intros.
simpl in |- *.
assumption.
intros.
elim H.
intros.
simpl in |- *.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
replace (-1 * Zpos p0)%Z with (Zneg p0).
replace (-1 * p)%Z with (- p)%Z.
apply Zlt_gt.
assumption.
ring.
simpl in |- *.
reflexivity.
Qed.
Lemma Zabs_4 : forall z p : Z, (Zabs z < p)%Z -> (- p < z < p)%Z.
Proof.
intros.
split.
apply proj2 with (A := (z < p)%Z).
apply Zabs_1.
assumption.
apply proj1 with (B := (- p < z)%Z).
apply Zabs_1.
assumption.
Qed.
Lemma Zabs_5 : forall z p : Z, (Zabs z <= p)%Z -> (- p <= z <= p)%Z.
Proof.
intros.
split.
replace (- p)%Z with (Zsucc (- Zsucc p)).
apply Zlt_le_succ.
apply proj2 with (A := (z < Zsucc p)%Z).
apply Zabs_1.
apply Zle_lt_succ.
assumption.
unfold Zsucc in |- *.
ring.
apply Zlt_succ_le.
apply proj1 with (B := (- Zsucc p < z)%Z).
apply Zabs_1.
apply Zle_lt_succ.
assumption.
Qed.
Lemma Zabs_6 : forall z p : Z, (Zabs z <= p)%Z -> (z <= p)%Z.
Proof.
intros.
apply proj2 with (A := (- p <= z)%Z).
apply Zabs_5.
assumption.
Qed.
Lemma Zabs_7 : forall z p : Z, (Zabs z <= p)%Z -> (- p <= z)%Z.
Proof.
intros.
apply proj1 with (B := (z <= p)%Z).
apply Zabs_5.
assumption.
Qed.
Lemma Zabs_8 : forall z p : Z, (- p <= z <= p)%Z -> (Zabs z <= p)%Z.
Proof.
intros.
apply Zlt_succ_le.
apply Zabs_3.
elim H.
intros.
split.
apply Zle_lt_succ.
assumption.
apply Zlt_le_trans with (m := (- p)%Z).
apply Zgt_lt.
apply Zlt_opp.
apply Zlt_succ.
assumption.
Qed.
Lemma Zabs_min : forall z : Z, Zabs z = Zabs (- z).
Proof.
intro.
case z.
simpl in |- *.
reflexivity.
intro.
simpl in |- *.
reflexivity.
intro.
simpl in |- *.
reflexivity.
Qed.
Lemma Zabs_9 :
forall z p : Z, (0 <= p)%Z -> (p < z)%Z \/ (z < - p)%Z -> (p < Zabs z)%Z.
Proof.
intros.
case H0.
intro.
replace (Zabs z) with z.
assumption.
symmetry in |- *.
apply Zabs_eq.
apply Zlt_le_weak.
apply Zle_lt_trans with (m := p).
assumption.
assumption.
intro.
cut (Zabs z = (- z)%Z).
intro.
rewrite H2.
apply Zmin_cancel_Zlt.
ring_simplify (- - z)%Z.
assumption.
rewrite Zabs_min.
apply Zabs_eq.
apply Zlt_le_weak.
apply Zle_lt_trans with (m := p).
assumption.
apply Zmin_cancel_Zlt.
ring_simplify (- - z)%Z.
assumption.
Qed.
Lemma Zabs_10 : forall z : Z, (0 <= Zabs z)%Z.
Proof.
intro.
case (Z_zerop z).
intro.
rewrite e.
simpl in |- *.
apply Zle_refl.
intro.
case (not_Zeq z 0 n).
intro.
apply Zlt_le_weak.
apply Zabs_9.
apply Zle_refl.
simpl in |- *.
right.
assumption.
intro.
apply Zlt_le_weak.
apply Zabs_9.
apply Zle_refl.
simpl in |- *.
left.
assumption.
Qed.
Lemma Zabs_11 : forall z : Z, z <> 0%Z -> (0 < Zabs z)%Z.
Proof.
intros.
apply Zabs_9.
apply Zle_refl.
simpl in |- *.
apply not_Zeq.
intro.
apply H.
symmetry in |- *.
assumption.
Qed.
Lemma Zabs_12 : forall z m : Z, (m < Zabs z)%Z -> {(m < z)%Z} + {(z < - m)%Z}.
Proof.
intros [| p| p] m; simpl in |- *; intros H;
[ left | left | right; apply Zmin_cancel_Zlt; rewrite Zopp_involutive ];
assumption.
Qed.
Lemma Zabs_mult : forall z p : Z, Zabs (z * p) = (Zabs z * Zabs p)%Z.
Proof.
intros.
case z.
simpl in |- *.
reflexivity.
case p.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
case p.
intro.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma Zabs_plus : forall z p : Z, (Zabs (z + p) <= Zabs z + Zabs p)%Z.
Proof.
intros.
case z.
simpl in |- *.
apply Zle_refl.
case p.
intro.
simpl in |- *.
apply Zle_refl.
intros.
simpl in |- *.
apply Zle_refl.
intros.
unfold Zabs at 2 in |- *.
unfold Zabs at 2 in |- *.
apply Zabs_8.
split.
apply Zplus_le_reg_l with (Zpos p1 - Zneg p0)%Z.
replace (Zpos p1 - Zneg p0 + - (Zpos p1 + Zpos p0))%Z with
(- (Zpos p0 + Zneg p0))%Z.
replace (Zpos p1 - Zneg p0 + (Zpos p1 + Zneg p0))%Z with (2 * Zpos p1)%Z.
replace (- (Zpos p0 + Zneg p0))%Z with 0%Z.
apply Zmult_gt_0_le_0_compat.
constructor.
apply Zlt_le_weak.
constructor.
rewrite <- Zopp_neg with p0.
ring.
ring.
ring.
apply Zplus_le_compat.
apply Zle_refl.
apply Zlt_le_weak.
constructor.
case p.
simpl in |- *.
intro.
apply Zle_refl.
intros.
unfold Zabs at 2 in |- *.
unfold Zabs at 2 in |- *.
apply Zabs_8.
split.
apply Zplus_le_reg_l with (Zpos p1 + Zneg p0)%Z.
replace (Zpos p1 + Zneg p0 + - (Zpos p1 + Zpos p0))%Z with
(Zneg p0 - Zpos p0)%Z.
replace (Zpos p1 + Zneg p0 + (Zneg p1 + Zpos p0))%Z with 0%Z.
apply Zplus_le_reg_l with (Zpos p0).
replace (Zpos p0 + (Zneg p0 - Zpos p0))%Z with (Zneg p0).
simpl in |- *.
apply Zlt_le_weak.
constructor.
ring.
replace (Zpos p1 + Zneg p0 + (Zneg p1 + Zpos p0))%Z with
(Zpos p1 + Zneg p1 + (Zpos p0 + Zneg p0))%Z.
replace 0%Z with (0 + 0)%Z.
apply Zplus_eq_compat.
rewrite <- Zopp_neg with p1.
ring.
rewrite <- Zopp_neg with p0.
ring.
simpl in |- *.
constructor.
ring.
ring.
apply Zplus_le_compat.
apply Zlt_le_weak.
constructor.
apply Zle_refl.
intros.
simpl in |- *.
apply Zle_refl.
Qed.
Lemma Zabs_neg : forall z : Z, (z <= 0)%Z -> Zabs z = (- z)%Z.
Proof.
intro.
case z.
simpl in |- *.
intro.
reflexivity.
intros.
apply False_ind.
apply H.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma Zle_Zabs: forall z, (z <= Zabs z)%Z.
Proof.
intros [|z|z]; simpl; auto with zarith; apply Zle_neg_pos.
Qed.
Hint Resolve Zabs_1 Zabs_2 Zabs_3 Zabs_4 Zabs_5 Zabs_6 Zabs_7 Zabs_8 Zabs_9
Zabs_10 Zabs_11 Zabs_12 Zabs_min Zabs_neg Zabs_mult Zabs_plus Zle_Zabs: zarith.
(*###########################################################################*)
(** Induction on Z *)
(*###########################################################################*)
Lemma Zind :
forall (P : Z -> Prop) (p : Z),
P p ->
(forall q : Z, (p <= q)%Z -> P q -> P (q + 1)%Z) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros P p.
intro.
intro.
cut (forall q : Z, (p <= q)%Z -> exists k : nat, q = (p + k)%Z).
intro.
cut (forall k : nat, P (p + k)%Z).
intro.
intros.
cut (exists k : nat, q = (p + Z_of_nat k)%Z).
intro.
case H4.
intros.
rewrite H5.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
ring_simplify (p + 0)%Z.
assumption.
replace (p + Z_of_nat (S k))%Z with (p + k + 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (Z_of_nat 0).
ring_simplify (- p + (p + Z_of_nat k))%Z.
apply Znat.inj_le.
apply le_O_n.
ring_simplify; auto with arith.
assumption.
rewrite (Znat.inj_S k).
unfold Zsucc in |- *.
ring.
intros.
cut (exists k : nat, (q - p)%Z = Z_of_nat k).
intro.
case H2.
intro k.
intros.
exists k.
apply Zplus_reg_l with (n := (- p)%Z).
replace (- p + q)%Z with (q - p)%Z.
rewrite H3.
ring.
ring.
apply Z_of_nat_complete.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zrec :
forall (P : Z -> Set) (p : Z),
P p ->
(forall q : Z, (p <= q)%Z -> P q -> P (q + 1)%Z) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros F p.
intro.
intro.
cut (forall q : Z, (p <= q)%Z -> {k : nat | q = (p + k)%Z}).
intro.
cut (forall k : nat, F (p + k)%Z).
intro.
intros.
cut {k : nat | q = (p + Z_of_nat k)%Z}.
intro.
case H4.
intros.
rewrite e.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
rewrite Zplus_0_r.
assumption.
replace (p + Z_of_nat (S k))%Z with (p + k + 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (Z_of_nat 0).
replace (- p + (p + Z_of_nat k))%Z with (Z_of_nat k).
apply Znat.inj_le.
apply le_O_n.
rewrite Zplus_assoc; rewrite Zplus_opp_l; reflexivity.
rewrite Zplus_opp_l; reflexivity.
assumption.
rewrite (Znat.inj_S k).
unfold Zsucc in |- *.
apply Zplus_assoc_reverse.
intros.
cut {k : nat | (q - p)%Z = Z_of_nat k}.
intro H2.
case H2.
intro k.
intros.
exists k.
apply Zplus_reg_l with (n := (- p)%Z).
replace (- p + q)%Z with (q - p)%Z.
rewrite e.
rewrite Zplus_assoc; rewrite Zplus_opp_l; reflexivity.
unfold Zminus in |- *.
apply Zplus_comm.
apply Z_of_nat_complete_inf.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zrec_down :
forall (P : Z -> Set) (p : Z),
P p ->
(forall q : Z, (q <= p)%Z -> P q -> P (q - 1)%Z) ->
forall q : Z, (q <= p)%Z -> P q.
Proof.
intros F p.
intro.
intro.
cut (forall q : Z, (q <= p)%Z -> {k : nat | q = (p - k)%Z}).
intro.
cut (forall k : nat, F (p - k)%Z).
intro.
intros.
cut {k : nat | q = (p - Z_of_nat k)%Z}.
intro.
case H4.
intros.
rewrite e.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
replace (p - 0)%Z with p.
assumption.
unfold Zminus in |- *.
unfold Zopp in |- *.
rewrite Zplus_0_r; reflexivity.
replace (p - Z_of_nat (S k))%Z with (p - k - 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (- Z_of_nat 0)%Z.
replace (- p + (p - Z_of_nat k))%Z with (- Z_of_nat k)%Z.
apply Zge_le.
apply Zge_opp.
apply Znat.inj_le.
apply le_O_n.
unfold Zminus in |- *; rewrite Zplus_assoc; rewrite Zplus_opp_l; reflexivity.
rewrite Zplus_opp_l; reflexivity.
assumption.
rewrite (Znat.inj_S k).
unfold Zsucc in |- *.
unfold Zminus at 1 2 in |- *.
rewrite Zplus_assoc_reverse.
rewrite <- Zopp_plus_distr.
reflexivity.
intros.
cut {k : nat | (p - q)%Z = Z_of_nat k}.
intro.
case H2.
intro k.
intros.
exists k.
apply Zopp_inj.
apply Zplus_reg_l with (n := p).
replace (p + - (p - Z_of_nat k))%Z with (Z_of_nat k).
rewrite <- e.
reflexivity.
unfold Zminus in |- *.
rewrite Zopp_plus_distr.
rewrite Zplus_assoc.
rewrite Zplus_opp_r.
rewrite Zopp_involutive.
reflexivity.
apply Z_of_nat_complete_inf.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zind_down :
forall (P : Z -> Prop) (p : Z),
P p ->
(forall q : Z, (q <= p)%Z -> P q -> P (q - 1)%Z) ->
forall q : Z, (q <= p)%Z -> P q.
Proof.
intros F p.
intro.
intro.
cut (forall q : Z, (q <= p)%Z -> exists k : nat, q = (p - k)%Z).
intro.
cut (forall k : nat, F (p - k)%Z).
intro.
intros.
cut (exists k : nat, q = (p - Z_of_nat k)%Z).
intro.
case H4.
intros x e.
rewrite e.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
replace (p - 0)%Z with p.
assumption.
ring.
replace (p - Z_of_nat (S k))%Z with (p - k - 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (- Z_of_nat 0)%Z.
replace (- p + (p - Z_of_nat k))%Z with (- Z_of_nat k)%Z.
apply Zge_le.
apply Zge_opp.
apply Znat.inj_le.
apply le_O_n.
ring.
ring_simplify; auto with arith.
assumption.
rewrite (Znat.inj_S k).
unfold Zsucc in |- *.
ring.
intros.
cut (exists k : nat, (p - q)%Z = Z_of_nat k).
intro.
case H2.
intro k.
intros.
exists k.
apply Zopp_inj.
apply Zplus_reg_l with (n := p).
replace (p + - (p - Z_of_nat k))%Z with (Z_of_nat k).
rewrite <- H3.
ring.
ring.
apply Z_of_nat_complete.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zrec_wf :
forall (P : Z -> Set) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros P p WF_ind_step q Hq.
cut (forall x : Z, (p <= x)%Z -> forall y : Z, (p <= y < x)%Z -> P y).
intro.
apply (H (Zsucc q)).
apply Zle_le_succ.
assumption.
split; [ assumption | exact (Zlt_succ q) ].
intros x0 Hx0; generalize Hx0; pattern x0 in |- *.
apply Zrec with (p := p).
intros.
absurd (p <= p)%Z.
apply Zgt_not_le.
apply Zgt_le_trans with (m := y).
apply Zlt_gt.
elim H.
intros.
assumption.
elim H.
intros.
assumption.
apply Zle_refl.
intros.
apply WF_ind_step.
intros.
apply (H0 H).
split.
elim H2.
intros.
assumption.
apply Zlt_le_trans with y.
elim H2.
intros.
assumption.
apply Zgt_succ_le.
apply Zlt_gt.
elim H1.
intros.
unfold Zsucc in |- *.
assumption.
assumption.
Qed.
Lemma Zrec_wf2 :
forall (q : Z) (P : Z -> Set) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
(p <= q)%Z -> P q.
Proof.
intros.
apply Zrec_wf with (p := p).
assumption.
assumption.
Qed.
Lemma Zrec_wf_double :
forall (P : Z -> Z -> Set) (p0 q0 : Z),
(forall n m : Z,
(forall p q : Z, (q0 <= q)%Z -> (p0 <= p < n)%Z -> P p q) ->
(forall p : Z, (q0 <= p < m)%Z -> P n p) -> P n m) ->
forall p q : Z, (q0 <= q)%Z -> (p0 <= p)%Z -> P p q.
Proof.
intros P p0 q0 Hrec p.
intros.
generalize q H.
pattern p in |- *.
apply Zrec_wf with (p := p0).
intros p1 H1.
intros.
pattern q1 in |- *.
apply Zrec_wf with (p := q0).
intros q2 H3.
apply Hrec.
intros.
apply H1.
assumption.
assumption.
intros.
apply H3.
assumption.
assumption.
assumption.
Qed.
Lemma Zind_wf :
forall (P : Z -> Prop) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros P p WF_ind_step q Hq.
cut (forall x : Z, (p <= x)%Z -> forall y : Z, (p <= y < x)%Z -> P y).
intro.
apply (H (Zsucc q)).
apply Zle_le_succ.
assumption.
split; [ assumption | exact (Zlt_succ q) ].
intros x0 Hx0; generalize Hx0; pattern x0 in |- *.
apply Zind with (p := p).
intros.
absurd (p <= p)%Z.
apply Zgt_not_le.
apply Zgt_le_trans with (m := y).
apply Zlt_gt.
elim H.
intros.
assumption.
elim H.
intros.
assumption.
apply Zle_refl.
intros.
apply WF_ind_step.
intros.
apply (H0 H).
split.
elim H2.
intros.
assumption.
apply Zlt_le_trans with y.
elim H2.
intros.
assumption.
apply Zgt_succ_le.
apply Zlt_gt.
elim H1.
intros.
unfold Zsucc in |- *.
assumption.
assumption.
Qed.
Lemma Zind_wf2 :
forall (q : Z) (P : Z -> Prop) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
(p <= q)%Z -> P q.
Proof.
intros.
apply Zind_wf with (p := p).
assumption.
assumption.
Qed.
Lemma Zind_wf_double :
forall (P : Z -> Z -> Prop) (p0 q0 : Z),
(forall n m : Z,
(forall p q : Z, (q0 <= q)%Z -> (p0 <= p < n)%Z -> P p q) ->
(forall p : Z, (q0 <= p < m)%Z -> P n p) -> P n m) ->
forall p q : Z, (q0 <= q)%Z -> (p0 <= p)%Z -> P p q.
Proof.
intros P p0 q0 Hrec p.
intros.
generalize q H.
pattern p in |- *.
apply Zind_wf with (p := p0).
intros p1 H1.
intros.
pattern q1 in |- *.
apply Zind_wf with (p := q0).
intros q2 H3.
apply Hrec.
intros.
apply H1.
assumption.
assumption.
intros.
apply H3.
assumption.
assumption.
assumption.
Qed.
(*###########################################################################*)
(** Properties of Zmax *)
(*###########################################################################*)
Definition Zmax (n m : Z) := (n + m - Zmin n m)%Z.
Lemma ZmaxSS : forall n m : Z, (Zmax n m + 1)%Z = Zmax (n + 1) (m + 1).
Proof.
intros.
unfold Zmax in |- *.
replace (Zmin (n + 1) (m + 1)) with (Zmin n m + 1)%Z.
ring.
symmetry in |- *.
change (Zmin (Zsucc n) (Zsucc m) = Zsucc (Zmin n m)) in |- *.
symmetry in |- *.
apply Zmin_SS.
Qed.
Lemma Zle_max_l : forall n m : Z, (n <= Zmax n m)%Z.
Proof.
intros.
unfold Zmax in |- *.
apply Zplus_le_reg_l with (p := (- n + Zmin n m)%Z).
ring_simplify (- n + Zmin n m + n)%Z.
ring_simplify (- n + Zmin n m + (n + m - Zmin n m))%Z.
apply Zle_min_r.
Qed.
Lemma Zle_max_r : forall n m : Z, (m <= Zmax n m)%Z.
Proof.
intros.
unfold Zmax in |- *.
apply Zplus_le_reg_l with (p := (- m + Zmin n m)%Z).
ring_simplify (- m + Zmin n m + m)%Z.
ring_simplify (- m + Zmin n m + (n + m - Zmin n m))%Z.
apply Zle_min_l.
Qed.
Lemma Zmin_or_informative : forall n m : Z, {Zmin n m = n} + {Zmin n m = m}.
Proof.
intros.
case (Z_lt_ge_dec n m).
unfold Zmin in |- *.
unfold Zlt in |- *.
intro z.
rewrite z.
left.
reflexivity.
intro.
cut ({(n > m)%Z} + {n = m :>Z}).
intro.
case H.
intros z0.
unfold Zmin in |- *.
unfold Zgt in z0.
rewrite z0.
right.
reflexivity.
intro.
rewrite e.
right.
apply Zmin_n_n.
cut ({(m < n)%Z} + {m = n :>Z}).
intro.
elim H.
intro.
left.
apply Zlt_gt.
assumption.
intro.
right.
symmetry in |- *.
assumption.
apply Z_le_lt_eq_dec.
apply Zge_le.
assumption.
Qed.
Lemma Zmax_case : forall (n m : Z) (P : Z -> Set), P n -> P m -> P (Zmax n m).
Proof.
intros.
unfold Zmax in |- *.
case Zmin_or_informative with (n := n) (m := m).
intro.
rewrite e.
cut ((n + m - n)%Z = m).
intro.
rewrite H1.
assumption.
ring.
intro.
rewrite e.
cut ((n + m - m)%Z = n).
intro.
rewrite H1.
assumption.
ring.
Qed.
Lemma Zmax_or_informative : forall n m : Z, {Zmax n m = n} + {Zmax n m = m}.
Proof.
intros.
unfold Zmax in |- *.
case Zmin_or_informative with (n := n) (m := m).
intro.
rewrite e.
right.
ring.
intro.
rewrite e.
left.
ring.
Qed.
Lemma Zmax_n_n : forall n : Z, Zmax n n = n.
Proof.
intros.
unfold Zmax in |- *.
rewrite (Zmin_n_n n).
ring.
Qed.
Hint Resolve ZmaxSS Zle_max_r Zle_max_l Zmax_n_n: zarith.
(*###########################################################################*)
(** Properties of Arity *)
(*###########################################################################*)
Lemma Zeven_S : forall x : Z, Zeven.Zodd x -> Zeven.Zeven (x + 1).
Proof.
exact Zeven.Zeven_Sn.
Qed.
Lemma Zeven_pred : forall x : Z, Zeven.Zodd x -> Zeven.Zeven (x - 1).
Proof.
exact Zeven.Zeven_pred.
Qed.
(* This lemma used to be useful since it was mentioned with an unnecessary premise
`x>=0` as Z_modulo_2 in ZArith, but the ZArith version has been fixed. *)
Definition Z_modulo_2_always :
forall x : Z, {y : Z | x = (2 * y)%Z} + {y : Z | x = (2 * y + 1)%Z} :=
Zeven.Z_modulo_2.
(*###########################################################################*)
(** Properties of Zdiv *)
(*###########################################################################*)
Lemma Z_div_mod_eq_2 :
forall a b : Z, (0 < b)%Z -> (b * (a / b))%Z = (a - a mod b)%Z.
Proof.
intros.
apply Zplus_minus_eq.
rewrite Zplus_comm.
apply Z_div_mod_eq.
Flip.
Qed.
Lemma Z_div_le :
forall a b c : Z, (0 < c)%Z -> (b <= a)%Z -> (b / c <= a / c)%Z.
Proof.
intros.
apply Zge_le.
apply Z_div_ge; Flip; assumption.
Qed.
Lemma Z_div_nonneg :
forall a b : Z, (0 < b)%Z -> (0 <= a)%Z -> (0 <= a / b)%Z.
Proof.
intros.
apply Zge_le.
apply Z_div_ge0; Flip; assumption.
Qed.
Lemma Z_div_neg : forall a b : Z, (0 < b)%Z -> (a < 0)%Z -> (a / b < 0)%Z.
Proof.
intros.
rewrite (Z_div_mod_eq a b) in H0.
elim (Z_mod_lt a b).
intros H1 _.
apply Znot_ge_lt.
intro.
apply (Zlt_not_le (b * (a / b) + a mod b) 0 H0).
apply Zplus_le_0_compat.
apply Zmult_le_0_compat.
apply Zlt_le_weak; assumption.
Flip.
assumption.
Flip.
Flip.
Qed.
Hint Resolve Z_div_mod_eq_2 Z_div_le Z_div_nonneg Z_div_neg: zarith.
(*###########################################################################*)
(** Properties of Zpower *)
(*###########################################################################*)
Lemma Zpower_1 : forall a : Z, (a ^ 1)%Z = a.
Proof.
intros; unfold Zpower in |- *; unfold Zpower_pos in |- *; simpl in |- *;
auto with zarith.
Qed.
Lemma Zpower_2 : forall a : Z, (a ^ 2)%Z = (a * a)%Z.
Proof.
intros; unfold Zpower in |- *; unfold Zpower_pos in |- *; simpl in |- *;
ring.
Qed.
Hint Resolve Zpower_1 Zpower_2: zarith.
|
module test_001(clk, a, a_old, b);
// test case taken from:
// http://www.reddit.com/r/yosys/comments/1wvpj6/trouble_with_assertions_and_sat_solver/
input wire clk;
input wire a;
output reg a_old = 0;
output reg b = 1;
wire assertion = (a_old != b);
always @(posedge clk) begin
a_old <= a;
b <= !a;
assert(a_old != b);
end
endmodule
module test_002(clk, a, a_old, b);
// copy from test_001 with modifications
input wire clk;
input wire a;
output reg a_old = 0;
output reg b = 0; // <-- this will fail
wire assertion = (a_old != b);
always @(posedge clk) begin
a_old <= a;
b <= !a;
assert(a_old != b);
end
endmodule
module test_003(clk, a, a_old, b);
// copy from test_001 with modifications
input wire clk;
input wire a;
output reg a_old = 0;
output reg b; // <-- this will fail
wire assertion = (a_old != b);
always @(posedge clk) begin
a_old <= a;
b <= !a;
assert(a_old != b);
end
endmodule
module test_004(clk, a, a_old, b);
// copy from test_001 with modifications
input wire clk;
input wire a;
output reg a_old = 0;
output reg b = 1;
wire assertion = (a_old != b);
always @(posedge clk) begin
a_old <= a;
b <= !a;
assert(a_old == b); // <-- this will fail
end
endmodule
module test_005(clk, a, a_old, b);
// copy from test_001 with modifications
input wire clk;
input wire a;
output reg a_old = 1; // <-- inverted, no problem
output reg b = 0;
wire assertion = (a_old != b);
always @(posedge clk) begin
a_old <= a;
b <= !a;
assert(a_old != b);
end
endmodule
|
/*
* Wishbone Compatible BIOS ROM core using megafunction ROM
* Copyright (C) 2010 Donna Polehn <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
// The following is to get rid of the warning about not initializing the ROM
// altera message_off 10030
module bootrom (
input clk,
input rst,
// Wishbone slave interface
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [19:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input wb_stb_i,
input wb_cyc_i,
input [ 1:0] wb_sel_i,
output wb_ack_o
);
// Net declarations
reg [15:0] rom[0:127]; // Instantiate the ROM
wire [ 6:0] rom_addr;
wire stb;
// Combinatorial logic
assign rom_addr = wb_adr_i[7:1];
assign stb = wb_stb_i & wb_cyc_i;
assign wb_ack_o = stb;
assign wb_dat_o = rom[rom_addr];
initial $readmemh("bootrom.dat", rom);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2015 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2015.4
// \ \ Description : Xilinx Unified Simulation Library Component
// / / _no_description_
// /___/ /\ Filename : OBUFDS_DPHY.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module OBUFDS_DPHY #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter IOSTANDARD = "DEFAULT"
)(
output O,
output OB,
input HSTX_I,
input HSTX_T,
input LPTX_I_N,
input LPTX_I_P,
input LPTX_T
);
// define constants
localparam MODULE_NAME = "OBUFDS_DPHY";
// Parameter encodings and registers
localparam IOSTANDARD_DEFAULT = 0;
reg trig_attr = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "OBUFDS_DPHY_dr.v"
`else
localparam [56:1] IOSTANDARD_REG = IOSTANDARD;
`endif
wire IOSTANDARD_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
reg OB_out;
reg O_out;
wire HSTX_I_in;
wire HSTX_T_in;
wire LPTX_I_N_in;
wire LPTX_I_P_in;
wire LPTX_T_in;
reg hs_mode = 1'b1;
assign (strong1,strong0) O = (hs_mode === 1'b0) ? O_out : 1'bz;
assign (strong1, strong0) OB = (hs_mode === 1'b0) ? OB_out : 1'bz;
assign (supply1,supply0) O = (hs_mode === 1'b1) ? O_out : 1'bz;
assign (supply1,supply0) OB = (hs_mode === 1'b1) ? OB_out : 1'bz;
assign HSTX_I_in = HSTX_I;
assign HSTX_T_in = HSTX_T;
assign LPTX_I_N_in = LPTX_I_N;
assign LPTX_I_P_in = LPTX_I_P;
assign LPTX_T_in = LPTX_T;
assign IOSTANDARD_BIN =
(IOSTANDARD_REG == "DEFAULT") ? IOSTANDARD_DEFAULT :
IOSTANDARD_DEFAULT;
//Commenting out the DRC check for IOSTANDARD attribute as it is not required as per IOTST.
/* initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((IOSTANDARD_REG != "DEFAULT"))) begin
$display("Error: [Unisim %s-101] IOSTANDARD attribute is set to %s. Legal values for this attribute are DEFAULT. Instance: %m", MODULE_NAME, IOSTANDARD_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
*/
always @ (LPTX_T_in or HSTX_T_in or LPTX_I_P_in or LPTX_I_N_in or HSTX_I_in) begin
if (LPTX_T_in === 1'b0) begin
O_out <= LPTX_I_P_in;
OB_out <= LPTX_I_N_in;
hs_mode <= 1'b0;
end else if (LPTX_T_in === 1'b1 && HSTX_T_in === 1'b0) begin
O_out <= HSTX_I_in;
OB_out <= ~HSTX_I_in;
hs_mode <= 1'b1;
end else begin
O_out <= 1'bz;
OB_out <= 1'bz;
hs_mode <= 1'bx;
end
end
specify
(HSTX_I => O) = (0:0:0, 0:0:0);
(HSTX_I => OB) = (0:0:0, 0:0:0);
(HSTX_T => O) = (0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
(HSTX_T => OB) = (0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
(LPTX_I_N => OB) = (0:0:0, 0:0:0);
(LPTX_I_P => O) = (0:0:0, 0:0:0);
(LPTX_T => O) = (0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
(LPTX_T => OB) = (0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
//************************************************************//
// - a lot work in progress, many thing are useless
// TODO: clean this up and make it more general
// TODO: add comments
//************************************************************//
module spoof(
instruction_opcode,
ex_freeze,
clk_in,
data_out,
reset,
debug_out
);
input [31:0] instruction_opcode;
input ex_freeze;
input clk_in;
input reset;
output data_out;
output debug_out;
localparam STATE_Initial = 3'd0,
STATE_1 = 3'd1,
STATE_2 = 3'd2,
STATE_3 = 3'd3,
STATE_4 = 3'd4,
STATE_5_Placeholder = 3'd5,
STATE_6_Placeholder = 3'd6,
STATE_7_Placeholder = 3'd7;
//OPCODES for sequence recognition
localparam OPCODE_A = 32'h15000000,
OPCODE_B = 32'h15000000,
OPCODE_C = 32'h15000000,
OPCODE_D = 32'h15000000;
wire [31:0] instruction_opcode;
wire ex_freeze;
wire clk_in;
wire reset;
reg data_out;
//state registers
reg[2:0] CurrentState;
reg[2:0] NextState;
reg[31:0] FirstOp;
reg[31:0] FirstOp_Next;
reg[31:0] SecondOp;
reg[31:0] SecondOp_Next;
reg[31:0] ThirdOp;
reg[31:0] ThirdOp_Next;
reg[31:0] CurrentOp;
reg[31:0] debug_out;
//synchronous state transition
always@ (posedge clk_in)
begin: STATE_TRANS
if(reset)
begin
CurrentState <= STATE_Initial;
FirstOp <= 32'h00000000;
SecondOp <= 32'h00000000;
ThirdOp <= 32'h00000000;
end
else
begin
CurrentState <= NextState;
FirstOp <= FirstOp_Next;
SecondOp <= SecondOp_Next;
ThirdOp <= ThirdOp_Next;
end
end
//conditional state transition
always@ (*)
begin
if(ex_freeze) begin
NextState <= CurrentState;
FirstOp_Next <= FirstOp;
SecondOp_Next <= SecondOp;
ThirdOp_Next <= ThirdOp;
end
else begin
FirstOp_Next <= SecondOp;
SecondOp_Next <= ThirdOp;
ThirdOp_Next <= instruction_opcode;
case(CurrentState)
STATE_Initial: begin
NextState <= STATE_1;
end
STATE_1: begin
NextState <= STATE_2;
end
STATE_2: begin
NextState <= STATE_3;
end
STATE_3: begin
if(instruction_opcode == OPCODE_D && FirstOp == OPCODE_A && SecondOp == OPCODE_B && ThirdOp == OPCODE_C) NextState <= STATE_4;
else NextState <= STATE_3;
end
STATE_4: begin
NextState <= STATE_3;
end
STATE_5_Placeholder: begin
end
STATE_6_Placeholder: begin
end
STATE_7_Placeholder: begin
end
endcase
end
end
//output
always@ (*)
begin
data_out = 1'b0;
debug_out <= FirstOp;
if(CurrentState == STATE_4) data_out = 1'b1;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2021 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
logic [7:0] subnet;
sub1 sub1(.*);
// Test loop
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc == 10) begin
`checkh(subnet, 8'h11);
force sub1.subnet = 8'h01; // sub1.subnet same as subnet
end
else if (cyc == 11) begin
`checkh(subnet, 8'h01);
force subnet = 8'h10; // sub1.subnet same as subnet
end
else if (cyc == 12) begin
`checkh(subnet, 8'h10);
release subnet; // sub1.subnet same as subnet
end
else if (cyc == 13) begin
`checkh(subnet, 8'h11);
end
//
else if (cyc == 99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub1(output logic [7:0] subnet);
assign subnet = 8'h11;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR2_BLACKBOX_V
`define SKY130_FD_SC_HDLL__OR2_BLACKBOX_V
/**
* or2: 2-input OR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__or2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR2_BLACKBOX_V
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Data Up-Sizer
// Mirror data for simple accesses.
// Merge data for burst.
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// w_upsizer
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_8_w_upsizer #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_S_AXI_DATA_WIDTH = 64,
// Width of s_axi_wdata and s_axi_rdata.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_M_AXI_DATA_WIDTH = 32,
// Width of m_axi_wdata and m_axi_rdata.
// Assume always >= than C_S_AXI_DATA_WIDTH.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_M_AXI_REGISTER = 0,
// Clock output data.
// Range: 0, 1
parameter integer C_PACKING_LEVEL = 1,
// 0 = Never pack (expander only); packing logic is omitted.
// 1 = Pack only when CACHE[1] (Modifiable) is high.
// 2 = Always pack, regardless of sub-size transaction or Modifiable bit.
// (Required when used as helper-core by mem-con.)
parameter integer C_S_AXI_BYTES_LOG = 3,
// Log2 of number of 32bit word on SI-side.
parameter integer C_M_AXI_BYTES_LOG = 3,
// Log2 of number of 32bit word on MI-side.
parameter integer C_RATIO = 2,
// Up-Sizing ratio for data.
parameter integer C_RATIO_LOG = 1
// Log2 of Up-Sizing ratio for data.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_valid,
input wire cmd_fix,
input wire cmd_modified,
input wire cmd_complete_wrap,
input wire cmd_packed_wrap,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_first_word,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_next_word,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_last_word,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_offset,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_mask,
input wire [C_S_AXI_BYTES_LOG:0] cmd_step,
input wire [8-1:0] cmd_length,
output wire cmd_ready,
// Slave Interface Write Data Ports
input wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Master Interface Write Data Ports
output wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for SI-side word lanes on MI-side.
genvar word_cnt;
// Generate variable for intra SI-word byte control (on MI-side) for always pack.
genvar byte_cnt;
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam integer C_NEVER_PACK = 0;
localparam integer C_DEFAULT_PACK = 1;
localparam integer C_ALWAYS_PACK = 2;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Sub-word handling.
wire sel_first_word;
wire first_word;
wire [C_M_AXI_BYTES_LOG-1:0] current_word_1;
wire [C_M_AXI_BYTES_LOG-1:0] current_word;
wire [C_M_AXI_BYTES_LOG-1:0] current_word_adjusted;
wire [C_RATIO-1:0] current_word_idx;
wire last_beat;
wire last_word;
wire last_word_extra_carry;
wire [C_M_AXI_BYTES_LOG-1:0] cmd_step_i;
// Sub-word handling for the next cycle.
wire [C_M_AXI_BYTES_LOG-1:0] pre_next_word_i;
wire [C_M_AXI_BYTES_LOG-1:0] pre_next_word;
wire [C_M_AXI_BYTES_LOG-1:0] pre_next_word_1;
wire [C_M_AXI_BYTES_LOG-1:0] next_word_i;
wire [C_M_AXI_BYTES_LOG-1:0] next_word;
// Burst length handling.
wire first_mi_word;
wire [8-1:0] length_counter_1;
reg [8-1:0] length_counter;
wire [8-1:0] next_length_counter;
// Handle wrap buffering.
wire store_in_wrap_buffer_enabled;
wire store_in_wrap_buffer;
wire ARESET_or_store_in_wrap_buffer;
wire use_wrap_buffer;
reg wrap_buffer_available;
// Detect start of MI word.
wire first_si_in_mi;
// Throttling help signals.
wire word_complete_next_wrap;
wire word_complete_next_wrap_qual;
wire word_complete_next_wrap_valid;
wire word_complete_next_wrap_pop;
wire word_complete_next_wrap_last;
wire word_complete_next_wrap_stall;
wire word_complete_last_word;
wire word_complete_rest;
wire word_complete_rest_qual;
wire word_complete_rest_valid;
wire word_complete_rest_pop;
wire word_complete_rest_last;
wire word_complete_rest_stall;
wire word_completed;
wire word_completed_qualified;
wire cmd_ready_i;
wire pop_si_data;
wire pop_mi_data_i;
wire pop_mi_data;
wire mi_stalling;
// Internal SI side control signals.
wire S_AXI_WREADY_I;
// Internal packed write data.
wire use_expander_data;
wire [C_M_AXI_DATA_WIDTH/8-1:0] wdata_qualifier; // For FPGA only
wire [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_qualifier; // For FPGA only
wire [C_M_AXI_DATA_WIDTH/8-1:0] wrap_qualifier; // For FPGA only
wire [C_M_AXI_DATA_WIDTH-1:0] wdata_buffer_i; // For FPGA only
wire [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_buffer_i; // For FPGA only
reg [C_M_AXI_DATA_WIDTH-1:0] wdata_buffer_q; // For RTL only
reg [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_buffer_q; // For RTL only
wire [C_M_AXI_DATA_WIDTH-1:0] wdata_buffer;
wire [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_buffer;
reg [C_M_AXI_DATA_WIDTH-1:0] wdata_last_word_mux;
reg [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_last_word_mux;
reg [C_M_AXI_DATA_WIDTH-1:0] wdata_wrap_buffer_cmb; // For FPGA only
reg [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_wrap_buffer_cmb; // For FPGA only
reg [C_M_AXI_DATA_WIDTH-1:0] wdata_wrap_buffer_q; // For RTL only
reg [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_wrap_buffer_q; // For RTL only
wire [C_M_AXI_DATA_WIDTH-1:0] wdata_wrap_buffer;
wire [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_wrap_buffer;
// Internal signals for MI-side.
wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA_cmb; // For FPGA only
wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA_q; // For FPGA only
reg [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA_I;
wire [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB_cmb; // For FPGA only
wire [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB_q; // For FPGA only
reg [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB_I;
wire M_AXI_WLAST_I;
wire M_AXI_WVALID_I;
wire M_AXI_WREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// Data on the MI-side is available when data a complete word has been
// assembled from the data on SI-side (and potentially from any remainder in
// the wrap buffer).
// No data is produced on the MI-side when a unaligned packed wrap is
// encountered, instead it stored in the wrap buffer to be used when the
// last SI-side data beat is received.
//
// The command is popped from the command queue once the last beat on the
// SI-side has been ackowledged.
//
// The packing process is stalled when a new MI-side is completed but not
// yet acknowledged (by ready).
//
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_RATIO_LOG > 1 ) begin : USE_LARGE_UPSIZING
assign cmd_step_i = {{C_RATIO_LOG-1{1'b0}}, cmd_step};
end else begin : NO_LARGE_UPSIZING
assign cmd_step_i = cmd_step;
end
endgenerate
generate
if ( C_FAMILY == "rtl" ||
( C_PACKING_LEVEL == C_NEVER_PACK ) ) begin : USE_RTL_WORD_COMPLETED
// Detect when MI-side word is completely assembled.
assign word_completed = ( cmd_fix ) |
( ~cmd_fix & ~cmd_complete_wrap & next_word == {C_M_AXI_BYTES_LOG{1'b0}} ) |
( ~cmd_fix & last_word ) |
( ~cmd_modified ) |
( C_PACKING_LEVEL == C_NEVER_PACK );
assign word_completed_qualified = word_completed & cmd_valid & ~store_in_wrap_buffer_enabled;
// RTL equivalent of optimized partial extressions (address wrap for next word).
assign word_complete_next_wrap = ( ~cmd_fix & ~cmd_complete_wrap &
next_word == {C_M_AXI_BYTES_LOG{1'b0}} ) |
( C_PACKING_LEVEL == C_NEVER_PACK );
assign word_complete_next_wrap_qual = word_complete_next_wrap & cmd_valid & ~store_in_wrap_buffer_enabled;
assign word_complete_next_wrap_valid = word_complete_next_wrap_qual & S_AXI_WVALID;
assign word_complete_next_wrap_pop = word_complete_next_wrap_valid & M_AXI_WREADY_I;
assign word_complete_next_wrap_last = word_complete_next_wrap_pop & M_AXI_WLAST_I;
assign word_complete_next_wrap_stall = word_complete_next_wrap_valid & ~M_AXI_WREADY_I;
// RTL equivalent of optimized partial extressions (last word and the remaining).
assign word_complete_last_word = last_word & ~cmd_fix;
assign word_complete_rest = word_complete_last_word | cmd_fix | ~cmd_modified;
assign word_complete_rest_qual = word_complete_rest & cmd_valid & ~store_in_wrap_buffer_enabled;
assign word_complete_rest_valid = word_complete_rest_qual & S_AXI_WVALID;
assign word_complete_rest_pop = word_complete_rest_valid & M_AXI_WREADY_I;
assign word_complete_rest_last = word_complete_rest_pop & M_AXI_WLAST_I;
assign word_complete_rest_stall = word_complete_rest_valid & ~M_AXI_WREADY_I;
end else begin : USE_FPGA_WORD_COMPLETED
wire next_word_wrap;
wire sel_word_complete_next_wrap;
wire sel_word_complete_next_wrap_qual;
wire sel_word_complete_next_wrap_stall;
wire sel_last_word;
wire sel_word_complete_rest;
wire sel_word_complete_rest_qual;
wire sel_word_complete_rest_stall;
// Optimize next word address wrap branch of expression.
//
generic_baseblocks_v2_1_0_comparator_sel_static #
(
.C_FAMILY(C_FAMILY),
.C_VALUE({C_M_AXI_BYTES_LOG{1'b0}}),
.C_DATA_WIDTH(C_M_AXI_BYTES_LOG)
) next_word_wrap_inst
(
.CIN(1'b1),
.S(sel_first_word),
.A(pre_next_word_1),
.B(cmd_next_word),
.COUT(next_word_wrap)
);
assign sel_word_complete_next_wrap = ~cmd_fix & ~cmd_complete_wrap;
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_inst
(
.CIN(next_word_wrap),
.S(sel_word_complete_next_wrap),
.COUT(word_complete_next_wrap)
);
assign sel_word_complete_next_wrap_qual = cmd_valid & ~store_in_wrap_buffer_enabled;
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_valid_inst
(
.CIN(word_complete_next_wrap),
.S(sel_word_complete_next_wrap_qual),
.COUT(word_complete_next_wrap_qual)
);
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_qual_inst
(
.CIN(word_complete_next_wrap_qual),
.S(S_AXI_WVALID),
.COUT(word_complete_next_wrap_valid)
);
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_pop_inst
(
.CIN(word_complete_next_wrap_valid),
.S(M_AXI_WREADY_I),
.COUT(word_complete_next_wrap_pop)
);
assign sel_word_complete_next_wrap_stall = ~M_AXI_WREADY_I;
generic_baseblocks_v2_1_0_carry_latch_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_stall_inst
(
.CIN(word_complete_next_wrap_valid),
.I(sel_word_complete_next_wrap_stall),
.O(word_complete_next_wrap_stall)
);
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_last_inst
(
.CIN(word_complete_next_wrap_pop),
.S(M_AXI_WLAST_I),
.COUT(word_complete_next_wrap_last)
);
// Optimize last word and "rest" branch of expression.
//
assign sel_last_word = ~cmd_fix;
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) last_word_inst_2
(
.CIN(last_word_extra_carry),
.S(sel_last_word),
.COUT(word_complete_last_word)
);
assign sel_word_complete_rest = cmd_fix | ~cmd_modified;
generic_baseblocks_v2_1_0_carry_or #
(
.C_FAMILY(C_FAMILY)
) pop_si_data_inst
(
.CIN(word_complete_last_word),
.S(sel_word_complete_rest),
.COUT(word_complete_rest)
);
assign sel_word_complete_rest_qual = cmd_valid & ~store_in_wrap_buffer_enabled;
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_rest_valid_inst
(
.CIN(word_complete_rest),
.S(sel_word_complete_rest_qual),
.COUT(word_complete_rest_qual)
);
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_rest_qual_inst
(
.CIN(word_complete_rest_qual),
.S(S_AXI_WVALID),
.COUT(word_complete_rest_valid)
);
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_rest_pop_inst
(
.CIN(word_complete_rest_valid),
.S(M_AXI_WREADY_I),
.COUT(word_complete_rest_pop)
);
assign sel_word_complete_rest_stall = ~M_AXI_WREADY_I;
generic_baseblocks_v2_1_0_carry_latch_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_rest_stall_inst
(
.CIN(word_complete_rest_valid),
.I(sel_word_complete_rest_stall),
.O(word_complete_rest_stall)
);
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_rest_last_inst
(
.CIN(word_complete_rest_pop),
.S(M_AXI_WLAST_I),
.COUT(word_complete_rest_last)
);
// Combine the two branches to generate the full signal.
assign word_completed = word_complete_next_wrap | word_complete_rest;
assign word_completed_qualified = word_complete_next_wrap_qual | word_complete_rest_qual;
end
endgenerate
// Pop word from SI-side.
assign S_AXI_WREADY_I = ~mi_stalling & cmd_valid;
assign S_AXI_WREADY = S_AXI_WREADY_I;
// Indicate when there is data available @ MI-side.
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_M_WVALID
assign M_AXI_WVALID_I = S_AXI_WVALID & word_completed_qualified;
end else begin : USE_FPGA_M_WVALID
assign M_AXI_WVALID_I = ( word_complete_next_wrap_valid | word_complete_rest_valid);
end
endgenerate
// Get SI-side data.
generate
if ( C_M_AXI_REGISTER ) begin : USE_REGISTER_SI_POP
assign pop_si_data = S_AXI_WVALID & ~mi_stalling & cmd_valid;
end else begin : NO_REGISTER_SI_POP
if ( C_FAMILY == "rtl" ) begin : USE_RTL_POP_SI
assign pop_si_data = S_AXI_WVALID & S_AXI_WREADY_I;
end else begin : USE_FPGA_POP_SI
assign pop_si_data = ~( word_complete_next_wrap_stall | word_complete_rest_stall ) &
cmd_valid & S_AXI_WVALID;
end
end
endgenerate
// Signal that the command is done (so that it can be poped from command queue).
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_CMD_READY
assign cmd_ready_i = cmd_valid & M_AXI_WLAST_I & pop_mi_data_i;
end else begin : USE_FPGA_CMD_READY
assign cmd_ready_i = ( word_complete_next_wrap_last | word_complete_rest_last);
end
endgenerate
assign cmd_ready = cmd_ready_i;
// Set last upsized word.
assign M_AXI_WLAST_I = S_AXI_WLAST;
/////////////////////////////////////////////////////////////////////////////
// Keep track of data extraction:
//
// Current address is taken form the command buffer for the first data beat
// to handle unaligned Write transactions. After this is the extraction
// address usually calculated from this point.
// FIX transactions uses the same word address for all data beats.
//
// Next word address is generated as current word plus the current step
// size, with masking to facilitate sub-sized wraping. The Mask is all ones
// for normal wraping, and less when sub-sized wraping is used.
//
// The calculated word addresses (current and next) is offseted by the
// current Offset. For sub-sized transaction the Offest points to the least
// significant address of the included data beats. (The least significant
// word is not necessarily the first data to be packed, consider WRAP).
// Offset is only used for sub-sized WRAP transcation that are Complete.
//
// First word is active during the first SI-side data beat.
//
// First MI is set while the entire first MI-side word is processed.
//
// The transaction length is taken from the command buffer combinatorialy
// during the First MI cycle. For each generated MI word it is decreased
// until Last beat is reached.
//
/////////////////////////////////////////////////////////////////////////////
// Select if the offset comes from command queue directly or
// from a counter while when extracting multiple SI words per MI word
assign sel_first_word = first_word | cmd_fix;
assign current_word = sel_first_word ? cmd_first_word :
current_word_1;
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_NEXT_WORD
// Calculate next word.
assign pre_next_word_i = ( next_word_i + cmd_step_i );
// Calculate next word.
assign next_word_i = sel_first_word ? cmd_next_word :
pre_next_word_1;
end else begin : USE_FPGA_NEXT_WORD
wire [C_M_AXI_BYTES_LOG-1:0] next_sel;
wire [C_M_AXI_BYTES_LOG:0] next_carry_local;
// Assign input to local vectors.
assign next_carry_local[0] = 1'b0;
// Instantiate one carry and per level.
for (bit_cnt = 0; bit_cnt < C_M_AXI_BYTES_LOG ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
LUT6_2 # (
.INIT(64'h5A5A_5A66_F0F0_F0CC)
) LUT6_2_inst (
.O6(next_sel[bit_cnt]), // 6/5-LUT output (1-bit)
.O5(next_word_i[bit_cnt]), // 5-LUT output (1-bit)
.I0(cmd_step_i[bit_cnt]), // LUT input (1-bit)
.I1(pre_next_word_1[bit_cnt]), // LUT input (1-bit)
.I2(cmd_next_word[bit_cnt]), // LUT input (1-bit)
.I3(first_word), // LUT input (1-bit)
.I4(cmd_fix), // LUT input (1-bit)
.I5(1'b1) // LUT input (1-bit)
);
MUXCY next_carry_inst
(
.O (next_carry_local[bit_cnt+1]),
.CI (next_carry_local[bit_cnt]),
.DI (cmd_step_i[bit_cnt]),
.S (next_sel[bit_cnt])
);
XORCY next_xorcy_inst
(
.O(pre_next_word_i[bit_cnt]),
.CI(next_carry_local[bit_cnt]),
.LI(next_sel[bit_cnt])
);
end // end for bit_cnt
end
endgenerate
// Calculate next word.
assign next_word = next_word_i & cmd_mask;
assign pre_next_word = pre_next_word_i & cmd_mask;
// Calculate the word address with offset.
assign current_word_adjusted = sel_first_word ? ( cmd_first_word | cmd_offset ) :
( current_word_1 | cmd_offset );
// Prepare next word address.
generate
if ( C_FAMILY == "rtl" || C_M_AXI_REGISTER ) begin : USE_RTL_CURR_WORD
reg [C_M_AXI_BYTES_LOG-1:0] current_word_q;
reg first_word_q;
reg [C_M_AXI_BYTES_LOG-1:0] pre_next_word_q;
always @ (posedge ACLK) begin
if (ARESET) begin
first_word_q <= 1'b1;
current_word_q <= {C_M_AXI_BYTES_LOG{1'b0}};
pre_next_word_q <= {C_M_AXI_BYTES_LOG{1'b0}};
end else begin
if ( pop_si_data ) begin
if ( S_AXI_WLAST ) begin
// Prepare for next access.
first_word_q <= 1'b1;
end else begin
first_word_q <= 1'b0;
end
current_word_q <= next_word;
pre_next_word_q <= pre_next_word;
end
end
end
assign first_word = first_word_q;
assign current_word_1 = current_word_q;
assign pre_next_word_1 = pre_next_word_q;
end else begin : USE_FPGA_CURR_WORD
reg first_word_cmb;
wire first_word_i;
wire [C_M_AXI_BYTES_LOG-1:0] current_word_i;
wire [C_M_AXI_BYTES_LOG-1:0] local_pre_next_word_i;
always @ *
begin
if ( S_AXI_WLAST ) begin
// Prepare for next access.
first_word_cmb = 1'b1;
end else begin
first_word_cmb = 1'b0;
end
end
for (bit_cnt = 0; bit_cnt < C_M_AXI_BYTES_LOG ; bit_cnt = bit_cnt + 1) begin : BIT_LANE
LUT6 # (
.INIT(64'hCCCA_CCCC_CCCC_CCCC)
) LUT6_current_inst (
.O(current_word_i[bit_cnt]), // 6-LUT output (1-bit)
.I0(next_word[bit_cnt]), // LUT input (1-bit)
.I1(current_word_1[bit_cnt]), // LUT input (1-bit)
.I2(word_complete_rest_stall), // LUT input (1-bit)
.I3(word_complete_next_wrap_stall), // LUT input (1-bit)
.I4(cmd_valid), // LUT input (1-bit)
.I5(S_AXI_WVALID) // LUT input (1-bit)
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_current_inst (
.Q(current_word_1[bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(current_word_i[bit_cnt]) // Data input
);
LUT6 # (
.INIT(64'hCCCA_CCCC_CCCC_CCCC)
) LUT6_next_inst (
.O(local_pre_next_word_i[bit_cnt]), // 6-LUT output (1-bit)
.I0(pre_next_word[bit_cnt]), // LUT input (1-bit)
.I1(pre_next_word_1[bit_cnt]), // LUT input (1-bit)
.I2(word_complete_rest_stall), // LUT input (1-bit)
.I3(word_complete_next_wrap_stall), // LUT input (1-bit)
.I4(cmd_valid), // LUT input (1-bit)
.I5(S_AXI_WVALID) // LUT input (1-bit)
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_next_inst (
.Q(pre_next_word_1[bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(local_pre_next_word_i[bit_cnt]) // Data input
);
end // end for bit_cnt
LUT6 # (
.INIT(64'hCCCA_CCCC_CCCC_CCCC)
) LUT6_first_inst (
.O(first_word_i), // 6-LUT output (1-bit)
.I0(first_word_cmb), // LUT input (1-bit)
.I1(first_word), // LUT input (1-bit)
.I2(word_complete_rest_stall), // LUT input (1-bit)
.I3(word_complete_next_wrap_stall), // LUT input (1-bit)
.I4(cmd_valid), // LUT input (1-bit)
.I5(S_AXI_WVALID) // LUT input (1-bit)
);
FDSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) FDSE_first_inst (
.Q(first_word), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.S(ARESET), // Synchronous reset input
.D(first_word_i) // Data input
);
end
endgenerate
// Select command length or counted length.
always @ *
begin
if ( first_mi_word )
length_counter = cmd_length;
else
length_counter = length_counter_1;
end
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_LENGTH
reg [8-1:0] length_counter_q;
reg first_mi_word_q;
// Calculate next length counter value.
assign next_length_counter = length_counter - 1'b1;
// Keep track of burst length.
always @ (posedge ACLK) begin
if (ARESET) begin
first_mi_word_q <= 1'b1;
length_counter_q <= 8'b0;
end else begin
if ( pop_mi_data_i ) begin
if ( M_AXI_WLAST_I ) begin
first_mi_word_q <= 1'b1;
end else begin
first_mi_word_q <= 1'b0;
end
length_counter_q <= next_length_counter;
end
end
end
assign first_mi_word = first_mi_word_q;
assign length_counter_1 = length_counter_q;
end else begin : USE_FPGA_LENGTH
wire [8-1:0] length_counter_i;
wire [8-1:0] length_counter_ii;
wire [8-1:0] length_sel;
wire [8-1:0] length_di;
wire [8:0] length_local_carry;
// Assign input to local vectors.
assign length_local_carry[0] = 1'b0;
for (bit_cnt = 0; bit_cnt < 8 ; bit_cnt = bit_cnt + 1) begin : BIT_LANE
LUT6_2 # (
.INIT(64'h333C_555A_FFF0_FFF0)
) LUT6_length_inst (
.O6(length_sel[bit_cnt]), // 6/5-LUT output (1-bit)
.O5(length_di[bit_cnt]), // 5-LUT output (1-bit)
.I0(length_counter_1[bit_cnt]), // LUT input (1-bit)
.I1(cmd_length[bit_cnt]), // LUT input (1-bit)
.I2(1'b1), // LUT input (1-bit)
.I3(1'b1), // LUT input (1-bit)
.I4(first_mi_word), // LUT input (1-bit)
.I5(1'b1) // LUT input (1-bit)
);
MUXCY carry_inst
(
.O (length_local_carry[bit_cnt+1]),
.CI (length_local_carry[bit_cnt]),
.DI (length_di[bit_cnt]),
.S (length_sel[bit_cnt])
);
XORCY xorcy_inst
(
.O(length_counter_ii[bit_cnt]),
.CI(length_local_carry[bit_cnt]),
.LI(length_sel[bit_cnt])
);
LUT4 # (
.INIT(16'hCCCA)
) LUT4_inst (
.O(length_counter_i[bit_cnt]), // 5-LUT output (1-bit)
.I0(length_counter_1[bit_cnt]), // LUT input (1-bit)
.I1(length_counter_ii[bit_cnt]), // LUT input (1-bit)
.I2(word_complete_rest_pop), // LUT input (1-bit)
.I3(word_complete_next_wrap_pop) // LUT input (1-bit)
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_length_inst (
.Q(length_counter_1[bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(length_counter_i[bit_cnt]) // Data input
);
end // end for bit_cnt
wire first_mi_word_i;
LUT6 # (
.INIT(64'hAAAC_AAAC_AAAC_AAAC)
) LUT6_first_mi_inst (
.O(first_mi_word_i), // 6-LUT output (1-bit)
.I0(M_AXI_WLAST_I), // LUT input (1-bit)
.I1(first_mi_word), // LUT input (1-bit)
.I2(word_complete_rest_pop), // LUT input (1-bit)
.I3(word_complete_next_wrap_pop), // LUT input (1-bit)
.I4(1'b1), // LUT input (1-bit)
.I5(1'b1) // LUT input (1-bit)
);
FDSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) FDSE_inst (
.Q(first_mi_word), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.S(ARESET), // Synchronous reset input
.D(first_mi_word_i) // Data input
);
end
endgenerate
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_LAST_WORD
// Detect last beat in a burst.
assign last_beat = ( length_counter == 8'b0 );
// Determine if this last word that shall be assembled into this MI-side word.
assign last_word = ( cmd_modified & last_beat & ( current_word == cmd_last_word ) );
end else begin : USE_FPGA_LAST_WORD
wire last_beat_curr_word;
generic_baseblocks_v2_1_0_comparator_sel_static #
(
.C_FAMILY(C_FAMILY),
.C_VALUE(8'b0),
.C_DATA_WIDTH(8)
) last_beat_inst
(
.CIN(1'b1),
.S(first_mi_word),
.A(length_counter_1),
.B(cmd_length),
.COUT(last_beat)
);
generic_baseblocks_v2_1_0_comparator_sel #
(
.C_FAMILY(C_FAMILY),
.C_DATA_WIDTH(C_M_AXI_BYTES_LOG)
) last_beat_curr_word_inst
(
.CIN(last_beat),
.S(sel_first_word),
.A(current_word_1),
.B(cmd_first_word),
.V(cmd_last_word),
.COUT(last_beat_curr_word)
);
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) last_word_inst
(
.CIN(last_beat_curr_word),
.S(cmd_modified),
.COUT(last_word)
);
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Handle wrap buffer:
//
// The wrap buffer is used to move data around in an unaligned WRAP
// transaction. SI-side data word(s) for an unaligned accesses are delay
// to be packed with with the tail of the transaction to make it a WRAP
// transaction that is aligned to native MI-side data with.
// For example: an 32bit to 64bit write upsizing @ 0x4 will delay the first
// word until the 0x0 data arrives in the last data beat. This will make the
// Upsized transaction be WRAP at 0x8 on the MI-side
// (was WRAP @ 0x4 on SI-side).
//
/////////////////////////////////////////////////////////////////////////////
// The unaligned SI-side words are pushed into the wrap buffer.
assign store_in_wrap_buffer_enabled = cmd_packed_wrap & ~wrap_buffer_available & cmd_valid;
assign store_in_wrap_buffer = store_in_wrap_buffer_enabled & S_AXI_WVALID;
assign ARESET_or_store_in_wrap_buffer = store_in_wrap_buffer | ARESET;
// The wrap buffer is used to complete last word.
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_USE_WRAP
assign use_wrap_buffer = wrap_buffer_available & last_word;
end else begin : USE_FPGA_USE_WRAP
wire last_word_carry;
carry_and #
(
.C_FAMILY(C_FAMILY)
) last_word_inst2
(
.CIN(last_word),
.S(1'b1),
.COUT(last_word_carry)
);
carry_and #
(
.C_FAMILY(C_FAMILY)
) last_word_inst3
(
.CIN(last_word_carry),
.S(1'b1),
.COUT(last_word_extra_carry)
);
carry_latch_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_stall_inst
(
.CIN(last_word_carry),
.I(wrap_buffer_available),
.O(use_wrap_buffer)
);
end
endgenerate
// Wrap buffer becomes available when the unaligned wrap words has been taken care of.
always @ (posedge ACLK) begin
if (ARESET) begin
wrap_buffer_available <= 1'b0;
end else begin
if ( store_in_wrap_buffer & word_completed ) begin
wrap_buffer_available <= 1'b1;
end else if ( cmd_ready_i ) begin
wrap_buffer_available <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pack multiple data SI-side words into fewer MI-side data word.
// Data is only packed when modify is set. Granularity is SI-side word for
// the combinatorial data mux.
//
// Expander:
// WDATA is expanded to all SI-word lane on the MI-side.
// WSTRB is activted to the correct SI-word lane on the MI-side.
//
// Packer:
// The WDATA and WSTRB registers are always cleared before a new word is
// assembled.
// WDATA is (SI-side word granularity)
// * Combinatorial WDATA is used for current word line or when expanding.
// * All other is taken from registers.
// WSTRB is
// * Combinatorial for single data to matching word lane
// * Zero for single data to mismatched word lane
// * Register data when multiple data
//
// To support sub-sized packing during Always Pack is the combinatorial
// information packed with "or" instead of multiplexing.
//
/////////////////////////////////////////////////////////////////////////////
// Determine if expander data should be used.
assign use_expander_data = ~cmd_modified & cmd_valid;
// Registers and combinatorial data word mux.
generate
for (word_cnt = 0; word_cnt < C_RATIO ; word_cnt = word_cnt + 1) begin : WORD_LANE
// Generate select signal per SI-side word.
if ( C_RATIO == 1 ) begin : SINGLE_WORD
assign current_word_idx[word_cnt] = 1'b1;
end else begin : MULTIPLE_WORD
assign current_word_idx[word_cnt] = current_word_adjusted[C_M_AXI_BYTES_LOG-C_RATIO_LOG +: C_RATIO_LOG] == word_cnt;
end
if ( ( C_PACKING_LEVEL == C_NEVER_PACK ) ) begin : USE_EXPANDER
// Expander only functionality.
if ( C_M_AXI_REGISTER ) begin : USE_REGISTER
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH +: C_S_AXI_DATA_WIDTH] = {C_S_AXI_DATA_WIDTH{1'b0}};
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8 +: C_S_AXI_DATA_WIDTH/8] = {C_S_AXI_DATA_WIDTH/8{1'b0}};
end else begin
if ( pop_si_data ) begin
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH +: C_S_AXI_DATA_WIDTH] = S_AXI_WDATA;
// Multiplex write strobe.
if ( current_word_idx[word_cnt] ) begin
// Combinatorial for last word to MI-side (only word for single).
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8 +: C_S_AXI_DATA_WIDTH/8] = S_AXI_WSTRB;
end else begin
// Use registered strobes. Registers are zero until valid data is written.
// I.e. zero when used for mismatched lanes while expanding.
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8 +: C_S_AXI_DATA_WIDTH/8] = {C_S_AXI_DATA_WIDTH/8{1'b0}};
end
end
end
end
end else begin : NO_REGISTER
always @ *
begin
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH +: C_S_AXI_DATA_WIDTH] = S_AXI_WDATA;
// Multiplex write strobe.
if ( current_word_idx[word_cnt] ) begin
// Combinatorial for last word to MI-side (only word for single).
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8 +: C_S_AXI_DATA_WIDTH/8] = S_AXI_WSTRB;
end else begin
// Use registered strobes. Registers are zero until valid data is written.
// I.e. zero when used for mismatched lanes while expanding.
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8 +: C_S_AXI_DATA_WIDTH/8] = {C_S_AXI_DATA_WIDTH/8{1'b0}};
end
end
end // end if C_M_AXI_REGISTER
end else begin : USE_ALWAYS_PACKER
// Packer functionality
for (byte_cnt = 0; byte_cnt < C_S_AXI_DATA_WIDTH / 8 ; byte_cnt = byte_cnt + 1) begin : BYTE_LANE
if ( C_FAMILY == "rtl" ) begin : USE_RTL_DATA
// Generate extended write data and strobe in wrap buffer.
always @ (posedge ACLK) begin
if (ARESET) begin
wdata_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0;
wstrb_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0;
end else begin
if ( cmd_ready_i ) begin
wdata_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0;
wstrb_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0;
end else if ( current_word_idx[word_cnt] & store_in_wrap_buffer & S_AXI_WSTRB[byte_cnt] ) begin
wdata_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= S_AXI_WDATA[byte_cnt*8 +: 8];
wstrb_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= S_AXI_WSTRB[byte_cnt];
end
end
end
assign wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] =
wdata_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8];
assign wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] =
wstrb_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1];
if ( C_M_AXI_REGISTER ) begin : USE_REGISTER
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0;
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0;
end else begin
if ( ( current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] | use_expander_data ) & pop_si_data & ~store_in_wrap_buffer ) begin
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= S_AXI_WDATA[byte_cnt*8 +: 8];
end else if ( use_wrap_buffer & pop_si_data &
wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] ) begin
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8];
end else if ( pop_mi_data ) begin
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0;
end
if ( current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] & pop_si_data & ~store_in_wrap_buffer ) begin
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= S_AXI_WSTRB[byte_cnt];
end else if ( use_wrap_buffer & pop_si_data &
wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] ) begin
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b1;
end else if ( pop_mi_data ) begin
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0;
end
end
end
end else begin : NO_REGISTER
// Generate extended write data and strobe.
always @ (posedge ACLK) begin
if (ARESET) begin
wdata_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0;
wstrb_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0;
end else begin
if ( pop_mi_data | store_in_wrap_buffer_enabled ) begin
wdata_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0;
wstrb_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0;
end else if ( current_word_idx[word_cnt] & pop_si_data & S_AXI_WSTRB[byte_cnt] ) begin
wdata_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= S_AXI_WDATA[byte_cnt*8 +: 8];
wstrb_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= S_AXI_WSTRB[byte_cnt];
end
end
end
assign wdata_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] =
wdata_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8];
assign wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] =
wstrb_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1];
// Select packed or extended data.
always @ *
begin
// Multiplex data.
if ( ( current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] ) | use_expander_data ) begin
wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = S_AXI_WDATA[byte_cnt*8 +: 8];
end else begin
wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = 8'b0;
end
// Multiplex write strobe.
if ( current_word_idx[word_cnt] ) begin
// Combinatorial for last word to MI-side (only word for single).
wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = S_AXI_WSTRB[byte_cnt];
end else begin
// Use registered strobes. Registers are zero until valid data is written.
// I.e. zero when used for mismatched lanes while expanding.
wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = 1'b0;
end
end
// Merge previous with current data.
always @ *
begin
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] =
( wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] ) |
( wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] ) |
( wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] & use_wrap_buffer );
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] =
( wdata_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] ) |
( wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] ) |
( wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] & {8{use_wrap_buffer}} );
end
end // end if C_M_AXI_REGISTER
end else begin : USE_FPGA_DATA
always @ *
begin
if ( cmd_ready_i ) begin
wdata_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = 8'b0;
wstrb_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = 1'b0;
end else if ( current_word_idx[word_cnt] & store_in_wrap_buffer & S_AXI_WSTRB[byte_cnt] ) begin
wdata_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = S_AXI_WDATA[byte_cnt*8 +: 8];
wstrb_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = S_AXI_WSTRB[byte_cnt];
end else begin
wdata_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] =
wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8];
wstrb_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] =
wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1];
end
end
for (bit_cnt = 0; bit_cnt < 8 ; bit_cnt = bit_cnt + 1) begin : BIT_LANE
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_wdata_inst (
.Q(wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(wdata_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]) // Data input
);
end // end for bit_cnt
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_wstrb_inst (
.Q(wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(wstrb_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]) // Data input
);
if ( C_M_AXI_REGISTER ) begin : USE_REGISTER
assign wdata_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] = ( current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] | use_expander_data ) & pop_si_data & ~store_in_wrap_buffer_enabled;
assign wstrb_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] = current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] & pop_si_data & ~store_in_wrap_buffer_enabled;
assign wrap_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] = use_wrap_buffer & pop_si_data &
wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1];
for (bit_cnt = 0; bit_cnt < 8 ; bit_cnt = bit_cnt + 1) begin : BIT_LANE
LUT6 # (
.INIT(64'hF0F0_F0F0_CCCC_00AA)
) LUT6_data_inst (
.O(M_AXI_WDATA_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // 6-LUT output (1-bit)
.I0(M_AXI_WDATA_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // LUT input (1-bit)
.I1(wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // LUT input (1-bit)
.I2(S_AXI_WDATA[byte_cnt*8+bit_cnt]), // LUT input (1-bit)
.I3(pop_mi_data), // LUT input (1-bit)
.I4(wrap_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)
.I5(wdata_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]) // LUT input (1-bit)
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_wdata_inst (
.Q(M_AXI_WDATA_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(M_AXI_WDATA_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]) // Data input
);
end // end for bit_cnt
LUT6 # (
.INIT(64'hF0F0_F0F0_CCCC_00AA)
) LUT6_strb_inst (
.O(M_AXI_WSTRB_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // 6-LUT output (1-bit)
.I0(M_AXI_WSTRB_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)
.I1(wrap_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)
.I2(S_AXI_WSTRB[byte_cnt]), // LUT input (1-bit)
.I3(pop_mi_data), // LUT input (1-bit)
.I4(wrap_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)
.I5(wstrb_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]) // LUT input (1-bit)
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_wstrb_inst (
.Q(M_AXI_WSTRB_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(M_AXI_WSTRB_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]) // Data input
);
always @ *
begin
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = M_AXI_WDATA_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8];
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = M_AXI_WSTRB_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1];
end
end else begin : NO_REGISTER
assign wdata_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] = current_word_idx[word_cnt] & cmd_valid & S_AXI_WSTRB[byte_cnt];
assign wstrb_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] = current_word_idx[word_cnt] &
S_AXI_WSTRB[byte_cnt] &
cmd_valid & S_AXI_WVALID;
for (bit_cnt = 0; bit_cnt < 8 ; bit_cnt = bit_cnt + 1) begin : BIT_LANE
LUT6 # (
.INIT(64'hCCCA_CCCC_CCCC_CCCC)
) LUT6_data_inst (
.O(wdata_buffer_i[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // 6-LUT output (1-bit)
.I0(S_AXI_WDATA[byte_cnt*8+bit_cnt]), // LUT input (1-bit)
.I1(wdata_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // LUT input (1-bit)
.I2(word_complete_rest_stall), // LUT input (1-bit)
.I3(word_complete_next_wrap_stall), // LUT input (1-bit)
.I4(wdata_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)
.I5(S_AXI_WVALID) // LUT input (1-bit)
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_wdata_inst (
.Q(wdata_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(wdata_buffer_i[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]) // Data input
);
end // end for bit_cnt
LUT6 # (
.INIT(64'h0000_0000_0000_AAAE)
) LUT6_strb_inst (
.O(wstrb_buffer_i[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // 6-LUT output (1-bit)
.I0(wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)
.I1(wstrb_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)
.I2(word_complete_rest_stall), // LUT input (1-bit)
.I3(word_complete_next_wrap_stall), // LUT input (1-bit)
.I4(word_complete_rest_pop), // LUT input (1-bit)
.I5(word_complete_next_wrap_pop) // LUT input (1-bit)
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_wstrb_inst (
.Q(wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET_or_store_in_wrap_buffer), // Synchronous reset input
.D(wstrb_buffer_i[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]) // Data input
);
// Select packed or extended data.
always @ *
begin
// Multiplex data.
if ( ( current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] ) | use_expander_data ) begin
wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = S_AXI_WDATA[byte_cnt*8 +: 8];
end else begin
wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] =
( wdata_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] & {8{wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]}} ) |
( wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] & {8{use_wrap_buffer}} );
end
// Multiplex write strobe.
if ( current_word_idx[word_cnt] ) begin
// Combinatorial for last word to MI-side (only word for single).
wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = S_AXI_WSTRB[byte_cnt] |
( wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] ) |
( wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] & use_wrap_buffer );
end else begin
// Use registered strobes. Registers are zero until valid data is written.
// I.e. zero when used for mismatched lanes while expanding.
wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] =
( wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] ) |
( wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] & use_wrap_buffer );
end
end
// Merge previous with current data.
always @ *
begin
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] =
( wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] );
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] =
( wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] );
end
end // end if C_M_AXI_REGISTER
end // end if C_FAMILY
end // end for byte_cnt
end // end if USE_ALWAYS_PACKER
end // end for word_cnt
endgenerate
/////////////////////////////////////////////////////////////////////////////
// MI-side output handling
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_M_AXI_REGISTER ) begin : USE_REGISTER
reg M_AXI_WLAST_q;
reg M_AXI_WVALID_q;
// Register MI-side Data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_WLAST_q <= 1'b0;
M_AXI_WVALID_q <= 1'b0;
end else begin
if ( M_AXI_WREADY_I ) begin
M_AXI_WLAST_q <= M_AXI_WLAST_I;
M_AXI_WVALID_q <= M_AXI_WVALID_I;
end
end
end
assign M_AXI_WDATA = M_AXI_WDATA_I;
assign M_AXI_WSTRB = M_AXI_WSTRB_I;
assign M_AXI_WLAST = M_AXI_WLAST_q;
assign M_AXI_WVALID = M_AXI_WVALID_q;
assign M_AXI_WREADY_I = ( M_AXI_WVALID_q & M_AXI_WREADY) | ~M_AXI_WVALID_q;
// Get MI-side data.
assign pop_mi_data_i = M_AXI_WVALID_I & M_AXI_WREADY_I;
assign pop_mi_data = M_AXI_WVALID_q & M_AXI_WREADY_I;
// Detect when MI-side is stalling.
assign mi_stalling = ( M_AXI_WVALID_q & ~M_AXI_WREADY_I ) & ~store_in_wrap_buffer_enabled;
end else begin : NO_REGISTER
// Combinatorial MI-side Data.
assign M_AXI_WDATA = M_AXI_WDATA_I;
assign M_AXI_WSTRB = M_AXI_WSTRB_I;
assign M_AXI_WLAST = M_AXI_WLAST_I;
assign M_AXI_WVALID = M_AXI_WVALID_I;
assign M_AXI_WREADY_I = M_AXI_WREADY;
// Get MI-side data.
if ( C_FAMILY == "rtl" ) begin : USE_RTL_POP_MI
assign pop_mi_data_i = M_AXI_WVALID_I & M_AXI_WREADY_I;
end else begin : USE_FPGA_POP_MI
assign pop_mi_data_i = ( word_complete_next_wrap_pop | word_complete_rest_pop);
end
assign pop_mi_data = pop_mi_data_i;
// Detect when MI-side is stalling.
assign mi_stalling = word_completed_qualified & ~M_AXI_WREADY_I;
end
endgenerate
endmodule
|
`define bmp_data_file "./bmp_dat.txt"
`timescale 1ns/1ns
module DMAtest( clk,
rst,
we,
ack_out,
done,
readstart,
mem_adr_i,
mem_dat_o,
mem_dat_i
);
input clk;
input rst;
input readstart;
input we;
input done;
input ack_out;
input [21:0] mem_adr_i;
input [31:0] mem_dat_i;
output reg [31:0] mem_dat_o;
reg [7:0] mem['h4b000-1:'h0]; //define memory address as 0H-F0000H
reg [7:0] Dmem['h4b000-1:'h0];
initial
$readmemh(`bmp_data_file,mem);//read original image data from text file into memory
integer DATAFILE;
initial
DATAFILE =$fopen("post_process_dat.txt");//sobelÔËËã½á¹û
always @ (posedge ack_out or posedge rst) begin
if (rst)
mem_dat_o = 32'd0;
else begin
while (!readstart) @(posedge clk);
if(!we)
mem_dat_o ={mem[mem_adr_i],mem[mem_adr_i+1],mem[mem_adr_i+2],mem[mem_adr_i+3]};
else if (we) begin
while (!done) @(posedge clk);
{Dmem[mem_adr_i],Dmem[mem_adr_i+1],Dmem[mem_adr_i+2],Dmem[mem_adr_i+3]}=mem_dat_i;
// if(ack_out) begin
$fdisplay(DATAFILE, "%0h", Dmem[mem_adr_i]);
$fdisplay(DATAFILE, "%0h", Dmem[mem_adr_i+1]);
$fdisplay(DATAFILE, "%0h", Dmem[mem_adr_i+2]);
$fdisplay(DATAFILE, "%0h", Dmem[mem_adr_i+3]);
// end
end
end
end
endmodule |
module sgpr_simx_wr_port_mux (
wr_port_select,
port0_wr_en,
port0_wr_addr,
port0_wr_data,
port0_wr_mask,
port1_wr_en,
port1_wr_addr,
port1_wr_data,
port1_wr_mask,
port2_wr_en,
port2_wr_addr,
port2_wr_data,
port2_wr_mask,
port3_wr_en,
port3_wr_addr,
port3_wr_data,
port3_wr_mask,
port4_wr_en,
port4_wr_addr,
port4_wr_data,
port4_wr_mask,
port5_wr_en,
port5_wr_addr,
port5_wr_data,
port5_wr_mask,
port6_wr_en,
port6_wr_addr,
port6_wr_data,
port6_wr_mask,
port7_wr_en,
port7_wr_addr,
port7_wr_data,
port7_wr_mask,
muxed_port_wr_en,
muxed_port_wr_addr,
muxed_port_wr_data,
muxed_port_wr_mask
);
output muxed_port_wr_en;
output [8:0] muxed_port_wr_addr;
output [63:0] muxed_port_wr_data;
output [63:0] muxed_port_wr_mask;
input [15:0] wr_port_select;
input port0_wr_en;
input [8:0] port0_wr_addr;
input [63:0] port0_wr_data;
input [63:0] port0_wr_mask;
input port1_wr_en;
input [8:0] port1_wr_addr;
input [63:0] port1_wr_data;
input [63:0] port1_wr_mask;
input port2_wr_en;
input [8:0] port2_wr_addr;
input [63:0] port2_wr_data;
input [63:0] port2_wr_mask;
input port3_wr_en;
input [8:0] port3_wr_addr;
input [63:0] port3_wr_data;
input [63:0] port3_wr_mask;
input port4_wr_en;
input [8:0] port4_wr_addr;
input [63:0] port4_wr_data;
input [63:0] port4_wr_mask;
input port5_wr_en;
input [8:0] port5_wr_addr;
input [63:0] port5_wr_data;
input [63:0] port5_wr_mask;
input port6_wr_en;
input [8:0] port6_wr_addr;
input [63:0] port6_wr_data;
input [63:0] port6_wr_mask;
input port7_wr_en;
input [8:0] port7_wr_addr;
input [63:0] port7_wr_data;
input [63:0] port7_wr_mask;
reg muxed_port_wr_en;
reg [8:0] muxed_port_wr_addr;
reg [63:0] muxed_port_wr_data;
reg [63:0] muxed_port_wr_mask;
always @ (
wr_port_select or
port0_wr_en or
port0_wr_addr or
port0_wr_data or
port0_wr_mask or
port1_wr_en or
port1_wr_addr or
port1_wr_data or
port1_wr_mask or
port2_wr_en or
port2_wr_addr or
port2_wr_data or
port2_wr_mask or
port3_wr_en or
port3_wr_addr or
port3_wr_data or
port3_wr_mask or
port4_wr_en or
port4_wr_addr or
port4_wr_data or
port4_wr_mask or
port5_wr_en or
port5_wr_addr or
port5_wr_data or
port5_wr_mask or
port6_wr_en or
port6_wr_addr or
port6_wr_data or
port6_wr_mask or
port7_wr_en or
port7_wr_addr or
port7_wr_data or
port7_wr_mask
) begin
casex(wr_port_select)
16'h0001:
begin
muxed_port_wr_en <= port0_wr_en;
muxed_port_wr_addr <= port0_wr_addr;
muxed_port_wr_data <= port0_wr_data;
muxed_port_wr_mask <= port0_wr_mask;
end
16'h0002:
begin
muxed_port_wr_en <= port1_wr_en;
muxed_port_wr_addr <= port1_wr_addr;
muxed_port_wr_data <= port1_wr_data;
muxed_port_wr_mask <= port1_wr_mask;
end
16'h0004:
begin
muxed_port_wr_en <= port2_wr_en;
muxed_port_wr_addr <= port2_wr_addr;
muxed_port_wr_data <= port2_wr_data;
muxed_port_wr_mask <= port2_wr_mask;
end
16'h0008:
begin
muxed_port_wr_en <= port3_wr_en;
muxed_port_wr_addr <= port3_wr_addr;
muxed_port_wr_data <= port3_wr_data;
muxed_port_wr_mask <= port3_wr_mask;
end
16'h0010:
begin
muxed_port_wr_en <= port4_wr_en;
muxed_port_wr_addr <= port4_wr_addr;
muxed_port_wr_data <= port4_wr_data;
muxed_port_wr_mask <= port4_wr_mask;
end
16'h0020:
begin
muxed_port_wr_en <= port5_wr_en;
muxed_port_wr_addr <= port5_wr_addr;
muxed_port_wr_data <= port5_wr_data;
muxed_port_wr_mask <= port5_wr_mask;
end
16'h0040:
begin
muxed_port_wr_en <= port6_wr_en;
muxed_port_wr_addr <= port6_wr_addr;
muxed_port_wr_data <= port6_wr_data;
muxed_port_wr_mask <= port6_wr_mask;
end
16'h0080:
begin
muxed_port_wr_en <= port7_wr_en;
muxed_port_wr_addr <= port7_wr_addr;
muxed_port_wr_data <= port7_wr_data;
muxed_port_wr_mask <= port7_wr_mask;
end
16'b0000:
begin
muxed_port_wr_en <= 1'b0;
muxed_port_wr_addr <= {9{1'bx}};
muxed_port_wr_data <= {64{1'bx}};
muxed_port_wr_mask <= {64{1'bx}};
end
default:
begin
muxed_port_wr_en <= 1'bx;
muxed_port_wr_addr <= {9{1'bx}};
muxed_port_wr_data <= {64{1'bx}};
muxed_port_wr_mask <= {64{1'bx}};
end
endcase
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:14:28 05/18/2015
// Design Name: median5x5
// Module Name: /home/vka/Programming/VHDL/workspace/sysrek/skin_color_segm/tb_median5x5.v
// Project Name: vision
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: median5x5
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_median5x5(
);
wire rx_pclk;
wire rx_de;
wire rx_hsync;
wire rx_vsync;
wire [7:0] rx_red;
wire [7:0] rx_green;
wire [7:0] rx_blue;
wire tx_de;
wire tx_hsync;
wire tx_vsync;
wire [7:0] tx_red;
wire [7:0] tx_green;
wire [7:0] tx_blue;
// --------------------------------------
// HDMI input
// --------------------------------------
hdmi_in file_input (
.hdmi_clk(rx_pclk),
.hdmi_de(rx_de),
.hdmi_hs(rx_hsync),
.hdmi_vs(rx_vsync),
.hdmi_r(rx_red),
.hdmi_g(rx_green),
.hdmi_b(rx_blue)
);
// proccessing
reg [7:0] median_r;
reg [7:0] median_g;
reg [7:0] median_b;
wire median;
wire median_de;
wire median_vsync;
wire median_hsync;
median5x5 #
(
.H_SIZE(10'd83)
)
med5
(
.clk(rx_pclk),
.ce(1'b1),
.rst(1'b0),
.mask((rx_red == 8'hFF) ? 1'b1 : 1'b0),
.in_de(rx_de),
.in_vsync(rx_vsync),
.in_hsync(rx_hsync),
.median(median),
.out_de(median_de),
.out_vsync(median_vsync),
.out_hsync(median_hsync)
);
always @(posedge rx_pclk) begin
median_r = (median) ? 8'hFF : 8'h00;
median_g = (median) ? 8'hFF : 8'h00;
median_b = (median) ? 8'hFF : 8'h00;
end
// --------------------------------------
// Output assigment
// --------------------------------------
assign tx_de = median_de;
assign tx_hsync = median_hsync;
assign tx_vsync = median_vsync;
assign tx_red = median_r;
assign tx_green = median_g;
assign tx_blue = median_b;
// --------------------------------------
// HDMI output
// --------------------------------------
hdmi_out file_output (
.hdmi_clk(rx_pclk),
.hdmi_vs(tx_vsync),
.hdmi_de(tx_de),
.hdmi_data({8'b0,tx_red,tx_green,tx_blue})
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg _ranit;
reg rnd;
reg [2:0] a;
reg [2:0] b;
reg [31:0] wide;
// surefire lint_off STMINI
initial _ranit = 0;
wire sigone1 = 1'b1;
wire sigone2 = 1'b1;
reg ok;
parameter [1:0] twounkn = 2'b?; // This gets extended to 2'b??
// Large case statements should be well optimizable.
reg [2:0] anot;
always @ (/*AS*/a) begin
casez (a)
default: anot = 3'b001;
3'd0: anot = 3'b111;
3'd1: anot = 3'b110;
3'd2: anot = 3'b101;
3'd3: anot = 3'b101;
3'd4: anot = 3'b011;
3'd5: anot = 3'b010;
3'd6: anot = 3'b001; // Same so folds with 7
endcase
end
always @ (posedge clk) begin
if (!_ranit) begin
_ranit <= 1;
rnd <= 1;
$write("[%0t] t_case: Running\n", $time);
//
a = 3'b101;
b = 3'b111;
// verilator lint_off CASEX
casex (a)
default: $stop;
3'bx1x: $stop;
3'b100: $stop;
3'bx01: ;
endcase
casez (a)
default: $stop;
3'b?1?: $stop;
3'b100: $stop;
3'b?01: ;
endcase
casez (a)
default: $stop;
{1'b0, twounkn}: $stop;
{1'b1, twounkn}: ;
endcase
casez (b)
default: $stop;
{1'b0, twounkn}: $stop;
{1'b1, twounkn}: ;
// {1'b0, 2'b??}: $stop;
// {1'b1, 2'b??}: ;
endcase
case(a[0])
default: ;
endcase
casex(a)
default: ;
3'b?0?: ;
endcase
// verilator lint_off CASEX
//This is illegal, the default occurs before the statements.
//case(a[0])
// default: $stop;
// 1'b1: ;
//endcase
//
wide = 32'h12345678;
casez (wide)
default: $stop;
32'h12345677,
32'h12345678,
32'h12345679: ;
endcase
//
ok = 0;
casez ({sigone1,sigone2})
//2'b10, 2'b01, 2'bXX: ; // verilator bails at this since in 2 state it can be true...
2'b10, 2'b01: ;
2'b00: ;
default: ok=1'b1;
endcase
if (ok !== 1'b1) $stop;
//
if (rnd) begin
$write("");
end
//
$write("*-* All Finished *-*\n");
$finish;
end
end
// Check parameters in case statements
parameter ALU_DO_REGISTER = 3'h1; // input selected by reg addr.
parameter DSP_REGISTER_V = 6'h03;
reg [2:0] alu_ctl_2s; // Delayed version of alu_ctl
reg [5:0] reg_addr_2s; // Delayed version of reg_addr
reg [7:0] ir_slave_2s; // Instruction Register delayed 2 phases
reg [15:10] f_tmp_2s; // Delayed copy of F
reg p00_2s;
initial begin
alu_ctl_2s = 3'h1;
reg_addr_2s = 6'h3;
ir_slave_2s= 0;
f_tmp_2s= 0;
casex ({alu_ctl_2s,reg_addr_2s,
ir_slave_2s[7],ir_slave_2s[5:4],ir_slave_2s[1:0],
f_tmp_2s[11:10]})
default: p00_2s = 1'b0;
{ALU_DO_REGISTER,DSP_REGISTER_V,1'bx,2'bx,2'bx,2'bx}: p00_2s = 1'b1;
endcase
if (1'b0) $display ("%x %x %x %x", alu_ctl_2s, ir_slave_2s, f_tmp_2s, p00_2s); //Prevent unused
//
case ({1'b1, 1'b1})
default: $stop;
{1'b1, p00_2s}: ;
endcase
end
// Check wide overlapping cases
// surefire lint_off CSEOVR
parameter ANY_STATE = 7'h??;
reg [19:0] foo;
initial begin
foo = {1'b0,1'b0,1'b0,1'b0,1'b0,7'h04,8'b0};
casez (foo)
default: $stop;
{1'b1,1'b?,1'b?,1'b?,1'b?,ANY_STATE,8'b?}: $stop;
{1'b?,1'b1,1'b?,1'b?,1'b?,7'h00,8'b?}: $stop;
{1'b?,1'b?,1'b1,1'b?,1'b?,7'h00,8'b?}: $stop;
{1'b?,1'b?,1'b?,1'b1,1'b?,7'h00,8'b?}: $stop;
{1'b?,1'b?,1'b?,1'b?,1'b?,7'h04,8'b?}: ;
{1'b?,1'b?,1'b?,1'b?,1'b?,7'h06,8'hdf}: $stop;
{1'b?,1'b?,1'b?,1'b?,1'b?,7'h06,8'h00}: $stop;
endcase
end
initial begin
foo = 20'b1010;
casex (foo[3:0])
default: $stop;
4'b0xxx,
4'b100x,
4'b11xx: $stop;
4'b1010: ;
endcase
end
initial begin
foo = 20'b1010;
ok = 1'b0;
// Test of RANGE(CONCAT reductions...
casex ({foo[3:2],foo[1:0],foo[3]})
5'bxx10x: begin ok=1'b0; foo=20'd1; ok=1'b1; end // Check multiple expressions
5'bxx00x: $stop;
5'bxx01x: $stop;
5'bxx11x: $stop;
endcase
if (!ok) $stop;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A222O_BEHAVIORAL_V
`define SKY130_FD_SC_MS__A222O_BEHAVIORAL_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a222o (
X ,
A1,
A2,
B1,
B2,
C1,
C2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire and2_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
and and2 (and2_out , C1, C2 );
or or0 (or0_out_X, and1_out, and0_out, and2_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A222O_BEHAVIORAL_V |
module display(CLK, BPM, PLAY, SEGA, SEGD);
input CLK; // 100MHz clock input
input [7:0] BPM; // 8-bit BPM value
//input [5:0] TONE; // 6-bit tone code
//input [3:0] DURATION; // 4-bit duration code
input PLAY; // Play/Pause Input
output reg [3:0] SEGA; // Display-select (common anode) output
output [7:0] SEGD; // Display-pattern output
wire [11:0] BCD;
reg [3:0] CURRENT_DIG;// Which BCD digit is currently displaying
//assign BCD = 12'h123;
byte_to_BCD btb_blk (BPM, BCD);
bcdtoseg seg_disp_blk (1'b1, 1'b1, CURRENT_DIG[3], CURRENT_DIG[2], CURRENT_DIG[1], CURRENT_DIG[0], 1'b1, /*unconnected*/
, SEGD[7], SEGD[6], SEGD[5], SEGD[4], SEGD[3], SEGD[2], SEGD[1]);
// Turn decimal point off
assign SEGD[0] = 1;
reg [16:0] waveCount;
parameter
KHZ_WAVE = 17'd100000, // The full period of a 1kHz wave with 100MHz clock
DISP_D0 = ~4'b0001,
DISP_D1 = ~4'b0010,
DISP_D2 = ~4'b0100,
DISP_D3 = ~4'b1000,
DISP_OFF = ~4'b0000;
initial begin
waveCount = 0;
// OFF
SEGA = ~4'h0;
CURRENT_DIG[3:0] = 4'h0;
end
always @(posedge CLK) begin
//increment waveCount to use as 1KHz wave
waveCount = waveCount + 1;
//increment the counter to count up to duration
//active contains state of whether you've finished the note or not
//selecting the digit to display
// TODO: Display state on the first digit, e.g. P for paused
if (waveCount < KHZ_WAVE/4) begin
if (~PLAY) begin
SEGA = DISP_D0;
CURRENT_DIG = 4'hF;
end else begin
SEGA = DISP_OFF;
CURRENT_DIG = 4'd0;
end
end else if (waveCount < KHZ_WAVE/2) begin
SEGA = DISP_D1;
CURRENT_DIG = BCD[11:8];
end else if (waveCount < KHZ_WAVE*3/4) begin
SEGA = DISP_D2;
CURRENT_DIG = BCD[7:4];
end else if (waveCount < KHZ_WAVE)begin
SEGA = DISP_D3;
CURRENT_DIG = BCD[3:0];
end else
waveCount = 0;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module fft16TB;
reg ED;
reg RST;
reg CLK;
reg START;
reg ifft;
wire [32-1:0] DIImag;
wire [32-1:0] DIReal;
wire [32+3:0] DOImag;
wire [32+3:0] DOReal;
wire RDY;
reg [4:0] count;
initial
begin
CLK = 1'b0;
forever #5 CLK = ~CLK;
end
initial
begin
ifft = 1'b0;
ED = 1'b1;
RST = 1'b0;
count = 0;
START = 1'b0;
#13 RST =1'b1;
#43 RST =1'b0;
#53 START =1'b1;
#12 START =1'b0;
end
reg [4:0] ct16;
always @(posedge CLK or posedge START)
if (ED) begin
if (START) ct16 = 7'b000_0000;
else ct16 = ct16+ 'd1;
end
wire [31:0] D_R,D_I;
READ_ROM32 UG( .ADDR(ct16) ,
.DATA_RE(D_R), .DATA_IM(D_I));
assign DIImag = D_I;
assign DIReal = D_R;
fft16 UUT(
.ED(ED),
.RST(RST),
.CLK(CLK),
.START(START),
.ifft(ifft),
.DIImag(DIImag),
.DIReal(DIReal),
.DOImag(DOImag),
.DOReal(DOReal),
.RDY(RDY));
always @(posedge RDY)
count <= 17;
always @(posedge CLK)
begin
if(count!=0)
begin
if(count!=17)
$display("count:%d result real:%d imag:%d",count,DOReal,DOImag);
count = count-1;
end
end
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: asyn_64_1.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module asyn_64_1 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw);
input aclr;
input [0:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [0:0] q;
output rdempty;
output [5:0] rdusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire0;
wire sub_wire1;
wire [5:0] sub_wire2;
wire [0:0] q = sub_wire0[0:0];
wire rdempty = sub_wire1;
wire [5:0] rdusedw = sub_wire2[5:0];
dcfifo dcfifo_component (
.rdclk (rdclk),
.wrclk (wrclk),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.rdusedw (sub_wire2),
.rdfull (),
.wrempty (),
.wrfull (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Arria II GX",
dcfifo_component.lpm_numwords = 64,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 1,
dcfifo_component.lpm_widthu = 6,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "64"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "1"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "1"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "64"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "6"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 1 0 INPUT NODEFVAL "data[0..0]"
// Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: rdusedw 0 0 6 0 OUTPUT NODEFVAL "rdusedw[5..0]"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 1 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 1 0 @q 0 0 1 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 6 0 @rdusedw 0 0 6 0
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_64_1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_64_1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_64_1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_64_1.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_64_1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_64_1_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_64_1_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_64_1_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire b;
reg reset;
integer cyc=0;
Testit testit (/*AUTOINST*/
// Outputs
.b (b),
// Inputs
.clk (clk),
.reset (reset));
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
reset <= 1'b0;
end
else if (cyc<10) begin
reset <= 1'b1;
end
else if (cyc<90) begin
reset <= 1'b0;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Testit (clk, reset, b);
input clk;
input reset;
output b;
wire [0:0] c;
wire my_sig;
wire [0:0] d;
genvar i;
generate
for(i = 0; i >= 0; i = i-1) begin: fnxtclk1
fnxtclk fnxtclk1
(.u(c[i]),
.reset(reset),
.clk(clk),
.w(d[i]) );
end
endgenerate
assign b = d[0];
assign c[0] = my_sig;
assign my_sig = 1'b1;
endmodule
module fnxtclk (u, reset, clk, w );
input u;
input reset;
input clk;
output reg w;
always @ (posedge clk or posedge reset) begin
if (reset == 1'b1) begin
w <= 1'b0;
end
else begin
w <= u;
end
end
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// MBT 8-18-2014
//
// BSG Assembler Out (Ring --> Assembler)
//
// prefer ready_o to yumi_o
// prefer yumi_i to ready_i
//
//
// takes a single wide channel and strict round-robin
// distributes it across a number of input channels.
//
// most of the heavy lifting is done by
// bsg_round_robin_fifo_to_fifo. this module
// places a set of fifos between the wide channel
// and the bsg_round_robin_fifo_to_fifo to support
// partial dequeuing from the wide channel.
//
`include "bsg_defines.v"
module bsg_assembler_out #(parameter `BSG_INV_PARAM(width_p )
,parameter `BSG_INV_PARAM(num_in_p )
,parameter `BSG_INV_PARAM(num_out_p )
,parameter out_channel_count_mask_p=(1 << (num_out_p-1)))
(input clk
, input reset
, input calibration_done_i
, input valid_i
, input [num_in_p*width_p-1:0] data_i
, output ready_o // more permissive than yumi_o
, input [`BSG_MAX($clog2(num_in_p)-1,0):0] in_top_channel_i
, input [`BSG_MAX($clog2(num_out_p)-1,0):0] out_top_channel_i
, output [num_out_p-1:0] valid_o
, output [width_p-1:0] data_o [num_out_p-1:0]
, input [num_out_p-1:0] ready_i // we need to peek before deciding what to do.
);
wire [num_in_p-1:0] fifo_valid_vec, fifo_not_full_vec, fifo_deq_vec;
wire [width_p-1:0] fifo_data_vec [num_in_p-1:0];
wire ready_o_tmp = (& fifo_not_full_vec) & calibration_done_i;
// enque if not fifo is full
assign ready_o = ready_o_tmp;
// generate fifos to hold words of input packet
genvar i;
for (i = 0; i < num_in_p; i=i+1)
begin : fifos
bsg_two_fifo #(.width_p(width_p)
,.ready_THEN_valid_p(1)
) ring_packet_fifo
(.clk_i (clk)
,.reset_i(reset)
// input side
,.ready_o(fifo_not_full_vec[i])
,.v_i (valid_i & ready_o_tmp)
,.data_i (data_i[width_p*i+:width_p])
// output side
,.v_o (fifo_valid_vec[i])
,.data_o (fifo_data_vec [i])
,.yumi_i (fifo_deq_vec [i])
);
end
bsg_round_robin_fifo_to_fifo #(.width_p(width_p)
,. num_in_p(num_in_p)
,. num_out_p(num_out_p)
,. out_channel_count_mask_p(out_channel_count_mask_p)
) rr_fifo_to_fifo
(.clk(clk)
,.reset(reset)
,.in_top_channel_i (in_top_channel_i)
,.out_top_channel_i(out_top_channel_i)
,.valid_i(fifo_valid_vec)
,.data_i(fifo_data_vec)
,.yumi_o(fifo_deq_vec)
,.valid_o(valid_o)
,.data_o(data_o)
,.ready_i(ready_i)
);
endmodule // bsg_assembler_out
`BSG_ABSTRACT_MODULE(bsg_assembler_out)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB4TO1_1_V
`define SKY130_FD_SC_HDLL__MUXB4TO1_1_V
/**
* muxb4to1: Buffered 4-input multiplexer.
*
* Verilog wrapper for muxb4to1 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__muxb4to1.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__muxb4to1_1 (
Z ,
D ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input [3:0] D ;
input [3:0] S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__muxb4to1 base (
.Z(Z),
.D(D),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__muxb4to1_1 (
Z,
D,
S
);
output Z;
input [3:0] D;
input [3:0] S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__muxb4to1 base (
.Z(Z),
.D(D),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB4TO1_1_V
|
`define ADDER_WIDTH 008
`define DUMMY_WIDTH 128
`define 3_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule |
//-----------------------------------------------------
// Design Name : parallel_crc_ccitt
// File Name : parallel_crc.v
// Function : CCITT Parallel CRC
// Coder : Deepak Kumar Tala
//-----------------------------------------------------
module parallel_crc_ccitt (
clk ,
reset ,
enable ,
init ,
data_in ,
crc_out
);
//-----------Input Ports---------------
input clk ;
input reset ;
input enable ;
input init ;
input [7:0] data_in ;
//-----------Output Ports---------------
output [15:0] crc_out;
//------------Internal Variables--------
reg [15:0] crc_reg;
wire [15:0] next_crc;
//-------------Code Start-----------------
assign crc_out = crc_reg;
// CRC Control logic
always @ (posedge clk)
if (reset) begin
crc_reg <= 16'hFFFF;
end else if (enable) begin
if (init) begin
crc_reg <= 16'hFFFF;
end else begin
crc_reg <= next_crc;
end
end
// Parallel CRC calculation
assign next_crc[0] = data_in[7] ^ data_in[0] ^ crc_reg[4] ^ crc_reg[11];
assign next_crc[1] = data_in[1] ^ crc_reg[5];
assign next_crc[2] = data_in[2] ^ crc_reg[6];
assign next_crc[3] = data_in[3] ^ crc_reg[7];
assign next_crc[4] = data_in[4] ^ crc_reg[8];
assign next_crc[5] = data_in[7] ^ data_in[5] ^ data_in[0] ^ crc_reg[4] ^ crc_reg[9] ^ crc_reg[11];
assign next_crc[6] = data_in[6] ^ data_in[1] ^ crc_reg[5] ^ crc_reg[10];
assign next_crc[7] = data_in[7] ^ data_in[2] ^ crc_reg[6] ^ crc_reg[11];
assign next_crc[8] = data_in[3] ^ crc_reg[0] ^ crc_reg[7];
assign next_crc[9] = data_in[4] ^ crc_reg[1] ^ crc_reg[8];
assign next_crc[10] = data_in[5] ^ crc_reg[2] ^ crc_reg[9];
assign next_crc[11] = data_in[6] ^ crc_reg[3] ^ crc_reg[10];
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title :
// File :
// Author : Jim MacLeod
// Created : 01-Dec-2011
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
//////////////////////////////////////////////////////////////////
// Float to fixed converts floating point numbers to 16.16 sign
//
//
module flt_fx_rnd
(
input [31:0] fp_in, // Floating point in IEEE fmt
output reg [31:0] int_out // Fixed point integer out
);
//
// 24.8, Z.
// 16.16
// 12.8 U,V
//
wire [7:0] bias_exp; /* Real exponent -127 - 128 */
wire [7:0] bias_exp2; /* Real exponent 2's comp */
wire [39:0] fixed_out2; /* 2's complement of fixed out */
wire [47:0] bias_mant; /* mantissa expanded to 16.16 fmt */
reg [38:0] int_fixed_out;
reg [31:0] fixed_out;
assign bias_mant = {25'h0001, fp_in[22:0]};
assign bias_exp = fp_in[30:23] - 'd127;
assign bias_exp2 = ~bias_exp + 1;
// infinity or NaN - Don't do anything special, will overflow
always @* begin
// zero condition
if (fp_in[30:0] == 31'b0) int_fixed_out = 0;
// negative exponent
else if (bias_exp[7]) int_fixed_out = bias_mant >> bias_exp2;
// positive exponent
else int_fixed_out = bias_mant << bias_exp;
fixed_out = int_fixed_out[38:7] + int_fixed_out[6];
int_out = (fp_in[31]) ? ~fixed_out + 1 : fixed_out;
end
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// BCHDecoderControlCore for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <[email protected]>
// Kibin Park <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <[email protected]>
// Kibin Park <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH decoder output controller core
// Module Name: BCHDecoderOutputControl
// File Name: BCHDecoderOutputControl.v
//
// Version: v1.0.0
//
// Description: BCH decoder output controller core
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module BCHDecoderOutputControl
#
(
parameter AddressWidth = 32 ,
parameter DataWidth = 32 ,
parameter InnerIFLengthWidth = 16 ,
parameter ThisID = 2 ,
parameter Multi = 4 ,
parameter MaxErrorCountBits = 9
)
(
iClock ,
iReset ,
oDstSourceID ,
oDstTargetID ,
oDstOpcode ,
oDstAddress ,
oDstLength ,
oDstCmdValid ,
iDstCmdReady ,
iCmdSourceID ,
iCmdTargetID ,
iCmdOpcode ,
iCmdType ,
iCmdAddress ,
iCmdLength ,
iCmdValid ,
oCmdReady ,
iBypassWriteData ,
iBypassWriteLast ,
iBypassWriteValid ,
oBypassWriteReady ,
iDecWriteData ,
iDecWriteValid ,
iDecWriteLast ,
oDecWriteReady ,
oDstWriteData ,
oDstWriteValid ,
oDstWriteLast ,
iDstWriteReady ,
iDecodeFinished ,
iDecodeSuccess ,
iErrorSum ,
iErrorCountOut ,
oCSReset ,
oDecStandby
);
input iClock ;
input iReset ;
output [4:0] oDstTargetID ;
output [4:0] oDstSourceID ;
output [5:0] oDstOpcode ;
output [AddressWidth - 1:0] oDstAddress ;
output [InnerIFLengthWidth - 1:0] oDstLength ;
output oDstCmdValid ;
input iDstCmdReady ;
input [4:0] iCmdSourceID ;
input [4:0] iCmdTargetID ;
input [5:0] iCmdOpcode ;
input [1:0] iCmdType ;
input [AddressWidth - 1:0] iCmdAddress ;
input [InnerIFLengthWidth - 1:0] iCmdLength ;
input iCmdValid ;
output oCmdReady ;
input [DataWidth - 1:0] iBypassWriteData ;
input iBypassWriteValid ;
input iBypassWriteLast ;
output oBypassWriteReady ;
input [DataWidth - 1:0] iDecWriteData ;
input iDecWriteValid ;
input iDecWriteLast ;
output oDecWriteReady ;
output [DataWidth - 1:0] oDstWriteData ;
output oDstWriteValid ;
output oDstWriteLast ;
input iDstWriteReady ;
input iDecodeFinished ;
input iDecodeSuccess ;
input [MaxErrorCountBits - 1:0] iErrorSum ;
input [4*Multi - 1:0] iErrorCountOut ;
output oCSReset ;
output oDecStandby ;
reg [2:0] rOutMuxSelect ;
reg [4:0] rCmdSourceID ;
reg [4:0] rCmdTargetID ;
reg [5:0] rCmdOpcode ;
reg [1:0] rCmdType ;
reg [AddressWidth - 1:0] rCmdAddress ;
reg [InnerIFLengthWidth - 1:0] rCmdLength ;
reg [DataWidth - 1:0] rBypassWriteData ;
reg rBypassWriteValid ;
reg rBypassWriteLast ;
reg rBypassWriteReady ;
wire [DataWidth - 1:0] wBypassWriteData ;
wire wBypassWriteValid ;
wire wBypassWriteLast ;
reg [DataWidth - 1:0] rDecWriteData ;
reg rDecWriteValid ;
reg rDecWriteLast ;
reg rDecWriteReady ;
wire [DataWidth - 1:0] wDecWriteData ;
wire wDecWriteValid ;
wire wDecWriteLast ;
reg [4:0] rDstTargetID ;
reg [4:0] rDstSourceID ;
reg [5:0] rDstOpcode ;
reg [AddressWidth - 1:0] rDstAddress ;
reg [InnerIFLengthWidth - 1:0] rDstLength ;
reg rDstCmdValid ;
reg [DataWidth - 1:0] rDstWriteData ;
reg rDstWriteValid ;
reg rDstWriteLast ;
wire [DataWidth - 1:0] wErrorCountRegister ;
reg [31:0] rPageDecodeSuccess ;
reg rSpareDecodeSuccess ;
reg [5:0] rWorstCaseErrorCount;
reg [9:0] rTotalErrorCount ;
reg [327:0] rPageErrorInfo ;
reg [4*Multi*33 - 1:0] rChunkErrorCount ;
reg rCrcCheckBit ;
reg rCrcEnable ;
wire [DataWidth - 1:0] wCrcInData ;
wire wCrcInDataValid ;
wire wCrcInDataLast ;
wire wCrcComplete ;
wire wCrcError ;
reg rZeroPadding ;
reg [5:0] rCounter ;
localparam ChunkIteration = 31 ;
localparam ChunkIterationBits = 7 ;
localparam ErrorInfoSize = 10 ;
localparam PageChunkSize = 128 ;
localparam SpareChunkSize = 64 ;
parameter DataWidthDiv = $clog2(DataWidth/8);
reg [ChunkIterationBits - 1:0] rCurLoopCount ;
reg [ChunkIterationBits - 1:0] rGoalLoopCount ;
localparam ECCCtrlCmdType_Bypass = 2'b00 ;
localparam ECCCtrlCmdType_PageDecode = 2'b01 ;
localparam ECCCtrlCmdType_SpareDecode = 2'b10 ;
localparam ECCCtrlCmdType_ErrCntReport = 2'b11 ;
localparam State_Idle = 9'b000000001 ;
localparam State_BypassCmd = 9'b000000010 ;
localparam State_BypassTrf = 9'b000000100 ;
localparam State_ErrCntCmd = 9'b000001000 ;
localparam State_ErrCntTrf = 9'b000010000 ;
localparam State_DecStandby = 9'b000100000 ;
localparam State_DecTrfCmd = 9'b001000000 ;
localparam State_DecTrf = 9'b010000000 ;
localparam State_DecLoop = 9'b100000000 ;
reg [8:0] rCurState ;
reg [8:0] rNextState ;
always @ (posedge iClock)
if (iReset)
rCurState <= State_Idle ;
else
rCurState <= rNextState ;
always @ (*)
case (rCurState)
State_Idle:
if (iCmdValid)
case (iCmdType)
ECCCtrlCmdType_PageDecode:
rNextState <= State_DecStandby;
ECCCtrlCmdType_SpareDecode:
rNextState <= State_DecStandby;
ECCCtrlCmdType_ErrCntReport:
rNextState <= State_ErrCntCmd;
default:
rNextState <= State_BypassCmd;
endcase
else
rNextState <= State_Idle;
State_BypassCmd:
if (iDstCmdReady)
begin
if (rCmdLength == 0)
rNextState <= State_Idle ;
else
rNextState <= State_BypassTrf ;
end
else
rNextState <= State_BypassCmd ;
State_BypassTrf:
rNextState <= (rDstWriteValid && rDstWriteLast && iDstWriteReady) ? State_Idle : State_BypassTrf;
State_ErrCntCmd:
rNextState <= (iDstCmdReady) ? State_ErrCntTrf : State_ErrCntCmd;
State_ErrCntTrf:
rNextState <= (rDstWriteValid && rDstWriteLast && iDstWriteReady) ? State_Idle : State_ErrCntTrf;
State_DecStandby:
rNextState <= (iDecodeFinished) ? State_DecTrfCmd : State_DecStandby;
State_DecTrfCmd:
rNextState <= (iDstCmdReady) ? State_DecTrf : State_DecTrfCmd;
State_DecTrf:
rNextState <= (rDstWriteValid && rDstWriteLast && iDstWriteReady) ? State_DecLoop : State_DecTrf;
State_DecLoop:
rNextState <= (rCurLoopCount == rGoalLoopCount) ? State_Idle : State_DecStandby;
default:
rNextState <= State_Idle;
endcase
always @ (posedge iClock)
if (iReset)
rCounter <= 6'b0;
else
case (rCurState)
State_DecTrf:
if (iDstWriteReady && rDstWriteValid && (rCmdType == ECCCtrlCmdType_SpareDecode))
rCounter <= rCounter + 1'b1;
State_Idle:
rCounter <= 6'b0;
endcase
always @ (posedge iClock)
if (iReset)
rZeroPadding <= 1'b0;
else
case (rCurState)
State_DecTrf:
if ((rCounter == 6'b111110) && iDstWriteReady && rDstWriteValid)
rZeroPadding <= ~rZeroPadding;
State_Idle:
rZeroPadding <= 1'b0;
endcase
always @ (posedge iClock)
if (iReset)
rCurLoopCount <= {(ChunkIterationBits){1'b0}};
else
case (rCurState)
State_DecLoop:
rCurLoopCount <= rCurLoopCount + 1'b1;
State_ErrCntTrf:
rCurLoopCount <= (iDstWriteReady && rDstWriteValid) ? rCurLoopCount + 1'b1 : rCurLoopCount;
State_Idle:
rCurLoopCount <= {(ChunkIterationBits){1'b0}};
endcase
always @ (posedge iClock)
if (iReset)
rGoalLoopCount <= {(ChunkIterationBits){1'b0}};
else
case (rCurState)
State_DecStandby:
if (rCmdType == ECCCtrlCmdType_PageDecode)
rGoalLoopCount <= ChunkIteration;
else
rGoalLoopCount <= {(ChunkIterationBits){1'b0}};
State_ErrCntCmd:
rGoalLoopCount <= ErrorInfoSize;
State_Idle:
rGoalLoopCount <= {(ChunkIterationBits){1'b0}};
endcase
always @ (posedge iClock)
if (iReset)
begin
rCmdSourceID <= 5'b0 ;
rCmdTargetID <= 5'b0 ;
rCmdOpcode <= 6'b0 ;
rCmdType <= 2'b0 ;
rCmdAddress <= {(AddressWidth){1'b0}} ;
rCmdLength <= {(InnerIFLengthWidth){1'b0}} ;
end
else
if (iCmdValid && oCmdReady)
begin
rCmdSourceID <= iCmdSourceID ;
rCmdTargetID <= iCmdTargetID ;
rCmdOpcode <= iCmdOpcode ;
rCmdType <= iCmdType ;
rCmdAddress <= iCmdAddress ;
rCmdLength <= iCmdLength ;
end
always @ (posedge iClock)
if (iReset)
begin
rDstSourceID <= 5'b0 ;
rDstTargetID <= 5'b0 ;
rDstOpcode <= 6'b0 ;
rDstAddress <= {(AddressWidth){1'b0}} ;
rDstLength <= {(InnerIFLengthWidth){1'b0}} ;
end
else
case (rNextState)
State_BypassCmd:
if (rCurState == State_Idle)
begin
rDstSourceID <= iCmdSourceID ;
rDstTargetID <= iCmdTargetID ;
rDstOpcode <= iCmdOpcode ;
rDstAddress <= iCmdAddress ;
rDstLength <= iCmdLength ;
end
State_ErrCntCmd:
if (rCurState == State_Idle)
begin
rDstSourceID <= ThisID ;
rDstTargetID <= 5'b0 ;
rDstOpcode <= 6'b0 ;
rDstAddress <= iCmdAddress ;
rDstLength <= ErrorInfoSize+1 ;
end
State_DecTrfCmd:
if (rCurLoopCount == 0)
begin
rDstSourceID <= ThisID ;
rDstTargetID <= 5'b0 ;
rDstOpcode <= rCmdOpcode ;
rDstAddress <= rCmdAddress ;
if (rCmdType == ECCCtrlCmdType_PageDecode)
rDstLength <= PageChunkSize ;
else
rDstLength <= SpareChunkSize ;
end
State_DecLoop:
if (rCmdType == ECCCtrlCmdType_PageDecode)
rDstAddress <= rDstAddress + (PageChunkSize << DataWidthDiv);
else
rDstAddress <= rDstAddress + (SpareChunkSize << DataWidthDiv);
endcase
always @ (*)
if ((rCurState == State_BypassCmd) || (rCurState == State_ErrCntCmd) || (rCurState == State_DecTrfCmd))
rDstCmdValid <= 1'b1;
else
rDstCmdValid <= 1'b0;
always @ (posedge iClock)
if (iReset)
rCrcCheckBit <= 1'b1;
else
case (rCurState)
State_ErrCntTrf:
if (rNextState == State_Idle)
rCrcCheckBit <= 1'b1;
State_DecLoop:
if (wCrcComplete && wCrcError)
rCrcCheckBit <= 1'b0;
endcase
assign oDstOpcode = rDstOpcode ;
assign oDstTargetID = rDstTargetID ;
assign oDstSourceID = rDstSourceID ;
assign oDstAddress = rDstAddress ;
assign oDstLength = rDstLength ;
assign oDstCmdValid = rDstCmdValid ;
assign oCSReset = (rCmdType == ECCCtrlCmdType_SpareDecode) && (rCurState == State_DecLoop);
assign oDecStandby = (rCurState == State_DecStandby);
always @ (posedge iClock)
if (iReset)
rSpareDecodeSuccess <= 1'b1;
else
if (rCmdType == ECCCtrlCmdType_SpareDecode)
case (rNextState)
State_DecTrfCmd:
if (iDecodeFinished)
begin
if (iDecodeSuccess)
rSpareDecodeSuccess <= 1'b1;
else
rSpareDecodeSuccess <= 1'b0;
end
endcase
always @ (posedge iClock)
if (iReset)
rPageDecodeSuccess <= 32'h0000_0000;
else
if (rCmdType == ECCCtrlCmdType_PageDecode)
case (rNextState)
State_DecTrfCmd:
if (iDecodeFinished)
begin
if (iDecodeSuccess)
rPageDecodeSuccess[rCurLoopCount] <= 1'b1;
else
rPageDecodeSuccess[rCurLoopCount] <= 1'b0;
end
endcase
always @ (posedge iClock)
if (iReset)
rChunkErrorCount <= {(4*Multi*33){1'b0}};
else
case (rNextState)
State_Idle:
if (rCurState == State_ErrCntTrf)
rChunkErrorCount <= {(4*Multi*33){1'b0}};
State_DecTrfCmd:
if (iDecodeFinished)
rChunkErrorCount[4*Multi - 1:0] <= iErrorCountOut;
State_DecLoop:
if (rCmdType == ECCCtrlCmdType_PageDecode)
rChunkErrorCount <= rChunkErrorCount << 4*Multi;
endcase
always @ (posedge iClock)
if (iReset)
rWorstCaseErrorCount <= 6'b0;
else
case (rNextState)
State_Idle:
if (rCurState == State_ErrCntTrf)
rWorstCaseErrorCount <= 6'b0;
State_DecTrfCmd:
if (iDecodeFinished && iDecodeSuccess && (iErrorSum > rWorstCaseErrorCount))
rWorstCaseErrorCount <= iErrorSum;
endcase
always @ (posedge iClock)
if (iReset)
rTotalErrorCount <= 10'b0;
else
case (rNextState)
State_Idle:
if (rCurState == State_ErrCntTrf)
rTotalErrorCount <= 10'b0;
State_DecTrfCmd:
if (iDecodeFinished && iDecodeSuccess)
rTotalErrorCount <= rTotalErrorCount + iErrorSum;
endcase
always @ (posedge iClock)
if (iReset)
rPageErrorInfo <= {(328){1'b0}};
else
case (rCurState)
State_ErrCntCmd:
begin
rPageErrorInfo[324] <= rCrcCheckBit ;
rPageErrorInfo[320] <= rSpareDecodeSuccess ;
rPageErrorInfo[317:312] <= rWorstCaseErrorCount ;
rPageErrorInfo[305:296] <= rTotalErrorCount ;
rPageErrorInfo[295:264] <= rPageDecodeSuccess ;
rPageErrorInfo[263:0] <= rChunkErrorCount ;
end
State_ErrCntTrf:
if (rDstWriteValid && iDstWriteReady)
rPageErrorInfo <= rPageErrorInfo << DataWidth;
endcase
assign wErrorCountRegister[DataWidth - 1:0] = rPageErrorInfo[327:296];
assign wErrCntWriteValid = (rCurState == State_ErrCntTrf);
assign wErrCntWriteLast = (rCurState == State_ErrCntTrf) && (rCurLoopCount == rGoalLoopCount);
assign wCrcInData = rDecWriteData ;
assign wCrcInDataValid = rDecWriteValid && iDstWriteReady ;
CRC_Checker
#
(
.DATA_WIDTH(DataWidth),
.HASH_LENGTH(64),
.INPUT_COUNT_BITS(13),
.INPUT_COUNT(4160)
)
Inst_CrcChencker
(
.i_clk (iClock ),
.i_RESET (iReset ),
.i_execute_crc_chk (1'b1 ),
.i_message_valid (wCrcInDataValid ),
.i_message (wCrcInData ),
.o_crc_chk_start ( ),
.o_last_message (wCrcInDataLast ),
.o_crc_chk_complete (wCrcComplete ),
.o_parity_chk (wCrcError )
);
always @ (posedge iClock)
if (iReset)
rOutMuxSelect <= 3'b000 ;
else
case (rNextState)
State_BypassTrf:
rOutMuxSelect <= 3'b001;
State_ErrCntTrf:
rOutMuxSelect <= 3'b100;
State_DecTrf:
rOutMuxSelect <= 3'b010;
default:
rOutMuxSelect <= 3'b000;
endcase
assign wBypassWriteData = rBypassWriteData ;
assign wBypassWriteLast = rBypassWriteLast ;
assign wBypassWriteValid = rBypassWriteValid ;
assign wDecWriteData = rDecWriteData ;
assign wDecWriteLast = rDecWriteLast ;
assign wDecWriteValid = rDecWriteValid ;
always @ (*)
case (rOutMuxSelect)
3'b001:
begin
rDstWriteData <= wBypassWriteData ;
rDstWriteLast <= wBypassWriteLast ;
rDstWriteValid <= wBypassWriteValid ;
end
3'b010:
if (rCmdType == ECCCtrlCmdType_SpareDecode)
begin
rDstWriteData <= wDecWriteData ;
rDstWriteLast <= rZeroPadding ;
rDstWriteValid <= wDecWriteValid ;
end
else
begin
rDstWriteData <= wDecWriteData ;
rDstWriteLast <= wDecWriteLast ;
rDstWriteValid <= wDecWriteValid ;
end
3'b100:
begin
rDstWriteData <= wErrorCountRegister ;
rDstWriteLast <= wErrCntWriteLast ;
rDstWriteValid <= wErrCntWriteValid ;
end
default:
begin
rDstWriteData <= {(DataWidth){1'b0}} ;
rDstWriteLast <= 1'b0 ;
rDstWriteValid <= 1'b0 ;
end
endcase
always @ (*)
case (rCurState)
State_BypassTrf:
begin
rBypassWriteData <= iBypassWriteData ;
rBypassWriteLast <= iBypassWriteLast ;
rBypassWriteValid <= iBypassWriteValid ;
end
default:
begin
rBypassWriteData <= {(DataWidth){1'b0}} ;
rBypassWriteLast <= 1'b0 ;
rBypassWriteValid <= 1'b0 ;
end
endcase
always @ (*)
case (rCurState)
State_DecTrf:
begin
rDecWriteData <= iDecWriteData ;
rDecWriteLast <= iDecWriteLast ;
rDecWriteValid <= iDecWriteValid ;
end
default:
begin
rDecWriteData <= {(DataWidth){1'b0}} ;
rDecWriteLast <= 1'b0 ;
rDecWriteValid <= 1'b0 ;
end
endcase
always @ (*)
case (rCurState)
State_BypassTrf:
rBypassWriteReady <= iDstWriteReady;
default:
rBypassWriteReady <= 1'b0;
endcase
always @ (*)
case (rCurState)
State_DecTrf:
rDecWriteReady <= iDstWriteReady;
default:
rDecWriteReady <= 1'b0;
endcase
assign oCmdReady = (rCurState == State_Idle) ;
assign oBypassWriteReady = rBypassWriteReady ;
assign oDecWriteReady = rDecWriteReady ;
assign oDstWriteData = rDstWriteData ;
assign oDstWriteValid = rDstWriteValid ;
assign oDstWriteLast = rDstWriteLast ;
endmodule |
(** * Equiv_J: プログラムの同値性 *)
(* * Equiv: Program Equivalence *)
(* $Date: 2011-04-05 21:37:47 -0400 (Tue, 05 Apr 2011) $ *)
Require Export Imp_J.
(* *** Some general advice for homework assignments
- We've tried to make sure that most of the Coq proofs we ask you
to do are similar to proofs that we've provided. Before
starting to work on the homework problems, take the time to work
through our proofs (both informally, on paper, and in Coq) and
make sure you understand them in detail. This will save you a
lot of time.
- The Coq proofs we're doing now are sufficiently complicated that
it is more or less impossible to complete them simply by
"following your nose" or random hacking. You need to start with
an idea about why the property is true and how the proof is
going to go. The best way to do this is to write out at least a
sketch of an informal proof on paper -- one that intuitively
convinces you of the truth of the theorem -- before starting to
work on the formal one.
- Use automation to save work! Some of the proofs in this
chapter's exercises are pretty long if you try to write out all
the cases explicitly. *)
(** *** 宿題割当てについての一般的アドバイス
- Coqによる証明問題は、そこまでに文中で行ってきた証明となるべく同じようにできるようにしています。
宿題に取り組む前に、そこまでの証明を自分でも(紙上とCoqの両方で)やってみなさい。
そして、細部まで理解していることを確認しなさい。
そうすることは、多くの時間を節約することになるでしょう。
- 問題にする Coq の証明はそれなりに複雑なため、
単に怪しそうなところをランダムに探ってみるような方法で解くことはまず無理です。
なぜその性質が真で、どう進めば証明になるかを最初に考える必要があります。
そのための一番良い方法は、形式的な証明を始める前に、
紙の上に非形式的な証明をスケッチでも良いので書いてみることです。
そうすることで、定理が成立することを直観的に確信できます。
- 仕事を減らすために自動化を使いなさい。この章の練習問題の証明のいくつかは、
もしすべての場合を明示的に書き出すとすると、とても長くなります。*)
(* ####################################################### *)
(* * Behavioral Equivalence *)
(** * 振る舞い同値性 *)
(* In the last chapter, we investigated the correctness of a very
simple program transformation: the [optimize_0plus] function. The
programming language we were considering was the first version of
the language of arithmetic expressions -- with no variables -- so
it was very easy to define what it _means_ for a program
transformation to be correct: it should always yield a program
that evaluates to the same number as the original.
To talk about the correctness of program transformations in the
full Imp language, we need to think about the role of variables
and the state. *)
(** 前の章で、簡単なプログラム変換の正しさを調べました。
[optimize_0plus]関数です。
対象としたプログラミング言語は、算術式の言語の最初のバージョンでした。
それには変数もなく、そのためプログラム変換が正しいとはどういうことを意味する(_means_)
かを定義することはとても簡単でした。
つまり、変換の結果得られるプログラムが常に、
それを評価すると元のプログラムと同じ数値になるということでした。
Imp言語全体についてプログラム変換の正しさを語るためには、
変数の役割、および状態について考えなければなりません。*)
(* ####################################################### *)
(* ** Definitions *)
(** ** 定義 *)
(* For [aexp]s and [bexp]s, the definition we want is clear. We say
that two [aexp]s or [bexp]s are _behaviorally equivalent_ if they
evaluate to the same result _in every state_. *)
(** [aexp]と[bexp]については、どう定義すれば良いかは明らかです。
2つの[aexp]または[bexp]が振る舞い同値である(_behaviorally equivalent_)とは、
「すべての状態で」2つの評価結果が同じになることです。*)
Definition aequiv (a1 a2 : aexp) : Prop :=
forall (st:state),
aeval st a1 = aeval st a2.
Definition bequiv (b1 b2 : bexp) : Prop :=
forall (st:state),
beval st b1 = beval st b2.
(* For commands, the situation is a little more subtle. We can't
simply say "two commands are behaviorally equivalent if they
evaluate to the same ending state whenever they are run in the
same initial state," because some commands (in some starting
states) don't terminate in any final state at all! What we need
instead is this: two commands are behaviorally equivalent if, for
any given starting state, they either both diverge or both
terminate in the same final state. A compact way to express this
is "if the first one terminates in a particular state then so does
the second, and vice versa." *)
(** コマンドについては、状況はもうちょっと微妙です。
簡単に「2つのコマンドが振る舞い同値であるとは、
両者を同じ状態から開始すれば同じ状態で終わることである」と言うわけには行きません。
コマンドによっては(特定の状態から開始したときには)
停止しないためどのような状態にもならないことがあるからです!
すると次のように言う必要があります。
2つのコマンドが振る舞い同値であるとは、任意の与えられた状態から両者をスタートすると、
両者ともに発散するか、両者ともに停止して同じ状態になることです。
これを簡潔に表現すると、「1つ目が停止して特定の状態になるならば2つ目も同じになり、
逆もまた成り立つ」となります。*)
Definition cequiv (c1 c2 : com) : Prop :=
forall (st st':state),
(c1 / st || st') <-> (c2 / st || st').
(* **** Exercise: 2 stars, optional (pairs_equiv) *)
(** **** 練習問題: ★★, optional (pairs_equiv) *)
(* Which of the following pairs of programs are equivalent? Write
"yes" or "no" for each one.
(a)
[[
WHILE (BLe (ANum 1) (AId X)) DO
X ::= APlus (AId X) (ANum 1)
END
]]
and
[[
WHILE (BLe (ANum 2) (AId X)) DO
X ::= APlus (AId X) (ANum 1)
END
]]
(* FILL IN HERE *)
(b)
[[
WHILE BTrue DO
WHILE BFalse DO X ::= APlus (AId X) (ANum 1) END
END
]]
and
[[
WHILE BFalse DO
WHILE BTrue DO X ::= APlus (AId X) (ANum 1) END
END
]]
(* FILL IN HERE *)
[] *)
(** 以下のプログラムの対の中で、同値なのはどれでしょうか？
それぞれについて、"yes" か "no" を書きなさい。
(a)
[[
WHILE (BLe (ANum 1) (AId X)) DO
X ::= APlus (AId X) (ANum 1)
END
]]
と
[[
WHILE (BLe (ANum 2) (AId X)) DO
X ::= APlus (AId X) (ANum 1)
END
]]
(* FILL IN HERE *)
(b)
[[
WHILE BTrue DO
WHILE BFalse DO X ::= APlus (AId X) (ANum 1) END
END
]]
と
[[
WHILE BFalse DO
WHILE BTrue DO X ::= APlus (AId X) (ANum 1) END
END
]]
(* FILL IN HERE *)
[] *)
(* ####################################################### *)
(* ** Examples *)
(** ** 例 *)
Theorem aequiv_example:
aequiv (AMinus (AId X) (AId X)) (ANum 0).
Proof.
intros st. simpl. apply minus_diag.
Qed.
Theorem bequiv_example:
bequiv (BEq (AMinus (AId X) (AId X)) (ANum 0)) BTrue.
Proof.
intros st. unfold beval.
rewrite aequiv_example. reflexivity.
Qed.
(* For examples of command equivalence, let's start by looking at
trivial transformations involving [SKIP]: *)
(** コマンドの同値性の例として、
[SKIP]にからんだ自明な変換から見てみましょう: *)
Theorem skip_left: forall c,
cequiv
(SKIP; c)
c.
Proof.
intros c st st'.
split; intros H.
Case "->".
inversion H. subst.
inversion H2. subst.
assumption.
Case "<-".
apply E_Seq with st.
apply E_Skip.
assumption.
Qed.
(* **** Exercise: 2 stars (skip_right) *)
(** **** 練習問題: ★★ (skip_right) *)
Theorem skip_right: forall c,
cequiv
(c; SKIP)
c.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* We can also explore transformations that simplify [IFB]
commands: *)
(** [IFB]コマンドを簡単化する変換を探索することもできます: *)
Theorem IFB_true_simple: forall c1 c2,
cequiv
(IFB BTrue THEN c1 ELSE c2 FI)
c1.
Proof.
intros c1 c2.
split; intros H.
Case "->".
inversion H; subst. assumption. inversion H5.
Case "<-".
apply E_IfTrue. reflexivity. assumption. Qed.
(* Of course, few programmers would be tempted to write a conditional
whose guard is literally [BTrue]. A more interesting case is when
the guard is _equivalent_ to true...
_Theorem_: If [b] is equivalent to [BTrue], then [IFB b THEN c1
ELSE c2 FI] is equivalent to [c1].
_Proof_:
- ([->]) We must show, for all [st] and [st'], that if [IFB b
THEN c1 ELSE c2 FI / st || st'] then [c1 / st || st'].
Proceed by cases on the rules that could possibly have been
used to show [IFB b THEN c1 ELSE c2 FI / st || st'], namely
[E_IfTrue] and [E_IfFalse].
- Suppose the final rule rule in the derivation of [IFB b THEN
c1 ELSE c2 FI / st || st'] was [E_IfTrue]. We then have, by
the premises of [E_IfTrue], that [c1 / st || st']. This is
exactly what we set out to prove.
- On the other hand, suppose the final rule in the derivation
of [IFB b THEN c1 ELSE c2 FI / st || st'] was [E_IfFalse].
We then know that [beval st b = false] and [c2 / st || st'].
Recall that [b] is equivalent to [BTrue], i.e. forall [st],
[beval st b = beval st BTrue]. In particular, this means
that [beval st b = true], since [beval st BTrue = true]. But
this is a contradiction, since [E_IfFalse] requires that
[beval st b = false]. Thus, the final rule could not have
been [E_IfFalse].
- ([<-]) We must show, for all [st] and [st'], that if [c1 / st
|| st'] then [IFB b THEN c1 ELSE c2 FI / st || st'].
Since [b] is equivalent to [BTrue], we know that [beval st b] =
[beval st BTrue] = [true]. Together with the assumption that
[c1 / st || st'], we can apply [E_IfTrue] to derive [IFB b THEN
c1 ELSE c2 FI / st || st']. []
Here is the formal version of this proof: *)
(** もちろん、ガードが[BTrue]そのままである条件文を書こうとするプログラマはほとんどいないでしょう。
より興味深いのは、ガードが真と「同値である」場合です...
「定理」:もし[b]が[BTrue]と同値ならば、[IFB b THEN c1 ELSE c2 FI]は[c1]と同値である。
「証明」:
- ([->]) すべての[st]と[st']に対して、もし[IFB b THEN c1 ELSE c2 FI / st || st']
ならば[c1 / st || st']となることを示す。
[IFB b THEN c1 ELSE c2 FI / st || st']を示すのに使うことができた可能性のある規則、
つまり[E_IfTrue]と[E_IfFalse]とで、場合分けをする。
- [IFB b THEN c1 ELSE c2 FI / st || st']
の導出の最後の規則が[E_IfTrue]であると仮定する。
このとき、[E_IfTrue]の仮定より[c1 / st || st']となる。
これはまさに証明したいことである。
- 一方、[IFB b THEN c1 ELSE c2 FI / st || st']
の導出の最後の規則が[E_IfFalse]と仮定する。
すると、[beval st b = false]かつ[c2 / st || st']となる。
[b]が[BTrue]と同値であったことから、
すべての[st]について、[beval st b = beval st BTrue]が成立する。
これは特に[beval st b = true]を意味する。
なぜなら[beval st BTrue = true]だからである。
しかしこれは矛盾である。なぜなら、
[E_IfFalse]から[beval st b = false]でなければならないからである。
従って、最後の規則は[E_IfFalse]ではあり得ない。
- ([<-]) すべての[st]と[st']について、もし[c1 / st|| st']ならば
[IFB b THEN c1 ELSE c2 FI / st || st']となることを示す。
[b]が[BTrue]と同値であることから、
[beval st b] = [beval st BTrue] = [true]となる。
仮定[c1 / st || st']より[E_IfTrue]が適用でき、
[IFB b THEN c1 ELSE c2 FI / st || st']となる。 []
以下がこの証明の形式化版です: *)
Theorem IFB_true: forall b c1 c2,
bequiv b BTrue ->
cequiv
(IFB b THEN c1 ELSE c2 FI)
c1.
Proof.
intros b c1 c2 Hb.
split; intros H.
Case "->".
inversion H; subst.
SCase "b evaluates to true".
assumption.
SCase "b evaluates to false (contradiction)".
rewrite Hb in H5.
inversion H5.
Case "<-".
apply E_IfTrue; try assumption.
rewrite Hb. reflexivity. Qed.
(* **** Exercise: 2 stars, recommended (IFB_false) *)
(** **** 練習問題: ★★, recommended (IFB_false) *)
Theorem IFB_false: forall b c1 c2,
bequiv b BFalse ->
cequiv
(IFB b THEN c1 ELSE c2 FI)
c2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 3 stars (swap_if_branches) *)
(** **** 練習問題: ★★★ (swap_if_branches) *)
Theorem swap_if_branches: forall b e1 e2,
cequiv
(IFB b THEN e1 ELSE e2 FI)
(IFB BNot b THEN e2 ELSE e1 FI).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* For while loops, there is a similar pair of theorems: a loop whose
guard is equivalent to [BFalse] is equivalent to [SKIP], while a
loop whose guard is equivalent to [BTrue] is equivalent to [WHILE
BTrue DO SKIP END] (or any other non-terminating program). The
first of these facts is easy. *)
(** whileループについては、同様の2つ定理があります:
ガードが[BFalse]と同値であるループは[SKIP]と同値である、というものと、
ガードが[BTrue]と同値であるループは[WHILE BTrue DO SKIP END]
(あるいは他の任意の停止しないプログラム)と同値である、というものです。
1つ目のものは簡単です。*)
Theorem WHILE_false : forall b c,
bequiv b BFalse ->
cequiv
(WHILE b DO c END)
SKIP.
Proof.
intros b c Hb. split; intros H.
Case "->".
inversion H; subst.
SCase "E_WhileEnd".
apply E_Skip.
SCase "E_WhileLoop".
rewrite Hb in H2. inversion H2.
Case "<-".
inversion H; subst.
apply E_WhileEnd.
rewrite Hb.
reflexivity. Qed.
(* **** Exercise: 2 stars (WHILE_false_informal) *)
(** **** 練習問題: ★★ (WHILE_false_informal) *)
(* Write an informal proof of WHILE_false.
(* FILL IN HERE *)
[]
*)
(** WHILE_falseの非形式的証明を記述しなさい。
(* FILL IN HERE *)
[]
*)
(* To prove the second fact, we need an auxiliary lemma stating that
while loops whose guards are equivalent to [BTrue] never
terminate:
_Lemma_: If [b] is equivalent to [BTrue], then it cannot be the
case that [(WHILE b DO c END) / st || st'].
_Proof_: Suppose that [(WHILE b DO c END) / st || st']. We show,
by induction on a derivation of [(WHILE b DO c END) / st || st'],
that this assumption leads to a contradiction.
- Suppose [(WHILE b DO c END) / st || st'] is proved using rule
[E_WhileEnd]. Then by assumption [beval st b = false]. But
this contradicts the assumption that [b] is equivalent to
[BTrue].
- Suppose [(WHILE b DO c END) / st || st'] is proved using rule
[E_WhileLoop]. Then we are given the induction hypothesis
that [(WHILE b DO c END) / st || st'] is contradictory, which
is exactly what we are trying to prove!
- Since these are the only rules that could have been used to
prove [(WHILE b DO c END) / st || st'], the other cases of
the induction are immediately contradictory. [] *)
(** 2つ目の事実を証明するためには、
ガードが[BTrue]と同値であるwhileループが停止しないことを言う補題が1つ必要です:
「補題」:[b]が[BTrue]と同値のとき、
[(WHILE b DO c END) / st || st']となることはない。
「証明」:[(WHILE b DO c END) / st || st']と仮定する。
[(WHILE b DO c END) / st || st']の導出についての帰納法によって、
この仮定から矛盾が導かれることを示す。
- [(WHILE b DO c END) / st || st']が規則[E_WhileEnd]
から証明されると仮定する。すると仮定から[beval st b = false]となる。
しかしこれは、[b]が[BTrue]と同値という仮定と矛盾する。
- [(WHILE b DO c END) / st || st']が規則[E_WhileLoop]
を使って証明されると仮定する。
すると帰納法の仮定として
[(WHILE b DO c END) / st || st']が矛盾するということが得られる。
これはまさに証明しようとしていることである。
- 上記が[(WHILE b DO c END) / st || st']
の証明に使うことができる可能性がある規則のすべてであり、
帰納法の他の場合は、すぐに矛盾になる。[] *)
Lemma WHILE_true_nonterm : forall b c st st',
bequiv b BTrue ->
~( (WHILE b DO c END) / st || st' ).
Proof.
intros b c st st' Hb.
intros H.
remember (WHILE b DO c END) as cw.
ceval_cases (induction H) Case;
(* Most rules don't apply, and we can rule them out
by inversion *)
inversion Heqcw; subst; clear Heqcw.
(* The two interesting cases are the ones for while loops: *)
Case "E_WhileEnd". (* contradictory -- b is always true! *)
rewrite Hb in H. inversion H.
Case "E_WhileLoop". (* immediate from the IH *)
apply IHceval2. reflexivity. Qed.
(* **** Exercise: 2 stars, optional (WHILE_true_nonterm_informal) *)
(** **** 練習問題: ★★, optional (WHILE_true_nonterm_informal) *)
(* Explain what the lemma [WHILE_true_nonterm] means in English.
(* FILL IN HERE *)
*)
(** 補題[WHILE_true_nonterm]が意味するものを日本語で書きなさい。
(* FILL IN HERE *)
*)
(** [] *)
(* **** Exercise: 2 stars, recommended (WHILE_true) *)
(** **** 練習問題: ★★, recommended (WHILE_true) *)
(* You'll want to use [WHILE_true_nonterm] here. *)
(** ここで[WHILE_true_nonterm]を使いなさい。*)
Theorem WHILE_true: forall b c,
bequiv b BTrue ->
cequiv
(WHILE b DO c END)
(WHILE BTrue DO SKIP END).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
Theorem loop_unrolling: forall b c,
cequiv
(WHILE b DO c END)
(IFB b THEN (c; WHILE b DO c END) ELSE SKIP FI).
Proof.
(* WORKED IN CLASS *)
intros b c st st'.
split; intros Hce.
Case "->".
inversion Hce; subst.
SCase "loop doesn't run".
apply E_IfFalse. assumption. apply E_Skip.
SCase "loop runs".
apply E_IfTrue. assumption.
apply E_Seq with (st' := st'0). assumption. assumption.
Case "<-".
inversion Hce; subst.
SCase "loop runs".
inversion H5; subst.
apply E_WhileLoop with (st' := st'0).
assumption. assumption. assumption.
SCase "loop doesn't run".
inversion H5; subst. apply E_WhileEnd. assumption. Qed.
(* **** Exercise: 2 stars, optional (seq_assoc) *)
(** **** 練習問題: ★★, optional (seq_assoc) *)
Theorem seq_assoc : forall c1 c2 c3,
cequiv ((c1;c2);c3) (c1;(c2;c3)).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* Finally, let's look at simple equivalences involving assignments.
This turns out to be a little tricky.
To start with, we might expect to be able to show that certain
kinds of "useless" assignments can be removed. Most trivially: *)
(** 最後に、代入に関する簡単な同値を見てみましょう。
これは、ちょっとトリッキーです。
まず最初に、ある種の「意味のない」代入が除去できることを示せないか、やってみましょう。
一番自明なのは: *)
Theorem identity_assignment_first_try : forall (X:id),
cequiv
(X ::= AId X)
SKIP.
Proof.
intros. split; intro H.
Case "->".
inversion H; subst. simpl.
replace (update st X (st X)) with st.
constructor.
(* But here we're stuck. The goal looks reasonable, but in fact
it is not provable! If we look back at the set of lemmas we
proved about [update] in the last chapter, we can see that
lemma [update_same] almost does the job, but not quite: it
says that the original and updated states agree at all
values, but this is not the same thing as saying that they
are [eq] in Coq's sense! *)
(* しかしここで行き詰まります。ゴールは合理的に見えますが、しかし実は証明できません!
前の章で[update]に関して証明した補題のセットをふりかえってみましょう。
補題[update_same]がほとんどのことをやっていますが、全部ではありません。
[update_same]
は元の状態と更新された状態がすべての値について一致することを言っていますが、
それは、Coqの意味で[eq]だと言っているわけではありません! *)
Admitted.
(* What is going on here? Recall that our states are just functions
from identifiers to values. For Coq, functions are only equal
when their definitions are syntactically the same, modulo
simplification. (This is the only way we can legally apply the
[eq] constructor!) In practice, for functions built up by repeated
uses of the [update] operation, this means that two functions can
be proven equal only if they were constructed using the _same_
[update] operations, applied in the same order. In the theorem
above, the sequence of updates on the first parameter [cequiv] is
one longer than for the second parameter, so it is no wonder that
the equality doesn't hold.
But the problem is quite general. If we try to prove other
"trivial" facts, such as
[[
cequiv (X ::= APlus (AId X ANum 1) ;
X ::= APlus (AId X ANum 1))
(X ::= APlus (AId X ANum 2))
]]
or
[[
cequiv (X ::= ANum 1; Y ::= ANum 2)
(y ::= ANum 2; X ::= ANum 1)
]]
we'll get stuck in the same way: we'll have two functions that
behave the same way on all inputs, but cannot be proven to be [eq]
to each other.
The reasoning principle we would like to use in these situations
is called _functional extensionality_:
[[[
forall x, f x = g x
-------------------
f = g
]]]
Although this principle is not derivable in Coq's built-in logic,
it is safe to add it as an additional _axiom_. *)
(** 何がどうなっているのでしょう？
我々の状態は単に識別子から値への関数であることを思い出してください。
Coqでは、関数同士が等しいとは、その定義が簡単化(simplification)
の範囲での変形を除いて構文的に同じということです。
(簡単化だけが Coq で[eq]コンストラクタに適用することが許されたものなのです!)
実際には、[update]操作の繰り返しで構築された関数については、
2つの関数が等しいと証明できるのは「同じ」[update]操作を同じ順番で適用した場合だけです。
上述の定理では、第一パラメータ[cequiv]のupdateの列は第二パラメータのものより1つ長いので、
等しさが成立しないのも当然です。
しかし、この問題はかなり一般的なものです。
何か別の「自明な」事実、例えば
[[
cequiv (X ::= APlus (AId X ANum 1) ;
X ::= APlus (AId X ANum 1))
(X ::= APlus (AId X ANum 2))
]]
あるいは
[[
cequiv (X ::= ANum 1; Y ::= ANum 2)
(y ::= ANum 2; X ::= ANum 1)
]]
を証明しようとするとき、同じように行き詰まることになります。
つまり、すべての入力に対して同一の振る舞いをする2つの関数が出てくるのですが、
その2つが[eq]であることが証明できないのです。
こういった状況でこれから使おうとしている推論原理は、
関数外延性(_functional extensionality_)と呼ばれます:
[[
forall x, f x = g x
-------------------
f = g
]]
この原理は Coq のビルトインの論理からは導出できませんが、
追加公理(_axiom_)として導入することは安全です。*)
Axiom functional_extensionality : forall {X Y: Type} {f g : X -> Y},
(forall (x: X), f x = g x) -> f = g.
(* It can be shown that adding this axiom doesn't introduce any
inconsistencies into Coq. (In this way, it is similar to adding
one of the classical logic axioms, such as [excluded_middle].)
With the benefit of this axiom we can prove our theorem: *)
(** Coq にこの公理を導入することが矛盾を生むものではないことを示すことができます。
(このように、この公理の導入は、
[excluded_middle]のような古典論理の公理を追加するのと同様なのです。)
この公理のおかげで、先の定理を証明することができます: *)
Theorem identity_assignment : forall (X:id),
cequiv
(X ::= AId X)
SKIP.
Proof.
intros. split; intro H.
Case "->".
inversion H; subst. simpl.
replace (update st X (st X)) with st.
constructor.
apply functional_extensionality. intro.
rewrite update_same; reflexivity.
Case "<-".
inversion H; subst.
assert (st' = (update st' X (st' X))).
apply functional_extensionality. intro.
rewrite update_same; reflexivity.
rewrite H0 at 2.
constructor. reflexivity.
Qed.
(* **** Exercise: 2 stars, recommended (assign_aequiv) *)
(** **** 練習問題: ★★, recommended (assign_aequiv) *)
Theorem assign_aequiv : forall X e,
aequiv (AId X) e ->
cequiv SKIP (X ::= e).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ####################################################### *)
(* * Properties of Behavioral Equivalence *)
(** * 振る舞い同値の性質 *)
(* We now turn to developing some of the properties of the program
equivalences we have defined. *)
(** ここからは、定義したプログラムの同値概念の性質を調べていきましょう。*)
(* ####################################################### *)
(* ** Behavioral Equivalence is an Equivalence *)
(** ** 振る舞い同値は同値関係である *)
(* First, we verify that the equivalences on [aexps], [bexps], and
[com]s really are _equivalences_ -- i.e., that they are reflexive,
symmetric, and transitive: *)
(** 最初に、[aexps]、[bexps]、[com]の同値が、本当に「同値関係」であること、つまり、
反射性、対称性、推移性を持つことを検証します: *)
Lemma refl_aequiv : forall (a : aexp), aequiv a a.
Proof.
intros a st. reflexivity. Qed.
Lemma sym_aequiv : forall (a1 a2 : aexp),
aequiv a1 a2 -> aequiv a2 a1.
Proof.
intros a1 a2 H. intros st. symmetry. apply H. Qed.
Lemma trans_aequiv : forall (a1 a2 a3 : aexp),
aequiv a1 a2 -> aequiv a2 a3 -> aequiv a1 a3.
Proof.
unfold aequiv. intros a1 a2 a3 H12 H23 st.
rewrite (H12 st). rewrite (H23 st). reflexivity. Qed.
Lemma refl_bequiv : forall (b : bexp), bequiv b b.
Proof.
unfold bequiv. intros b st. reflexivity. Qed.
Lemma sym_bequiv : forall (b1 b2 : bexp),
bequiv b1 b2 -> bequiv b2 b1.
Proof.
unfold bequiv. intros b1 b2 H. intros st. symmetry. apply H. Qed.
Lemma trans_bequiv : forall (b1 b2 b3 : bexp),
bequiv b1 b2 -> bequiv b2 b3 -> bequiv b1 b3.
Proof.
unfold bequiv. intros b1 b2 b3 H12 H23 st.
rewrite (H12 st). rewrite (H23 st). reflexivity. Qed.
Lemma refl_cequiv : forall (c : com), cequiv c c.
Proof.
unfold cequiv. intros c st st'. apply iff_refl. Qed.
Lemma sym_cequiv : forall (c1 c2 : com),
cequiv c1 c2 -> cequiv c2 c1.
Proof.
unfold cequiv. intros c1 c2 H st st'.
assert (c1 / st || st' <-> c2 / st || st') as H'.
SCase "Proof of assertion". apply H.
apply iff_sym. assumption.
Qed.
Lemma iff_trans : forall (P1 P2 P3 : Prop),
(P1 <-> P2) -> (P2 <-> P3) -> (P1 <-> P3).
Proof.
intros P1 P2 P3 H12 H23.
inversion H12. inversion H23.
split; intros A.
apply H1. apply H. apply A.
apply H0. apply H2. apply A. Qed.
Lemma trans_cequiv : forall (c1 c2 c3 : com),
cequiv c1 c2 -> cequiv c2 c3 -> cequiv c1 c3.
Proof.
unfold cequiv. intros c1 c2 c3 H12 H23 st st'.
apply iff_trans with (c2 / st || st'). apply H12. apply H23. Qed.
(* ########################################################*)
(* ** Behavioral Equivalence is a Congruence *)
(** ** 振る舞い同値は合同関係である *)
(* Less obviously, behavioral equivalence is also a _congruence_.
That is, the equivalence of two subprograms implies the
equivalence of the whole programs in which they are embedded:
[[[
aequiv a1 a1'
-----------------------------
cequiv (i ::= a1) (i ::= a1')
cequiv c1 c1'
cequiv c2 c2'
------------------------
cequiv (c1;c2) (c1';c2')
]]]
...and so on. (Note that we are using the inference rule notation
here not as part of a definition, but simply to write down some
valid implications in a readable format. We prove these
implications below.)
We will see a concrete example of why these congruence properties
are important in the following section (in the proof of
[fold_constants_com_sound]), but the main idea is that they allow
us to replace a small part of a large program with an equivalent
small part and know that the whole large programs are equivalent
_without_ doing an explicit proof about the non-varying parts --
i.e., the "proof burden" of a small change to a large program is
proportional to the size of the change, not the program. *)
(** よりわかりにくいですが、振る舞い同値は、合同関係(_congruence_)でもあります。
つまり、2つのサブプログラムが同値ならば、それを含むプログラム全体も同値です:
[[
aequiv a1 a1'
-----------------------------
cequiv (i ::= a1) (i ::= a1')
cequiv c1 c1'
cequiv c2 c2'
------------------------
cequiv (c1;c2) (c1';c2')
]]
...などです。
(注意して欲しいのですが、ここで推論規則の記法を使っていますが、これは定義の一部ではありません。
単に正しい含意を読みやすい形で書き出しただけです。
この含意は以下で証明します。)
合同性がなぜ重要なのか、
次の節で具体的な例([fold_constants_com_sound]の証明)によって見ます。
ただ、メインのアイデアは、大きなプログラムの小さな部分を同値の小さな部分で置き換えると、
大きなプログラム全体が元のものと同値になることを、
変化していない部分についての明示的な証明「なしに」わかるということです。
つまり、大きなプログラムの小さな変更についての証明の負担が、
プログラムではなく変更に比例するということです。*)
Theorem CAss_congruence : forall i a1 a1',
aequiv a1 a1' ->
cequiv (CAss i a1) (CAss i a1').
Proof.
intros i a1 a2 Heqv st st'.
split; intros Hceval.
Case "->".
inversion Hceval. subst. apply E_Ass.
rewrite Heqv. reflexivity.
Case "<-".
inversion Hceval. subst. apply E_Ass.
rewrite Heqv. reflexivity. Qed.
(* The congruence property for loops is a little more interesting,
since it requires induction.
_Theorem_: Equivalence is a congruence for [WHILE] -- that is, if
[b1] is equivalent to [b1'] and [c1] is equivalent to [c1'], then
[WHILE b1 DO c1 END] is equivalent to [WHILE b1' DO c1' END].
_Proof_: Suppose [b1] is equivalent to [b1'] and [c1] is
equivalent to [c1']. We must show, for every [st] and [st'], that
[WHILE b1 DO c1 END / st || st'] iff [WHILE b1' DO c1' END / st
|| st']. We consider the two directions separately.
- ([->]) We show that [WHILE b1 DO c1 END / st || st'] implies
[WHILE b1' DO c1' END / st || st'], by induction on a
derivation of [WHILE b1 DO c1 END / st || st']. The only
nontrivial cases are when the final rule in the derivation is
[E_WhileEnd] or [E_WhileLoop].
- [E_WhileEnd]: In this case, the form of the rule gives us
[beval st b1 = false] and [st = st']. But then, since
[b1] and [b1'] are equivalent, we have [beval st b1' =
false], and [E-WhileEnd] applies, giving us [WHILE b1' DO
c1' END / st || st'], as required.
- [E_WhileLoop]: The form of the rule now gives us [beval st
b1 = true], with [c1 / st || st'0] and [WHILE b1 DO c1
END / st'0 || st'] for some state [st'0], with the
induction hypothesis [WHILE b1' DO c1' END / st'0 ||
st'].
Since [c1] and [c1'] are equivalent, we know that [c1' /
st || st'0]. And since [b1] and [b1'] are equivalent, we
have [beval st b1' = true]. Now [E-WhileLoop] applies,
giving us [WHILE b1' DO c1' END / st || st'], as
required.
- ([<-]) Similar. [] *)
(** ループの合同性は帰納法が必要になるので、さらに少しおもしろいものになります。
「定理」:[WHILE]についての同値は合同関係である。
すなわち、もし[b1]が[b1']と同値であり、[c1]が[c1']と同値ならば、
[WHILE b1 DO c1 END]は[WHILE b1' DO c1' END]と同値である。
「証明」:[b1]が[b1']と同値、[c1]が[c1']と同値であるとする。
すべての[st]と[st']について、証明すべきことは、
[WHILE b1 DO c1 END / st || st']の必要十分条件は
[WHILE b1' DO c1' END / st || st']であることである。
必要条件と十分条件の両方向を別々に証明する。
- ([->]) [WHILE b1 DO c1 END / st || st']ならば
[WHILE b1' DO c1' END / st || st']であることを、
[WHILE b1 DO c1 END / st || st']の導出についての帰納法で示す。
自明でないのは、導出の最後の規則が[E_WhileEnd]または[E_WhileLoop]のときだけである。
- [E_WhileEnd]: この場合、
規則の形から[beval st b1 = false]かつ[st = st']となる。
しかし[b1]と[b1']が同値であることから
[beval st b1' = false]になる。
さらに[E-WhileEnd]を適用すると
証明すべき[WHILE b1' DO c1' END / st || st']が得られる。
- [E_WhileLoop]: 規則の形から
[beval st b1 = true]および、ある状態[st'0]について
帰納法の仮定[WHILE b1' DO c1' END / st'0 || st']のもとで、
[c1 / st || st'0]かつ[WHILE b1 DO c1 END / st'0 || st']となる。
[c1]と[c1']が同値であることから、[c1' / st || st'0]となる。
さらに[b1]と[b1']が同値であることから、[beval st b1' = true]となる。
[E-WhileLoop]を適用すると、
証明すべき[WHILE b1' DO c1' END / st || st']が得られる。
- ([<-]) 同様である。
[] *)
Theorem CWhile_congruence : forall b1 b1' c1 c1',
bequiv b1 b1' -> cequiv c1 c1' ->
cequiv (WHILE b1 DO c1 END) (WHILE b1' DO c1' END).
Proof.
unfold bequiv,cequiv.
intros b1 b1' c1 c1' Hb1e Hc1e st st'.
split; intros Hce.
Case "->".
remember (WHILE b1 DO c1 END) as cwhile.
induction Hce; inversion Heqcwhile; subst.
SCase "E_WhileEnd".
apply E_WhileEnd. rewrite <- Hb1e. apply H.
SCase "E_WhileLoop".
apply E_WhileLoop with (st' := st').
SSCase "show loop runs". rewrite <- Hb1e. apply H.
SSCase "body execution".
apply (Hc1e st st'). apply Hce1.
SSCase "subsequent loop execution".
apply IHHce2. reflexivity.
Case "<-".
remember (WHILE b1' DO c1' END) as c'while.
induction Hce; inversion Heqc'while; subst.
SCase "E_WhileEnd".
apply E_WhileEnd. rewrite -> Hb1e. apply H.
SCase "E_WhileLoop".
apply E_WhileLoop with (st' := st').
SSCase "show loop runs". rewrite -> Hb1e. apply H.
SSCase "body execution".
apply (Hc1e st st'). apply Hce1.
SSCase "subsequent loop execution".
apply IHHce2. reflexivity. Qed.
(* **** Exercise: 3 stars, optional (CSeq_congruence) *)
(** **** 練習問題: ★★★, optional (CSeq_congruence) *)
Theorem CSeq_congruence : forall c1 c1' c2 c2',
cequiv c1 c1' -> cequiv c2 c2' ->
cequiv (c1;c2) (c1';c2').
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 3 stars (CIf_congruence) *)
(** **** 練習問題: ★★★ (CIf_congruence) *)
Theorem CIf_congruence : forall b b' c1 c1' c2 c2',
bequiv b b' -> cequiv c1 c1' -> cequiv c2 c2' ->
cequiv (IFB b THEN c1 ELSE c2 FI) (IFB b' THEN c1' ELSE c2' FI).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* For example, here are two equivalent programs and a proof of their
equivalence... *)
(** 同値である2つのプログラムとその同値の証明の例です... *)
Example congruence_example:
cequiv
(X ::= ANum 0;
IFB (BEq (AId X) (ANum 0))
THEN
Y ::= ANum 0
ELSE
Y ::= ANum 42
FI)
(X ::= ANum 0;
IFB (BEq (AId X) (ANum 0))
THEN
Y ::= AMinus (AId X) (AId X) (* <--- changed here *)
ELSE
Y ::= ANum 42
FI).
Proof.
apply CSeq_congruence.
apply refl_cequiv.
apply CIf_congruence.
apply refl_bequiv.
apply CAss_congruence. unfold aequiv. simpl.
symmetry. apply minus_diag.
apply refl_cequiv.
Qed.
(* ####################################################### *)
(* * Case Study: Constant Folding *)
(** * ケーススタディ: 定数畳み込み *)
(* A _program transformation_ is a function that takes a program
as input and produces some variant of the program as its
output. Compiler optimizations such as constant folding are
a canonical example, but there are many others. *)
(** プログラム変換(_program transformation_)とは、
プログラムを入力とし、出力としてそのプログラムの何らかの変形を生成する関数です。
定数畳み込みのようなコンパイラの最適化は標準的な例ですが、それ以外のものもたくさんあります。*)
(* ####################################################### *)
(* ** Soundness of Program Transformations *)
(** ** プログラム変換の健全性 *)
(* A program transformation is _sound_ if it preserves the
behavior of the original program.
We can define a notion of soundness for translations of
[aexp]s, [bexp]s, and [com]s. *)
(** プログラム変換が健全(_sound_)とは、その変換が元のプログラムの振る舞いを保存することです。
[aexp]、[bexp]、[com]の変換の健全性の概念を定義することができます。*)
Definition atrans_sound (atrans : aexp -> aexp) : Prop :=
forall (a : aexp),
aequiv a (atrans a).
Definition btrans_sound (btrans : bexp -> bexp) : Prop :=
forall (b : bexp),
bequiv b (btrans b).
Definition ctrans_sound (ctrans : com -> com) : Prop :=
forall (c : com),
cequiv c (ctrans c).
(* ######################################################## *)
(* ** The Constant-Folding Transformation *)
(** ** 定数畳み込み変換 *)
(* An expression is _constant_ when it contains no variable
references.
Constant folding is an optimization that finds constant
expressions and replaces them by their values. *)
(** 式が定数(_constant_)であるとは、その式が変数参照を含まないことです。
定数畳み込みは、定数式をその値に置換する最適化です。*)
Fixpoint fold_constants_aexp (a : aexp) : aexp :=
match a with
| ANum n => ANum n
| AId i => AId i
| APlus a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) => ANum (n1 + n2)
| (a1', a2') => APlus a1' a2'
end
| AMinus a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) => ANum (n1 - n2)
| (a1', a2') => AMinus a1' a2'
end
| AMult a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) => ANum (n1 * n2)
| (a1', a2') => AMult a1' a2'
end
end.
Example fold_aexp_ex1 :
fold_constants_aexp
(AMult (APlus (ANum 1) (ANum 2)) (AId X))
= AMult (ANum 3) (AId X).
Proof. reflexivity. Qed.
(* Note that this version of constant folding doesn't eliminate
trivial additions, etc. -- we are focusing attention on a single
optimization for the sake of simplicity. It is not hard to
incorporate other ways of simplifying expressions; the definitions
and proofs just get longer. *)
(** 定数畳み込みのこのバージョンは簡単な足し算等を消去していないことに注意します。
複雑になるのを避けるため、1つの最適化に焦点を絞っています。
式の単純化の他の方法を組込むことはそれほど難しいことではありません。
定義と証明が長くなるだけです。*)
Example fold_aexp_ex2 :
fold_constants_aexp
(AMinus (AId X) (APlus (AMult (ANum 0) (ANum 6)) (AId Y)))
= AMinus (AId X) (APlus (ANum 0) (AId Y)).
Proof. reflexivity. Qed.
(* Not only can we lift [fold_constants_aexp] to [bexp]s (in the
[BEq] and [BLe] cases), we can also find constant _boolean_
expressions and reduce them in-place. *)
(** ([BEq]と[BLe]の場合に)[fold_constants_aexp]を[bexp]
に持ち上げることができるだけでなく、定数「ブール」式をみつけてその場で置換することもできます。*)
Fixpoint fold_constants_bexp (b : bexp) : bexp :=
match b with
| BTrue => BTrue
| BFalse => BFalse
| BEq a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) => if beq_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BEq a1' a2'
end
| BLe a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) => if ble_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BLe a1' a2'
end
| BNot b1 =>
match (fold_constants_bexp b1) with
| BTrue => BFalse
| BFalse => BTrue
| b1' => BNot b1'
end
| BAnd b1 b2 =>
match (fold_constants_bexp b1, fold_constants_bexp b2) with
| (BTrue, BTrue) => BTrue
| (BTrue, BFalse) => BFalse
| (BFalse, BTrue) => BFalse
| (BFalse, BFalse) => BFalse
| (b1', b2') => BAnd b1' b2'
end
end.
Example fold_bexp_ex1 :
fold_constants_bexp (BAnd BTrue (BNot (BAnd BFalse BTrue)))
= BTrue.
Proof. reflexivity. Qed.
Example fold_bexp_ex2 :
fold_constants_bexp
(BAnd (BEq (AId X) (AId Y))
(BEq (ANum 0)
(AMinus (ANum 2) (APlus (ANum 1) (ANum 1)))))
= BAnd (BEq (AId X) (AId Y)) BTrue.
Proof. reflexivity. Qed.
(* To fold constants in a command, we apply the appropriate folding
functions on all embedded expressions. *)
(** コマンド内の定数を畳み込みするために、含まれるすべての式に対応する畳み込み関数を適用します。*)
Fixpoint fold_constants_com (c : com) : com :=
match c with
| SKIP =>
SKIP
| i ::= a =>
CAss i (fold_constants_aexp a)
| c1 ; c2 =>
(fold_constants_com c1) ; (fold_constants_com c2)
| IFB b THEN c1 ELSE c2 FI =>
match fold_constants_bexp b with
| BTrue => fold_constants_com c1
| BFalse => fold_constants_com c2
| b' => IFB b' THEN fold_constants_com c1
ELSE fold_constants_com c2 FI
end
| WHILE b DO c END =>
match fold_constants_bexp b with
| BTrue => WHILE BTrue DO SKIP END
| BFalse => SKIP
| b' => WHILE b' DO (fold_constants_com c) END
end
end.
Example fold_com_ex1 :
fold_constants_com
(X ::= APlus (ANum 4) (ANum 5);
Y ::= AMinus (AId X) (ANum 3);
IFB BEq (AMinus (AId X) (AId Y)) (APlus (ANum 2) (ANum 4)) THEN
SKIP
ELSE
Y ::= ANum 0
FI;
IFB BLe (ANum 0) (AMinus (ANum 4) (APlus (ANum 2) (ANum 1))) THEN
Y ::= ANum 0
ELSE
SKIP
FI;
WHILE BEq (AId Y) (ANum 0) DO
X ::= APlus (AId X) (ANum 1)
END) =
(X ::= ANum 9;
Y ::= AMinus (AId X) (ANum 3);
IFB BEq (AMinus (AId X) (AId Y)) (ANum 6) THEN
SKIP
ELSE
(Y ::= ANum 0)
FI;
Y ::= ANum 0;
WHILE BEq (AId Y) (ANum 0) DO
X ::= APlus (AId X) (ANum 1)
END).
Proof. reflexivity. Qed.
(* ################################################### *)
(* ** Soundness of Constant Folding *)
(** ** 定数畳み込みの健全性 *)
(* Now we need to show that what we've done is correct. Here's
the proof for arithmetic expressions: *)
(** 上でやったことが正しいことを示さなければなりません。以下が算術式に対する証明です: *)
Theorem fold_constants_aexp_sound :
atrans_sound fold_constants_aexp.
Proof.
unfold atrans_sound. intros a. unfold aequiv. intros st.
aexp_cases (induction a) Case; simpl;
(* ANum and AId follow immediately *)
try reflexivity;
(* APlus, AMinus, and AMult follow from the IH
and the observation that
aeval st (APlus a1 a2)
= ANum ((aeval st a1) + (aeval st a2))
= aeval st (ANum ((aeval st a1) + (aeval st a2)))
(and similarly for AMinus/minus and AMult/mult) *)
try (destruct (fold_constants_aexp a1);
destruct (fold_constants_aexp a2);
rewrite IHa1; rewrite IHa2; reflexivity). Qed.
(* **** Exercise: 3 stars, optional (fold_bexp_BEq_informal) *)
(** **** 練習問題: ★★★, optional (fold_bexp_BEq_informal) *)
(* Here is an informal proof of the [BEq] case of the soundness
argument for boolean expression constant folding. Read it
carefully and compare it to the formal proof that follows. Then
fill in the [BLe] case of the formal proof (without looking at the
[BEq] case, if possible).
_Theorem_: The constant folding function for booleans,
[fold_constants_bexp], is sound.
_Proof_: We must show that [b] is equivalent to [fold_constants_bexp],
for all boolean expressions [b]. Proceed by induction on [b]. We
show just the case where [b] has the form [BEq a1 a2].
In this case, we must show
[[
beval st (BEq a1 a2)
= beval st (fold_constants_bexp (BEq a1 a2)).
]]
There are two cases to consider:
- First, suppose [fold_constants_aexp a1 = ANum n1] and
[fold_constants_aexp a2 = ANum n2] for some [n1] and [n2].
In this case, we have
[[
fold_constants_bexp (BEq a1 a2)
= if beq_nat n1 n2 then BTrue else BFalse
]]
and
[[
beval st (BEq a1 a2)
= beq_nat (aeval st a1) (aeval st a2).
]]
By the soundness of constant folding for arithmetic
expressions (Lemma [fold_constants_aexp_sound]), we know
[[
aeval st a1
= aeval st (fold_constants_aexp a1)
= aeval st (ANum n1)
= n1
]]
and
[[
aeval st a2
= aeval st (fold_constants_aexp a2)
= aeval st (ANum n2)
= n2,
]]
so
[[
beval st (BEq a1 a2)
= beq_nat (aeval a1) (aeval a2)
= beq_nat n1 n2.
]]
Also, it is easy to see (by considering the cases [n1 = n2] and
[n1 <> n2] separately) that
[[
beval st (if beq_nat n1 n2 then BTrue else BFalse)
= if beq_nat n1 n2 then beval st BTrue else beval st BFalse
= if beq_nat n1 n2 then true else false
= beq_nat n1 n2.
]]
So
[[
beval st (BEq a1 a2)
= beq_nat n1 n2.
= beval st (if beq_nat n1 n2 then BTrue else BFalse),
]]
as required.
- Otherwise, one of [fold_constants_aexp a1] and
[fold_constants_aexp a2] is not a constant. In this case, we
must show
[[
beval st (BEq a1 a2)
= beval st (BEq (fold_constants_aexp a1)
(fold_constants_aexp a2)),
]]
which, by the definition of [beval], is the same as showing
[[
beq_nat (aeval st a1) (aeval st a2)
= beq_nat (aeval st (fold_constants_aexp a1))
(aeval st (fold_constants_aexp a2)).
]]
But the soundness of constant folding for arithmetic
expressions ([fold_constants_aexp_sound]) gives us
[[
aeval st a1 = aeval st (fold_constants_aexp a1)
aeval st a2 = aeval st (fold_constants_aexp a2),
]]
completing the case. []
*)
(** ここに、ブール式の定数畳み込みに関する健全性の議論の[BEq]の場合の非形式的証明を示します。
これを丁寧に読みその後の形式的証明と比較しなさい。
次に、形式的証明の[BLe]部分を(もし可能ならば[BEq]の場合を見ないで)記述しなさい。
「定理」:ブール式に対する定数畳み込み関数[fold_constants_bexp]は健全である。
「証明」:すべてのブール式[b]について[b]が[fold_constants_bexp]
と同値であることを示す。
[b]についての帰納法を行う。
[b]が[BEq a1 a2]という形の場合を示す。
この場合、
[[
beval st (BEq a1 a2)
= beval st (fold_constants_bexp (BEq a1 a2)).
]]
を示せば良い。これには2種類の場合がある:
- 最初に、ある[n1]と[n2]について、[fold_constants_aexp a1 = ANum n1]かつ
[fold_constants_aexp a2 = ANum n2]と仮定する。
この場合、
[[
fold_constants_bexp (BEq a1 a2)
= if beq_nat n1 n2 then BTrue else BFalse
]]
かつ
[[
beval st (BEq a1 a2)
= beq_nat (aeval st a1) (aeval st a2).
]]
となる。
算術式についての定数畳み込みの健全性(補題[fold_constants_aexp_sound])より、
[[
aeval st a1
= aeval st (fold_constants_aexp a1)
= aeval st (ANum n1)
= n1
]]
かつ
[[
aeval st a2
= aeval st (fold_constants_aexp a2)
= aeval st (ANum n2)
= n2,
]]
である。
従って、
[[
beval st (BEq a1 a2)
= beq_nat (aeval a1) (aeval a2)
= beq_nat n1 n2.
]]
となる。また、([n1 = n2]と[n1 <> n2]の場合をそれぞれ考えると)
[[
beval st (if beq_nat n1 n2 then BTrue else BFalse)
= if beq_nat n1 n2 then beval st BTrue else beval st BFalse
= if beq_nat n1 n2 then true else false
= beq_nat n1 n2.
]]
となることは明らかである。
ゆえに
[[
beval st (BEq a1 a2)
= beq_nat n1 n2.
= beval st (if beq_nat n1 n2 then BTrue else BFalse),
]]
となる。これは求められる性質である。
- それ以外の場合、[fold_constants_aexp a1]と[fold_constants_aexp a2]
のどちらかは定数ではない。この場合、
[[
beval st (BEq a1 a2)
= beval st (BEq (fold_constants_aexp a1)
(fold_constants_aexp a2)),
]]
を示せば良い。
[beval]の定義から、これは
[[
beq_nat (aeval st a1) (aeval st a2)
= beq_nat (aeval st (fold_constants_aexp a1))
(aeval st (fold_constants_aexp a2)).
]]
を示すことと同じである。
算術式についての定数畳み込みの健全性([fold_constants_aexp_sound])より、
[[
aeval st a1 = aeval st (fold_constants_aexp a1)
aeval st a2 = aeval st (fold_constants_aexp a2),
]]
となり、この場合も成立する。[]
*)
Theorem fold_constants_bexp_sound:
btrans_sound fold_constants_bexp.
Proof.
unfold btrans_sound. intros b. unfold bequiv. intros st.
bexp_cases (induction b) Case;
(* BTrue and BFalse are immediate *)
try reflexivity.
Case "BEq".
(* Doing induction when there are a lot of constructors makes
specifying variable names a chore, but Coq doesn't always
choose nice variable names. We can rename entries in the
context with the [rename] tactic: [rename a into a1] will
change [a] to [a1] in the current goal and context. *)
rename a into a1. rename a0 into a2. simpl.
remember (fold_constants_aexp a1) as a1'.
remember (fold_constants_aexp a2) as a2'.
replace (aeval st a1) with (aeval st a1') by
(subst a1'; rewrite <- fold_constants_aexp_sound; reflexivity).
replace (aeval st a2) with (aeval st a2') by
(subst a2'; rewrite <- fold_constants_aexp_sound; reflexivity).
destruct a1'; destruct a2'; try reflexivity.
(* The only interesting case is when both a1 and a2
become constants after folding *)
simpl. destruct (beq_nat n n0); reflexivity.
Case "BLe".
(* FILL IN HERE *) admit.
Case "BNot".
simpl. remember (fold_constants_bexp b) as b'.
rewrite IHb.
destruct b'; reflexivity.
Case "BAnd".
simpl.
remember (fold_constants_bexp b1) as b1'.
remember (fold_constants_bexp b2) as b2'.
rewrite IHb1. rewrite IHb2.
destruct b1'; destruct b2'; reflexivity. Qed.
(** [] *)
(* **** Exercise: 3 stars (fold_constants_com_sound) *)
(** **** 練習問題: ★★★ (fold_constants_com_sound) *)
(* Complete the [WHILE] case of the following proof. *)
(** 次の証明の[WHILE]の場合を完成させなさい。*)
Theorem fold_constants_com_sound :
ctrans_sound fold_constants_com.
Proof.
unfold ctrans_sound. intros c.
com_cases (induction c) Case; simpl.
Case "SKIP". apply refl_cequiv.
Case "::=". apply CAss_congruence. apply fold_constants_aexp_sound.
Case ";". apply CSeq_congruence; assumption.
Case "IFB".
assert (bequiv b (fold_constants_bexp b)).
SCase "Pf of assertion". apply fold_constants_bexp_sound.
remember (fold_constants_bexp b) as b'.
destruct b';
(* If the optimization doesn't eliminate the if, then the result
is easy to prove from the IH and fold_constants_bexp_sound *)
try (apply CIf_congruence; assumption).
SCase "b always true".
apply trans_cequiv with c1; try assumption.
apply IFB_true; assumption.
SCase "b always false".
apply trans_cequiv with c2; try assumption.
apply IFB_false; assumption.
Case "WHILE".
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################################## *)
(* *** Soundness of (0 + n) Elimination, Redux *)
(** *** (0 + n)の消去の健全性、再び *)
(* **** Exercise: 4 stars, optional (optimize_0plus) *)
(** **** 練習問題: ★★★★, optional (optimize_0plus) *)
(* Recall the definition [optimize_0plus] from Imp.v:
[[
Fixpoint optimize_0plus (e:aexp) : aexp :=
match e with
| ANum n =>
ANum n
| APlus (ANum 0) e2 =>
optimize_0plus e2
| APlus e1 e2 =>
APlus (optimize_0plus e1) (optimize_0plus e2)
| AMinus e1 e2 =>
AMinus (optimize_0plus e1) (optimize_0plus e2)
| AMult e1 e2 =>
AMult (optimize_0plus e1) (optimize_0plus e2)
end.
]]
Note that this function is defined over the old [aexp]s,
without states.
Write a new version of this function that accounts for variables,
and analogous ones for [bexp]s and commands:
[[
optimize_0plus_aexp
optimize_0plus_bexp
optimize_0plus_com
]]
Prove that these three functions are sound, as we did for
[fold_constants_*]. Make sure you use the congruence lemmas in
the proof of [optimize_0plus_com] (otherwise it will be _long_!).
Then define an optimizer on commands that first folds
constants (using [fold_constants_com]) and then eliminates [0 + n]
terms (using [optimize_0plus_com]).
- Give a meaningful example of this optimizer's output.
- Prove that the optimizer is sound. (This part should be _very_
easy.) *)
(** Imp_J.vの[optimize_0plus]の定義をふり返ります。
[[
Fixpoint optimize_0plus (e:aexp) : aexp :=
match e with
| ANum n =>
ANum n
| APlus (ANum 0) e2 =>
optimize_0plus e2
| APlus e1 e2 =>
APlus (optimize_0plus e1) (optimize_0plus e2)
| AMinus e1 e2 =>
AMinus (optimize_0plus e1) (optimize_0plus e2)
| AMult e1 e2 =>
AMult (optimize_0plus e1) (optimize_0plus e2)
end.
]]
この関数は、[aexp]の上で定義されていて、状態を扱わないことに注意します。
変数を扱えるようにした、この関数の新しいバージョンを記述しなさい。
また、[bexp]およびコマンドに対しても、同様のものを記述しなさい:
[[
optimize_0plus_aexp
optimize_0plus_bexp
optimize_0plus_com
]]
これらの関数の健全性を、[fold_constants_*]について行ったのと同様に証明しなさい。
[optimize_0plus_com]の証明においては、合同性補題を確実に使いなさい
(そうしなければ証明はとても長くなるでしょう!)。
次に、コマンドに対して次の処理を行う最適化関数を定義しなさい。行うべき処理は、
まず定数畳み込みを([fold_constants_com]を使って)行い、
次に[0 + n]項を([optimize_0plus_com]を使って)消去することです。
- この最適化関数の出力の意味のある例を示しなさい。
- この最適化関数が健全であることを示しなさい。(この部分は「とても」簡単なはずです。) *)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(* * Proving That Programs Are _Not_ Equivalent *)
(** * プログラムが同値でないことを証明する *)
(* Suppose that [c1] is a command of the form [X ::= a1; Y ::= a2]
and [c2] is the command [X ::= a1; Y ::= a2'], where [a2'] is
formed by substituting [a1] for all occurrences of [X] in [a2].
For example, [c1] and [c2] might be:
[[
c1 = (X ::= 42 + 53;
Y ::= Y + X)
c2 = (X ::= 42 + 53;
Y ::= Y + (42 + 53))
]]
Clearly, this particular [c1] and [c2] are equivalent. But is
this true in general? *)
(** [c1]が[X ::= a1; Y ::= a2]という形のコマンドで、
[c2]がコマンド[X ::= a1; Y ::= a2']であると仮定します。ただし[a2']は、
[a2]の中のすべてのXを[a1]で置換したものとします。
例えば、[c1]と[c2]は次のようなものです。
[[
c1 = (X ::= 42 + 53;
Y ::= Y + X)
c2 = (X ::= 42 + 53;
Y ::= Y + (42 + 53))
]]
明らかに、この例の場合は[c1]と[c2]は同値です。
しかし、一般にそうだと言えるでしょうか？ *)
(* We will see in a moment that it is not, but it is worthwhile
to pause, now, and see if you can find a counter-example on your
own (or remember the one from the discussion in class). *)
(** この後すぐ、そうではないことを示します。
しかし、ここでちょっと立ち止まって、
自分の力で反例を見つけることができるか試してみるのは意味があることです。
(あるいは、クラスでの議論を思い出してください。) *)
(* Here, formally, is the function that substitutes an arithmetic
expression for each occurrence of a given variable in another
expression: *)
(** 次が、式の中の指定された変数を別の算術式で置換する関数の形式的定義です。*)
Fixpoint subst_aexp (i : id) (u : aexp) (a : aexp) : aexp :=
match a with
| ANum n => ANum n
| AId i' => if beq_id i i' then u else AId i'
| APlus a1 a2 => APlus (subst_aexp i u a1) (subst_aexp i u a2)
| AMinus a1 a2 => AMinus (subst_aexp i u a1) (subst_aexp i u a2)
| AMult a1 a2 => AMult (subst_aexp i u a1) (subst_aexp i u a2)
end.
Example subst_aexp_ex :
subst_aexp X (APlus (ANum 42) (ANum 53)) (APlus (AId Y) (AId X)) =
(APlus (AId Y) (APlus (ANum 42) (ANum 53))).
Proof. reflexivity. Qed.
(* And here is the property we are interested in, expressing the
claim that commands [c1] and [c2] as described above are
always equivalent. *)
(** そして次が、興味対象の性質です。
上記コマンド[c1]と[c2]が常に同値であることを主張するものです。*)
Definition subst_equiv_property := forall i1 i2 a1 a2,
cequiv (i1 ::= a1; i2 ::= a2)
(i1 ::= a1; i2 ::= subst_aexp i1 a1 a2).
(* Sadly, the property does _not_ always hold.
_Theorem_: It is not the case that, for all [i1], [i2], [a1],
and [a2],
[[
cequiv (i1 ::= a1; i2 ::= a2)
(i1 ::= a1; i2 ::= subst_aexp i1 a1 a2).
]]
_Proof_: Suppose, for a contradiction, that for all [i1], [i2],
[a1], and [a2], we have
[[
cequiv (i1 ::= a1; i2 ::= a2)
(i1 ::= a1; i2 ::= subst_aexp i1 a1 a2).
]]
Consider the following program:
[[
X ::= APlus (AId X) (ANum 1); Y ::= AId X
]]
Note that
[[
(X ::= APlus (AId X) (ANum 1); Y ::= AId X)
/ empty_state || st1,
]]
where [st1 = { X |-> 1, Y |-> 1 }].
By our assumption, we know that
[[
cequiv (X ::= APlus (AId X) (ANum 1); Y ::= AId X)
(X ::= APlus (AId X) (ANum 1); Y ::= APlus (AId X) (ANum 1))
]]
so, by the definition of [cequiv], we have
[[
(X ::= APlus (AId X) (ANum 1); Y ::= APlus (AId X) (ANum 1))
/ empty_state || st1.
]]
But we can also derive
[[
(X ::= APlus (AId X) (ANum 1); Y ::= APlus (AId X) (ANum 1))
/ empty_state || st2,
]]
where [st2 = { X |-> 1, Y |-> 2 }]. Note that [st1 <> st2]; this
is a contradiction, since [ceval] is deterministic! [] *)
(** 残念ながら、この性質は、常には成立「しません」。
「定理」:すべての[i1], [i2], [a1], [a2]について、次が成立するわけではない:
[[
cequiv (i1 ::= a1; i2 ::= a2)
(i1 ::= a1; i2 ::= subst_aexp i1 a1 a2).
]]
「証明」:仮にすべての[i1], [i2], [a1], [a2]について
[[
cequiv (i1 ::= a1; i2 ::= a2)
(i1 ::= a1; i2 ::= subst_aexp i1 a1 a2)
]]
が成立するとする。
次のプログラムを考える:
[[
X ::= APlus (AId X) (ANum 1); Y ::= AId X
]]
次のことに注意する:
[[
(X ::= APlus (AId X) (ANum 1); Y ::= AId X)
/ empty_state || st1,
]]
ここで [st1 = { X |-> 1, Y |-> 1 }]である。
仮定より、次が言える:
[[
cequiv (X ::= APlus (AId X) (ANum 1); Y ::= AId X)
(X ::= APlus (AId X) (ANum 1); Y ::= APlus (AId X) (ANum 1))
]]
すると、[cequiv]の定義より、次が言える:
[[
(X ::= APlus (AId X) (ANum 1); Y ::= APlus (AId X) (ANum 1))
/ empty_state || st1.
]]
しかし次のことも言える:
[[
(X ::= APlus (AId X) (ANum 1); Y ::= APlus (AId X) (ANum 1))
/ empty_state || st2,
]]
ただし[st2 = { X |-> 1, Y |-> 2 }]である。
[st1 <> st2]に注意すると、これは[ceval]が決定性を持つことに矛盾する!
[] *)
Theorem subst_inequiv :
~ subst_equiv_property.
Proof.
unfold subst_equiv_property.
intros Contra.
(* Here is the counterexample: assuming that [subst_equiv_property]
holds allows us to prove that these two programs are
equivalent... *)
remember (X ::= APlus (AId X) (ANum 1);
Y ::= AId X)
as c1.
remember (X ::= APlus (AId X) (ANum 1);
Y ::= APlus (AId X) (ANum 1))
as c2.
assert (cequiv c1 c2) by (subst; apply Contra).
(* ... allows us to show that the command [c2] can terminate
in two different final states:
st1 = {X |-> 1, Y |-> 1}
st2 = {X |-> 1, Y |-> 2}. *)
remember (update (update empty_state X 1) Y 1) as st1.
remember (update (update empty_state X 1) Y 2) as st2.
assert (H1: c1 / empty_state || st1);
assert (H2: c2 / empty_state || st2);
try (subst;
apply E_Seq with (st' := (update empty_state X 1));
apply E_Ass; reflexivity).
apply H in H1.
(* Finally, we use the fact that evaluation is deterministic
to obtain a contradiction. *)
assert (Hcontra: st1 = st2)
by (apply (ceval_deterministic c2 empty_state); assumption).
assert (Hcontra': st1 Y = st2 Y)
by (rewrite Hcontra; reflexivity).
subst. inversion Hcontra'. Qed.
(* **** Exercise: 4 stars (better_subst_equiv) *)
(** **** 練習問題: ★★★★ (better_subst_equiv) *)
(* The equivalence we had in mind above was not complete nonsense --
it was actually almost right. To make it correct, we just need to
exclude the case where the variable [X] occurs in the
right-hand-side of the first assignment statement. *)
(** 上で成立すると考えていた同値は、完全に意味がないものではありません。
それは実際、ほとんど正しいのです。それを直すためには、
最初の代入の右辺に変数[X]が現れる場合を排除すれば良いのです。*)
Inductive var_not_used_in_aexp (X:id) : aexp -> Prop :=
| VNUNum: forall n, var_not_used_in_aexp X (ANum n)
| VNUId: forall Y, X <> Y -> var_not_used_in_aexp X (AId Y)
| VNUPlus: forall a1 a2,
var_not_used_in_aexp X a1 ->
var_not_used_in_aexp X a2 ->
var_not_used_in_aexp X (APlus a1 a2)
| VNUMinus: forall a1 a2,
var_not_used_in_aexp X a1 ->
var_not_used_in_aexp X a2 ->
var_not_used_in_aexp X (AMinus a1 a2)
| VNUMult: forall a1 a2,
var_not_used_in_aexp X a1 ->
var_not_used_in_aexp X a2 ->
var_not_used_in_aexp X (AMult a1 a2).
Lemma aeval_weakening : forall i st a ni,
var_not_used_in_aexp i a ->
aeval (update st i ni) a = aeval st a.
Proof.
(* FILL IN HERE *) Admitted.
(* Using [var_not_used_in_aexp], formalize and prove a correct verson
of [subst_equiv_property]. *)
(** [var_not_used_in_aexp]を使って、[subst_equiv_property]の正しいバージョンを形式化し、
証明しなさい。*)
(* FILL IN HERE *)
(** [] *)
(* **** Exercise: 3 stars, recommended (inequiv_exercise) *)
(** **** 練習問題: ★★★, recommended (inequiv_exercise) *)
Theorem inequiv_exercise:
~ cequiv (WHILE BTrue DO SKIP END) SKIP.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ####################################################### *)
(* * Doing Without Extensionality (Optional) *)
(** * 外延性を使わずに行う (Optional) *)
(* Purists might object to using the [functional_extensionality]
axiom. In general, it can be quite dangerous to add axioms,
particularly several at once (as they may be mutually
inconsistent). In fact, [functional_extensionality] and
[excluded_middle] can both be assumed without any problems, but
some Coq users prefer to avoid such "heavyweight" general
techniques, and instead craft solutions for specific problems that
stay within Coq's standard logic.
For our particular problem here, rather than extending the
definition of equality to do what we want on functions
representing states, we could instead give an explicit notion of
_equivalence_ on states. For example: *)
(** 純粋主義者は、[functional_extensionality]を使うことに不服かもしれません。
一般に、公理を追加することは非常に危険です。
特に、一度にいくつも追加するときは(追加するものが相互に矛盾することもあるため)
そうです。
実際は、[functional_extensionality]と[excluded_middle]
は両者とも何の問題もなく導入できます。
しかし、Coqユーザの中には、このような「ヘビーウェイト」の一般テクニックを避け、
Coqの標準論理の中で特定の問題のために技巧的解法を使うことを選びたい人もいるでしょう。
ここで扱っている問題に特定するなら、
状態を表現している関数についてやりたいことをやるために等しさの定義を拡張するより、
状態の同値(_equivalence_)の概念を明示的に与えることもできたかもしれません。
例えば: *)
Definition stequiv (st1 st2 : state) : Prop :=
forall (X:id), st1 X = st2 X.
Notation "st1 '~' st2" := (stequiv st1 st2) (at level 30).
(* It is easy to prove that [stequiv] is an _equivalence_ (i.e., it
is reflexive, symmetric, and transitive), so it partitions the set
of all states into equivalence classes. *)
(** [stequiv]が同値関係(_equivalence_、 つまり、反射的、対称的、推移的関係)
であることを証明することは容易です。この同値関係により、
すべての状態の集合は同値類に分割されます。*)
(* **** Exercise: 1 star, optional (stequiv_refl) *)
(** **** 練習問題: ★, optional (stequiv_refl) *)
Lemma stequiv_refl : forall (st : state),
st ~ st.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 1 star, optional (stequiv_sym) *)
(** **** 練習問題: ★, optional (stequiv_sym) *)
Lemma stequiv_sym : forall (st1 st2 : state),
st1 ~ st2 ->
st2 ~ st1.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 1 star, optional (stequiv_trans) *)
(** **** 練習問題: ★, optional (stequiv_trans) *)
Lemma stequiv_trans : forall (st1 st2 st3 : state),
st1 ~ st2 ->
st2 ~ st3 ->
st1 ~ st3.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* Another useful fact... *)
(** 別の有用な事実です... *)
(* **** Exercise: 1 star, optional (stequiv_update) *)
(** **** 練習問題: ★, optional (stequiv_update) *)
Lemma stequiv_update : forall (st1 st2 : state),
st1 ~ st2 ->
forall (X:id) (n:nat),
update st1 X n ~ update st2 X n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* It is then straightforward to show that [aeval] and [beval] behave
uniformly on all members of an equivalence class: *)
(** [aeval]と[beval]が同値類のすべての要素に対して同じように振る舞うことは、
ここからストレートに証明できます: *)
(* **** Exercise: 2 stars, optional (stequiv_aeval) *)
(** **** 練習問題: ★★, optional (stequiv_aeval) *)
Lemma stequiv_aeval : forall (st1 st2 : state),
st1 ~ st2 ->
forall (a:aexp), aeval st1 a = aeval st2 a.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 2 stars, optional (stequiv_beval) *)
(** **** 練習問題: ★★, optional (stequiv_beval) *)
Lemma stequiv_beval : forall (st1 st2 : state),
st1 ~ st2 ->
forall (b:bexp), beval st1 b = beval st2 b.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* We can also characterize the behavior of [ceval] on equivalent
states (this result is a bit more complicated to write down
because [ceval] is a relation). *)
(** 同値である状態の面から[ceval]の振る舞いを特徴づけることもできます
([ceval]は関係なので、この結果を書き下すのはもうちょっと複雑です)。 *)
Lemma stequiv_ceval: forall (st1 st2 : state),
st1 ~ st2 ->
forall (c: com) (st1': state),
(c / st1 || st1') ->
exists st2' : state,
((c / st2 || st2') /\ st1' ~ st2').
Proof.
intros st1 st2 STEQV c st1' CEV1. generalize dependent st2.
induction CEV1; intros st2 STEQV.
Case "SKIP".
exists st2. split.
constructor.
assumption.
Case ":=".
exists (update st2 l n). split.
constructor. rewrite <- H. symmetry. apply stequiv_aeval.
assumption. apply stequiv_update. assumption.
Case ";".
destruct (IHCEV1_1 st2 STEQV) as [st2' [P1 EQV1]].
destruct (IHCEV1_2 st2' EQV1) as [st2'' [P2 EQV2]].
exists st2''. split.
apply E_Seq with st2'; assumption.
assumption.
Case "IfTrue".
destruct (IHCEV1 st2 STEQV) as [st2' [P EQV]].
exists st2'. split.
apply E_IfTrue. rewrite <- H. symmetry. apply stequiv_beval.
assumption. assumption. assumption.
Case "IfFalse".
destruct (IHCEV1 st2 STEQV) as [st2' [P EQV]].
exists st2'. split.
apply E_IfFalse. rewrite <- H. symmetry. apply stequiv_beval.
assumption. assumption. assumption.
Case "WhileEnd".
exists st2. split.
apply E_WhileEnd. rewrite <- H. symmetry. apply stequiv_beval.
assumption. assumption.
Case "WhileLoop".
destruct (IHCEV1_1 st2 STEQV) as [st2' [P1 EQV1]].
destruct (IHCEV1_2 st2' EQV1) as [st2'' [P2 EQV2]].
exists st2''. split.
apply E_WhileLoop with st2'. rewrite <- H. symmetry.
apply stequiv_beval. assumption. assumption. assumption.
assumption.
Qed.
(* Now we need to redefine [cequiv] to use [~] instead of [=]. It is
not completely trivial to do this in a way that keeps the
definition simple and symmetric, but here is one approach (thanks
to Andrew McCreight). We first define a looser variant of [||]
that "folds in" the notion of equivalence. *)
(** ここで[cequiv]を[=]の代わりに[~]を使って再定義する必要があります。
定義の簡潔さと対称性を保ったまま再定義するのは、それほど自明なことではありません。
しかしその方法はあります(Andrew McCreightに感謝します)。
最初に[||]のより緩いバージョンを定義します。
これは同値概念の中に「畳み込まれ」ます。*)
Reserved Notation "c1 '/' st '||'' st'" (at level 40, st at level 39).
Inductive ceval' : com -> state -> state -> Prop :=
| E_equiv : forall c st st' st'',
c / st || st' ->
st' ~ st'' ->
c / st ||' st''
where "c1 '/' st '||'' st'" := (ceval' c1 st st').
(* Now the revised definition of [cequiv'] looks familiar: *)
(** すると[cequiv']の新しい定義は馴染みのあるものになります: *)
Definition cequiv' (c1 c2 : com) : Prop :=
forall (st st' : state),
(c1 / st ||' st') <-> (c2 / st ||' st').
(* A sanity check shows that the original notion of command
equivalence is at least as strong as this new one. (The converse
is not true, naturally.) *)
(** もとのコマンド同値の概念が、新しいものと同じ強さかそれより強いことをサニティチェックします。
(その逆は当然成立しません。) *)
Lemma cequiv__cequiv' : forall (c1 c2: com),
cequiv c1 c2 -> cequiv' c1 c2.
Proof.
unfold cequiv, cequiv'; split; intros.
inversion H0 ; subst. apply E_equiv with st'0.
apply (H st st'0); assumption. assumption.
inversion H0 ; subst. apply E_equiv with st'0.
apply (H st st'0). assumption. assumption.
Qed.
(* **** Exercise: 2 stars, optional (identity_assignment') *)
(** **** 練習問題: ★★, optional (identity_assignment') *)
(* Finally, here is our example once more... (You can complete the
proof.) *)
(** 最後にもとの例を再度扱います... (証明を完成しなさい。) *)
Example identity_assignment' :
cequiv' SKIP (X ::= AId X).
Proof.
unfold cequiv'. intros. split; intros.
Case "->".
inversion H; subst; clear H. inversion H0; subst.
apply E_equiv with (update st'0 X (st'0 X)).
constructor. reflexivity. apply stequiv_trans with st'0.
unfold stequiv. intros. apply update_same.
reflexivity. assumption.
Case "<-".
(* FILL IN HERE *) Admitted.
(** [] *)
(* On the whole, this explicit equivalence approach is considerably
harder to work with than relying on functional
extensionality. (Coq does have an advanced mechanism called
"setoids" that makes working with equivalences somewhat easier, by
allowing them to be registered with the system so that standard
rewriting tactics work for them almost as well as for equalities.)
But it is worth knowing about, because it applies even in
situations where the equivalence in question is _not_ over
functions. For example, if we chose to represent state mappings
as binary search trees, we would need to use an explicit
equivalence of this kind. *)
(** 概して、この明示的な同値のアプローチは、関数外延性を使うものよりかなり難しくなります。
(Coqは"setoids"という先進的な仕組みを持っています。
setoid は同値関係の扱いをいくらか容易にします。
その方法は、同値関係をシステムに登録すると、
それを使った書き換えタクティックが、もとの等しさ(equality)
に対してとほとんど同じようにはたらくようになるというものです。)
しかしこの、状態の同値を明示的に記述する方法は知っておく価値があります。
なぜなら、この方法は、問題となる同値が関数についてのもの「ではない」状況でも使えるからです。
例えば、状態の写像を二分探索木を使って行ったとすると、
このような明示的な同値を使う必要があるでしょう。*)
(* ####################################################### *)
(* * Additional Exercises *)
(** * さらなる練習問題 *)
(* **** Exercise: 4 stars, optional (for_while_equiv) *)
(** **** 練習問題: ★★★★, optional (for_while_equiv) *)
(* This exercise extends the optional add_for_loop exercise from
Imp.v, where you were asked to extend the language of commands
with C-style [for] loops. Prove that the command:
[[
for (c1 ; b ; c2) {
c3
}
]]
is equivalent to:
[[
c1 ;
WHILE b DO
c3 ;
c2
END
]]
*)
(** この練習問題は、Imp_J.vのoptionalの練習問題 add_for_loop を拡張したものです。
もとの add_for_loop は、コマンド言語に C-言語のスタイルの [for]ループを
拡張しなさい、というものでした。
ここでは次のことを証明しなさい:
[[
for (c1 ; b ; c2) {
c3
}
]]
は
[[
c1 ;
WHILE b DO
c3 ;
c2
END
]]
と同値である。
*)
(* FILL IN HERE *)
(** [] *)
(* **** Exercise: 3 stars, optional (swap_noninterfering_assignments) *)
(** **** 練習問題: ★★★, optional (swap_noninterfering_assignments) *)
Theorem swap_noninterfering_assignments: forall l1 l2 a1 a2,
l1 <> l2 ->
var_not_used_in_aexp l1 a2 ->
var_not_used_in_aexp l2 a1 ->
cequiv
(l1 ::= a1; l2 ::= a2)
(l2 ::= a2; l1 ::= a1).
Proof.
(* Hint: You'll need [functional_extensionality] *)
(* ヒント: [functional_extensionality]を必要とするでしょう。 *)
(* FILL IN HERE *) Admitted.
(** [] *)
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
/*verilator public_module*/
input clk;
// No verilator_public needed, because it's outside the "" in the $c statement
reg [7:0] cyc; initial cyc=0;
reg c_worked;
reg [8:0] c_wider;
wire one = 1'b1;
always @ (posedge clk) begin
cyc <= cyc+8'd1;
// coverage testing
if (one) begin end
if (!one) begin end
if (cyc[0]) begin end if (!cyc[0]) begin end // multiple on a line
if (cyc == 8'd1) begin
c_worked <= 0;
end
if (cyc == 8'd2) begin
`ifdef VERILATOR
$c("VL_PRINTF(\"Calling $c, calling $c...\\n\");");
$c("VL_PRINTF(\"Cyc=%d\\n\",",cyc,");");
c_worked <= $c("my_function()");
c_wider <= $c9("0x10");
`else
c_worked <= 1'b1;
c_wider <= 9'h10;
`endif
end
if (cyc == 8'd3) begin
if (c_worked !== 1'b1) $stop;
if (c_wider !== 9'h10) $stop;
$finish;
end
end
`ifdef verilator
`systemc_header
#define DID_INT_HEADER 1
`systemc_interface
#ifndef DID_INT_HEADER
#error "`systemc_header didn't work"
#endif
bool m_did_ctor;
vluint32_t my_function() {
if (!m_did_ctor) vl_fatal(__FILE__,__LINE__,__FILE__,"`systemc_ctor didn't work");
return 1;
}
`systemc_imp_header
#define DID_IMP_HEADER 1
`systemc_implementation
#ifndef DID_IMP_HEADER
#error "`systemc_imp_header didn't work"
#endif
`systemc_ctor
m_did_ctor = 1;
`systemc_dtor
printf("In systemc_dtor\n");
printf("*-* All Finished *-*\n");
`verilog
// Test verilator comment after a endif
`endif // verilator
endmodule
|
//
// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
//
// On Mon Feb 3 15:04:41 EST 2014
//
//
// Ports:
// Name I/O size props
// wciS0_SResp O 2 reg
// wciS0_SData O 32 reg
// wciS0_SThreadBusy O 1
// wciS0_SFlag O 2
// wciS0_Clk I 1 clock
// wciS0_MReset_n I 1 reset
// wciS0_MCmd I 3
// wciS0_MAddrSpace I 1
// wciS0_MByteEn I 4
// wciS0_MAddr I 32
// wciS0_MData I 32
// wciS0_MFlag I 2 unused
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkICAPWorker(wciS0_Clk,
wciS0_MReset_n,
wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData,
wciS0_SResp,
wciS0_SData,
wciS0_SThreadBusy,
wciS0_SFlag,
wciS0_MFlag);
parameter icapPrim = "";
parameter [0 : 0] hasDebugLogic = 1'b0;
input wciS0_Clk;
input wciS0_MReset_n;
// action method wciS0_mCmd
input [2 : 0] wciS0_MCmd;
// action method wciS0_mAddrSpace
input wciS0_MAddrSpace;
// action method wciS0_mByteEn
input [3 : 0] wciS0_MByteEn;
// action method wciS0_mAddr
input [31 : 0] wciS0_MAddr;
// action method wciS0_mData
input [31 : 0] wciS0_MData;
// value method wciS0_sResp
output [1 : 0] wciS0_SResp;
// value method wciS0_sData
output [31 : 0] wciS0_SData;
// value method wciS0_sThreadBusy
output wciS0_SThreadBusy;
// value method wciS0_sFlag
output [1 : 0] wciS0_SFlag;
// action method wciS0_mFlag
input [1 : 0] wciS0_MFlag;
// signals for module outputs
wire [31 : 0] wciS0_SData;
wire [1 : 0] wciS0_SFlag, wciS0_SResp;
wire wciS0_SThreadBusy;
// inlined wires
wire [71 : 0] wci_wslv_wciReq_wget;
wire [33 : 0] wci_wslv_respF_x_wire_wget;
wire [31 : 0] coutF_wDataIn_wget,
coutF_wDataOut_wget,
icap_icapIn_1_wget,
icap_icapOut_1_wget,
wci_wci_Es_mAddr_w_wget,
wci_wci_Es_mData_w_wget;
wire [10 : 0] coutF_rRdPtr_wdCounterCrossing_wget,
coutF_rWrPtr_wdCounterCrossing_wget;
wire [3 : 0] wci_wci_Es_mByteEn_w_wget;
wire [2 : 0] wci_wci_Es_mCmd_w_wget, wci_wslv_wEdge_wget;
wire cinF_dClear_pw_whas,
cinF_deq_happened_whas,
cinF_deq_pw_whas,
cinF_enq_pw_whas,
cinF_sClear_pw_whas,
coutF_pwDequeue_whas,
coutF_pwEnqueue_whas,
coutF_rRdPtr_pwDecrement_whas,
coutF_rRdPtr_pwIncrement_whas,
coutF_rWrPtr_pwDecrement_whas,
coutF_rWrPtr_pwIncrement_whas,
coutF_wDataIn_whas,
coutF_wDataOut_whas,
icap_cre_wget,
icap_cre_whas,
icap_cwe_wget,
icap_cwe_whas,
icap_icapBusy_1_wget,
icap_icapBusy_1_whas,
icap_icapCs_1_wget,
icap_icapCs_1_whas,
icap_icapIn_1_whas,
icap_icapOut_1_whas,
icap_icapRd_1_wget,
icap_icapRd_1_whas,
wci_wci_Es_mAddrSpace_w_wget,
wci_wci_Es_mAddrSpace_w_whas,
wci_wci_Es_mAddr_w_whas,
wci_wci_Es_mByteEn_w_whas,
wci_wci_Es_mCmd_w_whas,
wci_wci_Es_mData_w_whas,
wci_wslv_ctlAckReg_1_wget,
wci_wslv_ctlAckReg_1_whas,
wci_wslv_reqF_r_clr_whas,
wci_wslv_reqF_r_deq_whas,
wci_wslv_reqF_r_enq_whas,
wci_wslv_respF_dequeueing_whas,
wci_wslv_respF_enqueueing_whas,
wci_wslv_respF_x_wire_whas,
wci_wslv_sFlagReg_1_wget,
wci_wslv_sFlagReg_1_whas,
wci_wslv_sThreadBusy_pw_whas,
wci_wslv_wEdge_whas,
wci_wslv_wciReq_whas,
wci_wslv_wci_cfrd_pw_whas,
wci_wslv_wci_cfwr_pw_whas,
wci_wslv_wci_ctrl_pw_whas;
// register cinF_head_wrapped
reg cinF_head_wrapped;
wire cinF_head_wrapped_D_IN, cinF_head_wrapped_EN;
// register cinF_tail_wrapped
reg cinF_tail_wrapped;
wire cinF_tail_wrapped_D_IN, cinF_tail_wrapped_EN;
// register cinS
reg [31 : 0] cinS;
wire [31 : 0] cinS_D_IN;
wire cinS_EN;
// register coutF_rRdPtr_rdCounter
reg [10 : 0] coutF_rRdPtr_rdCounter;
wire [10 : 0] coutF_rRdPtr_rdCounter_D_IN;
wire coutF_rRdPtr_rdCounter_EN;
// register coutF_rRdPtr_rdCounterPre
reg [10 : 0] coutF_rRdPtr_rdCounterPre;
wire [10 : 0] coutF_rRdPtr_rdCounterPre_D_IN;
wire coutF_rRdPtr_rdCounterPre_EN;
// register coutF_rRdPtr_rsCounter
reg [10 : 0] coutF_rRdPtr_rsCounter;
wire [10 : 0] coutF_rRdPtr_rsCounter_D_IN;
wire coutF_rRdPtr_rsCounter_EN;
// register coutF_rWrPtr_rdCounter
reg [10 : 0] coutF_rWrPtr_rdCounter;
wire [10 : 0] coutF_rWrPtr_rdCounter_D_IN;
wire coutF_rWrPtr_rdCounter_EN;
// register coutF_rWrPtr_rdCounterPre
reg [10 : 0] coutF_rWrPtr_rdCounterPre;
wire [10 : 0] coutF_rWrPtr_rdCounterPre_D_IN;
wire coutF_rWrPtr_rdCounterPre_EN;
// register coutF_rWrPtr_rsCounter
reg [10 : 0] coutF_rWrPtr_rsCounter;
wire [10 : 0] coutF_rWrPtr_rsCounter_D_IN;
wire coutF_rWrPtr_rsCounter_EN;
// register dwRead
reg [31 : 0] dwRead;
wire [31 : 0] dwRead_D_IN;
wire dwRead_EN;
// register dwWritten
reg [31 : 0] dwWritten;
wire [31 : 0] dwWritten_D_IN;
wire dwWritten_EN;
// register icapCtrl
reg [31 : 0] icapCtrl;
wire [31 : 0] icapCtrl_D_IN;
wire icapCtrl_EN;
// register icap_icapBusy
reg icap_icapBusy;
wire icap_icapBusy_D_IN, icap_icapBusy_EN;
// register icap_icapCs
reg icap_icapCs;
wire icap_icapCs_D_IN, icap_icapCs_EN;
// register icap_icapIn
reg [31 : 0] icap_icapIn;
wire [31 : 0] icap_icapIn_D_IN;
wire icap_icapIn_EN;
// register icap_icapOut
reg [31 : 0] icap_icapOut;
wire [31 : 0] icap_icapOut_D_IN;
wire icap_icapOut_EN;
// register icap_icapRd
reg icap_icapRd;
wire icap_icapRd_D_IN, icap_icapRd_EN;
// register icap_inCount
reg [31 : 0] icap_inCount;
wire [31 : 0] icap_inCount_D_IN;
wire icap_inCount_EN;
// register icap_outCount
reg [31 : 0] icap_outCount;
wire [31 : 0] icap_outCount_D_IN;
wire icap_outCount_EN;
// register wci_wslv_cEdge
reg [2 : 0] wci_wslv_cEdge;
wire [2 : 0] wci_wslv_cEdge_D_IN;
wire wci_wslv_cEdge_EN;
// register wci_wslv_cState
reg [2 : 0] wci_wslv_cState;
wire [2 : 0] wci_wslv_cState_D_IN;
wire wci_wslv_cState_EN;
// register wci_wslv_ctlAckReg
reg wci_wslv_ctlAckReg;
wire wci_wslv_ctlAckReg_D_IN, wci_wslv_ctlAckReg_EN;
// register wci_wslv_ctlOpActive
reg wci_wslv_ctlOpActive;
wire wci_wslv_ctlOpActive_D_IN, wci_wslv_ctlOpActive_EN;
// register wci_wslv_illegalEdge
reg wci_wslv_illegalEdge;
wire wci_wslv_illegalEdge_D_IN, wci_wslv_illegalEdge_EN;
// register wci_wslv_isReset_isInReset
reg wci_wslv_isReset_isInReset;
wire wci_wslv_isReset_isInReset_D_IN, wci_wslv_isReset_isInReset_EN;
// register wci_wslv_nState
reg [2 : 0] wci_wslv_nState;
reg [2 : 0] wci_wslv_nState_D_IN;
wire wci_wslv_nState_EN;
// register wci_wslv_reqF_countReg
reg [1 : 0] wci_wslv_reqF_countReg;
wire [1 : 0] wci_wslv_reqF_countReg_D_IN;
wire wci_wslv_reqF_countReg_EN;
// register wci_wslv_respF_cntr_r
reg [1 : 0] wci_wslv_respF_cntr_r;
wire [1 : 0] wci_wslv_respF_cntr_r_D_IN;
wire wci_wslv_respF_cntr_r_EN;
// register wci_wslv_respF_q_0
reg [33 : 0] wci_wslv_respF_q_0;
reg [33 : 0] wci_wslv_respF_q_0_D_IN;
wire wci_wslv_respF_q_0_EN;
// register wci_wslv_respF_q_1
reg [33 : 0] wci_wslv_respF_q_1;
reg [33 : 0] wci_wslv_respF_q_1_D_IN;
wire wci_wslv_respF_q_1_EN;
// register wci_wslv_sFlagReg
reg wci_wslv_sFlagReg;
wire wci_wslv_sFlagReg_D_IN, wci_wslv_sFlagReg_EN;
// register wci_wslv_sThreadBusy_d
reg wci_wslv_sThreadBusy_d;
wire wci_wslv_sThreadBusy_d_D_IN, wci_wslv_sThreadBusy_d_EN;
// ports of submodule cd
wire cd_CLK_OUT, cd_PREEDGE;
// ports of submodule cinF_dCombinedReset
wire cinF_dCombinedReset_RST_OUT;
// ports of submodule cinF_dCrossedsReset
wire cinF_dCrossedsReset_OUT_RST;
// ports of submodule cinF_dInReset
wire cinF_dInReset_VAL;
// ports of submodule cinF_sCombinedReset
wire cinF_sCombinedReset_RST_OUT;
// ports of submodule cinF_sCrosseddReset
wire cinF_sCrosseddReset_OUT_RST;
// ports of submodule cinF_sInReset
wire cinF_sInReset_VAL;
// ports of submodule coutF_memory
wire [31 : 0] coutF_memory_DIA, coutF_memory_DIB, coutF_memory_DOB;
wire [9 : 0] coutF_memory_ADDRA, coutF_memory_ADDRB;
wire coutF_memory_ENA, coutF_memory_ENB, coutF_memory_WEA, coutF_memory_WEB;
// ports of submodule cre
wire cre_dD_OUT, cre_sD_IN, cre_sEN, cre_sRDY;
// ports of submodule cwe
wire cwe_dD_OUT, cwe_sD_IN, cwe_sEN, cwe_sRDY;
// ports of submodule icap_cinF
wire [31 : 0] icap_cinF_D_IN, icap_cinF_D_OUT;
wire icap_cinF_CLR,
icap_cinF_DEQ,
icap_cinF_EMPTY_N,
icap_cinF_ENQ,
icap_cinF_FULL_N;
// ports of submodule icap_coutF
wire [31 : 0] icap_coutF_D_IN, icap_coutF_D_OUT;
wire icap_coutF_CLR,
icap_coutF_DEQ,
icap_coutF_EMPTY_N,
icap_coutF_ENQ,
icap_coutF_FULL_N;
// ports of submodule icap_icap
wire [31 : 0] icap_icap_I, icap_icap_O;
wire icap_icap_BUSY, icap_icap_CSB, icap_icap_RDWRB;
// ports of submodule inCnt
wire [31 : 0] inCnt_dD_OUT, inCnt_sD_IN;
wire inCnt_sEN, inCnt_sRDY;
// ports of submodule outCnt
wire [31 : 0] outCnt_dD_OUT, outCnt_sD_IN;
wire outCnt_sEN, outCnt_sRDY;
// ports of submodule slowReset
wire slowReset_OUT_RST;
// ports of submodule wci_wslv_reqF
wire [71 : 0] wci_wslv_reqF_D_IN, wci_wslv_reqF_D_OUT;
wire wci_wslv_reqF_CLR,
wci_wslv_reqF_DEQ,
wci_wslv_reqF_EMPTY_N,
wci_wslv_reqF_ENQ;
// rule scheduling signals
wire CAN_FIRE_RL_wci_cfrd,
WILL_FIRE_RL_cinF_deq_update_head,
WILL_FIRE_RL_cinF_enq_update_tail,
WILL_FIRE_RL_icap_read_configuration_data,
WILL_FIRE_RL_icap_write_configration_data,
WILL_FIRE_RL_wci_cfrd,
WILL_FIRE_RL_wci_cfwr,
WILL_FIRE_RL_wci_ctrl_EiI,
WILL_FIRE_RL_wci_ctrl_IsO,
WILL_FIRE_RL_wci_ctrl_OrE,
WILL_FIRE_RL_wci_wslv_ctl_op_complete,
WILL_FIRE_RL_wci_wslv_ctl_op_start,
WILL_FIRE_RL_wci_wslv_respF_both,
WILL_FIRE_RL_wci_wslv_respF_decCtr,
WILL_FIRE_RL_wci_wslv_respF_incCtr;
// inputs to muxes for submodule ports
reg [33 : 0] MUX_wci_wslv_respF_q_0_write_1__VAL_2;
wire [33 : 0] MUX_wci_wslv_respF_q_0_write_1__VAL_1,
MUX_wci_wslv_respF_q_1_write_1__VAL_1,
MUX_wci_wslv_respF_x_wire_wset_1__VAL_1,
MUX_wci_wslv_respF_x_wire_wset_1__VAL_2;
wire [10 : 0] MUX_coutF_rRdPtr_rsCounter_write_1__VAL_1,
MUX_coutF_rWrPtr_rsCounter_write_1__VAL_1;
wire [1 : 0] MUX_wci_wslv_respF_cntr_r_write_1__VAL_2;
wire MUX_wci_wslv_illegalEdge_write_1__SEL_1,
MUX_wci_wslv_illegalEdge_write_1__VAL_1,
MUX_wci_wslv_respF_q_0_write_1__SEL_1,
MUX_wci_wslv_respF_q_0_write_1__SEL_2,
MUX_wci_wslv_respF_q_1_write_1__SEL_1,
MUX_wci_wslv_respF_q_1_write_1__SEL_2;
// remaining internal signals
reg [63 : 0] v__h26628, v__h3563, v__h3738, v__h3882;
reg [31 : 0] v__h26380;
wire [31 : 0] IF_coutF_rRdPtr_rsCounter_91_BIT_0_98_OR_coutF_ETC___d439,
IF_coutF_rRdPtr_rsCounter_91_BIT_0_98_XOR_cout_ETC___d440,
IF_coutF_rWrPtr_rsCounter_22_BIT_0_29_OR_coutF_ETC___d370,
IF_coutF_rWrPtr_rsCounter_22_BIT_0_29_XOR_cout_ETC___d371,
icapStatus__h26003,
rdat__h26404,
rdat__h26410,
rdat__h26416,
rdat__h26422,
x3__h20684;
wire [10 : 0] coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549,
x__h16273,
x__h18575,
x__h21947,
x_dReadBin__h20388,
x_sReadBin__h20385,
y__h17160,
y__h19462;
wire [9 : 0] x2__h21916;
wire [2 : 0] x__h26497;
wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27;
wire NOT_coutF_rRdPtr_rsCounter_91_EQ_coutF_rWrPtr__ETC___d599,
NOT_wci_wslv_respF_cntr_r_8_EQ_2_1_2_AND_wci_w_ETC___d590,
_dfoo1,
_dfoo3,
coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d525,
coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d527,
coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d530,
coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d532,
coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d535,
coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d537,
coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d540,
coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d542,
coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d545,
coutF_rRdPtr_rsCounter_91_BIT_0_98_XOR_coutF_r_ETC___d418,
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d481,
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d482,
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d484,
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d485,
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d487,
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d488,
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d490,
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d491,
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d493,
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d494,
coutF_rWrPtr_rsCounter_22_BIT_0_29_XOR_coutF_r_ETC___d349,
coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d461,
coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d462,
coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d464,
coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d465,
coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d467,
coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d468,
coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d470,
coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d471,
coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d473,
z__h17204,
z__h17211,
z__h17218,
z__h17225,
z__h17232,
z__h17239,
z__h17246,
z__h17253,
z__h17260,
z__h19506,
z__h19513,
z__h19520,
z__h19527,
z__h19534,
z__h19541,
z__h19548,
z__h19555,
z__h19562;
// value method wciS0_sResp
assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ;
// value method wciS0_sData
assign wciS0_SData = wci_wslv_respF_q_0[31:0] ;
// value method wciS0_sThreadBusy
assign wciS0_SThreadBusy =
wci_wslv_reqF_countReg > 2'd1 || wci_wslv_isReset_isInReset ;
// value method wciS0_sFlag
assign wciS0_SFlag = { 1'd1, wci_wslv_sFlagReg } ;
// submodule cd
ClockDiv #(.width(32'd1),
.lower(32'd0),
.upper(32'd1),
.offset(32'd0)) cd(.CLK_IN(wciS0_Clk),
.RST(wciS0_MReset_n),
.PREEDGE(cd_PREEDGE),
.CLK_OUT(cd_CLK_OUT));
// submodule cinF_dCombinedReset
ResetEither cinF_dCombinedReset(.A_RST(slowReset_OUT_RST),
.B_RST(cinF_dCrossedsReset_OUT_RST),
.RST_OUT(cinF_dCombinedReset_RST_OUT));
// submodule cinF_dCrossedsReset
SyncReset0 cinF_dCrossedsReset(.IN_RST(wciS0_MReset_n),
.OUT_RST(cinF_dCrossedsReset_OUT_RST));
// submodule cinF_dInReset
ResetToBool cinF_dInReset(.RST(cinF_dCombinedReset_RST_OUT),
.VAL(cinF_dInReset_VAL));
// submodule cinF_sCombinedReset
ResetEither cinF_sCombinedReset(.A_RST(wciS0_MReset_n),
.B_RST(cinF_sCrosseddReset_OUT_RST),
.RST_OUT(cinF_sCombinedReset_RST_OUT));
// submodule cinF_sCrosseddReset
SyncReset0 cinF_sCrosseddReset(.IN_RST(slowReset_OUT_RST),
.OUT_RST(cinF_sCrosseddReset_OUT_RST));
// submodule cinF_sInReset
ResetToBool cinF_sInReset(.RST(cinF_sCombinedReset_RST_OUT),
.VAL(cinF_sInReset_VAL));
// submodule coutF_memory
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd10),
.DATA_WIDTH(32'd32),
.MEMSIZE(11'd1024)) coutF_memory(.CLKA(cd_CLK_OUT),
.CLKB(wciS0_Clk),
.ADDRA(coutF_memory_ADDRA),
.ADDRB(coutF_memory_ADDRB),
.DIA(coutF_memory_DIA),
.DIB(coutF_memory_DIB),
.WEA(coutF_memory_WEA),
.WEB(coutF_memory_WEB),
.ENA(coutF_memory_ENA),
.ENB(coutF_memory_ENB),
.DOA(),
.DOB(coutF_memory_DOB));
// submodule cre
SyncRegister #(.width(32'd1), .init(1'd0)) cre(.sCLK(wciS0_Clk),
.dCLK(cd_CLK_OUT),
.sRST(wciS0_MReset_n),
.sD_IN(cre_sD_IN),
.sEN(cre_sEN),
.dD_OUT(cre_dD_OUT),
.sRDY(cre_sRDY));
// submodule cwe
SyncRegister #(.width(32'd1), .init(1'd0)) cwe(.sCLK(wciS0_Clk),
.dCLK(cd_CLK_OUT),
.sRST(wciS0_MReset_n),
.sD_IN(cwe_sD_IN),
.sEN(cwe_sEN),
.dD_OUT(cwe_dD_OUT),
.sRDY(cwe_sRDY));
// submodule icap_cinF
FIFO2 #(.width(32'd32), .guarded(32'd1)) icap_cinF(.RST(slowReset_OUT_RST),
.CLK(cd_CLK_OUT),
.D_IN(icap_cinF_D_IN),
.ENQ(icap_cinF_ENQ),
.DEQ(icap_cinF_DEQ),
.CLR(icap_cinF_CLR),
.D_OUT(icap_cinF_D_OUT),
.FULL_N(icap_cinF_FULL_N),
.EMPTY_N(icap_cinF_EMPTY_N));
// submodule icap_coutF
FIFO2 #(.width(32'd32), .guarded(32'd1)) icap_coutF(.RST(slowReset_OUT_RST),
.CLK(cd_CLK_OUT),
.D_IN(icap_coutF_D_IN),
.ENQ(icap_coutF_ENQ),
.DEQ(icap_coutF_DEQ),
.CLR(icap_coutF_CLR),
.D_OUT(icap_coutF_D_OUT),
.FULL_N(icap_coutF_FULL_N),
.EMPTY_N(icap_coutF_EMPTY_N));
// submodule icap_icap
ICAP_VIRTEX6 #(.ICAP_WIDTH("X32")) icap_icap(.CLK(cd_CLK_OUT),
.CSB(icap_icap_CSB),
.I(icap_icap_I),
.RDWRB(icap_icap_RDWRB),
.O(icap_icap_O),
.BUSY(icap_icap_BUSY));
// submodule inCnt
SyncRegister #(.width(32'd32), .init(32'd0)) inCnt(.sCLK(cd_CLK_OUT),
.dCLK(wciS0_Clk),
.sRST(slowReset_OUT_RST),
.sD_IN(inCnt_sD_IN),
.sEN(inCnt_sEN),
.dD_OUT(inCnt_dD_OUT),
.sRDY(inCnt_sRDY));
// submodule outCnt
SyncRegister #(.width(32'd32), .init(32'd0)) outCnt(.sCLK(cd_CLK_OUT),
.dCLK(wciS0_Clk),
.sRST(slowReset_OUT_RST),
.sD_IN(outCnt_sD_IN),
.sEN(outCnt_sEN),
.dD_OUT(outCnt_dD_OUT),
.sRDY(outCnt_sRDY));
// submodule slowReset
SyncResetA #(.RSTDELAY(32'd1)) slowReset(.CLK(cd_CLK_OUT),
.IN_RST(wciS0_MReset_n),
.OUT_RST(slowReset_OUT_RST));
// submodule wci_wslv_reqF
SizedFIFO #(.p1width(32'd72),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wci_wslv_reqF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wci_wslv_reqF_D_IN),
.ENQ(wci_wslv_reqF_ENQ),
.DEQ(wci_wslv_reqF_DEQ),
.CLR(wci_wslv_reqF_CLR),
.D_OUT(wci_wslv_reqF_D_OUT),
.FULL_N(),
.EMPTY_N(wci_wslv_reqF_EMPTY_N));
// rule RL_wci_cfwr
assign WILL_FIRE_RL_wci_cfwr =
NOT_wci_wslv_respF_cntr_r_8_EQ_2_1_2_AND_wci_w_ETC___d590 &&
wci_wslv_wci_cfwr_pw_whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_wslv_ctl_op_start
assign WILL_FIRE_RL_wci_wslv_ctl_op_start =
wci_wslv_reqF_EMPTY_N && wci_wslv_wci_ctrl_pw_whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_ctrl_IsO
assign WILL_FIRE_RL_wci_ctrl_IsO =
wci_wslv_wci_ctrl_pw_whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd1 &&
wci_wslv_reqF_D_OUT[36:34] == 3'd1 ;
// rule RL_wci_ctrl_EiI
assign WILL_FIRE_RL_wci_ctrl_EiI =
wci_wslv_wci_ctrl_pw_whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd0 &&
wci_wslv_reqF_D_OUT[36:34] == 3'd0 ;
// rule RL_wci_ctrl_OrE
assign WILL_FIRE_RL_wci_ctrl_OrE =
wci_wslv_wci_ctrl_pw_whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd2 &&
wci_wslv_reqF_D_OUT[36:34] == 3'd3 ;
// rule RL_wci_wslv_ctl_op_complete
assign WILL_FIRE_RL_wci_wslv_ctl_op_complete =
wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_ctlOpActive &&
wci_wslv_ctlAckReg ;
// rule RL_icap_write_configration_data
assign WILL_FIRE_RL_icap_write_configration_data =
icap_cinF_EMPTY_N && cwe_dD_OUT && !cre_dD_OUT ;
// rule RL_icap_read_configuration_data
assign WILL_FIRE_RL_icap_read_configuration_data =
(icap_icapBusy || icap_coutF_FULL_N) && cre_dD_OUT &&
!cwe_dD_OUT ;
// rule RL_cinF_enq_update_tail
assign WILL_FIRE_RL_cinF_enq_update_tail =
!cinF_sInReset_VAL && cinF_enq_pw_whas ;
// rule RL_cinF_deq_update_head
assign WILL_FIRE_RL_cinF_deq_update_head =
!cinF_dInReset_VAL && cinF_deq_pw_whas ;
// rule RL_wci_cfrd
assign CAN_FIRE_RL_wci_cfrd =
wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF_EMPTY_N &&
(wci_wslv_reqF_D_OUT[63:32] != 32'h0000000C ||
NOT_coutF_rRdPtr_rsCounter_91_EQ_coutF_rWrPtr__ETC___d599) &&
wci_wslv_wci_cfrd_pw_whas ;
assign WILL_FIRE_RL_wci_cfrd =
CAN_FIRE_RL_wci_cfrd && !WILL_FIRE_RL_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_wslv_respF_incCtr
assign WILL_FIRE_RL_wci_wslv_respF_incCtr =
wci_wslv_respF_x_wire_whas && wci_wslv_respF_enqueueing_whas &&
!(wci_wslv_respF_cntr_r != 2'd0) ;
// rule RL_wci_wslv_respF_decCtr
assign WILL_FIRE_RL_wci_wslv_respF_decCtr =
wci_wslv_respF_cntr_r != 2'd0 &&
!wci_wslv_respF_enqueueing_whas ;
// rule RL_wci_wslv_respF_both
assign WILL_FIRE_RL_wci_wslv_respF_both =
wci_wslv_respF_x_wire_whas && wci_wslv_respF_cntr_r != 2'd0 &&
wci_wslv_respF_enqueueing_whas ;
// inputs to muxes for submodule ports
assign MUX_wci_wslv_illegalEdge_write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF_D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 &&
wci_wslv_cState != 3'd3 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd2 && wci_wslv_cState != 3'd2 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd3 && wci_wslv_cState != 3'd3 &&
wci_wslv_cState != 3'd2 &&
wci_wslv_cState != 3'd1 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd4 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd5 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd6 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd7) ;
assign MUX_wci_wslv_respF_q_0_write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ;
assign MUX_wci_wslv_respF_q_0_write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_cntr_r == 2'd0 ;
assign MUX_wci_wslv_respF_q_1_write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ;
assign MUX_wci_wslv_respF_q_1_write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_cntr_r == 2'd1 ;
assign MUX_coutF_rRdPtr_rsCounter_write_1__VAL_1 =
(~coutF_rRdPtr_rsCounter[IF_coutF_rRdPtr_rsCounter_91_BIT_0_98_XOR_cout_ETC___d440[3:0]]) ?
coutF_rRdPtr_rsCounter | x__h18575 :
coutF_rRdPtr_rsCounter & y__h19462 ;
assign MUX_coutF_rWrPtr_rsCounter_write_1__VAL_1 =
(~coutF_rWrPtr_rsCounter[IF_coutF_rWrPtr_rsCounter_22_BIT_0_29_XOR_cout_ETC___d371[3:0]]) ?
coutF_rWrPtr_rsCounter | x__h16273 :
coutF_rWrPtr_rsCounter & y__h17160 ;
assign MUX_wci_wslv_illegalEdge_write_1__VAL_1 =
wci_wslv_reqF_D_OUT[36:34] != 3'd4 &&
wci_wslv_reqF_D_OUT[36:34] != 3'd5 &&
wci_wslv_reqF_D_OUT[36:34] != 3'd6 ;
assign MUX_wci_wslv_respF_cntr_r_write_1__VAL_2 =
wci_wslv_respF_cntr_r + 2'd1 ;
assign MUX_wci_wslv_respF_q_0_write_1__VAL_1 =
(wci_wslv_respF_cntr_r == 2'd1) ?
MUX_wci_wslv_respF_q_0_write_1__VAL_2 :
wci_wslv_respF_q_1 ;
always@(WILL_FIRE_RL_wci_wslv_ctl_op_complete or
MUX_wci_wslv_respF_x_wire_wset_1__VAL_1 or
WILL_FIRE_RL_wci_cfrd or
MUX_wci_wslv_respF_x_wire_wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_wslv_ctl_op_complete:
MUX_wci_wslv_respF_q_0_write_1__VAL_2 =
MUX_wci_wslv_respF_x_wire_wset_1__VAL_1;
WILL_FIRE_RL_wci_cfrd:
MUX_wci_wslv_respF_q_0_write_1__VAL_2 =
MUX_wci_wslv_respF_x_wire_wset_1__VAL_2;
WILL_FIRE_RL_wci_cfwr:
MUX_wci_wslv_respF_q_0_write_1__VAL_2 = 34'h1C0DE4201;
default: MUX_wci_wslv_respF_q_0_write_1__VAL_2 =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign MUX_wci_wslv_respF_q_1_write_1__VAL_1 =
(wci_wslv_respF_cntr_r == 2'd2) ?
MUX_wci_wslv_respF_q_0_write_1__VAL_2 :
34'h0AAAAAAAA ;
assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_1 =
wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ;
assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_2 = { 2'd1, v__h26380 } ;
// inlined wires
assign wci_wslv_wciReq_wget =
{ wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData } ;
assign wci_wslv_wciReq_whas = 1'd1 ;
assign wci_wslv_respF_x_wire_wget = MUX_wci_wslv_respF_q_0_write_1__VAL_2 ;
assign wci_wslv_respF_x_wire_whas =
WILL_FIRE_RL_wci_wslv_ctl_op_complete || WILL_FIRE_RL_wci_cfrd ||
WILL_FIRE_RL_wci_cfwr ;
assign wci_wslv_wEdge_wget = wci_wslv_reqF_D_OUT[36:34] ;
assign wci_wslv_wEdge_whas = WILL_FIRE_RL_wci_wslv_ctl_op_start ;
assign wci_wslv_sFlagReg_1_wget = 1'b0 ;
assign wci_wslv_sFlagReg_1_whas = 1'b0 ;
assign wci_wslv_ctlAckReg_1_wget = 1'd1 ;
assign wci_wslv_ctlAckReg_1_whas =
WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO ||
WILL_FIRE_RL_wci_ctrl_EiI ;
assign wci_wci_Es_mCmd_w_wget = wciS0_MCmd ;
assign wci_wci_Es_mCmd_w_whas = 1'd1 ;
assign wci_wci_Es_mAddrSpace_w_wget = wciS0_MAddrSpace ;
assign wci_wci_Es_mAddrSpace_w_whas = 1'd1 ;
assign wci_wci_Es_mByteEn_w_wget = wciS0_MByteEn ;
assign wci_wci_Es_mByteEn_w_whas = 1'd1 ;
assign wci_wci_Es_mAddr_w_wget = wciS0_MAddr ;
assign wci_wci_Es_mAddr_w_whas = 1'd1 ;
assign wci_wci_Es_mData_w_wget = wciS0_MData ;
assign wci_wci_Es_mData_w_whas = 1'd1 ;
assign icap_icapCs_1_wget = 1'd1 ;
assign icap_icapCs_1_whas =
WILL_FIRE_RL_icap_read_configuration_data ||
WILL_FIRE_RL_icap_write_configration_data ;
assign icap_icapRd_1_wget = !WILL_FIRE_RL_icap_write_configration_data ;
assign icap_icapRd_1_whas =
WILL_FIRE_RL_icap_write_configration_data ||
WILL_FIRE_RL_icap_read_configuration_data ;
assign icap_icapIn_1_wget =
{ icap_cinF_D_OUT[24],
icap_cinF_D_OUT[25],
icap_cinF_D_OUT[26],
icap_cinF_D_OUT[27],
icap_cinF_D_OUT[28],
icap_cinF_D_OUT[29],
icap_cinF_D_OUT[30],
icap_cinF_D_OUT[31],
icap_cinF_D_OUT[16],
icap_cinF_D_OUT[17],
icap_cinF_D_OUT[18],
icap_cinF_D_OUT[19],
icap_cinF_D_OUT[20],
icap_cinF_D_OUT[21],
icap_cinF_D_OUT[22],
icap_cinF_D_OUT[23],
icap_cinF_D_OUT[8],
icap_cinF_D_OUT[9],
icap_cinF_D_OUT[10],
icap_cinF_D_OUT[11],
icap_cinF_D_OUT[12],
icap_cinF_D_OUT[13],
icap_cinF_D_OUT[14],
icap_cinF_D_OUT[15],
icap_cinF_D_OUT[0],
icap_cinF_D_OUT[1],
icap_cinF_D_OUT[2],
icap_cinF_D_OUT[3],
icap_cinF_D_OUT[4],
icap_cinF_D_OUT[5],
icap_cinF_D_OUT[6],
icap_cinF_D_OUT[7] } ;
assign icap_icapIn_1_whas = WILL_FIRE_RL_icap_write_configration_data ;
assign icap_icapOut_1_wget = icap_icap_O ;
assign icap_icapOut_1_whas = 1'd1 ;
assign icap_icapBusy_1_wget = icap_icap_BUSY ;
assign icap_icapBusy_1_whas = 1'd1 ;
assign icap_cwe_wget = cwe_dD_OUT ;
assign icap_cwe_whas = 1'd1 ;
assign icap_cre_wget = cre_dD_OUT ;
assign icap_cre_whas = 1'd1 ;
assign coutF_wDataIn_wget = icap_coutF_D_OUT ;
assign coutF_wDataIn_whas = coutF_pwEnqueue_whas ;
assign coutF_wDataOut_wget = coutF_memory_DOB ;
assign coutF_wDataOut_whas = 1'd1 ;
assign wci_wslv_reqF_r_enq_whas = wci_wslv_wciReq_wget[71:69] != 3'd0 ;
assign wci_wslv_reqF_r_deq_whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_wslv_ctl_op_start ;
assign wci_wslv_reqF_r_clr_whas = 1'b0 ;
assign wci_wslv_respF_enqueueing_whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
assign wci_wslv_respF_dequeueing_whas = wci_wslv_respF_cntr_r != 2'd0 ;
assign wci_wslv_sThreadBusy_pw_whas = 1'b0 ;
assign wci_wslv_wci_cfwr_pw_whas =
wci_wslv_reqF_EMPTY_N && wci_wslv_reqF_D_OUT[68] &&
wci_wslv_reqF_D_OUT[71:69] == 3'd1 ;
assign wci_wslv_wci_cfrd_pw_whas =
wci_wslv_reqF_EMPTY_N && wci_wslv_reqF_D_OUT[68] &&
wci_wslv_reqF_D_OUT[71:69] == 3'd2 ;
assign wci_wslv_wci_ctrl_pw_whas =
wci_wslv_reqF_EMPTY_N && !wci_wslv_reqF_D_OUT[68] &&
wci_wslv_reqF_D_OUT[71:69] == 3'd2 ;
assign cinF_enq_pw_whas =
WILL_FIRE_RL_wci_cfwr &&
wci_wslv_reqF_D_OUT[63:32] == 32'h00000008 ;
assign cinF_deq_pw_whas =
cinF_head_wrapped != cinF_tail_wrapped && !cinF_dInReset_VAL &&
icap_cinF_FULL_N ;
assign cinF_sClear_pw_whas = 1'b0 ;
assign cinF_dClear_pw_whas = 1'b0 ;
assign cinF_deq_happened_whas = 1'b0 ;
assign coutF_rWrPtr_pwIncrement_whas = coutF_pwEnqueue_whas ;
assign coutF_rWrPtr_pwDecrement_whas = 1'b0 ;
assign coutF_rRdPtr_pwIncrement_whas = coutF_pwDequeue_whas ;
assign coutF_rRdPtr_pwDecrement_whas = 1'b0 ;
assign coutF_pwDequeue_whas =
WILL_FIRE_RL_wci_cfrd &&
wci_wslv_reqF_D_OUT[63:32] == 32'h0000000C ;
assign coutF_pwEnqueue_whas =
coutF_rWrPtr_rsCounter !=
{ coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[10],
coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[10] ^
coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[9],
coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[9] ^
coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[8],
coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[8] ^
coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[7],
coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[7] ^
coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[6],
coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[6] ^
coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[5],
coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[5] ^
coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[4],
coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[4] ^
coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[3],
coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[3] ^
coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[2],
coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[2] ^
coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[1],
coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[1] ^
coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[0] } &&
icap_coutF_EMPTY_N ;
assign coutF_rWrPtr_wdCounterCrossing_wget = coutF_rWrPtr_rsCounter ;
assign coutF_rRdPtr_wdCounterCrossing_wget = coutF_rRdPtr_rsCounter ;
// register cinF_head_wrapped
assign cinF_head_wrapped_D_IN =
WILL_FIRE_RL_cinF_deq_update_head && !cinF_head_wrapped ;
assign cinF_head_wrapped_EN =
WILL_FIRE_RL_cinF_deq_update_head || cinF_dInReset_VAL ;
// register cinF_tail_wrapped
assign cinF_tail_wrapped_D_IN =
WILL_FIRE_RL_cinF_enq_update_tail && !cinF_tail_wrapped ;
assign cinF_tail_wrapped_EN =
WILL_FIRE_RL_cinF_enq_update_tail || cinF_sInReset_VAL ;
// register cinS
assign cinS_D_IN = wci_wslv_reqF_D_OUT[31:0] ;
assign cinS_EN = cinF_enq_pw_whas ;
// register coutF_rRdPtr_rdCounter
assign coutF_rRdPtr_rdCounter_D_IN = coutF_rRdPtr_rdCounterPre ;
assign coutF_rRdPtr_rdCounter_EN = 1'd1 ;
// register coutF_rRdPtr_rdCounterPre
assign coutF_rRdPtr_rdCounterPre_D_IN = coutF_rRdPtr_rsCounter ;
assign coutF_rRdPtr_rdCounterPre_EN = 1'd1 ;
// register coutF_rRdPtr_rsCounter
assign coutF_rRdPtr_rsCounter_D_IN =
MUX_coutF_rRdPtr_rsCounter_write_1__VAL_1 ;
assign coutF_rRdPtr_rsCounter_EN = coutF_pwDequeue_whas ;
// register coutF_rWrPtr_rdCounter
assign coutF_rWrPtr_rdCounter_D_IN = coutF_rWrPtr_rdCounterPre ;
assign coutF_rWrPtr_rdCounter_EN = 1'd1 ;
// register coutF_rWrPtr_rdCounterPre
assign coutF_rWrPtr_rdCounterPre_D_IN = coutF_rWrPtr_rsCounter ;
assign coutF_rWrPtr_rdCounterPre_EN = 1'd1 ;
// register coutF_rWrPtr_rsCounter
assign coutF_rWrPtr_rsCounter_D_IN =
MUX_coutF_rWrPtr_rsCounter_write_1__VAL_1 ;
assign coutF_rWrPtr_rsCounter_EN = coutF_pwEnqueue_whas ;
// register dwRead
assign dwRead_D_IN = 32'h0 ;
assign dwRead_EN = 1'b0 ;
// register dwWritten
assign dwWritten_D_IN = 32'h0 ;
assign dwWritten_EN = 1'b0 ;
// register icapCtrl
assign icapCtrl_D_IN = wci_wslv_reqF_D_OUT[31:0] ;
assign icapCtrl_EN =
WILL_FIRE_RL_wci_cfwr &&
wci_wslv_reqF_D_OUT[63:32] == 32'h00000004 ;
// register icap_icapBusy
assign icap_icapBusy_D_IN = icap_icap_BUSY ;
assign icap_icapBusy_EN = 1'd1 ;
// register icap_icapCs
assign icap_icapCs_D_IN = icap_icapCs_1_whas ;
assign icap_icapCs_EN = 1'd1 ;
// register icap_icapIn
assign icap_icapIn_D_IN =
WILL_FIRE_RL_icap_write_configration_data ?
icap_icapIn_1_wget :
32'hFFFFFFFF ;
assign icap_icapIn_EN = 1'd1 ;
// register icap_icapOut
assign icap_icapOut_D_IN = icap_icap_O ;
assign icap_icapOut_EN = 1'd1 ;
// register icap_icapRd
assign icap_icapRd_D_IN =
icap_icapRd_1_whas &&
!WILL_FIRE_RL_icap_write_configration_data ;
assign icap_icapRd_EN = 1'd1 ;
// register icap_inCount
assign icap_inCount_D_IN = icap_inCount + 32'd1 ;
assign icap_inCount_EN = WILL_FIRE_RL_icap_write_configration_data ;
// register icap_outCount
assign icap_outCount_D_IN = icap_outCount + 32'd1 ;
assign icap_outCount_EN =
WILL_FIRE_RL_icap_read_configuration_data && !icap_icapBusy ;
// register wci_wslv_cEdge
assign wci_wslv_cEdge_D_IN = wci_wslv_reqF_D_OUT[36:34] ;
assign wci_wslv_cEdge_EN = WILL_FIRE_RL_wci_wslv_ctl_op_start ;
// register wci_wslv_cState
assign wci_wslv_cState_D_IN = wci_wslv_nState ;
assign wci_wslv_cState_EN =
WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge ;
// register wci_wslv_ctlAckReg
assign wci_wslv_ctlAckReg_D_IN = wci_wslv_ctlAckReg_1_whas ;
assign wci_wslv_ctlAckReg_EN = 1'd1 ;
// register wci_wslv_ctlOpActive
assign wci_wslv_ctlOpActive_D_IN = !WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
assign wci_wslv_ctlOpActive_EN =
WILL_FIRE_RL_wci_wslv_ctl_op_complete ||
WILL_FIRE_RL_wci_wslv_ctl_op_start ;
// register wci_wslv_illegalEdge
assign wci_wslv_illegalEdge_D_IN =
MUX_wci_wslv_illegalEdge_write_1__SEL_1 &&
MUX_wci_wslv_illegalEdge_write_1__VAL_1 ;
assign wci_wslv_illegalEdge_EN =
MUX_wci_wslv_illegalEdge_write_1__SEL_1 ||
WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ;
// register wci_wslv_isReset_isInReset
assign wci_wslv_isReset_isInReset_D_IN = 1'd0 ;
assign wci_wslv_isReset_isInReset_EN = wci_wslv_isReset_isInReset ;
// register wci_wslv_nState
always@(wci_wslv_reqF_D_OUT)
begin
case (wci_wslv_reqF_D_OUT[36:34])
3'd0: wci_wslv_nState_D_IN = 3'd1;
3'd1: wci_wslv_nState_D_IN = 3'd2;
3'd2: wci_wslv_nState_D_IN = 3'd3;
default: wci_wslv_nState_D_IN = 3'd0;
endcase
end
assign wci_wslv_nState_EN =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF_D_OUT[36:34] == 3'd0 && wci_wslv_cState == 3'd0 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd1 &&
(wci_wslv_cState == 3'd1 || wci_wslv_cState == 3'd3) ||
wci_wslv_reqF_D_OUT[36:34] == 3'd2 && wci_wslv_cState == 3'd2 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd3 &&
(wci_wslv_cState == 3'd3 || wci_wslv_cState == 3'd2 ||
wci_wslv_cState == 3'd1)) ;
// register wci_wslv_reqF_countReg
assign wci_wslv_reqF_countReg_D_IN =
(wci_wslv_wciReq_wget[71:69] != 3'd0) ?
wci_wslv_reqF_countReg + 2'd1 :
wci_wslv_reqF_countReg - 2'd1 ;
assign wci_wslv_reqF_countReg_EN =
(wci_wslv_wciReq_wget[71:69] != 3'd0) !=
wci_wslv_reqF_r_deq_whas ;
// register wci_wslv_respF_cntr_r
assign wci_wslv_respF_cntr_r_D_IN =
WILL_FIRE_RL_wci_wslv_respF_decCtr ?
wci_wslv_respF_cntr_r_8_MINUS_1___d27 :
MUX_wci_wslv_respF_cntr_r_write_1__VAL_2 ;
assign wci_wslv_respF_cntr_r_EN =
WILL_FIRE_RL_wci_wslv_respF_decCtr ||
WILL_FIRE_RL_wci_wslv_respF_incCtr ;
// register wci_wslv_respF_q_0
always@(MUX_wci_wslv_respF_q_0_write_1__SEL_1 or
MUX_wci_wslv_respF_q_0_write_1__VAL_1 or
MUX_wci_wslv_respF_q_0_write_1__SEL_2 or
MUX_wci_wslv_respF_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wci_wslv_respF_decCtr or wci_wslv_respF_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_wslv_respF_q_0_write_1__SEL_1:
wci_wslv_respF_q_0_D_IN = MUX_wci_wslv_respF_q_0_write_1__VAL_1;
MUX_wci_wslv_respF_q_0_write_1__SEL_2:
wci_wslv_respF_q_0_D_IN = MUX_wci_wslv_respF_q_0_write_1__VAL_2;
WILL_FIRE_RL_wci_wslv_respF_decCtr:
wci_wslv_respF_q_0_D_IN = wci_wslv_respF_q_1;
default: wci_wslv_respF_q_0_D_IN =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_wslv_respF_q_0_EN =
WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ||
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_cntr_r == 2'd0 ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_respF_q_1
always@(MUX_wci_wslv_respF_q_1_write_1__SEL_1 or
MUX_wci_wslv_respF_q_1_write_1__VAL_1 or
MUX_wci_wslv_respF_q_1_write_1__SEL_2 or
MUX_wci_wslv_respF_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wci_wslv_respF_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_wslv_respF_q_1_write_1__SEL_1:
wci_wslv_respF_q_1_D_IN = MUX_wci_wslv_respF_q_1_write_1__VAL_1;
MUX_wci_wslv_respF_q_1_write_1__SEL_2:
wci_wslv_respF_q_1_D_IN = MUX_wci_wslv_respF_q_0_write_1__VAL_2;
WILL_FIRE_RL_wci_wslv_respF_decCtr:
wci_wslv_respF_q_1_D_IN = 34'h0AAAAAAAA;
default: wci_wslv_respF_q_1_D_IN =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_wslv_respF_q_1_EN =
WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ||
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_cntr_r == 2'd1 ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_sFlagReg
assign wci_wslv_sFlagReg_D_IN = 1'b0 ;
assign wci_wslv_sFlagReg_EN = 1'd1 ;
// register wci_wslv_sThreadBusy_d
assign wci_wslv_sThreadBusy_d_D_IN = 1'b0 ;
assign wci_wslv_sThreadBusy_d_EN = 1'd1 ;
// submodule coutF_memory
assign coutF_memory_ADDRA =
{ coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d461,
coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d462,
coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d464,
coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d465,
coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d467,
coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d468,
coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d470,
coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d471,
coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d473,
coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d473 ^
coutF_rWrPtr_rsCounter[0] } ;
assign coutF_memory_ADDRB =
coutF_pwDequeue_whas ? x__h21947[9:0] : x2__h21916 ;
assign coutF_memory_DIA = x3__h20684 ;
assign coutF_memory_DIB = 32'hAAAAAAAA /* unspecified value */ ;
assign coutF_memory_WEA = coutF_pwEnqueue_whas ;
assign coutF_memory_WEB = 1'd0 ;
assign coutF_memory_ENA = 1'd1 ;
assign coutF_memory_ENB = 1'd1 ;
// submodule cre
assign cre_sD_IN = icapCtrl[1] ;
assign cre_sEN = cwe_sRDY && cre_sRDY && wci_wslv_cState == 3'd2 ;
// submodule cwe
assign cwe_sD_IN = icapCtrl[0] ;
assign cwe_sEN = cwe_sRDY && cre_sRDY && wci_wslv_cState == 3'd2 ;
// submodule icap_cinF
assign icap_cinF_D_IN = cinS ;
assign icap_cinF_ENQ = cinF_deq_pw_whas ;
assign icap_cinF_DEQ = WILL_FIRE_RL_icap_write_configration_data ;
assign icap_cinF_CLR = 1'b0 ;
// submodule icap_coutF
assign icap_coutF_D_IN =
{ icap_icapOut[24],
icap_icapOut[25],
icap_icapOut[26],
icap_icapOut[27],
icap_icapOut[28],
icap_icapOut[29],
icap_icapOut[30],
icap_icapOut[31],
icap_icapOut[16],
icap_icapOut[17],
icap_icapOut[18],
icap_icapOut[19],
icap_icapOut[20],
icap_icapOut[21],
icap_icapOut[22],
icap_icapOut[23],
icap_icapOut[8],
icap_icapOut[9],
icap_icapOut[10],
icap_icapOut[11],
icap_icapOut[12],
icap_icapOut[13],
icap_icapOut[14],
icap_icapOut[15],
icap_icapOut[0],
icap_icapOut[1],
icap_icapOut[2],
icap_icapOut[3],
icap_icapOut[4],
icap_icapOut[5],
icap_icapOut[6],
icap_icapOut[7] } ;
assign icap_coutF_ENQ =
WILL_FIRE_RL_icap_read_configuration_data && !icap_icapBusy ;
assign icap_coutF_DEQ = coutF_pwEnqueue_whas ;
assign icap_coutF_CLR = 1'b0 ;
// submodule icap_icap
assign icap_icap_CSB = !icap_icapCs ;
assign icap_icap_I = icap_icapIn ;
assign icap_icap_RDWRB = icap_icapRd ;
// submodule inCnt
assign inCnt_sD_IN = icap_inCount ;
assign inCnt_sEN = inCnt_sRDY ;
// submodule outCnt
assign outCnt_sD_IN = icap_outCount ;
assign outCnt_sEN = outCnt_sRDY ;
// submodule wci_wslv_reqF
assign wci_wslv_reqF_D_IN = wci_wslv_wciReq_wget ;
assign wci_wslv_reqF_ENQ = wci_wslv_wciReq_wget[71:69] != 3'd0 ;
assign wci_wslv_reqF_DEQ = wci_wslv_reqF_r_deq_whas ;
assign wci_wslv_reqF_CLR = 1'b0 ;
// remaining internal signals
assign IF_coutF_rRdPtr_rsCounter_91_BIT_0_98_OR_coutF_ETC___d439 =
(coutF_rRdPtr_rsCounter[0] || coutF_rRdPtr_rsCounter[1] ||
coutF_rRdPtr_rsCounter[2] ||
coutF_rRdPtr_rsCounter[3] ||
coutF_rRdPtr_rsCounter[4] ||
coutF_rRdPtr_rsCounter[5] ||
coutF_rRdPtr_rsCounter[6] ||
coutF_rRdPtr_rsCounter[7] ||
coutF_rRdPtr_rsCounter[8] ||
coutF_rRdPtr_rsCounter[9]) ?
(coutF_rRdPtr_rsCounter[0] ?
32'd1 :
(coutF_rRdPtr_rsCounter[1] ?
32'd2 :
(coutF_rRdPtr_rsCounter[2] ?
32'd3 :
(coutF_rRdPtr_rsCounter[3] ?
32'd4 :
(coutF_rRdPtr_rsCounter[4] ?
32'd5 :
(coutF_rRdPtr_rsCounter[5] ?
32'd6 :
(coutF_rRdPtr_rsCounter[6] ?
32'd7 :
(coutF_rRdPtr_rsCounter[7] ?
32'd8 :
(coutF_rRdPtr_rsCounter[8] ?
32'd9 :
(coutF_rRdPtr_rsCounter[9] ?
32'd10 :
(coutF_rRdPtr_rsCounter[10] ?
32'd11 :
32'd12))))))))))) :
32'd10 ;
assign IF_coutF_rRdPtr_rsCounter_91_BIT_0_98_XOR_cout_ETC___d440 =
coutF_rRdPtr_rsCounter_91_BIT_0_98_XOR_coutF_r_ETC___d418 ?
IF_coutF_rRdPtr_rsCounter_91_BIT_0_98_OR_coutF_ETC___d439 :
32'd0 ;
assign IF_coutF_rWrPtr_rsCounter_22_BIT_0_29_OR_coutF_ETC___d370 =
(coutF_rWrPtr_rsCounter[0] || coutF_rWrPtr_rsCounter[1] ||
coutF_rWrPtr_rsCounter[2] ||
coutF_rWrPtr_rsCounter[3] ||
coutF_rWrPtr_rsCounter[4] ||
coutF_rWrPtr_rsCounter[5] ||
coutF_rWrPtr_rsCounter[6] ||
coutF_rWrPtr_rsCounter[7] ||
coutF_rWrPtr_rsCounter[8] ||
coutF_rWrPtr_rsCounter[9]) ?
(coutF_rWrPtr_rsCounter[0] ?
32'd1 :
(coutF_rWrPtr_rsCounter[1] ?
32'd2 :
(coutF_rWrPtr_rsCounter[2] ?
32'd3 :
(coutF_rWrPtr_rsCounter[3] ?
32'd4 :
(coutF_rWrPtr_rsCounter[4] ?
32'd5 :
(coutF_rWrPtr_rsCounter[5] ?
32'd6 :
(coutF_rWrPtr_rsCounter[6] ?
32'd7 :
(coutF_rWrPtr_rsCounter[7] ?
32'd8 :
(coutF_rWrPtr_rsCounter[8] ?
32'd9 :
(coutF_rWrPtr_rsCounter[9] ?
32'd10 :
(coutF_rWrPtr_rsCounter[10] ?
32'd11 :
32'd12))))))))))) :
32'd10 ;
assign IF_coutF_rWrPtr_rsCounter_22_BIT_0_29_XOR_cout_ETC___d371 =
coutF_rWrPtr_rsCounter_22_BIT_0_29_XOR_coutF_r_ETC___d349 ?
IF_coutF_rWrPtr_rsCounter_22_BIT_0_29_OR_coutF_ETC___d370 :
32'd0 ;
assign NOT_coutF_rRdPtr_rsCounter_91_EQ_coutF_rWrPtr__ETC___d599 =
coutF_rRdPtr_rsCounter != coutF_rWrPtr_rdCounter ;
assign NOT_wci_wslv_respF_cntr_r_8_EQ_2_1_2_AND_wci_w_ETC___d590 =
wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF_EMPTY_N &&
(wci_wslv_reqF_D_OUT[63:32] != 32'h00000008 ||
cinF_head_wrapped == cinF_tail_wrapped && !cinF_sInReset_VAL &&
cd_PREEDGE) ;
assign _dfoo1 =
wci_wslv_respF_cntr_r != 2'd2 ||
wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd1 ;
assign _dfoo3 =
wci_wslv_respF_cntr_r != 2'd1 ||
wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ;
assign coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549 =
x_dReadBin__h20388 + 11'd512 ;
assign coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d525 =
coutF_rRdPtr_rdCounter[10] ^ coutF_rRdPtr_rdCounter[9] ;
assign coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d527 =
coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d525 ^
coutF_rRdPtr_rdCounter[8] ;
assign coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d530 =
coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d527 ^
coutF_rRdPtr_rdCounter[7] ;
assign coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d532 =
coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d530 ^
coutF_rRdPtr_rdCounter[6] ;
assign coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d535 =
coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d532 ^
coutF_rRdPtr_rdCounter[5] ;
assign coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d537 =
coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d535 ^
coutF_rRdPtr_rdCounter[4] ;
assign coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d540 =
coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d537 ^
coutF_rRdPtr_rdCounter[3] ;
assign coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d542 =
coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d540 ^
coutF_rRdPtr_rdCounter[2] ;
assign coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d545 =
coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d542 ^
coutF_rRdPtr_rdCounter[1] ;
assign coutF_rRdPtr_rsCounter_91_BIT_0_98_XOR_coutF_r_ETC___d418 =
z__h19562 ^ coutF_rRdPtr_rsCounter[10] ;
assign coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d481 =
coutF_rRdPtr_rsCounter[10] ^ coutF_rRdPtr_rsCounter[9] ;
assign coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d482 =
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d481 ^
coutF_rRdPtr_rsCounter[8] ;
assign coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d484 =
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d482 ^
coutF_rRdPtr_rsCounter[7] ;
assign coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d485 =
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d484 ^
coutF_rRdPtr_rsCounter[6] ;
assign coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d487 =
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d485 ^
coutF_rRdPtr_rsCounter[5] ;
assign coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d488 =
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d487 ^
coutF_rRdPtr_rsCounter[4] ;
assign coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d490 =
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d488 ^
coutF_rRdPtr_rsCounter[3] ;
assign coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d491 =
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d490 ^
coutF_rRdPtr_rsCounter[2] ;
assign coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d493 =
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d491 ^
coutF_rRdPtr_rsCounter[1] ;
assign coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d494 =
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d493 ^
coutF_rRdPtr_rsCounter[0] ;
assign coutF_rWrPtr_rsCounter_22_BIT_0_29_XOR_coutF_r_ETC___d349 =
z__h17260 ^ coutF_rWrPtr_rsCounter[10] ;
assign coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d461 =
coutF_rWrPtr_rsCounter[10] ^ coutF_rWrPtr_rsCounter[9] ;
assign coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d462 =
coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d461 ^
coutF_rWrPtr_rsCounter[8] ;
assign coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d464 =
coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d462 ^
coutF_rWrPtr_rsCounter[7] ;
assign coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d465 =
coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d464 ^
coutF_rWrPtr_rsCounter[6] ;
assign coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d467 =
coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d465 ^
coutF_rWrPtr_rsCounter[5] ;
assign coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d468 =
coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d467 ^
coutF_rWrPtr_rsCounter[4] ;
assign coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d470 =
coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d468 ^
coutF_rWrPtr_rsCounter[3] ;
assign coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d471 =
coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d470 ^
coutF_rWrPtr_rsCounter[2] ;
assign coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d473 =
coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d471 ^
coutF_rWrPtr_rsCounter[1] ;
assign icapStatus__h26003 = { 29'd0, x__h26497 } ;
assign rdat__h26404 = hasDebugLogic ? dwWritten : 32'd0 ;
assign rdat__h26410 = hasDebugLogic ? dwRead : 32'd0 ;
assign rdat__h26416 = hasDebugLogic ? inCnt_dD_OUT : 32'd0 ;
assign rdat__h26422 = hasDebugLogic ? outCnt_dD_OUT : 32'd0 ;
assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 =
wci_wslv_respF_cntr_r - 2'd1 ;
assign x2__h21916 =
{ coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d481,
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d482,
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d484,
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d485,
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d487,
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d488,
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d490,
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d491,
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d493,
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d494 } ;
assign x3__h20684 = coutF_pwEnqueue_whas ? icap_coutF_D_OUT : 32'd0 ;
assign x__h16273 =
11'd1 <<
IF_coutF_rWrPtr_rsCounter_22_BIT_0_29_XOR_cout_ETC___d371 ;
assign x__h18575 =
11'd1 <<
IF_coutF_rRdPtr_rsCounter_91_BIT_0_98_XOR_cout_ETC___d440 ;
assign x__h21947 = x_sReadBin__h20385 + 11'd1 ;
assign x__h26497 =
{ NOT_coutF_rRdPtr_rsCounter_91_EQ_coutF_rWrPtr__ETC___d599,
icapCtrl[1:0] } ;
assign x_dReadBin__h20388 =
{ coutF_rRdPtr_rdCounter[10],
coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d525,
coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d527,
coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d530,
coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d532,
coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d535,
coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d537,
coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d540,
coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d542,
coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d545,
coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d545 ^
coutF_rRdPtr_rdCounter[0] } ;
assign x_sReadBin__h20385 =
{ coutF_rRdPtr_rsCounter[10],
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d481,
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d482,
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d484,
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d485,
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d487,
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d488,
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d490,
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d491,
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d493,
coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d494 } ;
assign y__h17160 = ~x__h16273 ;
assign y__h19462 = ~x__h18575 ;
assign z__h17204 = coutF_rWrPtr_rsCounter[0] ^ coutF_rWrPtr_rsCounter[1] ;
assign z__h17211 = z__h17204 ^ coutF_rWrPtr_rsCounter[2] ;
assign z__h17218 = z__h17211 ^ coutF_rWrPtr_rsCounter[3] ;
assign z__h17225 = z__h17218 ^ coutF_rWrPtr_rsCounter[4] ;
assign z__h17232 = z__h17225 ^ coutF_rWrPtr_rsCounter[5] ;
assign z__h17239 = z__h17232 ^ coutF_rWrPtr_rsCounter[6] ;
assign z__h17246 = z__h17239 ^ coutF_rWrPtr_rsCounter[7] ;
assign z__h17253 = z__h17246 ^ coutF_rWrPtr_rsCounter[8] ;
assign z__h17260 = z__h17253 ^ coutF_rWrPtr_rsCounter[9] ;
assign z__h19506 = coutF_rRdPtr_rsCounter[0] ^ coutF_rRdPtr_rsCounter[1] ;
assign z__h19513 = z__h19506 ^ coutF_rRdPtr_rsCounter[2] ;
assign z__h19520 = z__h19513 ^ coutF_rRdPtr_rsCounter[3] ;
assign z__h19527 = z__h19520 ^ coutF_rRdPtr_rsCounter[4] ;
assign z__h19534 = z__h19527 ^ coutF_rRdPtr_rsCounter[5] ;
assign z__h19541 = z__h19534 ^ coutF_rRdPtr_rsCounter[6] ;
assign z__h19548 = z__h19541 ^ coutF_rRdPtr_rsCounter[7] ;
assign z__h19555 = z__h19548 ^ coutF_rRdPtr_rsCounter[8] ;
assign z__h19562 = z__h19555 ^ coutF_rRdPtr_rsCounter[9] ;
always@(wci_wslv_reqF_D_OUT or
icapStatus__h26003 or
icapCtrl or
coutF_memory_DOB or
rdat__h26404 or rdat__h26410 or rdat__h26416 or rdat__h26422)
begin
case (wci_wslv_reqF_D_OUT[63:32])
32'h0: v__h26380 = icapStatus__h26003;
32'h00000004: v__h26380 = icapCtrl;
32'h0000000C: v__h26380 = coutF_memory_DOB;
32'h00000040: v__h26380 = rdat__h26404;
32'h00000044: v__h26380 = rdat__h26410;
32'h00000048: v__h26380 = rdat__h26416;
32'h0000004C: v__h26380 = rdat__h26422;
default: v__h26380 = 32'd0;
endcase
end
// handling of inlined registers
always@(posedge wciS0_Clk)
begin
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
cinF_tail_wrapped <= `BSV_ASSIGNMENT_DELAY 1'd0;
dwRead <= `BSV_ASSIGNMENT_DELAY 32'd0;
dwWritten <= `BSV_ASSIGNMENT_DELAY 32'd0;
icapCtrl <= `BSV_ASSIGNMENT_DELAY 32'd0;
wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2;
wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (cinF_tail_wrapped_EN)
cinF_tail_wrapped <= `BSV_ASSIGNMENT_DELAY cinF_tail_wrapped_D_IN;
if (dwRead_EN) dwRead <= `BSV_ASSIGNMENT_DELAY dwRead_D_IN;
if (dwWritten_EN) dwWritten <= `BSV_ASSIGNMENT_DELAY dwWritten_D_IN;
if (icapCtrl_EN) icapCtrl <= `BSV_ASSIGNMENT_DELAY icapCtrl_D_IN;
if (wci_wslv_cEdge_EN)
wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY wci_wslv_cEdge_D_IN;
if (wci_wslv_cState_EN)
wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY wci_wslv_cState_D_IN;
if (wci_wslv_ctlAckReg_EN)
wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_ctlAckReg_D_IN;
if (wci_wslv_ctlOpActive_EN)
wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY
wci_wslv_ctlOpActive_D_IN;
if (wci_wslv_illegalEdge_EN)
wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY
wci_wslv_illegalEdge_D_IN;
if (wci_wslv_nState_EN)
wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY wci_wslv_nState_D_IN;
if (wci_wslv_reqF_countReg_EN)
wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY
wci_wslv_reqF_countReg_D_IN;
if (wci_wslv_respF_cntr_r_EN)
wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY
wci_wslv_respF_cntr_r_D_IN;
if (wci_wslv_respF_q_0_EN)
wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_0_D_IN;
if (wci_wslv_respF_q_1_EN)
wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_1_D_IN;
if (wci_wslv_sFlagReg_EN)
wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_sFlagReg_D_IN;
if (wci_wslv_sThreadBusy_d_EN)
wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
wci_wslv_sThreadBusy_d_D_IN;
end
if (cinS_EN) cinS <= `BSV_ASSIGNMENT_DELAY cinS_D_IN;
end
always@(posedge cd_CLK_OUT)
begin
if (slowReset_OUT_RST == `BSV_RESET_VALUE)
begin
cinF_head_wrapped <= `BSV_ASSIGNMENT_DELAY 1'd0;
icap_icapBusy <= `BSV_ASSIGNMENT_DELAY 1'd1;
icap_icapCs <= `BSV_ASSIGNMENT_DELAY 1'd0;
icap_icapIn <= `BSV_ASSIGNMENT_DELAY 32'hFFFFFFFF;
icap_icapOut <= `BSV_ASSIGNMENT_DELAY 32'hFFFFFFFF;
icap_icapRd <= `BSV_ASSIGNMENT_DELAY 1'd0;
icap_inCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
icap_outCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
end
else
begin
if (cinF_head_wrapped_EN)
cinF_head_wrapped <= `BSV_ASSIGNMENT_DELAY cinF_head_wrapped_D_IN;
if (icap_icapBusy_EN)
icap_icapBusy <= `BSV_ASSIGNMENT_DELAY icap_icapBusy_D_IN;
if (icap_icapCs_EN)
icap_icapCs <= `BSV_ASSIGNMENT_DELAY icap_icapCs_D_IN;
if (icap_icapIn_EN)
icap_icapIn <= `BSV_ASSIGNMENT_DELAY icap_icapIn_D_IN;
if (icap_icapOut_EN)
icap_icapOut <= `BSV_ASSIGNMENT_DELAY icap_icapOut_D_IN;
if (icap_icapRd_EN)
icap_icapRd <= `BSV_ASSIGNMENT_DELAY icap_icapRd_D_IN;
if (icap_inCount_EN)
icap_inCount <= `BSV_ASSIGNMENT_DELAY icap_inCount_D_IN;
if (icap_outCount_EN)
icap_outCount <= `BSV_ASSIGNMENT_DELAY icap_outCount_D_IN;
end
end
always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n)
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
coutF_rRdPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY 11'd0;
coutF_rWrPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY 11'd0;
coutF_rWrPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY 11'd0;
wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (coutF_rRdPtr_rsCounter_EN)
coutF_rRdPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY
coutF_rRdPtr_rsCounter_D_IN;
if (coutF_rWrPtr_rdCounter_EN)
coutF_rWrPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY
coutF_rWrPtr_rdCounter_D_IN;
if (coutF_rWrPtr_rdCounterPre_EN)
coutF_rWrPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY
coutF_rWrPtr_rdCounterPre_D_IN;
if (wci_wslv_isReset_isInReset_EN)
wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wci_wslv_isReset_isInReset_D_IN;
end
always@(posedge cd_CLK_OUT or `BSV_RESET_EDGE slowReset_OUT_RST)
if (slowReset_OUT_RST == `BSV_RESET_VALUE)
begin
coutF_rRdPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY 11'd0;
coutF_rRdPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY 11'd0;
coutF_rWrPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY 11'd0;
end
else
begin
if (coutF_rRdPtr_rdCounter_EN)
coutF_rRdPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY
coutF_rRdPtr_rdCounter_D_IN;
if (coutF_rRdPtr_rdCounterPre_EN)
coutF_rRdPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY
coutF_rRdPtr_rdCounterPre_D_IN;
if (coutF_rWrPtr_rsCounter_EN)
coutF_rWrPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY
coutF_rWrPtr_rsCounter_D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
cinF_head_wrapped = 1'h0;
cinF_tail_wrapped = 1'h0;
cinS = 32'hAAAAAAAA;
coutF_rRdPtr_rdCounter = 11'h2AA;
coutF_rRdPtr_rdCounterPre = 11'h2AA;
coutF_rRdPtr_rsCounter = 11'h2AA;
coutF_rWrPtr_rdCounter = 11'h2AA;
coutF_rWrPtr_rdCounterPre = 11'h2AA;
coutF_rWrPtr_rsCounter = 11'h2AA;
dwRead = 32'hAAAAAAAA;
dwWritten = 32'hAAAAAAAA;
icapCtrl = 32'hAAAAAAAA;
icap_icapBusy = 1'h0;
icap_icapCs = 1'h0;
icap_icapIn = 32'hAAAAAAAA;
icap_icapOut = 32'hAAAAAAAA;
icap_icapRd = 1'h0;
icap_inCount = 32'hAAAAAAAA;
icap_outCount = 32'hAAAAAAAA;
wci_wslv_cEdge = 3'h2;
wci_wslv_cState = 3'h2;
wci_wslv_ctlAckReg = 1'h0;
wci_wslv_ctlOpActive = 1'h0;
wci_wslv_illegalEdge = 1'h0;
wci_wslv_isReset_isInReset = 1'h0;
wci_wslv_nState = 3'h2;
wci_wslv_reqF_countReg = 2'h2;
wci_wslv_respF_cntr_r = 2'h2;
wci_wslv_respF_q_0 = 34'h2AAAAAAAA;
wci_wslv_respF_q_1 = 34'h2AAAAAAAA;
wci_wslv_sFlagReg = 1'h0;
wci_wslv_sThreadBusy_d = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge wciS0_Clk)
begin
#0;
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_start)
begin
v__h3563 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_start)
$display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x",
v__h3563,
wci_wslv_reqF_D_OUT[36:34],
wci_wslv_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO)
begin
v__h26628 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO)
$display("[%0d]: %m: Starting ICAPWorker", v__h26628);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/ICAPWorker.bsv\", line 77, column 60: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/ICAPWorker.bsv\", line 77, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/ICAPWorker.bsv\", line 77, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge)
begin
v__h3882 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x",
v__h3882,
wci_wslv_cEdge,
wci_wslv_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge)
begin
v__h3738 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x",
v__h3738,
wci_wslv_cEdge,
wci_wslv_cState,
wci_wslv_nState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/ICAPWorker.bsv\", line 77, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/ICAPWorker.bsv\", line 77, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/wrk/ICAPWorker.bsv\", line 77, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd)
$display("Error: \"bsv/wrk/ICAPWorker.bsv\", line 77, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/ICAPWorker.bsv\", line 77, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/ICAPWorker.bsv\", line 77, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/wrk/ICAPWorker.bsv\", line 77, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
end
// synopsys translate_on
// synopsys translate_off
always@(negedge cd_CLK_OUT)
begin
#0;
if (slowReset_OUT_RST != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_icap_write_configration_data &&
WILL_FIRE_RL_icap_read_configuration_data)
$display("Error: \"bsv/dev/ICAP.bsv\", line 127, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_icap_write_configration_data]\n and [RL_icap_read_configuration_data] ) fired in the same clock cycle.\n");
end
// synopsys translate_on
endmodule // mkICAPWorker
|
//======================================================================
//
// tb_sha256_axi4.v
// ----------------
// Testbench for the SHA256 AXI4 wrapper.
//
//
// Author: Sanjay A Menon
// Copyright (c) 2020
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module tb_sha256_axi4();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 0;
parameter CLK_HALF_PERIOD = 2;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg tb_clk;
reg tb_reset_n;
reg [7:0] tb_awaddr;
reg [2:0] tb_awprot;
reg tb_awvalid;
wire tb_awready;
reg [31:0] tb_wdata;
reg [3:0] tb_wstrb;
reg tb_wvalid;
wire tb_wready;
wire [1:0] tb_bresp;
wire tb_bvalid;
reg tb_bready;
reg [7:0] tb_araddr;
reg [2:0] tb_arprot;
reg tb_arvalid;
wire tb_arready;
wire [31:0] tb_rdata;
wire [1:0] tb_rresp;
wire tb_rvalid;
reg tb_rready;
wire complete;
reg tb_init;
reg tb_next;
reg tb_mode;
reg [511 : 0] tb_block;
wire tb_ready;
reg [255 : 0] tb_digest;
wire tb_digest_valid;
reg [31:0] i;
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
sha256_axi4 dut(
.hash_complete(complete),
.s00_axi_aclk(tb_clk),
.s00_axi_aresetn(tb_reset_n),
.s00_axi_awaddr(tb_awaddr),
.s00_axi_awprot(tb_awprot),
.s00_axi_awvalid(tb_awvalid),
.s00_axi_awready(tb_awready),
.s00_axi_wdata(tb_wdata),
.s00_axi_wstrb(tb_wstrb),
.s00_axi_wvalid(tb_wvalid),
.s00_axi_wready(tb_wready),
.s00_axi_bresp(tb_bresp),
.s00_axi_bvalid(tb_bvalid),
.s00_axi_bready(tb_bready),
.s00_axi_araddr(tb_araddr),
.s00_axi_arprot(tb_arprot),
.s00_axi_arvalid(tb_arvalid),
.s00_axi_arready(tb_arready),
.s00_axi_rdata(tb_rdata),
.s00_axi_rresp(tb_rresp),
.s00_axi_rvalid(tb_rvalid),
.s00_axi_rready(tb_rready)
);
//----------------------------------------------------------------
// clk_gen
//
// Always running clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end // clk_gen
//----------------------------------------------------------------
// sys_monitor()
//
// An always running process that creates a cycle counter and
// conditionally displays information about the DUT.
//----------------------------------------------------------------
always
begin : sys_monitor
cycle_ctr = cycle_ctr + 1;
#(2 * CLK_HALF_PERIOD);
if (DEBUG)
begin
//dump_dut_state();
end
end
//----------------------------------------------------------------
// dump_dut_state()
//
// Dump the state of the dump when needed.
//----------------------------------------------------------------
/*task dump_dut_state;
begin
$display("State of DUT");
$display("------------");
$display("Inputs and outputs:");
$display("init = 0x%01x, next = 0x%01x",
dut.init, dut.next);
$display("block = 0x%0128x", dut.block);
$display("ready = 0x%01x, valid = 0x%01x",
dut.ready, dut.digest_valid);
$display("digest = 0x%064x", dut.digest);
$display("H0_reg = 0x%08x, H1_reg = 0x%08x, H2_reg = 0x%08x, H3_reg = 0x%08x",
dut.H0_reg, dut.H1_reg, dut.H2_reg, dut.H3_reg);
$display("H4_reg = 0x%08x, H5_reg = 0x%08x, H6_reg = 0x%08x, H7_reg = 0x%08x",
dut.H4_reg, dut.H5_reg, dut.H6_reg, dut.H7_reg);
$display("");
$display("Control signals and counter:");
$display("sha256_ctrl_reg = 0x%02x", dut.sha256_ctrl_reg);
$display("digest_init = 0x%01x, digest_update = 0x%01x",
dut.digest_init, dut.digest_update);
$display("state_init = 0x%01x, state_update = 0x%01x",
dut.state_init, dut.state_update);
$display("first_block = 0x%01x, ready_flag = 0x%01x, w_init = 0x%01x",
dut.first_block, dut.ready_flag, dut.w_init);
$display("t_ctr_inc = 0x%01x, t_ctr_rst = 0x%01x, t_ctr_reg = 0x%02x",
dut.t_ctr_inc, dut.t_ctr_rst, dut.t_ctr_reg);
$display("");
$display("State registers:");
$display("a_reg = 0x%08x, b_reg = 0x%08x, c_reg = 0x%08x, d_reg = 0x%08x",
dut.a_reg, dut.b_reg, dut.c_reg, dut.d_reg);
$display("e_reg = 0x%08x, f_reg = 0x%08x, g_reg = 0x%08x, h_reg = 0x%08x",
dut.e_reg, dut.f_reg, dut.g_reg, dut.h_reg);
$display("");
$display("a_new = 0x%08x, b_new = 0x%08x, c_new = 0x%08x, d_new = 0x%08x",
dut.a_new, dut.b_new, dut.c_new, dut.d_new);
$display("e_new = 0x%08x, f_new = 0x%08x, g_new = 0x%08x, h_new = 0x%08x",
dut.e_new, dut.f_new, dut.g_new, dut.h_new);
$display("");
$display("State update values:");
$display("w = 0x%08x, k = 0x%08x", dut.w_data, dut.k_data);
$display("t1 = 0x%08x, t2 = 0x%08x", dut.t1, dut.t2);
$display("");
end
endtask // dump_dut_state */
//----------------------------------------------------------------
// reset_dut()
//
// Toggle reset to put the DUT into a well known state.
//----------------------------------------------------------------
task reset_dut;
begin
$display("*** Toggle reset.");
tb_reset_n = 0;
#(4 * CLK_HALF_PERIOD);
tb_reset_n = 1;
end
endtask // reset_dut
//----------------------------------------------------------------
// init_sim()
//
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
task init_sim;
begin
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 1;
tb_awaddr = 8'h00;
tb_awprot = 3'b000;
tb_awvalid = 0;
tb_wdata = 32'h00000000;
tb_wstrb = 4'h0;
tb_wvalid = 0;
tb_bready = 0;
tb_araddr = 8'h00;
tb_arprot = 3'b000;
tb_arvalid = 0;
tb_rready = 0;
i = 0;
end
endtask // init_dut
//----------------------------------------------------------------
// display_test_result()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_result;
begin
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d test cases did not complete successfully.", error_ctr);
end
end
endtask // display_test_result
//----------------------------------------------------------------
// wait_ready()
//
// Wait for the ready flag in the dut to be set.
//
// Note: It is the callers responsibility to call the function
// when the dut is actively processing and will in fact at some
// point set the flag.
//----------------------------------------------------------------
task wait_ready;
begin
while (!tb_awready)
begin
#(CLK_PERIOD);
end
end
endtask // wait_ready
task wait_read;
begin
while (!tb_arready)//tb_arready
begin
#(CLK_PERIOD);
end
end
endtask // wait_read
task wait_hash_complete;
begin
while (!complete)
begin
#(CLK_PERIOD);
end
end
endtask // wait_hash_complete
//----------------------------------------------------------------
// single_block_test()
//
// Run a test case spanning a single data block.
//----------------------------------------------------------------
task single_block_test(input [7 : 0] tc_number,
input [511 : 0] block,
input [255 : 0] expected);
begin
$display("*** TC %0d single block test case started.", tc_number);
tc_ctr = tc_ctr + 1;
//Input Section
tb_awprot = 1;
tb_bready = 1;
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h1f;
tb_wdata = block[31:0];
#(CLK_PERIOD);
wait_ready();
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h1e;
tb_wdata = block[63:32];
#(CLK_PERIOD);
wait_ready();
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h1d;
tb_wdata = block[95:64];
#(CLK_PERIOD);
wait_ready();
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h1c;
tb_wdata = block[127:96];
#(CLK_PERIOD);
wait_ready();
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h1b;
tb_wdata = block[159:128];
#(CLK_PERIOD);
wait_ready();
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h1a;
tb_wdata = block[191:160];
#(CLK_PERIOD);
wait_ready();
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h19;
tb_wdata = block[223:192];
#(CLK_PERIOD);
wait_ready();
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h18;
tb_wdata = block[255:224];
#(CLK_PERIOD);
wait_ready();
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h17;
tb_wdata = block[287:256];
#(CLK_PERIOD);
wait_ready();
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h16;
tb_wdata = block[319:288];
#(CLK_PERIOD);
wait_ready();
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h15;
tb_wdata = block[351:320];
#(CLK_PERIOD);
wait_ready();
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h14;
tb_wdata = block[383:352];
#(CLK_PERIOD);
wait_ready();
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h13;
tb_wdata = block[415:384];
#(CLK_PERIOD);
wait_ready();
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h12;
tb_wdata = block[447:416];
#(CLK_PERIOD);
wait_ready();
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h11;
tb_wdata = block[479:448];
#(CLK_PERIOD);
wait_ready();
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h10;
tb_wdata = block[511:480];
#(CLK_PERIOD);
wait_ready();
//Computation initiation by specifying block_init/block_next
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h08;
tb_wdata = 32'h00000005;
#(CLK_PERIOD);
wait_ready();
tb_awvalid = 1;
tb_wvalid = 1;
tb_awaddr = 8'h08;
tb_wdata = 32'h00000004;
#(CLK_PERIOD);
wait_ready();
//output section
wait_hash_complete();
tb_awvalid = 0;
tb_wvalid = 0;
tb_arprot = 1;
tb_arvalid = 1;
tb_rready = 1;
tb_arvalid = 1;
tb_rready = 1;
tb_araddr = 8'h20;
#(CLK_PERIOD);
wait_read();
tb_digest[255:224] <= tb_rdata;
tb_arvalid = 1;
tb_rready = 1;
tb_araddr = 8'h21;
#(CLK_PERIOD);
wait_read();
tb_digest[223:192] <= tb_rdata;
tb_arvalid = 1;
tb_rready = 1;
tb_araddr = 8'h22;
#(CLK_PERIOD);
wait_read();
tb_digest[191:160] <= tb_rdata;
tb_arvalid = 1;
tb_rready = 1;
tb_araddr = 8'h23;
#(CLK_PERIOD);
wait_read();
tb_digest[159:128] <= tb_rdata;
tb_arvalid = 1;
tb_rready = 1;
tb_araddr = 8'h24;
#(CLK_PERIOD);
wait_read();
tb_digest[127:96] <= tb_rdata;
tb_arvalid = 1;
tb_rready = 1;
tb_araddr = 8'h25;
#(CLK_PERIOD);
wait_read();
tb_digest[95:64] <= tb_rdata;
tb_arvalid = 1;
tb_rready = 1;
tb_araddr = 8'h26;
#(CLK_PERIOD);
wait_read();
tb_digest[63:32] <= tb_rdata;
tb_arvalid = 1;
tb_rready = 1;
tb_araddr = 8'h27;
#(CLK_PERIOD);
wait_read();
tb_digest[31:0] <= tb_rdata;
tb_arvalid = 1;
tb_rready = 1;
tb_araddr = 8'h27;
#(CLK_PERIOD);
wait_read();
tb_digest[31:0] <= tb_rdata;
if (tb_digest == expected)
begin
$display("*** TC %0d successful.", tc_number);
end
else
begin
$display("*** ERROR: TC %0d NOT successful.", tc_number);
$display("Expected: 0x%064x", expected);
$display("Got: 0x%064x", tb_digest);
$display("");
error_ctr = error_ctr + 1;
end
end
endtask // single_block_test
//----------------------------------------------------------------
// double_block_test()
//
// Run a test case spanning two data blocks. We check both
// intermediate and final digest.
//----------------------------------------------------------------
task double_block_test(input [7 : 0] tc_number,
input [511 : 0] block1,
input [255 : 0] expected1,
input [511 : 0] block2,
input [255 : 0] expected2);
reg [255 : 0] db_digest1;
reg [255 : 0] db_digest2;
reg db_error;
begin
$display("*** TC %0d double block test case started.", tc_number);
db_error = 0;
tc_ctr = tc_ctr + 1;
$display("*** TC %0d first block started.", tc_number);
tb_block = block1;
tb_init = 1;
#(CLK_PERIOD);
tb_init = 0;
wait_ready();
db_digest1 = tb_digest;
$display("*** TC %0d first block done.", tc_number);
$display("*** TC %0d second block started.", tc_number);
tb_block = block2;
tb_next = 1;
#(CLK_PERIOD);
tb_next = 0;
wait_ready();
db_digest2 = tb_digest;
$display("*** TC %0d second block done.", tc_number);
if (DEBUG)
begin
$display("Generated digests:");
$display("Expected 1: 0x%064x", expected1);
$display("Got 1: 0x%064x", db_digest1);
$display("Expected 2: 0x%064x", expected2);
$display("Got 2: 0x%064x", db_digest2);
$display("");
end
if (db_digest1 == expected1)
begin
$display("*** TC %0d first block successful", tc_number);
$display("");
end
else
begin
$display("*** ERROR: TC %0d first block NOT successful", tc_number);
$display("Expected: 0x%064x", expected1);
$display("Got: 0x%064x", db_digest1);
$display("");
db_error = 1;
end
if (db_digest2 == expected2)
begin
$display("*** TC %0d second block successful", tc_number);
$display("");
end
else
begin
$display("*** ERROR: TC %0d second block NOT successful", tc_number);
$display("Expected: 0x%064x", expected2);
$display("Got: 0x%064x", db_digest2);
$display("");
db_error = 1;
end
if (db_error)
begin
error_ctr = error_ctr + 1;
end
end
endtask // double_block_test
//----------------------------------------------------------------
// issue_test()
//----------------------------------------------------------------
task issue_test;
reg [511 : 0] block0;
reg [511 : 0] block1;
reg [511 : 0] block2;
reg [511 : 0] block3;
reg [511 : 0] block4;
reg [511 : 0] block5;
reg [511 : 0] block6;
reg [511 : 0] block7;
reg [511 : 0] block8;
reg [255 : 0] expected;
begin : issue_test;
block0 = 512'h6b900001_496e2074_68652061_72656120_6f662049_6f542028_496e7465_726e6574_206f6620_5468696e_6773292c_206d6f72_6520616e_64206d6f_7265626f_6f6d2c20;
block1 = 512'h69742068_61732062_65656e20_6120756e_69766572_73616c20_636f6e73_656e7375_73207468_61742064_61746120_69732074_69732061_206e6577_20746563_686e6f6c;
block2 = 512'h6f677920_74686174_20696e74_65677261_74657320_64656365_6e747261_6c697a61_74696f6e_2c496e20_74686520_61726561_206f6620_496f5420_28496e74_65726e65;
block3 = 512'h74206f66_20546869_6e677329_2c206d6f_72652061_6e64206d_6f726562_6f6f6d2c_20697420_68617320_6265656e_20612075_6e697665_7273616c_20636f6e_73656e73;
block4 = 512'h75732074_68617420_64617461_20697320_74697320_61206e65_77207465_63686e6f_6c6f6779_20746861_7420696e_74656772_61746573_20646563_656e7472_616c697a;
block5 = 512'h6174696f_6e2c496e_20746865_20617265_61206f66_20496f54_2028496e_7465726e_6574206f_66205468_696e6773_292c206d_6f726520_616e6420_6d6f7265_626f6f6d;
block6 = 512'h2c206974_20686173_20626565_6e206120_756e6976_65727361_6c20636f_6e73656e_73757320_74686174_20646174_61206973_20746973_2061206e_65772074_6563686e;
block7 = 512'h6f6c6f67_79207468_61742069_6e746567_72617465_73206465_63656e74_72616c69_7a617469_6f6e2c49_6e207468_65206172_6561206f_6620496f_54202849_6e746572;
block8 = 512'h6e657420_6f662054_68696e67_73292c20_6d6f7265_20616e64_206d6f72_65800000_00000000_00000000_00000000_00000000_00000000_00000000_00000000_000010e8;
expected = 256'h7758a30bbdfc9cd92b284b05e9be9ca3d269d3d149e7e82ab4a9ed5e81fbcf9d;
$display("Running test for 9 block issue.");
tc_ctr = tc_ctr + 1;
tb_block = block0;
tb_init = 1;
#(CLK_PERIOD);
tb_init = 0;
wait_ready();
tb_block = block1;
tb_next = 1;
#(CLK_PERIOD);
tb_next = 0;
wait_ready();
tb_block = block2;
tb_next = 1;
#(CLK_PERIOD);
tb_next = 0;
wait_ready();
tb_block = block3;
tb_next = 1;
#(CLK_PERIOD);
tb_next = 0;
wait_ready();
tb_block = block4;
tb_next = 1;
#(CLK_PERIOD);
tb_next = 0;
wait_ready();
tb_block = block5;
tb_next = 1;
#(CLK_PERIOD);
tb_next = 0;
wait_ready();
tb_block = block6;
tb_next = 1;
#(CLK_PERIOD);
tb_next = 0;
wait_ready();
tb_block = block7;
tb_next = 1;
#(CLK_PERIOD);
tb_next = 0;
wait_ready();
tb_block = block8;
tb_next = 1;
#(CLK_PERIOD);
tb_next = 0;
wait_ready();
if (tb_digest == expected)
begin
$display("Digest ok.");
end
else
begin
error_ctr = error_ctr + 1;
$display("Error! Got: 0x%064x", tb_digest);
$display("Error! Expected: 0x%064x", expected);
end
end
endtask // issue_test
//----------------------------------------------------------------
// sha256_core_test
// Test cases taken from:
// http://csrc.nist.gov/groups/ST/toolkit/documents/Examples/SHA256.pdf
//----------------------------------------------------------------
task sha256_core_test;
reg [511 : 0] tc1;
reg [255 : 0] res1;
reg [511 : 0] tc2_1;
reg [255 : 0] res2_1;
reg [511 : 0] tc2_2;
reg [255 : 0] res2_2;
begin : sha256_core_test
// TC1: Single block message: "abc".
tc1 = 512'h61626380000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018;
res1 = 256'hBA7816BF8F01CFEA414140DE5DAE2223B00361A396177A9CB410FF61F20015AD;
//single_block_test(1, tc1, res1);
// TC2: Double block message.
// "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq"
tc2_1 = 512'h6162636462636465636465666465666765666768666768696768696A68696A6B696A6B6C6A6B6C6D6B6C6D6E6C6D6E6F6D6E6F706E6F70718000000000000000;
res2_1 = 256'h85E655D6417A17953363376A624CDE5C76E09589CAC5F811CC4B32C1F20E533A;
tc2_2 = 512'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001C0;
res2_2 = 256'h248D6A61D20638B8E5C026930C3E6039A33CE45964FF2167F6ECEDD419DB06C1;
//double_block_test(2, tc2_1, res2_1, tc2_2, res2_2);
single_block_test(1, tc1, res1);
//issue_test();
end
endtask // sha256_core_test
//----------------------------------------------------------------
// main()
//----------------------------------------------------------------
initial
begin : main
$display(" -- Testbench for sha256_axi4 started --");
init_sim();
//dump_dut_state();
reset_dut();
//dump_dut_state();
sha256_core_test();
//issue_test();
display_test_result();
$display("*** Simulation done.");
$finish;
end // main
endmodule // tb_sha256_axi4
//======================================================================
// EOF tb_sha256_axi4.v
//======================================================================
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t;
real n0; initial n0 = 0.0;
real n1; initial n1 = 1.0;
real n2; initial n2 = 0.1;
real n3; initial n3 = 1.2345e-15;
real n4; initial n4 = 2.579e+15;
reg [7:0] r8; initial r8 = 3;
initial begin
// Display formatting
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n0,n0,n0,n0);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n0,n0,n0,n0);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n0,n0,n0,n0);
$display;
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n1,n1,n1,n1);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n1,n1,n1,n1);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n1,n1,n1,n1);
$display;
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n2,n2,n2,n2);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n2,n2,n2,n2);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n2,n2,n2,n2);
$display;
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n3,n3,n3,n3);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n3,n3,n3,n3);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n3,n3,n3,n3);
$display;
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n4,n4,n4,n4);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n4,n4,n4,n4);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n4,n4,n4,n4);
$display;
$display("r8=%d n1=%g n2=%g", r8, n1, n2);
$display("n1=%g n2=%g r8=%d", n1, n2, r8);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2017 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** * Int31 numbers defines indeed a cyclic structure : Z/(2^31)Z *)
(**
Author: Arnaud Spiwack (+ Pierre Letouzey)
*)
Require Import List.
Require Import Min.
Require Export Int31.
Require Import Znumtheory.
Require Import Zgcd_alt.
Require Import Zpow_facts.
Require Import CyclicAxioms.
Require Import ROmega.
Declare ML Module "int31_syntax_plugin".
Local Open Scope nat_scope.
Local Open Scope int31_scope.
Local Hint Resolve Z.lt_gt Z.div_pos : zarith.
Section Basics.
(** * Basic results about [iszero], [shiftl], [shiftr] *)
Lemma iszero_eq0 : forall x, iszero x = true -> x=0.
Proof.
destruct x; simpl; intros.
repeat
match goal with H:(if ?d then _ else _) = true |- _ =>
destruct d; try discriminate
end.
reflexivity.
Qed.
Lemma iszero_not_eq0 : forall x, iszero x = false -> x<>0.
Proof.
intros x H Eq; rewrite Eq in H; simpl in *; discriminate.
Qed.
Lemma sneakl_shiftr : forall x,
x = sneakl (firstr x) (shiftr x).
Proof.
destruct x; simpl; auto.
Qed.
Lemma sneakr_shiftl : forall x,
x = sneakr (firstl x) (shiftl x).
Proof.
destruct x; simpl; auto.
Qed.
Lemma twice_zero : forall x,
twice x = 0 <-> twice_plus_one x = 1.
Proof.
destruct x; simpl in *; split;
intro H; injection H; intros; subst; auto.
Qed.
Lemma twice_or_twice_plus_one : forall x,
x = twice (shiftr x) \/ x = twice_plus_one (shiftr x).
Proof.
intros; case_eq (firstr x); intros.
destruct x; simpl in *; rewrite H; auto.
destruct x; simpl in *; rewrite H; auto.
Qed.
(** * Iterated shift to the right *)
Definition nshiftr x := nat_rect _ x (fun _ => shiftr).
Lemma nshiftr_S :
forall n x, nshiftr x (S n) = shiftr (nshiftr x n).
Proof.
reflexivity.
Qed.
Lemma nshiftr_S_tail :
forall n x, nshiftr x (S n) = nshiftr (shiftr x) n.
Proof.
intros n; elim n; simpl; auto.
intros; now f_equal.
Qed.
Lemma nshiftr_n_0 : forall n, nshiftr 0 n = 0.
Proof.
induction n; simpl; auto.
rewrite IHn; auto.
Qed.
Lemma nshiftr_size : forall x, nshiftr x size = 0.
Proof.
destruct x; simpl; auto.
Qed.
Lemma nshiftr_above_size : forall k x, size<=k ->
nshiftr x k = 0.
Proof.
intros.
replace k with ((k-size)+size)%nat by omega.
induction (k-size)%nat; auto.
rewrite nshiftr_size; auto.
simpl; rewrite IHn; auto.
Qed.
(** * Iterated shift to the left *)
Definition nshiftl x := nat_rect _ x (fun _ => shiftl).
Lemma nshiftl_S :
forall n x, nshiftl x (S n) = shiftl (nshiftl x n).
Proof.
reflexivity.
Qed.
Lemma nshiftl_S_tail :
forall n x, nshiftl x (S n) = nshiftl (shiftl x) n.
Proof.
intros n; elim n; simpl; intros; now f_equal.
Qed.
Lemma nshiftl_n_0 : forall n, nshiftl 0 n = 0.
Proof.
induction n; simpl; auto.
rewrite IHn; auto.
Qed.
Lemma nshiftl_size : forall x, nshiftl x size = 0.
Proof.
destruct x; simpl; auto.
Qed.
Lemma nshiftl_above_size : forall k x, size<=k ->
nshiftl x k = 0.
Proof.
intros.
replace k with ((k-size)+size)%nat by omega.
induction (k-size)%nat; auto.
rewrite nshiftl_size; auto.
simpl; rewrite IHn; auto.
Qed.
Lemma firstr_firstl :
forall x, firstr x = firstl (nshiftl x (pred size)).
Proof.
destruct x; simpl; auto.
Qed.
Lemma firstl_firstr :
forall x, firstl x = firstr (nshiftr x (pred size)).
Proof.
destruct x; simpl; auto.
Qed.
(** More advanced results about [nshiftr] *)
Lemma nshiftr_predsize_0_firstl : forall x,
nshiftr x (pred size) = 0 -> firstl x = D0.
Proof.
destruct x; compute; intros H; injection H; intros; subst; auto.
Qed.
Lemma nshiftr_0_propagates : forall n p x, n <= p ->
nshiftr x n = 0 -> nshiftr x p = 0.
Proof.
intros.
replace p with ((p-n)+n)%nat by omega.
induction (p-n)%nat.
simpl; auto.
simpl; rewrite IHn0; auto.
Qed.
Lemma nshiftr_0_firstl : forall n x, n < size ->
nshiftr x n = 0 -> firstl x = D0.
Proof.
intros.
apply nshiftr_predsize_0_firstl.
apply nshiftr_0_propagates with n; auto; omega.
Qed.
(** * Some induction principles over [int31] *)
(** Not used for the moment. Are they really useful ? *)
Lemma int31_ind_sneakl : forall P : int31->Prop,
P 0 ->
(forall x d, P x -> P (sneakl d x)) ->
forall x, P x.
Proof.
intros.
assert (forall n, n<=size -> P (nshiftr x (size - n))).
induction n; intros.
rewrite nshiftr_size; auto.
rewrite sneakl_shiftr.
apply H0.
change (P (nshiftr x (S (size - S n)))).
replace (S (size - S n))%nat with (size - n)%nat by omega.
apply IHn; omega.
change x with (nshiftr x (size-size)); auto.
Qed.
Lemma int31_ind_twice : forall P : int31->Prop,
P 0 ->
(forall x, P x -> P (twice x)) ->
(forall x, P x -> P (twice_plus_one x)) ->
forall x, P x.
Proof.
induction x using int31_ind_sneakl; auto.
destruct d; auto.
Qed.
(** * Some generic results about [recr] *)
Section Recr.
(** [recr] satisfies the fixpoint equation used for its definition. *)
Variable (A:Type)(case0:A)(caserec:digits->int31->A->A).
Lemma recr_aux_eqn : forall n x, iszero x = false ->
recr_aux (S n) A case0 caserec x =
caserec (firstr x) (shiftr x) (recr_aux n A case0 caserec (shiftr x)).
Proof.
intros; simpl; rewrite H; auto.
Qed.
Lemma recr_aux_converges :
forall n p x, n <= size -> n <= p ->
recr_aux n A case0 caserec (nshiftr x (size - n)) =
recr_aux p A case0 caserec (nshiftr x (size - n)).
Proof.
induction n.
simpl minus; intros.
rewrite nshiftr_size; destruct p; simpl; auto.
intros.
destruct p.
inversion H0.
unfold recr_aux; fold recr_aux.
destruct (iszero (nshiftr x (size - S n))); auto.
f_equal.
change (shiftr (nshiftr x (size - S n))) with (nshiftr x (S (size - S n))).
replace (S (size - S n))%nat with (size - n)%nat by omega.
apply IHn; auto with arith.
Qed.
Lemma recr_eqn : forall x, iszero x = false ->
recr A case0 caserec x =
caserec (firstr x) (shiftr x) (recr A case0 caserec (shiftr x)).
Proof.
intros.
unfold recr.
change x with (nshiftr x (size - size)).
rewrite (recr_aux_converges size (S size)); auto with arith.
rewrite recr_aux_eqn; auto.
Qed.
(** [recr] is usually equivalent to a variant [recrbis]
written without [iszero] check. *)
Fixpoint recrbis_aux (n:nat)(A:Type)(case0:A)(caserec:digits->int31->A->A)
(i:int31) : A :=
match n with
| O => case0
| S next =>
let si := shiftr i in
caserec (firstr i) si (recrbis_aux next A case0 caserec si)
end.
Definition recrbis := recrbis_aux size.
Hypothesis case0_caserec : caserec D0 0 case0 = case0.
Lemma recrbis_aux_equiv : forall n x,
recrbis_aux n A case0 caserec x = recr_aux n A case0 caserec x.
Proof.
induction n; simpl; auto; intros.
case_eq (iszero x); intros; [ | f_equal; auto ].
rewrite (iszero_eq0 _ H); simpl; auto.
replace (recrbis_aux n A case0 caserec 0) with case0; auto.
clear H IHn; induction n; simpl; congruence.
Qed.
Lemma recrbis_equiv : forall x,
recrbis A case0 caserec x = recr A case0 caserec x.
Proof.
intros; apply recrbis_aux_equiv; auto.
Qed.
End Recr.
(** * Incrementation *)
Section Incr.
(** Variant of [incr] via [recrbis] *)
Let Incr (b : digits) (si rec : int31) :=
match b with
| D0 => sneakl D1 si
| D1 => sneakl D0 rec
end.
Definition incrbis_aux n x := recrbis_aux n _ In Incr x.
Lemma incrbis_aux_equiv : forall x, incrbis_aux size x = incr x.
Proof.
unfold incr, recr, incrbis_aux; fold Incr; intros.
apply recrbis_aux_equiv; auto.
Qed.
(** Recursive equations satisfied by [incr] *)
Lemma incr_eqn1 :
forall x, firstr x = D0 -> incr x = twice_plus_one (shiftr x).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0); simpl; auto.
unfold incr; rewrite recr_eqn; fold incr; auto.
rewrite H; auto.
Qed.
Lemma incr_eqn2 :
forall x, firstr x = D1 -> incr x = twice (incr (shiftr x)).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0) in H; simpl in H; discriminate.
unfold incr; rewrite recr_eqn; fold incr; auto.
rewrite H; auto.
Qed.
Lemma incr_twice : forall x, incr (twice x) = twice_plus_one x.
Proof.
intros.
rewrite incr_eqn1; destruct x; simpl; auto.
Qed.
Lemma incr_twice_plus_one_firstl :
forall x, firstl x = D0 -> incr (twice_plus_one x) = twice (incr x).
Proof.
intros.
rewrite incr_eqn2; [ | destruct x; simpl; auto ].
f_equal; f_equal.
destruct x; simpl in *; rewrite H; auto.
Qed.
(** The previous result is actually true even without the
constraint on [firstl], but this is harder to prove
(see later). *)
End Incr.
(** * Conversion to [Z] : the [phi] function *)
Section Phi.
(** Variant of [phi] via [recrbis] *)
Let Phi := fun b (_:int31) =>
match b with D0 => Z.double | D1 => Z.succ_double end.
Definition phibis_aux n x := recrbis_aux n _ Z0 Phi x.
Lemma phibis_aux_equiv : forall x, phibis_aux size x = phi x.
Proof.
unfold phi, recr, phibis_aux; fold Phi; intros.
apply recrbis_aux_equiv; auto.
Qed.
(** Recursive equations satisfied by [phi] *)
Lemma phi_eqn1 : forall x, firstr x = D0 ->
phi x = Z.double (phi (shiftr x)).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0); simpl; auto.
intros; unfold phi; rewrite recr_eqn; fold phi; auto.
rewrite H; auto.
Qed.
Lemma phi_eqn2 : forall x, firstr x = D1 ->
phi x = Z.succ_double (phi (shiftr x)).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0) in H; simpl in H; discriminate.
intros; unfold phi; rewrite recr_eqn; fold phi; auto.
rewrite H; auto.
Qed.
Lemma phi_twice_firstl : forall x, firstl x = D0 ->
phi (twice x) = Z.double (phi x).
Proof.
intros.
rewrite phi_eqn1; auto; [ | destruct x; auto ].
f_equal; f_equal.
destruct x; simpl in *; rewrite H; auto.
Qed.
Lemma phi_twice_plus_one_firstl : forall x, firstl x = D0 ->
phi (twice_plus_one x) = Z.succ_double (phi x).
Proof.
intros.
rewrite phi_eqn2; auto; [ | destruct x; auto ].
f_equal; f_equal.
destruct x; simpl in *; rewrite H; auto.
Qed.
End Phi.
(** [phi x] is positive and lower than [2^31] *)
Lemma phibis_aux_pos : forall n x, (0 <= phibis_aux n x)%Z.
Proof.
induction n.
simpl; unfold phibis_aux; simpl; auto with zarith.
intros.
unfold phibis_aux, recrbis_aux; fold recrbis_aux;
fold (phibis_aux n (shiftr x)).
destruct (firstr x).
specialize IHn with (shiftr x); rewrite Z.double_spec; omega.
specialize IHn with (shiftr x); rewrite Z.succ_double_spec; omega.
Qed.
Lemma phibis_aux_bounded :
forall n x, n <= size ->
(phibis_aux n (nshiftr x (size-n)) < 2 ^ (Z.of_nat n))%Z.
Proof.
induction n.
simpl minus; unfold phibis_aux; simpl; auto with zarith.
intros.
unfold phibis_aux, recrbis_aux; fold recrbis_aux;
fold (phibis_aux n (shiftr (nshiftr x (size - S n)))).
assert (shiftr (nshiftr x (size - S n)) = nshiftr x (size-n)).
replace (size - n)%nat with (S (size - (S n))) by omega.
simpl; auto.
rewrite H0.
assert (H1 : n <= size) by omega.
specialize (IHn x H1).
set (y:=phibis_aux n (nshiftr x (size - n))) in *.
rewrite Nat2Z.inj_succ, Z.pow_succ_r; auto with zarith.
case_eq (firstr (nshiftr x (size - S n))); intros.
rewrite Z.double_spec; auto with zarith.
rewrite Z.succ_double_spec; auto with zarith.
Qed.
Lemma phi_nonneg : forall x, (0 <= phi x)%Z.
Proof.
intros.
rewrite <- phibis_aux_equiv.
apply phibis_aux_pos.
Qed.
Hint Resolve phi_nonneg : zarith.
Lemma phi_bounded : forall x, (0 <= phi x < 2 ^ (Z.of_nat size))%Z.
Proof.
intros. split; [auto with zarith|].
rewrite <- phibis_aux_equiv.
change x with (nshiftr x (size-size)).
apply phibis_aux_bounded; auto.
Qed.
Lemma phibis_aux_lowerbound :
forall n x, firstr (nshiftr x n) = D1 ->
(2 ^ Z.of_nat n <= phibis_aux (S n) x)%Z.
Proof.
induction n.
intros.
unfold nshiftr in H; simpl in *.
unfold phibis_aux, recrbis_aux.
rewrite H, Z.succ_double_spec; omega.
intros.
remember (S n) as m.
unfold phibis_aux, recrbis_aux; fold recrbis_aux;
fold (phibis_aux m (shiftr x)).
subst m.
rewrite Nat2Z.inj_succ, Z.pow_succ_r; auto with zarith.
assert (2^(Z.of_nat n) <= phibis_aux (S n) (shiftr x))%Z.
apply IHn.
rewrite <- nshiftr_S_tail; auto.
destruct (firstr x).
change (Z.double (phibis_aux (S n) (shiftr x))) with
(2*(phibis_aux (S n) (shiftr x)))%Z.
omega.
rewrite Z.succ_double_spec; omega.
Qed.
Lemma phi_lowerbound :
forall x, firstl x = D1 -> (2^(Z.of_nat (pred size)) <= phi x)%Z.
Proof.
intros.
generalize (phibis_aux_lowerbound (pred size) x).
rewrite <- firstl_firstr.
change (S (pred size)) with size; auto.
rewrite phibis_aux_equiv; auto.
Qed.
(** * Equivalence modulo [2^n] *)
Section EqShiftL.
(** After killing [n] bits at the left, are the numbers equal ?*)
Definition EqShiftL n x y :=
nshiftl x n = nshiftl y n.
Lemma EqShiftL_zero : forall x y, EqShiftL O x y <-> x = y.
Proof.
unfold EqShiftL; intros; unfold nshiftl; simpl; split; auto.
Qed.
Lemma EqShiftL_size : forall k x y, size<=k -> EqShiftL k x y.
Proof.
red; intros; rewrite 2 nshiftl_above_size; auto.
Qed.
Lemma EqShiftL_le : forall k k' x y, k <= k' ->
EqShiftL k x y -> EqShiftL k' x y.
Proof.
unfold EqShiftL; intros.
replace k' with ((k'-k)+k)%nat by omega.
remember (k'-k)%nat as n.
clear Heqn H k'.
induction n; simpl; auto.
f_equal; auto.
Qed.
Lemma EqShiftL_firstr : forall k x y, k < size ->
EqShiftL k x y -> firstr x = firstr y.
Proof.
intros.
rewrite 2 firstr_firstl.
f_equal.
apply EqShiftL_le with k; auto.
unfold size.
auto with arith.
Qed.
Lemma EqShiftL_twice : forall k x y,
EqShiftL k (twice x) (twice y) <-> EqShiftL (S k) x y.
Proof.
intros; unfold EqShiftL.
rewrite 2 nshiftl_S_tail; split; auto.
Qed.
(** * From int31 to list of digits. *)
(** Lower (=rightmost) bits comes first. *)
Definition i2l := recrbis _ nil (fun d _ rec => d::rec).
Lemma i2l_length : forall x, length (i2l x) = size.
Proof.
intros; reflexivity.
Qed.
Fixpoint lshiftl l x :=
match l with
| nil => x
| d::l => sneakl d (lshiftl l x)
end.
Definition l2i l := lshiftl l On.
Lemma l2i_i2l : forall x, l2i (i2l x) = x.
Proof.
destruct x; compute; auto.
Qed.
Lemma i2l_sneakr : forall x d,
i2l (sneakr d x) = tail (i2l x) ++ d::nil.
Proof.
destruct x; compute; auto.
Qed.
Lemma i2l_sneakl : forall x d,
i2l (sneakl d x) = d :: removelast (i2l x).
Proof.
destruct x; compute; auto.
Qed.
Lemma i2l_l2i : forall l, length l = size ->
i2l (l2i l) = l.
Proof.
repeat (destruct l as [ |? l]; [intros; discriminate | ]).
destruct l; [ | intros; discriminate].
intros _; compute; auto.
Qed.
Fixpoint cstlist (A:Type)(a:A) n :=
match n with
| O => nil
| S n => a::cstlist _ a n
end.
Lemma i2l_nshiftl : forall n x, n<=size ->
i2l (nshiftl x n) = cstlist _ D0 n ++ firstn (size-n) (i2l x).
Proof.
induction n.
intros.
assert (firstn (size-0) (i2l x) = i2l x).
rewrite <- minus_n_O, <- (i2l_length x).
induction (i2l x); simpl; f_equal; auto.
rewrite H0; clear H0.
reflexivity.
intros.
rewrite nshiftl_S.
unfold shiftl; rewrite i2l_sneakl.
simpl cstlist.
rewrite <- app_comm_cons; f_equal.
rewrite IHn; [ | omega].
rewrite removelast_app.
apply f_equal.
replace (size-n)%nat with (S (size - S n))%nat by omega.
rewrite removelast_firstn; auto.
rewrite i2l_length; omega.
generalize (firstn_length (size-n) (i2l x)).
rewrite i2l_length.
intros H0 H1. rewrite H1 in H0.
rewrite min_l in H0 by omega.
simpl length in H0.
omega.
Qed.
(** [i2l] can be used to define a relation equivalent to [EqShiftL] *)
Lemma EqShiftL_i2l : forall k x y,
EqShiftL k x y <-> firstn (size-k) (i2l x) = firstn (size-k) (i2l y).
Proof.
intros.
destruct (le_lt_dec size k) as [Hle|Hlt].
split; intros.
replace (size-k)%nat with O by omega.
unfold firstn; auto.
apply EqShiftL_size; auto.
unfold EqShiftL.
assert (k <= size) by omega.
split; intros.
assert (i2l (nshiftl x k) = i2l (nshiftl y k)) by (f_equal; auto).
rewrite 2 i2l_nshiftl in H1; auto.
eapply app_inv_head; eauto.
assert (i2l (nshiftl x k) = i2l (nshiftl y k)).
rewrite 2 i2l_nshiftl; auto.
f_equal; auto.
rewrite <- (l2i_i2l (nshiftl x k)), <- (l2i_i2l (nshiftl y k)).
f_equal; auto.
Qed.
(** This equivalence allows proving easily the following delicate
result *)
Lemma EqShiftL_twice_plus_one : forall k x y,
EqShiftL k (twice_plus_one x) (twice_plus_one y) <-> EqShiftL (S k) x y.
Proof.
intros.
destruct (le_lt_dec size k) as [Hle|Hlt].
split; intros; apply EqShiftL_size; auto.
rewrite 2 EqShiftL_i2l.
unfold twice_plus_one.
rewrite 2 i2l_sneakl.
replace (size-k)%nat with (S (size - S k))%nat by omega.
remember (size - S k)%nat as n.
remember (i2l x) as lx.
remember (i2l y) as ly.
simpl.
rewrite 2 firstn_removelast.
split; intros.
injection H; auto.
f_equal; auto.
subst ly n; rewrite i2l_length; omega.
subst lx n; rewrite i2l_length; omega.
Qed.
Lemma EqShiftL_shiftr : forall k x y, EqShiftL k x y ->
EqShiftL (S k) (shiftr x) (shiftr y).
Proof.
intros.
destruct (le_lt_dec size (S k)) as [Hle|Hlt].
apply EqShiftL_size; auto.
case_eq (firstr x); intros.
rewrite <- EqShiftL_twice.
unfold twice; rewrite <- H0.
rewrite <- sneakl_shiftr.
rewrite (EqShiftL_firstr k x y); auto.
rewrite <- sneakl_shiftr; auto.
omega.
rewrite <- EqShiftL_twice_plus_one.
unfold twice_plus_one; rewrite <- H0.
rewrite <- sneakl_shiftr.
rewrite (EqShiftL_firstr k x y); auto.
rewrite <- sneakl_shiftr; auto.
omega.
Qed.
Lemma EqShiftL_incrbis : forall n k x y, n<=size ->
(n+k=S size)%nat ->
EqShiftL k x y ->
EqShiftL k (incrbis_aux n x) (incrbis_aux n y).
Proof.
induction n; simpl; intros.
red; auto.
destruct (eq_nat_dec k size).
subst k; apply EqShiftL_size; auto.
unfold incrbis_aux; simpl;
fold (incrbis_aux n (shiftr x)); fold (incrbis_aux n (shiftr y)).
rewrite (EqShiftL_firstr k x y); auto; try omega.
case_eq (firstr y); intros.
rewrite EqShiftL_twice_plus_one.
apply EqShiftL_shiftr; auto.
rewrite EqShiftL_twice.
apply IHn; try omega.
apply EqShiftL_shiftr; auto.
Qed.
Lemma EqShiftL_incr : forall x y,
EqShiftL 1 x y -> EqShiftL 1 (incr x) (incr y).
Proof.
intros.
rewrite <- 2 incrbis_aux_equiv.
apply EqShiftL_incrbis; auto.
Qed.
End EqShiftL.
(** * More equations about [incr] *)
Lemma incr_twice_plus_one :
forall x, incr (twice_plus_one x) = twice (incr x).
Proof.
intros.
rewrite incr_eqn2; [ | destruct x; simpl; auto].
apply EqShiftL_incr.
red; destruct x; simpl; auto.
Qed.
Lemma incr_firstr : forall x, firstr (incr x) <> firstr x.
Proof.
intros.
case_eq (firstr x); intros.
rewrite incr_eqn1; auto.
destruct (shiftr x); simpl; discriminate.
rewrite incr_eqn2; auto.
destruct (incr (shiftr x)); simpl; discriminate.
Qed.
Lemma incr_inv : forall x y,
incr x = twice_plus_one y -> x = twice y.
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0) in *; simpl in *.
change (incr 0) with 1 in H.
symmetry; rewrite twice_zero; auto.
case_eq (firstr x); intros.
rewrite incr_eqn1 in H; auto.
clear H0; destruct x; destruct y; simpl in *.
injection H; intros; subst; auto.
elim (incr_firstr x).
rewrite H1, H; destruct y; simpl; auto.
Qed.
(** * Conversion from [Z] : the [phi_inv] function *)
(** First, recursive equations *)
Lemma phi_inv_double_plus_one : forall z,
phi_inv (Z.succ_double z) = twice_plus_one (phi_inv z).
Proof.
destruct z; simpl; auto.
induction p; simpl.
rewrite 2 incr_twice; auto.
rewrite incr_twice, incr_twice_plus_one.
f_equal.
apply incr_inv; auto.
auto.
Qed.
Lemma phi_inv_double : forall z,
phi_inv (Z.double z) = twice (phi_inv z).
Proof.
destruct z; simpl; auto.
rewrite incr_twice_plus_one; auto.
Qed.
Lemma phi_inv_incr : forall z,
phi_inv (Z.succ z) = incr (phi_inv z).
Proof.
destruct z.
simpl; auto.
simpl; auto.
induction p; simpl; auto.
rewrite <- Pos.add_1_r, IHp, incr_twice_plus_one; auto.
rewrite incr_twice; auto.
simpl; auto.
destruct p; simpl; auto.
rewrite incr_twice; auto.
f_equal.
rewrite incr_twice_plus_one; auto.
induction p; simpl; auto.
rewrite incr_twice; auto.
f_equal.
rewrite incr_twice_plus_one; auto.
Qed.
(** [phi_inv o inv], the always-exact and easy-to-prove trip :
from int31 to Z and then back to int31. *)
Lemma phi_inv_phi_aux :
forall n x, n <= size ->
phi_inv (phibis_aux n (nshiftr x (size-n))) =
nshiftr x (size-n).
Proof.
induction n.
intros; simpl minus.
rewrite nshiftr_size; auto.
intros.
unfold phibis_aux, recrbis_aux; fold recrbis_aux;
fold (phibis_aux n (shiftr (nshiftr x (size-S n)))).
assert (shiftr (nshiftr x (size - S n)) = nshiftr x (size-n)).
replace (size - n)%nat with (S (size - (S n))); auto; omega.
rewrite H0.
case_eq (firstr (nshiftr x (size - S n))); intros.
rewrite phi_inv_double.
rewrite IHn by omega.
rewrite <- H0.
remember (nshiftr x (size - S n)) as y.
destruct y; simpl in H1; rewrite H1; auto.
rewrite phi_inv_double_plus_one.
rewrite IHn by omega.
rewrite <- H0.
remember (nshiftr x (size - S n)) as y.
destruct y; simpl in H1; rewrite H1; auto.
Qed.
Lemma phi_inv_phi : forall x, phi_inv (phi x) = x.
Proof.
intros.
rewrite <- phibis_aux_equiv.
replace x with (nshiftr x (size - size)) by auto.
apply phi_inv_phi_aux; auto.
Qed.
(** The other composition [phi o phi_inv] is harder to prove correct.
In particular, an overflow can happen, so a modulo is needed.
For the moment, we proceed via several steps, the first one
being a detour to [positive_to_in31]. *)
(** * [positive_to_int31] *)
(** A variant of [p2i] with [twice] and [twice_plus_one] instead of
[2*i] and [2*i+1] *)
Fixpoint p2ibis n p : (N*int31)%type :=
match n with
| O => (Npos p, On)
| S n => match p with
| xO p => let (r,i) := p2ibis n p in (r, twice i)
| xI p => let (r,i) := p2ibis n p in (r, twice_plus_one i)
| xH => (N0, In)
end
end.
Lemma p2ibis_bounded : forall n p,
nshiftr (snd (p2ibis n p)) n = 0.
Proof.
induction n.
simpl; intros; auto.
simpl p2ibis; intros.
destruct p; simpl snd.
specialize IHn with p.
destruct (p2ibis n p). simpl @snd in *.
rewrite nshiftr_S_tail.
destruct (le_lt_dec size n) as [Hle|Hlt].
rewrite nshiftr_above_size; auto.
assert (H:=nshiftr_0_firstl _ _ Hlt IHn).
replace (shiftr (twice_plus_one i)) with i; auto.
destruct i; simpl in *. rewrite H; auto.
specialize IHn with p.
destruct (p2ibis n p); simpl @snd in *.
rewrite nshiftr_S_tail.
destruct (le_lt_dec size n) as [Hle|Hlt].
rewrite nshiftr_above_size; auto.
assert (H:=nshiftr_0_firstl _ _ Hlt IHn).
replace (shiftr (twice i)) with i; auto.
destruct i; simpl in *; rewrite H; auto.
rewrite nshiftr_S_tail; auto.
replace (shiftr In) with 0; auto.
apply nshiftr_n_0.
Qed.
Local Open Scope Z_scope.
Lemma p2ibis_spec : forall n p, (n<=size)%nat ->
Zpos p = (Z.of_N (fst (p2ibis n p)))*2^(Z.of_nat n) +
phi (snd (p2ibis n p)).
Proof.
induction n; intros.
simpl; rewrite Pos.mul_1_r; auto.
replace (2^(Z.of_nat (S n)))%Z with (2*2^(Z.of_nat n))%Z by
(rewrite <- Z.pow_succ_r, <- Zpos_P_of_succ_nat;
auto with zarith).
rewrite (Z.mul_comm 2).
assert (n<=size)%nat by omega.
destruct p; simpl; [ | | auto];
specialize (IHn p H0);
generalize (p2ibis_bounded n p);
destruct (p2ibis n p) as (r,i); simpl in *; intros.
change (Zpos p~1) with (2*Zpos p + 1)%Z.
rewrite phi_twice_plus_one_firstl, Z.succ_double_spec.
rewrite IHn; ring.
apply (nshiftr_0_firstl n); auto; try omega.
change (Zpos p~0) with (2*Zpos p)%Z.
rewrite phi_twice_firstl.
change (Z.double (phi i)) with (2*(phi i))%Z.
rewrite IHn; ring.
apply (nshiftr_0_firstl n); auto; try omega.
Qed.
(** We now prove that this [p2ibis] is related to [phi_inv_positive] *)
Lemma phi_inv_positive_p2ibis : forall n p, (n<=size)%nat ->
EqShiftL (size-n) (phi_inv_positive p) (snd (p2ibis n p)).
Proof.
induction n.
intros.
apply EqShiftL_size; auto.
intros.
simpl p2ibis; destruct p; [ | | red; auto];
specialize IHn with p;
destruct (p2ibis n p); simpl @snd in *; simpl phi_inv_positive;
rewrite ?EqShiftL_twice_plus_one, ?EqShiftL_twice;
replace (S (size - S n))%nat with (size - n)%nat by omega;
apply IHn; omega.
Qed.
(** This gives the expected result about [phi o phi_inv], at least
for the positive case. *)
Lemma phi_phi_inv_positive : forall p,
phi (phi_inv_positive p) = (Zpos p) mod (2^(Z.of_nat size)).
Proof.
intros.
replace (phi_inv_positive p) with (snd (p2ibis size p)).
rewrite (p2ibis_spec size p) by auto.
rewrite Z.add_comm, Z_mod_plus.
symmetry; apply Zmod_small.
apply phi_bounded.
auto with zarith.
symmetry.
rewrite <- EqShiftL_zero.
apply (phi_inv_positive_p2ibis size p); auto.
Qed.
(** Moreover, [p2ibis] is also related with [p2i] and hence with
[positive_to_int31]. *)
Lemma double_twice_firstl : forall x, firstl x = D0 ->
(Twon*x = twice x)%int31.
Proof.
intros.
unfold mul31.
rewrite <- Z.double_spec, <- phi_twice_firstl, phi_inv_phi; auto.
Qed.
Lemma double_twice_plus_one_firstl : forall x, firstl x = D0 ->
(Twon*x+In = twice_plus_one x)%int31.
Proof.
intros.
rewrite double_twice_firstl; auto.
unfold add31.
rewrite phi_twice_firstl, <- Z.succ_double_spec,
<- phi_twice_plus_one_firstl, phi_inv_phi; auto.
Qed.
Lemma p2i_p2ibis : forall n p, (n<=size)%nat ->
p2i n p = p2ibis n p.
Proof.
induction n; simpl; auto; intros.
destruct p; auto; specialize IHn with p;
generalize (p2ibis_bounded n p);
rewrite IHn; try omega; destruct (p2ibis n p); simpl; intros;
f_equal; auto.
apply double_twice_plus_one_firstl.
apply (nshiftr_0_firstl n); auto; omega.
apply double_twice_firstl.
apply (nshiftr_0_firstl n); auto; omega.
Qed.
Lemma positive_to_int31_phi_inv_positive : forall p,
snd (positive_to_int31 p) = phi_inv_positive p.
Proof.
intros; unfold positive_to_int31.
rewrite p2i_p2ibis; auto.
symmetry.
rewrite <- EqShiftL_zero.
apply (phi_inv_positive_p2ibis size); auto.
Qed.
Lemma positive_to_int31_spec : forall p,
Zpos p = (Z.of_N (fst (positive_to_int31 p)))*2^(Z.of_nat size) +
phi (snd (positive_to_int31 p)).
Proof.
unfold positive_to_int31.
intros; rewrite p2i_p2ibis; auto.
apply p2ibis_spec; auto.
Qed.
(** Thanks to the result about [phi o phi_inv_positive], we can
now establish easily the most general results about
[phi o twice] and so one. *)
Lemma phi_twice : forall x,
phi (twice x) = (Z.double (phi x)) mod 2^(Z.of_nat size).
Proof.
intros.
pattern x at 1; rewrite <- (phi_inv_phi x).
rewrite <- phi_inv_double.
assert (0 <= Z.double (phi x)).
rewrite Z.double_spec; generalize (phi_bounded x); omega.
destruct (Z.double (phi x)).
simpl; auto.
apply phi_phi_inv_positive.
compute in H; elim H; auto.
Qed.
Lemma phi_twice_plus_one : forall x,
phi (twice_plus_one x) = (Z.succ_double (phi x)) mod 2^(Z.of_nat size).
Proof.
intros.
pattern x at 1; rewrite <- (phi_inv_phi x).
rewrite <- phi_inv_double_plus_one.
assert (0 <= Z.succ_double (phi x)).
rewrite Z.succ_double_spec; generalize (phi_bounded x); omega.
destruct (Z.succ_double (phi x)).
simpl; auto.
apply phi_phi_inv_positive.
compute in H; elim H; auto.
Qed.
Lemma phi_incr : forall x,
phi (incr x) = (Z.succ (phi x)) mod 2^(Z.of_nat size).
Proof.
intros.
pattern x at 1; rewrite <- (phi_inv_phi x).
rewrite <- phi_inv_incr.
assert (0 <= Z.succ (phi x)).
change (Z.succ (phi x)) with ((phi x)+1)%Z;
generalize (phi_bounded x); omega.
destruct (Z.succ (phi x)).
simpl; auto.
apply phi_phi_inv_positive.
compute in H; elim H; auto.
Qed.
(** With the previous results, we can deal with [phi o phi_inv] even
in the negative case *)
Lemma phi_phi_inv_negative :
forall p, phi (incr (complement_negative p)) = (Zneg p) mod 2^(Z.of_nat size).
Proof.
induction p.
simpl complement_negative.
rewrite phi_incr in IHp.
rewrite incr_twice, phi_twice_plus_one.
remember (phi (complement_negative p)) as q.
rewrite Z.succ_double_spec.
replace (2*q+1) with (2*(Z.succ q)-1) by omega.
rewrite <- Zminus_mod_idemp_l, <- Zmult_mod_idemp_r, IHp.
rewrite Zmult_mod_idemp_r, Zminus_mod_idemp_l; auto with zarith.
simpl complement_negative.
rewrite incr_twice_plus_one, phi_twice.
remember (phi (incr (complement_negative p))) as q.
rewrite Z.double_spec, IHp, Zmult_mod_idemp_r; auto with zarith.
simpl; auto.
Qed.
Lemma phi_phi_inv :
forall z, phi (phi_inv z) = z mod 2 ^ (Z.of_nat size).
Proof.
destruct z.
simpl; auto.
apply phi_phi_inv_positive.
apply phi_phi_inv_negative.
Qed.
End Basics.
Instance int31_ops : ZnZ.Ops int31 :=
{
digits := 31%positive; (* number of digits *)
zdigits := 31; (* number of digits *)
to_Z := phi; (* conversion to Z *)
of_pos := positive_to_int31; (* positive -> N*int31 : p => N,i
where p = N*2^31+phi i *)
head0 := head031; (* number of head 0 *)
tail0 := tail031; (* number of tail 0 *)
zero := 0;
one := 1;
minus_one := Tn; (* 2^31 - 1 *)
compare := compare31;
eq0 := fun i => match i ?= 0 with Eq => true | _ => false end;
opp_c := fun i => 0 -c i;
opp := opp31;
opp_carry := fun i => 0-i-1;
succ_c := fun i => i +c 1;
add_c := add31c;
add_carry_c := add31carryc;
succ := fun i => i + 1;
add := add31;
add_carry := fun i j => i + j + 1;
pred_c := fun i => i -c 1;
sub_c := sub31c;
sub_carry_c := sub31carryc;
pred := fun i => i - 1;
sub := sub31;
sub_carry := fun i j => i - j - 1;
mul_c := mul31c;
mul := mul31;
square_c := fun x => x *c x;
div21 := div3121;
div_gt := div31; (* this is supposed to be the special case of
division a/b where a > b *)
div := div31;
modulo_gt := fun i j => let (_,r) := i/j in r;
modulo := fun i j => let (_,r) := i/j in r;
gcd_gt := gcd31;
gcd := gcd31;
add_mul_div := addmuldiv31;
pos_mod := (* modulo 2^p *)
fun p i =>
match p ?= 31 with
| Lt => addmuldiv31 p 0 (addmuldiv31 (31-p) i 0)
| _ => i
end;
is_even :=
fun i => let (_,r) := i/2 in
match r ?= 0 with Eq => true | _ => false end;
sqrt2 := sqrt312;
sqrt := sqrt31;
lor := lor31;
land := land31;
lxor := lxor31
}.
Section Int31_Specs.
Local Open Scope Z_scope.
Notation "[| x |]" := (phi x) (at level 0, x at level 99).
Local Notation wB := (2 ^ (Z.of_nat size)).
Lemma wB_pos : wB > 0.
Proof.
auto with zarith.
Qed.
Notation "[+| c |]" :=
(interp_carry 1 wB phi c) (at level 0, c at level 99).
Notation "[-| c |]" :=
(interp_carry (-1) wB phi c) (at level 0, c at level 99).
Notation "[|| x ||]" :=
(zn2z_to_Z wB phi x) (at level 0, x at level 99).
Lemma spec_zdigits : [| 31 |] = 31.
Proof.
reflexivity.
Qed.
Lemma spec_more_than_1_digit: 1 < 31.
Proof.
auto with zarith.
Qed.
Lemma spec_0 : [| 0 |] = 0.
Proof.
reflexivity.
Qed.
Lemma spec_1 : [| 1 |] = 1.
Proof.
reflexivity.
Qed.
Lemma spec_m1 : [| Tn |] = wB - 1.
Proof.
reflexivity.
Qed.
Lemma spec_compare : forall x y,
(x ?= y)%int31 = ([|x|] ?= [|y|]).
Proof. reflexivity. Qed.
(** Addition *)
Lemma spec_add_c : forall x y, [+|add31c x y|] = [|x|] + [|y|].
Proof.
intros; unfold add31c, add31, interp_carry; rewrite phi_phi_inv.
generalize (phi_bounded x)(phi_bounded y); intros.
set (X:=[|x|]) in *; set (Y:=[|y|]) in *; clearbody X Y.
assert ((X+Y) mod wB ?= X+Y <> Eq -> [+|C1 (phi_inv (X+Y))|] = X+Y).
unfold interp_carry; rewrite phi_phi_inv, Z.compare_eq_iff; intros.
destruct (Z_lt_le_dec (X+Y) wB).
contradict H1; auto using Zmod_small with zarith.
rewrite <- (Z_mod_plus_full (X+Y) (-1) wB).
rewrite Zmod_small; romega.
generalize (Z.compare_eq ((X+Y) mod wB) (X+Y)); intros Heq.
destruct Z.compare; intros;
[ rewrite phi_phi_inv; auto | now apply H1 | now apply H1].
Qed.
Lemma spec_succ_c : forall x, [+|add31c x 1|] = [|x|] + 1.
Proof.
intros; apply spec_add_c.
Qed.
Lemma spec_add_carry_c : forall x y, [+|add31carryc x y|] = [|x|] + [|y|] + 1.
Proof.
intros.
unfold add31carryc, interp_carry; rewrite phi_phi_inv.
generalize (phi_bounded x)(phi_bounded y); intros.
set (X:=[|x|]) in *; set (Y:=[|y|]) in *; clearbody X Y.
assert ((X+Y+1) mod wB ?= X+Y+1 <> Eq -> [+|C1 (phi_inv (X+Y+1))|] = X+Y+1).
unfold interp_carry; rewrite phi_phi_inv, Z.compare_eq_iff; intros.
destruct (Z_lt_le_dec (X+Y+1) wB).
contradict H1; auto using Zmod_small with zarith.
rewrite <- (Z_mod_plus_full (X+Y+1) (-1) wB).
rewrite Zmod_small; romega.
generalize (Z.compare_eq ((X+Y+1) mod wB) (X+Y+1)); intros Heq.
destruct Z.compare; intros;
[ rewrite phi_phi_inv; auto | now apply H1 | now apply H1].
Qed.
Lemma spec_add : forall x y, [|x+y|] = ([|x|] + [|y|]) mod wB.
Proof.
intros; apply phi_phi_inv.
Qed.
Lemma spec_add_carry :
forall x y, [|x+y+1|] = ([|x|] + [|y|] + 1) mod wB.
Proof.
unfold add31; intros.
repeat rewrite phi_phi_inv.
apply Zplus_mod_idemp_l.
Qed.
Lemma spec_succ : forall x, [|x+1|] = ([|x|] + 1) mod wB.
Proof.
intros; rewrite <- spec_1; apply spec_add.
Qed.
(** Substraction *)
Lemma spec_sub_c : forall x y, [-|sub31c x y|] = [|x|] - [|y|].
Proof.
unfold sub31c, sub31, interp_carry; intros.
rewrite phi_phi_inv.
generalize (phi_bounded x)(phi_bounded y); intros.
set (X:=[|x|]) in *; set (Y:=[|y|]) in *; clearbody X Y.
assert ((X-Y) mod wB ?= X-Y <> Eq -> [-|C1 (phi_inv (X-Y))|] = X-Y).
unfold interp_carry; rewrite phi_phi_inv, Z.compare_eq_iff; intros.
destruct (Z_lt_le_dec (X-Y) 0).
rewrite <- (Z_mod_plus_full (X-Y) 1 wB).
rewrite Zmod_small; romega.
contradict H1; apply Zmod_small; romega.
generalize (Z.compare_eq ((X-Y) mod wB) (X-Y)); intros Heq.
destruct Z.compare; intros;
[ rewrite phi_phi_inv; auto | now apply H1 | now apply H1].
Qed.
Lemma spec_sub_carry_c : forall x y, [-|sub31carryc x y|] = [|x|] - [|y|] - 1.
Proof.
unfold sub31carryc, sub31, interp_carry; intros.
rewrite phi_phi_inv.
generalize (phi_bounded x)(phi_bounded y); intros.
set (X:=[|x|]) in *; set (Y:=[|y|]) in *; clearbody X Y.
assert ((X-Y-1) mod wB ?= X-Y-1 <> Eq -> [-|C1 (phi_inv (X-Y-1))|] = X-Y-1).
unfold interp_carry; rewrite phi_phi_inv, Z.compare_eq_iff; intros.
destruct (Z_lt_le_dec (X-Y-1) 0).
rewrite <- (Z_mod_plus_full (X-Y-1) 1 wB).
rewrite Zmod_small; romega.
contradict H1; apply Zmod_small; romega.
generalize (Z.compare_eq ((X-Y-1) mod wB) (X-Y-1)); intros Heq.
destruct Z.compare; intros;
[ rewrite phi_phi_inv; auto | now apply H1 | now apply H1].
Qed.
Lemma spec_sub : forall x y, [|x-y|] = ([|x|] - [|y|]) mod wB.
Proof.
intros; apply phi_phi_inv.
Qed.
Lemma spec_sub_carry :
forall x y, [|x-y-1|] = ([|x|] - [|y|] - 1) mod wB.
Proof.
unfold sub31; intros.
repeat rewrite phi_phi_inv.
apply Zminus_mod_idemp_l.
Qed.
Lemma spec_opp_c : forall x, [-|sub31c 0 x|] = -[|x|].
Proof.
intros; apply spec_sub_c.
Qed.
Lemma spec_opp : forall x, [|0 - x|] = (-[|x|]) mod wB.
Proof.
intros; apply phi_phi_inv.
Qed.
Lemma spec_opp_carry : forall x, [|0 - x - 1|] = wB - [|x|] - 1.
Proof.
unfold sub31; intros.
repeat rewrite phi_phi_inv.
change [|1|] with 1; change [|0|] with 0.
rewrite <- (Z_mod_plus_full (0-[|x|]) 1 wB).
rewrite Zminus_mod_idemp_l.
rewrite Zmod_small; generalize (phi_bounded x); romega.
Qed.
Lemma spec_pred_c : forall x, [-|sub31c x 1|] = [|x|] - 1.
Proof.
intros; apply spec_sub_c.
Qed.
Lemma spec_pred : forall x, [|x-1|] = ([|x|] - 1) mod wB.
Proof.
intros; apply spec_sub.
Qed.
(** Multiplication *)
Lemma phi2_phi_inv2 : forall x, [||phi_inv2 x||] = x mod (wB^2).
Proof.
assert (forall z, (z / wB) mod wB * wB + z mod wB = z mod wB ^ 2).
intros.
assert ((z/wB) mod wB = z/wB - (z/wB/wB)*wB).
rewrite (Z_div_mod_eq (z/wB) wB wB_pos) at 2; ring.
assert (z mod wB = z - (z/wB)*wB).
rewrite (Z_div_mod_eq z wB wB_pos) at 2; ring.
rewrite H.
rewrite H0 at 1.
ring_simplify.
rewrite Zdiv_Zdiv; auto with zarith.
rewrite (Z_div_mod_eq z (wB*wB)) at 2; auto with zarith.
change (wB*wB) with (wB^2); ring.
unfold phi_inv2.
destruct x; unfold zn2z_to_Z; rewrite ?phi_phi_inv;
change base with wB; auto.
Qed.
Lemma spec_mul_c : forall x y, [|| mul31c x y ||] = [|x|] * [|y|].
Proof.
unfold mul31c; intros.
rewrite phi2_phi_inv2.
apply Zmod_small.
generalize (phi_bounded x)(phi_bounded y); intros.
change (wB^2) with (wB * wB).
auto using Z.mul_lt_mono_nonneg with zarith.
Qed.
Lemma spec_mul : forall x y, [|x*y|] = ([|x|] * [|y|]) mod wB.
Proof.
intros; apply phi_phi_inv.
Qed.
Lemma spec_square_c : forall x, [|| mul31c x x ||] = [|x|] * [|x|].
Proof.
intros; apply spec_mul_c.
Qed.
(** Division *)
Lemma spec_div21 : forall a1 a2 b,
wB/2 <= [|b|] ->
[|a1|] < [|b|] ->
let (q,r) := div3121 a1 a2 b in
[|a1|] *wB+ [|a2|] = [|q|] * [|b|] + [|r|] /\
0 <= [|r|] < [|b|].
Proof.
unfold div3121; intros.
generalize (phi_bounded a1)(phi_bounded a2)(phi_bounded b); intros.
assert ([|b|]>0) by (auto with zarith).
generalize (Z_div_mod (phi2 a1 a2) [|b|] H4) (Z_div_pos (phi2 a1 a2) [|b|] H4).
unfold Z.div; destruct (Z.div_eucl (phi2 a1 a2) [|b|]).
rewrite ?phi_phi_inv.
destruct 1; intros.
unfold phi2 in *.
change base with wB; change base with wB in H5.
change (Z.pow_pos 2 31) with wB; change (Z.pow_pos 2 31) with wB in H.
rewrite H5, Z.mul_comm.
replace (z0 mod wB) with z0 by (symmetry; apply Zmod_small; omega).
replace (z mod wB) with z; auto with zarith.
symmetry; apply Zmod_small.
split.
apply H7; change base with wB; auto with zarith.
apply Z.mul_lt_mono_pos_r with [|b|]; [omega| ].
rewrite Z.mul_comm.
apply Z.le_lt_trans with ([|b|]*z+z0); [omega| ].
rewrite <- H5.
apply Z.le_lt_trans with ([|a1|]*wB+(wB-1)); [omega | ].
replace ([|a1|]*wB+(wB-1)) with (wB*([|a1|]+1)-1) by ring.
assert (wB*([|a1|]+1) <= wB*[|b|]); try omega.
apply Z.mul_le_mono_nonneg; omega.
Qed.
Lemma spec_div : forall a b, 0 < [|b|] ->
let (q,r) := div31 a b in
[|a|] = [|q|] * [|b|] + [|r|] /\
0 <= [|r|] < [|b|].
Proof.
unfold div31; intros.
assert ([|b|]>0) by (auto with zarith).
generalize (Z_div_mod [|a|] [|b|] H0) (Z_div_pos [|a|] [|b|] H0).
unfold Z.div; destruct (Z.div_eucl [|a|] [|b|]).
rewrite ?phi_phi_inv.
destruct 1; intros.
rewrite H1, Z.mul_comm.
generalize (phi_bounded a)(phi_bounded b); intros.
replace (z0 mod wB) with z0 by (symmetry; apply Zmod_small; omega).
replace (z mod wB) with z; auto with zarith.
symmetry; apply Zmod_small.
split; auto with zarith.
apply Z.le_lt_trans with [|a|]; auto with zarith.
rewrite H1.
apply Z.le_trans with ([|b|]*z); try omega.
rewrite <- (Z.mul_1_l z) at 1.
apply Z.mul_le_mono_nonneg; auto with zarith.
Qed.
Lemma spec_mod : forall a b, 0 < [|b|] ->
[|let (_,r) := (a/b)%int31 in r|] = [|a|] mod [|b|].
Proof.
unfold div31; intros.
assert ([|b|]>0) by (auto with zarith).
unfold Z.modulo.
generalize (Z_div_mod [|a|] [|b|] H0).
destruct (Z.div_eucl [|a|] [|b|]).
rewrite ?phi_phi_inv.
destruct 1; intros.
generalize (phi_bounded b); intros.
apply Zmod_small; omega.
Qed.
Lemma phi_gcd : forall i j,
[|gcd31 i j|] = Zgcdn (2*size) [|j|] [|i|].
Proof.
unfold gcd31.
induction (2*size)%nat; intros.
reflexivity.
simpl euler.
unfold compare31.
change [|On|] with 0.
generalize (phi_bounded j)(phi_bounded i); intros.
case_eq [|j|]; intros.
simpl; intros.
generalize (Zabs_spec [|i|]); omega.
simpl. rewrite IHn, H1; f_equal.
rewrite spec_mod, H1; auto.
rewrite H1; compute; auto.
rewrite H1 in H; destruct H as [H _]; compute in H; elim H; auto.
Qed.
Lemma spec_gcd : forall a b, Zis_gcd [|a|] [|b|] [|gcd31 a b|].
Proof.
intros.
rewrite phi_gcd.
apply Zis_gcd_sym.
apply Zgcdn_is_gcd.
unfold Zgcd_bound.
generalize (phi_bounded b).
destruct [|b|].
unfold size; auto with zarith.
intros (_,H).
cut (Pos.size_nat p <= size)%nat; [ omega | rewrite <- Zpower2_Psize; auto].
intros (H,_); compute in H; elim H; auto.
Qed.
Lemma iter_int31_iter_nat : forall A f i a,
iter_int31 i A f a = iter_nat (Z.abs_nat [|i|]) A f a.
Proof.
intros.
unfold iter_int31.
rewrite <- recrbis_equiv; auto; unfold recrbis.
rewrite <- phibis_aux_equiv.
revert i a; induction size.
simpl; auto.
simpl; intros.
case_eq (firstr i); intros H; rewrite 2 IHn;
unfold phibis_aux; simpl; rewrite ?H; fold (phibis_aux n (shiftr i));
generalize (phibis_aux_pos n (shiftr i)); intros;
set (z := phibis_aux n (shiftr i)) in *; clearbody z;
rewrite <- nat_rect_plus.
f_equal.
rewrite Z.double_spec, <- Z.add_diag.
symmetry; apply Zabs2Nat.inj_add; auto with zarith.
change (iter_nat (S (Z.abs_nat z) + (Z.abs_nat z))%nat A f a =
iter_nat (Z.abs_nat (Z.succ_double z)) A f a); f_equal.
rewrite Z.succ_double_spec, <- Z.add_diag.
rewrite Zabs2Nat.inj_add; auto with zarith.
rewrite Zabs2Nat.inj_add; auto with zarith.
change (Z.abs_nat 1) with 1%nat; omega.
Qed.
Fixpoint addmuldiv31_alt n i j :=
match n with
| O => i
| S n => addmuldiv31_alt n (sneakl (firstl j) i) (shiftl j)
end.
Lemma addmuldiv31_equiv : forall p x y,
addmuldiv31 p x y = addmuldiv31_alt (Z.abs_nat [|p|]) x y.
Proof.
intros.
unfold addmuldiv31.
rewrite iter_int31_iter_nat.
set (n:=Z.abs_nat [|p|]); clearbody n; clear p.
revert x y; induction n.
simpl; auto.
intros.
simpl addmuldiv31_alt.
replace (S n) with (n+1)%nat by (rewrite plus_comm; auto).
rewrite nat_rect_plus; simpl; auto.
Qed.
Lemma spec_add_mul_div : forall x y p, [|p|] <= Zpos 31 ->
[| addmuldiv31 p x y |] =
([|x|] * (2 ^ [|p|]) + [|y|] / (2 ^ ((Zpos 31) - [|p|]))) mod wB.
Proof.
intros.
rewrite addmuldiv31_equiv.
assert ([|p|] = Z.of_nat (Z.abs_nat [|p|])).
rewrite Zabs2Nat.id_abs; symmetry; apply Z.abs_eq.
destruct (phi_bounded p); auto.
rewrite H0; rewrite H0 in H; clear H0; rewrite Zabs2Nat.id.
set (n := Z.abs_nat [|p|]) in *; clearbody n.
assert (n <= 31)%nat.
rewrite Nat2Z.inj_le; auto with zarith.
clear p H; revert x y.
induction n.
simpl Z.of_nat; intros.
rewrite Z.mul_1_r.
replace ([|y|] / 2^(31-0)) with 0.
rewrite Z.add_0_r.
symmetry; apply Zmod_small; apply phi_bounded.
symmetry; apply Zdiv_small; apply phi_bounded.
simpl addmuldiv31_alt; intros.
rewrite IHn; [ | omega ].
case_eq (firstl y); intros.
rewrite phi_twice, Z.double_spec.
rewrite phi_twice_firstl; auto.
change (Z.double [|y|]) with (2*[|y|]).
rewrite Nat2Z.inj_succ, Z.pow_succ_r; auto with zarith.
rewrite Zplus_mod; rewrite Zmult_mod_idemp_l; rewrite <- Zplus_mod.
f_equal.
f_equal.
ring.
replace (31-Z.of_nat n) with (Z.succ(31-Z.succ(Z.of_nat n))) by ring.
rewrite Z.pow_succ_r, <- Zdiv_Zdiv; auto with zarith.
rewrite Z.mul_comm, Z_div_mult; auto with zarith.
rewrite phi_twice_plus_one, Z.succ_double_spec.
rewrite phi_twice; auto.
change (Z.double [|y|]) with (2*[|y|]).
rewrite Nat2Z.inj_succ, Z.pow_succ_r; auto with zarith.
rewrite Zplus_mod; rewrite Zmult_mod_idemp_l; rewrite <- Zplus_mod.
rewrite Z.mul_add_distr_r, Z.mul_1_l, <- Z.add_assoc.
f_equal.
f_equal.
ring.
assert ((2*[|y|]) mod wB = 2*[|y|] - wB).
clear - H. symmetry. apply Zmod_unique with 1; [ | ring ].
generalize (phi_lowerbound _ H) (phi_bounded y).
set (wB' := 2^Z.of_nat (pred size)).
replace wB with (2*wB'); [ omega | ].
unfold wB'. rewrite <- Z.pow_succ_r, <- Nat2Z.inj_succ by (auto with zarith).
f_equal.
rewrite H1.
replace wB with (2^(Z.of_nat n)*2^(31-Z.of_nat n)) by
(rewrite <- Zpower_exp; auto with zarith; f_equal; unfold size; ring).
unfold Z.sub; rewrite <- Z.mul_opp_l.
rewrite Z_div_plus; auto with zarith.
ring_simplify.
replace (31+-Z.of_nat n) with (Z.succ(31-Z.succ(Z.of_nat n))) by ring.
rewrite Z.pow_succ_r, <- Zdiv_Zdiv; auto with zarith.
rewrite Z.mul_comm, Z_div_mult; auto with zarith.
Qed.
Lemma shift_unshift_mod_2 : forall n p a, 0 <= p <= n ->
((a * 2 ^ (n - p)) mod (2^n) / 2 ^ (n - p)) mod (2^n) =
a mod 2 ^ p.
Proof.
intros.
rewrite Zmod_small.
rewrite Zmod_eq by (auto with zarith).
unfold Z.sub at 1.
rewrite Z_div_plus_full_l
by (cut (0 < 2^(n-p)); auto with zarith).
assert (2^n = 2^(n-p)*2^p).
rewrite <- Zpower_exp by (auto with zarith).
replace (n-p+p) with n; auto with zarith.
rewrite H0.
rewrite <- Zdiv_Zdiv, Z_div_mult by (auto with zarith).
rewrite (Z.mul_comm (2^(n-p))), Z.mul_assoc.
rewrite <- Z.mul_opp_l.
rewrite Z_div_mult by (auto with zarith).
symmetry; apply Zmod_eq; auto with zarith.
remember (a * 2 ^ (n - p)) as b.
destruct (Z_mod_lt b (2^n)); auto with zarith.
split.
apply Z_div_pos; auto with zarith.
apply Zdiv_lt_upper_bound; auto with zarith.
apply Z.lt_le_trans with (2^n); auto with zarith.
rewrite <- (Z.mul_1_r (2^n)) at 1.
apply Z.mul_le_mono_nonneg; auto with zarith.
cut (0 < 2 ^ (n-p)); auto with zarith.
Qed.
Lemma spec_pos_mod : forall w p,
[|ZnZ.pos_mod p w|] = [|w|] mod (2 ^ [|p|]).
Proof.
unfold int31_ops, ZnZ.pos_mod, compare31.
change [|31|] with 31%Z.
assert (forall w p, 31<=p -> [|w|] = [|w|] mod 2^p).
intros.
generalize (phi_bounded w).
symmetry; apply Zmod_small.
split; auto with zarith.
apply Z.lt_le_trans with wB; auto with zarith.
apply Zpower_le_monotone; auto with zarith.
intros.
case_eq ([|p|] ?= 31); intros;
[ apply H; rewrite (Z.compare_eq _ _ H0); auto with zarith | |
apply H; change ([|p|]>31)%Z in H0; auto with zarith ].
change ([|p|]<31) in H0.
rewrite spec_add_mul_div by auto with zarith.
change [|0|] with 0%Z; rewrite Z.mul_0_l, Z.add_0_l.
generalize (phi_bounded p)(phi_bounded w); intros.
assert (31-[|p|]<wB).
apply Z.le_lt_trans with 31%Z; auto with zarith.
compute; auto.
assert ([|31-p|]=31-[|p|]).
unfold sub31; rewrite phi_phi_inv.
change [|31|] with 31%Z.
apply Zmod_small; auto with zarith.
rewrite spec_add_mul_div by (rewrite H4; auto with zarith).
change [|0|] with 0%Z; rewrite Zdiv_0_l, Z.add_0_r.
rewrite H4.
apply shift_unshift_mod_2; simpl; auto with zarith.
Qed.
(** Shift operations *)
Lemma spec_head00: forall x, [|x|] = 0 -> [|head031 x|] = Zpos 31.
Proof.
intros.
generalize (phi_inv_phi x).
rewrite H; simpl phi_inv.
intros H'; rewrite <- H'.
simpl; auto.
Qed.
Fixpoint head031_alt n x :=
match n with
| O => 0%nat
| S n => match firstl x with
| D0 => S (head031_alt n (shiftl x))
| D1 => 0%nat
end
end.
Lemma head031_equiv :
forall x, [|head031 x|] = Z.of_nat (head031_alt size x).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H).
simpl; auto.
unfold head031, recl.
change On with (phi_inv (Z.of_nat (31-size))).
replace (head031_alt size x) with
(head031_alt size x + (31 - size))%nat by auto.
assert (size <= 31)%nat by auto with arith.
revert x H; induction size; intros.
simpl; auto.
unfold recl_aux; fold recl_aux.
unfold head031_alt; fold head031_alt.
rewrite H.
assert ([|phi_inv (Z.of_nat (31-S n))|] = Z.of_nat (31 - S n)).
rewrite phi_phi_inv.
apply Zmod_small.
split.
change 0 with (Z.of_nat O); apply inj_le; omega.
apply Z.le_lt_trans with (Z.of_nat 31).
apply inj_le; omega.
compute; auto.
case_eq (firstl x); intros; auto.
rewrite plus_Sn_m, plus_n_Sm.
replace (S (31 - S n)) with (31 - n)%nat by omega.
rewrite <- IHn; [ | omega | ].
f_equal; f_equal.
unfold add31.
rewrite H1.
f_equal.
change [|In|] with 1.
replace (31-n)%nat with (S (31 - S n))%nat by omega.
rewrite Nat2Z.inj_succ; ring.
clear - H H2.
rewrite (sneakr_shiftl x) in H.
rewrite H2 in H.
case_eq (iszero (shiftl x)); intros; auto.
rewrite (iszero_eq0 _ H0) in H; discriminate.
Qed.
Lemma phi_nz : forall x, 0 < [|x|] <-> x <> 0%int31.
Proof.
split; intros.
red; intro; subst x; discriminate.
assert ([|x|]<>0%Z).
contradict H.
rewrite <- (phi_inv_phi x); rewrite H; auto.
generalize (phi_bounded x); auto with zarith.
Qed.
Lemma spec_head0 : forall x, 0 < [|x|] ->
wB/ 2 <= 2 ^ ([|head031 x|]) * [|x|] < wB.
Proof.
intros.
rewrite head031_equiv.
assert (nshiftl x size = 0%int31).
apply nshiftl_size.
revert x H H0.
unfold size at 2 5.
induction size.
simpl Z.of_nat.
intros.
compute in H0; rewrite H0 in H; discriminate.
intros.
simpl head031_alt.
case_eq (firstl x); intros.
rewrite (Nat2Z.inj_succ (head031_alt n (shiftl x))), Z.pow_succ_r; auto with zarith.
rewrite <- Z.mul_assoc, Z.mul_comm, <- Z.mul_assoc, <-(Z.mul_comm 2).
rewrite <- Z.double_spec, <- (phi_twice_firstl _ H1).
apply IHn.
rewrite phi_nz; rewrite phi_nz in H; contradict H.
change twice with shiftl in H.
rewrite (sneakr_shiftl x), H1, H; auto.
rewrite <- nshiftl_S_tail; auto.
change (2^(Z.of_nat 0)) with 1; rewrite Z.mul_1_l.
generalize (phi_bounded x); unfold size; split; auto with zarith.
change (2^(Z.of_nat 31)/2) with (2^(Z.of_nat (pred size))).
apply phi_lowerbound; auto.
Qed.
Lemma spec_tail00: forall x, [|x|] = 0 -> [|tail031 x|] = Zpos 31.
Proof.
intros.
generalize (phi_inv_phi x).
rewrite H; simpl phi_inv.
intros H'; rewrite <- H'.
simpl; auto.
Qed.
Fixpoint tail031_alt n x :=
match n with
| O => 0%nat
| S n => match firstr x with
| D0 => S (tail031_alt n (shiftr x))
| D1 => 0%nat
end
end.
Lemma tail031_equiv :
forall x, [|tail031 x|] = Z.of_nat (tail031_alt size x).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H).
simpl; auto.
unfold tail031, recr.
change On with (phi_inv (Z.of_nat (31-size))).
replace (tail031_alt size x) with
(tail031_alt size x + (31 - size))%nat by auto.
assert (size <= 31)%nat by auto with arith.
revert x H; induction size; intros.
simpl; auto.
unfold recr_aux; fold recr_aux.
unfold tail031_alt; fold tail031_alt.
rewrite H.
assert ([|phi_inv (Z.of_nat (31-S n))|] = Z.of_nat (31 - S n)).
rewrite phi_phi_inv.
apply Zmod_small.
split.
change 0 with (Z.of_nat O); apply inj_le; omega.
apply Z.le_lt_trans with (Z.of_nat 31).
apply inj_le; omega.
compute; auto.
case_eq (firstr x); intros; auto.
rewrite plus_Sn_m, plus_n_Sm.
replace (S (31 - S n)) with (31 - n)%nat by omega.
rewrite <- IHn; [ | omega | ].
f_equal; f_equal.
unfold add31.
rewrite H1.
f_equal.
change [|In|] with 1.
replace (31-n)%nat with (S (31 - S n))%nat by omega.
rewrite Nat2Z.inj_succ; ring.
clear - H H2.
rewrite (sneakl_shiftr x) in H.
rewrite H2 in H.
case_eq (iszero (shiftr x)); intros; auto.
rewrite (iszero_eq0 _ H0) in H; discriminate.
Qed.
Lemma spec_tail0 : forall x, 0 < [|x|] ->
exists y, 0 <= y /\ [|x|] = (2 * y + 1) * (2 ^ [|tail031 x|]).
Proof.
intros.
rewrite tail031_equiv.
assert (nshiftr x size = 0%int31).
apply nshiftr_size.
revert x H H0.
induction size.
simpl Z.of_nat.
intros.
compute in H0; rewrite H0 in H; discriminate.
intros.
simpl tail031_alt.
case_eq (firstr x); intros.
rewrite (Nat2Z.inj_succ (tail031_alt n (shiftr x))), Z.pow_succ_r; auto with zarith.
destruct (IHn (shiftr x)) as (y & Hy1 & Hy2).
rewrite phi_nz; rewrite phi_nz in H; contradict H.
rewrite (sneakl_shiftr x), H1, H; auto.
rewrite <- nshiftr_S_tail; auto.
exists y; split; auto.
rewrite phi_eqn1; auto.
rewrite Z.double_spec, Hy2; ring.
exists [|shiftr x|].
split.
generalize (phi_bounded (shiftr x)); auto with zarith.
rewrite phi_eqn2; auto.
rewrite Z.succ_double_spec; simpl; ring.
Qed.
(* Sqrt *)
(* Direct transcription of an old proof
of a fortran program in boyer-moore *)
Lemma quotient_by_2 a: a - 1 <= (a/2) + (a/2).
Proof.
case (Z_mod_lt a 2); auto with zarith.
intros H1; rewrite Zmod_eq_full; auto with zarith.
Qed.
Lemma sqrt_main_trick j k: 0 <= j -> 0 <= k ->
(j * k) + j <= ((j + k)/2 + 1) ^ 2.
Proof.
intros Hj; generalize Hj k; pattern j; apply natlike_ind;
auto; clear k j Hj.
intros _ k Hk; repeat rewrite Z.add_0_l.
apply Z.mul_nonneg_nonneg; generalize (Z_div_pos k 2); auto with zarith.
intros j Hj Hrec _ k Hk; pattern k; apply natlike_ind; auto; clear k Hk.
rewrite Z.mul_0_r, Z.add_0_r, Z.add_0_l.
generalize (sqr_pos (Z.succ j / 2)) (quotient_by_2 (Z.succ j));
unfold Z.succ.
rewrite Z.pow_2_r, Z.mul_add_distr_r; repeat rewrite Z.mul_add_distr_l.
auto with zarith.
intros k Hk _.
replace ((Z.succ j + Z.succ k) / 2) with ((j + k)/2 + 1).
generalize (Hrec Hj k Hk) (quotient_by_2 (j + k)).
unfold Z.succ; repeat rewrite Z.pow_2_r;
repeat rewrite Z.mul_add_distr_r; repeat rewrite Z.mul_add_distr_l.
repeat rewrite Z.mul_1_l; repeat rewrite Z.mul_1_r.
auto with zarith.
rewrite Z.add_comm, <- Z_div_plus_full_l; auto with zarith.
apply f_equal2 with (f := Z.div); auto with zarith.
Qed.
Lemma sqrt_main i j: 0 <= i -> 0 < j -> i < ((j + (i/j))/2 + 1) ^ 2.
Proof.
intros Hi Hj.
assert (Hij: 0 <= i/j) by (apply Z_div_pos; auto with zarith).
apply Z.lt_le_trans with (2 := sqrt_main_trick _ _ (Z.lt_le_incl _ _ Hj) Hij).
pattern i at 1; rewrite (Z_div_mod_eq i j); case (Z_mod_lt i j); auto with zarith.
Qed.
Lemma sqrt_init i: 1 < i -> i < (i/2 + 1) ^ 2.
Proof.
intros Hi.
assert (H1: 0 <= i - 2) by auto with zarith.
assert (H2: 1 <= (i / 2) ^ 2); auto with zarith.
replace i with (1* 2 + (i - 2)); auto with zarith.
rewrite Z.pow_2_r, Z_div_plus_full_l; auto with zarith.
generalize (sqr_pos ((i - 2)/ 2)) (Z_div_pos (i - 2) 2).
rewrite Z.mul_add_distr_r; repeat rewrite Z.mul_add_distr_l.
auto with zarith.
generalize (quotient_by_2 i).
rewrite Z.pow_2_r in H2 |- *;
repeat (rewrite Z.mul_add_distr_r ||
rewrite Z.mul_add_distr_l ||
rewrite Z.mul_1_l || rewrite Z.mul_1_r).
auto with zarith.
Qed.
Lemma sqrt_test_true i j: 0 <= i -> 0 < j -> i/j >= j -> j ^ 2 <= i.
Proof.
intros Hi Hj Hd; rewrite Z.pow_2_r.
apply Z.le_trans with (j * (i/j)); auto with zarith.
apply Z_mult_div_ge; auto with zarith.
Qed.
Lemma sqrt_test_false i j: 0 <= i -> 0 < j -> i/j < j -> (j + (i/j))/2 < j.
Proof.
intros Hi Hj H; case (Z.le_gt_cases j ((j + (i/j))/2)); auto.
intros H1; contradict H; apply Z.le_ngt.
assert (2 * j <= j + (i/j)); auto with zarith.
apply Z.le_trans with (2 * ((j + (i/j))/2)); auto with zarith.
apply Z_mult_div_ge; auto with zarith.
Qed.
Lemma sqrt31_step_def rec i j:
sqrt31_step rec i j =
match (fst (i/j) ?= j)%int31 with
Lt => rec i (fst ((j + fst(i/j))/2))%int31
| _ => j
end.
Proof.
unfold sqrt31_step; case div31; intros.
simpl; case compare31; auto.
Qed.
Lemma div31_phi i j: 0 < [|j|] -> [|fst (i/j)%int31|] = [|i|]/[|j|].
intros Hj; generalize (spec_div i j Hj).
case div31; intros q r; simpl @fst.
intros (H1,H2); apply Zdiv_unique with [|r|]; auto with zarith.
rewrite H1; ring.
Qed.
Lemma sqrt31_step_correct rec i j:
0 < [|i|] -> 0 < [|j|] -> [|i|] < ([|j|] + 1) ^ 2 ->
2 * [|j|] < wB ->
(forall j1 : int31,
0 < [|j1|] < [|j|] -> [|i|] < ([|j1|] + 1) ^ 2 ->
[|rec i j1|] ^ 2 <= [|i|] < ([|rec i j1|] + 1) ^ 2) ->
[|sqrt31_step rec i j|] ^ 2 <= [|i|] < ([|sqrt31_step rec i j|] + 1) ^ 2.
Proof.
assert (Hp2: 0 < [|2|]) by exact (eq_refl Lt).
intros Hi Hj Hij H31 Hrec; rewrite sqrt31_step_def.
rewrite spec_compare, div31_phi; auto.
case Z.compare_spec; auto; intros Hc;
try (split; auto; apply sqrt_test_true; auto with zarith; fail).
assert (E : [|(j + fst (i / j)%int31)|] = [|j|] + [|i|] / [|j|]).
{ rewrite spec_add, div31_phi; auto using Z.mod_small with zarith. }
apply Hrec; rewrite !div31_phi, E; auto using sqrt_main with zarith.
split; try apply sqrt_test_false; auto with zarith.
apply Z.le_succ_l in Hj. change (1 <= [|j|]) in Hj.
Z.le_elim Hj.
- replace ([|j|] + [|i|]/[|j|]) with
(1 * 2 + (([|j|] - 2) + [|i|] / [|j|])) by ring.
rewrite Z_div_plus_full_l; auto with zarith.
assert (0 <= [|i|]/ [|j|]) by auto with zarith.
assert (0 <= ([|j|] - 2 + [|i|] / [|j|]) / [|2|]); auto with zarith.
- rewrite <- Hj, Zdiv_1_r.
replace (1 + [|i|]) with (1 * 2 + ([|i|] - 1)) by ring.
rewrite Z_div_plus_full_l; auto with zarith.
assert (0 <= ([|i|] - 1) /2) by auto with zarith.
change ([|2|]) with 2; auto with zarith.
Qed.
Lemma iter31_sqrt_correct n rec i j: 0 < [|i|] -> 0 < [|j|] ->
[|i|] < ([|j|] + 1) ^ 2 -> 2 * [|j|] < 2 ^ (Z.of_nat size) ->
(forall j1, 0 < [|j1|] -> 2^(Z.of_nat n) + [|j1|] <= [|j|] ->
[|i|] < ([|j1|] + 1) ^ 2 -> 2 * [|j1|] < 2 ^ (Z.of_nat size) ->
[|rec i j1|] ^ 2 <= [|i|] < ([|rec i j1|] + 1) ^ 2) ->
[|iter31_sqrt n rec i j|] ^ 2 <= [|i|] < ([|iter31_sqrt n rec i j|] + 1) ^ 2.
Proof.
revert rec i j; elim n; unfold iter31_sqrt; fold iter31_sqrt; clear n.
intros rec i j Hi Hj Hij H31 Hrec; apply sqrt31_step_correct; auto with zarith.
intros; apply Hrec; auto with zarith.
rewrite Z.pow_0_r; auto with zarith.
intros n Hrec rec i j Hi Hj Hij H31 HHrec.
apply sqrt31_step_correct; auto.
intros j1 Hj1 Hjp1; apply Hrec; auto with zarith.
intros j2 Hj2 H2j2 Hjp2 Hj31; apply Hrec; auto with zarith.
intros j3 Hj3 Hpj3.
apply HHrec; auto.
rewrite Nat2Z.inj_succ, Z.pow_succ_r.
apply Z.le_trans with (2 ^Z.of_nat n + [|j2|]); auto with zarith.
apply Nat2Z.is_nonneg.
Qed.
Lemma spec_sqrt : forall x,
[|sqrt31 x|] ^ 2 <= [|x|] < ([|sqrt31 x|] + 1) ^ 2.
Proof.
intros i; unfold sqrt31.
rewrite spec_compare. case Z.compare_spec; change [|1|] with 1;
intros Hi; auto with zarith.
repeat rewrite Z.pow_2_r; auto with zarith.
apply iter31_sqrt_correct; auto with zarith.
rewrite div31_phi; change ([|2|]) with 2; auto with zarith.
replace ([|i|]) with (1 * 2 + ([|i|] - 2))%Z; try ring.
assert (0 <= ([|i|] - 2)/2)%Z by (apply Z_div_pos; auto with zarith).
rewrite Z_div_plus_full_l; auto with zarith.
rewrite div31_phi; change ([|2|]) with 2; auto with zarith.
apply sqrt_init; auto.
rewrite div31_phi; change ([|2|]) with 2; auto with zarith.
apply Z.le_lt_trans with ([|i|]).
apply Z_mult_div_ge; auto with zarith.
case (phi_bounded i); auto.
intros j2 H1 H2; contradict H2; apply Z.lt_nge.
rewrite div31_phi; change ([|2|]) with 2; auto with zarith.
apply Z.le_lt_trans with ([|i|]); auto with zarith.
assert (0 <= [|i|]/2)%Z by (apply Z_div_pos; auto with zarith).
apply Z.le_trans with (2 * ([|i|]/2)); auto with zarith.
apply Z_mult_div_ge; auto with zarith.
case (phi_bounded i); unfold size; auto with zarith.
change [|0|] with 0; auto with zarith.
case (phi_bounded i); repeat rewrite Z.pow_2_r; auto with zarith.
Qed.
Lemma sqrt312_step_def rec ih il j:
sqrt312_step rec ih il j =
match (ih ?= j)%int31 with
Eq => j
| Gt => j
| _ =>
match (fst (div3121 ih il j) ?= j)%int31 with
Lt => let m := match j +c fst (div3121 ih il j) with
C0 m1 => fst (m1/2)%int31
| C1 m1 => (fst (m1/2) + v30)%int31
end in rec ih il m
| _ => j
end
end.
Proof.
unfold sqrt312_step; case div3121; intros.
simpl; case compare31; auto.
Qed.
Lemma sqrt312_lower_bound ih il j:
phi2 ih il < ([|j|] + 1) ^ 2 -> [|ih|] <= [|j|].
Proof.
intros H1.
case (phi_bounded j); intros Hbj _.
case (phi_bounded il); intros Hbil _.
case (phi_bounded ih); intros Hbih Hbih1.
assert ([|ih|] < [|j|] + 1); auto with zarith.
apply Z.square_lt_simpl_nonneg; auto with zarith.
rewrite <- ?Z.pow_2_r; apply Z.le_lt_trans with (2 := H1).
apply Z.le_trans with ([|ih|] * wB).
- rewrite ? Z.pow_2_r; auto with zarith.
- unfold phi2. change base with wB; auto with zarith.
Qed.
Lemma div312_phi ih il j: (2^30 <= [|j|] -> [|ih|] < [|j|] ->
[|fst (div3121 ih il j)|] = phi2 ih il/[|j|])%Z.
Proof.
intros Hj Hj1.
generalize (spec_div21 ih il j Hj Hj1).
case div3121; intros q r (Hq, Hr).
apply Zdiv_unique with (phi r); auto with zarith.
simpl @fst; apply eq_trans with (1 := Hq); ring.
Qed.
Lemma sqrt312_step_correct rec ih il j:
2 ^ 29 <= [|ih|] -> 0 < [|j|] -> phi2 ih il < ([|j|] + 1) ^ 2 ->
(forall j1, 0 < [|j1|] < [|j|] -> phi2 ih il < ([|j1|] + 1) ^ 2 ->
[|rec ih il j1|] ^ 2 <= phi2 ih il < ([|rec ih il j1|] + 1) ^ 2) ->
[|sqrt312_step rec ih il j|] ^ 2 <= phi2 ih il
< ([|sqrt312_step rec ih il j|] + 1) ^ 2.
Proof.
assert (Hp2: (0 < [|2|])%Z) by exact (eq_refl Lt).
intros Hih Hj Hij Hrec; rewrite sqrt312_step_def.
assert (H1: ([|ih|] <= [|j|])) by (apply sqrt312_lower_bound with il; auto).
case (phi_bounded ih); intros Hih1 _.
case (phi_bounded il); intros Hil1 _.
case (phi_bounded j); intros _ Hj1.
assert (Hp3: (0 < phi2 ih il)).
{ unfold phi2; apply Z.lt_le_trans with ([|ih|] * base); auto with zarith.
apply Z.mul_pos_pos; auto with zarith.
apply Z.lt_le_trans with (2:= Hih); auto with zarith. }
rewrite spec_compare. case Z.compare_spec; intros Hc1.
- split; auto.
apply sqrt_test_true; auto.
+ unfold phi2, base; auto with zarith.
+ unfold phi2; rewrite Hc1.
assert (0 <= [|il|]/[|j|]) by (apply Z_div_pos; auto with zarith).
rewrite Z.mul_comm, Z_div_plus_full_l; auto with zarith.
change base with wB. auto with zarith.
- case (Z.le_gt_cases (2 ^ 30) [|j|]); intros Hjj.
+ rewrite spec_compare; case Z.compare_spec;
rewrite div312_phi; auto; intros Hc;
try (split; auto; apply sqrt_test_true; auto with zarith; fail).
apply Hrec.
* assert (Hf1: 0 <= phi2 ih il/ [|j|]) by auto with zarith.
apply Z.le_succ_l in Hj. change (1 <= [|j|]) in Hj.
Z.le_elim Hj;
[ | contradict Hc; apply Z.le_ngt;
rewrite <- Hj, Zdiv_1_r; auto with zarith ].
assert (Hf3: 0 < ([|j|] + phi2 ih il / [|j|]) / 2).
{ replace ([|j|] + phi2 ih il/ [|j|]) with
(1 * 2 + (([|j|] - 2) + phi2 ih il / [|j|])); try ring.
rewrite Z_div_plus_full_l; auto with zarith.
assert (0 <= ([|j|] - 2 + phi2 ih il / [|j|]) / 2) ;
auto with zarith. }
assert (Hf4: ([|j|] + phi2 ih il / [|j|]) / 2 < [|j|]).
{ apply sqrt_test_false; auto with zarith. }
generalize (spec_add_c j (fst (div3121 ih il j))).
unfold interp_carry; case add31c; intros r;
rewrite div312_phi; auto with zarith.
{ rewrite div31_phi; change [|2|] with 2; auto with zarith.
intros HH; rewrite HH; clear HH; auto with zarith. }
{ rewrite spec_add, div31_phi; change [|2|] with 2; auto.
rewrite Z.mul_1_l; intros HH.
rewrite Z.add_comm, <- Z_div_plus_full_l; auto with zarith.
change (phi v30 * 2) with (2 ^ Z.of_nat size).
rewrite HH, Zmod_small; auto with zarith. }
* replace (phi _) with (([|j|] + (phi2 ih il)/([|j|]))/2);
[ apply sqrt_main; auto with zarith | ].
generalize (spec_add_c j (fst (div3121 ih il j))).
unfold interp_carry; case add31c; intros r;
rewrite div312_phi; auto with zarith.
{ rewrite div31_phi; auto with zarith.
intros HH; rewrite HH; auto with zarith. }
{ intros HH; rewrite <- HH.
change (1 * 2 ^ Z.of_nat size) with (phi (v30) * 2).
rewrite Z_div_plus_full_l; auto with zarith.
rewrite Z.add_comm.
rewrite spec_add, Zmod_small.
- rewrite div31_phi; auto.
- split; auto with zarith.
+ case (phi_bounded (fst (r/2)%int31));
case (phi_bounded v30); auto with zarith.
+ rewrite div31_phi; change (phi 2) with 2; auto.
change (2 ^Z.of_nat size) with (base/2 + phi v30).
assert (phi r / 2 < base/2); auto with zarith.
apply Z.mul_lt_mono_pos_r with 2; auto with zarith.
change (base/2 * 2) with base.
apply Z.le_lt_trans with (phi r).
* rewrite Z.mul_comm; apply Z_mult_div_ge; auto with zarith.
* case (phi_bounded r); auto with zarith. }
+ contradict Hij; apply Z.le_ngt.
assert ((1 + [|j|]) <= 2 ^ 30); auto with zarith.
apply Z.le_trans with ((2 ^ 30) * (2 ^ 30)); auto with zarith.
* assert (0 <= 1 + [|j|]); auto with zarith.
apply Z.mul_le_mono_nonneg; auto with zarith.
* change ((2 ^ 30) * (2 ^ 30)) with ((2 ^ 29) * base).
apply Z.le_trans with ([|ih|] * base);
change wB with base in *; auto with zarith.
unfold phi2, base; auto with zarith.
- split; auto.
apply sqrt_test_true; auto.
+ unfold phi2, base; auto with zarith.
+ apply Z.le_ge; apply Z.le_trans with (([|j|] * base)/[|j|]).
* rewrite Z.mul_comm, Z_div_mult; auto with zarith.
* apply Z.ge_le; apply Z_div_ge; auto with zarith.
Qed.
Lemma iter312_sqrt_correct n rec ih il j:
2^29 <= [|ih|] -> 0 < [|j|] -> phi2 ih il < ([|j|] + 1) ^ 2 ->
(forall j1, 0 < [|j1|] -> 2^(Z.of_nat n) + [|j1|] <= [|j|] ->
phi2 ih il < ([|j1|] + 1) ^ 2 ->
[|rec ih il j1|] ^ 2 <= phi2 ih il < ([|rec ih il j1|] + 1) ^ 2) ->
[|iter312_sqrt n rec ih il j|] ^ 2 <= phi2 ih il
< ([|iter312_sqrt n rec ih il j|] + 1) ^ 2.
Proof.
revert rec ih il j; elim n; unfold iter312_sqrt; fold iter312_sqrt; clear n.
intros rec ih il j Hi Hj Hij Hrec; apply sqrt312_step_correct; auto with zarith.
intros; apply Hrec; auto with zarith.
rewrite Z.pow_0_r; auto with zarith.
intros n Hrec rec ih il j Hi Hj Hij HHrec.
apply sqrt312_step_correct; auto.
intros j1 Hj1 Hjp1; apply Hrec; auto with zarith.
intros j2 Hj2 H2j2 Hjp2; apply Hrec; auto with zarith.
intros j3 Hj3 Hpj3.
apply HHrec; auto.
rewrite Nat2Z.inj_succ, Z.pow_succ_r.
apply Z.le_trans with (2 ^Z.of_nat n + [|j2|]); auto with zarith.
apply Nat2Z.is_nonneg.
Qed.
(* Avoid expanding [iter312_sqrt] before variables in the context. *)
Strategy 1 [iter312_sqrt].
Lemma spec_sqrt2 : forall x y,
wB/ 4 <= [|x|] ->
let (s,r) := sqrt312 x y in
[||WW x y||] = [|s|] ^ 2 + [+|r|] /\
[+|r|] <= 2 * [|s|].
Proof.
intros ih il Hih; unfold sqrt312.
change [||WW ih il||] with (phi2 ih il).
assert (Hbin: forall s, s * s + 2* s + 1 = (s + 1) ^ 2) by
(intros s; ring).
assert (Hb: 0 <= base) by (red; intros HH; discriminate).
assert (Hi2: phi2 ih il < (phi Tn + 1) ^ 2).
{ change ((phi Tn + 1) ^ 2) with (2^62).
apply Z.le_lt_trans with ((2^31 -1) * base + (2^31 - 1)); auto with zarith.
2: simpl; unfold Z.pow_pos; simpl; auto with zarith.
case (phi_bounded ih); case (phi_bounded il); intros H1 H2 H3 H4.
unfold base, Z.pow, Z.pow_pos in H2,H4; simpl in H2,H4.
unfold phi2. cbn [Z.pow Z.pow_pos Pos.iter]. auto with zarith. }
case (iter312_sqrt_correct 31 (fun _ _ j => j) ih il Tn); auto with zarith.
change [|Tn|] with 2147483647; auto with zarith.
intros j1 _ HH; contradict HH.
apply Z.lt_nge.
change [|Tn|] with 2147483647; auto with zarith.
change (2 ^ Z.of_nat 31) with 2147483648; auto with zarith.
case (phi_bounded j1); auto with zarith.
set (s := iter312_sqrt 31 (fun _ _ j : int31 => j) ih il Tn).
intros Hs1 Hs2.
generalize (spec_mul_c s s); case mul31c.
simpl zn2z_to_Z; intros HH.
assert ([|s|] = 0).
{ symmetry in HH. rewrite Z.mul_eq_0 in HH. destruct HH; auto. }
contradict Hs2; apply Z.le_ngt; rewrite H.
change ((0 + 1) ^ 2) with 1.
apply Z.le_trans with (2 ^ Z.of_nat size / 4 * base).
simpl; auto with zarith.
apply Z.le_trans with ([|ih|] * base); auto with zarith.
unfold phi2; case (phi_bounded il); auto with zarith.
intros ih1 il1.
change [||WW ih1 il1||] with (phi2 ih1 il1).
intros Hihl1.
generalize (spec_sub_c il il1).
case sub31c; intros il2 Hil2.
rewrite spec_compare; case Z.compare_spec.
unfold interp_carry in *.
intros H1; split.
rewrite Z.pow_2_r, <- Hihl1.
unfold phi2; ring[Hil2 H1].
replace [|il2|] with (phi2 ih il - phi2 ih1 il1).
rewrite Hihl1.
rewrite <-Hbin in Hs2; auto with zarith.
unfold phi2; rewrite H1, Hil2; ring.
unfold interp_carry.
intros H1; contradict Hs1.
apply Z.lt_nge; rewrite Z.pow_2_r, <-Hihl1.
unfold phi2.
case (phi_bounded il); intros _ H2.
apply Z.lt_le_trans with (([|ih|] + 1) * base + 0).
rewrite Z.mul_add_distr_r, Z.add_0_r; auto with zarith.
case (phi_bounded il1); intros H3 _.
apply Z.add_le_mono; auto with zarith.
unfold interp_carry in *; change (1 * 2 ^ Z.of_nat size) with base.
rewrite Z.pow_2_r, <- Hihl1, Hil2.
intros H1.
rewrite <- Z.le_succ_l, <- Z.add_1_r in H1.
Z.le_elim H1.
contradict Hs2; apply Z.le_ngt.
replace (([|s|] + 1) ^ 2) with (phi2 ih1 il1 + 2 * [|s|] + 1).
unfold phi2.
case (phi_bounded il); intros Hpil _.
assert (Hl1l: [|il1|] <= [|il|]).
{ case (phi_bounded il2); rewrite Hil2; auto with zarith. }
assert ([|ih1|] * base + 2 * [|s|] + 1 <= [|ih|] * base); auto with zarith.
case (phi_bounded s); change (2 ^ Z.of_nat size) with base; intros _ Hps.
case (phi_bounded ih1); intros Hpih1 _; auto with zarith.
apply Z.le_trans with (([|ih1|] + 2) * base); auto with zarith.
rewrite Z.mul_add_distr_r.
assert (2 * [|s|] + 1 <= 2 * base); auto with zarith.
rewrite Hihl1, Hbin; auto.
split.
unfold phi2; rewrite <- H1; ring.
replace (base + ([|il|] - [|il1|])) with (phi2 ih il - ([|s|] * [|s|])).
rewrite <-Hbin in Hs2; auto with zarith.
rewrite <- Hihl1; unfold phi2; rewrite <- H1; ring.
unfold interp_carry in Hil2 |- *.
unfold interp_carry; change (1 * 2 ^ Z.of_nat size) with base.
assert (Hsih: [|ih - 1|] = [|ih|] - 1).
{ rewrite spec_sub, Zmod_small; auto; change [|1|] with 1.
case (phi_bounded ih); intros H1 H2.
generalize Hih; change (2 ^ Z.of_nat size / 4) with 536870912.
split; auto with zarith. }
rewrite spec_compare; case Z.compare_spec.
rewrite Hsih.
intros H1; split.
rewrite Z.pow_2_r, <- Hihl1.
unfold phi2; rewrite <-H1.
transitivity ([|ih|] * base + [|il1|] + ([|il|] - [|il1|])).
ring.
rewrite <-Hil2.
change (2 ^ Z.of_nat size) with base; ring.
replace [|il2|] with (phi2 ih il - phi2 ih1 il1).
rewrite Hihl1.
rewrite <-Hbin in Hs2; auto with zarith.
unfold phi2.
rewrite <-H1.
ring_simplify.
transitivity (base + ([|il|] - [|il1|])).
ring.
rewrite <-Hil2.
change (2 ^ Z.of_nat size) with base; ring.
rewrite Hsih; intros H1.
assert (He: [|ih|] = [|ih1|]).
{ apply Z.le_antisymm; auto with zarith.
case (Z.le_gt_cases [|ih1|] [|ih|]); auto; intros H2.
contradict Hs1; apply Z.lt_nge; rewrite Z.pow_2_r, <-Hihl1.
unfold phi2.
case (phi_bounded il); change (2 ^ Z.of_nat size) with base;
intros _ Hpil1.
apply Z.lt_le_trans with (([|ih|] + 1) * base).
rewrite Z.mul_add_distr_r, Z.mul_1_l; auto with zarith.
case (phi_bounded il1); intros Hpil2 _.
apply Z.le_trans with (([|ih1|]) * base); auto with zarith. }
rewrite Z.pow_2_r, <-Hihl1; unfold phi2; rewrite <-He.
contradict Hs1; apply Z.lt_nge; rewrite Z.pow_2_r, <-Hihl1.
unfold phi2; rewrite He.
assert (phi il - phi il1 < 0); auto with zarith.
rewrite <-Hil2.
case (phi_bounded il2); auto with zarith.
intros H1.
rewrite Z.pow_2_r, <-Hihl1.
assert (H2 : [|ih1|]+2 <= [|ih|]); auto with zarith.
Z.le_elim H2.
contradict Hs2; apply Z.le_ngt.
replace (([|s|] + 1) ^ 2) with (phi2 ih1 il1 + 2 * [|s|] + 1).
unfold phi2.
assert ([|ih1|] * base + 2 * phi s + 1 <= [|ih|] * base + ([|il|] - [|il1|]));
auto with zarith.
rewrite <-Hil2.
change (-1 * 2 ^ Z.of_nat size) with (-base).
case (phi_bounded il2); intros Hpil2 _.
apply Z.le_trans with ([|ih|] * base + - base); auto with zarith.
case (phi_bounded s); change (2 ^ Z.of_nat size) with base; intros _ Hps.
assert (2 * [|s|] + 1 <= 2 * base); auto with zarith.
apply Z.le_trans with ([|ih1|] * base + 2 * base); auto with zarith.
assert (Hi: ([|ih1|] + 3) * base <= [|ih|] * base); auto with zarith.
rewrite Z.mul_add_distr_r in Hi; auto with zarith.
rewrite Hihl1, Hbin; auto.
unfold phi2; rewrite <-H2.
split.
replace [|il|] with (([|il|] - [|il1|]) + [|il1|]); try ring.
rewrite <-Hil2.
change (-1 * 2 ^ Z.of_nat size) with (-base); ring.
replace (base + [|il2|]) with (phi2 ih il - phi2 ih1 il1).
rewrite Hihl1.
rewrite <-Hbin in Hs2; auto with zarith.
unfold phi2; rewrite <-H2.
replace [|il|] with (([|il|] - [|il1|]) + [|il1|]); try ring.
rewrite <-Hil2.
change (-1 * 2 ^ Z.of_nat size) with (-base); ring.
Qed.
(** [iszero] *)
Lemma spec_eq0 : forall x, ZnZ.eq0 x = true -> [|x|] = 0.
Proof.
clear; unfold ZnZ.eq0, int31_ops.
unfold compare31; intros.
change [|0|] with 0 in H.
apply Z.compare_eq.
now destruct ([|x|] ?= 0).
Qed.
(* Even *)
Lemma spec_is_even : forall x,
if ZnZ.is_even x then [|x|] mod 2 = 0 else [|x|] mod 2 = 1.
Proof.
unfold ZnZ.is_even, int31_ops; intros.
generalize (spec_div x 2).
destruct (x/2)%int31 as (q,r); intros.
unfold compare31.
change [|2|] with 2 in H.
change [|0|] with 0.
destruct H; auto with zarith.
replace ([|x|] mod 2) with [|r|].
destruct H; auto with zarith.
case Z.compare_spec; auto with zarith.
apply Zmod_unique with [|q|]; auto with zarith.
Qed.
(* Bitwise *)
Lemma log2_phi_bounded x : Z.log2 [|x|] < Z.of_nat size.
Proof.
destruct (phi_bounded x) as (H,H').
Z.le_elim H.
- now apply Z.log2_lt_pow2.
- now rewrite <- H.
Qed.
Lemma spec_lor x y : [| ZnZ.lor x y |] = Z.lor [|x|] [|y|].
Proof.
unfold ZnZ.lor,int31_ops. unfold lor31.
rewrite phi_phi_inv.
apply Z.mod_small; split; trivial.
- apply Z.lor_nonneg; split; apply phi_bounded.
- apply Z.log2_lt_cancel. rewrite Z.log2_pow2 by easy.
rewrite Z.log2_lor; try apply phi_bounded.
apply Z.max_lub_lt; apply log2_phi_bounded.
Qed.
Lemma spec_land x y : [| ZnZ.land x y |] = Z.land [|x|] [|y|].
Proof.
unfold ZnZ.land, int31_ops. unfold land31.
rewrite phi_phi_inv.
apply Z.mod_small; split; trivial.
- apply Z.land_nonneg; left; apply phi_bounded.
- apply Z.log2_lt_cancel. rewrite Z.log2_pow2 by easy.
eapply Z.le_lt_trans.
apply Z.log2_land; try apply phi_bounded.
apply Z.min_lt_iff; left; apply log2_phi_bounded.
Qed.
Lemma spec_lxor x y : [| ZnZ.lxor x y |] = Z.lxor [|x|] [|y|].
Proof.
unfold ZnZ.lxor, int31_ops. unfold lxor31.
rewrite phi_phi_inv.
apply Z.mod_small; split; trivial.
- apply Z.lxor_nonneg; split; intros; apply phi_bounded.
- apply Z.log2_lt_cancel. rewrite Z.log2_pow2 by easy.
eapply Z.le_lt_trans.
apply Z.log2_lxor; try apply phi_bounded.
apply Z.max_lub_lt; apply log2_phi_bounded.
Qed.
Global Instance int31_specs : ZnZ.Specs int31_ops := {
spec_to_Z := phi_bounded;
spec_of_pos := positive_to_int31_spec;
spec_zdigits := spec_zdigits;
spec_more_than_1_digit := spec_more_than_1_digit;
spec_0 := spec_0;
spec_1 := spec_1;
spec_m1 := spec_m1;
spec_compare := spec_compare;
spec_eq0 := spec_eq0;
spec_opp_c := spec_opp_c;
spec_opp := spec_opp;
spec_opp_carry := spec_opp_carry;
spec_succ_c := spec_succ_c;
spec_add_c := spec_add_c;
spec_add_carry_c := spec_add_carry_c;
spec_succ := spec_succ;
spec_add := spec_add;
spec_add_carry := spec_add_carry;
spec_pred_c := spec_pred_c;
spec_sub_c := spec_sub_c;
spec_sub_carry_c := spec_sub_carry_c;
spec_pred := spec_pred;
spec_sub := spec_sub;
spec_sub_carry := spec_sub_carry;
spec_mul_c := spec_mul_c;
spec_mul := spec_mul;
spec_square_c := spec_square_c;
spec_div21 := spec_div21;
spec_div_gt := fun a b _ => spec_div a b;
spec_div := spec_div;
spec_modulo_gt := fun a b _ => spec_mod a b;
spec_modulo := spec_mod;
spec_gcd_gt := fun a b _ => spec_gcd a b;
spec_gcd := spec_gcd;
spec_head00 := spec_head00;
spec_head0 := spec_head0;
spec_tail00 := spec_tail00;
spec_tail0 := spec_tail0;
spec_add_mul_div := spec_add_mul_div;
spec_pos_mod := spec_pos_mod;
spec_is_even := spec_is_even;
spec_sqrt2 := spec_sqrt2;
spec_sqrt := spec_sqrt;
spec_lor := spec_lor;
spec_land := spec_land;
spec_lxor := spec_lxor }.
End Int31_Specs.
Module Int31Cyclic <: CyclicType.
Definition t := int31.
Definition ops := int31_ops.
Definition specs := int31_specs.
End Int31Cyclic.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND2_BLACKBOX_V
`define SKY130_FD_SC_HD__NAND2_BLACKBOX_V
/**
* nand2: 2-input NAND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND2_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module sky130_fd_io__top_gpio_ovtv2 ( IN, IN_H, TIE_HI_ESD, TIE_LO_ESD, AMUXBUS_A,
AMUXBUS_B, PAD, PAD_A_ESD_0_H, PAD_A_ESD_1_H, PAD_A_NOESD_H,
ANALOG_EN, ANALOG_POL, ANALOG_SEL, DM, ENABLE_H, ENABLE_INP_H, ENABLE_VDDA_H, ENABLE_VDDIO, ENABLE_VSWITCH_H, HLD_H_N,
HLD_OVR, IB_MODE_SEL, INP_DIS, OE_N, OUT, SLOW, SLEW_CTL, VTRIP_SEL, HYS_TRIM, VINREF );
input OUT;
input OE_N;
input HLD_H_N;
input ENABLE_H;
input ENABLE_INP_H;
input ENABLE_VDDA_H;
input ENABLE_VDDIO;
input ENABLE_VSWITCH_H;
input INP_DIS;
input VTRIP_SEL;
input HYS_TRIM;
input SLOW;
input [1:0] SLEW_CTL;
input HLD_OVR;
input ANALOG_EN;
input ANALOG_SEL;
input ANALOG_POL;
input [2:0] DM;
input [1:0] IB_MODE_SEL;
input VINREF;
supply1 vddio;
supply1 vddio_q;
supply1 vdda;
supply1 vccd;
supply1 vswitch;
supply1 vcchib;
supply1 vpb;
supply1 vpbhib;
supply0 vssd;
supply0 vssio;
supply0 vssio_q;
supply0 vssa;
inout PAD;
inout PAD_A_NOESD_H,PAD_A_ESD_0_H,PAD_A_ESD_1_H;
inout AMUXBUS_A;
inout AMUXBUS_B;
output IN;
output IN_H;
output TIE_HI_ESD, TIE_LO_ESD;
wire hld_h_n_del;
wire hld_h_n_buf;
reg [2:0] dm_final;
reg [1:0] slew_ctl_final;
reg slow_final, vtrip_sel_final, inp_dis_final, out_final, oe_n_final, hld_ovr_final, hys_trim_final, analog_en_final,analog_en_vdda, analog_en_vswitch,analog_en_vddio_q;
reg [1:0] ib_mode_sel_final;
wire [2:0] dm_del;
wire [1:0] slew_ctl_del;
wire [1:0] ib_mode_sel_del;
wire slow_del, vtrip_sel_del, inp_dis_del, out_del, oe_n_del, hld_ovr_del, hys_trim_del;
wire [2:0] dm_buf;
wire [1:0] slew_ctl_buf;
wire [1:0] ib_mode_sel_buf;
wire slow_buf, vtrip_sel_buf, inp_dis_buf, out_buf, oe_n_buf, hld_ovr_buf, hys_trim_buf;
reg notifier_dm, notifier_slow, notifier_oe_n, notifier_out, notifier_vtrip_sel, notifier_hld_ovr, notifier_inp_dis;
reg notifier_slew_ctl, notifier_ib_mode_sel, notifier_hys_trim;
reg notifier_enable_h, notifier, dummy_notifier1;
assign hld_h_n_buf = HLD_H_N;
assign hld_ovr_buf = HLD_OVR;
assign dm_buf = DM;
assign inp_dis_buf = INP_DIS;
assign vtrip_sel_buf = VTRIP_SEL;
assign slow_buf = SLOW;
assign oe_n_buf = OE_N;
assign out_buf = OUT;
assign ib_mode_sel_buf = IB_MODE_SEL;
assign slew_ctl_buf = SLEW_CTL;
assign hys_trim_buf = HYS_TRIM;
wire pwr_good_amux = 1;
wire pwr_good_inpbuff_hv = 1;
wire pwr_good_inpbuff_lv = 1;
wire pwr_good_output_driver = 1;
wire pwr_good_hold_mode = 1;
wire pwr_good_hold_ovr_mode = 1;
wire pwr_good_active_mode = 1;
wire pwr_good_hold_mode_vdda = 1;
wire pwr_good_active_mode_vdda = 1;
wire pwr_good_amux_vccd = 1;
wire pwr_good_analog_en_vdda = 1;
wire pwr_good_analog_en_vddio_q = 1;
wire pwr_good_analog_en_vswitch = 1;
parameter MAX_WARNING_COUNT = 100;
wire pad_tristate = oe_n_final === 1 || dm_final === 3'b000 || dm_final === 3'b001;
wire x_on_pad = !pwr_good_output_driver
|| (dm_final !== 3'b000 && dm_final !== 3'b001 && oe_n_final===1'bx)
|| (^dm_final[2:0] === 1'bx && oe_n_final===1'b0)
|| (slow_final===1'bx && dm_final !== 3'b000 && dm_final !== 3'b001 && oe_n_final===1'b0)
|| (slow_final===1'b1 && ^slew_ctl_final[1:0] ===1'bx && dm_final === 3'b100 && oe_n_final===1'b0);
`ifdef SKY130_FD_IO_TOP_GPIO_OVTV2_SLOW_BEHV
parameter SLOW_1_DELAY= 70 ;
parameter SLOW_0_DELAY= 40;
`else
parameter SLOW_1_DELAY= 0;
parameter SLOW_0_DELAY= 0;
`endif
`ifdef SKY130_FD_IO_TOP_GPIO_OVTV2_SLEW_BEHV
parameter SLEW_00_DELAY= 127 ;
parameter SLEW_01_DELAY= 109;
parameter SLEW_10_DELAY= 193;
parameter SLEW_11_DELAY= 136;
`else
parameter SLEW_00_DELAY= 0 ;
parameter SLEW_01_DELAY= 0;
parameter SLEW_10_DELAY= 0;
parameter SLEW_11_DELAY= 0;
`endif
integer slow_1_delay,slow_0_delay,slow_delay,slew_00_delay,slew_01_delay,slew_10_delay,slew_11_delay;
initial slow_1_delay = SLOW_1_DELAY;
initial slow_0_delay = SLOW_0_DELAY;
initial slew_00_delay = SLEW_00_DELAY;
initial slew_01_delay = SLEW_01_DELAY;
initial slew_10_delay = SLEW_10_DELAY;
initial slew_11_delay = SLEW_11_DELAY;
always @(*)
begin
if (SLOW===1)
begin
if (DM[2]===1 && DM[1]===0 && DM[0]===0)
begin
`ifdef SKY130_FD_IO_TOP_GPIO_OVTV2_SLEW_BEHV
if (SLEW_CTL[1] ===0 && SLEW_CTL[0] ===0)
slow_delay = slew_00_delay;
else if (SLEW_CTL[1] ===0 && SLEW_CTL[0] ===1)
slow_delay = slew_01_delay;
else if (SLEW_CTL[1] ===1 && SLEW_CTL[0] ===0)
slow_delay = slew_10_delay;
else if (SLEW_CTL[1] ===1 && SLEW_CTL[0] ===1)
slow_delay = slew_11_delay;
`else
slow_delay = slow_1_delay;
`endif
end
else
slow_delay = slow_1_delay;
end
else
slow_delay = slow_0_delay;
end
bufif1 (pull1, strong0) #slow_delay dm2 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b010));
bufif1 (strong1, pull0) #slow_delay dm3 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b011));
bufif1 (highz1, strong0) #slow_delay dm4 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b100));
bufif1 (strong1, highz0) #slow_delay dm5 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b101));
bufif1 (strong1, strong0) #slow_delay dm6 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b110));
bufif1 (pull1, pull0) #slow_delay dm7 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b111));
tran pad_esd_1 (PAD,PAD_A_NOESD_H);
tran pad_esd_2 (PAD,PAD_A_ESD_0_H);
tran pad_esd_3 (PAD,PAD_A_ESD_1_H);
wire x_on_in_hv = (ENABLE_H===0 && ^ENABLE_INP_H===1'bx)
|| (inp_dis_final===1'bx && ^dm_final[2:0]!==1'bx && dm_final !== 3'b000)
|| (^ENABLE_H===1'bx)
|| (inp_dis_final===0 && ^dm_final[2:0] === 1'bx)
|| (^ib_mode_sel_final===1'bx && inp_dis_final===0 && dm_final !== 3'b000)
|| (vtrip_sel_final===1'bx && inp_dis_final===0 && dm_final !== 3'b000 && ib_mode_sel_final===2'b00)
|| (^ENABLE_VDDIO===1'bx && inp_dis_final===0 && dm_final !== 3'b000 && ib_mode_sel_final===2'b01)
|| (ib_mode_sel_final[1]===1'b1 && VINREF !== 1'b1 && inp_dis_final===0 && dm_final !== 3'b000)
|| (ib_mode_sel_final[1]===1'b1 && hys_trim_final===1'bx && inp_dis_final===0 && dm_final !== 3'b000);
wire x_on_in_lv = (ENABLE_H===0 && ^ENABLE_VDDIO===1'bx)
|| (ENABLE_H===0 && ^ENABLE_INP_H===1'bx)
|| (inp_dis_final===1'bx && ^dm_final[2:0]!==1'bx && dm_final !== 3'b000)
|| (^ENABLE_H===1'bx)
|| (inp_dis_final===0 && ^dm_final[2:0] === 1'bx)
|| (^ib_mode_sel_final===1'bx && inp_dis_final===0 && dm_final !== 3'b000)
|| (vtrip_sel_final===1'bx && inp_dis_final===0 && dm_final !== 3'b000 && ib_mode_sel_final===2'b00)
|| (^ENABLE_VDDIO===1'bx && inp_dis_final===0 && dm_final !== 3'b000 )
|| (ib_mode_sel_final[1]===1'b1 && VINREF !== 1'b1 && inp_dis_final===0 && dm_final !== 3'b000)
|| (ib_mode_sel_final[1]===1'b1 && hys_trim_final===1'bx && inp_dis_final===0 && dm_final !== 3'b000);
wire disable_inp_buff = ENABLE_H===1 ? (dm_final===3'b000 || inp_dis_final===1) : ENABLE_INP_H===0;
assign IN_H = (x_on_in_hv===1 || pwr_good_inpbuff_hv===0) ? 1'bx : (disable_inp_buff===1 ? 0 : (^PAD===1'bx ? 1'bx : PAD));
wire disable_inp_buff_lv = ENABLE_H===1 ? (dm_final===3'b000 || inp_dis_final===1) : ENABLE_VDDIO===0;
assign IN = (x_on_in_lv ===1 || pwr_good_inpbuff_lv===0) ? 1'bx : (disable_inp_buff_lv===1 ? 0 : (^PAD===1'bx ? 1'bx : PAD));
assign TIE_HI_ESD = vddio===1'b1 ? 1'b1 : 1'bx;
assign TIE_LO_ESD = vssio===1'b0 ? 1'b0 : 1'bx;
wire functional_mode_amux = (pwr_good_analog_en_vdda ===1 && pwr_good_analog_en_vddio_q ===1 && pwr_good_analog_en_vswitch ===1 );
wire x_on_analog_en_vdda = (pwr_good_analog_en_vdda !==1
|| (functional_mode_amux ==1 && (ENABLE_H !==0 && ^hld_h_n_buf === 1'bx) || (hld_h_n_buf!== 0 && ^ENABLE_H=== 1'bx) || pwr_good_amux_vccd !==1 )
|| (functional_mode_amux ==1 && (hld_h_n_buf ===1 && ENABLE_H===1 && ^ANALOG_EN === 1'bx && ENABLE_VDDA_H ===1 && ENABLE_VSWITCH_H===1 ) || (hld_h_n_buf ===1 && ENABLE_H===1 && ANALOG_EN ===0 && ^ENABLE_VDDA_H ===1'bx) ));
wire zero_on_analog_en_vdda = ( (pwr_good_analog_en_vdda ===1 && ENABLE_VDDA_H ===0)
|| (pwr_good_analog_en_vdda ===1 && pwr_good_analog_en_vddio_q ===1 && hld_h_n_buf===0)
|| (pwr_good_analog_en_vdda ===1 && pwr_good_analog_en_vddio_q ===1 && ENABLE_H===0)
|| (pwr_good_analog_en_vdda ===1 && pwr_good_analog_en_vddio_q ===1 && pwr_good_amux_vccd && ANALOG_EN===0) );
wire x_on_analog_en_vddio_q = ( pwr_good_analog_en_vddio_q !==1
|| (functional_mode_amux ==1 && (ENABLE_H !==0 && ^hld_h_n_buf === 1'bx) || (hld_h_n_buf!== 0 && ^ENABLE_H=== 1'bx) || pwr_good_amux_vccd !==1 )
|| (functional_mode_amux ==1 && (hld_h_n_buf ===1 && ENABLE_H===1 && ^ANALOG_EN === 1'bx && ENABLE_VDDA_H ===1 && ENABLE_VSWITCH_H===1 ) ));
wire zero_on_analog_en_vddio_q = ( (pwr_good_analog_en_vddio_q ===1 && hld_h_n_buf===0)
|| (pwr_good_analog_en_vddio_q ===1 && ENABLE_H===0)
|| (pwr_good_analog_en_vddio_q ===1 && pwr_good_amux_vccd && ANALOG_EN===0) );
wire x_on_analog_en_vswitch = (pwr_good_analog_en_vswitch !==1
|| (functional_mode_amux ==1 && (ENABLE_H !==0 && ^hld_h_n_buf === 1'bx) || (hld_h_n_buf!== 0 && ^ENABLE_H=== 1'bx) || pwr_good_amux_vccd !==1 )
|| (functional_mode_amux ==1 && (hld_h_n_buf ===1 && ENABLE_H===1 && ^ANALOG_EN === 1'bx && ENABLE_VDDA_H ===1 && ENABLE_VSWITCH_H===1 ) || (hld_h_n_buf ===1 && ENABLE_H===1 && ANALOG_EN ===0 && ^ENABLE_VSWITCH_H ===1'bx) ));
wire zero_on_analog_en_vswitch = ( (pwr_good_analog_en_vswitch ===1 && ENABLE_VSWITCH_H ===0)
|| (pwr_good_analog_en_vswitch ===1 && pwr_good_analog_en_vddio_q ===1 && hld_h_n_buf===0)
|| (pwr_good_analog_en_vswitch ===1 && pwr_good_analog_en_vddio_q ===1 && ENABLE_H===0)
|| (pwr_good_analog_en_vswitch ===1 && pwr_good_analog_en_vddio_q ===1 && pwr_good_amux_vccd && ANALOG_EN===0) );
always @(*)
begin : LATCH_dm
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
dm_final <= 3'bxxx;
end
else if (ENABLE_H===0)
begin
dm_final <= 3'b000;
end
else if (hld_h_n_buf===1)
begin
dm_final <= (^dm_buf[2:0] === 1'bx || !pwr_good_active_mode) ? 3'bxxx : dm_buf;
end
end
always @(notifier_enable_h or notifier_dm)
begin
disable LATCH_dm; dm_final <= 3'bxxx;
end
always @(*)
begin : LATCH_inp_dis
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
inp_dis_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
inp_dis_final <= 1'b1;
end
else if (hld_h_n_buf===1)
begin
inp_dis_final <= (^inp_dis_buf === 1'bx || !pwr_good_active_mode) ? 1'bx : inp_dis_buf;
end
end
always @(notifier_enable_h or notifier_inp_dis)
begin
disable LATCH_inp_dis; inp_dis_final <= 1'bx;
end
always @(*)
begin : LATCH_ib_mode_sel
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
ib_mode_sel_final <= 2'bxx;
end
else if (ENABLE_H===0)
begin
ib_mode_sel_final <= 2'b00;
end
else if (hld_h_n_buf===1)
begin
ib_mode_sel_final <= (^ib_mode_sel_buf[1:0] === 1'bx || !pwr_good_active_mode) ? 2'bxx : ib_mode_sel_buf;
end
end
always @(notifier_enable_h or notifier_ib_mode_sel)
begin
disable LATCH_ib_mode_sel; ib_mode_sel_final <= 2'bxx;
end
always @(*)
begin : LATCH_slew_ctl_final
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
slew_ctl_final <= 2'bxx;
end
else if (ENABLE_H===0)
begin
slew_ctl_final <= 2'b00;
end
else if (hld_h_n_buf===1)
begin
slew_ctl_final <= (^slew_ctl_buf[1:0] === 1'bx || !pwr_good_active_mode) ? 2'bxx : slew_ctl_buf;
end
end
always @(notifier_enable_h or notifier_slew_ctl)
begin
disable LATCH_slew_ctl_final; slew_ctl_final <= 2'bxx;
end
always @(*)
begin : LATCH_vtrip_sel
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
vtrip_sel_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
vtrip_sel_final <= 1'b0;
end
else if (hld_h_n_buf===1)
begin
vtrip_sel_final <= (^vtrip_sel_buf === 1'bx || !pwr_good_active_mode) ? 1'bx : vtrip_sel_buf;
end
end
always @(notifier_enable_h or notifier_vtrip_sel)
begin
disable LATCH_vtrip_sel; vtrip_sel_final <= 1'bx;
end
always @(*)
begin : LATCH_hys_trim
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
hys_trim_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
hys_trim_final <= 1'b0;
end
else if (hld_h_n_buf===1)
begin
hys_trim_final <= (^hys_trim_buf === 1'bx || !pwr_good_active_mode) ? 1'bx : hys_trim_buf;
end
end
always @(notifier_enable_h or notifier_hys_trim)
begin
disable LATCH_hys_trim; hys_trim_final <= 1'bx;
end
always @(*)
begin : LATCH_slow
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
slow_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
slow_final <= 1'b0;
end
else if (hld_h_n_buf===1)
begin
slow_final <= (^slow_buf === 1'bx || !pwr_good_active_mode) ? 1'bx : slow_buf;
end
end
always @(notifier_enable_h or notifier_slow)
begin
disable LATCH_slow; slow_final <= 1'bx;
end
always @(*)
begin : LATCH_hld_ovr
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
hld_ovr_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
hld_ovr_final <= 1'b0;
end
else if (hld_h_n_buf===1)
begin
hld_ovr_final <= (^hld_ovr_buf === 1'bx || !pwr_good_active_mode) ? 1'bx : hld_ovr_buf;
end
end
always @(notifier_enable_h or notifier_hld_ovr)
begin
disable LATCH_hld_ovr; hld_ovr_final <= 1'bx;
end
always @(*)
begin : LATCH_oe_n
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && (^hld_h_n_buf===1'bx || (hld_h_n_buf===0 && hld_ovr_final===1'bx)|| (hld_h_n_buf===1 && hld_ovr_final===1'bx))))
begin
oe_n_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
oe_n_final <= 1'b1;
end
else if (hld_h_n_buf===1 || hld_ovr_final===1)
begin
oe_n_final <= (^oe_n_buf === 1'bx || !pwr_good_hold_ovr_mode) ? 1'bx : oe_n_buf;
end
end
always @(notifier_enable_h or notifier_oe_n)
begin
disable LATCH_oe_n; oe_n_final <= 1'bx;
end
always @(*)
begin : LATCH_out
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && (^hld_h_n_buf===1'bx ||(hld_h_n_buf===0 && hld_ovr_final===1'bx)||(hld_h_n_buf===1 && hld_ovr_final===1'bx))))
begin
out_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
out_final <= 1'b1;
end
else if (hld_h_n_buf===1 || hld_ovr_final===1)
begin
out_final <= (^out_buf === 1'bx || !pwr_good_hold_ovr_mode) ? 1'bx : out_buf;
end
end
always @(notifier_enable_h or notifier_out)
begin
disable LATCH_out; out_final <= 1'bx;
end
always @(*)
begin
if (x_on_analog_en_vdda ===1 )
begin
analog_en_vdda <= 1'bx;
end
else if ( zero_on_analog_en_vdda ===1 )
begin
analog_en_vdda <= 1'b0;
end
else if (x_on_analog_en_vdda !==1 && zero_on_analog_en_vdda !==1)
begin
analog_en_vdda <= ANALOG_EN;
end
if (x_on_analog_en_vddio_q ===1 )
begin
analog_en_vddio_q <= 1'bx;
end
else if ( zero_on_analog_en_vddio_q ===1 )
begin
analog_en_vddio_q <= 1'b0;
end
else if ( x_on_analog_en_vddio_q !==1 && zero_on_analog_en_vddio_q !==1)
begin
analog_en_vddio_q <= ANALOG_EN;
end
if (x_on_analog_en_vswitch ===1 )
begin
analog_en_vswitch <= 1'bx;
end
else if ( zero_on_analog_en_vswitch ===1 )
begin
analog_en_vswitch <= 1'b0;
end
else if (x_on_analog_en_vswitch !==1 && zero_on_analog_en_vswitch !==1)
begin
analog_en_vswitch <= ANALOG_EN;
end
if ( (analog_en_vswitch ===1'bx && analog_en_vdda ===1'bx) || (analog_en_vswitch ===1'bx && analog_en_vddio_q ===1'bx) || (analog_en_vddio_q ===1'bx && analog_en_vdda ===1'bx ) )
begin
analog_en_final <= 1'bx;
end
else if (analog_en_vdda ===1'bx && (analog_en_vddio_q ===1 ||analog_en_vswitch===1 ))
begin
analog_en_final <= 1'bx;
end
else if (analog_en_vddio_q ===1'bx && (analog_en_vdda ===1 ||analog_en_vswitch===1 ))
begin
analog_en_final <= 1'bx;
end
else if (analog_en_vswitch===1'bx && (analog_en_vdda ===1 || analog_en_vddio_q ===1 ))
begin
analog_en_final <= 1'bx;
end
else if ((analog_en_vdda ===0 && analog_en_vddio_q ===0 )|| (analog_en_vdda ===0 && analog_en_vswitch===0 ) || (analog_en_vddio_q ===0 && analog_en_vswitch===0 ))
begin
analog_en_final <=0;
end
else if (analog_en_vdda ===1 && analog_en_vddio_q ===1 && analog_en_vswitch ===1)
begin
analog_en_final <=1;
end
end
wire [2:0] amux_select = {ANALOG_SEL, ANALOG_POL, out_buf};
wire invalid_controls_amux = (analog_en_final===1'bx && inp_dis_final===1)
|| !pwr_good_amux
|| (analog_en_final===1 && ^amux_select[2:0] === 1'bx && inp_dis_final===1);
wire enable_pad_amuxbus_a = invalid_controls_amux ? 1'bx : (amux_select===3'b001 || amux_select===3'b010) && (analog_en_final===1);
wire enable_pad_amuxbus_b = invalid_controls_amux ? 1'bx : (amux_select===3'b101 || amux_select===3'b110) && (analog_en_final===1);
wire enable_pad_vssio_q = invalid_controls_amux ? 1'bx : (amux_select===3'b100 || amux_select===3'b000) && (analog_en_final===1);
wire enable_pad_vddio_q = invalid_controls_amux ? 1'bx : (amux_select===3'b011 || amux_select===3'b111) && (analog_en_final===1);
tranif1 pad_amuxbus_a (PAD, AMUXBUS_A, enable_pad_amuxbus_a);
tranif1 pad_amuxbus_b (PAD, AMUXBUS_B, enable_pad_amuxbus_b);
bufif1 pad_vddio_q (PAD, vddio_q, enable_pad_vddio_q);
bufif1 pad_vssio_q (PAD, vssio_q, enable_pad_vssio_q);
reg dis_err_msgs;
integer msg_count_pad,msg_count_pad1,msg_count_pad2,msg_count_pad3,msg_count_pad4,msg_count_pad5,msg_count_pad6,msg_count_pad7,msg_count_pad8,msg_count_pad9,msg_count_pad10,msg_count_pad11,msg_count_pad12;
initial
begin
dis_err_msgs = 1'b1;
msg_count_pad = 0;
msg_count_pad1 = 0;
msg_count_pad2 = 0;
msg_count_pad3 = 0;
msg_count_pad4 = 0;
msg_count_pad5 = 0;
msg_count_pad6 = 0;
msg_count_pad7 = 0;
msg_count_pad8 = 0;
msg_count_pad9 = 0;
msg_count_pad10 = 0;
msg_count_pad11 = 0;
msg_count_pad12 = 0;
`ifdef SKY130_FD_IO_TOP_GPIO_OVTV2_DIS_ERR_MSGS
`else
#1;
dis_err_msgs = 1'b0;
`endif
end
wire #100 error_enable_vddio = (ENABLE_VDDIO===0 && ENABLE_H===1);
event event_error_enable_vddio;
always @(error_enable_vddio)
begin
if (!dis_err_msgs)
begin
if (error_enable_vddio===1)
begin
msg_count_pad = msg_count_pad + 1;
->event_error_enable_vddio;
if (msg_count_pad <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : Enable_h (= %b) and ENABLE_VDDIO (= %b) are complement of each \other. This is an illegal combination as ENABLE_VDDIO and ENABLE_H are the same input signals IN different power \domains %m", ENABLE_H, ENABLE_VDDIO, $stime);
end
else
if (msg_count_pad == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vdda = ( vdda===1 && vddio_q !==1 && ENABLE_VDDA_H===1 );
event event_error_vdda;
always @(error_vdda)
begin
if (!dis_err_msgs)
begin
if (error_vdda===1)
begin
msg_count_pad1 = msg_count_pad1 + 1;
->event_error_vdda;
if (msg_count_pad1 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ENABLE_VDDA_H (= %b) cannot be 1 when vdda (= %b) and vddio_q (= %b) %m",ENABLE_VDDA_H, vdda,vddio_q,$stime);
end
else
if (msg_count_pad1 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vdda2 = ( vdda===1 && vddio_q ===1 && vswitch !==1 && ENABLE_H===1 && hld_h_n_buf ===1 && vccd===1 && ANALOG_EN ===1 );
event event_error_vdda2;
always @(error_vdda2)
begin
if (!dis_err_msgs)
begin
if (error_vdda2===1)
begin
msg_count_pad2 = msg_count_pad2 + 1;
->event_error_vdda2;
if (msg_count_pad2 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ANALOG_EN (= %b) cannot be 1 when vdda (= %b) , vddio_q (= %b) , vswitch(= %b), ENABLE_H (= %b),hld_h_n_buf (= %b) and vccd (= %b) %m",ANALOG_EN,vdda,vddio_q,vswitch,ENABLE_H,hld_h_n_buf,vccd,$stime);
end
else
if (msg_count_pad2 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vdda3 = ( vdda===1 && vddio_q ===1 && vswitch !==1 && ENABLE_H===1 && hld_h_n_buf ===1 && vccd !==1 );
event event_error_vdda3;
always @(error_vdda3)
begin
if (!dis_err_msgs)
begin
if (error_vdda3===1)
begin
msg_count_pad3 = msg_count_pad3 + 1;
->event_error_vdda3;
if (msg_count_pad3 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : vccd (= %b) cannot be any value other than 1 when vdda (= %b) , vddio_q (= %b) , vswitch(= %b), ENABLE_H (= %b) and hld_h_n_buf (= %b) %m",vccd,vdda,vddio_q,vswitch,ENABLE_H,hld_h_n_buf,$stime);
end
else
if (msg_count_pad3 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vswitch1 = (vdda !==1 && vddio_q !==1 && vswitch ===1 && (ENABLE_VSWITCH_H===1)) ;
event event_error_vswitch1;
always @(error_vswitch1)
begin
if (!dis_err_msgs)
begin
if (error_vswitch1===1)
begin
msg_count_pad4 = msg_count_pad4 + 1;
->event_error_vswitch1;
if (msg_count_pad4 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ENABLE_VSWITCH_H (= %b) cannot be 1 when vdda (= %b) , vddio_q (= %b) & vswitch(= %b) %m",ENABLE_VSWITCH_H,vdda,vddio_q,vswitch,$stime);
end
else
if (msg_count_pad4 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vswitch2 = (vdda !==1 && vddio_q !==1 && vswitch ===1 && vccd===1 && ANALOG_EN===1);
event event_error_vswitch2;
always @(error_vswitch2)
begin
if (!dis_err_msgs)
begin
if (error_vswitch2===1)
begin
msg_count_pad5 = msg_count_pad5 + 1;
->event_error_vswitch2;
if (msg_count_pad5 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ANALOG_EN (= %b) cannot be 1 when vdda (= %b) , vddio_q (= %b) , vswitch(= %b) & vccd(= %b) %m",ANALOG_EN,vdda,vddio_q,vswitch,vccd,$stime);
end
else
if (msg_count_pad5 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vswitch3 = (vdda ===1 && vddio_q !==1 && vswitch ===1 && ENABLE_VSWITCH_H===1);
event event_error_vswitch3;
always @(error_vswitch3)
begin
if (!dis_err_msgs)
begin
if (error_vswitch3===1)
begin
msg_count_pad6 = msg_count_pad6 + 1;
->event_error_vswitch3;
if (msg_count_pad6 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ENABLE_VSWITCH_H(= %b) cannot be 1 when vdda (= %b) , vddio_q (= %b) & vswitch(= %b) %m",ENABLE_VSWITCH_H,vdda,vddio_q,vswitch,$stime);
end
else
if (msg_count_pad6 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vswitch4 = (vdda !==1 && vddio_q ===1 && vswitch ===1 && ENABLE_VSWITCH_H===1);
event event_error_vswitch4;
always @(error_vswitch4)
begin
if (!dis_err_msgs)
begin
if (error_vswitch4===1)
begin
msg_count_pad7 = msg_count_pad7 + 1;
->event_error_vswitch4;
if (msg_count_pad7 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ENABLE_VSWITCH_H(= %b) cannot be 1 when vdda (= %b) , vddio_q (= %b) & vswitch(= %b) %m",ENABLE_VSWITCH_H,vdda,vddio_q,vswitch,$stime);
end
else
if (msg_count_pad7 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vswitch5 = (vdda !==1 && vddio_q ===1 && vswitch ===1 && ENABLE_H ===1 && hld_h_n_buf ===1 && vccd ===1 && ANALOG_EN===1);
event event_error_vswitch5;
always @(error_vswitch5)
begin
if (!dis_err_msgs)
begin
if (error_vswitch5===1)
begin
msg_count_pad8 = msg_count_pad8 + 1;
->event_error_vswitch5;
if (msg_count_pad8 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ANALOG_EN(= %b) cannot be 1 when vdda (= %b) , vddio_q (= %b) , vswitch(= %b),ENABLE_H (= %b),hld_h_n_buf (= %b) and vccd (= %b) %m",ANALOG_EN,vdda,vddio_q,vswitch,ENABLE_H,hld_h_n_buf,vccd,$stime);
end
else
if (msg_count_pad8 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vddio_q1 = (vdda !==1 && vddio_q ===1 && vswitch !==1 && ENABLE_H ===1 && hld_h_n_buf ===1 && vccd!==1);
event event_error_vddio_q1;
always @(error_vddio_q1)
begin
if (!dis_err_msgs)
begin
if (error_vddio_q1===1)
begin
msg_count_pad9 = msg_count_pad9 + 1;
->event_error_vddio_q1;
if (msg_count_pad9 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : vccd(= %b) cannot be any value other than 1 when vdda (= %b) , vddio_q (= %b) , vswitch(= %b),ENABLE_H (= %b) and hld_h_n_buf (= %b) %m",vccd,vdda,vddio_q,vswitch,ENABLE_H,hld_h_n_buf,$stime);
end
else
if (msg_count_pad9 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vddio_q2 = (vdda !==1 && vddio_q ===1 && vswitch !==1 && ENABLE_H ===1 && hld_h_n_buf ===1 && vccd ===1 && ANALOG_EN===1);
event event_error_vddio_q2;
always @(error_vddio_q2)
begin
if (!dis_err_msgs)
begin
if (error_vddio_q2===1)
begin
msg_count_pad10 = msg_count_pad10 + 1;
->event_error_vddio_q2;
if (msg_count_pad10 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ANALOG_EN(= %b) cannot be 1 when vdda (= %b) , vddio_q (= %b) , vswitch(= %b),ENABLE_H (= %b) , hld_h_n_buf (= %b) && vccd (= %b) %m",ANALOG_EN, vdda,vddio_q,vswitch,ENABLE_H,hld_h_n_buf,vccd,$stime);
end
else
if (msg_count_pad10 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_supply_good = ( vdda ===1 && vddio_q ===1 && vswitch ===1 && ENABLE_H ===1 && hld_h_n_buf ===1 && vccd ===1 && ANALOG_EN===1 && ENABLE_VSWITCH_H !==1 && ENABLE_VSWITCH_H !==0 );
event event_error_supply_good;
always @(error_supply_good)
begin
if (!dis_err_msgs)
begin
if (error_supply_good===1)
begin
msg_count_pad11 = msg_count_pad11 + 1;
->event_error_supply_good;
if (msg_count_pad11 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ENABLE_VSWITCH_H(= %b) should be either 1 or 0 when vdda (= %b) , vddio_q (= %b) , vswitch(= %b), ENABLE_H (= %b), hld_h_n_buf (= %b) ,vccd (= %b) and ANALOG_EN(= %b) %m",ENABLE_VSWITCH_H, vdda,vddio_q,vswitch,ENABLE_H,hld_h_n_buf,vccd,ANALOG_EN,$stime);
end
else
if (msg_count_pad11 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vdda_vddioq_vswitch2 = ( vdda ===1 && vddio_q ===1 && vswitch ===1 && ENABLE_H ===1 && hld_h_n_buf ===1 && vccd ===1 && ANALOG_EN===1 && ENABLE_VDDA_H !==1 && ENABLE_VDDA_H !==0 );
event event_error_vdda_vddioq_vswitch2;
always @(error_vdda_vddioq_vswitch2)
begin
if (!dis_err_msgs)
begin
if (error_vdda_vddioq_vswitch2===1)
begin
msg_count_pad12 = msg_count_pad12 + 1;
->event_error_vdda_vddioq_vswitch2;
if (msg_count_pad12 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ENABLE_VDDA_H(= %b) should be either 1 or 0 when vdda (= %b) , vddio_q (= %b) , vswitch(= %b), ENABLE_H (= %b), hld_h_n_buf (= %b) ,vccd (= %b) and ANALOG_EN(= %b) %m",ENABLE_VDDA_H, vdda,vddio_q,vswitch,ENABLE_H,hld_h_n_buf,vccd,ANALOG_EN,$stime);
end
else
if (msg_count_pad12 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
endmodule
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