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/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_regc.v
*
* Date : 2012-11
*
* Description : Controller for Register Map Memory
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_regc(
rstn,
sw_clk,
/* Goes to port 0 of REG */
reg_rd_req_port0,
reg_rd_dv_port0,
reg_rd_addr_port0,
reg_rd_data_port0,
reg_rd_bytes_port0,
reg_rd_qos_port0,
/* Goes to port 1 of REG */
reg_rd_req_port1,
reg_rd_dv_port1,
reg_rd_addr_port1,
reg_rd_data_port1,
reg_rd_bytes_port1,
reg_rd_qos_port1
);
input rstn;
input sw_clk;
input reg_rd_req_port0;
output reg_rd_dv_port0;
input[31:0] reg_rd_addr_port0;
output[1023:0] reg_rd_data_port0;
input[7:0] reg_rd_bytes_port0;
input [3:0] reg_rd_qos_port0;
input reg_rd_req_port1;
output reg_rd_dv_port1;
input[31:0] reg_rd_addr_port1;
output[1023:0] reg_rd_data_port1;
input[7:0] reg_rd_bytes_port1;
input[3:0] reg_rd_qos_port1;
wire [3:0] rd_qos;
reg [1023:0] rd_data;
wire [31:0] rd_addr;
wire [7:0] rd_bytes;
reg rd_dv;
wire rd_req;
processing_system7_bfm_v2_0_5_arb_rd reg_read_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(reg_rd_qos_port0),
.qos2(reg_rd_qos_port1),
.prt_req1(reg_rd_req_port0),
.prt_req2(reg_rd_req_port1),
.prt_data1(reg_rd_data_port0),
.prt_data2(reg_rd_data_port1),
.prt_addr1(reg_rd_addr_port0),
.prt_addr2(reg_rd_addr_port1),
.prt_bytes1(reg_rd_bytes_port0),
.prt_bytes2(reg_rd_bytes_port1),
.prt_dv1(reg_rd_dv_port0),
.prt_dv2(reg_rd_dv_port1),
.prt_qos(rd_qos),
.prt_req(rd_req),
.prt_data(rd_data),
.prt_addr(rd_addr),
.prt_bytes(rd_bytes),
.prt_dv(rd_dv)
);
processing_system7_bfm_v2_0_5_reg_map regm();
reg state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
rd_dv <= 0;
state <= 0;
end else begin
case(state)
0:begin
state <= 0;
rd_dv <= 0;
if(rd_req) begin
regm.read_reg_mem(rd_data,rd_addr, rd_bytes);
rd_dv <= 1;
state <= 1;
end
end
1:begin
rd_dv <= 0;
state <= 0;
end
endcase
end /// if
end// always
endmodule
|
// Avalon_Test_Streaming.v
// Generated using ACDS version 16.1 196
`timescale 1 ps / 1 ps
module Avalon_Test_Streaming (
);
wire [0:0] st_source_bfm_src_valid; // st_source_bfm:src_valid -> st_sink_bfm:sink_valid
wire [31:0] st_source_bfm_src_data; // st_source_bfm:src_data -> st_sink_bfm:sink_data
wire st_source_bfm_src_ready; // st_sink_bfm:sink_ready -> st_source_bfm:src_ready
wire [0:0] st_source_bfm_src_channel; // st_source_bfm:src_channel -> st_sink_bfm:sink_channel
wire clock_source_bfm_clk_clk; // clock_source_bfm:clk -> [reset_source_bfm:clk, st_sink_bfm:clk, st_source_bfm:clk]
wire reset_source_bfm_reset_reset; // reset_source_bfm:reset -> [st_sink_bfm:reset, st_source_bfm:reset]
altera_avalon_clock_source #(
.CLOCK_RATE (50),
.CLOCK_UNIT (1000000)
) clock_source_bfm (
.clk (clock_source_bfm_clk_clk) // clk.clk
);
altera_avalon_reset_source #(
.ASSERT_HIGH_RESET (1),
.INITIAL_RESET_CYCLES (10)
) reset_source_bfm (
.reset (reset_source_bfm_reset_reset), // reset.reset
.clk (clock_source_bfm_clk_clk) // clk.clk
);
altera_avalon_st_sink_bfm #(
.USE_PACKET (0),
.USE_CHANNEL (1),
.USE_ERROR (0),
.USE_READY (1),
.USE_VALID (1),
.USE_EMPTY (0),
.ST_SYMBOL_W (8),
.ST_NUMSYMBOLS (4),
.ST_CHANNEL_W (1),
.ST_ERROR_W (1),
.ST_EMPTY_W (2),
.ST_READY_LATENCY (0),
.ST_BEATSPERCYCLE (1),
.ST_MAX_CHANNELS (1),
.VHDL_ID (0)
) st_sink_bfm (
.clk (clock_source_bfm_clk_clk), // clk.clk
.reset (reset_source_bfm_reset_reset), // clk_reset.reset
.sink_data (st_source_bfm_src_data), // sink.data
.sink_valid (st_source_bfm_src_valid), // .valid
.sink_ready (st_source_bfm_src_ready), // .ready
.sink_channel (st_source_bfm_src_channel), // .channel
.sink_startofpacket (1'b0), // (terminated)
.sink_endofpacket (1'b0), // (terminated)
.sink_empty (2'b00), // (terminated)
.sink_error (1'b0) // (terminated)
);
altera_avalon_st_source_bfm #(
.USE_PACKET (0),
.USE_CHANNEL (1),
.USE_ERROR (0),
.USE_READY (1),
.USE_VALID (1),
.USE_EMPTY (0),
.ST_SYMBOL_W (8),
.ST_NUMSYMBOLS (4),
.ST_CHANNEL_W (1),
.ST_ERROR_W (1),
.ST_EMPTY_W (2),
.ST_READY_LATENCY (0),
.ST_BEATSPERCYCLE (1),
.ST_MAX_CHANNELS (1),
.VHDL_ID (0)
) st_source_bfm (
.clk (clock_source_bfm_clk_clk), // clk.clk
.reset (reset_source_bfm_reset_reset), // clk_reset.reset
.src_data (st_source_bfm_src_data), // src.data
.src_valid (st_source_bfm_src_valid), // .valid
.src_ready (st_source_bfm_src_ready), // .ready
.src_channel (st_source_bfm_src_channel), // .channel
.src_startofpacket (), // (terminated)
.src_endofpacket (), // (terminated)
.src_empty (), // (terminated)
.src_error () // (terminated)
);
endmodule
|
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 2, Question 2
*/
// Testbench for behavioral model for the decoder
// Import the modules that will be tested for in this testbench
`include "decoder4to16.v"
`include "encoder_pl.v"
`include "decoder_pl.v"
`include "pipelinedec.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_pipeline();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUTs
// Output of stage 1
wire [14:0] c;
// Output of stage 2
wire [15:1] err;
wire [14:0] cx;
// Output of stage 3
wire [10:0] q;
wire [10:0] qx;
//wire [10:0] rb;
// Declare "reg" signals: inputs to the DUTs
// 1st stage
reg [10:0] b;
reg [10:0] r_b;
reg [3:0] e;
reg [3:0] r_e;
// 2nd stage
reg [14:0] r_c;
reg [3:0] rr_e;
reg [10:0] rr_b;
//reg [15:1] err;
// 3rd stage
//reg [14:0] cx;
//reg [10:0] qx;
reg [14:0] r_qx;
reg [10:0] rb;
reg clk,reset;
/**
* Instantiate an instance of arbiter_LRU4 so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "arb"
*/
decoder4to16 dec4to16 (
// instance_name(signal name),
// Signal name can be the same as the instance name
rr_e,err);
encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_b,c);
decoder dec (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_qx,q);
large_xor xr (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_c,err,cx);
parity_stripper ps (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_qx,qx);
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#10 clk = 0;
#10 clk = 1;
end
// Create the register (flip-flop) for the initial/1st stage
always@(posedge clk)
begin
if(reset)
begin
r_b<=0;
r_e<=0;
end
else
begin
r_e<=e;
r_b<=b;
end
end
// Create the register (flip-flop) for the 2nd stage
always@(posedge clk)
begin
if(reset)
begin
r_c<=0;
rr_e<=0;
rr_b<=0;
end
else
begin
r_c<=c;
rr_e<=r_e;
rr_b<=r_b;
end
end
// Create the register (flip-flop) for the 3rd stage
always@(posedge clk)
begin
if(reset)
begin
r_qx<=0;
rb<=0;
end
else
begin
r_qx<=cx;
rb<=rr_b;
end
end
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
reset=1;
#20;
reset=0;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#20;
b = $random;
e = $random;
$display(q, "<< Displaying q[10:0] >>");
$display(qx, "<< Displaying qx[10:0] >>");
$display(rb, "<< Displaying rb[10:0] >>");
#300;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
(** * PE: Partial Evaluation *)
(* Chapter author/maintainer: Chung-chieh Shan *)
(** Equiv.v introduced constant folding as an example of a program
transformation and proved that it preserves the meaning of the
program. Constant folding operates on manifest constants such
as [ANum] expressions. For example, it simplifies the command
[Y ::= APlus (ANum 3) (ANum 1)] to the command [Y ::= ANum 4].
However, it does not propagate known constants along data flow.
For example, it does not simplify the sequence
X ::= ANum 3;; Y ::= APlus (AId X) (ANum 1)
to
X ::= ANum 3;; Y ::= ANum 4
because it forgets that [X] is [3] by the time it gets to [Y].
We naturally want to enhance constant folding so that it
propagates known constants and uses them to simplify programs.
Doing so constitutes a rudimentary form of _partial evaluation_.
As we will see, partial evaluation is so called because it is
like running a program, except only part of the program can be
evaluated because only part of the input to the program is known.
For example, we can only simplify the program
X ::= ANum 3;; Y ::= AMinus (APlus (AId X) (ANum 1)) (AId Y)
to
X ::= ANum 3;; Y ::= AMinus (ANum 4) (AId Y)
without knowing the initial value of [Y]. *)
Require Export Imp.
Require Import FunctionalExtensionality.
(* ####################################################### *)
(** * Generalizing Constant Folding *)
(** The starting point of partial evaluation is to represent our
partial knowledge about the state. For example, between the two
assignments above, the partial evaluator may know only that [X] is
[3] and nothing about any other variable. *)
(** ** Partial States *)
(** Conceptually speaking, we can think of such partial states as the
type [id -> option nat] (as opposed to the type [id -> nat] of
concrete, full states). However, in addition to looking up and
updating the values of individual variables in a partial state, we
may also want to compare two partial states to see if and where
they differ, to handle conditional control flow. It is not possible
to compare two arbitrary functions in this way, so we represent
partial states in a more concrete format: as a list of [id * nat]
pairs. *)
Definition pe_state := list (id * nat).
(** The idea is that a variable [id] appears in the list if and only
if we know its current [nat] value. The [pe_lookup] function thus
interprets this concrete representation. (If the same variable
[id] appears multiple times in the list, the first occurrence
wins, but we will define our partial evaluator to never construct
such a [pe_state].) *)
Fixpoint pe_lookup (pe_st : pe_state) (V:id) : option nat :=
match pe_st with
| [] => None
| (V',n')::pe_st => if eq_id_dec V V' then Some n'
else pe_lookup pe_st V
end.
(** For example, [empty_pe_state] represents complete ignorance about
every variable -- the function that maps every [id] to [None]. *)
Definition empty_pe_state : pe_state := [].
(** More generally, if the [list] representing a [pe_state] does not
contain some [id], then that [pe_state] must map that [id] to
[None]. Before we prove this fact, we first define a useful
tactic for reasoning with [id] equality. The tactic
compare V V' SCase
means to reason by cases over [eq_id_dec V V'].
In the case where [V = V'], the tactic
substitutes [V] for [V'] throughout. *)
Tactic Notation "compare" ident(i) ident(j) ident(c) :=
let H := fresh "Heq" i j in
destruct (eq_id_dec i j);
[ Case_aux c "equal"; subst j
| Case_aux c "not equal" ].
Theorem pe_domain: forall pe_st V n,
pe_lookup pe_st V = Some n ->
In V (map (@fst _ _) pe_st).
Proof. intros pe_st V n H. induction pe_st as [| [V' n'] pe_st].
Case "[]". inversion H.
Case "::". simpl in H. simpl. compare V V' SCase; auto. Qed.
(** *** Aside on [In].
We will make heavy use of the [In] predicate from the standard library.
[In] is equivalent to the [appears_in] predicate introduced in Logic.v, but
defined using a [Fixpoint] rather than an [Inductive]. *)
Print In.
(* ===> Fixpoint In {A:Type} (a: A) (l:list A) : Prop :=
match l with
| [] => False
| b :: m => b = a \/ In a m
end
: forall A : Type, A -> list A -> Prop *)
(** [In] comes with various useful lemmas. *)
Check in_or_app.
(* ===> in_or_app: forall (A : Type) (l m : list A) (a : A),
In a l \/ In a m -> In a (l ++ m) *)
Check filter_In.
(* ===> filter_In : forall (A : Type) (f : A -> bool) (x : A) (l : list A),
In x (filter f l) <-> In x l /\ f x = true *)
Check in_dec.
(* ===> in_dec : forall A : Type,
(forall x y : A, {x = y} + {x <> y}) ->
forall (a : A) (l : list A), {In a l} + {~ In a l}] *)
(** Note that we can compute with [in_dec], just as with [eq_id_dec]. *)
(** ** Arithmetic Expressions *)
(** Partial evaluation of [aexp] is straightforward -- it is basically
the same as constant folding, [fold_constants_aexp], except that
sometimes the partial state tells us the current value of a
variable and we can replace it by a constant expression. *)
Fixpoint pe_aexp (pe_st : pe_state) (a : aexp) : aexp :=
match a with
| ANum n => ANum n
| AId i => match pe_lookup pe_st i with (* <----- NEW *)
| Some n => ANum n
| None => AId i
end
| APlus a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 + n2)
| (a1', a2') => APlus a1' a2'
end
| AMinus a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 - n2)
| (a1', a2') => AMinus a1' a2'
end
| AMult a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 * n2)
| (a1', a2') => AMult a1' a2'
end
end.
(** This partial evaluator folds constants but does not apply the
associativity of addition. *)
Example test_pe_aexp1:
pe_aexp [(X,3)] (APlus (APlus (AId X) (ANum 1)) (AId Y))
= APlus (ANum 4) (AId Y).
Proof. reflexivity. Qed.
Example text_pe_aexp2:
pe_aexp [(Y,3)] (APlus (APlus (AId X) (ANum 1)) (AId Y))
= APlus (APlus (AId X) (ANum 1)) (ANum 3).
Proof. reflexivity. Qed.
(** Now, in what sense is [pe_aexp] correct? It is reasonable to
define the correctness of [pe_aexp] as follows: whenever a full
state [st:state] is _consistent_ with a partial state
[pe_st:pe_state] (in other words, every variable to which [pe_st]
assigns a value is assigned the same value by [st]), evaluating
[a] and evaluating [pe_aexp pe_st a] in [st] yields the same
result. This statement is indeed true. *)
Definition pe_consistent (st:state) (pe_st:pe_state) :=
forall V n, Some n = pe_lookup pe_st V -> st V = n.
Theorem pe_aexp_correct_weak: forall st pe_st, pe_consistent st pe_st ->
forall a, aeval st a = aeval st (pe_aexp pe_st a).
Proof. unfold pe_consistent. intros st pe_st H a.
aexp_cases (induction a) Case; simpl;
try reflexivity;
try (destruct (pe_aexp pe_st a1);
destruct (pe_aexp pe_st a2);
rewrite IHa1; rewrite IHa2; reflexivity).
(* Compared to fold_constants_aexp_sound,
the only interesting case is AId *)
Case "AId".
remember (pe_lookup pe_st i) as l. destruct l.
SCase "Some". rewrite H with (n:=n) by apply Heql. reflexivity.
SCase "None". reflexivity.
Qed.
(** However, we will soon want our partial evaluator to remove
assignments. For example, it will simplify
X ::= ANum 3;; Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
to just
Y ::= AMinus (ANum 3) (AId Y);; X ::= ANum 4
by delaying the assignment to [X] until the end. To accomplish
this simplification, we need the result of partial evaluating
pe_aexp [(X,3)] (AMinus (AId X) (AId Y))
to be equal to [AMinus (ANum 3) (AId Y)] and _not_ the original
expression [AMinus (AId X) (AId Y)]. After all, it would be
incorrect, not just inefficient, to transform
X ::= ANum 3;; Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
to
Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
even though the output expressions [AMinus (ANum 3) (AId Y)] and
[AMinus (AId X) (AId Y)] both satisfy the correctness criterion
that we just proved. Indeed, if we were to just define [pe_aexp
pe_st a = a] then the theorem [pe_aexp_correct'] would already
trivially hold.
Instead, we want to prove that the [pe_aexp] is correct in a
stronger sense: evaluating the expression produced by partial
evaluation ([aeval st (pe_aexp pe_st a)]) must not depend on those
parts of the full state [st] that are already specified in the
partial state [pe_st]. To be more precise, let us define a
function [pe_override], which updates [st] with the contents of
[pe_st]. In other words, [pe_override] carries out the
assignments listed in [pe_st] on top of [st]. *)
Fixpoint pe_override (st:state) (pe_st:pe_state) : state :=
match pe_st with
| [] => st
| (V,n)::pe_st => update (pe_override st pe_st) V n
end.
Example test_pe_override:
pe_override (update empty_state Y 1) [(X,3);(Z,2)]
= update (update (update empty_state Y 1) Z 2) X 3.
Proof. reflexivity. Qed.
(** Although [pe_override] operates on a concrete [list] representing
a [pe_state], its behavior is defined entirely by the [pe_lookup]
interpretation of the [pe_state]. *)
Theorem pe_override_correct: forall st pe_st V0,
pe_override st pe_st V0 =
match pe_lookup pe_st V0 with
| Some n => n
| None => st V0
end.
Proof. intros. induction pe_st as [| [V n] pe_st]. reflexivity.
simpl in *. unfold update.
compare V0 V Case; auto. rewrite eq_id; auto. rewrite neq_id; auto. Qed.
(** We can relate [pe_consistent] to [pe_override] in two ways.
First, overriding a state with a partial state always gives a
state that is consistent with the partial state. Second, if a
state is already consistent with a partial state, then overriding
the state with the partial state gives the same state. *)
Theorem pe_override_consistent: forall st pe_st,
pe_consistent (pe_override st pe_st) pe_st.
Proof. intros st pe_st V n H. rewrite pe_override_correct.
destruct (pe_lookup pe_st V); inversion H. reflexivity. Qed.
Theorem pe_consistent_override: forall st pe_st,
pe_consistent st pe_st -> forall V, st V = pe_override st pe_st V.
Proof. intros st pe_st H V. rewrite pe_override_correct.
remember (pe_lookup pe_st V) as l. destruct l; auto. Qed.
(** Now we can state and prove that [pe_aexp] is correct in the
stronger sense that will help us define the rest of the partial
evaluator.
Intuitively, running a program using partial evaluation is a
two-stage process. In the first, _static_ stage, we partially
evaluate the given program with respect to some partial state to
get a _residual_ program. In the second, _dynamic_ stage, we
evaluate the residual program with respect to the rest of the
state. This dynamic state provides values for those variables
that are unknown in the static (partial) state. Thus, the
residual program should be equivalent to _prepending_ the
assignments listed in the partial state to the original program. *)
Theorem pe_aexp_correct: forall (pe_st:pe_state) (a:aexp) (st:state),
aeval (pe_override st pe_st) a = aeval st (pe_aexp pe_st a).
Proof.
intros pe_st a st.
aexp_cases (induction a) Case; simpl;
try reflexivity;
try (destruct (pe_aexp pe_st a1);
destruct (pe_aexp pe_st a2);
rewrite IHa1; rewrite IHa2; reflexivity).
(* Compared to fold_constants_aexp_sound, the only
interesting case is AId. *)
rewrite pe_override_correct. destruct (pe_lookup pe_st i); reflexivity.
Qed.
(** ** Boolean Expressions *)
(** The partial evaluation of boolean expressions is similar. In
fact, it is entirely analogous to the constant folding of boolean
expressions, because our language has no boolean variables. *)
Fixpoint pe_bexp (pe_st : pe_state) (b : bexp) : bexp :=
match b with
| BTrue => BTrue
| BFalse => BFalse
| BEq a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => if beq_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BEq a1' a2'
end
| BLe a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => if ble_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BLe a1' a2'
end
| BNot b1 =>
match (pe_bexp pe_st b1) with
| BTrue => BFalse
| BFalse => BTrue
| b1' => BNot b1'
end
| BAnd b1 b2 =>
match (pe_bexp pe_st b1, pe_bexp pe_st b2) with
| (BTrue, BTrue) => BTrue
| (BTrue, BFalse) => BFalse
| (BFalse, BTrue) => BFalse
| (BFalse, BFalse) => BFalse
| (b1', b2') => BAnd b1' b2'
end
end.
Example test_pe_bexp1:
pe_bexp [(X,3)] (BNot (BLe (AId X) (ANum 3)))
= BFalse.
Proof. reflexivity. Qed.
Example test_pe_bexp2: forall b,
b = BNot (BLe (AId X) (APlus (AId X) (ANum 1))) ->
pe_bexp [] b = b.
Proof. intros b H. rewrite -> H. reflexivity. Qed.
(** The correctness of [pe_bexp] is analogous to the correctness of
[pe_aexp] above. *)
Theorem pe_bexp_correct: forall (pe_st:pe_state) (b:bexp) (st:state),
beval (pe_override st pe_st) b = beval st (pe_bexp pe_st b).
Proof.
intros pe_st b st.
bexp_cases (induction b) Case; simpl;
try reflexivity;
try (remember (pe_aexp pe_st a) as a';
remember (pe_aexp pe_st a0) as a0';
assert (Ha: aeval (pe_override st pe_st) a = aeval st a');
assert (Ha0: aeval (pe_override st pe_st) a0 = aeval st a0');
try (subst; apply pe_aexp_correct);
destruct a'; destruct a0'; rewrite Ha; rewrite Ha0;
simpl; try destruct (beq_nat n n0); try destruct (ble_nat n n0);
reflexivity);
try (destruct (pe_bexp pe_st b); rewrite IHb; reflexivity);
try (destruct (pe_bexp pe_st b1);
destruct (pe_bexp pe_st b2);
rewrite IHb1; rewrite IHb2; reflexivity).
Qed.
(* ####################################################### *)
(** * Partial Evaluation of Commands, Without Loops *)
(** What about the partial evaluation of commands? The analogy
between partial evaluation and full evaluation continues: Just as
full evaluation of a command turns an initial state into a final
state, partial evaluation of a command turns an initial partial
state into a final partial state. The difference is that, because
the state is partial, some parts of the command may not be
executable at the static stage. Therefore, just as [pe_aexp]
returns a residual [aexp] and [pe_bexp] returns a residual [bexp]
above, partially evaluating a command yields a residual command.
Another way in which our partial evaluator is similar to a full
evaluator is that it does not terminate on all commands. It is
not hard to build a partial evaluator that terminates on all
commands; what is hard is building a partial evaluator that
terminates on all commands yet automatically performs desired
optimizations such as unrolling loops. Often a partial evaluator
can be coaxed into terminating more often and performing more
optimizations by writing the source program differently so that
the separation between static and dynamic information becomes more
apparent. Such coaxing is the art of _binding-time improvement_.
The binding time of a variable tells when its value is known --
either "static", or "dynamic."
Anyway, for now we will just live with the fact that our partial
evaluator is not a total function from the source command and the
initial partial state to the residual command and the final
partial state. To model this non-termination, just as with the
full evaluation of commands, we use an inductively defined
relation. We write
c1 / st || c1' / st'
to mean that partially evaluating the source command [c1] in the
initial partial state [st] yields the residual command [c1'] and
the final partial state [st']. For example, we want something like
(X ::= ANum 3 ;; Y ::= AMult (AId Z) (APlus (AId X) (AId X)))
/ [] || (Y ::= AMult (AId Z) (ANum 6)) / [(X,3)]
to hold. The assignment to [X] appears in the final partial state,
not the residual command. *)
(** ** Assignment *)
(** Let's start by considering how to partially evaluate an
assignment. The two assignments in the source program above needs
to be treated differently. The first assignment [X ::= ANum 3],
is _static_: its right-hand-side is a constant (more generally,
simplifies to a constant), so we should update our partial state
at [X] to [3] and produce no residual code. (Actually, we produce
a residual [SKIP].) The second assignment [Y ::= AMult (AId Z)
(APlus (AId X) (AId X))] is _dynamic_: its right-hand-side does
not simplify to a constant, so we should leave it in the residual
code and remove [Y], if present, from our partial state. To
implement these two cases, we define the functions [pe_add] and
[pe_remove]. Like [pe_override] above, these functions operate on
a concrete [list] representing a [pe_state], but the theorems
[pe_add_correct] and [pe_remove_correct] specify their behavior by
the [pe_lookup] interpretation of the [pe_state]. *)
Fixpoint pe_remove (pe_st:pe_state) (V:id) : pe_state :=
match pe_st with
| [] => []
| (V',n')::pe_st => if eq_id_dec V V' then pe_remove pe_st V
else (V',n') :: pe_remove pe_st V
end.
Theorem pe_remove_correct: forall pe_st V V0,
pe_lookup (pe_remove pe_st V) V0
= if eq_id_dec V V0 then None else pe_lookup pe_st V0.
Proof. intros pe_st V V0. induction pe_st as [| [V' n'] pe_st].
Case "[]". destruct (eq_id_dec V V0); reflexivity.
Case "::". simpl. compare V V' SCase.
SCase "equal". rewrite IHpe_st.
destruct (eq_id_dec V V0). reflexivity. rewrite neq_id; auto.
SCase "not equal". simpl. compare V0 V' SSCase.
SSCase "equal". rewrite neq_id; auto.
SSCase "not equal". rewrite IHpe_st. reflexivity.
Qed.
Definition pe_add (pe_st:pe_state) (V:id) (n:nat) : pe_state :=
(V,n) :: pe_remove pe_st V.
Theorem pe_add_correct: forall pe_st V n V0,
pe_lookup (pe_add pe_st V n) V0
= if eq_id_dec V V0 then Some n else pe_lookup pe_st V0.
Proof. intros pe_st V n V0. unfold pe_add. simpl.
compare V V0 Case.
Case "equal". rewrite eq_id; auto.
Case "not equal". rewrite pe_remove_correct. repeat rewrite neq_id; auto.
Qed.
(** We will use the two theorems below to show that our partial
evaluator correctly deals with dynamic assignments and static
assignments, respectively. *)
Theorem pe_override_update_remove: forall st pe_st V n,
update (pe_override st pe_st) V n =
pe_override (update st V n) (pe_remove pe_st V).
Proof. intros st pe_st V n. apply functional_extensionality. intros V0.
unfold update. rewrite !pe_override_correct. rewrite pe_remove_correct.
destruct (eq_id_dec V V0); reflexivity. Qed.
Theorem pe_override_update_add: forall st pe_st V n,
update (pe_override st pe_st) V n =
pe_override st (pe_add pe_st V n).
Proof. intros st pe_st V n. apply functional_extensionality. intros V0.
unfold update. rewrite !pe_override_correct. rewrite pe_add_correct.
destruct (eq_id_dec V V0); reflexivity. Qed.
(** ** Conditional *)
(** Trickier than assignments to partially evaluate is the
conditional, [IFB b1 THEN c1 ELSE c2 FI]. If [b1] simplifies to
[BTrue] or [BFalse] then it's easy: we know which branch will be
taken, so just take that branch. If [b1] does not simplify to a
constant, then we need to take both branches, and the final
partial state may differ between the two branches!
The following program illustrates the difficulty:
X ::= ANum 3;;
IFB BLe (AId Y) (ANum 4) THEN
Y ::= ANum 4;;
IFB BEq (AId X) (AId Y) THEN Y ::= ANum 999 ELSE SKIP FI
ELSE SKIP FI
Suppose the initial partial state is empty. We don't know
statically how [Y] compares to [4], so we must partially evaluate
both branches of the (outer) conditional. On the [THEN] branch,
we know that [Y] is set to [4] and can even use that knowledge to
simplify the code somewhat. On the [ELSE] branch, we still don't
know the exact value of [Y] at the end. What should the final
partial state and residual program be?
One way to handle such a dynamic conditional is to take the
intersection of the final partial states of the two branches. In
this example, we take the intersection of [(Y,4),(X,3)] and
[(X,3)], so the overall final partial state is [(X,3)]. To
compensate for forgetting that [Y] is [4], we need to add an
assignment [Y ::= ANum 4] to the end of the [THEN] branch. So,
the residual program will be something like
SKIP;;
IFB BLe (AId Y) (ANum 4) THEN
SKIP;;
SKIP;;
Y ::= ANum 4
ELSE SKIP FI
Programming this case in Coq calls for several auxiliary
functions: we need to compute the intersection of two [pe_state]s
and turn their difference into sequences of assignments.
First, we show how to compute whether two [pe_state]s to disagree
at a given variable. In the theorem [pe_disagree_domain], we
prove that two [pe_state]s can only disagree at variables that
appear in at least one of them. *)
Definition pe_disagree_at (pe_st1 pe_st2 : pe_state) (V:id) : bool :=
match pe_lookup pe_st1 V, pe_lookup pe_st2 V with
| Some x, Some y => negb (beq_nat x y)
| None, None => false
| _, _ => true
end.
Theorem pe_disagree_domain: forall (pe_st1 pe_st2 : pe_state) (V:id),
true = pe_disagree_at pe_st1 pe_st2 V ->
In V (map (@fst _ _) pe_st1 ++ map (@fst _ _) pe_st2).
Proof. unfold pe_disagree_at. intros pe_st1 pe_st2 V H.
apply in_or_app.
remember (pe_lookup pe_st1 V) as lookup1.
destruct lookup1 as [n1|]. left. apply pe_domain with n1. auto.
remember (pe_lookup pe_st2 V) as lookup2.
destruct lookup2 as [n2|]. right. apply pe_domain with n2. auto.
inversion H. Qed.
(** We define the [pe_compare] function to list the variables where
two given [pe_state]s disagree. This list is exact, according to
the theorem [pe_compare_correct]: a variable appears on the list
if and only if the two given [pe_state]s disagree at that
variable. Furthermore, we use the [pe_unique] function to
eliminate duplicates from the list. *)
Fixpoint pe_unique (l : list id) : list id :=
match l with
| [] => []
| x::l => x :: filter (fun y => if eq_id_dec x y then false else true) (pe_unique l)
end.
Theorem pe_unique_correct: forall l x,
In x l <-> In x (pe_unique l).
Proof. intros l x. induction l as [| h t]. reflexivity.
simpl in *. split.
Case "->".
intros. inversion H; clear H.
left. assumption.
destruct (eq_id_dec h x).
left. assumption.
right. apply filter_In. split.
apply IHt. assumption.
rewrite neq_id; auto.
Case "<-".
intros. inversion H; clear H.
left. assumption.
apply filter_In in H0. inversion H0. right. apply IHt. assumption.
Qed.
Definition pe_compare (pe_st1 pe_st2 : pe_state) : list id :=
pe_unique (filter (pe_disagree_at pe_st1 pe_st2)
(map (@fst _ _) pe_st1 ++ map (@fst _ _) pe_st2)).
Theorem pe_compare_correct: forall pe_st1 pe_st2 V,
pe_lookup pe_st1 V = pe_lookup pe_st2 V <->
~ In V (pe_compare pe_st1 pe_st2).
Proof. intros pe_st1 pe_st2 V.
unfold pe_compare. rewrite <- pe_unique_correct. rewrite filter_In.
split; intros Heq.
Case "->".
intro. destruct H. unfold pe_disagree_at in H0. rewrite Heq in H0.
destruct (pe_lookup pe_st2 V).
rewrite <- beq_nat_refl in H0. inversion H0.
inversion H0.
Case "<-".
assert (Hagree: pe_disagree_at pe_st1 pe_st2 V = false).
SCase "Proof of assertion".
remember (pe_disagree_at pe_st1 pe_st2 V) as disagree.
destruct disagree; [| reflexivity].
apply pe_disagree_domain in Heqdisagree.
apply ex_falso_quodlibet. apply Heq. split. assumption. reflexivity.
unfold pe_disagree_at in Hagree.
destruct (pe_lookup pe_st1 V) as [n1|];
destruct (pe_lookup pe_st2 V) as [n2|];
try reflexivity; try solve by inversion.
rewrite negb_false_iff in Hagree.
apply beq_nat_true in Hagree. subst. reflexivity. Qed.
(** The intersection of two partial states is the result of removing
from one of them all the variables where the two disagree. We
define the function [pe_removes], in terms of [pe_remove] above,
to perform such a removal of a whole list of variables at once.
The theorem [pe_compare_removes] testifies that the [pe_lookup]
interpretation of the result of this intersection operation is the
same no matter which of the two partial states we remove the
variables from. Because [pe_override] only depends on the
[pe_lookup] interpretation of partial states, [pe_override] also
does not care which of the two partial states we remove the
variables from; that theorem [pe_compare_override] is used in the
correctness proof shortly. *)
Fixpoint pe_removes (pe_st:pe_state) (ids : list id) : pe_state :=
match ids with
| [] => pe_st
| V::ids => pe_remove (pe_removes pe_st ids) V
end.
Theorem pe_removes_correct: forall pe_st ids V,
pe_lookup (pe_removes pe_st ids) V =
if in_dec eq_id_dec V ids then None else pe_lookup pe_st V.
Proof. intros pe_st ids V. induction ids as [| V' ids]. reflexivity.
simpl. rewrite pe_remove_correct. rewrite IHids.
compare V' V Case.
reflexivity.
destruct (in_dec eq_id_dec V ids);
reflexivity.
Qed.
Theorem pe_compare_removes: forall pe_st1 pe_st2 V,
pe_lookup (pe_removes pe_st1 (pe_compare pe_st1 pe_st2)) V =
pe_lookup (pe_removes pe_st2 (pe_compare pe_st1 pe_st2)) V.
Proof. intros pe_st1 pe_st2 V. rewrite !pe_removes_correct.
destruct (in_dec eq_id_dec V (pe_compare pe_st1 pe_st2)).
reflexivity.
apply pe_compare_correct. auto. Qed.
Theorem pe_compare_override: forall pe_st1 pe_st2 st,
pe_override st (pe_removes pe_st1 (pe_compare pe_st1 pe_st2)) =
pe_override st (pe_removes pe_st2 (pe_compare pe_st1 pe_st2)).
Proof. intros. apply functional_extensionality. intros V.
rewrite !pe_override_correct. rewrite pe_compare_removes. reflexivity.
Qed.
(** Finally, we define an [assign] function to turn the difference
between two partial states into a sequence of assignment commands.
More precisely, [assign pe_st ids] generates an assignment command
for each variable listed in [ids]. *)
Fixpoint assign (pe_st : pe_state) (ids : list id) : com :=
match ids with
| [] => SKIP
| V::ids => match pe_lookup pe_st V with
| Some n => (assign pe_st ids;; V ::= ANum n)
| None => assign pe_st ids
end
end.
(** The command generated by [assign] always terminates, because it is
just a sequence of assignments. The (total) function [assigned]
below computes the effect of the command on the (dynamic state).
The theorem [assign_removes] then confirms that the generated
assignments perfectly compensate for removing the variables from
the partial state. *)
Definition assigned (pe_st:pe_state) (ids : list id) (st:state) : state :=
fun V => if in_dec eq_id_dec V ids then
match pe_lookup pe_st V with
| Some n => n
| None => st V
end
else st V.
Theorem assign_removes: forall pe_st ids st,
pe_override st pe_st =
pe_override (assigned pe_st ids st) (pe_removes pe_st ids).
Proof. intros pe_st ids st. apply functional_extensionality. intros V.
rewrite !pe_override_correct. rewrite pe_removes_correct. unfold assigned.
destruct (in_dec eq_id_dec V ids); destruct (pe_lookup pe_st V); reflexivity.
Qed.
Lemma ceval_extensionality: forall c st st1 st2,
c / st || st1 -> (forall V, st1 V = st2 V) -> c / st || st2.
Proof. intros c st st1 st2 H Heq.
apply functional_extensionality in Heq. rewrite <- Heq. apply H. Qed.
Theorem eval_assign: forall pe_st ids st,
assign pe_st ids / st || assigned pe_st ids st.
Proof. intros pe_st ids st. induction ids as [| V ids]; simpl.
Case "[]". eapply ceval_extensionality. apply E_Skip. reflexivity.
Case "V::ids".
remember (pe_lookup pe_st V) as lookup. destruct lookup.
SCase "Some". eapply E_Seq. apply IHids. unfold assigned. simpl.
eapply ceval_extensionality. apply E_Ass. simpl. reflexivity.
intros V0. unfold update. compare V V0 SSCase.
SSCase "equal". rewrite <- Heqlookup. reflexivity.
SSCase "not equal". destruct (in_dec eq_id_dec V0 ids); auto.
SCase "None". eapply ceval_extensionality. apply IHids.
unfold assigned. intros V0. simpl. compare V V0 SSCase.
SSCase "equal". rewrite <- Heqlookup.
destruct (in_dec eq_id_dec V ids); reflexivity.
SSCase "not equal". destruct (in_dec eq_id_dec V0 ids); reflexivity. Qed.
(** ** The Partial Evaluation Relation *)
(** At long last, we can define a partial evaluator for commands
without loops, as an inductive relation! The inequality
conditions in [PE_AssDynamic] and [PE_If] are just to keep the
partial evaluator deterministic; they are not required for
correctness. *)
Reserved Notation "c1 '/' st '||' c1' '/' st'"
(at level 40, st at level 39, c1' at level 39).
Inductive pe_com : com -> pe_state -> com -> pe_state -> Prop :=
| PE_Skip : forall pe_st,
SKIP / pe_st || SKIP / pe_st
| PE_AssStatic : forall pe_st a1 n1 l,
pe_aexp pe_st a1 = ANum n1 ->
(l ::= a1) / pe_st || SKIP / pe_add pe_st l n1
| PE_AssDynamic : forall pe_st a1 a1' l,
pe_aexp pe_st a1 = a1' ->
(forall n, a1' <> ANum n) ->
(l ::= a1) / pe_st || (l ::= a1') / pe_remove pe_st l
| PE_Seq : forall pe_st pe_st' pe_st'' c1 c2 c1' c2',
c1 / pe_st || c1' / pe_st' ->
c2 / pe_st' || c2' / pe_st'' ->
(c1 ;; c2) / pe_st || (c1' ;; c2') / pe_st''
| PE_IfTrue : forall pe_st pe_st' b1 c1 c2 c1',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c1' / pe_st'
| PE_IfFalse : forall pe_st pe_st' b1 c1 c2 c2',
pe_bexp pe_st b1 = BFalse ->
c2 / pe_st || c2' / pe_st' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c2' / pe_st'
| PE_If : forall pe_st pe_st1 pe_st2 b1 c1 c2 c1' c2',
pe_bexp pe_st b1 <> BTrue ->
pe_bexp pe_st b1 <> BFalse ->
c1 / pe_st || c1' / pe_st1 ->
c2 / pe_st || c2' / pe_st2 ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st
|| (IFB pe_bexp pe_st b1
THEN c1' ;; assign pe_st1 (pe_compare pe_st1 pe_st2)
ELSE c2' ;; assign pe_st2 (pe_compare pe_st1 pe_st2) FI)
/ pe_removes pe_st1 (pe_compare pe_st1 pe_st2)
where "c1 '/' st '||' c1' '/' st'" := (pe_com c1 st c1' st').
Tactic Notation "pe_com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "PE_Skip"
| Case_aux c "PE_AssStatic" | Case_aux c "PE_AssDynamic"
| Case_aux c "PE_Seq"
| Case_aux c "PE_IfTrue" | Case_aux c "PE_IfFalse" | Case_aux c "PE_If" ].
Hint Constructors pe_com.
Hint Constructors ceval.
(** ** Examples *)
(** Below are some examples of using the partial evaluator. To make
the [pe_com] relation actually usable for automatic partial
evaluation, we would need to define more automation tactics in
Coq. That is not hard to do, but it is not needed here. *)
Example pe_example1:
(X ::= ANum 3 ;; Y ::= AMult (AId Z) (APlus (AId X) (AId X)))
/ [] || (SKIP;; Y ::= AMult (AId Z) (ANum 6)) / [(X,3)].
Proof. eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_AssDynamic. reflexivity. intros n H. inversion H. Qed.
Example pe_example2:
(X ::= ANum 3 ;; IFB BLe (AId X) (ANum 4) THEN X ::= ANum 4 ELSE SKIP FI)
/ [] || (SKIP;; SKIP) / [(X,4)].
Proof. eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_IfTrue. reflexivity.
eapply PE_AssStatic. reflexivity. Qed.
Example pe_example3:
(X ::= ANum 3;;
IFB BLe (AId Y) (ANum 4) THEN
Y ::= ANum 4;;
IFB BEq (AId X) (AId Y) THEN Y ::= ANum 999 ELSE SKIP FI
ELSE SKIP FI) / []
|| (SKIP;;
IFB BLe (AId Y) (ANum 4) THEN
(SKIP;; SKIP);; (SKIP;; Y ::= ANum 4)
ELSE SKIP;; SKIP FI)
/ [(X,3)].
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_If; intuition eauto; try solve by inversion.
econstructor. eapply PE_AssStatic. reflexivity.
eapply PE_IfFalse. reflexivity. econstructor.
reflexivity. reflexivity. Qed.
(** ** Correctness of Partial Evaluation *)
(** Finally let's prove that this partial evaluator is correct! *)
Reserved Notation "c' '/' pe_st' '/' st '||' st''"
(at level 40, pe_st' at level 39, st at level 39).
Inductive pe_ceval
(c':com) (pe_st':pe_state) (st:state) (st'':state) : Prop :=
| pe_ceval_intro : forall st',
c' / st || st' ->
pe_override st' pe_st' = st'' ->
c' / pe_st' / st || st''
where "c' '/' pe_st' '/' st '||' st''" := (pe_ceval c' pe_st' st st'').
Hint Constructors pe_ceval.
Theorem pe_com_complete:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' ->
forall st st'',
(c / pe_override st pe_st || st'') ->
(c' / pe_st' / st || st'').
Proof. intros c pe_st pe_st' c' Hpe.
pe_com_cases (induction Hpe) Case; intros st st'' Heval;
try (inversion Heval; subst;
try (rewrite -> pe_bexp_correct, -> H in *; solve by inversion);
[]);
eauto.
Case "PE_AssStatic". econstructor. econstructor.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_add.
rewrite -> H. reflexivity.
Case "PE_AssDynamic". econstructor. econstructor. reflexivity.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_remove.
reflexivity.
Case "PE_Seq".
edestruct IHHpe1. eassumption. subst.
edestruct IHHpe2. eassumption.
eauto.
Case "PE_If". inversion Heval; subst.
SCase "E'IfTrue". edestruct IHHpe1. eassumption.
econstructor. apply E_IfTrue. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite <- assign_removes. eassumption.
SCase "E_IfFalse". edestruct IHHpe2. eassumption.
econstructor. apply E_IfFalse. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite -> pe_compare_override.
rewrite <- assign_removes. eassumption.
Qed.
Theorem pe_com_sound:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' ->
forall st st'',
(c' / pe_st' / st || st'') ->
(c / pe_override st pe_st || st'').
Proof. intros c pe_st pe_st' c' Hpe.
pe_com_cases (induction Hpe) Case;
intros st st'' [st' Heval Heq];
try (inversion Heval; []; subst); auto.
Case "PE_AssStatic". rewrite <- pe_override_update_add. apply E_Ass.
rewrite -> pe_aexp_correct. rewrite -> H. reflexivity.
Case "PE_AssDynamic". rewrite <- pe_override_update_remove. apply E_Ass.
rewrite <- pe_aexp_correct. reflexivity.
Case "PE_Seq". eapply E_Seq; eauto.
Case "PE_IfTrue". apply E_IfTrue.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity. eauto.
Case "PE_IfFalse". apply E_IfFalse.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity. eauto.
Case "PE_If".
inversion Heval; subst; inversion H7;
(eapply ceval_deterministic in H8; [| apply eval_assign]); subst.
SCase "E_IfTrue".
apply E_IfTrue. rewrite -> pe_bexp_correct. assumption.
rewrite <- assign_removes. eauto.
SCase "E_IfFalse".
rewrite -> pe_compare_override.
apply E_IfFalse. rewrite -> pe_bexp_correct. assumption.
rewrite <- assign_removes. eauto.
Qed.
(** The main theorem. Thanks to David Menendez for this formulation! *)
Corollary pe_com_correct:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' ->
forall st st'',
(c / pe_override st pe_st || st'') <->
(c' / pe_st' / st || st'').
Proof. intros c pe_st pe_st' c' H st st''. split.
Case "->". apply pe_com_complete. apply H.
Case "<-". apply pe_com_sound. apply H.
Qed.
(* ####################################################### *)
(** * Partial Evaluation of Loops *)
(** It may seem straightforward at first glance to extend the partial
evaluation relation [pe_com] above to loops. Indeed, many loops
are easy to deal with. Considered this repeated-squaring loop,
for example:
WHILE BLe (ANum 1) (AId X) DO
Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1)
END
If we know neither [X] nor [Y] statically, then the entire loop is
dynamic and the residual command should be the same. If we know
[X] but not [Y], then the loop can be unrolled all the way and the
residual command should be
Y ::= AMult (AId Y) (AId Y);;
Y ::= AMult (AId Y) (AId Y);;
Y ::= AMult (AId Y) (AId Y)
if [X] is initially [3] (and finally [0]). In general, a loop is
easy to partially evaluate if the final partial state of the loop
body is equal to the initial state, or if its guard condition is
static.
But there are other loops for which it is hard to express the
residual program we want in Imp. For example, take this program
for checking if [Y] is even or odd:
X ::= ANum 0;;
WHILE BLe (ANum 1) (AId Y) DO
Y ::= AMinus (AId Y) (ANum 1);;
X ::= AMinus (ANum 1) (AId X)
END
The value of [X] alternates between [0] and [1] during the loop.
Ideally, we would like to unroll this loop, not all the way but
_two-fold_, into something like
WHILE BLe (ANum 1) (AId Y) DO
Y ::= AMinus (AId Y) (ANum 1);;
IF BLe (ANum 1) (AId Y) THEN
Y ::= AMinus (AId Y) (ANum 1)
ELSE
X ::= ANum 1;; EXIT
FI
END;;
X ::= ANum 0
Unfortunately, there is no [EXIT] command in Imp. Without
extending the range of control structures available in our
language, the best we can do is to repeat loop-guard tests or add
flag variables. Neither option is terribly attractive.
Still, as a digression, below is an attempt at performing partial
evaluation on Imp commands. We add one more command argument
[c''] to the [pe_com] relation, which keeps track of a loop to
roll up. *)
Module Loop.
Reserved Notation "c1 '/' st '||' c1' '/' st' '/' c''"
(at level 40, st at level 39, c1' at level 39, st' at level 39).
Inductive pe_com : com -> pe_state -> com -> pe_state -> com -> Prop :=
| PE_Skip : forall pe_st,
SKIP / pe_st || SKIP / pe_st / SKIP
| PE_AssStatic : forall pe_st a1 n1 l,
pe_aexp pe_st a1 = ANum n1 ->
(l ::= a1) / pe_st || SKIP / pe_add pe_st l n1 / SKIP
| PE_AssDynamic : forall pe_st a1 a1' l,
pe_aexp pe_st a1 = a1' ->
(forall n, a1' <> ANum n) ->
(l ::= a1) / pe_st || (l ::= a1') / pe_remove pe_st l / SKIP
| PE_Seq : forall pe_st pe_st' pe_st'' c1 c2 c1' c2' c'',
c1 / pe_st || c1' / pe_st' / SKIP ->
c2 / pe_st' || c2' / pe_st'' / c'' ->
(c1 ;; c2) / pe_st || (c1' ;; c2') / pe_st'' / c''
| PE_IfTrue : forall pe_st pe_st' b1 c1 c2 c1' c'',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c1' / pe_st' / c''
| PE_IfFalse : forall pe_st pe_st' b1 c1 c2 c2' c'',
pe_bexp pe_st b1 = BFalse ->
c2 / pe_st || c2' / pe_st' / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c2' / pe_st' / c''
| PE_If : forall pe_st pe_st1 pe_st2 b1 c1 c2 c1' c2' c'',
pe_bexp pe_st b1 <> BTrue ->
pe_bexp pe_st b1 <> BFalse ->
c1 / pe_st || c1' / pe_st1 / c'' ->
c2 / pe_st || c2' / pe_st2 / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st
|| (IFB pe_bexp pe_st b1
THEN c1' ;; assign pe_st1 (pe_compare pe_st1 pe_st2)
ELSE c2' ;; assign pe_st2 (pe_compare pe_st1 pe_st2) FI)
/ pe_removes pe_st1 (pe_compare pe_st1 pe_st2)
/ c''
| PE_WhileEnd : forall pe_st b1 c1,
pe_bexp pe_st b1 = BFalse ->
(WHILE b1 DO c1 END) / pe_st || SKIP / pe_st / SKIP
| PE_WhileLoop : forall pe_st pe_st' pe_st'' b1 c1 c1' c2' c2'',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st' || c2' / pe_st'' / c2'' ->
pe_compare pe_st pe_st'' <> [] ->
(WHILE b1 DO c1 END) / pe_st || (c1';;c2') / pe_st'' / c2''
| PE_While : forall pe_st pe_st' pe_st'' b1 c1 c1' c2' c2'',
pe_bexp pe_st b1 <> BFalse ->
pe_bexp pe_st b1 <> BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st' || c2' / pe_st'' / c2'' ->
pe_compare pe_st pe_st'' <> [] ->
(c2'' = SKIP \/ c2'' = WHILE b1 DO c1 END) ->
(WHILE b1 DO c1 END) / pe_st
|| (IFB pe_bexp pe_st b1
THEN c1';; c2';; assign pe_st'' (pe_compare pe_st pe_st'')
ELSE assign pe_st (pe_compare pe_st pe_st'') FI)
/ pe_removes pe_st (pe_compare pe_st pe_st'')
/ c2''
| PE_WhileFixedEnd : forall pe_st b1 c1,
pe_bexp pe_st b1 <> BFalse ->
(WHILE b1 DO c1 END) / pe_st || SKIP / pe_st / (WHILE b1 DO c1 END)
| PE_WhileFixedLoop : forall pe_st pe_st' pe_st'' b1 c1 c1' c2',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st'
|| c2' / pe_st'' / (WHILE b1 DO c1 END) ->
pe_compare pe_st pe_st'' = [] ->
(WHILE b1 DO c1 END) / pe_st
|| (WHILE BTrue DO SKIP END) / pe_st / SKIP
(* Because we have an infinite loop, we should actually
start to throw away the rest of the program:
(WHILE b1 DO c1 END) / pe_st
|| SKIP / pe_st / (WHILE BTrue DO SKIP END) *)
| PE_WhileFixed : forall pe_st pe_st' pe_st'' b1 c1 c1' c2',
pe_bexp pe_st b1 <> BFalse ->
pe_bexp pe_st b1 <> BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st'
|| c2' / pe_st'' / (WHILE b1 DO c1 END) ->
pe_compare pe_st pe_st'' = [] ->
(WHILE b1 DO c1 END) / pe_st
|| (WHILE pe_bexp pe_st b1 DO c1';; c2' END) / pe_st / SKIP
where "c1 '/' st '||' c1' '/' st' '/' c''" := (pe_com c1 st c1' st' c'').
Tactic Notation "pe_com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "PE_Skip"
| Case_aux c "PE_AssStatic" | Case_aux c "PE_AssDynamic"
| Case_aux c "PE_Seq"
| Case_aux c "PE_IfTrue" | Case_aux c "PE_IfFalse" | Case_aux c "PE_If"
| Case_aux c "PE_WhileEnd" | Case_aux c "PE_WhileLoop"
| Case_aux c "PE_While" | Case_aux c "PE_WhileFixedEnd"
| Case_aux c "PE_WhileFixedLoop" | Case_aux c "PE_WhileFixed" ].
Hint Constructors pe_com.
(** ** Examples *)
Ltac step i :=
(eapply i; intuition eauto; try solve by inversion);
repeat (try eapply PE_Seq;
try (eapply PE_AssStatic; simpl; reflexivity);
try (eapply PE_AssDynamic;
[ simpl; reflexivity
| intuition eauto; solve by inversion ])).
Definition square_loop: com :=
WHILE BLe (ANum 1) (AId X) DO
Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1)
END.
Example pe_loop_example1:
square_loop / []
|| (WHILE BLe (ANum 1) (AId X) DO
(Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1));; SKIP
END) / [] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
step PE_WhileFixed. step PE_WhileFixedEnd. reflexivity.
reflexivity. reflexivity. Qed.
Example pe_loop_example2:
(X ::= ANum 3;; square_loop) / []
|| (SKIP;;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
SKIP) / [(X,0)] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_WhileLoop.
step PE_WhileLoop.
step PE_WhileLoop.
step PE_WhileEnd.
inversion H. inversion H. inversion H.
reflexivity. reflexivity. Qed.
Example pe_loop_example3:
(Z ::= ANum 3;; subtract_slowly) / []
|| (SKIP;;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
WHILE BNot (BEq (AId X) (ANum 0)) DO
(SKIP;; X ::= AMinus (AId X) (ANum 1));; SKIP
END;;
SKIP;; Z ::= ANum 0
ELSE SKIP;; Z ::= ANum 1 FI;; SKIP
ELSE SKIP;; Z ::= ANum 2 FI;; SKIP
ELSE SKIP;; Z ::= ANum 3 FI) / [] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_While.
step PE_While.
step PE_While.
step PE_WhileFixed.
step PE_WhileFixedEnd.
reflexivity. inversion H. inversion H. inversion H.
reflexivity. reflexivity. Qed.
Example pe_loop_example4:
(X ::= ANum 0;;
WHILE BLe (AId X) (ANum 2) DO
X ::= AMinus (ANum 1) (AId X)
END) / [] || (SKIP;; WHILE BTrue DO SKIP END) / [(X,0)] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_WhileFixedLoop.
step PE_WhileLoop.
step PE_WhileFixedEnd.
inversion H. reflexivity. reflexivity. reflexivity. Qed.
(** ** Correctness *)
(** Because this partial evaluator can unroll a loop n-fold where n is
a (finite) integer greater than one, in order to show it correct
we need to perform induction not structurally on dynamic
evaluation but on the number of times dynamic evaluation enters a
loop body. *)
Reserved Notation "c1 '/' st '||' st' '#' n"
(at level 40, st at level 39, st' at level 39).
Inductive ceval_count : com -> state -> state -> nat -> Prop :=
| E'Skip : forall st,
SKIP / st || st # 0
| E'Ass : forall st a1 n l,
aeval st a1 = n ->
(l ::= a1) / st || (update st l n) # 0
| E'Seq : forall c1 c2 st st' st'' n1 n2,
c1 / st || st' # n1 ->
c2 / st' || st'' # n2 ->
(c1 ;; c2) / st || st'' # (n1 + n2)
| E'IfTrue : forall st st' b1 c1 c2 n,
beval st b1 = true ->
c1 / st || st' # n ->
(IFB b1 THEN c1 ELSE c2 FI) / st || st' # n
| E'IfFalse : forall st st' b1 c1 c2 n,
beval st b1 = false ->
c2 / st || st' # n ->
(IFB b1 THEN c1 ELSE c2 FI) / st || st' # n
| E'WhileEnd : forall b1 st c1,
beval st b1 = false ->
(WHILE b1 DO c1 END) / st || st # 0
| E'WhileLoop : forall st st' st'' b1 c1 n1 n2,
beval st b1 = true ->
c1 / st || st' # n1 ->
(WHILE b1 DO c1 END) / st' || st'' # n2 ->
(WHILE b1 DO c1 END) / st || st'' # S (n1 + n2)
where "c1 '/' st '||' st' # n" := (ceval_count c1 st st' n).
Tactic Notation "ceval_count_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E'Skip" | Case_aux c "E'Ass" | Case_aux c "E'Seq"
| Case_aux c "E'IfTrue" | Case_aux c "E'IfFalse"
| Case_aux c "E'WhileEnd" | Case_aux c "E'WhileLoop" ].
Hint Constructors ceval_count.
Theorem ceval_count_complete: forall c st st',
c / st || st' -> exists n, c / st || st' # n.
Proof. intros c st st' Heval.
induction Heval;
try inversion IHHeval1;
try inversion IHHeval2;
try inversion IHHeval;
eauto. Qed.
Theorem ceval_count_sound: forall c st st' n,
c / st || st' # n -> c / st || st'.
Proof. intros c st st' n Heval. induction Heval; eauto. Qed.
Theorem pe_compare_nil_lookup: forall pe_st1 pe_st2,
pe_compare pe_st1 pe_st2 = [] ->
forall V, pe_lookup pe_st1 V = pe_lookup pe_st2 V.
Proof. intros pe_st1 pe_st2 H V.
apply (pe_compare_correct pe_st1 pe_st2 V).
rewrite H. intro. inversion H0. Qed.
Theorem pe_compare_nil_override: forall pe_st1 pe_st2,
pe_compare pe_st1 pe_st2 = [] ->
forall st, pe_override st pe_st1 = pe_override st pe_st2.
Proof. intros pe_st1 pe_st2 H st.
apply functional_extensionality. intros V.
rewrite !pe_override_correct.
apply pe_compare_nil_lookup with (V:=V) in H.
rewrite H. reflexivity. Qed.
Reserved Notation "c' '/' pe_st' '/' c'' '/' st '||' st'' '#' n"
(at level 40, pe_st' at level 39, c'' at level 39,
st at level 39, st'' at level 39).
Inductive pe_ceval_count (c':com) (pe_st':pe_state) (c'':com)
(st:state) (st'':state) (n:nat) : Prop :=
| pe_ceval_count_intro : forall st' n',
c' / st || st' ->
c'' / pe_override st' pe_st' || st'' # n' ->
n' <= n ->
c' / pe_st' / c'' / st || st'' # n
where "c' '/' pe_st' '/' c'' '/' st '||' st'' '#' n" :=
(pe_ceval_count c' pe_st' c'' st st'' n).
Hint Constructors pe_ceval_count.
Lemma pe_ceval_count_le: forall c' pe_st' c'' st st'' n n',
n' <= n ->
c' / pe_st' / c'' / st || st'' # n' ->
c' / pe_st' / c'' / st || st'' # n.
Proof. intros c' pe_st' c'' st st'' n n' Hle H. inversion H.
econstructor; try eassumption. omega. Qed.
Theorem pe_com_complete:
forall c pe_st pe_st' c' c'', c / pe_st || c' / pe_st' / c'' ->
forall st st'' n,
(c / pe_override st pe_st || st'' # n) ->
(c' / pe_st' / c'' / st || st'' # n).
Proof. intros c pe_st pe_st' c' c'' Hpe.
pe_com_cases (induction Hpe) Case; intros st st'' n Heval;
try (inversion Heval; subst;
try (rewrite -> pe_bexp_correct, -> H in *; solve by inversion);
[]);
eauto.
Case "PE_AssStatic". econstructor. econstructor.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_add.
rewrite -> H. apply E'Skip. auto.
Case "PE_AssDynamic". econstructor. econstructor. reflexivity.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_remove.
apply E'Skip. auto.
Case "PE_Seq".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor; eauto. omega.
Case "PE_If". inversion Heval; subst.
SCase "E'IfTrue". edestruct IHHpe1. eassumption.
econstructor. apply E_IfTrue. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite <- assign_removes. eassumption. eassumption.
SCase "E_IfFalse". edestruct IHHpe2. eassumption.
econstructor. apply E_IfFalse. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite -> pe_compare_override.
rewrite <- assign_removes. eassumption. eassumption.
Case "PE_WhileLoop".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor; eauto. omega.
Case "PE_While". inversion Heval; subst.
SCase "E_WhileEnd". econstructor. apply E_IfFalse.
rewrite <- pe_bexp_correct. assumption.
apply eval_assign.
rewrite <- assign_removes. inversion H2; subst; auto.
auto.
SCase "E_WhileLoop".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor. apply E_IfTrue.
rewrite <- pe_bexp_correct. assumption.
repeat eapply E_Seq; eauto. apply eval_assign.
rewrite -> pe_compare_override, <- assign_removes. eassumption.
omega.
Case "PE_WhileFixedLoop". apply ex_falso_quodlibet.
generalize dependent (S (n1 + n2)). intros n.
clear - Case H H0 IHHpe1 IHHpe2. generalize dependent st.
induction n using lt_wf_ind; intros st Heval. inversion Heval; subst.
SCase "E'WhileEnd". rewrite pe_bexp_correct, H in H7. inversion H7.
SCase "E'WhileLoop".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
rewrite <- (pe_compare_nil_override _ _ H0) in H7.
apply H1 in H7; [| omega]. inversion H7.
Case "PE_WhileFixed". generalize dependent st.
induction n using lt_wf_ind; intros st Heval. inversion Heval; subst.
SCase "E'WhileEnd". rewrite pe_bexp_correct in H8. eauto.
SCase "E'WhileLoop". rewrite pe_bexp_correct in H5.
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
rewrite <- (pe_compare_nil_override _ _ H1) in H8.
apply H2 in H8; [| omega]. inversion H8.
econstructor; [ eapply E_WhileLoop; eauto | eassumption | omega].
Qed.
Theorem pe_com_sound:
forall c pe_st pe_st' c' c'', c / pe_st || c' / pe_st' / c'' ->
forall st st'' n,
(c' / pe_st' / c'' / st || st'' # n) ->
(c / pe_override st pe_st || st'').
Proof. intros c pe_st pe_st' c' c'' Hpe.
pe_com_cases (induction Hpe) Case;
intros st st'' n [st' n' Heval Heval' Hle];
try (inversion Heval; []; subst);
try (inversion Heval'; []; subst); eauto.
Case "PE_AssStatic". rewrite <- pe_override_update_add. apply E_Ass.
rewrite -> pe_aexp_correct. rewrite -> H. reflexivity.
Case "PE_AssDynamic". rewrite <- pe_override_update_remove. apply E_Ass.
rewrite <- pe_aexp_correct. reflexivity.
Case "PE_Seq". eapply E_Seq; eauto.
Case "PE_IfTrue". apply E_IfTrue.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe. eauto.
Case "PE_IfFalse". apply E_IfFalse.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe. eauto.
Case "PE_If". inversion Heval; subst; inversion H7; subst; clear H7.
SCase "E_IfTrue".
eapply ceval_deterministic in H8; [| apply eval_assign]. subst.
rewrite <- assign_removes in Heval'.
apply E_IfTrue. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe1. eauto.
SCase "E_IfFalse".
eapply ceval_deterministic in H8; [| apply eval_assign]. subst.
rewrite -> pe_compare_override in Heval'.
rewrite <- assign_removes in Heval'.
apply E_IfFalse. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe2. eauto.
Case "PE_WhileEnd". apply E_WhileEnd.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
Case "PE_WhileLoop". eapply E_WhileLoop.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe1. eauto. eapply IHHpe2. eauto.
Case "PE_While". inversion Heval; subst.
SCase "E_IfTrue".
inversion H9. subst. clear H9.
inversion H10. subst. clear H10.
eapply ceval_deterministic in H11; [| apply eval_assign]. subst.
rewrite -> pe_compare_override in Heval'.
rewrite <- assign_removes in Heval'.
eapply E_WhileLoop. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe1. eauto.
eapply IHHpe2. eauto.
SCase "E_IfFalse". apply ceval_count_sound in Heval'.
eapply ceval_deterministic in H9; [| apply eval_assign]. subst.
rewrite <- assign_removes in Heval'.
inversion H2; subst.
SSCase "c2'' = SKIP". inversion Heval'. subst. apply E_WhileEnd.
rewrite -> pe_bexp_correct. assumption.
SSCase "c2'' = WHILE b1 DO c1 END". assumption.
Case "PE_WhileFixedEnd". eapply ceval_count_sound. apply Heval'.
Case "PE_WhileFixedLoop".
apply loop_never_stops in Heval. inversion Heval.
Case "PE_WhileFixed".
clear - Case H1 IHHpe1 IHHpe2 Heval.
remember (WHILE pe_bexp pe_st b1 DO c1';; c2' END) as c'.
ceval_cases (induction Heval) SCase;
inversion Heqc'; subst; clear Heqc'.
SCase "E_WhileEnd". apply E_WhileEnd.
rewrite pe_bexp_correct. assumption.
SCase "E_WhileLoop".
assert (IHHeval2' := IHHeval2 (refl_equal _)).
apply ceval_count_complete in IHHeval2'. inversion IHHeval2'.
clear IHHeval1 IHHeval2 IHHeval2'.
inversion Heval1. subst.
eapply E_WhileLoop. rewrite pe_bexp_correct. assumption. eauto.
eapply IHHpe2. econstructor. eassumption.
rewrite <- (pe_compare_nil_override _ _ H1). eassumption. apply le_n.
Qed.
Corollary pe_com_correct:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' / SKIP ->
forall st st'',
(c / pe_override st pe_st || st'') <->
(exists st', c' / st || st' /\ pe_override st' pe_st' = st'').
Proof. intros c pe_st pe_st' c' H st st''. split.
Case "->". intros Heval.
apply ceval_count_complete in Heval. inversion Heval as [n Heval'].
apply pe_com_complete with (st:=st) (st'':=st'') (n:=n) in H.
inversion H as [? ? ? Hskip ?]. inversion Hskip. subst. eauto.
assumption.
Case "<-". intros [st' [Heval Heq]]. subst st''.
eapply pe_com_sound in H. apply H.
econstructor. apply Heval. apply E'Skip. apply le_n.
Qed.
End Loop.
(* ####################################################### *)
(** * Partial Evaluation of Flowchart Programs *)
(** Instead of partially evaluating [WHILE] loops directly, the
standard approach to partially evaluating imperative programs is
to convert them into _flowcharts_. In other words, it turns out
that adding labels and jumps to our language makes it much easier
to partially evaluate. The result of partially evaluating a
flowchart is a residual flowchart. If we are lucky, the jumps in
the residual flowchart can be converted back to [WHILE] loops, but
that is not possible in general; we do not pursue it here. *)
(** ** Basic blocks *)
(** A flowchart is made of _basic blocks_, which we represent with the
inductive type [block]. A basic block is a sequence of
assignments (the constructor [Assign]), concluding with a
conditional jump (the constructor [If]) or an unconditional jump
(the constructor [Goto]). The destinations of the jumps are
specified by _labels_, which can be of any type. Therefore, we
parameterize the [block] type by the type of labels. *)
Inductive block (Label:Type) : Type :=
| Goto : Label -> block Label
| If : bexp -> Label -> Label -> block Label
| Assign : id -> aexp -> block Label -> block Label.
Tactic Notation "block_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "Goto" | Case_aux c "If" | Case_aux c "Assign" ].
Arguments Goto {Label} _.
Arguments If {Label} _ _ _.
Arguments Assign {Label} _ _ _.
(** We use the "even or odd" program, expressed above in Imp, as our
running example. Converting this program into a flowchart turns
out to require 4 labels, so we define the following type. *)
Inductive parity_label : Type :=
| entry : parity_label
| loop : parity_label
| body : parity_label
| done : parity_label.
(** The following [block] is the basic block found at the [body] label
of the example program. *)
Definition parity_body : block parity_label :=
Assign Y (AMinus (AId Y) (ANum 1))
(Assign X (AMinus (ANum 1) (AId X))
(Goto loop)).
(** To evaluate a basic block, given an initial state, is to compute
the final state and the label to jump to next. Because basic
blocks do not _contain_ loops or other control structures,
evaluation of basic blocks is a total function -- we don't need to
worry about non-termination. *)
Fixpoint keval {L:Type} (st:state) (k : block L) : state * L :=
match k with
| Goto l => (st, l)
| If b l1 l2 => (st, if beval st b then l1 else l2)
| Assign i a k => keval (update st i (aeval st a)) k
end.
Example keval_example:
keval empty_state parity_body
= (update (update empty_state Y 0) X 1, loop).
Proof. reflexivity. Qed.
(** ** Flowchart programs *)
(** A flowchart program is simply a lookup function that maps labels
to basic blocks. Actually, some labels are _halting states_ and
do not map to any basic block. So, more precisely, a flowchart
[program] whose labels are of type [L] is a function from [L] to
[option (block L)]. *)
Definition program (L:Type) : Type := L -> option (block L).
Definition parity : program parity_label := fun l =>
match l with
| entry => Some (Assign X (ANum 0) (Goto loop))
| loop => Some (If (BLe (ANum 1) (AId Y)) body done)
| body => Some parity_body
| done => None (* halt *)
end.
(** Unlike a basic block, a program may not terminate, so we model the
evaluation of programs by an inductive relation [peval] rather
than a recursive function. *)
Inductive peval {L:Type} (p : program L)
: state -> L -> state -> L -> Prop :=
| E_None: forall st l,
p l = None ->
peval p st l st l
| E_Some: forall st l k st' l' st'' l'',
p l = Some k ->
keval st k = (st', l') ->
peval p st' l' st'' l'' ->
peval p st l st'' l''.
Example parity_eval: peval parity empty_state entry empty_state done.
Proof. erewrite f_equal with (f := fun st => peval _ _ _ st _).
eapply E_Some. reflexivity. reflexivity.
eapply E_Some. reflexivity. reflexivity.
apply E_None. reflexivity.
apply functional_extensionality. intros i. rewrite update_same; auto.
Qed.
Tactic Notation "peval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_None" | Case_aux c "E_Some" ].
(** ** Partial evaluation of basic blocks and flowchart programs *)
(** Partial evaluation changes the label type in a systematic way: if
the label type used to be [L], it becomes [pe_state * L]. So the
same label in the original program may be unfolded, or blown up,
into multiple labels by being paired with different partial
states. For example, the label [loop] in the [parity] program
will become two labels: [([(X,0)], loop)] and [([(X,1)], loop)].
This change of label type is reflected in the types of [pe_block]
and [pe_program] defined presently. *)
Fixpoint pe_block {L:Type} (pe_st:pe_state) (k : block L)
: block (pe_state * L) :=
match k with
| Goto l => Goto (pe_st, l)
| If b l1 l2 =>
match pe_bexp pe_st b with
| BTrue => Goto (pe_st, l1)
| BFalse => Goto (pe_st, l2)
| b' => If b' (pe_st, l1) (pe_st, l2)
end
| Assign i a k =>
match pe_aexp pe_st a with
| ANum n => pe_block (pe_add pe_st i n) k
| a' => Assign i a' (pe_block (pe_remove pe_st i) k)
end
end.
Example pe_block_example:
pe_block [(X,0)] parity_body
= Assign Y (AMinus (AId Y) (ANum 1)) (Goto ([(X,1)], loop)).
Proof. reflexivity. Qed.
Theorem pe_block_correct: forall (L:Type) st pe_st k st' pe_st' (l':L),
keval st (pe_block pe_st k) = (st', (pe_st', l')) ->
keval (pe_override st pe_st) k = (pe_override st' pe_st', l').
Proof. intros. generalize dependent pe_st. generalize dependent st.
block_cases (induction k as [l | b l1 l2 | i a k]) Case;
intros st pe_st H.
Case "Goto". inversion H; reflexivity.
Case "If".
replace (keval st (pe_block pe_st (If b l1 l2)))
with (keval st (If (pe_bexp pe_st b) (pe_st, l1) (pe_st, l2)))
in H by (simpl; destruct (pe_bexp pe_st b); reflexivity).
simpl in *. rewrite pe_bexp_correct.
destruct (beval st (pe_bexp pe_st b)); inversion H; reflexivity.
Case "Assign".
simpl in *. rewrite pe_aexp_correct.
destruct (pe_aexp pe_st a); simpl;
try solve [rewrite pe_override_update_add; apply IHk; apply H];
solve [rewrite pe_override_update_remove; apply IHk; apply H].
Qed.
Definition pe_program {L:Type} (p : program L)
: program (pe_state * L) :=
fun pe_l => match pe_l with (pe_st, l) =>
option_map (pe_block pe_st) (p l)
end.
Inductive pe_peval {L:Type} (p : program L)
(st:state) (pe_st:pe_state) (l:L) (st'o:state) (l':L) : Prop :=
| pe_peval_intro : forall st' pe_st',
peval (pe_program p) st (pe_st, l) st' (pe_st', l') ->
pe_override st' pe_st' = st'o ->
pe_peval p st pe_st l st'o l'.
Theorem pe_program_correct:
forall (L:Type) (p : program L) st pe_st l st'o l',
peval p (pe_override st pe_st) l st'o l' <->
pe_peval p st pe_st l st'o l'.
Proof. intros.
split; [Case "->" | Case "<-"].
Case "->". intros Heval.
remember (pe_override st pe_st) as sto.
generalize dependent pe_st. generalize dependent st.
peval_cases (induction Heval as
[ sto l Hlookup | sto l k st'o l' st''o l'' Hlookup Hkeval Heval ])
SCase; intros st pe_st Heqsto; subst sto.
SCase "E_None". eapply pe_peval_intro. apply E_None.
simpl. rewrite Hlookup. reflexivity. reflexivity.
SCase "E_Some".
remember (keval st (pe_block pe_st k)) as x.
destruct x as [st' [pe_st' l'_]].
symmetry in Heqx. erewrite pe_block_correct in Hkeval by apply Heqx.
inversion Hkeval. subst st'o l'_. clear Hkeval.
edestruct IHHeval. reflexivity. subst st''o. clear IHHeval.
eapply pe_peval_intro; [| reflexivity]. eapply E_Some; eauto.
simpl. rewrite Hlookup. reflexivity.
Case "<-". intros [st' pe_st' Heval Heqst'o].
remember (pe_st, l) as pe_st_l.
remember (pe_st', l') as pe_st'_l'.
generalize dependent pe_st. generalize dependent l.
peval_cases (induction Heval as
[ st [pe_st_ l_] Hlookup
| st [pe_st_ l_] pe_k st' [pe_st'_ l'_] st'' [pe_st'' l'']
Hlookup Hkeval Heval ])
SCase; intros l pe_st Heqpe_st_l;
inversion Heqpe_st_l; inversion Heqpe_st'_l'; repeat subst.
SCase "E_None". apply E_None. simpl in Hlookup.
destruct (p l'); [ solve [ inversion Hlookup ] | reflexivity ].
SCase "E_Some".
simpl in Hlookup. remember (p l) as k.
destruct k as [k|]; inversion Hlookup; subst.
eapply E_Some; eauto. apply pe_block_correct. apply Hkeval.
Qed.
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module FIFO_image_filter_src1_data_stream_2_V
#(parameter
MEM_STYLE = "block",
DATA_WIDTH = 8,
ADDR_WIDTH = 15,
DEPTH = 20000
)
(
// system signal
input wire clk,
input wire reset,
// write
output wire if_full_n,
input wire if_write_ce,
input wire if_write,
input wire [DATA_WIDTH-1:0] if_din,
// read
output wire if_empty_n,
input wire if_read_ce,
input wire if_read,
output wire [DATA_WIDTH-1:0] if_dout
);
//------------------------Parameter----------------------
//------------------------Local signal-------------------
(* ram_style = MEM_STYLE *)
reg [DATA_WIDTH-1:0] mem[0:DEPTH-1];
reg [DATA_WIDTH-1:0] q_buf = 1'b0;
reg [ADDR_WIDTH-1:0] waddr = 1'b0;
reg [ADDR_WIDTH-1:0] raddr = 1'b0;
wire [ADDR_WIDTH-1:0] wnext;
wire [ADDR_WIDTH-1:0] rnext;
wire push;
wire pop;
reg [ADDR_WIDTH-1:0] usedw = 1'b0;
reg full_n = 1'b1;
reg empty_n = 1'b0;
reg [DATA_WIDTH-1:0] q_tmp = 1'b0;
reg show_ahead = 1'b0;
reg [DATA_WIDTH-1:0] dout_buf = 1'b0;
reg dout_valid = 1'b0;
//------------------------Instantiation------------------
//------------------------Task and function--------------
//------------------------Body---------------------------
assign if_full_n = full_n;
assign if_empty_n = dout_valid;
assign if_dout = dout_buf;
assign push = full_n & if_write_ce & if_write;
assign pop = empty_n & if_read_ce & (~dout_valid | if_read);
assign wnext = !push ? waddr :
(waddr == DEPTH - 1) ? 1'b0 :
waddr + 1'b1;
assign rnext = !pop ? raddr :
(raddr == DEPTH - 1) ? 1'b0 :
raddr + 1'b1;
// waddr
always @(posedge clk) begin
if (reset == 1'b1)
waddr <= 1'b0;
else
waddr <= wnext;
end
// raddr
always @(posedge clk) begin
if (reset == 1'b1)
raddr <= 1'b0;
else
raddr <= rnext;
end
// usedw
always @(posedge clk) begin
if (reset == 1'b1)
usedw <= 1'b0;
else if (push & ~pop)
usedw <= usedw + 1'b1;
else if (~push & pop)
usedw <= usedw - 1'b1;
end
// full_n
always @(posedge clk) begin
if (reset == 1'b1)
full_n <= 1'b1;
else if (push & ~pop)
full_n <= (usedw != DEPTH - 1);
else if (~push & pop)
full_n <= 1'b1;
end
// empty_n
always @(posedge clk) begin
if (reset == 1'b1)
empty_n <= 1'b0;
else if (push & ~pop)
empty_n <= 1'b1;
else if (~push & pop)
empty_n <= (usedw != 1'b1);
end
// mem
always @(posedge clk) begin
if (push)
mem[waddr] <= if_din;
end
// q_buf
always @(posedge clk) begin
q_buf <= mem[rnext];
end
// q_tmp
always @(posedge clk) begin
if (reset == 1'b1)
q_tmp <= 1'b0;
else if (push)
q_tmp <= if_din;
end
// show_ahead
always @(posedge clk) begin
if (reset == 1'b1)
show_ahead <= 1'b0;
else if (push && usedw == pop)
show_ahead <= 1'b1;
else
show_ahead <= 1'b0;
end
// dout_buf
always @(posedge clk) begin
if (reset == 1'b1)
dout_buf <= 1'b0;
else if (pop)
dout_buf <= show_ahead? q_tmp : q_buf;
end
// dout_valid
always @(posedge clk) begin
if (reset == 1'b1)
dout_valid <= 1'b0;
else if (pop)
dout_valid <= 1'b1;
else if (if_read_ce & if_read)
dout_valid <= 1'b0;
end
endmodule
|
`timescale 1ns/1ps
/*
This file contains simulation models for GreenPAK cells which are possible to fully model using synthesizeable
behavioral Verilog constructs only.
*/
module GP_2LUT(input IN0, IN1, output OUT);
parameter [3:0] INIT = 0;
assign OUT = INIT[{IN1, IN0}];
endmodule
module GP_3LUT(input IN0, IN1, IN2, output OUT);
parameter [7:0] INIT = 0;
assign OUT = INIT[{IN2, IN1, IN0}];
endmodule
module GP_4LUT(
input wire IN0,
input wire IN1,
input wire IN2,
input wire IN3,
output wire OUT);
parameter [15:0] INIT = 0;
assign OUT = INIT[{IN3, IN2, IN1, IN0}];
endmodule
module GP_CLKBUF(input wire IN, output wire OUT);
assign OUT = IN;
endmodule
module GP_COUNT14(input CLK, input wire RST, output reg OUT);
parameter RESET_MODE = "RISING";
parameter COUNT_TO = 14'h1;
parameter CLKIN_DIVIDE = 1;
reg[13:0] count = COUNT_TO;
initial begin
if(CLKIN_DIVIDE != 1) begin
$display("ERROR: CLKIN_DIVIDE values other than 1 not implemented");
$finish;
end
end
//Combinatorially output underflow flag whenever we wrap low
always @(*) begin
OUT <= (count == 14'h0);
end
//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
generate
case(RESET_MODE)
"RISING": begin
always @(posedge CLK, posedge RST) begin
if(RST)
count <= 0;
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
"FALLING": begin
always @(posedge CLK, negedge RST) begin
if(!RST)
count <= 0;
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
"BOTH": begin
initial begin
$display("Both-edge reset mode for GP_COUNT14 not implemented");
$finish;
end
end
"LEVEL": begin
always @(posedge CLK, posedge RST) begin
if(RST)
count <= 0;
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
default: begin
initial begin
$display("Invalid RESET_MODE on GP_COUNT14");
$finish;
end
end
endcase
endgenerate
endmodule
module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
input UP, input KEEP, output reg[7:0] POUT);
parameter RESET_MODE = "RISING";
parameter RESET_VALUE = "ZERO";
parameter COUNT_TO = 14'h1;
parameter CLKIN_DIVIDE = 1;
initial begin
if(CLKIN_DIVIDE != 1) begin
$display("ERROR: CLKIN_DIVIDE values other than 1 not implemented");
$finish;
end
end
reg[13:0] count = COUNT_TO;
//Combinatorially output underflow flag whenever we wrap low
always @(*) begin
if(UP)
OUT <= (count == 14'h3fff);
else
OUT <= (count == 14'h0);
POUT <= count[7:0];
end
//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
generate
case(RESET_MODE)
"RISING": begin
always @(posedge CLK, posedge RST) begin
//Resets
if(RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
else if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
if(count == 14'h3fff)
count <= COUNT_TO;
end
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
"FALLING": begin
always @(posedge CLK, negedge RST) begin
//Resets
if(!RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
else if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
if(count == 14'h3fff)
count <= COUNT_TO;
end
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
"BOTH": begin
initial begin
$display("Both-edge reset mode for GP_COUNT14_ADV not implemented");
$finish;
end
end
"LEVEL": begin
always @(posedge CLK, posedge RST) begin
//Resets
if(RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
else begin
if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
if(count == 14'h3fff)
count <= COUNT_TO;
end
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
end
default: begin
initial begin
$display("Invalid RESET_MODE on GP_COUNT14_ADV");
$finish;
end
end
endcase
endgenerate
endmodule
module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
input UP, input KEEP, output reg[7:0] POUT);
parameter RESET_MODE = "RISING";
parameter RESET_VALUE = "ZERO";
parameter COUNT_TO = 8'h1;
parameter CLKIN_DIVIDE = 1;
reg[7:0] count = COUNT_TO;
initial begin
if(CLKIN_DIVIDE != 1) begin
$display("ERROR: CLKIN_DIVIDE values other than 1 not implemented");
$finish;
end
end
//Combinatorially output underflow flag whenever we wrap low
always @(*) begin
if(UP)
OUT <= (count == 8'hff);
else
OUT <= (count == 8'h0);
POUT <= count;
end
//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
generate
case(RESET_MODE)
"RISING": begin
always @(posedge CLK, posedge RST) begin
//Resets
if(RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
//Main counter
else if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
if(count == 8'hff)
count <= COUNT_TO;
end
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
"FALLING": begin
always @(posedge CLK, negedge RST) begin
//Resets
if(!RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
//Main counter
else if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
if(count == 8'hff)
count <= COUNT_TO;
end
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
"BOTH": begin
initial begin
$display("Both-edge reset mode for GP_COUNT8_ADV not implemented");
$finish;
end
end
"LEVEL": begin
always @(posedge CLK, posedge RST) begin
//Resets
if(RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
else begin
if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
if(count == 8'hff)
count <= COUNT_TO;
end
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
end
default: begin
initial begin
$display("Invalid RESET_MODE on GP_COUNT8_ADV");
$finish;
end
end
endcase
endgenerate
endmodule
module GP_COUNT8(
input wire CLK,
input wire RST,
output reg OUT,
output reg[7:0] POUT);
parameter RESET_MODE = "RISING";
parameter COUNT_TO = 8'h1;
parameter CLKIN_DIVIDE = 1;
initial begin
if(CLKIN_DIVIDE != 1) begin
$display("ERROR: CLKIN_DIVIDE values other than 1 not implemented");
$finish;
end
end
reg[7:0] count = COUNT_TO;
//Combinatorially output underflow flag whenever we wrap low
always @(*) begin
OUT <= (count == 8'h0);
POUT <= count;
end
//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
generate
case(RESET_MODE)
"RISING": begin
always @(posedge CLK, posedge RST) begin
if(RST)
count <= 0;
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
"FALLING": begin
always @(posedge CLK, negedge RST) begin
if(!RST)
count <= 0;
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
"BOTH": begin
initial begin
$display("Both-edge reset mode for GP_COUNT8 not implemented");
$finish;
end
end
"LEVEL": begin
always @(posedge CLK, posedge RST) begin
if(RST)
count <= 0;
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end
default: begin
initial begin
$display("Invalid RESET_MODE on GP_COUNT8");
$finish;
end
end
endcase
endgenerate
endmodule
module GP_DCMPREF(output reg[7:0]OUT);
parameter[7:0] REF_VAL = 8'h00;
initial OUT = REF_VAL;
endmodule
module GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2, input[7:0] IN3, output reg[7:0] OUTA, output reg[7:0] OUTB);
always @(*) begin
case(SEL)
2'd00: begin
OUTA <= IN0;
OUTB <= IN3;
end
2'd01: begin
OUTA <= IN1;
OUTB <= IN2;
end
2'd02: begin
OUTA <= IN2;
OUTB <= IN1;
end
2'd03: begin
OUTA <= IN3;
OUTB <= IN0;
end
endcase
end
endmodule
module GP_DELAY(input IN, output reg OUT);
parameter DELAY_STEPS = 1;
parameter GLITCH_FILTER = 0;
initial OUT = 0;
generate
if(GLITCH_FILTER) begin
initial begin
$display("ERROR: GP_DELAY glitch filter mode not implemented");
$finish;
end
end
//TODO: These delays are PTV dependent! For now, hard code 3v3 timing
//Change simulation-mode delay depending on global Vdd range (how to specify this?)
always @(*) begin
case(DELAY_STEPS)
1: #166 OUT = IN;
2: #318 OUT = IN;
2: #471 OUT = IN;
3: #622 OUT = IN;
default: begin
$display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]");
$finish;
end
endcase
end
endgenerate
endmodule
module GP_DFF(input D, CLK, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(posedge CLK) begin
Q <= D;
end
endmodule
module GP_DFFI(input D, CLK, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial nQ = INIT;
always @(posedge CLK) begin
nQ <= ~D;
end
endmodule
module GP_DFFR(input D, CLK, nRST, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(posedge CLK, negedge nRST) begin
if (!nRST)
Q <= 1'b0;
else
Q <= D;
end
endmodule
module GP_DFFRI(input D, CLK, nRST, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial nQ = INIT;
always @(posedge CLK, negedge nRST) begin
if (!nRST)
nQ <= 1'b1;
else
nQ <= ~D;
end
endmodule
module GP_DFFS(input D, CLK, nSET, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(posedge CLK, negedge nSET) begin
if (!nSET)
Q <= 1'b1;
else
Q <= D;
end
endmodule
module GP_DFFSI(input D, CLK, nSET, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial nQ = INIT;
always @(posedge CLK, negedge nSET) begin
if (!nSET)
nQ <= 1'b0;
else
nQ <= ~D;
end
endmodule
module GP_DFFSR(input D, CLK, nSR, output reg Q);
parameter [0:0] INIT = 1'bx;
parameter [0:0] SRMODE = 1'bx;
initial Q = INIT;
always @(posedge CLK, negedge nSR) begin
if (!nSR)
Q <= SRMODE;
else
Q <= D;
end
endmodule
module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
parameter [0:0] INIT = 1'bx;
parameter [0:0] SRMODE = 1'bx;
initial nQ = INIT;
always @(posedge CLK, negedge nSR) begin
if (!nSR)
nQ <= ~SRMODE;
else
nQ <= ~D;
end
endmodule
module GP_DLATCH(input D, input nCLK, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(*) begin
if(!nCLK)
Q <= D;
end
endmodule
module GP_DLATCHI(input D, input nCLK, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial nQ = INIT;
always @(*) begin
if(!nCLK)
nQ <= ~D;
end
endmodule
module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(*) begin
if(!nRST)
Q <= 1'b0;
else if(!nCLK)
Q <= D;
end
endmodule
module GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial nQ = INIT;
always @(*) begin
if(!nRST)
nQ <= 1'b1;
else if(!nCLK)
nQ <= ~D;
end
endmodule
module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(*) begin
if(!nSET)
Q <= 1'b1;
else if(!nCLK)
Q <= D;
end
endmodule
module GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ);
parameter [0:0] INIT = 1'bx;
initial nQ = INIT;
always @(*) begin
if(!nSET)
nQ <= 1'b0;
else if(!nCLK)
nQ <= ~D;
end
endmodule
module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
parameter [0:0] INIT = 1'bx;
parameter[0:0] SRMODE = 1'bx;
initial Q = INIT;
always @(*) begin
if(!nSR)
Q <= SRMODE;
else if(!nCLK)
Q <= D;
end
endmodule
module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ);
parameter [0:0] INIT = 1'bx;
parameter[0:0] SRMODE = 1'bx;
initial nQ = INIT;
always @(*) begin
if(!nSR)
nQ <= ~SRMODE;
else if(!nCLK)
nQ <= ~D;
end
endmodule
module GP_IBUF(input IN, output OUT);
assign OUT = IN;
endmodule
module GP_IOBUF(input IN, input OE, output OUT, inout IO);
assign OUT = IO;
assign IO = OE ? IN : 1'bz;
endmodule
module GP_INV(input IN, output OUT);
assign OUT = ~IN;
endmodule
module GP_OBUF(input IN, output OUT);
assign OUT = IN;
endmodule
module GP_OBUFT(input IN, input OE, output OUT);
assign OUT = OE ? IN : 1'bz;
endmodule
module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
initial OUT = 0;
parameter PATTERN_DATA = 16'h0;
parameter PATTERN_LEN = 5'd16;
localparam COUNT_MAX = PATTERN_LEN - 1'h1;
reg[3:0] count = 0;
always @(posedge CLK, negedge nRST) begin
if(!nRST)
count <= 0;
else begin
count <= count - 1'h1;
if(count == 0)
count <= COUNT_MAX;
end
end
always @(*)
OUT = PATTERN_DATA[count];
endmodule
module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
parameter OUTA_TAP = 1;
parameter OUTA_INVERT = 0;
parameter OUTB_TAP = 1;
reg[15:0] shreg = 0;
always @(posedge CLK, negedge nRST) begin
if(!nRST)
shreg = 0;
else
shreg <= {shreg[14:0], IN};
end
assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
assign OUTB = shreg[OUTB_TAP - 1];
endmodule
module GP_VDD(output OUT);
assign OUT = 1;
endmodule
module GP_VSS(output OUT);
assign OUT = 0;
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: sg_list_reader_128.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Reads data from the scatter gather list buffer.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_SGR128_RD_0 1'b1
`define S_SGR128_RD_WAIT 1'b0
`define S_SGR128_CAP_0 1'b0
`define S_SGR128_CAP_RDY 1'b1
`timescale 1ns/1ns
module sg_list_reader_128 #(
parameter C_DATA_WIDTH = 9'd128
)
(
input CLK,
input RST,
input [C_DATA_WIDTH-1:0] BUF_DATA, // Scatter gather buffer data
input BUF_DATA_EMPTY, // Scatter gather buffer data empty
output BUF_DATA_REN, // Scatter gather buffer data read enable
output VALID, // Scatter gather element data is valid
output EMPTY, // Scatter gather elements empty
input REN, // Scatter gather element data read enable
output [63:0] ADDR, // Scatter gather element address
output [31:0] LEN // Scatter gather element length (in words)
);
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg rRdState=`S_SGR128_RD_0, _rRdState=`S_SGR128_RD_0;
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg rCapState=`S_SGR128_CAP_0, _rCapState=`S_SGR128_CAP_0;
reg [C_DATA_WIDTH-1:0] rData={C_DATA_WIDTH{1'd0}}, _rData={C_DATA_WIDTH{1'd0}};
reg [63:0] rAddr=64'd0, _rAddr=64'd0;
reg [31:0] rLen=0, _rLen=0;
reg rFifoValid=0, _rFifoValid=0;
reg rDataValid=0, _rDataValid=0;
assign BUF_DATA_REN = rRdState; // Not S_SGR128_RD_WAIT
assign VALID = rCapState; // S_SGR128_CAP_RDY
assign EMPTY = (BUF_DATA_EMPTY & rRdState); // Not S_SGR128_RD_WAIT
assign ADDR = rAddr;
assign LEN = rLen;
// Capture address and length as it comes out of the FIFO
always @ (posedge CLK) begin
rRdState <= #1 (RST ? `S_SGR128_RD_0 : _rRdState);
rCapState <= #1 (RST ? `S_SGR128_CAP_0 : _rCapState);
rData <= #1 _rData;
rFifoValid <= #1 (RST ? 1'd0 : _rFifoValid);
rDataValid <= #1 (RST ? 1'd0 : _rDataValid);
rAddr <= #1 _rAddr;
rLen <= #1 _rLen;
end
always @ (*) begin
_rRdState = rRdState;
_rCapState = rCapState;
_rAddr = rAddr;
_rLen = rLen;
_rData = BUF_DATA;
_rFifoValid = (BUF_DATA_REN & !BUF_DATA_EMPTY);
_rDataValid = rFifoValid;
case (rCapState)
`S_SGR128_CAP_0: begin
if (rDataValid) begin
_rAddr = rData[63:0];
_rLen = rData[95:64];
_rCapState = `S_SGR128_CAP_RDY;
end
end
`S_SGR128_CAP_RDY: begin
if (REN)
_rCapState = `S_SGR128_CAP_0;
end
endcase
case (rRdState)
`S_SGR128_RD_0: begin // Read from the sg data FIFO
if (!BUF_DATA_EMPTY)
_rRdState = `S_SGR128_RD_WAIT;
end
`S_SGR128_RD_WAIT: begin // Wait for the data to be consumed
if (REN)
_rRdState = `S_SGR128_RD_0;
end
endcase
end
endmodule
|
// hps_sdram.v
// This file was auto-generated from altera_mem_if_hps_emif_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.1 196
`timescale 1 ps / 1 ps
module hps_sdram (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire [0:0] mem_ck, // .mem_ck
output wire [0:0] mem_ck_n, // .mem_ck_n
output wire [0:0] mem_cke, // .mem_cke
output wire [0:0] mem_cs_n, // .mem_cs_n
output wire [3:0] mem_dm, // .mem_dm
output wire [0:0] mem_ras_n, // .mem_ras_n
output wire [0:0] mem_cas_n, // .mem_cas_n
output wire [0:0] mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire [0:0] mem_odt, // .mem_odt
input wire oct_rzqin // oct.rzqin
);
wire pll_afi_clk_clk; // pll:afi_clk -> [c0:afi_clk, p0:afi_clk]
wire pll_afi_half_clk_clk; // pll:afi_half_clk -> [c0:afi_half_clk, p0:afi_half_clk]
wire [4:0] p0_afi_afi_rlat; // p0:afi_rlat -> c0:afi_rlat
wire p0_afi_afi_cal_success; // p0:afi_cal_success -> c0:afi_cal_success
wire [79:0] p0_afi_afi_rdata; // p0:afi_rdata -> c0:afi_rdata
wire [3:0] p0_afi_afi_wlat; // p0:afi_wlat -> c0:afi_wlat
wire p0_afi_afi_cal_fail; // p0:afi_cal_fail -> c0:afi_cal_fail
wire [0:0] p0_afi_afi_rdata_valid; // p0:afi_rdata_valid -> c0:afi_rdata_valid
wire p0_afi_reset_reset; // p0:afi_reset_n -> c0:afi_reset_n
wire [4:0] c0_afi_afi_rdata_en_full; // c0:afi_rdata_en_full -> p0:afi_rdata_en_full
wire [0:0] c0_afi_afi_rst_n; // c0:afi_rst_n -> p0:afi_rst_n
wire [4:0] c0_afi_afi_dqs_burst; // c0:afi_dqs_burst -> p0:afi_dqs_burst
wire [19:0] c0_afi_afi_addr; // c0:afi_addr -> p0:afi_addr
wire [9:0] c0_afi_afi_dm; // c0:afi_dm -> p0:afi_dm
wire [0:0] c0_afi_afi_mem_clk_disable; // c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable
wire [0:0] c0_afi_afi_we_n; // c0:afi_we_n -> p0:afi_we_n
wire [4:0] c0_afi_afi_rdata_en; // c0:afi_rdata_en -> p0:afi_rdata_en
wire [1:0] c0_afi_afi_odt; // c0:afi_odt -> p0:afi_odt
wire [0:0] c0_afi_afi_ras_n; // c0:afi_ras_n -> p0:afi_ras_n
wire [1:0] c0_afi_afi_cke; // c0:afi_cke -> p0:afi_cke
wire [4:0] c0_afi_afi_wdata_valid; // c0:afi_wdata_valid -> p0:afi_wdata_valid
wire [79:0] c0_afi_afi_wdata; // c0:afi_wdata -> p0:afi_wdata
wire [2:0] c0_afi_afi_ba; // c0:afi_ba -> p0:afi_ba
wire [0:0] c0_afi_afi_cas_n; // c0:afi_cas_n -> p0:afi_cas_n
wire [1:0] c0_afi_afi_cs_n; // c0:afi_cs_n -> p0:afi_cs_n
wire [7:0] c0_hard_phy_cfg_cfg_tmrd; // c0:cfg_tmrd -> p0:cfg_tmrd
wire [23:0] c0_hard_phy_cfg_cfg_dramconfig; // c0:cfg_dramconfig -> p0:cfg_dramconfig
wire [7:0] c0_hard_phy_cfg_cfg_rowaddrwidth; // c0:cfg_rowaddrwidth -> p0:cfg_rowaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_devicewidth; // c0:cfg_devicewidth -> p0:cfg_devicewidth
wire [15:0] c0_hard_phy_cfg_cfg_trefi; // c0:cfg_trefi -> p0:cfg_trefi
wire [7:0] c0_hard_phy_cfg_cfg_tcl; // c0:cfg_tcl -> p0:cfg_tcl
wire [7:0] c0_hard_phy_cfg_cfg_csaddrwidth; // c0:cfg_csaddrwidth -> p0:cfg_csaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_coladdrwidth; // c0:cfg_coladdrwidth -> p0:cfg_coladdrwidth
wire [7:0] c0_hard_phy_cfg_cfg_trfc; // c0:cfg_trfc -> p0:cfg_trfc
wire [7:0] c0_hard_phy_cfg_cfg_addlat; // c0:cfg_addlat -> p0:cfg_addlat
wire [7:0] c0_hard_phy_cfg_cfg_bankaddrwidth; // c0:cfg_bankaddrwidth -> p0:cfg_bankaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_interfacewidth; // c0:cfg_interfacewidth -> p0:cfg_interfacewidth
wire [7:0] c0_hard_phy_cfg_cfg_twr; // c0:cfg_twr -> p0:cfg_twr
wire [7:0] c0_hard_phy_cfg_cfg_caswrlat; // c0:cfg_caswrlat -> p0:cfg_caswrlat
wire p0_ctl_clk_clk; // p0:ctl_clk -> c0:ctl_clk
wire p0_ctl_reset_reset; // p0:ctl_reset_n -> c0:ctl_reset_n
wire p0_io_int_io_intaficalfail; // p0:io_intaficalfail -> c0:io_intaficalfail
wire p0_io_int_io_intaficalsuccess; // p0:io_intaficalsuccess -> c0:io_intaficalsuccess
wire [15:0] oct_oct_sharing_parallelterminationcontrol; // oct:parallelterminationcontrol -> p0:parallelterminationcontrol
wire [15:0] oct_oct_sharing_seriesterminationcontrol; // oct:seriesterminationcontrol -> p0:seriesterminationcontrol
wire pll_pll_sharing_pll_write_clk; // pll:pll_write_clk -> p0:pll_write_clk
wire pll_pll_sharing_pll_avl_clk; // pll:pll_avl_clk -> p0:pll_avl_clk
wire pll_pll_sharing_pll_write_clk_pre_phy_clk; // pll:pll_write_clk_pre_phy_clk -> p0:pll_write_clk_pre_phy_clk
wire pll_pll_sharing_pll_addr_cmd_clk; // pll:pll_addr_cmd_clk -> p0:pll_addr_cmd_clk
wire pll_pll_sharing_pll_config_clk; // pll:pll_config_clk -> p0:pll_config_clk
wire pll_pll_sharing_pll_avl_phy_clk; // pll:pll_avl_phy_clk -> p0:pll_avl_phy_clk
wire pll_pll_sharing_afi_phy_clk; // pll:afi_phy_clk -> p0:afi_phy_clk
wire pll_pll_sharing_pll_mem_clk; // pll:pll_mem_clk -> p0:pll_mem_clk
wire pll_pll_sharing_pll_locked; // pll:pll_locked -> p0:pll_locked
wire pll_pll_sharing_pll_mem_phy_clk; // pll:pll_mem_phy_clk -> p0:pll_mem_phy_clk
wire p0_dll_clk_clk; // p0:dll_clk -> dll:clk
wire p0_dll_sharing_dll_pll_locked; // p0:dll_pll_locked -> dll:dll_pll_locked
wire [6:0] dll_dll_sharing_dll_delayctrl; // dll:dll_delayctrl -> p0:dll_delayctrl
hps_sdram_pll pll (
.global_reset_n (global_reset_n), // global_reset.reset_n
.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk) // .pll_avl_phy_clk
);
hps_sdram_p0 p0 (
.global_reset_n (global_reset_n), // global_reset.reset_n
.soft_reset_n (soft_reset_n), // soft_reset.reset_n
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.afi_reset_export_n (), // afi_reset_export.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.avl_clk (), // avl_clk.clk
.avl_reset_n (), // avl_reset.reset_n
.scc_clk (), // scc_clk.clk
.scc_reset_n (), // scc_reset.reset_n
.avl_address (), // avl.address
.avl_write (), // .write
.avl_writedata (), // .writedata
.avl_read (), // .read
.avl_readdata (), // .readdata
.avl_waitrequest (), // .waitrequest
.dll_clk (p0_dll_clk_clk), // dll_clk.clk
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.scc_data (), // scc.scc_data
.scc_dqs_ena (), // .scc_dqs_ena
.scc_dqs_io_ena (), // .scc_dqs_io_ena
.scc_dq_ena (), // .scc_dq_ena
.scc_dm_ena (), // .scc_dm_ena
.capture_strobe_tracking (), // .capture_strobe_tracking
.scc_upd (), // .scc_upd
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // afi_mem_clk_disable.afi_mem_clk_disable
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk), // .pll_avl_phy_clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl), // .dll_delayctrl
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol), // .parallelterminationcontrol
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_dm (mem_dm), // .mem_dm
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.csr_soft_reset_req (1'b0), // (terminated)
.io_intaddrdout (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intbadout (12'b000000000000), // (terminated)
.io_intcasndout (4'b0000), // (terminated)
.io_intckdout (4'b0000), // (terminated)
.io_intckedout (8'b00000000), // (terminated)
.io_intckndout (4'b0000), // (terminated)
.io_intcsndout (8'b00000000), // (terminated)
.io_intdmdout (20'b00000000000000000000), // (terminated)
.io_intdqdin (), // (terminated)
.io_intdqdout (180'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqoe (90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqsbdout (20'b00000000000000000000), // (terminated)
.io_intdqsboe (10'b0000000000), // (terminated)
.io_intdqsdout (20'b00000000000000000000), // (terminated)
.io_intdqslogicdqsena (10'b0000000000), // (terminated)
.io_intdqslogicfiforeset (5'b00000), // (terminated)
.io_intdqslogicincrdataen (10'b0000000000), // (terminated)
.io_intdqslogicincwrptr (10'b0000000000), // (terminated)
.io_intdqslogicoct (10'b0000000000), // (terminated)
.io_intdqslogicrdatavalid (), // (terminated)
.io_intdqslogicreadlatency (25'b0000000000000000000000000), // (terminated)
.io_intdqsoe (10'b0000000000), // (terminated)
.io_intodtdout (8'b00000000), // (terminated)
.io_intrasndout (4'b0000), // (terminated)
.io_intresetndout (4'b0000), // (terminated)
.io_intwendout (4'b0000), // (terminated)
.io_intafirlat (), // (terminated)
.io_intafiwlat () // (terminated)
);
altera_mem_if_hhp_qseq_synth_top #(
.MEM_IF_DM_WIDTH (4),
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_DQ_WIDTH (32)
) seq (
);
altera_mem_if_hard_memory_controller_top_cyclonev #(
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_CHIP_BITS (1),
.MEM_IF_CLK_PAIR_COUNT (1),
.CSR_ADDR_WIDTH (10),
.CSR_DATA_WIDTH (8),
.CSR_BE_WIDTH (1),
.AVL_ADDR_WIDTH (27),
.AVL_DATA_WIDTH (64),
.AVL_SIZE_WIDTH (3),
.AVL_DATA_WIDTH_PORT_0 (1),
.AVL_ADDR_WIDTH_PORT_0 (1),
.AVL_NUM_SYMBOLS_PORT_0 (1),
.LSB_WFIFO_PORT_0 (5),
.MSB_WFIFO_PORT_0 (5),
.LSB_RFIFO_PORT_0 (5),
.MSB_RFIFO_PORT_0 (5),
.AVL_DATA_WIDTH_PORT_1 (1),
.AVL_ADDR_WIDTH_PORT_1 (1),
.AVL_NUM_SYMBOLS_PORT_1 (1),
.LSB_WFIFO_PORT_1 (5),
.MSB_WFIFO_PORT_1 (5),
.LSB_RFIFO_PORT_1 (5),
.MSB_RFIFO_PORT_1 (5),
.AVL_DATA_WIDTH_PORT_2 (1),
.AVL_ADDR_WIDTH_PORT_2 (1),
.AVL_NUM_SYMBOLS_PORT_2 (1),
.LSB_WFIFO_PORT_2 (5),
.MSB_WFIFO_PORT_2 (5),
.LSB_RFIFO_PORT_2 (5),
.MSB_RFIFO_PORT_2 (5),
.AVL_DATA_WIDTH_PORT_3 (1),
.AVL_ADDR_WIDTH_PORT_3 (1),
.AVL_NUM_SYMBOLS_PORT_3 (1),
.LSB_WFIFO_PORT_3 (5),
.MSB_WFIFO_PORT_3 (5),
.LSB_RFIFO_PORT_3 (5),
.MSB_RFIFO_PORT_3 (5),
.AVL_DATA_WIDTH_PORT_4 (1),
.AVL_ADDR_WIDTH_PORT_4 (1),
.AVL_NUM_SYMBOLS_PORT_4 (1),
.LSB_WFIFO_PORT_4 (5),
.MSB_WFIFO_PORT_4 (5),
.LSB_RFIFO_PORT_4 (5),
.MSB_RFIFO_PORT_4 (5),
.AVL_DATA_WIDTH_PORT_5 (1),
.AVL_ADDR_WIDTH_PORT_5 (1),
.AVL_NUM_SYMBOLS_PORT_5 (1),
.LSB_WFIFO_PORT_5 (5),
.MSB_WFIFO_PORT_5 (5),
.LSB_RFIFO_PORT_5 (5),
.MSB_RFIFO_PORT_5 (5),
.ENUM_ATTR_COUNTER_ONE_RESET ("DISABLED"),
.ENUM_ATTR_COUNTER_ZERO_RESET ("DISABLED"),
.ENUM_ATTR_STATIC_CONFIG_VALID ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_0 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_1 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_2 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_3 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_4 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_5 ("DISABLED"),
.ENUM_CAL_REQ ("DISABLED"),
.ENUM_CFG_BURST_LENGTH ("BL_8"),
.ENUM_CFG_INTERFACE_WIDTH ("DWIDTH_32"),
.ENUM_CFG_SELF_RFSH_EXIT_CYCLES ("SELF_RFSH_EXIT_CYCLES_512"),
.ENUM_CFG_STARVE_LIMIT ("STARVE_LIMIT_10"),
.ENUM_CFG_TYPE ("DDR3"),
.ENUM_CLOCK_OFF_0 ("DISABLED"),
.ENUM_CLOCK_OFF_1 ("DISABLED"),
.ENUM_CLOCK_OFF_2 ("DISABLED"),
.ENUM_CLOCK_OFF_3 ("DISABLED"),
.ENUM_CLOCK_OFF_4 ("DISABLED"),
.ENUM_CLOCK_OFF_5 ("DISABLED"),
.ENUM_CLR_INTR ("NO_CLR_INTR"),
.ENUM_CMD_PORT_IN_USE_0 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_1 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_2 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_3 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_4 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_5 ("FALSE"),
.ENUM_CPORT0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT0_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT0_TYPE ("DISABLE"),
.ENUM_CPORT0_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT1_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_TYPE ("DISABLE"),
.ENUM_CPORT1_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT2_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_TYPE ("DISABLE"),
.ENUM_CPORT2_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT3_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_TYPE ("DISABLE"),
.ENUM_CPORT3_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT4_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_TYPE ("DISABLE"),
.ENUM_CPORT4_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT5_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_TYPE ("DISABLE"),
.ENUM_CPORT5_WFIFO_MAP ("FIFO_0"),
.ENUM_CTL_ADDR_ORDER ("CHIP_ROW_BANK_COL"),
.ENUM_CTL_ECC_ENABLED ("CTL_ECC_DISABLED"),
.ENUM_CTL_ECC_RMW_ENABLED ("CTL_ECC_RMW_DISABLED"),
.ENUM_CTL_REGDIMM_ENABLED ("REGDIMM_DISABLED"),
.ENUM_CTL_USR_REFRESH ("CTL_USR_REFRESH_DISABLED"),
.ENUM_CTRL_WIDTH ("DATA_WIDTH_64_BIT"),
.ENUM_DELAY_BONDING ("BONDING_LATENCY_0"),
.ENUM_DFX_BYPASS_ENABLE ("DFX_BYPASS_DISABLED"),
.ENUM_DISABLE_MERGING ("MERGING_ENABLED"),
.ENUM_ECC_DQ_WIDTH ("ECC_DQ_WIDTH_0"),
.ENUM_ENABLE_ATPG ("DISABLED"),
.ENUM_ENABLE_BONDING_0 ("DISABLED"),
.ENUM_ENABLE_BONDING_1 ("DISABLED"),
.ENUM_ENABLE_BONDING_2 ("DISABLED"),
.ENUM_ENABLE_BONDING_3 ("DISABLED"),
.ENUM_ENABLE_BONDING_4 ("DISABLED"),
.ENUM_ENABLE_BONDING_5 ("DISABLED"),
.ENUM_ENABLE_BONDING_WRAPBACK ("DISABLED"),
.ENUM_ENABLE_DQS_TRACKING ("ENABLED"),
.ENUM_ENABLE_ECC_CODE_OVERWRITES ("DISABLED"),
.ENUM_ENABLE_FAST_EXIT_PPD ("DISABLED"),
.ENUM_ENABLE_INTR ("DISABLED"),
.ENUM_ENABLE_NO_DM ("DISABLED"),
.ENUM_ENABLE_PIPELINEGLOBAL ("DISABLED"),
.ENUM_GANGED_ARF ("DISABLED"),
.ENUM_GEN_DBE ("GEN_DBE_DISABLED"),
.ENUM_GEN_SBE ("GEN_SBE_DISABLED"),
.ENUM_INC_SYNC ("FIFO_SET_2"),
.ENUM_LOCAL_IF_CS_WIDTH ("ADDR_WIDTH_0"),
.ENUM_MASK_CORR_DROPPED_INTR ("DISABLED"),
.ENUM_MASK_DBE_INTR ("DISABLED"),
.ENUM_MASK_SBE_INTR ("DISABLED"),
.ENUM_MEM_IF_AL ("AL_0"),
.ENUM_MEM_IF_BANKADDR_WIDTH ("ADDR_WIDTH_3"),
.ENUM_MEM_IF_BURSTLENGTH ("MEM_IF_BURSTLENGTH_8"),
.ENUM_MEM_IF_COLADDR_WIDTH ("ADDR_WIDTH_10"),
.ENUM_MEM_IF_CS_PER_RANK ("MEM_IF_CS_PER_RANK_1"),
.ENUM_MEM_IF_CS_WIDTH ("MEM_IF_CS_WIDTH_1"),
.ENUM_MEM_IF_DQ_PER_CHIP ("MEM_IF_DQ_PER_CHIP_8"),
.ENUM_MEM_IF_DQS_WIDTH ("DQS_WIDTH_4"),
.ENUM_MEM_IF_DWIDTH ("MEM_IF_DWIDTH_32"),
.ENUM_MEM_IF_MEMTYPE ("DDR3_SDRAM"),
.ENUM_MEM_IF_ROWADDR_WIDTH ("ADDR_WIDTH_15"),
.ENUM_MEM_IF_SPEEDBIN ("DDR3_1600_8_8_8"),
.ENUM_MEM_IF_TCCD ("TCCD_4"),
.ENUM_MEM_IF_TCL ("TCL_11"),
.ENUM_MEM_IF_TCWL ("TCWL_8"),
.ENUM_MEM_IF_TFAW ("TFAW_12"),
.ENUM_MEM_IF_TMRD ("TMRD_4"),
.ENUM_MEM_IF_TRAS ("TRAS_14"),
.ENUM_MEM_IF_TRC ("TRC_20"),
.ENUM_MEM_IF_TRCD ("TRCD_6"),
.ENUM_MEM_IF_TRP ("TRP_6"),
.ENUM_MEM_IF_TRRD ("TRRD_3"),
.ENUM_MEM_IF_TRTP ("TRTP_3"),
.ENUM_MEM_IF_TWR ("TWR_6"),
.ENUM_MEM_IF_TWTR ("TWTR_4"),
.ENUM_MMR_CFG_MEM_BL ("MP_BL_8"),
.ENUM_OUTPUT_REGD ("DISABLED"),
.ENUM_PDN_EXIT_CYCLES ("SLOW_EXIT"),
.ENUM_PORT0_WIDTH ("PORT_32_BIT"),
.ENUM_PORT1_WIDTH ("PORT_32_BIT"),
.ENUM_PORT2_WIDTH ("PORT_32_BIT"),
.ENUM_PORT3_WIDTH ("PORT_32_BIT"),
.ENUM_PORT4_WIDTH ("PORT_32_BIT"),
.ENUM_PORT5_WIDTH ("PORT_32_BIT"),
.ENUM_PRIORITY_0_0 ("WEIGHT_0"),
.ENUM_PRIORITY_0_1 ("WEIGHT_0"),
.ENUM_PRIORITY_0_2 ("WEIGHT_0"),
.ENUM_PRIORITY_0_3 ("WEIGHT_0"),
.ENUM_PRIORITY_0_4 ("WEIGHT_0"),
.ENUM_PRIORITY_0_5 ("WEIGHT_0"),
.ENUM_PRIORITY_1_0 ("WEIGHT_0"),
.ENUM_PRIORITY_1_1 ("WEIGHT_0"),
.ENUM_PRIORITY_1_2 ("WEIGHT_0"),
.ENUM_PRIORITY_1_3 ("WEIGHT_0"),
.ENUM_PRIORITY_1_4 ("WEIGHT_0"),
.ENUM_PRIORITY_1_5 ("WEIGHT_0"),
.ENUM_PRIORITY_2_0 ("WEIGHT_0"),
.ENUM_PRIORITY_2_1 ("WEIGHT_0"),
.ENUM_PRIORITY_2_2 ("WEIGHT_0"),
.ENUM_PRIORITY_2_3 ("WEIGHT_0"),
.ENUM_PRIORITY_2_4 ("WEIGHT_0"),
.ENUM_PRIORITY_2_5 ("WEIGHT_0"),
.ENUM_PRIORITY_3_0 ("WEIGHT_0"),
.ENUM_PRIORITY_3_1 ("WEIGHT_0"),
.ENUM_PRIORITY_3_2 ("WEIGHT_0"),
.ENUM_PRIORITY_3_3 ("WEIGHT_0"),
.ENUM_PRIORITY_3_4 ("WEIGHT_0"),
.ENUM_PRIORITY_3_5 ("WEIGHT_0"),
.ENUM_PRIORITY_4_0 ("WEIGHT_0"),
.ENUM_PRIORITY_4_1 ("WEIGHT_0"),
.ENUM_PRIORITY_4_2 ("WEIGHT_0"),
.ENUM_PRIORITY_4_3 ("WEIGHT_0"),
.ENUM_PRIORITY_4_4 ("WEIGHT_0"),
.ENUM_PRIORITY_4_5 ("WEIGHT_0"),
.ENUM_PRIORITY_5_0 ("WEIGHT_0"),
.ENUM_PRIORITY_5_1 ("WEIGHT_0"),
.ENUM_PRIORITY_5_2 ("WEIGHT_0"),
.ENUM_PRIORITY_5_3 ("WEIGHT_0"),
.ENUM_PRIORITY_5_4 ("WEIGHT_0"),
.ENUM_PRIORITY_5_5 ("WEIGHT_0"),
.ENUM_PRIORITY_6_0 ("WEIGHT_0"),
.ENUM_PRIORITY_6_1 ("WEIGHT_0"),
.ENUM_PRIORITY_6_2 ("WEIGHT_0"),
.ENUM_PRIORITY_6_3 ("WEIGHT_0"),
.ENUM_PRIORITY_6_4 ("WEIGHT_0"),
.ENUM_PRIORITY_6_5 ("WEIGHT_0"),
.ENUM_PRIORITY_7_0 ("WEIGHT_0"),
.ENUM_PRIORITY_7_1 ("WEIGHT_0"),
.ENUM_PRIORITY_7_2 ("WEIGHT_0"),
.ENUM_PRIORITY_7_3 ("WEIGHT_0"),
.ENUM_PRIORITY_7_4 ("WEIGHT_0"),
.ENUM_PRIORITY_7_5 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_RCFG_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_RD_DWIDTH_0 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_1 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_2 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_3 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_4 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_5 ("DWIDTH_0"),
.ENUM_RD_FIFO_IN_USE_0 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_1 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_2 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_3 ("FALSE"),
.ENUM_RD_PORT_INFO_0 ("USE_NO"),
.ENUM_RD_PORT_INFO_1 ("USE_NO"),
.ENUM_RD_PORT_INFO_2 ("USE_NO"),
.ENUM_RD_PORT_INFO_3 ("USE_NO"),
.ENUM_RD_PORT_INFO_4 ("USE_NO"),
.ENUM_RD_PORT_INFO_5 ("USE_NO"),
.ENUM_READ_ODT_CHIP ("ODT_DISABLED"),
.ENUM_REORDER_DATA ("DATA_REORDERING"),
.ENUM_RFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_SINGLE_READY_0 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_1 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_2 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_3 ("CONCATENATE_RDY"),
.ENUM_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_SYNC_MODE_0 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_1 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_2 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_3 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_4 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_5 ("ASYNCHRONOUS"),
.ENUM_TEST_MODE ("NORMAL_MODE"),
.ENUM_THLD_JAR1_0 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_1 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_2 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_3 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_4 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_5 ("THRESHOLD_32"),
.ENUM_THLD_JAR2_0 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_1 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_2 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_3 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_4 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_5 ("THRESHOLD_16"),
.ENUM_USE_ALMOST_EMPTY_0 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_1 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_2 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_3 ("EMPTY"),
.ENUM_USER_ECC_EN ("DISABLE"),
.ENUM_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_WFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WR_DWIDTH_0 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_1 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_2 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_3 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_4 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_5 ("DWIDTH_0"),
.ENUM_WR_FIFO_IN_USE_0 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_1 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_2 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_3 ("FALSE"),
.ENUM_WR_PORT_INFO_0 ("USE_NO"),
.ENUM_WR_PORT_INFO_1 ("USE_NO"),
.ENUM_WR_PORT_INFO_2 ("USE_NO"),
.ENUM_WR_PORT_INFO_3 ("USE_NO"),
.ENUM_WR_PORT_INFO_4 ("USE_NO"),
.ENUM_WR_PORT_INFO_5 ("USE_NO"),
.ENUM_WRITE_ODT_CHIP ("WRITE_CHIP0_ODT0_CHIP1"),
.INTG_MEM_AUTO_PD_CYCLES (0),
.INTG_CYC_TO_RLD_JARS_0 (1),
.INTG_CYC_TO_RLD_JARS_1 (1),
.INTG_CYC_TO_RLD_JARS_2 (1),
.INTG_CYC_TO_RLD_JARS_3 (1),
.INTG_CYC_TO_RLD_JARS_4 (1),
.INTG_CYC_TO_RLD_JARS_5 (1),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_RDWR (0),
.INTG_EXTRA_CTL_CLK_ARF_PERIOD (0),
.INTG_EXTRA_CTL_CLK_ARF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PCH_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PDN_PERIOD (0),
.INTG_EXTRA_CTL_CLK_PDN_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP (0),
.INTG_EXTRA_CTL_CLK_RD_TO_WR (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_BC (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (2),
.INTG_EXTRA_CTL_CLK_SRF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL (0),
.INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_WR_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_WR_TO_RD (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_BC (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP (3),
.INTG_EXTRA_CTL_CLK_WR_TO_WR (0),
.INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP (0),
.INTG_MEM_IF_TREFI (3120),
.INTG_MEM_IF_TRFC (104),
.INTG_RCFG_SUM_WT_PRIORITY_0 (0),
.INTG_RCFG_SUM_WT_PRIORITY_1 (0),
.INTG_RCFG_SUM_WT_PRIORITY_2 (0),
.INTG_RCFG_SUM_WT_PRIORITY_3 (0),
.INTG_RCFG_SUM_WT_PRIORITY_4 (0),
.INTG_RCFG_SUM_WT_PRIORITY_5 (0),
.INTG_RCFG_SUM_WT_PRIORITY_6 (0),
.INTG_RCFG_SUM_WT_PRIORITY_7 (0),
.INTG_SUM_WT_PRIORITY_0 (0),
.INTG_SUM_WT_PRIORITY_1 (0),
.INTG_SUM_WT_PRIORITY_2 (0),
.INTG_SUM_WT_PRIORITY_3 (0),
.INTG_SUM_WT_PRIORITY_4 (0),
.INTG_SUM_WT_PRIORITY_5 (0),
.INTG_SUM_WT_PRIORITY_6 (0),
.INTG_SUM_WT_PRIORITY_7 (0),
.INTG_POWER_SAVING_EXIT_CYCLES (5),
.INTG_MEM_CLK_ENTRY_CYCLES (10),
.ENUM_ENABLE_BURST_INTERRUPT ("DISABLED"),
.ENUM_ENABLE_BURST_TERMINATE ("DISABLED"),
.AFI_RATE_RATIO (1),
.AFI_ADDR_WIDTH (15),
.AFI_BANKADDR_WIDTH (3),
.AFI_CONTROL_WIDTH (1),
.AFI_CS_WIDTH (1),
.AFI_DM_WIDTH (8),
.AFI_DQ_WIDTH (64),
.AFI_ODT_WIDTH (1),
.AFI_WRITE_DQS_WIDTH (4),
.AFI_RLAT_WIDTH (6),
.AFI_WLAT_WIDTH (6),
.HARD_PHY (1)
) c0 (
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.local_init_done (), // status.local_init_done
.local_cal_success (), // .local_cal_success
.local_cal_fail (), // .local_cal_fail
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // .afi_mem_clk_disable
.afi_init_req (), // .afi_init_req
.afi_cal_req (), // .afi_cal_req
.afi_seq_busy (), // .afi_seq_busy
.afi_ctl_refresh_done (), // .afi_ctl_refresh_done
.afi_ctl_long_idle (), // .afi_ctl_long_idle
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.mp_cmd_clk_0 (1'b0), // (terminated)
.mp_cmd_reset_n_0 (1'b1), // (terminated)
.mp_cmd_clk_1 (1'b0), // (terminated)
.mp_cmd_reset_n_1 (1'b1), // (terminated)
.mp_cmd_clk_2 (1'b0), // (terminated)
.mp_cmd_reset_n_2 (1'b1), // (terminated)
.mp_cmd_clk_3 (1'b0), // (terminated)
.mp_cmd_reset_n_3 (1'b1), // (terminated)
.mp_cmd_clk_4 (1'b0), // (terminated)
.mp_cmd_reset_n_4 (1'b1), // (terminated)
.mp_cmd_clk_5 (1'b0), // (terminated)
.mp_cmd_reset_n_5 (1'b1), // (terminated)
.mp_rfifo_clk_0 (1'b0), // (terminated)
.mp_rfifo_reset_n_0 (1'b1), // (terminated)
.mp_wfifo_clk_0 (1'b0), // (terminated)
.mp_wfifo_reset_n_0 (1'b1), // (terminated)
.mp_rfifo_clk_1 (1'b0), // (terminated)
.mp_rfifo_reset_n_1 (1'b1), // (terminated)
.mp_wfifo_clk_1 (1'b0), // (terminated)
.mp_wfifo_reset_n_1 (1'b1), // (terminated)
.mp_rfifo_clk_2 (1'b0), // (terminated)
.mp_rfifo_reset_n_2 (1'b1), // (terminated)
.mp_wfifo_clk_2 (1'b0), // (terminated)
.mp_wfifo_reset_n_2 (1'b1), // (terminated)
.mp_rfifo_clk_3 (1'b0), // (terminated)
.mp_rfifo_reset_n_3 (1'b1), // (terminated)
.mp_wfifo_clk_3 (1'b0), // (terminated)
.mp_wfifo_reset_n_3 (1'b1), // (terminated)
.csr_clk (1'b0), // (terminated)
.csr_reset_n (1'b1), // (terminated)
.avl_ready_0 (), // (terminated)
.avl_burstbegin_0 (1'b0), // (terminated)
.avl_addr_0 (1'b0), // (terminated)
.avl_rdata_valid_0 (), // (terminated)
.avl_rdata_0 (), // (terminated)
.avl_wdata_0 (1'b0), // (terminated)
.avl_be_0 (1'b0), // (terminated)
.avl_read_req_0 (1'b0), // (terminated)
.avl_write_req_0 (1'b0), // (terminated)
.avl_size_0 (3'b000), // (terminated)
.avl_ready_1 (), // (terminated)
.avl_burstbegin_1 (1'b0), // (terminated)
.avl_addr_1 (1'b0), // (terminated)
.avl_rdata_valid_1 (), // (terminated)
.avl_rdata_1 (), // (terminated)
.avl_wdata_1 (1'b0), // (terminated)
.avl_be_1 (1'b0), // (terminated)
.avl_read_req_1 (1'b0), // (terminated)
.avl_write_req_1 (1'b0), // (terminated)
.avl_size_1 (3'b000), // (terminated)
.avl_ready_2 (), // (terminated)
.avl_burstbegin_2 (1'b0), // (terminated)
.avl_addr_2 (1'b0), // (terminated)
.avl_rdata_valid_2 (), // (terminated)
.avl_rdata_2 (), // (terminated)
.avl_wdata_2 (1'b0), // (terminated)
.avl_be_2 (1'b0), // (terminated)
.avl_read_req_2 (1'b0), // (terminated)
.avl_write_req_2 (1'b0), // (terminated)
.avl_size_2 (3'b000), // (terminated)
.avl_ready_3 (), // (terminated)
.avl_burstbegin_3 (1'b0), // (terminated)
.avl_addr_3 (1'b0), // (terminated)
.avl_rdata_valid_3 (), // (terminated)
.avl_rdata_3 (), // (terminated)
.avl_wdata_3 (1'b0), // (terminated)
.avl_be_3 (1'b0), // (terminated)
.avl_read_req_3 (1'b0), // (terminated)
.avl_write_req_3 (1'b0), // (terminated)
.avl_size_3 (3'b000), // (terminated)
.avl_ready_4 (), // (terminated)
.avl_burstbegin_4 (1'b0), // (terminated)
.avl_addr_4 (1'b0), // (terminated)
.avl_rdata_valid_4 (), // (terminated)
.avl_rdata_4 (), // (terminated)
.avl_wdata_4 (1'b0), // (terminated)
.avl_be_4 (1'b0), // (terminated)
.avl_read_req_4 (1'b0), // (terminated)
.avl_write_req_4 (1'b0), // (terminated)
.avl_size_4 (3'b000), // (terminated)
.avl_ready_5 (), // (terminated)
.avl_burstbegin_5 (1'b0), // (terminated)
.avl_addr_5 (1'b0), // (terminated)
.avl_rdata_valid_5 (), // (terminated)
.avl_rdata_5 (), // (terminated)
.avl_wdata_5 (1'b0), // (terminated)
.avl_be_5 (1'b0), // (terminated)
.avl_read_req_5 (1'b0), // (terminated)
.avl_write_req_5 (1'b0), // (terminated)
.avl_size_5 (3'b000), // (terminated)
.csr_write_req (1'b0), // (terminated)
.csr_read_req (1'b0), // (terminated)
.csr_waitrequest (), // (terminated)
.csr_addr (10'b0000000000), // (terminated)
.csr_be (1'b0), // (terminated)
.csr_wdata (8'b00000000), // (terminated)
.csr_rdata (), // (terminated)
.csr_rdata_valid (), // (terminated)
.local_multicast (1'b0), // (terminated)
.local_refresh_req (1'b0), // (terminated)
.local_refresh_chip (1'b0), // (terminated)
.local_refresh_ack (), // (terminated)
.local_self_rfsh_req (1'b0), // (terminated)
.local_self_rfsh_chip (1'b0), // (terminated)
.local_self_rfsh_ack (), // (terminated)
.local_deep_powerdn_req (1'b0), // (terminated)
.local_deep_powerdn_chip (1'b0), // (terminated)
.local_deep_powerdn_ack (), // (terminated)
.local_powerdn_ack (), // (terminated)
.local_priority (1'b0), // (terminated)
.bonding_in_1 (4'b0000), // (terminated)
.bonding_in_2 (6'b000000), // (terminated)
.bonding_in_3 (6'b000000), // (terminated)
.bonding_out_1 (), // (terminated)
.bonding_out_2 (), // (terminated)
.bonding_out_3 () // (terminated)
);
altera_mem_if_oct_cyclonev #(
.OCT_TERM_CONTROL_WIDTH (16)
) oct (
.oct_rzqin (oct_rzqin), // oct.rzqin
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol) // .parallelterminationcontrol
);
altera_mem_if_dll_cyclonev #(
.DLL_DELAY_CTRL_WIDTH (7),
.DLL_OFFSET_CTRL_WIDTH (6),
.DELAY_BUFFER_MODE ("HIGH"),
.DELAY_CHAIN_LENGTH (8),
.DLL_INPUT_FREQUENCY_PS_STR ("2500 ps")
) dll (
.clk (p0_dll_clk_clk), // clk.clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl) // .dll_delayctrl
);
endmodule
|
//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// valid O 1
// addr O 64
// word64 O 64
// st_amo_val O 64
// exc O 1
// exc_code O 4
// RDY_flush_server_request_put O 1 reg
// RDY_flush_server_response_get O 1 reg
// RDY_tlb_flush O 1 const
// RDY_imem_ptw_server_request_put O 1 reg
// imem_ptw_server_response_get O 132 reg
// RDY_imem_ptw_server_response_get O 1 reg
// RDY_imem_pte_writeback_p_put O 1 reg
// l1_to_l2_client_request_first O 69 reg
// RDY_l1_to_l2_client_request_first O 1 reg
// RDY_l1_to_l2_client_request_deq O 1 reg
// l1_to_l2_client_request_notEmpty O 1 reg
// RDY_l1_to_l2_client_request_notEmpty O 1 const
// RDY_l1_to_l2_client_response_enq O 1 reg
// l1_to_l2_client_response_notFull O 1 reg
// RDY_l1_to_l2_client_response_notFull O 1 const
// RDY_l2_to_l1_server_request_enq O 1 reg
// l2_to_l1_server_request_notFull O 1 reg
// RDY_l2_to_l1_server_request_notFull O 1 const
// l2_to_l1_server_response_first O 579 reg
// RDY_l2_to_l1_server_response_first O 1 reg
// RDY_l2_to_l1_server_response_deq O 1 reg
// l2_to_l1_server_response_notEmpty O 1 reg
// RDY_l2_to_l1_server_response_notEmpty O 1 const
// mmio_client_request_get O 131 reg
// RDY_mmio_client_request_get O 1 reg
// RDY_mmio_client_response_put O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// ma_req_op I 2
// ma_req_f3 I 3
// ma_req_amo_funct7 I 7
// ma_req_va I 64
// ma_req_st_value I 64
// ma_req_priv I 2
// ma_req_sstatus_SUM I 1
// ma_req_mstatus_MXR I 1
// ma_req_satp I 64
// flush_server_request_put I 1 reg
// imem_ptw_server_request_put I 128 reg
// imem_pte_writeback_p_put I 128 reg
// l1_to_l2_client_response_enq_x I 579 reg
// l2_to_l1_server_request_enq_x I 66 reg
// mmio_client_response_put I 65 reg
// EN_ma_req I 1
// EN_flush_server_request_put I 1
// EN_flush_server_response_get I 1
// EN_tlb_flush I 1
// EN_imem_ptw_server_request_put I 1
// EN_imem_pte_writeback_p_put I 1
// EN_l1_to_l2_client_request_deq I 1
// EN_l1_to_l2_client_response_enq I 1
// EN_l2_to_l1_server_request_enq I 1
// EN_l2_to_l1_server_response_deq I 1
// EN_mmio_client_response_put I 1
// EN_imem_ptw_server_response_get I 1
// EN_mmio_client_request_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkD_MMU_Cache(CLK,
RST_N,
ma_req_op,
ma_req_f3,
ma_req_amo_funct7,
ma_req_va,
ma_req_st_value,
ma_req_priv,
ma_req_sstatus_SUM,
ma_req_mstatus_MXR,
ma_req_satp,
EN_ma_req,
valid,
addr,
word64,
st_amo_val,
exc,
exc_code,
flush_server_request_put,
EN_flush_server_request_put,
RDY_flush_server_request_put,
EN_flush_server_response_get,
RDY_flush_server_response_get,
EN_tlb_flush,
RDY_tlb_flush,
imem_ptw_server_request_put,
EN_imem_ptw_server_request_put,
RDY_imem_ptw_server_request_put,
EN_imem_ptw_server_response_get,
imem_ptw_server_response_get,
RDY_imem_ptw_server_response_get,
imem_pte_writeback_p_put,
EN_imem_pte_writeback_p_put,
RDY_imem_pte_writeback_p_put,
l1_to_l2_client_request_first,
RDY_l1_to_l2_client_request_first,
EN_l1_to_l2_client_request_deq,
RDY_l1_to_l2_client_request_deq,
l1_to_l2_client_request_notEmpty,
RDY_l1_to_l2_client_request_notEmpty,
l1_to_l2_client_response_enq_x,
EN_l1_to_l2_client_response_enq,
RDY_l1_to_l2_client_response_enq,
l1_to_l2_client_response_notFull,
RDY_l1_to_l2_client_response_notFull,
l2_to_l1_server_request_enq_x,
EN_l2_to_l1_server_request_enq,
RDY_l2_to_l1_server_request_enq,
l2_to_l1_server_request_notFull,
RDY_l2_to_l1_server_request_notFull,
l2_to_l1_server_response_first,
RDY_l2_to_l1_server_response_first,
EN_l2_to_l1_server_response_deq,
RDY_l2_to_l1_server_response_deq,
l2_to_l1_server_response_notEmpty,
RDY_l2_to_l1_server_response_notEmpty,
EN_mmio_client_request_get,
mmio_client_request_get,
RDY_mmio_client_request_get,
mmio_client_response_put,
EN_mmio_client_response_put,
RDY_mmio_client_response_put);
input CLK;
input RST_N;
// action method ma_req
input [1 : 0] ma_req_op;
input [2 : 0] ma_req_f3;
input [6 : 0] ma_req_amo_funct7;
input [63 : 0] ma_req_va;
input [63 : 0] ma_req_st_value;
input [1 : 0] ma_req_priv;
input ma_req_sstatus_SUM;
input ma_req_mstatus_MXR;
input [63 : 0] ma_req_satp;
input EN_ma_req;
// value method valid
output valid;
// value method addr
output [63 : 0] addr;
// value method word64
output [63 : 0] word64;
// value method st_amo_val
output [63 : 0] st_amo_val;
// value method exc
output exc;
// value method exc_code
output [3 : 0] exc_code;
// action method flush_server_request_put
input flush_server_request_put;
input EN_flush_server_request_put;
output RDY_flush_server_request_put;
// action method flush_server_response_get
input EN_flush_server_response_get;
output RDY_flush_server_response_get;
// action method tlb_flush
input EN_tlb_flush;
output RDY_tlb_flush;
// action method imem_ptw_server_request_put
input [127 : 0] imem_ptw_server_request_put;
input EN_imem_ptw_server_request_put;
output RDY_imem_ptw_server_request_put;
// actionvalue method imem_ptw_server_response_get
input EN_imem_ptw_server_response_get;
output [131 : 0] imem_ptw_server_response_get;
output RDY_imem_ptw_server_response_get;
// action method imem_pte_writeback_p_put
input [127 : 0] imem_pte_writeback_p_put;
input EN_imem_pte_writeback_p_put;
output RDY_imem_pte_writeback_p_put;
// value method l1_to_l2_client_request_first
output [68 : 0] l1_to_l2_client_request_first;
output RDY_l1_to_l2_client_request_first;
// action method l1_to_l2_client_request_deq
input EN_l1_to_l2_client_request_deq;
output RDY_l1_to_l2_client_request_deq;
// value method l1_to_l2_client_request_notEmpty
output l1_to_l2_client_request_notEmpty;
output RDY_l1_to_l2_client_request_notEmpty;
// action method l1_to_l2_client_response_enq
input [578 : 0] l1_to_l2_client_response_enq_x;
input EN_l1_to_l2_client_response_enq;
output RDY_l1_to_l2_client_response_enq;
// value method l1_to_l2_client_response_notFull
output l1_to_l2_client_response_notFull;
output RDY_l1_to_l2_client_response_notFull;
// action method l2_to_l1_server_request_enq
input [65 : 0] l2_to_l1_server_request_enq_x;
input EN_l2_to_l1_server_request_enq;
output RDY_l2_to_l1_server_request_enq;
// value method l2_to_l1_server_request_notFull
output l2_to_l1_server_request_notFull;
output RDY_l2_to_l1_server_request_notFull;
// value method l2_to_l1_server_response_first
output [578 : 0] l2_to_l1_server_response_first;
output RDY_l2_to_l1_server_response_first;
// action method l2_to_l1_server_response_deq
input EN_l2_to_l1_server_response_deq;
output RDY_l2_to_l1_server_response_deq;
// value method l2_to_l1_server_response_notEmpty
output l2_to_l1_server_response_notEmpty;
output RDY_l2_to_l1_server_response_notEmpty;
// actionvalue method mmio_client_request_get
input EN_mmio_client_request_get;
output [130 : 0] mmio_client_request_get;
output RDY_mmio_client_request_get;
// action method mmio_client_response_put
input [64 : 0] mmio_client_response_put;
input EN_mmio_client_response_put;
output RDY_mmio_client_response_put;
// signals for module outputs
wire [578 : 0] l2_to_l1_server_response_first;
wire [131 : 0] imem_ptw_server_response_get;
wire [130 : 0] mmio_client_request_get;
wire [68 : 0] l1_to_l2_client_request_first;
wire [63 : 0] addr, st_amo_val, word64;
wire [3 : 0] exc_code;
wire RDY_flush_server_request_put,
RDY_flush_server_response_get,
RDY_imem_pte_writeback_p_put,
RDY_imem_ptw_server_request_put,
RDY_imem_ptw_server_response_get,
RDY_l1_to_l2_client_request_deq,
RDY_l1_to_l2_client_request_first,
RDY_l1_to_l2_client_request_notEmpty,
RDY_l1_to_l2_client_response_enq,
RDY_l1_to_l2_client_response_notFull,
RDY_l2_to_l1_server_request_enq,
RDY_l2_to_l1_server_request_notFull,
RDY_l2_to_l1_server_response_deq,
RDY_l2_to_l1_server_response_first,
RDY_l2_to_l1_server_response_notEmpty,
RDY_mmio_client_request_get,
RDY_mmio_client_response_put,
RDY_tlb_flush,
exc,
l1_to_l2_client_request_notEmpty,
l1_to_l2_client_response_notFull,
l2_to_l1_server_request_notFull,
l2_to_l1_server_response_notEmpty,
valid;
// inlined wires
reg [3 : 0] crg_exc_code$port0__write_1, crg_state$port0__write_1;
reg [1 : 0] crg_mmu_cache_req_state$port0__write_1;
reg crg_exc$port0__write_1;
wire [207 : 0] crg_mmu_cache_req$port1__write_1,
crg_mmu_cache_req$port2__read;
wire [63 : 0] crg_final_st_val$port0__write_1,
crg_final_st_val$port1__read,
crg_ld_val$port0__write_1,
crg_ld_val$port1__read;
wire [3 : 0] crg_exc_code$port1__read, crg_state$port1__read;
wire [1 : 0] crg_mmu_cache_req_state$port1__read,
crg_mmu_cache_req_state$port1__write_1,
crg_mmu_cache_req_state$port2__read;
wire crg_exc$EN_port0__write,
crg_exc$port1__read,
crg_exc_code$EN_port0__write,
crg_final_st_val$EN_port0__write,
crg_ld_val$EN_port0__write,
crg_mmu_cache_req_state$EN_port0__write,
crg_state$EN_port0__write,
crg_valid$EN_port0__write,
crg_valid$port0__write_1,
crg_valid$port1__read,
crg_valid$port2__read;
// register crg_exc
reg crg_exc;
wire crg_exc$D_IN, crg_exc$EN;
// register crg_exc_code
reg [3 : 0] crg_exc_code;
wire [3 : 0] crg_exc_code$D_IN;
wire crg_exc_code$EN;
// register crg_final_st_val
reg [63 : 0] crg_final_st_val;
wire [63 : 0] crg_final_st_val$D_IN;
wire crg_final_st_val$EN;
// register crg_ld_val
reg [63 : 0] crg_ld_val;
wire [63 : 0] crg_ld_val$D_IN;
wire crg_ld_val$EN;
// register crg_mmu_cache_req
reg [207 : 0] crg_mmu_cache_req;
wire [207 : 0] crg_mmu_cache_req$D_IN;
wire crg_mmu_cache_req$EN;
// register crg_mmu_cache_req_state
reg [1 : 0] crg_mmu_cache_req_state;
wire [1 : 0] crg_mmu_cache_req_state$D_IN;
wire crg_mmu_cache_req_state$EN;
// register crg_state
reg [3 : 0] crg_state;
wire [3 : 0] crg_state$D_IN;
wire crg_state$EN;
// register crg_valid
reg crg_valid;
wire crg_valid$D_IN, crg_valid$EN;
// register rg_ptw_mem_req
reg [63 : 0] rg_ptw_mem_req;
wire [63 : 0] rg_ptw_mem_req$D_IN;
wire rg_ptw_mem_req$EN;
// register rg_state_stack_during_ptw_rd
reg [3 : 0] rg_state_stack_during_ptw_rd;
wire [3 : 0] rg_state_stack_during_ptw_rd$D_IN;
wire rg_state_stack_during_ptw_rd$EN;
// ports of submodule cache
reg [207 : 0] cache$mav_request_pa_req;
reg [63 : 0] cache$ma_request_va_va, cache$mav_request_pa_pa;
wire [578 : 0] cache$l1_to_l2_client_response_enq_x,
cache$l2_to_l1_server_response_first;
wire [129 : 0] cache$mav_request_pa;
wire [68 : 0] cache$l1_to_l2_client_request_first;
wire [65 : 0] cache$l2_to_l1_server_request_enq_x;
wire cache$EN_flush_server_request_put,
cache$EN_flush_server_response_get,
cache$EN_l1_to_l2_client_request_deq,
cache$EN_l1_to_l2_client_response_enq,
cache$EN_l2_to_l1_server_request_enq,
cache$EN_l2_to_l1_server_response_deq,
cache$EN_ma_request_va,
cache$EN_mav_request_pa,
cache$RDY_flush_server_request_put,
cache$RDY_flush_server_response_get,
cache$RDY_l1_to_l2_client_request_deq,
cache$RDY_l1_to_l2_client_request_first,
cache$RDY_l1_to_l2_client_response_enq,
cache$RDY_l2_to_l1_server_request_enq,
cache$RDY_l2_to_l1_server_response_deq,
cache$RDY_l2_to_l1_server_response_first,
cache$RDY_mav_request_pa,
cache$RDY_mv_refill_ok,
cache$flush_server_request_put,
cache$l1_to_l2_client_request_notEmpty,
cache$l1_to_l2_client_response_notFull,
cache$l2_to_l1_server_request_notFull,
cache$l2_to_l1_server_response_notEmpty,
cache$mv_is_idle,
cache$mv_refill_ok;
// ports of submodule f_cache_flush_reqs
wire f_cache_flush_reqs$CLR,
f_cache_flush_reqs$DEQ,
f_cache_flush_reqs$D_IN,
f_cache_flush_reqs$D_OUT,
f_cache_flush_reqs$EMPTY_N,
f_cache_flush_reqs$ENQ,
f_cache_flush_reqs$FULL_N;
// ports of submodule f_cache_flush_rsps
wire f_cache_flush_rsps$CLR,
f_cache_flush_rsps$DEQ,
f_cache_flush_rsps$EMPTY_N,
f_cache_flush_rsps$ENQ,
f_cache_flush_rsps$FULL_N;
// ports of submodule f_dmem_pte_writebacks
wire [127 : 0] f_dmem_pte_writebacks$D_IN, f_dmem_pte_writebacks$D_OUT;
wire f_dmem_pte_writebacks$CLR,
f_dmem_pte_writebacks$DEQ,
f_dmem_pte_writebacks$EMPTY_N,
f_dmem_pte_writebacks$ENQ,
f_dmem_pte_writebacks$FULL_N;
// ports of submodule f_imem_pte_writebacks
wire [127 : 0] f_imem_pte_writebacks$D_IN, f_imem_pte_writebacks$D_OUT;
wire f_imem_pte_writebacks$CLR,
f_imem_pte_writebacks$DEQ,
f_imem_pte_writebacks$EMPTY_N,
f_imem_pte_writebacks$ENQ,
f_imem_pte_writebacks$FULL_N;
// ports of submodule f_pte_writebacks
wire [127 : 0] f_pte_writebacks$D_IN, f_pte_writebacks$D_OUT;
wire f_pte_writebacks$CLR,
f_pte_writebacks$DEQ,
f_pte_writebacks$EMPTY_N,
f_pte_writebacks$ENQ,
f_pte_writebacks$FULL_N;
// ports of submodule mmio
wire [207 : 0] mmio$req_mmu_cache_req;
wire [130 : 0] mmio$mmio_client_request_get;
wire [64 : 0] mmio$mmio_client_response_put;
wire [63 : 0] mmio$result_snd_fst, mmio$result_snd_snd, mmio$start_pa;
wire mmio$EN_mmio_client_request_get,
mmio$EN_mmio_client_response_put,
mmio$EN_req,
mmio$EN_start,
mmio$RDY_mmio_client_request_get,
mmio$RDY_mmio_client_response_put,
mmio$RDY_result_fst,
mmio$RDY_result_snd_fst,
mmio$RDY_result_snd_snd,
mmio$result_fst;
// ports of submodule ptw
wire [131 : 0] ptw$dmem_server_response_get, ptw$imem_server_response_get;
wire [127 : 0] ptw$dmem_server_request_put, ptw$imem_server_request_put;
wire [64 : 0] ptw$mem_client_response_put;
wire [63 : 0] ptw$mem_client_request_get;
wire ptw$EN_dmem_server_request_put,
ptw$EN_dmem_server_response_get,
ptw$EN_imem_server_request_put,
ptw$EN_imem_server_response_get,
ptw$EN_mem_client_request_get,
ptw$EN_mem_client_response_put,
ptw$RDY_dmem_server_request_put,
ptw$RDY_dmem_server_response_get,
ptw$RDY_imem_server_request_put,
ptw$RDY_imem_server_response_get,
ptw$RDY_mem_client_request_get,
ptw$RDY_mem_client_response_put;
// ports of submodule soc_map
wire [63 : 0] soc_map$m_is_IO_addr_addr,
soc_map$m_is_mem_addr_addr,
soc_map$m_is_near_mem_IO_addr_addr;
wire soc_map$m_is_mem_addr;
// ports of submodule tlb
wire [200 : 0] tlb$mv_vm_xlate;
wire [63 : 0] tlb$ma_insert_pte,
tlb$ma_insert_pte_pa,
tlb$mv_vm_xlate_satp,
tlb$mv_vm_xlate_va;
wire [26 : 0] tlb$ma_insert_vpn;
wire [15 : 0] tlb$ma_insert_asid;
wire [1 : 0] tlb$ma_insert_level, tlb$mv_vm_xlate_priv;
wire tlb$EN_ma_flush,
tlb$EN_ma_insert,
tlb$mv_vm_xlate_mstatus_MXR,
tlb$mv_vm_xlate_read_not_write,
tlb$mv_vm_xlate_sstatus_SUM;
// rule scheduling signals
wire CAN_FIRE_RL_mkConnectionGetPut,
CAN_FIRE_RL_mkConnectionGetPut_1,
CAN_FIRE_RL_rl_CPU_ST_wait,
CAN_FIRE_RL_rl_CPU_cache_wait,
CAN_FIRE_RL_rl_CPU_req,
CAN_FIRE_RL_rl_CPU_req_A,
CAN_FIRE_RL_rl_CPU_req_B,
CAN_FIRE_RL_rl_CPU_req_mmio_WAIT,
CAN_FIRE_RL_rl_PTW_wait,
CAN_FIRE_RL_rl_cache_flush_finish,
CAN_FIRE_RL_rl_cache_flush_start,
CAN_FIRE_RL_rl_pte_wb_cache_WAIT,
CAN_FIRE_RL_rl_pte_wb_req_A,
CAN_FIRE_RL_rl_pte_wb_req_B,
CAN_FIRE_RL_rl_ptw_rd_A,
CAN_FIRE_RL_rl_ptw_rd_B,
CAN_FIRE_RL_rl_ptw_rd_wait,
CAN_FIRE_flush_server_request_put,
CAN_FIRE_flush_server_response_get,
CAN_FIRE_imem_pte_writeback_p_put,
CAN_FIRE_imem_ptw_server_request_put,
CAN_FIRE_imem_ptw_server_response_get,
CAN_FIRE_l1_to_l2_client_request_deq,
CAN_FIRE_l1_to_l2_client_response_enq,
CAN_FIRE_l2_to_l1_server_request_enq,
CAN_FIRE_l2_to_l1_server_response_deq,
CAN_FIRE_ma_req,
CAN_FIRE_mmio_client_request_get,
CAN_FIRE_mmio_client_response_put,
CAN_FIRE_tlb_flush,
WILL_FIRE_RL_mkConnectionGetPut,
WILL_FIRE_RL_mkConnectionGetPut_1,
WILL_FIRE_RL_rl_CPU_ST_wait,
WILL_FIRE_RL_rl_CPU_cache_wait,
WILL_FIRE_RL_rl_CPU_req,
WILL_FIRE_RL_rl_CPU_req_A,
WILL_FIRE_RL_rl_CPU_req_B,
WILL_FIRE_RL_rl_CPU_req_mmio_WAIT,
WILL_FIRE_RL_rl_PTW_wait,
WILL_FIRE_RL_rl_cache_flush_finish,
WILL_FIRE_RL_rl_cache_flush_start,
WILL_FIRE_RL_rl_pte_wb_cache_WAIT,
WILL_FIRE_RL_rl_pte_wb_req_A,
WILL_FIRE_RL_rl_pte_wb_req_B,
WILL_FIRE_RL_rl_ptw_rd_A,
WILL_FIRE_RL_rl_ptw_rd_B,
WILL_FIRE_RL_rl_ptw_rd_wait,
WILL_FIRE_flush_server_request_put,
WILL_FIRE_flush_server_response_get,
WILL_FIRE_imem_pte_writeback_p_put,
WILL_FIRE_imem_ptw_server_request_put,
WILL_FIRE_imem_ptw_server_response_get,
WILL_FIRE_l1_to_l2_client_request_deq,
WILL_FIRE_l1_to_l2_client_response_enq,
WILL_FIRE_l2_to_l1_server_request_enq,
WILL_FIRE_l2_to_l1_server_response_deq,
WILL_FIRE_ma_req,
WILL_FIRE_mmio_client_request_get,
WILL_FIRE_mmio_client_response_put,
WILL_FIRE_tlb_flush;
// inputs to muxes for submodule ports
wire [207 : 0] MUX_cache$mav_request_pa_1__VAL_2,
MUX_cache$mav_request_pa_1__VAL_3;
wire [64 : 0] MUX_ptw$mem_client_response_put_1__VAL_1;
wire [3 : 0] MUX_crg_exc_code$port0__write_1__VAL_1,
MUX_crg_exc_code$port0__write_1__VAL_3,
MUX_crg_state$port0__write_1__VAL_1,
MUX_crg_state$port0__write_1__VAL_2,
MUX_crg_state$port0__write_1__VAL_3,
MUX_crg_state$port0__write_1__VAL_4;
wire [1 : 0] MUX_crg_mmu_cache_req_state$port0__write_1__VAL_3;
wire MUX_cache$ma_request_va_1__SEL_1,
MUX_cache$mav_request_pa_1__SEL_1,
MUX_crg_exc$port0__write_1__SEL_1,
MUX_crg_exc$port0__write_1__SEL_2,
MUX_crg_exc$port0__write_1__SEL_3,
MUX_crg_exc$port0__write_1__VAL_1,
MUX_crg_exc_code$port0__write_1__SEL_1,
MUX_crg_final_st_val$port0__write_1__SEL_1,
MUX_crg_mmu_cache_req_state$port0__write_1__SEL_1,
MUX_crg_mmu_cache_req_state$port0__write_1__SEL_4,
MUX_crg_state$port0__write_1__SEL_1,
MUX_crg_state$port0__write_1__SEL_5,
MUX_crg_state$port0__write_1__SEL_8,
MUX_crg_valid$port0__write_1__SEL_1,
MUX_ptw$mem_client_response_put_1__SEL_1,
MUX_tlb$ma_insert_1__SEL_1,
MUX_tlb$ma_insert_1__SEL_2;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h7447;
reg [31 : 0] v__h8571;
reg [31 : 0] v__h2477;
reg [31 : 0] v__h2471;
reg [31 : 0] v__h7441;
reg [31 : 0] v__h8565;
// synopsys translate_on
// remaining internal signals
wire [3 : 0] x1__h3849, x1__h5472, x1__h6439;
wire NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d128,
NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d157,
NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d176,
NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d181,
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d192,
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d223,
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d155,
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d169,
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d197;
// action method ma_req
assign CAN_FIRE_ma_req = 1'd1 ;
assign WILL_FIRE_ma_req = EN_ma_req ;
// value method valid
assign valid = crg_valid ;
// value method addr
assign addr = crg_mmu_cache_req[202:139] ;
// value method word64
assign word64 = crg_ld_val ;
// value method st_amo_val
assign st_amo_val = crg_final_st_val ;
// value method exc
assign exc = crg_exc ;
// value method exc_code
assign exc_code = crg_exc_code ;
// action method flush_server_request_put
assign RDY_flush_server_request_put = f_cache_flush_reqs$FULL_N ;
assign CAN_FIRE_flush_server_request_put = f_cache_flush_reqs$FULL_N ;
assign WILL_FIRE_flush_server_request_put = EN_flush_server_request_put ;
// action method flush_server_response_get
assign RDY_flush_server_response_get = f_cache_flush_rsps$EMPTY_N ;
assign CAN_FIRE_flush_server_response_get = f_cache_flush_rsps$EMPTY_N ;
assign WILL_FIRE_flush_server_response_get = EN_flush_server_response_get ;
// action method tlb_flush
assign RDY_tlb_flush = 1'd1 ;
assign CAN_FIRE_tlb_flush = 1'd1 ;
assign WILL_FIRE_tlb_flush = EN_tlb_flush ;
// action method imem_ptw_server_request_put
assign RDY_imem_ptw_server_request_put = ptw$RDY_imem_server_request_put ;
assign CAN_FIRE_imem_ptw_server_request_put =
ptw$RDY_imem_server_request_put ;
assign WILL_FIRE_imem_ptw_server_request_put =
EN_imem_ptw_server_request_put ;
// actionvalue method imem_ptw_server_response_get
assign imem_ptw_server_response_get = ptw$imem_server_response_get ;
assign RDY_imem_ptw_server_response_get = ptw$RDY_imem_server_response_get ;
assign CAN_FIRE_imem_ptw_server_response_get =
ptw$RDY_imem_server_response_get ;
assign WILL_FIRE_imem_ptw_server_response_get =
EN_imem_ptw_server_response_get ;
// action method imem_pte_writeback_p_put
assign RDY_imem_pte_writeback_p_put = f_imem_pte_writebacks$FULL_N ;
assign CAN_FIRE_imem_pte_writeback_p_put = f_imem_pte_writebacks$FULL_N ;
assign WILL_FIRE_imem_pte_writeback_p_put = EN_imem_pte_writeback_p_put ;
// value method l1_to_l2_client_request_first
assign l1_to_l2_client_request_first = cache$l1_to_l2_client_request_first ;
assign RDY_l1_to_l2_client_request_first =
cache$RDY_l1_to_l2_client_request_first ;
// action method l1_to_l2_client_request_deq
assign RDY_l1_to_l2_client_request_deq =
cache$RDY_l1_to_l2_client_request_deq ;
assign CAN_FIRE_l1_to_l2_client_request_deq =
cache$RDY_l1_to_l2_client_request_deq ;
assign WILL_FIRE_l1_to_l2_client_request_deq =
EN_l1_to_l2_client_request_deq ;
// value method l1_to_l2_client_request_notEmpty
assign l1_to_l2_client_request_notEmpty =
cache$l1_to_l2_client_request_notEmpty ;
assign RDY_l1_to_l2_client_request_notEmpty = 1'd1 ;
// action method l1_to_l2_client_response_enq
assign RDY_l1_to_l2_client_response_enq =
cache$RDY_l1_to_l2_client_response_enq ;
assign CAN_FIRE_l1_to_l2_client_response_enq =
cache$RDY_l1_to_l2_client_response_enq ;
assign WILL_FIRE_l1_to_l2_client_response_enq =
EN_l1_to_l2_client_response_enq ;
// value method l1_to_l2_client_response_notFull
assign l1_to_l2_client_response_notFull =
cache$l1_to_l2_client_response_notFull ;
assign RDY_l1_to_l2_client_response_notFull = 1'd1 ;
// action method l2_to_l1_server_request_enq
assign RDY_l2_to_l1_server_request_enq =
cache$RDY_l2_to_l1_server_request_enq ;
assign CAN_FIRE_l2_to_l1_server_request_enq =
cache$RDY_l2_to_l1_server_request_enq ;
assign WILL_FIRE_l2_to_l1_server_request_enq =
EN_l2_to_l1_server_request_enq ;
// value method l2_to_l1_server_request_notFull
assign l2_to_l1_server_request_notFull =
cache$l2_to_l1_server_request_notFull ;
assign RDY_l2_to_l1_server_request_notFull = 1'd1 ;
// value method l2_to_l1_server_response_first
assign l2_to_l1_server_response_first =
cache$l2_to_l1_server_response_first ;
assign RDY_l2_to_l1_server_response_first =
cache$RDY_l2_to_l1_server_response_first ;
// action method l2_to_l1_server_response_deq
assign RDY_l2_to_l1_server_response_deq =
cache$RDY_l2_to_l1_server_response_deq ;
assign CAN_FIRE_l2_to_l1_server_response_deq =
cache$RDY_l2_to_l1_server_response_deq ;
assign WILL_FIRE_l2_to_l1_server_response_deq =
EN_l2_to_l1_server_response_deq ;
// value method l2_to_l1_server_response_notEmpty
assign l2_to_l1_server_response_notEmpty =
cache$l2_to_l1_server_response_notEmpty ;
assign RDY_l2_to_l1_server_response_notEmpty = 1'd1 ;
// actionvalue method mmio_client_request_get
assign mmio_client_request_get = mmio$mmio_client_request_get ;
assign RDY_mmio_client_request_get = mmio$RDY_mmio_client_request_get ;
assign CAN_FIRE_mmio_client_request_get = mmio$RDY_mmio_client_request_get ;
assign WILL_FIRE_mmio_client_request_get = EN_mmio_client_request_get ;
// action method mmio_client_response_put
assign RDY_mmio_client_response_put = mmio$RDY_mmio_client_response_put ;
assign CAN_FIRE_mmio_client_response_put =
mmio$RDY_mmio_client_response_put ;
assign WILL_FIRE_mmio_client_response_put = EN_mmio_client_response_put ;
// submodule cache
mkCache #(.dcache_not_icache(1'd1), .verbosity(3'd0)) cache(.CLK(CLK),
.RST_N(RST_N),
.flush_server_request_put(cache$flush_server_request_put),
.l1_to_l2_client_response_enq_x(cache$l1_to_l2_client_response_enq_x),
.l2_to_l1_server_request_enq_x(cache$l2_to_l1_server_request_enq_x),
.ma_request_va_va(cache$ma_request_va_va),
.mav_request_pa_pa(cache$mav_request_pa_pa),
.mav_request_pa_req(cache$mav_request_pa_req),
.EN_ma_request_va(cache$EN_ma_request_va),
.EN_mav_request_pa(cache$EN_mav_request_pa),
.EN_flush_server_request_put(cache$EN_flush_server_request_put),
.EN_flush_server_response_get(cache$EN_flush_server_response_get),
.EN_l1_to_l2_client_request_deq(cache$EN_l1_to_l2_client_request_deq),
.EN_l1_to_l2_client_response_enq(cache$EN_l1_to_l2_client_response_enq),
.EN_l2_to_l1_server_request_enq(cache$EN_l2_to_l1_server_request_enq),
.EN_l2_to_l1_server_response_deq(cache$EN_l2_to_l1_server_response_deq),
.mav_request_pa(cache$mav_request_pa),
.RDY_mav_request_pa(cache$RDY_mav_request_pa),
.mv_is_idle(cache$mv_is_idle),
.mv_refill_ok(cache$mv_refill_ok),
.RDY_mv_refill_ok(cache$RDY_mv_refill_ok),
.RDY_flush_server_request_put(cache$RDY_flush_server_request_put),
.RDY_flush_server_response_get(cache$RDY_flush_server_response_get),
.l1_to_l2_client_request_first(cache$l1_to_l2_client_request_first),
.RDY_l1_to_l2_client_request_first(cache$RDY_l1_to_l2_client_request_first),
.RDY_l1_to_l2_client_request_deq(cache$RDY_l1_to_l2_client_request_deq),
.l1_to_l2_client_request_notEmpty(cache$l1_to_l2_client_request_notEmpty),
.RDY_l1_to_l2_client_request_notEmpty(),
.RDY_l1_to_l2_client_response_enq(cache$RDY_l1_to_l2_client_response_enq),
.l1_to_l2_client_response_notFull(cache$l1_to_l2_client_response_notFull),
.RDY_l1_to_l2_client_response_notFull(),
.RDY_l2_to_l1_server_request_enq(cache$RDY_l2_to_l1_server_request_enq),
.l2_to_l1_server_request_notFull(cache$l2_to_l1_server_request_notFull),
.RDY_l2_to_l1_server_request_notFull(),
.l2_to_l1_server_response_first(cache$l2_to_l1_server_response_first),
.RDY_l2_to_l1_server_response_first(cache$RDY_l2_to_l1_server_response_first),
.RDY_l2_to_l1_server_response_deq(cache$RDY_l2_to_l1_server_response_deq),
.l2_to_l1_server_response_notEmpty(cache$l2_to_l1_server_response_notEmpty),
.RDY_l2_to_l1_server_response_notEmpty());
// submodule f_cache_flush_reqs
FIFO2 #(.width(32'd1), .guarded(32'd1)) f_cache_flush_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_cache_flush_reqs$D_IN),
.ENQ(f_cache_flush_reqs$ENQ),
.DEQ(f_cache_flush_reqs$DEQ),
.CLR(f_cache_flush_reqs$CLR),
.D_OUT(f_cache_flush_reqs$D_OUT),
.FULL_N(f_cache_flush_reqs$FULL_N),
.EMPTY_N(f_cache_flush_reqs$EMPTY_N));
// submodule f_cache_flush_rsps
FIFO20 #(.guarded(32'd1)) f_cache_flush_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(f_cache_flush_rsps$ENQ),
.DEQ(f_cache_flush_rsps$DEQ),
.CLR(f_cache_flush_rsps$CLR),
.FULL_N(f_cache_flush_rsps$FULL_N),
.EMPTY_N(f_cache_flush_rsps$EMPTY_N));
// submodule f_dmem_pte_writebacks
FIFO2 #(.width(32'd128), .guarded(32'd1)) f_dmem_pte_writebacks(.RST(RST_N),
.CLK(CLK),
.D_IN(f_dmem_pte_writebacks$D_IN),
.ENQ(f_dmem_pte_writebacks$ENQ),
.DEQ(f_dmem_pte_writebacks$DEQ),
.CLR(f_dmem_pte_writebacks$CLR),
.D_OUT(f_dmem_pte_writebacks$D_OUT),
.FULL_N(f_dmem_pte_writebacks$FULL_N),
.EMPTY_N(f_dmem_pte_writebacks$EMPTY_N));
// submodule f_imem_pte_writebacks
FIFO2 #(.width(32'd128), .guarded(32'd1)) f_imem_pte_writebacks(.RST(RST_N),
.CLK(CLK),
.D_IN(f_imem_pte_writebacks$D_IN),
.ENQ(f_imem_pte_writebacks$ENQ),
.DEQ(f_imem_pte_writebacks$DEQ),
.CLR(f_imem_pte_writebacks$CLR),
.D_OUT(f_imem_pte_writebacks$D_OUT),
.FULL_N(f_imem_pte_writebacks$FULL_N),
.EMPTY_N(f_imem_pte_writebacks$EMPTY_N));
// submodule f_pte_writebacks
FIFO2 #(.width(32'd128), .guarded(32'd1)) f_pte_writebacks(.RST(RST_N),
.CLK(CLK),
.D_IN(f_pte_writebacks$D_IN),
.ENQ(f_pte_writebacks$ENQ),
.DEQ(f_pte_writebacks$DEQ),
.CLR(f_pte_writebacks$CLR),
.D_OUT(f_pte_writebacks$D_OUT),
.FULL_N(f_pte_writebacks$FULL_N),
.EMPTY_N(f_pte_writebacks$EMPTY_N));
// submodule mmio
mkMMIO #(.verbosity(3'd0)) mmio(.CLK(CLK),
.RST_N(RST_N),
.mmio_client_response_put(mmio$mmio_client_response_put),
.req_mmu_cache_req(mmio$req_mmu_cache_req),
.start_pa(mmio$start_pa),
.EN_req(mmio$EN_req),
.EN_start(mmio$EN_start),
.EN_mmio_client_request_get(mmio$EN_mmio_client_request_get),
.EN_mmio_client_response_put(mmio$EN_mmio_client_response_put),
.RDY_req(),
.RDY_start(),
.result_fst(mmio$result_fst),
.RDY_result_fst(mmio$RDY_result_fst),
.result_snd_fst(mmio$result_snd_fst),
.RDY_result_snd_fst(mmio$RDY_result_snd_fst),
.result_snd_snd(mmio$result_snd_snd),
.RDY_result_snd_snd(mmio$RDY_result_snd_snd),
.mmio_client_request_get(mmio$mmio_client_request_get),
.RDY_mmio_client_request_get(mmio$RDY_mmio_client_request_get),
.RDY_mmio_client_response_put(mmio$RDY_mmio_client_response_put));
// submodule ptw
mkPTW #(.verbosity(3'd0)) ptw(.CLK(CLK),
.RST_N(RST_N),
.dmem_server_request_put(ptw$dmem_server_request_put),
.imem_server_request_put(ptw$imem_server_request_put),
.mem_client_response_put(ptw$mem_client_response_put),
.EN_imem_server_request_put(ptw$EN_imem_server_request_put),
.EN_imem_server_response_get(ptw$EN_imem_server_response_get),
.EN_dmem_server_request_put(ptw$EN_dmem_server_request_put),
.EN_dmem_server_response_get(ptw$EN_dmem_server_response_get),
.EN_mem_client_request_get(ptw$EN_mem_client_request_get),
.EN_mem_client_response_put(ptw$EN_mem_client_response_put),
.RDY_imem_server_request_put(ptw$RDY_imem_server_request_put),
.imem_server_response_get(ptw$imem_server_response_get),
.RDY_imem_server_response_get(ptw$RDY_imem_server_response_get),
.RDY_dmem_server_request_put(ptw$RDY_dmem_server_request_put),
.dmem_server_response_get(ptw$dmem_server_response_get),
.RDY_dmem_server_response_get(ptw$RDY_dmem_server_response_get),
.mem_client_request_get(ptw$mem_client_request_get),
.RDY_mem_client_request_get(ptw$RDY_mem_client_request_get),
.RDY_mem_client_response_put(ptw$RDY_mem_client_response_put));
// submodule soc_map
mkSoC_Map soc_map(.CLK(CLK),
.RST_N(RST_N),
.m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
.m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
.m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
.m_plic_addr_base(),
.m_plic_addr_size(),
.m_plic_addr_lim(),
.m_near_mem_io_addr_base(),
.m_near_mem_io_addr_size(),
.m_near_mem_io_addr_lim(),
.m_flash_mem_addr_base(),
.m_flash_mem_addr_size(),
.m_flash_mem_addr_lim(),
.m_ethernet_0_addr_base(),
.m_ethernet_0_addr_size(),
.m_ethernet_0_addr_lim(),
.m_dma_0_addr_base(),
.m_dma_0_addr_size(),
.m_dma_0_addr_lim(),
.m_uart16550_0_addr_base(),
.m_uart16550_0_addr_size(),
.m_uart16550_0_addr_lim(),
.m_gpio_0_addr_base(),
.m_gpio_0_addr_size(),
.m_gpio_0_addr_lim(),
.m_boot_rom_addr_base(),
.m_boot_rom_addr_size(),
.m_boot_rom_addr_lim(),
.m_ddr4_0_uncached_addr_base(),
.m_ddr4_0_uncached_addr_size(),
.m_ddr4_0_uncached_addr_lim(),
.m_ddr4_0_cached_addr_base(),
.m_ddr4_0_cached_addr_size(),
.m_ddr4_0_cached_addr_lim(),
.m_is_mem_addr(soc_map$m_is_mem_addr),
.m_is_IO_addr(),
.m_is_near_mem_IO_addr(),
.m_pc_reset_value(),
.m_mtvec_reset_value(),
.m_nmivec_reset_value());
// submodule tlb
mkTLB #(.dmem_not_imem(1'd1), .verbosity(3'd0)) tlb(.CLK(CLK),
.RST_N(RST_N),
.ma_insert_asid(tlb$ma_insert_asid),
.ma_insert_level(tlb$ma_insert_level),
.ma_insert_pte(tlb$ma_insert_pte),
.ma_insert_pte_pa(tlb$ma_insert_pte_pa),
.ma_insert_vpn(tlb$ma_insert_vpn),
.mv_vm_xlate_mstatus_MXR(tlb$mv_vm_xlate_mstatus_MXR),
.mv_vm_xlate_priv(tlb$mv_vm_xlate_priv),
.mv_vm_xlate_read_not_write(tlb$mv_vm_xlate_read_not_write),
.mv_vm_xlate_satp(tlb$mv_vm_xlate_satp),
.mv_vm_xlate_sstatus_SUM(tlb$mv_vm_xlate_sstatus_SUM),
.mv_vm_xlate_va(tlb$mv_vm_xlate_va),
.EN_ma_insert(tlb$EN_ma_insert),
.EN_ma_flush(tlb$EN_ma_flush),
.mv_vm_xlate(tlb$mv_vm_xlate),
.RDY_mv_vm_xlate(),
.RDY_ma_insert(),
.RDY_ma_flush());
// rule RL_rl_CPU_req_A
assign CAN_FIRE_RL_rl_CPU_req_A =
crg_state == 4'd0 && crg_mmu_cache_req_state == 2'd1 &&
cache$mv_is_idle ;
assign WILL_FIRE_RL_rl_CPU_req_A = CAN_FIRE_RL_rl_CPU_req_A && !EN_ma_req ;
// rule RL_rl_CPU_req_B
assign CAN_FIRE_RL_rl_CPU_req_B =
NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d157 &&
crg_state == 4'd0 &&
crg_mmu_cache_req_state == 2'd2 ;
assign WILL_FIRE_RL_rl_CPU_req_B = CAN_FIRE_RL_rl_CPU_req_B && !EN_ma_req ;
// rule RL_rl_CPU_ST_wait
assign CAN_FIRE_RL_rl_CPU_ST_wait = crg_state == 4'd1 ;
assign WILL_FIRE_RL_rl_CPU_ST_wait = CAN_FIRE_RL_rl_CPU_ST_wait ;
// rule RL_rl_CPU_cache_wait
assign CAN_FIRE_RL_rl_CPU_cache_wait =
cache$RDY_mv_refill_ok && crg_state == 4'd2 ;
assign WILL_FIRE_RL_rl_CPU_cache_wait = CAN_FIRE_RL_rl_CPU_cache_wait ;
// rule RL_rl_CPU_req_mmio_WAIT
assign CAN_FIRE_RL_rl_CPU_req_mmio_WAIT =
mmio$RDY_result_snd_snd && mmio$RDY_result_snd_fst &&
mmio$RDY_result_fst &&
crg_state == 4'd3 ;
assign WILL_FIRE_RL_rl_CPU_req_mmio_WAIT =
CAN_FIRE_RL_rl_CPU_req_mmio_WAIT ;
// rule RL_rl_PTW_wait
assign CAN_FIRE_RL_rl_PTW_wait =
ptw$RDY_dmem_server_response_get && crg_state == 4'd5 ;
assign WILL_FIRE_RL_rl_PTW_wait = CAN_FIRE_RL_rl_PTW_wait ;
// rule RL_rl_cache_flush_start
assign CAN_FIRE_RL_rl_cache_flush_start =
cache$RDY_flush_server_request_put &&
f_cache_flush_reqs$EMPTY_N &&
crg_state == 4'd0 &&
crg_mmu_cache_req_state == 2'd0 ;
assign WILL_FIRE_RL_rl_cache_flush_start =
CAN_FIRE_RL_rl_cache_flush_start ;
// rule RL_rl_cache_flush_finish
assign CAN_FIRE_RL_rl_cache_flush_finish =
cache$RDY_flush_server_response_get &&
f_cache_flush_reqs$EMPTY_N &&
f_cache_flush_rsps$FULL_N &&
crg_state == 4'd4 ;
assign WILL_FIRE_RL_rl_cache_flush_finish =
CAN_FIRE_RL_rl_cache_flush_finish ;
// rule RL_rl_ptw_rd_A
assign CAN_FIRE_RL_rl_ptw_rd_A =
ptw$RDY_mem_client_request_get &&
(crg_state == 4'd5 ||
crg_state == 4'd0 && crg_mmu_cache_req_state == 2'd0) ;
assign WILL_FIRE_RL_rl_ptw_rd_A =
CAN_FIRE_RL_rl_ptw_rd_A && !WILL_FIRE_RL_rl_cache_flush_start &&
!WILL_FIRE_RL_rl_PTW_wait &&
!EN_ma_req ;
// rule RL_rl_ptw_rd_B
assign CAN_FIRE_RL_rl_ptw_rd_B =
cache$RDY_mav_request_pa && ptw$RDY_mem_client_response_put &&
crg_state == 4'd6 ;
assign WILL_FIRE_RL_rl_ptw_rd_B = CAN_FIRE_RL_rl_ptw_rd_B && !EN_ma_req ;
// rule RL_rl_ptw_rd_wait
assign CAN_FIRE_RL_rl_ptw_rd_wait =
cache$RDY_mv_refill_ok &&
(cache$mv_refill_ok || ptw$RDY_mem_client_response_put) &&
crg_state == 4'd7 ;
assign WILL_FIRE_RL_rl_ptw_rd_wait = CAN_FIRE_RL_rl_ptw_rd_wait ;
// rule RL_mkConnectionGetPut
assign CAN_FIRE_RL_mkConnectionGetPut =
f_imem_pte_writebacks$EMPTY_N && f_pte_writebacks$FULL_N ;
assign WILL_FIRE_RL_mkConnectionGetPut = CAN_FIRE_RL_mkConnectionGetPut ;
// rule RL_mkConnectionGetPut_1
assign CAN_FIRE_RL_mkConnectionGetPut_1 =
f_pte_writebacks$FULL_N && f_dmem_pte_writebacks$EMPTY_N ;
assign WILL_FIRE_RL_mkConnectionGetPut_1 =
CAN_FIRE_RL_mkConnectionGetPut_1 &&
!WILL_FIRE_RL_mkConnectionGetPut ;
// rule RL_rl_pte_wb_req_A
assign CAN_FIRE_RL_rl_pte_wb_req_A =
f_pte_writebacks$EMPTY_N && crg_state == 4'd0 &&
crg_mmu_cache_req_state == 2'd0 ;
assign WILL_FIRE_RL_rl_pte_wb_req_A =
CAN_FIRE_RL_rl_pte_wb_req_A && !WILL_FIRE_RL_rl_ptw_rd_A &&
!WILL_FIRE_RL_rl_cache_flush_start &&
!EN_ma_req ;
// rule RL_rl_pte_wb_req_B
assign CAN_FIRE_RL_rl_pte_wb_req_B =
cache$RDY_mav_request_pa && f_pte_writebacks$EMPTY_N &&
crg_state == 4'd8 ;
assign WILL_FIRE_RL_rl_pte_wb_req_B =
CAN_FIRE_RL_rl_pte_wb_req_B && !EN_ma_req ;
// rule RL_rl_pte_wb_cache_WAIT
assign CAN_FIRE_RL_rl_pte_wb_cache_WAIT =
cache$RDY_mv_refill_ok &&
(cache$mv_refill_ok || f_pte_writebacks$EMPTY_N) &&
crg_state == 4'd9 ;
assign WILL_FIRE_RL_rl_pte_wb_cache_WAIT =
CAN_FIRE_RL_rl_pte_wb_cache_WAIT ;
// rule RL_rl_CPU_req
assign CAN_FIRE_RL_rl_CPU_req = EN_ma_req ;
assign WILL_FIRE_RL_rl_CPU_req = EN_ma_req ;
// inputs to muxes for submodule ports
assign MUX_cache$ma_request_va_1__SEL_1 =
EN_ma_req && crg_state$port1__read == 4'd0 && cache$mv_is_idle ;
assign MUX_cache$mav_request_pa_1__SEL_1 =
WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d192 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
soc_map$m_is_mem_addr ;
assign MUX_crg_exc$port0__write_1__SEL_1 =
WILL_FIRE_RL_rl_CPU_req_B &&
NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d181 ;
assign MUX_crg_exc$port0__write_1__SEL_2 =
WILL_FIRE_RL_rl_CPU_cache_wait && !cache$mv_refill_ok ;
assign MUX_crg_exc$port0__write_1__SEL_3 =
WILL_FIRE_RL_rl_PTW_wait &&
ptw$dmem_server_response_get[131:130] != 2'd0 ;
assign MUX_crg_exc_code$port0__write_1__SEL_1 =
WILL_FIRE_RL_rl_CPU_req_B &&
(NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d128 ||
tlb$mv_vm_xlate[200:199] == 2'd2) ;
assign MUX_crg_final_st_val$port0__write_1__SEL_1 =
WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d223 ;
assign MUX_crg_mmu_cache_req_state$port0__write_1__SEL_1 =
WILL_FIRE_RL_rl_CPU_req_B &&
NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d176 ;
assign MUX_crg_mmu_cache_req_state$port0__write_1__SEL_4 =
WILL_FIRE_RL_rl_CPU_req_mmio_WAIT ||
WILL_FIRE_RL_rl_CPU_ST_wait ;
assign MUX_crg_state$port0__write_1__SEL_1 =
WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d192 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d197 ;
assign MUX_crg_state$port0__write_1__SEL_5 =
WILL_FIRE_RL_rl_cache_flush_finish || WILL_FIRE_RL_rl_PTW_wait ||
WILL_FIRE_RL_rl_CPU_req_mmio_WAIT ||
WILL_FIRE_RL_rl_CPU_cache_wait ||
WILL_FIRE_RL_rl_CPU_ST_wait ;
assign MUX_crg_state$port0__write_1__SEL_8 =
WILL_FIRE_RL_rl_pte_wb_cache_WAIT ||
WILL_FIRE_RL_rl_pte_wb_req_A ;
assign MUX_crg_valid$port0__write_1__SEL_1 =
WILL_FIRE_RL_rl_CPU_req_B &&
(NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d128 ||
tlb$mv_vm_xlate[200:199] == 2'd1 ||
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d169) ;
assign MUX_ptw$mem_client_response_put_1__SEL_1 =
WILL_FIRE_RL_rl_ptw_rd_B &&
cache$mav_request_pa[129:128] == 2'd1 ;
assign MUX_tlb$ma_insert_1__SEL_1 =
WILL_FIRE_RL_rl_PTW_wait &&
ptw$dmem_server_response_get[131:130] == 2'd0 ;
assign MUX_tlb$ma_insert_1__SEL_2 =
WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d192 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
tlb$mv_vm_xlate[130] ;
assign MUX_cache$mav_request_pa_1__VAL_2 =
{ 5'd3,
rg_ptw_mem_req,
139'h555555555555555500C0000000000000000 } ;
assign MUX_cache$mav_request_pa_1__VAL_3 =
{ 5'd11, f_pte_writebacks$D_OUT, 75'h00C0000000000000000 } ;
assign MUX_crg_exc$port0__write_1__VAL_1 =
NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d128 ||
tlb$mv_vm_xlate[200:199] == 2'd2 ;
assign MUX_crg_exc_code$port0__write_1__VAL_1 =
NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d128 ?
x1__h3849 :
tlb$mv_vm_xlate[134:131] ;
assign MUX_crg_exc_code$port0__write_1__VAL_3 =
(ptw$dmem_server_response_get[131:130] == 2'd1) ?
x1__h5472 :
x1__h6439 ;
assign MUX_crg_mmu_cache_req_state$port0__write_1__VAL_3 =
(ptw$dmem_server_response_get[131:130] == 2'd0) ? 2'd1 : 2'd0 ;
assign MUX_crg_state$port0__write_1__VAL_1 =
(tlb$mv_vm_xlate[200:199] == 2'd1) ?
4'd5 :
(soc_map$m_is_mem_addr ?
((cache$mav_request_pa[129:128] == 2'd0) ? 4'd2 : 4'd1) :
4'd3) ;
assign MUX_crg_state$port0__write_1__VAL_2 =
(cache$mav_request_pa[129:128] == 2'd1) ?
rg_state_stack_during_ptw_rd :
4'd7 ;
assign MUX_crg_state$port0__write_1__VAL_3 =
cache$mv_refill_ok ? 4'd6 : 4'd0 ;
assign MUX_crg_state$port0__write_1__VAL_4 =
(cache$mav_request_pa[129:128] == 2'd2) ? 4'd0 : 4'd9 ;
assign MUX_ptw$mem_client_response_put_1__VAL_1 =
{ 1'd1, cache$mav_request_pa[127:64] } ;
// inlined wires
assign crg_state$EN_port0__write =
WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d192 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d197 ||
WILL_FIRE_RL_rl_ptw_rd_B ||
WILL_FIRE_RL_rl_ptw_rd_wait ||
WILL_FIRE_RL_rl_pte_wb_req_B ||
WILL_FIRE_RL_rl_cache_flush_finish ||
WILL_FIRE_RL_rl_PTW_wait ||
WILL_FIRE_RL_rl_CPU_req_mmio_WAIT ||
WILL_FIRE_RL_rl_CPU_cache_wait ||
WILL_FIRE_RL_rl_CPU_ST_wait ||
WILL_FIRE_RL_rl_cache_flush_start ||
WILL_FIRE_RL_rl_ptw_rd_A ||
WILL_FIRE_RL_rl_pte_wb_cache_WAIT ||
WILL_FIRE_RL_rl_pte_wb_req_A ;
always@(MUX_crg_state$port0__write_1__SEL_1 or
MUX_crg_state$port0__write_1__VAL_1 or
WILL_FIRE_RL_rl_ptw_rd_B or
MUX_crg_state$port0__write_1__VAL_2 or
WILL_FIRE_RL_rl_ptw_rd_wait or
MUX_crg_state$port0__write_1__VAL_3 or
WILL_FIRE_RL_rl_pte_wb_req_B or
MUX_crg_state$port0__write_1__VAL_4 or
MUX_crg_state$port0__write_1__SEL_5 or
WILL_FIRE_RL_rl_cache_flush_start or
WILL_FIRE_RL_rl_ptw_rd_A or MUX_crg_state$port0__write_1__SEL_8)
begin
case (1'b1) // synopsys parallel_case
MUX_crg_state$port0__write_1__SEL_1:
crg_state$port0__write_1 = MUX_crg_state$port0__write_1__VAL_1;
WILL_FIRE_RL_rl_ptw_rd_B:
crg_state$port0__write_1 = MUX_crg_state$port0__write_1__VAL_2;
WILL_FIRE_RL_rl_ptw_rd_wait:
crg_state$port0__write_1 = MUX_crg_state$port0__write_1__VAL_3;
WILL_FIRE_RL_rl_pte_wb_req_B:
crg_state$port0__write_1 = MUX_crg_state$port0__write_1__VAL_4;
MUX_crg_state$port0__write_1__SEL_5: crg_state$port0__write_1 = 4'd0;
WILL_FIRE_RL_rl_cache_flush_start: crg_state$port0__write_1 = 4'd4;
WILL_FIRE_RL_rl_ptw_rd_A: crg_state$port0__write_1 = 4'd6;
MUX_crg_state$port0__write_1__SEL_8: crg_state$port0__write_1 = 4'd8;
default: crg_state$port0__write_1 = 4'b1010 /* unspecified value */ ;
endcase
end
assign crg_state$port1__read =
crg_state$EN_port0__write ?
crg_state$port0__write_1 :
crg_state ;
assign crg_mmu_cache_req_state$EN_port0__write =
WILL_FIRE_RL_rl_CPU_req_B &&
NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d176 ||
WILL_FIRE_RL_rl_CPU_cache_wait && !cache$mv_refill_ok ||
WILL_FIRE_RL_rl_PTW_wait ||
WILL_FIRE_RL_rl_CPU_req_mmio_WAIT ||
WILL_FIRE_RL_rl_CPU_ST_wait ||
WILL_FIRE_RL_rl_CPU_req_A ;
always@(WILL_FIRE_RL_rl_PTW_wait or
MUX_crg_mmu_cache_req_state$port0__write_1__VAL_3 or
MUX_crg_mmu_cache_req_state$port0__write_1__SEL_1 or
MUX_crg_exc$port0__write_1__SEL_2 or
MUX_crg_mmu_cache_req_state$port0__write_1__SEL_4 or
WILL_FIRE_RL_rl_CPU_req_A)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_rl_PTW_wait:
crg_mmu_cache_req_state$port0__write_1 =
MUX_crg_mmu_cache_req_state$port0__write_1__VAL_3;
MUX_crg_mmu_cache_req_state$port0__write_1__SEL_1 ||
MUX_crg_exc$port0__write_1__SEL_2 ||
MUX_crg_mmu_cache_req_state$port0__write_1__SEL_4:
crg_mmu_cache_req_state$port0__write_1 = 2'd0;
WILL_FIRE_RL_rl_CPU_req_A:
crg_mmu_cache_req_state$port0__write_1 = 2'd2;
default: crg_mmu_cache_req_state$port0__write_1 =
2'b10 /* unspecified value */ ;
endcase
end
assign crg_mmu_cache_req_state$port1__read =
crg_mmu_cache_req_state$EN_port0__write ?
crg_mmu_cache_req_state$port0__write_1 :
crg_mmu_cache_req_state ;
assign crg_mmu_cache_req_state$port1__write_1 =
(crg_state$port1__read != 4'd0 || !cache$mv_is_idle) ?
2'd1 :
2'd2 ;
assign crg_mmu_cache_req_state$port2__read =
EN_ma_req ?
crg_mmu_cache_req_state$port1__write_1 :
crg_mmu_cache_req_state$port1__read ;
assign crg_mmu_cache_req$port1__write_1 =
{ ma_req_op,
ma_req_f3,
ma_req_va,
ma_req_st_value,
ma_req_amo_funct7,
ma_req_priv,
ma_req_sstatus_SUM,
ma_req_mstatus_MXR,
ma_req_satp } ;
assign crg_mmu_cache_req$port2__read =
EN_ma_req ?
crg_mmu_cache_req$port1__write_1 :
crg_mmu_cache_req ;
assign crg_valid$EN_port0__write =
WILL_FIRE_RL_rl_CPU_req_B &&
(NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d128 ||
tlb$mv_vm_xlate[200:199] == 2'd1 ||
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d169) ||
WILL_FIRE_RL_rl_CPU_cache_wait && !cache$mv_refill_ok ||
WILL_FIRE_RL_rl_PTW_wait &&
ptw$dmem_server_response_get[131:130] != 2'd0 ||
WILL_FIRE_RL_rl_CPU_req_mmio_WAIT ||
WILL_FIRE_RL_rl_CPU_ST_wait ;
assign crg_valid$port0__write_1 =
!MUX_crg_valid$port0__write_1__SEL_1 ||
NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d176 ;
assign crg_valid$port1__read =
crg_valid$EN_port0__write ?
crg_valid$port0__write_1 :
crg_valid ;
assign crg_valid$port2__read = !EN_ma_req && crg_valid$port1__read ;
assign crg_exc$EN_port0__write =
WILL_FIRE_RL_rl_CPU_req_B &&
NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d181 ||
WILL_FIRE_RL_rl_CPU_cache_wait && !cache$mv_refill_ok ||
WILL_FIRE_RL_rl_PTW_wait &&
ptw$dmem_server_response_get[131:130] != 2'd0 ||
WILL_FIRE_RL_rl_CPU_req_mmio_WAIT ;
always@(WILL_FIRE_RL_rl_CPU_req_mmio_WAIT or
mmio$result_fst or
MUX_crg_exc$port0__write_1__SEL_1 or
MUX_crg_exc$port0__write_1__VAL_1 or
MUX_crg_exc$port0__write_1__SEL_2 or
MUX_crg_exc$port0__write_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_rl_CPU_req_mmio_WAIT:
crg_exc$port0__write_1 = mmio$result_fst;
MUX_crg_exc$port0__write_1__SEL_1:
crg_exc$port0__write_1 = MUX_crg_exc$port0__write_1__VAL_1;
MUX_crg_exc$port0__write_1__SEL_2 || MUX_crg_exc$port0__write_1__SEL_3:
crg_exc$port0__write_1 = 1'd1;
default: crg_exc$port0__write_1 = 1'b0 /* unspecified value */ ;
endcase
end
assign crg_exc$port1__read =
crg_exc$EN_port0__write ? crg_exc$port0__write_1 : crg_exc ;
assign crg_exc_code$EN_port0__write =
WILL_FIRE_RL_rl_CPU_req_B &&
(NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d128 ||
tlb$mv_vm_xlate[200:199] == 2'd2) ||
WILL_FIRE_RL_rl_CPU_cache_wait && !cache$mv_refill_ok ||
WILL_FIRE_RL_rl_PTW_wait &&
ptw$dmem_server_response_get[131:130] != 2'd0 ||
WILL_FIRE_RL_rl_CPU_req_mmio_WAIT ;
always@(MUX_crg_exc_code$port0__write_1__SEL_1 or
MUX_crg_exc_code$port0__write_1__VAL_1 or
MUX_crg_exc$port0__write_1__SEL_2 or
x1__h5472 or
MUX_crg_exc$port0__write_1__SEL_3 or
MUX_crg_exc_code$port0__write_1__VAL_3 or
WILL_FIRE_RL_rl_CPU_req_mmio_WAIT)
begin
case (1'b1) // synopsys parallel_case
MUX_crg_exc_code$port0__write_1__SEL_1:
crg_exc_code$port0__write_1 =
MUX_crg_exc_code$port0__write_1__VAL_1;
MUX_crg_exc$port0__write_1__SEL_2:
crg_exc_code$port0__write_1 = x1__h5472;
MUX_crg_exc$port0__write_1__SEL_3:
crg_exc_code$port0__write_1 =
MUX_crg_exc_code$port0__write_1__VAL_3;
WILL_FIRE_RL_rl_CPU_req_mmio_WAIT:
crg_exc_code$port0__write_1 = x1__h5472;
default: crg_exc_code$port0__write_1 = 4'b1010 /* unspecified value */ ;
endcase
end
assign crg_exc_code$port1__read =
crg_exc_code$EN_port0__write ?
crg_exc_code$port0__write_1 :
crg_exc_code ;
assign crg_ld_val$EN_port0__write =
WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d223 ||
WILL_FIRE_RL_rl_CPU_req_mmio_WAIT ;
assign crg_ld_val$port0__write_1 =
MUX_crg_final_st_val$port0__write_1__SEL_1 ?
cache$mav_request_pa[127:64] :
mmio$result_snd_fst ;
assign crg_ld_val$port1__read =
crg_ld_val$EN_port0__write ?
crg_ld_val$port0__write_1 :
crg_ld_val ;
assign crg_final_st_val$EN_port0__write =
WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d223 ||
WILL_FIRE_RL_rl_CPU_req_mmio_WAIT ;
assign crg_final_st_val$port0__write_1 =
MUX_crg_final_st_val$port0__write_1__SEL_1 ?
cache$mav_request_pa[63:0] :
mmio$result_snd_snd ;
assign crg_final_st_val$port1__read =
crg_final_st_val$EN_port0__write ?
crg_final_st_val$port0__write_1 :
crg_final_st_val ;
// register crg_exc
assign crg_exc$D_IN = crg_exc$port1__read ;
assign crg_exc$EN = 1'b1 ;
// register crg_exc_code
assign crg_exc_code$D_IN = crg_exc_code$port1__read ;
assign crg_exc_code$EN = 1'b1 ;
// register crg_final_st_val
assign crg_final_st_val$D_IN = crg_final_st_val$port1__read ;
assign crg_final_st_val$EN = 1'b1 ;
// register crg_ld_val
assign crg_ld_val$D_IN = crg_ld_val$port1__read ;
assign crg_ld_val$EN = 1'b1 ;
// register crg_mmu_cache_req
assign crg_mmu_cache_req$D_IN = crg_mmu_cache_req$port2__read ;
assign crg_mmu_cache_req$EN = 1'b1 ;
// register crg_mmu_cache_req_state
assign crg_mmu_cache_req_state$D_IN = crg_mmu_cache_req_state$port2__read ;
assign crg_mmu_cache_req_state$EN = 1'b1 ;
// register crg_state
assign crg_state$D_IN = crg_state$port1__read ;
assign crg_state$EN = 1'b1 ;
// register crg_valid
assign crg_valid$D_IN = crg_valid$port2__read ;
assign crg_valid$EN = 1'b1 ;
// register rg_ptw_mem_req
assign rg_ptw_mem_req$D_IN = ptw$mem_client_request_get ;
assign rg_ptw_mem_req$EN = WILL_FIRE_RL_rl_ptw_rd_A ;
// register rg_state_stack_during_ptw_rd
assign rg_state_stack_during_ptw_rd$D_IN = crg_state ;
assign rg_state_stack_during_ptw_rd$EN = WILL_FIRE_RL_rl_ptw_rd_A ;
// submodule cache
assign cache$flush_server_request_put = f_cache_flush_reqs$D_OUT ;
assign cache$l1_to_l2_client_response_enq_x =
l1_to_l2_client_response_enq_x ;
assign cache$l2_to_l1_server_request_enq_x = l2_to_l1_server_request_enq_x ;
always@(MUX_cache$ma_request_va_1__SEL_1 or
crg_mmu_cache_req$port1__write_1 or
WILL_FIRE_RL_rl_CPU_req_A or
crg_mmu_cache_req or
WILL_FIRE_RL_rl_pte_wb_req_A or
f_pte_writebacks$D_OUT or
WILL_FIRE_RL_rl_ptw_rd_A or ptw$mem_client_request_get)
begin
case (1'b1) // synopsys parallel_case
MUX_cache$ma_request_va_1__SEL_1:
cache$ma_request_va_va = crg_mmu_cache_req$port1__write_1[202:139];
WILL_FIRE_RL_rl_CPU_req_A:
cache$ma_request_va_va = crg_mmu_cache_req[202:139];
WILL_FIRE_RL_rl_pte_wb_req_A:
cache$ma_request_va_va = f_pte_writebacks$D_OUT[127:64];
WILL_FIRE_RL_rl_ptw_rd_A:
cache$ma_request_va_va = ptw$mem_client_request_get;
default: cache$ma_request_va_va =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
always@(MUX_cache$mav_request_pa_1__SEL_1 or
tlb$mv_vm_xlate or
WILL_FIRE_RL_rl_ptw_rd_B or
rg_ptw_mem_req or
WILL_FIRE_RL_rl_pte_wb_req_B or f_pte_writebacks$D_OUT)
begin
case (1'b1) // synopsys parallel_case
MUX_cache$mav_request_pa_1__SEL_1:
cache$mav_request_pa_pa = tlb$mv_vm_xlate[198:135];
WILL_FIRE_RL_rl_ptw_rd_B: cache$mav_request_pa_pa = rg_ptw_mem_req;
WILL_FIRE_RL_rl_pte_wb_req_B:
cache$mav_request_pa_pa = f_pte_writebacks$D_OUT[127:64];
default: cache$mav_request_pa_pa =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
always@(MUX_cache$mav_request_pa_1__SEL_1 or
crg_mmu_cache_req or
WILL_FIRE_RL_rl_ptw_rd_B or
MUX_cache$mav_request_pa_1__VAL_2 or
WILL_FIRE_RL_rl_pte_wb_req_B or MUX_cache$mav_request_pa_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_cache$mav_request_pa_1__SEL_1:
cache$mav_request_pa_req = crg_mmu_cache_req;
WILL_FIRE_RL_rl_ptw_rd_B:
cache$mav_request_pa_req = MUX_cache$mav_request_pa_1__VAL_2;
WILL_FIRE_RL_rl_pte_wb_req_B:
cache$mav_request_pa_req = MUX_cache$mav_request_pa_1__VAL_3;
default: cache$mav_request_pa_req =
208'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign cache$EN_ma_request_va =
EN_ma_req && crg_state$port1__read == 4'd0 && cache$mv_is_idle ||
WILL_FIRE_RL_rl_CPU_req_A ||
WILL_FIRE_RL_rl_pte_wb_req_A ||
WILL_FIRE_RL_rl_ptw_rd_A ;
assign cache$EN_mav_request_pa =
WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d192 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
soc_map$m_is_mem_addr ||
WILL_FIRE_RL_rl_ptw_rd_B ||
WILL_FIRE_RL_rl_pte_wb_req_B ;
assign cache$EN_flush_server_request_put =
CAN_FIRE_RL_rl_cache_flush_start ;
assign cache$EN_flush_server_response_get =
CAN_FIRE_RL_rl_cache_flush_finish ;
assign cache$EN_l1_to_l2_client_request_deq =
EN_l1_to_l2_client_request_deq ;
assign cache$EN_l1_to_l2_client_response_enq =
EN_l1_to_l2_client_response_enq ;
assign cache$EN_l2_to_l1_server_request_enq =
EN_l2_to_l1_server_request_enq ;
assign cache$EN_l2_to_l1_server_response_deq =
EN_l2_to_l1_server_response_deq ;
// submodule f_cache_flush_reqs
assign f_cache_flush_reqs$D_IN = flush_server_request_put ;
assign f_cache_flush_reqs$ENQ = EN_flush_server_request_put ;
assign f_cache_flush_reqs$DEQ = CAN_FIRE_RL_rl_cache_flush_finish ;
assign f_cache_flush_reqs$CLR = 1'b0 ;
// submodule f_cache_flush_rsps
assign f_cache_flush_rsps$ENQ = CAN_FIRE_RL_rl_cache_flush_finish ;
assign f_cache_flush_rsps$DEQ = EN_flush_server_response_get ;
assign f_cache_flush_rsps$CLR = 1'b0 ;
// submodule f_dmem_pte_writebacks
assign f_dmem_pte_writebacks$D_IN =
{ tlb$mv_vm_xlate[63:0], tlb$mv_vm_xlate[129:66] } ;
assign f_dmem_pte_writebacks$ENQ = MUX_tlb$ma_insert_1__SEL_2 ;
assign f_dmem_pte_writebacks$DEQ = WILL_FIRE_RL_mkConnectionGetPut_1 ;
assign f_dmem_pte_writebacks$CLR = 1'b0 ;
// submodule f_imem_pte_writebacks
assign f_imem_pte_writebacks$D_IN = imem_pte_writeback_p_put ;
assign f_imem_pte_writebacks$ENQ = EN_imem_pte_writeback_p_put ;
assign f_imem_pte_writebacks$DEQ = CAN_FIRE_RL_mkConnectionGetPut ;
assign f_imem_pte_writebacks$CLR = 1'b0 ;
// submodule f_pte_writebacks
assign f_pte_writebacks$D_IN =
WILL_FIRE_RL_mkConnectionGetPut ?
f_imem_pte_writebacks$D_OUT :
f_dmem_pte_writebacks$D_OUT ;
assign f_pte_writebacks$ENQ =
WILL_FIRE_RL_mkConnectionGetPut ||
WILL_FIRE_RL_mkConnectionGetPut_1 ;
assign f_pte_writebacks$DEQ =
WILL_FIRE_RL_rl_pte_wb_req_B &&
cache$mav_request_pa[129:128] == 2'd2 ;
assign f_pte_writebacks$CLR = 1'b0 ;
// submodule mmio
assign mmio$mmio_client_response_put = mmio_client_response_put ;
assign mmio$req_mmu_cache_req = crg_mmu_cache_req$port1__write_1 ;
assign mmio$start_pa = tlb$mv_vm_xlate[198:135] ;
assign mmio$EN_req = EN_ma_req ;
assign mmio$EN_start =
WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d192 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
!soc_map$m_is_mem_addr ;
assign mmio$EN_mmio_client_request_get = EN_mmio_client_request_get ;
assign mmio$EN_mmio_client_response_put = EN_mmio_client_response_put ;
// submodule ptw
assign ptw$dmem_server_request_put =
{ crg_mmu_cache_req[202:139], crg_mmu_cache_req[63:0] } ;
assign ptw$imem_server_request_put = imem_ptw_server_request_put ;
assign ptw$mem_client_response_put =
MUX_ptw$mem_client_response_put_1__SEL_1 ?
MUX_ptw$mem_client_response_put_1__VAL_1 :
65'h0AAAAAAAAAAAAAAAA ;
assign ptw$EN_imem_server_request_put = EN_imem_ptw_server_request_put ;
assign ptw$EN_imem_server_response_get = EN_imem_ptw_server_response_get ;
assign ptw$EN_dmem_server_request_put =
WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d192 &&
tlb$mv_vm_xlate[200:199] == 2'd1 ;
assign ptw$EN_dmem_server_response_get = CAN_FIRE_RL_rl_PTW_wait ;
assign ptw$EN_mem_client_request_get = WILL_FIRE_RL_rl_ptw_rd_A ;
assign ptw$EN_mem_client_response_put =
WILL_FIRE_RL_rl_ptw_rd_B &&
cache$mav_request_pa[129:128] == 2'd1 ||
WILL_FIRE_RL_rl_ptw_rd_wait && !cache$mv_refill_ok ;
// submodule soc_map
assign soc_map$m_is_IO_addr_addr = 64'h0 ;
assign soc_map$m_is_mem_addr_addr = tlb$mv_vm_xlate[198:135] ;
assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;
// submodule tlb
assign tlb$ma_insert_asid = crg_mmu_cache_req[59:44] ;
assign tlb$ma_insert_level =
MUX_tlb$ma_insert_1__SEL_1 ?
ptw$dmem_server_response_get[65:64] :
tlb$mv_vm_xlate[65:64] ;
assign tlb$ma_insert_pte =
MUX_tlb$ma_insert_1__SEL_1 ?
ptw$dmem_server_response_get[129:66] :
tlb$mv_vm_xlate[129:66] ;
assign tlb$ma_insert_pte_pa =
MUX_tlb$ma_insert_1__SEL_1 ?
ptw$dmem_server_response_get[63:0] :
tlb$mv_vm_xlate[63:0] ;
assign tlb$ma_insert_vpn = crg_mmu_cache_req[177:151] ;
assign tlb$mv_vm_xlate_mstatus_MXR = crg_mmu_cache_req[64] ;
assign tlb$mv_vm_xlate_priv = crg_mmu_cache_req[67:66] ;
assign tlb$mv_vm_xlate_read_not_write =
crg_mmu_cache_req[207:206] == 2'd0 ||
crg_mmu_cache_req[207:206] == 2'd2 &&
crg_mmu_cache_req[74:70] == 5'b00010 ;
assign tlb$mv_vm_xlate_satp = crg_mmu_cache_req[63:0] ;
assign tlb$mv_vm_xlate_sstatus_SUM = crg_mmu_cache_req[65] ;
assign tlb$mv_vm_xlate_va = crg_mmu_cache_req[202:139] ;
assign tlb$EN_ma_insert =
WILL_FIRE_RL_rl_PTW_wait &&
ptw$dmem_server_response_get[131:130] == 2'd0 ||
WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d192 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
tlb$mv_vm_xlate[130] ;
assign tlb$EN_ma_flush = EN_tlb_flush ;
// remaining internal signals
assign NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d128 =
crg_mmu_cache_req[204:203] != 2'b0 &&
(crg_mmu_cache_req[204:203] != 2'b01 ||
crg_mmu_cache_req[139]) &&
(crg_mmu_cache_req[204:203] != 2'b10 ||
crg_mmu_cache_req[140:139] != 2'b0) &&
(crg_mmu_cache_req[204:203] != 2'b11 ||
crg_mmu_cache_req[141:139] != 3'b0) ;
assign NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d157 =
NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d128 ||
((tlb$mv_vm_xlate[200:199] == 2'd1) ?
ptw$RDY_dmem_server_request_put :
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d155) ;
assign NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d176 =
NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d128 ||
tlb$mv_vm_xlate[200:199] != 2'd1 &&
(tlb$mv_vm_xlate[200:199] == 2'd2 ||
soc_map$m_is_mem_addr &&
cache$mav_request_pa[129:128] == 2'd1) ;
assign NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d181 =
NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d128 ||
tlb$mv_vm_xlate[200:199] != 2'd1 &&
(tlb$mv_vm_xlate[200:199] == 2'd2 ||
soc_map$m_is_mem_addr &&
cache$mav_request_pa[129:128] != 2'd0) ;
assign crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d192 =
crg_mmu_cache_req[204:203] == 2'b0 ||
crg_mmu_cache_req[204:203] == 2'b01 && !crg_mmu_cache_req[139] ||
crg_mmu_cache_req[204:203] == 2'b10 &&
crg_mmu_cache_req[140:139] == 2'b0 ||
crg_mmu_cache_req[204:203] == 2'b11 &&
crg_mmu_cache_req[141:139] == 3'b0 ;
assign crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d223 =
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d192 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
soc_map$m_is_mem_addr &&
cache$mav_request_pa[129:128] != 2'd0 ;
assign tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d155 =
tlb$mv_vm_xlate[200:199] == 2'd2 ||
(!tlb$mv_vm_xlate[130] || f_dmem_pte_writebacks$FULL_N) &&
(!soc_map$m_is_mem_addr || cache$RDY_mav_request_pa) ;
assign tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d169 =
tlb$mv_vm_xlate[200:199] == 2'd2 ||
cache$mav_request_pa[129:128] == 2'd0 ||
cache$mav_request_pa[129:128] == 2'd1 ||
cache$mav_request_pa[129:128] == 2'd2 ||
!soc_map$m_is_mem_addr ;
assign tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d197 =
tlb$mv_vm_xlate[200:199] == 2'd1 ||
tlb$mv_vm_xlate[200:199] != 2'd2 &&
(cache$mav_request_pa[129:128] == 2'd0 ||
cache$mav_request_pa[129:128] == 2'd2 ||
!soc_map$m_is_mem_addr) ;
assign x1__h3849 =
(crg_mmu_cache_req[207:206] == 2'd0 ||
crg_mmu_cache_req[207:206] == 2'd2 &&
crg_mmu_cache_req[74:70] == 5'b00010) ?
4'd4 :
4'd6 ;
assign x1__h5472 =
(crg_mmu_cache_req[207:206] == 2'd0 ||
crg_mmu_cache_req[207:206] == 2'd2 &&
crg_mmu_cache_req[74:70] == 5'b00010) ?
4'd5 :
4'd7 ;
assign x1__h6439 =
(crg_mmu_cache_req[207:206] == 2'd0 ||
crg_mmu_cache_req[207:206] == 2'd2 &&
crg_mmu_cache_req[74:70] == 5'b00010) ?
4'd13 :
4'd15 ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
crg_mmu_cache_req_state <= `BSV_ASSIGNMENT_DELAY 2'd0;
crg_state <= `BSV_ASSIGNMENT_DELAY 4'd0;
crg_valid <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (crg_mmu_cache_req_state$EN)
crg_mmu_cache_req_state <= `BSV_ASSIGNMENT_DELAY
crg_mmu_cache_req_state$D_IN;
if (crg_state$EN) crg_state <= `BSV_ASSIGNMENT_DELAY crg_state$D_IN;
if (crg_valid$EN) crg_valid <= `BSV_ASSIGNMENT_DELAY crg_valid$D_IN;
end
if (crg_exc$EN) crg_exc <= `BSV_ASSIGNMENT_DELAY crg_exc$D_IN;
if (crg_exc_code$EN)
crg_exc_code <= `BSV_ASSIGNMENT_DELAY crg_exc_code$D_IN;
if (crg_final_st_val$EN)
crg_final_st_val <= `BSV_ASSIGNMENT_DELAY crg_final_st_val$D_IN;
if (crg_ld_val$EN) crg_ld_val <= `BSV_ASSIGNMENT_DELAY crg_ld_val$D_IN;
if (crg_mmu_cache_req$EN)
crg_mmu_cache_req <= `BSV_ASSIGNMENT_DELAY crg_mmu_cache_req$D_IN;
if (rg_ptw_mem_req$EN)
rg_ptw_mem_req <= `BSV_ASSIGNMENT_DELAY rg_ptw_mem_req$D_IN;
if (rg_state_stack_during_ptw_rd$EN)
rg_state_stack_during_ptw_rd <= `BSV_ASSIGNMENT_DELAY
rg_state_stack_during_ptw_rd$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
crg_exc = 1'h0;
crg_exc_code = 4'hA;
crg_final_st_val = 64'hAAAAAAAAAAAAAAAA;
crg_ld_val = 64'hAAAAAAAAAAAAAAAA;
crg_mmu_cache_req =
208'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
crg_mmu_cache_req_state = 2'h2;
crg_state = 4'hA;
crg_valid = 1'h0;
rg_ptw_mem_req = 64'hAAAAAAAAAAAAAAAA;
rg_state_stack_during_ptw_rd = 4'hA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d192 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
tlb$mv_vm_xlate[200:199] != 2'd0)
$display("Dynamic assertion failed: \"../src_Core/Near_Mem_VM_WB_L1_L2/D_MMU_Cache.bsv\", line 473, column 67\nFAIL: unknown vm_xlate result");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d192 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
tlb$mv_vm_xlate[200:199] != 2'd0)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_rd_B && cache$mav_request_pa[129:128] == 2'd2)
begin
v__h7447 = $stime;
#0;
end
v__h7441 = v__h7447 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_rd_B && cache$mav_request_pa[129:128] == 2'd2)
$display("%0d: %m.rl_ptw_rd_B", v__h7441);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_rd_B && cache$mav_request_pa[129:128] == 2'd2)
$display(" INTERNAL ERROR: cannot have CACHE_WRITE_HIT for PTW read-request to cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_rd_B && cache$mav_request_pa[129:128] == 2'd2)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_rd_B && cache$mav_request_pa[129:128] == 2'd2)
$write("MMU_Cache_Req{");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_rd_B && cache$mav_request_pa[129:128] == 2'd2)
$write("CACHE_LD", " f3 %3b", 3'b011);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_rd_B && cache$mav_request_pa[129:128] == 2'd2)
$write(" va %0h", rg_ptw_mem_req);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_rd_B && cache$mav_request_pa[129:128] == 2'd2)
$write(" priv %0d sstatus_SUM %0d mstatus_MXR %0d satp %0h",
2'b11,
1'd0,
1'd0,
64'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_rd_B && cache$mav_request_pa[129:128] == 2'd2)
$write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_rd_B && cache$mav_request_pa[129:128] == 2'd2)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_ptw_rd_B && cache$mav_request_pa[129:128] == 2'd2)
$finish(32'd1);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pte_wb_cache_WAIT && !cache$mv_refill_ok)
begin
v__h8571 = $stime;
#0;
end
v__h8565 = v__h8571 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pte_wb_cache_WAIT && !cache$mv_refill_ok)
$display("%0d: %m.rl_pte_wb_req_cache_WAIT: ERROR: unexpected cache error response",
v__h8565);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pte_wb_cache_WAIT && !cache$mv_refill_ok)
$display(" pte_pa %0d pa %0h",
f_pte_writebacks$D_OUT[127:64],
f_pte_writebacks$D_OUT[63:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pte_wb_cache_WAIT && !cache$mv_refill_ok)
$finish(32'd1);
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0)
begin
v__h2477 = $stime;
#0;
end
v__h2471 = v__h2477 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0)
$display("%0d: %m.rl_CPU_req", v__h2471);
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0)
$write(" INTERNAL ERROR: crg_mmu_cache_req_state: ");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read == 2'd1)
$write("REQ_STATE_FULL_A");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req_state$port1__read != 2'd1)
$write("REQ_STATE_FULL_B");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0)
$write("; expected EMPTY", "\n");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2)
$write("MMU_Cache_Req{");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] != 2'd2)
$write("MMU_Cache_Req{");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd0)
$write("CACHE_LD");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd1)
$write("CACHE_ST");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] != 2'd2 &&
crg_mmu_cache_req$port1__write_1[207:206] != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] != 2'd1)
$write("CACHE_AMO");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] != 2'd2)
$write(" f3 %3b", crg_mmu_cache_req$port1__write_1[205:203]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2)
$write("CACHE_AMO");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] != 2'd2)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2)
$write(" f3 %3b", crg_mmu_cache_req$port1__write_1[205:203]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] != 2'd2)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] != 2'd2)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2 &&
crg_mmu_cache_req$port1__write_1[74:70] == 5'b00010)
$write("LR");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2 &&
crg_mmu_cache_req$port1__write_1[74:70] == 5'b00011)
$write("SC");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2 &&
crg_mmu_cache_req$port1__write_1[74:70] == 5'b0)
$write("ADD");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2 &&
crg_mmu_cache_req$port1__write_1[74:70] == 5'b00001)
$write("SWAP");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2 &&
crg_mmu_cache_req$port1__write_1[74:70] == 5'b00100)
$write("XOR");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2 &&
crg_mmu_cache_req$port1__write_1[74:70] == 5'b01100)
$write("AND");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2 &&
crg_mmu_cache_req$port1__write_1[74:70] == 5'b01000)
$write("OR");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2 &&
crg_mmu_cache_req$port1__write_1[74:70] == 5'b10000)
$write("MIN");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2 &&
crg_mmu_cache_req$port1__write_1[74:70] == 5'b10100)
$write("MAX");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2 &&
crg_mmu_cache_req$port1__write_1[74:70] == 5'b11000)
$write("MINU");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2 &&
crg_mmu_cache_req$port1__write_1[74:70] != 5'b00010 &&
crg_mmu_cache_req$port1__write_1[74:70] != 5'b00011 &&
crg_mmu_cache_req$port1__write_1[74:70] != 5'b0 &&
crg_mmu_cache_req$port1__write_1[74:70] != 5'b00001 &&
crg_mmu_cache_req$port1__write_1[74:70] != 5'b00100 &&
crg_mmu_cache_req$port1__write_1[74:70] != 5'b01100 &&
crg_mmu_cache_req$port1__write_1[74:70] != 5'b01000 &&
crg_mmu_cache_req$port1__write_1[74:70] != 5'b10000 &&
crg_mmu_cache_req$port1__write_1[74:70] != 5'b10100 &&
crg_mmu_cache_req$port1__write_1[74:70] != 5'b11000)
$write("MAXU");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] != 2'd2)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2)
$write(" aqrl %2b", crg_mmu_cache_req$port1__write_1[69:68]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] != 2'd2)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0)
$write(" va %0h", crg_mmu_cache_req$port1__write_1[202:139]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
(crg_mmu_cache_req$port1__write_1[207:206] == 2'd2 &&
crg_mmu_cache_req$port1__write_1[74:70] != 5'b00010 ||
crg_mmu_cache_req$port1__write_1[207:206] == 2'd1))
$write(" st_val %0h", crg_mmu_cache_req$port1__write_1[138:75]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
(crg_mmu_cache_req$port1__write_1[207:206] != 2'd2 ||
crg_mmu_cache_req$port1__write_1[74:70] == 5'b00010) &&
crg_mmu_cache_req$port1__write_1[207:206] != 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0)
$write(" priv %0d sstatus_SUM %0d mstatus_MXR %0d satp %0h",
crg_mmu_cache_req$port1__write_1[67:66],
crg_mmu_cache_req$port1__write_1[65],
crg_mmu_cache_req$port1__write_1[64],
crg_mmu_cache_req$port1__write_1[63:0]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0)
$write("}");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0)
$finish(32'd1);
end
// synopsys translate_on
endmodule // mkD_MMU_Cache
|
//////////////////////////////////////////////////////////////////////////////////
// AutoFIFOPopControl for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: Auto FIFO pop controller
// Module Name: AutoFIFOPopControl
// File Name: AutoFIFOPopControl.v
//
// Version: v1.0.0
//
// Description: Automatical FIFO data pop control
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module AutoFIFOPopControl
(
iClock ,
iReset ,
oPopSignal ,
iEmpty ,
oValid ,
iReady
);
input iClock ;
input iReset ;
output oPopSignal ;
input iEmpty ;
output oValid ;
input iReady ;
reg rValid ;
assign oPopSignal = (!iEmpty && (!rValid || iReady));
assign oValid = rValid;
always @ (posedge iClock)
if (iReset)
rValid <= 1'b0;
else
if ((!rValid || iReady))
rValid <= oPopSignal;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21BOI_2_V
`define SKY130_FD_SC_LP__A21BOI_2_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21boi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a21boi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21boi_2 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21boi_2 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21BOI_2_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_dac_common (
// mmcm reset
mmcm_rst,
// dac interface
dac_clk,
dac_rst,
dac_sync,
dac_frame,
dac_par_type,
dac_par_enb,
dac_r1_mode,
dac_datafmt,
dac_datarate,
dac_status,
dac_status_ovf,
dac_status_unf,
dac_clk_ratio,
// drp interface
up_drp_sel,
up_drp_wr,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_locked,
// user channel control
up_usr_chanmax,
dac_usr_chanmax,
up_dac_gpio_in,
up_dac_gpio_out,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
localparam PCORE_VERSION = 32'h00080062;
parameter ID = 0;
// mmcm reset
output mmcm_rst;
// dac interface
input dac_clk;
output dac_rst;
output dac_sync;
output dac_frame;
output dac_par_type;
output dac_par_enb;
output dac_r1_mode;
output dac_datafmt;
output [ 7:0] dac_datarate;
input dac_status;
input dac_status_ovf;
input dac_status_unf;
input [31:0] dac_clk_ratio;
// drp interface
output up_drp_sel;
output up_drp_wr;
output [11:0] up_drp_addr;
output [15:0] up_drp_wdata;
input [15:0] up_drp_rdata;
input up_drp_ready;
input up_drp_locked;
// user channel control
output [ 7:0] up_usr_chanmax;
input [ 7:0] dac_usr_chanmax;
input [31:0] up_dac_gpio_in;
output [31:0] up_dac_gpio_out;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg up_core_preset = 'd0;
reg up_mmcm_preset = 'd0;
reg up_wack = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_mmcm_resetn = 'd0;
reg up_resetn = 'd0;
reg up_dac_sync = 'd0;
reg up_dac_par_type = 'd0;
reg up_dac_par_enb = 'd0;
reg up_dac_r1_mode = 'd0;
reg up_dac_datafmt = 'd0;
reg [ 7:0] up_dac_datarate = 'd0;
reg up_dac_frame = 'd0;
reg up_drp_sel = 'd0;
reg up_drp_wr = 'd0;
reg up_drp_status = 'd0;
reg up_drp_rwn = 'd0;
reg [11:0] up_drp_addr = 'd0;
reg [15:0] up_drp_wdata = 'd0;
reg [15:0] up_drp_rdata_hold = 'd0;
reg up_status_ovf = 'd0;
reg up_status_unf = 'd0;
reg [ 7:0] up_usr_chanmax = 'd0;
reg [31:0] up_dac_gpio_out = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
reg dac_sync_d = 'd0;
reg dac_sync_2d = 'd0;
reg [ 5:0] dac_sync_count = 'd0;
reg dac_sync = 'd0;
reg dac_frame_d = 'd0;
reg dac_frame_2d = 'd0;
reg dac_frame = 'd0;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire up_xfer_done_s;
wire up_status_s;
wire up_status_ovf_s;
wire up_status_unf_s;
wire dac_sync_s;
wire dac_frame_s;
wire [31:0] up_dac_clk_count_s;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == 6'h10) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == 6'h10) ? up_rreq : 1'b0;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_core_preset <= 1'd1;
up_mmcm_preset <= 1'd1;
up_wack <= 'd0;
up_scratch <= 'd0;
up_mmcm_resetn <= 'd0;
up_resetn <= 'd0;
up_dac_sync <= 'd0;
up_dac_par_type <= 'd0;
up_dac_par_enb <= 'd0;
up_dac_r1_mode <= 'd0;
up_dac_datafmt <= 'd0;
up_dac_datarate <= 'd0;
up_dac_frame <= 'd0;
up_drp_sel <= 'd0;
up_drp_wr <= 'd0;
up_drp_status <= 'd0;
up_drp_rwn <= 'd0;
up_drp_addr <= 'd0;
up_drp_wdata <= 'd0;
up_drp_rdata_hold <= 'd0;
up_status_ovf <= 'd0;
up_status_ovf <= 'd0;
up_usr_chanmax <= 'd0;
up_dac_gpio_out <= 'd0;
end else begin
up_core_preset <= ~up_resetn;
up_mmcm_preset <= ~up_mmcm_resetn;
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
up_mmcm_resetn <= up_wdata[1];
up_resetn <= up_wdata[0];
end
if (up_dac_sync == 1'b1) begin
if (up_xfer_done_s == 1'b1) begin
up_dac_sync <= 1'b0;
end
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
up_dac_sync <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h12)) begin
up_dac_par_type <= up_wdata[7];
up_dac_par_enb <= up_wdata[6];
up_dac_r1_mode <= up_wdata[5];
up_dac_datafmt <= up_wdata[4];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin
up_dac_datarate <= up_wdata[7:0];
end
if (up_dac_frame == 1'b1) begin
if (up_xfer_done_s == 1'b1) begin
up_dac_frame <= 1'b0;
end
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
up_dac_frame <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_sel <= 1'b1;
up_drp_wr <= ~up_wdata[28];
end else begin
up_drp_sel <= 1'b0;
up_drp_wr <= 1'b0;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_status <= 1'b1;
end else if (up_drp_ready == 1'b1) begin
up_drp_status <= 1'b0;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_rwn <= up_wdata[28];
up_drp_addr <= up_wdata[27:16];
up_drp_wdata <= up_wdata[15:0];
end
if (up_drp_ready == 1'b1) begin
up_drp_rdata_hold <= up_drp_rdata;
end
if (up_status_ovf_s == 1'b1) begin
up_status_ovf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
up_status_ovf <= up_status_ovf & ~up_wdata[1];
end
if (up_status_unf_s == 1'b1) begin
up_status_unf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
up_status_unf <= up_status_unf & ~up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin
up_usr_chanmax <= up_wdata[7:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2f)) begin
up_dac_gpio_out <= up_wdata;
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[7:0])
8'h00: up_rdata <= PCORE_VERSION;
8'h01: up_rdata <= ID;
8'h02: up_rdata <= up_scratch;
8'h10: up_rdata <= {30'd0, up_mmcm_resetn, up_resetn};
8'h11: up_rdata <= {31'd0, up_dac_sync};
8'h12: up_rdata <= {24'd0, up_dac_par_type, up_dac_par_enb, up_dac_r1_mode,
up_dac_datafmt, 4'd0};
8'h13: up_rdata <= {24'd0, up_dac_datarate};
8'h14: up_rdata <= {31'd0, up_dac_frame};
8'h15: up_rdata <= up_dac_clk_count_s;
8'h16: up_rdata <= dac_clk_ratio;
8'h17: up_rdata <= {31'd0, up_status_s};
8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, up_drp_wdata};
8'h1d: up_rdata <= {14'd0, up_drp_locked, up_drp_status, up_drp_rdata_hold};
8'h22: up_rdata <= {30'd0, up_status_ovf, up_status_unf};
8'h28: up_rdata <= {24'd0, dac_usr_chanmax};
8'h2e: up_rdata <= up_dac_gpio_in;
8'h2f: up_rdata <= up_dac_gpio_out;
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
// resets
ad_rst i_mmcm_rst_reg (.preset(up_mmcm_preset), .clk(up_clk), .rst(mmcm_rst));
ad_rst i_core_rst_reg (.preset(up_core_preset), .clk(dac_clk), .rst(dac_rst));
// dac control & status
up_xfer_cntrl #(.DATA_WIDTH(14)) i_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_dac_sync,
up_dac_frame,
up_dac_par_type,
up_dac_par_enb,
up_dac_r1_mode,
up_dac_datafmt,
up_dac_datarate}),
.up_xfer_done (up_xfer_done_s),
.d_rst (dac_rst),
.d_clk (dac_clk),
.d_data_cntrl ({ dac_sync_s,
dac_frame_s,
dac_par_type,
dac_par_enb,
dac_r1_mode,
dac_datafmt,
dac_datarate}));
up_xfer_status #(.DATA_WIDTH(3)) i_xfer_status (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status ({up_status_s,
up_status_ovf_s,
up_status_unf_s}),
.d_rst (dac_rst),
.d_clk (dac_clk),
.d_data_status ({ dac_status,
dac_status_ovf,
dac_status_unf}));
// generate frame and enable
always @(posedge dac_clk) begin
dac_sync_d <= dac_sync_s;
dac_sync_2d <= dac_sync_d;
if (dac_sync_count[5] == 1'b1) begin
dac_sync_count <= dac_sync_count + 1'b1;
end else if ((dac_sync_d == 1'b1) && (dac_sync_2d == 1'b0)) begin
dac_sync_count <= 6'h20;
end
dac_sync <= dac_sync_count[5];
dac_frame_d <= dac_frame_s;
dac_frame_2d <= dac_frame_d;
dac_frame <= dac_frame_d & ~dac_frame_2d;
end
// dac clock monitor
up_clock_mon i_clock_mon (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_d_count (up_dac_clk_count_s),
.d_rst (dac_rst),
.d_clk (dac_clk));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XNOR2_SYMBOL_V
`define SKY130_FD_SC_LP__XNOR2_SYMBOL_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__xnor2 (
//# {{data|Data Signals}}
input A,
input B,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__XNOR2_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21BOI_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__A21BOI_PP_BLACKBOX_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a21boi (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21BOI_PP_BLACKBOX_V
|
/* salsa_slowsixteen.v
*
* Copyright (c) 2013 kramble
* Derived from scrypt.c Copyright 2009 Colin Percival, 2011 ArtForz
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
module salsa (clk, B, Bx, Bo, X0out, Xaddr);
// Latency 16 clock cycles, approx 20nS propagation delay (SLOW!)
input clk;
// input feedback;
input [511:0]B;
input [511:0]Bx;
// output reg [511:0]Bo; // Output is registered
output [511:0]Bo; // Output is async
output [511:0]X0out; // Becomes new X0
output [9:0] Xaddr;
wire [9:0] xa1, xa2, xa3, xa4, ya1, ya2, ya3, ya4;
reg [511:0]x1d1, x1d1a;
reg [511:0]x1d2, x1d2a;
reg [511:0]x1d3, x1d3a;
reg [511:0]x1d4, x1d4a;
reg [511:0]Xod1, Xod1a;
reg [511:0]Xod2, Xod2a;
reg [511:0]Xod3, Xod3a;
reg [511:0]Xod4, X0out;
reg [511:0]xxd1, xxd1a;
reg [511:0]xxd2, xxd2a;
reg [511:0]xxd3, xxd3a;
reg [511:0]xxd4, xxd4a;
reg [511:0]yyd1, yyd1a;
reg [511:0]yyd2, yyd2a;
reg [511:0]yyd3, yyd3a;
reg [511:0]yyd4, yyd4a;
wire [511:0]xx; // Initial xor
wire [511:0]x1; // Salasa core outputs
wire [511:0]x2;
wire [511:0]x3;
wire [511:0]xr;
wire [511:0]Xo;
// Four salsa iterations. NB use registered salsa_core so 4 clock cycles.
salsa_core salsax1 (clk, xx, x1, xa1);
salsa_core salsax2 (clk, x1, x2, xa2);
salsa_core salsax3 (clk, x2, x3, xa3);
salsa_core salsax4 (clk, x3, xr, xa4);
wire [511:0]yy; // Initial xor
wire [511:0]y1; // Salasa core outputs
wire [511:0]y2;
wire [511:0]y3;
wire [511:0]yr;
// Four salsa iterations. NB use registered salsa_core so 4 clock cycles.
salsa_core salsay1 (clk, yy, y1, ya1);
salsa_core salsay2 (clk, y1, y2, ya2);
salsa_core salsay3 (clk, y2, y3, ya3);
salsa_core salsay4 (clk, y3, yr, ya4);
assign Xaddr = yyd4[9:0] + ya4;
genvar i;
generate
for (i = 0; i < 16; i = i + 1) begin : XX
// Initial XOR. NB this adds to the propagation delay of the first salsa, may want register it.
assign xx[`IDX(i)] = B[`IDX(i)] ^ Bx[`IDX(i)];
assign Xo[`IDX(i)] = xxd4a[`IDX(i)] + xr[`IDX(i)];
assign yy[`IDX(i)] = x1d4a[`IDX(i)] ^ Xo[`IDX(i)];
assign Bo[`IDX(i)] = yyd4a[`IDX(i)] + yr[`IDX(i)]; // Async output
end
endgenerate
always @ (posedge clk)
begin
x1d1 <= Bx;
x1d1a <= x1d1;
x1d2 <= x1d1a;
x1d2a <= x1d2;
x1d3 <= x1d2a;
x1d3a <= x1d3;
x1d4 <= x1d3a;
x1d4a <= x1d4;
Xod1 <= Xo;
Xod1a <= Xod1;
Xod2 <= Xod1a;
Xod2a <= Xod2;
Xod3 <= Xod2a;
Xod3a <= Xod3;
Xod4 <= Xod3a;
X0out <= Xod4; // We output this to become new X0
xxd1 <= xx;
xxd1a <= xxd1;
xxd2 <= xxd1a;
xxd2a <= xxd2;
xxd3 <= xxd2a;
xxd3a <= xxd3;
xxd4 <= xxd3a;
xxd4a <= xxd4;
yyd1 <= yy;
yyd1a <= yyd1;
yyd2 <= yyd1a;
yyd2a <= yyd2;
yyd3 <= yyd2a;
yyd3a <= yyd3;
yyd4 <= yyd3a;
yyd4a <= yyd4;
end
endmodule
module salsa_core (clk, xx, out, Xaddr);
input clk;
input [511:0]xx;
output reg [511:0]out; // Output is registered
output [9:0] Xaddr; // Address output unregistered
// This is clunky due to my lack of verilog skills but it works so elegance can come later
wire [31:0]c00; // Column results
wire [31:0]c01;
wire [31:0]c02;
wire [31:0]c03;
wire [31:0]c04;
wire [31:0]c05;
wire [31:0]c06;
wire [31:0]c07;
wire [31:0]c08;
wire [31:0]c09;
wire [31:0]c10;
wire [31:0]c11;
wire [31:0]c12;
wire [31:0]c13;
wire [31:0]c14;
wire [31:0]c15;
wire [31:0]r00; // Row results
wire [31:0]r01;
wire [31:0]r02;
wire [31:0]r03;
wire [31:0]r04;
wire [31:0]r05;
wire [31:0]r06;
wire [31:0]r07;
wire [31:0]r08;
wire [31:0]r09;
wire [31:0]r10;
wire [31:0]r11;
wire [31:0]r12;
wire [31:0]r13;
wire [31:0]r14;
wire [31:0]r15;
wire [31:0]c00s; // Column sums
wire [31:0]c01s;
wire [31:0]c02s;
wire [31:0]c03s;
wire [31:0]c04s;
wire [31:0]c05s;
wire [31:0]c06s;
wire [31:0]c07s;
wire [31:0]c08s;
wire [31:0]c09s;
wire [31:0]c10s;
wire [31:0]c11s;
wire [31:0]c12s;
wire [31:0]c13s;
wire [31:0]c14s;
wire [31:0]c15s;
wire [31:0]r00s; // Row sums
wire [31:0]r01s;
wire [31:0]r02s;
wire [31:0]r03s;
wire [31:0]r04s;
wire [31:0]r05s;
wire [31:0]r06s;
wire [31:0]r07s;
wire [31:0]r08s;
wire [31:0]r09s;
wire [31:0]r10s;
wire [31:0]r11s;
wire [31:0]r12s;
wire [31:0]r13s;
wire [31:0]r14s;
wire [31:0]r15s;
reg [31:0]c00d; // Column results registered
reg [31:0]c01d;
reg [31:0]c02d;
reg [31:0]c03d;
reg [31:0]c04d;
reg [31:0]c05d;
reg [31:0]c06d;
reg [31:0]c07d;
reg [31:0]c08d;
reg [31:0]c09d;
reg [31:0]c10d;
reg [31:0]c11d;
reg [31:0]c12d;
reg [31:0]c13d;
reg [31:0]c14d;
reg [31:0]c15d;
/* From scrypt.c
#define R(a,b) (((a) << (b)) | ((a) >> (32 - (b))))
for (i = 0; i < 8; i += 2) {
// Operate on columns
x04 ^= R(x00+x12, 7); x09 ^= R(x05+x01, 7); x14 ^= R(x10+x06, 7); x03 ^= R(x15+x11, 7);
x08 ^= R(x04+x00, 9); x13 ^= R(x09+x05, 9); x02 ^= R(x14+x10, 9); x07 ^= R(x03+x15, 9);
x12 ^= R(x08+x04,13); x01 ^= R(x13+x09,13); x06 ^= R(x02+x14,13); x11 ^= R(x07+x03,13);
x00 ^= R(x12+x08,18); x05 ^= R(x01+x13,18); x10 ^= R(x06+x02,18); x15 ^= R(x11+x07,18);
// Operate on rows
x01 ^= R(x00+x03, 7); x06 ^= R(x05+x04, 7); x11 ^= R(x10+x09, 7); x12 ^= R(x15+x14, 7);
x02 ^= R(x01+x00, 9); x07 ^= R(x06+x05, 9); x08 ^= R(x11+x10, 9); x13 ^= R(x12+x15, 9);
x03 ^= R(x02+x01,13); x04 ^= R(x07+x06,13); x09 ^= R(x08+x11,13); x14 ^= R(x13+x12,13);
x00 ^= R(x03+x02,18); x05 ^= R(x04+x07,18); x10 ^= R(x09+x08,18); x15 ^= R(x14+x13,18);
}
*/
// cols
assign c04s = xx[`IDX(0)] + xx[`IDX(12)];
assign c04 = xx[`IDX(4)] ^ { c04s[24:0], c04s[31:25] };
assign c09s = xx[`IDX(5)] + xx[`IDX(1)];
assign c09 = xx[`IDX(9)] ^ { c09s[24:0], c09s[31:25] };
assign c14s = xx[`IDX(10)] + xx[`IDX(6)];
assign c14 = xx[`IDX(14)] ^ { c14s[24:0], c14s[31:25] };
assign c03s = xx[`IDX(15)] + xx[`IDX(11)];
assign c03 = xx[`IDX(03)] ^ { c03s[24:0], c03s[31:25] };
assign c08s = c04 + xx[`IDX(0)];
assign c08 = xx[`IDX(8)] ^ { c08s[22:0], c08s[31:23] };
assign c13s = c09 + xx[`IDX(5)];
assign c13 = xx[`IDX(13)] ^ { c13s[22:0], c13s[31:23] };
assign c02s = c14 + xx[`IDX(10)];
assign c02 = xx[`IDX(2)] ^ { c02s[22:0], c02s[31:23] };
assign c07s = c03 + xx[`IDX(15)];
assign c07 = xx[`IDX(7)] ^ { c07s[22:0], c07s[31:23] };
assign c12s = c08 + c04;
assign c12 = xx[`IDX(12)] ^ { c12s[18:0], c12s[31:19] };
assign c01s = c13 + c09;
assign c01 = xx[`IDX(1)] ^ { c01s[18:0], c01s[31:19] };
assign c06s = c02 + c14;
assign c06 = xx[`IDX(6)] ^ { c06s[18:0], c06s[31:19] };
assign c11s = c07 + c03;
assign c11 = xx[`IDX(11)] ^ { c11s[18:0], c11s[31:19] };
assign c00s = c12 + c08;
assign c00 = xx[`IDX(0)] ^ { c00s[13:0], c00s[31:14] };
assign c05s = c01 + c13;
assign c05 = xx[`IDX(5)] ^ { c05s[13:0], c05s[31:14] };
assign c10s = c06 + c02;
assign c10 = xx[`IDX(10)] ^ { c10s[13:0], c10s[31:14] };
assign c15s = c11 + c07;
assign c15 = xx[`IDX(15)] ^ { c15s[13:0], c15s[31:14] };
// rows
assign r01s = c00d + c03d;
assign r01 = c01d ^ { r01s[24:0], r01s[31:25] };
assign r06s = c05d + c04d;
assign r06 = c06d ^ { r06s[24:0], r06s[31:25] };
assign r11s = c10d + c09d;
assign r11 = c11d ^ { r11s[24:0], r11s[31:25] };
assign r12s = c15d + c14d;
assign r12 = c12d ^ { r12s[24:0], r12s[31:25] };
assign r02s = r01 + c00d;
assign r02 = c02d ^ { r02s[22:0], r02s[31:23] };
assign r07s = r06 + c05d;
assign r07 = c07d ^ { r07s[22:0], r07s[31:23] };
assign r08s = r11 + c10d;
assign r08 = c08d ^ { r08s[22:0], r08s[31:23] };
assign r13s = r12 + c15d;
assign r13 = c13d ^ { r13s[22:0], r13s[31:23] };
assign r03s = r02 + r01;
assign r03 = c03d ^ { r03s[18:0], r03s[31:19] };
assign r04s = r07 + r06;
assign r04 = c04d ^ { r04s[18:0], r04s[31:19] };
assign r09s = r08 + r11;
assign r09 = c09d ^ { r09s[18:0], r09s[31:19] };
assign r14s = r13 + r12;
assign r14 = c14d ^ { r14s[18:0], r14s[31:19] };
assign r00s = r03 + r02;
assign r00 = c00d ^ { r00s[13:0], r00s[31:14] };
assign r05s = r04 + r07;
assign r05 = c05d ^ { r05s[13:0], r05s[31:14] };
assign r10s = r09 + r08;
assign r10 = c10d ^ { r10s[13:0], r10s[31:14] };
assign r15s = r14 + r13;
assign r15 = c15d ^ { r15s[13:0], r15s[31:14] };
wire [511:0]xo; // Rename row results
assign xo = { r15, r14, r13, r12, r11, r10, r09, r08, r07, r06, r05, r04, r03, r02, r01, r00 };
assign Xaddr = xo[9:0]; // Unregistered output
always @ (posedge clk)
begin
c00d <= c00;
c01d <= c01;
c02d <= c02;
c03d <= c03;
c04d <= c04;
c05d <= c05;
c06d <= c06;
c07d <= c07;
c08d <= c08;
c09d <= c09;
c10d <= c10;
c11d <= c11;
c12d <= c12;
c13d <= c13;
c14d <= c14;
c15d <= c15;
out <= xo; // Registered output
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB16 ////
//// - Xilinx Virtex RAMB4 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_spram_1024x8.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.9 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.8 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
// Revision 1.7 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.3 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/11/02 18:57:14 lampret
// Modified virtual silicon instantiations.
//
// Revision 1.7 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.1 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/30 05:38:02 lampret
// Adding empty directories required by HDL coding guidelines
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_spram_1024x8(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 10;
parameter dw = 8;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_1024x8 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_1024x8_bist artisan_ssp(
`else
art_hssp_1024x8 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(doq)
);
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
.clk(clk),
.adr(addr),
.d(di),
.we(we),
.oe(oe),
.me(ce),
.q(doq)
);
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_1024x8 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_1024x8_bist vs_ssp(
`else
vs_hdsp_1024x8 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
.WEN(~we),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq)
);
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S4 ramb4_s4_0(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[3:0]),
.EN(ce),
.WE(we),
.DO(doq[3:0])
);
//
// Block 1
//
RAMB4_S4 ramb4_s4_1(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[7:4]),
.EN(ce),
.WE(we),
.DO(doq[7:4])
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
RAMB16_S9 ramb16_s9(
.CLK(clk),
.SSR(rst),
.ADDR({1'b0,addr}),
.DI(di),
.DIP(1'b0),
.EN(ce),
.WE(we),
.DO(doq),
.DOP()
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
wire wr;
assign wr = ce & we;
initial $display("Using Altera LPM.");
lpm_ram_dq lpm_ram_dq_component (
.address(addr),
.inclock(clk),
.outclock(clk),
.data(di),
.we(wr),
.q(doq)
);
defparam lpm_ram_dq_component.lpm_width = dw,
lpm_ram_dq_component.lpm_widthad = aw,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_rx_req # (
parameter P_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [2:0] pcie_max_read_req_size,
output pcie_rx_cmd_rd_en,
input [33:0] pcie_rx_cmd_rd_data,
input pcie_rx_cmd_empty_n,
output pcie_tag_alloc,
output [7:0] pcie_alloc_tag,
output [9:4] pcie_tag_alloc_len,
input pcie_tag_full_n,
input pcie_rx_fifo_full_n,
output tx_dma_mrd_req,
output [7:0] tx_dma_mrd_tag,
output [11:2] tx_dma_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_dma_mrd_addr,
input tx_dma_mrd_req_ack
);
localparam LP_PCIE_TAG_PREFIX = 4'b0001;
localparam LP_PCIE_MRD_DELAY = 8;
localparam S_IDLE = 9'b000000001;
localparam S_PCIE_RX_CMD_0 = 9'b000000010;
localparam S_PCIE_RX_CMD_1 = 9'b000000100;
localparam S_PCIE_CHK_NUM_MRD = 9'b000001000;
localparam S_PCIE_MRD_REQ = 9'b000010000;
localparam S_PCIE_MRD_ACK = 9'b000100000;
localparam S_PCIE_MRD_DONE = 9'b001000000;
localparam S_PCIE_MRD_DELAY = 9'b010000000;
localparam S_PCIE_MRD_NEXT = 9'b100000000;
reg [8:0] cur_state;
reg [8:0] next_state;
reg [2:0] r_pcie_max_read_req_size;
reg r_pcie_rx_cmd_rd_en;
reg [12:2] r_pcie_rx_len;
reg [9:2] r_pcie_rx_cur_len;
reg [C_PCIE_ADDR_WIDTH-1:2] r_pcie_addr;
reg [3:0] r_pcie_rx_tag;
reg r_pcie_rx_tag_update;
reg [5:0] r_pcie_mrd_delay;
reg r_pcie_tag_alloc;
reg r_tx_dma_mrd_req;
assign pcie_rx_cmd_rd_en = r_pcie_rx_cmd_rd_en;
assign pcie_tag_alloc = r_pcie_tag_alloc;
assign pcie_alloc_tag = {LP_PCIE_TAG_PREFIX, r_pcie_rx_tag};
assign pcie_tag_alloc_len = r_pcie_rx_cur_len[9:4];
assign tx_dma_mrd_req = r_tx_dma_mrd_req;
assign tx_dma_mrd_tag = {LP_PCIE_TAG_PREFIX, r_pcie_rx_tag};
assign tx_dma_mrd_len = {2'b0, r_pcie_rx_cur_len};
assign tx_dma_mrd_addr = r_pcie_addr;
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(pcie_rx_cmd_empty_n == 1)
next_state <= S_PCIE_RX_CMD_0;
else
next_state <= S_IDLE;
end
S_PCIE_RX_CMD_0: begin
next_state <= S_PCIE_RX_CMD_1;
end
S_PCIE_RX_CMD_1: begin
next_state <= S_PCIE_CHK_NUM_MRD;
end
S_PCIE_CHK_NUM_MRD: begin
if(pcie_rx_fifo_full_n == 1 && pcie_tag_full_n == 1)
next_state <= S_PCIE_MRD_REQ;
else
next_state <= S_PCIE_CHK_NUM_MRD;
end
S_PCIE_MRD_REQ: begin
next_state <= S_PCIE_MRD_ACK;
end
S_PCIE_MRD_ACK: begin
if(tx_dma_mrd_req_ack == 1)
next_state <= S_PCIE_MRD_DONE;
else
next_state <= S_PCIE_MRD_ACK;
end
S_PCIE_MRD_DONE: begin
next_state <= S_PCIE_MRD_DELAY;
end
S_PCIE_MRD_DELAY: begin
if(r_pcie_mrd_delay == 0)
next_state <= S_PCIE_MRD_NEXT;
else
next_state <= S_PCIE_MRD_DELAY;
end
S_PCIE_MRD_NEXT: begin
if(r_pcie_rx_len == 0)
next_state <= S_IDLE;
else
next_state <= S_PCIE_CHK_NUM_MRD;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_pcie_rx_tag <= 0;
end
else begin
if(r_pcie_rx_tag_update == 1)
r_pcie_rx_tag <= r_pcie_rx_tag + 1;
end
end
always @ (posedge pcie_user_clk)
begin
r_pcie_max_read_req_size <= pcie_max_read_req_size;
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
end
S_PCIE_RX_CMD_0: begin
r_pcie_rx_len <= {pcie_rx_cmd_rd_data[10:2], 2'b0};
end
S_PCIE_RX_CMD_1: begin
case(r_pcie_max_read_req_size)
3'b010: begin
if(r_pcie_rx_len[8:7] == 0 && r_pcie_rx_len[6:2] == 0)
r_pcie_rx_cur_len[9:7] <= 3'b100;
else
r_pcie_rx_cur_len[9:7] <= {1'b0, r_pcie_rx_len[8:7]};
end
3'b001: begin
if(r_pcie_rx_len[7] == 0 && r_pcie_rx_len[6:2] == 0)
r_pcie_rx_cur_len[9:7] <= 3'b010;
else
r_pcie_rx_cur_len[9:7] <= {2'b0, r_pcie_rx_len[7]};
end
default: begin
if(r_pcie_rx_len[6:2] == 0)
r_pcie_rx_cur_len[9:7] <= 3'b001;
else
r_pcie_rx_cur_len[9:7] <= 3'b000;
end
endcase
r_pcie_rx_cur_len[6:2] <= r_pcie_rx_len[6:2];
r_pcie_addr <= {pcie_rx_cmd_rd_data[33:2], 2'b0};
end
S_PCIE_CHK_NUM_MRD: begin
end
S_PCIE_MRD_REQ: begin
end
S_PCIE_MRD_ACK: begin
end
S_PCIE_MRD_DONE: begin
r_pcie_addr <= r_pcie_addr + r_pcie_rx_cur_len;
r_pcie_rx_len <= r_pcie_rx_len - r_pcie_rx_cur_len;
case(r_pcie_max_read_req_size)
3'b010: r_pcie_rx_cur_len <= 8'h80;
3'b001: r_pcie_rx_cur_len <= 8'h40;
default: r_pcie_rx_cur_len <= 8'h20;
endcase
r_pcie_mrd_delay <= LP_PCIE_MRD_DELAY;
end
S_PCIE_MRD_DELAY: begin
r_pcie_mrd_delay <= r_pcie_mrd_delay - 1'b1;
end
S_PCIE_MRD_NEXT: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_pcie_rx_cmd_rd_en <= 0;
r_pcie_tag_alloc <= 0;
r_tx_dma_mrd_req <= 0;
r_pcie_rx_tag_update <= 0;
end
S_PCIE_RX_CMD_0: begin
r_pcie_rx_cmd_rd_en <= 1;
r_pcie_tag_alloc <= 0;
r_tx_dma_mrd_req <= 0;
r_pcie_rx_tag_update <= 0;
end
S_PCIE_RX_CMD_1: begin
r_pcie_rx_cmd_rd_en <= 1;
r_pcie_tag_alloc <= 0;
r_tx_dma_mrd_req <= 0;
r_pcie_rx_tag_update <= 0;
end
S_PCIE_CHK_NUM_MRD: begin
r_pcie_rx_cmd_rd_en <= 0;
r_pcie_tag_alloc <= 0;
r_tx_dma_mrd_req <= 0;
r_pcie_rx_tag_update <= 0;
end
S_PCIE_MRD_REQ: begin
r_pcie_rx_cmd_rd_en <= 0;
r_pcie_tag_alloc <= 1;
r_tx_dma_mrd_req <= 1;
r_pcie_rx_tag_update <= 0;
end
S_PCIE_MRD_ACK: begin
r_pcie_rx_cmd_rd_en <= 0;
r_pcie_tag_alloc <= 0;
r_tx_dma_mrd_req <= 0;
r_pcie_rx_tag_update <= 0;
end
S_PCIE_MRD_DONE: begin
r_pcie_rx_cmd_rd_en <= 0;
r_pcie_tag_alloc <= 0;
r_tx_dma_mrd_req <= 0;
r_pcie_rx_tag_update <= 1;
end
S_PCIE_MRD_DELAY: begin
r_pcie_rx_cmd_rd_en <= 0;
r_pcie_tag_alloc <= 0;
r_tx_dma_mrd_req <= 0;
r_pcie_rx_tag_update <= 0;
end
S_PCIE_MRD_NEXT: begin
r_pcie_rx_cmd_rd_en <= 0;
r_pcie_tag_alloc <= 0;
r_tx_dma_mrd_req <= 0;
r_pcie_rx_tag_update <= 0;
end
default: begin
r_pcie_rx_cmd_rd_en <= 0;
r_pcie_tag_alloc <= 0;
r_tx_dma_mrd_req <= 0;
r_pcie_rx_tag_update <= 0;
end
endcase
end
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: level2_256_139.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 222 10/21/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module level2_256_139 (
aclr,
clock,
data,
rdreq,
wrreq,
q,
usedw);
input aclr;
input clock;
input [138:0] data;
input rdreq;
input wrreq;
output [138:0] q;
output [7:0] usedw;
wire [7:0] sub_wire0;
wire [138:0] sub_wire1;
wire [7:0] usedw = sub_wire0[7:0];
wire [138:0] q = sub_wire1[138:0];
scfifo scfifo_component (
.rdreq (rdreq),
.aclr (aclr),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.q (sub_wire1)
// synopsys translate_off
,
.almost_empty (),
.almost_full (),
.empty (),
.full (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 139,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "139"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "139"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "139"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 139 0 INPUT NODEFVAL data[138..0]
// Retrieval info: USED_PORT: q 0 0 139 0 OUTPUT NODEFVAL q[138..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL usedw[7..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 139 0 data 0 0 139 0
// Retrieval info: CONNECT: q 0 0 139 0 @q 0 0 139 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL level2_256_139.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL level2_256_139.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL level2_256_139.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL level2_256_139.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL level2_256_139_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL level2_256_139_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL level2_256_139_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL level2_256_139_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* This is written by Zhiyang Ong
* for EE577b Extra Credit Homework , Question 2
*
* Behavioral model for the large XOR gate
*/
module large_xor (a,b,out);
// Output vector
output reg [14:0] out;
// Input vector
input [14:0] a;
// Another input vector
input [15:1] b;
// Declare "reg" signals...
//reg [3:0] in_bar;
// Declare "wire" signals...
// Defining constants: parameter [name_of_constant] = value;
always @(*)
begin
out[0]=a[0]^b[1];
out[1]=a[1]^b[2];
out[2]=a[2]^b[3];
out[3]=a[3]^b[4];
out[4]=a[4]^b[5];
out[5]=a[5]^b[6];
out[6]=a[6]^b[7];
out[7]=a[7]^b[8];
out[8]=a[8]^b[9];
out[9]=a[9]^b[10];
out[10]=a[10]^b[11];
out[11]=a[11]^b[12];
out[12]=a[12]^b[13];
out[13]=a[13]^b[14];
out[14]=a[14]^b[15];
end
endmodule
module parity_stripper (in,out);
// Output vector
output reg [10:0] out;
// Input vector
input [14:0] in;
// Declare "reg" signals...
//reg [3:0] in_bar;
// Declare "wire" signals...
// Defining constants: parameter [name_of_constant] = value;
always @(*)
begin
out[0]=in[2];
out[1]=in[4];
out[2]=in[5];
out[3]=in[6];
out[4]=in[8];
out[5]=in[9];
out[6]=in[10];
out[7]=in[11];
out[8]=in[12];
out[9]=in[13];
out[10]=in[14];
end
endmodule
|
`include "defines.v"
module rom(
input wire[15:0] insAddr_i,
output reg[31:0] ins_o
);
always @(*) begin
//-*case*-/
case (insAddr_i)
0: ins_o = 32'h00000000;
4: ins_o = 32'h10000001;
8: ins_o = 32'h00000000;
12: ins_o = 32'h3c08beff;
16: ins_o = 32'h3508fff8;
20: ins_o = 32'h240900ff;
24: ins_o = 32'had090000;
28: ins_o = 32'h3c10be00;
32: ins_o = 32'h240f0000;
36: ins_o = 32'h020f7821;
40: ins_o = 32'h8de90000;
44: ins_o = 32'h8def0004;
48: ins_o = 32'h000f7c00;
52: ins_o = 32'h012f4825;
56: ins_o = 32'h3c08464c;
60: ins_o = 32'h3508457f;
64: ins_o = 32'h11090003;
68: ins_o = 32'h00000000;
72: ins_o = 32'h10000042;
76: ins_o = 32'h00000000;
80: ins_o = 32'h240f0038;
84: ins_o = 32'h020f7821;
88: ins_o = 32'h8df10000;
92: ins_o = 32'h8def0004;
96: ins_o = 32'h000f7c00;
100: ins_o = 32'h022f8825;
104: ins_o = 32'h240f0058;
108: ins_o = 32'h020f7821;
112: ins_o = 32'h8df20000;
116: ins_o = 32'h8def0004;
120: ins_o = 32'h000f7c00;
124: ins_o = 32'h024f9025;
128: ins_o = 32'h3252ffff;
132: ins_o = 32'h240f0030;
136: ins_o = 32'h020f7821;
140: ins_o = 32'h8df30000;
144: ins_o = 32'h8def0004;
148: ins_o = 32'h000f7c00;
152: ins_o = 32'h026f9825;
156: ins_o = 32'h262f0008;
160: ins_o = 32'h000f7840;
164: ins_o = 32'h020f7821;
168: ins_o = 32'h8df40000;
172: ins_o = 32'h8def0004;
176: ins_o = 32'h000f7c00;
180: ins_o = 32'h028fa025;
184: ins_o = 32'h262f0010;
188: ins_o = 32'h000f7840;
192: ins_o = 32'h020f7821;
196: ins_o = 32'h8df50000;
200: ins_o = 32'h8def0004;
204: ins_o = 32'h000f7c00;
208: ins_o = 32'h02afa825;
212: ins_o = 32'h262f0004;
216: ins_o = 32'h000f7840;
220: ins_o = 32'h020f7821;
224: ins_o = 32'h8df60000;
228: ins_o = 32'h8def0004;
232: ins_o = 32'h000f7c00;
236: ins_o = 32'h02cfb025;
240: ins_o = 32'h12800010;
244: ins_o = 32'h00000000;
248: ins_o = 32'h12a0000e;
252: ins_o = 32'h00000000;
256: ins_o = 32'h26cf0000;
260: ins_o = 32'h000f7840;
264: ins_o = 32'h020f7821;
268: ins_o = 32'h8de80000;
272: ins_o = 32'h8def0004;
276: ins_o = 32'h000f7c00;
280: ins_o = 32'h010f4025;
284: ins_o = 32'hae880000;
288: ins_o = 32'h26d60004;
292: ins_o = 32'h26940004;
296: ins_o = 32'h26b5fffc;
300: ins_o = 32'h1ea0fff4;
304: ins_o = 32'h00000000;
308: ins_o = 32'h26310020;
312: ins_o = 32'h2652ffff;
316: ins_o = 32'h1e40ffd7;
320: ins_o = 32'h00000000;
324: ins_o = 32'h02600008;
328: ins_o = 32'h00000000;
332: ins_o = 32'h1000ffff;
336: ins_o = 32'h00000000;
340: ins_o = 32'h1000ffff;
344: ins_o = 32'h00000000;
default: ins_o = 0;
endcase
//-*case*-/
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EINVN_2_V
`define SKY130_FD_SC_HS__EINVN_2_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog wrapper for einvn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__einvn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__einvn_2 (
A ,
TE_B,
Z ,
VPWR,
VGND
);
input A ;
input TE_B;
output Z ;
input VPWR;
input VGND;
sky130_fd_sc_hs__einvn base (
.A(A),
.TE_B(TE_B),
.Z(Z),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__einvn_2 (
A ,
TE_B,
Z
);
input A ;
input TE_B;
output Z ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__einvn base (
.A(A),
.TE_B(TE_B),
.Z(Z)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__EINVN_2_V
|
(** * Hoare2: Hoare Logic, Part II *)
Require Export Hoare.
(* ####################################################### *)
(** * Decorated Programs *)
(** The beauty of Hoare Logic is that it is _compositional_ --
the structure of proofs exactly follows the structure of programs.
This suggests that we can record the essential ideas of a proof
informally (leaving out some low-level calculational details) by
decorating programs with appropriate assertions around each
statement. Such a _decorated program_ carries with it
an (informal) proof of its own correctness. *)
(** For example, here is a complete decorated program: *)
(**
{{ True }} ->>
{{ m = m }}
X ::= m;
{{ X = m }} ->>
{{ X = m /\ p = p }}
Z ::= p;
{{ X = m /\ Z = p }} ->>
{{ Z - X = p - m }}
WHILE X <> 0 DO
{{ Z - X = p - m /\ X <> 0 }} ->>
{{ (Z - 1) - (X - 1) = p - m }}
Z ::= Z - 1;
{{ Z - (X - 1) = p - m }}
X ::= X - 1
{{ Z - X = p - m }}
END;
{{ Z - X = p - m /\ ~ (X <> 0) }} ->>
{{ Z = p - m }} ->>
*)
(** Concretely, a decorated program consists of the program text
interleaved with assertions. To check that a decorated program
represents a valid proof, we check that each individual command is
_locally consistent_ with its accompanying assertions in the
following sense: *)
(**
- [SKIP] is locally consistent if its precondition and
postcondition are the same:
{{ P }}
SKIP
{{ P }}
- The sequential composition of [c1] and [c2] is locally
consistent (with respect to assertions [P] and [R]) if [c1] is
locally consistent (with respect to [P] and [Q]) and [c2] is
locally consistent (with respect to [Q] and [R]):
{{ P }}
c1;
{{ Q }}
c2
{{ R }}
- An assignment is locally consistent if its precondition is
the appropriate substitution of its postcondition:
{{ P [X |-> a] }}
X ::= a
{{ P }}
- A conditional is locally consistent (with respect to assertions
[P] and [Q]) if the assertions at the top of its "then" and
"else" branches are exactly [P /\ b] and [P /\ ~b] and if its "then"
branch is locally consistent (with respect to [P /\ b] and [Q])
and its "else" branch is locally consistent (with respect to
[P /\ ~b] and [Q]):
{{ P }}
IFB b THEN
{{ P /\ b }}
c1
{{ Q }}
ELSE
{{ P /\ ~b }}
c2
{{ Q }}
FI
{{ Q }}
- A while loop with precondition [P] is locally consistent if its
postcondition is [P /\ ~b] and if the pre- and postconditions of
its body are exactly [P /\ b] and [P]:
{{ P }}
WHILE b DO
{{ P /\ b }}
c1
{{ P }}
END
{{ P /\ ~b }}
- A pair of assertions separated by [->>] is locally consistent if
the first implies the second (in all states):
{{ P }} ->>
{{ P' }}
This corresponds to the application of [hoare_consequence] and
is the only place in a decorated program where checking if
decorations are correct is not fully mechanical and syntactic,
but involves logical and/or arithmetic reasoning.
*)
(** We have seen above how _verifying_ the correctness of a
given proof involves checking that every single command is locally
consistent with the accompanying assertions. If we are instead
interested in _finding_ a proof for a given specification we need
to discover the right assertions. This can be done in an almost
automatic way, with the exception of finding loop invariants,
which is the subject of in the next section. In the reminder of
this section we explain in detail how to construct decorations for
several simple programs that don't involve non-trivial loop
invariants. *)
(* ####################################################### *)
(** ** Example: Swapping Using Addition and Subtraction *)
(** Here is a program that swaps the values of two variables using
addition and subtraction (instead of by assigning to a temporary
variable).
X ::= X + Y;
Y ::= X - Y;
X ::= X - Y
We can prove using decorations that this program is correct --
i.e., it always swaps the values of variables [X] and [Y]. *)
(**
(1) {{ X = m /\ Y = n }} ->>
(2) {{ (X + Y) - ((X + Y) - Y) = n /\ (X + Y) - Y = m }}
X ::= X + Y;
(3) {{ X - (X - Y) = n /\ X - Y = m }}
Y ::= X - Y;
(4) {{ X - Y = n /\ Y = m }}
X ::= X - Y
(5) {{ X = n /\ Y = m }}
The decorations were constructed as follows:
- We begin with the undecorated program (the unnumbered lines).
- We then add the specification -- i.e., the outer
precondition (1) and postcondition (5). In the precondition we
use auxiliary variables (parameters) [m] and [n] to remember
the initial values of variables [X] and respectively [Y], so
that we can refer to them in the postcondition (5).
- We work backwards mechanically starting from (5) all the way
to (2). At each step, we obtain the precondition of the
assignment from its postcondition by substituting the assigned
variable with the right-hand-side of the assignment. For
instance, we obtain (4) by substituting [X] with [X - Y]
in (5), and (3) by substituting [Y] with [X - Y] in (4).
- Finally, we verify that (1) logically implies (2) -- i.e.,
that the step from (1) to (2) is a valid use of the law of
consequence. For this we substitute [X] by [m] and [Y] by [n]
and calculate as follows:
(m + n) - ((m + n) - n) = n /\ (m + n) - n = m
(m + n) - m = n /\ m = m
n = n /\ m = m
(Note that, since we are working with natural numbers, not
fixed-size machine integers, we don't need to worry about the
possibility of arithmetic overflow anywhere in this argument.)
*)
(* ####################################################### *)
(** ** Example: Simple Conditionals *)
(** Here is a simple decorated program using conditionals:
(1) {{True}}
IFB X <= Y THEN
(2) {{True /\ X <= Y}} ->>
(3) {{(Y - X) + X = Y \/ (Y - X) + Y = X}}
Z ::= Y - X
(4) {{Z + X = Y \/ Z + Y = X}}
ELSE
(5) {{True /\ ~(X <= Y) }} ->>
(6) {{(X - Y) + X = Y \/ (X - Y) + Y = X}}
Z ::= X - Y
(7) {{Z + X = Y \/ Z + Y = X}}
FI
(8) {{Z + X = Y \/ Z + Y = X}}
These decorations were constructed as follows:
- We start with the outer precondition (1) and postcondition (8).
- We follow the format dictated by the [hoare_if] rule and copy the
postcondition (8) to (4) and (7). We conjoin the precondition (1)
with the guard of the conditional to obtain (2). We conjoin (1)
with the negated guard of the conditional to obtain (5).
- In order to use the assignment rule and obtain (3), we substitute
[Z] by [Y - X] in (4). To obtain (6) we substitute [Z] by [X - Y]
in (7).
- Finally, we verify that (2) implies (3) and (5) implies (6). Both
of these implications crucially depend on the ordering of [X] and
[Y] obtained from the guard. For instance, knowing that [X <= Y]
ensures that subtracting [X] from [Y] and then adding back [X]
produces [Y], as required by the first disjunct of (3). Similarly,
knowing that [~(X <= Y)] ensures that subtracting [Y] from [X] and
then adding back [Y] produces [X], as needed by the second
disjunct of (6). Note that [n - m + m = n] does _not_ hold for
arbitrary natural numbers [n] and [m] (for example, [3 - 5 + 5 =
5]). *)
(** **** Exercise: 2 stars (if_minus_plus_reloaded) *)
(** Fill in valid decorations for the following program:
{{ True }}
IFB X <= Y THEN
{{ }} ->>
{{ }}
Z ::= Y - X
{{ }}
ELSE
{{ }} ->>
{{ }}
Y ::= X + Z
{{ }}
FI
{{ Y = X + Z }}
*)
(* ####################################################### *)
(** ** Example: Reduce to Zero (Trivial Loop) *)
(** Here is a [WHILE] loop that is so simple it needs no
invariant (i.e., the invariant [True] will do the job).
(1) {{ True }}
WHILE X <> 0 DO
(2) {{ True /\ X <> 0 }} ->>
(3) {{ True }}
X ::= X - 1
(4) {{ True }}
END
(5) {{ True /\ X = 0 }} ->>
(6) {{ X = 0 }}
The decorations can be constructed as follows:
- Start with the outer precondition (1) and postcondition (6).
- Following the format dictated by the [hoare_while] rule, we copy
(1) to (4). We conjoin (1) with the guard to obtain (2) and with
the negation of the guard to obtain (5). Note that, because the
outer postcondition (6) does not syntactically match (5), we need a
trivial use of the consequence rule from (5) to (6).
- Assertion (3) is the same as (4), because [X] does not appear in
[4], so the substitution in the assignment rule is trivial.
- Finally, the implication between (2) and (3) is also trivial.
*)
(** From this informal proof, it is easy to read off a formal proof
using the Coq versions of the Hoare rules. Note that we do _not_
unfold the definition of [hoare_triple] anywhere in this proof --
the idea is to use the Hoare rules as a "self-contained" logic for
reasoning about programs. *)
Definition reduce_to_zero' : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
X ::= AMinus (AId X) (ANum 1)
END.
Theorem reduce_to_zero_correct' :
{{fun st => True}}
reduce_to_zero'
{{fun st => st X = 0}}.
Proof.
unfold reduce_to_zero'.
(* First we need to transform the postcondition so
that hoare_while will apply. *)
eapply hoare_consequence_post.
apply hoare_while.
Case "Loop body preserves invariant".
(* Need to massage precondition before [hoare_asgn] applies *)
eapply hoare_consequence_pre. apply hoare_asgn.
(* Proving trivial implication (2) ->> (3) *)
intros st [HT Hbp]. unfold assn_sub. apply I.
Case "Invariant and negated guard imply postcondition".
intros st [Inv GuardFalse].
unfold bassn in GuardFalse. simpl in GuardFalse.
(* SearchAbout helps to find the right lemmas *)
SearchAbout [not true].
rewrite not_true_iff_false in GuardFalse.
SearchAbout [negb false].
rewrite negb_false_iff in GuardFalse.
SearchAbout [beq_nat true].
apply beq_nat_true in GuardFalse.
apply GuardFalse. Qed.
(* ####################################################### *)
(** ** Example: Division *)
(** The following Imp program calculates the integer division and
remainder of two numbers [m] and [n] that are arbitrary constants
in the program.
X ::= m;
Y ::= 0;
WHILE n <= X DO
X ::= X - n;
Y ::= Y + 1
END;
In other words, if we replace [m] and [n] by concrete numbers and
execute the program, it will terminate with the variable [X] set
to the remainder when [m] is divided by [n] and [Y] set to the
quotient. *)
(** In order to give a specification to this program we need to
remember that dividing [m] by [n] produces a reminder [X] and a
quotient [Y] so that [n * Y + X = m /\ X > n].
It turns out that we get lucky with this program and don't have to
think very hard about the loop invariant: the invariant is the
just first conjunct [n * Y + X = m], so we use that to decorate
the program.
(1) {{ True }} ->>
(2) {{ n * 0 + m = m }}
X ::= m;
(3) {{ n * 0 + X = m }}
Y ::= 0;
(4) {{ n * Y + X = m }}
WHILE n <= X DO
(5) {{ n * Y + X = m /\ n <= X }} ->>
(6) {{ n * (Y + 1) + (X - n) = m }}
X ::= X - n;
(7) {{ n * (Y + 1) + X = m }}
Y ::= Y + 1
(8) {{ n * Y + X = m }}
END
(9) {{ n * Y + X = m /\ X < n }}
Assertions (4), (5), (8), and (9) are derived mechanically from
the invariant and the loop's guard. Assertions (8), (7), and (6)
are derived using the assignment rule going backwards from (8) to
(6). Assertions (4), (3), and (2) are again backwards applications
of the assignment rule.
Now that we've decorated the program it only remains to check that
the two uses of the consequence rule are correct -- i.e., that (1)
implies (2) and that (5) implies (6). This is indeed the case, so
we have a valid decorated program.
*)
(* ####################################################### *)
(** * Finding Loop Invariants *)
(** Once the outermost precondition and postcondition are chosen, the
only creative part in verifying programs with Hoare Logic is
finding the right loop invariants. The reason this is difficult
is the same as the reason that doing inductive mathematical proofs
requires creativity: strengthening the loop invariant (or the
induction hypothesis) means that you have a stronger assumption to
work with when trying to establish the postcondition of the loop
body (complete the induction step of the proof), but it also means
that the loop body postcondition itself is harder to prove!
This section is dedicated to teaching you how to approach the
challenge of finding loop invariants using a series of examples
and exercises. *)
(** ** Example: Slow Subtraction *)
(** The following program subtracts the value of [X] from the value of
[Y] by repeatedly decrementing both [X] and [Y]. We want to verify its
correctness with respect to the following specification:
{{ X = m /\ Y = n }}
WHILE X <> 0 DO
Y ::= Y - 1;
X ::= X - 1
END
{{ Y = n - m }}
To verify this program we need to find an invariant [I] for the
loop. As a first step we can leave [I] as an unknown and build a
_skeleton_ for the proof by applying backward the rules for local
consistency. This process leads to the following skeleton:
(1) {{ X = m /\ Y = n }} ->> (a)
(2) {{ I }}
WHILE X <> 0 DO
(3) {{ I /\ X <> 0 }} ->> (c)
(4) {{ I[X |-> X-1][Y |-> Y-1] }}
Y ::= Y - 1;
(5) {{ I[X |-> X-1] }}
X ::= X - 1
(6) {{ I }}
END
(7) {{ I /\ ~(X <> 0) }} ->> (b)
(8) {{ Y = n - m }}
By examining this skeleton, we can see that any valid [I] will
have to respect three conditions:
- (a) it must be weak enough to be implied by the loop's
precondition, i.e. (1) must imply (2);
- (b) it must be strong enough to imply the loop's postcondition,
i.e. (7) must imply (8);
- (c) it must be preserved by one iteration of the loop, i.e. (3)
must imply (4). *)
(** These conditions are actually independent of the particular
program and specification we are considering. Indeed, every loop
invariant has to satisfy them. One way to find an invariant that
simultaneously satisfies these three conditions is by using an
iterative process: start with a "candidate" invariant (e.g. a
guess or a heuristic choice) and check the three conditions above;
if any of the checks fails, try to use the information that we get
from the failure to produce another (hopefully better) candidate
invariant, and repeat the process.
For instance, in the reduce-to-zero example above, we saw that,
for a very simple loop, choosing [True] as an invariant did the
job. So let's try it again here! I.e., let's instantiate [I] with
[True] in the skeleton above see what we get...
(1) {{ X = m /\ Y = n }} ->> (a - OK)
(2) {{ True }}
WHILE X <> 0 DO
(3) {{ True /\ X <> 0 }} ->> (c - OK)
(4) {{ True }}
Y ::= Y - 1;
(5) {{ True }}
X ::= X - 1
(6) {{ True }}
END
(7) {{ True /\ X = 0 }} ->> (b - WRONG!)
(8) {{ Y = n - m }}
While conditions (a) and (c) are trivially satisfied,
condition (b) is wrong, i.e. it is not the case that (7) [True /\
X = 0] implies (8) [Y = n - m]. In fact, the two assertions are
completely unrelated and it is easy to find a counterexample (say,
[Y = X = m = 0] and [n = 1]).
If we want (b) to hold, we need to strengthen the invariant so
that it implies the postcondition (8). One very simple way to do
this is to let the invariant _be_ the postcondition. So let's
return to our skeleton, instantiate [I] with [Y = n - m], and
check conditions (a) to (c) again.
(1) {{ X = m /\ Y = n }} ->> (a - WRONG!)
(2) {{ Y = n - m }}
WHILE X <> 0 DO
(3) {{ Y = n - m /\ X <> 0 }} ->> (c - WRONG!)
(4) {{ Y - 1 = n - m }}
Y ::= Y - 1;
(5) {{ Y = n - m }}
X ::= X - 1
(6) {{ Y = n - m }}
END
(7) {{ Y = n - m /\ X = 0 }} ->> (b - OK)
(8) {{ Y = n - m }}
This time, condition (b) holds trivially, but (a) and (c) are
broken. Condition (a) requires that (1) [X = m /\ Y = n]
implies (2) [Y = n - m]. If we substitute [X] by [m] we have to
show that [m = n - m] for arbitrary [m] and [n], which does not
hold (for instance, when [m = n = 1]). Condition (c) requires that
[n - m - 1 = n - m], which fails, for instance, for [n = 1] and [m =
0]. So, although [Y = n - m] holds at the end of the loop, it does
not hold from the start, and it doesn't hold on each iteration;
it is not a correct invariant.
This failure is not very surprising: the variable [Y] changes
during the loop, while [m] and [n] are constant, so the assertion
we chose didn't have much chance of being an invariant!
To do better, we need to generalize (8) to some statement that is
equivalent to (8) when [X] is [0], since this will be the case
when the loop terminates, and that "fills the gap" in some
appropriate way when [X] is nonzero. Looking at how the loop
works, we can observe that [X] and [Y] are decremented together
until [X] reaches [0]. So, if [X = 2] and [Y = 5] initially,
after one iteration of the loop we obtain [X = 1] and [Y = 4];
after two iterations [X = 0] and [Y = 3]; and then the loop stops.
Notice that the difference between [Y] and [X] stays constant
between iterations; initially, [Y = n] and [X = m], so this
difference is always [n - m]. So let's try instantiating [I] in
the skeleton above with [Y - X = n - m].
(1) {{ X = m /\ Y = n }} ->> (a - OK)
(2) {{ Y - X = n - m }}
WHILE X <> 0 DO
(3) {{ Y - X = n - m /\ X <> 0 }} ->> (c - OK)
(4) {{ (Y - 1) - (X - 1) = n - m }}
Y ::= Y - 1;
(5) {{ Y - (X - 1) = n - m }}
X ::= X - 1
(6) {{ Y - X = n - m }}
END
(7) {{ Y - X = n - m /\ X = 0 }} ->> (b - OK)
(8) {{ Y = n - m }}
Success! Conditions (a), (b) and (c) all hold now. (To
verify (c), we need to check that, under the assumption that [X <>
0], we have [Y - X = (Y - 1) - (X - 1)]; this holds for all
natural numbers [X] and [Y].) *)
(* ####################################################### *)
(** ** Exercise: Slow Assignment *)
(** **** Exercise: 2 stars (slow_assignment) *)
(** A roundabout way of assigning a number currently stored in [X] to
the variable [Y] is to start [Y] at [0], then decrement [X] until
it hits [0], incrementing [Y] at each step. Here is a program that
implements this idea:
{{ X = m }}
Y ::= 0;
WHILE X <> 0 DO
X ::= X - 1;
Y ::= Y + 1;
END
{{ Y = m }}
Write an informal decorated program showing that this is correct. *)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** ** Exercise: Slow Addition *)
(** **** Exercise: 3 stars, optional (add_slowly_decoration) *)
(** The following program adds the variable X into the variable Z
by repeatedly decrementing X and incrementing Z.
WHILE X <> 0 DO
Z ::= Z + 1;
X ::= X - 1
END
Following the pattern of the [subtract_slowly] example above, pick
a precondition and postcondition that give an appropriate
specification of [add_slowly]; then (informally) decorate the
program accordingly. *)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** ** Example: Parity *)
(** Here is a cute little program for computing the parity of the
value initially stored in [X] (due to Daniel Cristofani).
{{ X = m }}
WHILE 2 <= X DO
X ::= X - 2
END
{{ X = parity m }}
The mathematical [parity] function used in the specification is
defined in Coq as follows: *)
Fixpoint parity x :=
match x with
| 0 => 0
| 1 => 1
| S (S x') => parity x'
end.
(** The postcondition does not hold at the beginning of the loop,
since [m = parity m] does not hold for an arbitrary [m], so we
cannot use that as an invariant. To find an invariant that works,
let's think a bit about what this loop does. On each iteration it
decrements [X] by [2], which preserves the parity of [X]. So the
parity of [X] does not change, i.e. it is invariant. The initial
value of [X] is [m], so the parity of [X] is always equal to the
parity of [m]. Using [parity X = parity m] as an invariant we
obtain the following decorated program:
{{ X = m }} ->> (a - OK)
{{ parity X = parity m }}
WHILE 2 <= X DO
{{ parity X = parity m /\ 2 <= X }} ->> (c - OK)
{{ parity (X-2) = parity m }}
X ::= X - 2
{{ parity X = parity m }}
END
{{ parity X = parity m /\ X < 2 }} ->> (b - OK)
{{ X = parity m }}
With this invariant, conditions (a), (b), and (c) are all
satisfied. For verifying (b), we observe that, when [X < 2], we
have [parity X = X] (we can easily see this in the definition of
[parity]). For verifying (c), we observe that, when [2 <= X], we
have [parity X = parity (X-2)]. *)
(** **** Exercise: 3 stars, optional (parity_formal) *)
(** Translate this proof to Coq. Refer to the reduce-to-zero example
for ideas. You may find the following two lemmas useful: *)
Lemma parity_ge_2 : forall x,
2 <= x ->
parity (x - 2) = parity x.
Proof.
induction x; intro. reflexivity.
destruct x. inversion H. inversion H1.
simpl. rewrite <- minus_n_O. reflexivity.
Qed.
Lemma parity_lt_2 : forall x,
~ 2 <= x ->
parity (x) = x.
Proof.
intros. induction x. reflexivity. destruct x. reflexivity.
apply ex_falso_quodlibet. apply H. omega.
Qed.
Theorem parity_correct : forall m,
{{ fun st => st X = m }}
WHILE BLe (ANum 2) (AId X) DO
X ::= AMinus (AId X) (ANum 2)
END
{{ fun st => st X = parity m }}.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ####################################################### *)
(** ** Example: Finding Square Roots *)
(** The following program computes the square root of [X]
by naive iteration:
{{ X=m }}
Z ::= 0;
WHILE (Z+1)*(Z+1) <= X DO
Z ::= Z+1
END
{{ Z*Z<=m /\ m<(Z+1)*(Z+1) }}
*)
(** As above, we can try to use the postcondition as a candidate
invariant, obtaining the following decorated program:
(1) {{ X=m }} ->> (a - second conjunct of (2) WRONG!)
(2) {{ 0*0 <= m /\ m<1*1 }}
Z ::= 0;
(3) {{ Z*Z <= m /\ m<(Z+1)*(Z+1) }}
WHILE (Z+1)*(Z+1) <= X DO
(4) {{ Z*Z<=m /\ (Z+1)*(Z+1)<=X }} ->> (c - WRONG!)
(5) {{ (Z+1)*(Z+1)<=m /\ m<(Z+2)*(Z+2) }}
Z ::= Z+1
(6) {{ Z*Z<=m /\ m<(Z+1)*(Z+1) }}
END
(7) {{ Z*Z<=m /\ m<(Z+1)*(Z+1) /\ X<(Z+1)*(Z+1) }} ->> (b - OK)
(8) {{ Z*Z<=m /\ m<(Z+1)*(Z+1) }}
This didn't work very well: both conditions (a) and (c) failed.
Looking at condition (c), we see that the second conjunct of (4)
is almost the same as the first conjunct of (5), except that (4)
mentions [X] while (5) mentions [m]. But note that [X] is never
assigned in this program, so we should have [X=m], but we didn't
propagate this information from (1) into the loop invariant.
Also, looking at the second conjunct of (8), it seems quite
hopeless as an invariant -- and we don't even need it, since we
can obtain it from the negation of the guard (third conjunct
in (7)), again under the assumption that [X=m].
So we now try [X=m /\ Z*Z <= m] as the loop invariant:
{{ X=m }} ->> (a - OK)
{{ X=m /\ 0*0 <= m }}
Z ::= 0;
{{ X=m /\ Z*Z <= m }}
WHILE (Z+1)*(Z+1) <= X DO
{{ X=m /\ Z*Z<=m /\ (Z+1)*(Z+1)<=X }} ->> (c - OK)
{{ X=m /\ (Z+1)*(Z+1)<=m }}
Z ::= Z+1
{{ X=m /\ Z*Z<=m }}
END
{{ X=m /\ Z*Z<=m /\ X<(Z+1)*(Z+1) }} ->> (b - OK)
{{ Z*Z<=m /\ m<(Z+1)*(Z+1) }}
This works, since conditions (a), (b), and (c) are now all
trivially satisfied.
Very often, if a variable is used in a loop in a read-only
fashion (i.e., it is referred to by the program or by the
specification and it is not changed by the loop) it is necessary
to add the fact that it doesn't change to the loop invariant. *)
(* ####################################################### *)
(** ** Example: Squaring *)
(** Here is a program that squares [X] by repeated addition:
{{ X = m }}
Y ::= 0;
Z ::= 0;
WHILE Y <> X DO
Z ::= Z + X;
Y ::= Y + 1
END
{{ Z = m*m }}
*)
(** The first thing to note is that the loop reads [X] but doesn't
change its value. As we saw in the previous example, in such cases
it is a good idea to add [X = m] to the invariant. The other thing
we often use in the invariant is the postcondition, so let's add
that too, leading to the invariant candidate [Z = m * m /\ X = m].
{{ X = m }} ->> (a - WRONG)
{{ 0 = m*m /\ X = m }}
Y ::= 0;
{{ 0 = m*m /\ X = m }}
Z ::= 0;
{{ Z = m*m /\ X = m }}
WHILE Y <> X DO
{{ Z = Y*m /\ X = m /\ Y <> X }} ->> (c - WRONG)
{{ Z+X = m*m /\ X = m }}
Z ::= Z + X;
{{ Z = m*m /\ X = m }}
Y ::= Y + 1
{{ Z = m*m /\ X = m }}
END
{{ Z = m*m /\ X = m /\ Y = X }} ->> (b - OK)
{{ Z = m*m }}
Conditions (a) and (c) fail because of the [Z = m*m] part. While
[Z] starts at [0] and works itself up to [m*m], we can't expect
[Z] to be [m*m] from the start. If we look at how [Z] progesses
in the loop, after the 1st iteration [Z = m], after the 2nd
iteration [Z = 2*m], and at the end [Z = m*m]. Since the variable
[Y] tracks how many times we go through the loop, we derive the
new invariant candidate [Z = Y*m /\ X = m].
{{ X = m }} ->> (a - OK)
{{ 0 = 0*m /\ X = m }}
Y ::= 0;
{{ 0 = Y*m /\ X = m }}
Z ::= 0;
{{ Z = Y*m /\ X = m }}
WHILE Y <> X DO
{{ Z = Y*m /\ X = m /\ Y <> X }} ->> (c - OK)
{{ Z+X = (Y+1)*m /\ X = m }}
Z ::= Z + X;
{{ Z = (Y+1)*m /\ X = m }}
Y ::= Y + 1
{{ Z = Y*m /\ X = m }}
END
{{ Z = Y*m /\ X = m /\ Y = X }} ->> (b - OK)
{{ Z = m*m }}
This new invariant makes the proof go through: all three
conditions are easy to check.
It is worth comparing the postcondition [Z = m*m] and the [Z =
Y*m] conjunct of the invariant. It is often the case that one has
to replace auxiliary variabes (parameters) with variables -- or
with expressions involving both variables and parameters (like
[m - Y]) -- when going from postconditions to invariants. *)
(* ####################################################### *)
(** ** Exercise: Factorial *)
(** **** Exercise: 3 stars (factorial) *)
(** Recall that [n!] denotes the factorial of [n] (i.e. [n! =
1*2*...*n]). Here is an Imp program that calculates the factorial
of the number initially stored in the variable [X] and puts it in
the variable [Y]:
{{ X = m }} ;
Y ::= 1
WHILE X <> 0
DO
Y ::= Y * X
X ::= X - 1
END
{{ Y = m! }}
Fill in the blanks in following decorated program:
{{ X = m }} ->>
{{ }}
Y ::= 1;
{{ }}
WHILE X <> 0
DO {{ }} ->>
{{ }}
Y ::= Y * X;
{{ }}
X ::= X - 1
{{ }}
END
{{ }} ->>
{{ Y = m! }}
*)
(** [] *)
(* ####################################################### *)
(** ** Exercise: Min *)
(** **** Exercise: 3 stars (Min_Hoare) *)
(** Fill in valid decorations for the following program.
For the => steps in your annotations, you may rely (silently) on the
following facts about min
Lemma lemma1 : forall x y,
(x=0 \/ y=0) -> min x y = 0.
Lemma lemma2 : forall x y,
min (x-1) (y-1) = (min x y) - 1.
plus, as usual, standard high-school algebra.
{{ True }} ->>
{{ }}
X ::= a;
{{ }}
Y ::= b;
{{ }}
Z ::= 0;
{{ }}
WHILE (X <> 0 /\ Y <> 0) DO
{{ }} ->>
{{ }}
X := X - 1;
{{ }}
Y := Y - 1;
{{ }}
Z := Z + 1;
{{ }}
END
{{ }} ->>
{{ Z = min a b }}
*)
(** **** Exercise: 3 stars (two_loops) *)
(** Here is a very inefficient way of adding 3 numbers:
X ::= 0;
Y ::= 0;
Z ::= c;
WHILE X <> a DO
X ::= X + 1;
Z ::= Z + 1
END;
WHILE Y <> b DO
Y ::= Y + 1;
Z ::= Z + 1
END
Show that it does what it should by filling in the blanks in the
following decorated program.
{{ True }} ->>
{{ }}
X ::= 0;
{{ }}
Y ::= 0;
{{ }}
Z ::= c;
{{ }}
WHILE X <> a DO
{{ }} ->>
{{ }}
X ::= X + 1;
{{ }}
Z ::= Z + 1
{{ }}
END;
{{ }} ->>
{{ }}
WHILE Y <> b DO
{{ }} ->>
{{ }}
Y ::= Y + 1;
{{ }}
Z ::= Z + 1
{{ }}
END
{{ }} ->>
{{ Z = a + b + c }}
*)
(* ####################################################### *)
(** ** Exercise: Power Series *)
(** **** Exercise: 4 stars, optional (dpow2_down) *)
(** Here is a program that computes the series:
[1 + 2 + 2^2 + ... + 2^m = 2^(m+1) - 1]
X ::= 0;
Y ::= 1;
Z ::= 1;
WHILE X <> m DO
Z ::= 2 * Z;
Y ::= Y + Z;
X ::= X + 1;
END
Write a decorated program for this. *)
(* FILL IN HERE *)
(* ####################################################### *)
(** * Weakest Preconditions (Advanced) *)
(** Some Hoare triples are more interesting than others.
For example,
{{ False }} X ::= Y + 1 {{ X <= 5 }}
is _not_ very interesting: although it is perfectly valid, it
tells us nothing useful. Since the precondition isn't satisfied
by any state, it doesn't describe any situations where we can use
the command [X ::= Y + 1] to achieve the postcondition [X <= 5].
By contrast,
{{ Y <= 4 /\ Z = 0 }} X ::= Y + 1 {{ X <= 5 }}
is useful: it tells us that, if we can somehow create a situation
in which we know that [Y <= 4 /\ Z = 0], then running this command
will produce a state satisfying the postcondition. However, this
triple is still not as useful as it could be, because the [Z = 0]
clause in the precondition actually has nothing to do with the
postcondition [X <= 5]. The _most_ useful triple (for a given
command and postcondition) is this one:
{{ Y <= 4 }} X ::= Y + 1 {{ X <= 5 }}
In other words, [Y <= 4] is the _weakest_ valid precondition of
the command [X ::= Y + 1] for the postcondition [X <= 5]. *)
(** In general, we say that "[P] is the weakest precondition of
command [c] for postcondition [Q]" if [{{P}} c {{Q}}] and if,
whenever [P'] is an assertion such that [{{P'}} c {{Q}}], we have
[P' st] implies [P st] for all states [st]. *)
Definition is_wp P c Q :=
{{P}} c {{Q}} /\
forall P', {{P'}} c {{Q}} -> (P' ->> P).
(** That is, [P] is the weakest precondition of [c] for [Q]
if (a) [P] _is_ a precondition for [Q] and [c], and (b) [P] is the
_weakest_ (easiest to satisfy) assertion that guarantees [Q] after
executing [c]. *)
(** **** Exercise: 1 star, optional (wp) *)
(** What are the weakest preconditions of the following commands
for the following postconditions?
1) {{ ? }} SKIP {{ X = 5 }}
2) {{ ? }} X ::= Y + Z {{ X = 5 }}
3) {{ ? }} X ::= Y {{ X = Y }}
4) {{ ? }}
IFB X == 0 THEN Y ::= Z + 1 ELSE Y ::= W + 2 FI
{{ Y = 5 }}
5) {{ ? }}
X ::= 5
{{ X = 0 }}
6) {{ ? }}
WHILE True DO X ::= 0 END
{{ X = 0 }}
*)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, advanced, optional (is_wp_formal) *)
(** Prove formally using the definition of [hoare_triple] that [Y <= 4]
is indeed the weakest precondition of [X ::= Y + 1] with respect to
postcondition [X <= 5]. *)
Theorem is_wp_example :
is_wp (fun st => st Y <= 4)
(X ::= APlus (AId Y) (ANum 1)) (fun st => st X <= 5).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, advanced (hoare_asgn_weakest) *)
(** Show that the precondition in the rule [hoare_asgn] is in fact the
weakest precondition. *)
Theorem hoare_asgn_weakest : forall Q X a,
is_wp (Q [X |-> a]) (X ::= a) Q.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, advanced, optional (hoare_havoc_weakest) *)
(** Show that your [havoc_pre] rule from the [himp_hoare] exercise
in the [Hoare] chapter returns the weakest precondition. *)
Module Himp2.
Import Himp.
Lemma hoare_havoc_weakest : forall (P Q : Assertion) (X : id),
{{ P }} HAVOC X {{ Q }} ->
P ->> havoc_pre X Q.
Proof.
(* FILL IN HERE *) Admitted.
End Himp2.
(** [] *)
(* ####################################################### *)
(** * Formal Decorated Programs (Advanced) *)
(** The informal conventions for decorated programs amount to a way of
displaying Hoare triples in which commands are annotated with
enough embedded assertions that checking the validity of the
triple is reduced to simple logical and algebraic calculations
showing that some assertions imply others. In this section, we
show that this informal presentation style can actually be made
completely formal and indeed that checking the validity of
decorated programs can mostly be automated. *)
(** ** Syntax *)
(** The first thing we need to do is to formalize a variant of the
syntax of commands with embedded assertions. We call the new
commands _decorated commands_, or [dcom]s. *)
Inductive dcom : Type :=
| DCSkip : Assertion -> dcom
| DCSeq : dcom -> dcom -> dcom
| DCAsgn : id -> aexp -> Assertion -> dcom
| DCIf : bexp -> Assertion -> dcom -> Assertion -> dcom
-> Assertion-> dcom
| DCWhile : bexp -> Assertion -> dcom -> Assertion -> dcom
| DCPre : Assertion -> dcom -> dcom
| DCPost : dcom -> Assertion -> dcom.
Tactic Notation "dcom_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "Skip" | Case_aux c "Seq" | Case_aux c "Asgn"
| Case_aux c "If" | Case_aux c "While"
| Case_aux c "Pre" | Case_aux c "Post" ].
Notation "'SKIP' {{ P }}"
:= (DCSkip P)
(at level 10) : dcom_scope.
Notation "l '::=' a {{ P }}"
:= (DCAsgn l a P)
(at level 60, a at next level) : dcom_scope.
Notation "'WHILE' b 'DO' {{ Pbody }} d 'END' {{ Ppost }}"
:= (DCWhile b Pbody d Ppost)
(at level 80, right associativity) : dcom_scope.
Notation "'IFB' b 'THEN' {{ P }} d 'ELSE' {{ P' }} d' 'FI' {{ Q }}"
:= (DCIf b P d P' d' Q)
(at level 80, right associativity) : dcom_scope.
Notation "'->>' {{ P }} d"
:= (DCPre P d)
(at level 90, right associativity) : dcom_scope.
Notation "{{ P }} d"
:= (DCPre P d)
(at level 90) : dcom_scope.
Notation "d '->>' {{ P }}"
:= (DCPost d P)
(at level 80, right associativity) : dcom_scope.
Notation " d ;; d' "
:= (DCSeq d d')
(at level 80, right associativity) : dcom_scope.
Delimit Scope dcom_scope with dcom.
(** To avoid clashing with the existing [Notation] definitions
for ordinary [com]mands, we introduce these notations in a special
scope called [dcom_scope], and we wrap examples with the
declaration [% dcom] to signal that we want the notations to be
interpreted in this scope.
Careful readers will note that we've defined two notations for the
[DCPre] constructor, one with and one without a [->>]. The
"without" version is intended to be used to supply the initial
precondition at the very top of the program. *)
Example dec_while : dcom := (
{{ fun st => True }}
WHILE (BNot (BEq (AId X) (ANum 0)))
DO
{{ fun st => True /\ st X <> 0}}
X ::= (AMinus (AId X) (ANum 1))
{{ fun _ => True }}
END
{{ fun st => True /\ st X = 0}} ->>
{{ fun st => st X = 0 }}
) % dcom.
(** It is easy to go from a [dcom] to a [com] by erasing all
annotations. *)
Fixpoint extract (d:dcom) : com :=
match d with
| DCSkip _ => SKIP
| DCSeq d1 d2 => (extract d1 ;; extract d2)
| DCAsgn X a _ => X ::= a
| DCIf b _ d1 _ d2 _ => IFB b THEN extract d1 ELSE extract d2 FI
| DCWhile b _ d _ => WHILE b DO extract d END
| DCPre _ d => extract d
| DCPost d _ => extract d
end.
(** The choice of exactly where to put assertions in the definition of
[dcom] is a bit subtle. The simplest thing to do would be to
annotate every [dcom] with a precondition and postcondition. But
this would result in very verbose programs with a lot of repeated
annotations: for example, a program like [SKIP;SKIP] would have to
be annotated as
{{P}} ({{P}} SKIP {{P}}) ;; ({{P}} SKIP {{P}}) {{P}},
with pre- and post-conditions on each [SKIP], plus identical pre-
and post-conditions on the semicolon!
Instead, the rule we've followed is this:
- The _post_-condition expected by each [dcom] [d] is embedded in [d]
- The _pre_-condition is supplied by the context. *)
(** In other words, the invariant of the representation is that a
[dcom] [d] together with a precondition [P] determines a Hoare
triple [{{P}} (extract d) {{post d}}], where [post] is defined as
follows: *)
Fixpoint post (d:dcom) : Assertion :=
match d with
| DCSkip P => P
| DCSeq d1 d2 => post d2
| DCAsgn X a Q => Q
| DCIf _ _ d1 _ d2 Q => Q
| DCWhile b Pbody c Ppost => Ppost
| DCPre _ d => post d
| DCPost c Q => Q
end.
(** Similarly, we can extract the "initial precondition" from a
decorated program. *)
Fixpoint pre (d:dcom) : Assertion :=
match d with
| DCSkip P => fun st => True
| DCSeq c1 c2 => pre c1
| DCAsgn X a Q => fun st => True
| DCIf _ _ t _ e _ => fun st => True
| DCWhile b Pbody c Ppost => fun st => True
| DCPre P c => P
| DCPost c Q => pre c
end.
(** This function is not doing anything sophisticated like calculating
a weakest precondition; it just recursively searches for an
explicit annotation at the very beginning of the program,
returning default answers for programs that lack an explicit
precondition (like a bare assignment or [SKIP]). *)
(** Using [pre] and [post], and assuming that we adopt the convention
of always supplying an explicit precondition annotation at the
very beginning of our decorated programs, we can express what it
means for a decorated program to be correct as follows: *)
Definition dec_correct (d:dcom) :=
{{pre d}} (extract d) {{post d}}.
(** To check whether this Hoare triple is _valid_, we need a way to
extract the "proof obligations" from a decorated program. These
obligations are often called _verification conditions_, because
they are the facts that must be verified to see that the
decorations are logically consistent and thus add up to a complete
proof of correctness. *)
(** ** Extracting Verification Conditions *)
(** The function [verification_conditions] takes a [dcom] [d] together
with a precondition [P] and returns a _proposition_ that, if it
can be proved, implies that the triple [{{P}} (extract d) {{post d}}]
is valid. *)
(** It does this by walking over [d] and generating a big
conjunction including all the "local checks" that we listed when
we described the informal rules for decorated programs. (Strictly
speaking, we need to massage the informal rules a little bit to
add some uses of the rule of consequence, but the correspondence
should be clear.) *)
Fixpoint verification_conditions (P : Assertion) (d:dcom) : Prop :=
match d with
| DCSkip Q =>
(P ->> Q)
| DCSeq d1 d2 =>
verification_conditions P d1
/\ verification_conditions (post d1) d2
| DCAsgn X a Q =>
(P ->> Q [X |-> a])
| DCIf b P1 d1 P2 d2 Q =>
((fun st => P st /\ bassn b st) ->> P1)
/\ ((fun st => P st /\ ~ (bassn b st)) ->> P2)
/\ (Q <<->> post d1) /\ (Q <<->> post d2)
/\ verification_conditions P1 d1
/\ verification_conditions P2 d2
| DCWhile b Pbody d Ppost =>
(* post d is the loop invariant and the initial precondition *)
(P ->> post d)
/\ (Pbody <<->> (fun st => post d st /\ bassn b st))
/\ (Ppost <<->> (fun st => post d st /\ ~(bassn b st)))
/\ verification_conditions Pbody d
| DCPre P' d =>
(P ->> P') /\ verification_conditions P' d
| DCPost d Q =>
verification_conditions P d /\ (post d ->> Q)
end.
(** And now, the key theorem, which states that
[verification_conditions] does its job correctly. Not
surprisingly, we need to use each of the Hoare Logic rules at some
point in the proof. *)
(** We have used _in_ variants of several tactics before to
apply them to values in the context rather than the goal. An
extension of this idea is the syntax [tactic in *], which applies
[tactic] in the goal and every hypothesis in the context. We most
commonly use this facility in conjunction with the [simpl] tactic,
as below. *)
Theorem verification_correct : forall d P,
verification_conditions P d -> {{P}} (extract d) {{post d}}.
Proof.
dcom_cases (induction d) Case; intros P H; simpl in *.
Case "Skip".
eapply hoare_consequence_pre.
apply hoare_skip.
assumption.
Case "Seq".
inversion H as [H1 H2]. clear H.
eapply hoare_seq.
apply IHd2. apply H2.
apply IHd1. apply H1.
Case "Asgn".
eapply hoare_consequence_pre.
apply hoare_asgn.
assumption.
Case "If".
inversion H as [HPre1 [HPre2 [[Hd11 Hd12]
[[Hd21 Hd22] [HThen HElse]]]]].
clear H.
apply IHd1 in HThen. clear IHd1.
apply IHd2 in HElse. clear IHd2.
apply hoare_if.
eapply hoare_consequence_pre; eauto.
eapply hoare_consequence_post; eauto.
eapply hoare_consequence_pre; eauto.
eapply hoare_consequence_post; eauto.
Case "While".
inversion H as [Hpre [[Hbody1 Hbody2] [[Hpost1 Hpost2] Hd]]];
subst; clear H.
eapply hoare_consequence_pre; eauto.
eapply hoare_consequence_post; eauto.
apply hoare_while.
eapply hoare_consequence_pre; eauto.
Case "Pre".
inversion H as [HP Hd]; clear H.
eapply hoare_consequence_pre. apply IHd. apply Hd. assumption.
Case "Post".
inversion H as [Hd HQ]; clear H.
eapply hoare_consequence_post. apply IHd. apply Hd. assumption.
Qed.
(** ** Examples *)
(** The propositions generated by [verification_conditions] are fairly
big, and they contain many conjuncts that are essentially trivial. *)
Eval simpl in (verification_conditions (fun st => True) dec_while).
(**
==>
(((fun _ : state => True) ->> (fun _ : state => True)) /\
((fun _ : state => True) ->> (fun _ : state => True)) /\
(fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st) =
(fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st) /\
(fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st) =
(fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st) /\
(fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st) ->>
(fun _ : state => True) [X |-> AMinus (AId X) (ANum 1)]) /\
(fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st) ->>
(fun st : state => st X = 0)
*)
(** In principle, we could certainly work with them using just the
tactics we have so far, but we can make things much smoother with
a bit of automation. We first define a custom [verify] tactic
that applies splitting repeatedly to turn all the conjunctions
into separate subgoals and then uses [omega] and [eauto] (a handy
general-purpose automation tactic that we'll discuss in detail
later) to deal with as many of them as possible. *)
Lemma ble_nat_true_iff : forall n m : nat,
ble_nat n m = true <-> n <= m.
Proof.
intros n m. split. apply ble_nat_true.
generalize dependent m. induction n; intros m H. reflexivity.
simpl. destruct m. inversion H.
apply le_S_n in H. apply IHn. assumption.
Qed.
Lemma ble_nat_false_iff : forall n m : nat,
ble_nat n m = false <-> ~(n <= m).
Proof.
intros n m. split. apply ble_nat_false.
generalize dependent m. induction n; intros m H.
apply ex_falso_quodlibet. apply H. apply le_0_n.
simpl. destruct m. reflexivity.
apply IHn. intro Hc. apply H. apply le_n_S. assumption.
Qed.
Tactic Notation "verify" :=
apply verification_correct;
repeat split;
simpl; unfold assert_implies;
unfold bassn in *; unfold beval in *; unfold aeval in *;
unfold assn_sub; intros;
repeat rewrite update_eq;
repeat (rewrite update_neq; [| (intro X; inversion X)]);
simpl in *;
repeat match goal with [H : _ /\ _ |- _] => destruct H end;
repeat rewrite not_true_iff_false in *;
repeat rewrite not_false_iff_true in *;
repeat rewrite negb_true_iff in *;
repeat rewrite negb_false_iff in *;
repeat rewrite beq_nat_true_iff in *;
repeat rewrite beq_nat_false_iff in *;
repeat rewrite ble_nat_true_iff in *;
repeat rewrite ble_nat_false_iff in *;
try subst;
repeat
match goal with
[st : state |- _] =>
match goal with
[H : st _ = _ |- _] => rewrite -> H in *; clear H
| [H : _ = st _ |- _] => rewrite <- H in *; clear H
end
end;
try eauto; try omega.
(** What's left after [verify] does its thing is "just the interesting
parts" of checking that the decorations are correct. For very
simple examples [verify] immediately solves the goal (provided
that the annotations are correct). *)
Theorem dec_while_correct :
dec_correct dec_while.
Proof. verify. Qed.
(** Another example (formalizing a decorated program we've seen
before): *)
Example subtract_slowly_dec (m:nat) (p:nat) : dcom := (
{{ fun st => st X = m /\ st Z = p }} ->>
{{ fun st => st Z - st X = p - m }}
WHILE BNot (BEq (AId X) (ANum 0))
DO {{ fun st => st Z - st X = p - m /\ st X <> 0 }} ->>
{{ fun st => (st Z - 1) - (st X - 1) = p - m }}
Z ::= AMinus (AId Z) (ANum 1)
{{ fun st => st Z - (st X - 1) = p - m }} ;;
X ::= AMinus (AId X) (ANum 1)
{{ fun st => st Z - st X = p - m }}
END
{{ fun st => st Z - st X = p - m /\ st X = 0 }} ->>
{{ fun st => st Z = p - m }}
) % dcom.
Theorem subtract_slowly_dec_correct : forall m p,
dec_correct (subtract_slowly_dec m p).
Proof. intros m p. verify. (* this grinds for a bit! *) Qed.
(** **** Exercise: 3 stars, advanced (slow_assignment_dec) *)
(** In the [slow_assignment] exercise above, we saw a roundabout way
of assigning a number currently stored in [X] to the variable [Y]:
start [Y] at [0], then decrement [X] until it hits [0],
incrementing [Y] at each step.
Write a _formal_ version of this decorated program and prove it
correct. *)
Example slow_assignment_dec (m:nat) : dcom :=
(* FILL IN HERE *) admit.
Theorem slow_assignment_dec_correct : forall m,
dec_correct (slow_assignment_dec m).
Proof. (* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, advanced (factorial_dec) *)
(** Remember the factorial function we worked with before: *)
Fixpoint real_fact (n:nat) : nat :=
match n with
| O => 1
| S n' => n * (real_fact n')
end.
(** Following the pattern of [subtract_slowly_dec], write a decorated
program that implements the factorial function and prove it
correct. *)
(* FILL IN HERE *)
(** [] *)
(* $Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
|
// // (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Work-group limiter. This module has two interface points: the entry point
// and the exit point. The purpose of the module is to ensure that there are
// no more than WG_LIMIT work-groups in the pipeline between the entry and
// exit points. The limiter also remaps the kernel-level work-group id into
// a local work-group id; this is needed because in general the kernel-level
// work-group id space is larger than the local work-group id space. It is
// assumed that any work-item that passes through the entry point will pass
// through the exit point at some point.
//
// The ordering of the work-groups affects the implementation. In particular,
// if the work-group order is the same through the entry point and the exit
// point, the implementation is simple. This is referred to as work-group FIFO
// (first-in-first-out) order. It remains a TODO to support work-group
// non-FIFO order (through the exit point).
//
// The work-group order does NOT matter if WG_LIMIT >= KERNEL_WG_LIMIT.
// In this configuration, the real limiter is at the kernel-level and this
// work-group limiter does not do anything useful. It does match the latency
// specifiction though so that the latency and capacity of the core is the
// same regardless of the configuration.
//
// Latency/capacity:
// Through entry: 1 cycle
// Through exit: 1 cycle
module acl_work_group_limiter #(
parameter unsigned WG_LIMIT = 1, // >0
parameter unsigned KERNEL_WG_LIMIT = 1, // >0
parameter unsigned MAX_WG_SIZE = 1, // >0
parameter unsigned WG_FIFO_ORDER = 1, // 0|1
parameter string IMPL = "local" // kernel|local
)
(
clock,
resetn,
wg_size,
// Limiter entry
entry_valid_in,
entry_k_wgid,
entry_stall_out,
entry_valid_out,
entry_l_wgid,
entry_stall_in,
// Limiter exit
exit_valid_in,
exit_l_wgid,
exit_stall_out,
exit_valid_out,
exit_stall_in
);
input logic clock;
input logic resetn;
// check for overflow
localparam MAX_WG_SIZE_WIDTH = $clog2({1'b0, MAX_WG_SIZE} + 1);
input logic [MAX_WG_SIZE_WIDTH-1:0] wg_size;
// Limiter entry
input logic entry_valid_in;
input logic [$clog2(KERNEL_WG_LIMIT)-1:0] entry_k_wgid; // not used if WG_FIFO_ORDER==1
output logic entry_stall_out;
output logic entry_valid_out;
output logic [$clog2(WG_LIMIT)-1:0] entry_l_wgid;
input logic entry_stall_in;
// Limiter exit
input logic exit_valid_in;
input logic [$clog2(WG_LIMIT)-1:0] exit_l_wgid; // never used
output logic exit_stall_out;
output logic exit_valid_out;
input logic exit_stall_in;
generate
// WG_FIFO_ORDER needs to be handled first because the limiter always needs
// to generate the work-group
if( WG_FIFO_ORDER == 1 ) begin
// IMPLEMENTATION ASSUMPTION: complete work-groups are assumed to
// pass-through work-group and therefore it is sufficient to declare
// a work-group as done when wg_size work-items have appeared at one point
logic [MAX_WG_SIZE_WIDTH-1:0] wg_size_limit /* synthesis preserve */;
always @(posedge clock)
wg_size_limit <= wg_size - 'd1; // this is a constant throughout the execution of an kernel, but register to limit fanout of source
// Number of active work-groups that have (partially) entered the limiter and have not
// (completely) exited the limiter. Counts from 0 to WG_LIMIT.
logic [$clog2(WG_LIMIT+1)-1:0] active_wg_count;
logic incr_active_wg, decr_active_wg;
logic active_wg_limit_reached;
// Number of work-items seen in the currently-entering work-group.
// Counts from 0 to MAX_WG_SIZE-1.
logic [$clog2(MAX_WG_SIZE)-1:0] cur_entry_wg_wi_count;
logic cur_entry_wg_wi_count_eq_zero;
logic [$clog2(WG_LIMIT)-1:0] cur_entry_l_wgid;
// Number of work-items seen in the currently-exiting work-group.
// Counts from 0 to MAX_WG_SIZE-1.
logic [$clog2(MAX_WG_SIZE)-1:0] cur_exit_wg_wi_count;
always @( posedge clock or negedge resetn ) begin
if( ~resetn ) begin
active_wg_count <= '0;
active_wg_limit_reached <= 1'b0;
end
else begin
active_wg_count <= active_wg_count + incr_active_wg - decr_active_wg;
if( (active_wg_count == WG_LIMIT - 1) & incr_active_wg & ~decr_active_wg )
active_wg_limit_reached <= 1'b1;
else if( (active_wg_count == WG_LIMIT) & decr_active_wg )
active_wg_limit_reached <= 1'b0;
end
end
//
// Entry logic: latency = 1
//
logic accept_entry;
logic entry_output_stall_out;
always @( posedge clock or negedge resetn ) begin
if( ~resetn ) begin
cur_entry_wg_wi_count <= '0;
cur_entry_wg_wi_count_eq_zero <= 1'b1;
cur_entry_l_wgid <= '0;
end
else if( accept_entry ) begin
if( cur_entry_wg_wi_count == wg_size_limit ) begin
// The entering work-item is the last work-item of the current
// work-group. Prepare for the next work-group.
cur_entry_wg_wi_count <= '0;
cur_entry_wg_wi_count_eq_zero <= 1'b1;
if( cur_entry_l_wgid == WG_LIMIT - 1 )
cur_entry_l_wgid <= '0;
else
cur_entry_l_wgid <= cur_entry_l_wgid + 'd1;
end
else begin
// Increment work-item counter.
cur_entry_wg_wi_count <= cur_entry_wg_wi_count + 'd1;
cur_entry_wg_wi_count_eq_zero <= 1'b0;
end
end
end
assign incr_active_wg = cur_entry_wg_wi_count_eq_zero & accept_entry;
assign accept_entry = entry_valid_in & ~entry_output_stall_out & ~(active_wg_limit_reached & cur_entry_wg_wi_count_eq_zero);
// Register entry output.
always @( posedge clock or negedge resetn ) begin
if( ~resetn ) begin
entry_valid_out <= 1'b0;
entry_l_wgid <= 'x;
end
else if( ~entry_output_stall_out ) begin
entry_valid_out <= accept_entry;
entry_l_wgid <= cur_entry_l_wgid;
end
end
assign entry_output_stall_out = entry_valid_out & entry_stall_in;
assign entry_stall_out = entry_valid_in & ~accept_entry;
//
// Exit logic: latency = 1
//
always @( posedge clock or negedge resetn ) begin
if( ~resetn ) begin
cur_exit_wg_wi_count <= '0;
end
else if( exit_valid_in & ~exit_stall_out ) begin
if( cur_exit_wg_wi_count == wg_size_limit )
begin
// The exiting work-item is the last work-item of the current
// work-group. Entire work-group has cleared.
cur_exit_wg_wi_count <= '0;
end
else begin
// Increment work-item counter.
cur_exit_wg_wi_count <= cur_exit_wg_wi_count + 'd1;
end
end
end
assign decr_active_wg = exit_valid_in & ~exit_stall_out & (cur_exit_wg_wi_count == wg_size_limit);
// Register output.
always @( posedge clock or negedge resetn ) begin
if( ~resetn )
exit_valid_out <= 1'b0;
else if( ~exit_stall_out )
exit_valid_out <= exit_valid_in;
end
assign exit_stall_out = exit_valid_out & exit_stall_in;
end
else if( IMPL == "local" && WG_LIMIT >= KERNEL_WG_LIMIT ) begin
// In this scenario, this work-group limiter doesn't have to do anything
// because the kernel-level limit is already sufficient.
//
// Simply use the kernel hwid as the local hwid.
//
// This particular implementation is suitable for any kind of
// work-item ordering at entry and exit. Register to meet the latency
// requirements.
always @( posedge clock or negedge resetn ) begin
if( ~resetn ) begin
entry_valid_out <= 1'b0;
entry_l_wgid <= 'x;
end
else if( ~entry_stall_out ) begin
entry_valid_out <= entry_valid_in;
entry_l_wgid <= entry_k_wgid;
end
end
assign entry_stall_out = entry_valid_out & entry_stall_in;
always @( posedge clock or negedge resetn ) begin
if( ~resetn )
exit_valid_out <= 1'b0;
else if( ~exit_stall_out )
exit_valid_out <= exit_valid_in;
end
assign exit_stall_out = exit_valid_out & exit_stall_in;
end
else begin
// synthesis translate off
initial
$fatal("%m: unsupported configuration (WG_LIMIT < KERNEL_WG_LIMIT and WG_FIFO_ORDER != 1)");
// synthesis translate on
end
endgenerate
endmodule
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: icblbc_ram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.0 Build 156 04/24/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module icblbc_ram (
address,
clock,
data,
wren,
q);
input [10:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 11,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL icblbc_ram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL icblbc_ram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL icblbc_ram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL icblbc_ram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL icblbc_ram_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL icblbc_ram_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module i2c #(
parameter BASEADDR = 16'h0000,
parameter HIGHADDR = 16'h0000,
parameter ABUSWIDTH = 16,
parameter MEM_BYTES = 1,
parameter IGNORE_ACK = 0
) (
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
input wire I2C_CLK,
inout wire I2C_SDA,
inout wire I2C_SCL
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #(
.BASEADDR(BASEADDR),
.HIGHADDR(HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_bus_to_ip (
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
i2c_core #(
.ABUSWIDTH(ABUSWIDTH),
.MEM_BYTES(MEM_BYTES),
.IGNORE_ACK(IGNORE_ACK)
) i_i2c_core (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.I2C_CLK(I2C_CLK),
.I2C_SDA(I2C_SDA),
.I2C_SCL(I2C_SCL)
);
endmodule
|
`timescale 1ns/10ps
module vga_pll_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(2),
.output_clock_frequency0("65.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("130.000000 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
/***********************************************************
-- (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). A Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
//
//
// Owner: Gary Martin
// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/byte_lane.v#4 $
// $Author: gary $
// $DateTime: 2010/05/11 18:05:17 $
// $Change: 490882 $
// Description:
// This verilog file is a parameterizable single 10 or 12 bit byte lane.
//
// History:
// Date Engineer Description
// 04/01/2010 G. Martin Initial Checkin.
//
////////////////////////////////////////////////////////////
***********************************************************/
`timescale 1ps/1ps
//`include "phy.vh"
module mig_7series_v2_3_ddr_byte_lane #(
// these are used to scale the index into phaser,calib,scan,mc vectors
// to access fields used in this instance
parameter ABCD = "A", // A,B,C, or D
parameter PO_DATA_CTL = "FALSE",
parameter BITLANES = 12'b1111_1111_1111,
parameter BITLANES_OUTONLY = 12'b1111_1111_1111,
parameter BYTELANES_DDR_CK = 24'b0010_0010_0010_0010_0010_0010,
parameter RCLK_SELECT_LANE = "B",
parameter PC_CLK_RATIO = 4,
parameter USE_PRE_POST_FIFO = "FALSE",
//OUT_FIFO
parameter OF_ALMOST_EMPTY_VALUE = 1,
parameter OF_ALMOST_FULL_VALUE = 1,
parameter OF_ARRAY_MODE = "UNDECLARED",
parameter OF_OUTPUT_DISABLE = "FALSE",
parameter OF_SYNCHRONOUS_MODE = "TRUE",
//IN_FIFO
parameter IF_ALMOST_EMPTY_VALUE = 1,
parameter IF_ALMOST_FULL_VALUE = 1,
parameter IF_ARRAY_MODE = "UNDECLARED",
parameter IF_SYNCHRONOUS_MODE = "TRUE",
//PHASER_IN
parameter PI_BURST_MODE = "TRUE",
parameter PI_CLKOUT_DIV = 2,
parameter PI_FREQ_REF_DIV = "NONE",
parameter PI_FINE_DELAY = 1,
parameter PI_OUTPUT_CLK_SRC = "DELAYED_REF" , //"DELAYED_REF",
parameter PI_SEL_CLK_OFFSET = 0,
parameter PI_SYNC_IN_DIV_RST = "FALSE",
//PHASER_OUT
parameter PO_CLKOUT_DIV = (PO_DATA_CTL == "FALSE") ? 4 : 2,
parameter PO_FINE_DELAY = 0,
parameter PO_COARSE_BYPASS = "FALSE",
parameter PO_COARSE_DELAY = 0,
parameter PO_OCLK_DELAY = 0,
parameter PO_OCLKDELAY_INV = "TRUE",
parameter PO_OUTPUT_CLK_SRC = "DELAYED_REF",
parameter PO_SYNC_IN_DIV_RST = "FALSE",
// OSERDES
parameter OSERDES_DATA_RATE = "DDR",
parameter OSERDES_DATA_WIDTH = 4,
//IDELAY
parameter IDELAYE2_IDELAY_TYPE = "VARIABLE",
parameter IDELAYE2_IDELAY_VALUE = 00,
parameter IODELAY_GRP = "IODELAY_MIG",
parameter FPGA_SPEED_GRADE = 1,
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter real TCK = 0.00,
parameter SYNTHESIS = "FALSE",
// local constants, do not pass in from above
parameter BUS_WIDTH = 12,
parameter MSB_BURST_PEND_PO = 3,
parameter MSB_BURST_PEND_PI = 7,
parameter MSB_RANK_SEL_I = MSB_BURST_PEND_PI + 8,
parameter PHASER_CTL_BUS_WIDTH = MSB_RANK_SEL_I + 1
,parameter CKE_ODT_AUX = "FALSE"
)(
input rst,
input phy_clk,
input freq_refclk,
input mem_refclk,
input idelayctrl_refclk,
input sync_pulse,
output [BUS_WIDTH-1:0] mem_dq_out,
output [BUS_WIDTH-1:0] mem_dq_ts,
input [9:0] mem_dq_in,
output mem_dqs_out,
output mem_dqs_ts,
input mem_dqs_in,
output [11:0] ddr_ck_out,
output rclk,
input if_empty_def,
output if_a_empty,
output if_empty,
output if_a_full,
output if_full,
output of_a_empty,
output of_empty,
output of_a_full,
output of_full,
output pre_fifo_a_full,
output [79:0] phy_din,
input [79:0] phy_dout,
input phy_cmd_wr_en,
input phy_data_wr_en,
input phy_rd_en,
input [PHASER_CTL_BUS_WIDTH-1:0] phaser_ctl_bus,
input idelay_inc,
input idelay_ce,
input idelay_ld,
input if_rst,
input [2:0] byte_rd_en_oth_lanes,
input [1:0] byte_rd_en_oth_banks,
output byte_rd_en,
output po_coarse_overflow,
output po_fine_overflow,
output [8:0] po_counter_read_val,
input po_fine_enable,
input po_coarse_enable,
input [1:0] po_en_calib,
input po_fine_inc,
input po_coarse_inc,
input po_counter_load_en,
input po_counter_read_en,
input po_sel_fine_oclk_delay,
input [8:0] po_counter_load_val,
input [1:0] pi_en_calib,
input pi_rst_dqs_find,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input pi_counter_read_en,
input [5:0] pi_counter_load_val,
output wire pi_iserdes_rst,
output pi_phase_locked,
output pi_fine_overflow,
output [5:0] pi_counter_read_val,
output wire pi_dqs_found,
output dqs_out_of_range,
input [29:0] fine_delay,
input fine_delay_sel
);
localparam PHASER_INDEX =
(ABCD=="B" ? 1 : (ABCD == "C") ? 2 : (ABCD == "D" ? 3 : 0));
localparam L_OF_ARRAY_MODE =
(OF_ARRAY_MODE != "UNDECLARED") ? OF_ARRAY_MODE :
(PO_DATA_CTL == "FALSE" || PC_CLK_RATIO == 2) ? "ARRAY_MODE_4_X_4" : "ARRAY_MODE_8_X_4";
localparam L_IF_ARRAY_MODE = (IF_ARRAY_MODE != "UNDECLARED") ? IF_ARRAY_MODE :
(PC_CLK_RATIO == 2) ? "ARRAY_MODE_4_X_4" : "ARRAY_MODE_4_X_8";
localparam L_OSERDES_DATA_RATE = (OSERDES_DATA_RATE != "UNDECLARED") ? OSERDES_DATA_RATE : ((PO_DATA_CTL == "FALSE" && PC_CLK_RATIO == 4) ? "SDR" : "DDR") ;
localparam L_OSERDES_DATA_WIDTH = (OSERDES_DATA_WIDTH != "UNDECLARED") ? OSERDES_DATA_WIDTH : 4;
localparam real L_FREQ_REF_PERIOD_NS = TCK > 2500.0 ? (TCK/(PI_FREQ_REF_DIV == "DIV2" ? 2 : 1)/1000.0) : TCK/1000.0;
localparam real L_MEM_REF_PERIOD_NS = TCK/1000.0;
localparam real L_PHASE_REF_PERIOD_NS = TCK/1000.0;
localparam ODDR_CLK_EDGE = "SAME_EDGE";
localparam PO_DCD_CORRECTION = "ON";
localparam [2:0] PO_DCD_SETTING = (PO_DCD_CORRECTION == "ON") ? 3'b111 : 3'b000;
localparam DQS_AUTO_RECAL = (BANK_TYPE == "HR_IO" || BANK_TYPE == "HRL_IO" || (BANK_TYPE == "HPL_IO" && TCK > 2500)) ? 1 : 0;
localparam DQS_FIND_PATTERN = (BANK_TYPE == "HR_IO" || BANK_TYPE == "HRL_IO" || (BANK_TYPE == "HPL_IO" && TCK > 2500)) ? "001" : "000";
wire [1:0] oserdes_dqs;
wire [1:0] oserdes_dqs_ts;
wire [1:0] oserdes_dq_ts;
wire [3:0] of_q9;
wire [3:0] of_q8;
wire [3:0] of_q7;
wire [7:0] of_q6;
wire [7:0] of_q5;
wire [3:0] of_q4;
wire [3:0] of_q3;
wire [3:0] of_q2;
wire [3:0] of_q1;
wire [3:0] of_q0;
wire [7:0] of_d9;
wire [7:0] of_d8;
wire [7:0] of_d7;
wire [7:0] of_d6;
wire [7:0] of_d5;
wire [7:0] of_d4;
wire [7:0] of_d3;
wire [7:0] of_d2;
wire [7:0] of_d1;
wire [7:0] of_d0;
wire [7:0] if_q9;
wire [7:0] if_q8;
wire [7:0] if_q7;
wire [7:0] if_q6;
wire [7:0] if_q5;
wire [7:0] if_q4;
wire [7:0] if_q3;
wire [7:0] if_q2;
wire [7:0] if_q1;
wire [7:0] if_q0;
wire [3:0] if_d9;
wire [3:0] if_d8;
wire [3:0] if_d7;
wire [3:0] if_d6;
wire [3:0] if_d5;
wire [3:0] if_d4;
wire [3:0] if_d3;
wire [3:0] if_d2;
wire [3:0] if_d1;
wire [3:0] if_d0;
wire [3:0] dummy_i5;
wire [3:0] dummy_i6;
wire [48-1:0] of_dqbus;
wire [10*4-1:0] iserdes_dout;
wire iserdes_clk;
wire iserdes_clkdiv;
wire ififo_wr_enable;
wire phy_rd_en_;
wire dqs_to_phaser;
wire phy_wr_en = ( PO_DATA_CTL == "FALSE" ) ? phy_cmd_wr_en : phy_data_wr_en;
wire if_empty_;
wire if_a_empty_;
wire if_full_;
wire if_a_full_;
wire po_oserdes_rst;
wire empty_post_fifo;
reg [3:0] if_empty_r /* synthesis syn_maxfan = 3 */;
wire [79:0] rd_data;
reg [79:0] rd_data_r;
reg ififo_rst = 1'b1;
reg ofifo_rst = 1'b1;
wire of_wren_pre;
wire [79:0] pre_fifo_dout;
wire pre_fifo_full;
wire pre_fifo_rden;
wire [5:0] ddr_ck_out_q;
wire ififo_rd_en_in /* synthesis syn_maxfan = 10 */;
wire oserdes_clkdiv;
wire oserdes_clk_delayed;
wire po_rd_enable;
always @(posedge phy_clk) begin
ififo_rst <= #1 pi_rst_dqs_find | if_rst ;
// reset only data o-fifos on reset of dqs_found
ofifo_rst <= #1 (pi_rst_dqs_find & PO_DATA_CTL == "TRUE") | rst;
end
// IN_FIFO EMPTY->RDEN TIMING FIX:
// Always read from IN_FIFO - it doesn't hurt to read from an empty FIFO
// since the IN_FIFO read pointers are not incr'ed when the FIFO is empty
assign #(25) phy_rd_en_ = 1'b1;
//assign #(25) phy_rd_en_ = phy_rd_en;
generate
if ( PO_DATA_CTL == "FALSE" ) begin : if_empty_null
assign if_empty = 0;
assign if_a_empty = 0;
assign if_full = 0;
assign if_a_full = 0;
end
else begin : if_empty_gen
assign if_empty = empty_post_fifo;
assign if_a_empty = if_a_empty_;
assign if_full = if_full_;
assign if_a_full = if_a_full_;
end
endgenerate
generate
if ( PO_DATA_CTL == "FALSE" ) begin : dq_gen_48
assign of_dqbus[48-1:0] = {of_q6[7:4], of_q5[7:4], of_q9, of_q8, of_q7, of_q6[3:0], of_q5[3:0], of_q4, of_q3, of_q2, of_q1, of_q0};
assign phy_din = 80'h0;
assign byte_rd_en = 1'b1;
end
else begin : dq_gen_40
assign of_dqbus[40-1:0] = {of_q9, of_q8, of_q7, of_q6[3:0], of_q5[3:0], of_q4, of_q3, of_q2, of_q1, of_q0};
assign ififo_rd_en_in = !if_empty_def ? ((&byte_rd_en_oth_banks) && (&byte_rd_en_oth_lanes) && byte_rd_en) :
((|byte_rd_en_oth_banks) || (|byte_rd_en_oth_lanes) || byte_rd_en);
if (USE_PRE_POST_FIFO == "TRUE") begin : if_post_fifo_gen
// IN_FIFO EMPTY->RDEN TIMING FIX:
assign rd_data = {if_q9, if_q8, if_q7, if_q6, if_q5, if_q4, if_q3, if_q2, if_q1, if_q0};
always @(posedge phy_clk) begin
rd_data_r <= #(025) rd_data;
if_empty_r[0] <= #(025) if_empty_;
if_empty_r[1] <= #(025) if_empty_;
if_empty_r[2] <= #(025) if_empty_;
if_empty_r[3] <= #(025) if_empty_;
end
mig_7series_v2_3_ddr_if_post_fifo #
(
.TCQ (25), // simulation CK->Q delay
.DEPTH (4), //2 // depth - account for up to 2 cycles of skew
.WIDTH (80) // width
)
u_ddr_if_post_fifo
(
.clk (phy_clk),
.rst (ififo_rst),
.empty_in (if_empty_r),
.rd_en_in (ififo_rd_en_in),
.d_in (rd_data_r),
.empty_out (empty_post_fifo),
.byte_rd_en (byte_rd_en),
.d_out (phy_din)
);
end
else begin : phy_din_gen
assign phy_din = {if_q9, if_q8, if_q7, if_q6, if_q5, if_q4, if_q3, if_q2, if_q1, if_q0};
assign empty_post_fifo = if_empty_;
end
end
endgenerate
assign { if_d9, if_d8, if_d7, if_d6, if_d5, if_d4, if_d3, if_d2, if_d1, if_d0} = iserdes_dout;
wire [1:0] rank_sel_i = ((phaser_ctl_bus[MSB_RANK_SEL_I :MSB_RANK_SEL_I -7] >> (PHASER_INDEX << 1)) & 2'b11);
generate
if ( USE_PRE_POST_FIFO == "TRUE" ) begin : of_pre_fifo_gen
assign {of_d9, of_d8, of_d7, of_d6, of_d5, of_d4, of_d3, of_d2, of_d1, of_d0} = pre_fifo_dout;
mig_7series_v2_3_ddr_of_pre_fifo #
(
.TCQ (25), // simulation CK->Q delay
.DEPTH (9), // depth - set to 9 to accommodate flow control
.WIDTH (80) // width
)
u_ddr_of_pre_fifo
(
.clk (phy_clk),
.rst (ofifo_rst),
.full_in (of_full),
.wr_en_in (phy_wr_en),
.d_in (phy_dout),
.wr_en_out (of_wren_pre),
.d_out (pre_fifo_dout),
.afull (pre_fifo_a_full)
);
end
else begin
// wire direct to ofifo
assign {of_d9, of_d8, of_d7, of_d6, of_d5, of_d4, of_d3, of_d2, of_d1, of_d0} = phy_dout;
assign of_wren_pre = phy_wr_en;
end
endgenerate
generate
if ( PO_DATA_CTL == "TRUE" || ((RCLK_SELECT_LANE==ABCD) && (CKE_ODT_AUX =="TRUE"))) begin : phaser_in_gen
PHASER_IN_PHY #(
.BURST_MODE ( PI_BURST_MODE),
.CLKOUT_DIV ( PI_CLKOUT_DIV),
.DQS_AUTO_RECAL ( DQS_AUTO_RECAL),
.DQS_FIND_PATTERN ( DQS_FIND_PATTERN),
.SEL_CLK_OFFSET ( PI_SEL_CLK_OFFSET),
.FINE_DELAY ( PI_FINE_DELAY),
.FREQ_REF_DIV ( PI_FREQ_REF_DIV),
.OUTPUT_CLK_SRC ( PI_OUTPUT_CLK_SRC),
.SYNC_IN_DIV_RST ( PI_SYNC_IN_DIV_RST),
.REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS),
.MEMREFCLK_PERIOD ( L_MEM_REF_PERIOD_NS),
.PHASEREFCLK_PERIOD ( L_PHASE_REF_PERIOD_NS)
) phaser_in (
.DQSFOUND (pi_dqs_found),
.DQSOUTOFRANGE (dqs_out_of_range),
.FINEOVERFLOW (pi_fine_overflow),
.PHASELOCKED (pi_phase_locked),
.ISERDESRST (pi_iserdes_rst),
.ICLKDIV (iserdes_clkdiv),
.ICLK (iserdes_clk),
.COUNTERREADVAL (pi_counter_read_val),
.RCLK (rclk),
.WRENABLE (ififo_wr_enable),
.BURSTPENDINGPHY (phaser_ctl_bus[MSB_BURST_PEND_PI - 3 + PHASER_INDEX]),
.ENCALIBPHY (pi_en_calib),
.FINEENABLE (pi_fine_enable),
.FREQREFCLK (freq_refclk),
.MEMREFCLK (mem_refclk),
.RANKSELPHY (rank_sel_i),
.PHASEREFCLK (dqs_to_phaser),
.RSTDQSFIND (pi_rst_dqs_find),
.RST (rst),
.FINEINC (pi_fine_inc),
.COUNTERLOADEN (pi_counter_load_en),
.COUNTERREADEN (pi_counter_read_en),
.COUNTERLOADVAL (pi_counter_load_val),
.SYNCIN (sync_pulse),
.SYSCLK (phy_clk)
);
end
else begin
assign pi_dqs_found = 1'b1;
// assign pi_dqs_out_of_range = 1'b0;
assign pi_phase_locked = 1'b1;
end
endgenerate
wire #0 phase_ref = freq_refclk;
wire oserdes_clk;
PHASER_OUT_PHY #(
.CLKOUT_DIV ( PO_CLKOUT_DIV),
.DATA_CTL_N ( PO_DATA_CTL ),
.FINE_DELAY ( PO_FINE_DELAY),
.COARSE_BYPASS ( PO_COARSE_BYPASS ),
.COARSE_DELAY ( PO_COARSE_DELAY),
.OCLK_DELAY ( PO_OCLK_DELAY),
.OCLKDELAY_INV ( PO_OCLKDELAY_INV),
.OUTPUT_CLK_SRC ( PO_OUTPUT_CLK_SRC),
.SYNC_IN_DIV_RST ( PO_SYNC_IN_DIV_RST),
.REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS),
.PHASEREFCLK_PERIOD ( 1), // dummy, not used
.PO ( PO_DCD_SETTING ),
.MEMREFCLK_PERIOD ( L_MEM_REF_PERIOD_NS)
) phaser_out (
.COARSEOVERFLOW (po_coarse_overflow),
.CTSBUS (oserdes_dqs_ts),
.DQSBUS (oserdes_dqs),
.DTSBUS (oserdes_dq_ts),
.FINEOVERFLOW (po_fine_overflow),
.OCLKDIV (oserdes_clkdiv),
.OCLK (oserdes_clk),
.OCLKDELAYED (oserdes_clk_delayed),
.COUNTERREADVAL (po_counter_read_val),
.BURSTPENDINGPHY (phaser_ctl_bus[MSB_BURST_PEND_PO -3 + PHASER_INDEX]),
.ENCALIBPHY (po_en_calib),
.RDENABLE (po_rd_enable),
.FREQREFCLK (freq_refclk),
.MEMREFCLK (mem_refclk),
.PHASEREFCLK (/*phase_ref*/),
.RST (rst),
.OSERDESRST (po_oserdes_rst),
.COARSEENABLE (po_coarse_enable),
.FINEENABLE (po_fine_enable),
.COARSEINC (po_coarse_inc),
.FINEINC (po_fine_inc),
.SELFINEOCLKDELAY (po_sel_fine_oclk_delay),
.COUNTERLOADEN (po_counter_load_en),
.COUNTERREADEN (po_counter_read_en),
.COUNTERLOADVAL (po_counter_load_val),
.SYNCIN (sync_pulse),
.SYSCLK (phy_clk)
);
generate
if (PO_DATA_CTL == "TRUE") begin : in_fifo_gen
IN_FIFO #(
.ALMOST_EMPTY_VALUE ( IF_ALMOST_EMPTY_VALUE ),
.ALMOST_FULL_VALUE ( IF_ALMOST_FULL_VALUE ),
.ARRAY_MODE ( L_IF_ARRAY_MODE),
.SYNCHRONOUS_MODE ( IF_SYNCHRONOUS_MODE)
) in_fifo (
.ALMOSTEMPTY (if_a_empty_),
.ALMOSTFULL (if_a_full_),
.EMPTY (if_empty_),
.FULL (if_full_),
.Q0 (if_q0),
.Q1 (if_q1),
.Q2 (if_q2),
.Q3 (if_q3),
.Q4 (if_q4),
.Q5 (if_q5),
.Q6 (if_q6),
.Q7 (if_q7),
.Q8 (if_q8),
.Q9 (if_q9),
//===
.D0 (if_d0),
.D1 (if_d1),
.D2 (if_d2),
.D3 (if_d3),
.D4 (if_d4),
.D5 ({dummy_i5,if_d5}),
.D6 ({dummy_i6,if_d6}),
.D7 (if_d7),
.D8 (if_d8),
.D9 (if_d9),
.RDCLK (phy_clk),
.RDEN (phy_rd_en_),
.RESET (ififo_rst),
.WRCLK (iserdes_clkdiv),
.WREN (ififo_wr_enable)
);
end
endgenerate
OUT_FIFO #(
.ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
.ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
.ARRAY_MODE (L_OF_ARRAY_MODE),
.OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
.SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE)
) out_fifo (
.ALMOSTEMPTY (of_a_empty),
.ALMOSTFULL (of_a_full),
.EMPTY (of_empty),
.FULL (of_full),
.Q0 (of_q0),
.Q1 (of_q1),
.Q2 (of_q2),
.Q3 (of_q3),
.Q4 (of_q4),
.Q5 (of_q5),
.Q6 (of_q6),
.Q7 (of_q7),
.Q8 (of_q8),
.Q9 (of_q9),
.D0 (of_d0),
.D1 (of_d1),
.D2 (of_d2),
.D3 (of_d3),
.D4 (of_d4),
.D5 (of_d5),
.D6 (of_d6),
.D7 (of_d7),
.D8 (of_d8),
.D9 (of_d9),
.RDCLK (oserdes_clkdiv),
.RDEN (po_rd_enable),
.RESET (ofifo_rst),
.WRCLK (phy_clk),
.WREN (of_wren_pre)
);
mig_7series_v2_3_ddr_byte_group_io #
(
.PO_DATA_CTL (PO_DATA_CTL),
.BITLANES (BITLANES),
.BITLANES_OUTONLY (BITLANES_OUTONLY),
.OSERDES_DATA_RATE (L_OSERDES_DATA_RATE),
.OSERDES_DATA_WIDTH (L_OSERDES_DATA_WIDTH),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.IDELAYE2_IDELAY_TYPE (IDELAYE2_IDELAY_TYPE),
.IDELAYE2_IDELAY_VALUE (IDELAYE2_IDELAY_VALUE),
.TCK (TCK),
.SYNTHESIS (SYNTHESIS)
)
ddr_byte_group_io
(
.mem_dq_out (mem_dq_out),
.mem_dq_ts (mem_dq_ts),
.mem_dq_in (mem_dq_in),
.mem_dqs_in (mem_dqs_in),
.mem_dqs_out (mem_dqs_out),
.mem_dqs_ts (mem_dqs_ts),
.rst (rst),
.oserdes_rst (po_oserdes_rst),
.iserdes_rst (pi_iserdes_rst ),
.iserdes_dout (iserdes_dout),
.dqs_to_phaser (dqs_to_phaser),
.phy_clk (phy_clk),
.iserdes_clk (iserdes_clk),
.iserdes_clkb (!iserdes_clk),
.iserdes_clkdiv (iserdes_clkdiv),
.idelay_inc (idelay_inc),
.idelay_ce (idelay_ce),
.idelay_ld (idelay_ld),
.idelayctrl_refclk (idelayctrl_refclk),
.oserdes_clk (oserdes_clk),
.oserdes_clk_delayed (oserdes_clk_delayed),
.oserdes_clkdiv (oserdes_clkdiv),
.oserdes_dqs ({oserdes_dqs[1], oserdes_dqs[0]}),
.oserdes_dqsts ({oserdes_dqs_ts[1], oserdes_dqs_ts[0]}),
.oserdes_dq (of_dqbus),
.oserdes_dqts ({oserdes_dq_ts[1], oserdes_dq_ts[0]}),
.fine_delay (fine_delay),
.fine_delay_sel (fine_delay_sel)
);
genvar i;
generate
for (i = 0; i <= 5; i = i+1) begin : ddr_ck_gen_loop
if (PO_DATA_CTL== "FALSE" && (BYTELANES_DDR_CK[i*4+PHASER_INDEX])) begin : ddr_ck_gen
ODDR #(.DDR_CLK_EDGE (ODDR_CLK_EDGE))
ddr_ck (
.C (oserdes_clk),
.R (1'b0),
.S (),
.D1 (1'b0),
.D2 (1'b1),
.CE (1'b1),
.Q (ddr_ck_out_q[i])
);
OBUFDS ddr_ck_obuf (.I(ddr_ck_out_q[i]), .O(ddr_ck_out[i*2]), .OB(ddr_ck_out[i*2+1]));
end // ddr_ck_gen
else begin : ddr_ck_null
assign ddr_ck_out[i*2+1:i*2] = 2'b0;
end
end // ddr_ck_gen_loop
endgenerate
endmodule // byte_lane
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
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// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: phy_init.v
// /___/ /\ Date Last Modified: $Date: 2011/01/08 11:34:37 $
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// Memory initialization and overall master state control during
// initialization and calibration. Specifically, the following functions
// are performed:
// 1. Memory initialization (initial AR, mode register programming, etc.)
// 2. Initiating write leveling
// 3. Generate training pattern writes for read leveling. Generate
// memory readback for read leveling.
// This module has an interface for providing control/address and write
// data to the PHY Control Block during initialization/calibration.
// Once initialization and calibration are complete, control is passed to the MC.
//
//Reference:
//Revision History:
//
//*****************************************************************************
/******************************************************************************
**$Id: phy_init.v,v 1.12.4.1 2011/01/08 11:34:37 karthip Exp $
**$Date: 2011/01/08 11:34:37 $
**$Author: karthip $
**$Revision: 1.12.4.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_1/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/phy_init.v,v $
******************************************************************************/
`timescale 1ps/1ps
module phy_init #
(
parameter TCQ = 100,
parameter nCK_PER_CLK = 4, // # of memory clocks per CLK
parameter CLK_PERIOD = 3000, // Logic (internal) clk period (in ps)
parameter PRBS_WIDTH = 64, // PRBS sequence = 2^PRBS_WIDTH
parameter BANK_WIDTH = 2,
parameter COL_WIDTH = 10,
parameter nCS_PER_RANK = 1, // # of CS bits per rank e.g. for
// component I/F with CS_WIDTH=1,
// nCS_PER_RANK=# of components
parameter DQ_WIDTH = 64,
parameter DQS_WIDTH = 8,
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter ROW_WIDTH = 14,
parameter CS_WIDTH = 1,
parameter RANKS = 1, // # of memory ranks in the interface
parameter CKE_WIDTH = 1, // # of cke outputs
parameter DRAM_TYPE = "DDR3",
parameter REG_CTRL = "ON",
// calibration Address
parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address
parameter CALIB_COL_ADD = 12'h000, // Calibration column address
parameter CALIB_BA_ADD = 3'h0, // Calibration bank address
// DRAM mode settings
parameter AL = "0", // Additive Latency option
parameter BURST_MODE = "8", // Burst length
parameter BURST_TYPE = "SEQ", // Burst type
// parameter nAL = 0, // Additive latency (in clk cyc)
parameter nCL = 5, // Read CAS latency (in clk cyc)
parameter nCWL = 5, // Write CAS latency (in clk cyc)
parameter tRFC = 110000, // Refresh-to-command delay (in ps)
parameter OUTPUT_DRV = "HIGH", // DRAM reduced output drive option
parameter RTT_NOM = "60", // Nominal ODT termination value
parameter RTT_WR = "60", // Write ODT termination value
parameter WRLVL = "ON", // Enable write leveling
// parameter PHASE_DETECT = "ON", // Enable read phase detector
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter nSLOTS = 1, // Number of DIMM SLOTs in the system
parameter SIM_INIT_OPTION = "NONE", // "NONE", "SKIP_PU_DLY", "SKIP_INIT"
parameter SIM_CAL_OPTION = "NONE" // "NONE", "FAST_CAL", "SKIP_CAL"
)
(
input clk,
input rst,
input [PRBS_WIDTH-1:0] prbs_o,
input pi_phaselocked,
input pi_phase_locked_all,
input pi_dqs_found_done,
// output [DQS_CNT_WIDTH:0] pi_phaselock_calib_cnt,
output pi_calib_done,
input phy_if_empty,
// input ck_addr_cmd_delay_done,
input dqs_dly_done,
// Read/write calibration interface
input wrlvl_done,
input wrlvl_rank_done,
input done_dqs_tap_inc,
input [5:0] rd_data_offset,
input [6*RANKS-1:0] rd_data_offset_ranks,
input pi_dqs_found_rank_done,
input wrcal_done,
input wrcal_prech_req,
input [7:0] slot_0_present,
input [7:0] slot_1_present,
output reg wl_sm_start,
output reg wr_lvl_start,
output reg wrcal_start,
input rdlvl_stg1_done,
input rdlvl_stg1_rank_done,
output reg rdlvl_stg1_start,
output reg pi_dqs_found_start,
output reg detect_pi_found_dqs,
// rdlvl stage 1 precharge requested after each DQS
input rdlvl_prech_req,
input wrcal_resume,
// Signals shared btw multiple calibration stages
output reg prech_done,
// Data select / status
output reg init_calib_complete,
// PHY address/control
// 2 commands to PHY Control Block per div 2 clock in 2:1 mode
// 4 commands to PHY Control Block per div 4 clock in 4:1 mode
output reg [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address,
output reg [nCK_PER_CLK*BANK_WIDTH-1:0]phy_bank,
output reg [nCK_PER_CLK-1:0] phy_ras_n,
output reg [nCK_PER_CLK-1:0] phy_cas_n,
output reg [nCK_PER_CLK-1:0] phy_we_n,
output reg phy_reset_n,
// output reg [CKE_WIDTH-1:0] phy_cke,
output [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n,
// output phy_init_data_sel,
// Hard PHY Interface signals
input phy_ctl_ready,
input phy_ctl_full,
input phy_cmd_full,
input phy_data_full,
output reg calib_ctl_wren,
output reg calib_cmd_wren,
output reg [1:0] calib_seq,
output reg write_calib,
output reg read_calib,
// PHY_Ctl_Wd
output reg [2:0] calib_cmd,
// ODT bus width is fixed to 4 for up to 4 ranks support
// For single rank only calib_aux_out0 used
output reg [3:0] calib_aux_out0,
output reg [3:0] calib_aux_out1,
output [1:0] calib_rank_cnt,
// output reg [2:0] calib_bank_cnt,
output reg [5:0] calib_data_offset,
// PHY OUT_FIFO
output reg calib_wrdata_en,
output reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_wrdata,
// PHY Read
output phy_rddata_en,
output phy_rddata_valid
// // PHY sideband signals
// output reg [0:0] phy_ioconfig,
// output reg phy_ioconfig_en
);
//*****************************************************************************
// Assertions to be added
//*****************************************************************************
// The phy_ctl_full signal must never be asserted in synchronous mode of
// operation either 4:1 or 2:1
//
// The RANKS parameter must never be set to '0' by the user
// valid values: 1 to 4
//
//*****************************************************************************
// Number of Read level stage 1 writes limited to a SDRAM row
// The address of Read Level stage 1 reads must also be limited
// to a single SDRAM row
// (2^COL_WIDTH)/BURST_MODE = (2^10)/8 = 128
localparam NUM_STG1_WR_RD = (BURST_MODE == "8") ? 128 :
(BURST_MODE == "4") ? 256 : 128;
localparam ADDR_INC = (BURST_MODE == "8") ? 8 :
(BURST_MODE == "4") ? 4 : 8;
// In a 2 slot dual rank per system RTT_NOM values
// for Rank2 and Rank3 default to 40 ohms
localparam RTT_NOM2 = "40";
localparam RTT_NOM3 = "40";
// Specifically for use with half-frequency controller (nCK_PER_CLK=2)
// = 1 if burst length = 4, = 0 if burst length = 8. Determines how
// often row command needs to be issued during read-leveling
// For DDR3 the burst length is fixed during calibration
localparam BURST4_FLAG = (DRAM_TYPE == "DDR3")? 1'b0 :
(BURST_MODE == "8") ? 1'b0 :
((BURST_MODE == "4") ? 1'b1 : 1'b0);
//***************************************************************************
// Counter values used to determine bus timing
// NOTE on all counter terminal counts - these can/should be one less than
// the actual delay to take into account extra clock cycle delay in
// generating the corresponding "done" signal
//***************************************************************************
localparam CLK_MEM_PERIOD = CLK_PERIOD / nCK_PER_CLK;
// Calculate initial delay required in number of CLK clock cycles
// to delay initially. The counter is clocked by [CLK/1024] - which
// is approximately division by 1000 - note that the formulas below will
// result in more than the minimum wait time because of this approximation.
// NOTE: For DDR3 JEDEC specifies to delay reset
// by 200us, and CKE by an additional 500us after power-up
// For DDR2 CKE is delayed by 200us after power up.
localparam DDR3_RESET_DELAY_NS = 200000;
localparam DDR3_CKE_DELAY_NS = 500000 + DDR3_RESET_DELAY_NS;
localparam DDR2_CKE_DELAY_NS = 200000;
localparam PWRON_RESET_DELAY_CNT =
((DDR3_RESET_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD);
localparam PWRON_CKE_DELAY_CNT = (DRAM_TYPE == "DDR3") ?
(((DDR3_CKE_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD)) :
(((DDR2_CKE_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD));
// FOR DDR2 -1 taken out. With -1 not getting 200us. The equation
// needs to be reworked.
localparam DDR2_INIT_PRE_DELAY_PS = 400000;
localparam DDR2_INIT_PRE_CNT =
((DDR2_INIT_PRE_DELAY_PS+CLK_PERIOD-1)/CLK_PERIOD)-1;
// Calculate tXPR time: reset from CKE HIGH to valid command after power-up
// tXPR = (max(5nCK, tRFC(min)+10ns). Add a few (blah, messy) more clock
// cycles because this counter actually starts up before CKE is asserted
// to memory.
localparam TXPR_DELAY_CNT =
(5*CLK_MEM_PERIOD > tRFC+10000) ?
(((5+nCK_PER_CLK-1)/nCK_PER_CLK)-1)+11 :
(((tRFC+10000+CLK_PERIOD-1)/CLK_PERIOD)-1)+11;
// tDLLK/tZQINIT time = 512*tCK = 256*tCLKDIV
localparam TDLLK_TZQINIT_DELAY_CNT = 255;
// TWR values in ns. Both DDR2 and DDR3 have the same value.
// 15000ns/tCK
localparam TWR_CYC = ((15000) % CLK_MEM_PERIOD) ?
(15000/CLK_MEM_PERIOD) + 1 : 15000/CLK_MEM_PERIOD;
// time to wait between consecutive commands in PHY_INIT - this is a
// generic number, and must be large enough to account for worst case
// timing parameter (tRFC - refresh-to-active) across all memory speed
// grades and operating frequencies. Expressed in clk
// (Divided by 4 or Divided by 2) clock cycles.
localparam CNTNEXT_CMD = (nCK_PER_CLK == 4) ? 7'b1100110 : 7'b1111111;
// Counter values to keep track of which MR register to load during init
// Set value of INIT_CNT_MR_DONE to equal value of counter for last mode
// register configured during initialization.
// NOTE: Reserve more bits for DDR2 - more MR accesses for DDR2 init
localparam INIT_CNT_MR2 = 2'b00;
localparam INIT_CNT_MR3 = 2'b01;
localparam INIT_CNT_MR1 = 2'b10;
localparam INIT_CNT_MR0 = 2'b11;
localparam INIT_CNT_MR_DONE = 2'b11;
// Register chip programmable values for DDR3
// The register chip for the registered DIMM needs to be programmed
// before the initialization of the registered DIMM.
// Address for the control word is in : DBA2, DA2, DA1, DA0
// Data for the control word is in: DBA1 DBA0, DA4, DA3
// The values will be stored in the local param in the following format
// {DBA[2:0], DA[4:0]}
// RC0 is global features control word. Address == 000
localparam REG_RC0 = 8'b00000000;
// RC1 Clock driver enable control word. Enables or disables the four
// output clocks in the register chip. For single rank and dual rank
// two clocks will be enabled and for quad rank all the four clocks
// will be enabled. Address == 000. Data = 0110 for single and dual rank.
// = 0000 for quad rank
localparam REG_RC1 = (RANKS <= 2) ? 8'b00110001 : 8'b00000001;
// RC2 timing control word. Set in 1T timing mode
// Address = 010. Data = 0000
localparam REG_RC2 = 8'b00000010;
// RC3 timing control word. Setting the data to 0000
localparam REG_RC3 = 8'b00000011;
// RC4 timing control work. Setting the data to 0000
localparam REG_RC4 = 8'b00000100;
// RC5 timing control work. Setting the data to 0000
localparam REG_RC5 = 8'b00000101;
// For non-zero AL values
localparam nAL = (AL == "CL-1") ? nCL - 1 : 0;
// Adding the register dimm latency to write latency
localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL;
// Master state machine encoding
localparam INIT_IDLE = 6'b000000; //0
localparam INIT_WAIT_CKE_EXIT = 6'b000001; //1
localparam INIT_LOAD_MR = 6'b000010; //2
localparam INIT_LOAD_MR_WAIT = 6'b000011; //3
localparam INIT_ZQCL = 6'b000100; //4
localparam INIT_WAIT_DLLK_ZQINIT = 6'b000101; //5
localparam INIT_WRLVL_START = 6'b000110; //6
localparam INIT_WRLVL_WAIT = 6'b000111; //7
localparam INIT_WRLVL_LOAD_MR = 6'b001000; //8
localparam INIT_WRLVL_LOAD_MR_WAIT = 6'b001001; //9
localparam INIT_WRLVL_LOAD_MR2 = 6'b001010; //A
localparam INIT_WRLVL_LOAD_MR2_WAIT = 6'b001011; //B
localparam INIT_RDLVL_ACT = 6'b001100; //C
localparam INIT_RDLVL_ACT_WAIT = 6'b001101; //D
localparam INIT_RDLVL_STG1_WRITE = 6'b001110; //E
localparam INIT_RDLVL_STG1_WRITE_READ = 6'b001111; //F
localparam INIT_RDLVL_STG1_READ = 6'b010000; //10
localparam INIT_RDLVL_STG2_READ = 6'b010001; //11
localparam INIT_RDLVL_STG2_READ_WAIT = 6'b010010; //12
localparam INIT_PRECHARGE_PREWAIT = 6'b010011; //13
localparam INIT_PRECHARGE = 6'b010100; //14
localparam INIT_PRECHARGE_WAIT = 6'b010101; //15
localparam INIT_DONE = 6'b010110; //16
localparam INIT_DDR2_PRECHARGE = 6'b010111; //17
localparam INIT_DDR2_PRECHARGE_WAIT = 6'b011000; //18
localparam INIT_REFRESH = 6'b011001; //19
localparam INIT_REFRESH_WAIT = 6'b011010; //1A
localparam INIT_REG_WRITE = 6'b011011; //1B
localparam INIT_REG_WRITE_WAIT = 6'b011100; //1C
localparam INIT_DDR2_MULTI_RANK = 6'b011101; //1D
localparam INIT_DDR2_MULTI_RANK_WAIT = 6'b011110; //1E
localparam INIT_WRCAL_ACT = 6'b011111; //1F
localparam INIT_WRCAL_ACT_WAIT = 6'b100000; //20
localparam INIT_WRCAL_WRITE = 6'b100001; //21
localparam INIT_WRCAL_WRITE_READ = 6'b100010; //22
localparam INIT_WRCAL_READ = 6'b100011; //23
localparam INIT_WRCAL_READ_WAIT = 6'b100100; //24
localparam INIT_PI_PHASELOCK_READS = 6'b100101; //25
integer i, j, k, l, m, n, p;
reg stg1_wr_done;
reg pi_dqs_found_done_r1;
reg pi_dqs_found_rank_done_r;
reg dqs_dly_done_r1;
reg read_calib_int;
reg read_calib_r;
reg pi_calib_done_r;
reg burst_addr_r;
reg [1:0] chip_cnt_r;
reg [6:0] cnt_cmd_r;
reg cnt_cmd_done_r;
reg [7:0] cnt_dllk_zqinit_r;
reg cnt_dllk_zqinit_done_r;
reg cnt_init_af_done_r;
reg [1:0] cnt_init_af_r;
reg [1:0] cnt_init_data_r;
reg [1:0] cnt_init_mr_r;
reg cnt_init_mr_done_r;
reg cnt_init_pre_wait_done_r;
reg [7:0] cnt_init_pre_wait_r;
reg [9:0] cnt_pwron_ce_r;
reg cnt_pwron_cke_done_r;
reg cnt_pwron_cke_done_r1;
reg [8:0] cnt_pwron_r;
reg cnt_pwron_reset_done_r;
reg cnt_txpr_done_r;
reg [7:0] cnt_txpr_r;
reg ddr2_pre_flag_r;
reg ddr2_refresh_flag_r;
reg ddr3_lm_done_r;
reg [4:0] enable_wrlvl_cnt;
reg init_complete_r;
reg init_complete_r1;
reg init_complete_r2;
reg [5:0] init_next_state;
reg [5:0] init_state_r;
reg [5:0] init_state_r1;
wire [15:0] load_mr0;
wire [15:0] load_mr1;
wire [15:0] load_mr2;
wire [15:0] load_mr3;
reg mem_init_done_r;
reg [1:0] mr2_r [0:3];
reg [2:0] mr1_r [0:3];
reg new_burst_r;
reg [15:0] wrcal_start_dly_r;
wire wrcal_start_pre;
// Only one ODT signal per rank in PHY Control Block
reg [nCK_PER_CLK-1:0] phy_tmp_odt_r;
reg [nCK_PER_CLK-1:0] phy_tmp_odt_r1;
reg [CS_WIDTH*nCS_PER_RANK-1:0] phy_tmp_cs1_r;
reg [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_int_cs_n;
wire prech_done_pre;
reg [15:0] prech_done_dly_r;
reg prech_pending_r;
reg prech_req_posedge_r;
reg prech_req_r;
reg pwron_ce_r;
reg phy_wrdata_en;
reg phy_wrdata_en_r1;
reg phy_wrdata_en_r2;
reg phy_wrdata_en_r3;
reg [ROW_WIDTH-1:0] address_w;
reg [BANK_WIDTH-1:0] bank_w;
reg rdlvl_stg1_start_int;
reg [15:0] rdlvl_start_dly0_r;
wire rdlvl_start_pre;
wire rdlvl_rd;
wire rdlvl_wr;
reg rdlvl_wr_r;
wire rdlvl_wr_rd;
reg [2:0] reg_ctrl_cnt_r;
reg [1:0] tmp_mr2_r [0:3];
reg [2:0] tmp_mr1_r [0:3];
reg wrlvl_done_r;
reg wrlvl_done_r1;
reg wrlvl_rank_done_r1;
reg wrlvl_rank_done_r2;
reg wrlvl_rank_done_r3;
reg [2:0] wrlvl_rank_cntr;
reg wrlvl_odt;
reg wrlvl_active;
reg wrlvl_active_r1;
reg [1:0] num_reads;
reg [8:0] stg1_wr_rd_cnt;
reg wr_level_dqs_asrt;
reg wr_level_dqs_asrt_r1;
reg [1:0] dqs_asrt_cnt;
// reg pi_calib_start;
reg [PRBS_WIDTH-1:0] prbs_r1;
reg [PRBS_WIDTH-1:0] prbs_r2;
reg [PRBS_WIDTH-1:0] prbs_r3;
reg [PRBS_WIDTH-1:0] prbs_r4;
reg [PRBS_WIDTH-1:0] prbs_r5;
reg [PRBS_WIDTH-1:0] prbs_r6;
reg [PRBS_WIDTH-1:0] prbs_r7;
//***************************************************************************
// Debug
//***************************************************************************
//synthesis translate_off
always @(posedge mem_init_done_r) begin
if (!rst)
$display ("PHY_INIT: Memory Initialization completed at %t", $time);
end
always @(posedge wrlvl_done) begin
if (!rst && (WRLVL == "ON"))
$display ("PHY_INIT: Write Leveling completed at %t", $time);
end
always @(posedge rdlvl_stg1_done) begin
if (!rst)
$display ("PHY_INIT: Read Leveling Stage 1 completed at %t", $time);
end
always @(posedge pi_calib_done_r) begin
if (!rst)
$display ("PHY_INIT: Phaser_In Phase Locked at %t", $time);
end
always @(posedge pi_dqs_found_done) begin
if (!rst)
$display ("PHY_INIT: Phaser_In DQSFOUND completed at %t", $time);
end
always @(posedge wrcal_done) begin
if (!rst && (WRLVL == "ON"))
$display ("PHY_INIT: Write Calibration completed at %t", $time);
end
//synthesis translate_on
//***************************************************************************
// DQS count to be sent to hard PHY during Phaser_IN Phase Locking stage
//***************************************************************************
// assign pi_phaselock_calib_cnt = dqs_cnt_r;
assign pi_calib_done = pi_calib_done_r;
//***************************************************************************
// Signal PHY completion when calibration is finished
// Signal assertion is delayed by four clock cycles to account for the
// multi cycle path constraint to (phy_init_data_sel) signal.
//***************************************************************************
always @(posedge clk)
if (rst) begin
init_complete_r <= #TCQ 1'b0;
init_complete_r1 <= #TCQ 1'b0;
init_complete_r2 <= #TCQ 1'b0;
init_calib_complete <= #TCQ 1'b0;
end else begin
if (init_state_r == INIT_DONE)
init_complete_r <= #TCQ 1'b1;
init_complete_r1 <= #TCQ init_complete_r;
init_complete_r2 <= #TCQ init_complete_r1;
init_calib_complete <= #TCQ init_complete_r2;
end
//***************************************************************************
// Instantiate FF for the phy_init_data_sel signal. A multi cycle path
// constraint will be assigned to this signal. This signal will only be
// used within the PHY
//***************************************************************************
// FDRSE u_ff_phy_init_data_sel
// (
// .Q (phy_init_data_sel),
// .C (clk),
// .CE (1'b1),
// .D (init_complete_r),
// .R (1'b0),
// .S (1'b0)
// ) /* synthesis syn_preserve=1 */
// /* synthesis syn_replicate = 0 */;
//***************************************************************************
// Mode register programming
//***************************************************************************
//*****************************************************************
// DDR3 Load mode reg0
// Mode Register (MR0):
// [15:13] - unused - 000
// [12] - Precharge Power-down DLL usage - 0 (DLL frozen, slow-exit),
// 1 (DLL maintained)
// [11:9] - write recovery for Auto Precharge (tWR/tCK = 6)
// [8] - DLL reset - 0 or 1
// [7] - Test Mode - 0 (normal)
// [6:4],[2] - CAS latency - CAS_LAT
// [3] - Burst Type - BURST_TYPE
// [1:0] - Burst Length - BURST_LEN
// DDR2 Load mode register
// Mode Register (MR):
// [15:14] - unused - 00
// [13] - reserved - 0
// [12] - Power-down mode - 0 (normal)
// [11:9] - write recovery - write recovery for Auto Precharge
// (tWR/tCK = 6)
// [8] - DLL reset - 0 or 1
// [7] - Test Mode - 0 (normal)
// [6:4] - CAS latency - CAS_LAT
// [3] - Burst Type - BURST_TYPE
// [2:0] - Burst Length - BURST_LEN
//*****************************************************************
generate
if(DRAM_TYPE == "DDR3") begin: gen_load_mr0_DDR3
assign load_mr0[1:0] = (BURST_MODE == "8") ? 2'b00 :
(BURST_MODE == "OTF") ? 2'b01 :
(BURST_MODE == "4") ? 2'b10 : 2'b11;
assign load_mr0[2] = (nCL >= 12) ? 1'b1 : 1'b0; // LSb of CAS latency
assign load_mr0[3] = (BURST_TYPE == "SEQ") ? 1'b0 : 1'b1;
assign load_mr0[6:4] = ((nCL == 5) || (nCL == 13)) ? 3'b001 :
((nCL == 6) || (nCL == 14)) ? 3'b010 :
(nCL == 7) ? 3'b011 :
(nCL == 8) ? 3'b100 :
(nCL == 9) ? 3'b101 :
(nCL == 10) ? 3'b110 :
(nCL == 11) ? 3'b111 :
(nCL == 12) ? 3'b000 : 3'b111;
assign load_mr0[7] = 1'b0;
assign load_mr0[8] = 1'b1; // Reset DLL (init only)
assign load_mr0[11:9] = (TWR_CYC == 5) ? 3'b001 :
(TWR_CYC == 6) ? 3'b010 :
(TWR_CYC == 7) ? 3'b011 :
(TWR_CYC == 8) ? 3'b100 :
(TWR_CYC == 9) ? 3'b101 :
(TWR_CYC == 10) ? 3'b101 :
(TWR_CYC == 11) ? 3'b110 :
(TWR_CYC == 12) ? 3'b110 :
(TWR_CYC == 13) ? 3'b111 :
(TWR_CYC == 14) ? 3'b111 :
(TWR_CYC == 15) ? 3'b000 :
(TWR_CYC == 16) ? 3'b000 : 3'b010;
assign load_mr0[12] = 1'b0; // Precharge Power-Down DLL 'slow-exit'
assign load_mr0[15:13] = 3'b000;
end else if (DRAM_TYPE == "DDR2") begin: gen_load_mr0_DDR2 // block: gen
assign load_mr0[2:0] = (BURST_MODE == "8") ? 3'b011 :
(BURST_MODE == "4") ? 3'b010 : 3'b111;
assign load_mr0[3] = (BURST_TYPE == "SEQ") ? 1'b0 : 1'b1;
assign load_mr0[6:4] = (nCL == 3) ? 3'b011 :
(nCL == 4) ? 3'b100 :
(nCL == 5) ? 3'b101 :
(nCL == 6) ? 3'b110 : 3'b111;
assign load_mr0[7] = 1'b0;
assign load_mr0[8] = 1'b1; // Reset DLL (init only)
assign load_mr0[11:9] = (TWR_CYC == 2) ? 3'b001 :
(TWR_CYC == 3) ? 3'b010 :
(TWR_CYC == 4) ? 3'b011 :
(TWR_CYC == 5) ? 3'b100 :
(TWR_CYC == 6) ? 3'b101 : 3'b010;
assign load_mr0[15:12]= 4'b0000; // Reserved
end
endgenerate
//*****************************************************************
// DDR3 Load mode reg1
// Mode Register (MR1):
// [15:13] - unused - 00
// [12] - output enable - 0 (enabled for DQ, DQS, DQS#)
// [11] - TDQS enable - 0 (TDQS disabled and DM enabled)
// [10] - reserved - 0 (must be '0')
// [9] - RTT[2] - 0
// [8] - reserved - 0 (must be '0')
// [7] - write leveling - 0 (disabled), 1 (enabled)
// [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50)
// [5] - Output driver impedance[1] - 0 (RZQ/6 and RZQ/7)
// [4:3] - Additive CAS - ADDITIVE_CAS
// [2] - RTT[0]
// [1] - Output driver impedance[0] - 0(RZQ/6), or 1 (RZQ/7)
// [0] - DLL enable - 0 (normal)
// DDR2 ext mode register
// Extended Mode Register (MR):
// [15:14] - unused - 00
// [13] - reserved - 0
// [12] - output enable - 0 (enabled)
// [11] - RDQS enable - 0 (disabled)
// [10] - DQS# enable - 0 (enabled)
// [9:7] - OCD Program - 111 or 000 (first 111, then 000 during init)
// [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50)
// [5:3] - Additive CAS - ADDITIVE_CAS
// [2] - RTT[0]
// [1] - Output drive - REDUCE_DRV (= 0(full), = 1 (reduced)
// [0] - DLL enable - 0 (normal)
//*****************************************************************
generate
if(DRAM_TYPE == "DDR3") begin: gen_load_mr1_DDR3
assign load_mr1[0] = 1'b0; // DLL enabled during Imitialization
assign load_mr1[1] = (OUTPUT_DRV == "LOW") ? 1'b0 : 1'b1;
assign load_mr1[2] = ((RTT_NOM == "30") || (RTT_NOM == "40") ||
(RTT_NOM == "60")) ? 1'b1 : 1'b0;
assign load_mr1[4:3] = (AL == "0") ? 2'b00 :
(AL == "CL-1") ? 2'b01 :
(AL == "CL-2") ? 2'b10 : 2'b11;
assign load_mr1[5] = 1'b0;
assign load_mr1[6] = ((RTT_NOM == "40") || (RTT_NOM == "120")) ?
1'b1 : 1'b0;
assign load_mr1[7] = 1'b0; // Enable write lvl after init sequence
assign load_mr1[8] = 1'b0;
assign load_mr1[9] = ((RTT_NOM == "20") || (RTT_NOM == "30")) ?
1'b1 : 1'b0;
assign load_mr1[10] = 1'b0;
assign load_mr1[15:11] = 5'b00000;
end else if (DRAM_TYPE == "DDR2") begin: gen_load_mr1_DDR2
assign load_mr1[0] = 1'b0; // DLL enabled during Imitialization
assign load_mr1[1] = (OUTPUT_DRV == "LOW") ? 1'b1 : 1'b0;
assign load_mr1[2] = ((RTT_NOM == "75") || (RTT_NOM == "50")) ?
1'b1 : 1'b0;
assign load_mr1[5:3] = (AL == "0") ? 3'b000 :
(AL == "1") ? 3'b001 :
(AL == "2") ? 3'b010 :
(AL == "3") ? 3'b011 :
(AL == "4") ? 3'b100 : 3'b111;
assign load_mr1[6] = ((RTT_NOM == "50") ||
(RTT_NOM == "150")) ? 1'b1 : 1'b0;
assign load_mr1[9:7] = 3'b000;
assign load_mr1[10] = (DDR2_DQSN_ENABLE == "YES") ? 1'b0 : 1'b1;
assign load_mr1[15:11] = 5'b00000;
end
endgenerate
//*****************************************************************
// DDR3 Load mode reg2
// Mode Register (MR2):
// [15:11] - unused - 00
// [10:9] - RTT_WR - 00 (Dynamic ODT off)
// [8] - reserved - 0 (must be '0')
// [7] - self-refresh temperature range -
// 0 (normal), 1 (extended)
// [6] - Auto Self-Refresh - 0 (manual), 1(auto)
// [5:3] - CAS Write Latency (CWL) -
// 000 (5 for 400 MHz device),
// 001 (6 for 400 MHz to 533 MHz devices),
// 010 (7 for 533 MHz to 667 MHz devices),
// 011 (8 for 667 MHz to 800 MHz)
// [2:0] - Partial Array Self-Refresh (Optional) -
// 000 (full array)
// Not used for DDR2
//*****************************************************************
generate
if(DRAM_TYPE == "DDR3") begin: gen_load_mr2_DDR3
assign load_mr2[2:0] = 3'b000;
assign load_mr2[5:3] = (nCWL == 5) ? 3'b000 :
(nCWL == 6) ? 3'b001 :
(nCWL == 7) ? 3'b010 :
(nCWL == 8) ? 3'b011 :
(nCWL == 9) ? 3'b100 :
(nCWL == 10) ? 3'b101 :
(nCWL == 11) ? 3'b110 : 3'b111;
assign load_mr2[6] = 1'b0;
assign load_mr2[7] = 1'b0;
assign load_mr2[8] = 1'b0;
// Dynamic ODT disabled
assign load_mr2[10:9] = 2'b00;
assign load_mr2[15:11] = 5'b00000;
end else begin: gen_load_mr2_DDR2
assign load_mr2[15:0] = 16'd0;
end
endgenerate
//*****************************************************************
// DDR3 Load mode reg3
// Mode Register (MR3):
// [15:3] - unused - All zeros
// [2] - MPR Operation - 0(normal operation), 1(data flow from MPR)
// [1:0] - MPR location - 00 (Predefined pattern)
//*****************************************************************
assign load_mr3[1:0] = 2'b00;
assign load_mr3[2] = 1'b0;
assign load_mr3[15:3] = 13'b0000000000000;
// For multi-rank systems the rank being accessed during writes in
// Read Leveling must be sent to phy_write for the bitslip logic
assign calib_rank_cnt = chip_cnt_r;
//***************************************************************************
// Logic to begin initial calibration, and to handle precharge requests
// during read-leveling (to avoid tRAS violations if individual read
// levelling calibration stages take more than max{tRAS) to complete).
//***************************************************************************
// Assert when readback for each stage of read-leveling begins. However,
// note this indicates only when the read command is issued and when
// Phaser_IN has phase aligned FREQ_REF clock to read DQS. It does not
// indicate when the read data is present on the bus (when this happens
// after the read command is issued depends on CAS LATENCY) - there will
// need to be some delay before valid data is present on the bus.
// assign rdlvl_start_pre = (init_state_r == INIT_PI_PHASELOCK_READS);
// Assert when read back for write calibration begins
assign wrcal_start_pre = (init_state_r == INIT_WRCAL_READ);
// Common precharge signal done signal - pulses only when there has been
// a precharge issued as a result of a PRECH_REQ pulse. Note also a common
// PRECH_DONE signal is used for all blocks
assign prech_done_pre = (((init_state_r == INIT_RDLVL_STG1_READ) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_WRCAL_READ)) &&
prech_pending_r &&
!prech_req_posedge_r);
// Delay start of each calibration by 16 clock cycles to ensure that when
// calibration logic begins, read data is already appearing on the bus.
// Each circuit should synthesize using an SRL16. Assume that reset is
// long enough to clear contents of SRL16.
always @(posedge clk) begin
// rdlvl_start_dly0_r <= #TCQ {rdlvl_start_dly0_r[14:0],
// rdlvl_start_pre};
wrcal_start_dly_r <= #TCQ {wrcal_start_dly_r[14:0],
wrcal_start_pre};
prech_done_dly_r <= #TCQ {prech_done_dly_r[14:0],
prech_done_pre};
end
always @(posedge clk)
prech_done <= #TCQ prech_done_dly_r[15];
// Generate latched signals for start of write and read leveling
always @(posedge clk)
if (rst) begin
// pi_calib_start <= #TCQ 1'b0;
rdlvl_stg1_start <= #TCQ 1'b0;
rdlvl_stg1_start_int <= #TCQ 1'b0;
pi_dqs_found_start <= #TCQ 1'b0;
wrcal_start <= #TCQ 1'b0;
end else begin
if (!pi_dqs_found_done && init_state_r == INIT_RDLVL_STG2_READ)
pi_dqs_found_start <= #TCQ 1'b1;
if (pi_dqs_found_done && cnt_cmd_done_r &&
(init_state_r == INIT_RDLVL_ACT_WAIT))
rdlvl_stg1_start_int <= #TCQ 1'b1;
if (pi_dqs_found_done &&
(init_state_r == INIT_RDLVL_STG1_READ))
rdlvl_stg1_start <= #TCQ 1'b1;
if (wrcal_start_dly_r[5])
wrcal_start <= #TCQ 1'b1;
end // else: !if(rst)
always @(posedge clk)
if (rst)
pi_dqs_found_done_r1 <= #TCQ 1'b0;
else if (pi_dqs_found_done)
pi_dqs_found_done_r1 <= #TCQ 1'b1;
// Constantly enable DQS while write leveling is enabled in the memory
// This is more to get rid of warnings in simulation, can later change
// this code to only enable WRLVL_ACTIVE when WRLVL_START is asserted
generate
if (nCK_PER_CLK == 4) begin: en_cnt_div4
always @ (posedge clk)
if (rst || wrlvl_rank_done)
enable_wrlvl_cnt <= #TCQ 5'd0;
else if ((init_state_r == INIT_WRLVL_START) ||
(wrlvl_odt && (enable_wrlvl_cnt == 5'd0)))
enable_wrlvl_cnt <= #TCQ 5'd12;
else if ((enable_wrlvl_cnt > 5'd0) && ~(phy_ctl_full || phy_cmd_full))
enable_wrlvl_cnt <= #TCQ enable_wrlvl_cnt - 1;
// ODT stays asserted as long as write_calib
// signal is asserted
always @(posedge clk)
if (rst || wrlvl_rank_done || done_dqs_tap_inc)
wrlvl_odt <= #TCQ 1'b0;
else if (enable_wrlvl_cnt == 5'd1)
wrlvl_odt <= #TCQ 1'b1;
end else begin: en_cnt_div2
always @ (posedge clk)
if (rst)
enable_wrlvl_cnt <= #TCQ 5'd0;
else if ((init_state_r == INIT_WRLVL_START) ||
(wrlvl_odt && (enable_wrlvl_cnt == 5'd0)))
enable_wrlvl_cnt <= #TCQ 5'd21;
else if ((enable_wrlvl_cnt > 5'd0) && ~(phy_ctl_full || phy_cmd_full))
enable_wrlvl_cnt <= #TCQ enable_wrlvl_cnt - 1;
// ODT stays asserted as long as write_calib
// signal is asserted
always @(posedge clk)
if (rst || wrlvl_rank_done || done_dqs_tap_inc)
wrlvl_odt <= #TCQ 1'b0;
else if (enable_wrlvl_cnt == 5'd1)
wrlvl_odt <= #TCQ 1'b1;
end
endgenerate
always @(posedge clk)
if (rst || wrlvl_rank_done || done_dqs_tap_inc)
wrlvl_active <= #TCQ 1'b0;
else if ((enable_wrlvl_cnt == 5'd1) && wrlvl_odt && !wrlvl_active)
wrlvl_active <= #TCQ 1'b1;
// signal used to assert DQS for write leveling.
// the DQS will be asserted once every 16 clock cycles.
always @(posedge clk)begin
if(rst || (enable_wrlvl_cnt != 5'd1)) begin
wr_level_dqs_asrt <= #TCQ 1'd0;
end else if ((enable_wrlvl_cnt == 5'd1) && (wrlvl_active_r1)) begin
wr_level_dqs_asrt <= #TCQ 1'd1;
end
end
always @ (posedge clk) begin
if (rst)
dqs_asrt_cnt <= #TCQ 2'd0;
else if (wr_level_dqs_asrt && dqs_asrt_cnt != 2'd3)
dqs_asrt_cnt <= #TCQ (dqs_asrt_cnt + 1);
end
always @ (posedge clk) begin
if (rst || ~wrlvl_active)
wr_lvl_start <= #TCQ 1'd0;
else if (dqs_asrt_cnt == 2'd3)
wr_lvl_start <= #TCQ 1'd1;
end
always @(posedge clk) begin
if (rst)
wl_sm_start <= #TCQ 1'b0;
else
wl_sm_start <= #TCQ wr_level_dqs_asrt_r1;
end
always @(posedge clk) begin
wrlvl_active_r1 <= #TCQ wrlvl_active;
wr_level_dqs_asrt_r1 <= #TCQ wr_level_dqs_asrt;
wrlvl_done_r <= #TCQ wrlvl_done;
wrlvl_done_r1 <= #TCQ wrlvl_done_r;
wrlvl_rank_done_r1 <= #TCQ wrlvl_rank_done;
wrlvl_rank_done_r2 <= #TCQ wrlvl_rank_done_r1;
wrlvl_rank_done_r3 <= #TCQ wrlvl_rank_done_r2;
end
always @ (posedge clk) begin
if (rst)
wrlvl_rank_cntr <= #TCQ 3'd0;
else if (wrlvl_rank_done)
wrlvl_rank_cntr <= #TCQ wrlvl_rank_cntr + 1'b1;
end
//*****************************************************************
// Precharge request logic - those calibration logic blocks
// that require greater than tRAS(max) to finish must break up
// their calibration into smaller units of time, with precharges
// issued in between. This is done using the XXX_PRECH_REQ and
// PRECH_DONE handshaking between PHY_INIT and those blocks
//*****************************************************************
// Shared request from multiple sources
assign prech_req = rdlvl_prech_req | wrcal_prech_req;
// Handshaking logic to force precharge during read leveling, and to
// notify read leveling logic when precharge has been initiated and
// it's okay to proceed with leveling again
always @(posedge clk)
if (rst) begin
prech_req_r <= #TCQ 1'b0;
prech_req_posedge_r <= #TCQ 1'b0;
prech_pending_r <= #TCQ 1'b0;
end else begin
prech_req_r <= #TCQ prech_req;
prech_req_posedge_r <= #TCQ prech_req & ~prech_req_r;
if (prech_req_posedge_r)
prech_pending_r <= #TCQ 1'b1;
// Clear after we've finished with the precharge and have
// returned to issuing read leveling calibration reads
else if (prech_done_pre)
prech_pending_r <= #TCQ 1'b0;
end
//***************************************************************************
// Various timing counters
//***************************************************************************
//*****************************************************************
// Generic delay for various states that require it (e.g. for turnaround
// between read and write). Make this a sufficiently large number of clock
// cycles to cover all possible frequencies and memory components)
// Requirements for this counter:
// 1. Greater than tMRD
// 2. tRFC (refresh-active) for DDR2
// 3. (list the other requirements, slacker...)
//*****************************************************************
always @(posedge clk) begin
case (init_state_r)
INIT_LOAD_MR_WAIT,
INIT_WRLVL_LOAD_MR_WAIT,
INIT_WRLVL_LOAD_MR2_WAIT,
INIT_RDLVL_ACT_WAIT,
INIT_RDLVL_STG1_WRITE_READ,
INIT_RDLVL_STG2_READ_WAIT,
INIT_WRCAL_ACT_WAIT,
INIT_WRCAL_WRITE_READ,
INIT_WRCAL_READ_WAIT,
INIT_PRECHARGE_PREWAIT,
INIT_PRECHARGE_WAIT,
INIT_DDR2_PRECHARGE_WAIT,
INIT_REG_WRITE_WAIT,
INIT_REFRESH_WAIT: begin
if (phy_ctl_full || phy_cmd_full)
cnt_cmd_r <= #TCQ cnt_cmd_r;
else
cnt_cmd_r <= #TCQ cnt_cmd_r + 1;
end
INIT_WRLVL_WAIT:
cnt_cmd_r <= #TCQ 'b0;
default:
cnt_cmd_r <= #TCQ 'b0;
endcase
end
// pulse when count reaches terminal count
always @(posedge clk)
cnt_cmd_done_r <= #TCQ (cnt_cmd_r == CNTNEXT_CMD);
always @(posedge clk) begin
if (rst)
detect_pi_found_dqs <= #TCQ 1'b0;
else if ((cnt_cmd_r == CNTNEXT_CMD) &&
(init_state_r == INIT_RDLVL_STG2_READ_WAIT))
detect_pi_found_dqs <= #TCQ 1'b1;
else
detect_pi_found_dqs <= #TCQ 1'b0;
end
//*****************************************************************
// Initial delay after power-on for RESET, CKE
// NOTE: Could reduce power consumption by turning off these counters
// after initial power-up (at expense of more logic)
// NOTE: Likely can combine multiple counters into single counter
//*****************************************************************
// Create divided by 1024 version of clock
always @(posedge clk)
if (rst) begin
cnt_pwron_ce_r <= #TCQ 10'h000;
pwron_ce_r <= #TCQ 1'b0;
end else begin
cnt_pwron_ce_r <= #TCQ cnt_pwron_ce_r + 1;
pwron_ce_r <= #TCQ (cnt_pwron_ce_r == 10'h3FF);
end
// "Main" power-on counter - ticks every CLKDIV/1024 cycles
always @(posedge clk)
if (rst)
cnt_pwron_r <= #TCQ 'b0;
else if (pwron_ce_r)
cnt_pwron_r <= #TCQ cnt_pwron_r + 1;
always @(posedge clk)
if (rst || ~phy_ctl_ready) begin
cnt_pwron_reset_done_r <= #TCQ 1'b0;
cnt_pwron_cke_done_r <= #TCQ 1'b0;
end else begin
// skip power-up count for simulation purposes only
if ((SIM_INIT_OPTION == "SKIP_PU_DLY") ||
(SIM_INIT_OPTION == "SKIP_INIT")) begin
cnt_pwron_reset_done_r <= #TCQ 1'b1;
cnt_pwron_cke_done_r <= #TCQ 1'b1;
end else begin
// otherwise, create latched version of done signal for RESET, CKE
if (DRAM_TYPE == "DDR3") begin
if (!cnt_pwron_reset_done_r)
cnt_pwron_reset_done_r
<= #TCQ (cnt_pwron_r == PWRON_RESET_DELAY_CNT);
if (!cnt_pwron_cke_done_r)
cnt_pwron_cke_done_r
<= #TCQ (cnt_pwron_r == PWRON_CKE_DELAY_CNT);
end else begin // DDR2
cnt_pwron_reset_done_r <= #TCQ 1'b1; // not needed
if (!cnt_pwron_cke_done_r)
cnt_pwron_cke_done_r
<= #TCQ (cnt_pwron_r == PWRON_CKE_DELAY_CNT);
end
end
end // else: !if(rst || ~phy_ctl_ready)
always @(posedge clk)
cnt_pwron_cke_done_r1 <= #TCQ cnt_pwron_cke_done_r;
// Keep RESET asserted and CKE deasserted until after power-on delay
always @(posedge clk) begin
phy_reset_n <= #TCQ cnt_pwron_reset_done_r;
// phy_cke <= #TCQ {CKE_WIDTH{cnt_pwron_cke_done_r}};
end
//*****************************************************************
// Counter for tXPR (pronouned "Tax-Payer") - wait time after
// CKE deassertion before first MRS command can be asserted
//*****************************************************************
always @(posedge clk)
if (!cnt_pwron_cke_done_r) begin
cnt_txpr_r <= #TCQ 'b0;
cnt_txpr_done_r <= #TCQ 1'b0;
end else begin
cnt_txpr_r <= #TCQ cnt_txpr_r + 1;
if (!cnt_txpr_done_r)
cnt_txpr_done_r <= #TCQ (cnt_txpr_r == TXPR_DELAY_CNT);
end
//*****************************************************************
// Counter for the initial 400ns wait for issuing precharge all
// command after CKE assertion. Only for DDR2.
//*****************************************************************
always @(posedge clk)
if (!cnt_pwron_cke_done_r) begin
cnt_init_pre_wait_r <= #TCQ 'b0;
cnt_init_pre_wait_done_r <= #TCQ 1'b0;
end else begin
cnt_init_pre_wait_r <= #TCQ cnt_init_pre_wait_r + 1;
if (!cnt_init_pre_wait_done_r)
cnt_init_pre_wait_done_r
<= #TCQ (cnt_init_pre_wait_r >= DDR2_INIT_PRE_CNT);
end
//*****************************************************************
// Wait for both DLL to lock (tDLLK) and ZQ calibration to finish
// (tZQINIT). Both take the same amount of time (512*tCK)
//*****************************************************************
always @(posedge clk)
if (init_state_r == INIT_ZQCL) begin
cnt_dllk_zqinit_r <= #TCQ 'b0;
cnt_dllk_zqinit_done_r <= #TCQ 1'b0;
end else if (~(phy_ctl_full || phy_cmd_full)) begin
cnt_dllk_zqinit_r <= #TCQ cnt_dllk_zqinit_r + 1;
if (!cnt_dllk_zqinit_done_r)
cnt_dllk_zqinit_done_r
<= #TCQ (cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT);
end
//*****************************************************************
// Keep track of which MRS counter needs to be programmed during
// memory initialization
// The counter and the done signal are reset an additional time
// for DDR2. The same signals are used for the additional DDR2
// initialization sequence.
//*****************************************************************
always @(posedge clk)
if ((init_state_r == INIT_IDLE)||
((init_state_r == INIT_REFRESH)
&& (~mem_init_done_r))) begin
cnt_init_mr_r <= #TCQ 'b0;
cnt_init_mr_done_r <= #TCQ 1'b0;
end else if (init_state_r == INIT_LOAD_MR) begin
cnt_init_mr_r <= #TCQ cnt_init_mr_r + 1;
cnt_init_mr_done_r <= #TCQ (cnt_init_mr_r == INIT_CNT_MR_DONE);
end
//*****************************************************************
// Flag to tell if the first precharge for DDR2 init sequence is
// done
//*****************************************************************
always @(posedge clk)
if (init_state_r == INIT_IDLE)
ddr2_pre_flag_r<= #TCQ 'b0;
else if (init_state_r == INIT_LOAD_MR)
ddr2_pre_flag_r<= #TCQ 1'b1;
// reset the flag for multi rank case
else if ((ddr2_refresh_flag_r) &&
(init_state_r == INIT_LOAD_MR_WAIT)&&
(cnt_cmd_done_r) && (cnt_init_mr_done_r))
ddr2_pre_flag_r <= #TCQ 'b0;
//*****************************************************************
// Flag to tell if the refresh stat for DDR2 init sequence is
// reached
//*****************************************************************
always @(posedge clk)
if (init_state_r == INIT_IDLE)
ddr2_refresh_flag_r<= #TCQ 'b0;
else if ((init_state_r == INIT_REFRESH) && (~mem_init_done_r))
// reset the flag for multi rank case
ddr2_refresh_flag_r<= #TCQ 1'b1;
else if ((ddr2_refresh_flag_r) &&
(init_state_r == INIT_LOAD_MR_WAIT)&&
(cnt_cmd_done_r) && (cnt_init_mr_done_r))
ddr2_refresh_flag_r <= #TCQ 'b0;
//*****************************************************************
// Keep track of the number of auto refreshes for DDR2
// initialization. The spec asks for a minimum of two refreshes.
// Four refreshes are performed here. The two extra refreshes is to
// account for the 200 clock cycle wait between step h and l.
// Without the two extra refreshes we would have to have a
// wait state.
//*****************************************************************
always @(posedge clk)
if (init_state_r == INIT_IDLE) begin
cnt_init_af_r <= #TCQ 'b0;
cnt_init_af_done_r <= #TCQ 1'b0;
end else if ((init_state_r == INIT_REFRESH) && (~mem_init_done_r))begin
cnt_init_af_r <= #TCQ cnt_init_af_r + 1;
cnt_init_af_done_r <= #TCQ (cnt_init_af_r == 2'b11);
end
//*****************************************************************
// Keep track of the register control word programming for
// DDR3 RDIMM
//*****************************************************************
always @(posedge clk)
if (init_state_r == INIT_IDLE)
reg_ctrl_cnt_r <= #TCQ 'b0;
else if (init_state_r == INIT_REG_WRITE)
reg_ctrl_cnt_r <= #TCQ reg_ctrl_cnt_r + 1;
always @(posedge clk)
if (init_state_r == INIT_IDLE)
stg1_wr_done <= #TCQ 1'b0;
else if (init_state_r == INIT_RDLVL_STG1_WRITE_READ)
stg1_wr_done <= #TCQ 1'b1;
//***************************************************************************
// Initialization state machine
//***************************************************************************
//*****************************************************************
// Next-state logic
//*****************************************************************
always @(posedge clk)
if (rst)begin
init_state_r <= #TCQ INIT_IDLE;
init_state_r1 <= #TCQ INIT_IDLE;
end else begin
init_state_r <= #TCQ init_next_state;
init_state_r1 <= #TCQ init_state_r;
end
always @(burst_addr_r or chip_cnt_r or cnt_cmd_done_r
or cnt_dllk_zqinit_done_r or cnt_init_af_done_r
or cnt_init_mr_done_r or phy_ctl_ready or phy_ctl_full
or phy_cmd_full or num_reads or dqs_dly_done or stg1_wr_done
// or ck_addr_cmd_delay_done
or cnt_init_pre_wait_done_r or cnt_pwron_cke_done_r
or cnt_txpr_done_r or ddr2_pre_flag_r
or ddr2_refresh_flag_r or ddr3_lm_done_r
or init_state_r or mem_init_done_r
or prech_req_posedge_r or wrcal_done or wrcal_resume
or rdlvl_stg1_done or rdlvl_stg1_rank_done or rdlvl_stg1_start_int
or stg1_wr_rd_cnt or read_calib_int or read_calib_r or pi_calib_done_r
or pi_dqs_found_done or pi_dqs_found_rank_done or pi_dqs_found_start
or reg_ctrl_cnt_r or wrlvl_done_r1 or wrlvl_rank_done_r3) begin
init_next_state = init_state_r;
(* full_case, parallel_case *) case (init_state_r)
//*******************************************************
// DRAM initialization
//*******************************************************
// Initial state - wait for:
// 1. Power-on delays to pass
// 2. PHY Control Block to assert phy_ctl_ready
// 3. PHY Control FIFO must not be FULL
// 4. Read path initialization to finish
INIT_IDLE:
if (cnt_pwron_cke_done_r && phy_ctl_ready
&& ~(phy_ctl_full || phy_cmd_full) && dqs_dly_done) begin
//&& ck_addr_cmd_delay_done) begin
// If skipping memory initialization (simulation only)
if (SIM_INIT_OPTION == "SKIP_INIT")
if (WRLVL == "ON")
// Proceed to write leveling
init_next_state = INIT_WRLVL_START;
else //if (SIM_CAL_OPTION != "SKIP_CAL")
// Proceed to Phaser_In phase lock
init_next_state = INIT_RDLVL_ACT;
// else
// Skip read leveling
//init_next_state = INIT_DONE;
else
init_next_state = INIT_WAIT_CKE_EXIT;
end
// Wait minimum of Reset CKE exit time (tXPR = max(tXS,
INIT_WAIT_CKE_EXIT:
if ((cnt_txpr_done_r) && (DRAM_TYPE == "DDR3")
&& ~(phy_ctl_full || phy_cmd_full)) begin
if((REG_CTRL == "ON") && ((nCS_PER_RANK > 1) ||
(RANKS > 1)))
//register write for reg dimm. Some register chips
// have the register chip in a pre-programmed state
// in that case the nCS_PER_RANK == 1 && RANKS == 1
init_next_state = INIT_REG_WRITE;
else
// Load mode register - this state is repeated multiple times
init_next_state = INIT_LOAD_MR;
end else if ((cnt_init_pre_wait_done_r) && (DRAM_TYPE == "DDR2")
&& ~(phy_ctl_full || phy_cmd_full))
// DDR2 start with a precharge all command
init_next_state = INIT_DDR2_PRECHARGE;
INIT_REG_WRITE:
init_next_state = INIT_REG_WRITE_WAIT;
INIT_REG_WRITE_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin
if(reg_ctrl_cnt_r == 3'd5)
init_next_state = INIT_LOAD_MR;
else
init_next_state = INIT_REG_WRITE;
end
INIT_LOAD_MR:
init_next_state = INIT_LOAD_MR_WAIT;
// After loading MR, wait at least tMRD
INIT_LOAD_MR_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin
// If finished loading all mode registers, proceed to next step
if(rdlvl_stg1_done && pi_dqs_found_done)
// for ddr3 when the correct burst length is writtern at end
init_next_state = INIT_PRECHARGE;
else if (cnt_init_mr_done_r)begin
if(DRAM_TYPE == "DDR3")
init_next_state = INIT_ZQCL;
else begin //DDR2
if(ddr2_refresh_flag_r)begin
// memory initialization per rank for multi-rank case
if (!mem_init_done_r && (chip_cnt_r <= RANKS-1))
init_next_state = INIT_DDR2_MULTI_RANK;
else
init_next_state = INIT_RDLVL_ACT;
// ddr2 initialization done.load mode state after refresh
end else
init_next_state = INIT_DDR2_PRECHARGE;
end
end else
init_next_state = INIT_LOAD_MR;
end // if (cnt_cmd_done_r)
// DDR2 multi rank transition state
INIT_DDR2_MULTI_RANK:
init_next_state = INIT_DDR2_MULTI_RANK_WAIT;
INIT_DDR2_MULTI_RANK_WAIT:
init_next_state = INIT_DDR2_PRECHARGE;
// Initial ZQ calibration
INIT_ZQCL:
init_next_state = INIT_WAIT_DLLK_ZQINIT;
// Wait until both DLL have locked, and ZQ calibration done
INIT_WAIT_DLLK_ZQINIT:
if (cnt_dllk_zqinit_done_r && ~(phy_ctl_full || phy_cmd_full))
// memory initialization per rank for multi-rank case
if (!mem_init_done_r && (chip_cnt_r <= RANKS-1))
init_next_state = INIT_LOAD_MR;
else if (WRLVL == "ON")
init_next_state = INIT_WRLVL_START;
else
// skip write-leveling (e.g. for DDR2 interface)
init_next_state = INIT_RDLVL_ACT;
// Initial precharge for DDR2
INIT_DDR2_PRECHARGE:
init_next_state = INIT_DDR2_PRECHARGE_WAIT;
INIT_DDR2_PRECHARGE_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin
if(ddr2_pre_flag_r)
init_next_state = INIT_REFRESH;
else// from precharge state initally go to load mode
init_next_state = INIT_LOAD_MR;
end
INIT_REFRESH:
init_next_state = INIT_REFRESH_WAIT;
INIT_REFRESH_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))begin
if(cnt_init_af_done_r && (~mem_init_done_r))
// go to lm state as part of DDR2 init sequence
init_next_state = INIT_LOAD_MR;
else if (((rdlvl_stg1_done && pi_dqs_found_done) && (WRLVL == "ON"))
&& mem_init_done_r)
init_next_state = INIT_WRCAL_ACT;
else if (mem_init_done_r)
init_next_state = INIT_RDLVL_ACT;
else // to DDR2 init state as part of DDR2 init sequence
init_next_state = INIT_REFRESH;
end
//******************************************************
// Write Leveling
//*******************************************************
// Enable write leveling in MR1 and start write leveling
// for current rank
INIT_WRLVL_START:
init_next_state = INIT_WRLVL_WAIT;
// Wait for both MR load and write leveling to complete
// (write leveling should take much longer than MR load..)
INIT_WRLVL_WAIT:
if (wrlvl_rank_done_r3 && ~(phy_ctl_full || phy_cmd_full))
init_next_state = INIT_WRLVL_LOAD_MR;
// Disable write leveling in MR1 for current rank
INIT_WRLVL_LOAD_MR:
init_next_state = INIT_WRLVL_LOAD_MR_WAIT;
INIT_WRLVL_LOAD_MR_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))
init_next_state = INIT_WRLVL_LOAD_MR2;
// Load MR2 to set ODT: Dynamic ODT for single rank case
// And ODTs for multi-rank case as well
INIT_WRLVL_LOAD_MR2:
init_next_state = INIT_WRLVL_LOAD_MR2_WAIT;
// Wait tMRD before proceeding
INIT_WRLVL_LOAD_MR2_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin
if (~wrlvl_done_r1)
init_next_state = INIT_WRLVL_START;
else if (SIM_CAL_OPTION == "SKIP_CAL")
// If skip rdlvl, then we're done
init_next_state = INIT_DONE;
else
// Otherwise, proceed to read leveling
init_next_state = INIT_RDLVL_ACT;
end
//*******************************************************
// Read Leveling
//*******************************************************
// single row activate. All subsequent read leveling writes and
// read will take place in this row
INIT_RDLVL_ACT:
init_next_state = INIT_RDLVL_ACT_WAIT;
// hang out for awhile before issuing subsequent column commands
// it's also possible to reach this state at various points
// during read leveling - determine what the current stage is
INIT_RDLVL_ACT_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin
// Just finished an activate. Now either write, read, or precharge
// depending on where we are in the training sequence
if (read_calib_int && !read_calib_r)
init_next_state = INIT_PI_PHASELOCK_READS;
else if (!pi_dqs_found_done)
// (!pi_dqs_found_start || pi_dqs_found_rank_done))
init_next_state = INIT_RDLVL_STG2_READ;
else if (!rdlvl_stg1_done && ~stg1_wr_done)
// (!rdlvl_stg1_start_int || rdlvl_stg1_rank_done))
// Case 1: If in stage 1, and entering for first then, then
// write training pattern to memory
//init_next_state = INIT_IOCONFIG_WR;
init_next_state = INIT_RDLVL_STG1_WRITE;
else if (!rdlvl_stg1_done && rdlvl_stg1_start_int)
// Case 2: If in stage 1, and just precharged after training
// previous byte, then continue reading
init_next_state = INIT_RDLVL_STG1_READ;
else
// Otherwise, if we're finished with calibration, then precharge
// the row - silly, because we just opened it - possible to take
// this out by adding logic to avoid the ACT in first place. Make
// sure that cnt_cmd_done will handle tRAS(min)
init_next_state = INIT_PRECHARGE_PREWAIT;
end
//**************************************************
// Back-to-back reads for Phaser_IN Phase locking
// DQS to FREQ_REF clock
//**************************************************
INIT_PI_PHASELOCK_READS:
if (pi_calib_done_r)
init_next_state = INIT_PRECHARGE_PREWAIT;
//*********************************************
// Stage 1 read-leveling (write and continuous read)
//*********************************************
// Write training pattern for stage 1
// PRBS pattern of TBD length
INIT_RDLVL_STG1_WRITE:
// 4:1 DDR3 BL8 will require all 8 words in 1 DIV4 clock cycle
// 2:1 DDR2/DDR3 BL8 will require 2 DIV2 clock cycles for 8 words
// 2:1 DDR2 BL4 will require 1 DIV2 clock cycle for 4 words
// An entire row worth of writes issued before proceeding to reads
// The number of write is (2^column width)/burst length to accomodate
// PRBS pattern for window detection.
if (stg1_wr_rd_cnt == 9'd1)
init_next_state = INIT_RDLVL_STG1_WRITE_READ;
// Write-read turnaround
INIT_RDLVL_STG1_WRITE_READ:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))
init_next_state = INIT_RDLVL_STG1_READ;
// Continuous read, where interruptible by precharge request from
// calibration logic. Also precharges when stage 1 is complete
// No precharges when reads provided to Phaser_IN for phase locking
// FREQ_REF to read DQS since data integrity is not important.
INIT_RDLVL_STG1_READ:
if (rdlvl_stg1_rank_done || rdlvl_stg1_done || prech_req_posedge_r)
init_next_state = INIT_PRECHARGE_PREWAIT;
//*********************************************
// Stage 2 read-leveling (alternate writes and set of 4 reads)
//*********************************************
// Read of training data. Note that Stage 2 is not a constant read,
// instead there is a large gap between each set of back-to-back reads
INIT_RDLVL_STG2_READ:
// 4 read commands issued back-to-back
//if (burst_addr_r == 1'b1)
if (num_reads == 'b1)
init_next_state = INIT_RDLVL_STG2_READ_WAIT;
// Wait before issuing the next set of reads. If a precharge request
// comes in then handle it
INIT_RDLVL_STG2_READ_WAIT:
if (~(phy_ctl_full || phy_cmd_full)) begin
if (pi_dqs_found_rank_done ||
pi_dqs_found_done || prech_req_posedge_r)
init_next_state = INIT_PRECHARGE_PREWAIT;
else if (cnt_cmd_done_r)
init_next_state = INIT_RDLVL_STG2_READ;
end
//*********************************************
// Write calibration
//*********************************************
// single row activate
INIT_WRCAL_ACT:
init_next_state = INIT_WRCAL_ACT_WAIT;
// hang out for awhile before issuing subsequent column command
INIT_WRCAL_ACT_WAIT:
if (cnt_cmd_done_r)
init_next_state = INIT_WRCAL_WRITE;
// Write training pattern for write calibration
INIT_WRCAL_WRITE:
// Once we've issued enough commands for 8 words - proceed to reads
if (burst_addr_r == 1'b1)
init_next_state = INIT_WRCAL_WRITE_READ;
// Write-read turnaround
INIT_WRCAL_WRITE_READ:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))
init_next_state = INIT_WRCAL_READ;
INIT_WRCAL_READ:
if (burst_addr_r == 1'b1)
init_next_state = INIT_WRCAL_READ_WAIT;
INIT_WRCAL_READ_WAIT:
if (~(phy_ctl_full || phy_cmd_full)) begin
if (wrcal_resume)
init_next_state = INIT_WRCAL_WRITE;
else if (wrcal_done || prech_req_posedge_r)
init_next_state = INIT_PRECHARGE_PREWAIT;
// else if (cnt_cmd_done_r)
// init_next_state = INIT_WRCAL_READ;
end
//*********************************************
// Handling of precharge during and in between read-level stages
//*********************************************
// Make sure we aren't violating any timing specs by precharging
// immediately
INIT_PRECHARGE_PREWAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))
init_next_state = INIT_PRECHARGE;
// Initiate precharge
INIT_PRECHARGE:
init_next_state = INIT_PRECHARGE_WAIT;
INIT_PRECHARGE_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin
if ((wrcal_done || (WRLVL == "OFF")) && rdlvl_stg1_done &&
pi_dqs_found_done && ((ddr3_lm_done_r) || (DRAM_TYPE == "DDR2")))
// If read leveling and phase detection calibration complete,
// and programing the correct burst length then we're finished
init_next_state = INIT_DONE;
else if ((wrcal_done || (WRLVL == "OFF")) && rdlvl_stg1_done
&& pi_dqs_found_done)
// after all calibration program the correct burst length
init_next_state = INIT_LOAD_MR;
else if (rdlvl_stg1_done && pi_dqs_found_done && (WRLVL == "ON"))
// If read leveling finished, proceed to write calibration
init_next_state = INIT_REFRESH;
else
// Otherwise, open row for read-leveling purposes
init_next_state = INIT_REFRESH;
end
//*******************************************************
// Initialization/Calibration done. Take a long rest, relax
//*******************************************************
INIT_DONE:
init_next_state = INIT_DONE;
endcase
end
//*****************************************************************
// Initialization done signal - asserted before leveling starts
//*****************************************************************
always @(posedge clk)
if (rst)
mem_init_done_r <= #TCQ 1'b0;
else if ((!cnt_dllk_zqinit_done_r &&
(cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT) &&
(chip_cnt_r == RANKS-1) && (DRAM_TYPE == "DDR3"))
|| ( (init_state_r == INIT_LOAD_MR_WAIT) &&
(ddr2_refresh_flag_r) && (chip_cnt_r == RANKS-1)
&& (cnt_init_mr_done_r) && (DRAM_TYPE == "DDR2")))
mem_init_done_r <= #TCQ 1'b1;
//*****************************************************************
// Write Calibration signal to PHY Control Block - asserted before
// Write Leveling starts
//*****************************************************************
always @(posedge clk) begin
if (rst || done_dqs_tap_inc)
write_calib <= #TCQ 1'b0;
else if (wrlvl_active_r1)
write_calib <= #TCQ 1'b1;
end
//*****************************************************************
// Read Calibration signal to PHY Control Block - asserted after
// Write Leveling during PHASER_IN phase locking stage.
// Must be de-asserted before Read Leveling
//*****************************************************************
always @(posedge clk) begin
if (rst || pi_calib_done_r)
read_calib_int <= #TCQ 1'b0;
else if (~pi_calib_done_r && (init_state_r == INIT_RDLVL_ACT_WAIT) &&
(cnt_cmd_r == CNTNEXT_CMD))
read_calib_int <= #TCQ 1'b1;
end
always @(posedge clk)
read_calib_r <= #TCQ read_calib_int;
always @(posedge clk) begin
if (rst || pi_calib_done_r)
read_calib <= #TCQ 1'b0;
else if (~pi_calib_done_r && (init_state_r == INIT_PI_PHASELOCK_READS))
read_calib <= #TCQ 1'b1;
end
always @(posedge clk)
if (rst)
pi_calib_done_r <= #TCQ 1'b0;
else if (pi_phase_locked_all)
pi_calib_done_r <= #TCQ 1'b1;
//*****************************************************************
// DDR3 final burst length programming done. For DDR3 during
// calibration the burst length is fixed to BL8. After calibration
// the correct burst length is programmed.
//*****************************************************************
always @(posedge clk)
if (rst)
ddr3_lm_done_r <= #TCQ 1'b0;
else if ((init_state_r == INIT_LOAD_MR_WAIT) &&
(chip_cnt_r == RANKS-1) && wrcal_done)
ddr3_lm_done_r <= #TCQ 1'b1;
always @(posedge clk)
pi_dqs_found_rank_done_r <= #TCQ pi_dqs_found_rank_done;
//***************************************************************************
// Logic for deep memory (multi-rank) configurations
//
//***************************************************************************
// For DDR3 asserted when
always @(posedge clk)
if (rst || (wrlvl_done_r &&
(init_state_r==INIT_WRLVL_LOAD_MR2_WAIT)))begin
chip_cnt_r <= #TCQ 2'b00;
end else if ((((init_state_r == INIT_WAIT_DLLK_ZQINIT) &&
(cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT)) ||
((init_state_r!=INIT_WRLVL_LOAD_MR2_WAIT) &&
(init_next_state==INIT_WRLVL_LOAD_MR2_WAIT)) &&
(DRAM_TYPE == "DDR3")) ||
rdlvl_stg1_rank_done ||
(pi_dqs_found_rank_done && ~pi_dqs_found_rank_done_r) ||
((init_state_r == INIT_LOAD_MR_WAIT)&& cnt_cmd_done_r
&& wrcal_done) ||
((init_state_r == INIT_DDR2_MULTI_RANK)
&& (DRAM_TYPE == "DDR2"))) begin
if ((~mem_init_done_r || ~rdlvl_stg1_done || ~pi_dqs_found_done ||
// condition to increment chip_cnt during
// final burst length programming for DDR3
wrcal_done)
&& (chip_cnt_r != RANKS-1))
chip_cnt_r <= #TCQ chip_cnt_r + 1;
else
chip_cnt_r <= #TCQ 2'b00;
end
generate
if (DRAM_TYPE == "DDR3") begin: DDR3
always @(posedge clk)
if (rst)
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
else if (RANKS == 1)
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b0}};
else begin
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
case (chip_cnt_r)
2'b00:begin
for (n = 0; n < nCS_PER_RANK*nCK_PER_CLK*2; n = n + (nCS_PER_RANK*2)) begin
phy_int_cs_n[n+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}};
end
end
2'b01:begin
for (p = nCS_PER_RANK; p < nCS_PER_RANK*nCK_PER_CLK*2; p = p + (nCS_PER_RANK*2)) begin
phy_int_cs_n[p+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}};
end
end
endcase
end
end else begin: DDR2
always @(posedge clk)
if (rst) begin
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
end else begin
if (init_state_r == INIT_REG_WRITE) begin
// All ranks selected simultaneously
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b0}};
end else if ((wrlvl_odt) ||
(init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_ZQCL) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_PI_PHASELOCK_READS) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_RDLVL_STG1_READ) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_WRCAL_ACT) ||
(init_state_r == INIT_WRCAL_READ) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_DDR2_PRECHARGE) ||
(init_state_r == INIT_REFRESH)) begin
// phy_int_cs_n <= #TCQ phy_tmp_cs1_r;
phy_int_cs_n[0] <= #TCQ 1'b0;
end
else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
end // else: !if(rst)
end // block: DDR2
endgenerate
assign phy_cs_n = phy_int_cs_n;
//***************************************************************************
// Write/read burst logic for calibration
//***************************************************************************
assign rdlvl_wr = (init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE);
assign rdlvl_rd = (init_state_r == INIT_PI_PHASELOCK_READS) ||
(init_state_r == INIT_RDLVL_STG1_READ) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_WRCAL_READ);
assign rdlvl_wr_rd = rdlvl_wr | rdlvl_rd;
// keep track of current address - need this if burst length < 8 for
// calibration reads and writes. Make sure value always gets initialized
// to 0 before we enter write/read state. Used to keep track of when
// another burst must be issued on command/address bus
// Least significant two bits of address bus are always 2'b00 when
// command issued. Only bit[3] will vary depending on the burst length
// LS 3-bits of address to DRAM = {burst_addr, 2'b00}. This can be expanded
// for more bits if the training sequence is longer than 8 words
generate
if (nCK_PER_CLK == 4) begin:DIV4
always @(posedge clk)
if (rst || wrcal_done)
burst_addr_r <= #TCQ 1'b0;
else if ((init_state_r == INIT_WRCAL_ACT_WAIT) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE_READ) ||
(init_state_r == INIT_WRCAL_READ) ||
(init_state_r == INIT_WRCAL_READ_WAIT))
burst_addr_r <= #TCQ 1'b1;
else if (rdlvl_wr_rd)
burst_addr_r <= #TCQ ~burst_addr_r;
else
burst_addr_r <= #TCQ 1'b0;
end else begin: DIV2
always @(posedge clk)
// Address increments by
if (rdlvl_wr_rd)
burst_addr_r <= #TCQ ~burst_addr_r;
else
burst_addr_r <= #TCQ 1'b0;
end
endgenerate
// Read Level Stage 1 requires writes to the entire row since
// a PRBS pattern is being written. This counter keeps track
// of the number of writes which depends on the column width
// The (stg1_wr_rd_cnt==9'd0) condition was added so the col
// address wraps around during stage1 reads
always @(posedge clk)
if (rst || (init_state_r == INIT_RDLVL_STG1_WRITE_READ) ||
rdlvl_stg1_done || (stg1_wr_rd_cnt==9'd0))
stg1_wr_rd_cnt <= #TCQ NUM_STG1_WR_RD;
else if (init_state_r == INIT_RDLVL_STG1_WRITE)// ||
// (init_state_r == INIT_RDLVL_STG1_READ))
stg1_wr_rd_cnt <= #TCQ stg1_wr_rd_cnt - 1;
// 4 back-to-back reads with gaps for
// read data_offset calibration (rdlvl stage 2)
always @(posedge clk)
if (rst || (init_state_r == INIT_RDLVL_STG2_READ_WAIT))
num_reads <= #TCQ 2'b00;
else if ((num_reads > 2'b00) && ~(phy_ctl_full || phy_cmd_full))
num_reads <= #TCQ num_reads - 1;
else if ((init_state_r == INIT_RDLVL_STG2_READ) || phy_ctl_full || phy_cmd_full)
num_reads <= #TCQ 2'b11;
// determine how often to issue row command during read leveling writes
// and reads
always @(posedge clk)
if (rdlvl_wr_rd) begin
// if (BURST4_FLAG)
// new_burst_r <= #TCQ 1'b1;
// else
// new_burst_r <= #TCQ ~new_burst_r;
// end else
new_burst_r <= #TCQ 1'b1;
end
// indicate when a write is occurring. PHY_WRDATA_EN must be asserted
// simultaneous with the corresponding command/address for CWL = 5,6
always @(posedge clk) begin
rdlvl_wr_r <= #TCQ rdlvl_wr;
calib_wrdata_en <= #TCQ phy_wrdata_en;
end
generate
if ((nCK_PER_CLK == 4) || (BURST_MODE == "4")) begin: wrdqen_div4
// Write data enable asserted for one DIV4 clock cycle
// Only BL8 supported with DIV4. DDR2 BL4 will use DIV2.
always @(rst or phy_data_full or init_state_r) begin
//always @(posedge clk) begin
if (rst)
phy_wrdata_en = 1'b0;
else if (~phy_data_full && ((init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE)))
phy_wrdata_en = 1'b1;
else
phy_wrdata_en = 1'b0;
end
end else begin: wrdqen_div2
// For DDR2 BL8 when DIV2 mode is used phy_wrdata_en must be asserted for
// 2 DIV2 clock cycles because 4 words are output per DIV2 clock cycle.
always @(rdlvl_wr or rdlvl_wr_r)
phy_wrdata_en = rdlvl_wr | rdlvl_wr_r;
end
endgenerate
// indicate when a write is occurring. PHY_RDDATA_EN must be asserted
// simultaneous with the corresponding command/address. PHY_RDDATA_EN
// is used during read-leveling to determine read latency
assign phy_rddata_en = ~phy_if_empty;
// Read data valid generation for MC and User Interface after calibration is
// complete
assign phy_rddata_valid = (init_complete_r1) ? phy_rddata_en : 1'b0;
//***************************************************************************
// Generate training data written at start of each read-leveling stage
// For every stage of read leveling, 8 words are written into memory
// The format is as follows (shown as {rise,fall}):
// Stage 1: 0xF, 0x0, 0xF, 0x0, 0xF, 0x0, 0xF, 0x0
// Stage 2: 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6
//***************************************************************************
always @(posedge clk)
if ((init_state_r == INIT_IDLE) ||
(init_state_r == INIT_RDLVL_STG1_WRITE))
cnt_init_data_r <= #TCQ 2'b00;
else if (phy_wrdata_en)
cnt_init_data_r <= #TCQ cnt_init_data_r + 1;
else if (init_state_r == INIT_WRCAL_WRITE)
cnt_init_data_r <= #TCQ 2'b10;
always @(posedge clk) begin
prbs_r1 <= #TCQ prbs_o;
prbs_r2 <= #TCQ prbs_r1;
prbs_r3 <= #TCQ prbs_r2;
prbs_r4 <= #TCQ prbs_r3;
prbs_r5 <= #TCQ prbs_r4;
prbs_r6 <= #TCQ prbs_r5;
prbs_r7 <= #TCQ prbs_r6;
end
generate
if (nCK_PER_CLK == 4) begin: wrdq_div4_bl8
always @(posedge clk)
if (phy_wrdata_en && (!rdlvl_stg1_done)) //phy_wrdata_en
// Replace with PRBS pattern
phy_wrdata <= #TCQ {prbs_o[DQ_WIDTH-1:0],prbs_r1[DQ_WIDTH-1:0],
prbs_r2[DQ_WIDTH-1:0],prbs_r3[DQ_WIDTH-1:0],
prbs_r4[DQ_WIDTH-1:0],prbs_r5[DQ_WIDTH-1:0],
prbs_r6[DQ_WIDTH-1:0],prbs_r7[DQ_WIDTH-1:0]};
else if (phy_wrdata_en && rdlvl_stg1_done) //phy_wrdata_en
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}},
{DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}},
{DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}},
{DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}};
end else begin: wrdq_div2_bl4_8
always @(posedge clk)
(* full_case, parallel_case *) case (cnt_init_data_r)
// Replace with PRBS pattern
2'b00:
phy_wrdata <= #TCQ {prbs_o[DQ_WIDTH-1:0],prbs_r1[DQ_WIDTH-1:0],
prbs_r2[DQ_WIDTH-1:0],prbs_r3[DQ_WIDTH-1:0]};
// Replace with PRBS pattern
2'b01:
phy_wrdata <= #TCQ {prbs_r4[DQ_WIDTH-1:0],prbs_r5[DQ_WIDTH-1:0],
prbs_r6[DQ_WIDTH-1:0],prbs_r7[DQ_WIDTH-1:0]};
2'b10:
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}},
{DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}};
2'b11:
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}},
{DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}}};
endcase
end
endgenerate
//***************************************************************************
// Memory control/address
//***************************************************************************
generate
if (nCK_PER_CLK == 4) begin: div_4
// Assert RAS when: (1) Loading MRS, (2) Activating Row, (3) Precharging
// (4) auto refresh
if (!(CWL_M % 2)) begin: even_cwl
always @(posedge clk) begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_REG_WRITE) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_WRCAL_ACT) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE) ||
(init_state_r == INIT_REFRESH))begin
phy_ras_n[0] <= #TCQ 1'b0;
phy_ras_n[1] <= #TCQ 1'b1;
phy_ras_n[2] <= #TCQ 1'b1;
phy_ras_n[3] <= #TCQ 1'b1;
end else begin
phy_ras_n[0] <= #TCQ 1'b1;
phy_ras_n[1] <= #TCQ 1'b1;
phy_ras_n[2] <= #TCQ 1'b1;
phy_ras_n[3] <= #TCQ 1'b1;
end
end
// Assert CAS when: (1) Loading MRS, (2) Issuing Read/Write command
// (3) auto refresh
always @(posedge clk) begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_REG_WRITE) ||
(init_state_r == INIT_WRLVL_START) ||
// ((init_state_r == INIT_WRLVL_WAIT) && wr_level_dqs_asrt) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_REFRESH) ||
(rdlvl_wr_rd && new_burst_r))begin
phy_cas_n[0] <= #TCQ 1'b0;
phy_cas_n[1] <= #TCQ 1'b1;
phy_cas_n[2] <= #TCQ 1'b1;
phy_cas_n[3] <= #TCQ 1'b1;
end else begin
phy_cas_n[0] <= #TCQ 1'b1;
phy_cas_n[1] <= #TCQ 1'b1;
phy_cas_n[2] <= #TCQ 1'b1;
phy_cas_n[3] <= #TCQ 1'b1;
end
end
// Assert WE when: (1) Loading MRS, (2) Issuing Write command (only
// occur during read leveling), (3) Issuing ZQ Long Calib command,
// (4) Precharge
always @(posedge clk) begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_REG_WRITE) ||
(init_state_r == INIT_ZQCL) ||
(init_state_r == INIT_WRLVL_START) ||
// ((init_state_r == INIT_WRLVL_WAIT) && wr_level_dqs_asrt) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE)||
(rdlvl_wr && new_burst_r))begin
phy_we_n[0] <= #TCQ 1'b0;
phy_we_n[1] <= #TCQ 1'b1;
phy_we_n[2] <= #TCQ 1'b1;
phy_we_n[3] <= #TCQ 1'b1;
end else begin
phy_we_n[0] <= #TCQ 1'b1;
phy_we_n[1] <= #TCQ 1'b1;
phy_we_n[2] <= #TCQ 1'b1;
phy_we_n[3] <= #TCQ 1'b1;
end
end // even_cwl
end else begin: odd_cwl
always @(posedge clk) begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_REG_WRITE) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_WRCAL_ACT) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE) ||
(init_state_r == INIT_REFRESH))begin
phy_ras_n[0] <= #TCQ 1'b1;
phy_ras_n[1] <= #TCQ 1'b0;
phy_ras_n[2] <= #TCQ 1'b1;
phy_ras_n[3] <= #TCQ 1'b1;
end else begin
phy_ras_n[0] <= #TCQ 1'b1;
phy_ras_n[1] <= #TCQ 1'b1;
phy_ras_n[2] <= #TCQ 1'b1;
phy_ras_n[3] <= #TCQ 1'b1;
end
end
// Assert CAS when: (1) Loading MRS, (2) Issuing Read/Write command
// (3) auto refresh
always @(posedge clk) begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_REG_WRITE) ||
(init_state_r == INIT_WRLVL_START) ||
// ((init_state_r == INIT_WRLVL_WAIT) && wr_level_dqs_asrt) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_REFRESH) ||
(rdlvl_wr_rd && new_burst_r))begin
phy_cas_n[0] <= #TCQ 1'b1;
phy_cas_n[1] <= #TCQ 1'b0;
phy_cas_n[2] <= #TCQ 1'b1;
phy_cas_n[3] <= #TCQ 1'b1;
end else begin
phy_cas_n[0] <= #TCQ 1'b1;
phy_cas_n[1] <= #TCQ 1'b1;
phy_cas_n[2] <= #TCQ 1'b1;
phy_cas_n[3] <= #TCQ 1'b1;
end
end
// Assert WE when: (1) Loading MRS, (2) Issuing Write command (only
// occur during read leveling), (3) Issuing ZQ Long Calib command,
// (4) Precharge
always @(posedge clk) begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_REG_WRITE) ||
(init_state_r == INIT_ZQCL) ||
(init_state_r == INIT_WRLVL_START) ||
// ((init_state_r == INIT_WRLVL_WAIT) && wr_level_dqs_asrt) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE)||
(rdlvl_wr && new_burst_r))begin
phy_we_n[0] <= #TCQ 1'b1;
phy_we_n[1] <= #TCQ 1'b0;
phy_we_n[2] <= #TCQ 1'b1;
phy_we_n[3] <= #TCQ 1'b1;
end else begin
phy_we_n[0] <= #TCQ 1'b1;
phy_we_n[1] <= #TCQ 1'b1;
phy_we_n[2] <= #TCQ 1'b1;
phy_we_n[3] <= #TCQ 1'b1;
end
end
end // even_cwl
end else begin: div_2
// Assert RAS when: (1) Loading MRS, (2) Activating Row, (3) Precharging
// (4) auto refresh
always @(posedge clk) begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_REG_WRITE) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_WRCAL_ACT) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE) ||
(init_state_r == INIT_REFRESH))begin
phy_ras_n[0] <= #TCQ 1'b0;
phy_ras_n[1] <= #TCQ 1'b0;
end else begin
phy_ras_n[0] <= #TCQ 1'b1;
phy_ras_n[1] <= #TCQ 1'b1;
end
end
// Assert CAS when: (1) Loading MRS, (2) Issuing Read/Write command
// (3) auto refresh
always @(posedge clk) begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_REG_WRITE) ||
(init_state_r == INIT_WRLVL_START) ||
// ((init_state_r == INIT_WRLVL_WAIT) && wr_level_dqs_asrt) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_REFRESH) ||
(rdlvl_wr_rd && new_burst_r))begin
phy_cas_n[0] <= #TCQ 1'b0;
phy_cas_n[1] <= #TCQ 1'b0;
end else begin
phy_cas_n[0] <= #TCQ 1'b1;
phy_cas_n[1] <= #TCQ 1'b1;
end
end
// Assert WE when: (1) Loading MRS, (2) Issuing Write command (only
// occur during read leveling), (3) Issuing ZQ Long Calib command,
// (4) Precharge
always @(posedge clk) begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_REG_WRITE) ||
(init_state_r == INIT_ZQCL) ||
(init_state_r == INIT_WRLVL_START) ||
// ((init_state_r == INIT_WRLVL_WAIT) && wr_level_dqs_asrt) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE)||
(rdlvl_wr && new_burst_r))begin
phy_we_n[0] <= #TCQ 1'b0;
phy_we_n[1] <= #TCQ 1'b0;
end else begin
phy_we_n[0] <= #TCQ 1'b1;
phy_we_n[1] <= #TCQ 1'b1;
end
end
end
endgenerate
// Assign calib_cmd for the command field in PHY_Ctl_Word
always @(posedge clk) begin
if (wr_level_dqs_asrt) begin
// Request to toggle DQS during write leveling
calib_cmd <= #TCQ 3'b001;
if (CWL_M % 2) // odd write latency
calib_data_offset <= #TCQ CWL_M + 3;
else // even write latency
calib_data_offset <= #TCQ CWL_M + 2;
end else if (rdlvl_wr && new_burst_r) begin
// Write Command
calib_cmd <= #TCQ 3'b001;
if (CWL_M % 2) // odd write latency
calib_data_offset <= #TCQ CWL_M + 3;
else // even write latency
calib_data_offset <= #TCQ CWL_M + 2;
end else if (rdlvl_rd && new_burst_r) begin
// Read Command
calib_cmd <= #TCQ 3'b011;
if (~pi_calib_done_r)
calib_data_offset <= #TCQ 6'd0;
else if (~pi_dqs_found_done_r1)
calib_data_offset <= #TCQ rd_data_offset;
else
calib_data_offset <= #TCQ rd_data_offset_ranks[6*chip_cnt_r+:6];
end else begin
// Non-Data Commands like NOP, MRS, ZQ Long Cal, Precharge,
// Active, Refresh
calib_cmd <= #TCQ 3'b100;
calib_data_offset <= #TCQ 6'd0;
end
end
// Write Enable to PHY_Control FIFO always asserted
// No danger of this FIFO being Full with 4:1 sync clock ratio
// This is also the write enable to the command OUT_FIFO
always @(posedge clk) begin
if (rst) begin
calib_ctl_wren <= #TCQ 1'b0;
calib_cmd_wren <= #TCQ 1'b0;
calib_seq <= #TCQ 2'b00;
end else if (cnt_pwron_cke_done_r && phy_ctl_ready
&& ~(phy_ctl_full || phy_cmd_full)) begin
// && ck_addr_cmd_delay_done) begin
calib_ctl_wren <= #TCQ 1'b1;
calib_cmd_wren <= #TCQ 1'b1;
calib_seq <= #TCQ calib_seq + 1;
end else begin
calib_ctl_wren <= #TCQ 1'b0;
calib_cmd_wren <= #TCQ 1'b0;
calib_seq <= #TCQ calib_seq;
end
end
generate
genvar rnk_i;
for (rnk_i = 0; rnk_i < 4; rnk_i = rnk_i + 1) begin: gen_rnk
always @(posedge clk) begin
if (rst) begin
mr2_r[rnk_i] <= #TCQ 2'b00;
mr1_r[rnk_i] <= #TCQ 3'b000;
end else begin
mr2_r[rnk_i] <= #TCQ tmp_mr2_r[rnk_i];
mr1_r[rnk_i] <= #TCQ tmp_mr1_r[rnk_i];
end
end
end
endgenerate
// ODT assignment based on slot config and slot present
// For single slot systems slot_1_present input will be ignored
// Assuming component interfaces to be single slot systems
generate
if (nSLOTS == 1) begin: gen_single_slot_odt
always @(posedge clk) begin
tmp_mr2_r[1] <= #TCQ 2'b00;
tmp_mr2_r[2] <= #TCQ 2'b00;
tmp_mr2_r[3] <= #TCQ 2'b00;
tmp_mr1_r[1] <= #TCQ 3'b000;
tmp_mr1_r[2] <= #TCQ 3'b000;
tmp_mr1_r[3] <= #TCQ 3'b000;
phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}};
phy_tmp_odt_r <= #TCQ 4'b0000;
phy_tmp_odt_r1 <= #TCQ phy_tmp_odt_r;
case ({slot_0_present[0],slot_0_present[1],
slot_0_present[2],slot_0_present[3]})
// Single slot configuration with quad rank
// Assuming same behavior as single slot dual rank for now
// DDR2 does not have quad rank parts
4'b1111: begin
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ 3'b000;
end
phy_tmp_odt_r <= #TCQ 4'b0001;
// Chip Select assignments
phy_tmp_cs1_r[((chip_cnt_r*nCS_PER_RANK)
) +: nCS_PER_RANK] <= #TCQ 'b0;
end
// Single slot configuration with single rank
4'b1000: begin
phy_tmp_odt_r <= #TCQ 4'b0001;
if ((REG_CTRL == "ON") && (nCS_PER_RANK > 1)) begin
phy_tmp_cs1_r[chip_cnt_r] <= #TCQ 1'b0;
end else begin
phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
end
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done)) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
// Single slot configuration with dual rank
4'b1100: begin
phy_tmp_odt_r <= #TCQ 4'b0001;
// Chip Select assignments
phy_tmp_cs1_r[((chip_cnt_r*nCS_PER_RANK)
) +: nCS_PER_RANK] <= #TCQ 'b0;
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
default: begin
phy_tmp_odt_r <= #TCQ 4'b0001;
phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done)) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
endcase // case({slot_0_present[0],slot_0_present[1],...
end
end else if (nSLOTS == 2) begin: gen_dual_slot_odt
always @ (posedge clk) begin
tmp_mr2_r[1] <= #TCQ 2'b00;
tmp_mr2_r[2] <= #TCQ 2'b00;
tmp_mr2_r[3] <= #TCQ 2'b00;
tmp_mr1_r[1] <= #TCQ 3'b000;
tmp_mr1_r[2] <= #TCQ 3'b000;
tmp_mr1_r[3] <= #TCQ 3'b000;
phy_tmp_odt_r <= #TCQ 4'b0000;
phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}};
phy_tmp_odt_r1 <= #TCQ phy_tmp_odt_r;
case ({slot_0_present[0],slot_0_present[1],
slot_1_present[0],slot_1_present[1]})
// Two slot configuration, one slot present, single rank
4'b10_00: begin
if (//wrlvl_odt ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE)) begin
// odt turned on only during write
phy_tmp_odt_r <= #TCQ 4'b0001;
end
phy_tmp_cs1_r <= #TCQ {nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done)) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
4'b00_10: begin
//Rank1 ODT enabled
if (//wrlvl_odt ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE)) begin
// odt turned on only during write
phy_tmp_odt_r <= #TCQ 4'b0001;
end
phy_tmp_cs1_r <= #TCQ {nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done)) begin
//Rank1 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank1 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
// Two slot configuration, one slot present, dual rank
4'b00_11: begin
if (//wrlvl_odt ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE)) begin
// odt turned on only during write
phy_tmp_odt_r
<= #TCQ 4'b0001;
end
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
4'b11_00: begin
if (//wrlvl_odt ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE)) begin
// odt turned on only during write
phy_tmp_odt_r <= #TCQ 4'b0001;
end
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank1 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank1 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
// Two slot configuration, one rank per slot
4'b10_10: begin
if(DRAM_TYPE == "DDR2")begin
if(chip_cnt_r == 2'b00)begin
phy_tmp_odt_r
<= #TCQ 4'b0010; //bit0 for rank0
end else begin
phy_tmp_odt_r
<= #TCQ 4'b0001; //bit0 for rank0
end
end else begin
if (//wrlvl_odt ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE)) begin
phy_tmp_odt_r
<= #TCQ 4'b0011; //bit0 for rank0
end else if ((init_state_r == INIT_PI_PHASELOCK_READS) ||
(init_state_r == INIT_RDLVL_STG1_READ) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_WRCAL_READ)) begin
if (chip_cnt_r == 2'b00) begin
phy_tmp_odt_r
<= #TCQ 4'b0010;
end else if (chip_cnt_r == 2'b01) begin
phy_tmp_odt_r
<= #TCQ 4'b0001;
end
end
end // else: !if(DRAM_TYPE == "DDR2")
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
//Rank1 Dynamic ODT disabled
tmp_mr2_r[1] <= #TCQ 2'b00;
//Rank1 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[1] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM defaults to 40 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "60") ? 3'b001 :
(RTT_NOM == "120") ? 3'b010 :
(RTT_NOM == "20") ? 3'b100 :
(RTT_NOM == "30") ? 3'b101 :
3'b011;
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM defaults to 40 ohms
tmp_mr1_r[1] <= #TCQ (RTT_NOM == "60") ? 3'b001 :
(RTT_NOM == "120") ? 3'b010 :
(RTT_NOM == "20") ? 3'b100 :
(RTT_NOM == "30") ? 3'b101 :
3'b011;
end
end
// Two Slots - One slot with dual rank and the other with single rank
4'b10_11: begin
//Rank3 Rtt_NOM defaults to 40 ohms
tmp_mr1_r[2] <= #TCQ (RTT_NOM3 == "60") ? 3'b001 :
(RTT_NOM3 == "120") ? 3'b010 :
(RTT_NOM3 == "20") ? 3'b100 :
(RTT_NOM3 == "30") ? 3'b101 :
3'b011;
tmp_mr2_r[2] <= #TCQ 2'b00;
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
//Rank1 Dynamic ODT disabled
tmp_mr2_r[1] <= #TCQ 2'b00;
//Rank1 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[1] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM defaults to 40 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "60") ? 3'b001 :
(RTT_NOM == "120") ? 3'b010 :
(RTT_NOM == "20") ? 3'b100 :
(RTT_NOM == "30") ? 3'b101 :
3'b011;
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM
tmp_mr1_r[1] <= #TCQ 3'b000;
end
//Slot1 Rank1 or Rank3 is being written
if(DRAM_TYPE == "DDR2")begin
if(chip_cnt_r == 2'b00)begin
phy_tmp_odt_r
<= #TCQ 4'b0010;
end else begin
phy_tmp_odt_r
<= #TCQ 4'b0001;
end
end else begin
if (//wrlvl_odt ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE)) begin
if (chip_cnt_r[0] == 1'b1) begin
phy_tmp_odt_r
<= #TCQ 4'b0011;
//Slot0 Rank0 is being written
end else begin
phy_tmp_odt_r
<= #TCQ 4'b0101; // ODT for ranks 0 and 2 aserted
end
end else if ((init_state_r == INIT_RDLVL_STG1_READ)
|| (init_state_r == INIT_PI_PHASELOCK_READS) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_WRCAL_READ))begin
if (chip_cnt_r == 2'b00) begin
phy_tmp_odt_r
<= #TCQ 4'b0100;
end else begin
phy_tmp_odt_r
<= #TCQ 4'b0001;
end
end
end // else: !if(DRAM_TYPE == "DDR2")
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
end
// Two Slots - One slot with dual rank and the other with single rank
4'b11_10: begin
//Rank2 Rtt_NOM defaults to 40 ohms
tmp_mr1_r[2] <= #TCQ (RTT_NOM2 == "60") ? 3'b001 :
(RTT_NOM2 == "120") ? 3'b010 :
(RTT_NOM2 == "20") ? 3'b100 :
(RTT_NOM2 == "30") ? 3'b101 :
3'b011;
tmp_mr2_r[2] <= #TCQ 2'b00;
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
//Rank1 Dynamic ODT disabled
tmp_mr2_r[1] <= #TCQ 2'b00;
//Rank1 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[1] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM defaults to 40 ohms
tmp_mr1_r[1] <= #TCQ (RTT_NOM == "60") ? 3'b001 :
(RTT_NOM == "120") ? 3'b010 :
(RTT_NOM == "20") ? 3'b100 :
(RTT_NOM == "30") ? 3'b101 :
3'b011;
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ 3'b000;
end // else: !if((RTT_WR == "OFF") ||...
if(DRAM_TYPE == "DDR2")begin
if(chip_cnt_r[1] == 1'b1)begin
phy_tmp_odt_r <=
#TCQ 4'b0001;
end else begin
phy_tmp_odt_r
<= #TCQ 4'b0100; // rank 2 ODT asserted
end
end else begin
if (// wrlvl_odt ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE)) begin
if (chip_cnt_r[1] == 1'b1) begin
phy_tmp_odt_r
<= #TCQ 4'b0110;
end else begin
phy_tmp_odt_r <=
#TCQ 4'b0101;
end
end else if ((init_state_r == INIT_RDLVL_STG1_READ)
|| (init_state_r == INIT_PI_PHASELOCK_READS) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_WRCAL_READ)) begin
if (chip_cnt_r[1] == 1'b1) begin
phy_tmp_odt_r[(1*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ 4'b0010;
end else begin
phy_tmp_odt_r
<= #TCQ 4'b0100;
end
end // if (init_state_r == INIT_IOCONFIG_RD)
end // else: !if(DRAM_TYPE == "DDR2")
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
end
// Two Slots - two ranks per slot
4'b11_11: begin
//Rank2 Rtt_NOM defaults to 40 ohms
tmp_mr1_r[2] <= #TCQ (RTT_NOM2 == "60") ? 3'b001 :
(RTT_NOM2 == "120") ? 3'b010 :
(RTT_NOM2 == "20") ? 3'b100 :
(RTT_NOM2 == "30") ? 3'b101 :
3'b011;
//Rank3 Rtt_NOM defaults to 40 ohms
tmp_mr1_r[3] <= #TCQ (RTT_NOM3 == "60") ? 3'b001 :
(RTT_NOM3 == "120") ? 3'b010 :
(RTT_NOM3 == "20") ? 3'b100 :
(RTT_NOM3 == "30") ? 3'b101 :
3'b011;
tmp_mr2_r[2] <= #TCQ 2'b00;
tmp_mr2_r[3] <= #TCQ 2'b00;
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
//Rank1 Dynamic ODT disabled
tmp_mr2_r[1] <= #TCQ 2'b00;
//Rank1 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[1] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM
tmp_mr1_r[1] <= #TCQ 3'b000;
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ 3'b000;
end // else: !if((RTT_WR == "OFF") ||...
if(DRAM_TYPE == "DDR2")begin
if(chip_cnt_r[1] == 1'b1)begin
phy_tmp_odt_r
<= #TCQ 4'b0001;
end else begin
phy_tmp_odt_r
<= #TCQ 4'b0100;
end
end else begin
if (//wrlvl_odt ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE)) begin
//Slot1 Rank1 or Rank3 is being written
if (chip_cnt_r[0] == 1'b1) begin
phy_tmp_odt_r
<= #TCQ 4'b0110;
//Slot0 Rank0 or Rank2 is being written
end else begin
phy_tmp_odt_r
<= #TCQ 4'b1001;
end
end else if ((init_state_r == INIT_RDLVL_STG1_READ)
|| (init_state_r == INIT_PI_PHASELOCK_READS) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_WRCAL_READ))begin
//Slot1 Rank1 or Rank3 is being read
if (chip_cnt_r[0] == 1'b1) begin
phy_tmp_odt_r
<= #TCQ 4'b0100;
//Slot0 Rank0 or Rank2 is being read
end else begin
phy_tmp_odt_r
<= #TCQ 4'b1000;
end
end // if (init_state_r == INIT_IOCONFIG_RD)
end // else: !if(DRAM_TYPE == "DDR2")
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
end
default: begin
phy_tmp_odt_r <= #TCQ 4'b1111;
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done)) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
//Rank1 Dynamic ODT disabled
tmp_mr2_r[1] <= #TCQ 2'b00;
//Rank1 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[1] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM defaults to 40 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "60") ? 3'b001 :
(RTT_NOM == "120") ? 3'b010 :
(RTT_NOM == "20") ? 3'b100 :
(RTT_NOM == "30") ? 3'b101 :
3'b011;
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM defaults to 40 ohms
tmp_mr1_r[1] <= #TCQ (RTT_NOM == "60") ? 3'b001 :
(RTT_NOM == "120") ? 3'b010 :
(RTT_NOM == "20") ? 3'b100 :
(RTT_NOM == "30") ? 3'b101 :
3'b011;
end
end
endcase
end
end
endgenerate
// ODT (calib_aux_out) bus width is fixed to 4 for up to 4 ranks support
// CKE is also part of the calib_aux_out bus
// For single rank calib_aux_out0[1] used for ODT and calib_aux_out0[0]
// used for CKE.
// For dual rank I/Fs calib_aux_out0[1]&[3] used for ODT and
// calib_aux_out0[0] & [2] used for CKE.
// For 4 rank I/Fs calib_aux_out0[3:0] used for ODT and calib_aux_out1[3:0]
// used for CKE.
generate
if ((nSLOTS == 1) && (RANKS > 2)) begin
always @(posedge clk)
if (rst) begin
calib_aux_out0 <= #TCQ 4'b0000;
calib_aux_out1 <= #TCQ 4'b0000;
end else begin
if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)
calib_aux_out1 <= #TCQ {CKE_WIDTH{1'b1}};
else
calib_aux_out1 <= #TCQ {CKE_WIDTH{1'b0}};
if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) ||
wrlvl_rank_done || wrlvl_rank_done_r1 ||
(wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3"))
calib_aux_out0 <= #TCQ 4'b0000;
else if (((DRAM_TYPE == "DDR3")
||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2")))
&& (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE)))
// Quad rank in a single slot
calib_aux_out0 <= #TCQ phy_tmp_odt_r;
else
calib_aux_out0 <= #TCQ 4'b0000;
end
end else if ((nSLOTS == 1) && (RANKS <= 2)) begin
always @(posedge clk)
if (rst) begin
calib_aux_out0 <= #TCQ 4'b0000;
calib_aux_out1 <= #TCQ 4'b0000;
end else begin
if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin
calib_aux_out0[0] <= #TCQ 1'b1;
calib_aux_out0[2] <= #TCQ 1'b1;
end else begin
calib_aux_out0[0] <= #TCQ 1'b0;
calib_aux_out0[2] <= #TCQ 1'b0;
end
calib_aux_out1 <= #TCQ 4'b0000;
if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) ||
wrlvl_rank_done || wrlvl_rank_done_r1 ||
(wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin
calib_aux_out0[1] <= #TCQ 1'b0;
calib_aux_out0[3] <= #TCQ 1'b0;
end else if (((DRAM_TYPE == "DDR3")
||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2")))
&& (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE))) begin
// Quad rank in a single slot
calib_aux_out0[1] <= #TCQ phy_tmp_odt_r[0];
calib_aux_out0[3] <= #TCQ phy_tmp_odt_r[1];
end else begin
calib_aux_out0[1] <= #TCQ 1'b0;
calib_aux_out0[3] <= #TCQ 1'b0;
end
end
end else if ((nSLOTS == 2) && (RANKS > 2)) begin
always @(posedge clk)
if (rst) begin
calib_aux_out0 <= #TCQ 4'b0000;
calib_aux_out1 <= #TCQ 4'b0000;
end else begin
if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)
calib_aux_out1 <= #TCQ {CKE_WIDTH{1'b1}};
else
calib_aux_out1 <= #TCQ {CKE_WIDTH{1'b0}};
if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) ||
wrlvl_rank_done || wrlvl_rank_done_r1 ||
(wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3"))
calib_aux_out0 <= #TCQ 4'b0000;
else if (((DRAM_TYPE == "DDR3")
||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2")))
&& (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE)))
// Quad rank in a single slot
calib_aux_out0 <= #TCQ phy_tmp_odt_r | phy_tmp_odt_r1;
else
calib_aux_out0 <= #TCQ 4'b0000;
end
end else if ((nSLOTS == 2) && (RANKS <= 2)) begin
always @(posedge clk)
if (rst) begin
calib_aux_out0 <= #TCQ 4'b0000;
calib_aux_out1 <= #TCQ 4'b0000;
end else begin
if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin
calib_aux_out0[0] <= #TCQ 1'b1;
calib_aux_out0[2] <= #TCQ 1'b1;
end else begin
calib_aux_out0[0] <= #TCQ 1'b0;
calib_aux_out0[2] <= #TCQ 1'b0;
end
calib_aux_out1 <= #TCQ 4'b0000;
if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) ||
wrlvl_rank_done || wrlvl_rank_done_r1 ||
(wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin
calib_aux_out0[1] <= #TCQ 1'b0;
calib_aux_out0[3] <= #TCQ 1'b0;
end else if (((DRAM_TYPE == "DDR3")
||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2")))
&& (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE))) begin
// Quad rank in a single slot
calib_aux_out0[1] <= #TCQ phy_tmp_odt_r[0] | phy_tmp_odt_r1[0];
calib_aux_out0[3] <= #TCQ phy_tmp_odt_r[1] | phy_tmp_odt_r1[1];
end else begin
calib_aux_out0[1] <= #TCQ 1'b0;
calib_aux_out0[3] <= #TCQ 1'b0;
end
end
end
endgenerate
//*****************************************************************
// memory address during init
//*****************************************************************
always @(burst_addr_r or cnt_init_mr_r or chip_cnt_r
or ddr2_refresh_flag_r or init_state_r or load_mr0
or load_mr1 or load_mr2 or load_mr3 or mr1_r[chip_cnt_r][0]
or mr1_r[chip_cnt_r][1] or mr1_r[chip_cnt_r][2] or mr2_r[chip_cnt_r]
or rdlvl_stg1_done or pi_dqs_found_done or rdlvl_wr_rd
or reg_ctrl_cnt_r)begin
// Bus 0 for address/bank never used
address_w = 'b0;
bank_w = 'b0;
if ((init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_ZQCL) ||
(init_state_r == INIT_DDR2_PRECHARGE)) begin
// Set A10=1 for ZQ long calibration or Precharge All
address_w = 'b0;
address_w[10] = 1'b1;
bank_w = 'b0;
end else if (init_state_r == INIT_WRLVL_START) begin
// Enable wrlvl in MR1
bank_w[1:0] = 2'b01;
address_w = load_mr1[ROW_WIDTH-1:0];
address_w[7] = 1'b1;
end else if (init_state_r == INIT_WRLVL_LOAD_MR) begin
// Finished with write leveling, disable wrlvl in MR1
// For single rank disable Rtt_Nom
bank_w[1:0] = 2'b01;
address_w = load_mr1[ROW_WIDTH-1:0];
address_w[2] = mr1_r[chip_cnt_r][0];
address_w[6] = mr1_r[chip_cnt_r][1];
address_w[9] = mr1_r[chip_cnt_r][2];
end else if (init_state_r == INIT_WRLVL_LOAD_MR2) begin
// Set RTT_WR in MR2 after write leveling disabled
bank_w[1:0] = 2'b10;
address_w = load_mr2[ROW_WIDTH-1:0];
address_w[10:9] = mr2_r[chip_cnt_r];
end else if ((init_state_r == INIT_REG_WRITE)&
(DRAM_TYPE == "DDR3"))begin
// bank_w is assigned a 3 bit value. In some
// DDR2 cases there will be only two bank bits.
//Qualifying the condition with DDR3
bank_w = 'b0;
address_w = 'b0;
case (reg_ctrl_cnt_r)
REG_RC0[2:0]: address_w[4:0] = REG_RC0[4:0];
REG_RC1[2:0]:begin
address_w[4:0] = REG_RC1[4:0];
bank_w = REG_RC1[7:5];
end
REG_RC2[2:0]: address_w[4:0] = REG_RC2[4:0];
REG_RC3[2:0]: address_w[4:0] = REG_RC3[4:0];
REG_RC4[2:0]: address_w[4:0] = REG_RC4[4:0];
REG_RC5[2:0]: address_w[4:0] = REG_RC5[4:0];
endcase
end else if (init_state_r == INIT_LOAD_MR) begin
// If loading mode register, look at cnt_init_mr to determine
// which MR is currently being programmed
address_w = 'b0;
bank_w = 'b0;
if(DRAM_TYPE == "DDR3")begin
if(rdlvl_stg1_done && pi_dqs_found_done)begin
// end of the calibration programming correct
// burst length
bank_w[1:0] = 2'b00;
address_w = load_mr0[ROW_WIDTH-1:0];
address_w[8]= 1'b0; //Don't reset DLL
end else begin
case (cnt_init_mr_r)
INIT_CNT_MR2: begin
bank_w[1:0] = 2'b10;
address_w = load_mr2[ROW_WIDTH-1:0];
address_w[10:9] = mr2_r[chip_cnt_r];
end
INIT_CNT_MR3: begin
bank_w[1:0] = 2'b11;
address_w = load_mr3[ROW_WIDTH-1:0];
end
INIT_CNT_MR1: begin
bank_w[1:0] = 2'b01;
address_w = load_mr1[ROW_WIDTH-1:0];
address_w[2] = mr1_r[chip_cnt_r][0];
address_w[6] = mr1_r[chip_cnt_r][1];
address_w[9] = mr1_r[chip_cnt_r][2];
end
INIT_CNT_MR0: begin
bank_w[1:0] = 2'b00;
address_w = load_mr0[ROW_WIDTH-1:0];
// fixing it to BL8 for calibration
address_w[1:0] = 2'b00;
end
default: begin
bank_w = {BANK_WIDTH{1'bx}};
address_w = {ROW_WIDTH{1'bx}};
end
endcase // case(cnt_init_mr_r)
end // else: !if(rdlvl_stg1_done && rdlvl_stg2_done)
end else begin // DDR2
case (cnt_init_mr_r)
INIT_CNT_MR2: begin
if(~ddr2_refresh_flag_r)begin
bank_w[1:0] = 2'b10;
address_w = load_mr2[ROW_WIDTH-1:0];
end else begin // second set of lm commands
bank_w[1:0] = 2'b00;
address_w = load_mr0[ROW_WIDTH-1:0];
address_w[8]= 1'b0;
//MRS command without resetting DLL
end
end
INIT_CNT_MR3: begin
if(~ddr2_refresh_flag_r)begin
bank_w[1:0] = 2'b11;
address_w = load_mr3[ROW_WIDTH-1:0];
end else begin // second set of lm commands
bank_w[1:0] = 2'b00;
address_w = load_mr0[ROW_WIDTH-1:0];
address_w[8]= 1'b0;
//MRS command without resetting DLL. Repeted again
// because there is an extra state.
end
end
INIT_CNT_MR1: begin
bank_w[1:0] = 2'b01;
if(~ddr2_refresh_flag_r)begin
address_w = load_mr1[ROW_WIDTH-1:0];
end else begin // second set of lm commands
address_w = load_mr1[ROW_WIDTH-1:0];
address_w[9:7] = 3'b111;
//OCD default state
end
end
INIT_CNT_MR0: begin
if(~ddr2_refresh_flag_r)begin
bank_w[1:0] = 2'b00;
address_w = load_mr0[ROW_WIDTH-1:0];
end else begin // second set of lm commands
bank_w[1:0] = 2'b01;
address_w = load_mr1[ROW_WIDTH-1:0];
if((chip_cnt_r == 2'd1) || (chip_cnt_r == 2'd3))begin
// always disable odt for rank 1 and rank 3 as per SPEC
address_w[2] = 'b0;
address_w[6] = 'b0;
end
//OCD exit
end
end
default: begin
bank_w = {BANK_WIDTH{1'bx}};
address_w = {ROW_WIDTH{1'bx}};
end
endcase // case(cnt_init_mr_r)
end
end else if ((init_state_r == INIT_PI_PHASELOCK_READS) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_RDLVL_STG1_READ)) begin
// Writing and reading PRBS pattern for read leveling stage 1
// Need to support burst length 4 or 8. PRBS pattern will be
// written to entire row and read back from the same row repeatedly
bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0];
address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}};
if (stg1_wr_rd_cnt == NUM_STG1_WR_RD)
address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}};
else if (stg1_wr_rd_cnt >= 9'd0)
address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC;
end else if ((init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_WRCAL_READ) ||
(init_state_r == INIT_RDLVL_STG2_READ)) begin
// when writing or reading back training pattern for read leveling stage2
// need to support burst length of 4 or 8. This may mean issuing
// multiple commands to cover the entire range of addresses accessed
// during read leveling.
// Hard coding A[12] to 1 so that it will always be burst length of 8
// for DDR3. Does not have any effect on DDR2.
bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0];
address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}};
address_w[COL_WIDTH-1:0] =
{CALIB_COL_ADD[COL_WIDTH-1:3],burst_addr_r, 3'b000};
address_w[12] = 1'b1;
end else if ((init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_WRCAL_ACT)) begin
bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0];
address_w = CALIB_ROW_ADD[ROW_WIDTH-1:0];
end else begin
bank_w = {BANK_WIDTH{1'bx}};
address_w = {ROW_WIDTH{1'bx}};
end
end
// registring before sending out
always @(posedge clk) begin
for (i = 0; i < nCK_PER_CLK; i = i + 1) begin: div_clk_loop
phy_address[(i*ROW_WIDTH) +: ROW_WIDTH] <= #TCQ address_w;
phy_bank[(i*BANK_WIDTH) +: BANK_WIDTH] <= #TCQ bank_w;
end
end
/* always @(posedge clk) begin
if (rst)
calib_bank_cnt <= #TCQ 3'd0;
else
calib_bank_cnt <= #TCQ bank_w;
end*/
endmodule
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/14.0/ip/merlin/altera_irq_bridge/altera_irq_bridge.v#1 $
// $Revision: #1 $
// $Date: 2014/02/16 $
// $Author: swbranch $
// -------------------------------------------------------
// Altera IRQ Bridge
//
// Parameters
// IRQ_WIDTH : $IRQ_WIDTH
//
// -------------------------------------------------------
//------------------------------------------
// Message Supression Used
// QIS Warnings
// 15610 - Warning: Design contains x input pin(s) that do not drive logic
//------------------------------------------
`timescale 1 ns / 1 ns
module altera_irq_bridge
#(
parameter IRQ_WIDTH = 32
)
(
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset,
input [IRQ_WIDTH - 1:0] receiver_irq,
output sender31_irq,
output sender30_irq,
output sender29_irq,
output sender28_irq,
output sender27_irq,
output sender26_irq,
output sender25_irq,
output sender24_irq,
output sender23_irq,
output sender22_irq,
output sender21_irq,
output sender20_irq,
output sender19_irq,
output sender18_irq,
output sender17_irq,
output sender16_irq,
output sender15_irq,
output sender14_irq,
output sender13_irq,
output sender12_irq,
output sender11_irq,
output sender10_irq,
output sender9_irq,
output sender8_irq,
output sender7_irq,
output sender6_irq,
output sender5_irq,
output sender4_irq,
output sender3_irq,
output sender2_irq,
output sender1_irq,
output sender0_irq
);
wire [31:0] receiver_temp_irq;
assign receiver_temp_irq = {{(32 - IRQ_WIDTH){1'b0}}, receiver_irq}; //to align a non-32bit receiver interface with 32 interfaces of the receiver
assign sender0_irq = receiver_temp_irq[0];
assign sender1_irq = receiver_temp_irq[1];
assign sender2_irq = receiver_temp_irq[2];
assign sender3_irq = receiver_temp_irq[3];
assign sender4_irq = receiver_temp_irq[4];
assign sender5_irq = receiver_temp_irq[5];
assign sender6_irq = receiver_temp_irq[6];
assign sender7_irq = receiver_temp_irq[7];
assign sender8_irq = receiver_temp_irq[8];
assign sender9_irq = receiver_temp_irq[9];
assign sender10_irq = receiver_temp_irq[10];
assign sender11_irq = receiver_temp_irq[11];
assign sender12_irq = receiver_temp_irq[12];
assign sender13_irq = receiver_temp_irq[13];
assign sender14_irq = receiver_temp_irq[14];
assign sender15_irq = receiver_temp_irq[15];
assign sender16_irq = receiver_temp_irq[16];
assign sender17_irq = receiver_temp_irq[17];
assign sender18_irq = receiver_temp_irq[18];
assign sender19_irq = receiver_temp_irq[19];
assign sender20_irq = receiver_temp_irq[20];
assign sender21_irq = receiver_temp_irq[21];
assign sender22_irq = receiver_temp_irq[22];
assign sender23_irq = receiver_temp_irq[23];
assign sender24_irq = receiver_temp_irq[24];
assign sender25_irq = receiver_temp_irq[25];
assign sender26_irq = receiver_temp_irq[26];
assign sender27_irq = receiver_temp_irq[27];
assign sender28_irq = receiver_temp_irq[28];
assign sender29_irq = receiver_temp_irq[29];
assign sender30_irq = receiver_temp_irq[30];
assign sender31_irq = receiver_temp_irq[31];
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate function within a continuous assignment
module main ();
reg error;
reg [3:0] val2;
function [3:0] myfunc ;
input [31:0] in1 ;
myfunc = in1;
endfunction
wire [3:0] val1;
assign val1 = myfunc(val2);
initial
begin
error = 0;
val2 = 4'h0;
# 1 ;
if(val1 !== 4'b0)
begin
$display("FAILED - function3.11D - function within continuous assign(1)");
error = 1;
end
val2 = 32'h8;
# 1 ;
if(val1 !== val2)
begin
$display("FAILED - function3.11D - function within continuous assign(2)");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
`include "datapath/alu.v"
`include "datapath/comp.v"
`include "datapath/CoProcessor0RF.v"
`include "datapath/dm.v"
`include "datapath/ext.v"
`include "datapath/im.v"
`include "datapath/mux.v"
`include "datapath/npc.v"
`include "datapath/pc.v"
`include "datapath/rf.v"
`include "control/ctrl.v"
module mips (clk, rst);
input clk;
input rst;
// Wires.
wire [31:0] pc_next;
wire [31:0] pc_cur;
wire [31:0] ins;
wire [31:0] ext_imm;
wire [31:0] routa;
wire [31:0] routb;
wire [31:0] rin;
wire [31:0] aluSrcA_mux_out;
wire [31:0] aluSrcB_mux_out;
wire [31:0] alu_out;
wire [31:0] return_addr;
wire [31:0] dm_out;
wire [4:0] rWin;
wire [31:0] cop_out;
wire [31:0] npc_out;
wire [31:0] expiaddr;
wire [31:0] jiaddr;
// Control signals.
wire [3:0] aluCtr;
wire compare;
wire branch;
wire jump;
wire [1:0] regDst;
wire [1:0] aluSrcA;
wire [1:0] aluSrcB;
wire [1:0] regWr;
wire [1:0] memWr;
wire [1:0] immExt;
wire [1:0] memtoReg;
wire [1:0] copWr;
wire [1:0] byteExt;
wire [1:0] iaddrtoNPC;
wire [4:0] manInput_raddr;
wire [31:0] manInput_shf;
pc pc(
.clk(clk),
.rst(rst),
.niaddr(pc_next),
.iaddr(pc_cur)
);
npc npc(
.iaddr(pc_cur),
.branch(branch),
.jump(jump),
.ins(ins),
.jiaddr(jiaddr),
.imm16(ins[15:0]),
.imm26(ins[25:0]),
.riaddr(npc_out),
.niaddr(pc_next)
);
im_4k im(
.iaddr(pc_cur[11:2]),
.ins(ins)
);
ext immExt_ext(
.din(ins[15:0]),
.extOp(immExt),
.dout(ext_imm)
);
mux #(32) aluSrcA_mux(
.a(routa),
.b({{27{1'b0}}, ins[10:6]}),// Shift.
.c(manInput_shf),
.ctrl_s(aluSrcA),
.dout(aluSrcA_mux_out)
);
mux #(32) aluSrcB_mux(
.a(routb),
.b(ext_imm),
.ctrl_s(aluSrcB),
.dout(aluSrcB_mux_out)
);
mux #(5) regDst_mux(
.a(ins[20:16]),// rt.
.b(ins[15:11]),// rd.
.c(manInput_raddr),
.ctrl_s(regDst),
.dout(rWin)
);
regFile rf(
.busW(rin),
.clk(clk),
.wE(regWr),
.rW(rWin),
.rA(ins[25:21]),
.rB(ins[20:16]),
.busA(routa),
.busB(routb)
);
alu alu(
.ALUop(aluCtr),
.a(aluSrcA_mux_out),
.b(aluSrcB_mux_out),
.result(alu_out),
.clk(clk)
);
dm_4k dm(
.addr(alu_out[11:0]),
.din(routb),
.byteExt(byteExt),
.wEn(memWr),
.clk(clk),
.dout(dm_out)
);
mux #(32) memtoReg_mux(
.a(alu_out),
.b(dm_out),
.c(cop_out),
.d(npc_out),
.ctrl_s(memtoReg),
.dout(rin)
);
ctrl ctrl(
.ins(ins),
.compare(compare),
.jump(jump),
.regDst(regDst),
.aluSrcA(aluSrcA),
.aluSrcB(aluSrcB),
.aluCtr(aluCtr),
.regWr(regWr),
.memWr(memWr),
.immExt(immExt),
.memtoReg(memtoReg),
.copWr(copWr),
.byteExt(byteExt),
.manInput_raddr(manInput_raddr),
.manInput_shf(manInput_shf),
.iaddrtoNPC(iaddrtoNPC)
);
comp comp(
.dinA(aluSrcA_mux_out),
.dinB(aluSrcB_mux_out),
.ins(ins),
.compare(compare),
.branch(branch)
);
CoProcessor0RF CoP0(
.clk(clk),
.din(aluSrcB_mux_out),
.wEn(copWr),
.regNum(ins[15:11]),
.sel(ins[2:0]),
.dout(cop_out),
.npc_out(npc_out),
.expiaddr(expiaddr),
.ins(ins)
);
mux #(32) iaddrtoNPC_mux(
.a(aluSrcA_mux_out),
.b(expiaddr),
.ctrl_s(iaddrtoNPC),
.dout(jiaddr)
);
endmodule // MIPS main program;
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2111OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__A2111OI_BEHAVIORAL_PP_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a2111oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , B1, C1, D1, and0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2111OI_BEHAVIORAL_PP_V |
// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Description: SRL based FIFO for AXIS/AXI Channels.
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_axic_srl_fifo #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_FAMILY = "virtex7",
parameter integer C_PAYLOAD_WIDTH = 1,
parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire aclk, // Clock
input wire aresetn, // Reset
input wire [C_PAYLOAD_WIDTH-1:0] s_payload, // Input data
input wire s_valid, // Input data valid
output reg s_ready, // Input data ready
output wire [C_PAYLOAD_WIDTH-1:0] m_payload, // Output data
output reg m_valid, // Output data valid
input wire m_ready // Output data ready
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
// ceiling logb2
function integer f_clogb2 (input integer size);
integer s;
begin
s = size;
s = s - 1;
for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
s = s >> 1;
end
endfunction // clogb2
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [LP_LOG_FIFO_DEPTH-1:0] fifo_index;
wire [4-1:0] fifo_addr;
wire push;
wire pop ;
reg areset_r1;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
always @(posedge aclk) begin
areset_r1 <= ~aresetn;
end
always @(posedge aclk) begin
if (~aresetn) begin
fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};
end
else begin
fifo_index <= push & ~pop ? fifo_index + 1'b1 :
~push & pop ? fifo_index - 1'b1 :
fifo_index;
end
end
assign push = s_valid & s_ready;
always @(posedge aclk) begin
if (~aresetn) begin
s_ready <= 1'b0;
end
else begin
s_ready <= areset_r1 ? 1'b1 :
push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :
~push & pop ? 1'b1 :
s_ready;
end
end
assign pop = m_valid & m_ready;
always @(posedge aclk) begin
if (~aresetn) begin
m_valid <= 1'b0;
end
else begin
m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :
push & ~pop ? 1'b1 :
m_valid;
end
end
generate
if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr
assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};
end
else begin : gen_fifo_addr
assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
end
endgenerate
generate
genvar i;
for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit
SRL16E
u_srl_fifo(
.Q ( m_payload[i] ) ,
.A0 ( fifo_addr[0] ) ,
.A1 ( fifo_addr[1] ) ,
.A2 ( fifo_addr[2] ) ,
.A3 ( fifo_addr[3] ) ,
.CE ( push ) ,
.CLK ( aclk ) ,
.D ( s_payload[i] )
);
end
endgenerate
endmodule
`default_nettype wire
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`include "../../../../usrp/firmware/include/fpga_regs_common.v"
`include "../../../../usrp/firmware/include/fpga_regs_standard.v"
module sounder_ctrl(clk_i,rst_i,saddr_i,sdata_i,s_strobe_i,
reset_o,transmit_o,receive_o,loopback_o,
degree_o,ampl_o,mask_o,
tx_strobe_o,rx_strobe_o,sum_strobe_o,ref_strobe_o);
input clk_i; // Master clock @ 64 MHz
input rst_i; // Master synchronous reset
input [6:0] saddr_i; // Configuration bus address
input [31:0] sdata_i; // Configuration bus data
input s_strobe_i; // Configuration bus write
output reset_o;
output transmit_o;
output receive_o;
output loopback_o;
output [4:0] degree_o;
output [13:0] ampl_o;
output [15:0] mask_o;
output tx_strobe_o;
output rx_strobe_o;
output sum_strobe_o;
output ref_strobe_o;
setting_reg #(`FR_USER_0) sr_mode
( .clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
.out({loopback_o,receive_o,transmit_o,reset_o}) );
setting_reg #(`FR_USER_1) sr_lfsr_degree
( .clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
.out(degree_o) );
setting_reg #(`FR_USER_2) sr_lfsr_ampl
( .clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
.out(ampl_o) );
wire [16:0] len;
lfsr_constants constants
(.clk_i(clk_i),.rst_i(rst_i),.degree_i(degree_o),.mask_o(mask_o),
.len_o(len) );
reg [15:0] phase;
assign tx_strobe_o = ~phase[0];
assign ref_strobe_o = tx_strobe_o & !(phase>>1 == len>>1);
assign sum_strobe_o = (phase == len);
reg rx_strobe_o;
always @(posedge clk_i)
if (rst_i)
begin
phase <= #5 16'hFFFF;
rx_strobe_o <= #5 0;
end
else
if (sum_strobe_o)
begin
phase <= #5 0;
rx_strobe_o <= #5 1'b1;
end
else
begin
phase <= #5 phase + 16'b1;
rx_strobe_o <= #5 0;
end
endmodule // sounder_ctrl
|
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the users design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// 503-286-8001 (other locations)
//
// web: http://www.latticesemi.com/
// email: [email protected]
//
// --------------------------------------------------------------------
// FILE DETAILS
// File : rxcver.v
// Title : UART Component -- rxcver
// Code type : Register Transfer Level
// Dependencies :
// Description : Verilog file for the UART Receiver Module
// <Global reset and clock>
// reset : Master reset
// clk : Master clock
//
// <Register>
// rbr : Receiver Buffer Register
//
// <Rising edge of rbr, lsr read strobes>
// rbr_rd : one CPU clk width pulse indicating rising edge of rbr Read
// lsr_rd : one CPU clk width pulse indicating rising edge of lsr Read
//
// <Receiver input>
// sin : Receiver serial input
//
// <Receiver control>
// databits : "00"=5-bit, "01"=6-bit, "10"=7-bit, "11"=8-bit
// parity_en : '0'=Parity Bit Enable, '1'=Parity Bit Disable
// parity_even : '0'=Even Parity Selected, '1'=Odd Parity Selected
// parity_stick : '0'=Stick Parity Disable, '1'=Stick Parity Enable
//
// <Receiver/Transmitter status>
// rx_rdy : rbr data is ready to be read
// overrun_err : Overrun error
// parity_err : Parity error
// frame_err : Frame error
// break_int : BREAK interrupt
//
// =============================================================================
// REVISION HISTORY
// Version : 1.0
// Changes Made : Initial Creation
//
// Version : 7.0SP2, 3.0
// Changes Made : Add one more register to sin to avoid meta-stability
//
// Version : 3.1
// Changes Made : Baudrate Generation is modified.
// RX and TX path of the UART is updated to faster clock
// 16 word deep FIFO is implemented when FIFO option is
// selected
//
// Version : 3.5
// Changes Made : WISHBONE Data Bus can be 8 bits or 32 bits. All UART registers
// occupy byte instead of 4 bytes (i.e. registers are accessible
// using 3 bits only instead of original 5 bits).
// =============================================================================
`ifndef RXCVER_FILE
`define RXCVER_FILE
`include "system_conf.v"
`include "rxcver_fifo.v"
module rxcver #(parameter UART_WB_DAT_WIDTH=8,
parameter FIFO=0)
(
// Global reset and clock
reset,
clk,
// Register
rbr,
rbr_fifo,
// Rising edge of rbr, lsr read strobes
rbr_rd,
lsr_rd,
// Receiver input
sin,
// Receiver control
databits,
parity_en,
parity_even,
parity_stick,
// Receiver status
rx_rdy,
overrun_err,
parity_err,
frame_err,
break_int,
fifo_empty,
fifo_almost_full,
divisor
);
input reset ;
input clk ;
input rbr_rd ;
input lsr_rd ;
input sin ;
input [1:0] databits ;
input parity_en;
input parity_even;
input parity_stick;
output [7:0] rbr_fifo;
output [UART_WB_DAT_WIDTH-1:0] rbr ;
output rx_rdy ;
output overrun_err ;
output parity_err ;
output frame_err ;
output break_int ;
output fifo_empty ;
output fifo_almost_full;
input[15:0] divisor;
reg [3:0] databit_recved_num;
reg [UART_WB_DAT_WIDTH-1:0] rsr;
reg rx_parity_err ;
reg rx_frame_err ;
reg rx_idle;
reg rbr_datardy;
reg [3:0] count;
reg hunt;
reg hunt_one;
reg sin_d0;
reg sin_d1;
reg rx_frame_err_d1;
reg rx_idle_d1;
reg overrun_err_int;
reg parity_err_int;
reg frame_err_int;
reg break_int_int;
reg sampled_once;
reg rxclk_en;
wire [7:0] rbr_fifo;
wire [2:0] rbr_fifo_error;
reg [UART_WB_DAT_WIDTH-1:0] rbr;
// State Machine Definition
parameter idle = 3'b000;
parameter shift = 3'b001;
parameter parity = 3'b010;
parameter stop = 3'b011;
parameter idle1 = 3'b100;
reg [2:0] cs_state;
parameter lat_family = `LATTICE_FAMILY;
// FIFO signals for FIFO mode
wire fifo_full;
wire fifo_empty;
wire fifo_almost_full;
wire fifo_almost_empty;
reg[10:0] fifo_din;
reg fifo_wr;
reg fifo_wr_q;
wire fifo_wr_pulse;
reg [15:0] counter;
wire [15:0] divisor_2;
assign divisor_2 = divisor/2;
reg sin_d0_delay;
////////////////////////////////////////////////////////////////////////////////
// Generate hunt
////////////////////////////////////////////////////////////////////////////////
// hunt : will be TRUE when start bit is found
always @(posedge clk or posedge reset) begin
if (reset)
hunt <= 1'b0;
else if ((cs_state == idle) && (sin_d0 == 1'b0) && (sin_d1 == 1'b1))
// Set Hunt when SIN falling edge is found at the idle state
hunt <= 1'b1;
else if (sampled_once && ~sin_d0)
// Start bit is successfully sampled twice after framing error
// set Hunt_r "true" for resynchronizing of next frame
hunt <= 1'b1;
else if (~rx_idle || sin_d0)
hunt <= 1'b0;
end
// hunt_one :
// hunt_one, used for BI flag generation, indicates that there is at
// least a '1' in the (data + parity + stop) bits of the frame.
// Break Interrupt flag(BI) is set to '1' whenever the received input
// is held at the '0' state for all bits in the frame (Start bit +
// Data bits + Parity bit + Stop bit). So, as long as hunt_one is still
// low after all bits are received, BI will be set to '1'.
always @(posedge clk or posedge reset) begin
if (reset)
hunt_one <= 1'b0;
else if (hunt)
hunt_one <= 1'b0;
else if ((rx_idle == 1'b0) && (counter == divisor_2) && (sin_d0 == 1'b1))
hunt_one <= 1'b1;
end
// rbr_datardy :
// This will be set to indicate that the data in rbr is ready for read and
// will be cleared after rbr is read.
//
generate
begin
if (FIFO == 1) begin
always @(posedge clk or posedge reset) begin
if (reset)
rbr_datardy <= 1'b0;
else begin
if (fifo_empty)
// clear RbrDataRDY when RBR is read by CPU in 450 or FIFO is
// empty in 550 mode
rbr_datardy <= 1'b0;
else if (!fifo_empty)
// set RbrDataRDY at RxIdle_r rising edge
rbr_datardy <= 1'b1;
end
end
end
else begin
always @(posedge clk or posedge reset) begin
if (reset)
rbr_datardy <= 1'b0;
else begin
if (rbr_rd)
// clear RbrDataRDY when RBR is read by CPU in 450 or FIFO is
// empty in 550 mode
rbr_datardy <= 1'b0;
else if ((rx_idle == 1'b1) && (rx_idle_d1 == 1'b0))
// set RbrDataRDY at RxIdle_r rising edge
rbr_datardy <= 1'b1;
end
end
end
end
endgenerate
// sampled_once :
// This will be set for one clk clock after a framing error occurs not
// because of BREAK and a low sin signal is sampled by the clk right
// after the sample time of the Stop bit which causes the framing error.
always @ (posedge clk or posedge reset) begin
if (reset)
sampled_once <= 1'b0;
else if (rx_frame_err && ~rx_frame_err_d1 && ~sin_d0 && hunt_one)
// Start bit got sampled once
sampled_once <= 1'b1;
else
sampled_once <= 1'b0;
end
// rx_idle Flag
always @ (posedge clk or posedge reset) begin
if (reset)
rx_idle <= 1'b1;
else if (cs_state == idle)
rx_idle <= 1'b1;
else
rx_idle <= 1'b0;
end
////////////////////////////////////////////////////////////////////////////////
// Receiver Finite State Machine
////////////////////////////////////////////////////////////////////////////////
// rx_parity_err:
// rx_parity_err is a dynamic Parity Error indicator which is
// initialized to 0 for even parity and 1 for odd parity.
// For odd parity, if there are odd number of '1's in the
// (data + parity) bits, the XOR will bring rx_parity_err back to 0
// which means no parity error, otherwise rx_parity_err will be 1 to
// indicate a parity error.
// parity_stick='1' means Stick Parity is enabled. In this case,
// the accumulated dynamic rx_parity_err result will be ignored. A new
// value will be assigned to rx_parity_err based on the even/odd parity
// mode setting and the sin sampled in parity bit.
// parity_even='0'(odd parity):
// sin needs to be '1', otherwise it's a stick parity error.
// parity_even='1'(even parity):
// sin needs to be '0', otherwise it's a stick parity error.
always @ (posedge clk or posedge reset) begin
if (reset) begin
rsr <= 0;
databit_recved_num <= 4'h0;
rx_parity_err <= 1'b1;
rx_frame_err <= 1'b0;
cs_state <= idle;
counter <= 16'b0000_0000_0000_0000;
end
else case (cs_state)
idle: begin
if ((sin_d0 == 1'b0) && (sin_d0_delay == 1'b1)) begin
cs_state <= idle1;
end
counter <= divisor - 1'b1;
end
idle1: begin
if (counter == divisor_2) begin
if (sin_d0 == 1'b1)
cs_state <= idle;
else begin
rsr <= 0;
databit_recved_num <= 4'h0;
rx_parity_err <= ~ parity_even;
rx_frame_err <= 1'b0;
end
end
if (counter == 16'b0000_0000_0000_0001) begin
cs_state <= shift;
counter <= divisor;
end
else
counter <= counter - 1'b1;
end
shift: begin
if (counter == divisor_2) begin
rsr <= {sin_d0, rsr[7:1]};
rx_parity_err <= rx_parity_err ^ sin_d0;
databit_recved_num <= databit_recved_num + 1;
end
if (counter == 16'b0000_0000_0000_0001) begin
if ((databits==2'b00 && databit_recved_num == 4'h5) ||
(databits==2'b01 && databit_recved_num == 4'h6) ||
(databits==2'b10 && databit_recved_num == 4'h7) ||
(databits==2'b11 && databit_recved_num == 4'h8))
if (parity_en == 1'b0)
cs_state <= stop;
else
cs_state <= parity;
counter <= divisor;
end
else
counter <= counter - 1'b1;
end
parity: begin
if (counter == divisor_2) begin
if (parity_stick == 1'b0)
rx_parity_err <= rx_parity_err ^ sin_d0;
else
if (parity_even == 1'b0)
rx_parity_err <= ~sin_d0;
else
rx_parity_err <= sin_d0;
end
if (counter == 16'b0000_0000_0000_0001) begin
cs_state <= stop;
counter <= divisor;
end
else
counter <= counter - 1'b1;
end
stop: begin
if (counter == divisor_2) begin
// The Receiver checks the 1st Stopbit only regardless of the number
// of Stop bits selected.
// Stop bit needs to be '1', otherwise it's a Framing error
rx_frame_err <= ~sin_d0;
cs_state <= idle;
end
counter <= counter - 1'b1;
end
default:
cs_state <= idle;
endcase
end
////////////////////////////////////////////////////////////////////////////////
// Receiver Buffer Register
////////////////////////////////////////////////////////////////////////////////
generate
if (FIFO == 1) begin
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_din <= 0;
fifo_wr <= 0; end
else if ((rx_idle == 1'b1) && (rx_idle_d1 == 1'b0)) begin
if (break_int_int)
begin
fifo_din <= {8'b0, 3'b100};
fifo_wr <= 1'b1;
end
else begin
case (databits)
2'b00: fifo_din <= { 3'b000, rsr[7:3], 1'b0, parity_err_int, frame_err_int};
2'b01: fifo_din <= { 2'b00 , rsr[7:2], 1'b0, parity_err_int, frame_err_int};
2'b10: fifo_din <= { 1'b0 , rsr[7:1], 1'b0, parity_err_int, frame_err_int};
default: fifo_din <= {rsr, 1'b0, parity_err_int, frame_err_int};
endcase
fifo_wr <= 1'b1; end
end
else
fifo_wr <= 1'b0;
end
always @(posedge clk or posedge reset)
if (reset)
fifo_wr_q <= 0;
else
fifo_wr_q <= fifo_wr;
assign fifo_wr_pulse = fifo_wr & ~fifo_wr_q;
rxcver_fifo RX_FIFO(
.Data (fifo_din),
.Clock (clk),
.WrEn (fifo_wr_pulse),
.RdEn (rbr_rd),
.Reset (reset),
.Q (rbr_fifo),
.Q_error (rbr_fifo_error),
.Empty (fifo_empty),
.Full (fifo_full),
.AlmostEmpty (fifo_almost_empty),
.AlmostFull (fifo_almost_full));
end
else begin
always @(posedge clk or posedge reset) begin
if (reset)
rbr <= 0;
else if ((rx_idle == 1'b1) && (rx_idle_d1 == 1'b0))
case (databits)
2'b00: rbr <= { 3'b000, rsr[7:3]};
2'b01: rbr <= { 2'b00 , rsr[7:2]};
2'b10: rbr <= { 1'b0 , rsr[7:1]};
default: rbr <= rsr;
endcase
end
end
endgenerate
////////////////////////////////////////////////////////////////////////////////
// Delayed Signals for edge detections
////////////////////////////////////////////////////////////////////////////////
always @(posedge clk or posedge reset) begin
if (reset) begin
sin_d0 <= 1'b0;
sin_d0_delay <= 1'b0;
end
else begin
// sin_d0 : Signal for rising edge detection of signal sin
// must be registered before using with sin_d1,
// since sin is ASYNCHRONOUS!!! to the system clock
sin_d0 <= sin;
sin_d0_delay <= sin_d0;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
sin_d1 <= 1'b0;
rx_frame_err_d1 <= 1'b1;
end
else begin
//sin_d1 : Signal for falling edge detection of signal SIN
sin_d1 <= sin_d0;
// rx_frame_err_d1 :
// a delayed version of rx_frame_err for detacting the rising edge
// used to resynchronize the next frame after framing error
rx_frame_err_d1 <= rx_frame_err;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
rx_idle_d1 <= 1'b1;
end
else begin
// rx_idle_d1 : Signal for rising edge detection of signal rx_idle
rx_idle_d1 <= rx_idle;
end
end
////////////////////////////////////////////////////////////////////////////////
// Generate Error Flags
////////////////////////////////////////////////////////////////////////////////
// Receiver Error Flags in lsr
// overrun_err(OE), parity_err(PE), frame_err(FE), break_int(BI)
// will be set to reflect the sin line status only after the whole frame
// (Start bit + Data bits + Parity bit + Stop bit) is received. A rising
// edge of rx_idle indicates the whole frame is received.
generate
if (FIFO == 1) begin
always @(posedge clk or posedge reset) begin
if (reset) begin
parity_err_int <= 1'b0;
frame_err_int <= 1'b0;
break_int_int <= 1'b0;
end
else begin
// Set parity_err flag if rx_parity_err is 1 when Parity enable
parity_err_int <= (rx_parity_err) & parity_en;
// Set frame_err flag if rx_frame_err is 1(Stop bit is sampled low)
frame_err_int <= rx_frame_err;
// Set break_int flag if hunt_one is still low
break_int_int <= (~ hunt_one);
end
end
always @(posedge clk or posedge reset)
if (reset)
overrun_err_int <= 1'b0;
else if (fifo_full && fifo_wr)
overrun_err_int <= 1'b1;
else if (lsr_rd)
overrun_err_int <= 1'b0;
assign overrun_err = overrun_err_int;
assign parity_err = rbr_fifo_error[1];
assign frame_err = rbr_fifo_error[0];
assign break_int = rbr_fifo_error[2];
// Receiver ready for read when data is available in rbr
assign rx_rdy = rbr_datardy;
end
else begin
always @(posedge clk or posedge reset) begin
if (reset) begin
overrun_err_int <= 1'b0;
parity_err_int <= 1'b0;
frame_err_int <= 1'b0;
break_int_int <= 1'b0;
end
else if (rx_idle && !rx_idle_d1) begin // update at rxidle rising
// Set overrun_err flag if RBR data is still not read by CPU
overrun_err_int <= rbr_datardy;
// Set parity_err flag if rx_parity_err is 1 when Parity enable
parity_err_int <= (parity_err_int | rx_parity_err) & parity_en;
// Set frame_err flag if rx_frame_err is 1(Stop bit is sampled low)
frame_err_int <= frame_err_int | rx_frame_err;
// Set break_int flag if hunt_one is still low
break_int_int <= break_int_int | (~ hunt_one);
end
else if (lsr_rd) begin // clear when LSR is read
parity_err_int <= 1'b0;
frame_err_int <= 1'b0;
overrun_err_int <= 1'b0;
break_int_int <= 1'b0;
end
end
assign overrun_err = overrun_err_int;
assign parity_err = parity_err_int;
assign frame_err = frame_err_int;
assign break_int = break_int_int;
// Receiver ready for read when data is available in rbr
assign rx_rdy = rbr_datardy;
end
//`endif
endgenerate
endmodule
`endif // RXCVER_FILE
|
module bram_tb #(
parameter ABITS = 8, DBITS = 8,
parameter INIT_ADDR = 0, INIT_DATA = 0
);
reg clk;
reg [ABITS-1:0] WR_ADDR;
reg [DBITS-1:0] WR_DATA;
reg WR_EN;
reg [ABITS-1:0] RD_ADDR;
wire [DBITS-1:0] RD_DATA;
bram uut (
.clk (clk ),
.WR_ADDR(WR_ADDR),
.WR_DATA(WR_DATA),
.WR_EN (WR_EN ),
.RD_ADDR(RD_ADDR),
.RD_DATA(RD_DATA)
);
reg [63:0] xorshift64_state = 64'd88172645463325252 ^ (ABITS << 24) ^ (DBITS << 16);
task xorshift64_next;
begin
// see page 4 of Marsaglia, George (July 2003). "Xorshift RNGs". Journal of Statistical Software 8 (14).
xorshift64_state = xorshift64_state ^ (xorshift64_state << 13);
xorshift64_state = xorshift64_state ^ (xorshift64_state >> 7);
xorshift64_state = xorshift64_state ^ (xorshift64_state << 17);
end
endtask
reg [ABITS-1:0] randaddr1;
reg [ABITS-1:0] randaddr2;
reg [ABITS-1:0] randaddr3;
function [31:0] getaddr(input [3:0] n);
begin
case (n)
0: getaddr = 0;
1: getaddr = 2**ABITS-1;
2: getaddr = 'b101 << (ABITS / 3);
3: getaddr = 'b101 << (2*ABITS / 3);
4: getaddr = 'b11011 << (ABITS / 4);
5: getaddr = 'b11011 << (2*ABITS / 4);
6: getaddr = 'b11011 << (3*ABITS / 4);
7: getaddr = randaddr1;
8: getaddr = randaddr2;
9: getaddr = randaddr3;
default: begin
getaddr = 1 << (2*n-16);
if (!getaddr) getaddr = xorshift64_state;
end
endcase
end
endfunction
reg [DBITS-1:0] memory [0:2**ABITS-1];
reg [DBITS-1:0] expected_rd, expected_rd_masked;
event error;
integer i, j;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, bram_tb);
memory[INIT_ADDR] <= INIT_DATA;
xorshift64_next;
xorshift64_next;
xorshift64_next;
xorshift64_next;
randaddr1 = xorshift64_state;
xorshift64_next;
randaddr2 = xorshift64_state;
xorshift64_next;
randaddr3 = xorshift64_state;
xorshift64_next;
clk <= 0;
for (i = 0; i < 512; i = i+1) begin
WR_DATA = xorshift64_state;
xorshift64_next;
WR_ADDR = getaddr(i < 256 ? i[7:4] : xorshift64_state[63:60]);
xorshift64_next;
RD_ADDR = i == 0 ? INIT_ADDR : getaddr(i < 256 ? i[3:0] : xorshift64_state[59:56]);
WR_EN = xorshift64_state[55] && ((WR_ADDR & 'hff) != (RD_ADDR & 'hff));
xorshift64_next;
#1; clk <= 1;
#1; clk <= 0;
expected_rd = memory[RD_ADDR];
if (WR_EN) memory[WR_ADDR] = WR_DATA;
for (j = 0; j < DBITS; j = j+1)
expected_rd_masked[j] = expected_rd[j] !== 1'bx ? expected_rd[j] : RD_DATA[j];
$display("#OUT# %3d | WA=%x WD=%x WE=%x | RA=%x RD=%x (%x) | %s",
i, WR_ADDR, WR_DATA, WR_EN, RD_ADDR, RD_DATA, expected_rd,
expected_rd_masked === RD_DATA ? "ok" : "ERROR");
if (expected_rd_masked !== RD_DATA) begin -> error; end
end
end
endmodule
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: crossbar_sasd.v
//
// Description:
// This module is a M-master to N-slave AXI axi_crossbar_v2_1_10_crossbar switch.
// Single transaction issuing, single arbiter (both W&R), single data pathways.
// The interface of this module consists of a vectored slave and master interface
// in which all slots are sized and synchronized to the native width and clock
// of the interconnect, and are all AXI4 protocol.
// All width, clock and protocol conversions are done outside this block, as are
// any pipeline registers or data FIFOs.
// This module contains all arbitration, decoders and channel multiplexing logic.
// It also contains the diagnostic registers and control interface.
//
//--------------------------------------------------------------------------
//
// Structure:
// crossbar_sasd
// addr_arbiter_sasd
// mux_enc
// addr_decoder
// comparator_static
// splitter
// mux_enc
// axic_register_slice
// decerr_slave
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_10_crossbar_sasd #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_SLAVE_SLOTS = 1,
parameter integer C_NUM_MASTER_SLOTS = 1,
parameter integer C_NUM_ADDR_RANGES = 1,
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_PROTOCOL = 0,
parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b1}},
parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_HIGH_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b0}},
parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_BASE_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}},
parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_HIGH_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}},
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_WRITE = {C_NUM_SLAVE_SLOTS{1'b1}},
parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_READ = {C_NUM_SLAVE_SLOTS{1'b1}},
parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_WRITE = {C_NUM_MASTER_SLOTS{1'b1}},
parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_READ = {C_NUM_MASTER_SLOTS{1'b1}},
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY = {C_NUM_SLAVE_SLOTS{32'h00000000}},
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE = {C_NUM_MASTER_SLOTS{32'h00000000}},
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_ERR_MODE = {C_NUM_MASTER_SLOTS{32'h00000000}},
parameter integer C_R_REGISTER = 0,
parameter integer C_RANGE_CHECK = 0,
parameter integer C_ADDR_DECODE = 0,
parameter integer C_DEBUG = 1
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [C_NUM_SLAVE_SLOTS*8-1:0] S_AXI_AWLEN,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_AWSIZE,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_AWBURST,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_AWLOCK,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWCACHE,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_AWPROT,
// input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWREGION,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWQOS,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_AWVALID,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WLAST,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WVALID,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_BRESP,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_BVALID,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [C_NUM_SLAVE_SLOTS*8-1:0] S_AXI_ARLEN,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_ARSIZE,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_ARBURST,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_ARLOCK,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARCACHE,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_ARPROT,
// input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARREGION,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARQOS,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_ARVALID,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_RRESP,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RLAST,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RVALID,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [C_NUM_MASTER_SLOTS*8-1:0] M_AXI_AWLEN,
output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_AWSIZE,
output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_AWBURST,
output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_AWLOCK,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWCACHE,
output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_AWPROT,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWREGION,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWQOS,
output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_AWVALID,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WLAST,
output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WVALID,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_BID, // Unused
input wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_BRESP,
input wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_BVALID,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [C_NUM_MASTER_SLOTS*8-1:0] M_AXI_ARLEN,
output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_ARSIZE,
output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_ARBURST,
output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_ARLOCK,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARCACHE,
output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_ARPROT,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARREGION,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARQOS,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_ARVALID,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_RID, // Unused
input wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_RRESP,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RLAST,
input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RVALID,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RREADY
);
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
localparam integer P_NUM_MASTER_SLOTS_DE = C_RANGE_CHECK ? C_NUM_MASTER_SLOTS+1 : C_NUM_MASTER_SLOTS;
localparam integer P_NUM_MASTER_SLOTS_LOG = (C_NUM_MASTER_SLOTS>1) ? f_ceil_log2(C_NUM_MASTER_SLOTS) : 1;
localparam integer P_NUM_MASTER_SLOTS_DE_LOG = (P_NUM_MASTER_SLOTS_DE>1) ? f_ceil_log2(P_NUM_MASTER_SLOTS_DE) : 1;
localparam integer P_NUM_SLAVE_SLOTS_LOG = (C_NUM_SLAVE_SLOTS>1) ? f_ceil_log2(C_NUM_SLAVE_SLOTS) : 1;
localparam integer P_AXI_AUSER_WIDTH = (C_AXI_AWUSER_WIDTH > C_AXI_ARUSER_WIDTH) ? C_AXI_AWUSER_WIDTH : C_AXI_ARUSER_WIDTH;
localparam integer P_AXI_WID_WIDTH = (C_AXI_PROTOCOL == P_AXI3) ? C_AXI_ID_WIDTH : 1;
localparam integer P_AMESG_WIDTH = C_AXI_ID_WIDTH + C_AXI_ADDR_WIDTH + 8+3+2+3+2+4+4 + P_AXI_AUSER_WIDTH + 4;
localparam integer P_BMESG_WIDTH = 2 + C_AXI_BUSER_WIDTH;
localparam integer P_RMESG_WIDTH = 1+2 + C_AXI_DATA_WIDTH + C_AXI_RUSER_WIDTH;
localparam integer P_WMESG_WIDTH = 1 + C_AXI_DATA_WIDTH + C_AXI_DATA_WIDTH/8 + C_AXI_WUSER_WIDTH + P_AXI_WID_WIDTH;
localparam [31:0] P_AXILITE_ERRMODE = 32'h00000001;
localparam integer P_NONSECURE_BIT = 1;
localparam [C_NUM_MASTER_SLOTS-1:0] P_M_SECURE_MASK = f_bit32to1_mi(C_M_AXI_SECURE); // Mask of secure MI-slots
localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXILITE_MASK = f_m_axilite(0); // Mask of axilite rule-check MI-slots
localparam [1:0] P_FIXED = 2'b00;
localparam integer P_BYPASS = 0;
localparam integer P_LIGHTWT = 7;
localparam integer P_FULLY_REG = 1;
localparam integer P_R_REG_CONFIG = C_R_REGISTER == 8 ? // "Automatic" reg-slice
(C_RANGE_CHECK ? ((C_AXI_PROTOCOL == P_AXILITE) ? P_LIGHTWT : P_FULLY_REG) : P_BYPASS) : // Bypass if no R-channel mux
C_R_REGISTER;
localparam P_DECERR = 2'b11;
//---------------------------------------------------------------------------
// Functions
//---------------------------------------------------------------------------
// Ceiling of log2(x)
function integer f_ceil_log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
f_ceil_log2 = acc;
end
endfunction
// Isolate thread bits of input S_ID and add to BASE_ID (RNG00) to form MI-side ID value
// only for end-point SI-slots
function [C_AXI_ID_WIDTH-1:0] f_extend_ID
(
input [C_AXI_ID_WIDTH-1:0] s_id,
input integer slot
);
begin
f_extend_ID = C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] | (s_id & (C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] ^ C_S_AXI_HIGH_ID[slot*64+:C_AXI_ID_WIDTH]));
end
endfunction
// Convert Bit32 vector of range [0,1] to Bit1 vector on MI
function [C_NUM_MASTER_SLOTS-1:0] f_bit32to1_mi
(input [C_NUM_MASTER_SLOTS*32-1:0] vec32);
integer mi;
begin
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
f_bit32to1_mi[mi] = vec32[mi*32];
end
end
endfunction
// AxiLite error-checking mask (on MI)
function [C_NUM_MASTER_SLOTS-1:0] f_m_axilite
(
input integer null_arg
);
integer mi;
begin
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
f_m_axilite[mi] = (C_M_AXI_ERR_MODE[mi*32+:32] == P_AXILITE_ERRMODE);
end
end
endfunction
genvar gen_si_slot;
genvar gen_mi_slot;
wire [C_NUM_SLAVE_SLOTS*P_AMESG_WIDTH-1:0] si_awmesg ;
wire [C_NUM_SLAVE_SLOTS*P_AMESG_WIDTH-1:0] si_armesg ;
wire [P_AMESG_WIDTH-1:0] aa_amesg ;
wire [C_AXI_ID_WIDTH-1:0] mi_aid ;
wire [C_AXI_ADDR_WIDTH-1:0] mi_aaddr ;
wire [8-1:0] mi_alen ;
wire [3-1:0] mi_asize ;
wire [2-1:0] mi_alock ;
wire [3-1:0] mi_aprot ;
wire [2-1:0] mi_aburst ;
wire [4-1:0] mi_acache ;
wire [4-1:0] mi_aregion ;
wire [4-1:0] mi_aqos ;
wire [P_AXI_AUSER_WIDTH-1:0] mi_auser ;
wire [4-1:0] target_region ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] aa_grant_hot ;
wire [P_NUM_SLAVE_SLOTS_LOG-1:0] aa_grant_enc ;
wire aa_grant_rnw ;
wire aa_grant_any ;
wire [C_NUM_MASTER_SLOTS-1:0] target_mi_hot ;
wire [P_NUM_MASTER_SLOTS_LOG-1:0] target_mi_enc ;
reg [P_NUM_MASTER_SLOTS_DE-1:0] m_atarget_hot ;
reg [P_NUM_MASTER_SLOTS_DE_LOG-1:0] m_atarget_enc ;
wire [P_NUM_MASTER_SLOTS_DE_LOG-1:0] m_atarget_enc_comb ;
wire match;
wire any_error ;
wire [7:0] m_aerror_i ;
wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_awvalid ;
wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_awready ;
wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_arvalid ;
wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_arready ;
wire aa_awvalid ;
wire aa_awready ;
wire aa_arvalid ;
wire aa_arready ;
wire mi_awvalid_en;
wire mi_awready_mux;
wire mi_arvalid_en;
wire mi_arready_mux;
wire w_transfer_en;
wire w_complete_mux;
wire b_transfer_en;
wire b_complete_mux;
wire r_transfer_en;
wire r_complete_mux;
wire target_secure;
wire target_write;
wire target_read;
wire target_axilite;
wire [P_BMESG_WIDTH-1:0] si_bmesg ;
wire [P_NUM_MASTER_SLOTS_DE*P_BMESG_WIDTH-1:0] mi_bmesg ;
wire [P_NUM_MASTER_SLOTS_DE*2-1:0] mi_bresp ;
wire [P_NUM_MASTER_SLOTS_DE*C_AXI_BUSER_WIDTH-1:0] mi_buser ;
wire [2-1:0] si_bresp ;
wire [C_AXI_BUSER_WIDTH-1:0] si_buser ;
wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_bvalid ;
wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_bready ;
wire aa_bvalid ;
wire aa_bready ;
wire si_bready ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_bvalid;
wire [P_RMESG_WIDTH-1:0] aa_rmesg ;
wire [P_RMESG_WIDTH-1:0] sr_rmesg ;
wire [P_NUM_MASTER_SLOTS_DE*P_RMESG_WIDTH-1:0] mi_rmesg ;
wire [P_NUM_MASTER_SLOTS_DE*2-1:0] mi_rresp ;
wire [P_NUM_MASTER_SLOTS_DE*C_AXI_RUSER_WIDTH-1:0] mi_ruser ;
wire [P_NUM_MASTER_SLOTS_DE*C_AXI_DATA_WIDTH-1:0] mi_rdata ;
wire [P_NUM_MASTER_SLOTS_DE*1-1:0] mi_rlast ;
wire [2-1:0] si_rresp ;
wire [C_AXI_RUSER_WIDTH-1:0] si_ruser ;
wire [C_AXI_DATA_WIDTH-1:0] si_rdata ;
wire si_rlast ;
wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_rvalid ;
wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_rready ;
wire aa_rvalid ;
wire aa_rready ;
wire sr_rvalid ;
wire si_rready ;
wire sr_rready ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_rvalid;
wire [C_NUM_SLAVE_SLOTS*P_WMESG_WIDTH-1:0] si_wmesg ;
wire [P_WMESG_WIDTH-1:0] mi_wmesg ;
wire [C_AXI_ID_WIDTH-1:0] mi_wid ;
wire [C_AXI_DATA_WIDTH-1:0] mi_wdata ;
wire [C_AXI_DATA_WIDTH/8-1:0] mi_wstrb ;
wire [C_AXI_WUSER_WIDTH-1:0] mi_wuser ;
wire [1-1:0] mi_wlast ;
wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_wvalid ;
wire [P_NUM_MASTER_SLOTS_DE-1:0] mi_wready ;
wire aa_wvalid ;
wire aa_wready ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_wready;
reg [7:0] debug_r_beat_cnt_i;
reg [7:0] debug_w_beat_cnt_i;
reg [7:0] debug_aw_trans_seq_i;
reg [7:0] debug_ar_trans_seq_i;
reg aresetn_d = 1'b0; // Reset delay register
always @(posedge ACLK) begin
if (~ARESETN) begin
aresetn_d <= 1'b0;
end else begin
aresetn_d <= ARESETN;
end
end
wire reset;
assign reset = ~aresetn_d;
generate
axi_crossbar_v2_1_10_addr_arbiter_sasd #
(
.C_FAMILY (C_FAMILY),
.C_NUM_S (C_NUM_SLAVE_SLOTS),
.C_NUM_S_LOG (P_NUM_SLAVE_SLOTS_LOG),
.C_AMESG_WIDTH (P_AMESG_WIDTH),
.C_GRANT_ENC (1),
.C_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY)
)
addr_arbiter_inst
(
.ACLK (ACLK),
.ARESET (reset),
// Vector of SI-side AW command request inputs
.S_AWMESG (si_awmesg),
.S_ARMESG (si_armesg),
.S_AWVALID (S_AXI_AWVALID),
.S_AWREADY (S_AXI_AWREADY),
.S_ARVALID (S_AXI_ARVALID),
.S_ARREADY (S_AXI_ARREADY),
.M_GRANT_ENC (aa_grant_enc),
.M_GRANT_HOT (aa_grant_hot), // SI-slot 1-hot mask of granted command
.M_GRANT_ANY (aa_grant_any),
.M_GRANT_RNW (aa_grant_rnw),
.M_AMESG (aa_amesg), // Either S_AWMESG or S_ARMESG, as indicated by M_AWVALID and M_ARVALID.
.M_AWVALID (aa_awvalid),
.M_AWREADY (aa_awready),
.M_ARVALID (aa_arvalid),
.M_ARREADY (aa_arready)
);
if (C_ADDR_DECODE) begin : gen_addr_decoder
axi_crossbar_v2_1_10_addr_decoder #
(
.C_FAMILY (C_FAMILY),
.C_NUM_TARGETS (C_NUM_MASTER_SLOTS),
.C_NUM_TARGETS_LOG (P_NUM_MASTER_SLOTS_LOG),
.C_NUM_RANGES (C_NUM_ADDR_RANGES),
.C_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_TARGET_ENC (1),
.C_TARGET_HOT (1),
.C_REGION_ENC (1),
.C_BASE_ADDR (C_M_AXI_BASE_ADDR),
.C_HIGH_ADDR (C_M_AXI_HIGH_ADDR),
.C_TARGET_QUAL ({C_NUM_MASTER_SLOTS{1'b1}}),
.C_RESOLUTION (2)
)
addr_decoder_inst
(
.ADDR (mi_aaddr),
.TARGET_HOT (target_mi_hot),
.TARGET_ENC (target_mi_enc),
.MATCH (match),
.REGION (target_region)
);
end else begin : gen_no_addr_decoder
assign target_mi_hot = 1;
assign match = 1'b1;
assign target_region = 4'b0000;
end // gen_addr_decoder
// AW-channel arbiter command transfer completes upon completion of both M-side AW-channel transfer and B channel completion.
axi_crossbar_v2_1_10_splitter #
(
.C_NUM_M (3)
)
splitter_aw
(
.ACLK (ACLK),
.ARESET (reset),
.S_VALID (aa_awvalid),
.S_READY (aa_awready),
.M_VALID ({mi_awvalid_en, w_transfer_en, b_transfer_en}),
.M_READY ({mi_awready_mux, w_complete_mux, b_complete_mux})
);
// AR-channel arbiter command transfer completes upon completion of both M-side AR-channel transfer and R channel completion.
axi_crossbar_v2_1_10_splitter #
(
.C_NUM_M (2)
)
splitter_ar
(
.ACLK (ACLK),
.ARESET (reset),
.S_VALID (aa_arvalid),
.S_READY (aa_arready),
.M_VALID ({mi_arvalid_en, r_transfer_en}),
.M_READY ({mi_arready_mux, r_complete_mux})
);
assign target_secure = |(target_mi_hot & P_M_SECURE_MASK);
assign target_write = |(target_mi_hot & C_M_AXI_SUPPORTS_WRITE);
assign target_read = |(target_mi_hot & C_M_AXI_SUPPORTS_READ);
assign target_axilite = |(target_mi_hot & P_M_AXILITE_MASK);
assign any_error = C_RANGE_CHECK && (m_aerror_i != 0); // DECERR if error-detection enabled and any error condition.
assign m_aerror_i[0] = ~match; // Invalid target address
assign m_aerror_i[1] = target_secure && mi_aprot[P_NONSECURE_BIT]; // TrustZone violation
assign m_aerror_i[2] = target_axilite && ((mi_alen != 0) ||
(mi_asize[1:0] == 2'b11) || (mi_asize[2] == 1'b1)); // AxiLite access violation
assign m_aerror_i[3] = (~aa_grant_rnw && ~target_write) ||
(aa_grant_rnw && ~target_read); // R/W direction unsupported by target
assign m_aerror_i[7:4] = 4'b0000; // Reserved
assign m_atarget_enc_comb = any_error ? (P_NUM_MASTER_SLOTS_DE-1) : target_mi_enc; // Select MI slot or decerr_slave
always @(posedge ACLK) begin
if (reset) begin
m_atarget_hot <= 0;
m_atarget_enc <= 0;
end else begin
m_atarget_hot <= {P_NUM_MASTER_SLOTS_DE{aa_grant_any}} & (any_error ? {1'b1, {C_NUM_MASTER_SLOTS{1'b0}}} : {1'b0, target_mi_hot}); // Select MI slot or decerr_slave
m_atarget_enc <= m_atarget_enc_comb;
end
end
// Receive AWREADY from targeted MI.
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (P_NUM_MASTER_SLOTS_DE),
.C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG),
.C_DATA_WIDTH (1)
) mi_awready_mux_inst
(
.S (m_atarget_enc),
.A (mi_awready),
.O (mi_awready_mux),
.OE (mi_awvalid_en)
);
// Receive ARREADY from targeted MI.
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (P_NUM_MASTER_SLOTS_DE),
.C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG),
.C_DATA_WIDTH (1)
) mi_arready_mux_inst
(
.S (m_atarget_enc),
.A (mi_arready),
.O (mi_arready_mux),
.OE (mi_arvalid_en)
);
assign mi_awvalid = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{mi_awvalid_en}}; // Assert AWVALID on targeted MI.
assign mi_arvalid = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{mi_arvalid_en}}; // Assert ARVALID on targeted MI.
assign M_AXI_AWVALID = mi_awvalid[0+:C_NUM_MASTER_SLOTS]; // Propagate to MI slots.
assign M_AXI_ARVALID = mi_arvalid[0+:C_NUM_MASTER_SLOTS]; // Propagate to MI slots.
assign mi_awready[0+:C_NUM_MASTER_SLOTS] = M_AXI_AWREADY; // Copy from MI slots.
assign mi_arready[0+:C_NUM_MASTER_SLOTS] = M_AXI_ARREADY; // Copy from MI slots.
// Receive WREADY from targeted MI.
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (P_NUM_MASTER_SLOTS_DE),
.C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG),
.C_DATA_WIDTH (1)
) mi_wready_mux_inst
(
.S (m_atarget_enc),
.A (mi_wready),
.O (aa_wready),
.OE (w_transfer_en)
);
assign mi_wvalid = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{aa_wvalid}}; // Assert WVALID on targeted MI.
assign si_wready = aa_grant_hot & {C_NUM_SLAVE_SLOTS{aa_wready}}; // Assert WREADY on granted SI.
assign S_AXI_WREADY = si_wready;
assign w_complete_mux = aa_wready & aa_wvalid & mi_wlast; // W burst complete on on designated SI/MI.
// Receive RREADY from granted SI.
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (C_NUM_SLAVE_SLOTS),
.C_SEL_WIDTH (P_NUM_SLAVE_SLOTS_LOG),
.C_DATA_WIDTH (1)
) si_rready_mux_inst
(
.S (aa_grant_enc),
.A (S_AXI_RREADY),
.O (si_rready),
.OE (r_transfer_en)
);
assign sr_rready = si_rready & r_transfer_en;
assign mi_rready = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{aa_rready}}; // Assert RREADY on targeted MI.
assign si_rvalid = aa_grant_hot & {C_NUM_SLAVE_SLOTS{sr_rvalid}}; // Assert RVALID on granted SI.
assign S_AXI_RVALID = si_rvalid;
assign r_complete_mux = sr_rready & sr_rvalid & si_rlast; // R burst complete on on designated SI/MI.
// Receive BREADY from granted SI.
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (C_NUM_SLAVE_SLOTS),
.C_SEL_WIDTH (P_NUM_SLAVE_SLOTS_LOG),
.C_DATA_WIDTH (1)
) si_bready_mux_inst
(
.S (aa_grant_enc),
.A (S_AXI_BREADY),
.O (si_bready),
.OE (b_transfer_en)
);
assign aa_bready = si_bready & b_transfer_en;
assign mi_bready = m_atarget_hot & {P_NUM_MASTER_SLOTS_DE{aa_bready}}; // Assert BREADY on targeted MI.
assign si_bvalid = aa_grant_hot & {C_NUM_SLAVE_SLOTS{aa_bvalid}}; // Assert BVALID on granted SI.
assign S_AXI_BVALID = si_bvalid;
assign b_complete_mux = aa_bready & aa_bvalid; // B transfer complete on on designated SI/MI.
for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_si_amesg
assign si_armesg[gen_si_slot*P_AMESG_WIDTH +: P_AMESG_WIDTH] = { // Concatenate from MSB to LSB
4'b0000,
// S_AXI_ARREGION[gen_si_slot*4+:4],
S_AXI_ARUSER[gen_si_slot*C_AXI_ARUSER_WIDTH +: C_AXI_ARUSER_WIDTH],
S_AXI_ARQOS[gen_si_slot*4+:4],
S_AXI_ARCACHE[gen_si_slot*4+:4],
S_AXI_ARBURST[gen_si_slot*2+:2],
S_AXI_ARPROT[gen_si_slot*3+:3],
S_AXI_ARLOCK[gen_si_slot*2+:2],
S_AXI_ARSIZE[gen_si_slot*3+:3],
S_AXI_ARLEN[gen_si_slot*8+:8],
S_AXI_ARADDR[gen_si_slot*C_AXI_ADDR_WIDTH +: C_AXI_ADDR_WIDTH],
f_extend_ID(S_AXI_ARID[gen_si_slot*C_AXI_ID_WIDTH +: C_AXI_ID_WIDTH], gen_si_slot)
};
assign si_awmesg[gen_si_slot*P_AMESG_WIDTH +: P_AMESG_WIDTH] = { // Concatenate from MSB to LSB
4'b0000,
// S_AXI_AWREGION[gen_si_slot*4+:4],
S_AXI_AWUSER[gen_si_slot*C_AXI_AWUSER_WIDTH +: C_AXI_AWUSER_WIDTH],
S_AXI_AWQOS[gen_si_slot*4+:4],
S_AXI_AWCACHE[gen_si_slot*4+:4],
S_AXI_AWBURST[gen_si_slot*2+:2],
S_AXI_AWPROT[gen_si_slot*3+:3],
S_AXI_AWLOCK[gen_si_slot*2+:2],
S_AXI_AWSIZE[gen_si_slot*3+:3],
S_AXI_AWLEN[gen_si_slot*8+:8],
S_AXI_AWADDR[gen_si_slot*C_AXI_ADDR_WIDTH +: C_AXI_ADDR_WIDTH],
f_extend_ID(S_AXI_AWID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot)
};
end // gen_si_amesg
assign mi_aid = aa_amesg[0 +: C_AXI_ID_WIDTH];
assign mi_aaddr = aa_amesg[C_AXI_ID_WIDTH +: C_AXI_ADDR_WIDTH];
assign mi_alen = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +: 8];
assign mi_asize = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8 +: 3];
assign mi_alock = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3 +: 2];
assign mi_aprot = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2 +: 3];
assign mi_aburst = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3 +: 2];
assign mi_acache = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2 +: 4];
assign mi_aqos = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2+4 +: 4];
assign mi_auser = aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2+4+4 +: P_AXI_AUSER_WIDTH];
assign mi_aregion = (C_ADDR_DECODE != 0) ? target_region : aa_amesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+2+4+4+P_AXI_AUSER_WIDTH +: 4];
// Broadcast AW transfer payload to all MI-slots
assign M_AXI_AWID = {C_NUM_MASTER_SLOTS{mi_aid}};
assign M_AXI_AWADDR = {C_NUM_MASTER_SLOTS{mi_aaddr}};
assign M_AXI_AWLEN = {C_NUM_MASTER_SLOTS{mi_alen }};
assign M_AXI_AWSIZE = {C_NUM_MASTER_SLOTS{mi_asize}};
assign M_AXI_AWLOCK = {C_NUM_MASTER_SLOTS{mi_alock}};
assign M_AXI_AWPROT = {C_NUM_MASTER_SLOTS{mi_aprot}};
assign M_AXI_AWREGION = {C_NUM_MASTER_SLOTS{mi_aregion}};
assign M_AXI_AWBURST = {C_NUM_MASTER_SLOTS{mi_aburst}};
assign M_AXI_AWCACHE = {C_NUM_MASTER_SLOTS{mi_acache}};
assign M_AXI_AWQOS = {C_NUM_MASTER_SLOTS{mi_aqos }};
assign M_AXI_AWUSER = {C_NUM_MASTER_SLOTS{mi_auser[0+:C_AXI_AWUSER_WIDTH] }};
// Broadcast AR transfer payload to all MI-slots
assign M_AXI_ARID = {C_NUM_MASTER_SLOTS{mi_aid}};
assign M_AXI_ARADDR = {C_NUM_MASTER_SLOTS{mi_aaddr}};
assign M_AXI_ARLEN = {C_NUM_MASTER_SLOTS{mi_alen }};
assign M_AXI_ARSIZE = {C_NUM_MASTER_SLOTS{mi_asize}};
assign M_AXI_ARLOCK = {C_NUM_MASTER_SLOTS{mi_alock}};
assign M_AXI_ARPROT = {C_NUM_MASTER_SLOTS{mi_aprot}};
assign M_AXI_ARREGION = {C_NUM_MASTER_SLOTS{mi_aregion}};
assign M_AXI_ARBURST = {C_NUM_MASTER_SLOTS{mi_aburst}};
assign M_AXI_ARCACHE = {C_NUM_MASTER_SLOTS{mi_acache}};
assign M_AXI_ARQOS = {C_NUM_MASTER_SLOTS{mi_aqos }};
assign M_AXI_ARUSER = {C_NUM_MASTER_SLOTS{mi_auser[0+:C_AXI_ARUSER_WIDTH] }};
// W-channel MI handshakes
assign M_AXI_WVALID = mi_wvalid[0+:C_NUM_MASTER_SLOTS];
assign mi_wready[0+:C_NUM_MASTER_SLOTS] = M_AXI_WREADY;
// Broadcast W transfer payload to all MI-slots
assign M_AXI_WLAST = {C_NUM_MASTER_SLOTS{mi_wlast}};
assign M_AXI_WUSER = {C_NUM_MASTER_SLOTS{mi_wuser}};
assign M_AXI_WDATA = {C_NUM_MASTER_SLOTS{mi_wdata}};
assign M_AXI_WSTRB = {C_NUM_MASTER_SLOTS{mi_wstrb}};
assign M_AXI_WID = {C_NUM_MASTER_SLOTS{mi_wid}};
// Broadcast R transfer payload to all SI-slots
assign S_AXI_RLAST = {C_NUM_SLAVE_SLOTS{si_rlast}};
assign S_AXI_RRESP = {C_NUM_SLAVE_SLOTS{si_rresp}};
assign S_AXI_RUSER = {C_NUM_SLAVE_SLOTS{si_ruser}};
assign S_AXI_RDATA = {C_NUM_SLAVE_SLOTS{si_rdata}};
assign S_AXI_RID = {C_NUM_SLAVE_SLOTS{mi_aid}};
// Broadcast B transfer payload to all SI-slots
assign S_AXI_BRESP = {C_NUM_SLAVE_SLOTS{si_bresp}};
assign S_AXI_BUSER = {C_NUM_SLAVE_SLOTS{si_buser}};
assign S_AXI_BID = {C_NUM_SLAVE_SLOTS{mi_aid}};
if (C_NUM_SLAVE_SLOTS>1) begin : gen_wmux
// SI WVALID mux.
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (C_NUM_SLAVE_SLOTS),
.C_SEL_WIDTH (P_NUM_SLAVE_SLOTS_LOG),
.C_DATA_WIDTH (1)
) si_w_valid_mux_inst
(
.S (aa_grant_enc),
.A (S_AXI_WVALID),
.O (aa_wvalid),
.OE (w_transfer_en)
);
// SI W-channel payload mux
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (C_NUM_SLAVE_SLOTS),
.C_SEL_WIDTH (P_NUM_SLAVE_SLOTS_LOG),
.C_DATA_WIDTH (P_WMESG_WIDTH)
) si_w_payload_mux_inst
(
.S (aa_grant_enc),
.A (si_wmesg),
.O (mi_wmesg),
.OE (1'b1)
);
for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_wmesg
assign si_wmesg[gen_si_slot*P_WMESG_WIDTH+:P_WMESG_WIDTH] = { // Concatenate from MSB to LSB
((C_AXI_PROTOCOL == P_AXI3) ? f_extend_ID(S_AXI_WID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot) : 1'b0),
S_AXI_WUSER[gen_si_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH],
S_AXI_WSTRB[gen_si_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8],
S_AXI_WDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH],
S_AXI_WLAST[gen_si_slot*1+:1]
};
end // gen_wmesg
assign mi_wlast = mi_wmesg[0];
assign mi_wdata = mi_wmesg[1 +: C_AXI_DATA_WIDTH];
assign mi_wstrb = mi_wmesg[1+C_AXI_DATA_WIDTH +: C_AXI_DATA_WIDTH/8];
assign mi_wuser = mi_wmesg[1+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8 +: C_AXI_WUSER_WIDTH];
assign mi_wid = mi_wmesg[1+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8+C_AXI_WUSER_WIDTH +: P_AXI_WID_WIDTH];
end else begin : gen_no_wmux
assign aa_wvalid = w_transfer_en & S_AXI_WVALID;
assign mi_wlast = S_AXI_WLAST;
assign mi_wdata = S_AXI_WDATA;
assign mi_wstrb = S_AXI_WSTRB;
assign mi_wuser = S_AXI_WUSER;
assign mi_wid = S_AXI_WID;
end // gen_wmux
// Receive RVALID from targeted MI.
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (P_NUM_MASTER_SLOTS_DE),
.C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG),
.C_DATA_WIDTH (1)
) mi_rvalid_mux_inst
(
.S (m_atarget_enc),
.A (mi_rvalid),
.O (aa_rvalid),
.OE (r_transfer_en)
);
// MI R-channel payload mux
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (P_NUM_MASTER_SLOTS_DE),
.C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG),
.C_DATA_WIDTH (P_RMESG_WIDTH)
) mi_rmesg_mux_inst
(
.S (m_atarget_enc),
.A (mi_rmesg),
.O (aa_rmesg),
.OE (1'b1)
);
axi_register_slice_v2_1_9_axic_register_slice #
(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (P_RMESG_WIDTH),
.C_REG_CONFIG (P_R_REG_CONFIG)
)
reg_slice_r
(
// System Signals
.ACLK(ACLK),
.ARESET(reset),
// Slave side
.S_PAYLOAD_DATA(aa_rmesg),
.S_VALID(aa_rvalid),
.S_READY(aa_rready),
// Master side
.M_PAYLOAD_DATA(sr_rmesg),
.M_VALID(sr_rvalid),
.M_READY(sr_rready)
);
assign mi_rvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_RVALID;
assign mi_rlast[0+:C_NUM_MASTER_SLOTS] = M_AXI_RLAST;
assign mi_rresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_RRESP;
assign mi_ruser[0+:C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH] = M_AXI_RUSER;
assign mi_rdata[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH] = M_AXI_RDATA;
assign M_AXI_RREADY = mi_rready[0+:C_NUM_MASTER_SLOTS];
for (gen_mi_slot=0; gen_mi_slot<P_NUM_MASTER_SLOTS_DE; gen_mi_slot=gen_mi_slot+1) begin : gen_rmesg
assign mi_rmesg[gen_mi_slot*P_RMESG_WIDTH+:P_RMESG_WIDTH] = { // Concatenate from MSB to LSB
mi_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH],
mi_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH],
mi_rresp[gen_mi_slot*2+:2],
mi_rlast[gen_mi_slot*1+:1]
};
end // gen_rmesg
assign si_rlast = sr_rmesg[0];
assign si_rresp = sr_rmesg[1 +: 2];
assign si_rdata = sr_rmesg[1+2 +: C_AXI_DATA_WIDTH];
assign si_ruser = sr_rmesg[1+2+C_AXI_DATA_WIDTH +: C_AXI_RUSER_WIDTH];
// Receive BVALID from targeted MI.
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (P_NUM_MASTER_SLOTS_DE),
.C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG),
.C_DATA_WIDTH (1)
) mi_bvalid_mux_inst
(
.S (m_atarget_enc),
.A (mi_bvalid),
.O (aa_bvalid),
.OE (b_transfer_en)
);
// MI B-channel payload mux
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (P_NUM_MASTER_SLOTS_DE),
.C_SEL_WIDTH (P_NUM_MASTER_SLOTS_DE_LOG),
.C_DATA_WIDTH (P_BMESG_WIDTH)
) mi_bmesg_mux_inst
(
.S (m_atarget_enc),
.A (mi_bmesg),
.O (si_bmesg),
.OE (1'b1)
);
assign mi_bvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_BVALID;
assign mi_bresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_BRESP;
assign mi_buser[0+:C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH] = M_AXI_BUSER;
assign M_AXI_BREADY = mi_bready[0+:C_NUM_MASTER_SLOTS];
for (gen_mi_slot=0; gen_mi_slot<P_NUM_MASTER_SLOTS_DE; gen_mi_slot=gen_mi_slot+1) begin : gen_bmesg
assign mi_bmesg[gen_mi_slot*P_BMESG_WIDTH+:P_BMESG_WIDTH] = { // Concatenate from MSB to LSB
mi_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH],
mi_bresp[gen_mi_slot*2+:2]
};
end // gen_bmesg
assign si_bresp = si_bmesg[0 +: 2];
assign si_buser = si_bmesg[2 +: C_AXI_BUSER_WIDTH];
if (C_DEBUG) begin : gen_debug_trans_seq
// DEBUG WRITE TRANSACTION SEQUENCE COUNTER
always @(posedge ACLK) begin
if (reset) begin
debug_aw_trans_seq_i <= 1;
end else begin
if (aa_awvalid && aa_awready) begin
debug_aw_trans_seq_i <= debug_aw_trans_seq_i + 1;
end
end
end
// DEBUG READ TRANSACTION SEQUENCE COUNTER
always @(posedge ACLK) begin
if (reset) begin
debug_ar_trans_seq_i <= 1;
end else begin
if (aa_arvalid && aa_arready) begin
debug_ar_trans_seq_i <= debug_ar_trans_seq_i + 1;
end
end
end
// DEBUG WRITE BEAT COUNTER
always @(posedge ACLK) begin
if (reset) begin
debug_w_beat_cnt_i <= 0;
end else if (aa_wready & aa_wvalid) begin
if (mi_wlast) begin
debug_w_beat_cnt_i <= 0;
end else begin
debug_w_beat_cnt_i <= debug_w_beat_cnt_i + 1;
end
end
end // Clocked process
// DEBUG READ BEAT COUNTER
always @(posedge ACLK) begin
if (reset) begin
debug_r_beat_cnt_i <= 0;
end else if (sr_rready & sr_rvalid) begin
if (si_rlast) begin
debug_r_beat_cnt_i <= 0;
end else begin
debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1;
end
end
end // Clocked process
end // gen_debug_trans_seq
if (C_RANGE_CHECK) begin : gen_decerr
// Highest MI-slot (index C_NUM_MASTER_SLOTS) is the error handler
axi_crossbar_v2_1_10_decerr_slave #
(
.C_AXI_ID_WIDTH (1),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_RESP (P_DECERR)
)
decerr_slave_inst
(
.S_AXI_ACLK (ACLK),
.S_AXI_ARESET (reset),
.S_AXI_AWID (1'b0),
.S_AXI_AWVALID (mi_awvalid[C_NUM_MASTER_SLOTS]),
.S_AXI_AWREADY (mi_awready[C_NUM_MASTER_SLOTS]),
.S_AXI_WLAST (mi_wlast),
.S_AXI_WVALID (mi_wvalid[C_NUM_MASTER_SLOTS]),
.S_AXI_WREADY (mi_wready[C_NUM_MASTER_SLOTS]),
.S_AXI_BID (),
.S_AXI_BRESP (mi_bresp[C_NUM_MASTER_SLOTS*2+:2]),
.S_AXI_BUSER (mi_buser[C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]),
.S_AXI_BVALID (mi_bvalid[C_NUM_MASTER_SLOTS]),
.S_AXI_BREADY (mi_bready[C_NUM_MASTER_SLOTS]),
.S_AXI_ARID (1'b0),
.S_AXI_ARLEN (mi_alen),
.S_AXI_ARVALID (mi_arvalid[C_NUM_MASTER_SLOTS]),
.S_AXI_ARREADY (mi_arready[C_NUM_MASTER_SLOTS]),
.S_AXI_RID (),
.S_AXI_RDATA (mi_rdata[C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]),
.S_AXI_RRESP (mi_rresp[C_NUM_MASTER_SLOTS*2+:2]),
.S_AXI_RUSER (mi_ruser[C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]),
.S_AXI_RLAST (mi_rlast[C_NUM_MASTER_SLOTS]),
.S_AXI_RVALID (mi_rvalid[C_NUM_MASTER_SLOTS]),
.S_AXI_RREADY (mi_rready[C_NUM_MASTER_SLOTS])
);
end // gen_decerr
endgenerate
endmodule
`default_nettype wire
|
module main;
reg pass = 1'b1;
reg v1 = 1'b0;
reg v2 = 1'b0;
reg v3 = 1'b0;
reg v4 = 1'b0;
reg v5 = 1'b0;
reg v6 = 1'b0;
reg v7 = 1'b0;
reg v8 = 1'b0;
reg v9 = 1'b0;
reg v10 = 1'b0;
reg v11 = 1'b0;
reg v12 = 1'b0;
reg cond = 1'b1;
reg [1:0] cval = 2'b00;
always #1 v1 = 1'b1;
always v2 = #1 1'b1;
always if (1'b1) #1 v3 = 1'b1;
// This will pass since the else is optimized away!
always if (1'b1) #1 v4 = 1'b1; else v4 = 1'b0;
always if (cond) #1 v5 = 1'b1; else #1 v5 = 1'b0;
always begin #1 v6 = 1'b1; end // 1
always begin #1; v7 = 1'b1; end // 2
always begin #0; #1 v8 = 1'b1; end // 3
always begin if (cond) #1 v9 = 1'b0; else v9 = 1'b0; #1 v9 = 1'b1; end // 4
always repeat(1) #1 v10 = 1'b1;
always case(cval)
2'b00: #1 v11 = 1'b1;
2'b01: #1 v11 = 1'bx;
default: #1 v11 = 1'bz;
endcase
always definite_delay;
task definite_delay;
#1 v12 = 1'b1;
endtask
initial begin
#3;
if (v1 != 1'b1) begin
$display("Failed delayed assignment.");
pass = 1'b0;
end
if (v2 != 1'b1) begin
$display("Failed intra-assignment delay.");
pass = 1'b0;
end
if (v3 != 1'b1) begin
$display("Failed simple if statement.");
pass = 1'b0;
end
if (v4 != 1'b1) begin
$display("Failed constant if/else statement.");
pass = 1'b0;
end
if (v5 != 1'b1) begin
$display("Failed if/else statement.");
pass = 1'b0;
end
if (v6 != 1'b1) begin
$display("Failed block (1).");
pass = 1'b0;
end
if (v7 != 1'b1) begin
$display("Failed block (2).");
pass = 1'b0;
end
if (v8 != 1'b1) begin
$display("Failed block (3).");
pass = 1'b0;
end
if (v9 != 1'b1) begin
$display("Failed block (4).");
pass = 1'b0;
end
if (v10 != 1'b1) begin
$display("Failed repeat.");
pass = 1'b0;
end
if (v11 != 1'b1) begin
$display("Failed case.");
pass = 1'b0;
end
if (v12 != 1'b1) begin
$display("Failed task.");
pass = 1'b0;
end
if (pass) $display("PASSED");
$finish;
end
endmodule
|
// (c) Copyright 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////
//
// File name: axis_infrastructure_v1_1_0_cdc_handshake
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module axis_infrastructure_v1_1_0_cdc_handshake #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_WIDTH = 32,
parameter integer C_NUM_SYNCHRONIZER_STAGES = 2
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire from_clk,
input wire req,
output wire ack,
input wire [C_WIDTH-1:0] data_in,
input wire to_clk,
output wire data_valid,
output wire [C_WIDTH-1:0] data_out
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
xpm_cdc_handshake #(
.WIDTH ( C_WIDTH ) ,
.DEST_SYNC_FF ( C_NUM_SYNCHRONIZER_STAGES ) ,
.SRC_SYNC_FF ( C_NUM_SYNCHRONIZER_STAGES ) ,
.DEST_EXT_HSK ( 0 ) ,
.SIM_ASSERT_CHK ( 0 )
)
inst_xpm_cdc_handshake (
.src_in ( data_in ) ,
.src_send ( req ) ,
.src_rcv ( ack ) ,
.src_clk ( from_clk ) ,
.dest_out ( data_out ) ,
.dest_req ( data_valid ) ,
.dest_ack ( 1'b0 ) ,
.dest_clk ( to_clk )
);
endmodule // axis_infrastructure_v1_1_0_cdc_handshake
`default_nettype wire
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIeGen2x8If128_pipe_rate.v
// Version : 3.2
//------------------------------------------------------------------------------
// Filename : pipe_rate.v
// Description : PIPE Rate Module for 7 Series Transceiver
// Version : 20.1
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE Rate Module --------------------------------------------------
(* DowngradeIPIdentifiedWarnings = "yes" *)
module PCIeGen2x8If128_pipe_rate #
(
parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_USE_MODE = "3.0", // PCIe use mode
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving
parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_RXBUF_EN = "TRUE", // PCIe RX buffer enable for Gen3 only
parameter TXDATA_WAIT_MAX = 4'd15 // TXDATA wait max
)
(
//---------- Input -------------------------------------
input RATE_CLK,
input RATE_RST_N,
input RATE_RST_IDLE,
input RATE_ACTIVE_LANE,
input [ 1:0] RATE_RATE_IN,
input RATE_CPLLLOCK,
input RATE_QPLLLOCK,
input RATE_MMCM_LOCK,
input RATE_DRP_DONE,
input RATE_RXPMARESETDONE,
input RATE_TXRESETDONE,
input RATE_RXRESETDONE,
input RATE_TXRATEDONE,
input RATE_RXRATEDONE,
input RATE_PHYSTATUS,
input RATE_RESETOVRD_DONE,
input RATE_TXSYNC_DONE,
input RATE_RXSYNC_DONE,
//---------- Output ------------------------------------
output RATE_CPLLPD,
output RATE_QPLLPD,
output RATE_CPLLRESET,
output RATE_QPLLRESET,
output RATE_TXPMARESET,
output RATE_RXPMARESET,
output RATE_DRP_START,
output [ 1:0] RATE_SYSCLKSEL,
output RATE_PCLK_SEL,
output RATE_GEN3,
output RATE_DRP_X16X20_MODE,
output RATE_DRP_X16,
output [ 2:0] RATE_RATE_OUT,
output RATE_RESETOVRD_START,
output RATE_TXSYNC_START,
output RATE_DONE,
output RATE_RXSYNC_START,
output RATE_RXSYNC,
output RATE_IDLE,
output [ 4:0] RATE_FSM
);
//---------- Input FF or Buffer ------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg cplllock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg cplllock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_done_reg2;
//---------- Internal Signals --------------------------
wire pll_lock;
wire [ 2:0] rate;
reg [ 3:0] txdata_wait_cnt = 4'd0;
reg txratedone = 1'd0;
reg rxratedone = 1'd0;
reg phystatus = 1'd0;
reg ratedone = 1'd0;
reg gen3_exit = 1'd0;
//---------- Output FF or Buffer -----------------------
reg cpllpd = 1'd0;
reg qpllpd = 1'd0;
reg cpllreset = 1'd0;
reg qpllreset = 1'd0;
reg txpmareset = 1'd0;
reg rxpmareset = 1'd0;
reg [ 1:0] sysclksel = (PCIE_PLL_SEL == "QPLL") ? 2'd1 : 2'd0;
reg gen3 = 1'd0;
reg pclk_sel = 1'd0;
reg [ 2:0] rate_out = 3'd0;
reg drp_start = 1'd0;
reg drp_x16x20_mode = 1'd0;
reg drp_x16 = 1'd0;
reg [4:0] fsm = 0;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 0;
localparam FSM_PLL_PU = 1; // Gen 3 only
localparam FSM_PLL_PURESET = 2; // Gen 3 only
localparam FSM_PLL_LOCK = 3; // Gen 3 or reset only
localparam FSM_DRP_X16_GEN3_START = 4;
localparam FSM_DRP_X16_GEN3_DONE = 5;
localparam FSM_PMARESET_HOLD = 6; // Gen 3 or reset only
localparam FSM_PLL_SEL = 7; // Gen 3 or reset only
localparam FSM_MMCM_LOCK = 8; // Gen 3 or reset only
localparam FSM_DRP_START = 9; // Gen 3 or reset only
localparam FSM_DRP_DONE = 10; // Gen 3 or reset only
localparam FSM_PMARESET_RELEASE = 11; // Gen 3 only
localparam FSM_PMARESET_DONE = 12; // Gen 3 only
localparam FSM_TXDATA_WAIT = 13;
localparam FSM_PCLK_SEL = 14;
localparam FSM_DRP_X16_START = 15;
localparam FSM_DRP_X16_DONE = 16;
localparam FSM_RATE_SEL = 17;
localparam FSM_RXPMARESETDONE = 18;
localparam FSM_DRP_X20_START = 19;
localparam FSM_DRP_X20_DONE = 20;
localparam FSM_RATE_DONE = 21;
localparam FSM_RESETOVRD_START = 22; // PCIe use mode 1.0 only
localparam FSM_RESETOVRD_DONE = 23; // PCIe use mode 1.0 only
localparam FSM_PLL_PDRESET = 24;
localparam FSM_PLL_PD = 25;
localparam FSM_TXSYNC_START = 26;
localparam FSM_TXSYNC_DONE = 27;
localparam FSM_DONE = 28; // Must sync value to pipe_user.v
localparam FSM_RXSYNC_START = 29; // Gen 3 only
localparam FSM_RXSYNC_DONE = 30; // Gen 3 only
//---------- Input FF ----------------------------------------------------------
always @ (posedge RATE_CLK)
begin
if (!RATE_RST_N)
begin
//---------- 1st Stage FF --------------------------
rst_idle_reg1 <= 1'd0;
rate_in_reg1 <= 2'd0;
cplllock_reg1 <= 1'd0;
qplllock_reg1 <= 1'd0;
mmcm_lock_reg1 <= 1'd0;
drp_done_reg1 <= 1'd0;
rxpmaresetdone_reg1 <= 1'd0;
txresetdone_reg1 <= 1'd0;
rxresetdone_reg1 <= 1'd0;
txratedone_reg1 <= 1'd0;
rxratedone_reg1 <= 1'd0;
phystatus_reg1 <= 1'd0;
resetovrd_done_reg1 <= 1'd0;
txsync_done_reg1 <= 1'd0;
rxsync_done_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
rst_idle_reg2 <= 1'd0;
rate_in_reg2 <= 2'd0;
cplllock_reg2 <= 1'd0;
qplllock_reg2 <= 1'd0;
mmcm_lock_reg2 <= 1'd0;
drp_done_reg2 <= 1'd0;
rxpmaresetdone_reg2 <= 1'd0;
txresetdone_reg2 <= 1'd0;
rxresetdone_reg2 <= 1'd0;
txratedone_reg2 <= 1'd0;
rxratedone_reg2 <= 1'd0;
phystatus_reg2 <= 1'd0;
resetovrd_done_reg2 <= 1'd0;
txsync_done_reg2 <= 1'd0;
rxsync_done_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
rst_idle_reg1 <= RATE_RST_IDLE;
rate_in_reg1 <= RATE_RATE_IN;
cplllock_reg1 <= RATE_CPLLLOCK;
qplllock_reg1 <= RATE_QPLLLOCK;
mmcm_lock_reg1 <= RATE_MMCM_LOCK;
drp_done_reg1 <= RATE_DRP_DONE;
rxpmaresetdone_reg1 <= RATE_RXPMARESETDONE;
txresetdone_reg1 <= RATE_TXRESETDONE;
rxresetdone_reg1 <= RATE_RXRESETDONE;
txratedone_reg1 <= RATE_TXRATEDONE;
rxratedone_reg1 <= RATE_RXRATEDONE;
phystatus_reg1 <= RATE_PHYSTATUS;
resetovrd_done_reg1 <= RATE_RESETOVRD_DONE;
txsync_done_reg1 <= RATE_TXSYNC_DONE;
rxsync_done_reg1 <= RATE_RXSYNC_DONE;
//---------- 2nd Stage FF --------------------------
rst_idle_reg2 <= rst_idle_reg1;
rate_in_reg2 <= rate_in_reg1;
cplllock_reg2 <= cplllock_reg1;
qplllock_reg2 <= qplllock_reg1;
mmcm_lock_reg2 <= mmcm_lock_reg1;
drp_done_reg2 <= drp_done_reg1;
rxpmaresetdone_reg2 <= rxpmaresetdone_reg1;
txresetdone_reg2 <= txresetdone_reg1;
rxresetdone_reg2 <= rxresetdone_reg1;
txratedone_reg2 <= txratedone_reg1;
rxratedone_reg2 <= rxratedone_reg1;
phystatus_reg2 <= phystatus_reg1;
resetovrd_done_reg2 <= resetovrd_done_reg1;
txsync_done_reg2 <= txsync_done_reg1;
rxsync_done_reg2 <= rxsync_done_reg1;
end
end
//---------- Select CPLL or QPLL Lock ------------------------------------------
// Gen1 : Wait for QPLL lock if QPLL is used for Gen1/Gen2, else wait for CPLL lock
// Gen2 : Wait for QPLL lock if QPLL is used for Gen1/Gen2, else wait for CPLL lock
// Gen3 : Wait for QPLL lock
//------------------------------------------------------------------------------
assign pll_lock = (rate_in_reg2 == 2'd2) || (PCIE_PLL_SEL == "QPLL") ? qplllock_reg2 : cplllock_reg2;
//---------- Select Rate -------------------------------------------------------
// Gen1 : Div 4 using [TX/RX]OUT_DIV = 4 if QPLL is used for Gen1/Gen2, else div 2 using [TX/RX]OUT_DIV = 2
// Gen2 : Div 2 using [TX/RX]RATE = 3'd2 if QPLL is used for Gen1/Gen2, else div 1 using [TX/RX]RATE = 3'd1
// Gen3 : Div 1 using [TX/RX]OUT_DIV = 1
//------------------------------------------------------------------------------
assign rate = (rate_in_reg2 == 2'd1) && (PCIE_PLL_SEL == "QPLL") ? 3'd2 :
(rate_in_reg2 == 2'd1) && (PCIE_PLL_SEL == "CPLL") ? 3'd1 : 3'd0;
//---------- TXDATA Wait Counter -----------------------------------------------
always @ (posedge RATE_CLK)
begin
if (!RATE_RST_N)
txdata_wait_cnt <= 4'd0;
else
//---------- Increment Wait Counter ----------------
if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt < TXDATA_WAIT_MAX))
txdata_wait_cnt <= txdata_wait_cnt + 4'd1;
//---------- Hold Wait Counter ---------------------
else if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt == TXDATA_WAIT_MAX))
txdata_wait_cnt <= txdata_wait_cnt;
//---------- Reset Wait Counter --------------------
else
txdata_wait_cnt <= 4'd0;
end
//---------- Latch TXRATEDONE, RXRATEDONE, and PHYSTATUS -----------------------
always @ (posedge RATE_CLK)
begin
if (!RATE_RST_N)
begin
txratedone <= 1'd0;
rxratedone <= 1'd0;
phystatus <= 1'd0;
ratedone <= 1'd0;
end
else
begin
if (fsm == FSM_RATE_DONE)
begin
//---------- Latch TXRATEDONE ------------------
if (txratedone_reg2)
txratedone <= 1'd1;
else
txratedone <= txratedone;
//---------- Latch RXRATEDONE ------------------
if (rxratedone_reg2)
rxratedone <= 1'd1;
else
rxratedone <= rxratedone;
//---------- Latch PHYSTATUS -------------------
if (phystatus_reg2)
phystatus <= 1'd1;
else
phystatus <= phystatus;
//---------- Latch Rate Done -------------------
if (rxratedone && txratedone && phystatus)
ratedone <= 1'd1;
else
ratedone <= ratedone;
end
else
begin
txratedone <= 1'd0;
rxratedone <= 1'd0;
phystatus <= 1'd0;
ratedone <= 1'd0;
end
end
end
//---------- PIPE Rate FSM -----------------------------------------------------
always @ (posedge RATE_CLK)
begin
if (!RATE_RST_N)
begin
fsm <= FSM_PLL_LOCK;
gen3_exit <= 1'd0;
cpllpd <= 1'd0;
qpllpd <= 1'd0;
cpllreset <= 1'd0;
qpllreset <= 1'd0;
txpmareset <= 1'd0;
rxpmareset <= 1'd0;
sysclksel <= (PCIE_PLL_SEL == "QPLL") ? 2'd1 : 2'd0;
pclk_sel <= 1'd0;
gen3 <= 1'd0;
rate_out <= 3'd0;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
//---------- Detect Rate Change ----------------
if (rate_in_reg2 != rate_in_reg1)
begin
fsm <= ((rate_in_reg2 == 2'd2) || (rate_in_reg1 == 2'd2)) ? FSM_PLL_PU : FSM_TXDATA_WAIT;
gen3_exit <= (rate_in_reg2 == 2'd2);
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
else
begin
fsm <= FSM_IDLE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
end
//---------- Power-up PLL --------------------------
FSM_PLL_PU :
begin
fsm <= FSM_PLL_PURESET;
gen3_exit <= gen3_exit;
cpllpd <= (PCIE_PLL_SEL == "QPLL");
qpllpd <= 1'd0;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Release PLL Resets --------------------
FSM_PLL_PURESET :
begin
fsm <= FSM_PLL_LOCK;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= (PCIE_PLL_SEL == "QPLL");
qpllreset <= 1'd0;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for PLL Lock ---------------------
FSM_PLL_LOCK :
begin
fsm <= (pll_lock ? ((!rst_idle_reg2 || (rate_in_reg2 == 2'd1)) ? FSM_PMARESET_HOLD : FSM_DRP_X16_GEN3_START) : FSM_PLL_LOCK);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start DRP x16 -------------------------
FSM_DRP_X16_GEN3_START :
begin
fsm <= (!drp_done_reg2) ? FSM_DRP_X16_GEN3_DONE : FSM_DRP_X16_GEN3_START;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd1;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd1;
end
//---------- Wait for DRP x16 Done -----------------
FSM_DRP_X16_GEN3_DONE :
begin
fsm <= drp_done_reg2 ? FSM_PMARESET_HOLD : FSM_DRP_X16_GEN3_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd1;
end
//---------- Hold both PMA in Reset ----------------
// Gen1 : Release PMA Reset
// Gen2 : Release PMA Reset
// Gen3 : Hold PMA Reset
//--------------------------------------------------
FSM_PMARESET_HOLD :
begin
fsm <= FSM_PLL_SEL;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= ((rate_in_reg2 == 2'd2) || gen3_exit);
rxpmareset <= ((rate_in_reg2 == 2'd2) || gen3_exit);
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Select PLL ----------------------------
// Gen1 : QPLL if PCIE_PLL_SEL = QPLL, else CPLL
// Gen2 : QPLL if PCIE_PLL_SEL = QPLL, else CPLL
// Gen3 : QPLL
//--------------------------------------------------
FSM_PLL_SEL :
begin
fsm <= FSM_MMCM_LOCK;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= ((rate_in_reg2 == 2'd2) || (PCIE_PLL_SEL == "QPLL")) ? 2'd1 : 2'd0;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Check for MMCM Lock -------------------
FSM_MMCM_LOCK :
begin
fsm <= (mmcm_lock_reg2 && !rxpmaresetdone_reg2 ? FSM_DRP_START : FSM_MMCM_LOCK);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start DRP -----------------------------
FSM_DRP_START:
begin
fsm <= (!drp_done_reg2 ? FSM_DRP_DONE : FSM_DRP_START);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= ((rate_in_reg2 == 2'd1) || (rate_in_reg2 == 2'd2));
gen3 <= (rate_in_reg2 == 2'd2);
rate_out <= (((rate_in_reg2 == 2'd2) || gen3_exit) ? rate : rate_out);
drp_start <= 1'd1;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for DRP Done ---------------------
FSM_DRP_DONE :
begin
fsm <= ((drp_done_reg2 && pll_lock) ? (rst_idle_reg2 ? FSM_PMARESET_RELEASE : FSM_IDLE): FSM_DRP_DONE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Release PMA Resets --------------------
FSM_PMARESET_RELEASE :
begin
fsm <= FSM_PMARESET_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= 1'd0;
rxpmareset <= 1'd0;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for both TX/RX PMA Reset Dones and PHYSTATUS Deassertion
FSM_PMARESET_DONE :
begin
fsm <= (((rxresetdone_reg2 && txresetdone_reg2 && !phystatus_reg2) || !RATE_ACTIVE_LANE) ? FSM_TXDATA_WAIT : FSM_PMARESET_DONE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for TXDATA to TX[P/N] Latency ----
FSM_TXDATA_WAIT :
begin
fsm <= (txdata_wait_cnt == TXDATA_WAIT_MAX) ? FSM_PCLK_SEL : FSM_TXDATA_WAIT;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Select PCLK Frequency -----------------
// Gen1 : PCLK = 125 MHz
// Gen2 : PCLK = 250 MHz
// Gen3 : PCLK = 250 MHz
//--------------------------------------------------
FSM_PCLK_SEL :
begin
fsm <= ((PCIE_GT_DEVICE == "GTH") && ((rate_in_reg2 == 2'd1) || ((!gen3_exit) && (rate_in_reg2 == 2'd0)))) ? FSM_DRP_X16_START : FSM_RATE_SEL;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= ((rate_in_reg2 == 2'd1) || (rate_in_reg2 == 2'd2));
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start DRP x16 -------------------------
FSM_DRP_X16_START :
begin
fsm <= (!drp_done_reg2) ? FSM_DRP_X16_DONE : FSM_DRP_X16_START;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd1;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd1;
end
//---------- Wait for DRP x16 Done -----------------
FSM_DRP_X16_DONE :
begin
fsm <= drp_done_reg2 ? FSM_RATE_SEL : FSM_DRP_X16_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd1;
end
//---------- Select Rate ---------------------------
FSM_RATE_SEL :
begin
fsm <= ((PCIE_GT_DEVICE == "GTH") && ((rate_in_reg2 == 2'd1) || ((!gen3_exit) && (rate_in_reg2 == 2'd0)))) ? FSM_RXPMARESETDONE : FSM_RATE_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate; // Update [TX/RX]RATE
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for RXPMARESETDONE De-assertion --
FSM_RXPMARESETDONE :
begin
fsm <= (!rxpmaresetdone_reg2) ? FSM_DRP_X20_START : FSM_RXPMARESETDONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start DRP x20 -------------------------
FSM_DRP_X20_START :
begin
fsm <= (!drp_done_reg2) ? FSM_DRP_X20_DONE : FSM_DRP_X20_START;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd1;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd0;
end
//---------- Wait for DRP x20 Done -----------------
FSM_DRP_X20_DONE :
begin
fsm <= drp_done_reg2 ? FSM_RATE_DONE : FSM_DRP_X20_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd0;
end
//---------- Wait for Rate Change Done -------------
FSM_RATE_DONE :
begin
if (ratedone || (rate_in_reg2 == 2'd2) || (gen3_exit) || !RATE_ACTIVE_LANE)
if ((PCIE_USE_MODE == "1.0") && (rate_in_reg2 != 2'd2) && (!gen3_exit))
fsm <= FSM_RESETOVRD_START;
else
fsm <= FSM_PLL_PDRESET;
else
fsm <= FSM_RATE_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Reset Override Start ------------------
FSM_RESETOVRD_START:
begin
fsm <= (!resetovrd_done_reg2 ? FSM_RESETOVRD_DONE : FSM_RESETOVRD_START);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Reset Override Done -------------------
FSM_RESETOVRD_DONE :
begin
fsm <= (resetovrd_done_reg2 ? FSM_PLL_PDRESET : FSM_RESETOVRD_DONE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Hold PLL Not Used in Reset ------------
FSM_PLL_PDRESET :
begin
fsm <= FSM_PLL_PD;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= (PCIE_PLL_SEL == "QPLL") ? 1'd1 : (rate_in_reg2 == 2'd2);
qpllreset <= (PCIE_PLL_SEL == "QPLL") ? 1'd0 : (rate_in_reg2 != 2'd2);
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Power-Down PLL Not Used ---------------
FSM_PLL_PD :
begin
fsm <= (((rate_in_reg2 == 2'd2) || (PCIE_TXBUF_EN == "FALSE")) ? FSM_TXSYNC_START : FSM_DONE);
gen3_exit <= gen3_exit;
cpllpd <= (PCIE_PLL_SEL == "QPLL") ? 1'd1 : (rate_in_reg2 == 2'd2);
qpllpd <= (PCIE_PLL_SEL == "QPLL") ? 1'd0 : (rate_in_reg2 != 2'd2);
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start TX Sync -------------------------
FSM_TXSYNC_START:
begin
fsm <= (!txsync_done_reg2 ? FSM_TXSYNC_DONE : FSM_TXSYNC_START);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for TX Sync Done -----------------
FSM_TXSYNC_DONE:
begin
fsm <= (txsync_done_reg2 ? FSM_DONE : FSM_TXSYNC_DONE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Rate Change Done ----------------------
FSM_DONE :
begin
fsm <= (((rate_in_reg2 == 2'd2) && (PCIE_RXBUF_EN == "FALSE") && (PCIE_ASYNC_EN == "TRUE")) ? FSM_RXSYNC_START : FSM_IDLE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start RX Sync -------------------------
FSM_RXSYNC_START:
begin
fsm <= (!rxsync_done_reg2 ? FSM_RXSYNC_DONE : FSM_RXSYNC_START);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for RX Sync Done -----------------
FSM_RXSYNC_DONE:
begin
fsm <= (rxsync_done_reg2 ? FSM_IDLE : FSM_RXSYNC_DONE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_IDLE;
gen3_exit <= 1'd0;
cpllpd <= 1'd0;
qpllpd <= 1'd0;
cpllreset <= 1'd0;
qpllreset <= 1'd0;
txpmareset <= 1'd0;
rxpmareset <= 1'd0;
sysclksel <= (PCIE_PLL_SEL == "QPLL") ? 2'd1 : 2'd0;
pclk_sel <= 1'd0;
gen3 <= 1'd0;
rate_out <= 3'd0;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
endcase
end
end
//---------- PIPE Rate Output --------------------------------------------------
assign RATE_CPLLPD = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : cpllpd);
assign RATE_QPLLPD = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : qpllpd);
assign RATE_CPLLRESET = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : cpllreset);
assign RATE_QPLLRESET = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : qpllreset);
assign RATE_TXPMARESET = txpmareset;
assign RATE_RXPMARESET = rxpmareset;
assign RATE_SYSCLKSEL = sysclksel;
//assign RATE_DRP_START = (fsm == FSM_DRP_START) || (fsm == FSM_DRP_X16_GEN3_START) || (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START);
assign RATE_DRP_START = drp_start;
//assign RATE_DRP_X16X20_MODE = (fsm == FSM_DRP_X16_GEN3_START) || (fsm == FSM_DRP_X16_GEN3_DONE) ||
// (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE) ||
// (fsm == FSM_DRP_X20_START) || (fsm == FSM_DRP_X20_DONE);
assign RATE_DRP_X16X20_MODE = drp_x16x20_mode;
//assign RATE_DRP_X16 = (fsm == FSM_DRP_X16_GEN3_START) || (fsm == FSM_DRP_X16_GEN3_DONE) ||
// (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE);
assign RATE_DRP_X16 = drp_x16;
assign RATE_PCLK_SEL = pclk_sel;
assign RATE_GEN3 = gen3;
assign RATE_RATE_OUT = rate_out;
assign RATE_RESETOVRD_START = (fsm == FSM_RESETOVRD_START);
assign RATE_TXSYNC_START = (fsm == FSM_TXSYNC_START);
assign RATE_DONE = (fsm == FSM_DONE);
assign RATE_RXSYNC_START = (fsm == FSM_RXSYNC_START);
assign RATE_RXSYNC = ((fsm == FSM_RXSYNC_START) || (fsm == FSM_RXSYNC_DONE));
assign RATE_IDLE = (fsm == FSM_IDLE);
assign RATE_FSM = fsm;
endmodule
|
// part of NeoGS project (c) 2007-2008 NedoPC
//
// interrupt controller for Z80
module timer(
input wire clk_24mhz,
input wire clk_z80,
input wire [2:0] rate, // z80 clocked
// 3'b000 -- 37500/1
// 3'b001 -- 37500/2
// 3'b010 -- 37500/4
// 3'b011 -- 37500/8
// 3'b100 -- 37500/16
// 3'b101 -- 37500/64
// 3'b110 -- 37500/256
// 3'b111 -- 37500/1024
output reg int_stb
);
reg [ 2:0] ctr5;
reg [16:0] ctr128k;
reg ctrsel;
reg int_sync1,int_sync2,int_sync3;
always @(posedge clk_24mhz)
begin
if( !ctr5[2] )
ctr5 <= ctr5 + 3'd1;
else
ctr5 <= 3'd0;
end
//
initial
ctr128k = 'd0;
always @(posedge clk_24mhz)
begin
if( ctr5[2] )
ctr128k <= ctr128k + 17'd1;
end
always @*
case( rate )
3'b000: ctrsel = ctr128k[6];
3'b001: ctrsel = ctr128k[7];
3'b010: ctrsel = ctr128k[8];
3'b011: ctrsel = ctr128k[9];
3'b100: ctrsel = ctr128k[10];
3'b101: ctrsel = ctr128k[12];
3'b110: ctrsel = ctr128k[14];
3'b111: ctrsel = ctr128k[16];
endcase
// generate interrupt signal in clk_z80 domain
always @(posedge clk_z80)
begin
int_sync3 <= int_sync2;
int_sync2 <= int_sync1;
int_sync1 <= ctrsel;
end
always @(posedge clk_z80)
if( !int_sync2 && int_sync3 )
int_stb <= 1'b1;
else
int_stb <= 1'b0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_MUX_4TO2_BLACKBOX_V
`define SKY130_FD_SC_LP__UDP_MUX_4TO2_BLACKBOX_V
/**
* udp_mux_4to2: Four to one multiplexer with 2 select controls
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_mux_4to2 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_MUX_4TO2_BLACKBOX_V
|
// -- (c) Copyright 1995 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the fifo_generator wrapper file when simulating
// the core. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_data_fifo_v2_1_7_fifo_gen #(
parameter C_FAMILY = "virtex7",
parameter integer C_COMMON_CLOCK = 1,
parameter integer C_SYNCHRONIZER_STAGE = 3,
parameter integer C_FIFO_DEPTH_LOG = 5,
parameter integer C_FIFO_WIDTH = 64,
parameter C_FIFO_TYPE = "lut"
)(
clk,
rst,
wr_clk,
wr_en,
wr_ready,
wr_data,
rd_clk,
rd_en,
rd_valid,
rd_data);
input clk;
input wr_clk;
input rd_clk;
input rst;
input [C_FIFO_WIDTH-1 : 0] wr_data;
input wr_en;
input rd_en;
output [C_FIFO_WIDTH-1 : 0] rd_data;
output wr_ready;
output rd_valid;
wire full;
wire empty;
wire rd_valid = ~empty;
wire wr_ready = ~full;
localparam C_MEMORY_TYPE = (C_FIFO_TYPE == "bram")? 1 : 2;
localparam C_IMPLEMENTATION_TYPE = (C_COMMON_CLOCK == 1)? 0 : 2;
fifo_generator_v13_1_0 #(
.C_COMMON_CLOCK(C_COMMON_CLOCK),
.C_DIN_WIDTH(C_FIFO_WIDTH),
.C_DOUT_WIDTH(C_FIFO_WIDTH),
.C_FAMILY(C_FAMILY),
.C_IMPLEMENTATION_TYPE(C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE(C_MEMORY_TYPE),
.C_RD_DEPTH(1<<C_FIFO_DEPTH_LOG),
.C_RD_PNTR_WIDTH(C_FIFO_DEPTH_LOG),
.C_WR_DEPTH(1<<C_FIFO_DEPTH_LOG),
.C_WR_PNTR_WIDTH(C_FIFO_DEPTH_LOG),
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(2),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(6),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(31),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(30),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(6),
.C_RD_FREQ(1),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(0),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(6),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1)
)
fifo_gen_inst (
.clk(clk),
.din(wr_data),
.dout(rd_data),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_en(wr_en),
.almost_empty(),
.almost_full(),
.axi_ar_data_count(),
.axi_ar_dbiterr(),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(),
.axi_ar_prog_empty(),
.axi_ar_prog_empty_thresh(4'b0),
.axi_ar_prog_full(),
.axi_ar_prog_full_thresh(4'b0),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_underflow(),
.axi_ar_wr_data_count(),
.axi_aw_data_count(),
.axi_aw_dbiterr(),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(),
.axi_aw_prog_empty(),
.axi_aw_prog_empty_thresh(4'b0),
.axi_aw_prog_full(),
.axi_aw_prog_full_thresh(4'b0),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_underflow(),
.axi_aw_wr_data_count(),
.axi_b_data_count(),
.axi_b_dbiterr(),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(),
.axi_b_prog_empty(),
.axi_b_prog_empty_thresh(4'b0),
.axi_b_prog_full(),
.axi_b_prog_full_thresh(4'b0),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_underflow(),
.axi_b_wr_data_count(),
.axi_r_data_count(),
.axi_r_dbiterr(),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(),
.axi_r_prog_empty(),
.axi_r_prog_empty_thresh(10'b0),
.axi_r_prog_full(),
.axi_r_prog_full_thresh(10'b0),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_underflow(),
.axi_r_wr_data_count(),
.axi_w_data_count(),
.axi_w_dbiterr(),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(),
.axi_w_prog_empty(),
.axi_w_prog_empty_thresh(10'b0),
.axi_w_prog_full(),
.axi_w_prog_full_thresh(10'b0),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_underflow(),
.axi_w_wr_data_count(),
.axis_data_count(),
.axis_dbiterr(),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(),
.axis_prog_empty(),
.axis_prog_empty_thresh(10'b0),
.axis_prog_full(),
.axis_prog_full_thresh(10'b0),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_underflow(),
.axis_wr_data_count(),
.backup(1'b0),
.backup_marker(1'b0),
.data_count(),
.dbiterr(),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(),
.m_axi_arburst(),
.m_axi_arcache(),
.m_axi_arid(),
.m_axi_arlen(),
.m_axi_arlock(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arready(1'b0),
.m_axi_arregion(),
.m_axi_arsize(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_awaddr(),
.m_axi_awburst(),
.m_axi_awcache(),
.m_axi_awid(),
.m_axi_awlen(),
.m_axi_awlock(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awready(1'b0),
.m_axi_awregion(),
.m_axi_awsize(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_bid(4'b0),
.m_axi_bready(),
.m_axi_bresp(2'b0),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata(64'b0),
.m_axi_rid(4'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(),
.m_axi_rresp(2'b0),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(),
.m_axi_wid(),
.m_axi_wlast(),
.m_axi_wready(1'b0),
.m_axi_wstrb(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axis_tdata(),
.m_axis_tdest(),
.m_axis_tid(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tready(1'b0),
.m_axis_tstrb(),
.m_axis_tuser(),
.m_axis_tvalid(),
.overflow(),
.prog_empty(),
.prog_empty_thresh(5'b0),
.prog_empty_thresh_assert(5'b0),
.prog_empty_thresh_negate(5'b0),
.prog_full(),
.prog_full_thresh(5'b0),
.prog_full_thresh_assert(5'b0),
.prog_full_thresh_negate(5'b0),
.rd_data_count(),
.rd_rst(1'b0),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr(32'b0),
.s_axi_arburst(2'b0),
.s_axi_arcache(4'b0),
.s_axi_arid(4'b0),
.s_axi_arlen(8'b0),
.s_axi_arlock(2'b0),
.s_axi_arprot(3'b0),
.s_axi_arqos(4'b0),
.s_axi_arready(),
.s_axi_arregion(4'b0),
.s_axi_arsize(3'b0),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr(32'b0),
.s_axi_awburst(2'b0),
.s_axi_awcache(4'b0),
.s_axi_awid(4'b0),
.s_axi_awlen(8'b0),
.s_axi_awlock(2'b0),
.s_axi_awprot(3'b0),
.s_axi_awqos(4'b0),
.s_axi_awready(),
.s_axi_awregion(4'b0),
.s_axi_awsize(3'b0),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(),
.s_axi_bready(1'b0),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_rdata(),
.s_axi_rid(),
.s_axi_rlast(),
.s_axi_rready(1'b0),
.s_axi_rresp(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_wdata(64'b0),
.s_axi_wid(4'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(),
.s_axi_wstrb(8'b0),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata(64'b0),
.s_axis_tdest(4'b0),
.s_axis_tid(8'b0),
.s_axis_tkeep(4'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(),
.s_axis_tstrb(4'b0),
.s_axis_tuser(4'b0),
.s_axis_tvalid(1'b0),
.sbiterr(),
.srst(1'b0),
.underflow(),
.valid(),
.wr_ack(),
.wr_data_count(),
.wr_rst(1'b0),
.wr_rst_busy(),
.rd_rst_busy(),
.sleep(1'b0)
);
endmodule
|
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
//Date : Sun Apr 3 12:37:39 2016
//Host : ubuntu-desktop running 64-bit Ubuntu 14.04.4 LTS
//Command : generate_target design_1.bd
//Design : design_1
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire GND_1;
wire VCC_1;
wire [12:0]axi_bram_ctrl_0_BRAM_PORTA_ADDR;
wire axi_bram_ctrl_0_BRAM_PORTA_CLK;
wire [31:0]axi_bram_ctrl_0_BRAM_PORTA_DIN;
wire [31:0]axi_bram_ctrl_0_BRAM_PORTA_DOUT;
wire axi_bram_ctrl_0_BRAM_PORTA_EN;
wire axi_bram_ctrl_0_BRAM_PORTA_RST;
wire [3:0]axi_bram_ctrl_0_BRAM_PORTA_WE;
wire [12:0]axi_bram_ctrl_1_BRAM_PORTA_ADDR;
wire axi_bram_ctrl_1_BRAM_PORTA_CLK;
wire [31:0]axi_bram_ctrl_1_BRAM_PORTA_DIN;
wire [31:0]axi_bram_ctrl_1_BRAM_PORTA_DOUT;
wire axi_bram_ctrl_1_BRAM_PORTA_EN;
wire axi_bram_ctrl_1_BRAM_PORTA_RST;
wire [3:0]axi_bram_ctrl_1_BRAM_PORTA_WE;
wire [12:0]axi_mem_intercon_1_M00_AXI_ARADDR;
wire [1:0]axi_mem_intercon_1_M00_AXI_ARBURST;
wire [3:0]axi_mem_intercon_1_M00_AXI_ARCACHE;
wire [11:0]axi_mem_intercon_1_M00_AXI_ARID;
wire [7:0]axi_mem_intercon_1_M00_AXI_ARLEN;
wire [0:0]axi_mem_intercon_1_M00_AXI_ARLOCK;
wire [2:0]axi_mem_intercon_1_M00_AXI_ARPROT;
wire axi_mem_intercon_1_M00_AXI_ARREADY;
wire [2:0]axi_mem_intercon_1_M00_AXI_ARSIZE;
wire axi_mem_intercon_1_M00_AXI_ARVALID;
wire [12:0]axi_mem_intercon_1_M00_AXI_AWADDR;
wire [1:0]axi_mem_intercon_1_M00_AXI_AWBURST;
wire [3:0]axi_mem_intercon_1_M00_AXI_AWCACHE;
wire [11:0]axi_mem_intercon_1_M00_AXI_AWID;
wire [7:0]axi_mem_intercon_1_M00_AXI_AWLEN;
wire [0:0]axi_mem_intercon_1_M00_AXI_AWLOCK;
wire [2:0]axi_mem_intercon_1_M00_AXI_AWPROT;
wire axi_mem_intercon_1_M00_AXI_AWREADY;
wire [2:0]axi_mem_intercon_1_M00_AXI_AWSIZE;
wire axi_mem_intercon_1_M00_AXI_AWVALID;
wire [11:0]axi_mem_intercon_1_M00_AXI_BID;
wire axi_mem_intercon_1_M00_AXI_BREADY;
wire [1:0]axi_mem_intercon_1_M00_AXI_BRESP;
wire axi_mem_intercon_1_M00_AXI_BVALID;
wire [31:0]axi_mem_intercon_1_M00_AXI_RDATA;
wire [11:0]axi_mem_intercon_1_M00_AXI_RID;
wire axi_mem_intercon_1_M00_AXI_RLAST;
wire axi_mem_intercon_1_M00_AXI_RREADY;
wire [1:0]axi_mem_intercon_1_M00_AXI_RRESP;
wire axi_mem_intercon_1_M00_AXI_RVALID;
wire [31:0]axi_mem_intercon_1_M00_AXI_WDATA;
wire axi_mem_intercon_1_M00_AXI_WLAST;
wire axi_mem_intercon_1_M00_AXI_WREADY;
wire [3:0]axi_mem_intercon_1_M00_AXI_WSTRB;
wire axi_mem_intercon_1_M00_AXI_WVALID;
wire [12:0]axi_mem_intercon_M00_AXI_ARADDR;
wire [1:0]axi_mem_intercon_M00_AXI_ARBURST;
wire [3:0]axi_mem_intercon_M00_AXI_ARCACHE;
wire [11:0]axi_mem_intercon_M00_AXI_ARID;
wire [7:0]axi_mem_intercon_M00_AXI_ARLEN;
wire [0:0]axi_mem_intercon_M00_AXI_ARLOCK;
wire [2:0]axi_mem_intercon_M00_AXI_ARPROT;
wire axi_mem_intercon_M00_AXI_ARREADY;
wire [2:0]axi_mem_intercon_M00_AXI_ARSIZE;
wire axi_mem_intercon_M00_AXI_ARVALID;
wire [12:0]axi_mem_intercon_M00_AXI_AWADDR;
wire [1:0]axi_mem_intercon_M00_AXI_AWBURST;
wire [3:0]axi_mem_intercon_M00_AXI_AWCACHE;
wire [11:0]axi_mem_intercon_M00_AXI_AWID;
wire [7:0]axi_mem_intercon_M00_AXI_AWLEN;
wire [0:0]axi_mem_intercon_M00_AXI_AWLOCK;
wire [2:0]axi_mem_intercon_M00_AXI_AWPROT;
wire axi_mem_intercon_M00_AXI_AWREADY;
wire [2:0]axi_mem_intercon_M00_AXI_AWSIZE;
wire axi_mem_intercon_M00_AXI_AWVALID;
wire [11:0]axi_mem_intercon_M00_AXI_BID;
wire axi_mem_intercon_M00_AXI_BREADY;
wire [1:0]axi_mem_intercon_M00_AXI_BRESP;
wire axi_mem_intercon_M00_AXI_BVALID;
wire [31:0]axi_mem_intercon_M00_AXI_RDATA;
wire [11:0]axi_mem_intercon_M00_AXI_RID;
wire axi_mem_intercon_M00_AXI_RLAST;
wire axi_mem_intercon_M00_AXI_RREADY;
wire [1:0]axi_mem_intercon_M00_AXI_RRESP;
wire axi_mem_intercon_M00_AXI_RVALID;
wire [31:0]axi_mem_intercon_M00_AXI_WDATA;
wire axi_mem_intercon_M00_AXI_WLAST;
wire axi_mem_intercon_M00_AXI_WREADY;
wire [3:0]axi_mem_intercon_M00_AXI_WSTRB;
wire axi_mem_intercon_M00_AXI_WVALID;
wire [14:0]processing_system7_0_DDR_ADDR;
wire [2:0]processing_system7_0_DDR_BA;
wire processing_system7_0_DDR_CAS_N;
wire processing_system7_0_DDR_CKE;
wire processing_system7_0_DDR_CK_N;
wire processing_system7_0_DDR_CK_P;
wire processing_system7_0_DDR_CS_N;
wire [3:0]processing_system7_0_DDR_DM;
wire [31:0]processing_system7_0_DDR_DQ;
wire [3:0]processing_system7_0_DDR_DQS_N;
wire [3:0]processing_system7_0_DDR_DQS_P;
wire processing_system7_0_DDR_ODT;
wire processing_system7_0_DDR_RAS_N;
wire processing_system7_0_DDR_RESET_N;
wire processing_system7_0_DDR_WE_N;
wire processing_system7_0_FCLK_CLK0;
wire processing_system7_0_FCLK_RESET0_N;
wire processing_system7_0_FIXED_IO_DDR_VRN;
wire processing_system7_0_FIXED_IO_DDR_VRP;
wire [53:0]processing_system7_0_FIXED_IO_MIO;
wire processing_system7_0_FIXED_IO_PS_CLK;
wire processing_system7_0_FIXED_IO_PS_PORB;
wire processing_system7_0_FIXED_IO_PS_SRSTB;
wire [31:0]processing_system7_0_M_AXI_GP0_ARADDR;
wire [1:0]processing_system7_0_M_AXI_GP0_ARBURST;
wire [3:0]processing_system7_0_M_AXI_GP0_ARCACHE;
wire [11:0]processing_system7_0_M_AXI_GP0_ARID;
wire [3:0]processing_system7_0_M_AXI_GP0_ARLEN;
wire [1:0]processing_system7_0_M_AXI_GP0_ARLOCK;
wire [2:0]processing_system7_0_M_AXI_GP0_ARPROT;
wire [3:0]processing_system7_0_M_AXI_GP0_ARQOS;
wire processing_system7_0_M_AXI_GP0_ARREADY;
wire [2:0]processing_system7_0_M_AXI_GP0_ARSIZE;
wire processing_system7_0_M_AXI_GP0_ARVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_AWADDR;
wire [1:0]processing_system7_0_M_AXI_GP0_AWBURST;
wire [3:0]processing_system7_0_M_AXI_GP0_AWCACHE;
wire [11:0]processing_system7_0_M_AXI_GP0_AWID;
wire [3:0]processing_system7_0_M_AXI_GP0_AWLEN;
wire [1:0]processing_system7_0_M_AXI_GP0_AWLOCK;
wire [2:0]processing_system7_0_M_AXI_GP0_AWPROT;
wire [3:0]processing_system7_0_M_AXI_GP0_AWQOS;
wire processing_system7_0_M_AXI_GP0_AWREADY;
wire [2:0]processing_system7_0_M_AXI_GP0_AWSIZE;
wire processing_system7_0_M_AXI_GP0_AWVALID;
wire [11:0]processing_system7_0_M_AXI_GP0_BID;
wire processing_system7_0_M_AXI_GP0_BREADY;
wire [1:0]processing_system7_0_M_AXI_GP0_BRESP;
wire processing_system7_0_M_AXI_GP0_BVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_RDATA;
wire [11:0]processing_system7_0_M_AXI_GP0_RID;
wire processing_system7_0_M_AXI_GP0_RLAST;
wire processing_system7_0_M_AXI_GP0_RREADY;
wire [1:0]processing_system7_0_M_AXI_GP0_RRESP;
wire processing_system7_0_M_AXI_GP0_RVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_WDATA;
wire [11:0]processing_system7_0_M_AXI_GP0_WID;
wire processing_system7_0_M_AXI_GP0_WLAST;
wire processing_system7_0_M_AXI_GP0_WREADY;
wire [3:0]processing_system7_0_M_AXI_GP0_WSTRB;
wire processing_system7_0_M_AXI_GP0_WVALID;
wire [31:0]processing_system7_0_M_AXI_GP1_ARADDR;
wire [1:0]processing_system7_0_M_AXI_GP1_ARBURST;
wire [3:0]processing_system7_0_M_AXI_GP1_ARCACHE;
wire [11:0]processing_system7_0_M_AXI_GP1_ARID;
wire [3:0]processing_system7_0_M_AXI_GP1_ARLEN;
wire [1:0]processing_system7_0_M_AXI_GP1_ARLOCK;
wire [2:0]processing_system7_0_M_AXI_GP1_ARPROT;
wire [3:0]processing_system7_0_M_AXI_GP1_ARQOS;
wire processing_system7_0_M_AXI_GP1_ARREADY;
wire [2:0]processing_system7_0_M_AXI_GP1_ARSIZE;
wire processing_system7_0_M_AXI_GP1_ARVALID;
wire [31:0]processing_system7_0_M_AXI_GP1_AWADDR;
wire [1:0]processing_system7_0_M_AXI_GP1_AWBURST;
wire [3:0]processing_system7_0_M_AXI_GP1_AWCACHE;
wire [11:0]processing_system7_0_M_AXI_GP1_AWID;
wire [3:0]processing_system7_0_M_AXI_GP1_AWLEN;
wire [1:0]processing_system7_0_M_AXI_GP1_AWLOCK;
wire [2:0]processing_system7_0_M_AXI_GP1_AWPROT;
wire [3:0]processing_system7_0_M_AXI_GP1_AWQOS;
wire processing_system7_0_M_AXI_GP1_AWREADY;
wire [2:0]processing_system7_0_M_AXI_GP1_AWSIZE;
wire processing_system7_0_M_AXI_GP1_AWVALID;
wire [11:0]processing_system7_0_M_AXI_GP1_BID;
wire processing_system7_0_M_AXI_GP1_BREADY;
wire [1:0]processing_system7_0_M_AXI_GP1_BRESP;
wire processing_system7_0_M_AXI_GP1_BVALID;
wire [31:0]processing_system7_0_M_AXI_GP1_RDATA;
wire [11:0]processing_system7_0_M_AXI_GP1_RID;
wire processing_system7_0_M_AXI_GP1_RLAST;
wire processing_system7_0_M_AXI_GP1_RREADY;
wire [1:0]processing_system7_0_M_AXI_GP1_RRESP;
wire processing_system7_0_M_AXI_GP1_RVALID;
wire [31:0]processing_system7_0_M_AXI_GP1_WDATA;
wire [11:0]processing_system7_0_M_AXI_GP1_WID;
wire processing_system7_0_M_AXI_GP1_WLAST;
wire processing_system7_0_M_AXI_GP1_WREADY;
wire [3:0]processing_system7_0_M_AXI_GP1_WSTRB;
wire processing_system7_0_M_AXI_GP1_WVALID;
wire [0:0]rst_processing_system7_0_100M_interconnect_aresetn;
wire [0:0]rst_processing_system7_0_100M_peripheral_aresetn;
GND GND
(.G(GND_1));
VCC VCC
(.P(VCC_1));
(* BMM_INFO_ADDRESS_SPACE = "byte 0x40000000 32 > design_1 blk_mem_gen_0" *)
(* KEEP_HIERARCHY = "yes" *)
design_1_axi_bram_ctrl_0_0 axi_bram_ctrl_0
(.bram_addr_a(axi_bram_ctrl_0_BRAM_PORTA_ADDR),
.bram_clk_a(axi_bram_ctrl_0_BRAM_PORTA_CLK),
.bram_en_a(axi_bram_ctrl_0_BRAM_PORTA_EN),
.bram_rddata_a(axi_bram_ctrl_0_BRAM_PORTA_DOUT),
.bram_rst_a(axi_bram_ctrl_0_BRAM_PORTA_RST),
.bram_we_a(axi_bram_ctrl_0_BRAM_PORTA_WE),
.bram_wrdata_a(axi_bram_ctrl_0_BRAM_PORTA_DIN),
.s_axi_aclk(processing_system7_0_FCLK_CLK0),
.s_axi_araddr(axi_mem_intercon_M00_AXI_ARADDR),
.s_axi_arburst(axi_mem_intercon_M00_AXI_ARBURST),
.s_axi_arcache(axi_mem_intercon_M00_AXI_ARCACHE),
.s_axi_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.s_axi_arid(axi_mem_intercon_M00_AXI_ARID),
.s_axi_arlen(axi_mem_intercon_M00_AXI_ARLEN),
.s_axi_arlock(axi_mem_intercon_M00_AXI_ARLOCK),
.s_axi_arprot(axi_mem_intercon_M00_AXI_ARPROT),
.s_axi_arready(axi_mem_intercon_M00_AXI_ARREADY),
.s_axi_arsize(axi_mem_intercon_M00_AXI_ARSIZE),
.s_axi_arvalid(axi_mem_intercon_M00_AXI_ARVALID),
.s_axi_awaddr(axi_mem_intercon_M00_AXI_AWADDR),
.s_axi_awburst(axi_mem_intercon_M00_AXI_AWBURST),
.s_axi_awcache(axi_mem_intercon_M00_AXI_AWCACHE),
.s_axi_awid(axi_mem_intercon_M00_AXI_AWID),
.s_axi_awlen(axi_mem_intercon_M00_AXI_AWLEN),
.s_axi_awlock(axi_mem_intercon_M00_AXI_AWLOCK),
.s_axi_awprot(axi_mem_intercon_M00_AXI_AWPROT),
.s_axi_awready(axi_mem_intercon_M00_AXI_AWREADY),
.s_axi_awsize(axi_mem_intercon_M00_AXI_AWSIZE),
.s_axi_awvalid(axi_mem_intercon_M00_AXI_AWVALID),
.s_axi_bid(axi_mem_intercon_M00_AXI_BID),
.s_axi_bready(axi_mem_intercon_M00_AXI_BREADY),
.s_axi_bresp(axi_mem_intercon_M00_AXI_BRESP),
.s_axi_bvalid(axi_mem_intercon_M00_AXI_BVALID),
.s_axi_rdata(axi_mem_intercon_M00_AXI_RDATA),
.s_axi_rid(axi_mem_intercon_M00_AXI_RID),
.s_axi_rlast(axi_mem_intercon_M00_AXI_RLAST),
.s_axi_rready(axi_mem_intercon_M00_AXI_RREADY),
.s_axi_rresp(axi_mem_intercon_M00_AXI_RRESP),
.s_axi_rvalid(axi_mem_intercon_M00_AXI_RVALID),
.s_axi_wdata(axi_mem_intercon_M00_AXI_WDATA),
.s_axi_wlast(axi_mem_intercon_M00_AXI_WLAST),
.s_axi_wready(axi_mem_intercon_M00_AXI_WREADY),
.s_axi_wstrb(axi_mem_intercon_M00_AXI_WSTRB),
.s_axi_wvalid(axi_mem_intercon_M00_AXI_WVALID));
design_1_axi_bram_ctrl_1_0 axi_bram_ctrl_1
(.bram_addr_a(axi_bram_ctrl_1_BRAM_PORTA_ADDR),
.bram_clk_a(axi_bram_ctrl_1_BRAM_PORTA_CLK),
.bram_en_a(axi_bram_ctrl_1_BRAM_PORTA_EN),
.bram_rddata_a(axi_bram_ctrl_1_BRAM_PORTA_DOUT),
.bram_rst_a(axi_bram_ctrl_1_BRAM_PORTA_RST),
.bram_we_a(axi_bram_ctrl_1_BRAM_PORTA_WE),
.bram_wrdata_a(axi_bram_ctrl_1_BRAM_PORTA_DIN),
.s_axi_aclk(processing_system7_0_FCLK_CLK0),
.s_axi_araddr(axi_mem_intercon_1_M00_AXI_ARADDR),
.s_axi_arburst(axi_mem_intercon_1_M00_AXI_ARBURST),
.s_axi_arcache(axi_mem_intercon_1_M00_AXI_ARCACHE),
.s_axi_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.s_axi_arid(axi_mem_intercon_1_M00_AXI_ARID),
.s_axi_arlen(axi_mem_intercon_1_M00_AXI_ARLEN),
.s_axi_arlock(axi_mem_intercon_1_M00_AXI_ARLOCK),
.s_axi_arprot(axi_mem_intercon_1_M00_AXI_ARPROT),
.s_axi_arready(axi_mem_intercon_1_M00_AXI_ARREADY),
.s_axi_arsize(axi_mem_intercon_1_M00_AXI_ARSIZE),
.s_axi_arvalid(axi_mem_intercon_1_M00_AXI_ARVALID),
.s_axi_awaddr(axi_mem_intercon_1_M00_AXI_AWADDR),
.s_axi_awburst(axi_mem_intercon_1_M00_AXI_AWBURST),
.s_axi_awcache(axi_mem_intercon_1_M00_AXI_AWCACHE),
.s_axi_awid(axi_mem_intercon_1_M00_AXI_AWID),
.s_axi_awlen(axi_mem_intercon_1_M00_AXI_AWLEN),
.s_axi_awlock(axi_mem_intercon_1_M00_AXI_AWLOCK),
.s_axi_awprot(axi_mem_intercon_1_M00_AXI_AWPROT),
.s_axi_awready(axi_mem_intercon_1_M00_AXI_AWREADY),
.s_axi_awsize(axi_mem_intercon_1_M00_AXI_AWSIZE),
.s_axi_awvalid(axi_mem_intercon_1_M00_AXI_AWVALID),
.s_axi_bid(axi_mem_intercon_1_M00_AXI_BID),
.s_axi_bready(axi_mem_intercon_1_M00_AXI_BREADY),
.s_axi_bresp(axi_mem_intercon_1_M00_AXI_BRESP),
.s_axi_bvalid(axi_mem_intercon_1_M00_AXI_BVALID),
.s_axi_rdata(axi_mem_intercon_1_M00_AXI_RDATA),
.s_axi_rid(axi_mem_intercon_1_M00_AXI_RID),
.s_axi_rlast(axi_mem_intercon_1_M00_AXI_RLAST),
.s_axi_rready(axi_mem_intercon_1_M00_AXI_RREADY),
.s_axi_rresp(axi_mem_intercon_1_M00_AXI_RRESP),
.s_axi_rvalid(axi_mem_intercon_1_M00_AXI_RVALID),
.s_axi_wdata(axi_mem_intercon_1_M00_AXI_WDATA),
.s_axi_wlast(axi_mem_intercon_1_M00_AXI_WLAST),
.s_axi_wready(axi_mem_intercon_1_M00_AXI_WREADY),
.s_axi_wstrb(axi_mem_intercon_1_M00_AXI_WSTRB),
.s_axi_wvalid(axi_mem_intercon_1_M00_AXI_WVALID));
design_1_axi_mem_intercon_0 axi_mem_intercon
(.ACLK(processing_system7_0_FCLK_CLK0),
.ARESETN(rst_processing_system7_0_100M_interconnect_aresetn),
.M00_ACLK(processing_system7_0_FCLK_CLK0),
.M00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M00_AXI_araddr(axi_mem_intercon_M00_AXI_ARADDR),
.M00_AXI_arburst(axi_mem_intercon_M00_AXI_ARBURST),
.M00_AXI_arcache(axi_mem_intercon_M00_AXI_ARCACHE),
.M00_AXI_arid(axi_mem_intercon_M00_AXI_ARID),
.M00_AXI_arlen(axi_mem_intercon_M00_AXI_ARLEN),
.M00_AXI_arlock(axi_mem_intercon_M00_AXI_ARLOCK),
.M00_AXI_arprot(axi_mem_intercon_M00_AXI_ARPROT),
.M00_AXI_arready(axi_mem_intercon_M00_AXI_ARREADY),
.M00_AXI_arsize(axi_mem_intercon_M00_AXI_ARSIZE),
.M00_AXI_arvalid(axi_mem_intercon_M00_AXI_ARVALID),
.M00_AXI_awaddr(axi_mem_intercon_M00_AXI_AWADDR),
.M00_AXI_awburst(axi_mem_intercon_M00_AXI_AWBURST),
.M00_AXI_awcache(axi_mem_intercon_M00_AXI_AWCACHE),
.M00_AXI_awid(axi_mem_intercon_M00_AXI_AWID),
.M00_AXI_awlen(axi_mem_intercon_M00_AXI_AWLEN),
.M00_AXI_awlock(axi_mem_intercon_M00_AXI_AWLOCK),
.M00_AXI_awprot(axi_mem_intercon_M00_AXI_AWPROT),
.M00_AXI_awready(axi_mem_intercon_M00_AXI_AWREADY),
.M00_AXI_awsize(axi_mem_intercon_M00_AXI_AWSIZE),
.M00_AXI_awvalid(axi_mem_intercon_M00_AXI_AWVALID),
.M00_AXI_bid(axi_mem_intercon_M00_AXI_BID),
.M00_AXI_bready(axi_mem_intercon_M00_AXI_BREADY),
.M00_AXI_bresp(axi_mem_intercon_M00_AXI_BRESP),
.M00_AXI_bvalid(axi_mem_intercon_M00_AXI_BVALID),
.M00_AXI_rdata(axi_mem_intercon_M00_AXI_RDATA),
.M00_AXI_rid(axi_mem_intercon_M00_AXI_RID),
.M00_AXI_rlast(axi_mem_intercon_M00_AXI_RLAST),
.M00_AXI_rready(axi_mem_intercon_M00_AXI_RREADY),
.M00_AXI_rresp(axi_mem_intercon_M00_AXI_RRESP),
.M00_AXI_rvalid(axi_mem_intercon_M00_AXI_RVALID),
.M00_AXI_wdata(axi_mem_intercon_M00_AXI_WDATA),
.M00_AXI_wlast(axi_mem_intercon_M00_AXI_WLAST),
.M00_AXI_wready(axi_mem_intercon_M00_AXI_WREADY),
.M00_AXI_wstrb(axi_mem_intercon_M00_AXI_WSTRB),
.M00_AXI_wvalid(axi_mem_intercon_M00_AXI_WVALID),
.S00_ACLK(processing_system7_0_FCLK_CLK0),
.S00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.S00_AXI_araddr(processing_system7_0_M_AXI_GP0_ARADDR),
.S00_AXI_arburst(processing_system7_0_M_AXI_GP0_ARBURST),
.S00_AXI_arcache(processing_system7_0_M_AXI_GP0_ARCACHE),
.S00_AXI_arid(processing_system7_0_M_AXI_GP0_ARID),
.S00_AXI_arlen(processing_system7_0_M_AXI_GP0_ARLEN),
.S00_AXI_arlock(processing_system7_0_M_AXI_GP0_ARLOCK),
.S00_AXI_arprot(processing_system7_0_M_AXI_GP0_ARPROT),
.S00_AXI_arqos(processing_system7_0_M_AXI_GP0_ARQOS),
.S00_AXI_arready(processing_system7_0_M_AXI_GP0_ARREADY),
.S00_AXI_arsize(processing_system7_0_M_AXI_GP0_ARSIZE),
.S00_AXI_arvalid(processing_system7_0_M_AXI_GP0_ARVALID),
.S00_AXI_awaddr(processing_system7_0_M_AXI_GP0_AWADDR),
.S00_AXI_awburst(processing_system7_0_M_AXI_GP0_AWBURST),
.S00_AXI_awcache(processing_system7_0_M_AXI_GP0_AWCACHE),
.S00_AXI_awid(processing_system7_0_M_AXI_GP0_AWID),
.S00_AXI_awlen(processing_system7_0_M_AXI_GP0_AWLEN),
.S00_AXI_awlock(processing_system7_0_M_AXI_GP0_AWLOCK),
.S00_AXI_awprot(processing_system7_0_M_AXI_GP0_AWPROT),
.S00_AXI_awqos(processing_system7_0_M_AXI_GP0_AWQOS),
.S00_AXI_awready(processing_system7_0_M_AXI_GP0_AWREADY),
.S00_AXI_awsize(processing_system7_0_M_AXI_GP0_AWSIZE),
.S00_AXI_awvalid(processing_system7_0_M_AXI_GP0_AWVALID),
.S00_AXI_bid(processing_system7_0_M_AXI_GP0_BID),
.S00_AXI_bready(processing_system7_0_M_AXI_GP0_BREADY),
.S00_AXI_bresp(processing_system7_0_M_AXI_GP0_BRESP),
.S00_AXI_bvalid(processing_system7_0_M_AXI_GP0_BVALID),
.S00_AXI_rdata(processing_system7_0_M_AXI_GP0_RDATA),
.S00_AXI_rid(processing_system7_0_M_AXI_GP0_RID),
.S00_AXI_rlast(processing_system7_0_M_AXI_GP0_RLAST),
.S00_AXI_rready(processing_system7_0_M_AXI_GP0_RREADY),
.S00_AXI_rresp(processing_system7_0_M_AXI_GP0_RRESP),
.S00_AXI_rvalid(processing_system7_0_M_AXI_GP0_RVALID),
.S00_AXI_wdata(processing_system7_0_M_AXI_GP0_WDATA),
.S00_AXI_wid(processing_system7_0_M_AXI_GP0_WID),
.S00_AXI_wlast(processing_system7_0_M_AXI_GP0_WLAST),
.S00_AXI_wready(processing_system7_0_M_AXI_GP0_WREADY),
.S00_AXI_wstrb(processing_system7_0_M_AXI_GP0_WSTRB),
.S00_AXI_wvalid(processing_system7_0_M_AXI_GP0_WVALID));
design_1_axi_mem_intercon_1_0 axi_mem_intercon_1
(.ACLK(processing_system7_0_FCLK_CLK0),
.ARESETN(rst_processing_system7_0_100M_interconnect_aresetn),
.M00_ACLK(processing_system7_0_FCLK_CLK0),
.M00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M00_AXI_araddr(axi_mem_intercon_1_M00_AXI_ARADDR),
.M00_AXI_arburst(axi_mem_intercon_1_M00_AXI_ARBURST),
.M00_AXI_arcache(axi_mem_intercon_1_M00_AXI_ARCACHE),
.M00_AXI_arid(axi_mem_intercon_1_M00_AXI_ARID),
.M00_AXI_arlen(axi_mem_intercon_1_M00_AXI_ARLEN),
.M00_AXI_arlock(axi_mem_intercon_1_M00_AXI_ARLOCK),
.M00_AXI_arprot(axi_mem_intercon_1_M00_AXI_ARPROT),
.M00_AXI_arready(axi_mem_intercon_1_M00_AXI_ARREADY),
.M00_AXI_arsize(axi_mem_intercon_1_M00_AXI_ARSIZE),
.M00_AXI_arvalid(axi_mem_intercon_1_M00_AXI_ARVALID),
.M00_AXI_awaddr(axi_mem_intercon_1_M00_AXI_AWADDR),
.M00_AXI_awburst(axi_mem_intercon_1_M00_AXI_AWBURST),
.M00_AXI_awcache(axi_mem_intercon_1_M00_AXI_AWCACHE),
.M00_AXI_awid(axi_mem_intercon_1_M00_AXI_AWID),
.M00_AXI_awlen(axi_mem_intercon_1_M00_AXI_AWLEN),
.M00_AXI_awlock(axi_mem_intercon_1_M00_AXI_AWLOCK),
.M00_AXI_awprot(axi_mem_intercon_1_M00_AXI_AWPROT),
.M00_AXI_awready(axi_mem_intercon_1_M00_AXI_AWREADY),
.M00_AXI_awsize(axi_mem_intercon_1_M00_AXI_AWSIZE),
.M00_AXI_awvalid(axi_mem_intercon_1_M00_AXI_AWVALID),
.M00_AXI_bid(axi_mem_intercon_1_M00_AXI_BID),
.M00_AXI_bready(axi_mem_intercon_1_M00_AXI_BREADY),
.M00_AXI_bresp(axi_mem_intercon_1_M00_AXI_BRESP),
.M00_AXI_bvalid(axi_mem_intercon_1_M00_AXI_BVALID),
.M00_AXI_rdata(axi_mem_intercon_1_M00_AXI_RDATA),
.M00_AXI_rid(axi_mem_intercon_1_M00_AXI_RID),
.M00_AXI_rlast(axi_mem_intercon_1_M00_AXI_RLAST),
.M00_AXI_rready(axi_mem_intercon_1_M00_AXI_RREADY),
.M00_AXI_rresp(axi_mem_intercon_1_M00_AXI_RRESP),
.M00_AXI_rvalid(axi_mem_intercon_1_M00_AXI_RVALID),
.M00_AXI_wdata(axi_mem_intercon_1_M00_AXI_WDATA),
.M00_AXI_wlast(axi_mem_intercon_1_M00_AXI_WLAST),
.M00_AXI_wready(axi_mem_intercon_1_M00_AXI_WREADY),
.M00_AXI_wstrb(axi_mem_intercon_1_M00_AXI_WSTRB),
.M00_AXI_wvalid(axi_mem_intercon_1_M00_AXI_WVALID),
.S00_ACLK(processing_system7_0_FCLK_CLK0),
.S00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.S00_AXI_araddr(processing_system7_0_M_AXI_GP1_ARADDR),
.S00_AXI_arburst(processing_system7_0_M_AXI_GP1_ARBURST),
.S00_AXI_arcache(processing_system7_0_M_AXI_GP1_ARCACHE),
.S00_AXI_arid(processing_system7_0_M_AXI_GP1_ARID),
.S00_AXI_arlen(processing_system7_0_M_AXI_GP1_ARLEN),
.S00_AXI_arlock(processing_system7_0_M_AXI_GP1_ARLOCK),
.S00_AXI_arprot(processing_system7_0_M_AXI_GP1_ARPROT),
.S00_AXI_arqos(processing_system7_0_M_AXI_GP1_ARQOS),
.S00_AXI_arready(processing_system7_0_M_AXI_GP1_ARREADY),
.S00_AXI_arsize(processing_system7_0_M_AXI_GP1_ARSIZE),
.S00_AXI_arvalid(processing_system7_0_M_AXI_GP1_ARVALID),
.S00_AXI_awaddr(processing_system7_0_M_AXI_GP1_AWADDR),
.S00_AXI_awburst(processing_system7_0_M_AXI_GP1_AWBURST),
.S00_AXI_awcache(processing_system7_0_M_AXI_GP1_AWCACHE),
.S00_AXI_awid(processing_system7_0_M_AXI_GP1_AWID),
.S00_AXI_awlen(processing_system7_0_M_AXI_GP1_AWLEN),
.S00_AXI_awlock(processing_system7_0_M_AXI_GP1_AWLOCK),
.S00_AXI_awprot(processing_system7_0_M_AXI_GP1_AWPROT),
.S00_AXI_awqos(processing_system7_0_M_AXI_GP1_AWQOS),
.S00_AXI_awready(processing_system7_0_M_AXI_GP1_AWREADY),
.S00_AXI_awsize(processing_system7_0_M_AXI_GP1_AWSIZE),
.S00_AXI_awvalid(processing_system7_0_M_AXI_GP1_AWVALID),
.S00_AXI_bid(processing_system7_0_M_AXI_GP1_BID),
.S00_AXI_bready(processing_system7_0_M_AXI_GP1_BREADY),
.S00_AXI_bresp(processing_system7_0_M_AXI_GP1_BRESP),
.S00_AXI_bvalid(processing_system7_0_M_AXI_GP1_BVALID),
.S00_AXI_rdata(processing_system7_0_M_AXI_GP1_RDATA),
.S00_AXI_rid(processing_system7_0_M_AXI_GP1_RID),
.S00_AXI_rlast(processing_system7_0_M_AXI_GP1_RLAST),
.S00_AXI_rready(processing_system7_0_M_AXI_GP1_RREADY),
.S00_AXI_rresp(processing_system7_0_M_AXI_GP1_RRESP),
.S00_AXI_rvalid(processing_system7_0_M_AXI_GP1_RVALID),
.S00_AXI_wdata(processing_system7_0_M_AXI_GP1_WDATA),
.S00_AXI_wid(processing_system7_0_M_AXI_GP1_WID),
.S00_AXI_wlast(processing_system7_0_M_AXI_GP1_WLAST),
.S00_AXI_wready(processing_system7_0_M_AXI_GP1_WREADY),
.S00_AXI_wstrb(processing_system7_0_M_AXI_GP1_WSTRB),
.S00_AXI_wvalid(processing_system7_0_M_AXI_GP1_WVALID));
design_1_blk_mem_gen_0_0 blk_mem_gen_0
(.addra(axi_bram_ctrl_0_BRAM_PORTA_ADDR),
.addrb(axi_bram_ctrl_1_BRAM_PORTA_ADDR),
.clka(axi_bram_ctrl_0_BRAM_PORTA_CLK),
.clkb(axi_bram_ctrl_1_BRAM_PORTA_CLK),
.dina(axi_bram_ctrl_0_BRAM_PORTA_DIN),
.dinb(axi_bram_ctrl_1_BRAM_PORTA_DIN),
.douta(axi_bram_ctrl_0_BRAM_PORTA_DOUT),
.doutb(axi_bram_ctrl_1_BRAM_PORTA_DOUT),
.ena(axi_bram_ctrl_0_BRAM_PORTA_EN),
.enb(axi_bram_ctrl_1_BRAM_PORTA_EN),
.rsta(axi_bram_ctrl_0_BRAM_PORTA_RST),
.rstb(axi_bram_ctrl_1_BRAM_PORTA_RST),
.wea(axi_bram_ctrl_0_BRAM_PORTA_WE),
.web(axi_bram_ctrl_1_BRAM_PORTA_WE));
(* BMM_INFO_PROCESSOR = "ARM > design_1 axi_bram_ctrl_0" *)
(* KEEP_HIERARCHY = "yes" *)
design_1_processing_system7_0_0 processing_system7_0
(.DDR_Addr(DDR_addr[14:0]),
.DDR_BankAddr(DDR_ba[2:0]),
.DDR_CAS_n(DDR_cas_n),
.DDR_CKE(DDR_cke),
.DDR_CS_n(DDR_cs_n),
.DDR_Clk(DDR_ck_p),
.DDR_Clk_n(DDR_ck_n),
.DDR_DM(DDR_dm[3:0]),
.DDR_DQ(DDR_dq[31:0]),
.DDR_DQS(DDR_dqs_p[3:0]),
.DDR_DQS_n(DDR_dqs_n[3:0]),
.DDR_DRSTB(DDR_reset_n),
.DDR_ODT(DDR_odt),
.DDR_RAS_n(DDR_ras_n),
.DDR_VRN(FIXED_IO_ddr_vrn),
.DDR_VRP(FIXED_IO_ddr_vrp),
.DDR_WEB(DDR_we_n),
.FCLK_CLK0(processing_system7_0_FCLK_CLK0),
.FCLK_RESET0_N(processing_system7_0_FCLK_RESET0_N),
.MIO(FIXED_IO_mio[53:0]),
.M_AXI_GP0_ACLK(processing_system7_0_FCLK_CLK0),
.M_AXI_GP0_ARADDR(processing_system7_0_M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(processing_system7_0_M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(processing_system7_0_M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARID(processing_system7_0_M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(processing_system7_0_M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(processing_system7_0_M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(processing_system7_0_M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(processing_system7_0_M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(processing_system7_0_M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(processing_system7_0_M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(processing_system7_0_M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(processing_system7_0_M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(processing_system7_0_M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(processing_system7_0_M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(processing_system7_0_M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(processing_system7_0_M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(processing_system7_0_M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(processing_system7_0_M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(processing_system7_0_M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(processing_system7_0_M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(processing_system7_0_M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(processing_system7_0_M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(processing_system7_0_M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(processing_system7_0_M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(processing_system7_0_M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(processing_system7_0_M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(processing_system7_0_M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(processing_system7_0_M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(processing_system7_0_M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(processing_system7_0_M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(processing_system7_0_M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(processing_system7_0_M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(processing_system7_0_M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(processing_system7_0_M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(processing_system7_0_M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(processing_system7_0_M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(processing_system7_0_M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(processing_system7_0_M_AXI_GP0_WVALID),
.M_AXI_GP1_ACLK(processing_system7_0_FCLK_CLK0),
.M_AXI_GP1_ARADDR(processing_system7_0_M_AXI_GP1_ARADDR),
.M_AXI_GP1_ARBURST(processing_system7_0_M_AXI_GP1_ARBURST),
.M_AXI_GP1_ARCACHE(processing_system7_0_M_AXI_GP1_ARCACHE),
.M_AXI_GP1_ARID(processing_system7_0_M_AXI_GP1_ARID),
.M_AXI_GP1_ARLEN(processing_system7_0_M_AXI_GP1_ARLEN),
.M_AXI_GP1_ARLOCK(processing_system7_0_M_AXI_GP1_ARLOCK),
.M_AXI_GP1_ARPROT(processing_system7_0_M_AXI_GP1_ARPROT),
.M_AXI_GP1_ARQOS(processing_system7_0_M_AXI_GP1_ARQOS),
.M_AXI_GP1_ARREADY(processing_system7_0_M_AXI_GP1_ARREADY),
.M_AXI_GP1_ARSIZE(processing_system7_0_M_AXI_GP1_ARSIZE),
.M_AXI_GP1_ARVALID(processing_system7_0_M_AXI_GP1_ARVALID),
.M_AXI_GP1_AWADDR(processing_system7_0_M_AXI_GP1_AWADDR),
.M_AXI_GP1_AWBURST(processing_system7_0_M_AXI_GP1_AWBURST),
.M_AXI_GP1_AWCACHE(processing_system7_0_M_AXI_GP1_AWCACHE),
.M_AXI_GP1_AWID(processing_system7_0_M_AXI_GP1_AWID),
.M_AXI_GP1_AWLEN(processing_system7_0_M_AXI_GP1_AWLEN),
.M_AXI_GP1_AWLOCK(processing_system7_0_M_AXI_GP1_AWLOCK),
.M_AXI_GP1_AWPROT(processing_system7_0_M_AXI_GP1_AWPROT),
.M_AXI_GP1_AWQOS(processing_system7_0_M_AXI_GP1_AWQOS),
.M_AXI_GP1_AWREADY(processing_system7_0_M_AXI_GP1_AWREADY),
.M_AXI_GP1_AWSIZE(processing_system7_0_M_AXI_GP1_AWSIZE),
.M_AXI_GP1_AWVALID(processing_system7_0_M_AXI_GP1_AWVALID),
.M_AXI_GP1_BID(processing_system7_0_M_AXI_GP1_BID),
.M_AXI_GP1_BREADY(processing_system7_0_M_AXI_GP1_BREADY),
.M_AXI_GP1_BRESP(processing_system7_0_M_AXI_GP1_BRESP),
.M_AXI_GP1_BVALID(processing_system7_0_M_AXI_GP1_BVALID),
.M_AXI_GP1_RDATA(processing_system7_0_M_AXI_GP1_RDATA),
.M_AXI_GP1_RID(processing_system7_0_M_AXI_GP1_RID),
.M_AXI_GP1_RLAST(processing_system7_0_M_AXI_GP1_RLAST),
.M_AXI_GP1_RREADY(processing_system7_0_M_AXI_GP1_RREADY),
.M_AXI_GP1_RRESP(processing_system7_0_M_AXI_GP1_RRESP),
.M_AXI_GP1_RVALID(processing_system7_0_M_AXI_GP1_RVALID),
.M_AXI_GP1_WDATA(processing_system7_0_M_AXI_GP1_WDATA),
.M_AXI_GP1_WID(processing_system7_0_M_AXI_GP1_WID),
.M_AXI_GP1_WLAST(processing_system7_0_M_AXI_GP1_WLAST),
.M_AXI_GP1_WREADY(processing_system7_0_M_AXI_GP1_WREADY),
.M_AXI_GP1_WSTRB(processing_system7_0_M_AXI_GP1_WSTRB),
.M_AXI_GP1_WVALID(processing_system7_0_M_AXI_GP1_WVALID),
.PS_CLK(FIXED_IO_ps_clk),
.PS_PORB(FIXED_IO_ps_porb),
.PS_SRSTB(FIXED_IO_ps_srstb),
.USB0_VBUS_PWRFAULT(GND_1));
design_1_rst_processing_system7_0_100M_0 rst_processing_system7_0_100M
(.aux_reset_in(VCC_1),
.dcm_locked(VCC_1),
.ext_reset_in(processing_system7_0_FCLK_RESET0_N),
.interconnect_aresetn(rst_processing_system7_0_100M_interconnect_aresetn),
.mb_debug_sys_rst(GND_1),
.peripheral_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.slowest_sync_clk(processing_system7_0_FCLK_CLK0));
endmodule
module design_1_axi_mem_intercon_0
(ACLK,
ARESETN,
M00_ACLK,
M00_ARESETN,
M00_AXI_araddr,
M00_AXI_arburst,
M00_AXI_arcache,
M00_AXI_arid,
M00_AXI_arlen,
M00_AXI_arlock,
M00_AXI_arprot,
M00_AXI_arready,
M00_AXI_arsize,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awburst,
M00_AXI_awcache,
M00_AXI_awid,
M00_AXI_awlen,
M00_AXI_awlock,
M00_AXI_awprot,
M00_AXI_awready,
M00_AXI_awsize,
M00_AXI_awvalid,
M00_AXI_bid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rid,
M00_AXI_rlast,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wlast,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
S00_ACLK,
S00_ARESETN,
S00_AXI_araddr,
S00_AXI_arburst,
S00_AXI_arcache,
S00_AXI_arid,
S00_AXI_arlen,
S00_AXI_arlock,
S00_AXI_arprot,
S00_AXI_arqos,
S00_AXI_arready,
S00_AXI_arsize,
S00_AXI_arvalid,
S00_AXI_awaddr,
S00_AXI_awburst,
S00_AXI_awcache,
S00_AXI_awid,
S00_AXI_awlen,
S00_AXI_awlock,
S00_AXI_awprot,
S00_AXI_awqos,
S00_AXI_awready,
S00_AXI_awsize,
S00_AXI_awvalid,
S00_AXI_bid,
S00_AXI_bready,
S00_AXI_bresp,
S00_AXI_bvalid,
S00_AXI_rdata,
S00_AXI_rid,
S00_AXI_rlast,
S00_AXI_rready,
S00_AXI_rresp,
S00_AXI_rvalid,
S00_AXI_wdata,
S00_AXI_wid,
S00_AXI_wlast,
S00_AXI_wready,
S00_AXI_wstrb,
S00_AXI_wvalid);
input ACLK;
input [0:0]ARESETN;
input M00_ACLK;
input [0:0]M00_ARESETN;
output [12:0]M00_AXI_araddr;
output [1:0]M00_AXI_arburst;
output [3:0]M00_AXI_arcache;
output [11:0]M00_AXI_arid;
output [7:0]M00_AXI_arlen;
output [0:0]M00_AXI_arlock;
output [2:0]M00_AXI_arprot;
input M00_AXI_arready;
output [2:0]M00_AXI_arsize;
output M00_AXI_arvalid;
output [12:0]M00_AXI_awaddr;
output [1:0]M00_AXI_awburst;
output [3:0]M00_AXI_awcache;
output [11:0]M00_AXI_awid;
output [7:0]M00_AXI_awlen;
output [0:0]M00_AXI_awlock;
output [2:0]M00_AXI_awprot;
input M00_AXI_awready;
output [2:0]M00_AXI_awsize;
output M00_AXI_awvalid;
input [11:0]M00_AXI_bid;
output M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input M00_AXI_bvalid;
input [31:0]M00_AXI_rdata;
input [11:0]M00_AXI_rid;
input M00_AXI_rlast;
output M00_AXI_rready;
input [1:0]M00_AXI_rresp;
input M00_AXI_rvalid;
output [31:0]M00_AXI_wdata;
output M00_AXI_wlast;
input M00_AXI_wready;
output [3:0]M00_AXI_wstrb;
output M00_AXI_wvalid;
input S00_ACLK;
input [0:0]S00_ARESETN;
input [31:0]S00_AXI_araddr;
input [1:0]S00_AXI_arburst;
input [3:0]S00_AXI_arcache;
input [11:0]S00_AXI_arid;
input [3:0]S00_AXI_arlen;
input [1:0]S00_AXI_arlock;
input [2:0]S00_AXI_arprot;
input [3:0]S00_AXI_arqos;
output S00_AXI_arready;
input [2:0]S00_AXI_arsize;
input S00_AXI_arvalid;
input [31:0]S00_AXI_awaddr;
input [1:0]S00_AXI_awburst;
input [3:0]S00_AXI_awcache;
input [11:0]S00_AXI_awid;
input [3:0]S00_AXI_awlen;
input [1:0]S00_AXI_awlock;
input [2:0]S00_AXI_awprot;
input [3:0]S00_AXI_awqos;
output S00_AXI_awready;
input [2:0]S00_AXI_awsize;
input S00_AXI_awvalid;
output [11:0]S00_AXI_bid;
input S00_AXI_bready;
output [1:0]S00_AXI_bresp;
output S00_AXI_bvalid;
output [31:0]S00_AXI_rdata;
output [11:0]S00_AXI_rid;
output S00_AXI_rlast;
input S00_AXI_rready;
output [1:0]S00_AXI_rresp;
output S00_AXI_rvalid;
input [31:0]S00_AXI_wdata;
input [11:0]S00_AXI_wid;
input S00_AXI_wlast;
output S00_AXI_wready;
input [3:0]S00_AXI_wstrb;
input S00_AXI_wvalid;
wire S00_ACLK_1;
wire [0:0]S00_ARESETN_1;
wire axi_mem_intercon_ACLK_net;
wire [0:0]axi_mem_intercon_ARESETN_net;
wire [31:0]axi_mem_intercon_to_s00_couplers_ARADDR;
wire [1:0]axi_mem_intercon_to_s00_couplers_ARBURST;
wire [3:0]axi_mem_intercon_to_s00_couplers_ARCACHE;
wire [11:0]axi_mem_intercon_to_s00_couplers_ARID;
wire [3:0]axi_mem_intercon_to_s00_couplers_ARLEN;
wire [1:0]axi_mem_intercon_to_s00_couplers_ARLOCK;
wire [2:0]axi_mem_intercon_to_s00_couplers_ARPROT;
wire [3:0]axi_mem_intercon_to_s00_couplers_ARQOS;
wire axi_mem_intercon_to_s00_couplers_ARREADY;
wire [2:0]axi_mem_intercon_to_s00_couplers_ARSIZE;
wire axi_mem_intercon_to_s00_couplers_ARVALID;
wire [31:0]axi_mem_intercon_to_s00_couplers_AWADDR;
wire [1:0]axi_mem_intercon_to_s00_couplers_AWBURST;
wire [3:0]axi_mem_intercon_to_s00_couplers_AWCACHE;
wire [11:0]axi_mem_intercon_to_s00_couplers_AWID;
wire [3:0]axi_mem_intercon_to_s00_couplers_AWLEN;
wire [1:0]axi_mem_intercon_to_s00_couplers_AWLOCK;
wire [2:0]axi_mem_intercon_to_s00_couplers_AWPROT;
wire [3:0]axi_mem_intercon_to_s00_couplers_AWQOS;
wire axi_mem_intercon_to_s00_couplers_AWREADY;
wire [2:0]axi_mem_intercon_to_s00_couplers_AWSIZE;
wire axi_mem_intercon_to_s00_couplers_AWVALID;
wire [11:0]axi_mem_intercon_to_s00_couplers_BID;
wire axi_mem_intercon_to_s00_couplers_BREADY;
wire [1:0]axi_mem_intercon_to_s00_couplers_BRESP;
wire axi_mem_intercon_to_s00_couplers_BVALID;
wire [31:0]axi_mem_intercon_to_s00_couplers_RDATA;
wire [11:0]axi_mem_intercon_to_s00_couplers_RID;
wire axi_mem_intercon_to_s00_couplers_RLAST;
wire axi_mem_intercon_to_s00_couplers_RREADY;
wire [1:0]axi_mem_intercon_to_s00_couplers_RRESP;
wire axi_mem_intercon_to_s00_couplers_RVALID;
wire [31:0]axi_mem_intercon_to_s00_couplers_WDATA;
wire [11:0]axi_mem_intercon_to_s00_couplers_WID;
wire axi_mem_intercon_to_s00_couplers_WLAST;
wire axi_mem_intercon_to_s00_couplers_WREADY;
wire [3:0]axi_mem_intercon_to_s00_couplers_WSTRB;
wire axi_mem_intercon_to_s00_couplers_WVALID;
wire [12:0]s00_couplers_to_axi_mem_intercon_ARADDR;
wire [1:0]s00_couplers_to_axi_mem_intercon_ARBURST;
wire [3:0]s00_couplers_to_axi_mem_intercon_ARCACHE;
wire [11:0]s00_couplers_to_axi_mem_intercon_ARID;
wire [7:0]s00_couplers_to_axi_mem_intercon_ARLEN;
wire [0:0]s00_couplers_to_axi_mem_intercon_ARLOCK;
wire [2:0]s00_couplers_to_axi_mem_intercon_ARPROT;
wire s00_couplers_to_axi_mem_intercon_ARREADY;
wire [2:0]s00_couplers_to_axi_mem_intercon_ARSIZE;
wire s00_couplers_to_axi_mem_intercon_ARVALID;
wire [12:0]s00_couplers_to_axi_mem_intercon_AWADDR;
wire [1:0]s00_couplers_to_axi_mem_intercon_AWBURST;
wire [3:0]s00_couplers_to_axi_mem_intercon_AWCACHE;
wire [11:0]s00_couplers_to_axi_mem_intercon_AWID;
wire [7:0]s00_couplers_to_axi_mem_intercon_AWLEN;
wire [0:0]s00_couplers_to_axi_mem_intercon_AWLOCK;
wire [2:0]s00_couplers_to_axi_mem_intercon_AWPROT;
wire s00_couplers_to_axi_mem_intercon_AWREADY;
wire [2:0]s00_couplers_to_axi_mem_intercon_AWSIZE;
wire s00_couplers_to_axi_mem_intercon_AWVALID;
wire [11:0]s00_couplers_to_axi_mem_intercon_BID;
wire s00_couplers_to_axi_mem_intercon_BREADY;
wire [1:0]s00_couplers_to_axi_mem_intercon_BRESP;
wire s00_couplers_to_axi_mem_intercon_BVALID;
wire [31:0]s00_couplers_to_axi_mem_intercon_RDATA;
wire [11:0]s00_couplers_to_axi_mem_intercon_RID;
wire s00_couplers_to_axi_mem_intercon_RLAST;
wire s00_couplers_to_axi_mem_intercon_RREADY;
wire [1:0]s00_couplers_to_axi_mem_intercon_RRESP;
wire s00_couplers_to_axi_mem_intercon_RVALID;
wire [31:0]s00_couplers_to_axi_mem_intercon_WDATA;
wire s00_couplers_to_axi_mem_intercon_WLAST;
wire s00_couplers_to_axi_mem_intercon_WREADY;
wire [3:0]s00_couplers_to_axi_mem_intercon_WSTRB;
wire s00_couplers_to_axi_mem_intercon_WVALID;
assign M00_AXI_araddr[12:0] = s00_couplers_to_axi_mem_intercon_ARADDR;
assign M00_AXI_arburst[1:0] = s00_couplers_to_axi_mem_intercon_ARBURST;
assign M00_AXI_arcache[3:0] = s00_couplers_to_axi_mem_intercon_ARCACHE;
assign M00_AXI_arid[11:0] = s00_couplers_to_axi_mem_intercon_ARID;
assign M00_AXI_arlen[7:0] = s00_couplers_to_axi_mem_intercon_ARLEN;
assign M00_AXI_arlock[0] = s00_couplers_to_axi_mem_intercon_ARLOCK;
assign M00_AXI_arprot[2:0] = s00_couplers_to_axi_mem_intercon_ARPROT;
assign M00_AXI_arsize[2:0] = s00_couplers_to_axi_mem_intercon_ARSIZE;
assign M00_AXI_arvalid = s00_couplers_to_axi_mem_intercon_ARVALID;
assign M00_AXI_awaddr[12:0] = s00_couplers_to_axi_mem_intercon_AWADDR;
assign M00_AXI_awburst[1:0] = s00_couplers_to_axi_mem_intercon_AWBURST;
assign M00_AXI_awcache[3:0] = s00_couplers_to_axi_mem_intercon_AWCACHE;
assign M00_AXI_awid[11:0] = s00_couplers_to_axi_mem_intercon_AWID;
assign M00_AXI_awlen[7:0] = s00_couplers_to_axi_mem_intercon_AWLEN;
assign M00_AXI_awlock[0] = s00_couplers_to_axi_mem_intercon_AWLOCK;
assign M00_AXI_awprot[2:0] = s00_couplers_to_axi_mem_intercon_AWPROT;
assign M00_AXI_awsize[2:0] = s00_couplers_to_axi_mem_intercon_AWSIZE;
assign M00_AXI_awvalid = s00_couplers_to_axi_mem_intercon_AWVALID;
assign M00_AXI_bready = s00_couplers_to_axi_mem_intercon_BREADY;
assign M00_AXI_rready = s00_couplers_to_axi_mem_intercon_RREADY;
assign M00_AXI_wdata[31:0] = s00_couplers_to_axi_mem_intercon_WDATA;
assign M00_AXI_wlast = s00_couplers_to_axi_mem_intercon_WLAST;
assign M00_AXI_wstrb[3:0] = s00_couplers_to_axi_mem_intercon_WSTRB;
assign M00_AXI_wvalid = s00_couplers_to_axi_mem_intercon_WVALID;
assign S00_ACLK_1 = S00_ACLK;
assign S00_ARESETN_1 = S00_ARESETN[0];
assign S00_AXI_arready = axi_mem_intercon_to_s00_couplers_ARREADY;
assign S00_AXI_awready = axi_mem_intercon_to_s00_couplers_AWREADY;
assign S00_AXI_bid[11:0] = axi_mem_intercon_to_s00_couplers_BID;
assign S00_AXI_bresp[1:0] = axi_mem_intercon_to_s00_couplers_BRESP;
assign S00_AXI_bvalid = axi_mem_intercon_to_s00_couplers_BVALID;
assign S00_AXI_rdata[31:0] = axi_mem_intercon_to_s00_couplers_RDATA;
assign S00_AXI_rid[11:0] = axi_mem_intercon_to_s00_couplers_RID;
assign S00_AXI_rlast = axi_mem_intercon_to_s00_couplers_RLAST;
assign S00_AXI_rresp[1:0] = axi_mem_intercon_to_s00_couplers_RRESP;
assign S00_AXI_rvalid = axi_mem_intercon_to_s00_couplers_RVALID;
assign S00_AXI_wready = axi_mem_intercon_to_s00_couplers_WREADY;
assign axi_mem_intercon_ACLK_net = M00_ACLK;
assign axi_mem_intercon_ARESETN_net = M00_ARESETN[0];
assign axi_mem_intercon_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
assign axi_mem_intercon_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
assign axi_mem_intercon_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
assign axi_mem_intercon_to_s00_couplers_ARID = S00_AXI_arid[11:0];
assign axi_mem_intercon_to_s00_couplers_ARLEN = S00_AXI_arlen[3:0];
assign axi_mem_intercon_to_s00_couplers_ARLOCK = S00_AXI_arlock[1:0];
assign axi_mem_intercon_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
assign axi_mem_intercon_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];
assign axi_mem_intercon_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
assign axi_mem_intercon_to_s00_couplers_ARVALID = S00_AXI_arvalid;
assign axi_mem_intercon_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
assign axi_mem_intercon_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];
assign axi_mem_intercon_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];
assign axi_mem_intercon_to_s00_couplers_AWID = S00_AXI_awid[11:0];
assign axi_mem_intercon_to_s00_couplers_AWLEN = S00_AXI_awlen[3:0];
assign axi_mem_intercon_to_s00_couplers_AWLOCK = S00_AXI_awlock[1:0];
assign axi_mem_intercon_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
assign axi_mem_intercon_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];
assign axi_mem_intercon_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];
assign axi_mem_intercon_to_s00_couplers_AWVALID = S00_AXI_awvalid;
assign axi_mem_intercon_to_s00_couplers_BREADY = S00_AXI_bready;
assign axi_mem_intercon_to_s00_couplers_RREADY = S00_AXI_rready;
assign axi_mem_intercon_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
assign axi_mem_intercon_to_s00_couplers_WID = S00_AXI_wid[11:0];
assign axi_mem_intercon_to_s00_couplers_WLAST = S00_AXI_wlast;
assign axi_mem_intercon_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
assign axi_mem_intercon_to_s00_couplers_WVALID = S00_AXI_wvalid;
assign s00_couplers_to_axi_mem_intercon_ARREADY = M00_AXI_arready;
assign s00_couplers_to_axi_mem_intercon_AWREADY = M00_AXI_awready;
assign s00_couplers_to_axi_mem_intercon_BID = M00_AXI_bid[11:0];
assign s00_couplers_to_axi_mem_intercon_BRESP = M00_AXI_bresp[1:0];
assign s00_couplers_to_axi_mem_intercon_BVALID = M00_AXI_bvalid;
assign s00_couplers_to_axi_mem_intercon_RDATA = M00_AXI_rdata[31:0];
assign s00_couplers_to_axi_mem_intercon_RID = M00_AXI_rid[11:0];
assign s00_couplers_to_axi_mem_intercon_RLAST = M00_AXI_rlast;
assign s00_couplers_to_axi_mem_intercon_RRESP = M00_AXI_rresp[1:0];
assign s00_couplers_to_axi_mem_intercon_RVALID = M00_AXI_rvalid;
assign s00_couplers_to_axi_mem_intercon_WREADY = M00_AXI_wready;
s00_couplers_imp_7HNO1D s00_couplers
(.M_ACLK(axi_mem_intercon_ACLK_net),
.M_ARESETN(axi_mem_intercon_ARESETN_net),
.M_AXI_araddr(s00_couplers_to_axi_mem_intercon_ARADDR),
.M_AXI_arburst(s00_couplers_to_axi_mem_intercon_ARBURST),
.M_AXI_arcache(s00_couplers_to_axi_mem_intercon_ARCACHE),
.M_AXI_arid(s00_couplers_to_axi_mem_intercon_ARID),
.M_AXI_arlen(s00_couplers_to_axi_mem_intercon_ARLEN),
.M_AXI_arlock(s00_couplers_to_axi_mem_intercon_ARLOCK),
.M_AXI_arprot(s00_couplers_to_axi_mem_intercon_ARPROT),
.M_AXI_arready(s00_couplers_to_axi_mem_intercon_ARREADY),
.M_AXI_arsize(s00_couplers_to_axi_mem_intercon_ARSIZE),
.M_AXI_arvalid(s00_couplers_to_axi_mem_intercon_ARVALID),
.M_AXI_awaddr(s00_couplers_to_axi_mem_intercon_AWADDR),
.M_AXI_awburst(s00_couplers_to_axi_mem_intercon_AWBURST),
.M_AXI_awcache(s00_couplers_to_axi_mem_intercon_AWCACHE),
.M_AXI_awid(s00_couplers_to_axi_mem_intercon_AWID),
.M_AXI_awlen(s00_couplers_to_axi_mem_intercon_AWLEN),
.M_AXI_awlock(s00_couplers_to_axi_mem_intercon_AWLOCK),
.M_AXI_awprot(s00_couplers_to_axi_mem_intercon_AWPROT),
.M_AXI_awready(s00_couplers_to_axi_mem_intercon_AWREADY),
.M_AXI_awsize(s00_couplers_to_axi_mem_intercon_AWSIZE),
.M_AXI_awvalid(s00_couplers_to_axi_mem_intercon_AWVALID),
.M_AXI_bid(s00_couplers_to_axi_mem_intercon_BID),
.M_AXI_bready(s00_couplers_to_axi_mem_intercon_BREADY),
.M_AXI_bresp(s00_couplers_to_axi_mem_intercon_BRESP),
.M_AXI_bvalid(s00_couplers_to_axi_mem_intercon_BVALID),
.M_AXI_rdata(s00_couplers_to_axi_mem_intercon_RDATA),
.M_AXI_rid(s00_couplers_to_axi_mem_intercon_RID),
.M_AXI_rlast(s00_couplers_to_axi_mem_intercon_RLAST),
.M_AXI_rready(s00_couplers_to_axi_mem_intercon_RREADY),
.M_AXI_rresp(s00_couplers_to_axi_mem_intercon_RRESP),
.M_AXI_rvalid(s00_couplers_to_axi_mem_intercon_RVALID),
.M_AXI_wdata(s00_couplers_to_axi_mem_intercon_WDATA),
.M_AXI_wlast(s00_couplers_to_axi_mem_intercon_WLAST),
.M_AXI_wready(s00_couplers_to_axi_mem_intercon_WREADY),
.M_AXI_wstrb(s00_couplers_to_axi_mem_intercon_WSTRB),
.M_AXI_wvalid(s00_couplers_to_axi_mem_intercon_WVALID),
.S_ACLK(S00_ACLK_1),
.S_ARESETN(S00_ARESETN_1),
.S_AXI_araddr(axi_mem_intercon_to_s00_couplers_ARADDR),
.S_AXI_arburst(axi_mem_intercon_to_s00_couplers_ARBURST),
.S_AXI_arcache(axi_mem_intercon_to_s00_couplers_ARCACHE),
.S_AXI_arid(axi_mem_intercon_to_s00_couplers_ARID),
.S_AXI_arlen(axi_mem_intercon_to_s00_couplers_ARLEN),
.S_AXI_arlock(axi_mem_intercon_to_s00_couplers_ARLOCK),
.S_AXI_arprot(axi_mem_intercon_to_s00_couplers_ARPROT),
.S_AXI_arqos(axi_mem_intercon_to_s00_couplers_ARQOS),
.S_AXI_arready(axi_mem_intercon_to_s00_couplers_ARREADY),
.S_AXI_arsize(axi_mem_intercon_to_s00_couplers_ARSIZE),
.S_AXI_arvalid(axi_mem_intercon_to_s00_couplers_ARVALID),
.S_AXI_awaddr(axi_mem_intercon_to_s00_couplers_AWADDR),
.S_AXI_awburst(axi_mem_intercon_to_s00_couplers_AWBURST),
.S_AXI_awcache(axi_mem_intercon_to_s00_couplers_AWCACHE),
.S_AXI_awid(axi_mem_intercon_to_s00_couplers_AWID),
.S_AXI_awlen(axi_mem_intercon_to_s00_couplers_AWLEN),
.S_AXI_awlock(axi_mem_intercon_to_s00_couplers_AWLOCK),
.S_AXI_awprot(axi_mem_intercon_to_s00_couplers_AWPROT),
.S_AXI_awqos(axi_mem_intercon_to_s00_couplers_AWQOS),
.S_AXI_awready(axi_mem_intercon_to_s00_couplers_AWREADY),
.S_AXI_awsize(axi_mem_intercon_to_s00_couplers_AWSIZE),
.S_AXI_awvalid(axi_mem_intercon_to_s00_couplers_AWVALID),
.S_AXI_bid(axi_mem_intercon_to_s00_couplers_BID),
.S_AXI_bready(axi_mem_intercon_to_s00_couplers_BREADY),
.S_AXI_bresp(axi_mem_intercon_to_s00_couplers_BRESP),
.S_AXI_bvalid(axi_mem_intercon_to_s00_couplers_BVALID),
.S_AXI_rdata(axi_mem_intercon_to_s00_couplers_RDATA),
.S_AXI_rid(axi_mem_intercon_to_s00_couplers_RID),
.S_AXI_rlast(axi_mem_intercon_to_s00_couplers_RLAST),
.S_AXI_rready(axi_mem_intercon_to_s00_couplers_RREADY),
.S_AXI_rresp(axi_mem_intercon_to_s00_couplers_RRESP),
.S_AXI_rvalid(axi_mem_intercon_to_s00_couplers_RVALID),
.S_AXI_wdata(axi_mem_intercon_to_s00_couplers_WDATA),
.S_AXI_wid(axi_mem_intercon_to_s00_couplers_WID),
.S_AXI_wlast(axi_mem_intercon_to_s00_couplers_WLAST),
.S_AXI_wready(axi_mem_intercon_to_s00_couplers_WREADY),
.S_AXI_wstrb(axi_mem_intercon_to_s00_couplers_WSTRB),
.S_AXI_wvalid(axi_mem_intercon_to_s00_couplers_WVALID));
endmodule
module design_1_axi_mem_intercon_1_0
(ACLK,
ARESETN,
M00_ACLK,
M00_ARESETN,
M00_AXI_araddr,
M00_AXI_arburst,
M00_AXI_arcache,
M00_AXI_arid,
M00_AXI_arlen,
M00_AXI_arlock,
M00_AXI_arprot,
M00_AXI_arready,
M00_AXI_arsize,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awburst,
M00_AXI_awcache,
M00_AXI_awid,
M00_AXI_awlen,
M00_AXI_awlock,
M00_AXI_awprot,
M00_AXI_awready,
M00_AXI_awsize,
M00_AXI_awvalid,
M00_AXI_bid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rid,
M00_AXI_rlast,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wlast,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
S00_ACLK,
S00_ARESETN,
S00_AXI_araddr,
S00_AXI_arburst,
S00_AXI_arcache,
S00_AXI_arid,
S00_AXI_arlen,
S00_AXI_arlock,
S00_AXI_arprot,
S00_AXI_arqos,
S00_AXI_arready,
S00_AXI_arsize,
S00_AXI_arvalid,
S00_AXI_awaddr,
S00_AXI_awburst,
S00_AXI_awcache,
S00_AXI_awid,
S00_AXI_awlen,
S00_AXI_awlock,
S00_AXI_awprot,
S00_AXI_awqos,
S00_AXI_awready,
S00_AXI_awsize,
S00_AXI_awvalid,
S00_AXI_bid,
S00_AXI_bready,
S00_AXI_bresp,
S00_AXI_bvalid,
S00_AXI_rdata,
S00_AXI_rid,
S00_AXI_rlast,
S00_AXI_rready,
S00_AXI_rresp,
S00_AXI_rvalid,
S00_AXI_wdata,
S00_AXI_wid,
S00_AXI_wlast,
S00_AXI_wready,
S00_AXI_wstrb,
S00_AXI_wvalid);
input ACLK;
input [0:0]ARESETN;
input M00_ACLK;
input [0:0]M00_ARESETN;
output [12:0]M00_AXI_araddr;
output [1:0]M00_AXI_arburst;
output [3:0]M00_AXI_arcache;
output [11:0]M00_AXI_arid;
output [7:0]M00_AXI_arlen;
output [0:0]M00_AXI_arlock;
output [2:0]M00_AXI_arprot;
input M00_AXI_arready;
output [2:0]M00_AXI_arsize;
output M00_AXI_arvalid;
output [12:0]M00_AXI_awaddr;
output [1:0]M00_AXI_awburst;
output [3:0]M00_AXI_awcache;
output [11:0]M00_AXI_awid;
output [7:0]M00_AXI_awlen;
output [0:0]M00_AXI_awlock;
output [2:0]M00_AXI_awprot;
input M00_AXI_awready;
output [2:0]M00_AXI_awsize;
output M00_AXI_awvalid;
input [11:0]M00_AXI_bid;
output M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input M00_AXI_bvalid;
input [31:0]M00_AXI_rdata;
input [11:0]M00_AXI_rid;
input M00_AXI_rlast;
output M00_AXI_rready;
input [1:0]M00_AXI_rresp;
input M00_AXI_rvalid;
output [31:0]M00_AXI_wdata;
output M00_AXI_wlast;
input M00_AXI_wready;
output [3:0]M00_AXI_wstrb;
output M00_AXI_wvalid;
input S00_ACLK;
input [0:0]S00_ARESETN;
input [31:0]S00_AXI_araddr;
input [1:0]S00_AXI_arburst;
input [3:0]S00_AXI_arcache;
input [11:0]S00_AXI_arid;
input [3:0]S00_AXI_arlen;
input [1:0]S00_AXI_arlock;
input [2:0]S00_AXI_arprot;
input [3:0]S00_AXI_arqos;
output S00_AXI_arready;
input [2:0]S00_AXI_arsize;
input S00_AXI_arvalid;
input [31:0]S00_AXI_awaddr;
input [1:0]S00_AXI_awburst;
input [3:0]S00_AXI_awcache;
input [11:0]S00_AXI_awid;
input [3:0]S00_AXI_awlen;
input [1:0]S00_AXI_awlock;
input [2:0]S00_AXI_awprot;
input [3:0]S00_AXI_awqos;
output S00_AXI_awready;
input [2:0]S00_AXI_awsize;
input S00_AXI_awvalid;
output [11:0]S00_AXI_bid;
input S00_AXI_bready;
output [1:0]S00_AXI_bresp;
output S00_AXI_bvalid;
output [31:0]S00_AXI_rdata;
output [11:0]S00_AXI_rid;
output S00_AXI_rlast;
input S00_AXI_rready;
output [1:0]S00_AXI_rresp;
output S00_AXI_rvalid;
input [31:0]S00_AXI_wdata;
input [11:0]S00_AXI_wid;
input S00_AXI_wlast;
output S00_AXI_wready;
input [3:0]S00_AXI_wstrb;
input S00_AXI_wvalid;
wire S00_ACLK_1;
wire [0:0]S00_ARESETN_1;
wire axi_mem_intercon_1_ACLK_net;
wire [0:0]axi_mem_intercon_1_ARESETN_net;
wire [31:0]axi_mem_intercon_1_to_s00_couplers_ARADDR;
wire [1:0]axi_mem_intercon_1_to_s00_couplers_ARBURST;
wire [3:0]axi_mem_intercon_1_to_s00_couplers_ARCACHE;
wire [11:0]axi_mem_intercon_1_to_s00_couplers_ARID;
wire [3:0]axi_mem_intercon_1_to_s00_couplers_ARLEN;
wire [1:0]axi_mem_intercon_1_to_s00_couplers_ARLOCK;
wire [2:0]axi_mem_intercon_1_to_s00_couplers_ARPROT;
wire [3:0]axi_mem_intercon_1_to_s00_couplers_ARQOS;
wire axi_mem_intercon_1_to_s00_couplers_ARREADY;
wire [2:0]axi_mem_intercon_1_to_s00_couplers_ARSIZE;
wire axi_mem_intercon_1_to_s00_couplers_ARVALID;
wire [31:0]axi_mem_intercon_1_to_s00_couplers_AWADDR;
wire [1:0]axi_mem_intercon_1_to_s00_couplers_AWBURST;
wire [3:0]axi_mem_intercon_1_to_s00_couplers_AWCACHE;
wire [11:0]axi_mem_intercon_1_to_s00_couplers_AWID;
wire [3:0]axi_mem_intercon_1_to_s00_couplers_AWLEN;
wire [1:0]axi_mem_intercon_1_to_s00_couplers_AWLOCK;
wire [2:0]axi_mem_intercon_1_to_s00_couplers_AWPROT;
wire [3:0]axi_mem_intercon_1_to_s00_couplers_AWQOS;
wire axi_mem_intercon_1_to_s00_couplers_AWREADY;
wire [2:0]axi_mem_intercon_1_to_s00_couplers_AWSIZE;
wire axi_mem_intercon_1_to_s00_couplers_AWVALID;
wire [11:0]axi_mem_intercon_1_to_s00_couplers_BID;
wire axi_mem_intercon_1_to_s00_couplers_BREADY;
wire [1:0]axi_mem_intercon_1_to_s00_couplers_BRESP;
wire axi_mem_intercon_1_to_s00_couplers_BVALID;
wire [31:0]axi_mem_intercon_1_to_s00_couplers_RDATA;
wire [11:0]axi_mem_intercon_1_to_s00_couplers_RID;
wire axi_mem_intercon_1_to_s00_couplers_RLAST;
wire axi_mem_intercon_1_to_s00_couplers_RREADY;
wire [1:0]axi_mem_intercon_1_to_s00_couplers_RRESP;
wire axi_mem_intercon_1_to_s00_couplers_RVALID;
wire [31:0]axi_mem_intercon_1_to_s00_couplers_WDATA;
wire [11:0]axi_mem_intercon_1_to_s00_couplers_WID;
wire axi_mem_intercon_1_to_s00_couplers_WLAST;
wire axi_mem_intercon_1_to_s00_couplers_WREADY;
wire [3:0]axi_mem_intercon_1_to_s00_couplers_WSTRB;
wire axi_mem_intercon_1_to_s00_couplers_WVALID;
wire [12:0]s00_couplers_to_axi_mem_intercon_1_ARADDR;
wire [1:0]s00_couplers_to_axi_mem_intercon_1_ARBURST;
wire [3:0]s00_couplers_to_axi_mem_intercon_1_ARCACHE;
wire [11:0]s00_couplers_to_axi_mem_intercon_1_ARID;
wire [7:0]s00_couplers_to_axi_mem_intercon_1_ARLEN;
wire [0:0]s00_couplers_to_axi_mem_intercon_1_ARLOCK;
wire [2:0]s00_couplers_to_axi_mem_intercon_1_ARPROT;
wire s00_couplers_to_axi_mem_intercon_1_ARREADY;
wire [2:0]s00_couplers_to_axi_mem_intercon_1_ARSIZE;
wire s00_couplers_to_axi_mem_intercon_1_ARVALID;
wire [12:0]s00_couplers_to_axi_mem_intercon_1_AWADDR;
wire [1:0]s00_couplers_to_axi_mem_intercon_1_AWBURST;
wire [3:0]s00_couplers_to_axi_mem_intercon_1_AWCACHE;
wire [11:0]s00_couplers_to_axi_mem_intercon_1_AWID;
wire [7:0]s00_couplers_to_axi_mem_intercon_1_AWLEN;
wire [0:0]s00_couplers_to_axi_mem_intercon_1_AWLOCK;
wire [2:0]s00_couplers_to_axi_mem_intercon_1_AWPROT;
wire s00_couplers_to_axi_mem_intercon_1_AWREADY;
wire [2:0]s00_couplers_to_axi_mem_intercon_1_AWSIZE;
wire s00_couplers_to_axi_mem_intercon_1_AWVALID;
wire [11:0]s00_couplers_to_axi_mem_intercon_1_BID;
wire s00_couplers_to_axi_mem_intercon_1_BREADY;
wire [1:0]s00_couplers_to_axi_mem_intercon_1_BRESP;
wire s00_couplers_to_axi_mem_intercon_1_BVALID;
wire [31:0]s00_couplers_to_axi_mem_intercon_1_RDATA;
wire [11:0]s00_couplers_to_axi_mem_intercon_1_RID;
wire s00_couplers_to_axi_mem_intercon_1_RLAST;
wire s00_couplers_to_axi_mem_intercon_1_RREADY;
wire [1:0]s00_couplers_to_axi_mem_intercon_1_RRESP;
wire s00_couplers_to_axi_mem_intercon_1_RVALID;
wire [31:0]s00_couplers_to_axi_mem_intercon_1_WDATA;
wire s00_couplers_to_axi_mem_intercon_1_WLAST;
wire s00_couplers_to_axi_mem_intercon_1_WREADY;
wire [3:0]s00_couplers_to_axi_mem_intercon_1_WSTRB;
wire s00_couplers_to_axi_mem_intercon_1_WVALID;
assign M00_AXI_araddr[12:0] = s00_couplers_to_axi_mem_intercon_1_ARADDR;
assign M00_AXI_arburst[1:0] = s00_couplers_to_axi_mem_intercon_1_ARBURST;
assign M00_AXI_arcache[3:0] = s00_couplers_to_axi_mem_intercon_1_ARCACHE;
assign M00_AXI_arid[11:0] = s00_couplers_to_axi_mem_intercon_1_ARID;
assign M00_AXI_arlen[7:0] = s00_couplers_to_axi_mem_intercon_1_ARLEN;
assign M00_AXI_arlock[0] = s00_couplers_to_axi_mem_intercon_1_ARLOCK;
assign M00_AXI_arprot[2:0] = s00_couplers_to_axi_mem_intercon_1_ARPROT;
assign M00_AXI_arsize[2:0] = s00_couplers_to_axi_mem_intercon_1_ARSIZE;
assign M00_AXI_arvalid = s00_couplers_to_axi_mem_intercon_1_ARVALID;
assign M00_AXI_awaddr[12:0] = s00_couplers_to_axi_mem_intercon_1_AWADDR;
assign M00_AXI_awburst[1:0] = s00_couplers_to_axi_mem_intercon_1_AWBURST;
assign M00_AXI_awcache[3:0] = s00_couplers_to_axi_mem_intercon_1_AWCACHE;
assign M00_AXI_awid[11:0] = s00_couplers_to_axi_mem_intercon_1_AWID;
assign M00_AXI_awlen[7:0] = s00_couplers_to_axi_mem_intercon_1_AWLEN;
assign M00_AXI_awlock[0] = s00_couplers_to_axi_mem_intercon_1_AWLOCK;
assign M00_AXI_awprot[2:0] = s00_couplers_to_axi_mem_intercon_1_AWPROT;
assign M00_AXI_awsize[2:0] = s00_couplers_to_axi_mem_intercon_1_AWSIZE;
assign M00_AXI_awvalid = s00_couplers_to_axi_mem_intercon_1_AWVALID;
assign M00_AXI_bready = s00_couplers_to_axi_mem_intercon_1_BREADY;
assign M00_AXI_rready = s00_couplers_to_axi_mem_intercon_1_RREADY;
assign M00_AXI_wdata[31:0] = s00_couplers_to_axi_mem_intercon_1_WDATA;
assign M00_AXI_wlast = s00_couplers_to_axi_mem_intercon_1_WLAST;
assign M00_AXI_wstrb[3:0] = s00_couplers_to_axi_mem_intercon_1_WSTRB;
assign M00_AXI_wvalid = s00_couplers_to_axi_mem_intercon_1_WVALID;
assign S00_ACLK_1 = S00_ACLK;
assign S00_ARESETN_1 = S00_ARESETN[0];
assign S00_AXI_arready = axi_mem_intercon_1_to_s00_couplers_ARREADY;
assign S00_AXI_awready = axi_mem_intercon_1_to_s00_couplers_AWREADY;
assign S00_AXI_bid[11:0] = axi_mem_intercon_1_to_s00_couplers_BID;
assign S00_AXI_bresp[1:0] = axi_mem_intercon_1_to_s00_couplers_BRESP;
assign S00_AXI_bvalid = axi_mem_intercon_1_to_s00_couplers_BVALID;
assign S00_AXI_rdata[31:0] = axi_mem_intercon_1_to_s00_couplers_RDATA;
assign S00_AXI_rid[11:0] = axi_mem_intercon_1_to_s00_couplers_RID;
assign S00_AXI_rlast = axi_mem_intercon_1_to_s00_couplers_RLAST;
assign S00_AXI_rresp[1:0] = axi_mem_intercon_1_to_s00_couplers_RRESP;
assign S00_AXI_rvalid = axi_mem_intercon_1_to_s00_couplers_RVALID;
assign S00_AXI_wready = axi_mem_intercon_1_to_s00_couplers_WREADY;
assign axi_mem_intercon_1_ACLK_net = M00_ACLK;
assign axi_mem_intercon_1_ARESETN_net = M00_ARESETN[0];
assign axi_mem_intercon_1_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
assign axi_mem_intercon_1_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
assign axi_mem_intercon_1_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
assign axi_mem_intercon_1_to_s00_couplers_ARID = S00_AXI_arid[11:0];
assign axi_mem_intercon_1_to_s00_couplers_ARLEN = S00_AXI_arlen[3:0];
assign axi_mem_intercon_1_to_s00_couplers_ARLOCK = S00_AXI_arlock[1:0];
assign axi_mem_intercon_1_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
assign axi_mem_intercon_1_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];
assign axi_mem_intercon_1_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
assign axi_mem_intercon_1_to_s00_couplers_ARVALID = S00_AXI_arvalid;
assign axi_mem_intercon_1_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
assign axi_mem_intercon_1_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];
assign axi_mem_intercon_1_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];
assign axi_mem_intercon_1_to_s00_couplers_AWID = S00_AXI_awid[11:0];
assign axi_mem_intercon_1_to_s00_couplers_AWLEN = S00_AXI_awlen[3:0];
assign axi_mem_intercon_1_to_s00_couplers_AWLOCK = S00_AXI_awlock[1:0];
assign axi_mem_intercon_1_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
assign axi_mem_intercon_1_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];
assign axi_mem_intercon_1_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];
assign axi_mem_intercon_1_to_s00_couplers_AWVALID = S00_AXI_awvalid;
assign axi_mem_intercon_1_to_s00_couplers_BREADY = S00_AXI_bready;
assign axi_mem_intercon_1_to_s00_couplers_RREADY = S00_AXI_rready;
assign axi_mem_intercon_1_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
assign axi_mem_intercon_1_to_s00_couplers_WID = S00_AXI_wid[11:0];
assign axi_mem_intercon_1_to_s00_couplers_WLAST = S00_AXI_wlast;
assign axi_mem_intercon_1_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
assign axi_mem_intercon_1_to_s00_couplers_WVALID = S00_AXI_wvalid;
assign s00_couplers_to_axi_mem_intercon_1_ARREADY = M00_AXI_arready;
assign s00_couplers_to_axi_mem_intercon_1_AWREADY = M00_AXI_awready;
assign s00_couplers_to_axi_mem_intercon_1_BID = M00_AXI_bid[11:0];
assign s00_couplers_to_axi_mem_intercon_1_BRESP = M00_AXI_bresp[1:0];
assign s00_couplers_to_axi_mem_intercon_1_BVALID = M00_AXI_bvalid;
assign s00_couplers_to_axi_mem_intercon_1_RDATA = M00_AXI_rdata[31:0];
assign s00_couplers_to_axi_mem_intercon_1_RID = M00_AXI_rid[11:0];
assign s00_couplers_to_axi_mem_intercon_1_RLAST = M00_AXI_rlast;
assign s00_couplers_to_axi_mem_intercon_1_RRESP = M00_AXI_rresp[1:0];
assign s00_couplers_to_axi_mem_intercon_1_RVALID = M00_AXI_rvalid;
assign s00_couplers_to_axi_mem_intercon_1_WREADY = M00_AXI_wready;
s00_couplers_imp_1FI55ZU s00_couplers
(.M_ACLK(axi_mem_intercon_1_ACLK_net),
.M_ARESETN(axi_mem_intercon_1_ARESETN_net),
.M_AXI_araddr(s00_couplers_to_axi_mem_intercon_1_ARADDR),
.M_AXI_arburst(s00_couplers_to_axi_mem_intercon_1_ARBURST),
.M_AXI_arcache(s00_couplers_to_axi_mem_intercon_1_ARCACHE),
.M_AXI_arid(s00_couplers_to_axi_mem_intercon_1_ARID),
.M_AXI_arlen(s00_couplers_to_axi_mem_intercon_1_ARLEN),
.M_AXI_arlock(s00_couplers_to_axi_mem_intercon_1_ARLOCK),
.M_AXI_arprot(s00_couplers_to_axi_mem_intercon_1_ARPROT),
.M_AXI_arready(s00_couplers_to_axi_mem_intercon_1_ARREADY),
.M_AXI_arsize(s00_couplers_to_axi_mem_intercon_1_ARSIZE),
.M_AXI_arvalid(s00_couplers_to_axi_mem_intercon_1_ARVALID),
.M_AXI_awaddr(s00_couplers_to_axi_mem_intercon_1_AWADDR),
.M_AXI_awburst(s00_couplers_to_axi_mem_intercon_1_AWBURST),
.M_AXI_awcache(s00_couplers_to_axi_mem_intercon_1_AWCACHE),
.M_AXI_awid(s00_couplers_to_axi_mem_intercon_1_AWID),
.M_AXI_awlen(s00_couplers_to_axi_mem_intercon_1_AWLEN),
.M_AXI_awlock(s00_couplers_to_axi_mem_intercon_1_AWLOCK),
.M_AXI_awprot(s00_couplers_to_axi_mem_intercon_1_AWPROT),
.M_AXI_awready(s00_couplers_to_axi_mem_intercon_1_AWREADY),
.M_AXI_awsize(s00_couplers_to_axi_mem_intercon_1_AWSIZE),
.M_AXI_awvalid(s00_couplers_to_axi_mem_intercon_1_AWVALID),
.M_AXI_bid(s00_couplers_to_axi_mem_intercon_1_BID),
.M_AXI_bready(s00_couplers_to_axi_mem_intercon_1_BREADY),
.M_AXI_bresp(s00_couplers_to_axi_mem_intercon_1_BRESP),
.M_AXI_bvalid(s00_couplers_to_axi_mem_intercon_1_BVALID),
.M_AXI_rdata(s00_couplers_to_axi_mem_intercon_1_RDATA),
.M_AXI_rid(s00_couplers_to_axi_mem_intercon_1_RID),
.M_AXI_rlast(s00_couplers_to_axi_mem_intercon_1_RLAST),
.M_AXI_rready(s00_couplers_to_axi_mem_intercon_1_RREADY),
.M_AXI_rresp(s00_couplers_to_axi_mem_intercon_1_RRESP),
.M_AXI_rvalid(s00_couplers_to_axi_mem_intercon_1_RVALID),
.M_AXI_wdata(s00_couplers_to_axi_mem_intercon_1_WDATA),
.M_AXI_wlast(s00_couplers_to_axi_mem_intercon_1_WLAST),
.M_AXI_wready(s00_couplers_to_axi_mem_intercon_1_WREADY),
.M_AXI_wstrb(s00_couplers_to_axi_mem_intercon_1_WSTRB),
.M_AXI_wvalid(s00_couplers_to_axi_mem_intercon_1_WVALID),
.S_ACLK(S00_ACLK_1),
.S_ARESETN(S00_ARESETN_1),
.S_AXI_araddr(axi_mem_intercon_1_to_s00_couplers_ARADDR),
.S_AXI_arburst(axi_mem_intercon_1_to_s00_couplers_ARBURST),
.S_AXI_arcache(axi_mem_intercon_1_to_s00_couplers_ARCACHE),
.S_AXI_arid(axi_mem_intercon_1_to_s00_couplers_ARID),
.S_AXI_arlen(axi_mem_intercon_1_to_s00_couplers_ARLEN),
.S_AXI_arlock(axi_mem_intercon_1_to_s00_couplers_ARLOCK),
.S_AXI_arprot(axi_mem_intercon_1_to_s00_couplers_ARPROT),
.S_AXI_arqos(axi_mem_intercon_1_to_s00_couplers_ARQOS),
.S_AXI_arready(axi_mem_intercon_1_to_s00_couplers_ARREADY),
.S_AXI_arsize(axi_mem_intercon_1_to_s00_couplers_ARSIZE),
.S_AXI_arvalid(axi_mem_intercon_1_to_s00_couplers_ARVALID),
.S_AXI_awaddr(axi_mem_intercon_1_to_s00_couplers_AWADDR),
.S_AXI_awburst(axi_mem_intercon_1_to_s00_couplers_AWBURST),
.S_AXI_awcache(axi_mem_intercon_1_to_s00_couplers_AWCACHE),
.S_AXI_awid(axi_mem_intercon_1_to_s00_couplers_AWID),
.S_AXI_awlen(axi_mem_intercon_1_to_s00_couplers_AWLEN),
.S_AXI_awlock(axi_mem_intercon_1_to_s00_couplers_AWLOCK),
.S_AXI_awprot(axi_mem_intercon_1_to_s00_couplers_AWPROT),
.S_AXI_awqos(axi_mem_intercon_1_to_s00_couplers_AWQOS),
.S_AXI_awready(axi_mem_intercon_1_to_s00_couplers_AWREADY),
.S_AXI_awsize(axi_mem_intercon_1_to_s00_couplers_AWSIZE),
.S_AXI_awvalid(axi_mem_intercon_1_to_s00_couplers_AWVALID),
.S_AXI_bid(axi_mem_intercon_1_to_s00_couplers_BID),
.S_AXI_bready(axi_mem_intercon_1_to_s00_couplers_BREADY),
.S_AXI_bresp(axi_mem_intercon_1_to_s00_couplers_BRESP),
.S_AXI_bvalid(axi_mem_intercon_1_to_s00_couplers_BVALID),
.S_AXI_rdata(axi_mem_intercon_1_to_s00_couplers_RDATA),
.S_AXI_rid(axi_mem_intercon_1_to_s00_couplers_RID),
.S_AXI_rlast(axi_mem_intercon_1_to_s00_couplers_RLAST),
.S_AXI_rready(axi_mem_intercon_1_to_s00_couplers_RREADY),
.S_AXI_rresp(axi_mem_intercon_1_to_s00_couplers_RRESP),
.S_AXI_rvalid(axi_mem_intercon_1_to_s00_couplers_RVALID),
.S_AXI_wdata(axi_mem_intercon_1_to_s00_couplers_WDATA),
.S_AXI_wid(axi_mem_intercon_1_to_s00_couplers_WID),
.S_AXI_wlast(axi_mem_intercon_1_to_s00_couplers_WLAST),
.S_AXI_wready(axi_mem_intercon_1_to_s00_couplers_WREADY),
.S_AXI_wstrb(axi_mem_intercon_1_to_s00_couplers_WSTRB),
.S_AXI_wvalid(axi_mem_intercon_1_to_s00_couplers_WVALID));
endmodule
module s00_couplers_imp_1FI55ZU
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arburst,
M_AXI_arcache,
M_AXI_arid,
M_AXI_arlen,
M_AXI_arlock,
M_AXI_arprot,
M_AXI_arready,
M_AXI_arsize,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awburst,
M_AXI_awcache,
M_AXI_awid,
M_AXI_awlen,
M_AXI_awlock,
M_AXI_awprot,
M_AXI_awready,
M_AXI_awsize,
M_AXI_awvalid,
M_AXI_bid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rid,
M_AXI_rlast,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wlast,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arid,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awid,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rid,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wid,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [12:0]M_AXI_araddr;
output [1:0]M_AXI_arburst;
output [3:0]M_AXI_arcache;
output [11:0]M_AXI_arid;
output [7:0]M_AXI_arlen;
output [0:0]M_AXI_arlock;
output [2:0]M_AXI_arprot;
input M_AXI_arready;
output [2:0]M_AXI_arsize;
output M_AXI_arvalid;
output [12:0]M_AXI_awaddr;
output [1:0]M_AXI_awburst;
output [3:0]M_AXI_awcache;
output [11:0]M_AXI_awid;
output [7:0]M_AXI_awlen;
output [0:0]M_AXI_awlock;
output [2:0]M_AXI_awprot;
input M_AXI_awready;
output [2:0]M_AXI_awsize;
output M_AXI_awvalid;
input [11:0]M_AXI_bid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
input [11:0]M_AXI_rid;
input M_AXI_rlast;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
output M_AXI_wlast;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [11:0]S_AXI_arid;
input [3:0]S_AXI_arlen;
input [1:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [11:0]S_AXI_awid;
input [3:0]S_AXI_awlen;
input [1:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
output [11:0]S_AXI_bid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output [11:0]S_AXI_rid;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input [11:0]S_AXI_wid;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire [0:0]S_ARESETN_1;
wire [31:0]auto_pc_to_s00_couplers_ARADDR;
wire [1:0]auto_pc_to_s00_couplers_ARBURST;
wire [3:0]auto_pc_to_s00_couplers_ARCACHE;
wire [11:0]auto_pc_to_s00_couplers_ARID;
wire [7:0]auto_pc_to_s00_couplers_ARLEN;
wire [0:0]auto_pc_to_s00_couplers_ARLOCK;
wire [2:0]auto_pc_to_s00_couplers_ARPROT;
wire auto_pc_to_s00_couplers_ARREADY;
wire [2:0]auto_pc_to_s00_couplers_ARSIZE;
wire auto_pc_to_s00_couplers_ARVALID;
wire [31:0]auto_pc_to_s00_couplers_AWADDR;
wire [1:0]auto_pc_to_s00_couplers_AWBURST;
wire [3:0]auto_pc_to_s00_couplers_AWCACHE;
wire [11:0]auto_pc_to_s00_couplers_AWID;
wire [7:0]auto_pc_to_s00_couplers_AWLEN;
wire [0:0]auto_pc_to_s00_couplers_AWLOCK;
wire [2:0]auto_pc_to_s00_couplers_AWPROT;
wire auto_pc_to_s00_couplers_AWREADY;
wire [2:0]auto_pc_to_s00_couplers_AWSIZE;
wire auto_pc_to_s00_couplers_AWVALID;
wire [11:0]auto_pc_to_s00_couplers_BID;
wire auto_pc_to_s00_couplers_BREADY;
wire [1:0]auto_pc_to_s00_couplers_BRESP;
wire auto_pc_to_s00_couplers_BVALID;
wire [31:0]auto_pc_to_s00_couplers_RDATA;
wire [11:0]auto_pc_to_s00_couplers_RID;
wire auto_pc_to_s00_couplers_RLAST;
wire auto_pc_to_s00_couplers_RREADY;
wire [1:0]auto_pc_to_s00_couplers_RRESP;
wire auto_pc_to_s00_couplers_RVALID;
wire [31:0]auto_pc_to_s00_couplers_WDATA;
wire auto_pc_to_s00_couplers_WLAST;
wire auto_pc_to_s00_couplers_WREADY;
wire [3:0]auto_pc_to_s00_couplers_WSTRB;
wire auto_pc_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_auto_pc_ARADDR;
wire [1:0]s00_couplers_to_auto_pc_ARBURST;
wire [3:0]s00_couplers_to_auto_pc_ARCACHE;
wire [11:0]s00_couplers_to_auto_pc_ARID;
wire [3:0]s00_couplers_to_auto_pc_ARLEN;
wire [1:0]s00_couplers_to_auto_pc_ARLOCK;
wire [2:0]s00_couplers_to_auto_pc_ARPROT;
wire [3:0]s00_couplers_to_auto_pc_ARQOS;
wire s00_couplers_to_auto_pc_ARREADY;
wire [2:0]s00_couplers_to_auto_pc_ARSIZE;
wire s00_couplers_to_auto_pc_ARVALID;
wire [31:0]s00_couplers_to_auto_pc_AWADDR;
wire [1:0]s00_couplers_to_auto_pc_AWBURST;
wire [3:0]s00_couplers_to_auto_pc_AWCACHE;
wire [11:0]s00_couplers_to_auto_pc_AWID;
wire [3:0]s00_couplers_to_auto_pc_AWLEN;
wire [1:0]s00_couplers_to_auto_pc_AWLOCK;
wire [2:0]s00_couplers_to_auto_pc_AWPROT;
wire [3:0]s00_couplers_to_auto_pc_AWQOS;
wire s00_couplers_to_auto_pc_AWREADY;
wire [2:0]s00_couplers_to_auto_pc_AWSIZE;
wire s00_couplers_to_auto_pc_AWVALID;
wire [11:0]s00_couplers_to_auto_pc_BID;
wire s00_couplers_to_auto_pc_BREADY;
wire [1:0]s00_couplers_to_auto_pc_BRESP;
wire s00_couplers_to_auto_pc_BVALID;
wire [31:0]s00_couplers_to_auto_pc_RDATA;
wire [11:0]s00_couplers_to_auto_pc_RID;
wire s00_couplers_to_auto_pc_RLAST;
wire s00_couplers_to_auto_pc_RREADY;
wire [1:0]s00_couplers_to_auto_pc_RRESP;
wire s00_couplers_to_auto_pc_RVALID;
wire [31:0]s00_couplers_to_auto_pc_WDATA;
wire [11:0]s00_couplers_to_auto_pc_WID;
wire s00_couplers_to_auto_pc_WLAST;
wire s00_couplers_to_auto_pc_WREADY;
wire [3:0]s00_couplers_to_auto_pc_WSTRB;
wire s00_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[12:0] = auto_pc_to_s00_couplers_ARADDR[12:0];
assign M_AXI_arburst[1:0] = auto_pc_to_s00_couplers_ARBURST;
assign M_AXI_arcache[3:0] = auto_pc_to_s00_couplers_ARCACHE;
assign M_AXI_arid[11:0] = auto_pc_to_s00_couplers_ARID;
assign M_AXI_arlen[7:0] = auto_pc_to_s00_couplers_ARLEN;
assign M_AXI_arlock[0] = auto_pc_to_s00_couplers_ARLOCK;
assign M_AXI_arprot[2:0] = auto_pc_to_s00_couplers_ARPROT;
assign M_AXI_arsize[2:0] = auto_pc_to_s00_couplers_ARSIZE;
assign M_AXI_arvalid = auto_pc_to_s00_couplers_ARVALID;
assign M_AXI_awaddr[12:0] = auto_pc_to_s00_couplers_AWADDR[12:0];
assign M_AXI_awburst[1:0] = auto_pc_to_s00_couplers_AWBURST;
assign M_AXI_awcache[3:0] = auto_pc_to_s00_couplers_AWCACHE;
assign M_AXI_awid[11:0] = auto_pc_to_s00_couplers_AWID;
assign M_AXI_awlen[7:0] = auto_pc_to_s00_couplers_AWLEN;
assign M_AXI_awlock[0] = auto_pc_to_s00_couplers_AWLOCK;
assign M_AXI_awprot[2:0] = auto_pc_to_s00_couplers_AWPROT;
assign M_AXI_awsize[2:0] = auto_pc_to_s00_couplers_AWSIZE;
assign M_AXI_awvalid = auto_pc_to_s00_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_s00_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_s00_couplers_RREADY;
assign M_AXI_wdata[31:0] = auto_pc_to_s00_couplers_WDATA;
assign M_AXI_wlast = auto_pc_to_s00_couplers_WLAST;
assign M_AXI_wstrb[3:0] = auto_pc_to_s00_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_s00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN[0];
assign S_AXI_arready = s00_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = s00_couplers_to_auto_pc_AWREADY;
assign S_AXI_bid[11:0] = s00_couplers_to_auto_pc_BID;
assign S_AXI_bresp[1:0] = s00_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = s00_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[31:0] = s00_couplers_to_auto_pc_RDATA;
assign S_AXI_rid[11:0] = s00_couplers_to_auto_pc_RID;
assign S_AXI_rlast = s00_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = s00_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = s00_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = s00_couplers_to_auto_pc_WREADY;
assign auto_pc_to_s00_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_s00_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_s00_couplers_BID = M_AXI_bid[11:0];
assign auto_pc_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_s00_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_s00_couplers_RDATA = M_AXI_rdata[31:0];
assign auto_pc_to_s00_couplers_RID = M_AXI_rid[11:0];
assign auto_pc_to_s00_couplers_RLAST = M_AXI_rlast;
assign auto_pc_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_s00_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_s00_couplers_WREADY = M_AXI_wready;
assign s00_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign s00_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign s00_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign s00_couplers_to_auto_pc_ARID = S_AXI_arid[11:0];
assign s00_couplers_to_auto_pc_ARLEN = S_AXI_arlen[3:0];
assign s00_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[1:0];
assign s00_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign s00_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign s00_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign s00_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign s00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign s00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign s00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign s00_couplers_to_auto_pc_AWID = S_AXI_awid[11:0];
assign s00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[3:0];
assign s00_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[1:0];
assign s00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign s00_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign s00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign s00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign s00_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign s00_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign s00_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
assign s00_couplers_to_auto_pc_WID = S_AXI_wid[11:0];
assign s00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign s00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
assign s00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
design_1_auto_pc_1 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_s00_couplers_ARADDR),
.m_axi_arburst(auto_pc_to_s00_couplers_ARBURST),
.m_axi_arcache(auto_pc_to_s00_couplers_ARCACHE),
.m_axi_arid(auto_pc_to_s00_couplers_ARID),
.m_axi_arlen(auto_pc_to_s00_couplers_ARLEN),
.m_axi_arlock(auto_pc_to_s00_couplers_ARLOCK),
.m_axi_arprot(auto_pc_to_s00_couplers_ARPROT),
.m_axi_arready(auto_pc_to_s00_couplers_ARREADY),
.m_axi_arsize(auto_pc_to_s00_couplers_ARSIZE),
.m_axi_arvalid(auto_pc_to_s00_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_s00_couplers_AWADDR),
.m_axi_awburst(auto_pc_to_s00_couplers_AWBURST),
.m_axi_awcache(auto_pc_to_s00_couplers_AWCACHE),
.m_axi_awid(auto_pc_to_s00_couplers_AWID),
.m_axi_awlen(auto_pc_to_s00_couplers_AWLEN),
.m_axi_awlock(auto_pc_to_s00_couplers_AWLOCK),
.m_axi_awprot(auto_pc_to_s00_couplers_AWPROT),
.m_axi_awready(auto_pc_to_s00_couplers_AWREADY),
.m_axi_awsize(auto_pc_to_s00_couplers_AWSIZE),
.m_axi_awvalid(auto_pc_to_s00_couplers_AWVALID),
.m_axi_bid(auto_pc_to_s00_couplers_BID),
.m_axi_bready(auto_pc_to_s00_couplers_BREADY),
.m_axi_bresp(auto_pc_to_s00_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_s00_couplers_BVALID),
.m_axi_rdata(auto_pc_to_s00_couplers_RDATA),
.m_axi_rid(auto_pc_to_s00_couplers_RID),
.m_axi_rlast(auto_pc_to_s00_couplers_RLAST),
.m_axi_rready(auto_pc_to_s00_couplers_RREADY),
.m_axi_rresp(auto_pc_to_s00_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_s00_couplers_RVALID),
.m_axi_wdata(auto_pc_to_s00_couplers_WDATA),
.m_axi_wlast(auto_pc_to_s00_couplers_WLAST),
.m_axi_wready(auto_pc_to_s00_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_s00_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_s00_couplers_WVALID),
.s_axi_araddr(s00_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(s00_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(s00_couplers_to_auto_pc_ARCACHE),
.s_axi_arid(s00_couplers_to_auto_pc_ARID),
.s_axi_arlen(s00_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(s00_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(s00_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(s00_couplers_to_auto_pc_ARQOS),
.s_axi_arready(s00_couplers_to_auto_pc_ARREADY),
.s_axi_arsize(s00_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(s00_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(s00_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(s00_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(s00_couplers_to_auto_pc_AWCACHE),
.s_axi_awid(s00_couplers_to_auto_pc_AWID),
.s_axi_awlen(s00_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(s00_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(s00_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(s00_couplers_to_auto_pc_AWQOS),
.s_axi_awready(s00_couplers_to_auto_pc_AWREADY),
.s_axi_awsize(s00_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(s00_couplers_to_auto_pc_AWVALID),
.s_axi_bid(s00_couplers_to_auto_pc_BID),
.s_axi_bready(s00_couplers_to_auto_pc_BREADY),
.s_axi_bresp(s00_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(s00_couplers_to_auto_pc_BVALID),
.s_axi_rdata(s00_couplers_to_auto_pc_RDATA),
.s_axi_rid(s00_couplers_to_auto_pc_RID),
.s_axi_rlast(s00_couplers_to_auto_pc_RLAST),
.s_axi_rready(s00_couplers_to_auto_pc_RREADY),
.s_axi_rresp(s00_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(s00_couplers_to_auto_pc_RVALID),
.s_axi_wdata(s00_couplers_to_auto_pc_WDATA),
.s_axi_wid(s00_couplers_to_auto_pc_WID),
.s_axi_wlast(s00_couplers_to_auto_pc_WLAST),
.s_axi_wready(s00_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(s00_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(s00_couplers_to_auto_pc_WVALID));
endmodule
module s00_couplers_imp_7HNO1D
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arburst,
M_AXI_arcache,
M_AXI_arid,
M_AXI_arlen,
M_AXI_arlock,
M_AXI_arprot,
M_AXI_arready,
M_AXI_arsize,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awburst,
M_AXI_awcache,
M_AXI_awid,
M_AXI_awlen,
M_AXI_awlock,
M_AXI_awprot,
M_AXI_awready,
M_AXI_awsize,
M_AXI_awvalid,
M_AXI_bid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rid,
M_AXI_rlast,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wlast,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arid,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awid,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rid,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wid,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [12:0]M_AXI_araddr;
output [1:0]M_AXI_arburst;
output [3:0]M_AXI_arcache;
output [11:0]M_AXI_arid;
output [7:0]M_AXI_arlen;
output [0:0]M_AXI_arlock;
output [2:0]M_AXI_arprot;
input M_AXI_arready;
output [2:0]M_AXI_arsize;
output M_AXI_arvalid;
output [12:0]M_AXI_awaddr;
output [1:0]M_AXI_awburst;
output [3:0]M_AXI_awcache;
output [11:0]M_AXI_awid;
output [7:0]M_AXI_awlen;
output [0:0]M_AXI_awlock;
output [2:0]M_AXI_awprot;
input M_AXI_awready;
output [2:0]M_AXI_awsize;
output M_AXI_awvalid;
input [11:0]M_AXI_bid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
input [11:0]M_AXI_rid;
input M_AXI_rlast;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
output M_AXI_wlast;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [11:0]S_AXI_arid;
input [3:0]S_AXI_arlen;
input [1:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [11:0]S_AXI_awid;
input [3:0]S_AXI_awlen;
input [1:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
output [11:0]S_AXI_bid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output [11:0]S_AXI_rid;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input [11:0]S_AXI_wid;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire [0:0]S_ARESETN_1;
wire [31:0]auto_pc_to_s00_couplers_ARADDR;
wire [1:0]auto_pc_to_s00_couplers_ARBURST;
wire [3:0]auto_pc_to_s00_couplers_ARCACHE;
wire [11:0]auto_pc_to_s00_couplers_ARID;
wire [7:0]auto_pc_to_s00_couplers_ARLEN;
wire [0:0]auto_pc_to_s00_couplers_ARLOCK;
wire [2:0]auto_pc_to_s00_couplers_ARPROT;
wire auto_pc_to_s00_couplers_ARREADY;
wire [2:0]auto_pc_to_s00_couplers_ARSIZE;
wire auto_pc_to_s00_couplers_ARVALID;
wire [31:0]auto_pc_to_s00_couplers_AWADDR;
wire [1:0]auto_pc_to_s00_couplers_AWBURST;
wire [3:0]auto_pc_to_s00_couplers_AWCACHE;
wire [11:0]auto_pc_to_s00_couplers_AWID;
wire [7:0]auto_pc_to_s00_couplers_AWLEN;
wire [0:0]auto_pc_to_s00_couplers_AWLOCK;
wire [2:0]auto_pc_to_s00_couplers_AWPROT;
wire auto_pc_to_s00_couplers_AWREADY;
wire [2:0]auto_pc_to_s00_couplers_AWSIZE;
wire auto_pc_to_s00_couplers_AWVALID;
wire [11:0]auto_pc_to_s00_couplers_BID;
wire auto_pc_to_s00_couplers_BREADY;
wire [1:0]auto_pc_to_s00_couplers_BRESP;
wire auto_pc_to_s00_couplers_BVALID;
wire [31:0]auto_pc_to_s00_couplers_RDATA;
wire [11:0]auto_pc_to_s00_couplers_RID;
wire auto_pc_to_s00_couplers_RLAST;
wire auto_pc_to_s00_couplers_RREADY;
wire [1:0]auto_pc_to_s00_couplers_RRESP;
wire auto_pc_to_s00_couplers_RVALID;
wire [31:0]auto_pc_to_s00_couplers_WDATA;
wire auto_pc_to_s00_couplers_WLAST;
wire auto_pc_to_s00_couplers_WREADY;
wire [3:0]auto_pc_to_s00_couplers_WSTRB;
wire auto_pc_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_auto_pc_ARADDR;
wire [1:0]s00_couplers_to_auto_pc_ARBURST;
wire [3:0]s00_couplers_to_auto_pc_ARCACHE;
wire [11:0]s00_couplers_to_auto_pc_ARID;
wire [3:0]s00_couplers_to_auto_pc_ARLEN;
wire [1:0]s00_couplers_to_auto_pc_ARLOCK;
wire [2:0]s00_couplers_to_auto_pc_ARPROT;
wire [3:0]s00_couplers_to_auto_pc_ARQOS;
wire s00_couplers_to_auto_pc_ARREADY;
wire [2:0]s00_couplers_to_auto_pc_ARSIZE;
wire s00_couplers_to_auto_pc_ARVALID;
wire [31:0]s00_couplers_to_auto_pc_AWADDR;
wire [1:0]s00_couplers_to_auto_pc_AWBURST;
wire [3:0]s00_couplers_to_auto_pc_AWCACHE;
wire [11:0]s00_couplers_to_auto_pc_AWID;
wire [3:0]s00_couplers_to_auto_pc_AWLEN;
wire [1:0]s00_couplers_to_auto_pc_AWLOCK;
wire [2:0]s00_couplers_to_auto_pc_AWPROT;
wire [3:0]s00_couplers_to_auto_pc_AWQOS;
wire s00_couplers_to_auto_pc_AWREADY;
wire [2:0]s00_couplers_to_auto_pc_AWSIZE;
wire s00_couplers_to_auto_pc_AWVALID;
wire [11:0]s00_couplers_to_auto_pc_BID;
wire s00_couplers_to_auto_pc_BREADY;
wire [1:0]s00_couplers_to_auto_pc_BRESP;
wire s00_couplers_to_auto_pc_BVALID;
wire [31:0]s00_couplers_to_auto_pc_RDATA;
wire [11:0]s00_couplers_to_auto_pc_RID;
wire s00_couplers_to_auto_pc_RLAST;
wire s00_couplers_to_auto_pc_RREADY;
wire [1:0]s00_couplers_to_auto_pc_RRESP;
wire s00_couplers_to_auto_pc_RVALID;
wire [31:0]s00_couplers_to_auto_pc_WDATA;
wire [11:0]s00_couplers_to_auto_pc_WID;
wire s00_couplers_to_auto_pc_WLAST;
wire s00_couplers_to_auto_pc_WREADY;
wire [3:0]s00_couplers_to_auto_pc_WSTRB;
wire s00_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[12:0] = auto_pc_to_s00_couplers_ARADDR[12:0];
assign M_AXI_arburst[1:0] = auto_pc_to_s00_couplers_ARBURST;
assign M_AXI_arcache[3:0] = auto_pc_to_s00_couplers_ARCACHE;
assign M_AXI_arid[11:0] = auto_pc_to_s00_couplers_ARID;
assign M_AXI_arlen[7:0] = auto_pc_to_s00_couplers_ARLEN;
assign M_AXI_arlock[0] = auto_pc_to_s00_couplers_ARLOCK;
assign M_AXI_arprot[2:0] = auto_pc_to_s00_couplers_ARPROT;
assign M_AXI_arsize[2:0] = auto_pc_to_s00_couplers_ARSIZE;
assign M_AXI_arvalid = auto_pc_to_s00_couplers_ARVALID;
assign M_AXI_awaddr[12:0] = auto_pc_to_s00_couplers_AWADDR[12:0];
assign M_AXI_awburst[1:0] = auto_pc_to_s00_couplers_AWBURST;
assign M_AXI_awcache[3:0] = auto_pc_to_s00_couplers_AWCACHE;
assign M_AXI_awid[11:0] = auto_pc_to_s00_couplers_AWID;
assign M_AXI_awlen[7:0] = auto_pc_to_s00_couplers_AWLEN;
assign M_AXI_awlock[0] = auto_pc_to_s00_couplers_AWLOCK;
assign M_AXI_awprot[2:0] = auto_pc_to_s00_couplers_AWPROT;
assign M_AXI_awsize[2:0] = auto_pc_to_s00_couplers_AWSIZE;
assign M_AXI_awvalid = auto_pc_to_s00_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_s00_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_s00_couplers_RREADY;
assign M_AXI_wdata[31:0] = auto_pc_to_s00_couplers_WDATA;
assign M_AXI_wlast = auto_pc_to_s00_couplers_WLAST;
assign M_AXI_wstrb[3:0] = auto_pc_to_s00_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_s00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN[0];
assign S_AXI_arready = s00_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = s00_couplers_to_auto_pc_AWREADY;
assign S_AXI_bid[11:0] = s00_couplers_to_auto_pc_BID;
assign S_AXI_bresp[1:0] = s00_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = s00_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[31:0] = s00_couplers_to_auto_pc_RDATA;
assign S_AXI_rid[11:0] = s00_couplers_to_auto_pc_RID;
assign S_AXI_rlast = s00_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = s00_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = s00_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = s00_couplers_to_auto_pc_WREADY;
assign auto_pc_to_s00_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_s00_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_s00_couplers_BID = M_AXI_bid[11:0];
assign auto_pc_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_s00_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_s00_couplers_RDATA = M_AXI_rdata[31:0];
assign auto_pc_to_s00_couplers_RID = M_AXI_rid[11:0];
assign auto_pc_to_s00_couplers_RLAST = M_AXI_rlast;
assign auto_pc_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_s00_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_s00_couplers_WREADY = M_AXI_wready;
assign s00_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign s00_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign s00_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign s00_couplers_to_auto_pc_ARID = S_AXI_arid[11:0];
assign s00_couplers_to_auto_pc_ARLEN = S_AXI_arlen[3:0];
assign s00_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[1:0];
assign s00_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign s00_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign s00_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign s00_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign s00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign s00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign s00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign s00_couplers_to_auto_pc_AWID = S_AXI_awid[11:0];
assign s00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[3:0];
assign s00_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[1:0];
assign s00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign s00_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign s00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign s00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign s00_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign s00_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign s00_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
assign s00_couplers_to_auto_pc_WID = S_AXI_wid[11:0];
assign s00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign s00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
assign s00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
design_1_auto_pc_0 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_s00_couplers_ARADDR),
.m_axi_arburst(auto_pc_to_s00_couplers_ARBURST),
.m_axi_arcache(auto_pc_to_s00_couplers_ARCACHE),
.m_axi_arid(auto_pc_to_s00_couplers_ARID),
.m_axi_arlen(auto_pc_to_s00_couplers_ARLEN),
.m_axi_arlock(auto_pc_to_s00_couplers_ARLOCK),
.m_axi_arprot(auto_pc_to_s00_couplers_ARPROT),
.m_axi_arready(auto_pc_to_s00_couplers_ARREADY),
.m_axi_arsize(auto_pc_to_s00_couplers_ARSIZE),
.m_axi_arvalid(auto_pc_to_s00_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_s00_couplers_AWADDR),
.m_axi_awburst(auto_pc_to_s00_couplers_AWBURST),
.m_axi_awcache(auto_pc_to_s00_couplers_AWCACHE),
.m_axi_awid(auto_pc_to_s00_couplers_AWID),
.m_axi_awlen(auto_pc_to_s00_couplers_AWLEN),
.m_axi_awlock(auto_pc_to_s00_couplers_AWLOCK),
.m_axi_awprot(auto_pc_to_s00_couplers_AWPROT),
.m_axi_awready(auto_pc_to_s00_couplers_AWREADY),
.m_axi_awsize(auto_pc_to_s00_couplers_AWSIZE),
.m_axi_awvalid(auto_pc_to_s00_couplers_AWVALID),
.m_axi_bid(auto_pc_to_s00_couplers_BID),
.m_axi_bready(auto_pc_to_s00_couplers_BREADY),
.m_axi_bresp(auto_pc_to_s00_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_s00_couplers_BVALID),
.m_axi_rdata(auto_pc_to_s00_couplers_RDATA),
.m_axi_rid(auto_pc_to_s00_couplers_RID),
.m_axi_rlast(auto_pc_to_s00_couplers_RLAST),
.m_axi_rready(auto_pc_to_s00_couplers_RREADY),
.m_axi_rresp(auto_pc_to_s00_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_s00_couplers_RVALID),
.m_axi_wdata(auto_pc_to_s00_couplers_WDATA),
.m_axi_wlast(auto_pc_to_s00_couplers_WLAST),
.m_axi_wready(auto_pc_to_s00_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_s00_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_s00_couplers_WVALID),
.s_axi_araddr(s00_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(s00_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(s00_couplers_to_auto_pc_ARCACHE),
.s_axi_arid(s00_couplers_to_auto_pc_ARID),
.s_axi_arlen(s00_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(s00_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(s00_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(s00_couplers_to_auto_pc_ARQOS),
.s_axi_arready(s00_couplers_to_auto_pc_ARREADY),
.s_axi_arsize(s00_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(s00_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(s00_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(s00_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(s00_couplers_to_auto_pc_AWCACHE),
.s_axi_awid(s00_couplers_to_auto_pc_AWID),
.s_axi_awlen(s00_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(s00_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(s00_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(s00_couplers_to_auto_pc_AWQOS),
.s_axi_awready(s00_couplers_to_auto_pc_AWREADY),
.s_axi_awsize(s00_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(s00_couplers_to_auto_pc_AWVALID),
.s_axi_bid(s00_couplers_to_auto_pc_BID),
.s_axi_bready(s00_couplers_to_auto_pc_BREADY),
.s_axi_bresp(s00_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(s00_couplers_to_auto_pc_BVALID),
.s_axi_rdata(s00_couplers_to_auto_pc_RDATA),
.s_axi_rid(s00_couplers_to_auto_pc_RID),
.s_axi_rlast(s00_couplers_to_auto_pc_RLAST),
.s_axi_rready(s00_couplers_to_auto_pc_RREADY),
.s_axi_rresp(s00_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(s00_couplers_to_auto_pc_RVALID),
.s_axi_wdata(s00_couplers_to_auto_pc_WDATA),
.s_axi_wid(s00_couplers_to_auto_pc_WID),
.s_axi_wlast(s00_couplers_to_auto_pc_WLAST),
.s_axi_wready(s00_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(s00_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(s00_couplers_to_auto_pc_WVALID));
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_miim.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2005/02/21 12:48:07 igorm
// Warning fixes.
//
// Revision 1.5 2003/05/16 10:08:27 mohor
// Busy was set 2 cycles too late. Reported by Dennis Scott.
//
// Revision 1.4 2002/08/14 18:32:10 mohor
// - Busy signal was not set on time when scan status operation was performed
// and clock was divided with more than 2.
// - Nvalid remains valid two more clocks (was previously cleared too soon).
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.2 2001/08/02 09:25:31 mohor
// Unconnected signals are now connected.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/01 22:28:56 mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
`include "timescale.v"
module eth_miim
(
Clk,
Reset,
Divider,
NoPre,
CtrlData,
Rgad,
Fiad,
WCtrlData,
RStat,
ScanStat,
Mdi,
Mdo,
MdoEn,
Mdc,
Busy,
Prsd,
LinkFail,
Nvalid,
WCtrlDataStart,
RStatStart,
UpdateMIIRX_DATAReg
);
input Clk; // Host Clock
input Reset; // General Reset
input [7:0] Divider; // Divider for the host clock
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
input Mdi; // MII Management Data In
output Mdc; // MII Management Data Clock
output Mdo; // MII Management Data Output
output MdoEn; // MII Management Data Output Enable
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd; // Read Status Data (data read from the PHY)
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
parameter Tp = 1;
reg Nvalid;
reg EndBusy_d; // Pre-end Busy signal
reg EndBusy; // End Busy signal (stops the operation in progress)
reg WCtrlData_q1; // Write Control Data operation delayed 1 Clk cycle
reg WCtrlData_q2; // Write Control Data operation delayed 2 Clk cycles
reg WCtrlData_q3; // Write Control Data operation delayed 3 Clk cycles
reg WCtrlDataStart; // Start Write Control Data Command (positive edge detected)
reg WCtrlDataStart_q;
reg WCtrlDataStart_q1; // Start Write Control Data Command delayed 1 Mdc cycle
reg WCtrlDataStart_q2; // Start Write Control Data Command delayed 2 Mdc cycles
reg RStat_q1; // Read Status operation delayed 1 Clk cycle
reg RStat_q2; // Read Status operation delayed 2 Clk cycles
reg RStat_q3; // Read Status operation delayed 3 Clk cycles
reg RStatStart; // Start Read Status Command (positive edge detected)
reg RStatStart_q1; // Start Read Status Command delayed 1 Mdc cycle
reg RStatStart_q2; // Start Read Status Command delayed 2 Mdc cycles
reg ScanStat_q1; // Scan Status operation delayed 1 cycle
reg ScanStat_q2; // Scan Status operation delayed 2 cycles
reg SyncStatMdcEn; // Scan Status operation delayed at least cycles and synchronized to MdcEn
wire WriteDataOp; // Write Data Operation (positive edge detected)
wire ReadStatusOp; // Read Status Operation (positive edge detected)
wire ScanStatusOp; // Scan Status Operation (positive edge detected)
wire StartOp; // Start Operation (start of any of the preceding operations)
wire EndOp; // End of Operation
reg InProgress; // Operation in progress
reg InProgress_q1; // Operation in progress delayed 1 Mdc cycle
reg InProgress_q2; // Operation in progress delayed 2 Mdc cycles
reg InProgress_q3; // Operation in progress delayed 3 Mdc cycles
reg WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
reg [6:0] BitCounter; // Bit Counter
wire [3:0] ByteSelect; // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
wire MdcEn_n;
wire LatchByte1_d2;
wire LatchByte0_d2;
reg LatchByte1_d;
reg LatchByte0_d;
reg [1:0] LatchByte; // Latch Byte selects which part of Read Status Data is updated from the shift register
reg UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
EndBusy_d <= #Tp 1'b0;
EndBusy <= #Tp 1'b0;
end
else
begin
EndBusy_d <= #Tp ~InProgress_q2 & InProgress_q3;
EndBusy <= #Tp EndBusy_d;
end
end
// Update MII RX_DATA register
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
UpdateMIIRX_DATAReg <= #Tp 0;
else
if(EndBusy & ~WCtrlDataStart_q)
UpdateMIIRX_DATAReg <= #Tp 1;
else
UpdateMIIRX_DATAReg <= #Tp 0;
end
// Generation of the delayed signals used for positive edge triggering.
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
WCtrlData_q1 <= #Tp 1'b0;
WCtrlData_q2 <= #Tp 1'b0;
WCtrlData_q3 <= #Tp 1'b0;
RStat_q1 <= #Tp 1'b0;
RStat_q2 <= #Tp 1'b0;
RStat_q3 <= #Tp 1'b0;
ScanStat_q1 <= #Tp 1'b0;
ScanStat_q2 <= #Tp 1'b0;
SyncStatMdcEn <= #Tp 1'b0;
end
else
begin
WCtrlData_q1 <= #Tp WCtrlData;
WCtrlData_q2 <= #Tp WCtrlData_q1;
WCtrlData_q3 <= #Tp WCtrlData_q2;
RStat_q1 <= #Tp RStat;
RStat_q2 <= #Tp RStat_q1;
RStat_q3 <= #Tp RStat_q2;
ScanStat_q1 <= #Tp ScanStat;
ScanStat_q2 <= #Tp ScanStat_q1;
if(MdcEn)
SyncStatMdcEn <= #Tp ScanStat_q2;
end
end
// Generation of the Start Commands (Write Control Data or Read Status)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
WCtrlDataStart <= #Tp 1'b0;
WCtrlDataStart_q <= #Tp 1'b0;
RStatStart <= #Tp 1'b0;
end
else
begin
if(EndBusy)
begin
WCtrlDataStart <= #Tp 1'b0;
RStatStart <= #Tp 1'b0;
end
else
begin
if(WCtrlData_q2 & ~WCtrlData_q3)
WCtrlDataStart <= #Tp 1'b1;
if(RStat_q2 & ~RStat_q3)
RStatStart <= #Tp 1'b1;
WCtrlDataStart_q <= #Tp WCtrlDataStart;
end
end
end
// Generation of the Nvalid signal (indicates when the status is invalid)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Nvalid <= #Tp 1'b0;
else
begin
if(~InProgress_q2 & InProgress_q3)
begin
Nvalid <= #Tp 1'b0;
end
else
begin
if(ScanStat_q2 & ~SyncStatMdcEn)
Nvalid <= #Tp 1'b1;
end
end
end
// Signals used for the generation of the Operation signals (positive edge)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
WCtrlDataStart_q1 <= #Tp 1'b0;
WCtrlDataStart_q2 <= #Tp 1'b0;
RStatStart_q1 <= #Tp 1'b0;
RStatStart_q2 <= #Tp 1'b0;
InProgress_q1 <= #Tp 1'b0;
InProgress_q2 <= #Tp 1'b0;
InProgress_q3 <= #Tp 1'b0;
LatchByte0_d <= #Tp 1'b0;
LatchByte1_d <= #Tp 1'b0;
LatchByte <= #Tp 2'b00;
end
else
begin
if(MdcEn)
begin
WCtrlDataStart_q1 <= #Tp WCtrlDataStart;
WCtrlDataStart_q2 <= #Tp WCtrlDataStart_q1;
RStatStart_q1 <= #Tp RStatStart;
RStatStart_q2 <= #Tp RStatStart_q1;
LatchByte[0] <= #Tp LatchByte0_d;
LatchByte[1] <= #Tp LatchByte1_d;
LatchByte0_d <= #Tp LatchByte0_d2;
LatchByte1_d <= #Tp LatchByte1_d2;
InProgress_q1 <= #Tp InProgress;
InProgress_q2 <= #Tp InProgress_q1;
InProgress_q3 <= #Tp InProgress_q2;
end
end
end
// Generation of the Operation signals
assign WriteDataOp = WCtrlDataStart_q1 & ~WCtrlDataStart_q2;
assign ReadStatusOp = RStatStart_q1 & ~RStatStart_q2;
assign ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q1 & ~InProgress_q2;
assign StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp;
// Busy
assign Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
InProgress <= #Tp 1'b0;
WriteOp <= #Tp 1'b0;
end
else
begin
if(MdcEn)
begin
if(StartOp)
begin
if(~InProgress)
WriteOp <= #Tp WriteDataOp;
InProgress <= #Tp 1'b1;
end
else
begin
if(EndOp)
begin
InProgress <= #Tp 1'b0;
WriteOp <= #Tp 1'b0;
end
end
end
end
end
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
BitCounter[6:0] <= #Tp 7'h0;
else
begin
if(MdcEn)
begin
if(InProgress)
begin
if(NoPre & ( BitCounter == 7'h0 ))
BitCounter[6:0] <= #Tp 7'h21;
else
BitCounter[6:0] <= #Tp BitCounter[6:0] + 1'b1;
end
else
BitCounter[6:0] <= #Tp 7'h0;
end
end
end
// Operation ends when the Bit Counter reaches 63
assign EndOp = BitCounter==63;
assign ByteSelect[0] = InProgress & ((NoPre & (BitCounter == 7'h0)) | (~NoPre & (BitCounter == 7'h20)));
assign ByteSelect[1] = InProgress & (BitCounter == 7'h28);
assign ByteSelect[2] = InProgress & WriteOp & (BitCounter == 7'h30);
assign ByteSelect[3] = InProgress & WriteOp & (BitCounter == 7'h38);
// Latch Byte selects which part of Read Status Data is updated from the shift register
assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37;
assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F;
// Connecting the Clock Generator Module
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
);
// Connecting the Shift Register Module
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
);
// Connecting the Output Control Module
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
.Mdo(Mdo), .MdoEn(MdoEn)
);
endmodule
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 2025 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w32,
w31,
w256,
w257,
w2056,
w2025;
assign w1 = i_data0;
assign w2025 = w2056 - w31;
assign w2056 = w257 << 3;
assign w256 = w1 << 8;
assign w257 = w1 + w256;
assign w31 = w32 - w1;
assign w32 = w1 << 5;
assign o_data0 = w2025;
//multiplier_block area estimate = 5631.59510674265;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [11:0] in_a;
reg [31:0] sel;
wire [2:0] out_x;
extractor #(4,3) extractor (
// Outputs
.out (out_x),
// Inputs
.in (in_a),
.sel (sel));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x %x %x\n", cyc, in_a, sel, out_x);
if (cyc==1) begin
in_a <= 12'b001_101_111_010;
sel <= 32'd0;
end
if (cyc==2) begin
sel <= 32'd1;
if (out_x != 3'b010) $stop;
end
if (cyc==3) begin
sel <= 32'd2;
if (out_x != 3'b111) $stop;
end
if (cyc==4) begin
sel <= 32'd3;
if (out_x != 3'b101) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module extractor (/*AUTOARG*/
// Outputs
out,
// Inputs
in, sel
);
parameter IN_WIDTH=8;
parameter OUT_WIDTH=2;
input [IN_WIDTH*OUT_WIDTH-1:0] in;
output [OUT_WIDTH-1:0] out;
input [31:0] sel;
wire [OUT_WIDTH-1:0] out = selector(in,sel);
function [OUT_WIDTH-1:0] selector;
input [IN_WIDTH*OUT_WIDTH-1:0] inv;
input [31:0] selv;
integer i;
begin
selector = 0;
for (i=0; i<OUT_WIDTH; i=i+1) begin
selector[i] = inv[selv*OUT_WIDTH+i];
end
end
endfunction
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_queue.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Bank machine queue controller.
//
// Bank machines are always associated with a queue. When the system is
// idle, all bank machines are in the idle queue. As requests are
// received, the bank machine at the head of the idle queue accepts
// the request, removes itself from the idle queue and places itself
// in a queue associated with the rank-bank of the new request.
//
// If the new request is to an idle rank-bank, a new queue is created
// for that rank-bank. If the rank-bank is not idle, then the new
// request is added to the end of the existing rank-bank queue.
//
// When the head of the idle queue accepts a new request, all other
// bank machines move down one in the idle queue. When the idle queue
// is empty, the memory interface deasserts its accept signal.
//
// When new requests are received, the first step is to classify them
// as to whether the request targets an already open rank-bank, and if
// so, does the new request also hit on the already open page? As mentioned
// above, a new request places itself in the existing queue for a
// rank-bank hit. If it is also detected that the last entry in the
// existing rank-bank queue has the same page, then the current tail
// sets a bit telling itself to pass the open row when the column
// command is issued. The "passee" knows its in the head minus one
// position and hence takes control of the rank-bank.
//
// Requests are retired out of order to optimize DRAM array resources.
// However it is required that the user cannot "observe" this out of
// order processing as a data corruption. An ordering queue is
// used to enforce some ordering rules. As controlled by a paramter,
// there can be no ordering (RELAXED), ordering of writes only (NORM), and
// strict (STRICT) ordering whereby input request ordering is
// strictly adhered to.
//
// Note that ordering applies only to column commands. Row commands
// such as activate and precharge are allowed to proceed in any order
// with the proviso that within a rank-bank row commands are processed in
// the request order.
//
// When a bank machine accepts a new request, it looks at the ordering
// mode. If no ordering, nothing is done. If strict ordering, then
// it always places itself at the end of the ordering queue. If "normal"
// or write ordering, the row machine places itself in the ordering
// queue only if the new request is a write. The bank state machine
// looks at the ordering queue, and will only issue a column
// command when it sees itself at the head of the ordering queue.
//
// When a bank machine has completed its request, it must re-enter the
// idle queue. This is done by setting the idle_r bit, and setting q_entry_r
// to the idle count.
//
// There are several situations where more than one bank machine
// will enter the idle queue simultaneously. If two or more
// simply use the idle count to place themselves in the idle queue, multiple
// bank machines will end up at the same location in the idle queue, which
// is illegal.
//
// Based on the bank machine instance numbers, a count is made of
// the number of bank machines entering idle "below" this instance. This
// number is added to the idle count to compute the location in
// idle queue.
//
// There is also a single bit computed that says there were bank machines
// entering the idle queue "above" this instance. This is used to
// compute the tail bit.
//
// The word "queue" is used frequently to describe the behavior of the
// bank_queue block. In reality, there are no queues in the ordinary sense.
// As instantiated in this block, each bank machine has a q_entry_r number.
// This number represents the position of the bank machine in its current
// queue. At any given time, a bank machine may be in the idle queue,
// one of the dynamic rank-bank queues, or a single entry manitenance queue.
// A complete description of which queue a bank machine is currently in is
// given by idle_r, its rank-bank, mainteance status and its q_entry_r number.
//
// DRAM refresh and ZQ have a private single entry queue/channel. However,
// when a refresh request is made, it must be injected into the main queue
// properly. At the time of injection, the refresh rank is compared against
// all entryies in the queue. For those that match, if timing allows, and
// they are the tail of the rank-bank queue, then the auto_pre bit is set.
// Otherwise precharge is in progress. This results in a fully precharged
// rank.
//
// At the time of injection, the refresh channel builds a bit
// vector of queue entries that hit on the refresh rank. Once all
// of these entries finish, the refresh is forced in at the row arbiter.
//
// New requests that come after the refresh request will notice that
// a refresh is in progress for their rank and wait for the refresh
// to finish before attempting to arbitrate to send an activate.
//
// Injection of a refresh sets the q_has_rd bit for all queues hitting
// on the refresh rank. This insures a starved write request will not
// indefinitely hold off a refresh.
//
// Periodic reads are required to compare themselves against requests
// that are in progress. Adding a unique compare channel for this
// is not worthwhile. Periodic read requests inhibit the accept
// signal and override any new request that might be trying to
// enter the queue.
//
// Once a periodic read has entered the queue it is nearly indistinguishable
// from a normal read request. The req_periodic_rd_r bit is set for
// queue entry. This signal is used to inhibit the rd_data_en signal.
`timescale 1ps/1ps
`define BM_SHARED_BV (ID+nBANK_MACHS-1):(ID+1)
module mig_7series_v2_3_bank_queue #
(
parameter TCQ = 100,
parameter BM_CNT_WIDTH = 2,
parameter nBANK_MACHS = 4,
parameter ORDERING = "NORM",
parameter ID = 0
)
(/*AUTOARG*/
// Outputs
head_r, tail_r, idle_ns, idle_r, pass_open_bank_ns,
pass_open_bank_r, auto_pre_r, bm_end, passing_open_bank,
ordered_issued, ordered_r, order_q_zero, rcv_open_bank,
rb_hit_busies_r, q_has_rd, q_has_priority, wait_for_maint_r,
// Inputs
clk, rst, accept_internal_r, use_addr, periodic_rd_ack_r, bm_end_in,
idle_cnt, rb_hit_busy_cnt, accept_req, rb_hit_busy_r, maint_idle,
maint_hit, row_hit_r, pre_wait_r, allow_auto_pre, sending_col,
bank_wait_in_progress, precharge_bm_end, req_wr_r, rd_wr_r,
adv_order_q, order_cnt, rb_hit_busy_ns_in, passing_open_bank_in,
was_wr, maint_req_r, was_priority
);
localparam ZERO = 0;
localparam ONE = 1;
localparam [BM_CNT_WIDTH-1:0] BM_CNT_ZERO = ZERO[0+:BM_CNT_WIDTH];
localparam [BM_CNT_WIDTH-1:0] BM_CNT_ONE = ONE[0+:BM_CNT_WIDTH];
input clk;
input rst;
// Decide if this bank machine should accept a new request.
reg idle_r_lcl;
reg head_r_lcl;
input accept_internal_r;
wire bm_ready = idle_r_lcl && head_r_lcl && accept_internal_r;
// Accept request in this bank machine. Could be maintenance or
// regular request.
input use_addr;
input periodic_rd_ack_r;
wire accept_this_bm = bm_ready && (use_addr || periodic_rd_ack_r);
// Multiple machines may enter the idle queue in a single state.
// Based on bank machine instance number, compute how many
// bank machines with lower instance numbers are entering
// the idle queue.
input [(nBANK_MACHS*2)-1:0] bm_end_in;
reg [BM_CNT_WIDTH-1:0] idlers_below;
integer i;
always @(/*AS*/bm_end_in) begin
idlers_below = BM_CNT_ZERO;
for (i=0; i<ID; i=i+1)
idlers_below = idlers_below + bm_end_in[i];
end
reg idlers_above;
always @(/*AS*/bm_end_in) begin
idlers_above = 1'b0;
for (i=ID+1; i<ID+nBANK_MACHS; i=i+1)
idlers_above = idlers_above || bm_end_in[i];
end
`ifdef MC_SVA
bm_end_and_idlers_above: cover property (@(posedge clk)
(~rst && bm_end && idlers_above));
bm_end_and_idlers_below: cover property (@(posedge clk)
(~rst && bm_end && |idlers_below));
`endif
// Compute the q_entry number.
input [BM_CNT_WIDTH-1:0] idle_cnt;
input [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt;
input accept_req;
wire bm_end_lcl;
reg adv_queue = 1'b0;
reg [BM_CNT_WIDTH-1:0] q_entry_r;
reg [BM_CNT_WIDTH-1:0] q_entry_ns;
wire [BM_CNT_WIDTH-1:0] temp;
// always @(/*AS*/accept_req or accept_this_bm or adv_queue
// or bm_end_lcl or idle_cnt or idle_r_lcl or idlers_below
// or q_entry_r or rb_hit_busy_cnt /*or rst*/) begin
//// if (rst) q_entry_ns = ID[BM_CNT_WIDTH-1:0];
//// else begin
// q_entry_ns = q_entry_r;
// if ((~idle_r_lcl && adv_queue) ||
// (idle_r_lcl && accept_req && ~accept_this_bm))
// q_entry_ns = q_entry_r - BM_CNT_ONE;
// if (accept_this_bm)
//// q_entry_ns = rb_hit_busy_cnt - (adv_queue ? BM_CNT_ONE : BM_CNT_ZERO);
// q_entry_ns = adv_queue ? (rb_hit_busy_cnt - BM_CNT_ONE) : (rb_hit_busy_cnt -BM_CNT_ZERO);
// if (bm_end_lcl) begin
// q_entry_ns = idle_cnt + idlers_below;
// if (accept_req) q_entry_ns = q_entry_ns - BM_CNT_ONE;
//// end
// end
// end
assign temp = idle_cnt + idlers_below;
always @ (*)
begin
if (accept_req & bm_end_lcl)
q_entry_ns = temp - BM_CNT_ONE;
else if (bm_end_lcl)
q_entry_ns = temp;
else if (accept_this_bm)
q_entry_ns = adv_queue ? (rb_hit_busy_cnt - BM_CNT_ONE) : (rb_hit_busy_cnt -BM_CNT_ZERO);
else if ((!idle_r_lcl & adv_queue) |
(idle_r_lcl & accept_req & !accept_this_bm))
q_entry_ns = q_entry_r - BM_CNT_ONE;
else
q_entry_ns = q_entry_r;
end
always @(posedge clk)
if (rst)
q_entry_r <= #TCQ ID[BM_CNT_WIDTH-1:0];
else
q_entry_r <= #TCQ q_entry_ns;
// Determine if this entry is the head of its queue.
reg head_ns;
always @(/*AS*/accept_req or accept_this_bm or adv_queue
or bm_end_lcl or head_r_lcl or idle_cnt or idle_r_lcl
or idlers_below or q_entry_r or rb_hit_busy_cnt or rst) begin
if (rst) head_ns = ~|ID[BM_CNT_WIDTH-1:0];
else begin
head_ns = head_r_lcl;
if (accept_this_bm)
head_ns = ~|(rb_hit_busy_cnt - (adv_queue ? BM_CNT_ONE : BM_CNT_ZERO));
if ((~idle_r_lcl && adv_queue) ||
(idle_r_lcl && accept_req && ~accept_this_bm))
head_ns = ~|(q_entry_r - BM_CNT_ONE);
if (bm_end_lcl) begin
head_ns = ~|(idle_cnt - (accept_req ? BM_CNT_ONE : BM_CNT_ZERO)) &&
~|idlers_below;
end
end
end
always @(posedge clk) head_r_lcl <= #TCQ head_ns;
output wire head_r;
assign head_r = head_r_lcl;
// Determine if this entry is the tail of its queue. Note that
// an entry can be both head and tail.
input rb_hit_busy_r;
reg tail_r_lcl = 1'b1;
generate
if (nBANK_MACHS > 1) begin : compute_tail
reg tail_ns;
always @(accept_req or accept_this_bm
or bm_end_in or bm_end_lcl or idle_r_lcl
or idlers_above or rb_hit_busy_r or rst or tail_r_lcl) begin
if (rst) tail_ns = (ID == nBANK_MACHS);
// The order of the statements below is important in the case where
// another bank machine is retiring and this bank machine is accepting.
else begin
tail_ns = tail_r_lcl;
if ((accept_req && rb_hit_busy_r) ||
(|bm_end_in[`BM_SHARED_BV] && idle_r_lcl))
tail_ns = 1'b0;
if (accept_this_bm || (bm_end_lcl && ~idlers_above)) tail_ns = 1'b1;
end
end
always @(posedge clk) tail_r_lcl <= #TCQ tail_ns;
end // if (nBANK_MACHS > 1)
endgenerate
output wire tail_r;
assign tail_r = tail_r_lcl;
wire clear_req = bm_end_lcl || rst;
// Is this entry in the idle queue?
reg idle_ns_lcl;
always @(/*AS*/accept_this_bm or clear_req or idle_r_lcl) begin
idle_ns_lcl = idle_r_lcl;
if (accept_this_bm) idle_ns_lcl = 1'b0;
if (clear_req) idle_ns_lcl = 1'b1;
end
always @(posedge clk) idle_r_lcl <= #TCQ idle_ns_lcl;
output wire idle_ns;
assign idle_ns = idle_ns_lcl;
output wire idle_r;
assign idle_r = idle_r_lcl;
// Maintenance hitting on this active bank machine is in progress.
input maint_idle;
input maint_hit;
wire maint_hit_this_bm = ~maint_idle && maint_hit;
// Does new request hit on this bank machine while it is able to pass the
// open bank?
input row_hit_r;
input pre_wait_r;
wire pass_open_bank_eligible =
tail_r_lcl && rb_hit_busy_r && row_hit_r && ~pre_wait_r;
// Set pass open bank bit, but not if request preceded active maintenance.
reg wait_for_maint_r_lcl;
reg pass_open_bank_r_lcl;
wire pass_open_bank_ns_lcl = ~clear_req &&
(pass_open_bank_r_lcl ||
(accept_req && pass_open_bank_eligible &&
(~maint_hit_this_bm || wait_for_maint_r_lcl)));
always @(posedge clk) pass_open_bank_r_lcl <= #TCQ pass_open_bank_ns_lcl;
output wire pass_open_bank_ns;
assign pass_open_bank_ns = pass_open_bank_ns_lcl;
output wire pass_open_bank_r;
assign pass_open_bank_r = pass_open_bank_r_lcl;
`ifdef MC_SVA
pass_open_bank: cover property (@(posedge clk) (~rst && pass_open_bank_ns));
pass_open_bank_killed_by_maint: cover property (@(posedge clk)
(~rst && accept_req && pass_open_bank_eligible &&
maint_hit_this_bm && ~wait_for_maint_r_lcl));
pass_open_bank_following_maint: cover property (@(posedge clk)
(~rst && accept_req && pass_open_bank_eligible &&
maint_hit_this_bm && wait_for_maint_r_lcl));
`endif
// Should the column command be sent with the auto precharge bit set? This
// will happen when it is detected that next request is to a different row,
// or the next reqest is the next request is refresh to this rank.
reg auto_pre_r_lcl;
reg auto_pre_ns;
input allow_auto_pre;
always @(/*AS*/accept_req or allow_auto_pre or auto_pre_r_lcl
or clear_req or maint_hit_this_bm or rb_hit_busy_r
or row_hit_r or tail_r_lcl or wait_for_maint_r_lcl) begin
auto_pre_ns = auto_pre_r_lcl;
if (clear_req) auto_pre_ns = 1'b0;
else
if (accept_req && tail_r_lcl && allow_auto_pre && rb_hit_busy_r &&
(~row_hit_r || (maint_hit_this_bm && ~wait_for_maint_r_lcl)))
auto_pre_ns = 1'b1;
end
always @(posedge clk) auto_pre_r_lcl <= #TCQ auto_pre_ns;
output wire auto_pre_r;
assign auto_pre_r = auto_pre_r_lcl;
`ifdef MC_SVA
auto_precharge: cover property (@(posedge clk) (~rst && auto_pre_ns));
maint_triggers_auto_precharge: cover property (@(posedge clk)
(~rst && auto_pre_ns && ~auto_pre_r && row_hit_r));
`endif
// Determine when the current request is finished.
input sending_col;
input req_wr_r;
input rd_wr_r;
wire sending_col_not_rmw_rd = sending_col && !(req_wr_r && rd_wr_r);
input bank_wait_in_progress;
input precharge_bm_end;
reg pre_bm_end_r;
wire pre_bm_end_ns = precharge_bm_end ||
(bank_wait_in_progress && pass_open_bank_ns_lcl);
always @(posedge clk) pre_bm_end_r <= #TCQ pre_bm_end_ns;
assign bm_end_lcl =
pre_bm_end_r || (sending_col_not_rmw_rd && pass_open_bank_r_lcl);
output wire bm_end;
assign bm_end = bm_end_lcl;
// Determine that the open bank should be passed to the successor bank machine.
reg pre_passing_open_bank_r;
wire pre_passing_open_bank_ns =
bank_wait_in_progress && pass_open_bank_ns_lcl;
always @(posedge clk) pre_passing_open_bank_r <= #TCQ
pre_passing_open_bank_ns;
output wire passing_open_bank;
assign passing_open_bank =
pre_passing_open_bank_r || (sending_col_not_rmw_rd && pass_open_bank_r_lcl);
reg ordered_ns;
wire set_order_q = ((ORDERING == "STRICT") || ((ORDERING == "NORM") &&
req_wr_r)) && accept_this_bm;
wire ordered_issued_lcl =
sending_col_not_rmw_rd && !(req_wr_r && rd_wr_r) &&
((ORDERING == "STRICT") || ((ORDERING == "NORM") && req_wr_r));
output wire ordered_issued;
assign ordered_issued = ordered_issued_lcl;
reg ordered_r_lcl;
always @(/*AS*/ordered_issued_lcl or ordered_r_lcl or rst
or set_order_q) begin
if (rst) ordered_ns = 1'b0;
else begin
ordered_ns = ordered_r_lcl;
// Should never see accept_this_bm and adv_order_q at the same time.
if (set_order_q) ordered_ns = 1'b1;
if (ordered_issued_lcl) ordered_ns = 1'b0;
end
end
always @(posedge clk) ordered_r_lcl <= #TCQ ordered_ns;
output wire ordered_r;
assign ordered_r = ordered_r_lcl;
// Figure out when to advance the ordering queue.
input adv_order_q;
input [BM_CNT_WIDTH-1:0] order_cnt;
reg [BM_CNT_WIDTH-1:0] order_q_r;
reg [BM_CNT_WIDTH-1:0] order_q_ns;
always @(/*AS*/adv_order_q or order_cnt or order_q_r or rst
or set_order_q) begin
order_q_ns = order_q_r;
if (rst) order_q_ns = BM_CNT_ZERO;
if (set_order_q)
if (adv_order_q) order_q_ns = order_cnt - BM_CNT_ONE;
else order_q_ns = order_cnt;
if (adv_order_q && |order_q_r) order_q_ns = order_q_r - BM_CNT_ONE;
end
always @(posedge clk) order_q_r <= #TCQ order_q_ns;
output wire order_q_zero;
assign order_q_zero = ~|order_q_r ||
(adv_order_q && (order_q_r == BM_CNT_ONE)) ||
((ORDERING == "NORM") && rd_wr_r);
// Keep track of which other bank machine are ahead of this one in a
// rank-bank queue. This is necessary to know when to advance this bank
// machine in the queue, and when to update bank state machine counter upon
// passing a bank.
input [(nBANK_MACHS*2)-1:0] rb_hit_busy_ns_in;
reg [(nBANK_MACHS*2)-1:0] rb_hit_busies_r_lcl = {nBANK_MACHS*2{1'b0}};
input [(nBANK_MACHS*2)-1:0] passing_open_bank_in;
output reg rcv_open_bank = 1'b0;
generate
if (nBANK_MACHS > 1) begin : rb_hit_busies
// The clear_vector resets bits in the rb_hit_busies vector as bank machines
// completes requests. rst also resets all the bits.
wire [nBANK_MACHS-2:0] clear_vector =
({nBANK_MACHS-1{rst}} | bm_end_in[`BM_SHARED_BV]);
// As this bank machine takes on a new request, capture the vector of
// which other bank machines are in the same queue.
wire [`BM_SHARED_BV] rb_hit_busies_ns =
~clear_vector &
(idle_ns_lcl
? rb_hit_busy_ns_in[`BM_SHARED_BV]
: rb_hit_busies_r_lcl[`BM_SHARED_BV]);
always @(posedge clk) rb_hit_busies_r_lcl[`BM_SHARED_BV] <=
#TCQ rb_hit_busies_ns;
// Compute when to advance this queue entry based on seeing other bank machines
// in the same queue finish.
always @(bm_end_in or rb_hit_busies_r_lcl)
adv_queue =
|(bm_end_in[`BM_SHARED_BV] & rb_hit_busies_r_lcl[`BM_SHARED_BV]);
// Decide when to receive an open bank based on knowing this bank machine is
// one entry from the head, and a passing_open_bank hits on the
// rb_hit_busies vector.
always @(idle_r_lcl
or passing_open_bank_in or q_entry_r
or rb_hit_busies_r_lcl) rcv_open_bank =
|(rb_hit_busies_r_lcl[`BM_SHARED_BV] & passing_open_bank_in[`BM_SHARED_BV])
&& (q_entry_r == BM_CNT_ONE) && ~idle_r_lcl;
end
endgenerate
output wire [nBANK_MACHS*2-1:0] rb_hit_busies_r;
assign rb_hit_busies_r = rb_hit_busies_r_lcl;
// Keep track if the queue this entry is in has priority content.
input was_wr;
input maint_req_r;
reg q_has_rd_r;
wire q_has_rd_ns = ~clear_req &&
(q_has_rd_r || (accept_req && rb_hit_busy_r && ~was_wr) ||
(maint_req_r && maint_hit && ~idle_r_lcl));
always @(posedge clk) q_has_rd_r <= #TCQ q_has_rd_ns;
output wire q_has_rd;
assign q_has_rd = q_has_rd_r;
input was_priority;
reg q_has_priority_r;
wire q_has_priority_ns = ~clear_req &&
(q_has_priority_r || (accept_req && rb_hit_busy_r && was_priority));
always @(posedge clk) q_has_priority_r <= #TCQ q_has_priority_ns;
output wire q_has_priority;
assign q_has_priority = q_has_priority_r;
// Figure out if this entry should wait for maintenance to end.
wire wait_for_maint_ns = ~rst && ~maint_idle &&
(wait_for_maint_r_lcl || (maint_hit && accept_this_bm));
always @(posedge clk) wait_for_maint_r_lcl <= #TCQ wait_for_maint_ns;
output wire wait_for_maint_r;
assign wait_for_maint_r = wait_for_maint_r_lcl;
endmodule // bank_queue
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
wire noswap = crc[32];
wire nibble = crc[33];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
wire [31:0] swapped; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
.swapped (swapped[31:0]),
// Inputs
.clk (clk),
.noswap (noswap),
.nibble (nibble),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== 64'h89522c3f5e5ca324) $stop;
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out, swapped,
// Inputs
clk, noswap, nibble, in
);
input clk;
input noswap;
input nibble;
input [31:0] in;
output [31:0] out;
output [31:0] swapped;
function [7:0] EndianSwap;
input Nibble;
input [7:0] Data;
begin
EndianSwap = (Nibble ? { Data[0], Data[1], Data[2], Data[3],
Data[4], Data[5], Data[6], Data[7] }
: { 4'h0, Data[0], Data[1], Data[2], Data[3] });
end
endfunction
assign out[31:24] = (noswap ? in[31:24]
: EndianSwap(nibble, in[31:24]));
assign out[23:16] = (noswap ? in[23:16]
: EndianSwap(nibble, in[23:16]));
assign out[15:8] = (noswap ? in[15:8]
: EndianSwap(nibble, in[15:8]));
assign out[7:0] = (noswap ? in[7:0]
: EndianSwap(nibble, in[7:0]));
reg [31:0] swapped;
always @(posedge clk) begin
swapped[31:24] <= EndianSwap(nibble, in[31:24]);
swapped[23:16] <= EndianSwap(nibble, in[23:16]);
swapped[15:8] <= EndianSwap(nibble, in[15:8] );
swapped[7:0] <= EndianSwap(nibble, in[7:0] );
end
endmodule
|
`timescale 1ns / 1ps
module square_root_comb #(parameter N = 8, M = 16)(
input [N-1:0] A,
output [N/2-1:0] O
);
wire [N/2-1:0] Y[0:M];
wire [N/2-1:0] Y0[0:M];
assign Y[0] = {1'b1,{(N/2-1){1'b0}}};
assign Y0[0] = {1'b1,{(N/2-1){1'b0}}};
assign O = Y[M];
genvar gv;
generate
for (gv = 0; gv < M; gv = gv + 1)
begin: sqr_rt
squar_root_unit #(.N(N)) squar_root_unit(
.x(A),
.y_in(Y[gv]),
.y0_in(Y0[gv]),
.y(Y[gv+1]),
.y0(Y0[gv+1])
);
end
endgenerate
endmodule
module squar_root_unit #(parameter N = 8)(
input [N-1:0] x,
input [N/2-1:0] y_in, y0_in,
output [N/2-1:0] y, y0
);
wire t;
wire [N/2-1:0] y_min_y0, y_mid;
wire [N-1:0] y_sqr;
wire [1:0] temp;
//assign y_sqr = y_in * y_in;
MULT #(.N(N/2), .M(N/2)) MULT1 (.A(y_in), .B(y_in), .O(y_sqr));
//assign t = (y_sqr > x) ? 1 : 0;
COMP #(.N(N)) COMP1 (.A(x), .B(y_sqr), .O(t));
//assign y_min_y0 = y_in - y0_in;
SUB_ #(.N(N/2), .M(N/2)) SUB1 (.A(y_in), .B(y0_in), .O({temp[0], y_min_y0}));
//assign y_mid = t? y_min_y0 : y_in;
MUX #(.N(N/2)) MUX1 (.A(y_min_y0), .B(y_in), .S(t), .O(y_mid));
assign y0 = y0_in >> 1;
//assign y = y_mid + y0;
ADD_ #(.N(N/2), .M(N/2)) ADD1 (.A(y_mid), .B(y0), .O({temp[1],y}));
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Interface to Cypress FX2 bus
// A packet is 512 Bytes. Each fifo line is 2 bytes
// Fifo has 1024 or 2048 lines
module tx_buffer
( // USB Side
input usbclk,
input bus_reset, // Used here for the 257-Hack to fix the FX2 bug
input [15:0] usbdata,
input wire WR,
output reg have_space,
output reg tx_underrun,
input clear_status,
// DSP Side
input txclk,
input reset, // standard DSP-side reset
input wire [3:0] channels,
output reg [15:0] tx_i_0,
output reg [15:0] tx_q_0,
output reg [15:0] tx_i_1,
output reg [15:0] tx_q_1,
input txstrobe,
output wire tx_empty,
output [31:0] debugbus
);
wire [11:0] txfifolevel;
wire [15:0] fifodata;
wire rdreq;
reg [3:0] phase;
wire sop_f, iq_f;
reg sop;
// USB Side of FIFO
reg [15:0] usbdata_reg;
reg wr_reg;
reg [8:0] write_count;
always @(posedge usbclk)
have_space <= (txfifolevel < (4092-256)); // be extra conservative
always @(posedge usbclk)
begin
wr_reg <= WR;
usbdata_reg <= usbdata;
end
always @(posedge usbclk)
if(bus_reset)
write_count <= 0;
else if(wr_reg)
write_count <= write_count + 1;
else
write_count <= 0;
always @(posedge usbclk)
sop <= WR & ~wr_reg; // Edge detect
// FIFO
fifo_4k_18 txfifo
( // USB Write Side
.data ( {sop,write_count[0],usbdata_reg} ),
.wrreq ( wr_reg & ~write_count[8] ),
.wrclk ( usbclk ),
.wrfull ( ),
.wrempty ( ),
.wrusedw ( txfifolevel ),
// DSP Read Side
.q ( {sop_f, iq_f, fifodata} ),
.rdreq ( rdreq ),
.rdclk ( txclk ),
.rdfull ( ),
.rdempty ( tx_empty ),
.rdusedw ( ),
// Async, shared
.aclr ( reset ) );
// DAC Side of FIFO
always @(posedge txclk)
if(reset)
begin
{tx_i_0,tx_q_0,tx_i_1,tx_q_1} <= 64'h0;
phase <= 4'd0;
end
else if(phase == channels)
begin
if(txstrobe)
phase <= 4'd0;
end
else
if(~tx_empty)
begin
case(phase)
4'd0 : tx_i_0 <= fifodata;
4'd1 : tx_q_0 <= fifodata;
4'd2 : tx_i_1 <= fifodata;
4'd3 : tx_q_1 <= fifodata;
endcase // case(phase)
phase <= phase + 4'd1;
end
assign rdreq = ((phase != channels) & ~tx_empty);
// Detect Underruns, cross clock domains
reg clear_status_dsp, tx_underrun_dsp;
always @(posedge txclk)
clear_status_dsp <= clear_status;
always @(posedge usbclk)
tx_underrun <= tx_underrun_dsp;
always @(posedge txclk)
if(reset)
tx_underrun_dsp <= 1'b0;
else if(txstrobe & (phase != channels))
tx_underrun_dsp <= 1'b1;
else if(clear_status_dsp)
tx_underrun_dsp <= 1'b0;
// TX debug bus
//
// 15:0 txclk domain => TXA [15:0]
// 31:16 usbclk domain => RXA [15:0]
assign debugbus[0] = reset;
assign debugbus[1] = txstrobe;
assign debugbus[2] = rdreq;
assign debugbus[6:3] = phase;
assign debugbus[7] = tx_empty;
assign debugbus[8] = tx_underrun_dsp;
assign debugbus[9] = iq_f;
assign debugbus[10] = sop_f;
assign debugbus[14:11] = 0;
assign debugbus[15] = txclk;
assign debugbus[16] = bus_reset;
assign debugbus[17] = WR;
assign debugbus[18] = wr_reg;
assign debugbus[19] = have_space;
assign debugbus[20] = write_count[8];
assign debugbus[21] = write_count[0];
assign debugbus[22] = sop;
assign debugbus[23] = tx_underrun;
assign debugbus[30:24] = 0;
assign debugbus[31] = usbclk;
endmodule // tx_buffer
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_init.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:09 $
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// Memory initialization and overall master state control during
// initialization and calibration. Specifically, the following functions
// are performed:
// 1. Memory initialization (initial AR, mode register programming, etc.)
// 2. Initiating write leveling
// 3. Generate training pattern writes for read leveling. Generate
// memory readback for read leveling.
// This module has an interface for providing control/address and write
// data to the PHY Control Block during initialization/calibration.
// Once initialization and calibration are complete, control is passed to the MC.
//
//Reference:
//Revision History:
//
//*****************************************************************************
/******************************************************************************
**$Id: ddr_phy_init.v,v 1.1 2011/06/02 08:35:09 mishra Exp $
**$Date: 2011/06/02 08:35:09 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_init.v,v $
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v1_9_ddr_phy_init #
(
parameter TCQ = 100,
parameter nCK_PER_CLK = 4, // # of memory clocks per CLK
parameter CLK_PERIOD = 3000, // Logic (internal) clk period (in ps)
parameter USE_ODT_PORT = 0, // 0 - No ODT output from FPGA
// 1 - ODT output from FPGA
parameter PRBS_WIDTH = 8, // PRBS sequence = 2^PRBS_WIDTH
parameter BANK_WIDTH = 2,
parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank
parameter COL_WIDTH = 10,
parameter nCS_PER_RANK = 1, // # of CS bits per rank e.g. for
// component I/F with CS_WIDTH=1,
// nCS_PER_RANK=# of components
parameter DQ_WIDTH = 64,
parameter DQS_WIDTH = 8,
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter ROW_WIDTH = 14,
parameter CS_WIDTH = 1,
parameter RANKS = 1, // # of memory ranks in the interface
parameter CKE_WIDTH = 1, // # of cke outputs
parameter DRAM_TYPE = "DDR3",
parameter REG_CTRL = "ON",
parameter ADDR_CMD_MODE= "1T",
// calibration Address
parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address
parameter CALIB_COL_ADD = 12'h000, // Calibration column address
parameter CALIB_BA_ADD = 3'h0, // Calibration bank address
// DRAM mode settings
parameter AL = "0", // Additive Latency option
parameter BURST_MODE = "8", // Burst length
parameter BURST_TYPE = "SEQ", // Burst type
// parameter nAL = 0, // Additive latency (in clk cyc)
parameter nCL = 5, // Read CAS latency (in clk cyc)
parameter nCWL = 5, // Write CAS latency (in clk cyc)
parameter tRFC = 110000, // Refresh-to-command delay (in ps)
parameter OUTPUT_DRV = "HIGH", // DRAM reduced output drive option
parameter RTT_NOM = "60", // Nominal ODT termination value
parameter RTT_WR = "60", // Write ODT termination value
parameter WRLVL = "ON", // Enable write leveling
// parameter PHASE_DETECT = "ON", // Enable read phase detector
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter nSLOTS = 1, // Number of DIMM SLOTs in the system
parameter SIM_INIT_OPTION = "NONE", // "NONE", "SKIP_PU_DLY", "SKIP_INIT"
parameter SIM_CAL_OPTION = "NONE", // "NONE", "FAST_CAL", "SKIP_CAL"
parameter CKE_ODT_AUX = "FALSE",
parameter PRE_REV3ES = "OFF", // Enable TG error detection during calibration
parameter TEST_AL = "0" // Internal use for ICM verification
)
(
input clk,
input rst,
input [2*8*nCK_PER_CLK-1:0] prbs_o,
input delay_incdec_done,
input ck_addr_cmd_delay_done,
input pi_phase_locked_all,
input pi_dqs_found_done,
input dqsfound_retry,
input dqs_found_prech_req,
output reg pi_phaselock_start,
output pi_phase_locked_err,
output pi_calib_done,
input phy_if_empty,
// Read/write calibration interface
input wrlvl_done,
input wrlvl_rank_done,
input wrlvl_byte_done,
input wrlvl_byte_redo,
input wrlvl_final,
output reg wrlvl_final_if_rst,
input oclkdelay_calib_done,
input oclk_prech_req,
input oclk_calib_resume,
output reg oclkdelay_calib_start,
input done_dqs_tap_inc,
input [5:0] rd_data_offset_0,
input [5:0] rd_data_offset_1,
input [5:0] rd_data_offset_2,
input [6*RANKS-1:0] rd_data_offset_ranks_0,
input [6*RANKS-1:0] rd_data_offset_ranks_1,
input [6*RANKS-1:0] rd_data_offset_ranks_2,
input pi_dqs_found_rank_done,
input wrcal_done,
input wrcal_prech_req,
input wrcal_read_req,
input wrcal_act_req,
input temp_wrcal_done,
input [7:0] slot_0_present,
input [7:0] slot_1_present,
output reg wl_sm_start,
output reg wr_lvl_start,
output reg wrcal_start,
output reg wrcal_rd_wait,
output reg wrcal_sanity_chk,
output reg tg_timer_done,
output reg no_rst_tg_mc,
input rdlvl_stg1_done,
input rdlvl_stg1_rank_done,
output reg rdlvl_stg1_start,
output reg pi_dqs_found_start,
output reg detect_pi_found_dqs,
// rdlvl stage 1 precharge requested after each DQS
input rdlvl_prech_req,
input rdlvl_last_byte_done,
input wrcal_resume,
input wrcal_sanity_chk_done,
// MPR read leveling
input mpr_rdlvl_done,
input mpr_rnk_done,
input mpr_last_byte_done,
output reg mpr_rdlvl_start,
output reg mpr_end_if_reset,
// PRBS Read Leveling
input prbs_rdlvl_done,
input prbs_last_byte_done,
input prbs_rdlvl_prech_req,
output reg prbs_rdlvl_start,
output reg prbs_gen_clk_en,
// Signals shared btw multiple calibration stages
output reg prech_done,
// Data select / status
output reg init_calib_complete,
// Signal to mask memory model error for Invalid latching edge
output reg calib_writes,
// PHY address/control
// 2 commands to PHY Control Block per div 2 clock in 2:1 mode
// 4 commands to PHY Control Block per div 4 clock in 4:1 mode
output reg [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address,
output reg [nCK_PER_CLK*BANK_WIDTH-1:0]phy_bank,
output reg [nCK_PER_CLK-1:0] phy_ras_n,
output reg [nCK_PER_CLK-1:0] phy_cas_n,
output reg [nCK_PER_CLK-1:0] phy_we_n,
output reg phy_reset_n,
output [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n,
// Hard PHY Interface signals
input phy_ctl_ready,
input phy_ctl_full,
input phy_cmd_full,
input phy_data_full,
output reg calib_ctl_wren,
output reg calib_cmd_wren,
output reg [1:0] calib_seq,
output reg write_calib,
output reg read_calib,
// PHY_Ctl_Wd
output reg [2:0] calib_cmd,
// calib_aux_out used for CKE and ODT
output reg [3:0] calib_aux_out,
output reg [1:0] calib_odt ,
output reg [nCK_PER_CLK-1:0] calib_cke ,
output [1:0] calib_rank_cnt,
output reg [1:0] calib_cas_slot,
output reg [5:0] calib_data_offset_0,
output reg [5:0] calib_data_offset_1,
output reg [5:0] calib_data_offset_2,
// PHY OUT_FIFO
output reg calib_wrdata_en,
output reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_wrdata,
// PHY Read
output phy_rddata_en,
output phy_rddata_valid,
output [255:0] dbg_phy_init
);
//*****************************************************************************
// Assertions to be added
//*****************************************************************************
// The phy_ctl_full signal must never be asserted in synchronous mode of
// operation either 4:1 or 2:1
//
// The RANKS parameter must never be set to '0' by the user
// valid values: 1 to 4
//
//*****************************************************************************
//***************************************************************************
// Number of Read level stage 1 writes limited to a SDRAM row
// The address of Read Level stage 1 reads must also be limited
// to a single SDRAM row
// (2^COL_WIDTH)/BURST_MODE = (2^10)/8 = 128
localparam NUM_STG1_WR_RD = (BURST_MODE == "8") ? 4 :
(BURST_MODE == "4") ? 8 : 4;
localparam ADDR_INC = (BURST_MODE == "8") ? 8 :
(BURST_MODE == "4") ? 4 : 8;
// In a 2 slot dual rank per system RTT_NOM values
// for Rank2 and Rank3 default to 40 ohms
localparam RTT_NOM2 = "40";
localparam RTT_NOM3 = "40";
localparam RTT_NOM_int = (USE_ODT_PORT == 1) ? RTT_NOM : RTT_WR;
// Specifically for use with half-frequency controller (nCK_PER_CLK=2)
// = 1 if burst length = 4, = 0 if burst length = 8. Determines how
// often row command needs to be issued during read-leveling
// For DDR3 the burst length is fixed during calibration
localparam BURST4_FLAG = (DRAM_TYPE == "DDR3")? 1'b0 :
(BURST_MODE == "8") ? 1'b0 :
((BURST_MODE == "4") ? 1'b1 : 1'b0);
//***************************************************************************
// Counter values used to determine bus timing
// NOTE on all counter terminal counts - these can/should be one less than
// the actual delay to take into account extra clock cycle delay in
// generating the corresponding "done" signal
//***************************************************************************
localparam CLK_MEM_PERIOD = CLK_PERIOD / nCK_PER_CLK;
// Calculate initial delay required in number of CLK clock cycles
// to delay initially. The counter is clocked by [CLK/1024] - which
// is approximately division by 1000 - note that the formulas below will
// result in more than the minimum wait time because of this approximation.
// NOTE: For DDR3 JEDEC specifies to delay reset
// by 200us, and CKE by an additional 500us after power-up
// For DDR2 CKE is delayed by 200us after power up.
localparam DDR3_RESET_DELAY_NS = 200000;
localparam DDR3_CKE_DELAY_NS = 500000 + DDR3_RESET_DELAY_NS;
localparam DDR2_CKE_DELAY_NS = 200000;
localparam PWRON_RESET_DELAY_CNT =
((DDR3_RESET_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD);
localparam PWRON_CKE_DELAY_CNT = (DRAM_TYPE == "DDR3") ?
(((DDR3_CKE_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD)) :
(((DDR2_CKE_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD));
// FOR DDR2 -1 taken out. With -1 not getting 200us. The equation
// needs to be reworked.
localparam DDR2_INIT_PRE_DELAY_PS = 400000;
localparam DDR2_INIT_PRE_CNT =
((DDR2_INIT_PRE_DELAY_PS+CLK_PERIOD-1)/CLK_PERIOD)-1;
// Calculate tXPR time: reset from CKE HIGH to valid command after power-up
// tXPR = (max(5nCK, tRFC(min)+10ns). Add a few (blah, messy) more clock
// cycles because this counter actually starts up before CKE is asserted
// to memory.
localparam TXPR_DELAY_CNT =
(5*CLK_MEM_PERIOD > tRFC+10000) ?
(((5+nCK_PER_CLK-1)/nCK_PER_CLK)-1)+11 :
(((tRFC+10000+CLK_PERIOD-1)/CLK_PERIOD)-1)+11;
// tDLLK/tZQINIT time = 512*tCK = 256*tCLKDIV
localparam TDLLK_TZQINIT_DELAY_CNT = 255;
// TWR values in ns. Both DDR2 and DDR3 have the same value.
// 15000ns/tCK
localparam TWR_CYC = ((15000) % CLK_MEM_PERIOD) ?
(15000/CLK_MEM_PERIOD) + 1 : 15000/CLK_MEM_PERIOD;
// time to wait between consecutive commands in PHY_INIT - this is a
// generic number, and must be large enough to account for worst case
// timing parameter (tRFC - refresh-to-active) across all memory speed
// grades and operating frequencies. Expressed in clk
// (Divided by 4 or Divided by 2) clock cycles.
localparam CNTNEXT_CMD = 7'b1111111;
// Counter values to keep track of which MR register to load during init
// Set value of INIT_CNT_MR_DONE to equal value of counter for last mode
// register configured during initialization.
// NOTE: Reserve more bits for DDR2 - more MR accesses for DDR2 init
localparam INIT_CNT_MR2 = 2'b00;
localparam INIT_CNT_MR3 = 2'b01;
localparam INIT_CNT_MR1 = 2'b10;
localparam INIT_CNT_MR0 = 2'b11;
localparam INIT_CNT_MR_DONE = 2'b11;
// Register chip programmable values for DDR3
// The register chip for the registered DIMM needs to be programmed
// before the initialization of the registered DIMM.
// Address for the control word is in : DBA2, DA2, DA1, DA0
// Data for the control word is in: DBA1 DBA0, DA4, DA3
// The values will be stored in the local param in the following format
// {DBA[2:0], DA[4:0]}
// RC0 is global features control word. Address == 000
localparam REG_RC0 = 8'b00000000;
// RC1 Clock driver enable control word. Enables or disables the four
// output clocks in the register chip. For single rank and dual rank
// two clocks will be enabled and for quad rank all the four clocks
// will be enabled. Address == 000. Data = 0110 for single and dual rank.
// = 0000 for quad rank
localparam REG_RC1 = (RANKS <= 2) ? 8'b00110001 : 8'b00000001;
// RC2 timing control word. Set in 1T timing mode
// Address = 010. Data = 0000
localparam REG_RC2 = 8'b00000010;
// RC3 timing control word. Setting the data to 0000
localparam REG_RC3 = 8'b00000011;
// RC4 timing control work. Setting the data to 0000
localparam REG_RC4 = 8'b00000100;
// RC5 timing control work. Setting the data to 0000
localparam REG_RC5 = 8'b00000101;
// For non-zero AL values
localparam nAL = (AL == "CL-1") ? nCL - 1 : 0;
// Adding the register dimm latency to write latency
localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL;
// Count value to generate pi_phase_locked_err signal
localparam PHASELOCKED_TIMEOUT = (SIM_CAL_OPTION == "NONE") ? 16383 : 1000;
// Timeout interval for detecting error with Traffic Generator
localparam [13:0] TG_TIMER_TIMEOUT
= (SIM_CAL_OPTION == "NONE") ? 14'h3FFF : 14'h0001;
// Master state machine encoding
localparam INIT_IDLE = 6'b000000; //0
localparam INIT_WAIT_CKE_EXIT = 6'b000001; //1
localparam INIT_LOAD_MR = 6'b000010; //2
localparam INIT_LOAD_MR_WAIT = 6'b000011; //3
localparam INIT_ZQCL = 6'b000100; //4
localparam INIT_WAIT_DLLK_ZQINIT = 6'b000101; //5
localparam INIT_WRLVL_START = 6'b000110; //6
localparam INIT_WRLVL_WAIT = 6'b000111; //7
localparam INIT_WRLVL_LOAD_MR = 6'b001000; //8
localparam INIT_WRLVL_LOAD_MR_WAIT = 6'b001001; //9
localparam INIT_WRLVL_LOAD_MR2 = 6'b001010; //A
localparam INIT_WRLVL_LOAD_MR2_WAIT = 6'b001011; //B
localparam INIT_RDLVL_ACT = 6'b001100; //C
localparam INIT_RDLVL_ACT_WAIT = 6'b001101; //D
localparam INIT_RDLVL_STG1_WRITE = 6'b001110; //E
localparam INIT_RDLVL_STG1_WRITE_READ = 6'b001111; //F
localparam INIT_RDLVL_STG1_READ = 6'b010000; //10
localparam INIT_RDLVL_STG2_READ = 6'b010001; //11
localparam INIT_RDLVL_STG2_READ_WAIT = 6'b010010; //12
localparam INIT_PRECHARGE_PREWAIT = 6'b010011; //13
localparam INIT_PRECHARGE = 6'b010100; //14
localparam INIT_PRECHARGE_WAIT = 6'b010101; //15
localparam INIT_DONE = 6'b010110; //16
localparam INIT_DDR2_PRECHARGE = 6'b010111; //17
localparam INIT_DDR2_PRECHARGE_WAIT = 6'b011000; //18
localparam INIT_REFRESH = 6'b011001; //19
localparam INIT_REFRESH_WAIT = 6'b011010; //1A
localparam INIT_REG_WRITE = 6'b011011; //1B
localparam INIT_REG_WRITE_WAIT = 6'b011100; //1C
localparam INIT_DDR2_MULTI_RANK = 6'b011101; //1D
localparam INIT_DDR2_MULTI_RANK_WAIT = 6'b011110; //1E
localparam INIT_WRCAL_ACT = 6'b011111; //1F
localparam INIT_WRCAL_ACT_WAIT = 6'b100000; //20
localparam INIT_WRCAL_WRITE = 6'b100001; //21
localparam INIT_WRCAL_WRITE_READ = 6'b100010; //22
localparam INIT_WRCAL_READ = 6'b100011; //23
localparam INIT_WRCAL_READ_WAIT = 6'b100100; //24
localparam INIT_WRCAL_MULT_READS = 6'b100101; //25
localparam INIT_PI_PHASELOCK_READS = 6'b100110; //26
localparam INIT_MPR_RDEN = 6'b100111; //27
localparam INIT_MPR_WAIT = 6'b101000; //28
localparam INIT_MPR_READ = 6'b101001; //29
localparam INIT_MPR_DISABLE_PREWAIT = 6'b101010; //2A
localparam INIT_MPR_DISABLE = 6'b101011; //2B
localparam INIT_MPR_DISABLE_WAIT = 6'b101100; //2C
localparam INIT_OCLKDELAY_ACT = 6'b101101; //2D
localparam INIT_OCLKDELAY_ACT_WAIT = 6'b101110; //2E
localparam INIT_OCLKDELAY_WRITE = 6'b101111; //2F
localparam INIT_OCLKDELAY_WRITE_WAIT = 6'b110000; //30
localparam INIT_OCLKDELAY_READ = 6'b110001; //31
localparam INIT_OCLKDELAY_READ_WAIT = 6'b110010; //32
localparam INIT_REFRESH_RNK2_WAIT = 6'b110011; //33
integer i, j, k, l, m, n, p, q;
reg pi_dqs_found_all_r;
(* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r1;
(* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r2;
(* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r3;
(* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r4;
reg pi_calib_rank_done_r;
reg [13:0] pi_phaselock_timer;
reg stg1_wr_done;
reg rnk_ref_cnt;
reg pi_dqs_found_done_r1;
reg pi_dqs_found_rank_done_r;
reg read_calib_int;
reg read_calib_r;
reg pi_calib_done_r;
reg pi_calib_done_r1;
reg burst_addr_r;
reg [1:0] chip_cnt_r;
reg [6:0] cnt_cmd_r;
reg cnt_cmd_done_r;
reg cnt_cmd_done_m7_r;
reg [7:0] cnt_dllk_zqinit_r;
reg cnt_dllk_zqinit_done_r;
reg cnt_init_af_done_r;
reg [1:0] cnt_init_af_r;
reg [1:0] cnt_init_data_r;
reg [1:0] cnt_init_mr_r;
reg cnt_init_mr_done_r;
reg cnt_init_pre_wait_done_r;
reg [7:0] cnt_init_pre_wait_r;
reg [9:0] cnt_pwron_ce_r;
reg cnt_pwron_cke_done_r;
reg cnt_pwron_cke_done_r1;
reg [8:0] cnt_pwron_r;
reg cnt_pwron_reset_done_r;
reg cnt_txpr_done_r;
reg [7:0] cnt_txpr_r;
reg ddr2_pre_flag_r;
reg ddr2_refresh_flag_r;
reg ddr3_lm_done_r;
reg [4:0] enable_wrlvl_cnt;
reg init_complete_r;
reg init_complete_r1;
reg init_complete_r2;
(* keep = "true" *) reg init_complete_r_timing;
(* keep = "true" *) reg init_complete_r1_timing;
reg [5:0] init_next_state;
reg [5:0] init_state_r;
reg [5:0] init_state_r1;
wire [15:0] load_mr0;
wire [15:0] load_mr1;
wire [15:0] load_mr2;
wire [15:0] load_mr3;
reg mem_init_done_r;
reg [1:0] mr2_r [0:3];
reg [2:0] mr1_r [0:3];
reg new_burst_r;
reg [15:0] wrcal_start_dly_r;
wire wrcal_start_pre;
reg wrcal_resume_r;
// Only one ODT signal per rank in PHY Control Block
reg [nCK_PER_CLK-1:0] phy_tmp_odt_r;
reg [nCK_PER_CLK-1:0] phy_tmp_odt_r1;
reg [CS_WIDTH*nCS_PER_RANK-1:0] phy_tmp_cs1_r;
reg [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_int_cs_n;
wire prech_done_pre;
reg [15:0] prech_done_dly_r;
reg prech_pending_r;
reg prech_req_posedge_r;
reg prech_req_r;
reg pwron_ce_r;
reg first_rdlvl_pat_r;
reg first_wrcal_pat_r;
reg phy_wrdata_en;
reg phy_wrdata_en_r1;
reg [1:0] wrdata_pat_cnt;
reg [1:0] wrcal_pat_cnt;
reg [ROW_WIDTH-1:0] address_w;
reg [BANK_WIDTH-1:0] bank_w;
reg rdlvl_stg1_done_r1;
reg rdlvl_stg1_start_int;
reg [15:0] rdlvl_start_dly0_r;
reg rdlvl_start_pre;
reg rdlvl_last_byte_done_r;
wire rdlvl_rd;
wire rdlvl_wr;
reg rdlvl_wr_r;
wire rdlvl_wr_rd;
reg [2:0] reg_ctrl_cnt_r;
reg [1:0] tmp_mr2_r [0:3];
reg [2:0] tmp_mr1_r [0:3];
reg wrlvl_done_r;
reg wrlvl_done_r1;
reg wrlvl_rank_done_r1;
reg wrlvl_rank_done_r2;
reg wrlvl_rank_done_r3;
reg wrlvl_rank_done_r4;
reg wrlvl_rank_done_r5;
reg wrlvl_rank_done_r6;
reg wrlvl_rank_done_r7;
reg [2:0] wrlvl_rank_cntr;
reg wrlvl_odt_ctl;
reg wrlvl_odt;
reg wrlvl_active;
reg wrlvl_active_r1;
reg [2:0] num_reads;
reg temp_wrcal_done_r;
reg temp_lmr_done;
reg extend_cal_pat;
reg [13:0] tg_timer;
reg tg_timer_go;
reg cnt_wrcal_rd;
reg [3:0] cnt_wait;
reg [7:0] wrcal_reads;
reg [8:0] stg1_wr_rd_cnt;
reg phy_data_full_r;
reg wr_level_dqs_asrt;
reg wr_level_dqs_asrt_r1;
reg [1:0] dqs_asrt_cnt;
reg [3:0] num_refresh;
wire oclkdelay_calib_start_pre;
reg [15:0] oclkdelay_start_dly_r;
reg [3:0] oclk_wr_cnt;
reg [3:0] wrcal_wr_cnt;
reg wrlvl_final_r;
reg prbs_rdlvl_done_r1;
reg prbs_last_byte_done_r;
reg phy_if_empty_r;
reg wrcal_final_chk;
//***************************************************************************
// Debug
//***************************************************************************
//synthesis translate_off
always @(posedge mem_init_done_r) begin
if (!rst)
$display ("PHY_INIT: Memory Initialization completed at %t", $time);
end
always @(posedge wrlvl_done) begin
if (!rst && (WRLVL == "ON"))
$display ("PHY_INIT: Write Leveling completed at %t", $time);
end
always @(posedge rdlvl_stg1_done) begin
if (!rst)
$display ("PHY_INIT: Read Leveling Stage 1 completed at %t", $time);
end
always @(posedge mpr_rdlvl_done) begin
if (!rst)
$display ("PHY_INIT: MPR Read Leveling completed at %t", $time);
end
always @(posedge oclkdelay_calib_done) begin
if (!rst)
$display ("PHY_INIT: OCLKDELAY calibration completed at %t", $time);
end
always @(posedge pi_calib_done_r1) begin
if (!rst)
$display ("PHY_INIT: Phaser_In Phase Locked at %t", $time);
end
always @(posedge pi_dqs_found_done) begin
if (!rst)
$display ("PHY_INIT: Phaser_In DQSFOUND completed at %t", $time);
end
always @(posedge wrcal_done) begin
if (!rst && (WRLVL == "ON"))
$display ("PHY_INIT: Write Calibration completed at %t", $time);
end
//synthesis translate_on
assign dbg_phy_init[5:0] = init_state_r;
//***************************************************************************
// DQS count to be sent to hard PHY during Phaser_IN Phase Locking stage
//***************************************************************************
// assign pi_phaselock_calib_cnt = dqs_cnt_r;
assign pi_calib_done = pi_calib_done_r1;
always @(posedge clk) begin
if (rst)
wrcal_final_chk <= #TCQ 1'b0;
else if ((init_next_state == INIT_WRCAL_ACT) && wrcal_done &&
(DRAM_TYPE == "DDR3"))
wrcal_final_chk <= #TCQ 1'b1;
end
always @(posedge clk) begin
rdlvl_stg1_done_r1 <= #TCQ rdlvl_stg1_done;
prbs_rdlvl_done_r1 <= #TCQ prbs_rdlvl_done;
wrcal_resume_r <= #TCQ wrcal_resume;
wrcal_sanity_chk <= #TCQ wrcal_final_chk;
end
always @(posedge clk) begin
if (rst)
mpr_end_if_reset <= #TCQ 1'b0;
else if (mpr_last_byte_done && (num_refresh != 'd0))
mpr_end_if_reset <= #TCQ 1'b1;
else
mpr_end_if_reset <= #TCQ 1'b0;
end
// Siganl to mask memory model error for Invalid latching edge
always @(posedge clk)
if (rst)
calib_writes <= #TCQ 1'b0;
else if ((init_state_r == INIT_OCLKDELAY_WRITE) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_RDLVL_STG1_WRITE_READ) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE_READ))
calib_writes <= #TCQ 1'b1;
else
calib_writes <= #TCQ 1'b0;
always @(posedge clk)
if (rst)
wrcal_rd_wait <= #TCQ 1'b0;
else if (init_state_r == INIT_WRCAL_READ_WAIT)
wrcal_rd_wait <= #TCQ 1'b1;
else
wrcal_rd_wait <= #TCQ 1'b0;
//***************************************************************************
// Signal PHY completion when calibration is finished
// Signal assertion is delayed by four clock cycles to account for the
// multi cycle path constraint to (phy_init_data_sel) signal.
//***************************************************************************
always @(posedge clk)
if (rst) begin
init_complete_r <= #TCQ 1'b0;
init_complete_r_timing <= #TCQ 1'b0;
init_complete_r1 <= #TCQ 1'b0;
init_complete_r1_timing <= #TCQ 1'b0;
init_complete_r2 <= #TCQ 1'b0;
init_calib_complete <= #TCQ 1'b0;
end else begin
if (init_state_r == INIT_DONE) begin
init_complete_r <= #TCQ 1'b1;
init_complete_r_timing <= #TCQ 1'b1;
end
init_complete_r1 <= #TCQ init_complete_r;
init_complete_r1_timing <= #TCQ init_complete_r_timing;
init_complete_r2 <= #TCQ init_complete_r1;
init_calib_complete <= #TCQ init_complete_r2;
end
//***************************************************************************
// Instantiate FF for the phy_init_data_sel signal. A multi cycle path
// constraint will be assigned to this signal. This signal will only be
// used within the PHY
//***************************************************************************
// FDRSE u_ff_phy_init_data_sel
// (
// .Q (phy_init_data_sel),
// .C (clk),
// .CE (1'b1),
// .D (init_complete_r),
// .R (1'b0),
// .S (1'b0)
// ) /* synthesis syn_preserve=1 */
// /* synthesis syn_replicate = 0 */;
//***************************************************************************
// Mode register programming
//***************************************************************************
//*****************************************************************
// DDR3 Load mode reg0
// Mode Register (MR0):
// [15:13] - unused - 000
// [12] - Precharge Power-down DLL usage - 0 (DLL frozen, slow-exit),
// 1 (DLL maintained)
// [11:9] - write recovery for Auto Precharge (tWR/tCK = 6)
// [8] - DLL reset - 0 or 1
// [7] - Test Mode - 0 (normal)
// [6:4],[2] - CAS latency - CAS_LAT
// [3] - Burst Type - BURST_TYPE
// [1:0] - Burst Length - BURST_LEN
// DDR2 Load mode register
// Mode Register (MR):
// [15:14] - unused - 00
// [13] - reserved - 0
// [12] - Power-down mode - 0 (normal)
// [11:9] - write recovery - write recovery for Auto Precharge
// (tWR/tCK = 6)
// [8] - DLL reset - 0 or 1
// [7] - Test Mode - 0 (normal)
// [6:4] - CAS latency - CAS_LAT
// [3] - Burst Type - BURST_TYPE
// [2:0] - Burst Length - BURST_LEN
//*****************************************************************
generate
if(DRAM_TYPE == "DDR3") begin: gen_load_mr0_DDR3
assign load_mr0[1:0] = (BURST_MODE == "8") ? 2'b00 :
(BURST_MODE == "OTF") ? 2'b01 :
(BURST_MODE == "4") ? 2'b10 : 2'b11;
assign load_mr0[2] = (nCL >= 12) ? 1'b1 : 1'b0; // LSb of CAS latency
assign load_mr0[3] = (BURST_TYPE == "SEQ") ? 1'b0 : 1'b1;
assign load_mr0[6:4] = ((nCL == 5) || (nCL == 13)) ? 3'b001 :
((nCL == 6) || (nCL == 14)) ? 3'b010 :
(nCL == 7) ? 3'b011 :
(nCL == 8) ? 3'b100 :
(nCL == 9) ? 3'b101 :
(nCL == 10) ? 3'b110 :
(nCL == 11) ? 3'b111 :
(nCL == 12) ? 3'b000 : 3'b111;
assign load_mr0[7] = 1'b0;
assign load_mr0[8] = 1'b1; // Reset DLL (init only)
assign load_mr0[11:9] = (TWR_CYC == 5) ? 3'b001 :
(TWR_CYC == 6) ? 3'b010 :
(TWR_CYC == 7) ? 3'b011 :
(TWR_CYC == 8) ? 3'b100 :
(TWR_CYC == 9) ? 3'b101 :
(TWR_CYC == 10) ? 3'b101 :
(TWR_CYC == 11) ? 3'b110 :
(TWR_CYC == 12) ? 3'b110 :
(TWR_CYC == 13) ? 3'b111 :
(TWR_CYC == 14) ? 3'b111 :
(TWR_CYC == 15) ? 3'b000 :
(TWR_CYC == 16) ? 3'b000 : 3'b010;
assign load_mr0[12] = 1'b0; // Precharge Power-Down DLL 'slow-exit'
assign load_mr0[15:13] = 3'b000;
end else if (DRAM_TYPE == "DDR2") begin: gen_load_mr0_DDR2 // block: gen
assign load_mr0[2:0] = (BURST_MODE == "8") ? 3'b011 :
(BURST_MODE == "4") ? 3'b010 : 3'b111;
assign load_mr0[3] = (BURST_TYPE == "SEQ") ? 1'b0 : 1'b1;
assign load_mr0[6:4] = (nCL == 3) ? 3'b011 :
(nCL == 4) ? 3'b100 :
(nCL == 5) ? 3'b101 :
(nCL == 6) ? 3'b110 : 3'b111;
assign load_mr0[7] = 1'b0;
assign load_mr0[8] = 1'b1; // Reset DLL (init only)
assign load_mr0[11:9] = (TWR_CYC == 2) ? 3'b001 :
(TWR_CYC == 3) ? 3'b010 :
(TWR_CYC == 4) ? 3'b011 :
(TWR_CYC == 5) ? 3'b100 :
(TWR_CYC == 6) ? 3'b101 : 3'b010;
assign load_mr0[15:12]= 4'b0000; // Reserved
end
endgenerate
//*****************************************************************
// DDR3 Load mode reg1
// Mode Register (MR1):
// [15:13] - unused - 00
// [12] - output enable - 0 (enabled for DQ, DQS, DQS#)
// [11] - TDQS enable - 0 (TDQS disabled and DM enabled)
// [10] - reserved - 0 (must be '0')
// [9] - RTT[2] - 0
// [8] - reserved - 0 (must be '0')
// [7] - write leveling - 0 (disabled), 1 (enabled)
// [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50)
// [5] - Output driver impedance[1] - 0 (RZQ/6 and RZQ/7)
// [4:3] - Additive CAS - ADDITIVE_CAS
// [2] - RTT[0]
// [1] - Output driver impedance[0] - 0(RZQ/6), or 1 (RZQ/7)
// [0] - DLL enable - 0 (normal)
// DDR2 ext mode register
// Extended Mode Register (MR):
// [15:14] - unused - 00
// [13] - reserved - 0
// [12] - output enable - 0 (enabled)
// [11] - RDQS enable - 0 (disabled)
// [10] - DQS# enable - 0 (enabled)
// [9:7] - OCD Program - 111 or 000 (first 111, then 000 during init)
// [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50)
// [5:3] - Additive CAS - ADDITIVE_CAS
// [2] - RTT[0]
// [1] - Output drive - REDUCE_DRV (= 0(full), = 1 (reduced)
// [0] - DLL enable - 0 (normal)
//*****************************************************************
generate
if(DRAM_TYPE == "DDR3") begin: gen_load_mr1_DDR3
assign load_mr1[0] = 1'b0; // DLL enabled during Imitialization
assign load_mr1[1] = (OUTPUT_DRV == "LOW") ? 1'b0 : 1'b1;
assign load_mr1[2] = ((RTT_NOM_int == "30") || (RTT_NOM_int == "40") ||
(RTT_NOM_int == "60")) ? 1'b1 : 1'b0;
assign load_mr1[4:3] = (AL == "0") ? 2'b00 :
(AL == "CL-1") ? 2'b01 :
(AL == "CL-2") ? 2'b10 : 2'b11;
assign load_mr1[5] = 1'b0;
assign load_mr1[6] = ((RTT_NOM_int == "40") || (RTT_NOM_int == "120")) ?
1'b1 : 1'b0;
assign load_mr1[7] = 1'b0; // Enable write lvl after init sequence
assign load_mr1[8] = 1'b0;
assign load_mr1[9] = ((RTT_NOM_int == "20") || (RTT_NOM_int == "30")) ?
1'b1 : 1'b0;
assign load_mr1[10] = 1'b0;
assign load_mr1[15:11] = 5'b00000;
end else if (DRAM_TYPE == "DDR2") begin: gen_load_mr1_DDR2
assign load_mr1[0] = 1'b0; // DLL enabled during Imitialization
assign load_mr1[1] = (OUTPUT_DRV == "LOW") ? 1'b1 : 1'b0;
assign load_mr1[2] = ((RTT_NOM_int == "75") || (RTT_NOM_int == "50")) ?
1'b1 : 1'b0;
assign load_mr1[5:3] = (AL == "0") ? 3'b000 :
(AL == "1") ? 3'b001 :
(AL == "2") ? 3'b010 :
(AL == "3") ? 3'b011 :
(AL == "4") ? 3'b100 : 3'b111;
assign load_mr1[6] = ((RTT_NOM_int == "50") ||
(RTT_NOM_int == "150")) ? 1'b1 : 1'b0;
assign load_mr1[9:7] = 3'b000;
assign load_mr1[10] = (DDR2_DQSN_ENABLE == "YES") ? 1'b0 : 1'b1;
assign load_mr1[15:11] = 5'b00000;
end
endgenerate
//*****************************************************************
// DDR3 Load mode reg2
// Mode Register (MR2):
// [15:11] - unused - 00
// [10:9] - RTT_WR - 00 (Dynamic ODT off)
// [8] - reserved - 0 (must be '0')
// [7] - self-refresh temperature range -
// 0 (normal), 1 (extended)
// [6] - Auto Self-Refresh - 0 (manual), 1(auto)
// [5:3] - CAS Write Latency (CWL) -
// 000 (5 for 400 MHz device),
// 001 (6 for 400 MHz to 533 MHz devices),
// 010 (7 for 533 MHz to 667 MHz devices),
// 011 (8 for 667 MHz to 800 MHz)
// [2:0] - Partial Array Self-Refresh (Optional) -
// 000 (full array)
// Not used for DDR2
//*****************************************************************
generate
if(DRAM_TYPE == "DDR3") begin: gen_load_mr2_DDR3
assign load_mr2[2:0] = 3'b000;
assign load_mr2[5:3] = (nCWL == 5) ? 3'b000 :
(nCWL == 6) ? 3'b001 :
(nCWL == 7) ? 3'b010 :
(nCWL == 8) ? 3'b011 :
(nCWL == 9) ? 3'b100 :
(nCWL == 10) ? 3'b101 :
(nCWL == 11) ? 3'b110 : 3'b111;
assign load_mr2[6] = 1'b0;
assign load_mr2[7] = 1'b0;
assign load_mr2[8] = 1'b0;
// Dynamic ODT disabled
assign load_mr2[10:9] = 2'b00;
assign load_mr2[15:11] = 5'b00000;
end else begin: gen_load_mr2_DDR2
assign load_mr2[15:0] = 16'd0;
end
endgenerate
//*****************************************************************
// DDR3 Load mode reg3
// Mode Register (MR3):
// [15:3] - unused - All zeros
// [2] - MPR Operation - 0(normal operation), 1(data flow from MPR)
// [1:0] - MPR location - 00 (Predefined pattern)
//*****************************************************************
assign load_mr3[1:0] = 2'b00;
assign load_mr3[2] = 1'b0;
assign load_mr3[15:3] = 13'b0000000000000;
// For multi-rank systems the rank being accessed during writes in
// Read Leveling must be sent to phy_write for the bitslip logic
assign calib_rank_cnt = chip_cnt_r;
//***************************************************************************
// Logic to begin initial calibration, and to handle precharge requests
// during read-leveling (to avoid tRAS violations if individual read
// levelling calibration stages take more than max{tRAS) to complete).
//***************************************************************************
// Assert when readback for each stage of read-leveling begins. However,
// note this indicates only when the read command is issued and when
// Phaser_IN has phase aligned FREQ_REF clock to read DQS. It does not
// indicate when the read data is present on the bus (when this happens
// after the read command is issued depends on CAS LATENCY) - there will
// need to be some delay before valid data is present on the bus.
// assign rdlvl_start_pre = (init_state_r == INIT_PI_PHASELOCK_READS);
// Assert when read back for oclkdelay calibration begins
assign oclkdelay_calib_start_pre = (init_state_r == INIT_OCLKDELAY_READ);
// Assert when read back for write calibration begins
assign wrcal_start_pre = (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS);
// Common precharge signal done signal - pulses only when there has been
// a precharge issued as a result of a PRECH_REQ pulse. Note also a common
// PRECH_DONE signal is used for all blocks
assign prech_done_pre = (((init_state_r == INIT_RDLVL_STG1_READ) ||
((rdlvl_last_byte_done_r || prbs_last_byte_done_r) && (init_state_r == INIT_RDLVL_ACT_WAIT) && cnt_cmd_done_r) ||
(dqs_found_prech_req && (init_state_r == INIT_RDLVL_ACT_WAIT)) ||
(init_state_r == INIT_MPR_RDEN) ||
((init_state_r == INIT_WRCAL_ACT_WAIT) && cnt_cmd_done_r) ||
((init_state_r == INIT_OCLKDELAY_ACT_WAIT) && cnt_cmd_done_r) ||
(wrlvl_final && (init_state_r == INIT_REFRESH_WAIT) && cnt_cmd_done_r && ~oclkdelay_calib_done)) &&
prech_pending_r &&
!prech_req_posedge_r);
always @(posedge clk)
if (rst)
pi_phaselock_start <= #TCQ 1'b0;
else if (init_state_r == INIT_PI_PHASELOCK_READS)
pi_phaselock_start <= #TCQ 1'b1;
// Delay start of each calibration by 16 clock cycles to ensure that when
// calibration logic begins, read data is already appearing on the bus.
// Each circuit should synthesize using an SRL16. Assume that reset is
// long enough to clear contents of SRL16.
always @(posedge clk) begin
rdlvl_last_byte_done_r <= #TCQ rdlvl_last_byte_done;
prbs_last_byte_done_r <= #TCQ prbs_last_byte_done;
rdlvl_start_dly0_r <= #TCQ {rdlvl_start_dly0_r[14:0],
rdlvl_start_pre};
wrcal_start_dly_r <= #TCQ {wrcal_start_dly_r[14:0],
wrcal_start_pre};
oclkdelay_start_dly_r <= #TCQ {oclkdelay_start_dly_r[14:0],
oclkdelay_calib_start_pre};
prech_done_dly_r <= #TCQ {prech_done_dly_r[14:0],
prech_done_pre};
end
always @(posedge clk)
prech_done <= #TCQ prech_done_dly_r[15];
always @(posedge clk)
if (rst)
mpr_rdlvl_start <= #TCQ 1'b0;
else if (pi_dqs_found_done &&
(init_state_r == INIT_MPR_READ))
mpr_rdlvl_start <= #TCQ 1'b1;
always @(posedge clk)
phy_if_empty_r <= #TCQ phy_if_empty;
always @(posedge clk)
if (rst || (phy_if_empty_r && prbs_rdlvl_prech_req) ||
((stg1_wr_rd_cnt == 'd1) && ~stg1_wr_done) || prbs_rdlvl_done)
prbs_gen_clk_en <= #TCQ 1'b0;
else if ((~phy_if_empty_r && rdlvl_stg1_done_r1 && ~prbs_rdlvl_done) ||
((init_state_r == INIT_RDLVL_ACT_WAIT) && rdlvl_stg1_done_r1 && (cnt_cmd_r == 'd0)))
prbs_gen_clk_en <= #TCQ 1'b1;
generate
if (RANKS < 2) begin
always @(posedge clk)
if (rst) begin
rdlvl_stg1_start <= #TCQ 1'b0;
rdlvl_stg1_start_int <= #TCQ 1'b0;
rdlvl_start_pre <= #TCQ 1'b0;
prbs_rdlvl_start <= #TCQ 1'b0;
end else begin
if (pi_dqs_found_done && cnt_cmd_done_r &&
(init_state_r == INIT_RDLVL_ACT_WAIT))
rdlvl_stg1_start_int <= #TCQ 1'b1;
if (pi_dqs_found_done &&
(init_state_r == INIT_RDLVL_STG1_READ))begin
rdlvl_start_pre <= #TCQ 1'b1;
rdlvl_stg1_start <= #TCQ rdlvl_start_dly0_r[14];
end
if (pi_dqs_found_done && rdlvl_stg1_done &&
(init_state_r == INIT_RDLVL_STG1_READ) && (WRLVL == "ON")) begin
prbs_rdlvl_start <= #TCQ 1'b1;
end
end
end else begin
always @(posedge clk)
if (rst || rdlvl_stg1_rank_done) begin
rdlvl_stg1_start <= #TCQ 1'b0;
rdlvl_stg1_start_int <= #TCQ 1'b0;
rdlvl_start_pre <= #TCQ 1'b0;
prbs_rdlvl_start <= #TCQ 1'b0;
end else begin
if (pi_dqs_found_done && cnt_cmd_done_r &&
(init_state_r == INIT_RDLVL_ACT_WAIT))
rdlvl_stg1_start_int <= #TCQ 1'b1;
if (pi_dqs_found_done &&
(init_state_r == INIT_RDLVL_STG1_READ))begin
rdlvl_start_pre <= #TCQ 1'b1;
rdlvl_stg1_start <= #TCQ rdlvl_start_dly0_r[14];
end
if (pi_dqs_found_done && rdlvl_stg1_done &&
(init_state_r == INIT_RDLVL_STG1_READ) && (WRLVL == "ON")) begin
prbs_rdlvl_start <= #TCQ 1'b1;
end
end
end
endgenerate
always @(posedge clk) begin
if (rst || dqsfound_retry || wrlvl_byte_redo) begin
pi_dqs_found_start <= #TCQ 1'b0;
wrcal_start <= #TCQ 1'b0;
end else begin
if (!pi_dqs_found_done && init_state_r == INIT_RDLVL_STG2_READ)
pi_dqs_found_start <= #TCQ 1'b1;
if (wrcal_start_dly_r[5])
wrcal_start <= #TCQ 1'b1;
end
end // else: !if(rst)
always @(posedge clk)
if (rst)
oclkdelay_calib_start <= #TCQ 1'b0;
else if (oclkdelay_start_dly_r[5])
oclkdelay_calib_start <= #TCQ 1'b1;
always @(posedge clk)
if (rst)
pi_dqs_found_done_r1 <= #TCQ 1'b0;
else
pi_dqs_found_done_r1 <= #TCQ pi_dqs_found_done;
always @(posedge clk)
wrlvl_final_r <= #TCQ wrlvl_final;
// Reset IN_FIFO after final write leveling to make sure the FIFO
// pointers are initialized
always @(posedge clk)
if (rst || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_REFRESH))
wrlvl_final_if_rst <= #TCQ 1'b0;
else if (wrlvl_done_r && //(wrlvl_final_r && wrlvl_done_r &&
(init_state_r == INIT_WRLVL_LOAD_MR2))
wrlvl_final_if_rst <= #TCQ 1'b1;
// Constantly enable DQS while write leveling is enabled in the memory
// This is more to get rid of warnings in simulation, can later change
// this code to only enable WRLVL_ACTIVE when WRLVL_START is asserted
always @(posedge clk)
if (rst ||
((init_state_r1 != INIT_WRLVL_START) &&
(init_state_r == INIT_WRLVL_START)))
wrlvl_odt_ctl <= #TCQ 1'b0;
else if (wrlvl_rank_done && ~wrlvl_rank_done_r1)
wrlvl_odt_ctl <= #TCQ 1'b1;
generate
if (nCK_PER_CLK == 4) begin: en_cnt_div4
always @ (posedge clk)
if (rst)
enable_wrlvl_cnt <= #TCQ 5'd0;
else if ((init_state_r == INIT_WRLVL_START) ||
(wrlvl_odt && (enable_wrlvl_cnt == 5'd0)))
enable_wrlvl_cnt <= #TCQ 5'd12;
else if ((enable_wrlvl_cnt > 5'd0) && ~(phy_ctl_full || phy_cmd_full))
enable_wrlvl_cnt <= #TCQ enable_wrlvl_cnt - 1;
// ODT stays asserted as long as write_calib
// signal is asserted
always @(posedge clk)
if (rst || wrlvl_odt_ctl)
wrlvl_odt <= #TCQ 1'b0;
else if (enable_wrlvl_cnt == 5'd1)
wrlvl_odt <= #TCQ 1'b1;
end else begin: en_cnt_div2
always @ (posedge clk)
if (rst)
enable_wrlvl_cnt <= #TCQ 5'd0;
else if ((init_state_r == INIT_WRLVL_START) ||
(wrlvl_odt && (enable_wrlvl_cnt == 5'd0)))
enable_wrlvl_cnt <= #TCQ 5'd21;
else if ((enable_wrlvl_cnt > 5'd0) && ~(phy_ctl_full || phy_cmd_full))
enable_wrlvl_cnt <= #TCQ enable_wrlvl_cnt - 1;
// ODT stays asserted as long as write_calib
// signal is asserted
always @(posedge clk)
if (rst || wrlvl_odt_ctl)
wrlvl_odt <= #TCQ 1'b0;
else if (enable_wrlvl_cnt == 5'd1)
wrlvl_odt <= #TCQ 1'b1;
end
endgenerate
always @(posedge clk)
if (rst || wrlvl_rank_done || done_dqs_tap_inc)
wrlvl_active <= #TCQ 1'b0;
else if ((enable_wrlvl_cnt == 5'd1) && wrlvl_odt && !wrlvl_active)
wrlvl_active <= #TCQ 1'b1;
// signal used to assert DQS for write leveling.
// the DQS will be asserted once every 16 clock cycles.
always @(posedge clk)begin
if(rst || (enable_wrlvl_cnt != 5'd1)) begin
wr_level_dqs_asrt <= #TCQ 1'd0;
end else if ((enable_wrlvl_cnt == 5'd1) && (wrlvl_active_r1)) begin
wr_level_dqs_asrt <= #TCQ 1'd1;
end
end
always @ (posedge clk) begin
if (rst || (wrlvl_done_r && ~wrlvl_done_r1))
dqs_asrt_cnt <= #TCQ 2'd0;
else if (wr_level_dqs_asrt && dqs_asrt_cnt != 2'd3)
dqs_asrt_cnt <= #TCQ (dqs_asrt_cnt + 1);
end
always @ (posedge clk) begin
if (rst || ~wrlvl_active)
wr_lvl_start <= #TCQ 1'd0;
else if (dqs_asrt_cnt == 2'd3)
wr_lvl_start <= #TCQ 1'd1;
end
always @(posedge clk) begin
if (rst)
wl_sm_start <= #TCQ 1'b0;
else
wl_sm_start <= #TCQ wr_level_dqs_asrt_r1;
end
always @(posedge clk) begin
wrlvl_active_r1 <= #TCQ wrlvl_active;
wr_level_dqs_asrt_r1 <= #TCQ wr_level_dqs_asrt;
wrlvl_done_r <= #TCQ wrlvl_done;
wrlvl_done_r1 <= #TCQ wrlvl_done_r;
wrlvl_rank_done_r1 <= #TCQ wrlvl_rank_done;
wrlvl_rank_done_r2 <= #TCQ wrlvl_rank_done_r1;
wrlvl_rank_done_r3 <= #TCQ wrlvl_rank_done_r2;
wrlvl_rank_done_r4 <= #TCQ wrlvl_rank_done_r3;
wrlvl_rank_done_r5 <= #TCQ wrlvl_rank_done_r4;
wrlvl_rank_done_r6 <= #TCQ wrlvl_rank_done_r5;
wrlvl_rank_done_r7 <= #TCQ wrlvl_rank_done_r6;
end
always @ (posedge clk) begin
//if (rst)
wrlvl_rank_cntr <= #TCQ 3'd0;
//else if (wrlvl_rank_done)
// wrlvl_rank_cntr <= #TCQ wrlvl_rank_cntr + 1'b1;
end
//*****************************************************************
// Precharge request logic - those calibration logic blocks
// that require greater than tRAS(max) to finish must break up
// their calibration into smaller units of time, with precharges
// issued in between. This is done using the XXX_PRECH_REQ and
// PRECH_DONE handshaking between PHY_INIT and those blocks
//*****************************************************************
// Shared request from multiple sources
assign prech_req = oclk_prech_req | rdlvl_prech_req | wrcal_prech_req | prbs_rdlvl_prech_req |
(dqs_found_prech_req & (init_state_r == INIT_RDLVL_STG2_READ_WAIT));
// Handshaking logic to force precharge during read leveling, and to
// notify read leveling logic when precharge has been initiated and
// it's okay to proceed with leveling again
always @(posedge clk)
if (rst) begin
prech_req_r <= #TCQ 1'b0;
prech_req_posedge_r <= #TCQ 1'b0;
prech_pending_r <= #TCQ 1'b0;
end else begin
prech_req_r <= #TCQ prech_req;
prech_req_posedge_r <= #TCQ prech_req & ~prech_req_r;
if (prech_req_posedge_r)
prech_pending_r <= #TCQ 1'b1;
// Clear after we've finished with the precharge and have
// returned to issuing read leveling calibration reads
else if (prech_done_pre)
prech_pending_r <= #TCQ 1'b0;
end
//***************************************************************************
// Various timing counters
//***************************************************************************
//*****************************************************************
// Generic delay for various states that require it (e.g. for turnaround
// between read and write). Make this a sufficiently large number of clock
// cycles to cover all possible frequencies and memory components)
// Requirements for this counter:
// 1. Greater than tMRD
// 2. tRFC (refresh-active) for DDR2
// 3. (list the other requirements, slacker...)
//*****************************************************************
always @(posedge clk) begin
case (init_state_r)
INIT_LOAD_MR_WAIT,
INIT_WRLVL_LOAD_MR_WAIT,
INIT_WRLVL_LOAD_MR2_WAIT,
INIT_MPR_WAIT,
INIT_MPR_DISABLE_PREWAIT,
INIT_MPR_DISABLE_WAIT,
INIT_OCLKDELAY_ACT_WAIT,
INIT_OCLKDELAY_WRITE_WAIT,
INIT_RDLVL_ACT_WAIT,
INIT_RDLVL_STG1_WRITE_READ,
INIT_RDLVL_STG2_READ_WAIT,
INIT_WRCAL_ACT_WAIT,
INIT_WRCAL_WRITE_READ,
INIT_WRCAL_READ_WAIT,
INIT_PRECHARGE_PREWAIT,
INIT_PRECHARGE_WAIT,
INIT_DDR2_PRECHARGE_WAIT,
INIT_REG_WRITE_WAIT,
INIT_REFRESH_WAIT,
INIT_REFRESH_RNK2_WAIT: begin
if (phy_ctl_full || phy_cmd_full)
cnt_cmd_r <= #TCQ cnt_cmd_r;
else
cnt_cmd_r <= #TCQ cnt_cmd_r + 1;
end
INIT_WRLVL_WAIT:
cnt_cmd_r <= #TCQ 'b0;
default:
cnt_cmd_r <= #TCQ 'b0;
endcase
end
// pulse when count reaches terminal count
always @(posedge clk)
cnt_cmd_done_r <= #TCQ (cnt_cmd_r == CNTNEXT_CMD);
// For ODT deassertion - hold throughout post read/write wait stage, but
// deassert before next command. The post read/write stage is very long, so
// we simply address the longest case here plus some margin.
always @(posedge clk)
cnt_cmd_done_m7_r <= #TCQ (cnt_cmd_r == (CNTNEXT_CMD - 7));
//************************************************************************
// Added to support PO fine delay inc when TG errors
always @(posedge clk) begin
case (init_state_r)
INIT_WRCAL_READ_WAIT: begin
if (phy_ctl_full || phy_cmd_full)
cnt_wait <= #TCQ cnt_wait;
else
cnt_wait <= #TCQ cnt_wait + 1;
end
default:
cnt_wait <= #TCQ 'b0;
endcase
end
always @(posedge clk)
cnt_wrcal_rd <= #TCQ (cnt_wait == 'd4);
always @(posedge clk) begin
if (rst || ~temp_wrcal_done)
temp_lmr_done <= #TCQ 1'b0;
else if (temp_wrcal_done && (init_state_r == INIT_LOAD_MR))
temp_lmr_done <= #TCQ 1'b1;
end
always @(posedge clk)
temp_wrcal_done_r <= #TCQ temp_wrcal_done;
always @(posedge clk)
if (rst) begin
tg_timer_go <= #TCQ 1'b0;
end else if ((PRE_REV3ES == "ON") && temp_wrcal_done && temp_lmr_done &&
(init_state_r == INIT_WRCAL_READ_WAIT)) begin
tg_timer_go <= #TCQ 1'b1;
end else begin
tg_timer_go <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || (temp_wrcal_done && ~temp_wrcal_done_r) ||
(init_state_r == INIT_PRECHARGE_PREWAIT))
tg_timer <= #TCQ 'd0;
else if ((pi_phaselock_timer == PHASELOCKED_TIMEOUT) &&
tg_timer_go &&
(tg_timer != TG_TIMER_TIMEOUT))
tg_timer <= #TCQ tg_timer + 1;
end
always @(posedge clk) begin
if (rst)
tg_timer_done <= #TCQ 1'b0;
else if (tg_timer == TG_TIMER_TIMEOUT)
tg_timer_done <= #TCQ 1'b1;
else
tg_timer_done <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst)
no_rst_tg_mc <= #TCQ 1'b0;
else if ((init_state_r == INIT_WRCAL_ACT) && wrcal_read_req)
no_rst_tg_mc <= #TCQ 1'b1;
else
no_rst_tg_mc <= #TCQ 1'b0;
end
//************************************************************************
always @(posedge clk) begin
if (rst)
detect_pi_found_dqs <= #TCQ 1'b0;
else if ((cnt_cmd_r == 7'b0111111) &&
(init_state_r == INIT_RDLVL_STG2_READ_WAIT))
detect_pi_found_dqs <= #TCQ 1'b1;
else
detect_pi_found_dqs <= #TCQ 1'b0;
end
//*****************************************************************
// Initial delay after power-on for RESET, CKE
// NOTE: Could reduce power consumption by turning off these counters
// after initial power-up (at expense of more logic)
// NOTE: Likely can combine multiple counters into single counter
//*****************************************************************
// Create divided by 1024 version of clock
always @(posedge clk)
if (rst) begin
cnt_pwron_ce_r <= #TCQ 10'h000;
pwron_ce_r <= #TCQ 1'b0;
end else begin
cnt_pwron_ce_r <= #TCQ cnt_pwron_ce_r + 1;
pwron_ce_r <= #TCQ (cnt_pwron_ce_r == 10'h3FF);
end
// "Main" power-on counter - ticks every CLKDIV/1024 cycles
always @(posedge clk)
if (rst)
cnt_pwron_r <= #TCQ 'b0;
else if (pwron_ce_r)
cnt_pwron_r <= #TCQ cnt_pwron_r + 1;
always @(posedge clk)
if (rst || ~phy_ctl_ready) begin
cnt_pwron_reset_done_r <= #TCQ 1'b0;
cnt_pwron_cke_done_r <= #TCQ 1'b0;
end else begin
// skip power-up count for simulation purposes only
if ((SIM_INIT_OPTION == "SKIP_PU_DLY") ||
(SIM_INIT_OPTION == "SKIP_INIT")) begin
cnt_pwron_reset_done_r <= #TCQ 1'b1;
cnt_pwron_cke_done_r <= #TCQ 1'b1;
end else begin
// otherwise, create latched version of done signal for RESET, CKE
if (DRAM_TYPE == "DDR3") begin
if (!cnt_pwron_reset_done_r)
cnt_pwron_reset_done_r
<= #TCQ (cnt_pwron_r == PWRON_RESET_DELAY_CNT);
if (!cnt_pwron_cke_done_r)
cnt_pwron_cke_done_r
<= #TCQ (cnt_pwron_r == PWRON_CKE_DELAY_CNT);
end else begin // DDR2
cnt_pwron_reset_done_r <= #TCQ 1'b1; // not needed
if (!cnt_pwron_cke_done_r)
cnt_pwron_cke_done_r
<= #TCQ (cnt_pwron_r == PWRON_CKE_DELAY_CNT);
end
end
end // else: !if(rst || ~phy_ctl_ready)
always @(posedge clk)
cnt_pwron_cke_done_r1 <= #TCQ cnt_pwron_cke_done_r;
// Keep RESET asserted and CKE deasserted until after power-on delay
always @(posedge clk or posedge rst) begin
if (rst)
phy_reset_n <= #TCQ 1'b0;
else
phy_reset_n <= #TCQ cnt_pwron_reset_done_r;
// phy_cke <= #TCQ {CKE_WIDTH{cnt_pwron_cke_done_r}};
end
//*****************************************************************
// Counter for tXPR (pronouned "Tax-Payer") - wait time after
// CKE deassertion before first MRS command can be asserted
//*****************************************************************
always @(posedge clk)
if (!cnt_pwron_cke_done_r) begin
cnt_txpr_r <= #TCQ 'b0;
cnt_txpr_done_r <= #TCQ 1'b0;
end else begin
cnt_txpr_r <= #TCQ cnt_txpr_r + 1;
if (!cnt_txpr_done_r)
cnt_txpr_done_r <= #TCQ (cnt_txpr_r == TXPR_DELAY_CNT);
end
//*****************************************************************
// Counter for the initial 400ns wait for issuing precharge all
// command after CKE assertion. Only for DDR2.
//*****************************************************************
always @(posedge clk)
if (!cnt_pwron_cke_done_r) begin
cnt_init_pre_wait_r <= #TCQ 'b0;
cnt_init_pre_wait_done_r <= #TCQ 1'b0;
end else begin
cnt_init_pre_wait_r <= #TCQ cnt_init_pre_wait_r + 1;
if (!cnt_init_pre_wait_done_r)
cnt_init_pre_wait_done_r
<= #TCQ (cnt_init_pre_wait_r >= DDR2_INIT_PRE_CNT);
end
//*****************************************************************
// Wait for both DLL to lock (tDLLK) and ZQ calibration to finish
// (tZQINIT). Both take the same amount of time (512*tCK)
//*****************************************************************
always @(posedge clk)
if (init_state_r == INIT_ZQCL) begin
cnt_dllk_zqinit_r <= #TCQ 'b0;
cnt_dllk_zqinit_done_r <= #TCQ 1'b0;
end else if (~(phy_ctl_full || phy_cmd_full)) begin
cnt_dllk_zqinit_r <= #TCQ cnt_dllk_zqinit_r + 1;
if (!cnt_dllk_zqinit_done_r)
cnt_dllk_zqinit_done_r
<= #TCQ (cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT);
end
//*****************************************************************
// Keep track of which MRS counter needs to be programmed during
// memory initialization
// The counter and the done signal are reset an additional time
// for DDR2. The same signals are used for the additional DDR2
// initialization sequence.
//*****************************************************************
always @(posedge clk)
if ((init_state_r == INIT_IDLE)||
((init_state_r == INIT_REFRESH)
&& (~mem_init_done_r))) begin
cnt_init_mr_r <= #TCQ 'b0;
cnt_init_mr_done_r <= #TCQ 1'b0;
end else if (init_state_r == INIT_LOAD_MR) begin
cnt_init_mr_r <= #TCQ cnt_init_mr_r + 1;
cnt_init_mr_done_r <= #TCQ (cnt_init_mr_r == INIT_CNT_MR_DONE);
end
//*****************************************************************
// Flag to tell if the first precharge for DDR2 init sequence is
// done
//*****************************************************************
always @(posedge clk)
if (init_state_r == INIT_IDLE)
ddr2_pre_flag_r<= #TCQ 'b0;
else if (init_state_r == INIT_LOAD_MR)
ddr2_pre_flag_r<= #TCQ 1'b1;
// reset the flag for multi rank case
else if ((ddr2_refresh_flag_r) &&
(init_state_r == INIT_LOAD_MR_WAIT)&&
(cnt_cmd_done_r) && (cnt_init_mr_done_r))
ddr2_pre_flag_r <= #TCQ 'b0;
//*****************************************************************
// Flag to tell if the refresh stat for DDR2 init sequence is
// reached
//*****************************************************************
always @(posedge clk)
if (init_state_r == INIT_IDLE)
ddr2_refresh_flag_r<= #TCQ 'b0;
else if ((init_state_r == INIT_REFRESH) && (~mem_init_done_r))
// reset the flag for multi rank case
ddr2_refresh_flag_r<= #TCQ 1'b1;
else if ((ddr2_refresh_flag_r) &&
(init_state_r == INIT_LOAD_MR_WAIT)&&
(cnt_cmd_done_r) && (cnt_init_mr_done_r))
ddr2_refresh_flag_r <= #TCQ 'b0;
//*****************************************************************
// Keep track of the number of auto refreshes for DDR2
// initialization. The spec asks for a minimum of two refreshes.
// Four refreshes are performed here. The two extra refreshes is to
// account for the 200 clock cycle wait between step h and l.
// Without the two extra refreshes we would have to have a
// wait state.
//*****************************************************************
always @(posedge clk)
if (init_state_r == INIT_IDLE) begin
cnt_init_af_r <= #TCQ 'b0;
cnt_init_af_done_r <= #TCQ 1'b0;
end else if ((init_state_r == INIT_REFRESH) && (~mem_init_done_r))begin
cnt_init_af_r <= #TCQ cnt_init_af_r + 1;
cnt_init_af_done_r <= #TCQ (cnt_init_af_r == 2'b11);
end
//*****************************************************************
// Keep track of the register control word programming for
// DDR3 RDIMM
//*****************************************************************
always @(posedge clk)
if (init_state_r == INIT_IDLE)
reg_ctrl_cnt_r <= #TCQ 'b0;
else if (init_state_r == INIT_REG_WRITE)
reg_ctrl_cnt_r <= #TCQ reg_ctrl_cnt_r + 1;
generate
if (RANKS < 2) begin: one_rank
always @(posedge clk)
if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done)
stg1_wr_done <= #TCQ 1'b0;
else if (init_state_r == INIT_RDLVL_STG1_WRITE_READ)
stg1_wr_done <= #TCQ 1'b1;
end else begin: two_ranks
always @(posedge clk)
if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done ||
(rdlvl_stg1_rank_done ))
stg1_wr_done <= #TCQ 1'b0;
else if (init_state_r == INIT_RDLVL_STG1_WRITE_READ)
stg1_wr_done <= #TCQ 1'b1;
end
endgenerate
always @(posedge clk)
if (rst)
rnk_ref_cnt <= #TCQ 1'b0;
else if (stg1_wr_done &&
(init_state_r == INIT_REFRESH_WAIT) && cnt_cmd_done_r)
rnk_ref_cnt <= #TCQ ~rnk_ref_cnt;
always @(posedge clk)
if (rst || (init_state_r == INIT_MPR_RDEN) ||
(init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_RDLVL_ACT))
num_refresh <= #TCQ 'd0;
else if ((init_state_r == INIT_REFRESH) &&
(~pi_dqs_found_done || ((DRAM_TYPE == "DDR3") && ~oclkdelay_calib_done) ||
(rdlvl_stg1_done && ~prbs_rdlvl_done) ||
((CLK_PERIOD/nCK_PER_CLK <= 2500) && wrcal_done && ~rdlvl_stg1_done) ||
((CLK_PERIOD/nCK_PER_CLK > 2500) && wrlvl_done_r1 && ~rdlvl_stg1_done)))
num_refresh <= #TCQ num_refresh + 1;
//***************************************************************************
// Initialization state machine
//***************************************************************************
//*****************************************************************
// Next-state logic
//*****************************************************************
always @(posedge clk)
if (rst)begin
init_state_r <= #TCQ INIT_IDLE;
init_state_r1 <= #TCQ INIT_IDLE;
end else begin
init_state_r <= #TCQ init_next_state;
init_state_r1 <= #TCQ init_state_r;
end
always @(burst_addr_r or chip_cnt_r or cnt_cmd_done_r
or cnt_dllk_zqinit_done_r or cnt_init_af_done_r
or cnt_init_mr_done_r or phy_ctl_ready or phy_ctl_full
or stg1_wr_done or rdlvl_last_byte_done
or phy_cmd_full or num_reads or rnk_ref_cnt or mpr_last_byte_done
or oclk_wr_cnt or mpr_rdlvl_done or mpr_rnk_done or num_refresh
or oclkdelay_calib_done or oclk_prech_req or oclk_calib_resume
or wrlvl_byte_redo or wrlvl_byte_done or wrlvl_final or wrlvl_final_r
or cnt_init_pre_wait_done_r or cnt_pwron_cke_done_r
or delay_incdec_done or wrcal_wr_cnt
or ck_addr_cmd_delay_done or wrcal_read_req or wrcal_reads or cnt_wrcal_rd
or wrcal_act_req or temp_wrcal_done or temp_lmr_done
or cnt_txpr_done_r or ddr2_pre_flag_r
or ddr2_refresh_flag_r or ddr3_lm_done_r
or init_state_r or mem_init_done_r or dqsfound_retry or dqs_found_prech_req
or prech_req_posedge_r or prech_req_r or wrcal_done or wrcal_resume_r
or rdlvl_stg1_done or rdlvl_stg1_done_r1 or rdlvl_stg1_rank_done or rdlvl_stg1_start_int
or prbs_rdlvl_done or prbs_last_byte_done or prbs_rdlvl_done_r1
or stg1_wr_rd_cnt or rdlvl_prech_req or wrcal_prech_req
or read_calib_int or read_calib_r or pi_calib_done_r1
or pi_phase_locked_all_r3 or pi_phase_locked_all_r4
or pi_dqs_found_done or pi_dqs_found_rank_done or pi_dqs_found_start
or reg_ctrl_cnt_r or wrlvl_done_r1 or wrlvl_rank_done_r7
or wrcal_final_chk or wrcal_sanity_chk_done) begin
init_next_state = init_state_r;
(* full_case, parallel_case *) case (init_state_r)
//*******************************************************
// DRAM initialization
//*******************************************************
// Initial state - wait for:
// 1. Power-on delays to pass
// 2. PHY Control Block to assert phy_ctl_ready
// 3. PHY Control FIFO must not be FULL
// 4. Read path initialization to finish
INIT_IDLE:
if (cnt_pwron_cke_done_r && phy_ctl_ready && ck_addr_cmd_delay_done && delay_incdec_done
&& ~(phy_ctl_full || phy_cmd_full) ) begin
// If skipping memory initialization (simulation only)
if (SIM_INIT_OPTION == "SKIP_INIT")
//if (WRLVL == "ON")
// Proceed to write leveling
// init_next_state = INIT_WRLVL_START;
//else //if (SIM_CAL_OPTION != "SKIP_CAL")
// Proceed to Phaser_In phase lock
init_next_state = INIT_RDLVL_ACT;
// else
// Skip read leveling
//init_next_state = INIT_DONE;
else
init_next_state = INIT_WAIT_CKE_EXIT;
end
// Wait minimum of Reset CKE exit time (tXPR = max(tXS,
INIT_WAIT_CKE_EXIT:
if ((cnt_txpr_done_r) && (DRAM_TYPE == "DDR3")
&& ~(phy_ctl_full || phy_cmd_full)) begin
if((REG_CTRL == "ON") && ((nCS_PER_RANK > 1) ||
(RANKS > 1)))
//register write for reg dimm. Some register chips
// have the register chip in a pre-programmed state
// in that case the nCS_PER_RANK == 1 && RANKS == 1
init_next_state = INIT_REG_WRITE;
else
// Load mode register - this state is repeated multiple times
init_next_state = INIT_LOAD_MR;
end else if ((cnt_init_pre_wait_done_r) && (DRAM_TYPE == "DDR2")
&& ~(phy_ctl_full || phy_cmd_full))
// DDR2 start with a precharge all command
init_next_state = INIT_DDR2_PRECHARGE;
INIT_REG_WRITE:
init_next_state = INIT_REG_WRITE_WAIT;
INIT_REG_WRITE_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin
if(reg_ctrl_cnt_r == 3'd5)
init_next_state = INIT_LOAD_MR;
else
init_next_state = INIT_REG_WRITE;
end
INIT_LOAD_MR:
init_next_state = INIT_LOAD_MR_WAIT;
// After loading MR, wait at least tMRD
INIT_LOAD_MR_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin
// If finished loading all mode registers, proceed to next step
if (prbs_rdlvl_done && pi_dqs_found_done && rdlvl_stg1_done)
// for ddr3 when the correct burst length is writtern at end
init_next_state = INIT_PRECHARGE;
else if (~wrcal_done && temp_lmr_done)
init_next_state = INIT_PRECHARGE_PREWAIT;
else if (cnt_init_mr_done_r)begin
if(DRAM_TYPE == "DDR3")
init_next_state = INIT_ZQCL;
else begin //DDR2
if(ddr2_refresh_flag_r)begin
// memory initialization per rank for multi-rank case
if (!mem_init_done_r && (chip_cnt_r <= RANKS-1))
init_next_state = INIT_DDR2_MULTI_RANK;
else
init_next_state = INIT_RDLVL_ACT;
// ddr2 initialization done.load mode state after refresh
end else
init_next_state = INIT_DDR2_PRECHARGE;
end
end else
init_next_state = INIT_LOAD_MR;
end
// DDR2 multi rank transition state
INIT_DDR2_MULTI_RANK:
init_next_state = INIT_DDR2_MULTI_RANK_WAIT;
INIT_DDR2_MULTI_RANK_WAIT:
init_next_state = INIT_DDR2_PRECHARGE;
// Initial ZQ calibration
INIT_ZQCL:
init_next_state = INIT_WAIT_DLLK_ZQINIT;
// Wait until both DLL have locked, and ZQ calibration done
INIT_WAIT_DLLK_ZQINIT:
if (cnt_dllk_zqinit_done_r && ~(phy_ctl_full || phy_cmd_full))
// memory initialization per rank for multi-rank case
if (!mem_init_done_r && (chip_cnt_r <= RANKS-1))
init_next_state = INIT_LOAD_MR;
//else if (WRLVL == "ON")
// init_next_state = INIT_WRLVL_START;
else
// skip write-leveling (e.g. for DDR2 interface)
init_next_state = INIT_RDLVL_ACT;
// Initial precharge for DDR2
INIT_DDR2_PRECHARGE:
init_next_state = INIT_DDR2_PRECHARGE_WAIT;
INIT_DDR2_PRECHARGE_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin
if (ddr2_pre_flag_r)
init_next_state = INIT_REFRESH;
else // from precharge state initially go to load mode
init_next_state = INIT_LOAD_MR;
end
INIT_REFRESH:
if ((RANKS == 2) && (chip_cnt_r == RANKS - 1))
init_next_state = INIT_REFRESH_RNK2_WAIT;
else
init_next_state = INIT_REFRESH_WAIT;
INIT_REFRESH_RNK2_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))
init_next_state = INIT_PRECHARGE;
INIT_REFRESH_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))begin
if(cnt_init_af_done_r && (~mem_init_done_r))
// go to lm state as part of DDR2 init sequence
init_next_state = INIT_LOAD_MR;
else if (pi_dqs_found_done && ~wrlvl_done_r1 && ~wrlvl_final && ~wrlvl_byte_redo && (WRLVL == "ON"))
init_next_state = INIT_WRLVL_START;
else if (~pi_dqs_found_done ||
(rdlvl_stg1_done && ~prbs_rdlvl_done) ||
((CLK_PERIOD/nCK_PER_CLK <= 2500) && wrcal_done && ~rdlvl_stg1_done) ||
((CLK_PERIOD/nCK_PER_CLK > 2500) && wrlvl_done_r1 && ~rdlvl_stg1_done)) begin
if (num_refresh == 'd8)
init_next_state = INIT_RDLVL_ACT;
else
init_next_state = INIT_REFRESH;
end else if ((~wrcal_done && wrlvl_byte_redo)&& (DRAM_TYPE == "DDR3")
&& (CLK_PERIOD/nCK_PER_CLK > 2500))
init_next_state = INIT_WRLVL_LOAD_MR2;
else if (((prbs_rdlvl_done && rdlvl_stg1_done && pi_dqs_found_done) && (WRLVL == "ON"))
&& mem_init_done_r && (CLK_PERIOD/nCK_PER_CLK > 2500))
init_next_state = INIT_WRCAL_ACT;
else if (pi_dqs_found_done && (DRAM_TYPE == "DDR3") && ~(mpr_last_byte_done || mpr_rdlvl_done)) begin
if (num_refresh == 'd8)
init_next_state = INIT_MPR_RDEN;
else
init_next_state = INIT_REFRESH;
end else if (((~oclkdelay_calib_done && wrlvl_final) ||
(~wrcal_done && wrlvl_byte_redo)) && (DRAM_TYPE == "DDR3"))
init_next_state = INIT_WRLVL_LOAD_MR2;
else if (~oclkdelay_calib_done && (mpr_last_byte_done || mpr_rdlvl_done) && (DRAM_TYPE == "DDR3")) begin
if (num_refresh == 'd8)
init_next_state = INIT_OCLKDELAY_ACT;
else
init_next_state = INIT_REFRESH;
end else if ((~wrcal_done && (WRLVL == "ON") && (CLK_PERIOD/nCK_PER_CLK <= 2500))
&& pi_dqs_found_done)
init_next_state = INIT_WRCAL_ACT;
else if (mem_init_done_r) begin
if (RANKS < 2)
init_next_state = INIT_RDLVL_ACT;
else if (stg1_wr_done && ~rnk_ref_cnt && ~rdlvl_stg1_done)
init_next_state = INIT_PRECHARGE;
else
init_next_state = INIT_RDLVL_ACT;
end else // to DDR2 init state as part of DDR2 init sequence
init_next_state = INIT_REFRESH;
end
//******************************************************
// Write Leveling
//*******************************************************
// Enable write leveling in MR1 and start write leveling
// for current rank
INIT_WRLVL_START:
init_next_state = INIT_WRLVL_WAIT;
// Wait for both MR load and write leveling to complete
// (write leveling should take much longer than MR load..)
INIT_WRLVL_WAIT:
if (wrlvl_rank_done_r7 && ~(phy_ctl_full || phy_cmd_full))
init_next_state = INIT_WRLVL_LOAD_MR;
// Disable write leveling in MR1 for current rank
INIT_WRLVL_LOAD_MR:
init_next_state = INIT_WRLVL_LOAD_MR_WAIT;
INIT_WRLVL_LOAD_MR_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))
init_next_state = INIT_WRLVL_LOAD_MR2;
// Load MR2 to set ODT: Dynamic ODT for single rank case
// And ODTs for multi-rank case as well
INIT_WRLVL_LOAD_MR2:
init_next_state = INIT_WRLVL_LOAD_MR2_WAIT;
// Wait tMRD before proceeding
INIT_WRLVL_LOAD_MR2_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin
//if (wrlvl_byte_done)
// init_next_state = INIT_PRECHARGE_PREWAIT;
// else if ((RANKS == 2) && wrlvl_rank_done_r2)
// init_next_state = INIT_WRLVL_LOAD_MR2_WAIT;
if (~wrlvl_done_r1)
init_next_state = INIT_WRLVL_START;
else if (SIM_CAL_OPTION == "SKIP_CAL")
// If skip rdlvl, then we're done
init_next_state = INIT_DONE;
else
// Otherwise, proceed to read leveling
//init_next_state = INIT_RDLVL_ACT;
init_next_state = INIT_PRECHARGE_PREWAIT;
end
//*******************************************************
// Read Leveling
//*******************************************************
// single row activate. All subsequent read leveling writes and
// read will take place in this row
INIT_RDLVL_ACT:
init_next_state = INIT_RDLVL_ACT_WAIT;
// hang out for awhile before issuing subsequent column commands
// it's also possible to reach this state at various points
// during read leveling - determine what the current stage is
INIT_RDLVL_ACT_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin
// Just finished an activate. Now either write, read, or precharge
// depending on where we are in the training sequence
if (!pi_calib_done_r1)
init_next_state = INIT_PI_PHASELOCK_READS;
else if (!pi_dqs_found_done)
// (!pi_dqs_found_start || pi_dqs_found_rank_done))
init_next_state = INIT_RDLVL_STG2_READ;
else if (~wrcal_done && (WRLVL == "ON") && (CLK_PERIOD/nCK_PER_CLK <= 2500))
init_next_state = INIT_WRCAL_ACT_WAIT;
else if ((!rdlvl_stg1_done && ~stg1_wr_done && ~rdlvl_last_byte_done) ||
(!prbs_rdlvl_done && ~stg1_wr_done && ~prbs_last_byte_done)) begin
// Added to avoid rdlvl_stg1 write data pattern at the start of PRBS rdlvl
if (!prbs_rdlvl_done && ~stg1_wr_done && rdlvl_last_byte_done)
init_next_state = INIT_RDLVL_ACT_WAIT;
else
init_next_state = INIT_RDLVL_STG1_WRITE;
end else if ((!rdlvl_stg1_done && rdlvl_stg1_start_int) || !prbs_rdlvl_done) begin
if (rdlvl_last_byte_done || prbs_last_byte_done)
// Added to avoid extra reads at the end of read leveling
init_next_state = INIT_RDLVL_ACT_WAIT;
else
// Case 2: If in stage 1, and just precharged after training
// previous byte, then continue reading
init_next_state = INIT_RDLVL_STG1_READ;
end else if ((prbs_rdlvl_done && rdlvl_stg1_done && (RANKS == 1)) && (WRLVL == "ON") &&
(CLK_PERIOD/nCK_PER_CLK > 2500))
init_next_state = INIT_WRCAL_ACT_WAIT;
else
// Otherwise, if we're finished with calibration, then precharge
// the row - silly, because we just opened it - possible to take
// this out by adding logic to avoid the ACT in first place. Make
// sure that cnt_cmd_done will handle tRAS(min)
init_next_state = INIT_PRECHARGE_PREWAIT;
end
//**************************************************
// Back-to-back reads for Phaser_IN Phase locking
// DQS to FREQ_REF clock
//**************************************************
INIT_PI_PHASELOCK_READS:
if (pi_phase_locked_all_r3 && ~pi_phase_locked_all_r4)
init_next_state = INIT_PRECHARGE_PREWAIT;
//*********************************************
// Stage 1 read-leveling (write and continuous read)
//*********************************************
// Write training pattern for stage 1
// PRBS pattern of TBD length
INIT_RDLVL_STG1_WRITE:
// 4:1 DDR3 BL8 will require all 8 words in 1 DIV4 clock cycle
// 2:1 DDR2/DDR3 BL8 will require 2 DIV2 clock cycles for 8 words
// 2:1 DDR2 BL4 will require 1 DIV2 clock cycle for 4 words
// An entire row worth of writes issued before proceeding to reads
// The number of write is (2^column width)/burst length to accomodate
// PRBS pattern for window detection.
if (stg1_wr_rd_cnt == 9'd1)
init_next_state = INIT_RDLVL_STG1_WRITE_READ;
// Write-read turnaround
INIT_RDLVL_STG1_WRITE_READ:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))
init_next_state = INIT_RDLVL_STG1_READ;
// Continuous read, where interruptible by precharge request from
// calibration logic. Also precharges when stage 1 is complete
// No precharges when reads provided to Phaser_IN for phase locking
// FREQ_REF to read DQS since data integrity is not important.
INIT_RDLVL_STG1_READ:
if (rdlvl_stg1_rank_done || (rdlvl_stg1_done && ~rdlvl_stg1_done_r1) ||
prech_req_posedge_r || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1))
init_next_state = INIT_PRECHARGE_PREWAIT;
//*********************************************
// DQSFOUND calibration (set of 4 reads with gaps)
//*********************************************
// Read of training data. Note that Stage 2 is not a constant read,
// instead there is a large gap between each set of back-to-back reads
INIT_RDLVL_STG2_READ:
// 4 read commands issued back-to-back
if (num_reads == 'b1)
init_next_state = INIT_RDLVL_STG2_READ_WAIT;
// Wait before issuing the next set of reads. If a precharge request
// comes in then handle - this can occur after stage 2 calibration is
// completed for a DQS group
INIT_RDLVL_STG2_READ_WAIT:
if (~(phy_ctl_full || phy_cmd_full)) begin
if (pi_dqs_found_rank_done ||
pi_dqs_found_done || prech_req_posedge_r)
init_next_state = INIT_PRECHARGE_PREWAIT;
else if (cnt_cmd_done_r)
init_next_state = INIT_RDLVL_STG2_READ;
end
//******************************************************************
// MPR Read Leveling for DDR3 OCLK_DELAYED calibration
//******************************************************************
// Issue Load Mode Register 3 command with A[2]=1, A[1:0]=2'b00
// to enable Multi Purpose Register (MPR) Read
INIT_MPR_RDEN:
init_next_state = INIT_MPR_WAIT;
//Wait tMRD, tMOD
INIT_MPR_WAIT:
if (cnt_cmd_done_r) begin
init_next_state = INIT_MPR_READ;
end
// Issue back-to-back read commands to read from MPR with
// Address bus 0x0000 for BL=8. DQ[0] will output the pre-defined
// MPR pattern of 01010101 (Rise0 = 1'b0, Fall0 = 1'b1 ...)
INIT_MPR_READ:
if (mpr_rdlvl_done || mpr_rnk_done || rdlvl_prech_req)
init_next_state = INIT_MPR_DISABLE_PREWAIT;
INIT_MPR_DISABLE_PREWAIT:
if (cnt_cmd_done_r)
init_next_state = INIT_MPR_DISABLE;
// Issue Load Mode Register 3 command with A[2]=0 to disable
// MPR read
INIT_MPR_DISABLE:
init_next_state = INIT_MPR_DISABLE_WAIT;
INIT_MPR_DISABLE_WAIT:
init_next_state = INIT_PRECHARGE_PREWAIT;
//***********************************************************************
// OCLKDELAY Calibration
//***********************************************************************
// This calibration requires single write followed by single read to
// determine the Phaser_Out stage 3 delay required to center write DQS
// in write DQ valid window.
// Single Row Activate command before issuing Write command
INIT_OCLKDELAY_ACT:
init_next_state = INIT_OCLKDELAY_ACT_WAIT;
INIT_OCLKDELAY_ACT_WAIT:
if (cnt_cmd_done_r && ~oclk_prech_req)
init_next_state = INIT_OCLKDELAY_WRITE;
else if (oclkdelay_calib_done || prech_req_posedge_r)
init_next_state = INIT_PRECHARGE_PREWAIT;
INIT_OCLKDELAY_WRITE:
if (oclk_wr_cnt == 4'd1)
init_next_state = INIT_OCLKDELAY_WRITE_WAIT;
INIT_OCLKDELAY_WRITE_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))
init_next_state = INIT_OCLKDELAY_READ;
INIT_OCLKDELAY_READ:
init_next_state = INIT_OCLKDELAY_READ_WAIT;
INIT_OCLKDELAY_READ_WAIT:
if (~(phy_ctl_full || phy_cmd_full)) begin
if (oclk_calib_resume)
init_next_state = INIT_OCLKDELAY_WRITE;
else if (oclkdelay_calib_done || prech_req_posedge_r ||
wrlvl_final)
init_next_state = INIT_PRECHARGE_PREWAIT;
end
//*********************************************
// Write calibration
//*********************************************
// single row activate
INIT_WRCAL_ACT:
init_next_state = INIT_WRCAL_ACT_WAIT;
// hang out for awhile before issuing subsequent column command
INIT_WRCAL_ACT_WAIT:
if (cnt_cmd_done_r && ~wrcal_prech_req)
init_next_state = INIT_WRCAL_WRITE;
else if (wrcal_done || prech_req_posedge_r)
init_next_state = INIT_PRECHARGE_PREWAIT;
// Write training pattern for write calibration
INIT_WRCAL_WRITE:
// Once we've issued enough commands for 8 words - proceed to reads
//if (burst_addr_r == 1'b1)
if (wrcal_wr_cnt == 4'd1)
init_next_state = INIT_WRCAL_WRITE_READ;
// Write-read turnaround
INIT_WRCAL_WRITE_READ:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))
init_next_state = INIT_WRCAL_READ;
else if (dqsfound_retry)
init_next_state = INIT_RDLVL_STG2_READ_WAIT;
INIT_WRCAL_READ:
if (burst_addr_r == 1'b1)
init_next_state = INIT_WRCAL_READ_WAIT;
INIT_WRCAL_READ_WAIT:
if (~(phy_ctl_full || phy_cmd_full)) begin
if (wrcal_resume_r) begin
if (wrcal_final_chk)
init_next_state = INIT_WRCAL_READ;
else
init_next_state = INIT_WRCAL_WRITE;
end else if (wrcal_done || prech_req_posedge_r || wrcal_act_req ||
// Added to support PO fine delay inc when TG errors
wrlvl_byte_redo || (temp_wrcal_done && ~temp_lmr_done))
init_next_state = INIT_PRECHARGE_PREWAIT;
else if (dqsfound_retry)
init_next_state = INIT_RDLVL_STG2_READ_WAIT;
else if (wrcal_read_req && cnt_wrcal_rd)
init_next_state = INIT_WRCAL_MULT_READS;
end
INIT_WRCAL_MULT_READS:
// multiple read commands issued back-to-back
if (wrcal_reads == 'b1)
init_next_state = INIT_WRCAL_READ_WAIT;
//*********************************************
// Handling of precharge during and in between read-level stages
//*********************************************
// Make sure we aren't violating any timing specs by precharging
// immediately
INIT_PRECHARGE_PREWAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))
init_next_state = INIT_PRECHARGE;
// Initiate precharge
INIT_PRECHARGE:
init_next_state = INIT_PRECHARGE_WAIT;
INIT_PRECHARGE_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin
if ((wrcal_sanity_chk_done && (DRAM_TYPE == "DDR3")) ||
(rdlvl_stg1_done && prbs_rdlvl_done && pi_dqs_found_done &&
(DRAM_TYPE == "DDR2")))
init_next_state = INIT_DONE;
else if ((wrcal_done || (WRLVL == "OFF")) && rdlvl_stg1_done && prbs_rdlvl_done &&
pi_dqs_found_done && ((ddr3_lm_done_r) || (DRAM_TYPE == "DDR2")))
// If read leveling and phase detection calibration complete,
// and programing the correct burst length then we're finished
init_next_state = INIT_WRCAL_ACT;
else if ((wrcal_done || (WRLVL == "OFF") || (~wrcal_done && temp_wrcal_done && ~temp_lmr_done))
&& (rdlvl_stg1_done || (~wrcal_done && temp_wrcal_done && ~temp_lmr_done))
&& prbs_rdlvl_done && rdlvl_stg1_done && pi_dqs_found_done) begin
// after all calibration program the correct burst length
init_next_state = INIT_LOAD_MR;
// Added to support PO fine delay inc when TG errors
end else if (~wrcal_done && temp_wrcal_done && temp_lmr_done)
init_next_state = INIT_WRCAL_READ_WAIT;
else if (rdlvl_stg1_done && pi_dqs_found_done && (WRLVL == "ON"))
// If read leveling finished, proceed to write calibration
init_next_state = INIT_REFRESH;
else
// Otherwise, open row for read-leveling purposes
init_next_state = INIT_REFRESH;
end
//*******************************************************
// Initialization/Calibration done. Take a long rest, relax
//*******************************************************
INIT_DONE:
init_next_state = INIT_DONE;
endcase
end
//*****************************************************************
// Initialization done signal - asserted before leveling starts
//*****************************************************************
always @(posedge clk)
if (rst)
mem_init_done_r <= #TCQ 1'b0;
else if ((!cnt_dllk_zqinit_done_r &&
(cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT) &&
(chip_cnt_r == RANKS-1) && (DRAM_TYPE == "DDR3"))
|| ( (init_state_r == INIT_LOAD_MR_WAIT) &&
(ddr2_refresh_flag_r) && (chip_cnt_r == RANKS-1)
&& (cnt_init_mr_done_r) && (DRAM_TYPE == "DDR2")))
mem_init_done_r <= #TCQ 1'b1;
//*****************************************************************
// Write Calibration signal to PHY Control Block - asserted before
// Write Leveling starts
//*****************************************************************
//generate
//if (RANKS < 2) begin: ranks_one
always @(posedge clk) begin
if (rst || (done_dqs_tap_inc &&
(init_state_r == INIT_WRLVL_LOAD_MR2)))
write_calib <= #TCQ 1'b0;
else if (wrlvl_active_r1)
write_calib <= #TCQ 1'b1;
end
//end else begin: ranks_two
// always @(posedge clk) begin
// if (rst ||
// ((init_state_r1 == INIT_WRLVL_LOAD_MR_WAIT) &&
// ((wrlvl_rank_done_r2 && (chip_cnt_r == RANKS-1)) ||
// (SIM_CAL_OPTION == "FAST_CAL"))))
// write_calib <= #TCQ 1'b0;
// else if (wrlvl_active_r1)
// write_calib <= #TCQ 1'b1;
// end
//end
//endgenerate
//*****************************************************************
// Read Calibration signal to PHY Control Block - asserted after
// Write Leveling during PHASER_IN phase locking stage.
// Must be de-asserted before Read Leveling
//*****************************************************************
always @(posedge clk) begin
if (rst || pi_calib_done_r1)
read_calib_int <= #TCQ 1'b0;
else if (~pi_calib_done_r1 && (init_state_r == INIT_RDLVL_ACT_WAIT) &&
(cnt_cmd_r == CNTNEXT_CMD))
read_calib_int <= #TCQ 1'b1;
end
always @(posedge clk)
read_calib_r <= #TCQ read_calib_int;
always @(posedge clk) begin
if (rst || pi_calib_done_r1)
read_calib <= #TCQ 1'b0;
else if (~pi_calib_done_r1 && (init_state_r == INIT_PI_PHASELOCK_READS))
read_calib <= #TCQ 1'b1;
end
always @(posedge clk)
if (rst)
pi_calib_done_r <= #TCQ 1'b0;
else if (pi_calib_rank_done_r)// && (chip_cnt_r == RANKS-1))
pi_calib_done_r <= #TCQ 1'b1;
always @(posedge clk)
if (rst)
pi_calib_rank_done_r <= #TCQ 1'b0;
else if (pi_phase_locked_all_r3 && ~pi_phase_locked_all_r4)
pi_calib_rank_done_r <= #TCQ 1'b1;
else
pi_calib_rank_done_r <= #TCQ 1'b0;
always @(posedge clk) begin
if (rst || ((PRE_REV3ES == "ON") && temp_wrcal_done && ~temp_wrcal_done_r))
pi_phaselock_timer <= #TCQ 'd0;
else if (((init_state_r == INIT_PI_PHASELOCK_READS) &&
(pi_phaselock_timer != PHASELOCKED_TIMEOUT)) ||
tg_timer_go)
pi_phaselock_timer <= #TCQ pi_phaselock_timer + 1;
else
pi_phaselock_timer <= #TCQ pi_phaselock_timer;
end
assign pi_phase_locked_err = (pi_phaselock_timer == PHASELOCKED_TIMEOUT) ? 1'b1 : 1'b0;
//*****************************************************************
// DDR3 final burst length programming done. For DDR3 during
// calibration the burst length is fixed to BL8. After calibration
// the correct burst length is programmed.
//*****************************************************************
always @(posedge clk)
if (rst)
ddr3_lm_done_r <= #TCQ 1'b0;
else if ((init_state_r == INIT_LOAD_MR_WAIT) &&
(chip_cnt_r == RANKS-1) && wrcal_done)
ddr3_lm_done_r <= #TCQ 1'b1;
always @(posedge clk) begin
pi_dqs_found_rank_done_r <= #TCQ pi_dqs_found_rank_done;
pi_phase_locked_all_r1 <= #TCQ pi_phase_locked_all;
pi_phase_locked_all_r2 <= #TCQ pi_phase_locked_all_r1;
pi_phase_locked_all_r3 <= #TCQ pi_phase_locked_all_r2;
pi_phase_locked_all_r4 <= #TCQ pi_phase_locked_all_r3;
pi_dqs_found_all_r <= #TCQ pi_dqs_found_done;
pi_calib_done_r1 <= #TCQ pi_calib_done_r;
end
//***************************************************************************
// Logic for deep memory (multi-rank) configurations
//***************************************************************************
// For DDR3 asserted when
generate
if (RANKS < 2) begin: single_rank
always @(posedge clk)
chip_cnt_r <= #TCQ 2'b00;
end else begin: dual_rank
always @(posedge clk)
if (rst ||
// Set chip_cnt_r to 2'b00 after both Ranks are read leveled
(rdlvl_stg1_done && prbs_rdlvl_done && ~wrcal_done) ||
// Set chip_cnt_r to 2'b00 after both Ranks are write leveled
(wrlvl_done_r &&
(init_state_r==INIT_WRLVL_LOAD_MR2_WAIT)))begin
chip_cnt_r <= #TCQ 2'b00;
end else if ((((init_state_r == INIT_WAIT_DLLK_ZQINIT) &&
(cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT)) &&
(DRAM_TYPE == "DDR3")) ||
((init_state_r==INIT_REFRESH_RNK2_WAIT) &&
(cnt_cmd_r=='d36)) ||
//mpr_rnk_done ||
//(rdlvl_stg1_rank_done && ~rdlvl_last_byte_done) ||
//(stg1_wr_done && (init_state_r == INIT_REFRESH) &&
//~(rnk_ref_cnt && rdlvl_last_byte_done)) ||
// Increment chip_cnt_r to issue Refresh to second rank
(~pi_dqs_found_all_r &&
(init_state_r==INIT_PRECHARGE_PREWAIT) &&
(cnt_cmd_r=='d36)) ||
// Increment chip_cnt_r when DQSFOUND done for the Rank
(pi_dqs_found_rank_done && ~pi_dqs_found_rank_done_r) ||
((init_state_r == INIT_LOAD_MR_WAIT)&& cnt_cmd_done_r
&& wrcal_done) ||
((init_state_r == INIT_DDR2_MULTI_RANK)
&& (DRAM_TYPE == "DDR2"))) begin
if ((~mem_init_done_r || ~rdlvl_stg1_done || ~pi_dqs_found_done ||
// condition to increment chip_cnt during
// final burst length programming for DDR3
~pi_calib_done_r || wrcal_done) //~mpr_rdlvl_done ||
&& (chip_cnt_r != RANKS-1))
chip_cnt_r <= #TCQ chip_cnt_r + 1;
else
chip_cnt_r <= #TCQ 2'b00;
end
end
endgenerate
generate
if ((REG_CTRL == "ON") && (RANKS == 1)) begin: DDR3_RDIMM_1rank
always @(posedge clk) begin
if (rst)
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
else if (init_state_r == INIT_REG_WRITE) begin
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
if(!(CWL_M%2)) begin
phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0;
phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0;
end else begin
phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0;
phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0;
end
end else if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_MPR_RDEN) ||
(init_state_r == INIT_MPR_DISABLE) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_ZQCL) ||
(init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_WRCAL_ACT) ||
(init_state_r == INIT_OCLKDELAY_ACT) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE) ||
(init_state_r == INIT_REFRESH) ||
(rdlvl_wr_rd && new_burst_r)) begin
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
if (!(CWL_M % 2)) //even CWL
phy_int_cs_n[0] <= #TCQ 1'b0;
else // odd CWL
phy_int_cs_n[1*nCS_PER_RANK] <= #TCQ 1'b0;
end else
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
end
end else if (RANKS == 1) begin: DDR3_1rank
always @(posedge clk) begin
if (rst)
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
else if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_MPR_RDEN) ||
(init_state_r == INIT_MPR_DISABLE) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_ZQCL) ||
(init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_WRCAL_ACT) ||
(init_state_r == INIT_OCLKDELAY_ACT) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE) ||
(init_state_r == INIT_REFRESH) ||
(rdlvl_wr_rd && new_burst_r)) begin
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
if (!(CWL_M % 2)) begin //even CWL
for (n = 0; n < nCS_PER_RANK; n = n + 1) begin
phy_int_cs_n[n] <= #TCQ 1'b0;
end
end else begin //odd CWL
for (p = nCS_PER_RANK; p < 2*nCS_PER_RANK; p = p + 1) begin
phy_int_cs_n[p] <= #TCQ 1'b0;
end
end
end else
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
end
end else if ((REG_CTRL == "ON") && (RANKS == 2)) begin: DDR3_2rank
always @(posedge clk) begin
if (rst)
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
else if (init_state_r == INIT_REG_WRITE) begin
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
if(!(CWL_M%2)) begin
phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0;
phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0;
end else begin
phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0;
phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0;
end
end else begin
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
case (chip_cnt_r)
2'b00:begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_MPR_RDEN) ||
(init_state_r == INIT_MPR_DISABLE) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_ZQCL) ||
(init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_WRCAL_ACT) ||
(init_state_r == INIT_OCLKDELAY_ACT) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE) ||
(init_state_r == INIT_REFRESH) ||
(rdlvl_wr_rd && new_burst_r)) begin
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
if (!(CWL_M % 2)) //even CWL
phy_int_cs_n[0] <= #TCQ 1'b0;
else // odd CWL
phy_int_cs_n[1*CS_WIDTH*nCS_PER_RANK] <= #TCQ 1'b0;
end else
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
//for (n = 0; n < nCS_PER_RANK*nCK_PER_CLK*2; n = n + (nCS_PER_RANK*2)) begin
//
// phy_int_cs_n[n+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}};
//end
end
2'b01:begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_MPR_RDEN) ||
(init_state_r == INIT_MPR_DISABLE) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_ZQCL) ||
(init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_WRCAL_ACT) ||
(init_state_r == INIT_OCLKDELAY_ACT) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE) ||
(init_state_r == INIT_REFRESH) ||
(rdlvl_wr_rd && new_burst_r)) begin
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
if (!(CWL_M % 2)) //even CWL
phy_int_cs_n[1] <= #TCQ 1'b0;
else // odd CWL
phy_int_cs_n[1+1*CS_WIDTH*nCS_PER_RANK] <= #TCQ 1'b0;
end else
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
//for (p = nCS_PER_RANK; p < nCS_PER_RANK*nCK_PER_CLK*2; p = p + (nCS_PER_RANK*2)) begin
//
// phy_int_cs_n[p+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}};
//end
end
endcase
end
end
end else if (RANKS == 2) begin: DDR3_2rank
always @(posedge clk) begin
if (rst)
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
else if (init_state_r == INIT_REG_WRITE) begin
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
if(!(CWL_M%2)) begin
phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0;
phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0;
end else begin
phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0;
phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0;
end
end else begin
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
case (chip_cnt_r)
2'b00:begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_MPR_RDEN) ||
(init_state_r == INIT_MPR_DISABLE) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_ZQCL) ||
(init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_WRCAL_ACT) ||
(init_state_r == INIT_OCLKDELAY_ACT) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE) ||
(init_state_r == INIT_REFRESH) ||
(rdlvl_wr_rd && new_burst_r)) begin
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
if (!(CWL_M % 2)) begin //even CWL
for (n = 0; n < nCS_PER_RANK; n = n + 1) begin
phy_int_cs_n[n] <= #TCQ 1'b0;
end
end else begin // odd CWL
for (p = CS_WIDTH*nCS_PER_RANK; p < (CS_WIDTH*nCS_PER_RANK + nCS_PER_RANK); p = p + 1) begin
phy_int_cs_n[p] <= #TCQ 1'b0;
end
end
end else
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
//for (n = 0; n < nCS_PER_RANK*nCK_PER_CLK*2; n = n + (nCS_PER_RANK*2)) begin
//
// phy_int_cs_n[n+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}};
//end
end
2'b01:begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_MPR_RDEN) ||
(init_state_r == INIT_MPR_DISABLE) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_ZQCL) ||
(init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_WRCAL_ACT) ||
(init_state_r == INIT_OCLKDELAY_ACT) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE) ||
(init_state_r == INIT_REFRESH) ||
(rdlvl_wr_rd && new_burst_r)) begin
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
if (!(CWL_M % 2)) begin //even CWL
for (q = nCS_PER_RANK; q < (2 * nCS_PER_RANK); q = q + 1) begin
phy_int_cs_n[q] <= #TCQ 1'b0;
end
end else begin // odd CWL
for (m = (nCS_PER_RANK*CS_WIDTH + nCS_PER_RANK); m < (nCS_PER_RANK*CS_WIDTH + 2*nCS_PER_RANK); m = m + 1) begin
phy_int_cs_n[m] <= #TCQ 1'b0;
end
end
end else
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
//for (p = nCS_PER_RANK; p < nCS_PER_RANK*nCK_PER_CLK*2; p = p + (nCS_PER_RANK*2)) begin
//
// phy_int_cs_n[p+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}};
//end
end
endcase
end
end // always @ (posedge clk)
end
// commented out for now. Need it for DDR2 2T timing
/* end else begin: DDR2
always @(posedge clk)
if (rst) begin
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
end else begin
if (init_state_r == INIT_REG_WRITE) begin
// All ranks selected simultaneously
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b0}};
end else if ((wrlvl_odt) ||
(init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_ZQCL) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_PI_PHASELOCK_READS) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_RDLVL_STG1_READ) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_WRCAL_ACT) ||
(init_state_r == INIT_WRCAL_READ) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_DDR2_PRECHARGE) ||
(init_state_r == INIT_REFRESH)) begin
phy_int_cs_n[0] <= #TCQ 1'b0;
end
else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
end // else: !if(rst)
end // block: DDR2 */
endgenerate
assign phy_cs_n = phy_int_cs_n;
//***************************************************************************
// Write/read burst logic for calibration
//***************************************************************************
assign rdlvl_wr = (init_state_r == INIT_OCLKDELAY_WRITE) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE);
assign rdlvl_rd = (init_state_r == INIT_PI_PHASELOCK_READS) ||
(init_state_r == INIT_RDLVL_STG1_READ) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_OCLKDELAY_READ) ||
(init_state_r == INIT_WRCAL_READ) ||
(init_state_r == INIT_MPR_READ) ||
(init_state_r == INIT_WRCAL_MULT_READS);
assign rdlvl_wr_rd = rdlvl_wr | rdlvl_rd;
//***************************************************************************
// Address generation and logic to count # of writes/reads issued during
// certain stages of calibration
//***************************************************************************
// Column address generation logic:
// Keep track of the current column address - since all bursts are in
// increments of 8 only during calibration, we need to keep track of
// addresses [COL_WIDTH-1:3], lower order address bits will always = 0
always @(posedge clk)
if (rst || wrcal_done)
burst_addr_r <= #TCQ 1'b0;
else if ((init_state_r == INIT_WRCAL_ACT_WAIT) ||
(init_state_r == INIT_OCLKDELAY_ACT_WAIT) ||
(init_state_r == INIT_OCLKDELAY_WRITE) ||
(init_state_r == INIT_OCLKDELAY_READ) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE_READ) ||
(init_state_r == INIT_WRCAL_READ) ||
(init_state_r == INIT_WRCAL_MULT_READS) ||
(init_state_r == INIT_WRCAL_READ_WAIT))
burst_addr_r <= #TCQ 1'b1;
else if (rdlvl_wr_rd && new_burst_r)
burst_addr_r <= #TCQ ~burst_addr_r;
else
burst_addr_r <= #TCQ 1'b0;
// Read Level Stage 1 requires writes to the entire row since
// a PRBS pattern is being written. This counter keeps track
// of the number of writes which depends on the column width
// The (stg1_wr_rd_cnt==9'd0) condition was added so the col
// address wraps around during stage1 reads
always @(posedge clk)
if (rst || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) &&
~rdlvl_stg1_done))
stg1_wr_rd_cnt <= #TCQ NUM_STG1_WR_RD;
else if (rdlvl_last_byte_done || (stg1_wr_rd_cnt == 9'd1) ||
(prbs_rdlvl_prech_req && (init_state_r == INIT_RDLVL_ACT_WAIT)))
stg1_wr_rd_cnt <= #TCQ 'd128;
else if (((init_state_r == INIT_RDLVL_STG1_WRITE) && new_burst_r && ~phy_data_full)
||((init_state_r == INIT_RDLVL_STG1_READ) && rdlvl_stg1_done))
stg1_wr_rd_cnt <= #TCQ stg1_wr_rd_cnt - 1;
// OCLKDELAY calibration requires multiple writes because
// write can be up to 2 cycles early since OCLKDELAY tap
// can go down to 0
always @(posedge clk)
if (rst || (init_state_r == INIT_OCLKDELAY_WRITE_WAIT) ||
(oclk_wr_cnt == 4'd0))
oclk_wr_cnt <= #TCQ NUM_STG1_WR_RD;
else if ((init_state_r == INIT_OCLKDELAY_WRITE) &&
new_burst_r && ~phy_data_full)
oclk_wr_cnt <= #TCQ oclk_wr_cnt - 1;
// Write calibration requires multiple writes because
// write can be up to 2 cycles early due to new write
// leveling algorithm to avoid late writes
always @(posedge clk)
if (rst || (init_state_r == INIT_WRCAL_WRITE_READ) ||
(wrcal_wr_cnt == 4'd0))
wrcal_wr_cnt <= #TCQ NUM_STG1_WR_RD;
else if ((init_state_r == INIT_WRCAL_WRITE) &&
new_burst_r && ~phy_data_full)
wrcal_wr_cnt <= #TCQ wrcal_wr_cnt - 1;
generate
if(nCK_PER_CLK == 4) begin:back_to_back_reads_4_1
// 4 back-to-back reads with gaps for
// read data_offset calibration (rdlvl stage 2)
always @(posedge clk)
if (rst || (init_state_r == INIT_RDLVL_STG2_READ_WAIT))
num_reads <= #TCQ 3'b000;
else if ((num_reads > 3'b000) && ~(phy_ctl_full || phy_cmd_full))
num_reads <= #TCQ num_reads - 1;
else if ((init_state_r == INIT_RDLVL_STG2_READ) || phy_ctl_full ||
phy_cmd_full && new_burst_r)
num_reads <= #TCQ 3'b011;
end else if(nCK_PER_CLK == 2) begin: back_to_back_reads_2_1
// 4 back-to-back reads with gaps for
// read data_offset calibration (rdlvl stage 2)
always @(posedge clk)
if (rst || (init_state_r == INIT_RDLVL_STG2_READ_WAIT))
num_reads <= #TCQ 3'b000;
else if ((num_reads > 3'b000) && ~(phy_ctl_full || phy_cmd_full))
num_reads <= #TCQ num_reads - 1;
else if ((init_state_r == INIT_RDLVL_STG2_READ) || phy_ctl_full ||
phy_cmd_full && new_burst_r)
num_reads <= #TCQ 3'b111;
end
endgenerate
// back-to-back reads during write calibration
always @(posedge clk)
if (rst ||(init_state_r == INIT_WRCAL_READ_WAIT))
wrcal_reads <= #TCQ 2'b00;
else if ((wrcal_reads > 2'b00) && ~(phy_ctl_full || phy_cmd_full))
wrcal_reads <= #TCQ wrcal_reads - 1;
else if ((init_state_r == INIT_WRCAL_MULT_READS) || phy_ctl_full ||
phy_cmd_full && new_burst_r)
wrcal_reads <= #TCQ 'd255;
// determine how often to issue row command during read leveling writes
// and reads
always @(posedge clk)
if (rdlvl_wr_rd) begin
// 2:1 mode - every other command issued is a data command
// 4:1 mode - every command issued is a data command
if (nCK_PER_CLK == 2) begin
if (!phy_ctl_full)
new_burst_r <= #TCQ ~new_burst_r;
end else
new_burst_r <= #TCQ 1'b1;
end else
new_burst_r <= #TCQ 1'b1;
// indicate when a write is occurring. PHY_WRDATA_EN must be asserted
// simultaneous with the corresponding command/address for CWL = 5,6
always @(posedge clk) begin
rdlvl_wr_r <= #TCQ rdlvl_wr;
calib_wrdata_en <= #TCQ phy_wrdata_en;
end
always @(posedge clk) begin
if (rst || wrcal_done)
extend_cal_pat <= #TCQ 1'b0;
else if (temp_lmr_done && (PRE_REV3ES == "ON"))
extend_cal_pat <= #TCQ 1'b1;
end
generate
if ((nCK_PER_CLK == 4) || (BURST_MODE == "4")) begin: wrdqen_div4
// Write data enable asserted for one DIV4 clock cycle
// Only BL8 supported with DIV4. DDR2 BL4 will use DIV2.
always @(rst or phy_data_full or init_state_r) begin
if (~phy_data_full && ((init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_OCLKDELAY_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE)))
phy_wrdata_en = 1'b1;
else
phy_wrdata_en = 1'b0;
end
end else begin: wrdqen_div2 // block: wrdqen_div4
always @(rdlvl_wr or phy_ctl_full or new_burst_r or phy_wrdata_en_r1
or phy_data_full)
if((rdlvl_wr & ~phy_ctl_full & new_burst_r & ~phy_data_full)
| phy_wrdata_en_r1)
phy_wrdata_en = 1'b1;
else
phy_wrdata_en = 1'b0;
always @(posedge clk)
phy_wrdata_en_r1 <= #TCQ rdlvl_wr & ~phy_ctl_full & new_burst_r
& ~phy_data_full;
always @(posedge clk) begin
if (!phy_wrdata_en & first_rdlvl_pat_r)
wrdata_pat_cnt <= #TCQ 2'b00;
else if (wrdata_pat_cnt == 2'b11)
wrdata_pat_cnt <= #TCQ 2'b10;
else
wrdata_pat_cnt <= #TCQ wrdata_pat_cnt + 1;
end
always @(posedge clk) begin
if (!phy_wrdata_en & first_wrcal_pat_r)
wrcal_pat_cnt <= #TCQ 2'b00;
else if (extend_cal_pat && (wrcal_pat_cnt == 2'b01))
wrcal_pat_cnt <= #TCQ 2'b00;
else if (wrcal_pat_cnt == 2'b11)
wrcal_pat_cnt <= #TCQ 2'b10;
else
wrcal_pat_cnt <= #TCQ wrcal_pat_cnt + 1;
end
end
endgenerate
// indicate when a write is occurring. PHY_RDDATA_EN must be asserted
// simultaneous with the corresponding command/address. PHY_RDDATA_EN
// is used during read-leveling to determine read latency
assign phy_rddata_en = ~phy_if_empty;
// Read data valid generation for MC and User Interface after calibration is
// complete
assign phy_rddata_valid = init_complete_r1_timing ? phy_rddata_en : 1'b0;
//***************************************************************************
// Generate training data written at start of each read-leveling stage
// For every stage of read leveling, 8 words are written into memory
// The format is as follows (shown as {rise,fall}):
// Stage 1: 0xF, 0x0, 0xF, 0x0, 0xF, 0x0, 0xF, 0x0
// Stage 2: 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6
//***************************************************************************
always @(posedge clk)
if ((init_state_r == INIT_IDLE) ||
(init_state_r == INIT_RDLVL_STG1_WRITE))
cnt_init_data_r <= #TCQ 2'b00;
else if (phy_wrdata_en)
cnt_init_data_r <= #TCQ cnt_init_data_r + 1;
else if (init_state_r == INIT_WRCAL_WRITE)
cnt_init_data_r <= #TCQ 2'b10;
// write different sequence for very
// first write to memory only. Used to help us differentiate
// if the writes are "early" or "on-time" during read leveling
always @(posedge clk)
if (rst || rdlvl_stg1_rank_done)
first_rdlvl_pat_r <= #TCQ 1'b1;
else if (phy_wrdata_en && (init_state_r == INIT_RDLVL_STG1_WRITE))
first_rdlvl_pat_r <= #TCQ 1'b0;
always @(posedge clk)
if (rst || wrcal_resume ||
(init_state_r == INIT_WRCAL_ACT_WAIT))
first_wrcal_pat_r <= #TCQ 1'b1;
else if (phy_wrdata_en && (init_state_r == INIT_WRCAL_WRITE))
first_wrcal_pat_r <= #TCQ 1'b0;
generate
if ((CLK_PERIOD/nCK_PER_CLK > 2500) && (nCK_PER_CLK == 2)) begin: wrdq_div2_2to1_rdlvl_first
always @(posedge clk)
if (~oclkdelay_calib_done)
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}},
{DQ_WIDTH/4{4'h0}},
{DQ_WIDTH/4{4'hF}},
{DQ_WIDTH/4{4'h0}}};
else if (!rdlvl_stg1_done) begin
// The 16 words for stage 1 write data in 2:1 mode is written
// over 4 consecutive controller clock cycles. Note that write
// data follows phy_wrdata_en by one clock cycle
case (wrdata_pat_cnt)
2'b00: begin
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}},
{DQ_WIDTH/4{4'h7}},
{DQ_WIDTH/4{4'h3}},
{DQ_WIDTH/4{4'h9}}};
end
2'b01: begin
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},
{DQ_WIDTH/4{4'h2}},
{DQ_WIDTH/4{4'h9}},
{DQ_WIDTH/4{4'hC}}};
end
2'b10: begin
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}},
{DQ_WIDTH/4{4'h7}},
{DQ_WIDTH/4{4'h1}},
{DQ_WIDTH/4{4'hB}}};
end
2'b11: begin
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},
{DQ_WIDTH/4{4'h2}},
{DQ_WIDTH/4{4'h9}},
{DQ_WIDTH/4{4'hC}}};
end
endcase
end else if (!prbs_rdlvl_done && ~phy_data_full) begin
// prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in
// prbs_o being concatenated 8 times resulting in DQ_WIDTH
phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[4*8-1:3*8]}},
{DQ_WIDTH/8{prbs_o[3*8-1:2*8]}},
{DQ_WIDTH/8{prbs_o[2*8-1:8]}},
{DQ_WIDTH/8{prbs_o[8-1:0]}}};
end else if (!wrcal_done) begin
case (wrcal_pat_cnt)
2'b00: begin
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h5}},
{DQ_WIDTH/4{4'hA}},
{DQ_WIDTH/4{4'h0}},
{DQ_WIDTH/4{4'hF}}};
end
2'b01: begin
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},
{DQ_WIDTH/4{4'h9}},
{DQ_WIDTH/4{4'hA}},
{DQ_WIDTH/4{4'h5}}};
end
2'b10: begin
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},
{DQ_WIDTH/4{4'hE}},
{DQ_WIDTH/4{4'h1}},
{DQ_WIDTH/4{4'hB}}};
end
2'b11: begin
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}},
{DQ_WIDTH/4{4'hD}},
{DQ_WIDTH/4{4'hE}},
{DQ_WIDTH/4{4'h4}}};
end
endcase
end
end else if ((CLK_PERIOD/nCK_PER_CLK > 2500) && (nCK_PER_CLK == 4)) begin: wrdq_div2_4to1_rdlvl_first
always @(posedge clk)
if (~oclkdelay_calib_done)
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}},
{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}},
{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}},
{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}};
else if (!rdlvl_stg1_done && ~phy_data_full)
// write different sequence for very
// first write to memory only. Used to help us differentiate
// if the writes are "early" or "on-time" during read leveling
if (first_rdlvl_pat_r)
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}},
{DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}},
{DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}},
{DQ_WIDTH/4{4'h3}},{DQ_WIDTH/4{4'h9}}};
else
// For all others, change the first two words written in order
// to differentiate the "early write" and "on-time write"
// readback patterns during read leveling
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}},
{DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}},
{DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}},
{DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}};
else if (!prbs_rdlvl_done && ~phy_data_full)
// prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in
// prbs_o being concatenated 8 times resulting in DQ_WIDTH
phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[8*8-1:7*8]}},{DQ_WIDTH/8{prbs_o[7*8-1:6*8]}},
{DQ_WIDTH/8{prbs_o[6*8-1:5*8]}},{DQ_WIDTH/8{prbs_o[5*8-1:4*8]}},
{DQ_WIDTH/8{prbs_o[4*8-1:3*8]}},{DQ_WIDTH/8{prbs_o[3*8-1:2*8]}},
{DQ_WIDTH/8{prbs_o[2*8-1:8]}},{DQ_WIDTH/8{prbs_o[8-1:0]}}};
else if (!wrcal_done)
if (first_wrcal_pat_r)
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}},
{DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}},
{DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}},
{DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}};
else
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}},{DQ_WIDTH/4{4'hD}},
{DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h4}},
{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'hE}},
{DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}};
end else if (nCK_PER_CLK == 4) begin: wrdq_div1_4to1_wrcal_first
always @(posedge clk)
if ((~oclkdelay_calib_done) && (DRAM_TYPE == "DDR3"))
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}},
{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}},
{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}},
{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}};
else if ((!wrcal_done)&& (DRAM_TYPE == "DDR3")) begin
if (extend_cal_pat)
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}},
{DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}},
{DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}},
{DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}};
else if (first_wrcal_pat_r)
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}},
{DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}},
{DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}},
{DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}};
else
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}},{DQ_WIDTH/4{4'hD}},
{DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h4}},
{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'hE}},
{DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}};
end else if (!rdlvl_stg1_done && ~phy_data_full) begin
// write different sequence for very
// first write to memory only. Used to help us differentiate
// if the writes are "early" or "on-time" during read leveling
if (first_rdlvl_pat_r)
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}},
{DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}},
{DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}},
{DQ_WIDTH/4{4'h3}},{DQ_WIDTH/4{4'h9}}};
else
// For all others, change the first two words written in order
// to differentiate the "early write" and "on-time write"
// readback patterns during read leveling
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}},
{DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}},
{DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}},
{DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}};
end else if (!prbs_rdlvl_done && ~phy_data_full)
// prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in
// prbs_o being concatenated 8 times resulting in DQ_WIDTH
phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[8*8-1:7*8]}},{DQ_WIDTH/8{prbs_o[7*8-1:6*8]}},
{DQ_WIDTH/8{prbs_o[6*8-1:5*8]}},{DQ_WIDTH/8{prbs_o[5*8-1:4*8]}},
{DQ_WIDTH/8{prbs_o[4*8-1:3*8]}},{DQ_WIDTH/8{prbs_o[3*8-1:2*8]}},
{DQ_WIDTH/8{prbs_o[2*8-1:8]}},{DQ_WIDTH/8{prbs_o[8-1:0]}}};
end else begin: wrdq_div1_2to1_wrcal_first
always @(posedge clk)
if ((~oclkdelay_calib_done)&& (DRAM_TYPE == "DDR3"))
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}},
{DQ_WIDTH/4{4'h0}},
{DQ_WIDTH/4{4'hF}},
{DQ_WIDTH/4{4'h0}}};
else if ((!wrcal_done) && (DRAM_TYPE == "DDR3"))begin
case (wrcal_pat_cnt)
2'b00: begin
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h5}},
{DQ_WIDTH/4{4'hA}},
{DQ_WIDTH/4{4'h0}},
{DQ_WIDTH/4{4'hF}}};
end
2'b01: begin
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},
{DQ_WIDTH/4{4'h9}},
{DQ_WIDTH/4{4'hA}},
{DQ_WIDTH/4{4'h5}}};
end
2'b10: begin
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},
{DQ_WIDTH/4{4'hE}},
{DQ_WIDTH/4{4'h1}},
{DQ_WIDTH/4{4'hB}}};
end
2'b11: begin
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}},
{DQ_WIDTH/4{4'hD}},
{DQ_WIDTH/4{4'hE}},
{DQ_WIDTH/4{4'h4}}};
end
endcase
end else if (!rdlvl_stg1_done) begin
// The 16 words for stage 1 write data in 2:1 mode is written
// over 4 consecutive controller clock cycles. Note that write
// data follows phy_wrdata_en by one clock cycle
case (wrdata_pat_cnt)
2'b00: begin
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}},
{DQ_WIDTH/4{4'h7}},
{DQ_WIDTH/4{4'h3}},
{DQ_WIDTH/4{4'h9}}};
end
2'b01: begin
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},
{DQ_WIDTH/4{4'h2}},
{DQ_WIDTH/4{4'h9}},
{DQ_WIDTH/4{4'hC}}};
end
2'b10: begin
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}},
{DQ_WIDTH/4{4'h7}},
{DQ_WIDTH/4{4'h1}},
{DQ_WIDTH/4{4'hB}}};
end
2'b11: begin
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},
{DQ_WIDTH/4{4'h2}},
{DQ_WIDTH/4{4'h9}},
{DQ_WIDTH/4{4'hC}}};
end
endcase
end else if (!prbs_rdlvl_done && ~phy_data_full) begin
// prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in
// prbs_o being concatenated 8 times resulting in DQ_WIDTH
phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[4*8-1:3*8]}},
{DQ_WIDTH/8{prbs_o[3*8-1:2*8]}},
{DQ_WIDTH/8{prbs_o[2*8-1:8]}},
{DQ_WIDTH/8{prbs_o[8-1:0]}}};
end
end
endgenerate
//***************************************************************************
// Memory control/address
//***************************************************************************
// Phases [2] and [3] are always deasserted for 4:1 mode
generate
if (nCK_PER_CLK == 4) begin: gen_div4_ca_tieoff
always @(posedge clk) begin
phy_ras_n[3:2] <= #TCQ 3'b11;
phy_cas_n[3:2] <= #TCQ 3'b11;
phy_we_n[3:2] <= #TCQ 3'b11;
end
end
endgenerate
// Assert RAS when: (1) Loading MRS, (2) Activating Row, (3) Precharging
// (4) auto refresh
generate
if (!(CWL_M % 2)) begin: even_cwl
always @(posedge clk) begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_MPR_RDEN) ||
(init_state_r == INIT_MPR_DISABLE) ||
(init_state_r == INIT_REG_WRITE) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_WRCAL_ACT) ||
(init_state_r == INIT_OCLKDELAY_ACT) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE) ||
(init_state_r == INIT_REFRESH))begin
phy_ras_n[0] <= #TCQ 1'b0;
phy_ras_n[1] <= #TCQ 1'b1;
end else begin
phy_ras_n[0] <= #TCQ 1'b1;
phy_ras_n[1] <= #TCQ 1'b1;
end
end
// Assert CAS when: (1) Loading MRS, (2) Issuing Read/Write command
// (3) auto refresh
always @(posedge clk) begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_MPR_RDEN) ||
(init_state_r == INIT_MPR_DISABLE) ||
(init_state_r == INIT_REG_WRITE) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_REFRESH) ||
(rdlvl_wr_rd && new_burst_r))begin
phy_cas_n[0] <= #TCQ 1'b0;
phy_cas_n[1] <= #TCQ 1'b1;
end else begin
phy_cas_n[0] <= #TCQ 1'b1;
phy_cas_n[1] <= #TCQ 1'b1;
end
end
// Assert WE when: (1) Loading MRS, (2) Issuing Write command (only
// occur during read leveling), (3) Issuing ZQ Long Calib command,
// (4) Precharge
always @(posedge clk) begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_MPR_RDEN) ||
(init_state_r == INIT_MPR_DISABLE) ||
(init_state_r == INIT_REG_WRITE) ||
(init_state_r == INIT_ZQCL) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE)||
(rdlvl_wr && new_burst_r))begin
phy_we_n[0] <= #TCQ 1'b0;
phy_we_n[1] <= #TCQ 1'b1;
end else begin
phy_we_n[0] <= #TCQ 1'b1;
phy_we_n[1] <= #TCQ 1'b1;
end
end
end else begin: odd_cwl
always @(posedge clk) begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_MPR_RDEN) ||
(init_state_r == INIT_MPR_DISABLE) ||
(init_state_r == INIT_REG_WRITE) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_WRCAL_ACT) ||
(init_state_r == INIT_OCLKDELAY_ACT) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE) ||
(init_state_r == INIT_REFRESH))begin
phy_ras_n[0] <= #TCQ 1'b1;
phy_ras_n[1] <= #TCQ 1'b0;
end else begin
phy_ras_n[0] <= #TCQ 1'b1;
phy_ras_n[1] <= #TCQ 1'b1;
end
end
// Assert CAS when: (1) Loading MRS, (2) Issuing Read/Write command
// (3) auto refresh
always @(posedge clk) begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_MPR_RDEN) ||
(init_state_r == INIT_MPR_DISABLE) ||
(init_state_r == INIT_REG_WRITE) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_REFRESH) ||
(rdlvl_wr_rd && new_burst_r))begin
phy_cas_n[0] <= #TCQ 1'b1;
phy_cas_n[1] <= #TCQ 1'b0;
end else begin
phy_cas_n[0] <= #TCQ 1'b1;
phy_cas_n[1] <= #TCQ 1'b1;
end
end
// Assert WE when: (1) Loading MRS, (2) Issuing Write command (only
// occur during read leveling), (3) Issuing ZQ Long Calib command,
// (4) Precharge
always @(posedge clk) begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_MPR_RDEN) ||
(init_state_r == INIT_MPR_DISABLE) ||
(init_state_r == INIT_REG_WRITE) ||
(init_state_r == INIT_ZQCL) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE)||
(rdlvl_wr && new_burst_r))begin
phy_we_n[0] <= #TCQ 1'b1;
phy_we_n[1] <= #TCQ 1'b0;
end else begin
phy_we_n[0] <= #TCQ 1'b1;
phy_we_n[1] <= #TCQ 1'b1;
end
end
end
endgenerate
// Assign calib_cmd for the command field in PHY_Ctl_Word
always @(posedge clk) begin
if (wr_level_dqs_asrt) begin
// Request to toggle DQS during write leveling
calib_cmd <= #TCQ 3'b001;
if (CWL_M % 2) begin // odd write latency
calib_data_offset_0 <= #TCQ CWL_M + 3;
calib_data_offset_1 <= #TCQ CWL_M + 3;
calib_data_offset_2 <= #TCQ CWL_M + 3;
calib_cas_slot <= #TCQ 2'b01;
end else begin // even write latency
calib_data_offset_0 <= #TCQ CWL_M + 2;
calib_data_offset_1 <= #TCQ CWL_M + 2;
calib_data_offset_2 <= #TCQ CWL_M + 2;
calib_cas_slot <= #TCQ 2'b00;
end
end else if (rdlvl_wr && new_burst_r) begin
// Write Command
calib_cmd <= #TCQ 3'b001;
if (CWL_M % 2) begin // odd write latency
calib_data_offset_0 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1;
calib_data_offset_1 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1;
calib_data_offset_2 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1;
calib_cas_slot <= #TCQ 2'b01;
end else begin // even write latency
calib_data_offset_0 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ;
calib_data_offset_1 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ;
calib_data_offset_2 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ;
calib_cas_slot <= #TCQ 2'b00;
end
end else if (rdlvl_rd && new_burst_r) begin
// Read Command
calib_cmd <= #TCQ 3'b011;
if (CWL_M % 2)
calib_cas_slot <= #TCQ 2'b01;
else
calib_cas_slot <= #TCQ 2'b00;
if (~pi_calib_done_r1) begin
calib_data_offset_0 <= #TCQ 6'd0;
calib_data_offset_1 <= #TCQ 6'd0;
calib_data_offset_2 <= #TCQ 6'd0;
end else if (~pi_dqs_found_done_r1) begin
calib_data_offset_0 <= #TCQ rd_data_offset_0;
calib_data_offset_1 <= #TCQ rd_data_offset_1;
calib_data_offset_2 <= #TCQ rd_data_offset_2;
end else begin
calib_data_offset_0 <= #TCQ rd_data_offset_ranks_0[6*chip_cnt_r+:6];
calib_data_offset_1 <= #TCQ rd_data_offset_ranks_1[6*chip_cnt_r+:6];
calib_data_offset_2 <= #TCQ rd_data_offset_ranks_2[6*chip_cnt_r+:6];
end
end else begin
// Non-Data Commands like NOP, MRS, ZQ Long Cal, Precharge,
// Active, Refresh
calib_cmd <= #TCQ 3'b100;
calib_data_offset_0 <= #TCQ 6'd0;
calib_data_offset_1 <= #TCQ 6'd0;
calib_data_offset_2 <= #TCQ 6'd0;
if (CWL_M % 2)
calib_cas_slot <= #TCQ 2'b01;
else
calib_cas_slot <= #TCQ 2'b00;
end
end
// Write Enable to PHY_Control FIFO always asserted
// No danger of this FIFO being Full with 4:1 sync clock ratio
// This is also the write enable to the command OUT_FIFO
always @(posedge clk) begin
if (rst) begin
calib_ctl_wren <= #TCQ 1'b0;
calib_cmd_wren <= #TCQ 1'b0;
calib_seq <= #TCQ 2'b00;
end else if (cnt_pwron_cke_done_r && phy_ctl_ready
&& ~(phy_ctl_full || phy_cmd_full )) begin
calib_ctl_wren <= #TCQ 1'b1;
calib_cmd_wren <= #TCQ 1'b1;
calib_seq <= #TCQ calib_seq + 1;
end else begin
calib_ctl_wren <= #TCQ 1'b0;
calib_cmd_wren <= #TCQ 1'b0;
calib_seq <= #TCQ calib_seq;
end
end
generate
genvar rnk_i;
for (rnk_i = 0; rnk_i < 4; rnk_i = rnk_i + 1) begin: gen_rnk
always @(posedge clk) begin
if (rst) begin
mr2_r[rnk_i] <= #TCQ 2'b00;
mr1_r[rnk_i] <= #TCQ 3'b000;
end else begin
mr2_r[rnk_i] <= #TCQ tmp_mr2_r[rnk_i];
mr1_r[rnk_i] <= #TCQ tmp_mr1_r[rnk_i];
end
end
end
endgenerate
// ODT assignment based on slot config and slot present
// For single slot systems slot_1_present input will be ignored
// Assuming component interfaces to be single slot systems
generate
if (nSLOTS == 1) begin: gen_single_slot_odt
always @(posedge clk) begin
if (rst) begin
tmp_mr2_r[1] <= #TCQ 2'b00;
tmp_mr2_r[2] <= #TCQ 2'b00;
tmp_mr2_r[3] <= #TCQ 2'b00;
tmp_mr1_r[1] <= #TCQ 3'b000;
tmp_mr1_r[2] <= #TCQ 3'b000;
tmp_mr1_r[3] <= #TCQ 3'b000;
phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}};
phy_tmp_odt_r <= #TCQ 4'b0000;
phy_tmp_odt_r1 <= #TCQ phy_tmp_odt_r;
end else begin
case ({slot_0_present[0],slot_0_present[1],
slot_0_present[2],slot_0_present[3]})
// Single slot configuration with quad rank
// Assuming same behavior as single slot dual rank for now
// DDR2 does not have quad rank parts
4'b1111: begin
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 RTT_NOM
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
3'b000;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 RTT_NOM after write leveling completes
tmp_mr1_r[0] <= #TCQ 3'b000;
end
phy_tmp_odt_r <= #TCQ 4'b0001;
// Chip Select assignments
phy_tmp_cs1_r[((chip_cnt_r*nCS_PER_RANK)
) +: nCS_PER_RANK] <= #TCQ 'b0;
end
// Single slot configuration with single rank
4'b1000: begin
phy_tmp_odt_r <= #TCQ 4'b0001;
if ((REG_CTRL == "ON") && (nCS_PER_RANK > 1)) begin
phy_tmp_cs1_r[chip_cnt_r] <= #TCQ 1'b0;
end else begin
phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
end
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
((cnt_init_mr_r == 2'd0) || (USE_ODT_PORT == 1)))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 RTT_NOM
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
3'b000;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 RTT_NOM after write leveling completes
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
// Single slot configuration with dual rank
4'b1100: begin
phy_tmp_odt_r <= #TCQ 4'b0001;
// Chip Select assignments
phy_tmp_cs1_r[((chip_cnt_r*nCS_PER_RANK)
) +: nCS_PER_RANK] <= #TCQ 'b0;
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
3'b000;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM after write leveling completes
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
default: begin
phy_tmp_odt_r <= #TCQ 4'b0001;
phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done)) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
3'b000;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM after write leveling completes
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
endcase
end
end
end else if (nSLOTS == 2) begin: gen_dual_slot_odt
always @ (posedge clk) begin
if (rst) begin
tmp_mr2_r[1] <= #TCQ 2'b00;
tmp_mr2_r[2] <= #TCQ 2'b00;
tmp_mr2_r[3] <= #TCQ 2'b00;
tmp_mr1_r[1] <= #TCQ 3'b000;
tmp_mr1_r[2] <= #TCQ 3'b000;
tmp_mr1_r[3] <= #TCQ 3'b000;
phy_tmp_odt_r <= #TCQ 4'b0000;
phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}};
phy_tmp_odt_r1 <= #TCQ phy_tmp_odt_r;
end else begin
case ({slot_0_present[0],slot_0_present[1],
slot_1_present[0],slot_1_present[1]})
// Two slot configuration, one slot present, single rank
4'b10_00: begin
if (//wrlvl_odt ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_OCLKDELAY_WRITE)) begin
// odt turned on only during write
phy_tmp_odt_r <= #TCQ 4'b0001;
end
phy_tmp_cs1_r <= #TCQ {nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done)) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
3'b000;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM after write leveling completes
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
4'b00_10: begin
//Rank1 ODT enabled
if (//wrlvl_odt ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_OCLKDELAY_WRITE)) begin
// odt turned on only during write
phy_tmp_odt_r <= #TCQ 4'b0001;
end
phy_tmp_cs1_r <= #TCQ {nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done)) begin
//Rank1 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank1 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
3'b000;
end else begin
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM after write leveling completes
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
// Two slot configuration, one slot present, dual rank
4'b00_11: begin
if (//wrlvl_odt ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_OCLKDELAY_WRITE)) begin
// odt turned on only during write
phy_tmp_odt_r
<= #TCQ 4'b0001;
end
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
3'b000;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM after write leveling completes
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
4'b11_00: begin
if (//wrlvl_odt ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_OCLKDELAY_WRITE)) begin
// odt turned on only during write
phy_tmp_odt_r <= #TCQ 4'b0001;
end
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank1 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank1 Rtt_NOM
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
3'b000;
end else begin
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM after write leveling completes
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
// Two slot configuration, one rank per slot
4'b10_10: begin
if(DRAM_TYPE == "DDR2")begin
if(chip_cnt_r == 2'b00)begin
phy_tmp_odt_r
<= #TCQ 4'b0010; //bit0 for rank0
end else begin
phy_tmp_odt_r
<= #TCQ 4'b0001; //bit0 for rank0
end
end else begin
if(init_state_r == INIT_WRLVL_WAIT)
phy_tmp_odt_r <= #TCQ 4'b0011; // rank 0/1 odt0
else if((init_next_state == INIT_RDLVL_STG1_WRITE) ||
(init_next_state == INIT_WRCAL_WRITE) ||
(init_next_state == INIT_OCLKDELAY_WRITE))
phy_tmp_odt_r <= #TCQ 4'b0011; // bit0 for rank0/1 (write)
else if ((init_next_state == INIT_PI_PHASELOCK_READS) ||
(init_next_state == INIT_MPR_READ) ||
(init_next_state == INIT_RDLVL_STG1_READ) ||
(init_next_state == INIT_RDLVL_STG2_READ) ||
(init_next_state == INIT_OCLKDELAY_READ) ||
(init_next_state == INIT_WRCAL_READ) ||
(init_next_state == INIT_WRCAL_MULT_READS))
phy_tmp_odt_r <= #TCQ 4'b0010; // bit0 for rank1 (rank 0 rd)
end
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ (RTT_WR == "60") ? 3'b001 :
(RTT_WR == "120") ? 3'b010 :
3'b000;
//Rank1 Dynamic ODT disabled
tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM
tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
3'b000;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
(RTT_NOM_int == "20") ? 3'b100 :
(RTT_NOM_int == "30") ? 3'b101 :
(RTT_NOM_int == "40") ? 3'b011 :
3'b000;
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM
tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
(RTT_NOM_int == "20") ? 3'b100 :
(RTT_NOM_int == "30") ? 3'b101 :
(RTT_NOM_int == "40") ? 3'b011 :
3'b000;
end
end
// Two Slots - One slot with dual rank and other with single rank
4'b10_11: begin
//Rank3 Rtt_NOM
tmp_mr1_r[2] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
(RTT_NOM_int == "20") ? 3'b100 :
(RTT_NOM_int == "30") ? 3'b101 :
(RTT_NOM_int == "40") ? 3'b011 :
3'b000;
tmp_mr2_r[2] <= #TCQ 2'b00;
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
3'b000;
//Rank1 Dynamic ODT disabled
tmp_mr2_r[1] <= #TCQ 2'b00;
//Rank1 Rtt_NOM
tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
3'b000;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM after write leveling completes
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
(RTT_NOM_int == "20") ? 3'b100 :
(RTT_NOM_int == "30") ? 3'b101 :
(RTT_NOM_int == "40") ? 3'b011 :
3'b000;
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM after write leveling completes
tmp_mr1_r[1] <= #TCQ 3'b000;
end
//Slot1 Rank1 or Rank3 is being written
if(DRAM_TYPE == "DDR2")begin
if(chip_cnt_r == 2'b00)begin
phy_tmp_odt_r
<= #TCQ 4'b0010;
end else begin
phy_tmp_odt_r
<= #TCQ 4'b0001;
end
end else begin
if (//wrlvl_odt ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_OCLKDELAY_WRITE)) begin
if (chip_cnt_r[0] == 1'b1) begin
phy_tmp_odt_r
<= #TCQ 4'b0011;
//Slot0 Rank0 is being written
end else begin
phy_tmp_odt_r
<= #TCQ 4'b0101; // ODT for ranks 0 and 2 aserted
end
end else if ((init_state_r == INIT_RDLVL_STG1_READ)
|| (init_state_r == INIT_PI_PHASELOCK_READS) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_OCLKDELAY_READ) ||
(init_state_r == INIT_WRCAL_READ) ||
(init_state_r == INIT_WRCAL_MULT_READS))begin
if (chip_cnt_r == 2'b00) begin
phy_tmp_odt_r
<= #TCQ 4'b0100;
end else begin
phy_tmp_odt_r
<= #TCQ 4'b0001;
end
end
end
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
end
// Two Slots - One slot with dual rank and other with single rank
4'b11_10: begin
//Rank2 Rtt_NOM
tmp_mr1_r[2] <= #TCQ (RTT_NOM2 == "60") ? 3'b001 :
(RTT_NOM2 == "120") ? 3'b010 :
(RTT_NOM2 == "20") ? 3'b100 :
(RTT_NOM2 == "30") ? 3'b101 :
(RTT_NOM2 == "40") ? 3'b011:
3'b000;
tmp_mr2_r[2] <= #TCQ 2'b00;
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
3'b000;
//Rank1 Dynamic ODT disabled
tmp_mr2_r[1] <= #TCQ 2'b00;
//Rank1 Rtt_NOM
tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
3'b000;
end else begin
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM
tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
(RTT_NOM_int == "20") ? 3'b100 :
(RTT_NOM_int == "30") ? 3'b101 :
(RTT_NOM_int == "40") ? 3'b011:
3'b000;
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM after write leveling completes
tmp_mr1_r[0] <= #TCQ 3'b000;
end
if(DRAM_TYPE == "DDR2")begin
if(chip_cnt_r[1] == 1'b1)begin
phy_tmp_odt_r <=
#TCQ 4'b0001;
end else begin
phy_tmp_odt_r
<= #TCQ 4'b0100; // rank 2 ODT asserted
end
end else begin
if (// wrlvl_odt ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_OCLKDELAY_WRITE)) begin
if (chip_cnt_r[1] == 1'b1) begin
phy_tmp_odt_r
<= #TCQ 4'b0110;
end else begin
phy_tmp_odt_r <=
#TCQ 4'b0101;
end
end else if ((init_state_r == INIT_RDLVL_STG1_READ) ||
(init_state_r == INIT_PI_PHASELOCK_READS) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_OCLKDELAY_READ) ||
(init_state_r == INIT_WRCAL_READ) ||
(init_state_r == INIT_WRCAL_MULT_READS)) begin
if (chip_cnt_r[1] == 1'b1) begin
phy_tmp_odt_r[(1*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ 4'b0010;
end else begin
phy_tmp_odt_r
<= #TCQ 4'b0100;
end
end
end
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
end
// Two Slots - two ranks per slot
4'b11_11: begin
//Rank2 Rtt_NOM
tmp_mr1_r[2] <= #TCQ (RTT_NOM2 == "60") ? 3'b001 :
(RTT_NOM2 == "120") ? 3'b010 :
(RTT_NOM2 == "20") ? 3'b100 :
(RTT_NOM2 == "30") ? 3'b101 :
(RTT_NOM2 == "40") ? 3'b011 :
3'b000;
//Rank3 Rtt_NOM
tmp_mr1_r[3] <= #TCQ (RTT_NOM3 == "60") ? 3'b001 :
(RTT_NOM3 == "120") ? 3'b010 :
(RTT_NOM3 == "20") ? 3'b100 :
(RTT_NOM3 == "30") ? 3'b101 :
(RTT_NOM3 == "40") ? 3'b011 :
3'b000;
tmp_mr2_r[2] <= #TCQ 2'b00;
tmp_mr2_r[3] <= #TCQ 2'b00;
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
3'b000;
//Rank1 Dynamic ODT disabled
tmp_mr2_r[1] <= #TCQ 2'b00;
//Rank1 Rtt_NOM
tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
3'b000;
end else begin
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM after write leveling completes
tmp_mr1_r[1] <= #TCQ 3'b000;
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM after write leveling completes
tmp_mr1_r[0] <= #TCQ 3'b000;
end
if(DRAM_TYPE == "DDR2")begin
if(chip_cnt_r[1] == 1'b1)begin
phy_tmp_odt_r
<= #TCQ 4'b0001;
end else begin
phy_tmp_odt_r
<= #TCQ 4'b0100;
end
end else begin
if (//wrlvl_odt ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_OCLKDELAY_WRITE)) begin
//Slot1 Rank1 or Rank3 is being written
if (chip_cnt_r[0] == 1'b1) begin
phy_tmp_odt_r
<= #TCQ 4'b0110;
//Slot0 Rank0 or Rank2 is being written
end else begin
phy_tmp_odt_r
<= #TCQ 4'b1001;
end
end else if ((init_state_r == INIT_RDLVL_STG1_READ) ||
(init_state_r == INIT_PI_PHASELOCK_READS) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_OCLKDELAY_READ) ||
(init_state_r == INIT_WRCAL_READ) ||
(init_state_r == INIT_WRCAL_MULT_READS))begin
//Slot1 Rank1 or Rank3 is being read
if (chip_cnt_r[0] == 1'b1) begin
phy_tmp_odt_r
<= #TCQ 4'b0100;
//Slot0 Rank0 or Rank2 is being read
end else begin
phy_tmp_odt_r
<= #TCQ 4'b1000;
end
end
end
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
end
default: begin
phy_tmp_odt_r <= #TCQ 4'b1111;
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done)) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
3'b000;
//Rank1 Dynamic ODT disabled
tmp_mr2_r[1] <= #TCQ 2'b00;
//Rank1 Rtt_NOM
tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "60") ? 3'b010 :
3'b000;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
(RTT_NOM_int == "20") ? 3'b100 :
(RTT_NOM_int == "30") ? 3'b101 :
(RTT_NOM_int == "40") ? 3'b011 :
3'b000;
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM
tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
(RTT_NOM_int == "20") ? 3'b100 :
(RTT_NOM_int == "30") ? 3'b101 :
(RTT_NOM_int == "40") ? 3'b011 :
3'b000;
end
end
endcase
end
end
end
endgenerate
// PHY only supports two ranks.
// calib_aux_out[0] is CKE for rank 0 and calib_aux_out[1] is ODT for rank 0
// calib_aux_out[2] is CKE for rank 1 and calib_aux_out[3] is ODT for rank 1
generate
if(CKE_ODT_AUX == "FALSE") begin
if ((nSLOTS == 1) && (RANKS < 2)) begin
always @(posedge clk)
if (rst) begin
calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ;
calib_odt <= 2'b00 ;
end else begin
if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin
calib_cke <= #TCQ {nCK_PER_CLK{1'b1}};
end else begin
calib_cke <= #TCQ {nCK_PER_CLK{1'b0}};
end
if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF"))/* ||
wrlvl_rank_done || wrlvl_rank_done_r1 ||
(wrlvl_done && !wrlvl_done_r)*/) && (DRAM_TYPE == "DDR3")) begin
calib_odt[0] <= #TCQ 1'b0;
calib_odt[1] <= #TCQ 1'b0;
end else if (((DRAM_TYPE == "DDR3")
||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2")))
&& (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt ) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_RDLVL_STG1_WRITE_READ) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE_READ) ||
(init_state_r == INIT_OCLKDELAY_WRITE)||
(init_state_r == INIT_OCLKDELAY_WRITE_WAIT))) begin
// Quad rank in a single slot
calib_odt[0] <= #TCQ phy_tmp_odt_r[0];
calib_odt[1] <= #TCQ phy_tmp_odt_r[1];
end else begin
calib_odt[0] <= #TCQ 1'b0;
calib_odt[1] <= #TCQ 1'b0;
end
end
end else if ((nSLOTS == 1) && (RANKS <= 2)) begin
always @(posedge clk)
if (rst) begin
calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ;
calib_odt <= 2'b00 ;
end else begin
if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin
calib_cke <= #TCQ {nCK_PER_CLK{1'b1}};
end else begin
calib_cke <= #TCQ {nCK_PER_CLK{1'b0}};
end
if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF"))/* ||
wrlvl_rank_done_r2 ||
(wrlvl_done && !wrlvl_done_r)*/) && (DRAM_TYPE == "DDR3")) begin
calib_odt[0] <= #TCQ 1'b0;
calib_odt[1] <= #TCQ 1'b0;
end else if (((DRAM_TYPE == "DDR3")
||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2")))
&& (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt)||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_RDLVL_STG1_WRITE_READ) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE_READ) ||
(init_state_r == INIT_OCLKDELAY_WRITE)||
(init_state_r == INIT_OCLKDELAY_WRITE_WAIT))) begin
// Dual rank in a single slot
calib_odt[0] <= #TCQ phy_tmp_odt_r[0];
calib_odt[1] <= #TCQ phy_tmp_odt_r[1];
end else begin
calib_odt[0] <= #TCQ 1'b0;
calib_odt[1] <= #TCQ 1'b0;
end
end
end else if ((nSLOTS == 2) && (RANKS == 2)) begin
always @(posedge clk)
if (rst)begin
calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ;
calib_odt <= 2'b00 ;
end else begin
if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin
calib_cke <= #TCQ {nCK_PER_CLK{1'b1}};
end else begin
calib_cke <= #TCQ {nCK_PER_CLK{1'b0}};
end
if (((DRAM_TYPE == "DDR2") && (RTT_NOM == "DISABLED")) ||
((DRAM_TYPE == "DDR3") &&
(RTT_NOM == "DISABLED") && (RTT_WR == "OFF"))) begin
calib_odt[0] <= #TCQ 1'b0;
calib_odt[1] <= #TCQ 1'b0;
end else if (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_OCLKDELAY_WRITE)) begin
// Quad rank in a single slot
if (nCK_PER_CLK == 2) begin
calib_odt[0]
<= #TCQ (!calib_odt[0]) ? phy_tmp_odt_r[0] : 1'b0;
calib_odt[1]
<= #TCQ (!calib_odt[1]) ? phy_tmp_odt_r[1] : 1'b0;
end else begin
calib_odt[0] <= #TCQ phy_tmp_odt_r[0];
calib_odt[1] <= #TCQ phy_tmp_odt_r[1];
end
// Turn on for idle rank during read if dynamic ODT is enabled in DDR3
end else if(((DRAM_TYPE == "DDR3") && (RTT_WR != "OFF")) &&
((init_state_r == INIT_PI_PHASELOCK_READS) ||
(init_state_r == INIT_MPR_READ) ||
(init_state_r == INIT_RDLVL_STG1_READ) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_OCLKDELAY_READ) ||
(init_state_r == INIT_WRCAL_READ) ||
(init_state_r == INIT_WRCAL_MULT_READS))) begin
if (nCK_PER_CLK == 2) begin
calib_odt[0]
<= #TCQ (!calib_odt[0]) ? phy_tmp_odt_r[0] : 1'b0;
calib_odt[1]
<= #TCQ (!calib_odt[1]) ? phy_tmp_odt_r[1] : 1'b0;
end else begin
calib_odt[0] <= #TCQ phy_tmp_odt_r[0];
calib_odt[1] <= #TCQ phy_tmp_odt_r[1];
end
// disable well before next command and before disabling write leveling
end else if(cnt_cmd_done_m7_r ||
(init_state_r == INIT_WRLVL_WAIT && ~wrlvl_odt))
calib_odt <= #TCQ 2'b00;
end
end
end else begin//USE AUX OUTPUT for routing CKE and ODT.
if ((nSLOTS == 1) && (RANKS < 2)) begin
always @(posedge clk)
if (rst) begin
calib_aux_out <= #TCQ 4'b0000;
end else begin
if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin
calib_aux_out[0] <= #TCQ 1'b1;
calib_aux_out[2] <= #TCQ 1'b1;
end else begin
calib_aux_out[0] <= #TCQ 1'b0;
calib_aux_out[2] <= #TCQ 1'b0;
end
if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) ||
wrlvl_rank_done || wrlvl_rank_done_r1 ||
(wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin
calib_aux_out[1] <= #TCQ 1'b0;
calib_aux_out[3] <= #TCQ 1'b0;
end else if (((DRAM_TYPE == "DDR3")
||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2")))
&& (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_OCLKDELAY_WRITE))) begin
// Quad rank in a single slot
calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0];
calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1];
end else begin
calib_aux_out[1] <= #TCQ 1'b0;
calib_aux_out[3] <= #TCQ 1'b0;
end
end
end else if ((nSLOTS == 1) && (RANKS <= 2)) begin
always @(posedge clk)
if (rst) begin
calib_aux_out <= #TCQ 4'b0000;
end else begin
if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin
calib_aux_out[0] <= #TCQ 1'b1;
calib_aux_out[2] <= #TCQ 1'b1;
end else begin
calib_aux_out[0] <= #TCQ 1'b0;
calib_aux_out[2] <= #TCQ 1'b0;
end
if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) ||
wrlvl_rank_done_r2 ||
(wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin
calib_aux_out[1] <= #TCQ 1'b0;
calib_aux_out[3] <= #TCQ 1'b0;
end else if (((DRAM_TYPE == "DDR3")
||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2")))
&& (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_OCLKDELAY_WRITE))) begin
// Dual rank in a single slot
calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0];
calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1];
end else begin
calib_aux_out[1] <= #TCQ 1'b0;
calib_aux_out[3] <= #TCQ 1'b0;
end
end
end else if ((nSLOTS == 2) && (RANKS == 2)) begin
always @(posedge clk)
if (rst)
calib_aux_out <= #TCQ 4'b0000;
else begin
if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin
calib_aux_out[0] <= #TCQ 1'b1;
calib_aux_out[2] <= #TCQ 1'b1;
end else begin
calib_aux_out[0] <= #TCQ 1'b0;
calib_aux_out[2] <= #TCQ 1'b0;
end
if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) ||
wrlvl_rank_done_r2 ||
(wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin
calib_aux_out[1] <= #TCQ 1'b0;
calib_aux_out[3] <= #TCQ 1'b0;
end else if (((DRAM_TYPE == "DDR3")
||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2")))
&& (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_OCLKDELAY_WRITE))) begin
// Quad rank in a single slot
if (nCK_PER_CLK == 2) begin
calib_aux_out[1]
<= #TCQ (!calib_aux_out[1]) ? phy_tmp_odt_r[0] : 1'b0;
calib_aux_out[3]
<= #TCQ (!calib_aux_out[3]) ? phy_tmp_odt_r[1] : 1'b0;
end else begin
calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0];
calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1];
end
end else begin
calib_aux_out[1] <= #TCQ 1'b0;
calib_aux_out[3] <= #TCQ 1'b0;
end
end
end
end
endgenerate
//*****************************************************************
// memory address during init
//*****************************************************************
always @(posedge clk)
phy_data_full_r <= #TCQ phy_data_full;
always @(burst_addr_r or cnt_init_mr_r or chip_cnt_r or wrcal_wr_cnt
or ddr2_refresh_flag_r or init_state_r or load_mr0 or phy_data_full_r
or load_mr1 or load_mr2 or load_mr3 or new_burst_r or phy_address
or mr1_r[0][0] or mr1_r[0][1] or mr1_r[0][2]
or mr1_r[1][0] or mr1_r[1][1] or mr1_r[1][2]
or mr1_r[2][0] or mr1_r[2][1] or mr1_r[2][2]
or mr1_r[3][0] or mr1_r[3][1] or mr1_r[3][2]
or mr2_r[chip_cnt_r] or reg_ctrl_cnt_r or stg1_wr_rd_cnt or oclk_wr_cnt
or rdlvl_stg1_done or prbs_rdlvl_done or pi_dqs_found_done or rdlvl_wr_rd)begin
// Bus 0 for address/bank never used
address_w = 'b0;
bank_w = 'b0;
if ((init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_ZQCL) ||
(init_state_r == INIT_DDR2_PRECHARGE)) begin
// Set A10=1 for ZQ long calibration or Precharge All
address_w = 'b0;
address_w[10] = 1'b1;
bank_w = 'b0;
end else if (init_state_r == INIT_WRLVL_START) begin
// Enable wrlvl in MR1
bank_w[1:0] = 2'b01;
address_w = load_mr1[ROW_WIDTH-1:0];
address_w[2] = mr1_r[chip_cnt_r][0];
address_w[6] = mr1_r[chip_cnt_r][1];
address_w[9] = mr1_r[chip_cnt_r][2];
address_w[7] = 1'b1;
end else if (init_state_r == INIT_WRLVL_LOAD_MR) begin
// Finished with write leveling, disable wrlvl in MR1
// For single rank disable Rtt_Nom
bank_w[1:0] = 2'b01;
address_w = load_mr1[ROW_WIDTH-1:0];
address_w[2] = mr1_r[chip_cnt_r][0];
address_w[6] = mr1_r[chip_cnt_r][1];
address_w[9] = mr1_r[chip_cnt_r][2];
end else if (init_state_r == INIT_WRLVL_LOAD_MR2) begin
// Set RTT_WR in MR2 after write leveling disabled
bank_w[1:0] = 2'b10;
address_w = load_mr2[ROW_WIDTH-1:0];
address_w[10:9] = mr2_r[chip_cnt_r];
end else if (init_state_r == INIT_MPR_READ) begin
address_w = 'b0;
bank_w = 'b0;
end else if (init_state_r == INIT_MPR_RDEN) begin
// Enable MPR read with LMR3 and A2=1
bank_w[BANK_WIDTH-1:0] = 'd3;
address_w = {ROW_WIDTH{1'b0}};
address_w[2] = 1'b1;
end else if (init_state_r == INIT_MPR_DISABLE) begin
// Disable MPR read with LMR3 and A2=0
bank_w[BANK_WIDTH-1:0] = 'd3;
address_w = {ROW_WIDTH{1'b0}};
end else if ((init_state_r == INIT_REG_WRITE)&
(DRAM_TYPE == "DDR3"))begin
// bank_w is assigned a 3 bit value. In some
// DDR2 cases there will be only two bank bits.
//Qualifying the condition with DDR3
bank_w = 'b0;
address_w = 'b0;
case (reg_ctrl_cnt_r)
REG_RC0[2:0]: address_w[4:0] = REG_RC0[4:0];
REG_RC1[2:0]:begin
address_w[4:0] = REG_RC1[4:0];
bank_w = REG_RC1[7:5];
end
REG_RC2[2:0]: address_w[4:0] = REG_RC2[4:0];
REG_RC3[2:0]: address_w[4:0] = REG_RC3[4:0];
REG_RC4[2:0]: address_w[4:0] = REG_RC4[4:0];
REG_RC5[2:0]: address_w[4:0] = REG_RC5[4:0];
endcase
end else if (init_state_r == INIT_LOAD_MR) begin
// If loading mode register, look at cnt_init_mr to determine
// which MR is currently being programmed
address_w = 'b0;
bank_w = 'b0;
if(DRAM_TYPE == "DDR3")begin
if(rdlvl_stg1_done && prbs_rdlvl_done && pi_dqs_found_done)begin
// end of the calibration programming correct
// burst length
if (TEST_AL == "0") begin
bank_w[1:0] = 2'b00;
address_w = load_mr0[ROW_WIDTH-1:0];
address_w[8]= 1'b0; //Don't reset DLL
end else begin
// programming correct AL value
bank_w[1:0] = 2'b01;
address_w = load_mr1[ROW_WIDTH-1:0];
if (TEST_AL == "CL-1")
address_w[4:3]= 2'b01; // AL="CL-1"
else
address_w[4:3]= 2'b10; // AL="CL-2"
end
end else begin
case (cnt_init_mr_r)
INIT_CNT_MR2: begin
bank_w[1:0] = 2'b10;
address_w = load_mr2[ROW_WIDTH-1:0];
address_w[10:9] = mr2_r[chip_cnt_r];
end
INIT_CNT_MR3: begin
bank_w[1:0] = 2'b11;
address_w = load_mr3[ROW_WIDTH-1:0];
end
INIT_CNT_MR1: begin
bank_w[1:0] = 2'b01;
address_w = load_mr1[ROW_WIDTH-1:0];
address_w[2] = mr1_r[chip_cnt_r][0];
address_w[6] = mr1_r[chip_cnt_r][1];
address_w[9] = mr1_r[chip_cnt_r][2];
end
INIT_CNT_MR0: begin
bank_w[1:0] = 2'b00;
address_w = load_mr0[ROW_WIDTH-1:0];
// fixing it to BL8 for calibration
address_w[1:0] = 2'b00;
end
default: begin
bank_w = {BANK_WIDTH{1'bx}};
address_w = {ROW_WIDTH{1'bx}};
end
endcase
end
end else begin // DDR2
case (cnt_init_mr_r)
INIT_CNT_MR2: begin
if(~ddr2_refresh_flag_r)begin
bank_w[1:0] = 2'b10;
address_w = load_mr2[ROW_WIDTH-1:0];
end else begin // second set of lm commands
bank_w[1:0] = 2'b00;
address_w = load_mr0[ROW_WIDTH-1:0];
address_w[8]= 1'b0;
//MRS command without resetting DLL
end
end
INIT_CNT_MR3: begin
if(~ddr2_refresh_flag_r)begin
bank_w[1:0] = 2'b11;
address_w = load_mr3[ROW_WIDTH-1:0];
end else begin // second set of lm commands
bank_w[1:0] = 2'b00;
address_w = load_mr0[ROW_WIDTH-1:0];
address_w[8]= 1'b0;
//MRS command without resetting DLL. Repeted again
// because there is an extra state.
end
end
INIT_CNT_MR1: begin
bank_w[1:0] = 2'b01;
if(~ddr2_refresh_flag_r)begin
address_w = load_mr1[ROW_WIDTH-1:0];
end else begin // second set of lm commands
address_w = load_mr1[ROW_WIDTH-1:0];
address_w[9:7] = 3'b111;
//OCD default state
end
end
INIT_CNT_MR0: begin
if(~ddr2_refresh_flag_r)begin
bank_w[1:0] = 2'b00;
address_w = load_mr0[ROW_WIDTH-1:0];
end else begin // second set of lm commands
bank_w[1:0] = 2'b01;
address_w = load_mr1[ROW_WIDTH-1:0];
if((chip_cnt_r == 2'd1) || (chip_cnt_r == 2'd3))begin
// always disable odt for rank 1 and rank 3 as per SPEC
address_w[2] = 'b0;
address_w[6] = 'b0;
end
//OCD exit
end
end
default: begin
bank_w = {BANK_WIDTH{1'bx}};
address_w = {ROW_WIDTH{1'bx}};
end
endcase
end
end else if ((init_state_r == INIT_PI_PHASELOCK_READS) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_RDLVL_STG1_READ)) begin
// Writing and reading PRBS pattern for read leveling stage 1
// Need to support burst length 4 or 8. PRBS pattern will be
// written to entire row and read back from the same row repeatedly
bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0];
address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}};
if (((stg1_wr_rd_cnt == NUM_STG1_WR_RD) && ~rdlvl_stg1_done) || (stg1_wr_rd_cnt == 'd128))
address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}};
else if (phy_data_full_r || (!new_burst_r))
address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0];
else if ((stg1_wr_rd_cnt >= 9'd0) && new_burst_r && ~phy_data_full_r)
address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC;
end else if ((init_state_r == INIT_OCLKDELAY_WRITE) ||
(init_state_r == INIT_OCLKDELAY_READ)) begin
bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0];
address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}};
if (oclk_wr_cnt == NUM_STG1_WR_RD)
address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}};
else if (phy_data_full_r || (!new_burst_r))
address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0];
else if ((oclk_wr_cnt >= 4'd0) && new_burst_r && ~phy_data_full_r)
address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC;
end else if ((init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_WRCAL_READ)) begin
bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0];
address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}};
if (wrcal_wr_cnt == NUM_STG1_WR_RD)
address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}};
else if (phy_data_full_r || (!new_burst_r))
address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0];
else if ((wrcal_wr_cnt >= 4'd0) && new_burst_r && ~phy_data_full_r)
address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC;
end else if ((init_state_r == INIT_WRCAL_MULT_READS) ||
(init_state_r == INIT_RDLVL_STG2_READ)) begin
// when writing or reading back training pattern for read leveling stage2
// need to support burst length of 4 or 8. This may mean issuing
// multiple commands to cover the entire range of addresses accessed
// during read leveling.
// Hard coding A[12] to 1 so that it will always be burst length of 8
// for DDR3. Does not have any effect on DDR2.
bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0];
address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}};
address_w[COL_WIDTH-1:0] =
{CALIB_COL_ADD[COL_WIDTH-1:3],burst_addr_r, 3'b000};
address_w[12] = 1'b1;
end else if ((init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_WRCAL_ACT) ||
(init_state_r == INIT_OCLKDELAY_ACT)) begin
bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0];
address_w = CALIB_ROW_ADD[ROW_WIDTH-1:0];
end else begin
bank_w = {BANK_WIDTH{1'bx}};
address_w = {ROW_WIDTH{1'bx}};
end
end
// registring before sending out
generate
genvar r,s;
if ((DRAM_TYPE != "DDR3") || (CA_MIRROR != "ON")) begin: gen_no_mirror
for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: div_clk_loop
always @(posedge clk) begin
phy_address[(r*ROW_WIDTH) +: ROW_WIDTH] <= #TCQ address_w;
phy_bank[(r*BANK_WIDTH) +: BANK_WIDTH] <= #TCQ bank_w;
end
end
end else begin: gen_mirror
// Control/addressing mirroring (optional for DDR3 dual rank DIMMs)
// Mirror for the 2nd rank only. Logic needs to be enhanced to account
// for multiple slots, currently only supports one slot, 2-rank config
for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: gen_ba_div_clk_loop
for (s = 0; s < BANK_WIDTH; s = s + 1) begin: gen_ba
always @(posedge clk)
if (chip_cnt_r == 2'b00) begin
phy_bank[(r*BANK_WIDTH) + s] <= #TCQ bank_w[s];
end else begin
phy_bank[(r*BANK_WIDTH) + s] <= #TCQ bank_w[(s == 0) ? 1 : ((s == 1) ? 0 : s)];
end
end
end
for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: gen_addr_div_clk_loop
for (s = 0; s < ROW_WIDTH; s = s + 1) begin: gen_addr
always @(posedge clk)
if (chip_cnt_r == 2'b00) begin
phy_address[(r*ROW_WIDTH) + s] <= #TCQ address_w[s];
end else begin
phy_address[(r*ROW_WIDTH) + s] <= #TCQ address_w[
(s == 3) ? 4 :
((s == 4) ? 3 :
((s == 5) ? 6 :
((s == 6) ? 5 :
((s == 7) ? 8 :
((s == 8) ? 7 : s)))))];
end
end
end
end
endgenerate
endmodule
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module hb_dec_tb( ) ;
// Parameters for instantiation
parameter clocks = 9'd2 ; // Number of clocks per input
parameter decim = 1 ; // Sets the filter to decimate
parameter rate = 2 ; // Sets the decimation rate
reg clock ;
reg reset ;
reg enable ;
reg strobe_in ;
reg signed [17:0] data_in ;
wire strobe_out ;
wire signed [17:0] data_out ;
initial
begin
$dumpfile("hb_dec_tb.vcd");
$dumpvars(0,hb_dec_tb);
end
// Setup the clock
initial clock = 1'b0 ;
always #5 clock <= ~clock ;
// Come out of reset after a while
initial reset = 1'b1 ;
initial #1000 reset = 1'b0 ;
// Enable the entire system
initial enable = 1'b1 ;
// Instantiate UUT
/*
halfband_ideal
#(
.decim ( decim ),
.rate ( rate )
) uut(
.clock ( clock ),
.reset ( reset ),
.enable ( enable ),
.strobe_in ( strobe_in ),
.data_in ( data_in ),
.strobe_out ( strobe_out ),
.data_out ( data_out )
) ;
*/
small_hb_dec #(.WIDTH(18)) uut
(.clk(clock),.rst(reset),.bypass(0),.stb_in(strobe_in),.data_in(data_in),
.stb_out(strobe_out),.data_out(data_out) );
integer i, ri, ro, infile, outfile ;
always @(posedge clock)
begin
if(strobe_out)
$display(data_out);
end
// Setup file IO
initial begin
infile = $fopen("input.dat","r") ;
outfile = $fopen("output.dat","r") ;
$timeformat(-9, 2, " ns", 10) ;
end
reg endofsim ;
reg signed [17:0] compare ;
integer noe ;
initial noe = 0 ;
initial begin
// Initialize inputs
strobe_in <= 1'd0 ;
data_in <= 18'd0 ;
// Wait for reset to go away
@(negedge reset) #0 ;
// While we're still simulating ...
while( !endofsim ) begin
// Write the input from the file or 0 if EOF...
@( posedge clock ) begin
//#1 ;
strobe_in <= 1'b1 ;
if( !$feof(infile) )
ri = $fscanf( infile, "%d", data_in ) ;
else
data_in <= 18'd0 ;
end
// Clocked in - set the strobe to 0 if the number of
// clocks per sample is greater than 1
if( clocks > 1 ) begin
@(posedge clock) begin
strobe_in <= 1'b0 ;
end
// Wait for the specified number of cycles
for( i = 0 ; i < (clocks-2) ; i = i + 1 ) begin
@(posedge clock) #1 ;
end
end
end
// Print out the number of errors that occured
if( noe )
$display( "FAILED: %d errors during simulation", noe ) ;
else
$display( "PASSED: Simulation successful" ) ;
$finish ;
end
// Output comparison of simulated values versus known good values
always @ (posedge clock) begin
if( reset )
endofsim <= 1'b0 ;
else begin
if( !$feof(outfile) ) begin
if( strobe_out ) begin
ro = $fscanf( outfile, "%d\n", compare ) ;
if( compare != data_out ) begin
//$display( "%t: %d != %d", $realtime, data_out, compare ) ;
noe = noe + 1 ;
end
end
end else begin
// Signal end of simulation when no more outputs
endofsim <= 1'b1 ;
end
end
end
endmodule // hb_dec_tb
|
// This tests SystemVerilog interfaces
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
module test ();
// error counter
bit err = 0;
logic clk = 1'b1;
logic rst = 1'b1; // reset
integer rst_cnt = 0;
// clock generator
always #5 clk = ~clk;
// reset is removed after a delay
always @ (posedge clk)
begin
rst_cnt <= rst_cnt + 1;
rst <= rst_cnt <= 3;
end
// counters
int cnt;
int cnt_src;
int cnt_drn;
// add all counters
assign cnt = cnt_src + cnt_drn + inf.cnt;
// finish report
initial begin
wait (cnt == 3*16);
if (!err) $display("PASSED");
$finish;
end
// interface instance
handshake inf (
.clk (clk),
.rst (rst)
);
// source instance
source #(
.RW (8),
.RP (8'b11100001)
) source (
.clk (clk),
.rst (rst),
.inf (inf),
.cnt (cnt_src)
);
// drain instance
drain #(
.RW (8),
.RP (8'b11010100)
) drain (
.clk (clk),
.rst (rst),
.inf (inf),
.cnt (cnt_drn)
);
endmodule
// interface definition
interface handshake #(
parameter int unsigned WC = 32
)(
input logic clk,
input logic rst
);
// modport signals
logic req; // request
logic grt; // grant
logic inc; // increment
// local signals
integer cnt; // counter
// source
modport src (
output req,
input grt
);
// drain
modport drn (
input req,
output grt
);
// incremet condition
assign inc = req & grt;
// local logic (counter)
always @ (posedge clk, posedge rst)
if (rst) cnt <= '0;
else cnt <= cnt + inc;
endinterface
// source module
module source #(
// random generator parameters
parameter int unsigned RW=1, // LFSR width
parameter bit [RW-1:0] RP='0, // LFSR polinom
parameter bit [RW-1:0] RR='1 // LFSR reset state
)(
input logic clk,
input logic rst,
handshake.src inf,
output integer cnt
);
// LFSR
logic [RW-1:0] rnd;
// LFSR in Galois form
always @ (posedge clk, posedge rst)
if (rst) rnd <= RR;
else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP);
// counter
always @ (posedge clk, posedge rst)
if (rst) cnt <= 32'd0;
else cnt <= cnt + (inf.req & inf.grt);
// request signal
assign inf.req = rnd[0];
endmodule
// drain module
module drain #(
// random generator parameters
parameter int unsigned RW=1, // LFSR width
parameter bit [RW-1:0] RP='0, // LFSR polinom
parameter bit [RW-1:0] RR='1 // LFSR reset state
)(
input logic clk,
input logic rst,
handshake.drn inf,
output integer cnt
);
// LFSR
logic [RW-1:0] rnd;
// LFSR in Galois form
always @ (posedge clk, posedge rst)
if (rst) rnd <= RR;
else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP);
// counter
always @ (posedge clk, posedge rst)
if (rst) cnt <= 32'd0;
else cnt <= cnt + (inf.req & inf.grt);
// grant signal
assign inf.grt = rnd[0];
endmodule
|
// $Header: $
///////////////////////////////////////////////////////
// Copyright (c) 2010 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Fujisan PHASER IN
// /__/ /\ Filename : PHASER_IN_PHY.v
// \ \ / \
// \__\/\__ \
//
// Revision: Comment:
// 22APR2010 Initial UNI/UNP/SIM version from yaml
// 03JUN2010 yaml update
// 12JUL2010 enable secureip
// 12AUG2010 yaml, rtl update
// 24SEP2010 yaml, rtl update
// 29SEP2010 add width checks
// 13OCT2010 yaml, rtl update
// 26OCT2010 delay yaml, rtl update
// 02NOV2010 yaml update
// 05NOV2010 secureip parameter name update
// 11NOV2010 582473 multiple drivers on delay_MEMREFCLK
// 01DEC2010 yaml update, REFCLK_PERIOD max
// 09DEC2010 586079 yaml update, tie off defaults
// 20DEC2010 587097 yaml update, OUTPUT_CLK_SRC
// 11JAN2011 586040 correct spelling XIL_TIMING vs XIL_TIMIMG
// 02FEB2011 592485 yaml, rtl update
// 19MAY2011 611139 remove period, setup/hold checks on FREQ/MEM/PHASEREFCLK, SYNCIN
// 02JUN2011 610011 rtl update, ADD REFCLK_PERIOD parameter
// 27JUL2011 618669 REFCLK_PERIOD = 0 not allowed
// 15AUG2011 621681 yaml update, remove SIM_SPEEDUP make default
// 01DEC2011 635710 yaml update SEL_CLK_OFFSET = 0 per model alert
// 01MAR2012 637179 (and others) RTL update, TEST_OPT split apart
// 22MAY2012 660507 DQS_AUTO_RECAL default value change
// 13JUN2012 664620 Change dly ref clk for DQSFOUND
// 10JUL2012 669266 Make DQS_AUTO_RECAL and DQS_FIND_PATTERN visible
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module PHASER_IN_PHY #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter BURST_MODE = "FALSE",
parameter integer CLKOUT_DIV = 4,
parameter [0:0] DQS_AUTO_RECAL = 1'b1,
parameter DQS_BIAS_MODE = "FALSE",
parameter [2:0] DQS_FIND_PATTERN = 3'b001,
parameter integer FINE_DELAY = 0,
parameter FREQ_REF_DIV = "NONE",
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter real MEMREFCLK_PERIOD = 0.000,
parameter OUTPUT_CLK_SRC = "PHASE_REF",
parameter real PHASEREFCLK_PERIOD = 0.000,
parameter real REFCLK_PERIOD = 0.000,
parameter integer SEL_CLK_OFFSET = 5,
parameter SYNC_IN_DIV_RST = "FALSE",
parameter WR_CYCLES = "FALSE"
) (
output [5:0] COUNTERREADVAL,
output DQSFOUND,
output DQSOUTOFRANGE,
output FINEOVERFLOW,
output ICLK,
output ICLKDIV,
output ISERDESRST,
output PHASELOCKED,
output RCLK,
output WRENABLE,
input BURSTPENDINGPHY,
input COUNTERLOADEN,
input [5:0] COUNTERLOADVAL,
input COUNTERREADEN,
input [1:0] ENCALIBPHY,
input FINEENABLE,
input FINEINC,
input FREQREFCLK,
input MEMREFCLK,
input PHASEREFCLK,
input [1:0] RANKSELPHY,
input RST,
input RSTDQSFIND,
input SYNCIN,
input SYSCLK
);
`ifdef XIL_TIMING
localparam in_delay = 0;
localparam out_delay = 0;
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 0;
`else
localparam in_delay = 1;
localparam out_delay = 1;
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 1;
`endif
localparam MODULE_NAME = "PHASER_IN_PHY";
reg MEMREFCLK_PERIOD_BINARY;
reg PHASEREFCLK_PERIOD_BINARY;
reg REFCLK_PERIOD_BINARY;
reg [0:0] BURST_MODE_BINARY;
reg [0:0] CALIB_EDGE_IN_INV_BINARY;
reg [0:0] CTL_MODE_BINARY;
reg [0:0] DQS_AUTO_RECAL_BINARY;
reg [0:0] DQS_BIAS_MODE_BINARY;
reg [0:0] EN_ISERDES_RST_BINARY;
reg [0:0] EN_TEST_RING_BINARY;
reg [0:0] GATE_SET_CLK_MUX_BINARY;
reg [0:0] HALF_CYCLE_ADJ_BINARY;
reg [0:0] ICLK_TO_RCLK_BYPASS_BINARY;
reg [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED;
reg [0:0] PHASER_IN_EN_BINARY;
reg [0:0] REG_OPT_1_BINARY;
reg [0:0] REG_OPT_2_BINARY;
reg [0:0] REG_OPT_4_BINARY;
reg [0:0] RST_SEL_BINARY;
reg [0:0] SEL_OUT_BINARY;
reg [0:0] SYNC_IN_DIV_RST_BINARY;
reg [0:0] TEST_BP_BINARY;
reg [0:0] UPDATE_NONACTIVE_BINARY;
reg [0:0] WR_CYCLES_BINARY;
reg [1:0] FREQ_REF_DIV_BINARY;
reg [1:0] RD_ADDR_INIT_BINARY;
reg [2:0] DQS_FIND_PATTERN_BINARY;
reg [2:0] PD_REVERSE_BINARY;
reg [2:0] SEL_CLK_OFFSET_BINARY;
reg [2:0] STG1_PD_UPDATE_BINARY;
reg [3:0] CLKOUT_DIV_BINARY;
reg [3:0] CLKOUT_DIV_POS_BINARY;
reg [3:0] CLKOUT_DIV_ST_BINARY;
reg [3:0] OUTPUT_CLK_SRC_BINARY;
reg [5:0] FINE_DELAY_BINARY;
tri0 GSR = glbl.GSR;
`ifdef XIL_TIMING
reg notifier;
`endif
initial begin
case (BURST_MODE)
"FALSE" : BURST_MODE_BINARY <= 1'b0;
"TRUE" : BURST_MODE_BINARY <= 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute BURST_MODE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, BURST_MODE);
$finish;
end
endcase
case (CLKOUT_DIV)
4 : CLKOUT_DIV_BINARY <= 4'b0010;
2 : CLKOUT_DIV_BINARY <= 4'b0000;
3 : CLKOUT_DIV_BINARY <= 4'b0001;
5 : CLKOUT_DIV_BINARY <= 4'b0011;
6 : CLKOUT_DIV_BINARY <= 4'b0100;
7 : CLKOUT_DIV_BINARY <= 4'b0101;
8 : CLKOUT_DIV_BINARY <= 4'b0110;
9 : CLKOUT_DIV_BINARY <= 4'b0111;
10 : CLKOUT_DIV_BINARY <= 4'b1000;
11 : CLKOUT_DIV_BINARY <= 4'b1001;
12 : CLKOUT_DIV_BINARY <= 4'b1010;
13 : CLKOUT_DIV_BINARY <= 4'b1011;
14 : CLKOUT_DIV_BINARY <= 4'b1100;
15 : CLKOUT_DIV_BINARY <= 4'b1101;
16 : CLKOUT_DIV_BINARY <= 4'b1110;
default : begin
$display("Attribute Syntax Error : The Attribute CLKOUT_DIV on %s instance %m is set to %d. Legal values for this attribute are 2 to 16.", MODULE_NAME, CLKOUT_DIV);
$finish;
end
endcase
CTL_MODE_BINARY <= 1'b1; // model alert
case (DQS_BIAS_MODE)
"FALSE" : DQS_BIAS_MODE_BINARY <= 1'b0;
"TRUE" : DQS_BIAS_MODE_BINARY <= 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DQS_BIAS_MODE on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, DQS_BIAS_MODE);
$finish;
end
endcase
EN_ISERDES_RST_BINARY <= 1'b0;
EN_TEST_RING_BINARY <= 1'b0;
case (FREQ_REF_DIV)
"NONE" : FREQ_REF_DIV_BINARY <= 2'b00;
"DIV2" : FREQ_REF_DIV_BINARY <= 2'b01;
default : begin
$display("Attribute Syntax Error : The Attribute FREQ_REF_DIV on %s instance %m is set to %s. Legal values for this attribute are NONE or DIV2.", MODULE_NAME, FREQ_REF_DIV);
$finish;
end
endcase
HALF_CYCLE_ADJ_BINARY <= 1'b0;
ICLK_TO_RCLK_BYPASS_BINARY <= 1'b1;
case (OUTPUT_CLK_SRC)
"PHASE_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b0000;
"DELAYED_MEM_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b0101;
"DELAYED_PHASE_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b0011;
"DELAYED_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b0001;
"FREQ_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b1000;
"MEM_REF" : OUTPUT_CLK_SRC_BINARY <= 4'b0010;
default : begin
$display("Attribute Syntax Error : The Attribute OUTPUT_CLK_SRC on %s instance %m is set to %s. Legal values for this attribute are PHASE_REF, DELAYED_MEM_REF, DELAYED_PHASE_REF, DELAYED_REF, FREQ_REF or MEM_REF.", MODULE_NAME, OUTPUT_CLK_SRC);
$finish;
end
endcase
PD_REVERSE_BINARY <= 3'b011;
PHASER_IN_EN_BINARY <= 1'b1;
STG1_PD_UPDATE_BINARY <= 3'b000;
case (SYNC_IN_DIV_RST)
"FALSE" : SYNC_IN_DIV_RST_BINARY <= 1'b0;
"TRUE" : SYNC_IN_DIV_RST_BINARY <= 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute SYNC_IN_DIV_RST on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, SYNC_IN_DIV_RST);
$finish;
end
endcase
UPDATE_NONACTIVE_BINARY <= 1'b0;
case (WR_CYCLES)
"FALSE" : WR_CYCLES_BINARY <= 1'b0;
"TRUE" : WR_CYCLES_BINARY <= 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute WR_CYCLES on %s instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", MODULE_NAME, WR_CYCLES);
$finish;
end
endcase
CALIB_EDGE_IN_INV_BINARY <= 1'b0;
case (CLKOUT_DIV)
2 : CLKOUT_DIV_POS_BINARY <= 4'b0001;
3 : CLKOUT_DIV_POS_BINARY <= 4'b0001;
4 : CLKOUT_DIV_POS_BINARY <= 4'b0010;
5 : CLKOUT_DIV_POS_BINARY <= 4'b0010;
6 : CLKOUT_DIV_POS_BINARY <= 4'b0011;
7 : CLKOUT_DIV_POS_BINARY <= 4'b0011;
8 : CLKOUT_DIV_POS_BINARY <= 4'b0100;
9 : CLKOUT_DIV_POS_BINARY <= 4'b0100;
10 : CLKOUT_DIV_POS_BINARY <= 4'b0101;
11 : CLKOUT_DIV_POS_BINARY <= 4'b0101;
12 : CLKOUT_DIV_POS_BINARY <= 4'b0110;
13 : CLKOUT_DIV_POS_BINARY <= 4'b0110;
14 : CLKOUT_DIV_POS_BINARY <= 4'b0111;
15 : CLKOUT_DIV_POS_BINARY <= 4'b0111;
16 : CLKOUT_DIV_POS_BINARY <= 4'b1000;
default: CLKOUT_DIV_POS_BINARY <= 4'b0010;
endcase
CLKOUT_DIV_ST_BINARY <= 4'b0000;
if ((DQS_AUTO_RECAL >= 1'b0) && (DQS_AUTO_RECAL <= 1'b1))
DQS_AUTO_RECAL_BINARY <= DQS_AUTO_RECAL;
else begin
$display("Attribute Syntax Error : The Attribute DQS_AUTO_RECAL on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, DQS_AUTO_RECAL);
$finish;
end
if ((DQS_FIND_PATTERN >= 3'b000) && (DQS_FIND_PATTERN <= 3'b111))
DQS_FIND_PATTERN_BINARY <= DQS_FIND_PATTERN;
else begin
$display("Attribute Syntax Error : The Attribute DQS_FIND_PATTERN on %s instance %m is set to %b. Legal values for this attribute are 3'b000 to 3'b111.", MODULE_NAME, DQS_FIND_PATTERN);
$finish;
end
if ((FINE_DELAY >= 0) && (FINE_DELAY <= 63))
FINE_DELAY_BINARY <= FINE_DELAY;
else begin
$display("Attribute Syntax Error : The Attribute FINE_DELAY on %s instance %m is set to %d. Legal values for this attribute are 0 to 63.", MODULE_NAME, FINE_DELAY);
$finish;
end
GATE_SET_CLK_MUX_BINARY <= 1'b0;
if ((MEMREFCLK_PERIOD > 0.000) && (MEMREFCLK_PERIOD <= 5.000))
MEMREFCLK_PERIOD_BINARY <= 1'b1;
else begin
$display("Attribute Syntax Error : The Attribute MEMREFCLK_PERIOD on %s instance %m is set to %2.3f. Legal values for this attribute are greater than 0.000 but less than or equal 5.000.", MODULE_NAME, MEMREFCLK_PERIOD);
$finish;
end
if ((PHASEREFCLK_PERIOD > 0.000) && (PHASEREFCLK_PERIOD <= 5.000))
PHASEREFCLK_PERIOD_BINARY <= 1'b1;
else begin
$display("Attribute Syntax Error : The Attribute PHASEREFCLK_PERIOD on %s instance %m is set to %2.3f. Legal values for this attribute are greater than 0.000 but less than or equal 5.000.", MODULE_NAME, PHASEREFCLK_PERIOD);
$finish;
end
RD_ADDR_INIT_BINARY <= 2'b00;
if ((REFCLK_PERIOD > 0.000) && (REFCLK_PERIOD <= 2.500))
REFCLK_PERIOD_BINARY <= 1'b1;
else begin
$display("Attribute Syntax Error : The Attribute REFCLK_PERIOD on %s instance %m is set to %2.3f. Legal values for this attribute are greater than 0.000 but less than or equal to 2.500.", MODULE_NAME, REFCLK_PERIOD);
$finish;
end
REG_OPT_1_BINARY <= 1'b0;
REG_OPT_2_BINARY <= 1'b0;
REG_OPT_4_BINARY <= 1'b0;
RST_SEL_BINARY <= 1'b0;
if ((SEL_CLK_OFFSET >= 0) && (SEL_CLK_OFFSET <= 7))
SEL_CLK_OFFSET_BINARY <= 0; // Model Alert
else begin
$display("Attribute Syntax Error : The Attribute SEL_CLK_OFFSET on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, SEL_CLK_OFFSET);
$finish;
end
SEL_OUT_BINARY <= 1'b0;
TEST_BP_BINARY <= 1'b0;
end
wire [3:0] delay_TESTOUT;
wire [5:0] delay_COUNTERREADVAL;
wire [8:0] delay_STG1REGR;
wire delay_DQSFOUND;
wire delay_DQSOUTOFRANGE;
wire delay_FINEOVERFLOW;
wire delay_ICLK;
wire delay_ICLKDIV;
wire delay_ISERDESRST;
wire delay_PHASELOCKED;
wire delay_RCLK;
wire delay_SCANOUT;
wire delay_STG1OVERFLOW;
wire delay_WRENABLE;
wire [13:0] delay_TESTIN = 14'h3fff;
wire [1:0] delay_ENCALIB = 2'b11;
wire [1:0] delay_ENCALIBPHY;
wire [1:0] delay_RANKSEL = 2'b0;
wire [1:0] delay_RANKSELPHY;
wire [5:0] delay_COUNTERLOADVAL;
wire [8:0] delay_STG1REGL = 9'h1ff;
wire delay_BURSTPENDING = 1'b1;
wire delay_BURSTPENDINGPHY;
wire delay_COUNTERLOADEN;
wire delay_COUNTERREADEN;
wire delay_DIVIDERST = 1'b0;
wire delay_EDGEADV = 1'b0;
wire delay_ENSTG1 = 1'b1;
wire delay_ENSTG1ADJUSTB = 1'b1;
wire delay_FINEENABLE;
wire delay_FINEINC;
wire delay_FREQREFCLK;
wire delay_MEMREFCLK;
wire delay_PHASEREFCLK;
wire delay_RST;
wire delay_RSTDQSFIND;
wire delay_SCANCLK = 1'b1;
wire delay_SCANENB = 1'b1;
wire delay_SCANIN = 1'b1;
wire delay_SCANMODEB = 1'b1;
wire delay_SELCALORSTG1 = 1'b1;
wire delay_STG1INCDEC = 1'b1;
wire delay_STG1LOAD = 1'b1;
wire delay_STG1READ = 1'b1;
wire delay_SYNCIN;
wire delay_SYSCLK;
wire delay_GSR;
assign #(OUTCLK_DELAY) ICLK = delay_ICLK;
assign #(OUTCLK_DELAY) ICLKDIV = delay_ICLKDIV;
assign #(OUTCLK_DELAY) RCLK = delay_RCLK;
assign #(out_delay) COUNTERREADVAL = delay_COUNTERREADVAL;
assign #(out_delay) DQSFOUND = delay_DQSFOUND;
assign #(out_delay) DQSOUTOFRANGE = delay_DQSOUTOFRANGE;
assign #(out_delay) FINEOVERFLOW = delay_FINEOVERFLOW;
assign #(out_delay) ISERDESRST = delay_ISERDESRST;
assign #(out_delay) PHASELOCKED = delay_PHASELOCKED;
assign #(out_delay) WRENABLE = delay_WRENABLE;
`ifndef XIL_TIMING
assign #(INCLK_DELAY) delay_SYSCLK = SYSCLK;
`endif
assign #(in_delay) delay_BURSTPENDINGPHY = BURSTPENDINGPHY;
`ifndef XIL_TIMING
assign #(in_delay) delay_COUNTERLOADEN = COUNTERLOADEN;
assign #(in_delay) delay_COUNTERLOADVAL = COUNTERLOADVAL;
assign #(in_delay) delay_COUNTERREADEN = COUNTERREADEN;
`endif
assign #(in_delay) delay_ENCALIBPHY = ENCALIBPHY;
`ifndef XIL_TIMING
assign #(in_delay) delay_FINEENABLE = FINEENABLE;
assign #(in_delay) delay_FINEINC = FINEINC;
`endif
assign #(in_delay) delay_FREQREFCLK = FREQREFCLK;
assign #(in_delay) delay_MEMREFCLK = MEMREFCLK;
assign #(in_delay) delay_PHASEREFCLK = PHASEREFCLK;
assign #(in_delay) delay_RANKSELPHY = RANKSELPHY;
assign #(in_delay) delay_RST = RST;
`ifndef XIL_TIMING
assign #(in_delay) delay_RSTDQSFIND = RSTDQSFIND;
`endif
assign #(in_delay) delay_SYNCIN = SYNCIN;
assign delay_GSR = GSR;
SIP_PHASER_IN # (
.REFCLK_PERIOD (REFCLK_PERIOD)
) PHASER_IN_INST (
.BURST_MODE (BURST_MODE_BINARY),
.CALIB_EDGE_IN_INV (CALIB_EDGE_IN_INV_BINARY),
.CLKOUT_DIV (CLKOUT_DIV_BINARY),
.CLKOUT_DIV_ST (CLKOUT_DIV_ST_BINARY),
.CTL_MODE (CTL_MODE_BINARY),
.DQS_AUTO_RECAL (DQS_AUTO_RECAL_BINARY),
.DQS_BIAS_MODE (DQS_BIAS_MODE_BINARY),
.DQS_FIND_PATTERN (DQS_FIND_PATTERN_BINARY),
.EN_ISERDES_RST (EN_ISERDES_RST_BINARY),
.EN_TEST_RING (EN_TEST_RING_BINARY),
.FINE_DELAY (FINE_DELAY_BINARY),
.FREQ_REF_DIV (FREQ_REF_DIV_BINARY),
.GATE_SET_CLK_MUX (GATE_SET_CLK_MUX_BINARY),
.HALF_CYCLE_ADJ (HALF_CYCLE_ADJ_BINARY),
.ICLK_TO_RCLK_BYPASS (ICLK_TO_RCLK_BYPASS_BINARY),
.OUTPUT_CLK_SRC (OUTPUT_CLK_SRC_BINARY),
.PD_REVERSE (PD_REVERSE_BINARY),
.PHASER_IN_EN (PHASER_IN_EN_BINARY),
.RD_ADDR_INIT (RD_ADDR_INIT_BINARY),
.REG_OPT_1 (REG_OPT_1_BINARY),
.REG_OPT_2 (REG_OPT_2_BINARY),
.REG_OPT_4 (REG_OPT_4_BINARY),
.RST_SEL (RST_SEL_BINARY),
.SEL_CLK_OFFSET (SEL_CLK_OFFSET_BINARY),
.SEL_OUT (SEL_OUT_BINARY),
.STG1_PD_UPDATE (STG1_PD_UPDATE_BINARY),
.SYNC_IN_DIV_RST (SYNC_IN_DIV_RST_BINARY),
.TEST_BP (TEST_BP_BINARY),
.UPDATE_NONACTIVE (UPDATE_NONACTIVE_BINARY),
.WR_CYCLES (WR_CYCLES_BINARY),
.CLKOUT_DIV_POS (CLKOUT_DIV_POS_BINARY),
.COUNTERREADVAL (delay_COUNTERREADVAL),
.DQSFOUND (delay_DQSFOUND),
.DQSOUTOFRANGE (delay_DQSOUTOFRANGE),
.FINEOVERFLOW (delay_FINEOVERFLOW),
.ICLK (delay_ICLK),
.ICLKDIV (delay_ICLKDIV),
.ISERDESRST (delay_ISERDESRST),
.PHASELOCKED (delay_PHASELOCKED),
.RCLK (delay_RCLK),
.SCANOUT (delay_SCANOUT),
.STG1OVERFLOW (delay_STG1OVERFLOW),
.STG1REGR (delay_STG1REGR),
.TESTOUT (delay_TESTOUT),
.WRENABLE (delay_WRENABLE),
.BURSTPENDING (delay_BURSTPENDING),
.BURSTPENDINGPHY (delay_BURSTPENDINGPHY),
.COUNTERLOADEN (delay_COUNTERLOADEN),
.COUNTERLOADVAL (delay_COUNTERLOADVAL),
.COUNTERREADEN (delay_COUNTERREADEN),
.DIVIDERST (delay_DIVIDERST),
.EDGEADV (delay_EDGEADV),
.ENCALIB (delay_ENCALIB),
.ENCALIBPHY (delay_ENCALIBPHY),
.ENSTG1 (delay_ENSTG1),
.ENSTG1ADJUSTB (delay_ENSTG1ADJUSTB),
.FINEENABLE (delay_FINEENABLE),
.FINEINC (delay_FINEINC),
.FREQREFCLK (delay_FREQREFCLK),
.MEMREFCLK (delay_MEMREFCLK),
.PHASEREFCLK (delay_PHASEREFCLK),
.RANKSEL (delay_RANKSEL),
.RANKSELPHY (delay_RANKSELPHY),
.RST (delay_RST ^ IS_RST_INVERTED_REG),
.RSTDQSFIND (delay_RSTDQSFIND),
.SCANCLK (delay_SCANCLK),
.SCANENB (delay_SCANENB),
.SCANIN (delay_SCANIN),
.SCANMODEB (delay_SCANMODEB),
.SELCALORSTG1 (delay_SELCALORSTG1),
.STG1INCDEC (delay_STG1INCDEC),
.STG1LOAD (delay_STG1LOAD),
.STG1READ (delay_STG1READ),
.STG1REGL (delay_STG1REGL),
.SYNCIN (delay_SYNCIN),
.SYSCLK (delay_SYSCLK),
.TESTIN (delay_TESTIN),
.GSR (delay_GSR)
);
`ifdef XIL_TIMING
specify
$period (posedge SYSCLK, 0:0:0, notifier);
$setuphold (posedge SYSCLK, negedge COUNTERLOADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADEN);
$setuphold (posedge SYSCLK, negedge COUNTERLOADVAL, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADVAL);
$setuphold (posedge SYSCLK, negedge COUNTERREADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERREADEN);
$setuphold (posedge SYSCLK, negedge FINEENABLE, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEENABLE);
$setuphold (posedge SYSCLK, negedge FINEINC, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEINC);
$setuphold (posedge SYSCLK, negedge RSTDQSFIND, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_RSTDQSFIND);
$setuphold (posedge SYSCLK, posedge COUNTERLOADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADEN);
$setuphold (posedge SYSCLK, posedge COUNTERLOADVAL, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERLOADVAL);
$setuphold (posedge SYSCLK, posedge COUNTERREADEN, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_COUNTERREADEN);
$setuphold (posedge SYSCLK, posedge FINEENABLE, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEENABLE);
$setuphold (posedge SYSCLK, posedge FINEINC, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_FINEINC);
$setuphold (posedge SYSCLK, posedge RSTDQSFIND, 0:0:0, 0:0:0, notifier,,, delay_SYSCLK, delay_RSTDQSFIND);
$width (negedge FREQREFCLK, 0:0:0, 0, notifier);
$width (negedge MEMREFCLK, 0:0:0, 0, notifier);
$width (negedge PHASEREFCLK, 0:0:0, 0, notifier);
$width (negedge RST, 0:0:0, 0, notifier);
$width (negedge SYNCIN, 0:0:0, 0, notifier);
$width (negedge SYSCLK, 0:0:0, 0, notifier);
$width (posedge FREQREFCLK, 0:0:0, 0, notifier);
$width (posedge MEMREFCLK, 0:0:0, 0, notifier);
$width (posedge PHASEREFCLK, 0:0:0, 0, notifier);
$width (posedge RST, 0:0:0, 0, notifier);
$width (posedge SYNCIN, 0:0:0, 0, notifier);
$width (posedge SYSCLK, 0:0:0, 0, notifier);
( FREQREFCLK *> ICLK) = (10:10:10, 10:10:10);
( FREQREFCLK *> ICLKDIV) = (10:10:10, 10:10:10);
( FREQREFCLK *> ISERDESRST) = (10:10:10, 10:10:10);
( FREQREFCLK *> RCLK) = (10:10:10, 10:10:10);
( FREQREFCLK *> WRENABLE) = (10:10:10, 10:10:10);
( MEMREFCLK *> DQSFOUND) = (10:10:10, 10:10:10);
( MEMREFCLK *> ICLK) = (10:10:10, 10:10:10);
( MEMREFCLK *> ICLKDIV) = (10:10:10, 10:10:10);
( MEMREFCLK *> ISERDESRST) = (10:10:10, 10:10:10);
( MEMREFCLK *> RCLK) = (10:10:10, 10:10:10);
( MEMREFCLK *> WRENABLE) = (10:10:10, 10:10:10);
( PHASEREFCLK *> ICLK) = (10:10:10, 10:10:10);
( PHASEREFCLK *> ICLKDIV) = (10:10:10, 10:10:10);
( PHASEREFCLK *> ISERDESRST) = (10:10:10, 10:10:10);
( PHASEREFCLK *> RCLK) = (10:10:10, 10:10:10);
( PHASEREFCLK *> WRENABLE) = (10:10:10, 10:10:10);
( RST *> DQSOUTOFRANGE) = (10:10:10, 10:10:10);
( RST *> PHASELOCKED) = (10:10:10, 10:10:10);
( SYSCLK *> COUNTERREADVAL) = (10:10:10, 10:10:10);
( SYSCLK *> FINEOVERFLOW) = (10:10:10, 10:10:10);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule // PHASER_IN_PHY
`endcelldefine
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2013.4
// Copyright (C) 2013 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0(clk, reset, ce, a, b, s);
// ---- input/output ports list here ----
input clk;
input reset;
input ce;
input [32 - 1 : 0] a;
input [32 - 1 : 0] b;
output [32 - 1 : 0] s;
// ---- register and wire type variables list here ----
// wire for the primary inputs
wire [32 - 1 : 0] a_reg;
wire [32 - 1 : 0] b_reg;
// wires for each small adder
wire [4 - 1 : 0] a0_cb;
wire [4 - 1 : 0] b0_cb;
wire [8 - 1 : 4] a1_cb;
wire [8 - 1 : 4] b1_cb;
wire [12 - 1 : 8] a2_cb;
wire [12 - 1 : 8] b2_cb;
wire [16 - 1 : 12] a3_cb;
wire [16 - 1 : 12] b3_cb;
wire [20 - 1 : 16] a4_cb;
wire [20 - 1 : 16] b4_cb;
wire [24 - 1 : 20] a5_cb;
wire [24 - 1 : 20] b5_cb;
wire [28 - 1 : 24] a6_cb;
wire [28 - 1 : 24] b6_cb;
wire [32 - 1 : 28] a7_cb;
wire [32 - 1 : 28] b7_cb;
// registers for input register array
reg [4 - 1 : 0] a1_cb_regi1[1 - 1 : 0];
reg [4 - 1 : 0] b1_cb_regi1[1 - 1 : 0];
reg [4 - 1 : 0] a2_cb_regi2[2 - 1 : 0];
reg [4 - 1 : 0] b2_cb_regi2[2 - 1 : 0];
reg [4 - 1 : 0] a3_cb_regi3[3 - 1 : 0];
reg [4 - 1 : 0] b3_cb_regi3[3 - 1 : 0];
reg [4 - 1 : 0] a4_cb_regi4[4 - 1 : 0];
reg [4 - 1 : 0] b4_cb_regi4[4 - 1 : 0];
reg [4 - 1 : 0] a5_cb_regi5[5 - 1 : 0];
reg [4 - 1 : 0] b5_cb_regi5[5 - 1 : 0];
reg [4 - 1 : 0] a6_cb_regi6[6 - 1 : 0];
reg [4 - 1 : 0] b6_cb_regi6[6 - 1 : 0];
reg [4 - 1 : 0] a7_cb_regi7[7 - 1 : 0];
reg [4 - 1 : 0] b7_cb_regi7[7 - 1 : 0];
// wires for each full adder sum
wire [32 - 1 : 0] fas;
// wires and register for carry out bit
wire faccout_ini;
wire faccout0_co0;
wire faccout1_co1;
wire faccout2_co2;
wire faccout3_co3;
wire faccout4_co4;
wire faccout5_co5;
wire faccout6_co6;
wire faccout7_co7;
reg faccout0_co0_reg;
reg faccout1_co1_reg;
reg faccout2_co2_reg;
reg faccout3_co3_reg;
reg faccout4_co4_reg;
reg faccout5_co5_reg;
reg faccout6_co6_reg;
// registers for output register array
reg [4 - 1 : 0] s0_ca_rego0[6 - 0 : 0];
reg [4 - 1 : 0] s1_ca_rego1[6 - 1 : 0];
reg [4 - 1 : 0] s2_ca_rego2[6 - 2 : 0];
reg [4 - 1 : 0] s3_ca_rego3[6 - 3 : 0];
reg [4 - 1 : 0] s4_ca_rego4[6 - 4 : 0];
reg [4 - 1 : 0] s5_ca_rego5[6 - 5 : 0];
reg [4 - 1 : 0] s6_ca_rego6[6 - 6 : 0];
// wire for the temporary output
wire [32 - 1 : 0] s_tmp;
// ---- RTL code for assignment statements/always blocks/module instantiations here ----
assign a_reg = a;
assign b_reg = b;
// small adder input assigments
assign a0_cb = a_reg[4 - 1 : 0];
assign b0_cb = b_reg[4 - 1 : 0];
assign a1_cb = a_reg[8 - 1 : 4];
assign b1_cb = b_reg[8 - 1 : 4];
assign a2_cb = a_reg[12 - 1 : 8];
assign b2_cb = b_reg[12 - 1 : 8];
assign a3_cb = a_reg[16 - 1 : 12];
assign b3_cb = b_reg[16 - 1 : 12];
assign a4_cb = a_reg[20 - 1 : 16];
assign b4_cb = b_reg[20 - 1 : 16];
assign a5_cb = a_reg[24 - 1 : 20];
assign b5_cb = b_reg[24 - 1 : 20];
assign a6_cb = a_reg[28 - 1 : 24];
assign b6_cb = b_reg[28 - 1 : 24];
assign a7_cb = a_reg[32 - 1 : 28];
assign b7_cb = b_reg[32 - 1 : 28];
// input register array
always @ (posedge clk) begin
if (ce) begin
a1_cb_regi1 [0] <= a1_cb;
b1_cb_regi1 [0] <= b1_cb;
a2_cb_regi2 [0] <= a2_cb;
b2_cb_regi2 [0] <= b2_cb;
a3_cb_regi3 [0] <= a3_cb;
b3_cb_regi3 [0] <= b3_cb;
a4_cb_regi4 [0] <= a4_cb;
b4_cb_regi4 [0] <= b4_cb;
a5_cb_regi5 [0] <= a5_cb;
b5_cb_regi5 [0] <= b5_cb;
a6_cb_regi6 [0] <= a6_cb;
b6_cb_regi6 [0] <= b6_cb;
a7_cb_regi7 [0] <= a7_cb;
b7_cb_regi7 [0] <= b7_cb;
a2_cb_regi2 [1] <= a2_cb_regi2 [0];
b2_cb_regi2 [1] <= b2_cb_regi2 [0];
a3_cb_regi3 [1] <= a3_cb_regi3 [0];
b3_cb_regi3 [1] <= b3_cb_regi3 [0];
a4_cb_regi4 [1] <= a4_cb_regi4 [0];
b4_cb_regi4 [1] <= b4_cb_regi4 [0];
a5_cb_regi5 [1] <= a5_cb_regi5 [0];
b5_cb_regi5 [1] <= b5_cb_regi5 [0];
a6_cb_regi6 [1] <= a6_cb_regi6 [0];
b6_cb_regi6 [1] <= b6_cb_regi6 [0];
a7_cb_regi7 [1] <= a7_cb_regi7 [0];
b7_cb_regi7 [1] <= b7_cb_regi7 [0];
a3_cb_regi3 [2] <= a3_cb_regi3 [1];
b3_cb_regi3 [2] <= b3_cb_regi3 [1];
a4_cb_regi4 [2] <= a4_cb_regi4 [1];
b4_cb_regi4 [2] <= b4_cb_regi4 [1];
a5_cb_regi5 [2] <= a5_cb_regi5 [1];
b5_cb_regi5 [2] <= b5_cb_regi5 [1];
a6_cb_regi6 [2] <= a6_cb_regi6 [1];
b6_cb_regi6 [2] <= b6_cb_regi6 [1];
a7_cb_regi7 [2] <= a7_cb_regi7 [1];
b7_cb_regi7 [2] <= b7_cb_regi7 [1];
a4_cb_regi4 [3] <= a4_cb_regi4 [2];
b4_cb_regi4 [3] <= b4_cb_regi4 [2];
a5_cb_regi5 [3] <= a5_cb_regi5 [2];
b5_cb_regi5 [3] <= b5_cb_regi5 [2];
a6_cb_regi6 [3] <= a6_cb_regi6 [2];
b6_cb_regi6 [3] <= b6_cb_regi6 [2];
a7_cb_regi7 [3] <= a7_cb_regi7 [2];
b7_cb_regi7 [3] <= b7_cb_regi7 [2];
a5_cb_regi5 [4] <= a5_cb_regi5 [3];
b5_cb_regi5 [4] <= b5_cb_regi5 [3];
a6_cb_regi6 [4] <= a6_cb_regi6 [3];
b6_cb_regi6 [4] <= b6_cb_regi6 [3];
a7_cb_regi7 [4] <= a7_cb_regi7 [3];
b7_cb_regi7 [4] <= b7_cb_regi7 [3];
a6_cb_regi6 [5] <= a6_cb_regi6 [4];
b6_cb_regi6 [5] <= b6_cb_regi6 [4];
a7_cb_regi7 [5] <= a7_cb_regi7 [4];
b7_cb_regi7 [5] <= b7_cb_regi7 [4];
a7_cb_regi7 [6] <= a7_cb_regi7 [5];
b7_cb_regi7 [6] <= b7_cb_regi7 [5];
end
end
// carry out bit processing
always @ (posedge clk) begin
if (ce) begin
faccout0_co0_reg <= faccout0_co0;
faccout1_co1_reg <= faccout1_co1;
faccout2_co2_reg <= faccout2_co2;
faccout3_co3_reg <= faccout3_co3;
faccout4_co4_reg <= faccout4_co4;
faccout5_co5_reg <= faccout5_co5;
faccout6_co6_reg <= faccout6_co6;
end
end
// small adder generation
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder u0 (
.faa ( a0_cb ),
.fab ( b0_cb ),
.facin ( faccout_ini ),
.fas ( fas[3:0] ),
.facout ( faccout0_co0 )
);
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder u1 (
.faa ( a1_cb_regi1[0] ),
.fab ( b1_cb_regi1[0] ),
.facin ( faccout0_co0_reg),
.fas ( fas[7:4] ),
.facout ( faccout1_co1 )
);
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder u2 (
.faa ( a2_cb_regi2[1] ),
.fab ( b2_cb_regi2[1] ),
.facin ( faccout1_co1_reg),
.fas ( fas[11:8] ),
.facout ( faccout2_co2 )
);
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder u3 (
.faa ( a3_cb_regi3[2] ),
.fab ( b3_cb_regi3[2] ),
.facin ( faccout2_co2_reg),
.fas ( fas[15:12] ),
.facout ( faccout3_co3 )
);
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder u4 (
.faa ( a4_cb_regi4[3] ),
.fab ( b4_cb_regi4[3] ),
.facin ( faccout3_co3_reg),
.fas ( fas[19:16] ),
.facout ( faccout4_co4 )
);
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder u5 (
.faa ( a5_cb_regi5[4] ),
.fab ( b5_cb_regi5[4] ),
.facin ( faccout4_co4_reg),
.fas ( fas[23:20] ),
.facout ( faccout5_co5 )
);
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder u6 (
.faa ( a6_cb_regi6[5] ),
.fab ( b6_cb_regi6[5] ),
.facin ( faccout5_co5_reg),
.fas ( fas[27:24] ),
.facout ( faccout6_co6 )
);
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder_f u7 (
.faa ( a7_cb_regi7[6] ),
.fab ( b7_cb_regi7[6] ),
.facin ( faccout6_co6_reg ),
.fas ( fas[31 :28] ),
.facout ( faccout7_co7 )
);
assign faccout_ini = 1'b0;
// output register array
always @ (posedge clk) begin
if (ce) begin
s0_ca_rego0 [0] <= fas[4-1 : 0];
s1_ca_rego1 [0] <= fas[8-1 : 4];
s2_ca_rego2 [0] <= fas[12-1 : 8];
s3_ca_rego3 [0] <= fas[16-1 : 12];
s4_ca_rego4 [0] <= fas[20-1 : 16];
s5_ca_rego5 [0] <= fas[24-1 : 20];
s6_ca_rego6 [0] <= fas[28-1 : 24];
s0_ca_rego0 [1] <= s0_ca_rego0 [0];
s0_ca_rego0 [2] <= s0_ca_rego0 [1];
s0_ca_rego0 [3] <= s0_ca_rego0 [2];
s0_ca_rego0 [4] <= s0_ca_rego0 [3];
s0_ca_rego0 [5] <= s0_ca_rego0 [4];
s0_ca_rego0 [6] <= s0_ca_rego0 [5];
s1_ca_rego1 [1] <= s1_ca_rego1 [0];
s1_ca_rego1 [2] <= s1_ca_rego1 [1];
s1_ca_rego1 [3] <= s1_ca_rego1 [2];
s1_ca_rego1 [4] <= s1_ca_rego1 [3];
s1_ca_rego1 [5] <= s1_ca_rego1 [4];
s2_ca_rego2 [1] <= s2_ca_rego2 [0];
s2_ca_rego2 [2] <= s2_ca_rego2 [1];
s2_ca_rego2 [3] <= s2_ca_rego2 [2];
s2_ca_rego2 [4] <= s2_ca_rego2 [3];
s3_ca_rego3 [1] <= s3_ca_rego3 [0];
s3_ca_rego3 [2] <= s3_ca_rego3 [1];
s3_ca_rego3 [3] <= s3_ca_rego3 [2];
s4_ca_rego4 [1] <= s4_ca_rego4 [0];
s4_ca_rego4 [2] <= s4_ca_rego4 [1];
s5_ca_rego5 [1] <= s5_ca_rego5 [0];
end
end
// get the s_tmp, assign it to the primary output
assign s_tmp[4-1 : 0] = s0_ca_rego0[6];
assign s_tmp[8-1 : 4] = s1_ca_rego1[5];
assign s_tmp[12-1 : 8] = s2_ca_rego2[4];
assign s_tmp[16-1 : 12] = s3_ca_rego3[3];
assign s_tmp[20-1 : 16] = s4_ca_rego4[2];
assign s_tmp[24-1 : 20] = s5_ca_rego5[1];
assign s_tmp[28-1 : 24] = s6_ca_rego6[0];
assign s_tmp[32 - 1 : 28] = fas[31 :28];
assign s = s_tmp;
endmodule
// short adder
module nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder
#(parameter
N = 4
)(
input [N-1 : 0] faa,
input [N-1 : 0] fab,
input wire facin,
output [N-1 : 0] fas,
output wire facout
);
assign {facout, fas} = faa + fab + facin;
endmodule
// the final stage short adder
module nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_fadder_f
#(parameter
N = 4
)(
input [N-1 : 0] faa,
input [N-1 : 0] fab,
input wire facin,
output [N-1 : 0] fas,
output wire facout
);
assign {facout, fas} = faa + fab + facin;
endmodule
`timescale 1 ns / 1 ps
module nfa_accept_samples_generic_hw_add_32ns_32ns_32_8(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0 nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_AddSubnS_0_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.a( din0 ),
.b( din1 ),
.s( dout ));
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 6
(* X_CORE_INFO = "axi_crossbar_v2_1_axi_crossbar,Vivado 2015.1" *)
(* CHECK_LICENSE_TYPE = "triangle_intersect_xbar_0,axi_crossbar_v2_1_axi_crossbar,{}" *)
(* CORE_GENERATION_INFO = "triangle_intersect_xbar_0,axi_crossbar_v2_1_axi_crossbar,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_crossbar,x_ipVersion=2.1,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_NUM_SLAVE_SLOTS=3,C_NUM_MASTER_SLOTS=1,C_AXI_ID_WIDTH=2,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_PROTOCOL=0,C_NUM_ADDR_RANGES=1,C_M_AXI_BASE_ADDR=0x0000000000000000,C_M_AXI_ADDR_WIDTH=0x0000001d,C_S_AXI_BASE_ID=0x000000020000000100000000,C_S_AXI_THREAD_ID_WIDTH=0x000000000000000000000000,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_M_AXI_WRITE_CONNECTIVITY=0x00000006,C_M_AXI_READ_CONNECTIVITY=0x00000005,C_R_REGISTER=0,C_S_AXI_SINGLE_THREAD=0x000000000000000000000000,C_S_AXI_WRITE_ACCEPTANCE=0x000000020000000200000002,C_S_AXI_READ_ACCEPTANCE=0x000000020000000200000002,C_M_AXI_WRITE_ISSUING=0x00000008,C_M_AXI_READ_ISSUING=0x00000008,C_S_AXI_ARB_PRIORITY=0x000000000000000000000000,C_M_AXI_SECURE=0x00000000,C_CONNECTIVITY_MODE=1}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module triangle_intersect_xbar_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWID [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI AWID [1:0] [3:2], xilinx.com:interface:aximm:1.0 S02_AXI AWID [1:0] [5:4]" *)
input wire [5 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 S02_AXI AWADDR [31:0] [95:64]" *)
input wire [95 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 S02_AXI AWLEN [7:0] [23:16]" *)
input wire [23 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 S02_AXI AWSIZE [2:0] [8:6]" *)
input wire [8 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI AWBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 S02_AXI AWBURST [1:0] [5:4]" *)
input wire [5 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI AWLOCK [0:0] [2:2]" *)
input wire [2 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 S02_AXI AWCACHE [3:0] [11:8]" *)
input wire [11 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 S02_AXI AWPROT [2:0] [8:6]" *)
input wire [8 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 S02_AXI AWQOS [3:0] [11:8]" *)
input wire [11 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI AWVALID [0:0] [2:2]" *)
input wire [2 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI AWREADY [0:0] [2:2]" *)
output wire [2 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI WDATA [63:0] [127:64], xilinx.com:interface:aximm:1.0 S02_AXI WDATA [63:0] [191:128]" *)
input wire [191 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI WSTRB [7:0] [15:8], xilinx.com:interface:aximm:1.0 S02_AXI WSTRB [7:0] [23:16]" *)
input wire [23 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI WLAST [0:0] [2:2]" *)
input wire [2 : 0] s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI WVALID [0:0] [2:2]" *)
input wire [2 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI WREADY [0:0] [2:2]" *)
output wire [2 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BID [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI BID [1:0] [3:2], xilinx.com:interface:aximm:1.0 S02_AXI BID [1:0] [5:4]" *)
output wire [5 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 S02_AXI BRESP [1:0] [5:4]" *)
output wire [5 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI BVALID [0:0] [2:2]" *)
output wire [2 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI BREADY [0:0] [2:2]" *)
input wire [2 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARID [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI ARID [1:0] [3:2], xilinx.com:interface:aximm:1.0 S02_AXI ARID [1:0] [5:4]" *)
input wire [5 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 S02_AXI ARADDR [31:0] [95:64]" *)
input wire [95 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 S02_AXI ARLEN [7:0] [23:16]" *)
input wire [23 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 S02_AXI ARSIZE [2:0] [8:6]" *)
input wire [8 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI ARBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 S02_AXI ARBURST [1:0] [5:4]" *)
input wire [5 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI ARLOCK [0:0] [2:2]" *)
input wire [2 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 S02_AXI ARCACHE [3:0] [11:8]" *)
input wire [11 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 S02_AXI ARPROT [2:0] [8:6]" *)
input wire [8 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 S02_AXI ARQOS [3:0] [11:8]" *)
input wire [11 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI ARVALID [0:0] [2:2]" *)
input wire [2 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI ARREADY [0:0] [2:2]" *)
output wire [2 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RID [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI RID [1:0] [3:2], xilinx.com:interface:aximm:1.0 S02_AXI RID [1:0] [5:4]" *)
output wire [5 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI RDATA [63:0] [127:64], xilinx.com:interface:aximm:1.0 S02_AXI RDATA [63:0] [191:128]" *)
output wire [191 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 S02_AXI RRESP [1:0] [5:4]" *)
output wire [5 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI RLAST [0:0] [2:2]" *)
output wire [2 : 0] s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI RVALID [0:0] [2:2]" *)
output wire [2 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI RREADY [0:0] [2:2]" *)
input wire [2 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWID" *)
output wire [1 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID" *)
output wire [0 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY" *)
input wire [0 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WLAST" *)
output wire [0 : 0] m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID" *)
output wire [0 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY" *)
input wire [0 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BID" *)
input wire [1 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID" *)
input wire [0 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY" *)
output wire [0 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARID" *)
output wire [1 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID" *)
output wire [0 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY" *)
input wire [0 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RID" *)
input wire [1 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RLAST" *)
input wire [0 : 0] m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID" *)
input wire [0 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY" *)
output wire [0 : 0] m_axi_rready;
axi_crossbar_v2_1_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(3),
.C_NUM_MASTER_SLOTS(1),
.C_AXI_ID_WIDTH(2),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_PROTOCOL(0),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(64'H0000000000000000),
.C_M_AXI_ADDR_WIDTH(32'H0000001d),
.C_S_AXI_BASE_ID(96'H000000020000000100000000),
.C_S_AXI_THREAD_ID_WIDTH(96'H000000000000000000000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(32'H00000006),
.C_M_AXI_READ_CONNECTIVITY(32'H00000005),
.C_R_REGISTER(0),
.C_S_AXI_SINGLE_THREAD(96'H000000000000000000000000),
.C_S_AXI_WRITE_ACCEPTANCE(96'H000000020000000200000002),
.C_S_AXI_READ_ACCEPTANCE(96'H000000020000000200000002),
.C_M_AXI_WRITE_ISSUING(32'H00000008),
.C_M_AXI_READ_ISSUING(32'H00000008),
.C_S_AXI_ARB_PRIORITY(96'H000000000000000000000000),
.C_M_AXI_SECURE(32'H00000000),
.C_CONNECTIVITY_MODE(1)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(3'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(6'H00),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(3'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(3'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2009 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [15:0] in = crc[15:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [15:0] outa; // From test of Test.v
wire [15:0] outb; // From test of Test.v
wire [15:0] outc; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.outa (outa[15:0]),
.outb (outb[15:0]),
.outc (outc[15:0]),
// Inputs
.clk (clk),
.in (in[15:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {16'h0, outa, outb, outc};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h09be74b1b0f8c35d
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
outa, outb, outc,
// Inputs
clk, in
);
input clk;
input [15:0] in;
output reg [15:0] outa;
output reg [15:0] outb;
output reg [15:0] outc;
parameter WIDTH = 0;
always @(posedge clk) begin
outa <= {in};
outb <= {{WIDTH{1'b0}}, in};
outc <= {in, {WIDTH{1'b0}}};
end
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 9
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module block_design_auto_pc_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_9_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module image_filter_Mat2AXIvideo (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
img_rows_V_read,
img_cols_V_read,
img_data_stream_0_V_dout,
img_data_stream_0_V_empty_n,
img_data_stream_0_V_read,
img_data_stream_1_V_dout,
img_data_stream_1_V_empty_n,
img_data_stream_1_V_read,
img_data_stream_2_V_dout,
img_data_stream_2_V_empty_n,
img_data_stream_2_V_read,
OUTPUT_STREAM_TDATA,
OUTPUT_STREAM_TVALID,
OUTPUT_STREAM_TREADY,
OUTPUT_STREAM_TKEEP,
OUTPUT_STREAM_TSTRB,
OUTPUT_STREAM_TUSER,
OUTPUT_STREAM_TLAST,
OUTPUT_STREAM_TID,
OUTPUT_STREAM_TDEST
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 4'b1;
parameter ap_ST_st2_fsm_1 = 4'b10;
parameter ap_ST_pp0_stg0_fsm_2 = 4'b100;
parameter ap_ST_st5_fsm_3 = 4'b1000;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv32_2 = 32'b10;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv12_0 = 12'b000000000000;
parameter ap_const_lv32_3 = 32'b11;
parameter ap_const_lv4_F = 4'b1111;
parameter ap_const_lv4_0 = 4'b0000;
parameter ap_const_lv13_1FFF = 13'b1111111111111;
parameter ap_const_lv12_1 = 12'b1;
parameter ap_const_lv8_FF = 8'b11111111;
parameter ap_true = 1'b1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [11:0] img_rows_V_read;
input [11:0] img_cols_V_read;
input [7:0] img_data_stream_0_V_dout;
input img_data_stream_0_V_empty_n;
output img_data_stream_0_V_read;
input [7:0] img_data_stream_1_V_dout;
input img_data_stream_1_V_empty_n;
output img_data_stream_1_V_read;
input [7:0] img_data_stream_2_V_dout;
input img_data_stream_2_V_empty_n;
output img_data_stream_2_V_read;
output [31:0] OUTPUT_STREAM_TDATA;
output OUTPUT_STREAM_TVALID;
input OUTPUT_STREAM_TREADY;
output [3:0] OUTPUT_STREAM_TKEEP;
output [3:0] OUTPUT_STREAM_TSTRB;
output [0:0] OUTPUT_STREAM_TUSER;
output [0:0] OUTPUT_STREAM_TLAST;
output [0:0] OUTPUT_STREAM_TID;
output [0:0] OUTPUT_STREAM_TDEST;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg img_data_stream_0_V_read;
reg img_data_stream_1_V_read;
reg img_data_stream_2_V_read;
reg OUTPUT_STREAM_TVALID;
reg ap_done_reg = 1'b0;
(* fsm_encoding = "none" *) reg [3:0] ap_CS_fsm = 4'b1;
reg ap_sig_cseq_ST_st1_fsm_0;
reg ap_sig_bdd_23;
reg [11:0] p_3_reg_170;
reg ap_sig_bdd_60;
wire [12:0] op2_assign_fu_186_p2;
reg [12:0] op2_assign_reg_267;
wire [0:0] exitcond3_fu_197_p2;
reg ap_sig_cseq_ST_st2_fsm_1;
reg ap_sig_bdd_74;
wire [11:0] i_V_fu_202_p2;
reg [11:0] i_V_reg_276;
wire [0:0] exitcond4_fu_208_p2;
reg [0:0] exitcond4_reg_281;
reg ap_sig_cseq_ST_pp0_stg0_fsm_2;
reg ap_sig_bdd_85;
reg ap_reg_ppiten_pp0_it0 = 1'b0;
reg ap_sig_bdd_99;
reg ap_sig_ioackin_OUTPUT_STREAM_TREADY;
reg ap_reg_ppiten_pp0_it1 = 1'b0;
wire [11:0] j_V_fu_213_p2;
wire [0:0] axi_last_V_fu_223_p2;
reg [0:0] axi_last_V_reg_290;
reg [11:0] p_s_reg_159;
reg ap_sig_cseq_ST_st5_fsm_3;
reg ap_sig_bdd_130;
reg [0:0] tmp_user_V_fu_96;
reg ap_reg_ioackin_OUTPUT_STREAM_TREADY = 1'b0;
wire [12:0] tmp_cast_fu_182_p1;
wire [12:0] tmp_cast_35_fu_219_p1;
reg [3:0] ap_NS_fsm;
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_done_reg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_done_reg
if (ap_rst == 1'b1) begin
ap_done_reg <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_continue)) begin
ap_done_reg <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(exitcond3_fu_197_p2 == ap_const_lv1_0))) begin
ap_done_reg <= ap_const_logic_1;
end
end
end
/// ap_reg_ioackin_OUTPUT_STREAM_TREADY assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ioackin_OUTPUT_STREAM_TREADY
if (ap_rst == 1'b1) begin
ap_reg_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
ap_reg_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_99 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (ap_const_logic_1 == OUTPUT_STREAM_TREADY))) begin
ap_reg_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(exitcond4_fu_208_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (exitcond3_fu_197_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (exitcond4_fu_208_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
end else if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (exitcond3_fu_197_p2 == ap_const_lv1_0)) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(exitcond4_fu_208_p2 == ap_const_lv1_0)))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (exitcond4_fu_208_p2 == ap_const_lv1_0))) begin
p_3_reg_170 <= j_V_fu_213_p2;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (exitcond3_fu_197_p2 == ap_const_lv1_0))) begin
p_3_reg_170 <= ap_const_lv12_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_3)) begin
p_s_reg_159 <= i_V_reg_276;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_60)) begin
p_s_reg_159 <= ap_const_lv12_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
tmp_user_V_fu_96 <= ap_const_lv1_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_60)) begin
tmp_user_V_fu_96 <= ap_const_lv1_1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (exitcond4_fu_208_p2 == ap_const_lv1_0))) begin
axi_last_V_reg_290 <= axi_last_V_fu_223_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
exitcond4_reg_281 <= exitcond4_fu_208_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1)) begin
i_V_reg_276 <= i_V_fu_202_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_60)) begin
op2_assign_reg_267 <= op2_assign_fu_186_p2;
end
end
/// OUTPUT_STREAM_TVALID assign process. ///
always @ (exitcond4_reg_281 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_99 or ap_reg_ppiten_pp0_it1 or ap_reg_ioackin_OUTPUT_STREAM_TREADY)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_99 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (ap_const_logic_0 == ap_reg_ioackin_OUTPUT_STREAM_TREADY))) begin
OUTPUT_STREAM_TVALID = ap_const_logic_1;
end else begin
OUTPUT_STREAM_TVALID = ap_const_logic_0;
end
end
/// ap_done assign process. ///
always @ (ap_done_reg or exitcond3_fu_197_p2 or ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 == ap_done_reg) | ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(exitcond3_fu_197_p2 == ap_const_lv1_0)))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (exitcond3_fu_197_p2 or ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(exitcond3_fu_197_p2 == ap_const_lv1_0))) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_pp0_stg0_fsm_2 assign process. ///
always @ (ap_sig_bdd_85)
begin
if (ap_sig_bdd_85) begin
ap_sig_cseq_ST_pp0_stg0_fsm_2 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_pp0_stg0_fsm_2 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st1_fsm_0 assign process. ///
always @ (ap_sig_bdd_23)
begin
if (ap_sig_bdd_23) begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st2_fsm_1 assign process. ///
always @ (ap_sig_bdd_74)
begin
if (ap_sig_bdd_74) begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st5_fsm_3 assign process. ///
always @ (ap_sig_bdd_130)
begin
if (ap_sig_bdd_130) begin
ap_sig_cseq_ST_st5_fsm_3 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st5_fsm_3 = ap_const_logic_0;
end
end
/// ap_sig_ioackin_OUTPUT_STREAM_TREADY assign process. ///
always @ (OUTPUT_STREAM_TREADY or ap_reg_ioackin_OUTPUT_STREAM_TREADY)
begin
if ((ap_const_logic_0 == ap_reg_ioackin_OUTPUT_STREAM_TREADY)) begin
ap_sig_ioackin_OUTPUT_STREAM_TREADY = OUTPUT_STREAM_TREADY;
end else begin
ap_sig_ioackin_OUTPUT_STREAM_TREADY = ap_const_logic_1;
end
end
/// img_data_stream_0_V_read assign process. ///
always @ (exitcond4_reg_281 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_99 or ap_sig_ioackin_OUTPUT_STREAM_TREADY or ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
img_data_stream_0_V_read = ap_const_logic_1;
end else begin
img_data_stream_0_V_read = ap_const_logic_0;
end
end
/// img_data_stream_1_V_read assign process. ///
always @ (exitcond4_reg_281 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_99 or ap_sig_ioackin_OUTPUT_STREAM_TREADY or ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
img_data_stream_1_V_read = ap_const_logic_1;
end else begin
img_data_stream_1_V_read = ap_const_logic_0;
end
end
/// img_data_stream_2_V_read assign process. ///
always @ (exitcond4_reg_281 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_99 or ap_sig_ioackin_OUTPUT_STREAM_TREADY or ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
img_data_stream_2_V_read = ap_const_logic_1;
end else begin
img_data_stream_2_V_read = ap_const_logic_0;
end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (ap_CS_fsm or ap_sig_bdd_60 or exitcond3_fu_197_p2 or exitcond4_fu_208_p2 or exitcond4_reg_281 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_99 or ap_sig_ioackin_OUTPUT_STREAM_TREADY or ap_reg_ppiten_pp0_it1)
begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 :
begin
if (~ap_sig_bdd_60) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
end
ap_ST_st2_fsm_1 :
begin
if (~(exitcond3_fu_197_p2 == ap_const_lv1_0)) begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end else begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end
end
ap_ST_pp0_stg0_fsm_2 :
begin
if (~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(exitcond4_fu_208_p2 == ap_const_lv1_0))) begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(exitcond4_fu_208_p2 == ap_const_lv1_0))) begin
ap_NS_fsm = ap_ST_st5_fsm_3;
end else begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end
end
ap_ST_st5_fsm_3 :
begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end
default :
begin
ap_NS_fsm = 'bx;
end
endcase
end
assign OUTPUT_STREAM_TDATA = {{{{{{ap_const_lv8_FF}, {img_data_stream_2_V_dout}}}, {img_data_stream_1_V_dout}}}, {img_data_stream_0_V_dout}};
assign OUTPUT_STREAM_TDEST = ap_const_lv1_0;
assign OUTPUT_STREAM_TID = ap_const_lv1_0;
assign OUTPUT_STREAM_TKEEP = ap_const_lv4_F;
assign OUTPUT_STREAM_TLAST = axi_last_V_reg_290;
assign OUTPUT_STREAM_TSTRB = ap_const_lv4_0;
assign OUTPUT_STREAM_TUSER = tmp_user_V_fu_96;
/// ap_sig_bdd_130 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_130 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_3]);
end
/// ap_sig_bdd_23 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_23 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end
/// ap_sig_bdd_60 assign process. ///
always @ (ap_start or ap_done_reg)
begin
ap_sig_bdd_60 = ((ap_start == ap_const_logic_0) | (ap_done_reg == ap_const_logic_1));
end
/// ap_sig_bdd_74 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_74 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1]);
end
/// ap_sig_bdd_85 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_85 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2]);
end
/// ap_sig_bdd_99 assign process. ///
always @ (img_data_stream_0_V_empty_n or img_data_stream_1_V_empty_n or img_data_stream_2_V_empty_n or exitcond4_reg_281)
begin
ap_sig_bdd_99 = (((img_data_stream_0_V_empty_n == ap_const_logic_0) & (exitcond4_reg_281 == ap_const_lv1_0)) | ((exitcond4_reg_281 == ap_const_lv1_0) & (img_data_stream_1_V_empty_n == ap_const_logic_0)) | ((exitcond4_reg_281 == ap_const_lv1_0) & (img_data_stream_2_V_empty_n == ap_const_logic_0)));
end
assign axi_last_V_fu_223_p2 = (tmp_cast_35_fu_219_p1 == op2_assign_reg_267? 1'b1: 1'b0);
assign exitcond3_fu_197_p2 = (p_s_reg_159 == img_rows_V_read? 1'b1: 1'b0);
assign exitcond4_fu_208_p2 = (p_3_reg_170 == img_cols_V_read? 1'b1: 1'b0);
assign i_V_fu_202_p2 = (p_s_reg_159 + ap_const_lv12_1);
assign j_V_fu_213_p2 = (p_3_reg_170 + ap_const_lv12_1);
assign op2_assign_fu_186_p2 = ($signed(tmp_cast_fu_182_p1) + $signed(ap_const_lv13_1FFF));
assign tmp_cast_35_fu_219_p1 = p_3_reg_170;
assign tmp_cast_fu_182_p1 = img_cols_V_read;
endmodule //image_filter_Mat2AXIvideo
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:56:25 03/27/2014
// Design Name:
// Module Name: alu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module addsub(/*AUTOARG*/
// Outputs
data_c,overflow,
// Inputs
data_a, data_b, sign, addsub
);
// input clk;
input [31:0] data_a;
input [31:0] data_b;
//input [31:0] data_c;
input sign;
input addsub;
output overflow;
reg [32:0] temp;
output reg [31:0] data_c;
always @(/*AUTOSENSE*/addsub or data_a or data_b or sign) begin
case ({addsub, sign})
00:
temp <= {data_a[31], data_a} + {data_b[31], data_b};
01:
temp[31:0] <= data_a + data_b;
10:
temp <= {data_b[31], data_b} - {data_a[31], data_a};
11:
temp[31:0] <= data_b - data_a;
default:
data_c <= 32'h00000000;
endcase // case ({add_sub, sign})
data_c <= temp[31:0];
end
assign overflow = temp[32] != temp[31];
endmodule // addsub
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21AI_BLACKBOX_V
`define SKY130_FD_SC_HVL__O21AI_BLACKBOX_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__o21ai (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21AI_BLACKBOX_V
|
module lsu_transit_table(
in_wftag_resp,
in_wfid,
in_lddst_stsrc_addr,
in_exec_value,
in_gm_or_lds,
in_rd_en,
in_wr_en,
in_instr_pc,
out_exec_value,
out_gm_or_lds,
out_lddst_stsrc_addr,
out_reg_wr_en,
out_instr_pc,
clk,
rst
);
input [6:0] in_wftag_resp;
input [5:0] in_wfid;
input [11:0] in_lddst_stsrc_addr;
input [63:0] in_exec_value;
input in_gm_or_lds;
input [3:0] in_rd_en;
input [3:0] in_wr_en;
input [31:0] in_instr_pc;
output [63:0] out_exec_value;
output out_gm_or_lds;
output [11:0] out_lddst_stsrc_addr;
output [3:0] out_reg_wr_en;
output [31:0] out_instr_pc;
input clk;
input rst;
wire enable;
assign enable = |{in_rd_en,in_wr_en};
reg_40xX_1r_1w #(12) lddst_stsrc_addr(
.rd_addr(in_wftag_resp[6:1]),
.rd_data(out_lddst_stsrc_addr),
.wr_en(enable),
.wr_addr(in_wfid),
.wr_data(in_lddst_stsrc_addr),
.clk(clk),
.rst(rst)
);
reg_40xX_1r_1w #(64) exec_value(
.rd_addr(in_wftag_resp[6:1]),
.rd_data(out_exec_value),
.wr_en(enable),
.wr_addr(in_wfid),
.wr_data(in_exec_value),
.clk(clk),
.rst(rst)
);
reg_40xX_1r_1w #(1) gm_or_lds(
.rd_addr(in_wftag_resp[6:1]),
.rd_data(out_gm_or_lds),
.wr_en(enable),
.wr_addr(in_wfid),
.wr_data(in_gm_or_lds),
.clk(clk),
.rst(rst)
);
reg_40xX_1r_1w #(32) instr_pc(
.rd_addr(in_wftag_resp[6:1]),
.rd_data(out_instr_pc),
.wr_en(enable),
.wr_addr(in_wfid),
.wr_data(in_instr_pc),
.clk(clk),
.rst(rst)
);
reg_40xX_1r_1w #(4) register_wr_en(
.rd_addr(in_wftag_resp[6:1]),
//.rd_data(reg_wr_en),
.rd_data(out_reg_wr_en),
.wr_en(enable),
.wr_addr(in_wfid),
.wr_data(in_rd_en),
.clk(clk),
.rst(rst)
);
endmodule
|
/*
* Copyright (C) 2009 Onno Kortmann <[email protected]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
* THIS FILE HAS BEEN AUTOMATICALLY GENERATED FROM avr_tmpl.v.
* --- DO NOT EDIT MANUALLY! ---
*/
module ATtiny2313(clk, PA, PB, PD);
parameter progfile="UNSPECIFIED";
input clk;
inout [7:0] PA;
inout [7:0] PB;
inout [7:0] PD;
integer handle;
defparam core.progfile=progfile;
defparam core.name="attiny2313";
AVRCORE core(clk);
avr_pin #("A0") pa0(PA[0]);
avr_pin #("A1") pa1(PA[1]);
avr_pin #("A2") pa2(PA[2]);
avr_pin #("B0") pb0(PB[0]);
avr_pin #("B1") pb1(PB[1]);
avr_pin #("B2") pb2(PB[2]);
avr_pin #("B3") pb3(PB[3]);
avr_pin #("B4") pb4(PB[4]);
avr_pin #("B5") pb5(PB[5]);
avr_pin #("B6") pb6(PB[6]);
avr_pin #("B7") pb7(PB[7]);
avr_pin #("D0") pd0(PD[0]);
avr_pin #("D1") pd1(PD[1]);
avr_pin #("D2") pd2(PD[2]);
avr_pin #("D3") pd3(PD[3]);
avr_pin #("D4") pd4(PD[4]);
avr_pin #("D5") pd5(PD[5]);
avr_pin #("D6") pd6(PD[6]);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:23:44 11/04/2014
// Design Name:
// Module Name: addn
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:31:47 11/05/2014
// Design Name:
// Module Name: adder
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
/////////////////////////////////////////////////////////////////////////////////
module addn(
store000_0,
store001_0,
store010_0,
store100_0,
store101_0,
store110_0,
store000_1,
store001_1,
store010_1,
store100_1,
store101_1,
store110_1,
clock,
store000_0_out,
store001_0_out,
store010_0_out,
store100_0_out,
store101_0_out,
store110_0_out
);
// Input wire for the first number of DBNS Representation
input [3:0] store000_0;
input [3:0] store001_0;
input [3:0] store010_0;
input [3:0] store100_0;
input [3:0] store101_0;
input [3:0] store110_0;
// Input wire for the second number of the DBNS Representation
input [3:0] store000_1;
input [3:0] store001_1;
input [3:0] store010_1;
input [3:0] store100_1;
input [3:0] store101_1;
input [3:0] store110_1;
input clock;
// Output wires for the final representation in DBNS
output [3:0] store000_0_out;
output [3:0] store001_0_out;
output [3:0] store010_0_out;
output [3:0] store100_0_out;
output [3:0] store101_0_out;
output [3:0] store110_0_out;
reg [7:0] store000_temp;
reg [7:0] store001_temp;
reg [7:0] store010_temp;
reg [7:0] store100_temp;
reg [7:0] store101_temp;
reg [7:0] store110_temp;
reg [5:0] C_in = 6'b000000;
reg [5:0] C_out;
integer i;
always@(*)
begin
for(i=0;i<4;i=i+1)
begin
store000_temp[2*i+1:2*i] = {1'b0,store000_0[i]} + {1'b0,store000_1[i]};
store001_temp[2*i+1:2*i] = {1'b0,store001_0[i]} + {1'b0,store001_1[i]};
store010_temp[2*i+1:2*i] = {1'b0,store010_0[i]} + {1'b0,store010_1[i]};
store100_temp[2*i+1:2*i] = {1'b0,store100_0[i]} + {1'b0,store100_1[i]};
store101_temp[2*i+1:2*i] = {1'b0,store101_0[i]} + {1'b0,store101_1[i]};
store110_temp[2*i+1:2*i] = {1'b0,store110_0[i]} + {1'b0,store110_1[i]};
end
end
always@(*)
begin
case(store000_temp[7:0])
8'b00000000 : begin store000_0_out = 4'b0000; Cout = 6'b000000; end
8'b00000001 : begin store000_0_out = 4'b0001; Cout = 6'b000000; end
8'b00000010 : begin store000_0_out = 4'b0010; Cout = 6'b000000; end
//8'b00000011 : store
8'b00000100 : begin store000_0_out = 4'b0010; Cout = 6'b000000; end
8'b00000101 : begin store000_0_out = 4'b0100; Cout = 6'b000000; end
8'b00000110 : begin store000_0_out = 4'b0010; Cout = 6'b000000; end
//8'b00000111 : begin store000_0_out = 4'b0010; Cout = 6'b000000; end
8'b00001000 : begin store000_0_out = 4'b0010; Cout = 6'b000000; end
8'b00001001 : begin store000_0_out = 4'b0110; Cout = 6'b000000; end
8'b00001010 : begin store000_0_out = 4'b0101; Cout = 6'b000000; end
//8'b00001011 : begin store000_0_out = 4'b0010; Cout = 6'b000000; end
//8'b00001100 : begin store000_0_out = 4'b0010; Cout = 6'b000000; end
//8'b00001101 : store
//8'b00001110 : store
//8'b00001111 : store
8'b00010000 : begin store000_0_out = 4'b0010; Cout = 6'b000000; end
8'b00010001 : store
8'b00010010 : store
8'b00010011 : store
8'b00010100 : store
8'b00010101 : store
8'b00010110 : store
8'b00010111 : store
8'b00011000 : store
8'b00011001 : store
8'b00011010 : store
8'b00011011 : store
8'b00011100 : store
8'b00011101 : store
8'b00011110 : store
8'b00011111 : store
//////////////////////
8'b00100000 : store
8'b00100001 : store
8'b00100010 : store
8'b00100011 : store
8'b00100100 : store
8'b00100101 : store
8'b00100110 : store
8'b00100111 : store
8'b00101000 : store
8'b00101001 : store
8'b00101010 : store
8'b00101011 : store
8'b00101100 : store
8'b00101101 : store
8'b00101110 : store
8'b00101111 : store
8'b00110000 : store
8'b00110001 : store
8'b00110010 : store
8'b00110011 : store
8'b00110100 : store
8'b00110101 : store
8'b00110110 : store
8'b00110111 : store
8'b00111000 : store
8'b00111001 : store
8'b00111010 : store
8'b00111011 : store
8'b00111100 : store
8'b00111101 : store
8'b00111110 : store
8'b00111111 : store
///////////////////////////
8'b01000000 : store
8'b01000001 : store
8'b01000010 : store
8'b01000011 : store
8'b01000100 : store
8'b01000101 : store
8'b01000110 : store
8'b01000111 : store
8'b01001000 : store
8'b01001001 : store
8'b01001010 : store
8'b01001011 : store
8'b01001100 : store
8'b01001101 : store
8'b01001110 : store
8'b01001111 : store
8'b01010000 : store
8'b01010001 : store
8'b01010010 : store
8'b01010011 : store
8'b01010100 : store
8'b01010101 : store
8'b01010110 : store
8'b01010111 : store
8'b01011000 : store
8'b01011001 : store
8'b01011010 : store
8'b01011011 : store
8'b01011100 : store
8'b01011101 : store
8'b01011110 : store
8'b01011111 : store
///////////////////////
8'b01100000 : store
8'b01100001 : store
8'b01100010 : store
8'b01100011 : store
8'b01100100 : store
8'b01100101 : store
8'b01100110 : store
8'b01100111 : store
8'b01101000 : store
8'b01101001 : store
8'b01101010 : store
8'b01101011 : store
8'b01101100 : store
8'b01101101 : store
8'b01101110 : store
8'b01101111 : store
8'b01110000 : store
8'b01110001 : store
8'b01110010 : store
8'b01110011 : store
8'b01110100 : store
8'b01110101 : store
8'b01110110 : store
8'b01110111 : store
8'b01111000 : store
8'b01111001 : store
8'b01111010 : store
8'b01111011 : store
8'b01111100 : store
8'b01111101 : store
8'b01111110 : store
8'b01111111 : store
/////////////////////////////////
8'b10000000 : store
8'b10000001 : store
8'b10000010 : store
8'b10000011 : store
8'b10000100 : store
8'b10000101 : store
8'b10000110 : store
8'b10000111 : store
8'b10001000 : store
8'b10001001 : store
8'b10001010 : store
8'b10001011 : store
8'b10001100 : store
8'b10001101 : store
8'b10001110 : store
8'b10001111 : store
8'b10010000 : store
8'b10010001 : store
8'b10010010 : store
8'b10010011 : store
8'b10010100 : store
8'b10010101 : store
8'b10010110 : store
8'b10010111 : store
8'b10011000 : store
8'b10011001 : store
8'b10011010 : store
8'b10011011 : store
8'b10011100 : store
8'b10011101 : store
8'b10011110 : store
8'b10011111 : store
///////////////////////////////
8'b10100000 : store
8'b10100001 : store
8'b10100010 : store
8'b10100011 : store
8'b10100100 : store
8'b10100101 : store
8'b10100110 : store
8'b10100111 : store
8'b10101000 : store
8'b10101001 : store
8'b10101010 : store
8'b10101011 : store
8'b10101100 : store
8'b10101101 : store
8'b10101110 : store
8'b10101111 : store
8'b10110000 : store
8'b10110001 : store
8'b10110010 : store
8'b10110011 : store
8'b10110100 : store
8'b10110101 : store
8'b10110110 : store
8'b10110111 : store
8'b10111000 : store
8'b10111001 : store
8'b10111010 : store
8'b10111011 : store
8'b10111100 : store
8'b10111101 : store
8'b10111110 : store
8'b10111111 : store
endcase
case(store001_temp[7:0])
8'b00000000 : store
8'b00000001 : store
8'b00000010 : store
8'b00000011 : store
8'b00000100 : store
8'b00000101 : store
8'b00000110 : store
8'b00000111 : store
8'b00001000 : store
8'b00001001 : store
8'b00001010 : store
8'b00001011 : store
8'b00001100 : store
8'b00001101 : store
8'b00001110 : store
8'b00001111 : store
8'b00010000 : store
8'b00010001 : store
8'b00010010 : store
8'b00010011 : store
8'b00010100 : store
8'b00010101 : store
8'b00010110 : store
8'b00010111 : store
8'b00011000 : store
8'b00011001 : store
8'b00011010 : store
8'b00011011 : store
8'b00011100 : store
8'b00011101 : store
8'b00011110 : store
8'b00011111 : store
//////////////////////
8'b00100000 : store
8'b00100001 : store
8'b00100010 : store
8'b00100011 : store
8'b00100100 : store
8'b00100101 : store
8'b00100110 : store
8'b00100111 : store
8'b00101000 : store
8'b00101001 : store
8'b00101010 : store
8'b00101011 : store
8'b00101100 : store
8'b00101101 : store
8'b00101110 : store
8'b00101111 : store
8'b00110000 : store
8'b00110001 : store
8'b00110010 : store
8'b00110011 : store
8'b00110100 : store
8'b00110101 : store
8'b00110110 : store
8'b00110111 : store
8'b00111000 : store
8'b00111001 : store
8'b00111010 : store
8'b00111011 : store
8'b00111100 : store
8'b00111101 : store
8'b00111110 : store
8'b00111111 : store
///////////////////////////
8'b01000000 : store
8'b01000001 : store
8'b01000010 : store
8'b01000011 : store
8'b01000100 : store
8'b01000101 : store
8'b01000110 : store
8'b01000111 : store
8'b01001000 : store
8'b01001001 : store
8'b01001010 : store
8'b01001011 : store
8'b01001100 : store
8'b01001101 : store
8'b01001110 : store
8'b01001111 : store
8'b01010000 : store
8'b01010001 : store
8'b01010010 : store
8'b01010011 : store
8'b01010100 : store
8'b01010101 : store
8'b01010110 : store
8'b01010111 : store
8'b01011000 : store
8'b01011001 : store
8'b01011010 : store
8'b01011011 : store
8'b01011100 : store
8'b01011101 : store
8'b01011110 : store
8'b01011111 : store
///////////////////////
8'b01100000 : store
8'b01100001 : store
8'b01100010 : store
8'b01100011 : store
8'b01100100 : store
8'b01100101 : store
8'b01100110 : store
8'b01100111 : store
8'b01101000 : store
8'b01101001 : store
8'b01101010 : store
8'b01101011 : store
8'b01101100 : store
8'b01101101 : store
8'b01101110 : store
8'b01101111 : store
8'b01110000 : store
8'b01110001 : store
8'b01110010 : store
8'b01110011 : store
8'b01110100 : store
8'b01110101 : store
8'b01110110 : store
8'b01110111 : store
8'b01111000 : store
8'b01111001 : store
8'b01111010 : store
8'b01111011 : store
8'b01111100 : store
8'b01111101 : store
8'b01111110 : store
8'b01111111 : store
/////////////////////////////////
8'b10000000 : store
8'b10000001 : store
8'b10000010 : store
8'b10000011 : store
8'b10000100 : store
8'b10000101 : store
8'b10000110 : store
8'b10000111 : store
8'b10001000 : store
8'b10001001 : store
8'b10001010 : store
8'b10001011 : store
8'b10001100 : store
8'b10001101 : store
8'b10001110 : store
8'b10001111 : store
8'b10010000 : store
8'b10010001 : store
8'b10010010 : store
8'b10010011 : store
8'b10010100 : store
8'b10010101 : store
8'b10010110 : store
8'b10010111 : store
8'b10011000 : store
8'b10011001 : store
8'b10011010 : store
8'b10011011 : store
8'b10011100 : store
8'b10011101 : store
8'b10011110 : store
8'b10011111 : store
///////////////////////////////
8'b10100000 : store
8'b10100001 : store
8'b10100010 : store
8'b10100011 : store
8'b10100100 : store
8'b10100101 : store
8'b10100110 : store
8'b10100111 : store
8'b10101000 : store
8'b10101001 : store
8'b10101010 : store
8'b10101011 : store
8'b10101100 : store
8'b10101101 : store
8'b10101110 : store
8'b10101111 : store
8'b10110000 : store
8'b10110001 : store
8'b10110010 : store
8'b10110011 : store
8'b10110100 : store
8'b10110101 : store
8'b10110110 : store
8'b10110111 : store
8'b10111000 : store
8'b10111001 : store
8'b10111010 : store
8'b10111011 : store
8'b10111100 : store
8'b10111101 : store
8'b10111110 : store
8'b10111111 : store
endcase
case(store010_temp[7:0])
8'b00000000 : store
8'b00000001 : store
8'b00000010 : store
8'b00000011 : store
8'b00000100 : store
8'b00000101 : store
8'b00000110 : store
8'b00000111 : store
8'b00001000 : store
8'b00001001 : store
8'b00001010 : store
8'b00001011 : store
8'b00001100 : store
8'b00001101 : store
8'b00001110 : store
8'b00001111 : store
8'b00010000 : store
8'b00010001 : store
8'b00010010 : store
8'b00010011 : store
8'b00010100 : store
8'b00010101 : store
8'b00010110 : store
8'b00010111 : store
8'b00011000 : store
8'b00011001 : store
8'b00011010 : store
8'b00011011 : store
8'b00011100 : store
8'b00011101 : store
8'b00011110 : store
8'b00011111 : store
//////////////////////
8'b00100000 : store
8'b00100001 : store
8'b00100010 : store
8'b00100011 : store
8'b00100100 : store
8'b00100101 : store
8'b00100110 : store
8'b00100111 : store
8'b00101000 : store
8'b00101001 : store
8'b00101010 : store
8'b00101011 : store
8'b00101100 : store
8'b00101101 : store
8'b00101110 : store
8'b00101111 : store
8'b00110000 : store
8'b00110001 : store
8'b00110010 : store
8'b00110011 : store
8'b00110100 : store
8'b00110101 : store
8'b00110110 : store
8'b00110111 : store
8'b00111000 : store
8'b00111001 : store
8'b00111010 : store
8'b00111011 : store
8'b00111100 : store
8'b00111101 : store
8'b00111110 : store
8'b00111111 : store
///////////////////////////
8'b01000000 : store
8'b01000001 : store
8'b01000010 : store
8'b01000011 : store
8'b01000100 : store
8'b01000101 : store
8'b01000110 : store
8'b01000111 : store
8'b01001000 : store
8'b01001001 : store
8'b01001010 : store
8'b01001011 : store
8'b01001100 : store
8'b01001101 : store
8'b01001110 : store
8'b01001111 : store
8'b01010000 : store
8'b01010001 : store
8'b01010010 : store
8'b01010011 : store
8'b01010100 : store
8'b01010101 : store
8'b01010110 : store
8'b01010111 : store
8'b01011000 : store
8'b01011001 : store
8'b01011010 : store
8'b01011011 : store
8'b01011100 : store
8'b01011101 : store
8'b01011110 : store
8'b01011111 : store
///////////////////////
8'b01100000 : store
8'b01100001 : store
8'b01100010 : store
8'b01100011 : store
8'b01100100 : store
8'b01100101 : store
8'b01100110 : store
8'b01100111 : store
8'b01101000 : store
8'b01101001 : store
8'b01101010 : store
8'b01101011 : store
8'b01101100 : store
8'b01101101 : store
8'b01101110 : store
8'b01101111 : store
8'b01110000 : store
8'b01110001 : store
8'b01110010 : store
8'b01110011 : store
8'b01110100 : store
8'b01110101 : store
8'b01110110 : store
8'b01110111 : store
8'b01111000 : store
8'b01111001 : store
8'b01111010 : store
8'b01111011 : store
8'b01111100 : store
8'b01111101 : store
8'b01111110 : store
8'b01111111 : store
/////////////////////////////////
8'b10000000 : store
8'b10000001 : store
8'b10000010 : store
8'b10000011 : store
8'b10000100 : store
8'b10000101 : store
8'b10000110 : store
8'b10000111 : store
8'b10001000 : store
8'b10001001 : store
8'b10001010 : store
8'b10001011 : store
8'b10001100 : store
8'b10001101 : store
8'b10001110 : store
8'b10001111 : store
8'b10010000 : store
8'b10010001 : store
8'b10010010 : store
8'b10010011 : store
8'b10010100 : store
8'b10010101 : store
8'b10010110 : store
8'b10010111 : store
8'b10011000 : store
8'b10011001 : store
8'b10011010 : store
8'b10011011 : store
8'b10011100 : store
8'b10011101 : store
8'b10011110 : store
8'b10011111 : store
///////////////////////////////
8'b10100000 : store
8'b10100001 : store
8'b10100010 : store
8'b10100011 : store
8'b10100100 : store
8'b10100101 : store
8'b10100110 : store
8'b10100111 : store
8'b10101000 : store
8'b10101001 : store
8'b10101010 : store
8'b10101011 : store
8'b10101100 : store
8'b10101101 : store
8'b10101110 : store
8'b10101111 : store
8'b10110000 : store
8'b10110001 : store
8'b10110010 : store
8'b10110011 : store
8'b10110100 : store
8'b10110101 : store
8'b10110110 : store
8'b10110111 : store
8'b10111000 : store
8'b10111001 : store
8'b10111010 : store
8'b10111011 : store
8'b10111100 : store
8'b10111101 : store
8'b10111110 : store
8'b10111111 : store
endcase
case(store100_temp[7:0])
8'b00000000 : store
8'b00000001 : store
8'b00000010 : store
8'b00000011 : store
8'b00000100 : store
8'b00000101 : store
8'b00000110 : store
8'b00000111 : store
8'b00001000 : store
8'b00001001 : store
8'b00001010 : store
8'b00001011 : store
8'b00001100 : store
8'b00001101 : store
8'b00001110 : store
8'b00001111 : store
8'b00010000 : store
8'b00010001 : store
8'b00010010 : store
8'b00010011 : store
8'b00010100 : store
8'b00010101 : store
8'b00010110 : store
8'b00010111 : store
8'b00011000 : store
8'b00011001 : store
8'b00011010 : store
8'b00011011 : store
8'b00011100 : store
8'b00011101 : store
8'b00011110 : store
8'b00011111 : store
//////////////////////
8'b00100000 : store
8'b00100001 : store
8'b00100010 : store
8'b00100011 : store
8'b00100100 : store
8'b00100101 : store
8'b00100110 : store
8'b00100111 : store
8'b00101000 : store
8'b00101001 : store
8'b00101010 : store
8'b00101011 : store
8'b00101100 : store
8'b00101101 : store
8'b00101110 : store
8'b00101111 : store
8'b00110000 : store
8'b00110001 : store
8'b00110010 : store
8'b00110011 : store
8'b00110100 : store
8'b00110101 : store
8'b00110110 : store
8'b00110111 : store
8'b00111000 : store
8'b00111001 : store
8'b00111010 : store
8'b00111011 : store
8'b00111100 : store
8'b00111101 : store
8'b00111110 : store
8'b00111111 : store
///////////////////////////
8'b01000000 : store
8'b01000001 : store
8'b01000010 : store
8'b01000011 : store
8'b01000100 : store
8'b01000101 : store
8'b01000110 : store
8'b01000111 : store
8'b01001000 : store
8'b01001001 : store
8'b01001010 : store
8'b01001011 : store
8'b01001100 : store
8'b01001101 : store
8'b01001110 : store
8'b01001111 : store
8'b01010000 : store
8'b01010001 : store
8'b01010010 : store
8'b01010011 : store
8'b01010100 : store
8'b01010101 : store
8'b01010110 : store
8'b01010111 : store
8'b01011000 : store
8'b01011001 : store
8'b01011010 : store
8'b01011011 : store
8'b01011100 : store
8'b01011101 : store
8'b01011110 : store
8'b01011111 : store
///////////////////////
8'b01100000 : store
8'b01100001 : store
8'b01100010 : store
8'b01100011 : store
8'b01100100 : store
8'b01100101 : store
8'b01100110 : store
8'b01100111 : store
8'b01101000 : store
8'b01101001 : store
8'b01101010 : store
8'b01101011 : store
8'b01101100 : store
8'b01101101 : store
8'b01101110 : store
8'b01101111 : store
8'b01110000 : store
8'b01110001 : store
8'b01110010 : store
8'b01110011 : store
8'b01110100 : store
8'b01110101 : store
8'b01110110 : store
8'b01110111 : store
8'b01111000 : store
8'b01111001 : store
8'b01111010 : store
8'b01111011 : store
8'b01111100 : store
8'b01111101 : store
8'b01111110 : store
8'b01111111 : store
/////////////////////////////////
8'b10000000 : store
8'b10000001 : store
8'b10000010 : store
8'b10000011 : store
8'b10000100 : store
8'b10000101 : store
8'b10000110 : store
8'b10000111 : store
8'b10001000 : store
8'b10001001 : store
8'b10001010 : store
8'b10001011 : store
8'b10001100 : store
8'b10001101 : store
8'b10001110 : store
8'b10001111 : store
8'b10010000 : store
8'b10010001 : store
8'b10010010 : store
8'b10010011 : store
8'b10010100 : store
8'b10010101 : store
8'b10010110 : store
8'b10010111 : store
8'b10011000 : store
8'b10011001 : store
8'b10011010 : store
8'b10011011 : store
8'b10011100 : store
8'b10011101 : store
8'b10011110 : store
8'b10011111 : store
///////////////////////////////
8'b10100000 : store
8'b10100001 : store
8'b10100010 : store
8'b10100011 : store
8'b10100100 : store
8'b10100101 : store
8'b10100110 : store
8'b10100111 : store
8'b10101000 : store
8'b10101001 : store
8'b10101010 : store
8'b10101011 : store
8'b10101100 : store
8'b10101101 : store
8'b10101110 : store
8'b10101111 : store
8'b10110000 : store
8'b10110001 : store
8'b10110010 : store
8'b10110011 : store
8'b10110100 : store
8'b10110101 : store
8'b10110110 : store
8'b10110111 : store
8'b10111000 : store
8'b10111001 : store
8'b10111010 : store
8'b10111011 : store
8'b10111100 : store
8'b10111101 : store
8'b10111110 : store
8'b10111111 : store
endcase
case(store101_temp[7:0])
8'b00000000 : store
8'b00000001 : store
8'b00000010 : store
8'b00000011 : store
8'b00000100 : store
8'b00000101 : store
8'b00000110 : store
8'b00000111 : store
8'b00001000 : store
8'b00001001 : store
8'b00001010 : store
8'b00001011 : store
8'b00001100 : store
8'b00001101 : store
8'b00001110 : store
8'b00001111 : store
8'b00010000 : store
8'b00010001 : store
8'b00010010 : store
8'b00010011 : store
8'b00010100 : store
8'b00010101 : store
8'b00010110 : store
8'b00010111 : store
8'b00011000 : store
8'b00011001 : store
8'b00011010 : store
8'b00011011 : store
8'b00011100 : store
8'b00011101 : store
8'b00011110 : store
8'b00011111 : store
//////////////////////
8'b00100000 : store
8'b00100001 : store
8'b00100010 : store
8'b00100011 : store
8'b00100100 : store
8'b00100101 : store
8'b00100110 : store
8'b00100111 : store
8'b00101000 : store
8'b00101001 : store
8'b00101010 : store
8'b00101011 : store
8'b00101100 : store
8'b00101101 : store
8'b00101110 : store
8'b00101111 : store
8'b00110000 : store
8'b00110001 : store
8'b00110010 : store
8'b00110011 : store
8'b00110100 : store
8'b00110101 : store
8'b00110110 : store
8'b00110111 : store
8'b00111000 : store
8'b00111001 : store
8'b00111010 : store
8'b00111011 : store
8'b00111100 : store
8'b00111101 : store
8'b00111110 : store
8'b00111111 : store
///////////////////////////
8'b01000000 : store
8'b01000001 : store
8'b01000010 : store
8'b01000011 : store
8'b01000100 : store
8'b01000101 : store
8'b01000110 : store
8'b01000111 : store
8'b01001000 : store
8'b01001001 : store
8'b01001010 : store
8'b01001011 : store
8'b01001100 : store
8'b01001101 : store
8'b01001110 : store
8'b01001111 : store
8'b01010000 : store
8'b01010001 : store
8'b01010010 : store
8'b01010011 : store
8'b01010100 : store
8'b01010101 : store
8'b01010110 : store
8'b01010111 : store
8'b01011000 : store
8'b01011001 : store
8'b01011010 : store
8'b01011011 : store
8'b01011100 : store
8'b01011101 : store
8'b01011110 : store
8'b01011111 : store
///////////////////////
8'b01100000 : store
8'b01100001 : store
8'b01100010 : store
8'b01100011 : store
8'b01100100 : store
8'b01100101 : store
8'b01100110 : store
8'b01100111 : store
8'b01101000 : store
8'b01101001 : store
8'b01101010 : store
8'b01101011 : store
8'b01101100 : store
8'b01101101 : store
8'b01101110 : store
8'b01101111 : store
8'b01110000 : store
8'b01110001 : store
8'b01110010 : store
8'b01110011 : store
8'b01110100 : store
8'b01110101 : store
8'b01110110 : store
8'b01110111 : store
8'b01111000 : store
8'b01111001 : store
8'b01111010 : store
8'b01111011 : store
8'b01111100 : store
8'b01111101 : store
8'b01111110 : store
8'b01111111 : store
/////////////////////////////////
8'b10000000 : store
8'b10000001 : store
8'b10000010 : store
8'b10000011 : store
8'b10000100 : store
8'b10000101 : store
8'b10000110 : store
8'b10000111 : store
8'b10001000 : store
8'b10001001 : store
8'b10001010 : store
8'b10001011 : store
8'b10001100 : store
8'b10001101 : store
8'b10001110 : store
8'b10001111 : store
8'b10010000 : store
8'b10010001 : store
8'b10010010 : store
8'b10010011 : store
8'b10010100 : store
8'b10010101 : store
8'b10010110 : store
8'b10010111 : store
8'b10011000 : store
8'b10011001 : store
8'b10011010 : store
8'b10011011 : store
8'b10011100 : store
8'b10011101 : store
8'b10011110 : store
8'b10011111 : store
///////////////////////////////
8'b10100000 : store
8'b10100001 : store
8'b10100010 : store
8'b10100011 : store
8'b10100100 : store
8'b10100101 : store
8'b10100110 : store
8'b10100111 : store
8'b10101000 : store
8'b10101001 : store
8'b10101010 : store
8'b10101011 : store
8'b10101100 : store
8'b10101101 : store
8'b10101110 : store
8'b10101111 : store
8'b10110000 : store
8'b10110001 : store
8'b10110010 : store
8'b10110011 : store
8'b10110100 : store
8'b10110101 : store
8'b10110110 : store
8'b10110111 : store
8'b10111000 : store
8'b10111001 : store
8'b10111010 : store
8'b10111011 : store
8'b10111100 : store
8'b10111101 : store
8'b10111110 : store
8'b10111111 : store
endcase
case(store101_temp[7:0])
8'b00000000 : store
8'b00000001 : store
8'b00000010 : store
8'b00000011 : store
8'b00000100 : store
8'b00000101 : store
8'b00000110 : store
8'b00000111 : store
8'b00001000 : store
8'b00001001 : store
8'b00001010 : store
8'b00001011 : store
8'b00001100 : store
8'b00001101 : store
8'b00001110 : store
8'b00001111 : store
8'b00010000 : store
8'b00010001 : store
8'b00010010 : store
8'b00010011 : store
8'b00010100 : store
8'b00010101 : store
8'b00010110 : store
8'b00010111 : store
8'b00011000 : store
8'b00011001 : store
8'b00011010 : store
8'b00011011 : store
8'b00011100 : store
8'b00011101 : store
8'b00011110 : store
8'b00011111 : store
//////////////////////
8'b00100000 : store
8'b00100001 : store
8'b00100010 : store
8'b00100011 : store
8'b00100100 : store
8'b00100101 : store
8'b00100110 : store
8'b00100111 : store
8'b00101000 : store
8'b00101001 : store
8'b00101010 : store
8'b00101011 : store
8'b00101100 : store
8'b00101101 : store
8'b00101110 : store
8'b00101111 : store
8'b00110000 : store
8'b00110001 : store
8'b00110010 : store
8'b00110011 : store
8'b00110100 : store
8'b00110101 : store
8'b00110110 : store
8'b00110111 : store
8'b00111000 : store
8'b00111001 : store
8'b00111010 : store
8'b00111011 : store
8'b00111100 : store
8'b00111101 : store
8'b00111110 : store
8'b00111111 : store
///////////////////////////
8'b01000000 : store
8'b01000001 : store
8'b01000010 : store
8'b01000011 : store
8'b01000100 : store
8'b01000101 : store
8'b01000110 : store
8'b01000111 : store
8'b01001000 : store
8'b01001001 : store
8'b01001010 : store
8'b01001011 : store
8'b01001100 : store
8'b01001101 : store
8'b01001110 : store
8'b01001111 : store
8'b01010000 : store
8'b01010001 : store
8'b01010010 : store
8'b01010011 : store
8'b01010100 : store
8'b01010101 : store
8'b01010110 : store
8'b01010111 : store
8'b01011000 : store
8'b01011001 : store
8'b01011010 : store
8'b01011011 : store
8'b01011100 : store
8'b01011101 : store
8'b01011110 : store
8'b01011111 : store
///////////////////////
8'b01100000 : store
8'b01100001 : store
8'b01100010 : store
8'b01100011 : store
8'b01100100 : store
8'b01100101 : store
8'b01100110 : store
8'b01100111 : store
8'b01101000 : store
8'b01101001 : store
8'b01101010 : store
8'b01101011 : store
8'b01101100 : store
8'b01101101 : store
8'b01101110 : store
8'b01101111 : store
8'b01110000 : store
8'b01110001 : store
8'b01110010 : store
8'b01110011 : store
8'b01110100 : store
8'b01110101 : store
8'b01110110 : store
8'b01110111 : store
8'b01111000 : store
8'b01111001 : store
8'b01111010 : store
8'b01111011 : store
8'b01111100 : store
8'b01111101 : store
8'b01111110 : store
8'b01111111 : store
/////////////////////////////////
8'b10000000 : store
8'b10000001 : store
8'b10000010 : store
8'b10000011 : store
8'b10000100 : store
8'b10000101 : store
8'b10000110 : store
8'b10000111 : store
8'b10001000 : store
8'b10001001 : store
8'b10001010 : store
8'b10001011 : store
8'b10001100 : store
8'b10001101 : store
8'b10001110 : store
8'b10001111 : store
8'b10010000 : store
8'b10010001 : store
8'b10010010 : store
8'b10010011 : store
8'b10010100 : store
8'b10010101 : store
8'b10010110 : store
8'b10010111 : store
8'b10011000 : store
8'b10011001 : store
8'b10011010 : store
8'b10011011 : store
8'b10011100 : store
8'b10011101 : store
8'b10011110 : store
8'b10011111 : store
///////////////////////////////
8'b10100000 : store
8'b10100001 : store
8'b10100010 : store
8'b10100011 : store
8'b10100100 : store
8'b10100101 : store
8'b10100110 : store
8'b10100111 : store
8'b10101000 : store
8'b10101001 : store
8'b10101010 : store
8'b10101011 : store
8'b10101100 : store
8'b10101101 : store
8'b10101110 : store
8'b10101111 : store
8'b10110000 : store
8'b10110001 : store
8'b10110010 : store
8'b10110011 : store
8'b10110100 : store
8'b10110101 : store
8'b10110110 : store
8'b10110111 : store
8'b10111000 : store
8'b10111001 : store
8'b10111010 : store
8'b10111011 : store
8'b10111100 : store
8'b10111101 : store
8'b10111110 : store
8'b10111111 : store
endcase
endmodule
?
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/14.1/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_clock_crosser.v $
// $Revision: #1 $
// $Date: 2014/10/06 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_clock_crosser(
in_clk,
in_reset,
in_ready,
in_valid,
in_data,
out_clk,
out_reset,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter FORWARD_SYNC_DEPTH = 2;
parameter BACKWARD_SYNC_DEPTH = 2;
parameter USE_OUTPUT_PIPELINE = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input in_clk;
input in_reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_clk;
input out_reset;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
// Data is guaranteed valid by control signal clock crossing. Cut data
// buffer false path.
(* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\" ; -name SDC_STATEMENT \"set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
reg [DATA_WIDTH-1:0] out_data_buffer;
reg in_data_toggle;
wire in_data_toggle_returned;
wire out_data_toggle;
reg out_data_toggle_flopped;
wire take_in_data;
wire out_data_taken;
wire out_valid_internal;
wire out_ready_internal;
assign in_ready = ~(in_data_toggle_returned ^ in_data_toggle);
assign take_in_data = in_valid & in_ready;
assign out_valid_internal = out_data_toggle ^ out_data_toggle_flopped;
assign out_data_taken = out_ready_internal & out_valid_internal;
always @(posedge in_clk or posedge in_reset) begin
if (in_reset) begin
in_data_buffer <= 'b0;
in_data_toggle <= 1'b0;
end else begin
if (take_in_data) begin
in_data_toggle <= ~in_data_toggle;
in_data_buffer <= in_data;
end
end //in_reset
end //in_clk always block
always @(posedge out_clk or posedge out_reset) begin
if (out_reset) begin
out_data_toggle_flopped <= 1'b0;
out_data_buffer <= 'b0;
end else begin
out_data_buffer <= in_data_buffer;
if (out_data_taken) begin
out_data_toggle_flopped <= out_data_toggle;
end
end //end if
end //out_clk always block
altera_std_synchronizer #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
.clk(out_clk),
.reset_n(~out_reset),
.din(in_data_toggle),
.dout(out_data_toggle)
);
altera_std_synchronizer #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
.clk(in_clk),
.reset_n(~in_reset),
.din(out_data_toggle_flopped),
.dout(in_data_toggle_returned)
);
generate if (USE_OUTPUT_PIPELINE == 1) begin
altera_avalon_st_pipeline_base
#(
.BITS_PER_SYMBOL(BITS_PER_SYMBOL),
.SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
) output_stage (
.clk(out_clk),
.reset(out_reset),
.in_ready(out_ready_internal),
.in_valid(out_valid_internal),
.in_data(out_data_buffer),
.out_ready(out_ready),
.out_valid(out_valid),
.out_data(out_data)
);
end else begin
assign out_valid = out_valid_internal;
assign out_ready_internal = out_ready;
assign out_data = out_data_buffer;
end
endgenerate
endmodule
|
// hps_sdram.v
// This file was auto-generated from altera_mem_if_hps_emif_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.1 188 at 2015.01.20.10:18:34
`timescale 1 ps / 1 ps
module hps_sdram (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire [0:0] mem_ck, // .mem_ck
output wire [0:0] mem_ck_n, // .mem_ck_n
output wire [0:0] mem_cke, // .mem_cke
output wire [0:0] mem_cs_n, // .mem_cs_n
output wire [3:0] mem_dm, // .mem_dm
output wire [0:0] mem_ras_n, // .mem_ras_n
output wire [0:0] mem_cas_n, // .mem_cas_n
output wire [0:0] mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire [0:0] mem_odt, // .mem_odt
input wire oct_rzqin // oct.rzqin
);
wire pll_afi_clk_clk; // pll:afi_clk -> [c0:afi_clk, p0:afi_clk]
wire pll_afi_half_clk_clk; // pll:afi_half_clk -> [c0:afi_half_clk, p0:afi_half_clk]
wire [4:0] p0_afi_afi_rlat; // p0:afi_rlat -> c0:afi_rlat
wire p0_afi_afi_cal_success; // p0:afi_cal_success -> c0:afi_cal_success
wire [79:0] p0_afi_afi_rdata; // p0:afi_rdata -> c0:afi_rdata
wire [3:0] p0_afi_afi_wlat; // p0:afi_wlat -> c0:afi_wlat
wire p0_afi_afi_cal_fail; // p0:afi_cal_fail -> c0:afi_cal_fail
wire [0:0] p0_afi_afi_rdata_valid; // p0:afi_rdata_valid -> c0:afi_rdata_valid
wire p0_afi_reset_reset; // p0:afi_reset_n -> c0:afi_reset_n
wire [4:0] c0_afi_afi_rdata_en_full; // c0:afi_rdata_en_full -> p0:afi_rdata_en_full
wire [0:0] c0_afi_afi_rst_n; // c0:afi_rst_n -> p0:afi_rst_n
wire [4:0] c0_afi_afi_dqs_burst; // c0:afi_dqs_burst -> p0:afi_dqs_burst
wire [19:0] c0_afi_afi_addr; // c0:afi_addr -> p0:afi_addr
wire [9:0] c0_afi_afi_dm; // c0:afi_dm -> p0:afi_dm
wire [0:0] c0_afi_afi_mem_clk_disable; // c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable
wire [0:0] c0_afi_afi_we_n; // c0:afi_we_n -> p0:afi_we_n
wire [4:0] c0_afi_afi_rdata_en; // c0:afi_rdata_en -> p0:afi_rdata_en
wire [1:0] c0_afi_afi_odt; // c0:afi_odt -> p0:afi_odt
wire [0:0] c0_afi_afi_ras_n; // c0:afi_ras_n -> p0:afi_ras_n
wire [1:0] c0_afi_afi_cke; // c0:afi_cke -> p0:afi_cke
wire [4:0] c0_afi_afi_wdata_valid; // c0:afi_wdata_valid -> p0:afi_wdata_valid
wire [79:0] c0_afi_afi_wdata; // c0:afi_wdata -> p0:afi_wdata
wire [2:0] c0_afi_afi_ba; // c0:afi_ba -> p0:afi_ba
wire [0:0] c0_afi_afi_cas_n; // c0:afi_cas_n -> p0:afi_cas_n
wire [1:0] c0_afi_afi_cs_n; // c0:afi_cs_n -> p0:afi_cs_n
wire [7:0] c0_hard_phy_cfg_cfg_tmrd; // c0:cfg_tmrd -> p0:cfg_tmrd
wire [23:0] c0_hard_phy_cfg_cfg_dramconfig; // c0:cfg_dramconfig -> p0:cfg_dramconfig
wire [7:0] c0_hard_phy_cfg_cfg_rowaddrwidth; // c0:cfg_rowaddrwidth -> p0:cfg_rowaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_devicewidth; // c0:cfg_devicewidth -> p0:cfg_devicewidth
wire [15:0] c0_hard_phy_cfg_cfg_trefi; // c0:cfg_trefi -> p0:cfg_trefi
wire [7:0] c0_hard_phy_cfg_cfg_tcl; // c0:cfg_tcl -> p0:cfg_tcl
wire [7:0] c0_hard_phy_cfg_cfg_csaddrwidth; // c0:cfg_csaddrwidth -> p0:cfg_csaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_coladdrwidth; // c0:cfg_coladdrwidth -> p0:cfg_coladdrwidth
wire [7:0] c0_hard_phy_cfg_cfg_trfc; // c0:cfg_trfc -> p0:cfg_trfc
wire [7:0] c0_hard_phy_cfg_cfg_addlat; // c0:cfg_addlat -> p0:cfg_addlat
wire [7:0] c0_hard_phy_cfg_cfg_bankaddrwidth; // c0:cfg_bankaddrwidth -> p0:cfg_bankaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_interfacewidth; // c0:cfg_interfacewidth -> p0:cfg_interfacewidth
wire [7:0] c0_hard_phy_cfg_cfg_twr; // c0:cfg_twr -> p0:cfg_twr
wire [7:0] c0_hard_phy_cfg_cfg_caswrlat; // c0:cfg_caswrlat -> p0:cfg_caswrlat
wire p0_ctl_clk_clk; // p0:ctl_clk -> c0:ctl_clk
wire p0_ctl_reset_reset; // p0:ctl_reset_n -> c0:ctl_reset_n
wire p0_io_int_io_intaficalfail; // p0:io_intaficalfail -> c0:io_intaficalfail
wire p0_io_int_io_intaficalsuccess; // p0:io_intaficalsuccess -> c0:io_intaficalsuccess
wire [15:0] oct_oct_sharing_parallelterminationcontrol; // oct:parallelterminationcontrol -> p0:parallelterminationcontrol
wire [15:0] oct_oct_sharing_seriesterminationcontrol; // oct:seriesterminationcontrol -> p0:seriesterminationcontrol
wire pll_pll_sharing_pll_write_clk; // pll:pll_write_clk -> p0:pll_write_clk
wire pll_pll_sharing_pll_avl_clk; // pll:pll_avl_clk -> p0:pll_avl_clk
wire pll_pll_sharing_pll_write_clk_pre_phy_clk; // pll:pll_write_clk_pre_phy_clk -> p0:pll_write_clk_pre_phy_clk
wire pll_pll_sharing_pll_addr_cmd_clk; // pll:pll_addr_cmd_clk -> p0:pll_addr_cmd_clk
wire pll_pll_sharing_pll_config_clk; // pll:pll_config_clk -> p0:pll_config_clk
wire pll_pll_sharing_pll_avl_phy_clk; // pll:pll_avl_phy_clk -> p0:pll_avl_phy_clk
wire pll_pll_sharing_afi_phy_clk; // pll:afi_phy_clk -> p0:afi_phy_clk
wire pll_pll_sharing_pll_mem_clk; // pll:pll_mem_clk -> p0:pll_mem_clk
wire pll_pll_sharing_pll_locked; // pll:pll_locked -> p0:pll_locked
wire pll_pll_sharing_pll_mem_phy_clk; // pll:pll_mem_phy_clk -> p0:pll_mem_phy_clk
wire p0_dll_clk_clk; // p0:dll_clk -> dll:clk
wire p0_dll_sharing_dll_pll_locked; // p0:dll_pll_locked -> dll:dll_pll_locked
wire [6:0] dll_dll_sharing_dll_delayctrl; // dll:dll_delayctrl -> p0:dll_delayctrl
hps_sdram_pll pll (
.global_reset_n (global_reset_n), // global_reset.reset_n
.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk) // .pll_avl_phy_clk
);
hps_sdram_p0 p0 (
.global_reset_n (global_reset_n), // global_reset.reset_n
.soft_reset_n (soft_reset_n), // soft_reset.reset_n
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.afi_reset_export_n (), // afi_reset_export.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.avl_clk (), // avl_clk.clk
.avl_reset_n (), // avl_reset.reset_n
.scc_clk (), // scc_clk.clk
.scc_reset_n (), // scc_reset.reset_n
.avl_address (), // avl.address
.avl_write (), // .write
.avl_writedata (), // .writedata
.avl_read (), // .read
.avl_readdata (), // .readdata
.avl_waitrequest (), // .waitrequest
.dll_clk (p0_dll_clk_clk), // dll_clk.clk
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.scc_data (), // scc.scc_data
.scc_dqs_ena (), // .scc_dqs_ena
.scc_dqs_io_ena (), // .scc_dqs_io_ena
.scc_dq_ena (), // .scc_dq_ena
.scc_dm_ena (), // .scc_dm_ena
.capture_strobe_tracking (), // .capture_strobe_tracking
.scc_upd (), // .scc_upd
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // afi_mem_clk_disable.afi_mem_clk_disable
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk), // .pll_avl_phy_clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl), // .dll_delayctrl
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol), // .parallelterminationcontrol
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_dm (mem_dm), // .mem_dm
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.csr_soft_reset_req (1'b0), // (terminated)
.io_intaddrdout (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intbadout (12'b000000000000), // (terminated)
.io_intcasndout (4'b0000), // (terminated)
.io_intckdout (4'b0000), // (terminated)
.io_intckedout (8'b00000000), // (terminated)
.io_intckndout (4'b0000), // (terminated)
.io_intcsndout (8'b00000000), // (terminated)
.io_intdmdout (20'b00000000000000000000), // (terminated)
.io_intdqdin (), // (terminated)
.io_intdqdout (180'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqoe (90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqsbdout (20'b00000000000000000000), // (terminated)
.io_intdqsboe (10'b0000000000), // (terminated)
.io_intdqsdout (20'b00000000000000000000), // (terminated)
.io_intdqslogicdqsena (10'b0000000000), // (terminated)
.io_intdqslogicfiforeset (5'b00000), // (terminated)
.io_intdqslogicincrdataen (10'b0000000000), // (terminated)
.io_intdqslogicincwrptr (10'b0000000000), // (terminated)
.io_intdqslogicoct (10'b0000000000), // (terminated)
.io_intdqslogicrdatavalid (), // (terminated)
.io_intdqslogicreadlatency (25'b0000000000000000000000000), // (terminated)
.io_intdqsoe (10'b0000000000), // (terminated)
.io_intodtdout (8'b00000000), // (terminated)
.io_intrasndout (4'b0000), // (terminated)
.io_intresetndout (4'b0000), // (terminated)
.io_intwendout (4'b0000), // (terminated)
.io_intafirlat (), // (terminated)
.io_intafiwlat () // (terminated)
);
altera_mem_if_hhp_qseq_synth_top #(
.MEM_IF_DM_WIDTH (4),
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_DQ_WIDTH (32)
) seq (
);
altera_mem_if_hard_memory_controller_top_cyclonev #(
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_CHIP_BITS (1),
.MEM_IF_CLK_PAIR_COUNT (1),
.CSR_ADDR_WIDTH (10),
.CSR_DATA_WIDTH (8),
.CSR_BE_WIDTH (1),
.AVL_ADDR_WIDTH (27),
.AVL_DATA_WIDTH (64),
.AVL_SIZE_WIDTH (3),
.AVL_DATA_WIDTH_PORT_0 (1),
.AVL_ADDR_WIDTH_PORT_0 (1),
.AVL_NUM_SYMBOLS_PORT_0 (1),
.LSB_WFIFO_PORT_0 (5),
.MSB_WFIFO_PORT_0 (5),
.LSB_RFIFO_PORT_0 (5),
.MSB_RFIFO_PORT_0 (5),
.AVL_DATA_WIDTH_PORT_1 (1),
.AVL_ADDR_WIDTH_PORT_1 (1),
.AVL_NUM_SYMBOLS_PORT_1 (1),
.LSB_WFIFO_PORT_1 (5),
.MSB_WFIFO_PORT_1 (5),
.LSB_RFIFO_PORT_1 (5),
.MSB_RFIFO_PORT_1 (5),
.AVL_DATA_WIDTH_PORT_2 (1),
.AVL_ADDR_WIDTH_PORT_2 (1),
.AVL_NUM_SYMBOLS_PORT_2 (1),
.LSB_WFIFO_PORT_2 (5),
.MSB_WFIFO_PORT_2 (5),
.LSB_RFIFO_PORT_2 (5),
.MSB_RFIFO_PORT_2 (5),
.AVL_DATA_WIDTH_PORT_3 (1),
.AVL_ADDR_WIDTH_PORT_3 (1),
.AVL_NUM_SYMBOLS_PORT_3 (1),
.LSB_WFIFO_PORT_3 (5),
.MSB_WFIFO_PORT_3 (5),
.LSB_RFIFO_PORT_3 (5),
.MSB_RFIFO_PORT_3 (5),
.AVL_DATA_WIDTH_PORT_4 (1),
.AVL_ADDR_WIDTH_PORT_4 (1),
.AVL_NUM_SYMBOLS_PORT_4 (1),
.LSB_WFIFO_PORT_4 (5),
.MSB_WFIFO_PORT_4 (5),
.LSB_RFIFO_PORT_4 (5),
.MSB_RFIFO_PORT_4 (5),
.AVL_DATA_WIDTH_PORT_5 (1),
.AVL_ADDR_WIDTH_PORT_5 (1),
.AVL_NUM_SYMBOLS_PORT_5 (1),
.LSB_WFIFO_PORT_5 (5),
.MSB_WFIFO_PORT_5 (5),
.LSB_RFIFO_PORT_5 (5),
.MSB_RFIFO_PORT_5 (5),
.ENUM_ATTR_COUNTER_ONE_RESET ("DISABLED"),
.ENUM_ATTR_COUNTER_ZERO_RESET ("DISABLED"),
.ENUM_ATTR_STATIC_CONFIG_VALID ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_0 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_1 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_2 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_3 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_4 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_5 ("DISABLED"),
.ENUM_CAL_REQ ("DISABLED"),
.ENUM_CFG_BURST_LENGTH ("BL_8"),
.ENUM_CFG_INTERFACE_WIDTH ("DWIDTH_32"),
.ENUM_CFG_SELF_RFSH_EXIT_CYCLES ("SELF_RFSH_EXIT_CYCLES_512"),
.ENUM_CFG_STARVE_LIMIT ("STARVE_LIMIT_10"),
.ENUM_CFG_TYPE ("DDR3"),
.ENUM_CLOCK_OFF_0 ("DISABLED"),
.ENUM_CLOCK_OFF_1 ("DISABLED"),
.ENUM_CLOCK_OFF_2 ("DISABLED"),
.ENUM_CLOCK_OFF_3 ("DISABLED"),
.ENUM_CLOCK_OFF_4 ("DISABLED"),
.ENUM_CLOCK_OFF_5 ("DISABLED"),
.ENUM_CLR_INTR ("NO_CLR_INTR"),
.ENUM_CMD_PORT_IN_USE_0 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_1 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_2 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_3 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_4 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_5 ("FALSE"),
.ENUM_CPORT0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT0_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT0_TYPE ("DISABLE"),
.ENUM_CPORT0_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT1_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_TYPE ("DISABLE"),
.ENUM_CPORT1_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT2_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_TYPE ("DISABLE"),
.ENUM_CPORT2_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT3_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_TYPE ("DISABLE"),
.ENUM_CPORT3_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT4_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_TYPE ("DISABLE"),
.ENUM_CPORT4_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT5_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_TYPE ("DISABLE"),
.ENUM_CPORT5_WFIFO_MAP ("FIFO_0"),
.ENUM_CTL_ADDR_ORDER ("CHIP_ROW_BANK_COL"),
.ENUM_CTL_ECC_ENABLED ("CTL_ECC_DISABLED"),
.ENUM_CTL_ECC_RMW_ENABLED ("CTL_ECC_RMW_DISABLED"),
.ENUM_CTL_REGDIMM_ENABLED ("REGDIMM_DISABLED"),
.ENUM_CTL_USR_REFRESH ("CTL_USR_REFRESH_DISABLED"),
.ENUM_CTRL_WIDTH ("DATA_WIDTH_64_BIT"),
.ENUM_DELAY_BONDING ("BONDING_LATENCY_0"),
.ENUM_DFX_BYPASS_ENABLE ("DFX_BYPASS_DISABLED"),
.ENUM_DISABLE_MERGING ("MERGING_ENABLED"),
.ENUM_ECC_DQ_WIDTH ("ECC_DQ_WIDTH_0"),
.ENUM_ENABLE_ATPG ("DISABLED"),
.ENUM_ENABLE_BONDING_0 ("DISABLED"),
.ENUM_ENABLE_BONDING_1 ("DISABLED"),
.ENUM_ENABLE_BONDING_2 ("DISABLED"),
.ENUM_ENABLE_BONDING_3 ("DISABLED"),
.ENUM_ENABLE_BONDING_4 ("DISABLED"),
.ENUM_ENABLE_BONDING_5 ("DISABLED"),
.ENUM_ENABLE_BONDING_WRAPBACK ("DISABLED"),
.ENUM_ENABLE_DQS_TRACKING ("ENABLED"),
.ENUM_ENABLE_ECC_CODE_OVERWRITES ("DISABLED"),
.ENUM_ENABLE_FAST_EXIT_PPD ("DISABLED"),
.ENUM_ENABLE_INTR ("DISABLED"),
.ENUM_ENABLE_NO_DM ("DISABLED"),
.ENUM_ENABLE_PIPELINEGLOBAL ("DISABLED"),
.ENUM_GANGED_ARF ("DISABLED"),
.ENUM_GEN_DBE ("GEN_DBE_DISABLED"),
.ENUM_GEN_SBE ("GEN_SBE_DISABLED"),
.ENUM_INC_SYNC ("FIFO_SET_2"),
.ENUM_LOCAL_IF_CS_WIDTH ("ADDR_WIDTH_0"),
.ENUM_MASK_CORR_DROPPED_INTR ("DISABLED"),
.ENUM_MASK_DBE_INTR ("DISABLED"),
.ENUM_MASK_SBE_INTR ("DISABLED"),
.ENUM_MEM_IF_AL ("AL_0"),
.ENUM_MEM_IF_BANKADDR_WIDTH ("ADDR_WIDTH_3"),
.ENUM_MEM_IF_BURSTLENGTH ("MEM_IF_BURSTLENGTH_8"),
.ENUM_MEM_IF_COLADDR_WIDTH ("ADDR_WIDTH_10"),
.ENUM_MEM_IF_CS_PER_RANK ("MEM_IF_CS_PER_RANK_1"),
.ENUM_MEM_IF_CS_WIDTH ("MEM_IF_CS_WIDTH_1"),
.ENUM_MEM_IF_DQ_PER_CHIP ("MEM_IF_DQ_PER_CHIP_8"),
.ENUM_MEM_IF_DQS_WIDTH ("DQS_WIDTH_4"),
.ENUM_MEM_IF_DWIDTH ("MEM_IF_DWIDTH_32"),
.ENUM_MEM_IF_MEMTYPE ("DDR3_SDRAM"),
.ENUM_MEM_IF_ROWADDR_WIDTH ("ADDR_WIDTH_15"),
.ENUM_MEM_IF_SPEEDBIN ("DDR3_1600_8_8_8"),
.ENUM_MEM_IF_TCCD ("TCCD_4"),
.ENUM_MEM_IF_TCL ("TCL_7"),
.ENUM_MEM_IF_TCWL ("TCWL_7"),
.ENUM_MEM_IF_TFAW ("TFAW_15"),
.ENUM_MEM_IF_TMRD ("TMRD_4"),
.ENUM_MEM_IF_TRAS ("TRAS_14"),
.ENUM_MEM_IF_TRC ("TRC_20"),
.ENUM_MEM_IF_TRCD ("TRCD_6"),
.ENUM_MEM_IF_TRP ("TRP_6"),
.ENUM_MEM_IF_TRRD ("TRRD_3"),
.ENUM_MEM_IF_TRTP ("TRTP_3"),
.ENUM_MEM_IF_TWR ("TWR_6"),
.ENUM_MEM_IF_TWTR ("TWTR_4"),
.ENUM_MMR_CFG_MEM_BL ("MP_BL_8"),
.ENUM_OUTPUT_REGD ("DISABLED"),
.ENUM_PDN_EXIT_CYCLES ("SLOW_EXIT"),
.ENUM_PORT0_WIDTH ("PORT_32_BIT"),
.ENUM_PORT1_WIDTH ("PORT_32_BIT"),
.ENUM_PORT2_WIDTH ("PORT_32_BIT"),
.ENUM_PORT3_WIDTH ("PORT_32_BIT"),
.ENUM_PORT4_WIDTH ("PORT_32_BIT"),
.ENUM_PORT5_WIDTH ("PORT_32_BIT"),
.ENUM_PRIORITY_0_0 ("WEIGHT_0"),
.ENUM_PRIORITY_0_1 ("WEIGHT_0"),
.ENUM_PRIORITY_0_2 ("WEIGHT_0"),
.ENUM_PRIORITY_0_3 ("WEIGHT_0"),
.ENUM_PRIORITY_0_4 ("WEIGHT_0"),
.ENUM_PRIORITY_0_5 ("WEIGHT_0"),
.ENUM_PRIORITY_1_0 ("WEIGHT_0"),
.ENUM_PRIORITY_1_1 ("WEIGHT_0"),
.ENUM_PRIORITY_1_2 ("WEIGHT_0"),
.ENUM_PRIORITY_1_3 ("WEIGHT_0"),
.ENUM_PRIORITY_1_4 ("WEIGHT_0"),
.ENUM_PRIORITY_1_5 ("WEIGHT_0"),
.ENUM_PRIORITY_2_0 ("WEIGHT_0"),
.ENUM_PRIORITY_2_1 ("WEIGHT_0"),
.ENUM_PRIORITY_2_2 ("WEIGHT_0"),
.ENUM_PRIORITY_2_3 ("WEIGHT_0"),
.ENUM_PRIORITY_2_4 ("WEIGHT_0"),
.ENUM_PRIORITY_2_5 ("WEIGHT_0"),
.ENUM_PRIORITY_3_0 ("WEIGHT_0"),
.ENUM_PRIORITY_3_1 ("WEIGHT_0"),
.ENUM_PRIORITY_3_2 ("WEIGHT_0"),
.ENUM_PRIORITY_3_3 ("WEIGHT_0"),
.ENUM_PRIORITY_3_4 ("WEIGHT_0"),
.ENUM_PRIORITY_3_5 ("WEIGHT_0"),
.ENUM_PRIORITY_4_0 ("WEIGHT_0"),
.ENUM_PRIORITY_4_1 ("WEIGHT_0"),
.ENUM_PRIORITY_4_2 ("WEIGHT_0"),
.ENUM_PRIORITY_4_3 ("WEIGHT_0"),
.ENUM_PRIORITY_4_4 ("WEIGHT_0"),
.ENUM_PRIORITY_4_5 ("WEIGHT_0"),
.ENUM_PRIORITY_5_0 ("WEIGHT_0"),
.ENUM_PRIORITY_5_1 ("WEIGHT_0"),
.ENUM_PRIORITY_5_2 ("WEIGHT_0"),
.ENUM_PRIORITY_5_3 ("WEIGHT_0"),
.ENUM_PRIORITY_5_4 ("WEIGHT_0"),
.ENUM_PRIORITY_5_5 ("WEIGHT_0"),
.ENUM_PRIORITY_6_0 ("WEIGHT_0"),
.ENUM_PRIORITY_6_1 ("WEIGHT_0"),
.ENUM_PRIORITY_6_2 ("WEIGHT_0"),
.ENUM_PRIORITY_6_3 ("WEIGHT_0"),
.ENUM_PRIORITY_6_4 ("WEIGHT_0"),
.ENUM_PRIORITY_6_5 ("WEIGHT_0"),
.ENUM_PRIORITY_7_0 ("WEIGHT_0"),
.ENUM_PRIORITY_7_1 ("WEIGHT_0"),
.ENUM_PRIORITY_7_2 ("WEIGHT_0"),
.ENUM_PRIORITY_7_3 ("WEIGHT_0"),
.ENUM_PRIORITY_7_4 ("WEIGHT_0"),
.ENUM_PRIORITY_7_5 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_RCFG_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_RD_DWIDTH_0 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_1 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_2 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_3 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_4 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_5 ("DWIDTH_0"),
.ENUM_RD_FIFO_IN_USE_0 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_1 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_2 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_3 ("FALSE"),
.ENUM_RD_PORT_INFO_0 ("USE_NO"),
.ENUM_RD_PORT_INFO_1 ("USE_NO"),
.ENUM_RD_PORT_INFO_2 ("USE_NO"),
.ENUM_RD_PORT_INFO_3 ("USE_NO"),
.ENUM_RD_PORT_INFO_4 ("USE_NO"),
.ENUM_RD_PORT_INFO_5 ("USE_NO"),
.ENUM_READ_ODT_CHIP ("ODT_DISABLED"),
.ENUM_REORDER_DATA ("DATA_REORDERING"),
.ENUM_RFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_SINGLE_READY_0 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_1 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_2 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_3 ("CONCATENATE_RDY"),
.ENUM_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_SYNC_MODE_0 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_1 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_2 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_3 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_4 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_5 ("ASYNCHRONOUS"),
.ENUM_TEST_MODE ("NORMAL_MODE"),
.ENUM_THLD_JAR1_0 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_1 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_2 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_3 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_4 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_5 ("THRESHOLD_32"),
.ENUM_THLD_JAR2_0 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_1 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_2 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_3 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_4 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_5 ("THRESHOLD_16"),
.ENUM_USE_ALMOST_EMPTY_0 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_1 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_2 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_3 ("EMPTY"),
.ENUM_USER_ECC_EN ("DISABLE"),
.ENUM_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_WFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WR_DWIDTH_0 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_1 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_2 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_3 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_4 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_5 ("DWIDTH_0"),
.ENUM_WR_FIFO_IN_USE_0 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_1 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_2 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_3 ("FALSE"),
.ENUM_WR_PORT_INFO_0 ("USE_NO"),
.ENUM_WR_PORT_INFO_1 ("USE_NO"),
.ENUM_WR_PORT_INFO_2 ("USE_NO"),
.ENUM_WR_PORT_INFO_3 ("USE_NO"),
.ENUM_WR_PORT_INFO_4 ("USE_NO"),
.ENUM_WR_PORT_INFO_5 ("USE_NO"),
.ENUM_WRITE_ODT_CHIP ("WRITE_CHIP0_ODT0_CHIP1"),
.INTG_MEM_AUTO_PD_CYCLES (0),
.INTG_CYC_TO_RLD_JARS_0 (1),
.INTG_CYC_TO_RLD_JARS_1 (1),
.INTG_CYC_TO_RLD_JARS_2 (1),
.INTG_CYC_TO_RLD_JARS_3 (1),
.INTG_CYC_TO_RLD_JARS_4 (1),
.INTG_CYC_TO_RLD_JARS_5 (1),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_RDWR (0),
.INTG_EXTRA_CTL_CLK_ARF_PERIOD (0),
.INTG_EXTRA_CTL_CLK_ARF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PCH_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PDN_PERIOD (0),
.INTG_EXTRA_CTL_CLK_PDN_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP (0),
.INTG_EXTRA_CTL_CLK_RD_TO_WR (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_BC (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (2),
.INTG_EXTRA_CTL_CLK_SRF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL (0),
.INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_WR_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_WR_TO_RD (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_BC (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP (3),
.INTG_EXTRA_CTL_CLK_WR_TO_WR (0),
.INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP (0),
.INTG_MEM_IF_TREFI (3120),
.INTG_MEM_IF_TRFC (120),
.INTG_RCFG_SUM_WT_PRIORITY_0 (0),
.INTG_RCFG_SUM_WT_PRIORITY_1 (0),
.INTG_RCFG_SUM_WT_PRIORITY_2 (0),
.INTG_RCFG_SUM_WT_PRIORITY_3 (0),
.INTG_RCFG_SUM_WT_PRIORITY_4 (0),
.INTG_RCFG_SUM_WT_PRIORITY_5 (0),
.INTG_RCFG_SUM_WT_PRIORITY_6 (0),
.INTG_RCFG_SUM_WT_PRIORITY_7 (0),
.INTG_SUM_WT_PRIORITY_0 (0),
.INTG_SUM_WT_PRIORITY_1 (0),
.INTG_SUM_WT_PRIORITY_2 (0),
.INTG_SUM_WT_PRIORITY_3 (0),
.INTG_SUM_WT_PRIORITY_4 (0),
.INTG_SUM_WT_PRIORITY_5 (0),
.INTG_SUM_WT_PRIORITY_6 (0),
.INTG_SUM_WT_PRIORITY_7 (0),
.INTG_POWER_SAVING_EXIT_CYCLES (5),
.INTG_MEM_CLK_ENTRY_CYCLES (10),
.ENUM_ENABLE_BURST_INTERRUPT ("DISABLED"),
.ENUM_ENABLE_BURST_TERMINATE ("DISABLED"),
.AFI_RATE_RATIO (1),
.AFI_ADDR_WIDTH (15),
.AFI_BANKADDR_WIDTH (3),
.AFI_CONTROL_WIDTH (1),
.AFI_CS_WIDTH (1),
.AFI_DM_WIDTH (8),
.AFI_DQ_WIDTH (64),
.AFI_ODT_WIDTH (1),
.AFI_WRITE_DQS_WIDTH (4),
.AFI_RLAT_WIDTH (6),
.AFI_WLAT_WIDTH (6),
.HARD_PHY (1)
) c0 (
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.local_init_done (), // status.local_init_done
.local_cal_success (), // .local_cal_success
.local_cal_fail (), // .local_cal_fail
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // .afi_mem_clk_disable
.afi_init_req (), // .afi_init_req
.afi_cal_req (), // .afi_cal_req
.afi_seq_busy (), // .afi_seq_busy
.afi_ctl_refresh_done (), // .afi_ctl_refresh_done
.afi_ctl_long_idle (), // .afi_ctl_long_idle
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.mp_cmd_clk_0 (1'b0), // (terminated)
.mp_cmd_reset_n_0 (1'b1), // (terminated)
.mp_cmd_clk_1 (1'b0), // (terminated)
.mp_cmd_reset_n_1 (1'b1), // (terminated)
.mp_cmd_clk_2 (1'b0), // (terminated)
.mp_cmd_reset_n_2 (1'b1), // (terminated)
.mp_cmd_clk_3 (1'b0), // (terminated)
.mp_cmd_reset_n_3 (1'b1), // (terminated)
.mp_cmd_clk_4 (1'b0), // (terminated)
.mp_cmd_reset_n_4 (1'b1), // (terminated)
.mp_cmd_clk_5 (1'b0), // (terminated)
.mp_cmd_reset_n_5 (1'b1), // (terminated)
.mp_rfifo_clk_0 (1'b0), // (terminated)
.mp_rfifo_reset_n_0 (1'b1), // (terminated)
.mp_wfifo_clk_0 (1'b0), // (terminated)
.mp_wfifo_reset_n_0 (1'b1), // (terminated)
.mp_rfifo_clk_1 (1'b0), // (terminated)
.mp_rfifo_reset_n_1 (1'b1), // (terminated)
.mp_wfifo_clk_1 (1'b0), // (terminated)
.mp_wfifo_reset_n_1 (1'b1), // (terminated)
.mp_rfifo_clk_2 (1'b0), // (terminated)
.mp_rfifo_reset_n_2 (1'b1), // (terminated)
.mp_wfifo_clk_2 (1'b0), // (terminated)
.mp_wfifo_reset_n_2 (1'b1), // (terminated)
.mp_rfifo_clk_3 (1'b0), // (terminated)
.mp_rfifo_reset_n_3 (1'b1), // (terminated)
.mp_wfifo_clk_3 (1'b0), // (terminated)
.mp_wfifo_reset_n_3 (1'b1), // (terminated)
.csr_clk (1'b0), // (terminated)
.csr_reset_n (1'b1), // (terminated)
.avl_ready_0 (), // (terminated)
.avl_burstbegin_0 (1'b0), // (terminated)
.avl_addr_0 (1'b0), // (terminated)
.avl_rdata_valid_0 (), // (terminated)
.avl_rdata_0 (), // (terminated)
.avl_wdata_0 (1'b0), // (terminated)
.avl_be_0 (1'b0), // (terminated)
.avl_read_req_0 (1'b0), // (terminated)
.avl_write_req_0 (1'b0), // (terminated)
.avl_size_0 (3'b000), // (terminated)
.avl_ready_1 (), // (terminated)
.avl_burstbegin_1 (1'b0), // (terminated)
.avl_addr_1 (1'b0), // (terminated)
.avl_rdata_valid_1 (), // (terminated)
.avl_rdata_1 (), // (terminated)
.avl_wdata_1 (1'b0), // (terminated)
.avl_be_1 (1'b0), // (terminated)
.avl_read_req_1 (1'b0), // (terminated)
.avl_write_req_1 (1'b0), // (terminated)
.avl_size_1 (3'b000), // (terminated)
.avl_ready_2 (), // (terminated)
.avl_burstbegin_2 (1'b0), // (terminated)
.avl_addr_2 (1'b0), // (terminated)
.avl_rdata_valid_2 (), // (terminated)
.avl_rdata_2 (), // (terminated)
.avl_wdata_2 (1'b0), // (terminated)
.avl_be_2 (1'b0), // (terminated)
.avl_read_req_2 (1'b0), // (terminated)
.avl_write_req_2 (1'b0), // (terminated)
.avl_size_2 (3'b000), // (terminated)
.avl_ready_3 (), // (terminated)
.avl_burstbegin_3 (1'b0), // (terminated)
.avl_addr_3 (1'b0), // (terminated)
.avl_rdata_valid_3 (), // (terminated)
.avl_rdata_3 (), // (terminated)
.avl_wdata_3 (1'b0), // (terminated)
.avl_be_3 (1'b0), // (terminated)
.avl_read_req_3 (1'b0), // (terminated)
.avl_write_req_3 (1'b0), // (terminated)
.avl_size_3 (3'b000), // (terminated)
.avl_ready_4 (), // (terminated)
.avl_burstbegin_4 (1'b0), // (terminated)
.avl_addr_4 (1'b0), // (terminated)
.avl_rdata_valid_4 (), // (terminated)
.avl_rdata_4 (), // (terminated)
.avl_wdata_4 (1'b0), // (terminated)
.avl_be_4 (1'b0), // (terminated)
.avl_read_req_4 (1'b0), // (terminated)
.avl_write_req_4 (1'b0), // (terminated)
.avl_size_4 (3'b000), // (terminated)
.avl_ready_5 (), // (terminated)
.avl_burstbegin_5 (1'b0), // (terminated)
.avl_addr_5 (1'b0), // (terminated)
.avl_rdata_valid_5 (), // (terminated)
.avl_rdata_5 (), // (terminated)
.avl_wdata_5 (1'b0), // (terminated)
.avl_be_5 (1'b0), // (terminated)
.avl_read_req_5 (1'b0), // (terminated)
.avl_write_req_5 (1'b0), // (terminated)
.avl_size_5 (3'b000), // (terminated)
.csr_write_req (1'b0), // (terminated)
.csr_read_req (1'b0), // (terminated)
.csr_waitrequest (), // (terminated)
.csr_addr (10'b0000000000), // (terminated)
.csr_be (1'b0), // (terminated)
.csr_wdata (8'b00000000), // (terminated)
.csr_rdata (), // (terminated)
.csr_rdata_valid (), // (terminated)
.local_multicast (1'b0), // (terminated)
.local_refresh_req (1'b0), // (terminated)
.local_refresh_chip (1'b0), // (terminated)
.local_refresh_ack (), // (terminated)
.local_self_rfsh_req (1'b0), // (terminated)
.local_self_rfsh_chip (1'b0), // (terminated)
.local_self_rfsh_ack (), // (terminated)
.local_deep_powerdn_req (1'b0), // (terminated)
.local_deep_powerdn_chip (1'b0), // (terminated)
.local_deep_powerdn_ack (), // (terminated)
.local_powerdn_ack (), // (terminated)
.local_priority (1'b0), // (terminated)
.bonding_in_1 (4'b0000), // (terminated)
.bonding_in_2 (6'b000000), // (terminated)
.bonding_in_3 (6'b000000), // (terminated)
.bonding_out_1 (), // (terminated)
.bonding_out_2 (), // (terminated)
.bonding_out_3 () // (terminated)
);
altera_mem_if_oct_cyclonev #(
.OCT_TERM_CONTROL_WIDTH (16)
) oct (
.oct_rzqin (oct_rzqin), // oct.rzqin
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol) // .parallelterminationcontrol
);
altera_mem_if_dll_cyclonev #(
.DLL_DELAY_CTRL_WIDTH (7),
.DLL_OFFSET_CTRL_WIDTH (6),
.DELAY_BUFFER_MODE ("HIGH"),
.DELAY_CHAIN_LENGTH (8),
.DLL_INPUT_FREQUENCY_PS_STR ("2500 ps")
) dll (
.clk (p0_dll_clk_clk), // clk.clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl) // .dll_delayctrl
);
endmodule
|
// file: pll.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____80.000______0.000______50.0______196.659____144.334
// CLK_OUT2____80.000______0.000______50.0______196.659____144.334
// CLK_OUT3____80.000______0.000______50.0______196.659____144.334
// CLK_OUT4____50.000______0.000______50.0______222.587____144.334
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary__________50.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "pll,clk_wiz_v3_6,{component_name=pll,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=4,clkin1_period=20.0,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
module pll
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
output CLK_OUT3,
output CLK_OUT4,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the MMCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire clkfbout;
wire clkfbout_buf;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2b_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
PLLE2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.COMPENSATION ("ZHOLD"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (16),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (10),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DIVIDE (10),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT2_DIVIDE (10),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT3_DIVIDE (16),
.CLKOUT3_PHASE (0.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKIN1_PERIOD (20.0),
.REF_JITTER1 (0.010))
plle2_adv_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKOUT0 (clkout0),
.CLKOUT1 (clkout1),
.CLKOUT2 (clkout2),
.CLKOUT3 (clkout3),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
// Input clock control
.CLKFBIN (clkfbout_buf),
.CLKIN1 (clkin1),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Other control and status signals
.LOCKED (LOCKED),
.PWRDWN (1'b0),
.RST (RESET));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf),
.I (clkfbout));
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkout0));
BUFG clkout2_buf
(.O (CLK_OUT2),
.I (clkout1));
BUFG clkout3_buf
(.O (CLK_OUT3),
.I (clkout2));
BUFG clkout4_buf
(.O (CLK_OUT4),
.I (clkout3));
endmodule
|
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 10G Ethernet MAC/PHY combination with TX and RX FIFOs
*/
module eth_mac_phy_10g_fifo #
(
parameter DATA_WIDTH = 64,
parameter HDR_WIDTH = (DATA_WIDTH/32),
parameter AXIS_DATA_WIDTH = DATA_WIDTH,
parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8),
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8),
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter TX_SERDES_PIPELINE = 0,
parameter RX_SERDES_PIPELINE = 0,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8,
parameter COUNT_125US = 125000/6.4,
parameter TX_FIFO_DEPTH = 4096,
parameter TX_FIFO_PIPELINE_OUTPUT = 2,
parameter TX_FRAME_FIFO = 1,
parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO,
parameter TX_DROP_WHEN_FULL = 0,
parameter RX_FIFO_DEPTH = 4096,
parameter RX_FIFO_PIPELINE_OUTPUT = 2,
parameter RX_FRAME_FIFO = 1,
parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO,
parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO,
parameter LOGIC_PTP_PERIOD_NS = 4'h6,
parameter LOGIC_PTP_PERIOD_FNS = 16'h6666,
parameter PTP_PERIOD_NS = 4'h6,
parameter PTP_PERIOD_FNS = 16'h6666,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter TX_PTP_TS_ENABLE = 0,
parameter RX_PTP_TS_ENABLE = 0,
parameter TX_PTP_TS_FIFO_DEPTH = 64,
parameter RX_PTP_TS_FIFO_DEPTH = 64,
parameter PTP_TS_WIDTH = 96,
parameter TX_PTP_TAG_ENABLE = 0,
parameter PTP_TAG_WIDTH = 16
)
(
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,
input wire tx_rst,
input wire logic_clk,
input wire logic_rst,
input wire ptp_sample_clk,
/*
* AXI input
*/
input wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire tx_axis_tuser,
/*
* Transmit timestamp tag input
*/
input wire [PTP_TAG_WIDTH-1:0] s_axis_tx_ptp_ts_tag,
input wire s_axis_tx_ptp_ts_valid,
output wire s_axis_tx_ptp_ts_ready,
/*
* Transmit timestamp output
*/
output wire [PTP_TS_WIDTH-1:0] m_axis_tx_ptp_ts_96,
output wire [PTP_TAG_WIDTH-1:0] m_axis_tx_ptp_ts_tag,
output wire m_axis_tx_ptp_ts_valid,
input wire m_axis_tx_ptp_ts_ready,
/*
* AXI output
*/
output wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata,
output wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep,
output wire rx_axis_tvalid,
input wire rx_axis_tready,
output wire rx_axis_tlast,
output wire rx_axis_tuser,
/*
* Receive timestamp output
*/
output wire [PTP_TS_WIDTH-1:0] m_axis_rx_ptp_ts_96,
output wire m_axis_rx_ptp_ts_valid,
input wire m_axis_rx_ptp_ts_ready,
/*
* SERDES interface
*/
output wire [DATA_WIDTH-1:0] serdes_tx_data,
output wire [HDR_WIDTH-1:0] serdes_tx_hdr,
input wire [DATA_WIDTH-1:0] serdes_rx_data,
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitslip,
/*
* Status
*/
output wire tx_error_underflow,
output wire tx_fifo_overflow,
output wire tx_fifo_bad_frame,
output wire tx_fifo_good_frame,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire rx_bad_block,
output wire rx_block_lock,
output wire rx_high_ber,
output wire rx_fifo_overflow,
output wire rx_fifo_bad_frame,
output wire rx_fifo_good_frame,
/*
* PTP clock
*/
input wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
/*
* Configuration
*/
input wire [7:0] ifg_delay,
input wire tx_prbs31_enable,
input wire rx_prbs31_enable
);
parameter KEEP_WIDTH = DATA_WIDTH/8;
localparam TX_USER_WIDTH = (TX_PTP_TS_ENABLE && TX_PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + 1;
localparam RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1;
wire [DATA_WIDTH-1:0] tx_fifo_axis_tdata;
wire [KEEP_WIDTH-1:0] tx_fifo_axis_tkeep;
wire tx_fifo_axis_tvalid;
wire tx_fifo_axis_tready;
wire tx_fifo_axis_tlast;
wire [TX_USER_WIDTH-1:0] tx_fifo_axis_tuser;
wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata_int;
wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep_int;
wire tx_axis_tvalid_int;
wire tx_axis_tready_int;
wire tx_axis_tlast_int;
wire [TX_USER_WIDTH-1:0] tx_axis_tuser_int;
wire [DATA_WIDTH-1:0] rx_fifo_axis_tdata;
wire [KEEP_WIDTH-1:0] rx_fifo_axis_tkeep;
wire rx_fifo_axis_tvalid;
wire rx_fifo_axis_tlast;
wire [RX_USER_WIDTH-1:0] rx_fifo_axis_tuser;
wire [RX_USER_WIDTH-1:0] rx_axis_tuser_int;
wire [PTP_TS_WIDTH-1:0] tx_ptp_ts_96;
wire [PTP_TS_WIDTH-1:0] rx_ptp_ts_96;
wire [PTP_TS_WIDTH-1:0] tx_axis_ptp_ts_96;
wire [PTP_TAG_WIDTH-1:0] tx_axis_ptp_ts_tag;
wire tx_axis_ptp_ts_valid;
wire [PTP_TS_WIDTH-1:0] rx_axis_ptp_ts_96;
wire rx_axis_ptp_ts_valid;
// synchronize MAC status signals into logic clock domain
wire tx_error_underflow_int;
reg [0:0] tx_sync_reg_1 = 1'b0;
reg [0:0] tx_sync_reg_2 = 1'b0;
reg [0:0] tx_sync_reg_3 = 1'b0;
reg [0:0] tx_sync_reg_4 = 1'b0;
assign tx_error_underflow = tx_sync_reg_3[0] ^ tx_sync_reg_4[0];
always @(posedge tx_clk or posedge tx_rst) begin
if (tx_rst) begin
tx_sync_reg_1 <= 1'b0;
end else begin
tx_sync_reg_1 <= tx_sync_reg_1 ^ {tx_error_underflow_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
tx_sync_reg_2 <= 1'b0;
tx_sync_reg_3 <= 1'b0;
tx_sync_reg_4 <= 1'b0;
end else begin
tx_sync_reg_2 <= tx_sync_reg_1;
tx_sync_reg_3 <= tx_sync_reg_2;
tx_sync_reg_4 <= tx_sync_reg_3;
end
end
wire rx_error_bad_frame_int;
wire rx_error_bad_fcs_int;
reg [4:0] rx_sync_reg_1 = 5'd0;
reg [4:0] rx_sync_reg_2 = 5'd0;
reg [4:0] rx_sync_reg_3 = 5'd0;
reg [4:0] rx_sync_reg_4 = 5'd0;
assign rx_error_bad_frame = rx_sync_reg_3[0] ^ rx_sync_reg_4[0];
assign rx_error_bad_fcs = rx_sync_reg_3[1] ^ rx_sync_reg_4[1];
assign rx_bad_block = rx_sync_reg_3[2] ^ rx_sync_reg_4[2];
assign rx_block_lock = rx_sync_reg_3[3] ^ rx_sync_reg_4[3];
assign rx_high_ber = rx_sync_reg_3[4] ^ rx_sync_reg_4[4];
always @(posedge rx_clk or posedge rx_rst) begin
if (rx_rst) begin
rx_sync_reg_1 <= 5'd0;
end else begin
rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_high_ber_int, rx_block_lock_int, rx_bad_block_int, rx_error_bad_fcs_int, rx_error_bad_frame_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
rx_sync_reg_2 <= 5'd0;
rx_sync_reg_3 <= 5'd0;
rx_sync_reg_4 <= 5'd0;
end else begin
rx_sync_reg_2 <= rx_sync_reg_1;
rx_sync_reg_3 <= rx_sync_reg_2;
rx_sync_reg_4 <= rx_sync_reg_3;
end
end
// PTP timestamping
generate
if (TX_PTP_TS_ENABLE) begin
ptp_clock_cdc #(
.TS_WIDTH(PTP_TS_WIDTH),
.NS_WIDTH(4),
.FNS_WIDTH(16),
.INPUT_PERIOD_NS(LOGIC_PTP_PERIOD_NS),
.INPUT_PERIOD_FNS(LOGIC_PTP_PERIOD_FNS),
.OUTPUT_PERIOD_NS(PTP_PERIOD_NS),
.OUTPUT_PERIOD_FNS(PTP_PERIOD_FNS),
.USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK)
)
tx_ptp_cdc (
.input_clk(logic_clk),
.input_rst(logic_rst),
.output_clk(tx_clk),
.output_rst(tx_rst),
.sample_clk(ptp_sample_clk),
.input_ts(ptp_ts_96),
.output_ts(tx_ptp_ts_96),
.output_ts_step(),
.output_pps()
);
if (TX_PTP_TAG_ENABLE) begin
ptp_tag_insert #(
.DATA_WIDTH(AXIS_DATA_WIDTH),
.KEEP_WIDTH(AXIS_KEEP_WIDTH),
.TAG_WIDTH(PTP_TAG_WIDTH),
.TAG_OFFSET(1),
.USER_WIDTH(TX_USER_WIDTH)
)
tx_ptp_tag_insert (
.clk(logic_clk),
.rst(logic_rst),
// AXI stream input
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tuser(tx_axis_tuser),
// AXI stream input
.m_axis_tdata(tx_axis_tdata_int),
.m_axis_tkeep(tx_axis_tkeep_int),
.m_axis_tvalid(tx_axis_tvalid_int),
.m_axis_tready(tx_axis_tready_int),
.m_axis_tlast(tx_axis_tlast_int),
.m_axis_tuser(tx_axis_tuser_int),
// Tag input
.s_axis_tag(s_axis_tx_ptp_ts_tag),
.s_axis_tag_valid(s_axis_tx_ptp_ts_valid),
.s_axis_tag_ready(s_axis_tx_ptp_ts_ready)
);
axis_async_fifo #(
.DEPTH(TX_PTP_TS_FIFO_DEPTH),
.DATA_WIDTH(PTP_TAG_WIDTH+PTP_TS_WIDTH),
.KEEP_ENABLE(0),
.LAST_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.FRAME_FIFO(0)
)
tx_ptp_ts_fifo (
.async_rst(logic_rst | tx_rst),
// AXI input
.s_clk(tx_clk),
.s_axis_tdata({tx_axis_ptp_ts_tag, tx_axis_ptp_ts_96}),
.s_axis_tkeep(0),
.s_axis_tvalid(tx_axis_ptp_ts_valid),
.s_axis_tready(),
.s_axis_tlast(0),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(0),
// AXI output
.m_clk(logic_clk),
.m_axis_tdata({m_axis_tx_ptp_ts_tag, m_axis_tx_ptp_ts_96}),
.m_axis_tkeep(),
.m_axis_tvalid(m_axis_tx_ptp_ts_valid),
.m_axis_tready(m_axis_tx_ptp_ts_ready),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
end else begin
assign tx_axis_tdata_int = tx_axis_tdata;
assign tx_axis_tkeep_int = tx_axis_tkeep;
assign tx_axis_tvalid_int = tx_axis_tvalid;
assign tx_axis_tready = tx_axis_tready_int;
assign tx_axis_tlast_int = tx_axis_tlast;
assign tx_axis_tuser_int = tx_axis_tuser;
axis_async_fifo #(
.DEPTH(TX_PTP_TS_FIFO_DEPTH),
.DATA_WIDTH(PTP_TS_WIDTH),
.KEEP_ENABLE(0),
.LAST_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.FRAME_FIFO(0)
)
tx_ptp_ts_fifo (
.async_rst(logic_rst | tx_rst),
// AXI input
.s_clk(tx_clk),
.s_axis_tdata(tx_axis_ptp_ts_96),
.s_axis_tkeep(0),
.s_axis_tvalid(tx_axis_ptp_ts_valid),
.s_axis_tready(),
.s_axis_tlast(0),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(0),
// AXI output
.m_clk(logic_clk),
.m_axis_tdata(m_axis_tx_ptp_ts_96),
.m_axis_tkeep(),
.m_axis_tvalid(m_axis_tx_ptp_ts_valid),
.m_axis_tready(m_axis_tx_ptp_ts_ready),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
assign s_axis_tx_ptp_ts_ready = 1'b0;
assign m_axis_tx_ptp_ts_tag = {PTP_TAG_WIDTH{1'b0}};
end
end else begin
assign s_axis_tx_ptp_ts_ready = 1'b0;
assign m_axis_tx_ptp_ts_96 = {PTP_TS_WIDTH{1'b0}};
assign m_axis_tx_ptp_ts_tag = {PTP_TAG_WIDTH{1'b0}};
assign m_axis_tx_ptp_ts_valid = 1'b0;
assign tx_ptp_ts_96 = {PTP_TS_WIDTH{1'b0}};
assign tx_axis_tdata_int = tx_axis_tdata;
assign tx_axis_tkeep_int = tx_axis_tkeep;
assign tx_axis_tvalid_int = tx_axis_tvalid;
assign tx_axis_tready = tx_axis_tready_int;
assign tx_axis_tlast_int = tx_axis_tlast;
assign tx_axis_tuser_int = tx_axis_tuser;
end
if (RX_PTP_TS_ENABLE) begin
ptp_clock_cdc #(
.TS_WIDTH(PTP_TS_WIDTH),
.NS_WIDTH(4),
.FNS_WIDTH(16),
.INPUT_PERIOD_NS(LOGIC_PTP_PERIOD_NS),
.INPUT_PERIOD_FNS(LOGIC_PTP_PERIOD_FNS),
.OUTPUT_PERIOD_NS(PTP_PERIOD_NS),
.OUTPUT_PERIOD_FNS(PTP_PERIOD_FNS),
.USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK)
)
rx_ptp_cdc (
.input_clk(logic_clk),
.input_rst(logic_rst),
.output_clk(rx_clk),
.output_rst(rx_rst),
.sample_clk(ptp_sample_clk),
.input_ts(ptp_ts_96),
.output_ts(rx_ptp_ts_96),
.output_ts_step(),
.output_pps()
);
axis_fifo #(
.DEPTH(RX_PTP_TS_FIFO_DEPTH),
.DATA_WIDTH(PTP_TS_WIDTH),
.KEEP_ENABLE(0),
.LAST_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.FRAME_FIFO(0)
)
rx_ptp_ts_fifo (
.clk(logic_clk),
.rst(logic_rst),
// AXI input
.s_axis_tdata(rx_axis_ptp_ts_96),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_axis_ptp_ts_valid),
.s_axis_tready(),
.s_axis_tlast(0),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(0),
// AXI output
.m_axis_tdata(m_axis_rx_ptp_ts_96),
.m_axis_tkeep(),
.m_axis_tvalid(m_axis_rx_ptp_ts_valid),
.m_axis_tready(m_axis_rx_ptp_ts_ready),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
ptp_ts_extract #(
.TS_WIDTH(PTP_TS_WIDTH),
.TS_OFFSET(1),
.USER_WIDTH(RX_USER_WIDTH)
)
rx_ptp_ts_extract (
.clk(logic_clk),
.rst(logic_rst),
// AXI stream input
.s_axis_tvalid(rx_axis_tvalid && rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser_int),
// Timestamp output
.m_axis_ts(rx_axis_ptp_ts_96),
.m_axis_ts_valid(rx_axis_ptp_ts_valid)
);
end else begin
assign m_axis_rx_ptp_ts_96 = {PTP_TS_WIDTH{1'b0}};
assign m_axis_rx_ptp_ts_valid = 1'b0;
assign rx_ptp_ts_96 = {PTP_TS_WIDTH{1'b0}};
end
assign rx_axis_tuser = rx_axis_tuser_int[0];
endgenerate
eth_mac_phy_10g #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.TX_PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
.TX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.TX_PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.RX_PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
.RX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_USER_WIDTH(TX_USER_WIDTH),
.RX_USER_WIDTH(RX_USER_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
eth_mac_phy_10g_inst (
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_axis_tdata(tx_fifo_axis_tdata),
.tx_axis_tkeep(tx_fifo_axis_tkeep),
.tx_axis_tvalid(tx_fifo_axis_tvalid),
.tx_axis_tready(tx_fifo_axis_tready),
.tx_axis_tlast(tx_fifo_axis_tlast),
.tx_axis_tuser(tx_fifo_axis_tuser),
.rx_axis_tdata(rx_fifo_axis_tdata),
.rx_axis_tkeep(rx_fifo_axis_tkeep),
.rx_axis_tvalid(rx_fifo_axis_tvalid),
.rx_axis_tlast(rx_fifo_axis_tlast),
.rx_axis_tuser(rx_fifo_axis_tuser),
.serdes_tx_data(serdes_tx_data),
.serdes_tx_hdr(serdes_tx_hdr),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_bitslip(serdes_rx_bitslip),
.tx_ptp_ts(tx_ptp_ts_96),
.rx_ptp_ts(rx_ptp_ts_96),
.tx_axis_ptp_ts(tx_axis_ptp_ts_96),
.tx_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.tx_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.tx_error_underflow(tx_error_underflow_int),
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.rx_bad_block(rx_bad_block_int),
.rx_block_lock(rx_block_lock_int),
.rx_high_ber(rx_high_ber_int),
.ifg_delay(ifg_delay),
.tx_prbs31_enable(tx_prbs31_enable),
.rx_prbs31_enable(rx_prbs31_enable)
);
axis_async_fifo_adapter #(
.DEPTH(TX_FIFO_DEPTH),
.S_DATA_WIDTH(AXIS_DATA_WIDTH),
.S_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.S_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.M_DATA_WIDTH(DATA_WIDTH),
.M_KEEP_ENABLE(1),
.M_KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
.USER_WIDTH(TX_USER_WIDTH),
.FRAME_FIFO(TX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(TX_DROP_WHEN_FULL)
)
tx_fifo (
// AXI input
.s_clk(logic_clk),
.s_rst(logic_rst),
.s_axis_tdata(tx_axis_tdata_int),
.s_axis_tkeep(tx_axis_tkeep_int),
.s_axis_tvalid(tx_axis_tvalid_int),
.s_axis_tready(tx_axis_tready_int),
.s_axis_tlast(tx_axis_tlast_int),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(tx_axis_tuser_int),
// AXI output
.m_clk(tx_clk),
.m_rst(tx_rst),
.m_axis_tdata(tx_fifo_axis_tdata),
.m_axis_tkeep(tx_fifo_axis_tkeep),
.m_axis_tvalid(tx_fifo_axis_tvalid),
.m_axis_tready(tx_fifo_axis_tready),
.m_axis_tlast(tx_fifo_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_axis_tuser),
// Status
.s_status_overflow(tx_fifo_overflow),
.s_status_bad_frame(tx_fifo_bad_frame),
.s_status_good_frame(tx_fifo_good_frame),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
axis_async_fifo_adapter #(
.DEPTH(RX_FIFO_DEPTH),
.S_DATA_WIDTH(DATA_WIDTH),
.S_KEEP_ENABLE(1),
.S_KEEP_WIDTH(KEEP_WIDTH),
.M_DATA_WIDTH(AXIS_DATA_WIDTH),
.M_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.M_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
.USER_WIDTH(RX_USER_WIDTH),
.FRAME_FIFO(RX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
)
rx_fifo (
// AXI input
.s_clk(rx_clk),
.s_rst(rx_rst),
.s_axis_tdata(rx_fifo_axis_tdata),
.s_axis_tkeep(rx_fifo_axis_tkeep),
.s_axis_tvalid(rx_fifo_axis_tvalid),
.s_axis_tready(),
.s_axis_tlast(rx_fifo_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_axis_tuser),
// AXI output
.m_clk(logic_clk),
.m_rst(logic_rst),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tready(rx_axis_tready),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(rx_axis_tuser_int),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(rx_fifo_overflow),
.m_status_bad_frame(rx_fifo_bad_frame),
.m_status_good_frame(rx_fifo_good_frame)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21AI_1_V
`define SKY130_FD_SC_LP__O21AI_1_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog wrapper for o21ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o21ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21ai_1 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21AI_1_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// Transmit HDMI, RGB to CrYCb conversion
// The multiplication coefficients are in 1.4.12 format
// The addition coefficients are in 1.12.12 format
// Cr = (+112.439/256)*R + (-094.154/256)*G + (-018.285/256)*B + 128;
// Y = (+065.738/256)*R + (+129.057/256)*G + (+025.064/256)*B + 16;
// Cb = (-037.945/256)*R + (-074.494/256)*G + (+112.439/256)*B + 128;
module cf_csc_RGB2CrYCb (
// R-G-B inputs
clk,
RGB_vs,
RGB_hs,
RGB_de,
RGB_data,
// Cr-Y-Cb outputs
CrYCb_vs,
CrYCb_hs,
CrYCb_de,
CrYCb_data);
// R-G-B inputs
input clk;
input RGB_vs;
input RGB_hs;
input RGB_de;
input [23:0] RGB_data;
// Cr-Y-Cb outputs
output CrYCb_vs;
output CrYCb_hs;
output CrYCb_de;
output [23:0] CrYCb_data;
reg CrYCb_vs = 'd0;
reg CrYCb_hs = 'd0;
reg CrYCb_de = 'd0;
reg [23:0] CrYCb_data = 'd0;
wire Cr_vs_s;
wire Cr_hs_s;
wire Cr_de_s;
wire [ 7:0] Cr_data_s;
wire Y_vs_s;
wire Y_hs_s;
wire Y_de_s;
wire [ 7:0] Y_data_s;
wire Cb_vs_s;
wire Cb_hs_s;
wire Cb_de_s;
wire [ 7:0] Cb_data_s;
// output registers (the control signals are gated together)
always @(posedge clk) begin
CrYCb_vs <= Cr_vs_s & Y_vs_s & Cb_vs_s;
CrYCb_hs <= Cr_hs_s & Y_hs_s & Cb_hs_s;
CrYCb_de <= Cr_de_s & Y_de_s & Cb_de_s;
CrYCb_data <= {Cr_data_s, Y_data_s, Cb_data_s};
end
// Cr (red-diff)
cf_csc_1 i_csc_Cr (
.clk (clk),
.vs (RGB_vs),
.hs (RGB_hs),
.de (RGB_de),
.data (RGB_data),
.C1 (17'h00707),
.C2 (17'h105e2),
.C3 (17'h10124),
.C4 (25'h0080000),
.csc_vs (Cr_vs_s),
.csc_hs (Cr_hs_s),
.csc_de (Cr_de_s),
.csc_data_1 (Cr_data_s));
// Y (luma)
cf_csc_1 i_csc_Y (
.clk (clk),
.vs (RGB_vs),
.hs (RGB_hs),
.de (RGB_de),
.data (RGB_data),
.C1 (17'h0041b),
.C2 (17'h00810),
.C3 (17'h00191),
.C4 (25'h0010000),
.csc_vs (Y_vs_s),
.csc_hs (Y_hs_s),
.csc_de (Y_de_s),
.csc_data_1 (Y_data_s));
// Cb (blue-diff)
cf_csc_1 i_csc_Cb (
.clk (clk),
.vs (RGB_vs),
.hs (RGB_hs),
.de (RGB_de),
.data (RGB_data),
.C1 (17'h1025f),
.C2 (17'h104a7),
.C3 (17'h00707),
.C4 (25'h0080000),
.csc_vs (Cb_vs_s),
.csc_hs (Cb_hs_s),
.csc_de (Cb_de_s),
.csc_data_1 (Cb_data_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MUX2_BLACKBOX_V
`define SKY130_FD_SC_LS__MUX2_BLACKBOX_V
/**
* mux2: 2-input multiplexer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__mux2 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__MUX2_BLACKBOX_V
|
//altpll_avalon avalon_use_separate_sysclk="NO" CBX_SINGLE_OUTPUT_FILE="ON" CBX_SUBMODULE_USED_PORTS="altpll:areset,clk,locked,inclk" address areset c0 clk locked phasedone read readdata reset write writedata bandwidth_type="AUTO" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=1 clk0_phase_shift="-3000" compensate_clock="CLK0" device_family="CYCLONEIVE" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5
//VERSION_BEGIN 15.1 cbx_altclkbuf 2015:10:14:18:59:15:SJ cbx_altiobuf_bidir 2015:10:14:18:59:15:SJ cbx_altiobuf_in 2015:10:14:18:59:15:SJ cbx_altiobuf_out 2015:10:14:18:59:15:SJ cbx_altpll 2015:10:14:18:59:15:SJ cbx_altpll_avalon 2015:10:14:18:59:15:SJ cbx_cycloneii 2015:10:14:18:59:15:SJ cbx_lpm_add_sub 2015:10:14:18:59:15:SJ cbx_lpm_compare 2015:10:14:18:59:15:SJ cbx_lpm_counter 2015:10:14:18:59:15:SJ cbx_lpm_decode 2015:10:14:18:59:15:SJ cbx_lpm_mux 2015:10:14:18:59:15:SJ cbx_lpm_shiftreg 2015:10:14:18:59:15:SJ cbx_mgl 2015:10:21:19:02:34:SJ cbx_nadder 2015:10:14:18:59:15:SJ cbx_stratix 2015:10:14:18:59:15:SJ cbx_stratixii 2015:10:14:18:59:15:SJ cbx_stratixiii 2015:10:14:18:59:15:SJ cbx_stratixv 2015:10:14:18:59:15:SJ cbx_util_mgl 2015:10:14:18:59:15:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//altera_std_synchronizer CBX_SINGLE_OUTPUT_FILE="ON" clk din dout reset_n
//VERSION_BEGIN 15.1 cbx_mgl 2015:10:21:19:02:34:SJ cbx_stratixii 2015:10:14:18:59:15:SJ cbx_util_mgl 2015:10:14:18:59:15:SJ VERSION_END
//dffpipe CBX_SINGLE_OUTPUT_FILE="ON" DELAY=3 WIDTH=1 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
//VERSION_BEGIN 15.1 cbx_mgl 2015:10:21:19:02:34:SJ cbx_stratixii 2015:10:14:18:59:15:SJ cbx_util_mgl 2015:10:14:18:59:15:SJ VERSION_END
//synthesis_resources = reg 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF"} *)
module qsys_sdram_clock_dffpipe_l2c
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */;
input clock;
input clrn;
input [0:0] d;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 clock;
tri1 clrn;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dffe4a;
reg [0:0] dffe5a;
reg [0:0] dffe6a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe4a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a <= {1{1'b1}};
else if (clrn == 1'b0) dffe4a <= 1'b0;
else if (ena == 1'b1) dffe4a <= (d & (~ sclr));
// synopsys translate_off
initial
dffe5a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe5a <= {1{1'b1}};
else if (clrn == 1'b0) dffe5a <= 1'b0;
else if (ena == 1'b1) dffe5a <= (dffe4a & (~ sclr));
// synopsys translate_off
initial
dffe6a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a <= {1{1'b1}};
else if (clrn == 1'b0) dffe6a <= 1'b0;
else if (ena == 1'b1) dffe6a <= (dffe5a & (~ sclr));
assign
ena = 1'b1,
prn = 1'b1,
q = dffe6a,
sclr = 1'b0;
endmodule //qsys_sdram_clock_dffpipe_l2c
//synthesis_resources = reg 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module qsys_sdram_clock_stdsync_sv6
(
clk,
din,
dout,
reset_n) /* synthesis synthesis_clearbox=1 */;
input clk;
input din;
output dout;
input reset_n;
wire [0:0] wire_dffpipe3_q;
qsys_sdram_clock_dffpipe_l2c dffpipe3
(
.clock(clk),
.clrn(reset_n),
.d(din),
.q(wire_dffpipe3_q));
assign
dout = wire_dffpipe3_q;
endmodule //qsys_sdram_clock_stdsync_sv6
//altpll bandwidth_type="AUTO" CBX_SINGLE_OUTPUT_FILE="ON" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=1 clk0_phase_shift="-3000" compensate_clock="CLK0" device_family="CYCLONEIVE" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 areset clk inclk locked
//VERSION_BEGIN 15.1 cbx_altclkbuf 2015:10:14:18:59:15:SJ cbx_altiobuf_bidir 2015:10:14:18:59:15:SJ cbx_altiobuf_in 2015:10:14:18:59:15:SJ cbx_altiobuf_out 2015:10:14:18:59:15:SJ cbx_altpll 2015:10:14:18:59:15:SJ cbx_cycloneii 2015:10:14:18:59:15:SJ cbx_lpm_add_sub 2015:10:14:18:59:15:SJ cbx_lpm_compare 2015:10:14:18:59:15:SJ cbx_lpm_counter 2015:10:14:18:59:15:SJ cbx_lpm_decode 2015:10:14:18:59:15:SJ cbx_lpm_mux 2015:10:14:18:59:15:SJ cbx_mgl 2015:10:21:19:02:34:SJ cbx_nadder 2015:10:14:18:59:15:SJ cbx_stratix 2015:10:14:18:59:15:SJ cbx_stratixii 2015:10:14:18:59:15:SJ cbx_stratixiii 2015:10:14:18:59:15:SJ cbx_stratixv 2015:10:14:18:59:15:SJ cbx_util_mgl 2015:10:14:18:59:15:SJ VERSION_END
//synthesis_resources = cycloneive_pll 1 reg 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C104;SUPPRESS_DA_RULE_INTERNAL=R101"} *)
module qsys_sdram_clock_altpll_l942
(
areset,
clk,
inclk,
locked) /* synthesis synthesis_clearbox=1 */;
input areset;
output [4:0] clk;
input [1:0] inclk;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg pll_lock_sync;
wire [4:0] wire_pll7_clk;
wire wire_pll7_fbout;
wire wire_pll7_locked;
// synopsys translate_off
initial
pll_lock_sync = 0;
// synopsys translate_on
always @ ( posedge wire_pll7_locked or posedge areset)
if (areset == 1'b1) pll_lock_sync <= 1'b0;
else pll_lock_sync <= 1'b1;
cycloneive_pll pll7
(
.activeclock(),
.areset(areset),
.clk(wire_pll7_clk),
.clkbad(),
.fbin(wire_pll7_fbout),
.fbout(wire_pll7_fbout),
.inclk(inclk),
.locked(wire_pll7_locked),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll7.bandwidth_type = "auto",
pll7.clk0_divide_by = 1,
pll7.clk0_duty_cycle = 50,
pll7.clk0_multiply_by = 1,
pll7.clk0_phase_shift = "-3000",
pll7.compensate_clock = "clk0",
pll7.inclk0_input_frequency = 20000,
pll7.operation_mode = "normal",
pll7.pll_type = "auto",
pll7.lpm_type = "cycloneive_pll";
assign
clk = {wire_pll7_clk[4:0]},
locked = (wire_pll7_locked & pll_lock_sync);
endmodule //qsys_sdram_clock_altpll_l942
//synthesis_resources = cycloneive_pll 1 reg 6
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module qsys_sdram_clock
(
address,
areset,
c0,
clk,
locked,
phasedone,
read,
readdata,
reset,
write,
writedata) /* synthesis synthesis_clearbox=1 */;
input [1:0] address;
input areset;
output c0;
input clk;
output locked;
output phasedone;
input read;
output [31:0] readdata;
input reset;
input write;
input [31:0] writedata;
wire wire_stdsync2_dout;
wire [4:0] wire_sd1_clk;
wire wire_sd1_locked;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=HIGH"} *)
reg pfdena_reg;
wire wire_pfdena_reg_ena;
reg prev_reset;
wire w_locked;
wire w_pfdena;
wire w_phasedone;
wire w_pll_areset_in;
wire w_reset;
wire w_select_control;
wire w_select_status;
qsys_sdram_clock_stdsync_sv6 stdsync2
(
.clk(clk),
.din(wire_sd1_locked),
.dout(wire_stdsync2_dout),
.reset_n((~ reset)));
qsys_sdram_clock_altpll_l942 sd1
(
.areset((w_pll_areset_in | areset)),
.clk(wire_sd1_clk),
.inclk({{1{1'b0}}, clk}),
.locked(wire_sd1_locked));
// synopsys translate_off
initial
pfdena_reg = {1{1'b1}};
// synopsys translate_on
always @ ( posedge clk or posedge reset)
if (reset == 1'b1) pfdena_reg <= {1{1'b1}};
else if (wire_pfdena_reg_ena == 1'b1) pfdena_reg <= writedata[1];
assign
wire_pfdena_reg_ena = (write & w_select_control);
// synopsys translate_off
initial
prev_reset = 0;
// synopsys translate_on
always @ ( posedge clk or posedge reset)
if (reset == 1'b1) prev_reset <= 1'b0;
else prev_reset <= w_reset;
assign
c0 = wire_sd1_clk[0],
locked = wire_sd1_locked,
phasedone = 1'b0,
readdata = {{30{1'b0}}, (read & ((w_select_control & w_pfdena) | (w_select_status & w_phasedone))), (read & ((w_select_control & w_pll_areset_in) | (w_select_status & w_locked)))},
w_locked = wire_stdsync2_dout,
w_pfdena = pfdena_reg,
w_phasedone = 1'b1,
w_pll_areset_in = prev_reset,
w_reset = ((write & w_select_control) & writedata[0]),
w_select_control = ((~ address[1]) & address[0]),
w_select_status = ((~ address[1]) & (~ address[0]));
endmodule //qsys_sdram_clock
//VALID FILE
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_ifu_errdp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_ifu_errdp
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "lsu.h"
`include "ifu.h"
module sparc_ifu_errdp(/*AUTOARG*/
// Outputs
so, ifu_lsu_ldxa_data_w2, erb_dtu_imask, erd_erc_tlbt_pe_s1,
erd_erc_tlbd_pe_s1, erd_erc_tagpe_s1, erd_erc_nirpe_s1,
erd_erc_fetpe_s1, erd_erc_tte_pgsz,
// Inputs
rclk, se, si, erb_reset, itlb_rd_tte_data, itlb_rd_tte_tag,
itlb_ifq_paddr_s, wsel_fdp_fetdata_s1, wsel_fdp_topdata_s1,
wsel_erb_asidata_s, ict_itlb_tags_f, icv_itlb_valid_f,
lsu_ifu_err_addr, spu_ifu_err_addr_w2, fdp_erb_pc_f,
exu_ifu_err_reg_m, exu_ifu_err_synd_m, ffu_ifu_err_reg_w2,
ffu_ifu_err_synd_w2, tlu_itlb_rw_index_g, erc_erd_pgsz_b0,
erc_erd_pgsz_b1, erc_erd_erren_asidata, erc_erd_errstat_asidata,
erc_erd_errinj_asidata, ifq_erb_asidata_i2, ifq_erb_wrtag_f,
ifq_erb_wrindex_f, erc_erd_asiway_s1_l, fcl_erb_itlbrd_data_s,
erc_erd_ld_imask, erc_erd_asisrc_sel_icd_s_l,
erc_erd_asisrc_sel_misc_s_l, erc_erd_asisrc_sel_err_s_l,
erc_erd_asisrc_sel_itlb_s_l, erc_erd_errasi_sel_en_l,
erc_erd_errasi_sel_stat_l, erc_erd_errasi_sel_inj_l,
erc_erd_errasi_sel_addr_l, erc_erd_miscasi_sel_ict_l,
erc_erd_miscasi_sel_imask_l, erc_erd_miscasi_sel_other_l,
erc_erd_asi_thr_l, erc_erd_eadr0_sel_irf_l,
erc_erd_eadr0_sel_itlb_l, erc_erd_eadr0_sel_frf_l,
erc_erd_eadr0_sel_lsu_l, erc_erd_eadr1_sel_pcd1_l,
erc_erd_eadr1_sel_l1pa_l, erc_erd_eadr1_sel_l2pa_l,
erc_erd_eadr1_sel_other_l, erc_erd_eadr2_sel_mx1_l,
erc_erd_eadr2_sel_wrt_l, erc_erd_eadr2_sel_mx0_l,
erc_erd_eadr2_sel_old_l
);
input rclk,
se,
si,
erb_reset;
input [42:0] itlb_rd_tte_data; // this is in s1
input [58:0] itlb_rd_tte_tag; // this is in s1
input [39:10] itlb_ifq_paddr_s;
input [33:0] wsel_fdp_fetdata_s1,
wsel_fdp_topdata_s1;
input [33:0] wsel_erb_asidata_s;
input [`IC_TAG_ALL_HI:0] ict_itlb_tags_f;
input [3:0] icv_itlb_valid_f;
input [47:4] lsu_ifu_err_addr;
input [39:4] spu_ifu_err_addr_w2;
input [47:0] fdp_erb_pc_f;
input [7:0] exu_ifu_err_reg_m;
input [7:0] exu_ifu_err_synd_m;
input [5:0] ffu_ifu_err_reg_w2;
input [13:0] ffu_ifu_err_synd_w2;
input [5:0] tlu_itlb_rw_index_g;
input erc_erd_pgsz_b0,
erc_erd_pgsz_b1;
input [1:0] erc_erd_erren_asidata;
input [22:0] erc_erd_errstat_asidata;
input [31:0] erc_erd_errinj_asidata;
input [47:0] ifq_erb_asidata_i2;
input [`IC_TAG_SZ-1:0] ifq_erb_wrtag_f;
input [`IC_IDX_HI:4] ifq_erb_wrindex_f;
// mux selects
input [3:0] erc_erd_asiway_s1_l;
input fcl_erb_itlbrd_data_s;
input erc_erd_ld_imask;
input erc_erd_asisrc_sel_icd_s_l,
erc_erd_asisrc_sel_misc_s_l,
erc_erd_asisrc_sel_err_s_l,
erc_erd_asisrc_sel_itlb_s_l;
input erc_erd_errasi_sel_en_l,
erc_erd_errasi_sel_stat_l,
erc_erd_errasi_sel_inj_l,
erc_erd_errasi_sel_addr_l;
input erc_erd_miscasi_sel_ict_l,
erc_erd_miscasi_sel_imask_l,
erc_erd_miscasi_sel_other_l;
input [3:0] erc_erd_asi_thr_l;
input [3:0] erc_erd_eadr0_sel_irf_l,
erc_erd_eadr0_sel_itlb_l,
erc_erd_eadr0_sel_frf_l,
erc_erd_eadr0_sel_lsu_l;
input [3:0] erc_erd_eadr1_sel_pcd1_l,
erc_erd_eadr1_sel_l1pa_l,
erc_erd_eadr1_sel_l2pa_l,
erc_erd_eadr1_sel_other_l;
input [3:0] erc_erd_eadr2_sel_mx1_l,
erc_erd_eadr2_sel_wrt_l,
erc_erd_eadr2_sel_mx0_l,
erc_erd_eadr2_sel_old_l;
output so;
output [63:0] ifu_lsu_ldxa_data_w2;
output [38:0] erb_dtu_imask;
// output [9:0] erb_ifq_paddr_s;
output [1:0] erd_erc_tlbt_pe_s1,
erd_erc_tlbd_pe_s1;
output [3:0] erd_erc_tagpe_s1;
output erd_erc_nirpe_s1,
erd_erc_fetpe_s1;
output [2:0] erd_erc_tte_pgsz;
//
// local signals
//
wire [47:4] lsu_err_addr;
wire [`IC_TAG_ALL_HI:0] ictags_s1;
wire [3:0] icv_data_s1;
wire [31:0] tag_asi_data;
wire [47:4] t0_eadr_mx0_out,
t1_eadr_mx0_out,
t2_eadr_mx0_out,
t3_eadr_mx0_out,
t0_eadr_mx1_out,
t1_eadr_mx1_out,
t2_eadr_mx1_out,
t3_eadr_mx1_out;
wire [47:4] t0_err_addr_nxt,
t0_err_addr,
t1_err_addr_nxt,
t1_err_addr,
t2_err_addr_nxt,
t2_err_addr,
t3_err_addr_nxt,
t3_err_addr;
wire [47:4] err_addr_asidata;
wire [63:0] formatted_tte_data,
formatted_tte_tag,
tlb_asi_data,
misc_asi_data,
err_asi_data,
ldxa_data_s,
ldxa_data_d;
wire [39:4] paddr_s1,
paddr_d1;
wire [39:4] ifet_addr_f;
wire [47:0] pc_s1;
wire [47:4] pc_d1;
wire [7:0] irfaddr_w,
irfsynd_w;
wire irfaddr_4_w;
wire [5:0] itlb_asi_index;
wire [38:0] imask_next;
wire clk;
//
// Code Begins Here
//
assign clk = rclk;
//-------------
// Tags
//-------------
dff_s #(`IC_TAG_ALL) tags_reg(.din (ict_itlb_tags_f),
.q (ictags_s1),
.clk (clk),
.se (se), .si(), .so());
dff_s #(4) vbits_reg(.din (icv_itlb_valid_f[3:0]),
.q (icv_data_s1),
.clk (clk), .se(se), .si(), .so());
// check parity
sparc_ifu_par32 tag_par0(.in ({3'b0, ictags_s1[`IC_TAG_SZ:0]}),
.out (erd_erc_tagpe_s1[0]));
sparc_ifu_par32 tag_par1(.in ({3'b0, ictags_s1[((2*`IC_TAG_SZ) + 1):(`IC_TAG_SZ+1)]}),
.out (erd_erc_tagpe_s1[1]));
sparc_ifu_par32 tag_par2(.in ({3'b0, ictags_s1[((3*`IC_TAG_SZ) + 2):(2*(`IC_TAG_SZ)+2)]}),
.out (erd_erc_tagpe_s1[2]));
sparc_ifu_par32 tag_par3(.in ({3'b0, ictags_s1[((4*`IC_TAG_SZ) + 3):(3*(`IC_TAG_SZ)+3)]}),
.out (erd_erc_tagpe_s1[3]));
dp_mux4ds #(32) asitag_mux(.dout (tag_asi_data[31:0]),
.in0 ({icv_data_s1[0], 1'b0, ictags_s1[28], 1'b0, ictags_s1[27:0]}),
.in1 ({icv_data_s1[1], 1'b0, ictags_s1[57], 1'b0, ictags_s1[56:29]}),
.in2 ({icv_data_s1[2], 1'b0, ictags_s1[86], 1'b0, ictags_s1[85:58]}),
.in3 ({icv_data_s1[3], 1'b0, ictags_s1[115], 1'b0, ictags_s1[114:87]}),
.sel0_l (erc_erd_asiway_s1_l[0]),
.sel1_l (erc_erd_asiway_s1_l[1]),
.sel2_l (erc_erd_asiway_s1_l[2]),
.sel3_l (erc_erd_asiway_s1_l[3]));
//------------------
// Data
//------------------
// parity check on instruction
// This may have to be done in the next stage (at least partially)
sparc_ifu_par34 nir_par(.in (wsel_fdp_topdata_s1[33:0]),
.out (erd_erc_nirpe_s1));
sparc_ifu_par34 inst_par(.in (wsel_fdp_fetdata_s1[33:0]),
.out (erd_erc_fetpe_s1));
//----------------------------------------------------------------------
// TLB read data
//----------------------------------------------------------------------
//`ifdef SPARC_HPV_EN
// don't include v(26) and u(24) bits in parity
sparc_ifu_par32 tt_tag_par0(.in ({itlb_rd_tte_tag[33:27],
itlb_rd_tte_tag[25],
itlb_rd_tte_tag[23:0]}),
.out (erd_erc_tlbt_pe_s1[0]));
//`else
// // don't include v(28) and u(26) bits in parity
// sparc_ifu_par32 tt_tag_par0(.in ({itlb_rd_tte_tag[33:29],
// itlb_rd_tte_tag[27],
// itlb_rd_tte_tag[25:0]}),
// .out (erd_erc_tlbt_pe_s1[0]));
//`endif // !`ifdef SPARC_HPV_EN
sparc_ifu_par32 tt_tag_par1(.in ({7'b0, itlb_rd_tte_tag[58:34]}),
.out (erd_erc_tlbt_pe_s1[1]));
sparc_ifu_par32 tt_data_par0(.in (itlb_rd_tte_data[31:0]),
.out (erd_erc_tlbd_pe_s1[0]));
sparc_ifu_par16 tt_data_par1(.in ({5'b0, itlb_rd_tte_data[42:32]}),
.out (erd_erc_tlbd_pe_s1[1]));
// assign erd_erc_tte_lock_s1 = itlb_rd_tte_data[`STLB_DATA_L];
//`ifdef SPARC_HPV_EN
assign erd_erc_tte_pgsz[2:0] = {itlb_rd_tte_data[`STLB_DATA_27_22_SEL],
itlb_rd_tte_data[`STLB_DATA_21_16_SEL],
itlb_rd_tte_data[`STLB_DATA_15_13_SEL]};
assign formatted_tte_tag[63:0] =
{
// `ifdef SUN4V_TAG_RD
// implement this!
itlb_rd_tte_tag[58:55],
// `else
// {4{itlb_rd_tte_tag[53]}}, // 4b
// `endif
itlb_rd_tte_tag[`STLB_TAG_PARITY], // Parity 1b
itlb_rd_tte_tag[`STLB_TAG_VA_27_22_V], // mxsel2 - b27:22 vld 1b
itlb_rd_tte_tag[`STLB_TAG_VA_21_16_V], // mxsel1 - b21:16 vld 1b
itlb_rd_tte_tag[`STLB_TAG_VA_15_13_V], // mxsel0 - b15:13 vld 1b
{8{itlb_rd_tte_tag[53]}}, // 8b
itlb_rd_tte_tag[`STLB_TAG_VA_47_28_HI:`STLB_TAG_VA_47_28_LO], // 20b
itlb_rd_tte_tag[`STLB_TAG_VA_27_22_HI:`STLB_TAG_VA_27_22_LO], // 6b
itlb_rd_tte_tag[`STLB_TAG_VA_21_16_HI:`STLB_TAG_VA_21_16_LO], // 6b
itlb_rd_tte_tag[`STLB_TAG_VA_15_13_HI:`STLB_TAG_VA_15_13_LO], // 3b
itlb_rd_tte_tag[`STLB_TAG_CTXT_12_0_HI:`STLB_TAG_CTXT_12_0_LO]// 13b
} ;
//`else
// assign erd_erc_tte_pgsz[2:0] = {itlb_rd_tte_data[`STLB_DATA_21_19_SEL],
// itlb_rd_tte_data[`STLB_DATA_18_16_SEL],
// itlb_rd_tte_data[`STLB_DATA_15_13_SEL]};
//
// assign formatted_tte_tag[63:0] =
// {
// {16{itlb_rd_tte_tag[54]}}, // 16b
// itlb_rd_tte_tag[`STLB_TAG_VA_47_22_HI:`STLB_TAG_VA_47_22_LO], // 26b
// itlb_rd_tte_tag[`STLB_TAG_VA_21_20_HI:`STLB_TAG_VA_21_20_LO], // 3b
// itlb_rd_tte_tag[`STLB_TAG_VA_19],
// itlb_rd_tte_tag[`STLB_TAG_VA_18_17_HI:`STLB_TAG_VA_18_17_LO], // 3b
// itlb_rd_tte_tag[`STLB_TAG_VA_16],
// itlb_rd_tte_tag[`STLB_TAG_VA_15_14_HI:`STLB_TAG_VA_15_14_LO], // 3b
// itlb_rd_tte_tag[`STLB_TAG_VA_13],
// itlb_rd_tte_tag[`STLB_TAG_CTXT_12_7_HI:`STLB_TAG_CTXT_12_7_LO],//13b
// itlb_rd_tte_tag[`STLB_TAG_CTXT_6_0_HI:`STLB_TAG_CTXT_6_0_LO]
// } ;
//`endif // !`ifdef SPARC_HPV_EN
//`ifdef SPARC_HPV_EN
assign formatted_tte_data[63:0] =
{
itlb_rd_tte_tag[`STLB_TAG_V], // V (1b)
erc_erd_pgsz_b1, // pg SZ msb 4m or 512k
erc_erd_pgsz_b0, // pg sz lsb 4m or 64k
itlb_rd_tte_data[`STLB_DATA_NFO], // NFO (1b)
itlb_rd_tte_data[`STLB_DATA_IE], // IE (1b)
10'b0, // soft2
itlb_rd_tte_data[`STLB_DATA_27_22_SEL], // pgsz b2
itlb_rd_tte_tag[`STLB_TAG_U],
itlb_rd_tte_data[`STLB_DATA_PARITY], // Parity (1b)
itlb_rd_tte_data[`STLB_DATA_27_22_SEL], // mxsel2_l (1b)
itlb_rd_tte_data[`STLB_DATA_21_16_SEL], // mxsel1_l (1b)
itlb_rd_tte_data[`STLB_DATA_15_13_SEL], // mxsel0_l (1b)
2'b0, // unused diag 2b
1'b0, // ?? PA (28b)
itlb_rd_tte_data[`STLB_DATA_PA_39_28_HI:`STLB_DATA_PA_39_28_LO],
itlb_rd_tte_data[`STLB_DATA_PA_27_22_HI:`STLB_DATA_PA_27_22_LO],
itlb_rd_tte_data[`STLB_DATA_PA_21_16_HI:`STLB_DATA_PA_21_16_LO],
itlb_rd_tte_data[`STLB_DATA_PA_15_13_HI:`STLB_DATA_PA_15_13_LO],
6'b0, // ?? 12-7 (6b)
itlb_rd_tte_data[`STLB_DATA_L], // L (1b)
itlb_rd_tte_data[`STLB_DATA_CP], // CP (1b)
itlb_rd_tte_data[`STLB_DATA_CV], // CV (1b)
itlb_rd_tte_data[`STLB_DATA_E], // E (1b)
itlb_rd_tte_data[`STLB_DATA_P], // P (1b)
itlb_rd_tte_data[`STLB_DATA_W], // W (1b)
1'b0
} ;
//`else // !`ifdef SPARC_HPV_EN
//
// assign formatted_tte_data[63:0] =
// {
// itlb_rd_tte_tag[`STLB_TAG_V], // V (1b)
// erc_erd_pgsz_b1, // pg SZ msb 4m or 512k
// erc_erd_pgsz_b0, // pg sz lsb 4m or 64k
// itlb_rd_tte_data[`STLB_DATA_NFO], // NFO (1b)
// itlb_rd_tte_data[`STLB_DATA_IE], // IE (1b)
// 9'b0, // soft2 58-42 (17b)
// 8'b0, // diag 8b
// itlb_rd_tte_tag[`STLB_TAG_U], // U (1b)
// 1'b0, // ?? PA (28b)
// itlb_rd_tte_data[`STLB_DATA_PA_39_22_HI:`STLB_DATA_PA_39_22_LO],
// itlb_rd_tte_data[`STLB_DATA_PA_21_19_HI:`STLB_DATA_PA_21_19_LO],
// itlb_rd_tte_data[`STLB_DATA_PA_18_16_HI:`STLB_DATA_PA_18_16_LO],
// itlb_rd_tte_data[`STLB_DATA_PA_15_13_HI:`STLB_DATA_PA_15_13_LO],
// 6'b0, // ?? 12-7 (6b)
// itlb_rd_tte_data[`STLB_DATA_L], // L (1b)
// itlb_rd_tte_data[`STLB_DATA_CP], // CP (1b)
// itlb_rd_tte_data[`STLB_DATA_CV], // CV (1b)
// itlb_rd_tte_data[`STLB_DATA_E], // E (1b)
// itlb_rd_tte_data[`STLB_DATA_P], // P (1b)
// itlb_rd_tte_data[`STLB_DATA_W], // W (1b)
// itlb_rd_tte_data[`STLB_DATA_G] // G (1b)
// } ;
//`endif // !`ifdef SPARC_HPV_EN
// mux in all asi values
dp_mux2es #(64) itlbrd_mux(.dout (tlb_asi_data[63:0]),
.in0 (formatted_tte_tag[63:0]),
.in1 (formatted_tte_data[63:0]),
.sel (fcl_erb_itlbrd_data_s));
dp_mux4ds #(64) err_mux(.dout (err_asi_data[63:0]),
.in0 ({62'b0, erc_erd_erren_asidata}),
.in1 ({32'b0, erc_erd_errstat_asidata, 9'b0}),
.in2 ({32'b0, erc_erd_errinj_asidata}),
.in3 ({16'b0, err_addr_asidata, 4'b0}),
.sel0_l (erc_erd_errasi_sel_en_l),
.sel1_l (erc_erd_errasi_sel_stat_l),
.sel2_l (erc_erd_errasi_sel_inj_l),
.sel3_l (erc_erd_errasi_sel_addr_l));
dp_mux3ds #(64) misc_asi_mux(.dout (misc_asi_data[63:0]),
.in0 ({29'b0,
tag_asi_data[31:28],
3'b0,
tag_asi_data[27:0]}),
.in1 ({25'b0, erb_dtu_imask}),
.in2 (64'b0),
.sel0_l (erc_erd_miscasi_sel_ict_l),
.sel1_l (erc_erd_miscasi_sel_imask_l),
.sel2_l (erc_erd_miscasi_sel_other_l));
// Final asi data
// May need to add a flop to this mux output before sending it to the LSU
dp_mux4ds #(64) final_asi_mux(.dout (ldxa_data_s),
.in0 (tlb_asi_data[63:0]),
.in1 (err_asi_data),
.in2 (misc_asi_data),
.in3 ({30'b0,
wsel_erb_asidata_s[0],
wsel_erb_asidata_s[33:1]}),
.sel0_l (erc_erd_asisrc_sel_itlb_s_l),
.sel1_l (erc_erd_asisrc_sel_err_s_l),
.sel2_l (erc_erd_asisrc_sel_misc_s_l),
.sel3_l (erc_erd_asisrc_sel_icd_s_l));
dff_s #(64) ldxa_reg(.din (ldxa_data_s),
.q (ldxa_data_d),
.clk (clk), .se(se), .si(), .so());
assign ifu_lsu_ldxa_data_w2 = ldxa_data_d;
//----------------------------------------
// Error Address
//----------------------------------------
assign ifet_addr_f = {ifq_erb_wrtag_f[`IC_TAG_SZ-1:0],
ifq_erb_wrindex_f[`IC_IDX_HI:4]};
// pc of latest access
dff_s #(48) pcs1_reg(.din (fdp_erb_pc_f[47:0]),
.q (pc_s1[47:0]),
.clk (clk), .se(se), .si(), .so());
// Physical address
assign paddr_s1[39:10] = itlb_ifq_paddr_s[39:10];
assign paddr_s1[9:4] = pc_s1[9:4];
dff_s #(36) padd_reg(.din (paddr_s1[39:4]),
.q (paddr_d1[39:4]),
.clk (clk), .se(se), .si(), .so());
// assign erb_ifq_paddr_s[9:0] = pc_s1[9:0];
// stage PC one more cycle
dff_s #(44) pcd1_reg(.din (pc_s1[47:4]),
.q (pc_d1[47:4]),
.clk (clk), .se(se), .si(), .so());
// IRF address
dff_s #(16) irf_reg(.din ({exu_ifu_err_reg_m[7:0],
exu_ifu_err_synd_m[7:0]}),
.q ({irfaddr_w[7:5],
irfaddr_4_w,
irfaddr_w[3:0],
irfsynd_w[7:0]}),
.clk (clk), .se(se), .si(), .so());
// fix for bug 5594
// nand2 + xnor
assign irfaddr_w[4] = irfaddr_4_w ^ (irfaddr_w[5] & irfaddr_w[3]);
// itlb asi address
dff_s #(6) itlbidx_reg(.din (tlu_itlb_rw_index_g),
.q (itlb_asi_index),
.clk (clk), .se(se), .si(), .so());
// lsu error address
dff_s #(44) lsadr_reg(.din (lsu_ifu_err_addr),
.q (lsu_err_addr),
.clk (clk), .se(se), .si(), .so());
// mux in the different error addresses
// thread 0
dp_mux4ds #(44) t0_eadr_mx0(.dout (t0_eadr_mx0_out),
.in0 ({24'b0, irfsynd_w[7:0], 4'b0, irfaddr_w[7:0]}),
.in1 ({38'b0, itlb_asi_index}),
.in2 ({17'b0, ffu_ifu_err_synd_w2[13:7],
1'b0, ffu_ifu_err_synd_w2[6:0],
6'b0, ffu_ifu_err_reg_w2[5:0]}),
.in3 (lsu_err_addr),
.sel0_l (erc_erd_eadr0_sel_irf_l[0]),
.sel1_l (erc_erd_eadr0_sel_itlb_l[0]),
.sel2_l (erc_erd_eadr0_sel_frf_l[0]),
.sel3_l (erc_erd_eadr0_sel_lsu_l[0]));
dp_mux4ds #(44) t0_eadr_mx1(.dout (t0_eadr_mx1_out),
.in0 (pc_d1[47:4]),
.in1 ({8'b0, paddr_d1[39:4]}),
.in2 ({8'b0, ifet_addr_f}),
.in3 ({8'b0, spu_ifu_err_addr_w2[39:4]}),
.sel0_l (erc_erd_eadr1_sel_pcd1_l[0]),
.sel1_l (erc_erd_eadr1_sel_l1pa_l[0]),
.sel2_l (erc_erd_eadr1_sel_l2pa_l[0]),
.sel3_l (erc_erd_eadr1_sel_other_l[0]));
dp_mux4ds #(44) t0_eadr_mx2(.dout (t0_err_addr_nxt),
.in0 (t0_eadr_mx0_out),
.in1 (t0_eadr_mx1_out),
.in2 (ifq_erb_asidata_i2[47:4]),
.in3 (t0_err_addr),
.sel0_l (erc_erd_eadr2_sel_mx0_l[0]),
.sel1_l (erc_erd_eadr2_sel_mx1_l[0]),
.sel2_l (erc_erd_eadr2_sel_wrt_l[0]),
.sel3_l (erc_erd_eadr2_sel_old_l[0]));
dff_s #(44) t0_eadr_reg(.din (t0_err_addr_nxt),
.q (t0_err_addr),
.clk (clk), .se(se), .si(), .so());
`ifdef FPGA_SYN_1THREAD
assign err_addr_asidata = t0_err_addr;
`else
// thread 1
dp_mux4ds #(44) t1_eadr_mx0(.dout (t1_eadr_mx0_out),
.in0 ({24'b0, irfsynd_w[7:0], 4'b0, irfaddr_w[7:0]}),
.in1 ({38'b0, itlb_asi_index}),
.in2 ({17'b0, ffu_ifu_err_synd_w2[13:7],
1'b0, ffu_ifu_err_synd_w2[6:0],
6'b0, ffu_ifu_err_reg_w2[5:0]}),
.in3 (lsu_err_addr),
.sel0_l (erc_erd_eadr0_sel_irf_l[1]),
.sel1_l (erc_erd_eadr0_sel_itlb_l[1]),
.sel2_l (erc_erd_eadr0_sel_frf_l[1]),
.sel3_l (erc_erd_eadr0_sel_lsu_l[1]));
dp_mux4ds #(44) t1_eadr_mx1(.dout (t1_eadr_mx1_out),
.in0 (pc_d1[47:4]),
.in1 ({8'b0, paddr_d1[39:4]}),
.in2 ({8'b0, ifet_addr_f}),
.in3 ({8'b0, spu_ifu_err_addr_w2[39:4]}),
// .in3 ({44'b0}),
.sel0_l (erc_erd_eadr1_sel_pcd1_l[1]),
.sel1_l (erc_erd_eadr1_sel_l1pa_l[1]),
.sel2_l (erc_erd_eadr1_sel_l2pa_l[1]),
.sel3_l (erc_erd_eadr1_sel_other_l[1]));
dp_mux4ds #(44) t1_eadr_mx2(.dout (t1_err_addr_nxt),
.in0 (t1_eadr_mx0_out),
.in1 (t1_eadr_mx1_out),
.in2 (ifq_erb_asidata_i2[47:4]),
.in3 (t1_err_addr),
.sel0_l (erc_erd_eadr2_sel_mx0_l[1]),
.sel1_l (erc_erd_eadr2_sel_mx1_l[1]),
.sel2_l (erc_erd_eadr2_sel_wrt_l[1]),
.sel3_l (erc_erd_eadr2_sel_old_l[1]));
dff_s #(44) t1_eadr_reg(.din (t1_err_addr_nxt),
.q (t1_err_addr),
.clk (clk), .se(se), .si(), .so());
// thread 2
dp_mux4ds #(44) t2_eadr_mx0(.dout (t2_eadr_mx0_out),
.in0 ({24'b0, irfsynd_w[7:0], 4'b0, irfaddr_w[7:0]}),
.in1 ({38'b0, itlb_asi_index}),
.in2 ({17'b0, ffu_ifu_err_synd_w2[13:7],
1'b0, ffu_ifu_err_synd_w2[6:0],
6'b0, ffu_ifu_err_reg_w2[5:0]}),
.in3 (lsu_err_addr),
.sel0_l (erc_erd_eadr0_sel_irf_l[2]),
.sel1_l (erc_erd_eadr0_sel_itlb_l[2]),
.sel2_l (erc_erd_eadr0_sel_frf_l[2]),
.sel3_l (erc_erd_eadr0_sel_lsu_l[2]));
dp_mux4ds #(44) t2_eadr_mx1(.dout (t2_eadr_mx1_out),
.in0 (pc_d1[47:4]),
.in1 ({8'b0, paddr_d1[39:4]}),
.in2 ({8'b0, ifet_addr_f}),
.in3 ({8'b0, spu_ifu_err_addr_w2[39:4]}),
// .in3 ({44'b0}),
.sel0_l (erc_erd_eadr1_sel_pcd1_l[2]),
.sel1_l (erc_erd_eadr1_sel_l1pa_l[2]),
.sel2_l (erc_erd_eadr1_sel_l2pa_l[2]),
.sel3_l (erc_erd_eadr1_sel_other_l[2]));
dp_mux4ds #(44) t2_eadr_mx2(.dout (t2_err_addr_nxt),
.in0 (t2_eadr_mx0_out),
.in1 (t2_eadr_mx1_out),
.in2 (ifq_erb_asidata_i2[47:4]),
.in3 (t2_err_addr),
.sel0_l (erc_erd_eadr2_sel_mx0_l[2]),
.sel1_l (erc_erd_eadr2_sel_mx1_l[2]),
.sel2_l (erc_erd_eadr2_sel_wrt_l[2]),
.sel3_l (erc_erd_eadr2_sel_old_l[2]));
dff_s #(44) t2_eadr_reg(.din (t2_err_addr_nxt),
.q (t2_err_addr),
.clk (clk), .se(se), .si(), .so());
// thread 3
dp_mux4ds #(44) t3_eadr_mx0(.dout (t3_eadr_mx0_out),
.in0 ({24'b0, irfsynd_w[7:0], 4'b0, irfaddr_w[7:0]}),
.in1 ({38'b0, itlb_asi_index}),
.in2 ({17'b0, ffu_ifu_err_synd_w2[13:7],
1'b0, ffu_ifu_err_synd_w2[6:0],
6'b0, ffu_ifu_err_reg_w2[5:0]}),
.in3 (lsu_err_addr),
.sel0_l (erc_erd_eadr0_sel_irf_l[3]),
.sel1_l (erc_erd_eadr0_sel_itlb_l[3]),
.sel2_l (erc_erd_eadr0_sel_frf_l[3]),
.sel3_l (erc_erd_eadr0_sel_lsu_l[3]));
dp_mux4ds #(44) t3_eadr_mx1(.dout (t3_eadr_mx1_out),
.in0 (pc_d1[47:4]),
.in1 ({8'b0, paddr_d1[39:4]}),
.in2 ({8'b0, ifet_addr_f}),
.in3 ({8'b0, spu_ifu_err_addr_w2[39:4]}),
// .in3 ({44'b0}),
.sel0_l (erc_erd_eadr1_sel_pcd1_l[3]),
.sel1_l (erc_erd_eadr1_sel_l1pa_l[3]),
.sel2_l (erc_erd_eadr1_sel_l2pa_l[3]),
.sel3_l (erc_erd_eadr1_sel_other_l[3]));
dp_mux4ds #(44) t3_eadr_mx2(.dout (t3_err_addr_nxt),
.in0 (t3_eadr_mx0_out),
.in1 (t3_eadr_mx1_out),
.in2 (ifq_erb_asidata_i2[47:4]),
.in3 (t3_err_addr),
.sel0_l (erc_erd_eadr2_sel_mx0_l[3]),
.sel1_l (erc_erd_eadr2_sel_mx1_l[3]),
.sel2_l (erc_erd_eadr2_sel_wrt_l[3]),
.sel3_l (erc_erd_eadr2_sel_old_l[3]));
dff_s #(44) t3_eadr_reg(.din (t3_err_addr_nxt),
.q (t3_err_addr),
.clk (clk), .se(se), .si(), .so());
// asi read
dp_mux4ds #(44) asi_eadr_mx(.dout (err_addr_asidata),
.in0 (t0_err_addr),
.in1 (t1_err_addr),
.in2 (t2_err_addr),
.in3 (t3_err_addr),
.sel0_l (erc_erd_asi_thr_l[0]),
.sel1_l (erc_erd_asi_thr_l[1]),
.sel2_l (erc_erd_asi_thr_l[2]),
.sel3_l (erc_erd_asi_thr_l[3]));
`endif
// Instruction Mask
dp_mux2es #(39) imask_en_mux(.dout (imask_next),
.in0 (erb_dtu_imask),
.in1 (ifq_erb_asidata_i2[38:0]),
.sel (erc_erd_ld_imask));
// need to reset top 7 bits only
dffr_s #(39) imask_reg(.din (imask_next),
.q (erb_dtu_imask),
.rst (erb_reset),
.clk (clk), .se(se), .si(), .so());
sink #(4) s0(.in (pc_s1[3:0]));
endmodule // sparc_ifu_erb
|
//-----------------------------------------------------------------------------
// system_stub.v
//-----------------------------------------------------------------------------
module system_stub
(
processing_system7_0_MIO,
processing_system7_0_PS_SRSTB_pin,
processing_system7_0_PS_CLK_pin,
processing_system7_0_PS_PORB_pin,
processing_system7_0_DDR_Clk,
processing_system7_0_DDR_Clk_n,
processing_system7_0_DDR_CKE,
processing_system7_0_DDR_CS_n,
processing_system7_0_DDR_RAS_n,
processing_system7_0_DDR_CAS_n,
processing_system7_0_DDR_WEB_pin,
processing_system7_0_DDR_BankAddr,
processing_system7_0_DDR_Addr,
processing_system7_0_DDR_ODT,
processing_system7_0_DDR_DRSTB,
processing_system7_0_DDR_DQ,
processing_system7_0_DDR_DM,
processing_system7_0_DDR_DQS,
processing_system7_0_DDR_DQS_n,
processing_system7_0_DDR_VRN,
processing_system7_0_DDR_VRP,
processing_system7_0_M_AXI_GP1_ARESETN_pin,
processing_system7_0_S_AXI_HP1_ARESETN_pin,
processing_system7_0_FCLK_CLK3_pin,
processing_system7_0_FCLK_CLK0_pin,
processing_system7_0_M_AXI_GP1_ARVALID_pin,
processing_system7_0_M_AXI_GP1_AWVALID_pin,
processing_system7_0_M_AXI_GP1_BREADY_pin,
processing_system7_0_M_AXI_GP1_RREADY_pin,
processing_system7_0_M_AXI_GP1_WLAST_pin,
processing_system7_0_M_AXI_GP1_WVALID_pin,
processing_system7_0_M_AXI_GP1_ARID_pin,
processing_system7_0_M_AXI_GP1_AWID_pin,
processing_system7_0_M_AXI_GP1_WID_pin,
processing_system7_0_M_AXI_GP1_ARBURST_pin,
processing_system7_0_M_AXI_GP1_ARLOCK_pin,
processing_system7_0_M_AXI_GP1_ARSIZE_pin,
processing_system7_0_M_AXI_GP1_AWBURST_pin,
processing_system7_0_M_AXI_GP1_AWLOCK_pin,
processing_system7_0_M_AXI_GP1_AWSIZE_pin,
processing_system7_0_M_AXI_GP1_ARPROT_pin,
processing_system7_0_M_AXI_GP1_AWPROT_pin,
processing_system7_0_M_AXI_GP1_ARADDR_pin,
processing_system7_0_M_AXI_GP1_AWADDR_pin,
processing_system7_0_M_AXI_GP1_WDATA_pin,
processing_system7_0_M_AXI_GP1_ARCACHE_pin,
processing_system7_0_M_AXI_GP1_ARLEN_pin,
processing_system7_0_M_AXI_GP1_ARQOS_pin,
processing_system7_0_M_AXI_GP1_AWCACHE_pin,
processing_system7_0_M_AXI_GP1_AWLEN_pin,
processing_system7_0_M_AXI_GP1_AWQOS_pin,
processing_system7_0_M_AXI_GP1_WSTRB_pin,
processing_system7_0_M_AXI_GP1_ACLK_pin,
processing_system7_0_M_AXI_GP1_ARREADY_pin,
processing_system7_0_M_AXI_GP1_AWREADY_pin,
processing_system7_0_M_AXI_GP1_BVALID_pin,
processing_system7_0_M_AXI_GP1_RLAST_pin,
processing_system7_0_M_AXI_GP1_RVALID_pin,
processing_system7_0_M_AXI_GP1_WREADY_pin,
processing_system7_0_M_AXI_GP1_BID_pin,
processing_system7_0_M_AXI_GP1_RID_pin,
processing_system7_0_M_AXI_GP1_BRESP_pin,
processing_system7_0_M_AXI_GP1_RRESP_pin,
processing_system7_0_M_AXI_GP1_RDATA_pin,
processing_system7_0_S_AXI_HP1_ARREADY_pin,
processing_system7_0_S_AXI_HP1_AWREADY_pin,
processing_system7_0_S_AXI_HP1_BVALID_pin,
processing_system7_0_S_AXI_HP1_RLAST_pin,
processing_system7_0_S_AXI_HP1_RVALID_pin,
processing_system7_0_S_AXI_HP1_WREADY_pin,
processing_system7_0_S_AXI_HP1_BRESP_pin,
processing_system7_0_S_AXI_HP1_RRESP_pin,
processing_system7_0_S_AXI_HP1_BID_pin,
processing_system7_0_S_AXI_HP1_RID_pin,
processing_system7_0_S_AXI_HP1_RDATA_pin,
processing_system7_0_S_AXI_HP1_ACLK_pin,
processing_system7_0_S_AXI_HP1_ARVALID_pin,
processing_system7_0_S_AXI_HP1_AWVALID_pin,
processing_system7_0_S_AXI_HP1_BREADY_pin,
processing_system7_0_S_AXI_HP1_RREADY_pin,
processing_system7_0_S_AXI_HP1_WLAST_pin,
processing_system7_0_S_AXI_HP1_WVALID_pin,
processing_system7_0_S_AXI_HP1_ARBURST_pin,
processing_system7_0_S_AXI_HP1_ARLOCK_pin,
processing_system7_0_S_AXI_HP1_ARSIZE_pin,
processing_system7_0_S_AXI_HP1_AWBURST_pin,
processing_system7_0_S_AXI_HP1_AWLOCK_pin,
processing_system7_0_S_AXI_HP1_AWSIZE_pin,
processing_system7_0_S_AXI_HP1_ARPROT_pin,
processing_system7_0_S_AXI_HP1_AWPROT_pin,
processing_system7_0_S_AXI_HP1_ARADDR_pin,
processing_system7_0_S_AXI_HP1_AWADDR_pin,
processing_system7_0_S_AXI_HP1_ARCACHE_pin,
processing_system7_0_S_AXI_HP1_ARLEN_pin,
processing_system7_0_S_AXI_HP1_ARQOS_pin,
processing_system7_0_S_AXI_HP1_AWCACHE_pin,
processing_system7_0_S_AXI_HP1_AWLEN_pin,
processing_system7_0_S_AXI_HP1_AWQOS_pin,
processing_system7_0_S_AXI_HP1_ARID_pin,
processing_system7_0_S_AXI_HP1_AWID_pin,
processing_system7_0_S_AXI_HP1_WID_pin,
processing_system7_0_S_AXI_HP1_WDATA_pin,
processing_system7_0_S_AXI_HP1_WSTRB_pin,
processing_system7_0_I2C0_SDA_pin,
processing_system7_0_I2C0_SCL_pin,
processing_system7_0_GPIO_I_pin,
processing_system7_0_GPIO_O_pin,
processing_system7_0_GPIO_T_pin
);
inout [53:0] processing_system7_0_MIO;
input processing_system7_0_PS_SRSTB_pin;
input processing_system7_0_PS_CLK_pin;
input processing_system7_0_PS_PORB_pin;
inout processing_system7_0_DDR_Clk;
inout processing_system7_0_DDR_Clk_n;
inout processing_system7_0_DDR_CKE;
inout processing_system7_0_DDR_CS_n;
inout processing_system7_0_DDR_RAS_n;
inout processing_system7_0_DDR_CAS_n;
output processing_system7_0_DDR_WEB_pin;
inout [2:0] processing_system7_0_DDR_BankAddr;
inout [14:0] processing_system7_0_DDR_Addr;
inout processing_system7_0_DDR_ODT;
inout processing_system7_0_DDR_DRSTB;
inout [31:0] processing_system7_0_DDR_DQ;
inout [3:0] processing_system7_0_DDR_DM;
inout [3:0] processing_system7_0_DDR_DQS;
inout [3:0] processing_system7_0_DDR_DQS_n;
inout processing_system7_0_DDR_VRN;
inout processing_system7_0_DDR_VRP;
output processing_system7_0_M_AXI_GP1_ARESETN_pin;
output processing_system7_0_S_AXI_HP1_ARESETN_pin;
output processing_system7_0_FCLK_CLK3_pin;
output processing_system7_0_FCLK_CLK0_pin;
output processing_system7_0_M_AXI_GP1_ARVALID_pin;
output processing_system7_0_M_AXI_GP1_AWVALID_pin;
output processing_system7_0_M_AXI_GP1_BREADY_pin;
output processing_system7_0_M_AXI_GP1_RREADY_pin;
output processing_system7_0_M_AXI_GP1_WLAST_pin;
output processing_system7_0_M_AXI_GP1_WVALID_pin;
output [11:0] processing_system7_0_M_AXI_GP1_ARID_pin;
output [11:0] processing_system7_0_M_AXI_GP1_AWID_pin;
output [11:0] processing_system7_0_M_AXI_GP1_WID_pin;
output [1:0] processing_system7_0_M_AXI_GP1_ARBURST_pin;
output [1:0] processing_system7_0_M_AXI_GP1_ARLOCK_pin;
output [2:0] processing_system7_0_M_AXI_GP1_ARSIZE_pin;
output [1:0] processing_system7_0_M_AXI_GP1_AWBURST_pin;
output [1:0] processing_system7_0_M_AXI_GP1_AWLOCK_pin;
output [2:0] processing_system7_0_M_AXI_GP1_AWSIZE_pin;
output [2:0] processing_system7_0_M_AXI_GP1_ARPROT_pin;
output [2:0] processing_system7_0_M_AXI_GP1_AWPROT_pin;
output [31:0] processing_system7_0_M_AXI_GP1_ARADDR_pin;
output [31:0] processing_system7_0_M_AXI_GP1_AWADDR_pin;
output [31:0] processing_system7_0_M_AXI_GP1_WDATA_pin;
output [3:0] processing_system7_0_M_AXI_GP1_ARCACHE_pin;
output [3:0] processing_system7_0_M_AXI_GP1_ARLEN_pin;
output [3:0] processing_system7_0_M_AXI_GP1_ARQOS_pin;
output [3:0] processing_system7_0_M_AXI_GP1_AWCACHE_pin;
output [3:0] processing_system7_0_M_AXI_GP1_AWLEN_pin;
output [3:0] processing_system7_0_M_AXI_GP1_AWQOS_pin;
output [3:0] processing_system7_0_M_AXI_GP1_WSTRB_pin;
input processing_system7_0_M_AXI_GP1_ACLK_pin;
input processing_system7_0_M_AXI_GP1_ARREADY_pin;
input processing_system7_0_M_AXI_GP1_AWREADY_pin;
input processing_system7_0_M_AXI_GP1_BVALID_pin;
input processing_system7_0_M_AXI_GP1_RLAST_pin;
input processing_system7_0_M_AXI_GP1_RVALID_pin;
input processing_system7_0_M_AXI_GP1_WREADY_pin;
input [11:0] processing_system7_0_M_AXI_GP1_BID_pin;
input [11:0] processing_system7_0_M_AXI_GP1_RID_pin;
input [1:0] processing_system7_0_M_AXI_GP1_BRESP_pin;
input [1:0] processing_system7_0_M_AXI_GP1_RRESP_pin;
input [31:0] processing_system7_0_M_AXI_GP1_RDATA_pin;
output processing_system7_0_S_AXI_HP1_ARREADY_pin;
output processing_system7_0_S_AXI_HP1_AWREADY_pin;
output processing_system7_0_S_AXI_HP1_BVALID_pin;
output processing_system7_0_S_AXI_HP1_RLAST_pin;
output processing_system7_0_S_AXI_HP1_RVALID_pin;
output processing_system7_0_S_AXI_HP1_WREADY_pin;
output [1:0] processing_system7_0_S_AXI_HP1_BRESP_pin;
output [1:0] processing_system7_0_S_AXI_HP1_RRESP_pin;
output [5:0] processing_system7_0_S_AXI_HP1_BID_pin;
output [5:0] processing_system7_0_S_AXI_HP1_RID_pin;
output [63:0] processing_system7_0_S_AXI_HP1_RDATA_pin;
input processing_system7_0_S_AXI_HP1_ACLK_pin;
input processing_system7_0_S_AXI_HP1_ARVALID_pin;
input processing_system7_0_S_AXI_HP1_AWVALID_pin;
input processing_system7_0_S_AXI_HP1_BREADY_pin;
input processing_system7_0_S_AXI_HP1_RREADY_pin;
input processing_system7_0_S_AXI_HP1_WLAST_pin;
input processing_system7_0_S_AXI_HP1_WVALID_pin;
input [1:0] processing_system7_0_S_AXI_HP1_ARBURST_pin;
input [1:0] processing_system7_0_S_AXI_HP1_ARLOCK_pin;
input [2:0] processing_system7_0_S_AXI_HP1_ARSIZE_pin;
input [1:0] processing_system7_0_S_AXI_HP1_AWBURST_pin;
input [1:0] processing_system7_0_S_AXI_HP1_AWLOCK_pin;
input [2:0] processing_system7_0_S_AXI_HP1_AWSIZE_pin;
input [2:0] processing_system7_0_S_AXI_HP1_ARPROT_pin;
input [2:0] processing_system7_0_S_AXI_HP1_AWPROT_pin;
input [31:0] processing_system7_0_S_AXI_HP1_ARADDR_pin;
input [31:0] processing_system7_0_S_AXI_HP1_AWADDR_pin;
input [3:0] processing_system7_0_S_AXI_HP1_ARCACHE_pin;
input [3:0] processing_system7_0_S_AXI_HP1_ARLEN_pin;
input [3:0] processing_system7_0_S_AXI_HP1_ARQOS_pin;
input [3:0] processing_system7_0_S_AXI_HP1_AWCACHE_pin;
input [3:0] processing_system7_0_S_AXI_HP1_AWLEN_pin;
input [3:0] processing_system7_0_S_AXI_HP1_AWQOS_pin;
input [5:0] processing_system7_0_S_AXI_HP1_ARID_pin;
input [5:0] processing_system7_0_S_AXI_HP1_AWID_pin;
input [5:0] processing_system7_0_S_AXI_HP1_WID_pin;
input [63:0] processing_system7_0_S_AXI_HP1_WDATA_pin;
input [7:0] processing_system7_0_S_AXI_HP1_WSTRB_pin;
inout processing_system7_0_I2C0_SDA_pin;
inout processing_system7_0_I2C0_SCL_pin;
input [47:0] processing_system7_0_GPIO_I_pin;
output [47:0] processing_system7_0_GPIO_O_pin;
output [47:0] processing_system7_0_GPIO_T_pin;
(* BOX_TYPE = "user_black_box" *)
system
system_i (
.processing_system7_0_MIO ( processing_system7_0_MIO ),
.processing_system7_0_PS_SRSTB_pin ( processing_system7_0_PS_SRSTB_pin ),
.processing_system7_0_PS_CLK_pin ( processing_system7_0_PS_CLK_pin ),
.processing_system7_0_PS_PORB_pin ( processing_system7_0_PS_PORB_pin ),
.processing_system7_0_DDR_Clk ( processing_system7_0_DDR_Clk ),
.processing_system7_0_DDR_Clk_n ( processing_system7_0_DDR_Clk_n ),
.processing_system7_0_DDR_CKE ( processing_system7_0_DDR_CKE ),
.processing_system7_0_DDR_CS_n ( processing_system7_0_DDR_CS_n ),
.processing_system7_0_DDR_RAS_n ( processing_system7_0_DDR_RAS_n ),
.processing_system7_0_DDR_CAS_n ( processing_system7_0_DDR_CAS_n ),
.processing_system7_0_DDR_WEB_pin ( processing_system7_0_DDR_WEB_pin ),
.processing_system7_0_DDR_BankAddr ( processing_system7_0_DDR_BankAddr ),
.processing_system7_0_DDR_Addr ( processing_system7_0_DDR_Addr ),
.processing_system7_0_DDR_ODT ( processing_system7_0_DDR_ODT ),
.processing_system7_0_DDR_DRSTB ( processing_system7_0_DDR_DRSTB ),
.processing_system7_0_DDR_DQ ( processing_system7_0_DDR_DQ ),
.processing_system7_0_DDR_DM ( processing_system7_0_DDR_DM ),
.processing_system7_0_DDR_DQS ( processing_system7_0_DDR_DQS ),
.processing_system7_0_DDR_DQS_n ( processing_system7_0_DDR_DQS_n ),
.processing_system7_0_DDR_VRN ( processing_system7_0_DDR_VRN ),
.processing_system7_0_DDR_VRP ( processing_system7_0_DDR_VRP ),
.processing_system7_0_M_AXI_GP1_ARESETN_pin ( processing_system7_0_M_AXI_GP1_ARESETN_pin ),
.processing_system7_0_S_AXI_HP1_ARESETN_pin ( processing_system7_0_S_AXI_HP1_ARESETN_pin ),
.processing_system7_0_FCLK_CLK3_pin ( processing_system7_0_FCLK_CLK3_pin ),
.processing_system7_0_FCLK_CLK0_pin ( processing_system7_0_FCLK_CLK0_pin ),
.processing_system7_0_M_AXI_GP1_ARVALID_pin ( processing_system7_0_M_AXI_GP1_ARVALID_pin ),
.processing_system7_0_M_AXI_GP1_AWVALID_pin ( processing_system7_0_M_AXI_GP1_AWVALID_pin ),
.processing_system7_0_M_AXI_GP1_BREADY_pin ( processing_system7_0_M_AXI_GP1_BREADY_pin ),
.processing_system7_0_M_AXI_GP1_RREADY_pin ( processing_system7_0_M_AXI_GP1_RREADY_pin ),
.processing_system7_0_M_AXI_GP1_WLAST_pin ( processing_system7_0_M_AXI_GP1_WLAST_pin ),
.processing_system7_0_M_AXI_GP1_WVALID_pin ( processing_system7_0_M_AXI_GP1_WVALID_pin ),
.processing_system7_0_M_AXI_GP1_ARID_pin ( processing_system7_0_M_AXI_GP1_ARID_pin ),
.processing_system7_0_M_AXI_GP1_AWID_pin ( processing_system7_0_M_AXI_GP1_AWID_pin ),
.processing_system7_0_M_AXI_GP1_WID_pin ( processing_system7_0_M_AXI_GP1_WID_pin ),
.processing_system7_0_M_AXI_GP1_ARBURST_pin ( processing_system7_0_M_AXI_GP1_ARBURST_pin ),
.processing_system7_0_M_AXI_GP1_ARLOCK_pin ( processing_system7_0_M_AXI_GP1_ARLOCK_pin ),
.processing_system7_0_M_AXI_GP1_ARSIZE_pin ( processing_system7_0_M_AXI_GP1_ARSIZE_pin ),
.processing_system7_0_M_AXI_GP1_AWBURST_pin ( processing_system7_0_M_AXI_GP1_AWBURST_pin ),
.processing_system7_0_M_AXI_GP1_AWLOCK_pin ( processing_system7_0_M_AXI_GP1_AWLOCK_pin ),
.processing_system7_0_M_AXI_GP1_AWSIZE_pin ( processing_system7_0_M_AXI_GP1_AWSIZE_pin ),
.processing_system7_0_M_AXI_GP1_ARPROT_pin ( processing_system7_0_M_AXI_GP1_ARPROT_pin ),
.processing_system7_0_M_AXI_GP1_AWPROT_pin ( processing_system7_0_M_AXI_GP1_AWPROT_pin ),
.processing_system7_0_M_AXI_GP1_ARADDR_pin ( processing_system7_0_M_AXI_GP1_ARADDR_pin ),
.processing_system7_0_M_AXI_GP1_AWADDR_pin ( processing_system7_0_M_AXI_GP1_AWADDR_pin ),
.processing_system7_0_M_AXI_GP1_WDATA_pin ( processing_system7_0_M_AXI_GP1_WDATA_pin ),
.processing_system7_0_M_AXI_GP1_ARCACHE_pin ( processing_system7_0_M_AXI_GP1_ARCACHE_pin ),
.processing_system7_0_M_AXI_GP1_ARLEN_pin ( processing_system7_0_M_AXI_GP1_ARLEN_pin ),
.processing_system7_0_M_AXI_GP1_ARQOS_pin ( processing_system7_0_M_AXI_GP1_ARQOS_pin ),
.processing_system7_0_M_AXI_GP1_AWCACHE_pin ( processing_system7_0_M_AXI_GP1_AWCACHE_pin ),
.processing_system7_0_M_AXI_GP1_AWLEN_pin ( processing_system7_0_M_AXI_GP1_AWLEN_pin ),
.processing_system7_0_M_AXI_GP1_AWQOS_pin ( processing_system7_0_M_AXI_GP1_AWQOS_pin ),
.processing_system7_0_M_AXI_GP1_WSTRB_pin ( processing_system7_0_M_AXI_GP1_WSTRB_pin ),
.processing_system7_0_M_AXI_GP1_ACLK_pin ( processing_system7_0_M_AXI_GP1_ACLK_pin ),
.processing_system7_0_M_AXI_GP1_ARREADY_pin ( processing_system7_0_M_AXI_GP1_ARREADY_pin ),
.processing_system7_0_M_AXI_GP1_AWREADY_pin ( processing_system7_0_M_AXI_GP1_AWREADY_pin ),
.processing_system7_0_M_AXI_GP1_BVALID_pin ( processing_system7_0_M_AXI_GP1_BVALID_pin ),
.processing_system7_0_M_AXI_GP1_RLAST_pin ( processing_system7_0_M_AXI_GP1_RLAST_pin ),
.processing_system7_0_M_AXI_GP1_RVALID_pin ( processing_system7_0_M_AXI_GP1_RVALID_pin ),
.processing_system7_0_M_AXI_GP1_WREADY_pin ( processing_system7_0_M_AXI_GP1_WREADY_pin ),
.processing_system7_0_M_AXI_GP1_BID_pin ( processing_system7_0_M_AXI_GP1_BID_pin ),
.processing_system7_0_M_AXI_GP1_RID_pin ( processing_system7_0_M_AXI_GP1_RID_pin ),
.processing_system7_0_M_AXI_GP1_BRESP_pin ( processing_system7_0_M_AXI_GP1_BRESP_pin ),
.processing_system7_0_M_AXI_GP1_RRESP_pin ( processing_system7_0_M_AXI_GP1_RRESP_pin ),
.processing_system7_0_M_AXI_GP1_RDATA_pin ( processing_system7_0_M_AXI_GP1_RDATA_pin ),
.processing_system7_0_S_AXI_HP1_ARREADY_pin ( processing_system7_0_S_AXI_HP1_ARREADY_pin ),
.processing_system7_0_S_AXI_HP1_AWREADY_pin ( processing_system7_0_S_AXI_HP1_AWREADY_pin ),
.processing_system7_0_S_AXI_HP1_BVALID_pin ( processing_system7_0_S_AXI_HP1_BVALID_pin ),
.processing_system7_0_S_AXI_HP1_RLAST_pin ( processing_system7_0_S_AXI_HP1_RLAST_pin ),
.processing_system7_0_S_AXI_HP1_RVALID_pin ( processing_system7_0_S_AXI_HP1_RVALID_pin ),
.processing_system7_0_S_AXI_HP1_WREADY_pin ( processing_system7_0_S_AXI_HP1_WREADY_pin ),
.processing_system7_0_S_AXI_HP1_BRESP_pin ( processing_system7_0_S_AXI_HP1_BRESP_pin ),
.processing_system7_0_S_AXI_HP1_RRESP_pin ( processing_system7_0_S_AXI_HP1_RRESP_pin ),
.processing_system7_0_S_AXI_HP1_BID_pin ( processing_system7_0_S_AXI_HP1_BID_pin ),
.processing_system7_0_S_AXI_HP1_RID_pin ( processing_system7_0_S_AXI_HP1_RID_pin ),
.processing_system7_0_S_AXI_HP1_RDATA_pin ( processing_system7_0_S_AXI_HP1_RDATA_pin ),
.processing_system7_0_S_AXI_HP1_ACLK_pin ( processing_system7_0_S_AXI_HP1_ACLK_pin ),
.processing_system7_0_S_AXI_HP1_ARVALID_pin ( processing_system7_0_S_AXI_HP1_ARVALID_pin ),
.processing_system7_0_S_AXI_HP1_AWVALID_pin ( processing_system7_0_S_AXI_HP1_AWVALID_pin ),
.processing_system7_0_S_AXI_HP1_BREADY_pin ( processing_system7_0_S_AXI_HP1_BREADY_pin ),
.processing_system7_0_S_AXI_HP1_RREADY_pin ( processing_system7_0_S_AXI_HP1_RREADY_pin ),
.processing_system7_0_S_AXI_HP1_WLAST_pin ( processing_system7_0_S_AXI_HP1_WLAST_pin ),
.processing_system7_0_S_AXI_HP1_WVALID_pin ( processing_system7_0_S_AXI_HP1_WVALID_pin ),
.processing_system7_0_S_AXI_HP1_ARBURST_pin ( processing_system7_0_S_AXI_HP1_ARBURST_pin ),
.processing_system7_0_S_AXI_HP1_ARLOCK_pin ( processing_system7_0_S_AXI_HP1_ARLOCK_pin ),
.processing_system7_0_S_AXI_HP1_ARSIZE_pin ( processing_system7_0_S_AXI_HP1_ARSIZE_pin ),
.processing_system7_0_S_AXI_HP1_AWBURST_pin ( processing_system7_0_S_AXI_HP1_AWBURST_pin ),
.processing_system7_0_S_AXI_HP1_AWLOCK_pin ( processing_system7_0_S_AXI_HP1_AWLOCK_pin ),
.processing_system7_0_S_AXI_HP1_AWSIZE_pin ( processing_system7_0_S_AXI_HP1_AWSIZE_pin ),
.processing_system7_0_S_AXI_HP1_ARPROT_pin ( processing_system7_0_S_AXI_HP1_ARPROT_pin ),
.processing_system7_0_S_AXI_HP1_AWPROT_pin ( processing_system7_0_S_AXI_HP1_AWPROT_pin ),
.processing_system7_0_S_AXI_HP1_ARADDR_pin ( processing_system7_0_S_AXI_HP1_ARADDR_pin ),
.processing_system7_0_S_AXI_HP1_AWADDR_pin ( processing_system7_0_S_AXI_HP1_AWADDR_pin ),
.processing_system7_0_S_AXI_HP1_ARCACHE_pin ( processing_system7_0_S_AXI_HP1_ARCACHE_pin ),
.processing_system7_0_S_AXI_HP1_ARLEN_pin ( processing_system7_0_S_AXI_HP1_ARLEN_pin ),
.processing_system7_0_S_AXI_HP1_ARQOS_pin ( processing_system7_0_S_AXI_HP1_ARQOS_pin ),
.processing_system7_0_S_AXI_HP1_AWCACHE_pin ( processing_system7_0_S_AXI_HP1_AWCACHE_pin ),
.processing_system7_0_S_AXI_HP1_AWLEN_pin ( processing_system7_0_S_AXI_HP1_AWLEN_pin ),
.processing_system7_0_S_AXI_HP1_AWQOS_pin ( processing_system7_0_S_AXI_HP1_AWQOS_pin ),
.processing_system7_0_S_AXI_HP1_ARID_pin ( processing_system7_0_S_AXI_HP1_ARID_pin ),
.processing_system7_0_S_AXI_HP1_AWID_pin ( processing_system7_0_S_AXI_HP1_AWID_pin ),
.processing_system7_0_S_AXI_HP1_WID_pin ( processing_system7_0_S_AXI_HP1_WID_pin ),
.processing_system7_0_S_AXI_HP1_WDATA_pin ( processing_system7_0_S_AXI_HP1_WDATA_pin ),
.processing_system7_0_S_AXI_HP1_WSTRB_pin ( processing_system7_0_S_AXI_HP1_WSTRB_pin ),
.processing_system7_0_I2C0_SDA_pin ( processing_system7_0_I2C0_SDA_pin ),
.processing_system7_0_I2C0_SCL_pin ( processing_system7_0_I2C0_SCL_pin ),
.processing_system7_0_GPIO_I_pin ( processing_system7_0_GPIO_I_pin ),
.processing_system7_0_GPIO_O_pin ( processing_system7_0_GPIO_O_pin ),
.processing_system7_0_GPIO_T_pin ( processing_system7_0_GPIO_T_pin )
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
// $Id: unused_reg.v 1914 2007-07-11 23:58:33Z grg $
//
// Module: unused_reg.v
// Project: NetFPGA
// Description: Unused register block
//
///////////////////////////////////////////////////////////////////////////////
module unused_reg
#(
parameter REG_ADDR_WIDTH = 5
)
(
// Register interface signals
input reg_req,
output reg_ack,
input reg_rd_wr_L,
input [REG_ADDR_WIDTH - 1:0] reg_addr,
output [`CPCI_NF2_DATA_WIDTH - 1:0] reg_rd_data,
input [`CPCI_NF2_DATA_WIDTH - 1:0] reg_wr_data,
//
input clk,
input reset
);
reg reg_req_d1;
assign reg_rd_data = 'h dead_beef;
// Only generate an ack on a new request
assign reg_ack = reg_req && !reg_req_d1;
always @(posedge clk)
begin
reg_req_d1 <= reg_req;
end
endmodule // unused_reg
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module switch_pio (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 15: 0] out_port;
output [ 15: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input [ 15: 0] in_port;
input reset_n;
input write_n;
input [ 15: 0] writedata;
wire clk_en;
wire [ 15: 0] data_in;
reg [ 15: 0] data_out;
wire [ 15: 0] out_port;
wire [ 15: 0] read_mux_out;
reg [ 15: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {16 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[15 : 0];
end
assign out_port = data_out;
assign data_in = in_port;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg check;
initial check = 1'b0;
Genit g (.clk(clk), .check(check));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d %x %x\n",$time, cyc, check, out);
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
check <= 1'b0;
end
else if (cyc==1) begin
check <= 1'b1;
end
else if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
//`define WAVES
`ifdef WAVES
initial begin
$dumpfile("obj_dir/t_gen_intdot2/t_gen_intdot.vcd");
$dumpvars(12, t);
end
`endif
endmodule
module One;
wire one = 1'b1;
endmodule
module Genit (
input clk,
input check);
// ARRAY
One cellarray1[1:0] (); //cellarray[0..1][0..1]
always @ (posedge clk) if (cellarray1[0].one !== 1'b1) $stop;
always @ (posedge clk) if (cellarray1[1].one !== 1'b1) $stop;
// IF
generate
// genblk1 refers to the if's name, not the "generate" itself.
if (1'b1) // IMPLIED begin: genblk1
One ifcell1(); // genblk1.ifcell1
else
One ifcell1(); // genblk1.ifcell1
endgenerate
// On compliant simulators "Implicit name" not allowed here; IE we can't use "genblk1" etc
`ifdef verilator
always @ (posedge clk) if (genblk1.ifcell1.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
generate
begin : namedif2
if (1'b1)
One ifcell2(); // namedif2.genblk1.ifcell2
end
endgenerate
`ifdef verilator
always @ (posedge clk) if (namedif2.genblk1.ifcell2.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
generate
if (1'b1)
begin : namedif3
One ifcell3(); // namedif3.ifcell3
end
endgenerate
always @ (posedge clk) if (namedif3.ifcell3.one !== 1'b1) $stop;
// CASE
generate
case (1'b1)
1'b1 :
One casecell10(); // genblk3.casecell10
endcase
endgenerate
`ifdef verilator
always @ (posedge clk) if (genblk3.casecell10.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
generate
case (1'b1)
1'b1 : begin : namedcase11
One casecell11();
end
endcase
endgenerate
always @ (posedge clk) if (namedcase11.casecell11.one !== 1'b1) $stop;
genvar i;
genvar j;
// IF
generate
for (i = 0; i < 2; i = i + 1)
One cellfor20 (); // genblk4[0..1].cellfor20
endgenerate
`ifdef verilator
always @ (posedge clk) if (genblk4[0].cellfor20.one !== 1'b1) $stop;
always @ (posedge clk) if (genblk4[1].cellfor20.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
// COMBO
generate
for (i = 0; i < 2; i = i + 1)
begin : namedfor21
One cellfor21 (); // namedfor21[0..1].cellfor21
end
endgenerate
always @ (posedge clk) if (namedfor21[0].cellfor21.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor21[1].cellfor21.one !== 1'b1) $stop;
generate
for (i = 0; i < 2; i = i + 1)
begin : namedfor30
for (j = 0; j < 2; j = j + 1)
begin : forb30
if (j == 0)
begin : forif30
One cellfor30a (); // namedfor30[0..1].forb30[0].forif30.cellfor30a
end
else
`ifdef verilator
begin : forif30b
`else
begin : forif30 // forif30 seems to work on some simulators, not verilator yet
`endif
One cellfor30b (); // namedfor30[0..1].forb30[1].forif30.cellfor30b
end
end
end
endgenerate
always @ (posedge clk) if (namedfor30[0].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor30[1].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop;
`ifdef verilator
always @ (posedge clk) if (namedfor30[0].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor30[1].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop;
`else
always @ (posedge clk) if (namedfor30[0].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor30[1].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop;
`endif
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: rx_port_reader.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Handles the RX lifecycle and issuing requests for receiving
// data input.
// for the RIFFA channel.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_RXPORTRD_MAIN_IDLE 6'b00_0001
`define S_RXPORTRD_MAIN_CHECK 6'b00_0010
`define S_RXPORTRD_MAIN_READ 6'b00_0100
`define S_RXPORTRD_MAIN_FLUSH 6'b00_1000
`define S_RXPORTRD_MAIN_DONE 6'b01_0000
`define S_RXPORTRD_MAIN_RESET 6'b10_0000
`define S_RXPORTRD_RX_IDLE 8'b0000_0001
`define S_RXPORTRD_RX_BUF 8'b0000_0010
`define S_RXPORTRD_RX_ADJ_0 8'b0000_0100
`define S_RXPORTRD_RX_ADJ_1 8'b0000_1000
`define S_RXPORTRD_RX_ISSUE 8'b0001_0000
`define S_RXPORTRD_RX_WAIT_0 8'b0010_0000
`define S_RXPORTRD_RX_WAIT_1 8'b0100_0000
`define S_RXPORTRD_RX_DONE 8'b1000_0000
`timescale 1ns/1ns
module rx_port_reader #(
parameter C_DATA_WIDTH = 9'd64,
parameter C_FIFO_DEPTH = 1024,
parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
// Local parameters
parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1),
parameter C_FIFO_WORDS = (C_DATA_WIDTH/32)*C_FIFO_DEPTH
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input [31:0] TXN_DATA, // Read transaction data
input TXN_LEN_VALID, // Read transaction length valid
input TXN_OFF_LAST_VALID, // Read transaction offset/last valid
output [31:0] TXN_DONE_LEN, // Read transaction actual transfer length
output TXN_DONE, // Read transaction done
output TXN_ERR, // Read transaction completed with error
input TXN_DONE_ACK, // Read transaction actual transfer length read
output TXN_DATA_FLUSH, // Request that all data in the packer be flushed
input TXN_DATA_FLUSHED, // All data in the packer has been flushed
output RX_REQ, // Issue a read request
output [63:0] RX_ADDR, // Request address
output [9:0] RX_LEN, // Request length
input RX_REQ_ACK, // Request has been accepted
input [C_DATA_WORD_WIDTH-1:0] RX_DATA_EN, // Incoming read data enable
input RX_DONE, // Incoming read completed
input RX_ERR, // Incoming read completed with error
input SG_DONE, // Incoming scatter gather read completed
input SG_ERR, // Incoming scatter gather read completed with error
input [63:0] SG_ELEM_ADDR, // Scatter gather element address
input [31:0] SG_ELEM_LEN, // Scatter gather element length (in words)
input SG_ELEM_RDY, // Scatter gather element ready
output SG_ELEM_REN, // Scatter gather element read enable
output SG_RST, // Scatter gather reset
output CHNL_RX, // Signal channel RX
output [31:0] CHNL_RX_LEN, // Channel RX length
output CHNL_RX_LAST, // Channel RX last
output [30:0] CHNL_RX_OFF, // Channel RX offset
input CHNL_RX_RECVD, // Channel RX received
input CHNL_RX_ACK_RECVD, // Channel RX acknowledgment received
input [31:0] CHNL_RX_CONSUMED // Channel words consumed in current RX
);
`include "functions.vh"
reg [31:0] rTxnData=0, _rTxnData=0;
reg rTxnOffLastValid=0, _rTxnOffLastValid=0;
reg rTxnLenValid=0, _rTxnLenValid=0;
reg [C_DATA_WORD_WIDTH-1:0] rRxDataEn=0, _rRxDataEn=0;
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [5:0] rMainState=`S_RXPORTRD_MAIN_IDLE, _rMainState=`S_RXPORTRD_MAIN_IDLE;
reg [31:0] rOffLast=0, _rOffLast=0;
reg [31:0] rReadWords=0, _rReadWords=0;
reg rReadWordsZero=0, _rReadWordsZero=0;
reg [0:0] rStart=0, _rStart=0;
reg [3:0] rFlushed=0, _rFlushed=0;
reg [31:0] rDoneLen=0, _rDoneLen=0;
reg rTxnDone=0, _rTxnDone=0;
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [7:0] rRxState=`S_RXPORTRD_RX_IDLE, _rRxState=`S_RXPORTRD_RX_IDLE;
reg rSgRen=0, _rSgRen=0;
reg [31:0] rWords=0, _rWords=0;
reg [31:0] rBufWords=0, _rBufWords=0;
reg [31:0] rBufWordsInit=0, _rBufWordsInit=0;
reg rLargeBuf=0, _rLargeBuf=0;
reg [63:0] rAddr=64'd0, _rAddr=64'd0;
reg [3:0] rValsProp=0, _rValsProp=0;
reg [2:0] rCarry=0, _rCarry=0;
reg rCopyBufWords=0, _rCopyBufWords=0;
reg rUseInit=0, _rUseInit=0;
reg [10:0] rPageRem=0, _rPageRem=0;
reg rPageSpill=0, _rPageSpill=0;
reg rPageSpillInit=0, _rPageSpillInit=0;
reg [10:0] rPreLen=0, _rPreLen=0;
reg [2:0] rMaxPayloadTrain=0, _rMaxPayloadTrain=0;
reg [2:0] rMaxPayloadShift=0, _rMaxPayloadShift=0;
reg [9:0] rMaxPayload=0, _rMaxPayload=0;
reg rPayloadSpill=0, _rPayloadSpill=0;
reg rMaxLen=0, _rMaxLen=0;
reg [9:0] rLen=0, _rLen=0;
reg rLenEQWordsHi=0, _rLenEQWordsHi=0;
reg rLenEQWordsLo=0, _rLenEQWordsLo=0;
reg rLenEQBufWordsHi=0, _rLenEQBufWordsHi=0;
reg rLenEQBufWordsLo=0, _rLenEQBufWordsLo=0;
reg [31:0] rRecvdWords=0, _rRecvdWords=0;
reg [31:0] rReqdWords=0, _rReqdWords=0;
reg [31:0] rRequestingWords=0, _rRequestingWords=0;
reg [31:0] rAvailWords=0, _rAvailWords=0;
reg [31:0] rPartWords=0, _rPartWords=0;
reg [10:0] rAckCount=0, _rAckCount=0;
reg rAckCountEQ0=0, _rAckCountEQ0=0;
reg rLastDoneRead=1, _rLastDoneRead=1;
reg rTxnDoneAck=0, _rTxnDoneAck=0;
reg rPartWordsRecvd=0, _rPartWordsRecvd=0;
reg rCarryInv=0, _rCarryInv=0;
reg rSpaceAvail=0, _rSpaceAvail=0;
reg rPartialDone=0, _rPartialDone=0;
reg rReqPartialDone=0, _rReqPartialDone=0;
reg rErr=0, _rErr=0;
assign TXN_DONE_LEN = rDoneLen;
assign TXN_DONE = (rTxnDone | rPartialDone);
assign TXN_ERR = rErr;
assign TXN_DATA_FLUSH = rMainState[3]; // S_RXPORTRD_MAIN_FLUSH
assign RX_REQ = (rRxState[4] & rSpaceAvail); // S_RXPORTRD_RX_ISSUE
assign RX_ADDR = rAddr;
assign RX_LEN = rLen;
assign SG_ELEM_REN = rSgRen;
assign SG_RST = rMainState[1]; // S_RXPORTRD_MAIN_CHECK
assign CHNL_RX = (rMainState[2] | rMainState[3] | rMainState[4]); // S_RXPORTRD_MAIN_READ | S_RXPORTRD_MAIN_FLUSH | S_RXPORTRD_MAIN_DONE
assign CHNL_RX_LEN = rReadWords;
assign CHNL_RX_LAST = rOffLast[0];
assign CHNL_RX_OFF = rOffLast[31:1];
// Buffer signals that come from outside the rx_port.
always @ (posedge CLK) begin
rTxnData <= #1 _rTxnData;
rTxnOffLastValid <= #1 _rTxnOffLastValid;
rTxnLenValid <= #1 _rTxnLenValid;
rTxnDoneAck <= #1 (RST ? 1'd0 : _rTxnDoneAck);
rRxDataEn <= #1 _rRxDataEn;
end
always @ (*) begin
_rTxnData = TXN_DATA;
_rTxnOffLastValid = TXN_OFF_LAST_VALID;
_rTxnLenValid = TXN_LEN_VALID;
_rTxnDoneAck = TXN_DONE_ACK;
_rRxDataEn = RX_DATA_EN;
end
// Handle RX lifecycle.
always @ (posedge CLK) begin
rMainState <= #1 (RST ? `S_RXPORTRD_MAIN_IDLE : _rMainState);
rOffLast <= #1 _rOffLast;
rReadWords <= #1 _rReadWords;
rReadWordsZero <= #1 _rReadWordsZero;
rStart <= #1 _rStart;
rFlushed <= #1 _rFlushed;
rDoneLen <= #1 (RST ? 0 : _rDoneLen);
rTxnDone <= #1 _rTxnDone;
end
always @ (*) begin
_rMainState = rMainState;
_rDoneLen = rDoneLen;
_rTxnDone = rTxnDone;
_rOffLast = (rTxnOffLastValid ? rTxnData : rOffLast);
_rReadWords = (rMainState[0] & rTxnLenValid ? rTxnData : rReadWords);
_rReadWordsZero = (rReadWords == 0);
_rStart = ((rStart<<1) | rTxnLenValid);
_rFlushed = ((rFlushed<<1) | TXN_DATA_FLUSHED);
case (rMainState)
`S_RXPORTRD_MAIN_IDLE: begin // Wait for new read transaction offset/last & length
_rTxnDone = 0;
if (rStart[0])
_rMainState = `S_RXPORTRD_MAIN_CHECK;
end
`S_RXPORTRD_MAIN_CHECK: begin // See if we should start a transaction
if (!rReadWordsZero)
_rMainState = `S_RXPORTRD_MAIN_READ;
else if (rOffLast[0])
_rMainState = `S_RXPORTRD_MAIN_FLUSH;
else
_rMainState = `S_RXPORTRD_MAIN_IDLE;
end
`S_RXPORTRD_MAIN_READ: begin // Issue read transfers, wait for data to arrive
if (rRxState[7] & rLastDoneRead) begin // S_RXPORTRD_RX_DONE
_rDoneLen = rRecvdWords;
_rMainState = `S_RXPORTRD_MAIN_FLUSH;
end
end
`S_RXPORTRD_MAIN_FLUSH: begin // Wait for data to be flushed
if (rFlushed[3])
_rMainState = `S_RXPORTRD_MAIN_DONE;
end
`S_RXPORTRD_MAIN_DONE: begin // Wait for RX to be received and ackd in the channel
if (CHNL_RX_RECVD & CHNL_RX_ACK_RECVD)
_rMainState = `S_RXPORTRD_MAIN_RESET;
end
`S_RXPORTRD_MAIN_RESET: begin // Wait until RX has dropped in the channel
if (!CHNL_RX_RECVD) begin
_rTxnDone = 1;
_rMainState = `S_RXPORTRD_MAIN_IDLE;
end
end
default: begin
_rMainState = `S_RXPORTRD_MAIN_IDLE;
end
endcase
end
// Issue the read requests at the buffer level. Decrement the amount requested
// after every request. Continue until all words have been requested.
wire [9:0] wAddrLoInv = ~rAddr[11:2];
always @ (posedge CLK) begin
rRxState <= #1 (RST ? `S_RXPORTRD_RX_IDLE : _rRxState);
rSgRen <= #1 (RST ? 1'd0: _rSgRen);
rWords <= #1 _rWords;
rBufWords <= #1 _rBufWords;
rBufWordsInit <= #1 _rBufWordsInit;
rLargeBuf <= #1 _rLargeBuf;
rAddr <= #1 _rAddr;
rCarry <= #1 _rCarry;
rValsProp <= #1 _rValsProp;
rPageRem <= #1 _rPageRem;
rPageSpill <= #1 _rPageSpill;
rPageSpillInit <= #1 _rPageSpillInit;
rCopyBufWords <= #1 _rCopyBufWords;
rUseInit <= #1 _rUseInit;
rPreLen <= #1 _rPreLen;
rMaxPayloadTrain <= #1 _rMaxPayloadTrain;
rMaxPayloadShift <= #1 _rMaxPayloadShift;
rMaxPayload <= #1 _rMaxPayload;
rPayloadSpill <= #1 _rPayloadSpill;
rMaxLen <= #1 _rMaxLen;
rLen <= #1 _rLen;
rLenEQWordsHi <= #1 _rLenEQWordsHi;
rLenEQWordsLo <= #1 _rLenEQWordsLo;
rLenEQBufWordsHi <= #1 _rLenEQBufWordsHi;
rLenEQBufWordsLo <= #1 _rLenEQBufWordsLo;
end
always @ (*) begin
_rRxState = rRxState;
_rCopyBufWords = rCopyBufWords;
_rUseInit = rUseInit;
_rSgRen = rSgRen;
_rValsProp = ((rValsProp<<1) | rRxState[2]); // S_RXPORTRD_RX_ADJ_0
_rLargeBuf = (SG_ELEM_LEN > rWords);
{_rCarry[0], _rAddr[15:0]} = (rRxState[1] ? SG_ELEM_ADDR[15:0] : (rAddr[15:0] + ({12{RX_REQ_ACK}} & {rLen,2'd0})));
{_rCarry[1], _rAddr[31:16]} = (rRxState[1] ? SG_ELEM_ADDR[31:16] : (rAddr[31:16] + rCarry[0]));
{_rCarry[2], _rAddr[47:32]} = (rRxState[1] ? SG_ELEM_ADDR[47:32] : (rAddr[47:32] + rCarry[1]));
_rAddr[63:48] = (rRxState[1] ? SG_ELEM_ADDR[63:48] : (rAddr[63:48] + rCarry[2]));
_rWords = (rRxState[0] ? rReadWords : (rWords - ({10{RX_REQ_ACK}} & rLen)));
_rBufWordsInit = (rLargeBuf ? rWords : SG_ELEM_LEN);
_rBufWords = (rCopyBufWords ? rBufWordsInit : rBufWords) - ({10{RX_REQ_ACK}} & rLen);
_rPageRem = (wAddrLoInv + 1'd1);
_rPageSpillInit = (rBufWordsInit > rPageRem);
_rPageSpill = (rBufWords > rPageRem);
_rPreLen = ((rPageSpillInit & rUseInit) | (rPageSpill & !rUseInit) ? rPageRem : rBufWords[10:0]);
_rMaxPayloadTrain = (CONFIG_MAX_READ_REQUEST_SIZE > 3'd4 ? 3'd4 : CONFIG_MAX_READ_REQUEST_SIZE);
_rMaxPayloadShift = (C_MAX_READ_REQ[2:0] < rMaxPayloadTrain ? C_MAX_READ_REQ[2:0] : rMaxPayloadTrain);
_rMaxPayload = (6'd32<<rMaxPayloadShift);
_rPayloadSpill = (rPreLen > rMaxPayload);
_rMaxLen = ((rMaxLen & !rValsProp[2]) | RX_REQ_ACK);
_rLen = (rPayloadSpill | rMaxLen ? rMaxPayload : rPreLen[9:0]);
_rLenEQWordsHi = (16'd0 == rWords[31:16]);
_rLenEQWordsLo = ({6'd0, rLen} == rWords[15:0]);
_rLenEQBufWordsHi = (16'd0 == rBufWords[31:16]);
_rLenEQBufWordsLo = ({6'd0, rLen} == rBufWords[15:0]);
case (rRxState)
`S_RXPORTRD_RX_IDLE: begin // Wait for a new read transaction
if (rMainState[2]) // S_RXPORTRD_MAIN_READ
_rRxState = `S_RXPORTRD_RX_BUF;
end
`S_RXPORTRD_RX_BUF: begin // Wait for buffer length and address
if (SG_ELEM_RDY) begin
_rSgRen = 1;
_rRxState = `S_RXPORTRD_RX_ADJ_0;
end
else if (rErr) begin
_rRxState = `S_RXPORTRD_RX_WAIT_0;
end
end
`S_RXPORTRD_RX_ADJ_0: begin // Fix for large buffer
_rSgRen = 0;
_rCopyBufWords = rSgRen;
_rRxState = `S_RXPORTRD_RX_ADJ_1;
end
// (bufwords and pagerem valid here)
`S_RXPORTRD_RX_ADJ_1: begin // Wait for the value to propagate
// Check for page boundary crossing
// Fix for page boundary crossing
// Check for max read payload
// Fix for max read payload
_rCopyBufWords = 0;
_rUseInit = rCopyBufWords;
if (rValsProp[3])
_rRxState = `S_RXPORTRD_RX_ISSUE;
end
`S_RXPORTRD_RX_ISSUE: begin // Wait for the request to be accepted
if (RX_REQ_ACK) begin
if (rErr | (rLenEQWordsHi & rLenEQWordsLo))
_rRxState = `S_RXPORTRD_RX_WAIT_0;
else if (rLenEQBufWordsHi & rLenEQBufWordsLo)
_rRxState = `S_RXPORTRD_RX_BUF;
else
_rRxState = `S_RXPORTRD_RX_ADJ_0;
end
end
`S_RXPORTRD_RX_WAIT_0: begin // Wait for rAckCount to update
_rRxState = `S_RXPORTRD_RX_WAIT_1;
end
`S_RXPORTRD_RX_WAIT_1: begin // Wait for requested data to arrive
if (rAckCountEQ0)
_rRxState = `S_RXPORTRD_RX_DONE;
end
`S_RXPORTRD_RX_DONE: begin // Signal done
if (rMainState[3]) // S_RXPORTRD_MAIN_FLUSH
_rRxState = `S_RXPORTRD_RX_IDLE;
end
default: begin
_rRxState = `S_RXPORTRD_RX_IDLE;
end
endcase
end
// Count the data.
always @ (posedge CLK) begin
rRecvdWords <= #1 _rRecvdWords;
rReqdWords <= #1 _rReqdWords;
rPartWords <= #1 _rPartWords;
rAckCount <= #1 _rAckCount;
rAckCountEQ0 <= #1 _rAckCountEQ0;
rPartWordsRecvd <= #1 _rPartWordsRecvd;
rRequestingWords <= #1 _rRequestingWords;
rAvailWords <= #1 _rAvailWords;
rCarryInv <= #1 _rCarryInv;
rSpaceAvail <= #1 _rSpaceAvail;
rLastDoneRead <= #1 (RST ? 1'd1 : _rLastDoneRead);
end
always @ (*) begin
// Count words as they arrive (words from the rx_engine directly).
if (rMainState[0]) // S_RXPORTRD_MAIN_IDLE
_rRecvdWords = #1 0;
else
_rRecvdWords = #1 rRecvdWords + rRxDataEn;
// Count words as they are requested.
if (rMainState[0]) // S_RXPORTRD_MAIN_IDLE
_rReqdWords = #1 0;
else
_rReqdWords = #1 rReqdWords + ({10{RX_REQ_ACK}} & rLen);
// Track outstanding requests
if (rMainState[0]) // S_RXPORTRD_MAIN_IDLE
_rAckCount = 0;
else
_rAckCount = rAckCount + RX_REQ_ACK - RX_DONE;
_rAckCountEQ0 = (rAckCount == 11'd0);
// Track when the user reads the actual transfer amount.
_rLastDoneRead = (rTxnDone ? 1'd0 : (rLastDoneRead | rTxnDoneAck));
// Track the amount of words that are expected to arrive.
_rPartWords = #1 (rTxnLenValid ? rTxnData : rPartWords);
// Compare counts.
_rPartWordsRecvd = (rRecvdWords >= rPartWords);
_rRequestingWords = rReqdWords + rLen;
{_rCarryInv, _rAvailWords[15:0]} = {1'd1, rRequestingWords[15:0]} - CHNL_RX_CONSUMED[15:0];
_rAvailWords[31:16] = rRequestingWords[31:16] - CHNL_RX_CONSUMED[31:16] - !rCarryInv;
_rSpaceAvail = (rAvailWords <= C_FIFO_WORDS);
end
// Facilitate sending a TXN_DONE when we receive a TXN_ACK after the transaction
// has begun sending. This will happen when the workstation detects that it has
// sent/used all its currently mapped scatter gather elements, but it's not enough
// to complete the transaction. The TXN_DONE will let the workstation know it can
// release the current scatter gather mappings and allocate new ones.
always @ (posedge CLK) begin
rPartialDone <= #1 _rPartialDone;
rReqPartialDone <= #1 (RST ? 1'd0 : _rReqPartialDone);
end
always @ (*) begin
// Signal TXN_DONE after we've recieved the (seemingly superfluous) TXN_ACK
// and received the corresponding amount of words.
_rPartialDone = (rReqPartialDone & rPartWordsRecvd);
// Keep track of (seemingly superfluous) TXN_ACK requests.
if ((rReqPartialDone & rPartWordsRecvd) | rMainState[0]) // S_RXPORTRD_MAIN_IDLE
_rReqPartialDone = 0;
else
_rReqPartialDone = (rReqPartialDone | rTxnLenValid);
end
// Handle errors in the main data or scatter gather data.
always @ (posedge CLK) begin
rErr <= #1 (RST ? 1'd0 : _rErr);
end
always @ (*) begin
// Keep track of errors if we encounter them.
if (rMainState[0]) // S_RXPORTRD_MAIN_IDLE
_rErr = 0;
else
_rErr = (rErr | (RX_DONE & RX_ERR) | (SG_DONE & SG_ERR));
end
/*
wire [35:0] wControl0;
chipscope_icon_1 cs_icon(
.CONTROL0(wControl0)
);
chipscope_ila_t8_512 a0(
.CLK(CLK),
.CONTROL(wControl0),
.TRIG0({TXN_LEN_VALID | TXN_DONE_ACK | TXN_DONE | TXN_ERR, 1'd0, rMainState}),
.DATA({176'd0,
64'd0, // 64
rAddr, // 64
SG_ELEM_RDY, // 1
1'd0, // 1
1'd0, // 1
1'd0, // 1
rSgRen, // 1
1'd0, // 1
rLastDoneRead, // 1
rLen, // 10
rWords, // 32
rAckCount, // 11
rPartWords, // 32
rPartWordsRecvd, // 1
rReqPartialDone, // 1
rPartialDone, // 1
rTxnDone, // 1
rRxState, // 8
rRecvdWords, // 32
rReadWords, // 32
TXN_LEN_VALID, // 1
TXN_DONE_ACK, // 1
rDoneLen, // 32
rMainState}) // 6
);
*/
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:%version
// \ \ Application: MIG
// / / Filename: mig_7series_v2_3_poc_meta.v
// /___/ /\ Date Last Modified: $$
// \ \ / \ Date Created:Tue 15 Jan 2014
// \___\/\___\
//
//Device: Virtex-7
//Design Name: DDR3 SDRAM
//Purpose: Phaser output calibration meta controller.
//
// Compute center of the window set up with with the ktap_left,
// ktap_right dance (hereafter "the window"). Also compute center of the
// edge (hereafter "the edge") to be aligned in the center
// of this window.
//
// Following the ktap_left/right dance, the to be centered edge is
// always left at the right edge of the window
// if SCANFROMRIGHT == 1, and the left edge otherwise.
//
// An assumption is the rise(0) case has a window wider than the noise on the
// edge. The noise case with the possibly narrow window
// will always be shifted by 90. And the fall(180) case is shifted by
// 90 twice. Hence when we start, we can assume the center of the
// edge is to the right/left of the the window center.
//
// The actual hardware does not necessarily monotonically appear to
// move the window centers. Because of noise, it is possible for the
// centered edge to move opposite the expected direction with a tap increment.
//
// This problem is solved by computing the absolute difference between
// the centers and the circular distance between the centers. These will
// be the same until the difference transits through zero. Then the circular
// difference will jump to almost the value of TAPSPERKCLK.
//
// The window center computation is done at 1/2 tap increments to maintain
// resolution through the divide by 2 for centering.
//
// There is a corner case of when the shift is greater than 180 degress. In
// this case the absolute difference and the circular difference will be
// unequal at the beginning of the alignment. This is solved by latching
// if they are equal at the end of each cycle. The completion must see
// that they were equal in the previous cycle, but are not equal in this cycle.
//
// Since the phaser out steps are of unknown size, it is possible to overshoot
// the center. The previous difference is recorded and if its less than the current
// difference, poc_backup is driven high.
//
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v2_3_poc_meta #
(parameter SCANFROMRIGHT = 0,
parameter TCQ = 100,
parameter TAPCNTRWIDTH = 7,
parameter TAPSPERKCLK = 112)
(/*AUTOARG*/
// Outputs
mmcm_edge_detect_done, poc_backup, mmcm_lbclk_edge_aligned,
// Inputs
rst, clk, mmcm_edge_detect_rdy, run, run_polarity, run_end,
rise_lead_right, rise_trail_left, rise_lead_center,
rise_trail_center, rise_trail_right, rise_lead_left, ninety_offsets,
use_noise_window, ktap_at_right_edge, ktap_at_left_edge
);
localparam NINETY = TAPSPERKCLK/4;
function [TAPCNTRWIDTH-1:0] offset (input [TAPCNTRWIDTH-1:0] a,
input [1:0] b,
input integer base);
integer offset_ii;
begin
offset_ii = (a + b * NINETY) < base
? (a + b * NINETY)
: (a + b * NINETY - base);
offset = offset_ii[TAPCNTRWIDTH-1:0];
end
endfunction // offset
function [TAPCNTRWIDTH-1:0] mod_sub (input [TAPCNTRWIDTH-1:0] a,
input [TAPCNTRWIDTH-1:0] b,
input integer base);
begin
mod_sub = (a>=b) ? a-b : a+base-b;
end
endfunction // mod_sub
function [TAPCNTRWIDTH:0] center (input [TAPCNTRWIDTH-1:0] left,
input [TAPCNTRWIDTH-1:0] diff,
input integer base);
integer center_ii;
begin
center_ii = ({left, 1'b0} + diff < base * 2)
? {left, 1'b0} + diff + 32'h0
: {left, 1'b0} + diff - base * 2;
center = center_ii[TAPCNTRWIDTH:0];
end
endfunction // center
input rst;
input clk;
input mmcm_edge_detect_rdy;
wire reset_run_ends = rst || ~mmcm_edge_detect_rdy;
// This input used only for the SVA.
input [TAPCNTRWIDTH-1:0] run;
input run_end;
reg run_end_r, run_end_r1, run_end_r2, run_end_r3;
always @(posedge clk) run_end_r <= #TCQ run_end;
always @(posedge clk) run_end_r1 <= #TCQ run_end_r;
always @(posedge clk) run_end_r2 <= #TCQ run_end_r1;
always @(posedge clk) run_end_r3 <= #TCQ run_end_r2;
input run_polarity;
reg run_polarity_held_ns, run_polarity_held_r;
always @(posedge clk) run_polarity_held_r <= #TCQ run_polarity_held_ns;
always @(*) run_polarity_held_ns = run_end ? run_polarity : run_polarity_held_r;
reg [1:0] run_ends_r;
reg [1:0] run_ends_ns;
always @(posedge clk) run_ends_r <= #TCQ run_ends_ns;
always @(*) begin
run_ends_ns = run_ends_r;
if (reset_run_ends) run_ends_ns = 2'b0;
else case (run_ends_r)
2'b00 : run_ends_ns = run_ends_r + {1'b0, run_end_r3 && run_polarity_held_r};
2'b01, 2'b10 : run_ends_ns = run_ends_r + {1'b0, run_end_r3};
endcase // case (run_ends_r)
end
reg done_r;
wire done_ns = mmcm_edge_detect_rdy && &run_ends_r;
always @(posedge clk) done_r <= #TCQ done_ns;
output mmcm_edge_detect_done;
assign mmcm_edge_detect_done = done_r;
input [TAPCNTRWIDTH-1:0] rise_lead_right;
input [TAPCNTRWIDTH-1:0] rise_trail_left;
input [TAPCNTRWIDTH-1:0] rise_lead_center;
input [TAPCNTRWIDTH-1:0] rise_trail_center;
input [TAPCNTRWIDTH-1:0] rise_trail_right;
input [TAPCNTRWIDTH-1:0] rise_lead_left;
input [1:0] ninety_offsets;
wire [1:0] offsets = SCANFROMRIGHT == 1 ? ninety_offsets : 2'b00 - ninety_offsets;
wire [TAPCNTRWIDTH-1:0] rise_lead_center_offset_ns = offset(rise_lead_center, offsets, TAPSPERKCLK);
wire [TAPCNTRWIDTH-1:0] rise_trail_center_offset_ns = offset(rise_trail_center, offsets, TAPSPERKCLK);
reg [TAPCNTRWIDTH-1:0] rise_lead_center_offset_r, rise_trail_center_offset_r;
always @(posedge clk) rise_lead_center_offset_r <= #TCQ rise_lead_center_offset_ns;
always @(posedge clk) rise_trail_center_offset_r <= #TCQ rise_trail_center_offset_ns;
wire [TAPCNTRWIDTH-1:0] edge_diff_ns = mod_sub(rise_trail_center_offset_r, rise_lead_center_offset_r, TAPSPERKCLK);
reg [TAPCNTRWIDTH-1:0] edge_diff_r;
always @(posedge clk) edge_diff_r <= #TCQ edge_diff_ns;
wire [TAPCNTRWIDTH:0] edge_center_ns = center(rise_lead_center_offset_r, edge_diff_r, TAPSPERKCLK);
reg [TAPCNTRWIDTH:0] edge_center_r;
always @(posedge clk) edge_center_r <= #TCQ edge_center_ns;
input use_noise_window;
wire [TAPCNTRWIDTH-1:0] left = use_noise_window ? rise_lead_left : rise_trail_left;
wire [TAPCNTRWIDTH-1:0] right = use_noise_window ? rise_trail_right : rise_lead_right;
wire [TAPCNTRWIDTH-1:0] center_diff_ns = mod_sub(right, left, TAPSPERKCLK);
reg [TAPCNTRWIDTH-1:0] center_diff_r;
always @(posedge clk) center_diff_r <= #TCQ center_diff_ns;
wire [TAPCNTRWIDTH:0] window_center_ns = center(left, center_diff_r, TAPSPERKCLK);
reg [TAPCNTRWIDTH:0] window_center_r;
always @(posedge clk) window_center_r <= #TCQ window_center_ns;
localparam TAPSPERKCLKX2 = TAPSPERKCLK * 2;
wire [TAPCNTRWIDTH+1:0] left_center = {1'b0, SCANFROMRIGHT == 1 ? window_center_r : edge_center_r};
wire [TAPCNTRWIDTH+1:0] right_center = {1'b0, SCANFROMRIGHT == 1 ? edge_center_r : window_center_r};
wire [TAPCNTRWIDTH+1:0] diff_ns = right_center >= left_center
? right_center - left_center
: right_center + TAPSPERKCLKX2[TAPCNTRWIDTH+1:0] - left_center;
reg [TAPCNTRWIDTH+1:0] diff_r;
always @(posedge clk) diff_r <= #TCQ diff_ns;
wire [TAPCNTRWIDTH+1:0] abs_diff = diff_r > TAPSPERKCLKX2[TAPCNTRWIDTH+1:0]/2
? TAPSPERKCLKX2[TAPCNTRWIDTH+1:0] - diff_r
: diff_r;
reg [TAPCNTRWIDTH+1:0] prev_ns, prev_r;
always @(posedge clk) prev_r <= #TCQ prev_ns;
always @(*) prev_ns = done_ns ? diff_r : prev_r;
input ktap_at_right_edge;
input ktap_at_left_edge;
wire centering = !(ktap_at_right_edge || ktap_at_left_edge);
wire diffs_eq = abs_diff == diff_r;
reg diffs_eq_ns, diffs_eq_r;
always @(*) diffs_eq_ns = centering && ((done_r && done_ns) ? diffs_eq : diffs_eq_r);
always @(posedge clk) diffs_eq_r <= #TCQ diffs_eq_ns;
reg edge_aligned_r;
reg prev_valid_ns, prev_valid_r;
always @(posedge clk) prev_valid_r <= #TCQ prev_valid_ns;
always @(*) prev_valid_ns = (~rst && ~ktap_at_right_edge && ~ktap_at_left_edge && ~edge_aligned_r) && prev_valid_r | done_ns;
wire indicate_alignment = ~rst && centering && done_ns;
wire edge_aligned_ns = indicate_alignment && (~|diff_r || ~diffs_eq & diffs_eq_r);
always @(posedge clk) edge_aligned_r <= #TCQ edge_aligned_ns;
reg poc_backup_r;
wire poc_backup_ns = edge_aligned_ns && abs_diff > prev_r;
always @(posedge clk) poc_backup_r <= #TCQ poc_backup_ns;
output poc_backup;
assign poc_backup = poc_backup_r;
output mmcm_lbclk_edge_aligned;
assign mmcm_lbclk_edge_aligned = edge_aligned_r;
endmodule // mig_7series_v2_3_poc_meta
// Local Variables:
// verilog-library-directories:(".")
// verilog-library-extensions:(".v")
// End:
|
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * Copyright INRIA, CNRS and contributors *)
(* <O___,, * (see version control and CREDITS file for authors & dates) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(** * Typeclass-based relations, tactics and standard instances
This is the basic theory needed to formalize morphisms and setoids.
Author: Matthieu Sozeau
Institution: LRI, CNRS UMR 8623 - University Paris Sud
*)
Require Export Coq.Classes.Init.
Require Import Coq.Program.Basics.
Require Import Coq.Program.Tactics.
Generalizable Variables A B C D R S T U l eqA eqB eqC eqD.
Set Universe Polymorphism.
Definition crelation (A : Type) := A -> A -> Type.
Definition arrow (A B : Type) := A -> B.
Definition flip {A B C : Type} (f : A -> B -> C) := fun x y => f y x.
Definition iffT (A B : Type) := ((A -> B) * (B -> A))%type.
(** We allow to unfold the [crelation] definition while doing morphism search. *)
Section Defs.
Context {A : Type}.
(** We rebind crelational properties in separate classes to be able to overload each proof. *)
Class Reflexive (R : crelation A) :=
reflexivity : forall x : A, R x x.
Definition complement (R : crelation A) : crelation A :=
fun x y => R x y -> False.
(** Opaque for proof-search. *)
Typeclasses Opaque complement iffT.
(** These are convertible. *)
Lemma complement_inverse R : complement (flip R) = flip (complement R).
Proof. reflexivity. Qed.
Class Irreflexive (R : crelation A) :=
irreflexivity : Reflexive (complement R).
Class Symmetric (R : crelation A) :=
symmetry : forall {x y}, R x y -> R y x.
Class Asymmetric (R : crelation A) :=
asymmetry : forall {x y}, R x y -> (complement R y x : Type).
Class Transitive (R : crelation A) :=
transitivity : forall {x y z}, R x y -> R y z -> R x z.
(** Various combinations of reflexivity, symmetry and transitivity. *)
(** A [PreOrder] is both Reflexive and Transitive. *)
Class PreOrder (R : crelation A) := {
PreOrder_Reflexive :> Reflexive R | 2 ;
PreOrder_Transitive :> Transitive R | 2 }.
(** A [StrictOrder] is both Irreflexive and Transitive. *)
Class StrictOrder (R : crelation A) := {
StrictOrder_Irreflexive :> Irreflexive R ;
StrictOrder_Transitive :> Transitive R }.
(** By definition, a strict order is also asymmetric *)
Global Instance StrictOrder_Asymmetric `(StrictOrder R) : Asymmetric R.
Proof. firstorder. Qed.
(** A partial equivalence crelation is Symmetric and Transitive. *)
Class PER (R : crelation A) := {
PER_Symmetric :> Symmetric R | 3 ;
PER_Transitive :> Transitive R | 3 }.
(** Equivalence crelations. *)
Class Equivalence (R : crelation A) := {
Equivalence_Reflexive :> Reflexive R ;
Equivalence_Symmetric :> Symmetric R ;
Equivalence_Transitive :> Transitive R }.
(** An Equivalence is a PER plus reflexivity. *)
Global Instance Equivalence_PER {R} `(Equivalence R) : PER R | 10 :=
{ PER_Symmetric := Equivalence_Symmetric ;
PER_Transitive := Equivalence_Transitive }.
(** We can now define antisymmetry w.r.t. an equivalence crelation on the carrier. *)
Class Antisymmetric eqA `{equ : Equivalence eqA} (R : crelation A) :=
antisymmetry : forall {x y}, R x y -> R y x -> eqA x y.
Class subrelation (R R' : crelation A) :=
is_subrelation : forall {x y}, R x y -> R' x y.
(** Any symmetric crelation is equal to its inverse. *)
Lemma subrelation_symmetric R `(Symmetric R) : subrelation (flip R) R.
Proof. hnf. intros x y H'. red in H'. apply symmetry. assumption. Qed.
Section flip.
Lemma flip_Reflexive `{Reflexive R} : Reflexive (flip R).
Proof. tauto. Qed.
Program Definition flip_Irreflexive `(Irreflexive R) : Irreflexive (flip R) :=
irreflexivity (R:=R).
Program Definition flip_Symmetric `(Symmetric R) : Symmetric (flip R) :=
fun x y H => symmetry (R:=R) H.
Program Definition flip_Asymmetric `(Asymmetric R) : Asymmetric (flip R) :=
fun x y H H' => asymmetry (R:=R) H H'.
Program Definition flip_Transitive `(Transitive R) : Transitive (flip R) :=
fun x y z H H' => transitivity (R:=R) H' H.
Program Definition flip_Antisymmetric `(Antisymmetric eqA R) :
Antisymmetric eqA (flip R).
Proof. firstorder. Qed.
(** Inversing the larger structures *)
Lemma flip_PreOrder `(PreOrder R) : PreOrder (flip R).
Proof. firstorder. Qed.
Lemma flip_StrictOrder `(StrictOrder R) : StrictOrder (flip R).
Proof. firstorder. Qed.
Lemma flip_PER `(PER R) : PER (flip R).
Proof. firstorder. Qed.
Lemma flip_Equivalence `(Equivalence R) : Equivalence (flip R).
Proof. firstorder. Qed.
End flip.
Section complement.
Definition complement_Irreflexive `(Reflexive R)
: Irreflexive (complement R).
Proof. firstorder. Qed.
Definition complement_Symmetric `(Symmetric R) : Symmetric (complement R).
Proof. firstorder. Qed.
End complement.
(** Rewrite crelation on a given support: declares a crelation as a rewrite
crelation for use by the generalized rewriting tactic.
It helps choosing if a rewrite should be handled
by the generalized or the regular rewriting tactic using leibniz equality.
Users can declare an [RewriteRelation A RA] anywhere to declare default
crelations. This is also done automatically by the [Declare Relation A RA]
commands. *)
Class RewriteRelation (RA : crelation A).
(** Any [Equivalence] declared in the context is automatically considered
a rewrite crelation. *)
Global Instance equivalence_rewrite_crelation `(Equivalence eqA) : RewriteRelation eqA.
Defined.
(** Leibniz equality. *)
Section Leibniz.
Global Instance eq_Reflexive : Reflexive (@eq A) := @eq_refl A.
Global Instance eq_Symmetric : Symmetric (@eq A) := @eq_sym A.
Global Instance eq_Transitive : Transitive (@eq A) := @eq_trans A.
(** Leibinz equality [eq] is an equivalence crelation.
The instance has low priority as it is always applicable
if only the type is constrained. *)
Global Program Instance eq_equivalence : Equivalence (@eq A) | 10.
End Leibniz.
End Defs.
(** Default rewrite crelations handled by [setoid_rewrite]. *)
Instance: RewriteRelation impl.
Defined.
Instance: RewriteRelation iff.
Defined.
(** Hints to drive the typeclass resolution avoiding loops
due to the use of full unification. *)
#[global]
Hint Extern 1 (Reflexive (complement _)) => class_apply @irreflexivity : typeclass_instances.
#[global]
Hint Extern 3 (Symmetric (complement _)) => class_apply complement_Symmetric : typeclass_instances.
#[global]
Hint Extern 3 (Irreflexive (complement _)) => class_apply complement_Irreflexive : typeclass_instances.
#[global]
Hint Extern 3 (Reflexive (flip _)) => apply flip_Reflexive : typeclass_instances.
#[global]
Hint Extern 3 (Irreflexive (flip _)) => class_apply flip_Irreflexive : typeclass_instances.
#[global]
Hint Extern 3 (Symmetric (flip _)) => class_apply flip_Symmetric : typeclass_instances.
#[global]
Hint Extern 3 (Asymmetric (flip _)) => class_apply flip_Asymmetric : typeclass_instances.
#[global]
Hint Extern 3 (Antisymmetric (flip _)) => class_apply flip_Antisymmetric : typeclass_instances.
#[global]
Hint Extern 3 (Transitive (flip _)) => class_apply flip_Transitive : typeclass_instances.
#[global]
Hint Extern 3 (StrictOrder (flip _)) => class_apply flip_StrictOrder : typeclass_instances.
#[global]
Hint Extern 3 (PreOrder (flip _)) => class_apply flip_PreOrder : typeclass_instances.
#[global]
Hint Extern 4 (subrelation (flip _) _) =>
class_apply @subrelation_symmetric : typeclass_instances.
#[global]
Hint Resolve irreflexivity : ord.
Unset Implicit Arguments.
Ltac solve_crelation :=
match goal with
| [ |- ?R ?x ?x ] => reflexivity
| [ H : ?R ?x ?y |- ?R ?y ?x ] => symmetry ; exact H
end.
#[global]
Hint Extern 4 => solve_crelation : crelations.
(** We can already dualize all these properties. *)
(** * Standard instances. *)
Ltac reduce_hyp H :=
match type of H with
| context [ _ <-> _ ] => fail 1
| _ => red in H ; try reduce_hyp H
end.
Ltac reduce_goal :=
match goal with
| [ |- _ <-> _ ] => fail 1
| _ => red ; intros ; try reduce_goal
end.
Tactic Notation "reduce" "in" hyp(Hid) := reduce_hyp Hid.
Ltac reduce := reduce_goal.
Tactic Notation "apply" "*" constr(t) :=
first [ refine t | refine (t _) | refine (t _ _) | refine (t _ _ _) | refine (t _ _ _ _) |
refine (t _ _ _ _ _) | refine (t _ _ _ _ _ _) | refine (t _ _ _ _ _ _ _) ].
Ltac simpl_crelation :=
unfold flip, impl, arrow ; try reduce ; program_simpl ;
try ( solve [ dintuition ]).
Local Obligation Tactic := simpl_crelation.
(** Logical implication. *)
Program Instance impl_Reflexive : Reflexive impl.
Program Instance impl_Transitive : Transitive impl.
(** Logical equivalence. *)
Instance iff_Reflexive : Reflexive iff := iff_refl.
Instance iff_Symmetric : Symmetric iff := iff_sym.
Instance iff_Transitive : Transitive iff := iff_trans.
(** Logical equivalence [iff] is an equivalence crelation. *)
Program Instance iff_equivalence : Equivalence iff.
Program Instance arrow_Reflexive : Reflexive arrow.
Program Instance arrow_Transitive : Transitive arrow.
Instance iffT_Reflexive : Reflexive iffT.
Proof. firstorder. Defined.
Instance iffT_Symmetric : Symmetric iffT.
Proof. firstorder. Defined.
Instance iffT_Transitive : Transitive iffT.
Proof. firstorder. Defined.
(** We now develop a generalization of results on crelations for arbitrary predicates.
The resulting theory can be applied to homogeneous binary crelations but also to
arbitrary n-ary predicates. *)
Local Open Scope list_scope.
(** A compact representation of non-dependent arities, with the codomain singled-out. *)
(** We define the various operations which define the algebra on binary crelations *)
Section Binary.
Context {A : Type}.
Definition relation_equivalence : crelation (crelation A) :=
fun R R' => forall x y, iffT (R x y) (R' x y).
Global Instance: RewriteRelation relation_equivalence.
Defined.
Definition relation_conjunction (R : crelation A) (R' : crelation A) : crelation A :=
fun x y => prod (R x y) (R' x y).
Definition relation_disjunction (R : crelation A) (R' : crelation A) : crelation A :=
fun x y => sum (R x y) (R' x y).
(** Relation equivalence is an equivalence, and subrelation defines a partial order. *)
Global Instance relation_equivalence_equivalence :
Equivalence relation_equivalence.
Proof.
split; red; unfold relation_equivalence, iffT.
- firstorder.
- firstorder.
- intros x y z X X0 x0 y0. specialize (X x0 y0). specialize (X0 x0 y0). firstorder.
Qed.
Global Instance relation_implication_preorder : PreOrder (@subrelation A).
Proof. firstorder. Qed.
(** *** Partial Order.
A partial order is a preorder which is additionally antisymmetric.
We give an equivalent definition, up-to an equivalence crelation
on the carrier. *)
Class PartialOrder eqA `{equ : Equivalence A eqA} R `{preo : PreOrder A R} :=
partial_order_equivalence : relation_equivalence eqA (relation_conjunction R (flip R)).
(** The equivalence proof is sufficient for proving that [R] must be a
morphism for equivalence (see Morphisms). It is also sufficient to
show that [R] is antisymmetric w.r.t. [eqA] *)
Global Instance partial_order_antisym `(PartialOrder eqA R) : Antisymmetric eqA R.
Proof with auto.
reduce_goal.
apply H. firstorder.
Qed.
Lemma PartialOrder_inverse `(PartialOrder eqA R) : PartialOrder eqA (flip R).
Proof.
unfold flip; constructor; unfold flip.
- intros X. apply H. apply symmetry. apply X.
- unfold relation_conjunction. intros [H1 H2]. apply H. constructor; assumption.
Qed.
End Binary.
#[global]
Hint Extern 3 (PartialOrder (flip _)) => class_apply PartialOrder_inverse : typeclass_instances.
(** The partial order defined by subrelation and crelation equivalence. *)
(* Program Instance subrelation_partial_order : *)
(* ! PartialOrder (crelation A) relation_equivalence subrelation. *)
(* Obligation Tactic := idtac. *)
(* Next Obligation. *)
(* Proof. *)
(* intros x. refine (fun x => x). *)
(* Qed. *)
Typeclasses Opaque relation_equivalence.
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
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// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
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// special, incidental, or consequential loss or damage
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// regulations governing limitations on product liability.
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 15
(* X_CORE_INFO = "axi_crossbar_v2_1_15_axi_crossbar,Vivado 2017.3" *)
(* CHECK_LICENSE_TYPE = "DemoInterconnect_xbar_0,axi_crossbar_v2_1_15_axi_crossbar,{}" *)
(* CORE_GENERATION_INFO = "DemoInterconnect_xbar_0,axi_crossbar_v2_1_15_axi_crossbar,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_crossbar,x_ipVersion=2.1,x_ipCoreRevision=15,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_NUM_SLAVE_SLOTS=3,C_NUM_MASTER_SLOTS=7,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_PROTOCOL=2,C_NUM_ADDR_RANGES=1,C_M_AXI_BASE_ADDR=0x0000000000300000000000000020000000000000001000000000000000030000000000000002000000000000000100000000000000000\
000,C_M_AXI_ADDR_WIDTH=0x0000001000000010000000100000000c0000000c0000000c0000000c,C_S_AXI_BASE_ID=0x000000020000000100000000,C_S_AXI_THREAD_ID_WIDTH=0x000000000000000000000000,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_M_AXI_WRITE_CONNECTIVITY=0x00000007000000070000000700000007000000070000000700000007,C_M_AXI_READ_CONNECTIVITY=0x00000007000000070000000700000007000000070000000700000007,C_R_REGISTER=1,C_S_AX\
I_SINGLE_THREAD=0x000000010000000100000001,C_S_AXI_WRITE_ACCEPTANCE=0x000000010000000100000001,C_S_AXI_READ_ACCEPTANCE=0x000000010000000100000001,C_M_AXI_WRITE_ISSUING=0x00000001000000010000000100000001000000010000000100000001,C_M_AXI_READ_ISSUING=0x00000001000000010000000100000001000000010000000100000001,C_S_AXI_ARB_PRIORITY=0x000000000000000000000000,C_M_AXI_SECURE=0x00000000000000000000000000000000000000000000000000000000,C_CONNECTIVITY_MODE=0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module DemoInterconnect_xbar_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET ARESETN" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 S02_AXI AWADDR [31:0] [95:64]" *)
input wire [95 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 S02_AXI AWPROT [2:0] [8:6]" *)
input wire [8 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI AWVALID [0:0] [2:2]" *)
input wire [2 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI AWREADY [0:0] [2:2]" *)
output wire [2 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 S02_AXI WDATA [31:0] [95:64]" *)
input wire [95 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 S02_AXI WSTRB [3:0] [11:8]" *)
input wire [11 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI WVALID [0:0] [2:2]" *)
input wire [2 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI WREADY [0:0] [2:2]" *)
output wire [2 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 S02_AXI BRESP [1:0] [5:4]" *)
output wire [5 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI BVALID [0:0] [2:2]" *)
output wire [2 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI BREADY [0:0] [2:2]" *)
input wire [2 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 S02_AXI ARADDR [31:0] [95:64]" *)
input wire [95 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 S02_AXI ARPROT [2:0] [8:6]" *)
input wire [8 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI ARVALID [0:0] [2:2]" *)
input wire [2 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI ARREADY [0:0] [2:2]" *)
output wire [2 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 S02_AXI RDATA [31:0] [95:64]" *)
output wire [95 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 S02_AXI RRESP [1:0] [5:4]" *)
output wire [5 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI RVALID [0:0] [2:2]" *)
output wire [2 : 0] s_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME S01_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME S02_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI RREADY [0:0] [2:2]" *)
input wire [2 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI AWADDR [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI AWADDR [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI AWADDR [31:0] [223:192]" *)
output wire [223 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI AWPROT [2:0] [14:12], xilinx.com:interface:aximm:1.0 M05_AXI AWPROT [2:0] [17:15], xilinx.com:interface:aximm:1.0 M06_AXI AWPROT [2:0] [20:18]" *)
output wire [20 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI AWVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI AWVALID [0:0] [6:6]" *)
output wire [6 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI AWREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI AWREADY [0:0] [6:6]" *)
input wire [6 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI WDATA [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI WDATA [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI WDATA [31:0] [223:192]" *)
output wire [223 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [3:0] [15:12], xilinx.com:interface:aximm:1.0 M04_AXI WSTRB [3:0] [19:16], xilinx.com:interface:aximm:1.0 M05_AXI WSTRB [3:0] [23:20], xilinx.com:interface:aximm:1.0 M06_AXI WSTRB [3:0] [27:24]" *)
output wire [27 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI WVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI WVALID [0:0] [6:6]" *)
output wire [6 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI WREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI WREADY [0:0] [6:6]" *)
input wire [6 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI BRESP [1:0] [9:8], xilinx.com:interface:aximm:1.0 M05_AXI BRESP [1:0] [11:10], xilinx.com:interface:aximm:1.0 M06_AXI BRESP [1:0] [13:12]" *)
input wire [13 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI BVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI BVALID [0:0] [6:6]" *)
input wire [6 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI BREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI BREADY [0:0] [6:6]" *)
output wire [6 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI ARADDR [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI ARADDR [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI ARADDR [31:0] [223:192]" *)
output wire [223 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI ARPROT [2:0] [14:12], xilinx.com:interface:aximm:1.0 M05_AXI ARPROT [2:0] [17:15], xilinx.com:interface:aximm:1.0 M06_AXI ARPROT [2:0] [20:18]" *)
output wire [20 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI ARVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI ARVALID [0:0] [6:6]" *)
output wire [6 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI ARREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI ARREADY [0:0] [6:6]" *)
input wire [6 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI RDATA [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI RDATA [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI RDATA [31:0] [223:192]" *)
input wire [223 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI RRESP [1:0] [9:8], xilinx.com:interface:aximm:1.0 M05_AXI RRESP [1:0] [11:10], xilinx.com:interface:aximm:1.0 M06_AXI RRESP [1:0] [13:12]" *)
input wire [13 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI RVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI RVALID [0:0] [6:6]" *)
input wire [6 : 0] m_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M02_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M03_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M04_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M05_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M06_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI RREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI RREADY [0:0] [6:6]" *)
output wire [6 : 0] m_axi_rready;
axi_crossbar_v2_1_15_axi_crossbar #(
.C_FAMILY("artix7"),
.C_NUM_SLAVE_SLOTS(3),
.C_NUM_MASTER_SLOTS(7),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_PROTOCOL(2),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(448'H0000000000300000000000000020000000000000001000000000000000030000000000000002000000000000000100000000000000000000),
.C_M_AXI_ADDR_WIDTH(224'H0000001000000010000000100000000c0000000c0000000c0000000c),
.C_S_AXI_BASE_ID(96'H000000020000000100000000),
.C_S_AXI_THREAD_ID_WIDTH(96'H000000000000000000000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(224'H00000007000000070000000700000007000000070000000700000007),
.C_M_AXI_READ_CONNECTIVITY(224'H00000007000000070000000700000007000000070000000700000007),
.C_R_REGISTER(1),
.C_S_AXI_SINGLE_THREAD(96'H000000010000000100000001),
.C_S_AXI_WRITE_ACCEPTANCE(96'H000000010000000100000001),
.C_S_AXI_READ_ACCEPTANCE(96'H000000010000000100000001),
.C_M_AXI_WRITE_ISSUING(224'H00000001000000010000000100000001000000010000000100000001),
.C_M_AXI_READ_ISSUING(224'H00000001000000010000000100000001000000010000000100000001),
.C_S_AXI_ARB_PRIORITY(96'H000000000000000000000000),
.C_M_AXI_SECURE(224'H00000000000000000000000000000000000000000000000000000000),
.C_CONNECTIVITY_MODE(0)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(3'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(24'H000000),
.s_axi_awsize(9'H000),
.s_axi_awburst(6'H00),
.s_axi_awlock(3'H0),
.s_axi_awcache(12'H000),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(12'H000),
.s_axi_awuser(3'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(3'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(3'H7),
.s_axi_wuser(3'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(3'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(24'H000000),
.s_axi_arsize(9'H000),
.s_axi_arburst(6'H00),
.s_axi_arlock(3'H0),
.s_axi_arcache(12'H000),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(12'H000),
.s_axi_aruser(3'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(7'H00),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(7'H00),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(7'H00),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(7'H7F),
.m_axi_ruser(7'H00),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/*
Copyright 2010 David Fritz, Brian Gordon, Wira Mulia
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module mod_X(rst, clk, ie, de, iaddr, daddr, drw, din, iout, dout);
input rst;
input clk;
input ie,de;
input [31:0] iaddr, daddr;
input [1:0] drw;
input [31:0] din;
output [31:0] iout, dout;
wire [31:0] idata, ddata;
assign iout = idata;
assign dout = ddata;
/* all data bus activity is negative edge triggered */
always @(negedge clk) begin
if (drw[0] && de && !rst) begin
/* write cycle */
end else if (rst) begin
/* idle / read cycle */
end
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.92
// \ \ Application: MIG
// / / Filename: iodelay_ctrl.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:00 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// This module instantiates the IDELAYCTRL primitive, which continously
// calibrates the IODELAY elements in the region to account for varying
// environmental conditions. A 200MHz or 300MHz reference clock (depending
// on the desired IODELAY tap resolution) must be supplied
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: iodelay_ctrl.v,v 1.1 2011/06/02 07:18:00 mishra Exp $
**$Date: 2011/06/02 07:18:00 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/verilog/rtl/ip_top/iodelay_ctrl.v,v $
******************************************************************************/
`timescale 1ps/1ps
module iodelay_ctrl #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter IODELAY_GRP = "IODELAY_MIG", // May be assigned unique name when
// multiple IP cores used in design
parameter INPUT_CLK_TYPE = "DIFFERENTIAL", // input clock type
// "DIFFERENTIAL","SINGLE_ENDED"
parameter RST_ACT_LOW = 1 // Reset input polarity
// (0 = active high, 1 = active low)
)
(
input clk_ref_p,
input clk_ref_n,
input clk_ref,
input sys_rst,
output iodelay_ctrl_rdy
);
// # of clock cycles to delay deassertion of reset. Needs to be a fairly
// high number not so much for metastability protection, but to give time
// for reset (i.e. stable clock cycles) to propagate through all state
// machines and to all control signals (i.e. not all control signals have
// resets, instead they rely on base state logic being reset, and the effect
// of that reset propagating through the logic). Need this because we may not
// be getting stable clock cycles while reset asserted (i.e. since reset
// depends on DCM lock status)
// COMMENTED, RC, 01/13/09 - causes pack error in MAP w/ larger #
localparam RST_SYNC_NUM = 15;
// localparam RST_SYNC_NUM = 25;
wire clk_ref_bufg;
wire clk_ref_ibufg;
wire rst_ref;
reg [RST_SYNC_NUM-1:0] rst_ref_sync_r /* synthesis syn_maxfan = 10 */;
wire rst_tmp_idelay;
wire sys_rst_act_hi;
//***************************************************************************
// Possible inversion of system reset as appropriate
assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst: sys_rst;
//***************************************************************************
// Input buffer for IDELAYCTRL reference clock - handle either a
// differential or single-ended input
//***************************************************************************
generate
if (INPUT_CLK_TYPE == "DIFFERENTIAL") begin: diff_clk_ref
IBUFGDS #
(
.DIFF_TERM ("TRUE"),
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_clk_ref
(
.I (clk_ref_p),
.IB (clk_ref_n),
.O (clk_ref_ibufg)
);
end else if (INPUT_CLK_TYPE == "SINGLE_ENDED") begin : se_clk_ref
IBUFG #
(
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_clk_ref
(
.I (clk_ref),
.O (clk_ref_ibufg)
);
end
endgenerate
//***************************************************************************
// Global clock buffer for IDELAY reference clock
//***************************************************************************
BUFG u_bufg_clk_ref
(
.O (clk_ref_bufg),
.I (clk_ref_ibufg)
);
//*****************************************************************
// IDELAYCTRL reset
// This assumes an external clock signal driving the IDELAYCTRL
// blocks. Otherwise, if a PLL drives IDELAYCTRL, then the PLL
// lock signal will need to be incorporated in this.
//*****************************************************************
// Add PLL lock if PLL drives IDELAYCTRL in user design
assign rst_tmp_idelay = sys_rst_act_hi;
always @(posedge clk_ref_bufg or posedge rst_tmp_idelay)
if (rst_tmp_idelay)
rst_ref_sync_r <= #TCQ {RST_SYNC_NUM{1'b1}};
else
rst_ref_sync_r <= #TCQ rst_ref_sync_r << 1;
assign rst_ref = rst_ref_sync_r[RST_SYNC_NUM-1];
//*****************************************************************
(* IODELAY_GROUP = IODELAY_GRP *) IDELAYCTRL u_idelayctrl
(
.RDY (iodelay_ctrl_rdy),
.REFCLK (clk_ref_bufg),
.RST (rst_ref)
);
endmodule
|
//////////////////////////////////////////////////////////////////////////////
//
// Main
//
//////////////////////////////////////////////////////////////////////////////
module test();
integer count;
bit test_clk;
// Create a test clock
always #01.8 test_clk = ~test_clk;
//**********************************************************************
// Testing.
// Shift a moving set of ones up the input vector. At each shift
// the outputs should change, which is checked by the assertions
// below. This test doesnt care which output changes, as that was
// checked to be accurate by formal means.
//**********************************************************************
initial begin
count=0;
end
always @(posedge test_clk) begin
count++;
end
//**********************************************************************
// SV assertions
//**********************************************************************
property p_lane_output_change_on_input_change;
@(negedge test_clk)
disable iff (ana_byp == 0)
!$stable(lane_inputs) |-> !$stable(lane_outputs);
endproperty
a_lane_output_change_on_input_change: assert property (p_lane_output_change_on_input_change)
else begin
$error("ERROR! Analog Bypass: Input change not observed on the outputs: %h (lane)",
lane_inputs);
end // UNMATCHED !!
endproperty //FIXME
property p_sup_output_change_on_input_change;
@(negedge test_clk)
disable iff (ana_byp == 0)
!$stable(sup_inputs) |-> !$stable(sup_outputs);
endproperty
a_sup_output_change_on_input_change: assert property (p_sup_output_change_on_input_change)
else begin
$error("ERROR! Analog Bypass: Input change not observed on the outputs: %h (sup)",
sup_inputs);
end
endproperty
endmodule // test
|
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_modf_s5 (
enable,
clock,
dataa,
datab,
result);
input enable;
input clock;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
fp_modf_s5 inst (
.en (enable),
.areset(1'b0),
.clk(clock),
.a(dataa),
.b(datab),
.q(sub_wire0));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAPVGND_BEHAVIORAL_V
`define SKY130_FD_SC_LP__TAPVGND_BEHAVIORAL_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection 1
* row down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__tapvgnd ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAPVGND_BEHAVIORAL_V |
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: completer_pkt_gen
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: Completer Packet Generator module. This block creates the header
// info for completer packets- it also passes along the data source and
// address info for the TRN state machine block to request the data from
// the egress data presenter.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module completer_pkt_gen(
input clk,
input rst,
//interface from RX Engine
input [6:0] bar_hit, //denotes which base address was hit
input comp_req, //gets asserted when the rx engine recevies a MemRd request
input [31:0] MEM_addr, //needed to fetch data from egress_data_presenter
input [15:0] MEM_req_id,//needed for completion header
input [15:0] comp_id, //needed for completion header
input [7:0] MEM_tag, //neede for completion header
//interface to completion header fifo
output reg comp_fifo_wren,
output reg [63:0] comp_fifo_data
);
//State machine states
localparam IDLE = 4'h0;
localparam HEAD1 = 4'h1;
localparam HEAD2 = 4'h2;
//parameters used to define fixed header fields
localparam rsvd = 1'b0;
localparam fmt = 2'b10; //always with data
localparam CplD = 5'b01010; //completer
localparam TC = 3'b000;
localparam TD = 1'b0;
localparam EP = 1'b0;
localparam ATTR = 2'b00;
localparam Length = 10'b0000000001; //length is always one DWORD
localparam ByteCount = 12'b000000000100; //BC is always one DWORD
localparam BCM = 1'b0;
reg [3:0] state;
reg [6:0] bar_hit_reg;
reg [26:0] MEM_addr_reg;
reg [15:0] MEM_req_id_reg;
reg [15:0] comp_id_reg;
reg [7:0] MEM_tag_reg;
reg rst_reg;
always@(posedge clk) rst_reg <= rst;
//if there is a memory read request then latch the header information
//needed to create the completion TLP header
always@(posedge clk)begin
if(comp_req)begin
bar_hit_reg <= bar_hit;
MEM_addr_reg[26:0] <= MEM_addr[26:0];
MEM_req_id_reg <= MEM_req_id;
comp_id_reg <= comp_id;
MEM_tag_reg <= MEM_tag;
end
end
// State machine
// Builds headers for completion TLP headers
// Writes them into a FIFO
always @ (posedge clk) begin
if (rst_reg) begin
comp_fifo_data <= 0;
comp_fifo_wren <= 1'b0;
state <= IDLE;
end else begin
case (state)
IDLE : begin
comp_fifo_data <= 0;
comp_fifo_wren <= 1'b0;
if(comp_req)
state<= HEAD1;
else
state<= IDLE;
end
HEAD1 : begin //create first 64-bit completion TLP header
//NOTE: bar_hit_reg[6:0],MEM_addr_reg[26:2] are not part of completion TLP
//header but are used by tx_trn_sm module to fetch data from the
//egress_data_presenter
comp_fifo_data <= {bar_hit_reg[6:0],MEM_addr_reg[26:2],
rsvd,fmt,CplD,rsvd,TC,rsvd,rsvd,rsvd,rsvd,
TD,EP,ATTR,rsvd,rsvd,Length};
comp_fifo_wren <= 1'b1; //write to comp header fifo
state <= HEAD2;
end
HEAD2 : begin //create second 64-bit completion TLP header
comp_fifo_data <= {comp_id_reg[15:0],3'b000, BCM,ByteCount,
MEM_req_id_reg[15:0],MEM_tag_reg[7:0],rsvd,
MEM_addr_reg[6:0]};
comp_fifo_wren <= 1'b1; //write to comp header fifo
state <= IDLE;
end
default : begin
comp_fifo_data <= 0;
comp_fifo_wren <= 1'b0;
state <= IDLE;
end
endcase
end
end
endmodule
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2015 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** * Int31 numbers defines indeed a cyclic structure : Z/(2^31)Z *)
(**
Author: Arnaud Spiwack (+ Pierre Letouzey)
*)
Require Import List.
Require Import Min.
Require Export Int31.
Require Import Znumtheory.
Require Import Zgcd_alt.
Require Import Zpow_facts.
Require Import BigNumPrelude.
Require Import CyclicAxioms.
Require Import ROmega.
Local Open Scope nat_scope.
Local Open Scope int31_scope.
Section Basics.
(** * Basic results about [iszero], [shiftl], [shiftr] *)
Lemma iszero_eq0 : forall x, iszero x = true -> x=0.
Proof.
destruct x; simpl; intros.
repeat
match goal with H:(if ?d then _ else _) = true |- _ =>
destruct d; try discriminate
end.
reflexivity.
Qed.
Lemma iszero_not_eq0 : forall x, iszero x = false -> x<>0.
Proof.
intros x H Eq; rewrite Eq in H; simpl in *; discriminate.
Qed.
Lemma sneakl_shiftr : forall x,
x = sneakl (firstr x) (shiftr x).
Proof.
destruct x; simpl; auto.
Qed.
Lemma sneakr_shiftl : forall x,
x = sneakr (firstl x) (shiftl x).
Proof.
destruct x; simpl; auto.
Qed.
Lemma twice_zero : forall x,
twice x = 0 <-> twice_plus_one x = 1.
Proof.
destruct x; simpl in *; split;
intro H; injection H; intros; subst; auto.
Qed.
Lemma twice_or_twice_plus_one : forall x,
x = twice (shiftr x) \/ x = twice_plus_one (shiftr x).
Proof.
intros; case_eq (firstr x); intros.
destruct x; simpl in *; rewrite H; auto.
destruct x; simpl in *; rewrite H; auto.
Qed.
(** * Iterated shift to the right *)
Definition nshiftr x := nat_rect _ x (fun _ => shiftr).
Lemma nshiftr_S :
forall n x, nshiftr x (S n) = shiftr (nshiftr x n).
Proof.
reflexivity.
Qed.
Lemma nshiftr_S_tail :
forall n x, nshiftr x (S n) = nshiftr (shiftr x) n.
Proof.
intros n; elim n; simpl; auto.
intros; now f_equal.
Qed.
Lemma nshiftr_n_0 : forall n, nshiftr 0 n = 0.
Proof.
induction n; simpl; auto.
rewrite IHn; auto.
Qed.
Lemma nshiftr_size : forall x, nshiftr x size = 0.
Proof.
destruct x; simpl; auto.
Qed.
Lemma nshiftr_above_size : forall k x, size<=k ->
nshiftr x k = 0.
Proof.
intros.
replace k with ((k-size)+size)%nat by omega.
induction (k-size)%nat; auto.
rewrite nshiftr_size; auto.
simpl; rewrite IHn; auto.
Qed.
(** * Iterated shift to the left *)
Definition nshiftl x := nat_rect _ x (fun _ => shiftl).
Lemma nshiftl_S :
forall n x, nshiftl x (S n) = shiftl (nshiftl x n).
Proof.
reflexivity.
Qed.
Lemma nshiftl_S_tail :
forall n x, nshiftl x (S n) = nshiftl (shiftl x) n.
Proof.
intros n; elim n; simpl; intros; now f_equal.
Qed.
Lemma nshiftl_n_0 : forall n, nshiftl 0 n = 0.
Proof.
induction n; simpl; auto.
rewrite IHn; auto.
Qed.
Lemma nshiftl_size : forall x, nshiftl x size = 0.
Proof.
destruct x; simpl; auto.
Qed.
Lemma nshiftl_above_size : forall k x, size<=k ->
nshiftl x k = 0.
Proof.
intros.
replace k with ((k-size)+size)%nat by omega.
induction (k-size)%nat; auto.
rewrite nshiftl_size; auto.
simpl; rewrite IHn; auto.
Qed.
Lemma firstr_firstl :
forall x, firstr x = firstl (nshiftl x (pred size)).
Proof.
destruct x; simpl; auto.
Qed.
Lemma firstl_firstr :
forall x, firstl x = firstr (nshiftr x (pred size)).
Proof.
destruct x; simpl; auto.
Qed.
(** More advanced results about [nshiftr] *)
Lemma nshiftr_predsize_0_firstl : forall x,
nshiftr x (pred size) = 0 -> firstl x = D0.
Proof.
destruct x; compute; intros H; injection H; intros; subst; auto.
Qed.
Lemma nshiftr_0_propagates : forall n p x, n <= p ->
nshiftr x n = 0 -> nshiftr x p = 0.
Proof.
intros.
replace p with ((p-n)+n)%nat by omega.
induction (p-n)%nat.
simpl; auto.
simpl; rewrite IHn0; auto.
Qed.
Lemma nshiftr_0_firstl : forall n x, n < size ->
nshiftr x n = 0 -> firstl x = D0.
Proof.
intros.
apply nshiftr_predsize_0_firstl.
apply nshiftr_0_propagates with n; auto; omega.
Qed.
(** * Some induction principles over [int31] *)
(** Not used for the moment. Are they really useful ? *)
Lemma int31_ind_sneakl : forall P : int31->Prop,
P 0 ->
(forall x d, P x -> P (sneakl d x)) ->
forall x, P x.
Proof.
intros.
assert (forall n, n<=size -> P (nshiftr x (size - n))).
induction n; intros.
rewrite nshiftr_size; auto.
rewrite sneakl_shiftr.
apply H0.
change (P (nshiftr x (S (size - S n)))).
replace (S (size - S n))%nat with (size - n)%nat by omega.
apply IHn; omega.
change x with (nshiftr x (size-size)); auto.
Qed.
Lemma int31_ind_twice : forall P : int31->Prop,
P 0 ->
(forall x, P x -> P (twice x)) ->
(forall x, P x -> P (twice_plus_one x)) ->
forall x, P x.
Proof.
induction x using int31_ind_sneakl; auto.
destruct d; auto.
Qed.
(** * Some generic results about [recr] *)
Section Recr.
(** [recr] satisfies the fixpoint equation used for its definition. *)
Variable (A:Type)(case0:A)(caserec:digits->int31->A->A).
Lemma recr_aux_eqn : forall n x, iszero x = false ->
recr_aux (S n) A case0 caserec x =
caserec (firstr x) (shiftr x) (recr_aux n A case0 caserec (shiftr x)).
Proof.
intros; simpl; rewrite H; auto.
Qed.
Lemma recr_aux_converges :
forall n p x, n <= size -> n <= p ->
recr_aux n A case0 caserec (nshiftr x (size - n)) =
recr_aux p A case0 caserec (nshiftr x (size - n)).
Proof.
induction n.
simpl minus; intros.
rewrite nshiftr_size; destruct p; simpl; auto.
intros.
destruct p.
inversion H0.
unfold recr_aux; fold recr_aux.
destruct (iszero (nshiftr x (size - S n))); auto.
f_equal.
change (shiftr (nshiftr x (size - S n))) with (nshiftr x (S (size - S n))).
replace (S (size - S n))%nat with (size - n)%nat by omega.
apply IHn; auto with arith.
Qed.
Lemma recr_eqn : forall x, iszero x = false ->
recr A case0 caserec x =
caserec (firstr x) (shiftr x) (recr A case0 caserec (shiftr x)).
Proof.
intros.
unfold recr.
change x with (nshiftr x (size - size)).
rewrite (recr_aux_converges size (S size)); auto with arith.
rewrite recr_aux_eqn; auto.
Qed.
(** [recr] is usually equivalent to a variant [recrbis]
written without [iszero] check. *)
Fixpoint recrbis_aux (n:nat)(A:Type)(case0:A)(caserec:digits->int31->A->A)
(i:int31) : A :=
match n with
| O => case0
| S next =>
let si := shiftr i in
caserec (firstr i) si (recrbis_aux next A case0 caserec si)
end.
Definition recrbis := recrbis_aux size.
Hypothesis case0_caserec : caserec D0 0 case0 = case0.
Lemma recrbis_aux_equiv : forall n x,
recrbis_aux n A case0 caserec x = recr_aux n A case0 caserec x.
Proof.
induction n; simpl; auto; intros.
case_eq (iszero x); intros; [ | f_equal; auto ].
rewrite (iszero_eq0 _ H); simpl; auto.
replace (recrbis_aux n A case0 caserec 0) with case0; auto.
clear H IHn; induction n; simpl; congruence.
Qed.
Lemma recrbis_equiv : forall x,
recrbis A case0 caserec x = recr A case0 caserec x.
Proof.
intros; apply recrbis_aux_equiv; auto.
Qed.
End Recr.
(** * Incrementation *)
Section Incr.
(** Variant of [incr] via [recrbis] *)
Let Incr (b : digits) (si rec : int31) :=
match b with
| D0 => sneakl D1 si
| D1 => sneakl D0 rec
end.
Definition incrbis_aux n x := recrbis_aux n _ In Incr x.
Lemma incrbis_aux_equiv : forall x, incrbis_aux size x = incr x.
Proof.
unfold incr, recr, incrbis_aux; fold Incr; intros.
apply recrbis_aux_equiv; auto.
Qed.
(** Recursive equations satisfied by [incr] *)
Lemma incr_eqn1 :
forall x, firstr x = D0 -> incr x = twice_plus_one (shiftr x).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0); simpl; auto.
unfold incr; rewrite recr_eqn; fold incr; auto.
rewrite H; auto.
Qed.
Lemma incr_eqn2 :
forall x, firstr x = D1 -> incr x = twice (incr (shiftr x)).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0) in H; simpl in H; discriminate.
unfold incr; rewrite recr_eqn; fold incr; auto.
rewrite H; auto.
Qed.
Lemma incr_twice : forall x, incr (twice x) = twice_plus_one x.
Proof.
intros.
rewrite incr_eqn1; destruct x; simpl; auto.
Qed.
Lemma incr_twice_plus_one_firstl :
forall x, firstl x = D0 -> incr (twice_plus_one x) = twice (incr x).
Proof.
intros.
rewrite incr_eqn2; [ | destruct x; simpl; auto ].
f_equal; f_equal.
destruct x; simpl in *; rewrite H; auto.
Qed.
(** The previous result is actually true even without the
constraint on [firstl], but this is harder to prove
(see later). *)
End Incr.
(** * Conversion to [Z] : the [phi] function *)
Section Phi.
(** Variant of [phi] via [recrbis] *)
Let Phi := fun b (_:int31) =>
match b with D0 => Z.double | D1 => Z.succ_double end.
Definition phibis_aux n x := recrbis_aux n _ Z0 Phi x.
Lemma phibis_aux_equiv : forall x, phibis_aux size x = phi x.
Proof.
unfold phi, recr, phibis_aux; fold Phi; intros.
apply recrbis_aux_equiv; auto.
Qed.
(** Recursive equations satisfied by [phi] *)
Lemma phi_eqn1 : forall x, firstr x = D0 ->
phi x = Z.double (phi (shiftr x)).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0); simpl; auto.
intros; unfold phi; rewrite recr_eqn; fold phi; auto.
rewrite H; auto.
Qed.
Lemma phi_eqn2 : forall x, firstr x = D1 ->
phi x = Z.succ_double (phi (shiftr x)).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0) in H; simpl in H; discriminate.
intros; unfold phi; rewrite recr_eqn; fold phi; auto.
rewrite H; auto.
Qed.
Lemma phi_twice_firstl : forall x, firstl x = D0 ->
phi (twice x) = Z.double (phi x).
Proof.
intros.
rewrite phi_eqn1; auto; [ | destruct x; auto ].
f_equal; f_equal.
destruct x; simpl in *; rewrite H; auto.
Qed.
Lemma phi_twice_plus_one_firstl : forall x, firstl x = D0 ->
phi (twice_plus_one x) = Z.succ_double (phi x).
Proof.
intros.
rewrite phi_eqn2; auto; [ | destruct x; auto ].
f_equal; f_equal.
destruct x; simpl in *; rewrite H; auto.
Qed.
End Phi.
(** [phi x] is positive and lower than [2^31] *)
Lemma phibis_aux_pos : forall n x, (0 <= phibis_aux n x)%Z.
Proof.
induction n.
simpl; unfold phibis_aux; simpl; auto with zarith.
intros.
unfold phibis_aux, recrbis_aux; fold recrbis_aux;
fold (phibis_aux n (shiftr x)).
destruct (firstr x).
specialize IHn with (shiftr x); rewrite Z.double_spec; omega.
specialize IHn with (shiftr x); rewrite Z.succ_double_spec; omega.
Qed.
Lemma phibis_aux_bounded :
forall n x, n <= size ->
(phibis_aux n (nshiftr x (size-n)) < 2 ^ (Z.of_nat n))%Z.
Proof.
induction n.
simpl minus; unfold phibis_aux; simpl; auto with zarith.
intros.
unfold phibis_aux, recrbis_aux; fold recrbis_aux;
fold (phibis_aux n (shiftr (nshiftr x (size - S n)))).
assert (shiftr (nshiftr x (size - S n)) = nshiftr x (size-n)).
replace (size - n)%nat with (S (size - (S n))) by omega.
simpl; auto.
rewrite H0.
assert (H1 : n <= size) by omega.
specialize (IHn x H1).
set (y:=phibis_aux n (nshiftr x (size - n))) in *.
rewrite Nat2Z.inj_succ, Z.pow_succ_r; auto with zarith.
case_eq (firstr (nshiftr x (size - S n))); intros.
rewrite Z.double_spec; auto with zarith.
rewrite Z.succ_double_spec; auto with zarith.
Qed.
Lemma phi_bounded : forall x, (0 <= phi x < 2 ^ (Z.of_nat size))%Z.
Proof.
intros.
rewrite <- phibis_aux_equiv.
split.
apply phibis_aux_pos.
change x with (nshiftr x (size-size)).
apply phibis_aux_bounded; auto.
Qed.
Lemma phibis_aux_lowerbound :
forall n x, firstr (nshiftr x n) = D1 ->
(2 ^ Z.of_nat n <= phibis_aux (S n) x)%Z.
Proof.
induction n.
intros.
unfold nshiftr in H; simpl in *.
unfold phibis_aux, recrbis_aux.
rewrite H, Z.succ_double_spec; omega.
intros.
remember (S n) as m.
unfold phibis_aux, recrbis_aux; fold recrbis_aux;
fold (phibis_aux m (shiftr x)).
subst m.
rewrite Nat2Z.inj_succ, Z.pow_succ_r; auto with zarith.
assert (2^(Z.of_nat n) <= phibis_aux (S n) (shiftr x))%Z.
apply IHn.
rewrite <- nshiftr_S_tail; auto.
destruct (firstr x).
change (Z.double (phibis_aux (S n) (shiftr x))) with
(2*(phibis_aux (S n) (shiftr x)))%Z.
omega.
rewrite Z.succ_double_spec; omega.
Qed.
Lemma phi_lowerbound :
forall x, firstl x = D1 -> (2^(Z.of_nat (pred size)) <= phi x)%Z.
Proof.
intros.
generalize (phibis_aux_lowerbound (pred size) x).
rewrite <- firstl_firstr.
change (S (pred size)) with size; auto.
rewrite phibis_aux_equiv; auto.
Qed.
(** * Equivalence modulo [2^n] *)
Section EqShiftL.
(** After killing [n] bits at the left, are the numbers equal ?*)
Definition EqShiftL n x y :=
nshiftl x n = nshiftl y n.
Lemma EqShiftL_zero : forall x y, EqShiftL O x y <-> x = y.
Proof.
unfold EqShiftL; intros; unfold nshiftl; simpl; split; auto.
Qed.
Lemma EqShiftL_size : forall k x y, size<=k -> EqShiftL k x y.
Proof.
red; intros; rewrite 2 nshiftl_above_size; auto.
Qed.
Lemma EqShiftL_le : forall k k' x y, k <= k' ->
EqShiftL k x y -> EqShiftL k' x y.
Proof.
unfold EqShiftL; intros.
replace k' with ((k'-k)+k)%nat by omega.
remember (k'-k)%nat as n.
clear Heqn H k'.
induction n; simpl; auto.
f_equal; auto.
Qed.
Lemma EqShiftL_firstr : forall k x y, k < size ->
EqShiftL k x y -> firstr x = firstr y.
Proof.
intros.
rewrite 2 firstr_firstl.
f_equal.
apply EqShiftL_le with k; auto.
unfold size.
auto with arith.
Qed.
Lemma EqShiftL_twice : forall k x y,
EqShiftL k (twice x) (twice y) <-> EqShiftL (S k) x y.
Proof.
intros; unfold EqShiftL.
rewrite 2 nshiftl_S_tail; split; auto.
Qed.
(** * From int31 to list of digits. *)
(** Lower (=rightmost) bits comes first. *)
Definition i2l := recrbis _ nil (fun d _ rec => d::rec).
Lemma i2l_length : forall x, length (i2l x) = size.
Proof.
intros; reflexivity.
Qed.
Fixpoint lshiftl l x :=
match l with
| nil => x
| d::l => sneakl d (lshiftl l x)
end.
Definition l2i l := lshiftl l On.
Lemma l2i_i2l : forall x, l2i (i2l x) = x.
Proof.
destruct x; compute; auto.
Qed.
Lemma i2l_sneakr : forall x d,
i2l (sneakr d x) = tail (i2l x) ++ d::nil.
Proof.
destruct x; compute; auto.
Qed.
Lemma i2l_sneakl : forall x d,
i2l (sneakl d x) = d :: removelast (i2l x).
Proof.
destruct x; compute; auto.
Qed.
Lemma i2l_l2i : forall l, length l = size ->
i2l (l2i l) = l.
Proof.
repeat (destruct l as [ |? l]; [intros; discriminate | ]).
destruct l; [ | intros; discriminate].
intros _; compute; auto.
Qed.
Fixpoint cstlist (A:Type)(a:A) n :=
match n with
| O => nil
| S n => a::cstlist _ a n
end.
Lemma i2l_nshiftl : forall n x, n<=size ->
i2l (nshiftl x n) = cstlist _ D0 n ++ firstn (size-n) (i2l x).
Proof.
induction n.
intros.
assert (firstn (size-0) (i2l x) = i2l x).
rewrite <- minus_n_O, <- (i2l_length x).
induction (i2l x); simpl; f_equal; auto.
rewrite H0; clear H0.
reflexivity.
intros.
rewrite nshiftl_S.
unfold shiftl; rewrite i2l_sneakl.
simpl cstlist.
rewrite <- app_comm_cons; f_equal.
rewrite IHn; [ | omega].
rewrite removelast_app.
apply f_equal.
replace (size-n)%nat with (S (size - S n))%nat by omega.
rewrite removelast_firstn; auto.
rewrite i2l_length; omega.
generalize (firstn_length (size-n) (i2l x)).
rewrite i2l_length.
intros H0 H1. rewrite H1 in H0.
rewrite min_l in H0 by omega.
simpl length in H0.
omega.
Qed.
(** [i2l] can be used to define a relation equivalent to [EqShiftL] *)
Lemma EqShiftL_i2l : forall k x y,
EqShiftL k x y <-> firstn (size-k) (i2l x) = firstn (size-k) (i2l y).
Proof.
intros.
destruct (le_lt_dec size k) as [Hle|Hlt].
split; intros.
replace (size-k)%nat with O by omega.
unfold firstn; auto.
apply EqShiftL_size; auto.
unfold EqShiftL.
assert (k <= size) by omega.
split; intros.
assert (i2l (nshiftl x k) = i2l (nshiftl y k)) by (f_equal; auto).
rewrite 2 i2l_nshiftl in H1; auto.
eapply app_inv_head; eauto.
assert (i2l (nshiftl x k) = i2l (nshiftl y k)).
rewrite 2 i2l_nshiftl; auto.
f_equal; auto.
rewrite <- (l2i_i2l (nshiftl x k)), <- (l2i_i2l (nshiftl y k)).
f_equal; auto.
Qed.
(** This equivalence allows proving easily the following delicate
result *)
Lemma EqShiftL_twice_plus_one : forall k x y,
EqShiftL k (twice_plus_one x) (twice_plus_one y) <-> EqShiftL (S k) x y.
Proof.
intros.
destruct (le_lt_dec size k) as [Hle|Hlt].
split; intros; apply EqShiftL_size; auto.
rewrite 2 EqShiftL_i2l.
unfold twice_plus_one.
rewrite 2 i2l_sneakl.
replace (size-k)%nat with (S (size - S k))%nat by omega.
remember (size - S k)%nat as n.
remember (i2l x) as lx.
remember (i2l y) as ly.
simpl.
rewrite 2 firstn_removelast.
split; intros.
injection H; auto.
f_equal; auto.
subst ly n; rewrite i2l_length; omega.
subst lx n; rewrite i2l_length; omega.
Qed.
Lemma EqShiftL_shiftr : forall k x y, EqShiftL k x y ->
EqShiftL (S k) (shiftr x) (shiftr y).
Proof.
intros.
destruct (le_lt_dec size (S k)) as [Hle|Hlt].
apply EqShiftL_size; auto.
case_eq (firstr x); intros.
rewrite <- EqShiftL_twice.
unfold twice; rewrite <- H0.
rewrite <- sneakl_shiftr.
rewrite (EqShiftL_firstr k x y); auto.
rewrite <- sneakl_shiftr; auto.
omega.
rewrite <- EqShiftL_twice_plus_one.
unfold twice_plus_one; rewrite <- H0.
rewrite <- sneakl_shiftr.
rewrite (EqShiftL_firstr k x y); auto.
rewrite <- sneakl_shiftr; auto.
omega.
Qed.
Lemma EqShiftL_incrbis : forall n k x y, n<=size ->
(n+k=S size)%nat ->
EqShiftL k x y ->
EqShiftL k (incrbis_aux n x) (incrbis_aux n y).
Proof.
induction n; simpl; intros.
red; auto.
destruct (eq_nat_dec k size).
subst k; apply EqShiftL_size; auto.
unfold incrbis_aux; simpl;
fold (incrbis_aux n (shiftr x)); fold (incrbis_aux n (shiftr y)).
rewrite (EqShiftL_firstr k x y); auto; try omega.
case_eq (firstr y); intros.
rewrite EqShiftL_twice_plus_one.
apply EqShiftL_shiftr; auto.
rewrite EqShiftL_twice.
apply IHn; try omega.
apply EqShiftL_shiftr; auto.
Qed.
Lemma EqShiftL_incr : forall x y,
EqShiftL 1 x y -> EqShiftL 1 (incr x) (incr y).
Proof.
intros.
rewrite <- 2 incrbis_aux_equiv.
apply EqShiftL_incrbis; auto.
Qed.
End EqShiftL.
(** * More equations about [incr] *)
Lemma incr_twice_plus_one :
forall x, incr (twice_plus_one x) = twice (incr x).
Proof.
intros.
rewrite incr_eqn2; [ | destruct x; simpl; auto].
apply EqShiftL_incr.
red; destruct x; simpl; auto.
Qed.
Lemma incr_firstr : forall x, firstr (incr x) <> firstr x.
Proof.
intros.
case_eq (firstr x); intros.
rewrite incr_eqn1; auto.
destruct (shiftr x); simpl; discriminate.
rewrite incr_eqn2; auto.
destruct (incr (shiftr x)); simpl; discriminate.
Qed.
Lemma incr_inv : forall x y,
incr x = twice_plus_one y -> x = twice y.
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0) in *; simpl in *.
change (incr 0) with 1 in H.
symmetry; rewrite twice_zero; auto.
case_eq (firstr x); intros.
rewrite incr_eqn1 in H; auto.
clear H0; destruct x; destruct y; simpl in *.
injection H; intros; subst; auto.
elim (incr_firstr x).
rewrite H1, H; destruct y; simpl; auto.
Qed.
(** * Conversion from [Z] : the [phi_inv] function *)
(** First, recursive equations *)
Lemma phi_inv_double_plus_one : forall z,
phi_inv (Z.succ_double z) = twice_plus_one (phi_inv z).
Proof.
destruct z; simpl; auto.
induction p; simpl.
rewrite 2 incr_twice; auto.
rewrite incr_twice, incr_twice_plus_one.
f_equal.
apply incr_inv; auto.
auto.
Qed.
Lemma phi_inv_double : forall z,
phi_inv (Z.double z) = twice (phi_inv z).
Proof.
destruct z; simpl; auto.
rewrite incr_twice_plus_one; auto.
Qed.
Lemma phi_inv_incr : forall z,
phi_inv (Z.succ z) = incr (phi_inv z).
Proof.
destruct z.
simpl; auto.
simpl; auto.
induction p; simpl; auto.
rewrite <- Pos.add_1_r, IHp, incr_twice_plus_one; auto.
rewrite incr_twice; auto.
simpl; auto.
destruct p; simpl; auto.
rewrite incr_twice; auto.
f_equal.
rewrite incr_twice_plus_one; auto.
induction p; simpl; auto.
rewrite incr_twice; auto.
f_equal.
rewrite incr_twice_plus_one; auto.
Qed.
(** [phi_inv o inv], the always-exact and easy-to-prove trip :
from int31 to Z and then back to int31. *)
Lemma phi_inv_phi_aux :
forall n x, n <= size ->
phi_inv (phibis_aux n (nshiftr x (size-n))) =
nshiftr x (size-n).
Proof.
induction n.
intros; simpl minus.
rewrite nshiftr_size; auto.
intros.
unfold phibis_aux, recrbis_aux; fold recrbis_aux;
fold (phibis_aux n (shiftr (nshiftr x (size-S n)))).
assert (shiftr (nshiftr x (size - S n)) = nshiftr x (size-n)).
replace (size - n)%nat with (S (size - (S n))); auto; omega.
rewrite H0.
case_eq (firstr (nshiftr x (size - S n))); intros.
rewrite phi_inv_double.
rewrite IHn by omega.
rewrite <- H0.
remember (nshiftr x (size - S n)) as y.
destruct y; simpl in H1; rewrite H1; auto.
rewrite phi_inv_double_plus_one.
rewrite IHn by omega.
rewrite <- H0.
remember (nshiftr x (size - S n)) as y.
destruct y; simpl in H1; rewrite H1; auto.
Qed.
Lemma phi_inv_phi : forall x, phi_inv (phi x) = x.
Proof.
intros.
rewrite <- phibis_aux_equiv.
replace x with (nshiftr x (size - size)) by auto.
apply phi_inv_phi_aux; auto.
Qed.
(** The other composition [phi o phi_inv] is harder to prove correct.
In particular, an overflow can happen, so a modulo is needed.
For the moment, we proceed via several steps, the first one
being a detour to [positive_to_in31]. *)
(** * [positive_to_int31] *)
(** A variant of [p2i] with [twice] and [twice_plus_one] instead of
[2*i] and [2*i+1] *)
Fixpoint p2ibis n p : (N*int31)%type :=
match n with
| O => (Npos p, On)
| S n => match p with
| xO p => let (r,i) := p2ibis n p in (r, twice i)
| xI p => let (r,i) := p2ibis n p in (r, twice_plus_one i)
| xH => (N0, In)
end
end.
Lemma p2ibis_bounded : forall n p,
nshiftr (snd (p2ibis n p)) n = 0.
Proof.
induction n.
simpl; intros; auto.
simpl p2ibis; intros.
destruct p; simpl snd.
specialize IHn with p.
destruct (p2ibis n p). simpl @snd in *.
rewrite nshiftr_S_tail.
destruct (le_lt_dec size n) as [Hle|Hlt].
rewrite nshiftr_above_size; auto.
assert (H:=nshiftr_0_firstl _ _ Hlt IHn).
replace (shiftr (twice_plus_one i)) with i; auto.
destruct i; simpl in *. rewrite H; auto.
specialize IHn with p.
destruct (p2ibis n p); simpl @snd in *.
rewrite nshiftr_S_tail.
destruct (le_lt_dec size n) as [Hle|Hlt].
rewrite nshiftr_above_size; auto.
assert (H:=nshiftr_0_firstl _ _ Hlt IHn).
replace (shiftr (twice i)) with i; auto.
destruct i; simpl in *; rewrite H; auto.
rewrite nshiftr_S_tail; auto.
replace (shiftr In) with 0; auto.
apply nshiftr_n_0.
Qed.
Local Open Scope Z_scope.
Lemma p2ibis_spec : forall n p, (n<=size)%nat ->
Zpos p = (Z.of_N (fst (p2ibis n p)))*2^(Z.of_nat n) +
phi (snd (p2ibis n p)).
Proof.
induction n; intros.
simpl; rewrite Pos.mul_1_r; auto.
replace (2^(Z.of_nat (S n)))%Z with (2*2^(Z.of_nat n))%Z by
(rewrite <- Z.pow_succ_r, <- Zpos_P_of_succ_nat;
auto with zarith).
rewrite (Z.mul_comm 2).
assert (n<=size)%nat by omega.
destruct p; simpl; [ | | auto];
specialize (IHn p H0);
generalize (p2ibis_bounded n p);
destruct (p2ibis n p) as (r,i); simpl in *; intros.
change (Zpos p~1) with (2*Zpos p + 1)%Z.
rewrite phi_twice_plus_one_firstl, Z.succ_double_spec.
rewrite IHn; ring.
apply (nshiftr_0_firstl n); auto; try omega.
change (Zpos p~0) with (2*Zpos p)%Z.
rewrite phi_twice_firstl.
change (Z.double (phi i)) with (2*(phi i))%Z.
rewrite IHn; ring.
apply (nshiftr_0_firstl n); auto; try omega.
Qed.
(** We now prove that this [p2ibis] is related to [phi_inv_positive] *)
Lemma phi_inv_positive_p2ibis : forall n p, (n<=size)%nat ->
EqShiftL (size-n) (phi_inv_positive p) (snd (p2ibis n p)).
Proof.
induction n.
intros.
apply EqShiftL_size; auto.
intros.
simpl p2ibis; destruct p; [ | | red; auto];
specialize IHn with p;
destruct (p2ibis n p); simpl @snd in *; simpl phi_inv_positive;
rewrite ?EqShiftL_twice_plus_one, ?EqShiftL_twice;
replace (S (size - S n))%nat with (size - n)%nat by omega;
apply IHn; omega.
Qed.
(** This gives the expected result about [phi o phi_inv], at least
for the positive case. *)
Lemma phi_phi_inv_positive : forall p,
phi (phi_inv_positive p) = (Zpos p) mod (2^(Z.of_nat size)).
Proof.
intros.
replace (phi_inv_positive p) with (snd (p2ibis size p)).
rewrite (p2ibis_spec size p) by auto.
rewrite Z.add_comm, Z_mod_plus.
symmetry; apply Zmod_small.
apply phi_bounded.
auto with zarith.
symmetry.
rewrite <- EqShiftL_zero.
apply (phi_inv_positive_p2ibis size p); auto.
Qed.
(** Moreover, [p2ibis] is also related with [p2i] and hence with
[positive_to_int31]. *)
Lemma double_twice_firstl : forall x, firstl x = D0 ->
(Twon*x = twice x)%int31.
Proof.
intros.
unfold mul31.
rewrite <- Z.double_spec, <- phi_twice_firstl, phi_inv_phi; auto.
Qed.
Lemma double_twice_plus_one_firstl : forall x, firstl x = D0 ->
(Twon*x+In = twice_plus_one x)%int31.
Proof.
intros.
rewrite double_twice_firstl; auto.
unfold add31.
rewrite phi_twice_firstl, <- Z.succ_double_spec,
<- phi_twice_plus_one_firstl, phi_inv_phi; auto.
Qed.
Lemma p2i_p2ibis : forall n p, (n<=size)%nat ->
p2i n p = p2ibis n p.
Proof.
induction n; simpl; auto; intros.
destruct p; auto; specialize IHn with p;
generalize (p2ibis_bounded n p);
rewrite IHn; try omega; destruct (p2ibis n p); simpl; intros;
f_equal; auto.
apply double_twice_plus_one_firstl.
apply (nshiftr_0_firstl n); auto; omega.
apply double_twice_firstl.
apply (nshiftr_0_firstl n); auto; omega.
Qed.
Lemma positive_to_int31_phi_inv_positive : forall p,
snd (positive_to_int31 p) = phi_inv_positive p.
Proof.
intros; unfold positive_to_int31.
rewrite p2i_p2ibis; auto.
symmetry.
rewrite <- EqShiftL_zero.
apply (phi_inv_positive_p2ibis size); auto.
Qed.
Lemma positive_to_int31_spec : forall p,
Zpos p = (Z.of_N (fst (positive_to_int31 p)))*2^(Z.of_nat size) +
phi (snd (positive_to_int31 p)).
Proof.
unfold positive_to_int31.
intros; rewrite p2i_p2ibis; auto.
apply p2ibis_spec; auto.
Qed.
(** Thanks to the result about [phi o phi_inv_positive], we can
now establish easily the most general results about
[phi o twice] and so one. *)
Lemma phi_twice : forall x,
phi (twice x) = (Z.double (phi x)) mod 2^(Z.of_nat size).
Proof.
intros.
pattern x at 1; rewrite <- (phi_inv_phi x).
rewrite <- phi_inv_double.
assert (0 <= Z.double (phi x)).
rewrite Z.double_spec; generalize (phi_bounded x); omega.
destruct (Z.double (phi x)).
simpl; auto.
apply phi_phi_inv_positive.
compute in H; elim H; auto.
Qed.
Lemma phi_twice_plus_one : forall x,
phi (twice_plus_one x) = (Z.succ_double (phi x)) mod 2^(Z.of_nat size).
Proof.
intros.
pattern x at 1; rewrite <- (phi_inv_phi x).
rewrite <- phi_inv_double_plus_one.
assert (0 <= Z.succ_double (phi x)).
rewrite Z.succ_double_spec; generalize (phi_bounded x); omega.
destruct (Z.succ_double (phi x)).
simpl; auto.
apply phi_phi_inv_positive.
compute in H; elim H; auto.
Qed.
Lemma phi_incr : forall x,
phi (incr x) = (Z.succ (phi x)) mod 2^(Z.of_nat size).
Proof.
intros.
pattern x at 1; rewrite <- (phi_inv_phi x).
rewrite <- phi_inv_incr.
assert (0 <= Z.succ (phi x)).
change (Z.succ (phi x)) with ((phi x)+1)%Z;
generalize (phi_bounded x); omega.
destruct (Z.succ (phi x)).
simpl; auto.
apply phi_phi_inv_positive.
compute in H; elim H; auto.
Qed.
(** With the previous results, we can deal with [phi o phi_inv] even
in the negative case *)
Lemma phi_phi_inv_negative :
forall p, phi (incr (complement_negative p)) = (Zneg p) mod 2^(Z.of_nat size).
Proof.
induction p.
simpl complement_negative.
rewrite phi_incr in IHp.
rewrite incr_twice, phi_twice_plus_one.
remember (phi (complement_negative p)) as q.
rewrite Z.succ_double_spec.
replace (2*q+1) with (2*(Z.succ q)-1) by omega.
rewrite <- Zminus_mod_idemp_l, <- Zmult_mod_idemp_r, IHp.
rewrite Zmult_mod_idemp_r, Zminus_mod_idemp_l; auto with zarith.
simpl complement_negative.
rewrite incr_twice_plus_one, phi_twice.
remember (phi (incr (complement_negative p))) as q.
rewrite Z.double_spec, IHp, Zmult_mod_idemp_r; auto with zarith.
simpl; auto.
Qed.
Lemma phi_phi_inv :
forall z, phi (phi_inv z) = z mod 2 ^ (Z.of_nat size).
Proof.
destruct z.
simpl; auto.
apply phi_phi_inv_positive.
apply phi_phi_inv_negative.
Qed.
End Basics.
Instance int31_ops : ZnZ.Ops int31 :=
{
digits := 31%positive; (* number of digits *)
zdigits := 31; (* number of digits *)
to_Z := phi; (* conversion to Z *)
of_pos := positive_to_int31; (* positive -> N*int31 : p => N,i
where p = N*2^31+phi i *)
head0 := head031; (* number of head 0 *)
tail0 := tail031; (* number of tail 0 *)
zero := 0;
one := 1;
minus_one := Tn; (* 2^31 - 1 *)
compare := compare31;
eq0 := fun i => match i ?= 0 with Eq => true | _ => false end;
opp_c := fun i => 0 -c i;
opp := opp31;
opp_carry := fun i => 0-i-1;
succ_c := fun i => i +c 1;
add_c := add31c;
add_carry_c := add31carryc;
succ := fun i => i + 1;
add := add31;
add_carry := fun i j => i + j + 1;
pred_c := fun i => i -c 1;
sub_c := sub31c;
sub_carry_c := sub31carryc;
pred := fun i => i - 1;
sub := sub31;
sub_carry := fun i j => i - j - 1;
mul_c := mul31c;
mul := mul31;
square_c := fun x => x *c x;
div21 := div3121;
div_gt := div31; (* this is supposed to be the special case of
division a/b where a > b *)
div := div31;
modulo_gt := fun i j => let (_,r) := i/j in r;
modulo := fun i j => let (_,r) := i/j in r;
gcd_gt := gcd31;
gcd := gcd31;
add_mul_div := addmuldiv31;
pos_mod := (* modulo 2^p *)
fun p i =>
match p ?= 31 with
| Lt => addmuldiv31 p 0 (addmuldiv31 (31-p) i 0)
| _ => i
end;
is_even :=
fun i => let (_,r) := i/2 in
match r ?= 0 with Eq => true | _ => false end;
sqrt2 := sqrt312;
sqrt := sqrt31;
lor := lor31;
land := land31;
lxor := lxor31
}.
Section Int31_Specs.
Local Open Scope Z_scope.
Notation "[| x |]" := (phi x) (at level 0, x at level 99).
Local Notation wB := (2 ^ (Z.of_nat size)).
Lemma wB_pos : wB > 0.
Proof.
auto with zarith.
Qed.
Notation "[+| c |]" :=
(interp_carry 1 wB phi c) (at level 0, c at level 99).
Notation "[-| c |]" :=
(interp_carry (-1) wB phi c) (at level 0, c at level 99).
Notation "[|| x ||]" :=
(zn2z_to_Z wB phi x) (at level 0, x at level 99).
Lemma spec_zdigits : [| 31 |] = 31.
Proof.
reflexivity.
Qed.
Lemma spec_more_than_1_digit: 1 < 31.
Proof.
auto with zarith.
Qed.
Lemma spec_0 : [| 0 |] = 0.
Proof.
reflexivity.
Qed.
Lemma spec_1 : [| 1 |] = 1.
Proof.
reflexivity.
Qed.
Lemma spec_m1 : [| Tn |] = wB - 1.
Proof.
reflexivity.
Qed.
Lemma spec_compare : forall x y,
(x ?= y)%int31 = ([|x|] ?= [|y|]).
Proof. reflexivity. Qed.
(** Addition *)
Lemma spec_add_c : forall x y, [+|add31c x y|] = [|x|] + [|y|].
Proof.
intros; unfold add31c, add31, interp_carry; rewrite phi_phi_inv.
generalize (phi_bounded x)(phi_bounded y); intros.
set (X:=[|x|]) in *; set (Y:=[|y|]) in *; clearbody X Y.
assert ((X+Y) mod wB ?= X+Y <> Eq -> [+|C1 (phi_inv (X+Y))|] = X+Y).
unfold interp_carry; rewrite phi_phi_inv, Z.compare_eq_iff; intros.
destruct (Z_lt_le_dec (X+Y) wB).
contradict H1; auto using Zmod_small with zarith.
rewrite <- (Z_mod_plus_full (X+Y) (-1) wB).
rewrite Zmod_small; romega.
generalize (Z.compare_eq ((X+Y) mod wB) (X+Y)); intros Heq.
destruct Z.compare; intros;
[ rewrite phi_phi_inv; auto | now apply H1 | now apply H1].
Qed.
Lemma spec_succ_c : forall x, [+|add31c x 1|] = [|x|] + 1.
Proof.
intros; apply spec_add_c.
Qed.
Lemma spec_add_carry_c : forall x y, [+|add31carryc x y|] = [|x|] + [|y|] + 1.
Proof.
intros.
unfold add31carryc, interp_carry; rewrite phi_phi_inv.
generalize (phi_bounded x)(phi_bounded y); intros.
set (X:=[|x|]) in *; set (Y:=[|y|]) in *; clearbody X Y.
assert ((X+Y+1) mod wB ?= X+Y+1 <> Eq -> [+|C1 (phi_inv (X+Y+1))|] = X+Y+1).
unfold interp_carry; rewrite phi_phi_inv, Z.compare_eq_iff; intros.
destruct (Z_lt_le_dec (X+Y+1) wB).
contradict H1; auto using Zmod_small with zarith.
rewrite <- (Z_mod_plus_full (X+Y+1) (-1) wB).
rewrite Zmod_small; romega.
generalize (Z.compare_eq ((X+Y+1) mod wB) (X+Y+1)); intros Heq.
destruct Z.compare; intros;
[ rewrite phi_phi_inv; auto | now apply H1 | now apply H1].
Qed.
Lemma spec_add : forall x y, [|x+y|] = ([|x|] + [|y|]) mod wB.
Proof.
intros; apply phi_phi_inv.
Qed.
Lemma spec_add_carry :
forall x y, [|x+y+1|] = ([|x|] + [|y|] + 1) mod wB.
Proof.
unfold add31; intros.
repeat rewrite phi_phi_inv.
apply Zplus_mod_idemp_l.
Qed.
Lemma spec_succ : forall x, [|x+1|] = ([|x|] + 1) mod wB.
Proof.
intros; rewrite <- spec_1; apply spec_add.
Qed.
(** Substraction *)
Lemma spec_sub_c : forall x y, [-|sub31c x y|] = [|x|] - [|y|].
Proof.
unfold sub31c, sub31, interp_carry; intros.
rewrite phi_phi_inv.
generalize (phi_bounded x)(phi_bounded y); intros.
set (X:=[|x|]) in *; set (Y:=[|y|]) in *; clearbody X Y.
assert ((X-Y) mod wB ?= X-Y <> Eq -> [-|C1 (phi_inv (X-Y))|] = X-Y).
unfold interp_carry; rewrite phi_phi_inv, Z.compare_eq_iff; intros.
destruct (Z_lt_le_dec (X-Y) 0).
rewrite <- (Z_mod_plus_full (X-Y) 1 wB).
rewrite Zmod_small; romega.
contradict H1; apply Zmod_small; romega.
generalize (Z.compare_eq ((X-Y) mod wB) (X-Y)); intros Heq.
destruct Z.compare; intros;
[ rewrite phi_phi_inv; auto | now apply H1 | now apply H1].
Qed.
Lemma spec_sub_carry_c : forall x y, [-|sub31carryc x y|] = [|x|] - [|y|] - 1.
Proof.
unfold sub31carryc, sub31, interp_carry; intros.
rewrite phi_phi_inv.
generalize (phi_bounded x)(phi_bounded y); intros.
set (X:=[|x|]) in *; set (Y:=[|y|]) in *; clearbody X Y.
assert ((X-Y-1) mod wB ?= X-Y-1 <> Eq -> [-|C1 (phi_inv (X-Y-1))|] = X-Y-1).
unfold interp_carry; rewrite phi_phi_inv, Z.compare_eq_iff; intros.
destruct (Z_lt_le_dec (X-Y-1) 0).
rewrite <- (Z_mod_plus_full (X-Y-1) 1 wB).
rewrite Zmod_small; romega.
contradict H1; apply Zmod_small; romega.
generalize (Z.compare_eq ((X-Y-1) mod wB) (X-Y-1)); intros Heq.
destruct Z.compare; intros;
[ rewrite phi_phi_inv; auto | now apply H1 | now apply H1].
Qed.
Lemma spec_sub : forall x y, [|x-y|] = ([|x|] - [|y|]) mod wB.
Proof.
intros; apply phi_phi_inv.
Qed.
Lemma spec_sub_carry :
forall x y, [|x-y-1|] = ([|x|] - [|y|] - 1) mod wB.
Proof.
unfold sub31; intros.
repeat rewrite phi_phi_inv.
apply Zminus_mod_idemp_l.
Qed.
Lemma spec_opp_c : forall x, [-|sub31c 0 x|] = -[|x|].
Proof.
intros; apply spec_sub_c.
Qed.
Lemma spec_opp : forall x, [|0 - x|] = (-[|x|]) mod wB.
Proof.
intros; apply phi_phi_inv.
Qed.
Lemma spec_opp_carry : forall x, [|0 - x - 1|] = wB - [|x|] - 1.
Proof.
unfold sub31; intros.
repeat rewrite phi_phi_inv.
change [|1|] with 1; change [|0|] with 0.
rewrite <- (Z_mod_plus_full (0-[|x|]) 1 wB).
rewrite Zminus_mod_idemp_l.
rewrite Zmod_small; generalize (phi_bounded x); romega.
Qed.
Lemma spec_pred_c : forall x, [-|sub31c x 1|] = [|x|] - 1.
Proof.
intros; apply spec_sub_c.
Qed.
Lemma spec_pred : forall x, [|x-1|] = ([|x|] - 1) mod wB.
Proof.
intros; apply spec_sub.
Qed.
(** Multiplication *)
Lemma phi2_phi_inv2 : forall x, [||phi_inv2 x||] = x mod (wB^2).
Proof.
assert (forall z, (z / wB) mod wB * wB + z mod wB = z mod wB ^ 2).
intros.
assert ((z/wB) mod wB = z/wB - (z/wB/wB)*wB).
rewrite (Z_div_mod_eq (z/wB) wB wB_pos) at 2; ring.
assert (z mod wB = z - (z/wB)*wB).
rewrite (Z_div_mod_eq z wB wB_pos) at 2; ring.
rewrite H.
rewrite H0 at 1.
ring_simplify.
rewrite Zdiv_Zdiv; auto with zarith.
rewrite (Z_div_mod_eq z (wB*wB)) at 2; auto with zarith.
change (wB*wB) with (wB^2); ring.
unfold phi_inv2.
destruct x; unfold zn2z_to_Z; rewrite ?phi_phi_inv;
change base with wB; auto.
Qed.
Lemma spec_mul_c : forall x y, [|| mul31c x y ||] = [|x|] * [|y|].
Proof.
unfold mul31c; intros.
rewrite phi2_phi_inv2.
apply Zmod_small.
generalize (phi_bounded x)(phi_bounded y); intros.
change (wB^2) with (wB * wB).
auto using Z.mul_lt_mono_nonneg with zarith.
Qed.
Lemma spec_mul : forall x y, [|x*y|] = ([|x|] * [|y|]) mod wB.
Proof.
intros; apply phi_phi_inv.
Qed.
Lemma spec_square_c : forall x, [|| mul31c x x ||] = [|x|] * [|x|].
Proof.
intros; apply spec_mul_c.
Qed.
(** Division *)
Lemma spec_div21 : forall a1 a2 b,
wB/2 <= [|b|] ->
[|a1|] < [|b|] ->
let (q,r) := div3121 a1 a2 b in
[|a1|] *wB+ [|a2|] = [|q|] * [|b|] + [|r|] /\
0 <= [|r|] < [|b|].
Proof.
unfold div3121; intros.
generalize (phi_bounded a1)(phi_bounded a2)(phi_bounded b); intros.
assert ([|b|]>0) by (auto with zarith).
generalize (Z_div_mod (phi2 a1 a2) [|b|] H4) (Z_div_pos (phi2 a1 a2) [|b|] H4).
unfold Z.div; destruct (Z.div_eucl (phi2 a1 a2) [|b|]).
rewrite ?phi_phi_inv.
destruct 1; intros.
unfold phi2 in *.
change base with wB; change base with wB in H5.
change (Z.pow_pos 2 31) with wB; change (Z.pow_pos 2 31) with wB in H.
rewrite H5, Z.mul_comm.
replace (z0 mod wB) with z0 by (symmetry; apply Zmod_small; omega).
replace (z mod wB) with z; auto with zarith.
symmetry; apply Zmod_small.
split.
apply H7; change base with wB; auto with zarith.
apply Z.mul_lt_mono_pos_r with [|b|]; [omega| ].
rewrite Z.mul_comm.
apply Z.le_lt_trans with ([|b|]*z+z0); [omega| ].
rewrite <- H5.
apply Z.le_lt_trans with ([|a1|]*wB+(wB-1)); [omega | ].
replace ([|a1|]*wB+(wB-1)) with (wB*([|a1|]+1)-1) by ring.
assert (wB*([|a1|]+1) <= wB*[|b|]); try omega.
apply Z.mul_le_mono_nonneg; omega.
Qed.
Lemma spec_div : forall a b, 0 < [|b|] ->
let (q,r) := div31 a b in
[|a|] = [|q|] * [|b|] + [|r|] /\
0 <= [|r|] < [|b|].
Proof.
unfold div31; intros.
assert ([|b|]>0) by (auto with zarith).
generalize (Z_div_mod [|a|] [|b|] H0) (Z_div_pos [|a|] [|b|] H0).
unfold Z.div; destruct (Z.div_eucl [|a|] [|b|]).
rewrite ?phi_phi_inv.
destruct 1; intros.
rewrite H1, Z.mul_comm.
generalize (phi_bounded a)(phi_bounded b); intros.
replace (z0 mod wB) with z0 by (symmetry; apply Zmod_small; omega).
replace (z mod wB) with z; auto with zarith.
symmetry; apply Zmod_small.
split; auto with zarith.
apply Z.le_lt_trans with [|a|]; auto with zarith.
rewrite H1.
apply Z.le_trans with ([|b|]*z); try omega.
rewrite <- (Z.mul_1_l z) at 1.
apply Z.mul_le_mono_nonneg; auto with zarith.
Qed.
Lemma spec_mod : forall a b, 0 < [|b|] ->
[|let (_,r) := (a/b)%int31 in r|] = [|a|] mod [|b|].
Proof.
unfold div31; intros.
assert ([|b|]>0) by (auto with zarith).
unfold Z.modulo.
generalize (Z_div_mod [|a|] [|b|] H0).
destruct (Z.div_eucl [|a|] [|b|]).
rewrite ?phi_phi_inv.
destruct 1; intros.
generalize (phi_bounded b); intros.
apply Zmod_small; omega.
Qed.
Lemma phi_gcd : forall i j,
[|gcd31 i j|] = Zgcdn (2*size) [|j|] [|i|].
Proof.
unfold gcd31.
induction (2*size)%nat; intros.
reflexivity.
simpl euler.
unfold compare31.
change [|On|] with 0.
generalize (phi_bounded j)(phi_bounded i); intros.
case_eq [|j|]; intros.
simpl; intros.
generalize (Zabs_spec [|i|]); omega.
simpl. rewrite IHn, H1; f_equal.
rewrite spec_mod, H1; auto.
rewrite H1; compute; auto.
rewrite H1 in H; destruct H as [H _]; compute in H; elim H; auto.
Qed.
Lemma spec_gcd : forall a b, Zis_gcd [|a|] [|b|] [|gcd31 a b|].
Proof.
intros.
rewrite phi_gcd.
apply Zis_gcd_sym.
apply Zgcdn_is_gcd.
unfold Zgcd_bound.
generalize (phi_bounded b).
destruct [|b|].
unfold size; auto with zarith.
intros (_,H).
cut (Pos.size_nat p <= size)%nat; [ omega | rewrite <- Zpower2_Psize; auto].
intros (H,_); compute in H; elim H; auto.
Qed.
Lemma iter_int31_iter_nat : forall A f i a,
iter_int31 i A f a = iter_nat (Z.abs_nat [|i|]) A f a.
Proof.
intros.
unfold iter_int31.
rewrite <- recrbis_equiv; auto; unfold recrbis.
rewrite <- phibis_aux_equiv.
revert i a; induction size.
simpl; auto.
simpl; intros.
case_eq (firstr i); intros H; rewrite 2 IHn;
unfold phibis_aux; simpl; rewrite ?H; fold (phibis_aux n (shiftr i));
generalize (phibis_aux_pos n (shiftr i)); intros;
set (z := phibis_aux n (shiftr i)) in *; clearbody z;
rewrite <- nat_rect_plus.
f_equal.
rewrite Z.double_spec, <- Z.add_diag.
symmetry; apply Zabs2Nat.inj_add; auto with zarith.
change (iter_nat (S (Z.abs_nat z) + (Z.abs_nat z))%nat A f a =
iter_nat (Z.abs_nat (Z.succ_double z)) A f a); f_equal.
rewrite Z.succ_double_spec, <- Z.add_diag.
rewrite Zabs2Nat.inj_add; auto with zarith.
rewrite Zabs2Nat.inj_add; auto with zarith.
change (Z.abs_nat 1) with 1%nat; omega.
Qed.
Fixpoint addmuldiv31_alt n i j :=
match n with
| O => i
| S n => addmuldiv31_alt n (sneakl (firstl j) i) (shiftl j)
end.
Lemma addmuldiv31_equiv : forall p x y,
addmuldiv31 p x y = addmuldiv31_alt (Z.abs_nat [|p|]) x y.
Proof.
intros.
unfold addmuldiv31.
rewrite iter_int31_iter_nat.
set (n:=Z.abs_nat [|p|]); clearbody n; clear p.
revert x y; induction n.
simpl; auto.
intros.
simpl addmuldiv31_alt.
replace (S n) with (n+1)%nat by (rewrite plus_comm; auto).
rewrite nat_rect_plus; simpl; auto.
Qed.
Lemma spec_add_mul_div : forall x y p, [|p|] <= Zpos 31 ->
[| addmuldiv31 p x y |] =
([|x|] * (2 ^ [|p|]) + [|y|] / (2 ^ ((Zpos 31) - [|p|]))) mod wB.
Proof.
intros.
rewrite addmuldiv31_equiv.
assert ([|p|] = Z.of_nat (Z.abs_nat [|p|])).
rewrite Zabs2Nat.id_abs; symmetry; apply Z.abs_eq.
destruct (phi_bounded p); auto.
rewrite H0; rewrite H0 in H; clear H0; rewrite Zabs2Nat.id.
set (n := Z.abs_nat [|p|]) in *; clearbody n.
assert (n <= 31)%nat.
rewrite Nat2Z.inj_le; auto with zarith.
clear p H; revert x y.
induction n.
simpl Z.of_nat; intros.
rewrite Z.mul_1_r.
replace ([|y|] / 2^(31-0)) with 0.
rewrite Z.add_0_r.
symmetry; apply Zmod_small; apply phi_bounded.
symmetry; apply Zdiv_small; apply phi_bounded.
simpl addmuldiv31_alt; intros.
rewrite IHn; [ | omega ].
case_eq (firstl y); intros.
rewrite phi_twice, Z.double_spec.
rewrite phi_twice_firstl; auto.
change (Z.double [|y|]) with (2*[|y|]).
rewrite Nat2Z.inj_succ, Z.pow_succ_r; auto with zarith.
rewrite Zplus_mod; rewrite Zmult_mod_idemp_l; rewrite <- Zplus_mod.
f_equal.
f_equal.
ring.
replace (31-Z.of_nat n) with (Z.succ(31-Z.succ(Z.of_nat n))) by ring.
rewrite Z.pow_succ_r, <- Zdiv_Zdiv; auto with zarith.
rewrite Z.mul_comm, Z_div_mult; auto with zarith.
rewrite phi_twice_plus_one, Z.succ_double_spec.
rewrite phi_twice; auto.
change (Z.double [|y|]) with (2*[|y|]).
rewrite Nat2Z.inj_succ, Z.pow_succ_r; auto with zarith.
rewrite Zplus_mod; rewrite Zmult_mod_idemp_l; rewrite <- Zplus_mod.
rewrite Z.mul_add_distr_r, Z.mul_1_l, <- Z.add_assoc.
f_equal.
f_equal.
ring.
assert ((2*[|y|]) mod wB = 2*[|y|] - wB).
clear - H. symmetry. apply Zmod_unique with 1; [ | ring ].
generalize (phi_lowerbound _ H) (phi_bounded y).
set (wB' := 2^Z.of_nat (pred size)).
replace wB with (2*wB'); [ omega | ].
unfold wB'. rewrite <- Z.pow_succ_r, <- Nat2Z.inj_succ by (auto with zarith).
f_equal.
rewrite H1.
replace wB with (2^(Z.of_nat n)*2^(31-Z.of_nat n)) by
(rewrite <- Zpower_exp; auto with zarith; f_equal; unfold size; ring).
unfold Z.sub; rewrite <- Z.mul_opp_l.
rewrite Z_div_plus; auto with zarith.
ring_simplify.
replace (31+-Z.of_nat n) with (Z.succ(31-Z.succ(Z.of_nat n))) by ring.
rewrite Z.pow_succ_r, <- Zdiv_Zdiv; auto with zarith.
rewrite Z.mul_comm, Z_div_mult; auto with zarith.
Qed.
Lemma spec_pos_mod : forall w p,
[|ZnZ.pos_mod p w|] = [|w|] mod (2 ^ [|p|]).
Proof.
unfold int31_ops, ZnZ.pos_mod, compare31.
change [|31|] with 31%Z.
assert (forall w p, 31<=p -> [|w|] = [|w|] mod 2^p).
intros.
generalize (phi_bounded w).
symmetry; apply Zmod_small.
split; auto with zarith.
apply Z.lt_le_trans with wB; auto with zarith.
apply Zpower_le_monotone; auto with zarith.
intros.
case_eq ([|p|] ?= 31); intros;
[ apply H; rewrite (Z.compare_eq _ _ H0); auto with zarith | |
apply H; change ([|p|]>31)%Z in H0; auto with zarith ].
change ([|p|]<31) in H0.
rewrite spec_add_mul_div by auto with zarith.
change [|0|] with 0%Z; rewrite Z.mul_0_l, Z.add_0_l.
generalize (phi_bounded p)(phi_bounded w); intros.
assert (31-[|p|]<wB).
apply Z.le_lt_trans with 31%Z; auto with zarith.
compute; auto.
assert ([|31-p|]=31-[|p|]).
unfold sub31; rewrite phi_phi_inv.
change [|31|] with 31%Z.
apply Zmod_small; auto with zarith.
rewrite spec_add_mul_div by (rewrite H4; auto with zarith).
change [|0|] with 0%Z; rewrite Zdiv_0_l, Z.add_0_r.
rewrite H4.
apply shift_unshift_mod_2; auto with zarith.
Qed.
(** Shift operations *)
Lemma spec_head00: forall x, [|x|] = 0 -> [|head031 x|] = Zpos 31.
Proof.
intros.
generalize (phi_inv_phi x).
rewrite H; simpl phi_inv.
intros H'; rewrite <- H'.
simpl; auto.
Qed.
Fixpoint head031_alt n x :=
match n with
| O => 0%nat
| S n => match firstl x with
| D0 => S (head031_alt n (shiftl x))
| D1 => 0%nat
end
end.
Lemma head031_equiv :
forall x, [|head031 x|] = Z.of_nat (head031_alt size x).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H).
simpl; auto.
unfold head031, recl.
change On with (phi_inv (Z.of_nat (31-size))).
replace (head031_alt size x) with
(head031_alt size x + (31 - size))%nat by auto.
assert (size <= 31)%nat by auto with arith.
revert x H; induction size; intros.
simpl; auto.
unfold recl_aux; fold recl_aux.
unfold head031_alt; fold head031_alt.
rewrite H.
assert ([|phi_inv (Z.of_nat (31-S n))|] = Z.of_nat (31 - S n)).
rewrite phi_phi_inv.
apply Zmod_small.
split.
change 0 with (Z.of_nat O); apply inj_le; omega.
apply Z.le_lt_trans with (Z.of_nat 31).
apply inj_le; omega.
compute; auto.
case_eq (firstl x); intros; auto.
rewrite plus_Sn_m, plus_n_Sm.
replace (S (31 - S n)) with (31 - n)%nat by omega.
rewrite <- IHn; [ | omega | ].
f_equal; f_equal.
unfold add31.
rewrite H1.
f_equal.
change [|In|] with 1.
replace (31-n)%nat with (S (31 - S n))%nat by omega.
rewrite Nat2Z.inj_succ; ring.
clear - H H2.
rewrite (sneakr_shiftl x) in H.
rewrite H2 in H.
case_eq (iszero (shiftl x)); intros; auto.
rewrite (iszero_eq0 _ H0) in H; discriminate.
Qed.
Lemma phi_nz : forall x, 0 < [|x|] <-> x <> 0%int31.
Proof.
split; intros.
red; intro; subst x; discriminate.
assert ([|x|]<>0%Z).
contradict H.
rewrite <- (phi_inv_phi x); rewrite H; auto.
generalize (phi_bounded x); auto with zarith.
Qed.
Lemma spec_head0 : forall x, 0 < [|x|] ->
wB/ 2 <= 2 ^ ([|head031 x|]) * [|x|] < wB.
Proof.
intros.
rewrite head031_equiv.
assert (nshiftl x size = 0%int31).
apply nshiftl_size.
revert x H H0.
unfold size at 2 5.
induction size.
simpl Z.of_nat.
intros.
compute in H0; rewrite H0 in H; discriminate.
intros.
simpl head031_alt.
case_eq (firstl x); intros.
rewrite (Nat2Z.inj_succ (head031_alt n (shiftl x))), Z.pow_succ_r; auto with zarith.
rewrite <- Z.mul_assoc, Z.mul_comm, <- Z.mul_assoc, <-(Z.mul_comm 2).
rewrite <- Z.double_spec, <- (phi_twice_firstl _ H1).
apply IHn.
rewrite phi_nz; rewrite phi_nz in H; contradict H.
change twice with shiftl in H.
rewrite (sneakr_shiftl x), H1, H; auto.
rewrite <- nshiftl_S_tail; auto.
change (2^(Z.of_nat 0)) with 1; rewrite Z.mul_1_l.
generalize (phi_bounded x); unfold size; split; auto with zarith.
change (2^(Z.of_nat 31)/2) with (2^(Z.of_nat (pred size))).
apply phi_lowerbound; auto.
Qed.
Lemma spec_tail00: forall x, [|x|] = 0 -> [|tail031 x|] = Zpos 31.
Proof.
intros.
generalize (phi_inv_phi x).
rewrite H; simpl phi_inv.
intros H'; rewrite <- H'.
simpl; auto.
Qed.
Fixpoint tail031_alt n x :=
match n with
| O => 0%nat
| S n => match firstr x with
| D0 => S (tail031_alt n (shiftr x))
| D1 => 0%nat
end
end.
Lemma tail031_equiv :
forall x, [|tail031 x|] = Z.of_nat (tail031_alt size x).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H).
simpl; auto.
unfold tail031, recr.
change On with (phi_inv (Z.of_nat (31-size))).
replace (tail031_alt size x) with
(tail031_alt size x + (31 - size))%nat by auto.
assert (size <= 31)%nat by auto with arith.
revert x H; induction size; intros.
simpl; auto.
unfold recr_aux; fold recr_aux.
unfold tail031_alt; fold tail031_alt.
rewrite H.
assert ([|phi_inv (Z.of_nat (31-S n))|] = Z.of_nat (31 - S n)).
rewrite phi_phi_inv.
apply Zmod_small.
split.
change 0 with (Z.of_nat O); apply inj_le; omega.
apply Z.le_lt_trans with (Z.of_nat 31).
apply inj_le; omega.
compute; auto.
case_eq (firstr x); intros; auto.
rewrite plus_Sn_m, plus_n_Sm.
replace (S (31 - S n)) with (31 - n)%nat by omega.
rewrite <- IHn; [ | omega | ].
f_equal; f_equal.
unfold add31.
rewrite H1.
f_equal.
change [|In|] with 1.
replace (31-n)%nat with (S (31 - S n))%nat by omega.
rewrite Nat2Z.inj_succ; ring.
clear - H H2.
rewrite (sneakl_shiftr x) in H.
rewrite H2 in H.
case_eq (iszero (shiftr x)); intros; auto.
rewrite (iszero_eq0 _ H0) in H; discriminate.
Qed.
Lemma spec_tail0 : forall x, 0 < [|x|] ->
exists y, 0 <= y /\ [|x|] = (2 * y + 1) * (2 ^ [|tail031 x|]).
Proof.
intros.
rewrite tail031_equiv.
assert (nshiftr x size = 0%int31).
apply nshiftr_size.
revert x H H0.
induction size.
simpl Z.of_nat.
intros.
compute in H0; rewrite H0 in H; discriminate.
intros.
simpl tail031_alt.
case_eq (firstr x); intros.
rewrite (Nat2Z.inj_succ (tail031_alt n (shiftr x))), Z.pow_succ_r; auto with zarith.
destruct (IHn (shiftr x)) as (y & Hy1 & Hy2).
rewrite phi_nz; rewrite phi_nz in H; contradict H.
rewrite (sneakl_shiftr x), H1, H; auto.
rewrite <- nshiftr_S_tail; auto.
exists y; split; auto.
rewrite phi_eqn1; auto.
rewrite Z.double_spec, Hy2; ring.
exists [|shiftr x|].
split.
generalize (phi_bounded (shiftr x)); auto with zarith.
rewrite phi_eqn2; auto.
rewrite Z.succ_double_spec; simpl; ring.
Qed.
(* Sqrt *)
(* Direct transcription of an old proof
of a fortran program in boyer-moore *)
Lemma quotient_by_2 a: a - 1 <= (a/2) + (a/2).
Proof.
case (Z_mod_lt a 2); auto with zarith.
intros H1; rewrite Zmod_eq_full; auto with zarith.
Qed.
Lemma sqrt_main_trick j k: 0 <= j -> 0 <= k ->
(j * k) + j <= ((j + k)/2 + 1) ^ 2.
Proof.
intros Hj; generalize Hj k; pattern j; apply natlike_ind;
auto; clear k j Hj.
intros _ k Hk; repeat rewrite Z.add_0_l.
apply Z.mul_nonneg_nonneg; generalize (Z_div_pos k 2); auto with zarith.
intros j Hj Hrec _ k Hk; pattern k; apply natlike_ind; auto; clear k Hk.
rewrite Z.mul_0_r, Z.add_0_r, Z.add_0_l.
generalize (sqr_pos (Z.succ j / 2)) (quotient_by_2 (Z.succ j));
unfold Z.succ.
rewrite Z.pow_2_r, Z.mul_add_distr_r; repeat rewrite Z.mul_add_distr_l.
auto with zarith.
intros k Hk _.
replace ((Z.succ j + Z.succ k) / 2) with ((j + k)/2 + 1).
generalize (Hrec Hj k Hk) (quotient_by_2 (j + k)).
unfold Z.succ; repeat rewrite Z.pow_2_r;
repeat rewrite Z.mul_add_distr_r; repeat rewrite Z.mul_add_distr_l.
repeat rewrite Z.mul_1_l; repeat rewrite Z.mul_1_r.
auto with zarith.
rewrite Z.add_comm, <- Z_div_plus_full_l; auto with zarith.
apply f_equal2 with (f := Z.div); auto with zarith.
Qed.
Lemma sqrt_main i j: 0 <= i -> 0 < j -> i < ((j + (i/j))/2 + 1) ^ 2.
Proof.
intros Hi Hj.
assert (Hij: 0 <= i/j) by (apply Z_div_pos; auto with zarith).
apply Z.lt_le_trans with (2 := sqrt_main_trick _ _ (Z.lt_le_incl _ _ Hj) Hij).
pattern i at 1; rewrite (Z_div_mod_eq i j); case (Z_mod_lt i j); auto with zarith.
Qed.
Lemma sqrt_init i: 1 < i -> i < (i/2 + 1) ^ 2.
Proof.
intros Hi.
assert (H1: 0 <= i - 2) by auto with zarith.
assert (H2: 1 <= (i / 2) ^ 2); auto with zarith.
replace i with (1* 2 + (i - 2)); auto with zarith.
rewrite Z.pow_2_r, Z_div_plus_full_l; auto with zarith.
generalize (sqr_pos ((i - 2)/ 2)) (Z_div_pos (i - 2) 2).
rewrite Z.mul_add_distr_r; repeat rewrite Z.mul_add_distr_l.
auto with zarith.
generalize (quotient_by_2 i).
rewrite Z.pow_2_r in H2 |- *;
repeat (rewrite Z.mul_add_distr_r ||
rewrite Z.mul_add_distr_l ||
rewrite Z.mul_1_l || rewrite Z.mul_1_r).
auto with zarith.
Qed.
Lemma sqrt_test_true i j: 0 <= i -> 0 < j -> i/j >= j -> j ^ 2 <= i.
Proof.
intros Hi Hj Hd; rewrite Z.pow_2_r.
apply Z.le_trans with (j * (i/j)); auto with zarith.
apply Z_mult_div_ge; auto with zarith.
Qed.
Lemma sqrt_test_false i j: 0 <= i -> 0 < j -> i/j < j -> (j + (i/j))/2 < j.
Proof.
intros Hi Hj H; case (Z.le_gt_cases j ((j + (i/j))/2)); auto.
intros H1; contradict H; apply Z.le_ngt.
assert (2 * j <= j + (i/j)); auto with zarith.
apply Z.le_trans with (2 * ((j + (i/j))/2)); auto with zarith.
apply Z_mult_div_ge; auto with zarith.
Qed.
Lemma sqrt31_step_def rec i j:
sqrt31_step rec i j =
match (fst (i/j) ?= j)%int31 with
Lt => rec i (fst ((j + fst(i/j))/2))%int31
| _ => j
end.
Proof.
unfold sqrt31_step; case div31; intros.
simpl; case compare31; auto.
Qed.
Lemma div31_phi i j: 0 < [|j|] -> [|fst (i/j)%int31|] = [|i|]/[|j|].
intros Hj; generalize (spec_div i j Hj).
case div31; intros q r; simpl @fst.
intros (H1,H2); apply Zdiv_unique with [|r|]; auto with zarith.
rewrite H1; ring.
Qed.
Lemma sqrt31_step_correct rec i j:
0 < [|i|] -> 0 < [|j|] -> [|i|] < ([|j|] + 1) ^ 2 ->
2 * [|j|] < wB ->
(forall j1 : int31,
0 < [|j1|] < [|j|] -> [|i|] < ([|j1|] + 1) ^ 2 ->
[|rec i j1|] ^ 2 <= [|i|] < ([|rec i j1|] + 1) ^ 2) ->
[|sqrt31_step rec i j|] ^ 2 <= [|i|] < ([|sqrt31_step rec i j|] + 1) ^ 2.
Proof.
assert (Hp2: 0 < [|2|]) by exact (eq_refl Lt).
intros Hi Hj Hij H31 Hrec; rewrite sqrt31_step_def.
rewrite spec_compare, div31_phi; auto.
case Z.compare_spec; auto; intros Hc;
try (split; auto; apply sqrt_test_true; auto with zarith; fail).
apply Hrec; repeat rewrite div31_phi; auto with zarith.
replace [|(j + fst (i / j)%int31)|] with ([|j|] + [|i|] / [|j|]).
split.
apply Z.le_succ_l in Hj. change (1 <= [|j|]) in Hj.
Z.le_elim Hj.
replace ([|j|] + [|i|]/[|j|]) with
(1 * 2 + (([|j|] - 2) + [|i|] / [|j|])); try ring.
rewrite Z_div_plus_full_l; auto with zarith.
assert (0 <= [|i|]/ [|j|]) by (apply Z_div_pos; auto with zarith).
assert (0 <= ([|j|] - 2 + [|i|] / [|j|]) / [|2|]) ; auto with zarith.
rewrite <- Hj, Zdiv_1_r.
replace (1 + [|i|])%Z with (1 * 2 + ([|i|] - 1))%Z; try ring.
rewrite Z_div_plus_full_l; auto with zarith.
assert (0 <= ([|i|] - 1) /2)%Z by (apply Z_div_pos; auto with zarith).
change ([|2|]) with 2%Z; auto with zarith.
apply sqrt_test_false; auto with zarith.
rewrite spec_add, div31_phi; auto.
symmetry; apply Zmod_small.
split; auto with zarith.
replace [|j + fst (i / j)%int31|] with ([|j|] + [|i|] / [|j|]).
apply sqrt_main; auto with zarith.
rewrite spec_add, div31_phi; auto.
symmetry; apply Zmod_small.
split; auto with zarith.
Qed.
Lemma iter31_sqrt_correct n rec i j: 0 < [|i|] -> 0 < [|j|] ->
[|i|] < ([|j|] + 1) ^ 2 -> 2 * [|j|] < 2 ^ (Z.of_nat size) ->
(forall j1, 0 < [|j1|] -> 2^(Z.of_nat n) + [|j1|] <= [|j|] ->
[|i|] < ([|j1|] + 1) ^ 2 -> 2 * [|j1|] < 2 ^ (Z.of_nat size) ->
[|rec i j1|] ^ 2 <= [|i|] < ([|rec i j1|] + 1) ^ 2) ->
[|iter31_sqrt n rec i j|] ^ 2 <= [|i|] < ([|iter31_sqrt n rec i j|] + 1) ^ 2.
Proof.
revert rec i j; elim n; unfold iter31_sqrt; fold iter31_sqrt; clear n.
intros rec i j Hi Hj Hij H31 Hrec; apply sqrt31_step_correct; auto with zarith.
intros; apply Hrec; auto with zarith.
rewrite Z.pow_0_r; auto with zarith.
intros n Hrec rec i j Hi Hj Hij H31 HHrec.
apply sqrt31_step_correct; auto.
intros j1 Hj1 Hjp1; apply Hrec; auto with zarith.
intros j2 Hj2 H2j2 Hjp2 Hj31; apply Hrec; auto with zarith.
intros j3 Hj3 Hpj3.
apply HHrec; auto.
rewrite Nat2Z.inj_succ, Z.pow_succ_r.
apply Z.le_trans with (2 ^Z.of_nat n + [|j2|]); auto with zarith.
apply Nat2Z.is_nonneg.
Qed.
Lemma spec_sqrt : forall x,
[|sqrt31 x|] ^ 2 <= [|x|] < ([|sqrt31 x|] + 1) ^ 2.
Proof.
intros i; unfold sqrt31.
rewrite spec_compare. case Z.compare_spec; change [|1|] with 1;
intros Hi; auto with zarith.
repeat rewrite Z.pow_2_r; auto with zarith.
apply iter31_sqrt_correct; auto with zarith.
rewrite div31_phi; change ([|2|]) with 2; auto with zarith.
replace ([|i|]) with (1 * 2 + ([|i|] - 2))%Z; try ring.
assert (0 <= ([|i|] - 2)/2)%Z by (apply Z_div_pos; auto with zarith).
rewrite Z_div_plus_full_l; auto with zarith.
rewrite div31_phi; change ([|2|]) with 2; auto with zarith.
apply sqrt_init; auto.
rewrite div31_phi; change ([|2|]) with 2; auto with zarith.
apply Z.le_lt_trans with ([|i|]).
apply Z_mult_div_ge; auto with zarith.
case (phi_bounded i); auto.
intros j2 H1 H2; contradict H2; apply Z.lt_nge.
rewrite div31_phi; change ([|2|]) with 2; auto with zarith.
apply Z.le_lt_trans with ([|i|]); auto with zarith.
assert (0 <= [|i|]/2)%Z by (apply Z_div_pos; auto with zarith).
apply Z.le_trans with (2 * ([|i|]/2)); auto with zarith.
apply Z_mult_div_ge; auto with zarith.
case (phi_bounded i); unfold size; auto with zarith.
change [|0|] with 0; auto with zarith.
case (phi_bounded i); repeat rewrite Z.pow_2_r; auto with zarith.
Qed.
Lemma sqrt312_step_def rec ih il j:
sqrt312_step rec ih il j =
match (ih ?= j)%int31 with
Eq => j
| Gt => j
| _ =>
match (fst (div3121 ih il j) ?= j)%int31 with
Lt => let m := match j +c fst (div3121 ih il j) with
C0 m1 => fst (m1/2)%int31
| C1 m1 => (fst (m1/2) + v30)%int31
end in rec ih il m
| _ => j
end
end.
Proof.
unfold sqrt312_step; case div3121; intros.
simpl; case compare31; auto.
Qed.
Lemma sqrt312_lower_bound ih il j:
phi2 ih il < ([|j|] + 1) ^ 2 -> [|ih|] <= [|j|].
Proof.
intros H1.
case (phi_bounded j); intros Hbj _.
case (phi_bounded il); intros Hbil _.
case (phi_bounded ih); intros Hbih Hbih1.
assert (([|ih|] < [|j|] + 1)%Z); auto with zarith.
apply Z.square_lt_simpl_nonneg; auto with zarith.
repeat rewrite <-Z.pow_2_r; apply Z.le_lt_trans with (2 := H1).
apply Z.le_trans with ([|ih|] * base)%Z; unfold phi2, base;
try rewrite Z.pow_2_r; auto with zarith.
Qed.
Lemma div312_phi ih il j: (2^30 <= [|j|] -> [|ih|] < [|j|] ->
[|fst (div3121 ih il j)|] = phi2 ih il/[|j|])%Z.
Proof.
intros Hj Hj1.
generalize (spec_div21 ih il j Hj Hj1).
case div3121; intros q r (Hq, Hr).
apply Zdiv_unique with (phi r); auto with zarith.
simpl @fst; apply eq_trans with (1 := Hq); ring.
Qed.
Lemma sqrt312_step_correct rec ih il j:
2 ^ 29 <= [|ih|] -> 0 < [|j|] -> phi2 ih il < ([|j|] + 1) ^ 2 ->
(forall j1, 0 < [|j1|] < [|j|] -> phi2 ih il < ([|j1|] + 1) ^ 2 ->
[|rec ih il j1|] ^ 2 <= phi2 ih il < ([|rec ih il j1|] + 1) ^ 2) ->
[|sqrt312_step rec ih il j|] ^ 2 <= phi2 ih il
< ([|sqrt312_step rec ih il j|] + 1) ^ 2.
Proof.
assert (Hp2: (0 < [|2|])%Z) by exact (eq_refl Lt).
intros Hih Hj Hij Hrec; rewrite sqrt312_step_def.
assert (H1: ([|ih|] <= [|j|])%Z) by (apply sqrt312_lower_bound with il; auto).
case (phi_bounded ih); intros Hih1 _.
case (phi_bounded il); intros Hil1 _.
case (phi_bounded j); intros _ Hj1.
assert (Hp3: (0 < phi2 ih il)).
unfold phi2; apply Z.lt_le_trans with ([|ih|] * base)%Z; auto with zarith.
apply Z.mul_pos_pos; auto with zarith.
apply Z.lt_le_trans with (2:= Hih); auto with zarith.
rewrite spec_compare. case Z.compare_spec; intros Hc1.
split; auto.
apply sqrt_test_true; auto.
unfold phi2, base; auto with zarith.
unfold phi2; rewrite Hc1.
assert (0 <= [|il|]/[|j|]) by (apply Z_div_pos; auto with zarith).
rewrite Z.mul_comm, Z_div_plus_full_l; unfold base; auto with zarith.
simpl wB in Hj1. unfold Z.pow_pos in Hj1. simpl in Hj1. auto with zarith.
case (Z.le_gt_cases (2 ^ 30) [|j|]); intros Hjj.
rewrite spec_compare; case Z.compare_spec;
rewrite div312_phi; auto; intros Hc;
try (split; auto; apply sqrt_test_true; auto with zarith; fail).
apply Hrec.
assert (Hf1: 0 <= phi2 ih il/ [|j|]) by (apply Z_div_pos; auto with zarith).
apply Z.le_succ_l in Hj. change (1 <= [|j|]) in Hj.
Z.le_elim Hj.
2: contradict Hc; apply Z.le_ngt; rewrite <- Hj, Zdiv_1_r; auto with zarith.
assert (Hf3: 0 < ([|j|] + phi2 ih il / [|j|]) / 2).
replace ([|j|] + phi2 ih il/ [|j|])%Z with
(1 * 2 + (([|j|] - 2) + phi2 ih il / [|j|])); try ring.
rewrite Z_div_plus_full_l; auto with zarith.
assert (0 <= ([|j|] - 2 + phi2 ih il / [|j|]) / 2) ; auto with zarith.
assert (Hf4: ([|j|] + phi2 ih il / [|j|]) / 2 < [|j|]).
apply sqrt_test_false; auto with zarith.
generalize (spec_add_c j (fst (div3121 ih il j))).
unfold interp_carry; case add31c; intros r;
rewrite div312_phi; auto with zarith.
rewrite div31_phi; change [|2|] with 2%Z; auto with zarith.
intros HH; rewrite HH; clear HH; auto with zarith.
rewrite spec_add, div31_phi; change [|2|] with 2%Z; auto.
rewrite Z.mul_1_l; intros HH.
rewrite Z.add_comm, <- Z_div_plus_full_l; auto with zarith.
change (phi v30 * 2) with (2 ^ Z.of_nat size).
rewrite HH, Zmod_small; auto with zarith.
replace (phi
match j +c fst (div3121 ih il j) with
| C0 m1 => fst (m1 / 2)%int31
| C1 m1 => fst (m1 / 2)%int31 + v30
end) with ((([|j|] + (phi2 ih il)/([|j|]))/2)).
apply sqrt_main; auto with zarith.
generalize (spec_add_c j (fst (div3121 ih il j))).
unfold interp_carry; case add31c; intros r;
rewrite div312_phi; auto with zarith.
rewrite div31_phi; auto with zarith.
intros HH; rewrite HH; auto with zarith.
intros HH; rewrite <- HH.
change (1 * 2 ^ Z.of_nat size) with (phi (v30) * 2).
rewrite Z_div_plus_full_l; auto with zarith.
rewrite Z.add_comm.
rewrite spec_add, Zmod_small.
rewrite div31_phi; auto.
split; auto with zarith.
case (phi_bounded (fst (r/2)%int31));
case (phi_bounded v30); auto with zarith.
rewrite div31_phi; change (phi 2) with 2%Z; auto.
change (2 ^Z.of_nat size) with (base/2 + phi v30).
assert (phi r / 2 < base/2); auto with zarith.
apply Z.mul_lt_mono_pos_r with 2; auto with zarith.
change (base/2 * 2) with base.
apply Z.le_lt_trans with (phi r).
rewrite Z.mul_comm; apply Z_mult_div_ge; auto with zarith.
case (phi_bounded r); auto with zarith.
contradict Hij; apply Z.le_ngt.
assert ((1 + [|j|]) <= 2 ^ 30); auto with zarith.
apply Z.le_trans with ((2 ^ 30) * (2 ^ 30)); auto with zarith.
assert (0 <= 1 + [|j|]); auto with zarith.
apply Z.mul_le_mono_nonneg; auto with zarith.
change ((2 ^ 30) * (2 ^ 30)) with ((2 ^ 29) * base).
apply Z.le_trans with ([|ih|] * base); auto with zarith.
unfold phi2, base; auto with zarith.
split; auto.
apply sqrt_test_true; auto.
unfold phi2, base; auto with zarith.
apply Z.le_ge; apply Z.le_trans with (([|j|] * base)/[|j|]).
rewrite Z.mul_comm, Z_div_mult; auto with zarith.
apply Z.ge_le; apply Z_div_ge; auto with zarith.
Qed.
Lemma iter312_sqrt_correct n rec ih il j:
2^29 <= [|ih|] -> 0 < [|j|] -> phi2 ih il < ([|j|] + 1) ^ 2 ->
(forall j1, 0 < [|j1|] -> 2^(Z.of_nat n) + [|j1|] <= [|j|] ->
phi2 ih il < ([|j1|] + 1) ^ 2 ->
[|rec ih il j1|] ^ 2 <= phi2 ih il < ([|rec ih il j1|] + 1) ^ 2) ->
[|iter312_sqrt n rec ih il j|] ^ 2 <= phi2 ih il
< ([|iter312_sqrt n rec ih il j|] + 1) ^ 2.
Proof.
revert rec ih il j; elim n; unfold iter312_sqrt; fold iter312_sqrt; clear n.
intros rec ih il j Hi Hj Hij Hrec; apply sqrt312_step_correct; auto with zarith.
intros; apply Hrec; auto with zarith.
rewrite Z.pow_0_r; auto with zarith.
intros n Hrec rec ih il j Hi Hj Hij HHrec.
apply sqrt312_step_correct; auto.
intros j1 Hj1 Hjp1; apply Hrec; auto with zarith.
intros j2 Hj2 H2j2 Hjp2; apply Hrec; auto with zarith.
intros j3 Hj3 Hpj3.
apply HHrec; auto.
rewrite Nat2Z.inj_succ, Z.pow_succ_r.
apply Z.le_trans with (2 ^Z.of_nat n + [|j2|])%Z; auto with zarith.
apply Nat2Z.is_nonneg.
Qed.
(* Avoid expanding [iter312_sqrt] before variables in the context. *)
Strategy 1 [iter312_sqrt].
Lemma spec_sqrt2 : forall x y,
wB/ 4 <= [|x|] ->
let (s,r) := sqrt312 x y in
[||WW x y||] = [|s|] ^ 2 + [+|r|] /\
[+|r|] <= 2 * [|s|].
Proof.
intros ih il Hih; unfold sqrt312.
change [||WW ih il||] with (phi2 ih il).
assert (Hbin: forall s, s * s + 2* s + 1 = (s + 1) ^ 2) by
(intros s; ring).
assert (Hb: 0 <= base) by (red; intros HH; discriminate).
assert (Hi2: phi2 ih il < (phi Tn + 1) ^ 2).
{ change ((phi Tn + 1) ^ 2) with (2^62).
apply Z.le_lt_trans with ((2^31 -1) * base + (2^31 - 1)); auto with zarith.
2: simpl; unfold Z.pow_pos; simpl; auto with zarith.
case (phi_bounded ih); case (phi_bounded il); intros H1 H2 H3 H4.
unfold base, Z.pow, Z.pow_pos in H2,H4; simpl in H2,H4.
unfold phi2. cbn [Z.pow Z.pow_pos Pos.iter]. auto with zarith. }
case (iter312_sqrt_correct 31 (fun _ _ j => j) ih il Tn); auto with zarith.
change [|Tn|] with 2147483647; auto with zarith.
intros j1 _ HH; contradict HH.
apply Z.lt_nge.
change [|Tn|] with 2147483647; auto with zarith.
change (2 ^ Z.of_nat 31) with 2147483648; auto with zarith.
case (phi_bounded j1); auto with zarith.
set (s := iter312_sqrt 31 (fun _ _ j : int31 => j) ih il Tn).
intros Hs1 Hs2.
generalize (spec_mul_c s s); case mul31c.
simpl zn2z_to_Z; intros HH.
assert ([|s|] = 0).
{ symmetry in HH. rewrite Z.mul_eq_0 in HH. destruct HH; auto. }
contradict Hs2; apply Z.le_ngt; rewrite H.
change ((0 + 1) ^ 2) with 1.
apply Z.le_trans with (2 ^ Z.of_nat size / 4 * base).
simpl; auto with zarith.
apply Z.le_trans with ([|ih|] * base); auto with zarith.
unfold phi2; case (phi_bounded il); auto with zarith.
intros ih1 il1.
change [||WW ih1 il1||] with (phi2 ih1 il1).
intros Hihl1.
generalize (spec_sub_c il il1).
case sub31c; intros il2 Hil2.
rewrite spec_compare; case Z.compare_spec.
unfold interp_carry in *.
intros H1; split.
rewrite Z.pow_2_r, <- Hihl1.
unfold phi2; ring[Hil2 H1].
replace [|il2|] with (phi2 ih il - phi2 ih1 il1).
rewrite Hihl1.
rewrite <-Hbin in Hs2; auto with zarith.
unfold phi2; rewrite H1, Hil2; ring.
unfold interp_carry.
intros H1; contradict Hs1.
apply Z.lt_nge; rewrite Z.pow_2_r, <-Hihl1.
unfold phi2.
case (phi_bounded il); intros _ H2.
apply Z.lt_le_trans with (([|ih|] + 1) * base + 0).
rewrite Z.mul_add_distr_r, Z.add_0_r; auto with zarith.
case (phi_bounded il1); intros H3 _.
apply Z.add_le_mono; auto with zarith.
unfold interp_carry in *; change (1 * 2 ^ Z.of_nat size) with base.
rewrite Z.pow_2_r, <- Hihl1, Hil2.
intros H1.
rewrite <- Z.le_succ_l, <- Z.add_1_r in H1.
Z.le_elim H1.
contradict Hs2; apply Z.le_ngt.
replace (([|s|] + 1) ^ 2) with (phi2 ih1 il1 + 2 * [|s|] + 1).
unfold phi2.
case (phi_bounded il); intros Hpil _.
assert (Hl1l: [|il1|] <= [|il|]).
{ case (phi_bounded il2); rewrite Hil2; auto with zarith. }
assert ([|ih1|] * base + 2 * [|s|] + 1 <= [|ih|] * base); auto with zarith.
case (phi_bounded s); change (2 ^ Z.of_nat size) with base; intros _ Hps.
case (phi_bounded ih1); intros Hpih1 _; auto with zarith.
apply Z.le_trans with (([|ih1|] + 2) * base); auto with zarith.
rewrite Z.mul_add_distr_r.
assert (2 * [|s|] + 1 <= 2 * base); auto with zarith.
rewrite Hihl1, Hbin; auto.
split.
unfold phi2; rewrite <- H1; ring.
replace (base + ([|il|] - [|il1|])) with (phi2 ih il - ([|s|] * [|s|])).
rewrite <-Hbin in Hs2; auto with zarith.
rewrite <- Hihl1; unfold phi2; rewrite <- H1; ring.
unfold interp_carry in Hil2 |- *.
unfold interp_carry; change (1 * 2 ^ Z.of_nat size) with base.
assert (Hsih: [|ih - 1|] = [|ih|] - 1).
{ rewrite spec_sub, Zmod_small; auto; change [|1|] with 1.
case (phi_bounded ih); intros H1 H2.
generalize Hih; change (2 ^ Z.of_nat size / 4) with 536870912.
split; auto with zarith. }
rewrite spec_compare; case Z.compare_spec.
rewrite Hsih.
intros H1; split.
rewrite Z.pow_2_r, <- Hihl1.
unfold phi2; rewrite <-H1.
transitivity ([|ih|] * base + [|il1|] + ([|il|] - [|il1|])).
ring.
rewrite <-Hil2.
change (2 ^ Z.of_nat size) with base; ring.
replace [|il2|] with (phi2 ih il - phi2 ih1 il1).
rewrite Hihl1.
rewrite <-Hbin in Hs2; auto with zarith.
unfold phi2.
rewrite <-H1.
ring_simplify.
transitivity (base + ([|il|] - [|il1|])).
ring.
rewrite <-Hil2.
change (2 ^ Z.of_nat size) with base; ring.
rewrite Hsih; intros H1.
assert (He: [|ih|] = [|ih1|]).
{ apply Z.le_antisymm; auto with zarith.
case (Z.le_gt_cases [|ih1|] [|ih|]); auto; intros H2.
contradict Hs1; apply Z.lt_nge; rewrite Z.pow_2_r, <-Hihl1.
unfold phi2.
case (phi_bounded il); change (2 ^ Z.of_nat size) with base;
intros _ Hpil1.
apply Z.lt_le_trans with (([|ih|] + 1) * base).
rewrite Z.mul_add_distr_r, Z.mul_1_l; auto with zarith.
case (phi_bounded il1); intros Hpil2 _.
apply Z.le_trans with (([|ih1|]) * base); auto with zarith. }
rewrite Z.pow_2_r, <-Hihl1; unfold phi2; rewrite <-He.
contradict Hs1; apply Z.lt_nge; rewrite Z.pow_2_r, <-Hihl1.
unfold phi2; rewrite He.
assert (phi il - phi il1 < 0); auto with zarith.
rewrite <-Hil2.
case (phi_bounded il2); auto with zarith.
intros H1.
rewrite Z.pow_2_r, <-Hihl1.
assert (H2 : [|ih1|]+2 <= [|ih|]); auto with zarith.
Z.le_elim H2.
contradict Hs2; apply Z.le_ngt.
replace (([|s|] + 1) ^ 2) with (phi2 ih1 il1 + 2 * [|s|] + 1).
unfold phi2.
assert ([|ih1|] * base + 2 * phi s + 1 <= [|ih|] * base + ([|il|] - [|il1|]));
auto with zarith.
rewrite <-Hil2.
change (-1 * 2 ^ Z.of_nat size) with (-base).
case (phi_bounded il2); intros Hpil2 _.
apply Z.le_trans with ([|ih|] * base + - base); auto with zarith.
case (phi_bounded s); change (2 ^ Z.of_nat size) with base; intros _ Hps.
assert (2 * [|s|] + 1 <= 2 * base); auto with zarith.
apply Z.le_trans with ([|ih1|] * base + 2 * base); auto with zarith.
assert (Hi: ([|ih1|] + 3) * base <= [|ih|] * base); auto with zarith.
rewrite Z.mul_add_distr_r in Hi; auto with zarith.
rewrite Hihl1, Hbin; auto.
unfold phi2; rewrite <-H2.
split.
replace [|il|] with (([|il|] - [|il1|]) + [|il1|]); try ring.
rewrite <-Hil2.
change (-1 * 2 ^ Z.of_nat size) with (-base); ring.
replace (base + [|il2|]) with (phi2 ih il - phi2 ih1 il1).
rewrite Hihl1.
rewrite <-Hbin in Hs2; auto with zarith.
unfold phi2; rewrite <-H2.
replace [|il|] with (([|il|] - [|il1|]) + [|il1|]); try ring.
rewrite <-Hil2.
change (-1 * 2 ^ Z.of_nat size) with (-base); ring.
Qed.
(** [iszero] *)
Lemma spec_eq0 : forall x, ZnZ.eq0 x = true -> [|x|] = 0.
Proof.
clear; unfold ZnZ.eq0, int31_ops.
unfold compare31; intros.
change [|0|] with 0 in H.
apply Z.compare_eq.
now destruct ([|x|] ?= 0).
Qed.
(* Even *)
Lemma spec_is_even : forall x,
if ZnZ.is_even x then [|x|] mod 2 = 0 else [|x|] mod 2 = 1.
Proof.
unfold ZnZ.is_even, int31_ops; intros.
generalize (spec_div x 2).
destruct (x/2)%int31 as (q,r); intros.
unfold compare31.
change [|2|] with 2 in H.
change [|0|] with 0.
destruct H; auto with zarith.
replace ([|x|] mod 2) with [|r|].
destruct H; auto with zarith.
case Z.compare_spec; auto with zarith.
apply Zmod_unique with [|q|]; auto with zarith.
Qed.
(* Bitwise *)
Lemma log2_phi_bounded x : Z.log2 [|x|] < Z.of_nat size.
Proof.
destruct (phi_bounded x) as (H,H').
Z.le_elim H.
- now apply Z.log2_lt_pow2.
- now rewrite <- H.
Qed.
Lemma spec_lor x y : [| ZnZ.lor x y |] = Z.lor [|x|] [|y|].
Proof.
unfold ZnZ.lor,int31_ops. unfold lor31.
rewrite phi_phi_inv.
apply Z.mod_small; split; trivial.
- apply Z.lor_nonneg; split; apply phi_bounded.
- apply Z.log2_lt_cancel. rewrite Z.log2_pow2 by easy.
rewrite Z.log2_lor; try apply phi_bounded.
apply Z.max_lub_lt; apply log2_phi_bounded.
Qed.
Lemma spec_land x y : [| ZnZ.land x y |] = Z.land [|x|] [|y|].
Proof.
unfold ZnZ.land, int31_ops. unfold land31.
rewrite phi_phi_inv.
apply Z.mod_small; split; trivial.
- apply Z.land_nonneg; left; apply phi_bounded.
- apply Z.log2_lt_cancel. rewrite Z.log2_pow2 by easy.
eapply Z.le_lt_trans.
apply Z.log2_land; try apply phi_bounded.
apply Z.min_lt_iff; left; apply log2_phi_bounded.
Qed.
Lemma spec_lxor x y : [| ZnZ.lxor x y |] = Z.lxor [|x|] [|y|].
Proof.
unfold ZnZ.lxor, int31_ops. unfold lxor31.
rewrite phi_phi_inv.
apply Z.mod_small; split; trivial.
- apply Z.lxor_nonneg; split; intros; apply phi_bounded.
- apply Z.log2_lt_cancel. rewrite Z.log2_pow2 by easy.
eapply Z.le_lt_trans.
apply Z.log2_lxor; try apply phi_bounded.
apply Z.max_lub_lt; apply log2_phi_bounded.
Qed.
Global Instance int31_specs : ZnZ.Specs int31_ops := {
spec_to_Z := phi_bounded;
spec_of_pos := positive_to_int31_spec;
spec_zdigits := spec_zdigits;
spec_more_than_1_digit := spec_more_than_1_digit;
spec_0 := spec_0;
spec_1 := spec_1;
spec_m1 := spec_m1;
spec_compare := spec_compare;
spec_eq0 := spec_eq0;
spec_opp_c := spec_opp_c;
spec_opp := spec_opp;
spec_opp_carry := spec_opp_carry;
spec_succ_c := spec_succ_c;
spec_add_c := spec_add_c;
spec_add_carry_c := spec_add_carry_c;
spec_succ := spec_succ;
spec_add := spec_add;
spec_add_carry := spec_add_carry;
spec_pred_c := spec_pred_c;
spec_sub_c := spec_sub_c;
spec_sub_carry_c := spec_sub_carry_c;
spec_pred := spec_pred;
spec_sub := spec_sub;
spec_sub_carry := spec_sub_carry;
spec_mul_c := spec_mul_c;
spec_mul := spec_mul;
spec_square_c := spec_square_c;
spec_div21 := spec_div21;
spec_div_gt := fun a b _ => spec_div a b;
spec_div := spec_div;
spec_modulo_gt := fun a b _ => spec_mod a b;
spec_modulo := spec_mod;
spec_gcd_gt := fun a b _ => spec_gcd a b;
spec_gcd := spec_gcd;
spec_head00 := spec_head00;
spec_head0 := spec_head0;
spec_tail00 := spec_tail00;
spec_tail0 := spec_tail0;
spec_add_mul_div := spec_add_mul_div;
spec_pos_mod := spec_pos_mod;
spec_is_even := spec_is_even;
spec_sqrt2 := spec_sqrt2;
spec_sqrt := spec_sqrt;
spec_lor := spec_lor;
spec_land := spec_land;
spec_lxor := spec_lxor }.
End Int31_Specs.
Module Int31Cyclic <: CyclicType.
Definition t := int31.
Definition ops := int31_ops.
Definition specs := int31_specs.
End Int31Cyclic.
|
(** * Hoare: Hoare Logic, Part I *)
Require Export Imp.
(** In the past couple of chapters, we've begun applying the
mathematical tools developed in the first part of the course to
studying the theory of a small programming language, Imp.
- We defined a type of _abstract syntax trees_ for Imp, together
with an _evaluation relation_ (a partial function on states)
that specifies the _operational semantics_ of programs.
The language we defined, though small, captures some of the key
features of full-blown languages like C, C++, and Java,
including the fundamental notion of mutable state and some
common control structures.
- We proved a number of _metatheoretic properties_ -- "meta" in
the sense that they are properties of the language as a whole,
rather than properties of particular programs in the language.
These included:
- determinism of evaluation
- equivalence of some different ways of writing down the
definitions (e.g. functional and relational definitions of
arithmetic expression evaluation)
- guaranteed termination of certain classes of programs
- correctness (in the sense of preserving meaning) of a number
of useful program transformations
- behavioral equivalence of programs (in the [Equiv] chapter).
If we stopped here, we would already have something useful: a set
of tools for defining and discussing programming languages and
language features that are mathematically precise, flexible, and
easy to work with, applied to a set of key properties. All of
these properties are things that language designers, compiler
writers, and users might care about knowing. Indeed, many of them
are so fundamental to our understanding of the programming
languages we deal with that we might not consciously recognize
them as "theorems." But properties that seem intuitively obvious
can sometimes be quite subtle (in some cases, even subtly wrong!).
We'll return to the theme of metatheoretic properties of whole
languages later in the course when we discuss _types_ and _type
soundness_. In this chapter, though, we'll turn to a different
set of issues.
Our goal is to see how to carry out some simple examples of
_program verification_ -- i.e., using the precise definition of
Imp to prove formally that particular programs satisfy particular
specifications of their behavior. We'll develop a reasoning system
called _Floyd-Hoare Logic_ -- often shortened to just _Hoare
Logic_ -- in which each of the syntactic constructs of Imp is
equipped with a single, generic "proof rule" that can be used to
reason compositionally about the correctness of programs involving
this construct.
Hoare Logic originates in the 1960s, and it continues to be the
subject of intensive research right up to the present day. It
lies at the core of a multitude of tools that are being used in
academia and industry to specify and verify real software
systems. *)
(* ####################################################### *)
(** * Hoare Logic *)
(** Hoare Logic combines two beautiful ideas: a natural way of
writing down _specifications_ of programs, and a _compositional
proof technique_ for proving that programs are correct with
respect to such specifications -- where by "compositional" we mean
that the structure of proofs directly mirrors the structure of the
programs that they are about. *)
(* ####################################################### *)
(** ** Assertions *)
(** To talk about specifications of programs, the first thing we
need is a way of making _assertions_ about properties that hold at
particular points during a program's execution -- i.e., claims
about the current state of the memory when program execution
reaches that point. Formally, an assertion is just a family of
propositions indexed by a [state]. *)
Definition Assertion := state -> Prop.
(** **** Exercise: 1 star, optional (assertions) *)
Module ExAssertions.
(** Paraphrase the following assertions in English. *)
Definition as1 : Assertion := fun st => st X = 3.
Definition as2 : Assertion := fun st => st X <= st Y.
Definition as3 : Assertion :=
fun st => st X = 3 \/ st X <= st Y.
Definition as4 : Assertion :=
fun st => st Z * st Z <= st X /\
~ (((S (st Z)) * (S (st Z))) <= st X).
Definition as5 : Assertion := fun st => True.
Definition as6 : Assertion := fun st => False.
(* FILL IN HERE *)
End ExAssertions.
(** [] *)
(* ####################################################### *)
(** ** Notation for Assertions *)
(** This way of writing assertions can be a little bit heavy,
for two reasons: (1) every single assertion that we ever write is
going to begin with [fun st => ]; and (2) this state [st] is the
only one that we ever use to look up variables (we will never need
to talk about two different memory states at the same time). For
discussing examples informally, we'll adopt some simplifying
conventions: we'll drop the initial [fun st =>], and we'll write
just [X] to mean [st X]. Thus, instead of writing *)
(**
fun st => (st Z) * (st Z) <= m /\
~ ((S (st Z)) * (S (st Z)) <= m)
we'll write just
Z * Z <= m /\ ~((S Z) * (S Z) <= m).
*)
(** Given two assertions [P] and [Q], we say that [P] _implies_ [Q],
written [P ->> Q] (in ASCII, [P -][>][> Q]), if, whenever [P]
holds in some state [st], [Q] also holds. *)
Definition assert_implies (P Q : Assertion) : Prop :=
forall st, P st -> Q st.
Notation "P ->> Q" :=
(assert_implies P Q) (at level 80) : hoare_spec_scope.
Open Scope hoare_spec_scope.
(** We'll also have occasion to use the "iff" variant of implication
between assertions: *)
Notation "P <<->> Q" :=
(P ->> Q /\ Q ->> P) (at level 80) : hoare_spec_scope.
(* ####################################################### *)
(** ** Hoare Triples *)
(** Next, we need a way of making formal claims about the
behavior of commands. *)
(** Since the behavior of a command is to transform one state to
another, it is natural to express claims about commands in terms
of assertions that are true before and after the command executes:
- "If command [c] is started in a state satisfying assertion
[P], and if [c] eventually terminates in some final state,
then this final state will satisfy the assertion [Q]."
Such a claim is called a _Hoare Triple_. The property [P] is
called the _precondition_ of [c], while [Q] is the
_postcondition_. Formally: *)
Definition hoare_triple
(P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st',
c / st || st' ->
P st ->
Q st'.
(** Since we'll be working a lot with Hoare triples, it's useful to
have a compact notation:
{{P}} c {{Q}}.
*)
(** (The traditional notation is [{P} c {Q}], but single braces
are already used for other things in Coq.) *)
Notation "{{ P }} c {{ Q }}" :=
(hoare_triple P c Q) (at level 90, c at next level)
: hoare_spec_scope.
(** (The [hoare_spec_scope] annotation here tells Coq that this
notation is not global but is intended to be used in particular
contexts. The [Open Scope] tells Coq that this file is one such
context.) *)
(** **** Exercise: 1 star, optional (triples) *)
(** Paraphrase the following Hoare triples in English.
1) {{True}} c {{X = 5}}
X will *always* be 5 after running c, for any starting state.
2) {{X = m}} c {{X = m + 5)}}
c adds 5 to x.
3) {{X <= Y}} c {{Y <= X}}
If X <= Y initially, then Y <= X after running c.
4) {{True}} c {{False}}
c doesn't terminate.
5) {{X = m}}
c
{{Y = real_fact m}}.
c replaces X with its factorial.
6) {{True}}
c
{{(Z * Z) <= m /\ ~ (((S Z) * (S Z)) <= m)}}
Z^2 and (Z+1)^2 will always be less than a given m
after running c.
*)
(** [] *)
(** **** Exercise: 1 star, optional (valid_triples) *)
(** Which of the following Hoare triples are _valid_ -- i.e., the
claimed relation between [P], [c], and [Q] is true?
1) {{True}} X ::= 5 {{X = 5}}
Yes
2) {{X = 2}} X ::= X + 1 {{X = 3}}
Yes
3) {{True}} X ::= 5; Y ::= 0 {{X = 5}}
Yes
4) {{X = 2 /\ X = 3}} X ::= 5 {{X = 0}}
Yes
5) {{True}} SKIP {{False}}
No
6) {{False}} SKIP {{True}}
Yes
7) {{True}} WHILE True DO SKIP END {{False}}
Yes
8) {{X = 0}}
WHILE X == 0 DO X ::= X + 1 END
{{X = 1}}
Yes
9) {{X = 1}}
WHILE X <> 0 DO X ::= X + 1 END
{{X = 100}}
No
*)
(** [] *)
(** (Note that we're using informal mathematical notations for
expressions inside of commands, for readability, rather than their
formal [aexp] and [bexp] encodings. We'll continue doing so
throughout the chapter.) *)
(** To get us warmed up for what's coming, here are two simple
facts about Hoare triples. *)
Theorem hoare_post_true : forall (P Q : Assertion) c,
(forall st, Q st) ->
{{P}} c {{Q}}.
Proof.
intros P Q c H. unfold hoare_triple.
intros st st' Heval HP.
apply H. Qed.
Theorem hoare_pre_false : forall (P Q : Assertion) c,
(forall st, ~(P st)) ->
{{P}} c {{Q}}.
Proof.
intros P Q c H. unfold hoare_triple.
intros st st' Heval HP.
unfold not in H. apply H in HP.
inversion HP. Qed.
(* ####################################################### *)
(** ** Proof Rules *)
(** The goal of Hoare logic is to provide a _compositional_
method for proving the validity of Hoare triples. That is, the
structure of a program's correctness proof should mirror the
structure of the program itself. To this end, in the sections
below, we'll introduce one rule for reasoning about each of the
different syntactic forms of commands in Imp -- one for
assignment, one for sequencing, one for conditionals, etc. -- plus
a couple of "structural" rules that are useful for gluing things
together. We will prove programs correct using these proof rules,
without ever unfolding the definition of [hoare_triple]. *)
(* ####################################################### *)
(** *** Assignment *)
(** The rule for assignment is the most fundamental of the Hoare logic
proof rules. Here's how it works.
Consider this (valid) Hoare triple:
{{ Y = 1 }} X ::= Y {{ X = 1 }}
In English: if we start out in a state where the value of [Y]
is [1] and we assign [Y] to [X], then we'll finish in a
state where [X] is [1]. That is, the property of being equal
to [1] gets transferred from [Y] to [X].
Similarly, in
{{ Y + Z = 1 }} X ::= Y + Z {{ X = 1 }}
the same property (being equal to one) gets transferred to
[X] from the expression [Y + Z] on the right-hand side of
the assignment.
More generally, if [a] is _any_ arithmetic expression, then
{{ a = 1 }} X ::= a {{ X = 1 }}
is a valid Hoare triple.
This can be made even more general. To conclude that an
_arbitrary_ property [Q] holds after [X ::= a], we need to assume
that [Q] holds before [X ::= a], but _with all occurrences of_ [X]
replaced by [a] in [Q]. This leads to the Hoare rule for
assignment
{{ Q [X |-> a] }} X ::= a {{ Q }}
where "[Q [X |-> a]]" is pronounced "[Q] where [a] is substituted
for [X]".
For example, these are valid applications of the assignment
rule:
{{ (X <= 5) [X |-> X + 1]
i.e., X + 1 <= 5 }}
X ::= X + 1
{{ X <= 5 }}
{{ (X = 3) [X |-> 3]
i.e., 3 = 3}}
X ::= 3
{{ X = 3 }}
{{ (0 <= X /\ X <= 5) [X |-> 3]
i.e., (0 <= 3 /\ 3 <= 5)}}
X ::= 3
{{ 0 <= X /\ X <= 5 }}
*)
(** To formalize the rule, we must first formalize the idea of
"substituting an expression for an Imp variable in an assertion."
That is, given a proposition [P], a variable [X], and an
arithmetic expression [a], we want to derive another proposition
[P'] that is just the same as [P] except that, wherever [P]
mentions [X], [P'] should instead mention [a].
Since [P] is an arbitrary Coq proposition, we can't directly
"edit" its text. Instead, we can achieve the effect we want by
evaluating [P] in an updated state: *)
Definition assn_sub X a P : Assertion :=
fun (st : state) =>
P (update st X (aeval st a)).
Notation "P [ X |-> a ]" := (assn_sub X a P) (at level 10).
(** That is, [P [X |-> a]] is an assertion [P'] that is just like [P]
except that, wherever [P] looks up the variable [X] in the current
state, [P'] instead uses the value of the expression [a].
To see how this works, let's calculate what happens with a couple
of examples. First, suppose [P'] is [(X <= 5) [X |-> 3]] -- that
is, more formally, [P'] is the Coq expression
fun st =>
(fun st' => st' X <= 5)
(update st X (aeval st (ANum 3))),
which simplifies to
fun st =>
(fun st' => st' X <= 5)
(update st X 3)
and further simplifies to
fun st =>
((update st X 3) X) <= 5)
and by further simplification to
fun st =>
(3 <= 5).
That is, [P'] is the assertion that [3] is less than or equal to
[5] (as expected).
For a more interesting example, suppose [P'] is [(X <= 5) [X |->
X+1]]. Formally, [P'] is the Coq expression
fun st =>
(fun st' => st' X <= 5)
(update st X (aeval st (APlus (AId X) (ANum 1)))),
which simplifies to
fun st =>
(((update st X (aeval st (APlus (AId X) (ANum 1))))) X) <= 5
and further simplifies to
fun st =>
(aeval st (APlus (AId X) (ANum 1))) <= 5.
That is, [P'] is the assertion that [X+1] is at most [5].
*)
(** Now we can give the precise proof rule for assignment:
------------------------------ (hoare_asgn)
{{Q [X |-> a]}} X ::= a {{Q}}
*)
(** We can prove formally that this rule is indeed valid. *)
Theorem hoare_asgn : forall Q X a,
{{Q [X |-> a]}} (X ::= a) {{Q}}.
Proof.
unfold hoare_triple.
intros Q X a st st' HE HQ.
inversion HE. subst.
unfold assn_sub in HQ. assumption. Qed.
(** Here's a first formal proof using this rule. *)
Example assn_sub_example :
{{(fun st => st X = 3) [X |-> ANum 3]}}
(X ::= (ANum 3))
{{fun st => st X = 3}}.
Proof.
apply hoare_asgn. Qed.
(** **** Exercise: 2 stars (hoare_asgn_examples) *)
(** Translate these informal Hoare triples...
1) {{ (X <= 5) [X |-> X + 1] }}
X ::= X + 1
{{ X <= 5 }}
2) {{ (0 <= X /\ X <= 5) [X |-> 3] }}
X ::= 3
{{ 0 <= X /\ X <= 5 }}
...into formal statements [assn_sub_ex1, assn_sub_ex2]
and use [hoare_asgn] to prove them. *)
Example hoare_asgn_examples_1 :
{{(fun st => st X <= 5) [X |-> (APlus (AId X) (ANum 1))]}}
(X ::= (APlus (AId X) (ANum 1)))
{{fun st => st X <= 5 }}.
Proof.
apply hoare_asgn.
Qed.
Example hoare_asgn_examples_2 :
{{(fun st => 0 <= st X /\ st X <= 5) [X |-> (ANum 3)]}}
(X ::= (ANum 3))
{{fun st => 0 <= st X /\ st X <= 5}}.
Proof.
apply hoare_asgn.
Qed.
(** [] *)
(** **** Exercise: 2 stars (hoare_asgn_wrong) *)
(** The assignment rule looks backward to almost everyone the first
time they see it. If it still seems backward to you, it may help
to think a little about alternative "forward" rules. Here is a
seemingly natural one:
------------------------------ (hoare_asgn_wrong)
{{ True }} X ::= a {{ X = a }}
Give a counterexample showing that this rule is incorrect
(informally). Hint: The rule universally quantifies over the
arithmetic expression [a], and your counterexample needs to
exhibit an [a] for which the rule doesn't work. *)
Lemma stupid : forall n,
n <> n + 1.
Proof.
induction n as [| n'].
Case "n = 0". inversion 1.
Case "n = S n'".
unfold not in IHn'. unfold not. intros. inversion H.
apply IHn' in H1. inversion H1.
Qed.
Example hoare_asgn_wrong : exists a,
{{fun st => True}}
(X ::= a)
{{fun st => st X <> (aeval st a)}}.
Proof.
exists (APlus (AId X) (ANum 1)).
unfold hoare_triple. intros.
inversion H; subst.
simpl. apply stupid.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (hoare_asgn_fwd) *)
(** However, using an auxiliary variable [m] to remember the original
value of [X] we can define a Hoare rule for assignment that does,
intuitively, "work forwards" rather than backwards.
------------------------------------------ (hoare_asgn_fwd)
{{fun st => P st /\ st X = m}}
X ::= a
{{fun st => P st' /\ st X = aeval st' a }}
(where st' = update st X m)
Note that we use the original value of [X] to reconstruct the
state [st'] before the assignment took place. Prove that this rule
is correct (the first hypothesis is the functional extensionality
axiom, which you will need at some point). Also note that this
rule is more complicated than [hoare_asgn].
*)
Theorem hoare_asgn_fwd :
(forall {X Y: Type} {f g : X -> Y},
(forall (x: X), f x = g x) -> f = g) ->
forall m a P,
{{fun st => P st /\ st X = m}}
X ::= a
{{fun st => P (update st X m) /\ st X = aeval (update st X m) a }}.
Proof.
intros functional_extensionality m a P.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, advanced (hoare_asgn_fwd_exists) *)
(** Another way to define a forward rule for assignment is to
existentially quantify over the previous value of the assigned
variable.
------------------------------------------ (hoare_asgn_fwd_exists)
{{fun st => P st}}
X ::= a
{{fun st => exists m, P (update st X m) /\
st X = aeval (update st X m) a }}
*)
(* This rule was proposed by Nick Giannarakis and Zoe Paraskevopoulou. *)
Theorem hoare_asgn_fwd_exists :
(forall {X Y: Type} {f g : X -> Y},
(forall (x: X), f x = g x) -> f = g) ->
forall a P,
{{fun st => P st}}
X ::= a
{{fun st => exists m, P (update st X m) /\
st X = aeval (update st X m) a }}.
Proof.
intros functional_extensionality a P.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ####################################################### *)
(** *** Consequence *)
(** Sometimes the preconditions and postconditions we get from the
Hoare rules won't quite be the ones we want in the particular
situation at hand -- they may be logically equivalent but have a
different syntactic form that fails to unify with the goal we are
trying to prove, or they actually may be logically weaker (for
preconditions) or stronger (for postconditions) than what we need.
For instance, while
{{(X = 3) [X |-> 3]}} X ::= 3 {{X = 3}},
follows directly from the assignment rule,
{{True}} X ::= 3 {{X = 3}}.
does not. This triple is valid, but it is not an instance of
[hoare_asgn] because [True] and [(X = 3) [X |-> 3]] are not
syntactically equal assertions. However, they are logically
equivalent, so if one triple is valid, then the other must
certainly be as well. We might capture this observation with the
following rule:
{{P'}} c {{Q}}
P <<->> P'
----------------------------- (hoare_consequence_pre_equiv)
{{P}} c {{Q}}
Taking this line of thought a bit further, we can see that
strengthening the precondition or weakening the postcondition of a
valid triple always produces another valid triple. This
observation is captured by two _Rules of Consequence_.
{{P'}} c {{Q}}
P ->> P'
----------------------------- (hoare_consequence_pre)
{{P}} c {{Q}}
{{P}} c {{Q'}}
Q' ->> Q
----------------------------- (hoare_consequence_post)
{{P}} c {{Q}}
*)
(** Here are the formal versions: *)
Theorem hoare_consequence_pre : forall (P P' Q : Assertion) c,
{{P'}} c {{Q}} ->
P ->> P' ->
{{P}} c {{Q}}.
Proof.
intros P P' Q c Hhoare Himp.
intros st st' Hc HP. apply (Hhoare st st').
assumption. apply Himp. assumption. Qed.
Theorem hoare_consequence_post : forall (P Q Q' : Assertion) c,
{{P}} c {{Q'}} ->
Q' ->> Q ->
{{P}} c {{Q}}.
Proof.
intros P Q Q' c Hhoare Himp.
intros st st' Hc HP.
apply Himp.
apply (Hhoare st st').
assumption. assumption. Qed.
(** For example, we might use the first consequence rule like this:
{{ True }} ->>
{{ 1 = 1 }}
X ::= 1
{{ X = 1 }}
Or, formally...
*)
Example hoare_asgn_example1 :
{{fun st => True}} (X ::= (ANum 1)) {{fun st => st X = 1}}.
Proof.
apply hoare_consequence_pre
with (P' := (fun st => st X = 1) [X |-> ANum 1]).
apply hoare_asgn.
intros st H. unfold assn_sub, update. simpl. reflexivity.
Qed.
(** Finally, for convenience in some proofs, we can state a "combined"
rule of consequence that allows us to vary both the precondition
and the postcondition.
{{P'}} c {{Q'}}
P ->> P'
Q' ->> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
*)
Theorem hoare_consequence : forall (P P' Q Q' : Assertion) c,
{{P'}} c {{Q'}} ->
P ->> P' ->
Q' ->> Q ->
{{P}} c {{Q}}.
Proof.
intros P P' Q Q' c Hht HPP' HQ'Q.
apply hoare_consequence_pre with (P' := P').
apply hoare_consequence_post with (Q' := Q').
assumption. assumption. assumption. Qed.
(* ####################################################### *)
(** *** Digression: The [eapply] Tactic *)
(** This is a good moment to introduce another convenient feature of
Coq. We had to write "[with (P' := ...)]" explicitly in the proof
of [hoare_asgn_example1] and [hoare_consequence] above, to make
sure that all of the metavariables in the premises to the
[hoare_consequence_pre] rule would be set to specific
values. (Since [P'] doesn't appear in the conclusion of
[hoare_consequence_pre], the process of unifying the conclusion
with the current goal doesn't constrain [P'] to a specific
assertion.)
This is a little annoying, both because the assertion is a bit
long and also because for [hoare_asgn_example1] the very next
thing we are going to do -- applying the [hoare_asgn] rule -- will
tell us exactly what it should be! We can use [eapply] instead of
[apply] to tell Coq, essentially, "Be patient: The missing part is
going to be filled in soon." *)
Example hoare_asgn_example1' :
{{fun st => True}}
(X ::= (ANum 1))
{{fun st => st X = 1}}.
Proof.
eapply hoare_consequence_pre.
apply hoare_asgn.
intros st H. reflexivity. Qed.
(** In general, [eapply H] tactic works just like [apply H] except
that, instead of failing if unifying the goal with the conclusion
of [H] does not determine how to instantiate all of the variables
appearing in the premises of [H], [eapply H] will replace these
variables with so-called _existential variables_ (written [?nnn])
as placeholders for expressions that will be determined (by
further unification) later in the proof. *)
(** In order for [Qed] to succeed, all existential variables need to
be determined by the end of the proof. Otherwise Coq
will (rightly) refuse to accept the proof. Remember that the Coq
tactics build proof objects, and proof objects containing
existential variables are not complete. *)
Lemma silly1 : forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(forall x y : nat, P x y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. eapply HQ. apply HP.
(** Coq gives a warning after [apply HP]:
No more subgoals but non-instantiated existential variables:
Existential 1 =
?171 : [P : nat -> nat -> Prop
Q : nat -> Prop
HP : forall x y : nat, P x y
HQ : forall x y : nat, P x y -> Q x |- nat]
(dependent evars: ?171 open,)
You can use Grab Existential Variables.
Trying to finish the proof with [Qed] gives an error:
<<
Error: Attempt to save a proof with existential variables still
non-instantiated
>> *)
Abort.
(** An additional constraint is that existential variables cannot be
instantiated with terms containing (ordinary) variables that did
not exist at the time the existential variable was created. *)
Lemma silly2 :
forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. eapply HQ. destruct HP as [y HP'].
(** Doing [apply HP'] above fails with the following error:
Error: Impossible to unify "?175" with "y".
In this case there is an easy fix:
doing [destruct HP] _before_ doing [eapply HQ].
*)
Abort.
Lemma silly2_fixed :
forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. destruct HP as [y HP'].
eapply HQ. apply HP'.
Qed.
(** In the last step we did [apply HP'] which unifies the existential
variable in the goal with the variable [y]. The [assumption]
tactic doesn't work in this case, since it cannot handle
existential variables. However, Coq also provides an [eassumption]
tactic that solves the goal if one of the premises matches the
goal up to instantiations of existential variables. We can use
it instead of [apply HP']. *)
Lemma silly2_eassumption : forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. destruct HP as [y HP']. eapply HQ. eassumption.
Qed.
(** **** Exercise: 2 stars (hoare_asgn_examples_2) *)
(** Translate these informal Hoare triples...
{{ X + 1 <= 5 }} X ::= X + 1 {{ X <= 5 }}
{{ 0 <= 3 /\ 3 <= 5 }} X ::= 3 {{ 0 <= X /\ X <= 5 }}
...into formal statements [assn_sub_ex1', assn_sub_ex2'] and
use [hoare_asgn] and [hoare_consequence_pre] to prove them. *)
Theorem assn_sub_ex1' :
{{fun st => st X + 1 <= 5}}
(X ::= APlus (AId X) (ANum 1))
{{fun st => st X <= 5}}.
Proof.
apply hoare_consequence_pre
with (P' := (fun st => st X <= 5) [X |-> APlus (AId X) (ANum 1)]).
apply hoare_asgn.
intros st H.
unfold assn_sub. simpl. rewrite update_eq. assumption.
Qed.
Theorem assn_sub_ex2' :
{{fun st => 0 <= 3 /\ 3 <= 5}}
(X ::= (ANum 3))
{{ (fun st => 0 < st X /\ st X <= 5) }}.
Proof.
apply hoare_consequence_pre
with (P' := (fun st => 0 < st X /\ st X <= 5) [X |-> ANum 3]).
apply hoare_asgn.
intros st H.
unfold assn_sub. simpl. rewrite update_eq.
omega.
Qed.
(** [] *)
(* ####################################################### *)
(** *** Skip *)
(** Since [SKIP] doesn't change the state, it preserves any
property P:
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
*)
Theorem hoare_skip : forall P,
{{P}} SKIP {{P}}.
Proof.
intros P st st' H HP. inversion H. subst.
assumption. Qed.
(* ####################################################### *)
(** *** Sequencing *)
(** More interestingly, if the command [c1] takes any state where
[P] holds to a state where [Q] holds, and if [c2] takes any
state where [Q] holds to one where [R] holds, then doing [c1]
followed by [c2] will take any state where [P] holds to one
where [R] holds:
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;;c2 {{ R }}
*)
Theorem hoare_seq : forall P Q R c1 c2,
{{Q}} c2 {{R}} ->
{{P}} c1 {{Q}} ->
{{P}} c1;;c2 {{R}}.
Proof.
intros P Q R c1 c2 H1 H2 st st' H12 Pre.
inversion H12; subst.
apply (H1 st'0 st'); try assumption.
apply (H2 st st'0); assumption. Qed.
(** Note that, in the formal rule [hoare_seq], the premises are
given in "backwards" order ([c2] before [c1]). This matches the
natural flow of information in many of the situations where we'll
use the rule: the natural way to construct a Hoare-logic proof is
to begin at the end of the program (with the final postcondition)
and push postconditions backwards through commands until we reach
the beginning. *)
(** Informally, a nice way of recording a proof using the sequencing
rule is as a "decorated program" where the intermediate assertion
[Q] is written between [c1] and [c2]:
{{ a = n }}
X ::= a;;
{{ X = n }} <---- decoration for Q
SKIP
{{ X = n }}
*)
Example hoare_asgn_example3 : forall a n,
{{fun st => aeval st a = n}}
(X ::= a;; SKIP)
{{fun st => st X = n}}.
Proof.
intros a n. eapply hoare_seq.
Case "right part of seq".
apply hoare_skip.
Case "left part of seq".
eapply hoare_consequence_pre. apply hoare_asgn.
intros st H. subst. reflexivity. Qed.
(** You will most often use [hoare_seq] and
[hoare_consequence_pre] in conjunction with the [eapply] tactic,
as done above. *)
(** **** Exercise: 2 stars (hoare_asgn_example4) *)
(** Translate this "decorated program" into a formal proof:
{{ True }} ->>
{{ 1 = 1 }}
X ::= 1;;
{{ X = 1 }} ->>
{{ X = 1 /\ 2 = 2 }}
Y ::= 2
{{ X = 1 /\ Y = 2 }}
*)
Example hoare_asgn_example4 :
{{fun st => True}} (X ::= (ANum 1);; Y ::= (ANum 2))
{{fun st => st X = 1 /\ st Y = 2}}.
Proof.
eapply hoare_seq.
apply hoare_asgn.
eapply hoare_consequence_pre.
apply hoare_asgn.
intros st HT.
unfold assn_sub.
auto.
Qed.
(** [] *)
(** **** Exercise: 3 stars (swap_exercise) *)
(** Write an Imp program [c] that swaps the values of [X] and [Y]
and show (in Coq) that it satisfies the following
specification:
{{X <= Y}} c {{Y <= X}}
*)
Definition swap_program : com :=
Z ::= AId X;; X ::= AId Y;; Y ::= AId Z.
Theorem swap_exercise :
{{fun st => st X <= st Y}}
swap_program
{{fun st => st Y <= st X}}.
Proof.
unfold swap_program.
eapply hoare_seq. eapply hoare_seq.
apply hoare_asgn. apply hoare_asgn.
Admitted.
(** [] *)
(** **** Exercise: 3 stars (hoarestate1) *)
(** Explain why the following proposition can't be proven:
forall (a : aexp) (n : nat),
{{fun st => aeval st a = n}}
(X ::= (ANum 3);; Y ::= a)
{{fun st => st Y = n}}.
*)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** *** Conditionals *)
(** What sort of rule do we want for reasoning about conditional
commands? Certainly, if the same assertion [Q] holds after
executing either branch, then it holds after the whole
conditional. So we might be tempted to write:
{{P}} c1 {{Q}}
{{P}} c2 {{Q}}
--------------------------------
{{P}} IFB b THEN c1 ELSE c2 {{Q}}
However, this is rather weak. For example, using this rule,
we cannot show that:
{{ True }}
IFB X == 0
THEN Y ::= 2
ELSE Y ::= X + 1
FI
{{ X <= Y }}
since the rule tells us nothing about the state in which the
assignments take place in the "then" and "else" branches. *)
(** But we can actually say something more precise. In the
"then" branch, we know that the boolean expression [b] evaluates to
[true], and in the "else" branch, we know it evaluates to [false].
Making this information available in the premises of the rule gives
us more information to work with when reasoning about the behavior
of [c1] and [c2] (i.e., the reasons why they establish the
postcondition [Q]). *)
(**
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
*)
(** To interpret this rule formally, we need to do a little work.
Strictly speaking, the assertion we've written, [P /\ b], is the
conjunction of an assertion and a boolean expression -- i.e., it
doesn't typecheck. To fix this, we need a way of formally
"lifting" any bexp [b] to an assertion. We'll write [bassn b] for
the assertion "the boolean expression [b] evaluates to [true] (in
the given state)." *)
Definition bassn b : Assertion :=
fun st => (beval st b = true).
(** A couple of useful facts about [bassn]: *)
Lemma bexp_eval_true : forall b st,
beval st b = true -> (bassn b) st.
Proof.
intros b st Hbe.
unfold bassn. assumption. Qed.
Lemma bexp_eval_false : forall b st,
beval st b = false -> ~ ((bassn b) st).
Proof.
intros b st Hbe contra.
unfold bassn in contra.
rewrite -> contra in Hbe. inversion Hbe. Qed.
(** Now we can formalize the Hoare proof rule for conditionals
and prove it correct. *)
Theorem hoare_if : forall P Q b c1 c2,
{{fun st => P st /\ bassn b st}} c1 {{Q}} ->
{{fun st => P st /\ ~(bassn b st)}} c2 {{Q}} ->
{{P}} (IFB b THEN c1 ELSE c2 FI) {{Q}}.
Proof.
intros P Q b c1 c2 HTrue HFalse st st' HE HP.
inversion HE; subst.
Case "b is true".
apply (HTrue st st').
assumption.
split. assumption.
apply bexp_eval_true. assumption.
Case "b is false".
apply (HFalse st st').
assumption.
split. assumption.
apply bexp_eval_false. assumption. Qed.
(* ####################################################### *)
(** * Hoare Logic: So Far *)
(**
Idea: create a _domain specific logic_ for reasoning about properties of Imp programs.
- This hides the low-level details of the semantics of the program
- Leads to a compositional reasoning process
The basic structure is given by _Hoare triples_ of the form:
{{P}} c {{Q}}
]]
- [P] and [Q] are predicates about the state of the Imp program
- "If command [c] is started in a state satisfying assertion
[P], and if [c] eventually terminates in some final state,
then this final state will satisfy the assertion [Q]."
*)
(** ** Hoare Logic Rules (so far) *)
(**
------------------------------ (hoare_asgn)
{{Q [X |-> a]}} X::=a {{Q}}
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;;c2 {{ R }}
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
{{P'}} c {{Q'}}
P ->> P'
Q' ->> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
*)
(** *** Example *)
(** Here is a formal proof that the program we used to motivate the
rule satisfies the specification we gave. *)
Example if_example :
{{fun st => True}}
IFB (BEq (AId X) (ANum 0))
THEN (Y ::= (ANum 2))
ELSE (Y ::= APlus (AId X) (ANum 1))
FI
{{fun st => st X <= st Y}}.
Proof.
(* WORKED IN CLASS *)
apply hoare_if.
Case "Then".
eapply hoare_consequence_pre. apply hoare_asgn.
unfold bassn, assn_sub, update, assert_implies.
simpl. intros st [_ H].
apply beq_nat_true in H.
rewrite H. omega.
Case "Else".
eapply hoare_consequence_pre. apply hoare_asgn.
unfold assn_sub, update, assert_implies.
simpl; intros st _. omega.
Qed.
(** **** Exercise: 2 stars (if_minus_plus) *)
(** Prove the following hoare triple using [hoare_if]: *)
Theorem if_minus_plus :
{{fun st => True}}
IFB (BLe (AId X) (AId Y))
THEN (Z ::= AMinus (AId Y) (AId X))
ELSE (Y ::= APlus (AId X) (AId Z))
FI
{{fun st => st Y = st X + st Z}}.
Proof.
(* FILL IN HERE *) Admitted.
(* ####################################################### *)
(** *** Exercise: One-sided conditionals *)
(** **** Exercise: 4 stars (if1_hoare) *)
(** In this exercise we consider extending Imp with "one-sided
conditionals" of the form [IF1 b THEN c FI]. Here [b] is a
boolean expression, and [c] is a command. If [b] evaluates to
[true], then command [c] is evaluated. If [b] evaluates to
[false], then [IF1 b THEN c FI] does nothing.
We recommend that you do this exercise before the ones that
follow, as it should help solidify your understanding of the
material. *)
(** The first step is to extend the syntax of commands and introduce
the usual notations. (We've done this for you. We use a separate
module to prevent polluting the global name space.) *)
Module If1.
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CIf1 : bexp -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "CIF1" ].
Notation "'SKIP'" :=
CSkip.
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "X '::=' a" :=
(CAss X a) (at level 60).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'IF1' b 'THEN' c 'FI'" :=
(CIf1 b c) (at level 80, right associativity).
(** Next we need to extend the evaluation relation to accommodate
[IF1] branches. This is for you to do... What rule(s) need to be
added to [ceval] to evaluate one-sided conditionals? *)
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st : state, SKIP / st || st
| E_Ass : forall (st : state) (a1 : aexp) (n : nat) (X : id),
aeval st a1 = n -> (X ::= a1) / st || update st X n
| E_Seq : forall (c1 c2 : com) (st st' st'' : state),
c1 / st || st' -> c2 / st' || st'' -> (c1 ;; c2) / st || st''
| E_IfTrue : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = true ->
c1 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = false ->
c2 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall (b1 : bexp) (st : state) (c1 : com),
beval st b1 = false -> (WHILE b1 DO c1 END) / st || st
| E_WhileLoop : forall (st st' st'' : state) (b1 : bexp) (c1 : com),
beval st b1 = true ->
c1 / st || st' ->
(WHILE b1 DO c1 END) / st' || st'' ->
(WHILE b1 DO c1 END) / st || st''
(* FILL IN HERE *)
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
(* FILL IN HERE *)
].
(** Now we repeat (verbatim) the definition and notation of Hoare triples. *)
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st',
c / st || st' ->
P st ->
Q st'.
Notation "{{ P }} c {{ Q }}" := (hoare_triple P c Q)
(at level 90, c at next level)
: hoare_spec_scope.
(** Finally, we (i.e., you) need to state and prove a theorem,
[hoare_if1], that expresses an appropriate Hoare logic proof rule
for one-sided conditionals. Try to come up with a rule that is
both sound and as precise as possible. *)
(* FILL IN HERE *)
(** For full credit, prove formally [hoare_if1_good] that your rule is
precise enough to show the following valid Hoare triple:
{{ X + Y = Z }}
IF1 Y <> 0 THEN
X ::= X + Y
FI
{{ X = Z }}
*)
(** Hint: Your proof of this triple may need to use the other proof
rules also. Because we're working in a separate module, you'll
need to copy here the rules you find necessary. *)
Lemma hoare_if1_good :
{{ fun st => st X + st Y = st Z }}
IF1 BNot (BEq (AId Y) (ANum 0)) THEN
X ::= APlus (AId X) (AId Y)
FI
{{ fun st => st X = st Z }}.
Proof. (* FILL IN HERE *) Admitted.
End If1.
(** [] *)
(* ####################################################### *)
(** *** Loops *)
(** Finally, we need a rule for reasoning about while loops. *)
(** Suppose we have a loop
WHILE b DO c END
and we want to find a pre-condition [P] and a post-condition
[Q] such that
{{P}} WHILE b DO c END {{Q}}
is a valid triple. *)
(** *** *)
(** First of all, let's think about the case where [b] is false at the
beginning -- i.e., let's assume that the loop body never executes
at all. In this case, the loop behaves like [SKIP], so we might
be tempted to write: *)
(**
{{P}} WHILE b DO c END {{P}}.
*)
(**
But, as we remarked above for the conditional, we know a
little more at the end -- not just [P], but also the fact
that [b] is false in the current state. So we can enrich the
postcondition a little:
*)
(**
{{P}} WHILE b DO c END {{P /\ ~b}}
*)
(**
What about the case where the loop body _does_ get executed?
In order to ensure that [P] holds when the loop finally
exits, we certainly need to make sure that the command [c]
guarantees that [P] holds whenever [c] is finished.
Moreover, since [P] holds at the beginning of the first
execution of [c], and since each execution of [c]
re-establishes [P] when it finishes, we can always assume
that [P] holds at the beginning of [c]. This leads us to the
following rule:
*)
(**
{{P}} c {{P}}
-----------------------------------
{{P}} WHILE b DO c END {{P /\ ~b}}
*)
(**
This is almost the rule we want, but again it can be improved a
little: at the beginning of the loop body, we know not only that
[P] holds, but also that the guard [b] is true in the current
state. This gives us a little more information to use in
reasoning about [c] (showing that it establishes the invariant by
the time it finishes). This gives us the final version of the rule:
*)
(**
{{P /\ b}} c {{P}}
----------------------------------- (hoare_while)
{{P}} WHILE b DO c END {{P /\ ~b}}
The proposition [P] is called an _invariant_ of the loop.
*)
Lemma hoare_while : forall P b c,
{{fun st => P st /\ bassn b st}} c {{P}} ->
{{P}} WHILE b DO c END {{fun st => P st /\ ~ (bassn b st)}}.
Proof.
intros P b c Hhoare st st' He HP.
(* Like we've seen before, we need to reason by induction
on [He], because, in the "keep looping" case, its hypotheses
talk about the whole loop instead of just [c]. *)
remember (WHILE b DO c END) as wcom eqn:Heqwcom.
ceval_cases (induction He) Case;
try (inversion Heqwcom); subst; clear Heqwcom.
Case "E_WhileEnd".
split. assumption. apply bexp_eval_false. assumption.
Case "E_WhileLoop".
apply IHHe2. reflexivity.
apply (Hhoare st st'). assumption.
split. assumption. apply bexp_eval_true. assumption.
Qed.
(**
One subtlety in the terminology is that calling some assertion [P]
a "loop invariant" doesn't just mean that it is preserved by the
body of the loop in question (i.e., [{{P}} c {{P}}], where [c] is
the loop body), but rather that [P] _together with the fact that
the loop's guard is true_ is a sufficient precondition for [c] to
ensure [P] as a postcondition.
This is a slightly (but significantly) weaker requirement. For
example, if [P] is the assertion [X = 0], then [P] _is_ an
invariant of the loop
WHILE X = 2 DO X := 1 END
although it is clearly _not_ preserved by the body of the
loop.
*)
Example while_example :
{{fun st => st X <= 3}}
WHILE (BLe (AId X) (ANum 2))
DO X ::= APlus (AId X) (ANum 1) END
{{fun st => st X = 3}}.
Proof.
eapply hoare_consequence_post.
apply hoare_while.
eapply hoare_consequence_pre.
apply hoare_asgn.
unfold bassn, assn_sub, assert_implies, update. simpl.
intros st [H1 H2]. apply ble_nat_true in H2. omega.
unfold bassn, assert_implies. intros st [Hle Hb].
simpl in Hb. destruct (ble_nat (st X) 2) eqn : Heqle.
apply ex_falso_quodlibet. apply Hb; reflexivity.
apply ble_nat_false in Heqle. omega.
Qed.
(** *** *)
(** We can use the while rule to prove the following Hoare triple,
which may seem surprising at first... *)
Theorem always_loop_hoare : forall P Q,
{{P}} WHILE BTrue DO SKIP END {{Q}}.
Proof.
(* WORKED IN CLASS *)
intros P Q.
apply hoare_consequence_pre with (P' := fun st : state => True).
eapply hoare_consequence_post.
apply hoare_while.
Case "Loop body preserves invariant".
apply hoare_post_true. intros st. apply I.
Case "Loop invariant and negated guard imply postcondition".
simpl. intros st [Hinv Hguard].
apply ex_falso_quodlibet. apply Hguard. reflexivity.
Case "Precondition implies invariant".
intros st H. constructor. Qed.
(** Of course, this result is not surprising if we remember that
the definition of [hoare_triple] asserts that the postcondition
must hold _only_ when the command terminates. If the command
doesn't terminate, we can prove anything we like about the
post-condition. *)
(** Hoare rules that only talk about terminating commands are
often said to describe a logic of "partial" correctness. It is
also possible to give Hoare rules for "total" correctness, which
build in the fact that the commands terminate. However, in this
course we will only talk about partial correctness. *)
(* ####################################################### *)
(** *** Exercise: [REPEAT] *)
Module RepeatExercise.
(** **** Exercise: 4 stars, advanced (hoare_repeat) *)
(** In this exercise, we'll add a new command to our language of
commands: [REPEAT] c [UNTIL] a [END]. You will write the
evaluation rule for [repeat] and add a new Hoare rule to
the language for programs involving it. *)
Inductive com : Type :=
| CSkip : com
| CAsgn : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CRepeat : com -> bexp -> com.
(** [REPEAT] behaves like [WHILE], except that the loop guard is
checked _after_ each execution of the body, with the loop
repeating as long as the guard stays _false_. Because of this,
the body will always execute at least once. *)
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE"
| Case_aux c "CRepeat" ].
Notation "'SKIP'" :=
CSkip.
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "X '::=' a" :=
(CAsgn X a) (at level 60).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'REPEAT' e1 'UNTIL' b2 'END'" :=
(CRepeat e1 b2) (at level 80, right associativity).
(** Add new rules for [REPEAT] to [ceval] below. You can use the rules
for [WHILE] as a guide, but remember that the body of a [REPEAT]
should always execute at least once, and that the loop ends when
the guard becomes true. Then update the [ceval_cases] tactic to
handle these added cases. *)
Inductive ceval : state -> com -> state -> Prop :=
| E_Skip : forall st,
ceval st SKIP st
| E_Ass : forall st a1 n X,
aeval st a1 = n ->
ceval st (X ::= a1) (update st X n)
| E_Seq : forall c1 c2 st st' st'',
ceval st c1 st' ->
ceval st' c2 st'' ->
ceval st (c1 ;; c2) st''
| E_IfTrue : forall st st' b1 c1 c2,
beval st b1 = true ->
ceval st c1 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_IfFalse : forall st st' b1 c1 c2,
beval st b1 = false ->
ceval st c2 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_WhileEnd : forall b1 st c1,
beval st b1 = false ->
ceval st (WHILE b1 DO c1 END) st
| E_WhileLoop : forall st st' st'' b1 c1,
beval st b1 = true ->
ceval st c1 st' ->
ceval st' (WHILE b1 DO c1 END) st'' ->
ceval st (WHILE b1 DO c1 END) st''
(* FILL IN HERE *)
.
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass"
| Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
(* FILL IN HERE *)
].
(** A couple of definitions from above, copied here so they use the
new [ceval]. *)
Notation "c1 '/' st '||' st'" := (ceval st c1 st')
(at level 40, st at level 39).
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion)
: Prop :=
forall st st', (c / st || st') -> P st -> Q st'.
Notation "{{ P }} c {{ Q }}" :=
(hoare_triple P c Q) (at level 90, c at next level).
(** To make sure you've got the evaluation rules for [REPEAT] right,
prove that [ex1_repeat evaluates correctly. *)
Definition ex1_repeat :=
REPEAT
X ::= ANum 1;;
Y ::= APlus (AId Y) (ANum 1)
UNTIL (BEq (AId X) (ANum 1)) END.
Theorem ex1_repeat_works :
ex1_repeat / empty_state ||
update (update empty_state X 1) Y 1.
Proof.
(* FILL IN HERE *) Admitted.
(** Now state and prove a theorem, [hoare_repeat], that expresses an
appropriate proof rule for [repeat] commands. Use [hoare_while]
as a model, and try to make your rule as precise as possible. *)
(* FILL IN HERE *)
(** For full credit, make sure (informally) that your rule can be used
to prove the following valid Hoare triple:
{{ X > 0 }}
REPEAT
Y ::= X;;
X ::= X - 1
UNTIL X = 0 END
{{ X = 0 /\ Y > 0 }}
*)
End RepeatExercise.
(** [] *)
(* ####################################################### *)
(** ** Exercise: [HAVOC] *)
(** **** Exercise: 3 stars (himp_hoare) *)
(** In this exercise, we will derive proof rules for the [HAVOC] command
which we studied in the last chapter. First, we enclose this work
in a separate module, and recall the syntax and big-step semantics
of Himp commands. *)
Module Himp.
Inductive com : Type :=
| CSkip : com
| CAsgn : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CHavoc : id -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "HAVOC" ].
Notation "'SKIP'" :=
CSkip.
Notation "X '::=' a" :=
(CAsgn X a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'HAVOC' X" := (CHavoc X) (at level 60).
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st : state, SKIP / st || st
| E_Ass : forall (st : state) (a1 : aexp) (n : nat) (X : id),
aeval st a1 = n -> (X ::= a1) / st || update st X n
| E_Seq : forall (c1 c2 : com) (st st' st'' : state),
c1 / st || st' -> c2 / st' || st'' -> (c1 ;; c2) / st || st''
| E_IfTrue : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = true ->
c1 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = false ->
c2 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall (b1 : bexp) (st : state) (c1 : com),
beval st b1 = false -> (WHILE b1 DO c1 END) / st || st
| E_WhileLoop : forall (st st' st'' : state) (b1 : bexp) (c1 : com),
beval st b1 = true ->
c1 / st || st' ->
(WHILE b1 DO c1 END) / st' || st'' ->
(WHILE b1 DO c1 END) / st || st''
| E_Havoc : forall (st : state) (X : id) (n : nat),
(HAVOC X) / st || update st X n
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
| Case_aux c "E_Havoc" ].
(** The definition of Hoare triples is exactly as before. Unlike our
notion of program equivalence, which had subtle consequences with
occassionally nonterminating commands (exercise [havoc_diverge]),
this definition is still fully satisfactory. Convince yourself of
this before proceeding. *)
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st', c / st || st' -> P st -> Q st'.
Notation "{{ P }} c {{ Q }}" := (hoare_triple P c Q)
(at level 90, c at next level)
: hoare_spec_scope.
(** Complete the Hoare rule for [HAVOC] commands below by defining
[havoc_pre] and prove that the resulting rule is correct. *)
Definition havoc_pre (X : id) (Q : Assertion) : Assertion :=
(* FILL IN HERE *) admit.
Theorem hoare_havoc : forall (Q : Assertion) (X : id),
{{ havoc_pre X Q }} HAVOC X {{ Q }}.
Proof.
(* FILL IN HERE *) Admitted.
End Himp.
(** [] *)
(* ####################################################### *)
(** ** Complete List of Hoare Logic Rules *)
(** Above, we've introduced Hoare Logic as a tool to reasoning
about Imp programs. In the reminder of this chapter we will
explore a systematic way to use Hoare Logic to prove properties
about programs. The rules of Hoare Logic are the following: *)
(**
------------------------------ (hoare_asgn)
{{Q [X |-> a]}} X::=a {{Q}}
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;;c2 {{ R }}
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
{{P /\ b}} c {{P}}
----------------------------------- (hoare_while)
{{P}} WHILE b DO c END {{P /\ ~b}}
{{P'}} c {{Q'}}
P ->> P'
Q' ->> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
In the next chapter, we'll see how these rules are used to prove
that programs satisfy specifications of their behavior.
*)
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
|
`timescale 1ns / 1ps
module test_bottleneck();
reg clk_i, reset_i;
reg [15:0] story_i;
reg [63:0] m_adr_i;
reg m_cyc_i;
reg [63:0] m_dat_i;
reg m_signed_i;
reg [1:0] m_siz_i;
reg m_stb_i;
reg m_we_i;
wire m_ack_o;
wire [63:0] m_dat_o;
wire m_err_align_o;
wire [63:0] s_adr_o;
wire s_cyc_o;
wire [15:0] s_dat_o;
wire s_signed_o;
wire s_siz_o;
wire s_stb_o;
wire s_we_o;
reg s_ack_i;
reg [15:0] s_dat_i;
bottleneck b(
.m_adr_i(m_adr_i),
.m_cyc_i(m_cyc_i),
.m_dat_i(m_dat_i),
.m_signed_i(m_signed_i),
.m_siz_i(m_siz_i),
.m_stb_i(m_stb_i),
.m_we_i(m_we_i),
.m_ack_o(m_ack_o),
.m_dat_o(m_dat_o),
.m_err_align_o(m_err_align_o),
.s_adr_o(s_adr_o),
.s_cyc_o(s_cyc_o),
.s_signed_o(s_signed_o),
.s_siz_o(s_siz_o),
.s_stb_o(s_stb_o),
.s_we_o(s_we_o),
.s_ack_i(s_ack_i),
.s_dat_i(s_dat_i),
.s_dat_o(s_dat_o),
.clk_i(clk_i),
.reset_i(reset_i)
);
always begin
#20 clk_i <= ~clk_i;
end
task tick;
input [7:0] substory;
begin
story_i <= {story_i[15:8], substory};
wait(clk_i);
wait(~clk_i);
#5;
end
endtask
task scenario;
input [7:0] story;
begin
story_i <= {story, 8'h00};
tick(8'h00);
$display("@S SCENARIO %0d (8'h%02X)", story, story);
end
endtask
task assert_s_adr_o;
input [63:0] expected;
begin
if(s_adr_o !== expected) begin
$display("@E %04X S_ADR_O Expected $%016X Got $%016X", story_i, expected, s_adr_o);
$stop;
end
end
endtask
task assert_s_cyc_o;
input expected;
begin
if(s_cyc_o !== expected) begin
$display("@E %04X S_CYC_O Expected %d Got %d", story_i, expected, s_cyc_o);
$stop;
end
end
endtask
task assert_s_signed_o;
input expected;
begin
if(s_signed_o !== expected) begin
$display("@E %04X S_SIGNED_O Expected %d Got %d", story_i, expected, s_signed_o);
$stop;
end
end
endtask
task assert_s_siz_o;
input expected;
begin
if(s_siz_o !== expected) begin
$display("@E %04X S_SIZ_O Expected %d Got %d", story_i, expected, s_siz_o);
$stop;
end
end
endtask
task assert_s_stb_o;
input expected;
begin
if(s_stb_o !== expected) begin
$display("@E %04X S_STB_O Expected %d Got %d", story_i, expected, s_stb_o);
$stop;
end
end
endtask
task assert_s_we_o;
input expected;
begin
if(s_we_o !== expected) begin
$display("@E %04X S_WE_O Expected %d Got %d", story_i, expected, s_we_o);
$stop;
end
end
endtask
task assert_s_dat_o;
input [15:0] expected;
begin
if(s_dat_o !== expected) begin
$display("@E %04X S_DAT_O Expected %04X Got %04X", story_i, expected, s_dat_o);
$stop;
end
end
endtask
task assert_m_ack_o;
input expected;
begin
if(m_ack_o !== expected) begin
$display("@E %04X M_ACK_O Expected %d Got %d", story_i, expected, m_ack_o);
$stop;
end
end
endtask
task assert_m_dat_o;
input [63:0] expected;
begin
if(m_dat_o !== expected) begin
$display("@E %04X M_DAT_O Expected %016X Got %016X", story_i, expected, m_dat_o);
$stop;
end
end
endtask
task assert_m_err_align_o;
input expected;
begin
if(m_err_align_o !== expected) begin
$display("@E %04X M_ERR_ALIGN_O Expected %d Got %d", story_i, expected, m_err_align_o);
$stop;
end
end
endtask
task test_byte_rd;
begin
scenario(1);
m_adr_i <= 64'h4444_3333_2222_1111;
m_cyc_i <= 1;
m_dat_i <= 64'h0000_0000_0000_0000;
m_signed_i <= 1;
m_siz_i <= 2'b00;
m_stb_i <= 1;
m_we_i <= 0;
tick(8'h01);
assert_m_err_align_o(0);
assert_s_adr_o(64'h4444_3333_2222_1111);
assert_s_cyc_o(1);
assert_s_signed_o(1);
assert_s_siz_o(2'b00);
assert_s_stb_o(1);
assert_s_we_o(0);
s_ack_i <= 0;
s_dat_i <= 16'h00AA;
tick(8'h02);
assert_m_ack_o(0);
s_ack_i <= 1;
tick(8'h03);
assert_m_ack_o(1);
assert_m_dat_o(64'hFFFF_FFFF_FFFF_FFAA);
m_signed_i <= 0;
tick(8'h04);
assert_m_dat_o(64'h0000_0000_0000_00AA);
end
endtask
task test_byte_wr;
begin
scenario(2);
m_adr_i <= 64'h4444_3333_2222_1111;
m_cyc_i <= 1;
m_dat_i <= 64'hAAAA_BBBB_CCCC_DDDD;
m_signed_i <= 1;
m_siz_i <= 2'b00;
m_stb_i <= 1;
m_we_i <= 1;
tick(8'h01);
assert_m_err_align_o(0);
assert_s_adr_o(64'h4444_3333_2222_1111);
assert_s_cyc_o(1);
assert_s_signed_o(1);
assert_s_siz_o(0);
assert_s_stb_o(1);
assert_s_we_o(1);
assert_s_dat_o(16'h00DD);
s_ack_i <= 0;
tick(8'h02);
assert_m_ack_o(0);
s_ack_i <= 1;
tick(8'h03);
assert_m_ack_o(1);
end
endtask
task test_hword_rd;
begin
scenario(3);
s_ack_i <= 0;
m_adr_i <= 64'h4444_3333_2222_1111;
m_cyc_i <= 1;
m_dat_i <= 64'h0000_0000_0000_0000;
m_signed_i <= 1;
m_siz_i <= 2'b01;
m_stb_i <= 1;
m_we_i <= 0;
tick(8'h01);
assert_m_err_align_o(1);
assert_m_ack_o(0);
assert_s_stb_o(0);
assert_s_cyc_o(0);
s_ack_i <= 1;
tick(8'h02);
assert_m_err_align_o(1);
assert_m_ack_o(0);
assert_s_stb_o(0);
assert_s_cyc_o(0);
m_adr_i <= 64'h4444_3333_2222_1112;
m_cyc_i <= 1;
m_dat_i <= 64'h0000_0000_0000_0000;
m_signed_i <= 1;
m_siz_i <= 2'b01;
m_stb_i <= 1;
m_we_i <= 0;
tick(8'h03);
assert_m_err_align_o(0);
assert_s_adr_o(64'h4444_3333_2222_1112);
assert_s_cyc_o(1);
assert_s_signed_o(1);
assert_s_siz_o(1);
assert_s_stb_o(1);
assert_s_we_o(0);
s_ack_i <= 0;
s_dat_i <= 16'hAA55;
tick(8'h04);
assert_m_ack_o(0);
s_ack_i <= 1;
tick(8'h05);
assert_m_ack_o(1);
assert_m_dat_o(64'hFFFF_FFFF_FFFF_AA55);
m_signed_i <= 0;
tick(8'h06);
assert_m_dat_o(64'h0000_0000_0000_AA55);
end
endtask
task test_hword_wr;
begin
scenario(4);
s_ack_i <= 1;
m_adr_i <= 64'h4444_3333_2222_1111;
m_cyc_i <= 1;
m_dat_i <= 64'hAAAA_BBBB_CCCC_DDDD;
m_signed_i <= 1;
m_siz_i <= 2'b01;
m_stb_i <= 1;
m_we_i <= 1;
tick(8'h01);
assert_m_err_align_o(1);
assert_m_ack_o(0);
assert_s_stb_o(0);
assert_s_cyc_o(0);
s_ack_i <= 0;
tick(8'h02);
assert_m_err_align_o(1);
assert_m_ack_o(0);
assert_s_stb_o(0);
assert_s_cyc_o(0);
m_adr_i <= 64'h4444_3333_2222_1112;
m_cyc_i <= 1;
m_dat_i <= 64'hAAAA_BBBB_CCCC_DDDD;
m_signed_i <= 1;
m_siz_i <= 2'b01;
m_stb_i <= 1;
m_we_i <= 1;
tick(8'h03);
assert_m_err_align_o(0);
assert_m_ack_o(0);
assert_s_adr_o(64'h4444_3333_2222_1112);
assert_s_cyc_o(1);
assert_s_signed_o(1);
assert_s_siz_o(1);
assert_s_stb_o(1);
assert_s_we_o(1);
assert_s_dat_o(16'hDDDD);
s_ack_i <= 1;
tick(8'h04);
assert_m_err_align_o(0);
assert_m_ack_o(1);
end
endtask
task test_word_rd;
begin
scenario(5);
s_ack_i <= 0;
m_adr_i <= 64'h4444_3333_2222_1111;
m_cyc_i <= 1;
m_dat_i <= 64'h0000_0000_0000_0000;
m_signed_i <= 1;
m_siz_i <= 2'b10;
m_stb_i <= 1;
m_we_i <= 0;
tick(8'h01);
assert_m_err_align_o(1);
assert_m_ack_o(0);
assert_s_stb_o(0);
assert_s_cyc_o(0);
s_ack_i <= 0;
m_adr_i <= 64'h4444_3333_2222_1112;
m_cyc_i <= 1;
m_dat_i <= 64'h0000_0000_0000_0000;
m_signed_i <= 1;
m_siz_i <= 2'b10;
m_stb_i <= 1;
m_we_i <= 0;
tick(8'h02);
assert_m_err_align_o(1);
assert_m_ack_o(0);
assert_s_stb_o(0);
assert_s_cyc_o(0);
s_ack_i <= 0;
m_adr_i <= 64'h4444_3333_2222_1113;
m_cyc_i <= 1;
m_dat_i <= 64'h0000_0000_0000_0000;
m_signed_i <= 1;
m_siz_i <= 2'b10;
m_stb_i <= 1;
m_we_i <= 0;
tick(8'h03);
assert_m_err_align_o(1);
assert_m_ack_o(0);
assert_s_stb_o(0);
assert_s_cyc_o(0);
s_ack_i <= 0;
m_adr_i <= 64'h4444_3333_2222_1114;
m_cyc_i <= 1;
m_dat_i <= 64'h0000_0000_0000_0000;
m_signed_i <= 1;
m_siz_i <= 2'b10;
m_stb_i <= 1;
m_we_i <= 0;
tick(8'h04);
assert_m_err_align_o(0);
assert_m_ack_o(0);
assert_s_adr_o(64'h4444_3333_2222_1116);
assert_s_cyc_o(1);
assert_s_signed_o(1);
assert_s_siz_o(1);
assert_s_stb_o(1);
assert_s_we_o(0);
s_ack_i <= 1;
s_dat_i <= 16'hDEAD;
tick(8'h05);
assert_m_err_align_o(0);
// NOTE: m_ack_o is asserted ONLY because we've just entered into
// the 2nd cycle of a two-cycle transaction. This means that whatever
// appears on s_ack_i will be channeled to m_ack_o. We clear s_ack_i
// below.
assert_m_ack_o(1);
assert_m_dat_o(64'hFFFF_FFFF_DEAD_DEAD);
assert_s_adr_o(64'h4444_3333_2222_1114);
assert_s_cyc_o(1);
assert_s_signed_o(1);
assert_s_siz_o(1);
assert_s_stb_o(1);
assert_s_we_o(0);
s_ack_i <= 0;
s_dat_i <= 16'hBEEF;
tick(8'h06);
assert_m_err_align_o(0);
assert_m_ack_o(0);
assert_m_dat_o(64'hFFFF_FFFF_DEAD_BEEF);
// Transient response testing.
s_ack_i <= 1;
#5;
assert_m_ack_o(1);
tick(8'h07);
#60;
assert_m_ack_o(0);
m_siz_i <= 2'b01;
#5;
assert_m_ack_o(1);
end
endtask
task test_word_wr;
begin
scenario(6);
s_ack_i <= 0;
m_adr_i <= 64'h4444_3333_2222_1114;
m_cyc_i <= 1;
m_dat_i <= 64'h1111_2222_3333_4444;
m_signed_i <= 1;
m_siz_i <= 2'b10;
m_stb_i <= 1;
m_we_i <= 1;
tick(8'h01);
assert_m_err_align_o(0);
assert_m_ack_o(0);
assert_s_adr_o(64'h4444_3333_2222_1116);
assert_s_cyc_o(1);
assert_s_signed_o(1);
assert_s_siz_o(1);
assert_s_stb_o(1);
assert_s_we_o(1);
assert_s_dat_o(16'h3333);
s_ack_i <= 1;
tick(8'h05);
assert_m_err_align_o(0);
// NOTE: m_ack_o is asserted ONLY because we've just entered into
// the 2nd cycle of a two-cycle transaction. This means that whatever
// appears on s_ack_i will be channeled to m_ack_o. We clear s_ack_i
// below.
assert_m_ack_o(1);
assert_s_adr_o(64'h4444_3333_2222_1114);
assert_s_cyc_o(1);
assert_s_signed_o(1);
assert_s_siz_o(1);
assert_s_stb_o(1);
assert_s_we_o(1);
assert_s_dat_o(16'h4444);
s_ack_i <= 0;
tick(8'h06);
assert_m_err_align_o(0);
assert_m_ack_o(0);
s_ack_i <= 1;
// NOTE: m_ack_o is asserted after the above statement becomes true.
// However, at the next clock tick, m_ack_o will drop back to 0, since
// the bridge will try to start another 32-bit write cycle again.
tick(8'h07);
assert_m_err_align_o(0);
assert_m_ack_o(0);
end
endtask
task test_dword_rd;
begin
scenario(7);
// In this test, we just drive our bus at maximum speed.
s_ack_i <= 1;
m_adr_i <= 64'h4444_3333_2222_1114;
m_cyc_i <= 1;
m_dat_i <= 64'h0000_0000_0000_0000;
m_signed_i <= 1;
m_siz_i <= 2'b11;
m_stb_i <= 1;
m_we_i <= 0;
tick(8'h01);
assert_m_err_align_o(1);
assert_m_ack_o(0);
assert_s_stb_o(0);
assert_s_cyc_o(0);
m_adr_i <= 64'h4444_3333_2222_1118;
m_cyc_i <= 1;
m_dat_i <= 64'h0000_0000_0000_0000;
m_signed_i <= 1;
m_siz_i <= 2'b11;
m_stb_i <= 1;
m_we_i <= 0;
s_ack_i <= 0;
tick(8'h02);
assert_m_err_align_o(0);
assert_m_ack_o(0);
assert_s_adr_o(64'h4444_3333_2222_111E);
assert_s_cyc_o(1);
assert_s_signed_o(1);
assert_s_siz_o(1);
assert_s_stb_o(1);
assert_s_we_o(0);
s_ack_i <= 1;
s_dat_i <= 16'hDEAD;
tick(8'h05);
assert_m_err_align_o(0);
assert_m_ack_o(0);
assert_m_dat_o(64'd0);
assert_s_adr_o(64'h4444_3333_2222_111C);
assert_s_cyc_o(1);
assert_s_signed_o(1);
assert_s_siz_o(1);
assert_s_stb_o(1);
assert_s_we_o(0);
s_dat_i <= 16'hBEEF;
tick(8'h06);
assert_m_err_align_o(0);
assert_m_ack_o(0);
assert_m_dat_o(64'd0);
assert_s_adr_o(64'h4444_3333_2222_111A);
assert_s_cyc_o(1);
assert_s_signed_o(1);
assert_s_siz_o(1);
assert_s_stb_o(1);
assert_s_we_o(0);
s_dat_i <= 16'hFEED;
tick(8'h07);
assert_m_err_align_o(0);
assert_m_ack_o(1);
assert_s_adr_o(64'h4444_3333_2222_1118);
assert_s_cyc_o(1);
assert_s_signed_o(1);
assert_s_siz_o(1);
assert_s_stb_o(1);
assert_s_we_o(0);
s_dat_i <= 16'hFACE;
#2;
assert_m_dat_o(64'hDEAD_BEEF_FEED_FACE);
tick(8'h08);
assert_m_err_align_o(0);
assert_m_ack_o(0);
end
endtask
task test_dword_wr;
begin
scenario(8);
m_cyc_i <= 0; // Reset the state of the bridge
wait(clk_i);
story_i <= 16'h0801;
s_ack_i <= 1;
m_adr_i <= 64'h4444_3333_2222_1118;
m_cyc_i <= 1;
m_dat_i <= 64'h1111_2222_3333_4444;
m_signed_i <= 1;
m_siz_i <= 2'b11;
m_stb_i <= 1;
m_we_i <= 1;
wait(~clk_i);
assert_m_err_align_o(0);
assert_m_ack_o(0);
assert_s_adr_o(64'h4444_3333_2222_111E);
assert_s_cyc_o(1);
assert_s_signed_o(1);
assert_s_siz_o(1);
assert_s_stb_o(1);
assert_s_we_o(1);
assert_s_dat_o(16'h1111);
wait(clk_i);
story_i <= 16'h0802;
s_ack_i <= 1;
m_adr_i <= 64'h4444_3333_2222_1118;
m_cyc_i <= 1;
m_dat_i <= 64'h1111_2222_3333_4444;
m_signed_i <= 1;
m_siz_i <= 2'b11;
m_stb_i <= 1;
m_we_i <= 1;
wait(~clk_i);
assert_m_err_align_o(0);
assert_m_ack_o(0);
assert_s_adr_o(64'h4444_3333_2222_111C);
assert_s_cyc_o(1);
assert_s_signed_o(1);
assert_s_siz_o(1);
assert_s_stb_o(1);
assert_s_we_o(1);
assert_s_dat_o(16'h2222);
wait(clk_i);
story_i <= 16'h0803;
s_ack_i <= 1;
m_adr_i <= 64'h4444_3333_2222_1118;
m_cyc_i <= 1;
m_dat_i <= 64'h1111_2222_3333_4444;
m_signed_i <= 1;
m_siz_i <= 2'b11;
m_stb_i <= 1;
m_we_i <= 1;
wait(~clk_i);
assert_m_err_align_o(0);
assert_m_ack_o(0);
assert_s_adr_o(64'h4444_3333_2222_111A);
assert_s_cyc_o(1);
assert_s_signed_o(1);
assert_s_siz_o(1);
assert_s_stb_o(1);
assert_s_we_o(1);
assert_s_dat_o(16'h3333);
wait(clk_i);
story_i <= 16'h0804;
s_ack_i <= 1;
m_adr_i <= 64'h4444_3333_2222_1118;
m_cyc_i <= 1;
m_dat_i <= 64'h1111_2222_3333_4444;
m_signed_i <= 1;
m_siz_i <= 2'b11;
m_stb_i <= 1;
m_we_i <= 1;
wait(~clk_i);
assert_m_err_align_o(0);
assert_m_ack_o(1);
assert_s_adr_o(64'h4444_3333_2222_1118);
assert_s_cyc_o(1);
assert_s_signed_o(1);
assert_s_siz_o(1);
assert_s_stb_o(1);
assert_s_we_o(1);
assert_s_dat_o(16'h4444);
wait(clk_i);
end
endtask
initial begin
// $dumpfile("wtf.vcd");
// $dumpvars;
clk_i <= 0;
reset_i <= 0;
story_i <= 0;
tick(8'h00);
test_byte_rd();
test_byte_wr();
test_hword_rd();
test_hword_wr();
test_word_rd();
test_word_wr();
test_dword_rd();
test_dword_wr();
$display("@I Done.");
$stop;
end
endmodule
|
// File bigfile.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
// vhd2vl settings:
// * Verilog Module Declaration Style: 1995
// vhd2vl is Free (libre) Software:
// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
// http://www.ocean-logic.com
// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
// Modifications (C) 2010 Shankar Giri
// Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
// http://doolittle.icarus.com/~larry/vhd2vl/
//
// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
// Verilog for correctness, ideally with a formal verification tool.
//
// You are welcome to redistribute vhd2vl under certain conditions.
// See the license (GPLv2) file included with the source for details.
// The result of translation follows. Its copyright status should be
// considered unchanged from the original VHDL.
// CONNECTIVITY DEFINITION
// no timescale needed
module bigfile(
sysclk,
g_zaq_in,
g_aux,
scanb,
g_wrb,
g_rdb,
g_noop_clr,
swe_ed,
swe_lv,
din,
g_dout_w0x0f,
n9_bit_write,
reset,
alu_u,
debct_ping,
g_sys_in,
g_zaq_in_rst_hold,
g_zaq_hhh_enb,
g_zaq_out,
g_dout,
g_zaq_ctl,
g_zaq_qaz_hb,
g_zaq_qaz_lb,
gwerth,
g_noop,
g_vector,
swe_qaz1
);
// from external pins
input sysclk;
input [31:0] g_zaq_in;
input [31:0] g_aux;
input scanb;
input g_wrb;
input g_rdb;
input [31:0] g_noop_clr;
input swe_ed;
input swe_lv;
input [63:0] din;
input [4:0] g_dout_w0x0f;
input n9_bit_write;
// from reset_gen block
input reset;
input [31:0] alu_u;
input debct_ping;
output [31:0] g_sys_in;
output [31:0] g_zaq_in_rst_hold;
output [31:0] g_zaq_hhh_enb;
output [31:0] g_zaq_out;
output [31:0] g_dout;
output [31:0] g_zaq_ctl;
output [31:0] g_zaq_qaz_hb;
output [31:0] g_zaq_qaz_lb;
output [31:0] gwerth;
output [31:0] g_noop;
output [8 * 32 - 1:0] g_vector;
output [31:0] swe_qaz1;
wire sysclk;
wire [31:0] g_zaq_in;
wire [31:0] g_aux;
wire scanb;
wire g_wrb;
wire g_rdb;
wire [31:0] g_noop_clr;
wire swe_ed;
wire swe_lv;
wire [63:0] din;
wire [4:0] g_dout_w0x0f;
wire n9_bit_write;
wire reset;
wire [31:0] alu_u;
wire debct_ping;
wire [31:0] g_sys_in;
wire [31:0] g_zaq_in_rst_hold;
wire [31:0] g_zaq_hhh_enb;
wire [31:0] g_zaq_out;
wire [31:0] g_dout;
wire [31:0] g_zaq_ctl;
wire [31:0] g_zaq_qaz_hb;
wire [31:0] g_zaq_qaz_lb;
reg [31:0] gwerth;
wire [31:0] g_noop;
reg [8 * 32 - 1:0] g_vector;
reg [31:0] swe_qaz1;
// IMPLEMENTATION
// constants
parameter g_t_klim_w0x0f = 5'b 00000;
parameter g_t_u_w0x0f = 5'b 00001;
parameter g_t_l_w0x0f = 5'b 00010;
parameter g_t_hhh_l_w0x0f = 5'b 00011;
parameter g_t_jkl_sink_l_w0x0f = 5'b 00100;
parameter g_secondary_t_l_w0x0f = 5'b 00101;
parameter g_style_c_l_w0x0f = 5'b 00110;
parameter g_e_z_w0x0f = 5'b 00111;
parameter g_n_both_qbars_l_w0x0f = 5'b 01000;
parameter g_style_vfr_w0x0f = 5'b 01001;
parameter g_style_klim_w0x0f = 5'b 01010;
parameter g_unklimed_style_vfr_w0x0f = 5'b 01011;
parameter g_style_t_y_w0x0f = 5'b 01100;
parameter g_n_l_w0x0f = 5'b 01101;
parameter g_n_vfr_w0x0f = 5'b 01110;
parameter g_e_n_r_w0x0f = 5'b 01111;
parameter g_n_r_bne_w0x0f = 5'b 10000;
parameter g_n_div_rebeq_w0x0f = 5'b 10001;
parameter g_alu_l_w0x0f = 5'b 10010;
parameter g_t_qaz_mult_low_w0x0f = 5'b 10011;
parameter g_t_qaz_mult_high_w0x0f = 5'b 10100;
parameter gwerthernal_style_u_w0x0f = 5'b 10101;
parameter gwerthernal_style_l_w0x0f = 5'b 10110;
parameter g_style_main_reset_hold_w0x0f = 5'b 10111; // comment
reg [31:0] g_t_klim_dout;
reg [31:0] g_t_u_dout;
reg [31:0] g_t_l_dout;
reg [31:0] g_t_hhh_l_dout;
reg [31:0] g_t_jkl_sink_l_dout;
reg [31:0] g_secondary_t_l_dout;
reg [3:0] g_style_c_l_dout; // not used
reg [31:0] g_e_z_dout;
reg [31:0] g_n_both_qbars_l_dout;
wire [31:0] g_style_vfr_dout;
reg [31:0] g_style_klim_dout;
wire [31:0] g_unklimed_style_vfr_dout;
reg [31:0] g_style_t_y_dout;
reg [31:0] g_n_l_dout;
reg [31:0] g_n_vfr_dout;
reg [31:0] g_e_n_r_dout;
reg g_n_r_bne_dout;
reg [31:0] g_n_div_rebeq_dout;
reg [31:0] g_alu_l_dout;
reg [31:0] g_t_qaz_mult_low_dout;
reg [31:0] g_t_qaz_mult_high_dout;
reg [31:0] gwerthernal_style_u_dout;
reg [31:0] gwerthernal_style_l_dout;
reg [31:0] g_style_main_reset_hold_dout; // other
reg [31:0] q_g_zaq_in;
reg [31:0] q2_g_zaq_in;
reg [31:0] q3_g_zaq_in;
reg [3:0] q_g_zaq_in_cd;
reg [31:0] q_g_style_vfr_dout;
reg [3:0] q_g_unzq; // i
wire [31:0] g_n_active; // inter
wire [31:0] g_zaq_in_y;
wire [31:0] g_zaq_in_y_no_dout;
wire [31:0] g_zaq_out_i;
wire [31:0] g_zaq_ctl_i;
wire [31:0] g_sys_in_i;
wire [31:0] g_sys_in_ii;
wire [31:0] g_dout_i;
// qaz out
assign g_zaq_out_i = ((g_secondary_t_l_dout & ((g_aux ^ g_style_t_y_dout)))) | ((g_alu_l_dout & alu_u & ~g_secondary_t_l_dout)) | (( ~g_alu_l_dout & ~g_secondary_t_l_dout & g_t_u_dout));
// Changed
assign g_zaq_out = g_zaq_out_i & ~g_t_jkl_sink_l_dout;
// qaz
// JLB
assign g_zaq_ctl_i = ~((((g_t_l_dout & ~g_t_jkl_sink_l_dout)) | ((g_t_l_dout & g_t_jkl_sink_l_dout & ~g_zaq_out_i))));
// mux
//vnavigatoroff
assign g_zaq_ctl = scanb == 1'b 1 ? g_zaq_ctl_i : 32'b 00000000000000000000000000000000;
//vnavigatoron
assign g_zaq_hhh_enb = ~((g_t_hhh_l_dout));
assign g_zaq_qaz_hb = g_t_qaz_mult_high_dout;
assign g_zaq_qaz_lb = g_t_qaz_mult_low_dout;
// Dout
assign g_dout_i = g_dout_w0x0f == g_t_klim_w0x0f ? g_t_klim_dout & g_style_klim_dout : g_dout_w0x0f == g_t_u_w0x0f ? g_t_u_dout & g_style_klim_dout : g_dout_w0x0f == g_t_l_w0x0f ? g_t_l_dout & g_style_klim_dout : g_dout_w0x0f == g_t_hhh_l_w0x0f ? g_t_hhh_l_dout & g_style_klim_dout : g_dout_w0x0f == g_t_jkl_sink_l_w0x0f ? g_t_jkl_sink_l_dout & g_style_klim_dout : g_dout_w0x0f == g_secondary_t_l_w0x0f ? g_secondary_t_l_dout & g_style_klim_dout : g_dout_w0x0f == g_style_c_l_w0x0f ? ({28'b 0000000000000000000000000000,g_style_c_l_dout}) & g_style_klim_dout : g_dout_w0x0f == g_e_z_w0x0f ? g_e_z_dout : g_dout_w0x0f == g_n_both_qbars_l_w0x0f ? g_n_both_qbars_l_dout : g_dout_w0x0f == g_style_vfr_w0x0f ? g_style_vfr_dout & g_style_klim_dout : g_dout_w0x0f == g_style_klim_w0x0f ? g_style_klim_dout : g_dout_w0x0f == g_unklimed_style_vfr_w0x0f ? g_unklimed_style_vfr_dout : g_dout_w0x0f == g_style_t_y_w0x0f ? g_style_t_y_dout & g_style_klim_dout : g_dout_w0x0f == g_n_l_w0x0f ? g_n_l_dout : g_dout_w0x0f == g_n_vfr_w0x0f ? g_n_vfr_dout : g_dout_w0x0f == g_e_n_r_w0x0f ? g_e_n_r_dout : g_dout_w0x0f == g_n_r_bne_w0x0f ? {31'b 0000000000000000000000000000000,g_n_r_bne_dout} : g_dout_w0x0f == g_n_div_rebeq_w0x0f ? g_n_div_rebeq_dout : g_dout_w0x0f == g_alu_l_w0x0f ? g_alu_l_dout & g_style_klim_dout : g_dout_w0x0f == g_t_qaz_mult_low_w0x0f ? g_t_qaz_mult_low_dout & g_style_klim_dout : g_dout_w0x0f == g_t_qaz_mult_high_w0x0f ? g_t_qaz_mult_high_dout & g_style_klim_dout : g_dout_w0x0f == gwerthernal_style_u_w0x0f ? gwerthernal_style_u_dout & g_style_klim_dout : g_dout_w0x0f == g_style_main_reset_hold_w0x0f ? g_style_main_reset_hold_dout & g_style_klim_dout : g_dout_w0x0f == gwerthernal_style_l_w0x0f ? gwerthernal_style_l_dout & g_style_klim_dout : 32'b 00000000000000000000000000000000;
assign g_dout = g_rdb == 1'b 0 ? g_dout_i : {32{1'b1}};
// this can be used to use zzz1
always @(posedge sysclk) begin
if((scanb == 1'b 1)) begin
if((reset == 1'b 1)) begin
g_style_main_reset_hold_dout <= g_zaq_in;
end
//vnavigatoroff
end
else begin
g_style_main_reset_hold_dout <= q2_g_zaq_in;
end
//vnavigatoron
end
// qaz
assign g_zaq_in_rst_hold = g_style_main_reset_hold_dout;
// Din
always @(posedge reset or posedge sysclk) begin : P2
reg [4:0] g_dout_w0x0f_v;
if((reset != 1'b 0)) begin
g_t_klim_dout <= {32{1'b0}};
g_t_u_dout <= {32{1'b0}};
g_t_l_dout <= {32{1'b0}};
g_t_hhh_l_dout <= {32{1'b0}};
g_t_jkl_sink_l_dout <= {32{1'b0}};
g_secondary_t_l_dout <= {32{1'b0}};
g_style_c_l_dout <= {4{1'b0}};
g_e_z_dout <= {32{1'b0}};
g_n_both_qbars_l_dout <= {32{1'b0}};
g_style_klim_dout <= {32{1'b0}};
g_style_t_y_dout <= {32{1'b0}};
g_n_l_dout <= {32{1'b0}};
g_e_n_r_dout <= {32{1'b0}};
g_n_r_bne_dout <= 1'b 0;
g_n_div_rebeq_dout <= {32{1'b1}};
g_alu_l_dout <= {32{1'b0}};
g_t_qaz_mult_low_dout <= {32{1'b1}};
// NOTE Low
g_t_qaz_mult_high_dout <= {32{1'b0}};
gwerthernal_style_u_dout <= {32{1'b0}};
gwerthernal_style_l_dout <= {32{1'b0}};
end else begin
// clear
g_n_div_rebeq_dout <= g_n_div_rebeq_dout & ~g_noop_clr;
if((g_wrb == 1'b 0)) begin
// because we now...
for (i=0; i <= 1; i = i + 1) begin
if((i == 0)) begin
g_dout_w0x0f_v = g_dout_w0x0f;
end
else if((i == 1)) begin
if((n9_bit_write == 1'b 1)) begin
// set
g_dout_w0x0f_v = {g_dout_w0x0f[4:1],1'b 1};
end
else begin
disable; //VHD2VL: add block name here
end
//vnavigatoroff
end
else begin
// not possible but added for code coverage's sake
end
//vnavigatoron
case(g_dout_w0x0f_v)
g_t_klim_w0x0f : begin
g_t_klim_dout <= din[i * 32 + 31:i * 32];
end
g_t_u_w0x0f : begin
// output klim
for (j=0; j <= 31; j = j + 1) begin
if(((g_t_klim_dout[j] == 1'b 0 && n9_bit_write == 1'b 0) || (din[j] == 1'b 0 && n9_bit_write == 1'b 1))) begin
g_t_u_dout[j] <= din[32 * i + j];
end
end
end
g_t_l_w0x0f : begin
g_t_l_dout <= din[i * 32 + 31:i * 32];
end
g_t_hhh_l_w0x0f : begin
g_t_hhh_l_dout <= din[i * 32 + 31:i * 32];
end
g_t_jkl_sink_l_w0x0f : begin
g_t_jkl_sink_l_dout <= din[i * 32 + 31:i * 32];
end
g_secondary_t_l_w0x0f : begin
g_secondary_t_l_dout <= din[i * 32 + 31:i * 32];
end
g_style_c_l_w0x0f : begin
g_style_c_l_dout[3:0] <= din[3 + i * 32:i * 32];
end
g_e_z_w0x0f : begin
g_e_z_dout <= din[i * 32 + 31:i * 32];
end
g_n_both_qbars_l_w0x0f : begin
g_n_both_qbars_l_dout <= din[i * 32 + 31:i * 32];
end
g_style_vfr_w0x0f : begin
// read-only register
end
g_style_klim_w0x0f : begin
g_style_klim_dout <= din[i * 32 + 31:i * 32];
end
g_unklimed_style_vfr_w0x0f : begin
// read-only register
end
g_style_t_y_w0x0f : begin
g_style_t_y_dout <= din[i * 32 + 31:i * 32];
end
g_n_l_w0x0f : begin
g_n_l_dout <= din[i * 32 + 31:i * 32];
end
g_n_vfr_w0x0f : begin
// writes
end
g_e_n_r_w0x0f : begin
g_e_n_r_dout <= din[i * 32 + 31:i * 32];
end
g_n_r_bne_w0x0f : begin
g_n_r_bne_dout <= din[i * 32];
end
g_n_div_rebeq_w0x0f : begin
g_n_div_rebeq_dout <= din[i * 32 + 31:i * 32] | g_n_div_rebeq_dout;
// a '1' writes
end
g_alu_l_w0x0f : begin
g_alu_l_dout <= din[i * 32 + 31:i * 32];
end
g_t_qaz_mult_low_w0x0f : begin
g_t_qaz_mult_low_dout <= din[i * 32 + 31:i * 32];
end
g_t_qaz_mult_high_w0x0f : begin
g_t_qaz_mult_high_dout <= din[i * 32 + 31:i * 32];
end
gwerthernal_style_u_w0x0f : begin
gwerthernal_style_u_dout <= din[i * 32 + 31:i * 32];
end
gwerthernal_style_l_w0x0f : begin
gwerthernal_style_l_dout <= din[i * 32 + 31:i * 32];
//vnavigatoroff
end
default : begin
//vnavigatoron
end
endcase
end
end
end
end
// sample
always @(posedge reset or posedge sysclk) begin
if((reset != 1'b 0)) begin
q_g_zaq_in <= {32{1'b0}};
q2_g_zaq_in <= {32{1'b0}};
q3_g_zaq_in <= {32{1'b0}};
end else begin
q_g_zaq_in <= g_zaq_in;
q2_g_zaq_in <= q_g_zaq_in;
q3_g_zaq_in <= g_zaq_in_y;
end
end
// vfr register
assign g_unklimed_style_vfr_dout = q2_g_zaq_in;
// switch
assign g_zaq_in_y = g_style_t_y_dout ^ q2_g_zaq_in;
// qaz
assign g_style_vfr_dout = {g_zaq_in_y[31:4],(((g_style_c_l_dout[3:0] & q_g_zaq_in_cd)) | (( ~g_style_c_l_dout[3:0] & g_zaq_in_y[3:0])))};
// in scan mode
assign g_zaq_in_y_no_dout = scanb == 1'b 1 ? (g_style_t_y_dout ^ g_zaq_in) : g_style_t_y_dout;
//vnavigatoron
assign g_sys_in_i = ({g_zaq_in_y_no_dout[31:4],(((g_style_c_l_dout[3:0] & q_g_zaq_in_cd)) | (( ~g_style_c_l_dout[3:0] & g_zaq_in_y_no_dout[3:0])))});
assign g_sys_in_ii = ((g_sys_in_i & ~gwerthernal_style_l_dout)) | ((gwerthernal_style_u_dout & gwerthernal_style_l_dout));
assign g_sys_in = g_sys_in_ii;
always @(posedge reset or posedge sysclk) begin
if((reset != 1'b 0)) begin
q_g_zaq_in_cd <= {4{1'b0}};
q_g_unzq <= {4{1'b1}};
end else begin
// sample
if((debct_ping == 1'b 1)) begin
// taken
for (i=0; i <= 3; i = i + 1) begin
if((g_zaq_in_y[i] != q3_g_zaq_in[i])) begin
q_g_unzq[i] <= 1'b 1;
end
else begin
if((q_g_unzq[i] == 1'b 0)) begin
q_g_zaq_in_cd[i] <= g_zaq_in_y[i];
end
else begin
q_g_unzq[i] <= 1'b 0;
end
end
end
end
else begin
for (i=0; i <= 3; i = i + 1) begin
if((g_zaq_in_y[i] != q3_g_zaq_in[i])) begin
q_g_unzq[i] <= 1'b 1;
end
end
end
end
end
// generate lqqs
always @(posedge reset or posedge sysclk) begin
if((reset != 1'b 0)) begin
q_g_style_vfr_dout <= {32{1'b0}};
end else begin
if((scanb == 1'b 1)) begin
q_g_style_vfr_dout <= g_style_vfr_dout;
//vnavigatoroff
end
else begin
// in scan
q_g_style_vfr_dout <= g_style_vfr_dout | ({g_zaq_out_i[31:17],1'b 0,g_zaq_out_i[15:1],1'b 0}) | g_zaq_ctl_i | g_sys_in_ii;
end
//vnavigatoron
end
end
// generate
assign g_n_active = (((((q_g_style_vfr_dout & ~g_style_vfr_dout)) | (( ~q_g_style_vfr_dout & g_style_vfr_dout & g_n_both_qbars_l_dout))))) & g_n_l_dout;
// check for lqq active and set lqq vfr register
// also clear
always @(posedge reset or posedge sysclk) begin
if((reset != 1'b 0)) begin
g_n_vfr_dout <= {32{1'b0}};
gwerth <= {32{1'b0}};
end else begin
for (i=0; i <= 31; i = i + 1) begin
// lqq
// vfr matches
if((g_n_active[i] == 1'b 1)) begin
gwerth[i] <= 1'b 1;
if((g_e_z_dout[i] == 1'b 1)) begin
// lqq
g_n_vfr_dout[i] <= 1'b 1;
end
else begin
g_n_vfr_dout[i] <= q_g_style_vfr_dout[i];
end
end
else begin
// clear
if((g_e_z_dout[i] == 1'b 0)) begin
g_n_vfr_dout[i] <= q_g_style_vfr_dout[i];
// default always assign
// in both
if((g_n_both_qbars_l_dout[i] == 1'b 1 || g_style_vfr_dout[i] == 1'b 1)) begin
gwerth[i] <= 1'b 0;
end
end
else begin
// write
if((g_wrb == 1'b 0 && g_dout_w0x0f == g_n_vfr_w0x0f && din[i] == 1'b 1)) begin
gwerth[i] <= 1'b 0;
g_n_vfr_dout[i] <= 1'b 0;
end
end
end
end
end
end
//--
// Create the Lqq
always @(g_n_r_bne_dout or g_e_n_r_dout) begin : P1
reg [31:0] imod8, idiv8;
for (i=0; i <= 31; i = i + 1) begin
imod8 = i % 8;
idiv8 = i / 8;
if((g_n_r_bne_dout == 1'b 0)) begin
// non-unique
g_vector[8 * i + 7:8 * i] <= g_e_n_r_dout[8 * idiv8 + 7:8 * idiv8];
end
else begin
// unique
if((imod8 == 0)) begin
g_vector[8 * i + 7:8 * i] <= g_e_n_r_dout[8 * idiv8 + 7:8 * idiv8];
end
else begin
g_vector[8 * i + 7:8 * i] <= (((g_e_n_r_dout[8 * idiv8 + 7:8 * idiv8])) + ((imod8)));
end
end
end
end
//--
// Qaz
assign g_noop = g_n_div_rebeq_dout;
always @(swe_ed or swe_lv or g_e_z_dout) begin
for (i=0; i <= 31; i = i + 1) begin
if((g_e_z_dout[i] == 1'b 1)) begin
swe_qaz1[i] <= swe_ed;
end
else begin
swe_qaz1[i] <= swe_lv;
end
end
end
endmodule
|
/*
Anthony De Caria - April 4, 2014
This module creates a Shift Register with a seperate enable signal.
This specific module creates an output that is 16-bits wide.
This module uses asyncronous D Flip Flops.
It also can allow data to be inputed into the flip flops before shifting.
*/
module ShiftRegisterWEnableSixteenAsyncMuxedInput(clk, resetn, enable, select, d, q);
//Define the inputs and outputs
input clk;
input resetn;
input enable;
input select;
input [15:0] d;
output [15:0] q;
wire [15:1]muxOut;
mux2to1_1bit One_mux(.data1x(d[1]), .data0x(q[0]), .sel(select), .result(muxOut[1]) );
mux2to1_1bit Two_mux(.data1x(d[2]), .data0x(q[1]), .sel(select), .result(muxOut[2]) );
mux2to1_1bit Three_mux(.data1x(d[3]), .data0x(q[2]), .sel(select), .result(muxOut[3]) );
mux2to1_1bit Four_mux(.data1x(d[4]), .data0x(q[3]), .sel(select), .result(muxOut[4]) );
mux2to1_1bit Five_mux(.data1x(d[5]), .data0x(q[4]), .sel(select), .result(muxOut[5]) );
mux2to1_1bit Six_mux(.data1x(d[6]), .data0x(q[5]), .sel(select), .result(muxOut[6]) );
mux2to1_1bit Seven_mux(.data1x(d[7]), .data0x(q[6]), .sel(select), .result(muxOut[7]) );
mux2to1_1bit Eight_mux(.data1x(d[8]), .data0x(q[7]), .sel(select), .result(muxOut[8]) );
mux2to1_1bit Nine_mux(.data1x(d[9]), .data0x(q[8]), .sel(select), .result(muxOut[9]) );
mux2to1_1bit Ten_mux(.data1x(d[10]), .data0x(q[9]), .sel(select), .result(muxOut[10]) );
mux2to1_1bit Eleven_mux(.data1x(d[11]), .data0x(q[10]), .sel(select), .result(muxOut[11]) );
mux2to1_1bit Twelve_mux(.data1x(d[12]), .data0x(q[11]), .sel(select), .result(muxOut[12]) );
mux2to1_1bit Thirteen_mux(.data1x(d[13]), .data0x(q[12]), .sel(select), .result(muxOut[13]) );
mux2to1_1bit Fourteen_mux(.data1x(d[14]), .data0x(q[13]), .sel(select), .result(muxOut[14]) );
mux2to1_1bit Fifteen_mux(.data1x(d[15]), .data0x(q[14]), .sel(select), .result(muxOut[15]) );
D_FF_with_Enable Zero(.clk(clk), .resetn(resetn), .enable(enable), .d(d[0]), .q(q[0]) );
D_FF_with_Enable One(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[1]), .q(q[1]) );
D_FF_with_Enable Two(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[2]), .q(q[2]) );
D_FF_with_Enable Three(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[3]), .q(q[3]) );
D_FF_with_Enable Four(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[4]), .q(q[4]) );
D_FF_with_Enable Five(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[5]), .q(q[5]) );
D_FF_with_Enable Six(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[6]), .q(q[6]) );
D_FF_with_Enable Seven(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[7]), .q(q[7]) );
D_FF_with_Enable Eight(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[8]), .q(q[8]) );
D_FF_with_Enable Nine(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[9]), .q(q[9]) );
D_FF_with_Enable Ten(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[10]), .q(q[10]) );
D_FF_with_Enable Eleven(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[11]), .q(q[11]) );
D_FF_with_Enable Twelve(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[12]), .q(q[12]) );
D_FF_with_Enable Thirteen(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[13]), .q(q[13]) );
D_FF_with_Enable Fourteen(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[14]), .q(q[14]) );
D_FF_with_Enable Fifteen(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[15]), .q(q[15]) );
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND3_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__NAND3_FUNCTIONAL_V
/**
* nand3: 3-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__nand3 (
Y,
A,
B,
C
);
// Module ports
output Y;
input A;
input B;
input C;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, B, A, C );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND3_FUNCTIONAL_V |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Thu Sep 28 09:34:25 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_rx_inst_stub.v
// Design : fifo_generator_rx_inst
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, rst, din, wr_en, rd_en, dout, full, empty)
/* synthesis syn_black_box black_box_pad_pin="clk,rst,din[63:0],wr_en,rd_en,dout[63:0],full,empty" */;
input clk;
input rst;
input [63:0]din;
input wr_en;
input rd_en;
output [63:0]dout;
output full;
output empty;
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.92
// \ \ Application : MIG
// / / Filename : round_robin_arb.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : Virtex-6
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// A simple round robin arbiter implemented in a not so simple
// way. Two things make this special. First, it takes width as
// a parameter and secondly it's constructed in a way to work with
// restrictions synthesis programs.
//
// Consider each req/grant pair to be a
// "channel". The arbiter computes a grant response to a request
// on a channel by channel basis.
//
// The arbiter implementes a "round robin" algorithm. Ie, the granting
// process is totally fair and symmetric. Each requester is given
// equal priority. If all requests are asserted, the arbiter will
// work sequentially around the list of requesters, giving each a grant.
//
// Grant priority is based on the "last_master". The last_master
// vector stores the channel receiving the most recent grant. The
// next higher numbered channel (wrapping around to zero) has highest
// priority in subsequent cycles. Relative priority wraps around
// the request vector with the last_master channel having lowest priority.
//
// At the highest implementation level, a per channel inhibit signal is computed.
// This inhibit is bit-wise AND'ed with the incoming requests to
// generate the grant.
//
// There will be at most a single grant per state. The logic
// of the arbiter depends on this.
//
// Once a grant is given, it is stored as the last_master. The
// last_master vector is initialized at reset to the zero'th channel.
// Although the particular channel doesn't matter, it does matter
// that the last_master contains a valid grant pattern.
//
// The heavy lifting is in computing the per channel inhibit signals.
// This is accomplished in the generate statement.
//
// The first "for" loop in the generate statement steps through the channels.
//
// The second "for" loop steps through the last mast_master vector
// for each channel. For each last_master bit, an inh_group is generated.
// Following the end of the second "for" loop, the inh_group signals are OR'ed
// together to generate the overall inhibit bit for the channel.
//
// For a four bit wide arbiter, this is what's generated for channel zero:
//
// inh_group[1] = last_master[0] && |req[3:1]; // any other req inhibits
// inh_group[2] = last_master[1] && |req[3:2]; // req[3], or req[2] inhibit
// inh_group[3] = last_master[2] && |req[3:3]; // only req[3] inhibits
//
// For req[0], last_master[3] is ignored because channel zero is highest priority
// if last_master[3] is true.
//
`timescale 1ps/1ps
module round_robin_arb
#(
parameter TCQ = 100,
parameter WIDTH = 3
)
(
/*AUTOARG*/
// Outputs
grant_ns, grant_r,
// Inputs
clk, rst, req, disable_grant, current_master, upd_last_master
);
input clk;
input rst;
input [WIDTH-1:0] req;
wire [WIDTH-1:0] last_master_ns;
reg [WIDTH*2-1:0] dbl_last_master_ns;
always @(/*AS*/last_master_ns)
dbl_last_master_ns = {last_master_ns, last_master_ns};
reg [WIDTH*2-1:0] dbl_req;
always @(/*AS*/req) dbl_req = {req, req};
reg [WIDTH-1:0] inhibit = {WIDTH{1'b0}};
genvar i;
genvar j;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : channel
wire [WIDTH-1:1] inh_group;
for (j = 0; j < (WIDTH-1); j = j + 1) begin : last_master
assign inh_group[j+1] =
dbl_last_master_ns[i+j] && |dbl_req[i+WIDTH-1:i+j+1];
end
always @(/*AS*/inh_group) inhibit[i] = |inh_group;
end
endgenerate
input disable_grant;
output wire [WIDTH-1:0] grant_ns;
assign grant_ns = req & ~inhibit & {WIDTH{~disable_grant}};
output reg [WIDTH-1:0] grant_r;
always @(posedge clk) grant_r <= #TCQ grant_ns;
input [WIDTH-1:0] current_master;
input upd_last_master;
reg [WIDTH-1:0] last_master_r;
localparam ONE = 1 << (WIDTH - 1); //Changed form '1' to fix the CR #544024
//A '1' in the LSB of the last_master_r
//signal gives a low priority to req[0]
//after reset. To avoid this made MSB as
//'1' at reset.
assign last_master_ns = rst
? ONE[0+:WIDTH]
: upd_last_master
? current_master
: last_master_r;
always @(posedge clk) last_master_r <= #TCQ last_master_ns;
`ifdef MC_SVA
grant_is_one_hot_zero:
assert property (@(posedge clk) (rst || $onehot0(grant_ns)));
last_master_r_is_one_hot:
assert property (@(posedge clk) (rst || $onehot(last_master_r)));
`endif
endmodule
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.4
// \ \ Application: MIG
// / / Filename: ddr2_usr_wr.v
// /___/ /\ Date Last Modified: $Date: 2009/11/03 04:43:18 $
// \ \ / \ Date Created: Mon Aug 28 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR/DDR2
//Purpose:
// This module instantiates the modules containing internal FIFOs
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_usr_wr #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module mig_v3_4 module. Please refer to
// the mig_v3_4 module for actual values.
parameter BANK_WIDTH = 2,
parameter COL_WIDTH = 10,
parameter CS_BITS = 0,
parameter DQ_WIDTH = 72,
parameter APPDATA_WIDTH = 144,
parameter ECC_ENABLE = 0,
parameter ROW_WIDTH = 14
)
(
input clk0,
input clk90,
input rst0,
// Write data FIFO interface
input app_wdf_wren,
input [APPDATA_WIDTH-1:0] app_wdf_data,
input [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data,
input wdf_rden,
output app_wdf_afull,
output [(2*DQ_WIDTH)-1:0] wdf_data,
output [((2*DQ_WIDTH)/8)-1:0] wdf_mask_data
);
// determine number of FIFO72's to use based on data width
// round up to next integer value when determining WDF_FIFO_NUM
localparam WDF_FIFO_NUM = (ECC_ENABLE) ? (APPDATA_WIDTH+63)/64 :
((2*DQ_WIDTH)+63)/64;
// MASK_WIDTH = number of bytes in data bus
localparam MASK_WIDTH = DQ_WIDTH/8;
wire [WDF_FIFO_NUM-1:0] i_wdf_afull;
wire [DQ_WIDTH-1:0] i_wdf_data_fall_in;
wire [DQ_WIDTH-1:0] i_wdf_data_fall_out;
wire [(64*WDF_FIFO_NUM)-1:0] i_wdf_data_in;
wire [(64*WDF_FIFO_NUM)-1:0] i_wdf_data_out;
wire [DQ_WIDTH-1:0] i_wdf_data_rise_in;
wire [DQ_WIDTH-1:0] i_wdf_data_rise_out;
wire [MASK_WIDTH-1:0] i_wdf_mask_data_fall_in;
wire [MASK_WIDTH-1:0] i_wdf_mask_data_fall_out;
wire [(8*WDF_FIFO_NUM)-1:0] i_wdf_mask_data_in;
wire [(8*WDF_FIFO_NUM)-1:0] i_wdf_mask_data_out;
wire [MASK_WIDTH-1:0] i_wdf_mask_data_rise_in;
wire [MASK_WIDTH-1:0] i_wdf_mask_data_rise_out;
reg rst_r;
// ECC signals
wire [(2*DQ_WIDTH)-1:0] i_wdf_data_out_ecc;
wire [((2*DQ_WIDTH)/8)-1:0] i_wdf_mask_data_out_ecc;
wire [63:0] i_wdf_mask_data_out_ecc_wire;
wire [((2*DQ_WIDTH)/8)-1:0] mask_data_in_ecc;
wire [63:0] mask_data_in_ecc_wire;
//***************************************************************************
assign app_wdf_afull = i_wdf_afull[0];
always @(posedge clk0 )
rst_r <= rst0;
genvar wdf_di_i;
genvar wdf_do_i;
genvar mask_i;
genvar wdf_i;
generate
if(ECC_ENABLE) begin // ECC code
assign wdf_data = i_wdf_data_out_ecc;
// the byte 9 dm is always held to 0
assign wdf_mask_data = i_wdf_mask_data_out_ecc;
// generate for write data fifo .
for (wdf_i = 0; wdf_i < WDF_FIFO_NUM; wdf_i = wdf_i + 1) begin: gen_wdf
FIFO36_72 #
(
.ALMOST_EMPTY_OFFSET (9'h007),
.ALMOST_FULL_OFFSET (9'h00F),
.DO_REG (1), // extra CC output delay
.EN_ECC_WRITE ("TRUE"),
.EN_ECC_READ ("FALSE"),
.EN_SYN ("FALSE"),
.FIRST_WORD_FALL_THROUGH ("FALSE")
)
u_wdf_ecc
(
.ALMOSTEMPTY (),
.ALMOSTFULL (i_wdf_afull[wdf_i]),
.DBITERR (),
.DO (i_wdf_data_out_ecc[((64*(wdf_i+1))+(wdf_i *8))-1:
(64*wdf_i)+(wdf_i *8)]),
.DOP (i_wdf_data_out_ecc[(72*(wdf_i+1))-1:
(64*(wdf_i+1))+ (8*wdf_i) ]),
.ECCPARITY (),
.EMPTY (),
.FULL (),
.RDCOUNT (),
.RDERR (),
.SBITERR (),
.WRCOUNT (),
.WRERR (),
.DI (app_wdf_data[(64*(wdf_i+1))-1:
(64*wdf_i)]),
.DIP (),
.RDCLK (clk90),
.RDEN (wdf_rden),
.RST (rst_r), // or can use rst0
.WRCLK (clk0),
.WREN (app_wdf_wren)
);
end
// remapping the mask data. The mask data from user i/f does not have
// the mask for the ECC byte. Assigning 0 to the ECC mask byte.
for (mask_i = 0; mask_i < (DQ_WIDTH)/36;
mask_i = mask_i +1) begin: gen_mask
assign mask_data_in_ecc[((8*(mask_i+1))+ mask_i)-1:((8*mask_i)+mask_i)]
= app_wdf_mask_data[(8*(mask_i+1))-1:8*(mask_i)] ;
assign mask_data_in_ecc[((8*(mask_i+1))+mask_i)] = 1'd0;
end
// assign ecc bits to temp variables to avoid
// sim warnings. Not all the 64 bits of the fifo
// are used in ECC mode.
assign mask_data_in_ecc_wire[((2*DQ_WIDTH)/8)-1:0] = mask_data_in_ecc;
assign mask_data_in_ecc_wire[63:((2*DQ_WIDTH)/8)] =
{(64-((2*DQ_WIDTH)/8)){1'b0}};
assign i_wdf_mask_data_out_ecc =
i_wdf_mask_data_out_ecc_wire[((2*DQ_WIDTH)/8)-1:0];
FIFO36_72 #
(
.ALMOST_EMPTY_OFFSET (9'h007),
.ALMOST_FULL_OFFSET (9'h00F),
.DO_REG (1), // extra CC output delay
.EN_ECC_WRITE ("TRUE"),
.EN_ECC_READ ("FALSE"),
.EN_SYN ("FALSE"),
.FIRST_WORD_FALL_THROUGH ("FALSE")
)
u_wdf_ecc_mask
(
.ALMOSTEMPTY (),
.ALMOSTFULL (),
.DBITERR (),
.DO (i_wdf_mask_data_out_ecc_wire),
.DOP (),
.ECCPARITY (),
.EMPTY (),
.FULL (),
.RDCOUNT (),
.RDERR (),
.SBITERR (),
.WRCOUNT (),
.WRERR (),
.DI (mask_data_in_ecc_wire),
.DIP (),
.RDCLK (clk90),
.RDEN (wdf_rden),
.RST (rst_r), // or can use rst0
.WRCLK (clk0),
.WREN (app_wdf_wren)
);
end else begin
//***********************************************************************
// Define intermediate buses:
assign i_wdf_data_rise_in
= app_wdf_data[DQ_WIDTH-1:0];
assign i_wdf_data_fall_in
= app_wdf_data[(2*DQ_WIDTH)-1:DQ_WIDTH];
assign i_wdf_mask_data_rise_in
= app_wdf_mask_data[MASK_WIDTH-1:0];
assign i_wdf_mask_data_fall_in
= app_wdf_mask_data[(2*MASK_WIDTH)-1:MASK_WIDTH];
//***********************************************************************
// Write data FIFO Input:
// Arrange DQ's so that the rise data and fall data are interleaved.
// the data arrives at the input of the wdf fifo as {fall,rise}.
// It is remapped as:
// {...fall[15:8],rise[15:8],fall[7:0],rise[7:0]}
// This is done to avoid having separate fifo's for rise and fall data
// and to keep rise/fall data for the same DQ's on same FIFO
// Data masks are interleaved in a similar manner
// NOTE: Initialization data from PHY_INIT module does not need to be
// interleaved - it's already in the correct format - and the same
// initialization pattern from PHY_INIT is sent to all write FIFOs
//***********************************************************************
for (wdf_di_i = 0; wdf_di_i < MASK_WIDTH;
wdf_di_i = wdf_di_i + 1) begin: gen_wdf_data_in
assign i_wdf_data_in[(16*wdf_di_i)+15:(16*wdf_di_i)]
= {i_wdf_data_fall_in[(8*wdf_di_i)+7:(8*wdf_di_i)],
i_wdf_data_rise_in[(8*wdf_di_i)+7:(8*wdf_di_i)]};
assign i_wdf_mask_data_in[(2*wdf_di_i)+1:(2*wdf_di_i)]
= {i_wdf_mask_data_fall_in[wdf_di_i],
i_wdf_mask_data_rise_in[wdf_di_i]};
end
//***********************************************************************
// Write data FIFO Output:
// FIFO DQ and mask outputs must be untangled and put in the standard
// format of {fall,rise}. Same goes for mask output
//***********************************************************************
for (wdf_do_i = 0; wdf_do_i < MASK_WIDTH;
wdf_do_i = wdf_do_i + 1) begin: gen_wdf_data_out
assign i_wdf_data_rise_out[(8*wdf_do_i)+7:(8*wdf_do_i)]
= i_wdf_data_out[(16*wdf_do_i)+7:(16*wdf_do_i)];
assign i_wdf_data_fall_out[(8*wdf_do_i)+7:(8*wdf_do_i)]
= i_wdf_data_out[(16*wdf_do_i)+15:(16*wdf_do_i)+8];
assign i_wdf_mask_data_rise_out[wdf_do_i]
= i_wdf_mask_data_out[2*wdf_do_i];
assign i_wdf_mask_data_fall_out[wdf_do_i]
= i_wdf_mask_data_out[(2*wdf_do_i)+1];
end
assign wdf_data = {i_wdf_data_fall_out,
i_wdf_data_rise_out};
assign wdf_mask_data = {i_wdf_mask_data_fall_out,
i_wdf_mask_data_rise_out};
//***********************************************************************
for (wdf_i = 0; wdf_i < WDF_FIFO_NUM; wdf_i = wdf_i + 1) begin: gen_wdf
FIFO36_72 #
(
.ALMOST_EMPTY_OFFSET (9'h007),
.ALMOST_FULL_OFFSET (9'h00F),
.DO_REG (1), // extra CC output delay
.EN_ECC_WRITE ("FALSE"),
.EN_ECC_READ ("FALSE"),
.EN_SYN ("FALSE"),
.FIRST_WORD_FALL_THROUGH ("FALSE")
)
u_wdf
(
.ALMOSTEMPTY (),
.ALMOSTFULL (i_wdf_afull[wdf_i]),
.DBITERR (),
.DO (i_wdf_data_out[(64*(wdf_i+1))-1:64*wdf_i]),
.DOP (i_wdf_mask_data_out[(8*(wdf_i+1))-1:8*wdf_i]),
.ECCPARITY (),
.EMPTY (),
.FULL (),
.RDCOUNT (),
.RDERR (),
.SBITERR (),
.WRCOUNT (),
.WRERR (),
.DI (i_wdf_data_in[(64*(wdf_i+1))-1:64*wdf_i]),
.DIP (i_wdf_mask_data_in[(8*(wdf_i+1))-1:8*wdf_i]),
.RDCLK (clk90),
.RDEN (wdf_rden),
.RST (rst_r), // or can use rst0
.WRCLK (clk0),
.WREN (app_wdf_wren)
);
end
end
endgenerate
endmodule
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module increases the frame size of video streams. *
* *
******************************************************************************/
module altera_up_video_clipper_add (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bi-Directional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 15; // Image's Data Width
parameter EW = 0; // Image's Empty Width
parameter IMAGE_WIDTH = 640; // Final image width in pixels
parameter IMAGE_HEIGHT = 480; // Final image height in lines
parameter WW = 9; // Final image width address width
parameter HW = 8; // Final image height address width
parameter ADD_PIXELS_AT_START = 0;
parameter ADD_PIXELS_AT_END = 0;
parameter ADD_LINES_AT_START = 0;
parameter ADD_LINES_AT_END = 0;
parameter ADD_DATA = 16'h0; // Data for added pixels
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [EW: 0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [DW: 0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [EW: 0] stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire increment_counters;
wire new_startofpacket;
wire new_endofpacket;
wire pass_inner_frame;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 'h0;
stream_out_valid <= 1'b0;
end
else if (stream_out_ready | ~stream_out_valid)
begin
if (pass_inner_frame)
stream_out_data <= stream_in_data;
else
stream_out_data <= ADD_DATA;
stream_out_startofpacket <= new_startofpacket;
stream_out_endofpacket <= new_endofpacket;
stream_out_empty <= 'h0;
if (pass_inner_frame)
stream_out_valid <= stream_in_valid;
else
stream_out_valid <= 1'b1;
end
end
// Internal registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output assignments
assign stream_in_ready = pass_inner_frame & (~stream_out_valid | stream_out_ready);
// Internal assignments
assign increment_counters = (~stream_out_valid | stream_out_ready) &
(~pass_inner_frame | stream_in_valid);
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_video_clipper_counters Clipper_Add_Counters (
// Inputs
.clk (clk),
.reset (reset),
.increment_counters (increment_counters),
// Bidirectional
// Outputs
.start_of_outer_frame (new_startofpacket),
.end_of_outer_frame (new_endofpacket),
.start_of_inner_frame (),
.end_of_inner_frame (),
.inner_frame_valid (pass_inner_frame)
);
defparam
Clipper_Add_Counters.IMAGE_WIDTH = IMAGE_WIDTH,
Clipper_Add_Counters.IMAGE_HEIGHT = IMAGE_HEIGHT,
Clipper_Add_Counters.WW = WW,
Clipper_Add_Counters.HW = HW,
Clipper_Add_Counters.LEFT_OFFSET = ADD_PIXELS_AT_START,
Clipper_Add_Counters.RIGHT_OFFSET = ADD_PIXELS_AT_END,
Clipper_Add_Counters.TOP_OFFSET = ADD_LINES_AT_START,
Clipper_Add_Counters.BOTTOM_OFFSET = ADD_LINES_AT_END;
endmodule
|
//`include "elink_regmap.v"
module dut(/*AUTOARG*/
// Outputs
dut_active, clkout, wait_out, access_out, packet_out,
// Inputs
clk1, clk2, nreset, vdd, vss, access_in, packet_in, wait_in
);
//##########################################################################
//# INTERFACE
//##########################################################################
parameter AW = 32;
parameter ID = 12'h810;
parameter S_IDW = 12;
parameter M_IDW = 6;
parameter PW = 2*AW + 40;
parameter N = 1;
//clock,reset
input clk1;
input clk2;
input nreset;
input [N*N-1:0] vdd;
input vss;
output dut_active;
output clkout;
//Stimulus Driven Transaction
input [N-1:0] access_in;
input [N*PW-1:0] packet_in;
output [N-1:0] wait_out;
//DUT driven transaction
output [N-1:0] access_out;
output [N*PW-1:0] packet_out;
input [N-1:0] wait_in;
//##########################################################################
//#BODY
//##########################################################################
wire mem_rd_wait;
wire mem_wr_wait;
wire mem_access;
wire [PW-1:0] mem_packet;
/*AUTOINPUT*/
// End of automatics
/*AUTOWIRE*/
assign clkout = clk1;
assign dut_active = 1'b1;
assign wait_out = 1'b0;
emailbox emailbox (.reg_rdata (),
.mailbox_irq (mailbox_irq),
.mailbox_wait (),
// Inputs
.nreset (nreset),
.wr_clk (clk1),
.rd_clk (clk1),
.emesh_access (access_in),
.emesh_packet (packet_in[PW-1:0]),
.reg_access (1'b0),
.reg_packet ({(PW){1'b0}}),
.mailbox_irq_en (1'b1)
);
endmodule
// Local Variables:
// verilog-library-directories:("." "../hdl")
// End:
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.1 (win64) Build 1538259 Fri Apr 8 15:45:27 MDT 2016
// Date : Thu Aug 18 13:15:29 2016
// Host : STEVENHERBSC43A running 64-bit major release (build 9200)
// Command : write_verilog -mode funcsim -nolib -force -file
// C:/Users/sgherbst/ft232h_test_program/ft232h_test_program.sim/sim_1/impl/func/top_tb_func_impl.v
// Design : top
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* ECO_CHECKSUM = "570f66de" *)
(* NotValidForBitStream *)
module top
(CLK100MHZ,
CIS_MODE,
CIS_CLK,
CIS_SP,
CIS_LED_BLUE,
CIS_LED_GREEN,
CIS_LED_RED);
input CLK100MHZ;
output CIS_MODE;
output CIS_CLK;
output CIS_SP;
output CIS_LED_BLUE;
output CIS_LED_GREEN;
output CIS_LED_RED;
wire CIS_CLK;
wire CIS_CLK_OBUF;
wire CIS_CLK_i_1_n_0;
wire CIS_LED_BLUE;
wire CIS_LED_BLUE__0;
wire CIS_LED_BLUE_i_1_n_0;
wire CIS_LED_BLUE_i_3_n_0;
wire CIS_LED_BLUE_i_4_n_0;
wire CIS_LED_BLUE_i_5_n_0;
wire CIS_LED_GREEN;
wire CIS_LED_RED;
wire CIS_LED_RED_OBUF;
wire CIS_MODE;
wire CIS_SP;
wire CIS_SP_OBUF;
wire CLK100MHZ;
wire CLK100MHZ_IBUF;
wire CLK100MHZ_IBUF_BUFG;
wire [3:0]counter_100MHZ;
wire \counter_100MHZ[0]_i_1_n_0 ;
wire \counter_100MHZ[1]_i_1_n_0 ;
wire \counter_100MHZ[2]_i_1_n_0 ;
wire \counter_100MHZ[3]_i_1_n_0 ;
wire [0:0]counter_cis;
wire \counter_cis[11]_i_1_n_0 ;
wire \counter_cis[11]_i_3_n_0 ;
wire \counter_cis[11]_i_4_n_0 ;
wire \counter_cis_reg[4]_i_1_n_0 ;
wire \counter_cis_reg[8]_i_1_n_0 ;
wire \counter_cis_reg_n_0_[0] ;
wire \counter_cis_reg_n_0_[10] ;
wire \counter_cis_reg_n_0_[11] ;
wire \counter_cis_reg_n_0_[1] ;
wire \counter_cis_reg_n_0_[2] ;
wire \counter_cis_reg_n_0_[3] ;
wire \counter_cis_reg_n_0_[4] ;
wire \counter_cis_reg_n_0_[5] ;
wire \counter_cis_reg_n_0_[6] ;
wire \counter_cis_reg_n_0_[7] ;
wire \counter_cis_reg_n_0_[8] ;
wire \counter_cis_reg_n_0_[9] ;
wire [11:1]data0;
wire [3:0]\NLW_counter_cis_reg[11]_i_2_CO_UNCONNECTED ;
wire [3:3]\NLW_counter_cis_reg[11]_i_2_O_UNCONNECTED ;
wire [2:0]\NLW_counter_cis_reg[4]_i_1_CO_UNCONNECTED ;
wire [2:0]\NLW_counter_cis_reg[8]_i_1_CO_UNCONNECTED ;
OBUF CIS_CLK_OBUF_inst
(.I(CIS_CLK_OBUF),
.O(CIS_CLK));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hFFBF0040))
CIS_CLK_i_1
(.I0(counter_100MHZ[2]),
.I1(counter_100MHZ[3]),
.I2(counter_100MHZ[1]),
.I3(counter_100MHZ[0]),
.I4(CIS_CLK_OBUF),
.O(CIS_CLK_i_1_n_0));
FDRE #(
.INIT(1'b0))
CIS_CLK_reg
(.C(CLK100MHZ_IBUF_BUFG),
.CE(1'b1),
.D(CIS_CLK_i_1_n_0),
.Q(CIS_CLK_OBUF),
.R(1'b0));
OBUF CIS_LED_BLUE_OBUF_inst
(.I(CIS_LED_RED_OBUF),
.O(CIS_LED_BLUE));
LUT5 #(
.INIT(32'h00000002))
CIS_LED_BLUE_i_1
(.I0(CIS_LED_BLUE_i_3_n_0),
.I1(\counter_cis_reg_n_0_[10] ),
.I2(\counter_cis_reg_n_0_[0] ),
.I3(\counter_cis_reg_n_0_[1] ),
.I4(\counter_cis[11]_i_4_n_0 ),
.O(CIS_LED_BLUE_i_1_n_0));
LUT6 #(
.INIT(64'h0000004000000000))
CIS_LED_BLUE_i_2
(.I0(CIS_LED_BLUE_i_4_n_0),
.I1(\counter_cis_reg_n_0_[2] ),
.I2(\counter_cis_reg_n_0_[1] ),
.I3(\counter_cis_reg_n_0_[4] ),
.I4(\counter_cis_reg_n_0_[3] ),
.I5(CIS_LED_BLUE_i_5_n_0),
.O(CIS_LED_BLUE__0));
LUT5 #(
.INIT(32'h00000001))
CIS_LED_BLUE_i_3
(.I0(\counter_cis_reg_n_0_[4] ),
.I1(\counter_cis_reg_n_0_[7] ),
.I2(\counter_cis_reg_n_0_[8] ),
.I3(\counter_cis_reg_n_0_[11] ),
.I4(\counter_cis_reg_n_0_[9] ),
.O(CIS_LED_BLUE_i_3_n_0));
LUT2 #(
.INIT(4'hE))
CIS_LED_BLUE_i_4
(.I0(\counter_cis_reg_n_0_[0] ),
.I1(\counter_cis_reg_n_0_[10] ),
.O(CIS_LED_BLUE_i_4_n_0));
LUT6 #(
.INIT(64'h0000000000000010))
CIS_LED_BLUE_i_5
(.I0(\counter_cis_reg_n_0_[7] ),
.I1(\counter_cis_reg_n_0_[8] ),
.I2(\counter_cis_reg_n_0_[6] ),
.I3(\counter_cis_reg_n_0_[5] ),
.I4(\counter_cis_reg_n_0_[11] ),
.I5(\counter_cis_reg_n_0_[9] ),
.O(CIS_LED_BLUE_i_5_n_0));
FDRE #(
.INIT(1'b1))
CIS_LED_BLUE_reg
(.C(CIS_CLK_OBUF),
.CE(CIS_LED_BLUE__0),
.D(CIS_LED_BLUE__0),
.Q(CIS_LED_RED_OBUF),
.R(CIS_LED_BLUE_i_1_n_0));
OBUF CIS_LED_GREEN_OBUF_inst
(.I(CIS_LED_RED_OBUF),
.O(CIS_LED_GREEN));
OBUF CIS_LED_RED_OBUF_inst
(.I(CIS_LED_RED_OBUF),
.O(CIS_LED_RED));
OBUF CIS_MODE_OBUF_inst
(.I(1'b0),
.O(CIS_MODE));
OBUF CIS_SP_OBUF_inst
(.I(CIS_SP_OBUF),
.O(CIS_SP));
FDRE #(
.INIT(1'b1))
CIS_SP_reg
(.C(CIS_CLK_OBUF),
.CE(1'b1),
.D(\counter_cis[11]_i_1_n_0 ),
.Q(CIS_SP_OBUF),
.R(1'b0));
BUFG CLK100MHZ_IBUF_BUFG_inst
(.I(CLK100MHZ_IBUF),
.O(CLK100MHZ_IBUF_BUFG));
IBUF CLK100MHZ_IBUF_inst
(.I(CLK100MHZ),
.O(CLK100MHZ_IBUF));
LUT1 #(
.INIT(2'h1))
\counter_100MHZ[0]_i_1
(.I0(counter_100MHZ[0]),
.O(\counter_100MHZ[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h0FB0))
\counter_100MHZ[1]_i_1
(.I0(counter_100MHZ[2]),
.I1(counter_100MHZ[3]),
.I2(counter_100MHZ[1]),
.I3(counter_100MHZ[0]),
.O(\counter_100MHZ[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h6A))
\counter_100MHZ[2]_i_1
(.I0(counter_100MHZ[2]),
.I1(counter_100MHZ[1]),
.I2(counter_100MHZ[0]),
.O(\counter_100MHZ[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h6C8C))
\counter_100MHZ[3]_i_1
(.I0(counter_100MHZ[2]),
.I1(counter_100MHZ[3]),
.I2(counter_100MHZ[1]),
.I3(counter_100MHZ[0]),
.O(\counter_100MHZ[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\counter_100MHZ_reg[0]
(.C(CLK100MHZ_IBUF_BUFG),
.CE(1'b1),
.D(\counter_100MHZ[0]_i_1_n_0 ),
.Q(counter_100MHZ[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\counter_100MHZ_reg[1]
(.C(CLK100MHZ_IBUF_BUFG),
.CE(1'b1),
.D(\counter_100MHZ[1]_i_1_n_0 ),
.Q(counter_100MHZ[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\counter_100MHZ_reg[2]
(.C(CLK100MHZ_IBUF_BUFG),
.CE(1'b1),
.D(\counter_100MHZ[2]_i_1_n_0 ),
.Q(counter_100MHZ[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\counter_100MHZ_reg[3]
(.C(CLK100MHZ_IBUF_BUFG),
.CE(1'b1),
.D(\counter_100MHZ[3]_i_1_n_0 ),
.Q(counter_100MHZ[3]),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\counter_cis[0]_i_1
(.I0(\counter_cis_reg_n_0_[0] ),
.O(counter_cis));
LUT5 #(
.INIT(32'h00000001))
\counter_cis[11]_i_1
(.I0(\counter_cis[11]_i_3_n_0 ),
.I1(\counter_cis_reg_n_0_[10] ),
.I2(\counter_cis_reg_n_0_[0] ),
.I3(\counter_cis_reg_n_0_[1] ),
.I4(\counter_cis[11]_i_4_n_0 ),
.O(\counter_cis[11]_i_1_n_0 ));
LUT5 #(
.INIT(32'h7FFFFFFF))
\counter_cis[11]_i_3
(.I0(\counter_cis_reg_n_0_[4] ),
.I1(\counter_cis_reg_n_0_[9] ),
.I2(\counter_cis_reg_n_0_[11] ),
.I3(\counter_cis_reg_n_0_[8] ),
.I4(\counter_cis_reg_n_0_[7] ),
.O(\counter_cis[11]_i_3_n_0 ));
LUT4 #(
.INIT(16'hFFDF))
\counter_cis[11]_i_4
(.I0(\counter_cis_reg_n_0_[3] ),
.I1(\counter_cis_reg_n_0_[2] ),
.I2(\counter_cis_reg_n_0_[5] ),
.I3(\counter_cis_reg_n_0_[6] ),
.O(\counter_cis[11]_i_4_n_0 ));
FDRE #(
.INIT(1'b1))
\counter_cis_reg[0]
(.C(CIS_CLK_OBUF),
.CE(1'b1),
.D(counter_cis),
.Q(\counter_cis_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\counter_cis_reg[10]
(.C(CIS_CLK_OBUF),
.CE(1'b1),
.D(data0[10]),
.Q(\counter_cis_reg_n_0_[10] ),
.R(\counter_cis[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\counter_cis_reg[11]
(.C(CIS_CLK_OBUF),
.CE(1'b1),
.D(data0[11]),
.Q(\counter_cis_reg_n_0_[11] ),
.R(\counter_cis[11]_i_1_n_0 ));
CARRY4 \counter_cis_reg[11]_i_2
(.CI(\counter_cis_reg[8]_i_1_n_0 ),
.CO(\NLW_counter_cis_reg[11]_i_2_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_counter_cis_reg[11]_i_2_O_UNCONNECTED [3],data0[11:9]}),
.S({1'b0,\counter_cis_reg_n_0_[11] ,\counter_cis_reg_n_0_[10] ,\counter_cis_reg_n_0_[9] }));
FDRE #(
.INIT(1'b0))
\counter_cis_reg[1]
(.C(CIS_CLK_OBUF),
.CE(1'b1),
.D(data0[1]),
.Q(\counter_cis_reg_n_0_[1] ),
.R(\counter_cis[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\counter_cis_reg[2]
(.C(CIS_CLK_OBUF),
.CE(1'b1),
.D(data0[2]),
.Q(\counter_cis_reg_n_0_[2] ),
.R(\counter_cis[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\counter_cis_reg[3]
(.C(CIS_CLK_OBUF),
.CE(1'b1),
.D(data0[3]),
.Q(\counter_cis_reg_n_0_[3] ),
.R(\counter_cis[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\counter_cis_reg[4]
(.C(CIS_CLK_OBUF),
.CE(1'b1),
.D(data0[4]),
.Q(\counter_cis_reg_n_0_[4] ),
.R(\counter_cis[11]_i_1_n_0 ));
CARRY4 \counter_cis_reg[4]_i_1
(.CI(1'b0),
.CO({\counter_cis_reg[4]_i_1_n_0 ,\NLW_counter_cis_reg[4]_i_1_CO_UNCONNECTED [2:0]}),
.CYINIT(\counter_cis_reg_n_0_[0] ),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(data0[4:1]),
.S({\counter_cis_reg_n_0_[4] ,\counter_cis_reg_n_0_[3] ,\counter_cis_reg_n_0_[2] ,\counter_cis_reg_n_0_[1] }));
FDRE #(
.INIT(1'b0))
\counter_cis_reg[5]
(.C(CIS_CLK_OBUF),
.CE(1'b1),
.D(data0[5]),
.Q(\counter_cis_reg_n_0_[5] ),
.R(\counter_cis[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\counter_cis_reg[6]
(.C(CIS_CLK_OBUF),
.CE(1'b1),
.D(data0[6]),
.Q(\counter_cis_reg_n_0_[6] ),
.R(\counter_cis[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\counter_cis_reg[7]
(.C(CIS_CLK_OBUF),
.CE(1'b1),
.D(data0[7]),
.Q(\counter_cis_reg_n_0_[7] ),
.R(\counter_cis[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\counter_cis_reg[8]
(.C(CIS_CLK_OBUF),
.CE(1'b1),
.D(data0[8]),
.Q(\counter_cis_reg_n_0_[8] ),
.R(\counter_cis[11]_i_1_n_0 ));
CARRY4 \counter_cis_reg[8]_i_1
(.CI(\counter_cis_reg[4]_i_1_n_0 ),
.CO({\counter_cis_reg[8]_i_1_n_0 ,\NLW_counter_cis_reg[8]_i_1_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(data0[8:5]),
.S({\counter_cis_reg_n_0_[8] ,\counter_cis_reg_n_0_[7] ,\counter_cis_reg_n_0_[6] ,\counter_cis_reg_n_0_[5] }));
FDRE #(
.INIT(1'b0))
\counter_cis_reg[9]
(.C(CIS_CLK_OBUF),
.CE(1'b1),
.D(data0[9]),
.Q(\counter_cis_reg_n_0_[9] ),
.R(\counter_cis[11]_i_1_n_0 ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
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