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`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:24:04 11/07/2015
// Design Name: RAM_Block
// Module Name: C:/Users/Camilo/Documents/Xilinx_Workspace/Transflineal/RAM_tst.v
// Project Name: Transflineal
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: RAM_Block
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module RAM_tst;
// Inputs
reg clk;
reg [7:0] Address_w;
reg [7:0] Address;
reg W_ref;
reg W;
reg [31:0] Data_I;
// Outputs
wire [31:0] Data_O;
wire [15:0] Ref;
reg [8:0] i;
reg [15:0] ssin;
reg [15:0] ccos;
// Instantiate the Unit Under Test (UUT)
RAM_Block uut (
.clk(clk),
.Address(Address),
.Address_w(Address_w),
.W(W),
.W_ref(W_ref),
.Data_I(Data_I),
.Data_O(Data_O),
.Ref(Ref)
);
initial begin
// Initialize Inputs
clk = 0;
Address_w = 0;
Address = 0;
W = 0;
W_ref = 0;
Data_I = 0;
i = 0;
ssin = 16'd143;
ccos = 16'd8191;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
for(i = 0; i <= 255; i = i+1) begin
ssin = ssin+1;
if(i == 13) ccos = 16'd8190;
if(i == 55) ccos = 16'd8189;
if(i == 89) ccos = 16'd8188;
if(i == 118) ccos = 16'd8187;
if(i == 145) ccos = 16'd8186;
if(i == 169) ccos = 16'd8185;
if(i == 191) ccos = 16'd8184;
if(i == 212) ccos = 16'd8183;
if(i == 231) ccos = 16'd8182;
if(i == 250) ccos = 16'd8181;
#3 Address_w = i[7:0];
#10 Data_I = {ssin,ccos};
#10 W = 1;
#10 W = 0;
#10 Address = i[7:0];
#10;
end
Data_I = 32'd259;
#10;
W_ref = 1;
#10;
W_ref = 0;
#100;
Address = 128;
end
always #5 clk = !clk;
endmodule
|
`timescale 1 ns / 1 ps
module myip_v1_0_S01_AXI #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of ID for for write address, write data, read address and read data
parameter integer C_S_AXI_ID_WIDTH = 1,
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 6,
// Width of optional user defined signal in write address channel
parameter integer C_S_AXI_AWUSER_WIDTH = 0,
// Width of optional user defined signal in read address channel
parameter integer C_S_AXI_ARUSER_WIDTH = 0,
// Width of optional user defined signal in write data channel
parameter integer C_S_AXI_WUSER_WIDTH = 0,
// Width of optional user defined signal in read data channel
parameter integer C_S_AXI_RUSER_WIDTH = 0,
// Width of optional user defined signal in write response channel
parameter integer C_S_AXI_BUSER_WIDTH = 0
)
(
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write Address ID
input wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_AWID,
// Write address
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Burst length. The burst length gives the exact number of transfers in a burst
input wire [7 : 0] S_AXI_AWLEN,
// Burst size. This signal indicates the size of each transfer in the burst
input wire [2 : 0] S_AXI_AWSIZE,
// Burst type. The burst type and the size information,
// determine how the address for each transfer within the burst is calculated.
input wire [1 : 0] S_AXI_AWBURST,
// Lock type. Provides additional information about the
// atomic characteristics of the transfer.
input wire S_AXI_AWLOCK,
// Memory type. This signal indicates how transactions
// are required to progress through a system.
input wire [3 : 0] S_AXI_AWCACHE,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Quality of Service, QoS identifier sent for each
// write transaction.
input wire [3 : 0] S_AXI_AWQOS,
// Region identifier. Permits a single physical interface
// on a slave to be used for multiple logical interfaces.
input wire [3 : 0] S_AXI_AWREGION,
// Optional User-defined signal in the write address channel.
input wire [C_S_AXI_AWUSER_WIDTH-1 : 0] S_AXI_AWUSER,
// Write address valid. This signal indicates that
// the channel is signaling valid write address and
// control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that
// the slave is ready to accept an address and associated
// control signals.
output wire S_AXI_AWREADY,
// Write Data
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte
// lanes hold valid data. There is one write strobe
// bit for each eight bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write last. This signal indicates the last transfer
// in a write burst.
input wire S_AXI_WLAST,
// Optional User-defined signal in the write data channel.
input wire [C_S_AXI_WUSER_WIDTH-1 : 0] S_AXI_WUSER,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Response ID tag. This signal is the ID tag of the
// write response.
output wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_BID,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Optional User-defined signal in the write response channel.
output wire [C_S_AXI_BUSER_WIDTH-1 : 0] S_AXI_BUSER,
// Write response valid. This signal indicates that the
// channel is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address ID. This signal is the identification
// tag for the read address group of signals.
input wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_ARID,
// Read address. This signal indicates the initial
// address of a read burst transaction.
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Burst length. The burst length gives the exact number of transfers in a burst
input wire [7 : 0] S_AXI_ARLEN,
// Burst size. This signal indicates the size of each transfer in the burst
input wire [2 : 0] S_AXI_ARSIZE,
// Burst type. The burst type and the size information,
// determine how the address for each transfer within the burst is calculated.
input wire [1 : 0] S_AXI_ARBURST,
// Lock type. Provides additional information about the
// atomic characteristics of the transfer.
input wire S_AXI_ARLOCK,
// Memory type. This signal indicates how transactions
// are required to progress through a system.
input wire [3 : 0] S_AXI_ARCACHE,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Quality of Service, QoS identifier sent for each
// read transaction.
input wire [3 : 0] S_AXI_ARQOS,
// Region identifier. Permits a single physical interface
// on a slave to be used for multiple logical interfaces.
input wire [3 : 0] S_AXI_ARREGION,
// Optional User-defined signal in the read address channel.
input wire [C_S_AXI_ARUSER_WIDTH-1 : 0] S_AXI_ARUSER,
// Write address valid. This signal indicates that
// the channel is signaling valid read address and
// control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that
// the slave is ready to accept an address and associated
// control signals.
output wire S_AXI_ARREADY,
// Read ID tag. This signal is the identification tag
// for the read data group of signals generated by the slave.
output wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_RID,
// Read Data
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of
// the read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read last. This signal indicates the last transfer
// in a read burst.
output wire S_AXI_RLAST,
// Optional User-defined signal in the read address channel.
output wire [C_S_AXI_RUSER_WIDTH-1 : 0] S_AXI_RUSER,
// Read valid. This signal indicates that the channel
// is signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
);
// AXI4FULL signals
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg [C_S_AXI_BUSER_WIDTH-1 : 0] axi_buser;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rlast;
reg [C_S_AXI_RUSER_WIDTH-1 : 0] axi_ruser;
reg axi_rvalid;
// aw_wrap_en determines wrap boundary and enables wrapping
wire aw_wrap_en;
// ar_wrap_en determines wrap boundary and enables wrapping
wire ar_wrap_en;
// aw_wrap_size is the size of the write transfer, the
// write address wraps to a lower address if upper address
// limit is reached
wire integer aw_wrap_size ;
// ar_wrap_size is the size of the read transfer, the
// read address wraps to a lower address if upper address
// limit is reached
wire integer ar_wrap_size ;
// The axi_awv_awr_flag flag marks the presence of write address valid
reg axi_awv_awr_flag;
//The axi_arv_arr_flag flag marks the presence of read address valid
reg axi_arv_arr_flag;
// The axi_awlen_cntr internal write address counter to keep track of beats in a burst transaction
reg [7:0] axi_awlen_cntr;
//The axi_arlen_cntr internal read address counter to keep track of beats in a burst transaction
reg [7:0] axi_arlen_cntr;
//local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
//ADDR_LSB is used for addressing 32/64 bit registers/memories
//ADDR_LSB = 2 for 32 bits (n downto 2)
//ADDR_LSB = 3 for 42 bits (n downto 3)
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32)+ 1;
localparam integer OPT_MEM_ADDR_BITS = 3;
localparam integer USER_NUM_MEM = 1;
//----------------------------------------------
//-- Signals for user logic memory space example
//------------------------------------------------
wire [OPT_MEM_ADDR_BITS:0] mem_address;
wire [USER_NUM_MEM-1:0] mem_select;
reg [C_S_AXI_DATA_WIDTH-1:0] mem_data_out[0 : USER_NUM_MEM-1];
genvar i;
genvar j;
genvar mem_byte_index;
// I/O Connections assignments
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BUSER = axi_buser;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RLAST = axi_rlast;
assign S_AXI_RUSER = axi_ruser;
assign S_AXI_RVALID = axi_rvalid;
assign S_AXI_BID = S_AXI_AWID;
assign S_AXI_RID = S_AXI_ARID;
assign aw_wrap_size = (C_S_AXI_DATA_WIDTH/8 * (S_AXI_AWLEN));
assign ar_wrap_size = (C_S_AXI_DATA_WIDTH/8 * (S_AXI_ARLEN));
assign aw_wrap_en = ((axi_awaddr & aw_wrap_size) == aw_wrap_size)? 1'b1: 1'b0;
assign ar_wrap_en = ((axi_araddr & ar_wrap_size) == ar_wrap_size)? 1'b1: 1'b0;
assign S_AXI_BUSER = 0;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
axi_awv_awr_flag <= 1'b0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && ~axi_awv_awr_flag && ~axi_arv_arr_flag)
begin
// slave is ready to accept an address and
// associated control signals
axi_awready <= 1'b1;
axi_awv_awr_flag <= 1'b1;
// used for generation of bresp() and bvalid
end
else if (S_AXI_WLAST && axi_wready)
// preparing to accept next address after current write burst tx completion
begin
axi_awv_awr_flag <= 1'b0;
end
else
begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
axi_awlen_cntr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && ~axi_awv_awr_flag)
begin
// address latching
axi_awaddr <= S_AXI_AWADDR[C_S_AXI_ADDR_WIDTH - 1:0];
// start address of transfer
axi_awlen_cntr <= 0;
end
else if((axi_awlen_cntr <= S_AXI_AWLEN) && axi_wready && S_AXI_WVALID)
begin
axi_awlen_cntr <= axi_awlen_cntr + 1;
case (S_AXI_AWBURST)
2'b00: // fixed burst
// The write address for all the beats in the transaction are fixed
begin
axi_awaddr <= axi_awaddr;
//for awsize = 4 bytes (010)
end
2'b01: //incremental burst
// The write address for all the beats in the transaction are increments by awsize
begin
axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
//awaddr aligned to 4 byte boundary
axi_awaddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}};
//for awsize = 4 bytes (010)
end
2'b10: //Wrapping burst
// The write address wraps when the address reaches wrap boundary
if (aw_wrap_en)
begin
axi_awaddr <= (axi_awaddr - aw_wrap_size);
end
else
begin
axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
axi_awaddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}};
end
default: //reserved (incremental burst for example)
begin
axi_awaddr <= axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
//for awsize = 4 bytes (010)
end
endcase
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if ( ~axi_wready && S_AXI_WVALID && axi_awv_awr_flag)
begin
// slave can accept the write data
axi_wready <= 1'b1;
end
//else if (~axi_awv_awr_flag)
else if (S_AXI_WLAST && axi_wready)
begin
axi_wready <= 1'b0;
end
end
end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awv_awr_flag && axi_wready && S_AXI_WVALID && ~axi_bvalid && S_AXI_WLAST )
begin
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0;
// 'OKAY' response
end
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_arv_arr_flag <= 1'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID && ~axi_awv_awr_flag && ~axi_arv_arr_flag)
begin
axi_arready <= 1'b1;
axi_arv_arr_flag <= 1'b1;
end
else if (axi_rvalid && S_AXI_RREADY && axi_arlen_cntr == S_AXI_ARLEN)
// preparing to accept next address after current read completion
begin
axi_arv_arr_flag <= 1'b0;
end
else
begin
axi_arready <= 1'b0;
end
end
end
// Implement axi_araddr latching
//This process is used to latch the address when both
//S_AXI_ARVALID and S_AXI_RVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_araddr <= 0;
axi_arlen_cntr <= 0;
axi_rlast <= 1'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID && ~axi_arv_arr_flag)
begin
// address latching
axi_araddr <= S_AXI_ARADDR[C_S_AXI_ADDR_WIDTH - 1:0];
// start address of transfer
axi_arlen_cntr <= 0;
axi_rlast <= 1'b0;
end
else if((axi_arlen_cntr <= S_AXI_ARLEN) && axi_rvalid && S_AXI_RREADY)
begin
axi_arlen_cntr <= axi_arlen_cntr + 1;
axi_rlast <= 1'b0;
case (S_AXI_ARBURST)
2'b00: // fixed burst
// The read address for all the beats in the transaction are fixed
begin
axi_araddr <= axi_araddr;
//for arsize = 4 bytes (010)
end
2'b01: //incremental burst
// The read address for all the beats in the transaction are increments by awsize
begin
axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
//araddr aligned to 4 byte boundary
axi_araddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}};
//for awsize = 4 bytes (010)
end
2'b10: //Wrapping burst
// The read address wraps when the address reaches wrap boundary
if (ar_wrap_en)
begin
axi_araddr <= (axi_araddr - ar_wrap_size);
end
else
begin
axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
//araddr aligned to 4 byte boundary
axi_araddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}};
end
default: //reserved (incremental burst for example)
begin
axi_araddr <= axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB]+1;
//for arsize = 4 bytes (010)
end
endcase
end
else if((axi_arlen_cntr == S_AXI_ARLEN) && ~axi_rlast && axi_arv_arr_flag )
begin
axi_rlast <= 1'b1;
end
else if (S_AXI_RREADY)
begin
axi_rlast <= 1'b0;
end
end
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arv_arr_flag && ~axi_rvalid)
begin
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0;
// 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
axi_rvalid <= 1'b0;
end
end
end
// ------------------------------------------
// -- Example code to access user logic memory region
// ------------------------------------------
generate
if (USER_NUM_MEM >= 1)
begin
assign mem_select = 1;
assign mem_address = (axi_arv_arr_flag? axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB]:(axi_awv_awr_flag? axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB]:0));
end
endgenerate
// implement Block RAM(s)
generate
for(i=0; i<= USER_NUM_MEM-1; i=i+1)
begin:BRAM_GEN
wire mem_rden;
wire mem_wren;
assign mem_wren = axi_wready && S_AXI_WVALID ;
assign mem_rden = axi_arv_arr_flag ; //& ~axi_rvalid
for(mem_byte_index=0; mem_byte_index<= (C_S_AXI_DATA_WIDTH/8-1); mem_byte_index=mem_byte_index+1)
begin:BYTE_BRAM_GEN
wire [8-1:0] data_in ;
wire [8-1:0] data_out;
reg [8-1:0] byte_ram [0 : 15];
integer j;
//assigning 8 bit data
assign data_in = S_AXI_WDATA[(mem_byte_index*8+7) -: 8];
assign data_out = byte_ram[mem_address];
always @( posedge S_AXI_ACLK )
begin
if (mem_wren && S_AXI_WSTRB[mem_byte_index])
begin
byte_ram[mem_address] <= data_in;
end
end
always @( posedge S_AXI_ACLK )
begin
if (mem_rden)
begin
mem_data_out[i][(mem_byte_index*8+7) -: 8] <= data_out;
end
end
end
end
endgenerate
//Output register or memory read data
always @( mem_data_out, axi_rvalid)
begin
if (axi_rvalid)
begin
// Read address mux
axi_rdata <= mem_data_out[0];
end
else
begin
axi_rdata <= 32'h00000000;
end
end
// Add user logic here
// User logic ends
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_intr_rd_mem.v
*
* Date : 2012-11
*
* Description : Mimics interconnect for Reads between AFI and DDRC/OCM
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_intr_rd_mem(
sw_clk,
rstn,
full,
empty,
req,
invalid_rd_req,
rd_info,
RD_DATA_OCM,
RD_DATA_DDR,
RD_DATA_VALID_OCM,
RD_DATA_VALID_DDR
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input sw_clk, rstn;
output full, empty;
input RD_DATA_VALID_DDR, RD_DATA_VALID_OCM;
input [max_burst_bits-1:0] RD_DATA_DDR, RD_DATA_OCM;
input req, invalid_rd_req;
input [rd_info_bits-1:0] rd_info;
reg [intr_cnt_width-1:0] wr_ptr = 0, rd_ptr = 0;
reg [rd_afi_fifo_bits-1:0] rd_fifo [0:intr_max_outstanding-1]; // Data, addr, size, burst, len, RID, RRESP, valid bytes
wire full, empty;
assign empty = (wr_ptr === rd_ptr)?1'b1: 1'b0;
assign full = ((wr_ptr[intr_cnt_width-1]!== rd_ptr[intr_cnt_width-1]) && (wr_ptr[intr_cnt_width-2:0] === rd_ptr[intr_cnt_width-2:0]))?1'b1 :1'b0;
/* read from the fifo */
task read_mem;
output [rd_afi_fifo_bits-1:0] data;
begin
data = rd_fifo[rd_ptr[intr_cnt_width-1:0]];
if(rd_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1)
rd_ptr[intr_cnt_width-2:0] = 0;
else
rd_ptr = rd_ptr + 1;
end
endtask
reg state;
reg invalid_rd;
/* write in the fifo */
always@(negedge rstn or posedge sw_clk)
begin
if(!rstn) begin
wr_ptr = 0;
rd_ptr = 0;
state = 0;
invalid_rd = 0;
end else begin
case (state)
0 : begin
state = 0;
invalid_rd = 0;
if(req)begin
state = 1;
invalid_rd = invalid_rd_req;
end
end
1 : begin
state = 1;
if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd) begin
if(RD_DATA_VALID_DDR)
rd_fifo[wr_ptr[intr_cnt_width-2:0]] = {RD_DATA_DDR,rd_info};
else if(RD_DATA_VALID_OCM)
rd_fifo[wr_ptr[intr_cnt_width-2:0]] = {RD_DATA_OCM,rd_info};
else
rd_fifo[wr_ptr[intr_cnt_width-2:0]] = rd_info;
if(wr_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1)
wr_ptr[intr_cnt_width-2:0] = 0;
else
wr_ptr = wr_ptr + 1;
state = 0;
invalid_rd = 0;
end
end
endcase
end
end
endmodule
|
module fmrv32im_plic
(
input RST_N,
input CLK,
input BUS_WE,
input [3:0] BUS_ADDR,
input [31:0] BUS_WDATA,
output reg [31:0] BUS_RDATA,
input [31:0] INT_IN,
output wire INT_OUT
);
// Interrupt Mask
reg [31:0] int_reg, int_mask;
always @(posedge CLK) begin
if(!RST_N) begin
int_mask <= 0;
end else begin
if(BUS_WE & (BUS_ADDR == 4'h1)) begin
int_mask <= BUS_WDATA;
end
end
end
wire BUS_WE_reg;
assign BUS_WE_reg = BUS_WE & (BUS_ADDR == 4'h0);
// Interrupt Register
always @(posedge CLK) begin
if(!RST_N) begin
int_reg <= 0;
end else begin
int_reg[00] <= INT_IN[00] | (BUS_WE_reg & BUS_WDATA[00])?1'b0:int_reg[00];
int_reg[01] <= INT_IN[01] | (BUS_WE_reg & BUS_WDATA[01])?1'b0:int_reg[01];
int_reg[02] <= INT_IN[02] | (BUS_WE_reg & BUS_WDATA[02])?1'b0:int_reg[02];
int_reg[03] <= INT_IN[03] | (BUS_WE_reg & BUS_WDATA[03])?1'b0:int_reg[03];
int_reg[04] <= INT_IN[04] | (BUS_WE_reg & BUS_WDATA[04])?1'b0:int_reg[04];
int_reg[05] <= INT_IN[05] | (BUS_WE_reg & BUS_WDATA[05])?1'b0:int_reg[05];
int_reg[06] <= INT_IN[06] | (BUS_WE_reg & BUS_WDATA[06])?1'b0:int_reg[06];
int_reg[07] <= INT_IN[07] | (BUS_WE_reg & BUS_WDATA[07])?1'b0:int_reg[07];
int_reg[08] <= INT_IN[08] | (BUS_WE_reg & BUS_WDATA[08])?1'b0:int_reg[08];
int_reg[09] <= INT_IN[09] | (BUS_WE_reg & BUS_WDATA[09])?1'b0:int_reg[09];
int_reg[10] <= INT_IN[10] | (BUS_WE_reg & BUS_WDATA[10])?1'b0:int_reg[10];
int_reg[11] <= INT_IN[11] | (BUS_WE_reg & BUS_WDATA[11])?1'b0:int_reg[11];
int_reg[12] <= INT_IN[12] | (BUS_WE_reg & BUS_WDATA[12])?1'b0:int_reg[12];
int_reg[13] <= INT_IN[13] | (BUS_WE_reg & BUS_WDATA[13])?1'b0:int_reg[13];
int_reg[14] <= INT_IN[14] | (BUS_WE_reg & BUS_WDATA[14])?1'b0:int_reg[14];
int_reg[15] <= INT_IN[15] | (BUS_WE_reg & BUS_WDATA[15])?1'b0:int_reg[15];
int_reg[16] <= INT_IN[16] | (BUS_WE_reg & BUS_WDATA[16])?1'b0:int_reg[16];
int_reg[17] <= INT_IN[17] | (BUS_WE_reg & BUS_WDATA[17])?1'b0:int_reg[17];
int_reg[18] <= INT_IN[18] | (BUS_WE_reg & BUS_WDATA[18])?1'b0:int_reg[18];
int_reg[19] <= INT_IN[19] | (BUS_WE_reg & BUS_WDATA[19])?1'b0:int_reg[19];
int_reg[20] <= INT_IN[20] | (BUS_WE_reg & BUS_WDATA[20])?1'b0:int_reg[20];
int_reg[21] <= INT_IN[21] | (BUS_WE_reg & BUS_WDATA[21])?1'b0:int_reg[21];
int_reg[22] <= INT_IN[22] | (BUS_WE_reg & BUS_WDATA[22])?1'b0:int_reg[22];
int_reg[23] <= INT_IN[23] | (BUS_WE_reg & BUS_WDATA[23])?1'b0:int_reg[23];
int_reg[24] <= INT_IN[24] | (BUS_WE_reg & BUS_WDATA[24])?1'b0:int_reg[24];
int_reg[25] <= INT_IN[25] | (BUS_WE_reg & BUS_WDATA[25])?1'b0:int_reg[25];
int_reg[26] <= INT_IN[26] | (BUS_WE_reg & BUS_WDATA[26])?1'b0:int_reg[26];
int_reg[27] <= INT_IN[27] | (BUS_WE_reg & BUS_WDATA[27])?1'b0:int_reg[27];
int_reg[28] <= INT_IN[28] | (BUS_WE_reg & BUS_WDATA[28])?1'b0:int_reg[28];
int_reg[29] <= INT_IN[29] | (BUS_WE_reg & BUS_WDATA[29])?1'b0:int_reg[29];
int_reg[30] <= INT_IN[30] | (BUS_WE_reg & BUS_WDATA[30])?1'b0:int_reg[30];
int_reg[31] <= INT_IN[31] | (BUS_WE_reg & BUS_WDATA[31])?1'b0:int_reg[31];
end // else: !if(!RST_N)
end
assign INT_OUT = |(int_reg & (~(int_mask)));
always @(*) begin
case(BUS_ADDR)
4'h0:
begin
BUS_RDATA <= int_reg;
end
4'h1:
begin
BUS_RDATA <= int_mask;
end
default:
begin
BUS_RDATA <= 32'd0;
end
endcase
end
endmodule // fmrv32im_plic
|
// soc_system_fpga_only_master.v
// This file was auto-generated from altera_jtag_avalon_master_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.1 186 at 2015.01.06.14:12:46
`timescale 1 ps / 1 ps
module soc_system_fpga_only_master #(
parameter USE_PLI = 0,
parameter PLI_PORT = 50000,
parameter FIFO_DEPTHS = 2
) (
input wire clk_clk, // clk.clk
input wire clk_reset_reset, // clk_reset.reset
output wire [31:0] master_address, // master.address
input wire [31:0] master_readdata, // .readdata
output wire master_read, // .read
output wire master_write, // .write
output wire [31:0] master_writedata, // .writedata
input wire master_waitrequest, // .waitrequest
input wire master_readdatavalid, // .readdatavalid
output wire [3:0] master_byteenable, // .byteenable
output wire master_reset_reset // master_reset.reset
);
wire jtag_phy_embedded_in_jtag_master_src_valid; // jtag_phy_embedded_in_jtag_master:source_valid -> timing_adt:in_valid
wire [7:0] jtag_phy_embedded_in_jtag_master_src_data; // jtag_phy_embedded_in_jtag_master:source_data -> timing_adt:in_data
wire timing_adt_out_valid; // timing_adt:out_valid -> fifo:in_valid
wire [7:0] timing_adt_out_data; // timing_adt:out_data -> fifo:in_data
wire timing_adt_out_ready; // fifo:in_ready -> timing_adt:out_ready
wire fifo_out_valid; // fifo:out_valid -> b2p:in_valid
wire [7:0] fifo_out_data; // fifo:out_data -> b2p:in_data
wire fifo_out_ready; // b2p:in_ready -> fifo:out_ready
wire b2p_out_packets_stream_valid; // b2p:out_valid -> b2p_adapter:in_valid
wire [7:0] b2p_out_packets_stream_data; // b2p:out_data -> b2p_adapter:in_data
wire b2p_out_packets_stream_ready; // b2p_adapter:in_ready -> b2p:out_ready
wire [7:0] b2p_out_packets_stream_channel; // b2p:out_channel -> b2p_adapter:in_channel
wire b2p_out_packets_stream_startofpacket; // b2p:out_startofpacket -> b2p_adapter:in_startofpacket
wire b2p_out_packets_stream_endofpacket; // b2p:out_endofpacket -> b2p_adapter:in_endofpacket
wire b2p_adapter_out_valid; // b2p_adapter:out_valid -> transacto:in_valid
wire [7:0] b2p_adapter_out_data; // b2p_adapter:out_data -> transacto:in_data
wire b2p_adapter_out_ready; // transacto:in_ready -> b2p_adapter:out_ready
wire b2p_adapter_out_startofpacket; // b2p_adapter:out_startofpacket -> transacto:in_startofpacket
wire b2p_adapter_out_endofpacket; // b2p_adapter:out_endofpacket -> transacto:in_endofpacket
wire transacto_out_stream_valid; // transacto:out_valid -> p2b_adapter:in_valid
wire [7:0] transacto_out_stream_data; // transacto:out_data -> p2b_adapter:in_data
wire transacto_out_stream_ready; // p2b_adapter:in_ready -> transacto:out_ready
wire transacto_out_stream_startofpacket; // transacto:out_startofpacket -> p2b_adapter:in_startofpacket
wire transacto_out_stream_endofpacket; // transacto:out_endofpacket -> p2b_adapter:in_endofpacket
wire p2b_adapter_out_valid; // p2b_adapter:out_valid -> p2b:in_valid
wire [7:0] p2b_adapter_out_data; // p2b_adapter:out_data -> p2b:in_data
wire p2b_adapter_out_ready; // p2b:in_ready -> p2b_adapter:out_ready
wire [7:0] p2b_adapter_out_channel; // p2b_adapter:out_channel -> p2b:in_channel
wire p2b_adapter_out_startofpacket; // p2b_adapter:out_startofpacket -> p2b:in_startofpacket
wire p2b_adapter_out_endofpacket; // p2b_adapter:out_endofpacket -> p2b:in_endofpacket
wire p2b_out_bytes_stream_valid; // p2b:out_valid -> jtag_phy_embedded_in_jtag_master:sink_valid
wire [7:0] p2b_out_bytes_stream_data; // p2b:out_data -> jtag_phy_embedded_in_jtag_master:sink_data
wire p2b_out_bytes_stream_ready; // jtag_phy_embedded_in_jtag_master:sink_ready -> p2b:out_ready
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [b2p:reset_n, b2p_adapter:reset_n, fifo:reset, jtag_phy_embedded_in_jtag_master:reset_n, p2b:reset_n, p2b_adapter:reset_n, timing_adt:reset_n, transacto:reset_n]
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (USE_PLI != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
use_pli_check ( .error(1'b1) );
end
if (PLI_PORT != 50000)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
pli_port_check ( .error(1'b1) );
end
if (FIFO_DEPTHS != 2)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
fifo_depths_check ( .error(1'b1) );
end
endgenerate
altera_avalon_st_jtag_interface #(
.PURPOSE (1),
.UPSTREAM_FIFO_SIZE (0),
.DOWNSTREAM_FIFO_SIZE (64),
.MGMT_CHANNEL_WIDTH (-1),
.EXPORT_JTAG (0),
.USE_PLI (0),
.PLI_PORT (50000)
) jtag_phy_embedded_in_jtag_master (
.clk (clk_clk), // clock.clk
.reset_n (~rst_controller_reset_out_reset), // clock_reset.reset_n
.source_data (jtag_phy_embedded_in_jtag_master_src_data), // src.data
.source_valid (jtag_phy_embedded_in_jtag_master_src_valid), // .valid
.sink_data (p2b_out_bytes_stream_data), // sink.data
.sink_valid (p2b_out_bytes_stream_valid), // .valid
.sink_ready (p2b_out_bytes_stream_ready), // .ready
.resetrequest (master_reset_reset), // resetrequest.reset
.source_ready (1'b1), // (terminated)
.mgmt_valid (), // (terminated)
.mgmt_channel (), // (terminated)
.mgmt_data (), // (terminated)
.jtag_tck (1'b0), // (terminated)
.jtag_tms (1'b0), // (terminated)
.jtag_tdi (1'b0), // (terminated)
.jtag_tdo (), // (terminated)
.jtag_ena (1'b0), // (terminated)
.jtag_usr1 (1'b0), // (terminated)
.jtag_clr (1'b0), // (terminated)
.jtag_clrn (1'b0), // (terminated)
.jtag_state_tlr (1'b0), // (terminated)
.jtag_state_rti (1'b0), // (terminated)
.jtag_state_sdrs (1'b0), // (terminated)
.jtag_state_cdr (1'b0), // (terminated)
.jtag_state_sdr (1'b0), // (terminated)
.jtag_state_e1dr (1'b0), // (terminated)
.jtag_state_pdr (1'b0), // (terminated)
.jtag_state_e2dr (1'b0), // (terminated)
.jtag_state_udr (1'b0), // (terminated)
.jtag_state_sirs (1'b0), // (terminated)
.jtag_state_cir (1'b0), // (terminated)
.jtag_state_sir (1'b0), // (terminated)
.jtag_state_e1ir (1'b0), // (terminated)
.jtag_state_pir (1'b0), // (terminated)
.jtag_state_e2ir (1'b0), // (terminated)
.jtag_state_uir (1'b0), // (terminated)
.jtag_ir_in (3'b000), // (terminated)
.jtag_irq (), // (terminated)
.jtag_ir_out () // (terminated)
);
soc_system_fpga_only_master_timing_adt timing_adt (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.in_data (jtag_phy_embedded_in_jtag_master_src_data), // in.data
.in_valid (jtag_phy_embedded_in_jtag_master_src_valid), // .valid
.out_data (timing_adt_out_data), // out.data
.out_valid (timing_adt_out_valid), // .valid
.out_ready (timing_adt_out_ready) // .ready
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (8),
.FIFO_DEPTH (64),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (timing_adt_out_data), // in.data
.in_valid (timing_adt_out_valid), // .valid
.in_ready (timing_adt_out_ready), // .ready
.out_data (fifo_out_data), // out.data
.out_valid (fifo_out_valid), // .valid
.out_ready (fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_st_bytes_to_packets #(
.CHANNEL_WIDTH (8),
.ENCODING (0)
) b2p (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
.out_channel (b2p_out_packets_stream_channel), // out_packets_stream.channel
.out_ready (b2p_out_packets_stream_ready), // .ready
.out_valid (b2p_out_packets_stream_valid), // .valid
.out_data (b2p_out_packets_stream_data), // .data
.out_startofpacket (b2p_out_packets_stream_startofpacket), // .startofpacket
.out_endofpacket (b2p_out_packets_stream_endofpacket), // .endofpacket
.in_ready (fifo_out_ready), // in_bytes_stream.ready
.in_valid (fifo_out_valid), // .valid
.in_data (fifo_out_data) // .data
);
altera_avalon_st_packets_to_bytes #(
.CHANNEL_WIDTH (8),
.ENCODING (0)
) p2b (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
.in_ready (p2b_adapter_out_ready), // in_packets_stream.ready
.in_valid (p2b_adapter_out_valid), // .valid
.in_data (p2b_adapter_out_data), // .data
.in_channel (p2b_adapter_out_channel), // .channel
.in_startofpacket (p2b_adapter_out_startofpacket), // .startofpacket
.in_endofpacket (p2b_adapter_out_endofpacket), // .endofpacket
.out_ready (p2b_out_bytes_stream_ready), // out_bytes_stream.ready
.out_valid (p2b_out_bytes_stream_valid), // .valid
.out_data (p2b_out_bytes_stream_data) // .data
);
altera_avalon_packets_to_master #(
.FAST_VER (0),
.FIFO_DEPTHS (2),
.FIFO_WIDTHU (1)
) transacto (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
.out_ready (transacto_out_stream_ready), // out_stream.ready
.out_valid (transacto_out_stream_valid), // .valid
.out_data (transacto_out_stream_data), // .data
.out_startofpacket (transacto_out_stream_startofpacket), // .startofpacket
.out_endofpacket (transacto_out_stream_endofpacket), // .endofpacket
.in_ready (b2p_adapter_out_ready), // in_stream.ready
.in_valid (b2p_adapter_out_valid), // .valid
.in_data (b2p_adapter_out_data), // .data
.in_startofpacket (b2p_adapter_out_startofpacket), // .startofpacket
.in_endofpacket (b2p_adapter_out_endofpacket), // .endofpacket
.address (master_address), // avalon_master.address
.readdata (master_readdata), // .readdata
.read (master_read), // .read
.write (master_write), // .write
.writedata (master_writedata), // .writedata
.waitrequest (master_waitrequest), // .waitrequest
.readdatavalid (master_readdatavalid), // .readdatavalid
.byteenable (master_byteenable) // .byteenable
);
soc_system_fpga_only_master_b2p_adapter b2p_adapter (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.in_data (b2p_out_packets_stream_data), // in.data
.in_valid (b2p_out_packets_stream_valid), // .valid
.in_ready (b2p_out_packets_stream_ready), // .ready
.in_startofpacket (b2p_out_packets_stream_startofpacket), // .startofpacket
.in_endofpacket (b2p_out_packets_stream_endofpacket), // .endofpacket
.in_channel (b2p_out_packets_stream_channel), // .channel
.out_data (b2p_adapter_out_data), // out.data
.out_valid (b2p_adapter_out_valid), // .valid
.out_ready (b2p_adapter_out_ready), // .ready
.out_startofpacket (b2p_adapter_out_startofpacket), // .startofpacket
.out_endofpacket (b2p_adapter_out_endofpacket) // .endofpacket
);
soc_system_fpga_only_master_p2b_adapter p2b_adapter (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.in_data (transacto_out_stream_data), // in.data
.in_valid (transacto_out_stream_valid), // .valid
.in_ready (transacto_out_stream_ready), // .ready
.in_startofpacket (transacto_out_stream_startofpacket), // .startofpacket
.in_endofpacket (transacto_out_stream_endofpacket), // .endofpacket
.out_data (p2b_adapter_out_data), // out.data
.out_valid (p2b_adapter_out_valid), // .valid
.out_ready (p2b_adapter_out_ready), // .ready
.out_startofpacket (p2b_adapter_out_startofpacket), // .startofpacket
.out_endofpacket (p2b_adapter_out_endofpacket), // .endofpacket
.out_channel (p2b_adapter_out_channel) // .channel
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (clk_reset_reset), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLCLKP_FUNCTIONAL_V
`define SKY130_FD_SC_MS__DLCLKP_FUNCTIONAL_V
/**
* dlclkp: Clock gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p/sky130_fd_sc_ms__udp_dlatch_p.v"
`celldefine
module sky130_fd_sc_ms__dlclkp (
GCLK,
GATE,
CLK
);
// Module ports
output GCLK;
input GATE;
input CLK ;
// Local signals
wire m0 ;
wire clkn;
// Name Output Other arguments
not not0 (clkn , CLK );
sky130_fd_sc_ms__udp_dlatch$P dlatch0 (m0 , GATE, clkn );
and and0 (GCLK , m0, CLK );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLCLKP_FUNCTIONAL_V |
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module is a buffer that holds characters to be displayed on a *
* VGA or LCD screen. *
* *
******************************************************************************/
module niosII_system_video_character_buffer_with_dma_0 (
// Inputs
clk,
reset,
ctrl_address,
ctrl_byteenable,
ctrl_chipselect,
ctrl_read,
ctrl_write,
ctrl_writedata,
buf_address,
buf_byteenable,
buf_chipselect,
buf_read,
buf_write,
buf_writedata,
stream_ready,
// Bidirectionals
// Outputs
ctrl_readdata,
buf_readdata,
buf_waitrequest,
stream_data,
stream_startofpacket,
stream_endofpacket,
stream_empty,
stream_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 8;
parameter ENLARGE_CHAR = 0;
parameter AW = 13;
parameter BUFFER_SIZE = 8192;
parameter PIXELS = 640;
parameter LINES = 480;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input ctrl_address;
input [ 3: 0] ctrl_byteenable;
input ctrl_chipselect;
input ctrl_read;
input ctrl_write;
input [31: 0] ctrl_writedata;
input [(AW-1): 0] buf_address;
input buf_byteenable;
input buf_chipselect;
input buf_read;
input buf_write;
input [ 7: 0] buf_writedata;
input stream_ready;
// Bidirectionals
// Outputs
output reg [31: 0] ctrl_readdata;
output reg [ 7: 0] buf_readdata;
output buf_waitrequest;
output [29: 0] stream_data;
output stream_startofpacket;
output stream_endofpacket;
output [ 1: 0] stream_empty;
output stream_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
//localparam NUMBER_OF_BITS_FOR_X_COORD = 10;
//localparam NUMBER_OF_BITS_FOR_Y_COORD = 9;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [DW: 1] char_data_to_buffer;
wire [DW: 1] char_data_from_buffer;
wire [AW: 1] cur_char_position;
wire [15: 0] cur_char_for_display;
wire cur_char_data;
wire [ 9: 0] char_red;
wire [ 9: 0] char_green;
wire [ 9: 0] char_blue;
// Internal Registers
reg [31: 0] control_reg;
reg [ 1: 0] delayed_buf_waitrequest;
reg clear_screen;
reg [ 9: 0] x_position;
reg [ 8: 0] y_position;
reg [ 5: 0] delayed_x_position;
reg [ 5: 0] delayed_y_position;
reg [ 3: 0] delayed_startofpacket;
reg [ 3: 0] delayed_endofpacket;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
ctrl_readdata <= 32'h00000000;
else if (ctrl_chipselect & ctrl_read & ctrl_address)
ctrl_readdata <= {16'd60, 16'd80};
else if (ctrl_chipselect & ctrl_read)
ctrl_readdata <= control_reg;
end
always @(posedge clk)
begin
if (reset)
buf_readdata <= 8'h00;
else if (buf_chipselect & buf_read)
buf_readdata <= {1'b0, char_data_from_buffer[7:1]};
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
control_reg <= 32'h00010000;
else if (ctrl_chipselect & ctrl_write & ~ctrl_address)
begin
if (ctrl_byteenable[0])
control_reg[ 7: 0] <= ctrl_writedata[ 7: 0];
if (ctrl_byteenable[1])
control_reg[15: 8] <= ctrl_writedata[15: 8];
if (ctrl_byteenable[2])
control_reg[23:16] <= ctrl_writedata[23:16];
if (ctrl_byteenable[3])
control_reg[31:24] <= ctrl_writedata[31:24];
end
else if (clear_screen & stream_ready &
(x_position == (PIXELS - 1)) && (y_position == (LINES - 1)))
control_reg[16] <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
delayed_buf_waitrequest <= 2'h0;
else if (buf_chipselect & buf_read)
delayed_buf_waitrequest <= {delayed_buf_waitrequest[0], 1'b1};
else
delayed_buf_waitrequest <= 2'h0;
end
always @(posedge clk)
begin
if (reset)
clear_screen <= 1'b1;
else if (~(control_reg[16]))
clear_screen <= 1'b0;
else if ((x_position == 10'h000) && (y_position == 9'h000))
clear_screen <= 1'b1;
end
always @(posedge clk)
begin
if (reset)
x_position <= 10'h000;
else if (stream_ready)
begin
if (x_position == (PIXELS - 1))
x_position <= 10'h000;
else
x_position <= x_position + 10'h001;
end
end
always @(posedge clk)
begin
if (reset)
y_position <= 9'h000;
else if (stream_ready && (x_position == (PIXELS - 1)))
begin
if (y_position == (LINES - 1))
y_position <= 9'h000;
else
y_position <= y_position + 9'h001;
end
end
always @(posedge clk)
begin
if (reset)
begin
delayed_x_position <= 6'h00;
delayed_y_position <= 6'h00;
end
else if (stream_ready)
begin
delayed_x_position <= {delayed_x_position[2:0],
x_position[(ENLARGE_CHAR+2):ENLARGE_CHAR]};
delayed_y_position <= {delayed_y_position[2:0],
y_position[(ENLARGE_CHAR+2):ENLARGE_CHAR]};
end
end
always @(posedge clk)
begin
if (reset)
delayed_startofpacket <= 4'h0;
else if (stream_ready)
begin
delayed_startofpacket[3:1] <= delayed_startofpacket[2:0];
if ((x_position == 10'h000) && (y_position == 9'h000))
delayed_startofpacket[0] <= 1'b1;
else
delayed_startofpacket[0] <= 1'b0;
end
end
always @(posedge clk)
begin
if (reset)
delayed_endofpacket <= 4'h0;
else if (stream_ready)
begin
delayed_endofpacket[3:1] <= delayed_endofpacket[2:0];
if ((x_position == (PIXELS - 1)) && (y_position == (LINES - 1)))
delayed_endofpacket[0] <= 1'b1;
else
delayed_endofpacket[0] <= 1'b0;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign buf_waitrequest =
(buf_chipselect & buf_read) & ~delayed_buf_waitrequest[1];
assign stream_data[29: 0] = {char_red, char_green, char_blue};
assign stream_startofpacket = delayed_startofpacket[3];
assign stream_endofpacket = delayed_endofpacket[3];
assign stream_empty = 2'h0;
assign stream_valid = 1'b1;
// Internal Assignments
assign char_data_to_buffer = {control_reg[(DW-8):0], buf_writedata[6:0]};
assign cur_char_position =
{y_position[8:(3 + ENLARGE_CHAR)], x_position[9:(3 + ENLARGE_CHAR)]};
assign char_red = {10{cur_char_data}};
assign char_green = {10{cur_char_data}};
assign char_blue = {10{cur_char_data}};
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altsyncram Char_Buffer_Memory (
// Inputs
.clock0 (clk),
.address_a (buf_address),
.wren_a (buf_byteenable & buf_chipselect & buf_write),
.data_a (char_data_to_buffer),
.clock1 (clk),
.clocken1 (stream_ready),
.address_b (cur_char_position),
.wren_b (clear_screen),
.data_b ({{(DW - 7){1'b0}}, 7'h20}),
// Bidirectionals
// Outputs
.q_a (char_data_from_buffer),
.q_b (cur_char_for_display),
// Unused
.rden_b (1'b1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.clocken0 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.byteena_a (1'b1),
.byteena_b (1'b1),
.rden_a (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0)
);
defparam
Char_Buffer_Memory.init_file = "UNUSED",
Char_Buffer_Memory.intended_device_family = "Cyclone II",
Char_Buffer_Memory.lpm_type = "altsyncram",
Char_Buffer_Memory.operation_mode = "BIDIR_DUAL_PORT",
Char_Buffer_Memory.read_during_write_mode_mixed_ports = "DONT_CARE",
Char_Buffer_Memory.power_up_uninitialized = "FALSE",
Char_Buffer_Memory.address_reg_b = "CLOCK1",
Char_Buffer_Memory.indata_reg_b = "CLOCK1",
Char_Buffer_Memory.wrcontrol_wraddress_reg_b = "CLOCK1",
Char_Buffer_Memory.clock_enable_input_a = "BYPASS",
Char_Buffer_Memory.clock_enable_input_b = "NORMAL",
Char_Buffer_Memory.clock_enable_output_a = "BYPASS",
Char_Buffer_Memory.clock_enable_output_b = "NORMAL",
Char_Buffer_Memory.numwords_a = BUFFER_SIZE,
Char_Buffer_Memory.numwords_b = BUFFER_SIZE,
Char_Buffer_Memory.outdata_aclr_a = "NONE",
Char_Buffer_Memory.outdata_aclr_b = "NONE",
Char_Buffer_Memory.outdata_reg_a = "CLOCK0",
Char_Buffer_Memory.outdata_reg_b = "CLOCK1",
Char_Buffer_Memory.widthad_a = AW,
Char_Buffer_Memory.widthad_b = AW,
Char_Buffer_Memory.width_a = DW,
Char_Buffer_Memory.width_b = DW,
Char_Buffer_Memory.width_byteena_a = 1,
Char_Buffer_Memory.width_byteena_b = 1;
altera_up_video_128_character_rom Character_Rom (
// Inputs
.clk (clk),
.clk_en (stream_ready),
.character (cur_char_for_display[ 6: 0]),
.x_coordinate (delayed_x_position[ 5: 3]),
.y_coordinate (delayed_y_position[ 5: 3]),
// Bidirectionals
// Outputs
.character_data (cur_char_data)
);
endmodule
|
(** * Hoare2: Hoare Logic, Part II *)
Require Export Hoare.
(* ####################################################### *)
(** * Decorated Programs *)
(** The beauty of Hoare Logic is that it is _compositional_ --
the structure of proofs exactly follows the structure of programs.
This suggests that we can record the essential ideas of a proof
informally (leaving out some low-level calculational details) by
decorating programs with appropriate assertions around each
statement. Such a _decorated program_ carries with it
an (informal) proof of its own correctness. *)
(** For example, here is a complete decorated program: *)
(**
{{ True }} ->>
{{ m = m }}
X ::= m;;
{{ X = m }} ->>
{{ X = m /\ p = p }}
Z ::= p;
{{ X = m /\ Z = p }} ->>
{{ Z - X = p - m }}
WHILE X <> 0 DO
{{ Z - X = p - m /\ X <> 0 }} ->>
{{ (Z - 1) - (X - 1) = p - m }}
Z ::= Z - 1;;
{{ Z - (X - 1) = p - m }}
X ::= X - 1
{{ Z - X = p - m }}
END;
{{ Z - X = p - m /\ ~ (X <> 0) }} ->>
{{ Z = p - m }}
*)
(** Concretely, a decorated program consists of the program text
interleaved with assertions. To check that a decorated program
represents a valid proof, we check that each individual command is
_locally consistent_ with its accompanying assertions in the
following sense: *)
(**
- [SKIP] is locally consistent if its precondition and
postcondition are the same:
{{ P }}
SKIP
{{ P }}
*)
(**
- The sequential composition of [c1] and [c2] is locally
consistent (with respect to assertions [P] and [R]) if [c1] is
locally consistent (with respect to [P] and [Q]) and [c2] is
locally consistent (with respect to [Q] and [R]):
{{ P }}
c1;;
{{ Q }}
c2
{{ R }}
*)
(**
- An assignment is locally consistent if its precondition is
the appropriate substitution of its postcondition:
{{ P [X |-> a] }}
X ::= a
{{ P }}
*)
(**
- A conditional is locally consistent (with respect to assertions
[P] and [Q]) if the assertions at the top of its "then" and
"else" branches are exactly [P /\ b] and [P /\ ~b] and if its "then"
branch is locally consistent (with respect to [P /\ b] and [Q])
and its "else" branch is locally consistent (with respect to
[P /\ ~b] and [Q]):
{{ P }}
IFB b THEN
{{ P /\ b }}
c1
{{ Q }}
ELSE
{{ P /\ ~b }}
c2
{{ Q }}
FI
{{ Q }}
*)
(**
- A while loop with precondition [P] is locally consistent if its
postcondition is [P /\ ~b] and if the pre- and postconditions of
its body are exactly [P /\ b] and [P]:
{{ P }}
WHILE b DO
{{ P /\ b }}
c1
{{ P }}
END
{{ P /\ ~b }}
*)
(**
- A pair of assertions separated by [->>] is locally consistent if
the first implies the second (in all states):
{{ P }} ->>
{{ P' }}
This corresponds to the application of [hoare_consequence] and
is the only place in a decorated program where checking if
decorations are correct is not fully mechanical and syntactic,
but involves logical and/or arithmetic reasoning.
*)
(** We have seen above how _verifying_ the correctness of a
given proof involves checking that every single command is locally
consistent with the accompanying assertions. If we are instead
interested in _finding_ a proof for a given specification we need
to discover the right assertions. This can be done in an almost
automatic way, with the exception of finding loop invariants,
which is the subject of in the next section. In the reminder of
this section we explain in detail how to construct decorations for
several simple programs that don't involve non-trivial loop
invariants. *)
(* ####################################################### *)
(** ** Example: Swapping Using Addition and Subtraction *)
(** Here is a program that swaps the values of two variables using
addition and subtraction (instead of by assigning to a temporary
variable).
X ::= X + Y;;
Y ::= X - Y;;
X ::= X - Y
We can prove using decorations that this program is correct --
i.e., it always swaps the values of variables [X] and [Y]. *)
(**
(1) {{ X = m /\ Y = n }} ->>
(2) {{ (X + Y) - ((X + Y) - Y) = n /\ (X + Y) - Y = m }}
X ::= X + Y;;
(3) {{ X - (X - Y) = n /\ X - Y = m }}
Y ::= X - Y;;
(4) {{ X - Y = n /\ Y = m }}
X ::= X - Y
(5) {{ X = n /\ Y = m }}
The decorations were constructed as follows:
- We begin with the undecorated program (the unnumbered lines).
- We then add the specification -- i.e., the outer
precondition (1) and postcondition (5). In the precondition we
use auxiliary variables (parameters) [m] and [n] to remember
the initial values of variables [X] and respectively [Y], so
that we can refer to them in the postcondition (5).
- We work backwards mechanically starting from (5) all the way
to (2). At each step, we obtain the precondition of the
assignment from its postcondition by substituting the assigned
variable with the right-hand-side of the assignment. For
instance, we obtain (4) by substituting [X] with [X - Y]
in (5), and (3) by substituting [Y] with [X - Y] in (4).
- Finally, we verify that (1) logically implies (2) -- i.e.,
that the step from (1) to (2) is a valid use of the law of
consequence. For this we substitute [X] by [m] and [Y] by [n]
and calculate as follows:
(m + n) - ((m + n) - n) = n /\ (m + n) - n = m
(m + n) - m = n /\ m = m
n = n /\ m = m
(Note that, since we are working with natural numbers, not
fixed-size machine integers, we don't need to worry about the
possibility of arithmetic overflow anywhere in this argument.)
*)
(* ####################################################### *)
(** ** Example: Simple Conditionals *)
(** Here is a simple decorated program using conditionals:
(1) {{True}}
IFB X <= Y THEN
(2) {{True /\ X <= Y}} ->>
(3) {{(Y - X) + X = Y \/ (Y - X) + Y = X}}
Z ::= Y - X
(4) {{Z + X = Y \/ Z + Y = X}}
ELSE
(5) {{True /\ ~(X <= Y) }} ->>
(6) {{(X - Y) + X = Y \/ (X - Y) + Y = X}}
Z ::= X - Y
(7) {{Z + X = Y \/ Z + Y = X}}
FI
(8) {{Z + X = Y \/ Z + Y = X}}
These decorations were constructed as follows:
- We start with the outer precondition (1) and postcondition (8).
- We follow the format dictated by the [hoare_if] rule and copy the
postcondition (8) to (4) and (7). We conjoin the precondition (1)
with the guard of the conditional to obtain (2). We conjoin (1)
with the negated guard of the conditional to obtain (5).
- In order to use the assignment rule and obtain (3), we substitute
[Z] by [Y - X] in (4). To obtain (6) we substitute [Z] by [X - Y]
in (7).
- Finally, we verify that (2) implies (3) and (5) implies (6). Both
of these implications crucially depend on the ordering of [X] and
[Y] obtained from the guard. For instance, knowing that [X <= Y]
ensures that subtracting [X] from [Y] and then adding back [X]
produces [Y], as required by the first disjunct of (3). Similarly,
knowing that [~(X <= Y)] ensures that subtracting [Y] from [X] and
then adding back [Y] produces [X], as needed by the second
disjunct of (6). Note that [n - m + m = n] does _not_ hold for
arbitrary natural numbers [n] and [m] (for example, [3 - 5 + 5 =
5]). *)
(** **** Exercise: 2 stars (if_minus_plus_reloaded) *)
(** Fill in valid decorations for the following program:
{{ True }}
IFB X <= Y THEN
{{ }} ->>
{{ }}
Z ::= Y - X
{{ }}
ELSE
{{ }} ->>
{{ }}
Y ::= X + Z
{{ }}
FI
{{ Y = X + Z }}
*)
(** [] *)
(* ####################################################### *)
(** ** Example: Reduce to Zero (Trivial Loop) *)
(** Here is a [WHILE] loop that is so simple it needs no
invariant (i.e., the invariant [True] will do the job).
(1) {{ True }}
WHILE X <> 0 DO
(2) {{ True /\ X <> 0 }} ->>
(3) {{ True }}
X ::= X - 1
(4) {{ True }}
END
(5) {{ True /\ X = 0 }} ->>
(6) {{ X = 0 }}
The decorations can be constructed as follows:
- Start with the outer precondition (1) and postcondition (6).
- Following the format dictated by the [hoare_while] rule, we copy
(1) to (4). We conjoin (1) with the guard to obtain (2) and with
the negation of the guard to obtain (5). Note that, because the
outer postcondition (6) does not syntactically match (5), we need a
trivial use of the consequence rule from (5) to (6).
- Assertion (3) is the same as (4), because [X] does not appear in
[4], so the substitution in the assignment rule is trivial.
- Finally, the implication between (2) and (3) is also trivial.
*)
(** From this informal proof, it is easy to read off a formal proof
using the Coq versions of the Hoare rules. Note that we do _not_
unfold the definition of [hoare_triple] anywhere in this proof --
the idea is to use the Hoare rules as a "self-contained" logic for
reasoning about programs. *)
Definition reduce_to_zero' : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
X ::= AMinus (AId X) (ANum 1)
END.
Theorem reduce_to_zero_correct' :
{{fun st => True}}
reduce_to_zero'
{{fun st => st X = 0}}.
Proof.
unfold reduce_to_zero'.
(* First we need to transform the postcondition so
that hoare_while will apply. *)
eapply hoare_consequence_post.
apply hoare_while.
Case "Loop body preserves invariant".
(* Need to massage precondition before [hoare_asgn] applies *)
eapply hoare_consequence_pre. apply hoare_asgn.
(* Proving trivial implication (2) ->> (3) *)
intros st [HT Hbp]. unfold assn_sub. apply I.
Case "Invariant and negated guard imply postcondition".
intros st [Inv GuardFalse].
unfold bassn in GuardFalse. simpl in GuardFalse.
(* SearchAbout helps to find the right lemmas *)
SearchAbout [not true].
rewrite not_true_iff_false in GuardFalse.
SearchAbout [negb false].
rewrite negb_false_iff in GuardFalse.
SearchAbout [beq_nat true].
apply beq_nat_true in GuardFalse.
apply GuardFalse. Qed.
(* ####################################################### *)
(** ** Example: Division *)
(** The following Imp program calculates the integer division and
remainder of two numbers [m] and [n] that are arbitrary constants
in the program.
X ::= m;;
Y ::= 0;;
WHILE n <= X DO
X ::= X - n;;
Y ::= Y + 1
END;
In other words, if we replace [m] and [n] by concrete numbers and
execute the program, it will terminate with the variable [X] set
to the remainder when [m] is divided by [n] and [Y] set to the
quotient. *)
(** In order to give a specification to this program we need to
remember that dividing [m] by [n] produces a reminder [X] and a
quotient [Y] so that [n * Y + X = m /\ X < n].
It turns out that we get lucky with this program and don't have to
think very hard about the loop invariant: the invariant is the
just first conjunct [n * Y + X = m], so we use that to decorate
the program.
(1) {{ True }} ->>
(2) {{ n * 0 + m = m }}
X ::= m;;
(3) {{ n * 0 + X = m }}
Y ::= 0;;
(4) {{ n * Y + X = m }}
WHILE n <= X DO
(5) {{ n * Y + X = m /\ n <= X }} ->>
(6) {{ n * (Y + 1) + (X - n) = m }}
X ::= X - n;;
(7) {{ n * (Y + 1) + X = m }}
Y ::= Y + 1
(8) {{ n * Y + X = m }}
END
(9) {{ n * Y + X = m /\ X < n }}
Assertions (4), (5), (8), and (9) are derived mechanically from
the invariant and the loop's guard. Assertions (8), (7), and (6)
are derived using the assignment rule going backwards from (8) to
(6). Assertions (4), (3), and (2) are again backwards applications
of the assignment rule.
Now that we've decorated the program it only remains to check that
the two uses of the consequence rule are correct -- i.e., that (1)
implies (2) and that (5) implies (6). This is indeed the case, so
we have a valid decorated program.
*)
(* ####################################################### *)
(** * Finding Loop Invariants *)
(** Once the outermost precondition and postcondition are chosen, the
only creative part in verifying programs with Hoare Logic is
finding the right loop invariants. The reason this is difficult
is the same as the reason that doing inductive mathematical proofs
requires creativity: strengthening the loop invariant (or the
induction hypothesis) means that you have a stronger assumption to
work with when trying to establish the postcondition of the loop
body (complete the induction step of the proof), but it also means
that the loop body postcondition itself is harder to prove!
This section is dedicated to teaching you how to approach the
challenge of finding loop invariants using a series of examples
and exercises. *)
(** ** Example: Slow Subtraction *)
(** The following program subtracts the value of [X] from the value of
[Y] by repeatedly decrementing both [X] and [Y]. We want to verify its
correctness with respect to the following specification:
{{ X = m /\ Y = n }}
WHILE X <> 0 DO
Y ::= Y - 1;;
X ::= X - 1
END
{{ Y = n - m }}
To verify this program we need to find an invariant [I] for the
loop. As a first step we can leave [I] as an unknown and build a
_skeleton_ for the proof by applying backward the rules for local
consistency. This process leads to the following skeleton:
(1) {{ X = m /\ Y = n }} ->> (a)
(2) {{ I }}
WHILE X <> 0 DO
(3) {{ I /\ X <> 0 }} ->> (c)
(4) {{ I[X |-> X-1][Y |-> Y-1] }}
Y ::= Y - 1;;
(5) {{ I[X |-> X-1] }}
X ::= X - 1
(6) {{ I }}
END
(7) {{ I /\ ~(X <> 0) }} ->> (b)
(8) {{ Y = n - m }}
By examining this skeleton, we can see that any valid [I] will
have to respect three conditions:
- (a) it must be weak enough to be implied by the loop's
precondition, i.e. (1) must imply (2);
- (b) it must be strong enough to imply the loop's postcondition,
i.e. (7) must imply (8);
- (c) it must be preserved by one iteration of the loop, i.e. (3)
must imply (4). *)
(** These conditions are actually independent of the particular
program and specification we are considering. Indeed, every loop
invariant has to satisfy them. One way to find an invariant that
simultaneously satisfies these three conditions is by using an
iterative process: start with a "candidate" invariant (e.g. a
guess or a heuristic choice) and check the three conditions above;
if any of the checks fails, try to use the information that we get
from the failure to produce another (hopefully better) candidate
invariant, and repeat the process.
For instance, in the reduce-to-zero example above, we saw that,
for a very simple loop, choosing [True] as an invariant did the
job. So let's try it again here! I.e., let's instantiate [I] with
[True] in the skeleton above see what we get...
(1) {{ X = m /\ Y = n }} ->> (a - OK)
(2) {{ True }}
WHILE X <> 0 DO
(3) {{ True /\ X <> 0 }} ->> (c - OK)
(4) {{ True }}
Y ::= Y - 1;;
(5) {{ True }}
X ::= X - 1
(6) {{ True }}
END
(7) {{ True /\ X = 0 }} ->> (b - WRONG!)
(8) {{ Y = n - m }}
While conditions (a) and (c) are trivially satisfied,
condition (b) is wrong, i.e. it is not the case that (7) [True /\
X = 0] implies (8) [Y = n - m]. In fact, the two assertions are
completely unrelated and it is easy to find a counterexample (say,
[Y = X = m = 0] and [n = 1]).
If we want (b) to hold, we need to strengthen the invariant so
that it implies the postcondition (8). One very simple way to do
this is to let the invariant _be_ the postcondition. So let's
return to our skeleton, instantiate [I] with [Y = n - m], and
check conditions (a) to (c) again.
(1) {{ X = m /\ Y = n }} ->> (a - WRONG!)
(2) {{ Y = n - m }}
WHILE X <> 0 DO
(3) {{ Y = n - m /\ X <> 0 }} ->> (c - WRONG!)
(4) {{ Y - 1 = n - m }}
Y ::= Y - 1;;
(5) {{ Y = n - m }}
X ::= X - 1
(6) {{ Y = n - m }}
END
(7) {{ Y = n - m /\ X = 0 }} ->> (b - OK)
(8) {{ Y = n - m }}
This time, condition (b) holds trivially, but (a) and (c) are
broken. Condition (a) requires that (1) [X = m /\ Y = n]
implies (2) [Y = n - m]. If we substitute [Y] by [n] we have to
show that [n = n - m] for arbitrary [m] and [n], which does not
hold (for instance, when [m = n = 1]). Condition (c) requires that
[n - m - 1 = n - m], which fails, for instance, for [n = 1] and [m =
0]. So, although [Y = n - m] holds at the end of the loop, it does
not hold from the start, and it doesn't hold on each iteration;
it is not a correct invariant.
This failure is not very surprising: the variable [Y] changes
during the loop, while [m] and [n] are constant, so the assertion
we chose didn't have much chance of being an invariant!
To do better, we need to generalize (8) to some statement that is
equivalent to (8) when [X] is [0], since this will be the case
when the loop terminates, and that "fills the gap" in some
appropriate way when [X] is nonzero. Looking at how the loop
works, we can observe that [X] and [Y] are decremented together
until [X] reaches [0]. So, if [X = 2] and [Y = 5] initially,
after one iteration of the loop we obtain [X = 1] and [Y = 4];
after two iterations [X = 0] and [Y = 3]; and then the loop stops.
Notice that the difference between [Y] and [X] stays constant
between iterations; initially, [Y = n] and [X = m], so this
difference is always [n - m]. So let's try instantiating [I] in
the skeleton above with [Y - X = n - m].
(1) {{ X = m /\ Y = n }} ->> (a - OK)
(2) {{ Y - X = n - m }}
WHILE X <> 0 DO
(3) {{ Y - X = n - m /\ X <> 0 }} ->> (c - OK)
(4) {{ (Y - 1) - (X - 1) = n - m }}
Y ::= Y - 1;;
(5) {{ Y - (X - 1) = n - m }}
X ::= X - 1
(6) {{ Y - X = n - m }}
END
(7) {{ Y - X = n - m /\ X = 0 }} ->> (b - OK)
(8) {{ Y = n - m }}
Success! Conditions (a), (b) and (c) all hold now. (To
verify (c), we need to check that, under the assumption that [X <>
0], we have [Y - X = (Y - 1) - (X - 1)]; this holds for all
natural numbers [X] and [Y].) *)
(* ####################################################### *)
(** ** Exercise: Slow Assignment *)
(** **** Exercise: 2 stars (slow_assignment) *)
(** A roundabout way of assigning a number currently stored in [X] to
the variable [Y] is to start [Y] at [0], then decrement [X] until
it hits [0], incrementing [Y] at each step. Here is a program that
implements this idea:
{{ X = m }}
Y ::= 0;;
WHILE X <> 0 DO
X ::= X - 1;;
Y ::= Y + 1
END
{{ Y = m }}
Write an informal decorated program showing that this is correct. *)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** ** Exercise: Slow Addition *)
(** **** Exercise: 3 stars, optional (add_slowly_decoration) *)
(** The following program adds the variable X into the variable Z
by repeatedly decrementing X and incrementing Z.
WHILE X <> 0 DO
Z ::= Z + 1;;
X ::= X - 1
END
Following the pattern of the [subtract_slowly] example above, pick
a precondition and postcondition that give an appropriate
specification of [add_slowly]; then (informally) decorate the
program accordingly. *)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** ** Example: Parity *)
(** Here is a cute little program for computing the parity of the
value initially stored in [X] (due to Daniel Cristofani).
{{ X = m }}
WHILE 2 <= X DO
X ::= X - 2
END
{{ X = parity m }}
The mathematical [parity] function used in the specification is
defined in Coq as follows: *)
Fixpoint parity x :=
match x with
| 0 => 0
| 1 => 1
| S (S x') => parity x'
end.
(** The postcondition does not hold at the beginning of the loop,
since [m = parity m] does not hold for an arbitrary [m], so we
cannot use that as an invariant. To find an invariant that works,
let's think a bit about what this loop does. On each iteration it
decrements [X] by [2], which preserves the parity of [X]. So the
parity of [X] does not change, i.e. it is invariant. The initial
value of [X] is [m], so the parity of [X] is always equal to the
parity of [m]. Using [parity X = parity m] as an invariant we
obtain the following decorated program:
{{ X = m }} ->> (a - OK)
{{ parity X = parity m }}
WHILE 2 <= X DO
{{ parity X = parity m /\ 2 <= X }} ->> (c - OK)
{{ parity (X-2) = parity m }}
X ::= X - 2
{{ parity X = parity m }}
END
{{ parity X = parity m /\ X < 2 }} ->> (b - OK)
{{ X = parity m }}
With this invariant, conditions (a), (b), and (c) are all
satisfied. For verifying (b), we observe that, when [X < 2], we
have [parity X = X] (we can easily see this in the definition of
[parity]). For verifying (c), we observe that, when [2 <= X], we
have [parity X = parity (X-2)]. *)
(** **** Exercise: 3 stars, optional (parity_formal) *)
(** Translate this proof to Coq. Refer to the reduce-to-zero example
for ideas. You may find the following two lemmas useful: *)
Lemma parity_ge_2 : forall x,
2 <= x ->
parity (x - 2) = parity x.
Proof.
induction x; intro. reflexivity.
destruct x. inversion H. inversion H1.
simpl. rewrite <- minus_n_O. reflexivity.
Qed.
Lemma parity_lt_2 : forall x,
~ 2 <= x ->
parity (x) = x.
Proof.
intros. induction x. reflexivity. destruct x. reflexivity.
apply ex_falso_quodlibet. apply H. omega.
Qed.
Theorem parity_correct : forall m,
{{ fun st => st X = m }}
WHILE BLe (ANum 2) (AId X) DO
X ::= AMinus (AId X) (ANum 2)
END
{{ fun st => st X = parity m }}.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ####################################################### *)
(** ** Example: Finding Square Roots *)
(** The following program computes the square root of [X]
by naive iteration:
{{ X=m }}
Z ::= 0;;
WHILE (Z+1)*(Z+1) <= X DO
Z ::= Z+1
END
{{ Z*Z<=m /\ m<(Z+1)*(Z+1) }}
*)
(** As above, we can try to use the postcondition as a candidate
invariant, obtaining the following decorated program:
(1) {{ X=m }} ->> (a - second conjunct of (2) WRONG!)
(2) {{ 0*0 <= m /\ m<1*1 }}
Z ::= 0;;
(3) {{ Z*Z <= m /\ m<(Z+1)*(Z+1) }}
WHILE (Z+1)*(Z+1) <= X DO
(4) {{ Z*Z<=m /\ (Z+1)*(Z+1)<=X }} ->> (c - WRONG!)
(5) {{ (Z+1)*(Z+1)<=m /\ m<(Z+2)*(Z+2) }}
Z ::= Z+1
(6) {{ Z*Z<=m /\ m<(Z+1)*(Z+1) }}
END
(7) {{ Z*Z<=m /\ m<(Z+1)*(Z+1) /\ X<(Z+1)*(Z+1) }} ->> (b - OK)
(8) {{ Z*Z<=m /\ m<(Z+1)*(Z+1) }}
This didn't work very well: both conditions (a) and (c) failed.
Looking at condition (c), we see that the second conjunct of (4)
is almost the same as the first conjunct of (5), except that (4)
mentions [X] while (5) mentions [m]. But note that [X] is never
assigned in this program, so we should have [X=m], but we didn't
propagate this information from (1) into the loop invariant.
Also, looking at the second conjunct of (8), it seems quite
hopeless as an invariant -- and we don't even need it, since we
can obtain it from the negation of the guard (third conjunct
in (7)), again under the assumption that [X=m].
So we now try [X=m /\ Z*Z <= m] as the loop invariant:
{{ X=m }} ->> (a - OK)
{{ X=m /\ 0*0 <= m }}
Z ::= 0;
{{ X=m /\ Z*Z <= m }}
WHILE (Z+1)*(Z+1) <= X DO
{{ X=m /\ Z*Z<=m /\ (Z+1)*(Z+1)<=X }} ->> (c - OK)
{{ X=m /\ (Z+1)*(Z+1)<=m }}
Z ::= Z+1
{{ X=m /\ Z*Z<=m }}
END
{{ X=m /\ Z*Z<=m /\ X<(Z+1)*(Z+1) }} ->> (b - OK)
{{ Z*Z<=m /\ m<(Z+1)*(Z+1) }}
This works, since conditions (a), (b), and (c) are now all
trivially satisfied.
Very often, if a variable is used in a loop in a read-only
fashion (i.e., it is referred to by the program or by the
specification and it is not changed by the loop) it is necessary
to add the fact that it doesn't change to the loop invariant. *)
(* ####################################################### *)
(** ** Example: Squaring *)
(** Here is a program that squares [X] by repeated addition:
{{ X = m }}
Y ::= 0;;
Z ::= 0;;
WHILE Y <> X DO
Z ::= Z + X;;
Y ::= Y + 1
END
{{ Z = m*m }}
*)
(** The first thing to note is that the loop reads [X] but doesn't
change its value. As we saw in the previous example, in such cases
it is a good idea to add [X = m] to the invariant. The other thing
we often use in the invariant is the postcondition, so let's add
that too, leading to the invariant candidate [Z = m * m /\ X = m].
{{ X = m }} ->> (a - WRONG)
{{ 0 = m*m /\ X = m }}
Y ::= 0;;
{{ 0 = m*m /\ X = m }}
Z ::= 0;;
{{ Z = m*m /\ X = m }}
WHILE Y <> X DO
{{ Z = Y*m /\ X = m /\ Y <> X }} ->> (c - WRONG)
{{ Z+X = m*m /\ X = m }}
Z ::= Z + X;;
{{ Z = m*m /\ X = m }}
Y ::= Y + 1
{{ Z = m*m /\ X = m }}
END
{{ Z = m*m /\ X = m /\ Y = X }} ->> (b - OK)
{{ Z = m*m }}
Conditions (a) and (c) fail because of the [Z = m*m] part. While
[Z] starts at [0] and works itself up to [m*m], we can't expect
[Z] to be [m*m] from the start. If we look at how [Z] progesses
in the loop, after the 1st iteration [Z = m], after the 2nd
iteration [Z = 2*m], and at the end [Z = m*m]. Since the variable
[Y] tracks how many times we go through the loop, we derive the
new invariant candidate [Z = Y*m /\ X = m].
{{ X = m }} ->> (a - OK)
{{ 0 = 0*m /\ X = m }}
Y ::= 0;;
{{ 0 = Y*m /\ X = m }}
Z ::= 0;;
{{ Z = Y*m /\ X = m }}
WHILE Y <> X DO
{{ Z = Y*m /\ X = m /\ Y <> X }} ->> (c - OK)
{{ Z+X = (Y+1)*m /\ X = m }}
Z ::= Z + X;
{{ Z = (Y+1)*m /\ X = m }}
Y ::= Y + 1
{{ Z = Y*m /\ X = m }}
END
{{ Z = Y*m /\ X = m /\ Y = X }} ->> (b - OK)
{{ Z = m*m }}
This new invariant makes the proof go through: all three
conditions are easy to check.
It is worth comparing the postcondition [Z = m*m] and the [Z =
Y*m] conjunct of the invariant. It is often the case that one has
to replace auxiliary variabes (parameters) with variables -- or
with expressions involving both variables and parameters (like
[m - Y]) -- when going from postconditions to invariants. *)
(* ####################################################### *)
(** ** Exercise: Factorial *)
(** **** Exercise: 3 stars (factorial) *)
(** Recall that [n!] denotes the factorial of [n] (i.e. [n! =
1*2*...*n]). Here is an Imp program that calculates the factorial
of the number initially stored in the variable [X] and puts it in
the variable [Y]:
{{ X = m }}
Y ::= 1 ;;
WHILE X <> 0
DO
Y ::= Y * X ;;
X ::= X - 1
END
{{ Y = m! }}
Fill in the blanks in following decorated program:
{{ X = m }} ->>
{{ }}
Y ::= 1;;
{{ }}
WHILE X <> 0
DO {{ }} ->>
{{ }}
Y ::= Y * X;;
{{ }}
X ::= X - 1
{{ }}
END
{{ }} ->>
{{ Y = m! }}
*)
(** [] *)
(* ####################################################### *)
(** ** Exercise: Min *)
(** **** Exercise: 3 stars (Min_Hoare) *)
(** Fill in valid decorations for the following program.
For the => steps in your annotations, you may rely (silently) on the
following facts about min
Lemma lemma1 : forall x y,
(x=0 \/ y=0) -> min x y = 0.
Lemma lemma2 : forall x y,
min (x-1) (y-1) = (min x y) - 1.
plus, as usual, standard high-school algebra.
{{ True }} ->>
{{ }}
X ::= a;;
{{ }}
Y ::= b;;
{{ }}
Z ::= 0;;
{{ }}
WHILE (X <> 0 /\ Y <> 0) DO
{{ }} ->>
{{ }}
X := X - 1;;
{{ }}
Y := Y - 1;;
{{ }}
Z := Z + 1
{{ }}
END
{{ }} ->>
{{ Z = min a b }}
*)
(** [] *)
(** **** Exercise: 3 stars (two_loops) *)
(** Here is a very inefficient way of adding 3 numbers:
X ::= 0;;
Y ::= 0;;
Z ::= c;;
WHILE X <> a DO
X ::= X + 1;;
Z ::= Z + 1
END;;
WHILE Y <> b DO
Y ::= Y + 1;;
Z ::= Z + 1
END
Show that it does what it should by filling in the blanks in the
following decorated program.
{{ True }} ->>
{{ }}
X ::= 0;;
{{ }}
Y ::= 0;;
{{ }}
Z ::= c;;
{{ }}
WHILE X <> a DO
{{ }} ->>
{{ }}
X ::= X + 1;;
{{ }}
Z ::= Z + 1
{{ }}
END;;
{{ }} ->>
{{ }}
WHILE Y <> b DO
{{ }} ->>
{{ }}
Y ::= Y + 1;;
{{ }}
Z ::= Z + 1
{{ }}
END
{{ }} ->>
{{ Z = a + b + c }}
*)
(** [] *)
(* ####################################################### *)
(** ** Exercise: Power Series *)
(** **** Exercise: 4 stars, optional (dpow2_down) *)
(** Here is a program that computes the series:
[1 + 2 + 2^2 + ... + 2^m = 2^(m+1) - 1]
X ::= 0;;
Y ::= 1;;
Z ::= 1;;
WHILE X <> m DO
Z ::= 2 * Z;;
Y ::= Y + Z;;
X ::= X + 1
END
Write a decorated program for this. *)
(* FILL IN HERE *)
(* ####################################################### *)
(** * Weakest Preconditions (Advanced) *)
(** Some Hoare triples are more interesting than others.
For example,
{{ False }} X ::= Y + 1 {{ X <= 5 }}
is _not_ very interesting: although it is perfectly valid, it
tells us nothing useful. Since the precondition isn't satisfied
by any state, it doesn't describe any situations where we can use
the command [X ::= Y + 1] to achieve the postcondition [X <= 5].
By contrast,
{{ Y <= 4 /\ Z = 0 }} X ::= Y + 1 {{ X <= 5 }}
is useful: it tells us that, if we can somehow create a situation
in which we know that [Y <= 4 /\ Z = 0], then running this command
will produce a state satisfying the postcondition. However, this
triple is still not as useful as it could be, because the [Z = 0]
clause in the precondition actually has nothing to do with the
postcondition [X <= 5]. The _most_ useful triple (for a given
command and postcondition) is this one:
{{ Y <= 4 }} X ::= Y + 1 {{ X <= 5 }}
In other words, [Y <= 4] is the _weakest_ valid precondition of
the command [X ::= Y + 1] for the postcondition [X <= 5]. *)
(** In general, we say that "[P] is the weakest precondition of
command [c] for postcondition [Q]" if [{{P}} c {{Q}}] and if,
whenever [P'] is an assertion such that [{{P'}} c {{Q}}], we have
[P' st] implies [P st] for all states [st]. *)
Definition is_wp P c Q :=
{{P}} c {{Q}} /\
forall P', {{P'}} c {{Q}} -> (P' ->> P).
(** That is, [P] is the weakest precondition of [c] for [Q]
if (a) [P] _is_ a precondition for [Q] and [c], and (b) [P] is the
_weakest_ (easiest to satisfy) assertion that guarantees [Q] after
executing [c]. *)
(** **** Exercise: 1 star, optional (wp) *)
(** What are the weakest preconditions of the following commands
for the following postconditions?
1) {{ ? }} SKIP {{ X = 5 }}
2) {{ ? }} X ::= Y + Z {{ X = 5 }}
3) {{ ? }} X ::= Y {{ X = Y }}
4) {{ ? }}
IFB X == 0 THEN Y ::= Z + 1 ELSE Y ::= W + 2 FI
{{ Y = 5 }}
5) {{ ? }}
X ::= 5
{{ X = 0 }}
6) {{ ? }}
WHILE True DO X ::= 0 END
{{ X = 0 }}
*)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, advanced, optional (is_wp_formal) *)
(** Prove formally using the definition of [hoare_triple] that [Y <= 4]
is indeed the weakest precondition of [X ::= Y + 1] with respect to
postcondition [X <= 5]. *)
Theorem is_wp_example :
is_wp (fun st => st Y <= 4)
(X ::= APlus (AId Y) (ANum 1)) (fun st => st X <= 5).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, advanced (hoare_asgn_weakest) *)
(** Show that the precondition in the rule [hoare_asgn] is in fact the
weakest precondition. *)
Theorem hoare_asgn_weakest : forall Q X a,
is_wp (Q [X |-> a]) (X ::= a) Q.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, advanced, optional (hoare_havoc_weakest) *)
(** Show that your [havoc_pre] rule from the [himp_hoare] exercise
in the [Hoare] chapter returns the weakest precondition. *)
Module Himp2.
Import Himp.
Lemma hoare_havoc_weakest : forall (P Q : Assertion) (X : id),
{{ P }} HAVOC X {{ Q }} ->
P ->> havoc_pre X Q.
Proof.
(* FILL IN HERE *) Admitted.
End Himp2.
(** [] *)
(* ####################################################### *)
(** * Formal Decorated Programs (Advanced) *)
(** The informal conventions for decorated programs amount to a way of
displaying Hoare triples in which commands are annotated with
enough embedded assertions that checking the validity of the
triple is reduced to simple logical and algebraic calculations
showing that some assertions imply others. In this section, we
show that this informal presentation style can actually be made
completely formal and indeed that checking the validity of
decorated programs can mostly be automated. *)
(** ** Syntax *)
(** The first thing we need to do is to formalize a variant of the
syntax of commands with embedded assertions. We call the new
commands _decorated commands_, or [dcom]s. *)
Inductive dcom : Type :=
| DCSkip : Assertion -> dcom
| DCSeq : dcom -> dcom -> dcom
| DCAsgn : id -> aexp -> Assertion -> dcom
| DCIf : bexp -> Assertion -> dcom -> Assertion -> dcom
-> Assertion-> dcom
| DCWhile : bexp -> Assertion -> dcom -> Assertion -> dcom
| DCPre : Assertion -> dcom -> dcom
| DCPost : dcom -> Assertion -> dcom.
Tactic Notation "dcom_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "Skip" | Case_aux c "Seq" | Case_aux c "Asgn"
| Case_aux c "If" | Case_aux c "While"
| Case_aux c "Pre" | Case_aux c "Post" ].
Notation "'SKIP' {{ P }}"
:= (DCSkip P)
(at level 10) : dcom_scope.
Notation "l '::=' a {{ P }}"
:= (DCAsgn l a P)
(at level 60, a at next level) : dcom_scope.
Notation "'WHILE' b 'DO' {{ Pbody }} d 'END' {{ Ppost }}"
:= (DCWhile b Pbody d Ppost)
(at level 80, right associativity) : dcom_scope.
Notation "'IFB' b 'THEN' {{ P }} d 'ELSE' {{ P' }} d' 'FI' {{ Q }}"
:= (DCIf b P d P' d' Q)
(at level 80, right associativity) : dcom_scope.
Notation "'->>' {{ P }} d"
:= (DCPre P d)
(at level 90, right associativity) : dcom_scope.
Notation "{{ P }} d"
:= (DCPre P d)
(at level 90) : dcom_scope.
Notation "d '->>' {{ P }}"
:= (DCPost d P)
(at level 80, right associativity) : dcom_scope.
Notation " d ;; d' "
:= (DCSeq d d')
(at level 80, right associativity) : dcom_scope.
Delimit Scope dcom_scope with dcom.
(** To avoid clashing with the existing [Notation] definitions
for ordinary [com]mands, we introduce these notations in a special
scope called [dcom_scope], and we wrap examples with the
declaration [% dcom] to signal that we want the notations to be
interpreted in this scope.
Careful readers will note that we've defined two notations for the
[DCPre] constructor, one with and one without a [->>]. The
"without" version is intended to be used to supply the initial
precondition at the very top of the program. *)
Example dec_while : dcom := (
{{ fun st => True }}
WHILE (BNot (BEq (AId X) (ANum 0)))
DO
{{ fun st => True /\ st X <> 0}}
X ::= (AMinus (AId X) (ANum 1))
{{ fun _ => True }}
END
{{ fun st => True /\ st X = 0}} ->>
{{ fun st => st X = 0 }}
) % dcom.
(** It is easy to go from a [dcom] to a [com] by erasing all
annotations. *)
Fixpoint extract (d:dcom) : com :=
match d with
| DCSkip _ => SKIP
| DCSeq d1 d2 => (extract d1 ;; extract d2)
| DCAsgn X a _ => X ::= a
| DCIf b _ d1 _ d2 _ => IFB b THEN extract d1 ELSE extract d2 FI
| DCWhile b _ d _ => WHILE b DO extract d END
| DCPre _ d => extract d
| DCPost d _ => extract d
end.
(** The choice of exactly where to put assertions in the definition of
[dcom] is a bit subtle. The simplest thing to do would be to
annotate every [dcom] with a precondition and postcondition. But
this would result in very verbose programs with a lot of repeated
annotations: for example, a program like [SKIP;SKIP] would have to
be annotated as
{{P}} ({{P}} SKIP {{P}}) ;; ({{P}} SKIP {{P}}) {{P}},
with pre- and post-conditions on each [SKIP], plus identical pre-
and post-conditions on the semicolon!
Instead, the rule we've followed is this:
- The _post_-condition expected by each [dcom] [d] is embedded in [d]
- The _pre_-condition is supplied by the context. *)
(** In other words, the invariant of the representation is that a
[dcom] [d] together with a precondition [P] determines a Hoare
triple [{{P}} (extract d) {{post d}}], where [post] is defined as
follows: *)
Fixpoint post (d:dcom) : Assertion :=
match d with
| DCSkip P => P
| DCSeq d1 d2 => post d2
| DCAsgn X a Q => Q
| DCIf _ _ d1 _ d2 Q => Q
| DCWhile b Pbody c Ppost => Ppost
| DCPre _ d => post d
| DCPost c Q => Q
end.
(** Similarly, we can extract the "initial precondition" from a
decorated program. *)
Fixpoint pre (d:dcom) : Assertion :=
match d with
| DCSkip P => fun st => True
| DCSeq c1 c2 => pre c1
| DCAsgn X a Q => fun st => True
| DCIf _ _ t _ e _ => fun st => True
| DCWhile b Pbody c Ppost => fun st => True
| DCPre P c => P
| DCPost c Q => pre c
end.
(** This function is not doing anything sophisticated like calculating
a weakest precondition; it just recursively searches for an
explicit annotation at the very beginning of the program,
returning default answers for programs that lack an explicit
precondition (like a bare assignment or [SKIP]). *)
(** Using [pre] and [post], and assuming that we adopt the convention
of always supplying an explicit precondition annotation at the
very beginning of our decorated programs, we can express what it
means for a decorated program to be correct as follows: *)
Definition dec_correct (d:dcom) :=
{{pre d}} (extract d) {{post d}}.
(** To check whether this Hoare triple is _valid_, we need a way to
extract the "proof obligations" from a decorated program. These
obligations are often called _verification conditions_, because
they are the facts that must be verified to see that the
decorations are logically consistent and thus add up to a complete
proof of correctness. *)
(** ** Extracting Verification Conditions *)
(** The function [verification_conditions] takes a [dcom] [d] together
with a precondition [P] and returns a _proposition_ that, if it
can be proved, implies that the triple [{{P}} (extract d) {{post d}}]
is valid. *)
(** It does this by walking over [d] and generating a big
conjunction including all the "local checks" that we listed when
we described the informal rules for decorated programs. (Strictly
speaking, we need to massage the informal rules a little bit to
add some uses of the rule of consequence, but the correspondence
should be clear.) *)
Fixpoint verification_conditions (P : Assertion) (d:dcom) : Prop :=
match d with
| DCSkip Q =>
(P ->> Q)
| DCSeq d1 d2 =>
verification_conditions P d1
/\ verification_conditions (post d1) d2
| DCAsgn X a Q =>
(P ->> Q [X |-> a])
| DCIf b P1 d1 P2 d2 Q =>
((fun st => P st /\ bassn b st) ->> P1)
/\ ((fun st => P st /\ ~ (bassn b st)) ->> P2)
/\ (Q <<->> post d1) /\ (Q <<->> post d2)
/\ verification_conditions P1 d1
/\ verification_conditions P2 d2
| DCWhile b Pbody d Ppost =>
(* post d is the loop invariant and the initial precondition *)
(P ->> post d)
/\ (Pbody <<->> (fun st => post d st /\ bassn b st))
/\ (Ppost <<->> (fun st => post d st /\ ~(bassn b st)))
/\ verification_conditions Pbody d
| DCPre P' d =>
(P ->> P') /\ verification_conditions P' d
| DCPost d Q =>
verification_conditions P d /\ (post d ->> Q)
end.
(** And now, the key theorem, which states that
[verification_conditions] does its job correctly. Not
surprisingly, we need to use each of the Hoare Logic rules at some
point in the proof. *)
(** We have used _in_ variants of several tactics before to
apply them to values in the context rather than the goal. An
extension of this idea is the syntax [tactic in *], which applies
[tactic] in the goal and every hypothesis in the context. We most
commonly use this facility in conjunction with the [simpl] tactic,
as below. *)
Theorem verification_correct : forall d P,
verification_conditions P d -> {{P}} (extract d) {{post d}}.
Proof.
dcom_cases (induction d) Case; intros P H; simpl in *.
Case "Skip".
eapply hoare_consequence_pre.
apply hoare_skip.
assumption.
Case "Seq".
inversion H as [H1 H2]. clear H.
eapply hoare_seq.
apply IHd2. apply H2.
apply IHd1. apply H1.
Case "Asgn".
eapply hoare_consequence_pre.
apply hoare_asgn.
assumption.
Case "If".
inversion H as [HPre1 [HPre2 [[Hd11 Hd12]
[[Hd21 Hd22] [HThen HElse]]]]].
clear H.
apply IHd1 in HThen. clear IHd1.
apply IHd2 in HElse. clear IHd2.
apply hoare_if.
eapply hoare_consequence_pre; eauto.
eapply hoare_consequence_post; eauto.
eapply hoare_consequence_pre; eauto.
eapply hoare_consequence_post; eauto.
Case "While".
inversion H as [Hpre [[Hbody1 Hbody2] [[Hpost1 Hpost2] Hd]]];
subst; clear H.
eapply hoare_consequence_pre; eauto.
eapply hoare_consequence_post; eauto.
apply hoare_while.
eapply hoare_consequence_pre; eauto.
Case "Pre".
inversion H as [HP Hd]; clear H.
eapply hoare_consequence_pre. apply IHd. apply Hd. assumption.
Case "Post".
inversion H as [Hd HQ]; clear H.
eapply hoare_consequence_post. apply IHd. apply Hd. assumption.
Qed.
(** ** Examples *)
(** The propositions generated by [verification_conditions] are fairly
big, and they contain many conjuncts that are essentially trivial. *)
Eval simpl in (verification_conditions (fun st => True) dec_while).
(**
==>
(((fun _ : state => True) ->> (fun _ : state => True)) /\
((fun _ : state => True) ->> (fun _ : state => True)) /\
(fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st) =
(fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st) /\
(fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st) =
(fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st) /\
(fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st) ->>
(fun _ : state => True) [X |-> AMinus (AId X) (ANum 1)]) /\
(fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st) ->>
(fun st : state => st X = 0)
*)
(** In principle, we could certainly work with them using just the
tactics we have so far, but we can make things much smoother with
a bit of automation. We first define a custom [verify] tactic
that applies splitting repeatedly to turn all the conjunctions
into separate subgoals and then uses [omega] and [eauto] (a handy
general-purpose automation tactic that we'll discuss in detail
later) to deal with as many of them as possible. *)
Lemma ble_nat_true_iff : forall n m : nat,
ble_nat n m = true <-> n <= m.
Proof.
intros n m. split. apply ble_nat_true.
generalize dependent m. induction n; intros m H. reflexivity.
simpl. destruct m. inversion H.
apply le_S_n in H. apply IHn. assumption.
Qed.
Lemma ble_nat_false_iff : forall n m : nat,
ble_nat n m = false <-> ~(n <= m).
Proof.
intros n m. split. apply ble_nat_false.
generalize dependent m. induction n; intros m H.
apply ex_falso_quodlibet. apply H. apply le_0_n.
simpl. destruct m. reflexivity.
apply IHn. intro Hc. apply H. apply le_n_S. assumption.
Qed.
Tactic Notation "verify" :=
apply verification_correct;
repeat split;
simpl; unfold assert_implies;
unfold bassn in *; unfold beval in *; unfold aeval in *;
unfold assn_sub; intros;
repeat rewrite update_eq;
repeat (rewrite update_neq; [| (intro X; inversion X)]);
simpl in *;
repeat match goal with [H : _ /\ _ |- _] => destruct H end;
repeat rewrite not_true_iff_false in *;
repeat rewrite not_false_iff_true in *;
repeat rewrite negb_true_iff in *;
repeat rewrite negb_false_iff in *;
repeat rewrite beq_nat_true_iff in *;
repeat rewrite beq_nat_false_iff in *;
repeat rewrite ble_nat_true_iff in *;
repeat rewrite ble_nat_false_iff in *;
try subst;
repeat
match goal with
[st : state |- _] =>
match goal with
[H : st _ = _ |- _] => rewrite -> H in *; clear H
| [H : _ = st _ |- _] => rewrite <- H in *; clear H
end
end;
try eauto; try omega.
(** What's left after [verify] does its thing is "just the interesting
parts" of checking that the decorations are correct. For very
simple examples [verify] immediately solves the goal (provided
that the annotations are correct). *)
Theorem dec_while_correct :
dec_correct dec_while.
Proof. verify. Qed.
(** Another example (formalizing a decorated program we've seen
before): *)
Example subtract_slowly_dec (m:nat) (p:nat) : dcom := (
{{ fun st => st X = m /\ st Z = p }} ->>
{{ fun st => st Z - st X = p - m }}
WHILE BNot (BEq (AId X) (ANum 0))
DO {{ fun st => st Z - st X = p - m /\ st X <> 0 }} ->>
{{ fun st => (st Z - 1) - (st X - 1) = p - m }}
Z ::= AMinus (AId Z) (ANum 1)
{{ fun st => st Z - (st X - 1) = p - m }} ;;
X ::= AMinus (AId X) (ANum 1)
{{ fun st => st Z - st X = p - m }}
END
{{ fun st => st Z - st X = p - m /\ st X = 0 }} ->>
{{ fun st => st Z = p - m }}
) % dcom.
Theorem subtract_slowly_dec_correct : forall m p,
dec_correct (subtract_slowly_dec m p).
Proof. intros m p. verify. (* this grinds for a bit! *) Qed.
(** **** Exercise: 3 stars, advanced (slow_assignment_dec) *)
(** In the [slow_assignment] exercise above, we saw a roundabout way
of assigning a number currently stored in [X] to the variable [Y]:
start [Y] at [0], then decrement [X] until it hits [0],
incrementing [Y] at each step.
Write a _formal_ version of this decorated program and prove it
correct. *)
Example slow_assignment_dec (m:nat) : dcom :=
(* FILL IN HERE *) admit.
Theorem slow_assignment_dec_correct : forall m,
dec_correct (slow_assignment_dec m).
Proof. (* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, advanced (factorial_dec) *)
(** Remember the factorial function we worked with before: *)
Fixpoint real_fact (n:nat) : nat :=
match n with
| O => 1
| S n' => n * (real_fact n')
end.
(** Following the pattern of [subtract_slowly_dec], write a decorated
program [factorial_dec] that implements the factorial function and
prove it correct as [factorial_dec_correct]. *)
(* FILL IN HERE *)
(** [] *)
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
|
`timescale 1ns/10ps
module master_pll_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked,
// interface 'reconfig_to_pll'
input wire [63:0] reconfig_to_pll,
// interface 'reconfig_from_pll'
output wire [63:0] reconfig_from_pll
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.pll_fractional_cout(32),
.pll_dsm_out_sel("1st_order"),
.operation_mode("direct"),
.number_of_clocks(1),
.output_clock_frequency0("26.600985 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("Cyclone V"),
.pll_subtype("Reconfigurable"),
.m_cnt_hi_div(54),
.m_cnt_lo_div(54),
.n_cnt_hi_div(4),
.n_cnt_lo_div(3),
.m_cnt_bypass_en("false"),
.n_cnt_bypass_en("false"),
.m_cnt_odd_div_duty_en("false"),
.n_cnt_odd_div_duty_en("true"),
.c_cnt_hi_div0(15),
.c_cnt_lo_div0(14),
.c_cnt_prst0(1),
.c_cnt_ph_mux_prst0(0),
.c_cnt_in_src0("ph_mux_clk"),
.c_cnt_bypass_en0("false"),
.c_cnt_odd_div_duty_en0("true"),
.c_cnt_hi_div1(1),
.c_cnt_lo_div1(1),
.c_cnt_prst1(1),
.c_cnt_ph_mux_prst1(0),
.c_cnt_in_src1("ph_mux_clk"),
.c_cnt_bypass_en1("true"),
.c_cnt_odd_div_duty_en1("false"),
.c_cnt_hi_div2(1),
.c_cnt_lo_div2(1),
.c_cnt_prst2(1),
.c_cnt_ph_mux_prst2(0),
.c_cnt_in_src2("ph_mux_clk"),
.c_cnt_bypass_en2("true"),
.c_cnt_odd_div_duty_en2("false"),
.c_cnt_hi_div3(1),
.c_cnt_lo_div3(1),
.c_cnt_prst3(1),
.c_cnt_ph_mux_prst3(0),
.c_cnt_in_src3("ph_mux_clk"),
.c_cnt_bypass_en3("true"),
.c_cnt_odd_div_duty_en3("false"),
.c_cnt_hi_div4(1),
.c_cnt_lo_div4(1),
.c_cnt_prst4(1),
.c_cnt_ph_mux_prst4(0),
.c_cnt_in_src4("ph_mux_clk"),
.c_cnt_bypass_en4("true"),
.c_cnt_odd_div_duty_en4("false"),
.c_cnt_hi_div5(1),
.c_cnt_lo_div5(1),
.c_cnt_prst5(1),
.c_cnt_ph_mux_prst5(0),
.c_cnt_in_src5("ph_mux_clk"),
.c_cnt_bypass_en5("true"),
.c_cnt_odd_div_duty_en5("false"),
.c_cnt_hi_div6(1),
.c_cnt_lo_div6(1),
.c_cnt_prst6(1),
.c_cnt_ph_mux_prst6(0),
.c_cnt_in_src6("ph_mux_clk"),
.c_cnt_bypass_en6("true"),
.c_cnt_odd_div_duty_en6("false"),
.c_cnt_hi_div7(1),
.c_cnt_lo_div7(1),
.c_cnt_prst7(1),
.c_cnt_ph_mux_prst7(0),
.c_cnt_in_src7("ph_mux_clk"),
.c_cnt_bypass_en7("true"),
.c_cnt_odd_div_duty_en7("false"),
.c_cnt_hi_div8(1),
.c_cnt_lo_div8(1),
.c_cnt_prst8(1),
.c_cnt_ph_mux_prst8(0),
.c_cnt_in_src8("ph_mux_clk"),
.c_cnt_bypass_en8("true"),
.c_cnt_odd_div_duty_en8("false"),
.c_cnt_hi_div9(1),
.c_cnt_lo_div9(1),
.c_cnt_prst9(1),
.c_cnt_ph_mux_prst9(0),
.c_cnt_in_src9("ph_mux_clk"),
.c_cnt_bypass_en9("true"),
.c_cnt_odd_div_duty_en9("false"),
.c_cnt_hi_div10(1),
.c_cnt_lo_div10(1),
.c_cnt_prst10(1),
.c_cnt_ph_mux_prst10(0),
.c_cnt_in_src10("ph_mux_clk"),
.c_cnt_bypass_en10("true"),
.c_cnt_odd_div_duty_en10("false"),
.c_cnt_hi_div11(1),
.c_cnt_lo_div11(1),
.c_cnt_prst11(1),
.c_cnt_ph_mux_prst11(0),
.c_cnt_in_src11("ph_mux_clk"),
.c_cnt_bypass_en11("true"),
.c_cnt_odd_div_duty_en11("false"),
.c_cnt_hi_div12(1),
.c_cnt_lo_div12(1),
.c_cnt_prst12(1),
.c_cnt_ph_mux_prst12(0),
.c_cnt_in_src12("ph_mux_clk"),
.c_cnt_bypass_en12("true"),
.c_cnt_odd_div_duty_en12("false"),
.c_cnt_hi_div13(1),
.c_cnt_lo_div13(1),
.c_cnt_prst13(1),
.c_cnt_ph_mux_prst13(0),
.c_cnt_in_src13("ph_mux_clk"),
.c_cnt_bypass_en13("true"),
.c_cnt_odd_div_duty_en13("false"),
.c_cnt_hi_div14(1),
.c_cnt_lo_div14(1),
.c_cnt_prst14(1),
.c_cnt_ph_mux_prst14(0),
.c_cnt_in_src14("ph_mux_clk"),
.c_cnt_bypass_en14("true"),
.c_cnt_odd_div_duty_en14("false"),
.c_cnt_hi_div15(1),
.c_cnt_lo_div15(1),
.c_cnt_prst15(1),
.c_cnt_ph_mux_prst15(0),
.c_cnt_in_src15("ph_mux_clk"),
.c_cnt_bypass_en15("true"),
.c_cnt_odd_div_duty_en15("false"),
.c_cnt_hi_div16(1),
.c_cnt_lo_div16(1),
.c_cnt_prst16(1),
.c_cnt_ph_mux_prst16(0),
.c_cnt_in_src16("ph_mux_clk"),
.c_cnt_bypass_en16("true"),
.c_cnt_odd_div_duty_en16("false"),
.c_cnt_hi_div17(1),
.c_cnt_lo_div17(1),
.c_cnt_prst17(1),
.c_cnt_ph_mux_prst17(0),
.c_cnt_in_src17("ph_mux_clk"),
.c_cnt_bypass_en17("true"),
.c_cnt_odd_div_duty_en17("false"),
.pll_vco_div(1),
.pll_cp_current(20),
.pll_bwctrl(10000),
.pll_output_clk_frequency("771.428571 MHz"),
.pll_fractional_division("1"),
.mimic_fbclk_type("none"),
.pll_fbclk_mux_1("glb"),
.pll_fbclk_mux_2("m_cnt"),
.pll_m_cnt_in_src("ph_mux_clk"),
.pll_slf_rst("false")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_0}),
.locked (locked),
.reconfig_to_pll (reconfig_to_pll),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk),
.reconfig_from_pll (reconfig_from_pll)
);
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 05/11/2009
Version 2.0
This logic recieves registers the byte address of the master when 'start'
is asserted. This block then barrelshifts the write data based on the byte
address to make sure that the input data (from the FIFO) is reformatted to
line up with memory properly.
The only throttling mechanism in this block is the FIFO not empty signal as
well as waitreqeust from the fabric.
Revision History:
1.0 Initial version
2.0 Removed 'bytes_to_next_boundary' and using the address to determine how
much out of alignment the master begins.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ST_to_MM_Adapter (
clk,
reset,
enable,
address,
start,
waitrequest,
stall,
write_data,
fifo_data,
fifo_empty,
fifo_readack
);
parameter DATA_WIDTH = 32;
parameter BYTEENABLE_WIDTH_LOG2 = 2;
parameter ADDRESS_WIDTH = 32;
parameter UNALIGNED_ACCESS_ENABLE = 0; // when set to 0 this block will be a pass through (save on resources when unaligned accesses are not needed)
localparam BYTES_TO_NEXT_BOUNDARY_WIDTH = BYTEENABLE_WIDTH_LOG2 + 1; // 2, 3, 4, 5, 6 for byte enable widths of 2, 4, 8, 16, 32
input clk;
input reset;
input enable; // must make sure that the adapter doesn't accept data when a transfer it doesn't know what "bytes_to_transfer" is yet
input [ADDRESS_WIDTH-1:0] address;
input start; // one cycle strobe at the start of a transfer used to determine bytes_to_transfer
input waitrequest;
input stall;
output wire [DATA_WIDTH-1:0] write_data;
input [DATA_WIDTH-1:0] fifo_data;
input fifo_empty;
output wire fifo_readack;
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-1:0] bytes_to_next_boundary;
wire [DATA_WIDTH-1:0] barrelshifter_A;
wire [DATA_WIDTH-1:0] barrelshifter_B;
reg [DATA_WIDTH-1:0] barrelshifter_B_d1;
wire [DATA_WIDTH-1:0] combined_word; // bitwise OR between barrelshifter_A and barrelshifter_B (each has zero padding so that bytelanes don't overlap)
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one; // simplifies barrelshifter select logic
reg [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one_d1;
wire [DATA_WIDTH-1:0] barrelshifter_input_A [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_A inputs
wire [DATA_WIDTH-1:0] barrelshifter_input_B [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_B inputs
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
bytes_to_next_boundary_minus_one_d1 <= 0;
end
else if (start)
begin
bytes_to_next_boundary_minus_one_d1 <= bytes_to_next_boundary_minus_one;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
barrelshifter_B_d1 <= 0;
end
else
begin
if (start == 1)
begin
barrelshifter_B_d1 <= 0;
end
else if (fifo_readack == 1)
begin
barrelshifter_B_d1 <= barrelshifter_B;
end
end
end
assign bytes_to_next_boundary = (DATA_WIDTH/8) - address[BYTEENABLE_WIDTH_LOG2-1:0]; // bytes per word - unaligned byte offset = distance to next boundary
assign bytes_to_next_boundary_minus_one = bytes_to_next_boundary - 1;
assign combined_word = barrelshifter_A | barrelshifter_B_d1;
generate
genvar input_offset;
for(input_offset = 0; input_offset < (DATA_WIDTH/8); input_offset = input_offset + 1)
begin: barrel_shifter_inputs
assign barrelshifter_input_A[input_offset] = fifo_data << (8 * ((DATA_WIDTH/8)-(input_offset+1)));
assign barrelshifter_input_B[input_offset] = fifo_data >> (8 * (input_offset + 1));
end
endgenerate
assign barrelshifter_A = barrelshifter_input_A[bytes_to_next_boundary_minus_one_d1];
assign barrelshifter_B = barrelshifter_input_B[bytes_to_next_boundary_minus_one_d1];
generate
if (UNALIGNED_ACCESS_ENABLE == 1)
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1) & (start == 0);
assign write_data = combined_word;
end
else
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1);
assign write_data = fifo_data;
end
endgenerate
endmodule
|
module wb_ram
#(//Wishbone parameters
parameter dw = 32,
//Memory parameters
parameter depth = 256,
parameter aw = $clog2(depth),
parameter memfile = "")
(input wb_clk_i,
input wb_rst_i,
input [aw-1:0] wb_adr_i,
input [dw-1:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_we_i,
input [1:0] wb_bte_i,
input [2:0] wb_cti_i,
input wb_cyc_i,
input wb_stb_i,
output reg wb_ack_o,
output wb_err_o,
output [dw-1:0] wb_dat_o);
reg [aw-1:0] adr_r;
wire [aw-1:0] next_adr;
wire valid = wb_cyc_i & wb_stb_i;
reg valid_r;
wire new_cycle = valid & !valid_r;
wb_next_adr #(.aw(aw)) wb_next_adr0(adr_r, wb_cti_i, wb_bte_i, next_adr);
wire [aw-1:0] adr = new_cycle ? wb_adr_i : next_adr;
always@(posedge wb_clk_i) begin
adr_r <= adr;
valid_r <= valid;
//Ack generation
wb_ack_o <= valid & (!((wb_cti_i == 3'b000) | (wb_cti_i == 3'b111)) | !wb_ack_o);
if(wb_rst_i) begin
adr_r <= {aw{1'b0}};
valid_r <= 1'b0;
wb_ack_o <= 1'b0;
end
end
wire ram_we = wb_we_i & valid & wb_ack_o;
//TODO:ck for burst address errors
assign wb_err_o = 1'b0;
wb_ram_generic
#(.depth(depth/4),
.memfile (memfile))
ram0
(.clk (wb_clk_i),
.we ({4{ram_we}} & wb_sel_i),
.din (wb_dat_i),
.waddr(adr_r[aw-1:2]),
.raddr (adr[aw-1:2]),
.dout (wb_dat_o));
endmodule
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <[email protected]>
* Copyright (C) 2018 David Shah <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* techmap_celltype = "$alu" *)
module _80_gw1n_alu(A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = B_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] C = {CO, CI};
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
ALU #(.ALU_MODE(2)) // ADDSUB I3 ? add : sub
alu(.I0(AA[i]),
.I1(BB[i]),
.I3(~BI),
.CIN(C[i]),
.COUT(CO[i]),
.SUM(Y[i])
);
end endgenerate
assign X = AA ^ BB;
endmodule
|
//-----------------------------------------------------------------------------
// Title : MIPS Single-Cycle Control Unit
// Project : ECE 313 - Computer Organization
//-----------------------------------------------------------------------------
// File : control_single.v
// Author : John Nestor <[email protected]>
// Organization : Lafayette College
//
// Created : November 2002
// Last modified : 7 January 2005
//-----------------------------------------------------------------------------
// Description :
// Control unit for the MIPS pipelined processor implementation described
// Section 6.3 of "Computer Organization and Design, 3rd ed."
// by David Patterson & John Hennessey, Morgan Kaufmann, 2004 (COD3e).
//
// It implements the function specified in Figure 6.25 on p. 401 of COD3e.
//
//-----------------------------------------------------------------------------
module control_pipeline(opcode, RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch, ALUOp, Jumper);
input [5:0] opcode;
output RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch, Jumper;
output [1:0] ALUOp;
reg RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch, Jumper;
reg [1:0] ALUOp;
parameter R_FORMAT = 6'd0;
parameter LW = 6'd35;
parameter SW = 6'd43;
parameter BEQ = 6'd4;
parameter J = 6'd2; // J opcode
always @(opcode)
begin
case (opcode)
R_FORMAT :
begin
RegDst=1'b1; ALUSrc=1'b0; MemtoReg=1'b0; RegWrite=1'b1; MemRead=1'b0;
MemWrite=1'b0; Branch=1'b0; ALUOp = 2'b10; Jumper = 1'b0;
end
LW :
begin
RegDst=1'b0; ALUSrc=1'b1; MemtoReg=1'b1; RegWrite=1'b1; MemRead=1'b1;
MemWrite=1'b0; Branch=1'b0; ALUOp = 2'b00; Jumper = 1'b0;
end
SW :
begin
RegDst=1'bx; ALUSrc=1'b1; MemtoReg=1'bx; RegWrite=1'b0; MemRead=1'b0;
MemWrite=1'b1; Branch=1'b0; ALUOp = 2'b00; Jumper = 1'b0;
end
BEQ :
begin
RegDst=1'bx; ALUSrc=1'b0; MemtoReg=1'bx; RegWrite=1'b0; MemRead=1'b0;
MemWrite=1'b0; Branch=1'b1; ALUOp = 2'b01; Jumper = 1'b0;
end
J :
begin
RegDst=1'bx; ALUSrc=1'bX; MemtoReg=1'bx; RegWrite=1'b0; MemRead=1'b0;
MemWrite=1'b0; Branch=1'b0; ALUOp = 2'b01; Jumper = 1'b1;
end
default
begin
$display("control_single unimplemented opcode %d", opcode);
RegDst=1'b0; ALUSrc=1'b0; MemtoReg=1'b0; RegWrite=1'b0; MemRead=1'b0;
MemWrite=1'b0; Branch=1'b0; ALUOp = 2'b00; Jumper = 1'b0;
end
endcase
end
endmodule
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
|
/*
#######################################################
# Synchronizer circuit
#######################################################
*/
module synchronizer (/*AUTOARG*/
// Outputs
out,
// Inputs
in, clk, reset
);
parameter DW = 1;
//Input Side
input [DW-1:0] in;
input clk;
input reset;
//Output Side
output [DW-1:0] out;
//Three stages
reg [DW-1:0] sync_reg0;
reg [DW-1:0] out;
//We use two flip-flops for metastability improvement
always @ (posedge clk or posedge reset)
if(reset)
begin
sync_reg0[DW-1:0] <= {(DW){1'b0}};
out[DW-1:0] <= {(DW){1'b0}};
end
else
begin
sync_reg0[DW-1:0] <= in[DW-1:0];
out[DW-1:0] <= sync_reg0[DW-1:0];
end
endmodule // synchronizer
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
`include "bsg_nonsynth_dramsim3.svh"
`define dram_pkg bsg_dramsim3_hbm2_8gb_x128_pkg
module testbench();
bit clk;
bit reset;
bsg_nonsynth_clock_gen #(
.cycle_time_p(1000)
) cg0 (
.o(clk)
);
bsg_nonsynth_reset_gen #(
.reset_cycles_lo_p(0)
,.reset_cycles_hi_p(10)
) rg0 (
.clk_i(clk)
,.async_reset_o(reset)
);
import `dram_pkg::*;
// trace replay
localparam write_data_width_lp = 32; // we only write 32-bit data to save space.
localparam payload_width_p = `dram_pkg::channel_addr_width_p + 1 + write_data_width_lp;
localparam rom_addr_width_p = 20;
typedef struct packed {
logic write_not_read;
logic [`dram_pkg::channel_addr_width_p-1:0] ch_addr;
logic [write_data_width_lp-1:0] data;
} trace_s;
trace_s tr_data_lo;
logic tr_v_lo;
logic tr_yumi_li;
logic [rom_addr_width_p-1:0] rom_addr;
logic [payload_width_p+4-1:0] rom_data;
logic tr_done_lo;
bsg_trace_replay #(
.payload_width_p(payload_width_p)
,.rom_addr_width_p(rom_addr_width_p)
) tr0 (
.clk_i(clk)
,.reset_i(reset)
,.en_i(1'b1)
,.v_i(1'b0)
,.data_i('0)
,.ready_o()
,.v_o(tr_v_lo)
,.data_o(tr_data_lo)
,.yumi_i(tr_yumi_li)
,.rom_addr_o(rom_addr)
,.rom_data_i(rom_data)
,.done_o(tr_done_lo)
,.error_o()
);
bsg_nonsynth_test_rom #(
.filename_p("trace.tr")
,.data_width_p(payload_width_p+4)
,.addr_width_p(rom_addr_width_p)
) trom0 (
.addr_i(rom_addr)
,.data_o(rom_data)
);
// dramsim3
//
logic [num_channels_p-1:0] dramsim3_v_li;
logic [num_channels_p-1:0][channel_addr_width_p-1:0] dramsim3_ch_addr_li;
logic [num_channels_p-1:0] dramsim3_yumi_lo;
logic [num_channels_p-1:0] dramsim3_write_not_read_li;
logic [num_channels_p-1:0] dramsim3_data_v_li;
logic [num_channels_p-1:0] dramsim3_data_yumi_lo;
logic [num_channels_p-1:0][data_width_p-1:0] dramsim3_data_li;
logic [num_channels_p-1:0] dramsim3_data_v_lo;
logic [num_channels_p-1:0][data_width_p-1:0] dramsim3_data_lo;
logic [num_channels_p-1:0][channel_addr_width_p-1:0] dramsim3_read_done_ch_addr_lo;
logic [num_channels_p-1:0] dramsim3_write_done_lo;
bsg_nonsynth_dramsim3 #(
.channel_addr_width_p(`dram_pkg::channel_addr_width_p)
,.data_width_p(`dram_pkg::data_width_p)
,.num_channels_p(`dram_pkg::num_channels_p)
,.num_columns_p(`dram_pkg::num_columns_p)
,.num_rows_p(`dram_pkg::num_rows_p)
,.num_ba_p(`dram_pkg::num_ba_p)
,.num_bg_p(`dram_pkg::num_bg_p)
,.num_ranks_p(`dram_pkg::num_ranks_p)
,.size_in_bits_p(`dram_pkg::size_in_bits_p)
,.address_mapping_p(`dram_pkg::address_mapping_p)
,.config_p(`dram_pkg::config_p)
,.masked_p(0)
,.debug_p(1)
,.init_mem_p(1)
) DUT (
.clk_i(clk)
,.reset_i(reset)
,.v_i(dramsim3_v_li)
,.write_not_read_i(dramsim3_write_not_read_li)
,.ch_addr_i(dramsim3_ch_addr_li)
,.yumi_o(dramsim3_yumi_lo)
,.data_v_i(dramsim3_data_v_li)
,.data_i(dramsim3_data_li)
,.mask_i('0)
,.data_yumi_o(dramsim3_data_yumi_lo)
,.data_v_o(dramsim3_data_v_lo)
,.data_o(dramsim3_data_lo)
,.read_done_ch_addr_o(dramsim3_read_done_ch_addr_lo)
,.write_done_o(dramsim3_write_done_lo)
,.write_done_ch_addr_o()
);
assign dramsim3_v_li[0] = tr_v_lo;
assign dramsim3_write_not_read_li[0] = tr_data_lo.write_not_read;
assign dramsim3_ch_addr_li[0] = tr_data_lo.ch_addr;
assign tr_yumi_li = dramsim3_yumi_lo[0];
assign dramsim3_data_v_li[0] = tr_v_lo & tr_data_lo.write_not_read;
assign dramsim3_data_li[0] = {{(`dram_pkg::data_width_p-write_data_width_lp){1'b0}}, tr_data_lo.data};
for (genvar i = 1; i < `dram_pkg::num_channels_p; i++) begin
assign dramsim3_v_li[i] = 1'b0;
assign dramsim3_ch_addr_li[i] = '0;
assign dramsim3_write_not_read_li[i] = 1'b0;
assign dramsim3_data_v_li[i] = 1'b0;
assign dramsim3_data_li[i] = '0;
end
// request tracker
integer sent_r;
integer recv_r;
always_ff @ (posedge clk) begin
if (reset) begin
sent_r <= 0;
recv_r <= 0;
end
else begin
if (tr_v_lo & tr_yumi_li) sent_r <= sent_r + 1;
recv_r <= recv_r + dramsim3_data_v_lo[0] + dramsim3_write_done_lo[0];
end
end
initial begin
wait(tr_done_lo & (sent_r == recv_r));
#30000;
$display("[BSG_FINISH] test successful.");
$finish();
end
// consistency checker
// num_cols_p = columns_per_row * num_banks * ba_per_bg * num_rows
localparam num_cols_p = 64*4*4*(2**15);
logic [31:0] shadow_mem [num_cols_p-1:0];
logic [`dram_pkg::channel_addr_width_p-5-1:0] col_addr;
logic [`dram_pkg::channel_addr_width_p-5-1:0] read_done_col_addr;
assign col_addr = dramsim3_ch_addr_li[0][`dram_pkg::channel_addr_width_p-1:5];
assign read_done_col_addr = dramsim3_read_done_ch_addr_lo[0][`dram_pkg::channel_addr_width_p-1:5];
always_ff @ (posedge clk) begin
if (reset) begin
for (integer i = 0; i < num_cols_p; i++)
shadow_mem[i] = '0;
end
else begin
// input record
if (dramsim3_v_li[0] & dramsim3_yumi_lo[0]) begin
if (dramsim3_write_not_read_li[0]) begin
shadow_mem[col_addr] <= dramsim3_data_li[0][0+:32];
$display("[BSG_DEBUG] t=%t writing 0x%08x to 0x%08x\n", $time, dramsim3_data_li[0][0+:32], dramsim3_ch_addr_li[0]);
end
end
// output checker
if (dramsim3_data_v_lo[0]) begin
$display("[BSG_DEBUG] t=%t read 0x%08x from 0x%08x\n",$time, dramsim3_data_lo[0][0+:32], dramsim3_read_done_ch_addr_lo[0]);
assert(shadow_mem[read_done_col_addr] == dramsim3_data_lo[0][0+:32])
//$display("[BSG_INFO] output matched. Id=%d, Expected=%x, Actual=%x", recv_id, result[recv_id], dramsim3_data_lo[0][0+:32]);
else $fatal("[BSG_FATAL] output does not match expected result for 0x%x. Expected=%x, Actual=%x",
dramsim3_read_done_ch_addr_lo[0], shadow_mem[read_done_col_addr], dramsim3_data_lo[0][0+:32]);
end
end
end
endmodule
|
module alu_controller
(/*AUTOARG*/
// Outputs
out_alu_ready, out_vcc_wr_en, out_instr_done, out_vgpr_wr_en,
out_vgpr_dest_addr, out_sgpr_wr_en, out_sgpr_dest_addr,
out_alu_control, out_alu_start, out_src_buffer_wr_en,
out_source1_mux_select, out_source2_mux_select,
out_source3_mux_select, out_source1_src_constant,
out_source2_src_constant, out_source3_src_constant,
out_vgpr_source1_rd_en, out_vgpr_source2_rd_en,
out_vgpr_source3_rd_en, out_sgpr_rd_en, out_exec_rd_en,
// Inputs
in_alu_select_flopped, in_alu_select, in_source1_addr,
in_source2_addr, in_source3_addr, in_dest1_addr, in_dest2_addr,
in_opcode, in_valu_done, clk, rst
);
parameter MODULE = `MODULE_SIMD;
input in_alu_select_flopped;
input in_alu_select;
input [11:0] in_source1_addr;
input [11:0] in_source2_addr;
input [11:0] in_source3_addr;
input [11:0] in_dest1_addr;
input [11:0] in_dest2_addr;
input [31:0] in_opcode;
input in_valu_done;
output out_alu_ready;
output out_vcc_wr_en;
output out_instr_done;
output out_vgpr_wr_en;
output [11:0] out_vgpr_dest_addr;
output out_sgpr_wr_en;
output [11:0] out_sgpr_dest_addr;
output [31:0] out_alu_control;
output out_alu_start;
output out_src_buffer_wr_en;
output [3:0] out_source1_mux_select;
output [3:0] out_source2_mux_select;
output [3:0] out_source3_mux_select;
output [9:0] out_source1_src_constant;
output [9:0] out_source2_src_constant;
output [9:0] out_source3_src_constant;
output out_vgpr_source1_rd_en;
output out_vgpr_source2_rd_en;
output out_vgpr_source3_rd_en;
output out_sgpr_rd_en;
output out_exec_rd_en;
input clk;
input rst;
reg out_vcc_wr_en;
reg out_instr_done;
reg out_vgpr_wr_en;
reg out_sgpr_wr_en;
reg [31:0] out_alu_control;
reg out_src_buffer_wr_en;
wire out_vgpr_source1_rd_en;
wire out_vgpr_source2_rd_en;
wire out_vgpr_source3_rd_en;
wire out_sgpr_rd_en;
wire out_exec_rd_en;
reg [11:0] out_vgpr_dest_addr;
reg [11:0] out_sgpr_dest_addr;
reg [9:0] out_source1_src_constant;
reg [9:0] out_source2_src_constant;
reg [9:0] out_source3_src_constant;
reg [3:0] out_source1_mux_select;
reg [3:0] out_source2_mux_select;
reg [3:0] out_source3_mux_select;
wire dec_vcc_wr_en;
wire dec_vgpr_wr_en;
wire dec_sgpr_wr_en;
reg dec_vgpr_source1_rd_en;
reg dec_vgpr_source2_rd_en;
reg dec_vgpr_source3_rd_en;
wire dec_sgpr_rd_en;
wire dec_exec_rd_en;
reg [3:0] dec_out_source1_mux_select;
reg [3:0] dec_out_source2_mux_select;
reg [3:0] dec_out_source3_mux_select;
wire RD, EX, WB;
assign dec_sgpr_rd_en = 1'b1;
assign dec_exec_rd_en = 1'b1;
always @ (in_source1_addr) begin
dec_vgpr_source1_rd_en <= 1'b0;
casex(in_source1_addr)
12'b0_11111111111 : //literal constant
begin
dec_out_source1_mux_select <= 4'b0000;
end
12'b0_0_?????????? : //constant value
begin
dec_out_source1_mux_select <= 4'b0001;
end
12'b1_0_?????????? : //read VGPR
begin
dec_out_source1_mux_select <= 4'b0010;
dec_vgpr_source1_rd_en <= 1'b1;
end
12'b1_1_0_????????? : //read value from SGPR
begin
dec_out_source1_mux_select <= 4'b0011;
end
12'b1_1_1_0_0000_0001 : //read VCC_LO
begin
dec_out_source1_mux_select <= 4'b0100;
end
12'b1_1_1_0_0000_0010 : //read VCC_HI
begin
dec_out_source1_mux_select <= 4'b0101;
end
12'b1_1_1_0_0000_0100 : //read M0
begin
dec_out_source1_mux_select <= 4'b0110;
end
12'b1_1_1_0_0000_1000 : //read EXEC_LO
begin
dec_out_source1_mux_select <= 4'b0111;
end
12'b1_1_1_0_0001_0000 : //read EXEC_HI
begin
dec_out_source1_mux_select <= 4'b1000;
end
12'b1_1_1_0_0010_0000 : //read VCCZ
begin
dec_out_source1_mux_select <= 4'b1001;
end
12'b1_1_1_0_0100_0000 : //read EXECZ
begin
dec_out_source1_mux_select <= 4'b1010;
end
12'b1_1_1_0_1000_0000 : //read SCC
begin
dec_out_source1_mux_select <= 4'b1011;
end
default:
begin
dec_out_source1_mux_select <= 4'bx;
end
endcase
end
always @ (in_source2_addr) begin
dec_vgpr_source2_rd_en <= 1'b0;
casex(in_source2_addr)
12'b0_11111111111 : //literal constant
begin
dec_out_source2_mux_select <= 4'b0000;
end
12'b0_0_?????????? : //constant value
begin
dec_out_source2_mux_select <= 4'b0001;
end
12'b1_0_?????????? : //read VGPR
begin
dec_out_source2_mux_select <= 4'b0010;
dec_vgpr_source2_rd_en <= 1'b1;
end
12'b1_1_0_????????? : //read value from SGPR
begin
dec_out_source2_mux_select <= 4'b0011;
end
12'b1_1_1_0_0000_0001 : //read VCC_LO
begin
dec_out_source2_mux_select <= 4'b0100;
end
12'b1_1_1_0_0000_0010 : //read VCC_HI
begin
dec_out_source2_mux_select <= 4'b0101;
end
12'b1_1_1_0_0000_0100 : //read M0
begin
dec_out_source2_mux_select <= 4'b0110;
end
12'b1_1_1_0_0000_1000 : //read EXEC_LO
begin
dec_out_source2_mux_select <= 4'b0111;
end
12'b1_1_1_0_0001_0000 : //read EXEC_HI
begin
dec_out_source2_mux_select <= 4'b1000;
end
12'b1_1_1_0_0010_0000 : //read VCCZ
begin
dec_out_source2_mux_select <= 4'b1001;
end
12'b1_1_1_0_0100_0000 : //read EXECZ
begin
dec_out_source2_mux_select <= 4'b1010;
end
12'b1_1_1_0_1000_0000 : //read SCC
begin
dec_out_source2_mux_select <= 4'b1011;
end
default:
begin
dec_out_source2_mux_select <= 4'bx;
end
endcase
end
always @ (in_source3_addr) begin
dec_vgpr_source3_rd_en <= 1'b0;
casex(in_source3_addr)
12'b0_11111111111 : //literal constant
begin
dec_out_source3_mux_select <= 4'b0000;
end
12'b0_0_?????????? : //constant value
begin
dec_out_source3_mux_select <= 4'b0001;
end
12'b1_0_?????????? : //read VGPR
begin
dec_out_source3_mux_select <= 4'b0010;
dec_vgpr_source3_rd_en <= 1'b1;
end
12'b1_1_0_????????? : //read value from SGPR
begin
dec_out_source3_mux_select <= 4'b0011;
end
12'b1_1_1_0_0000_0001 : //read VCC_LO
begin
dec_out_source3_mux_select <= 4'b0100;
end
12'b1_1_1_0_0000_0010 : //read VCC_HI
begin
dec_out_source3_mux_select <= 4'b0101;
end
12'b1_1_1_0_0000_0100 : //read M0
begin
dec_out_source3_mux_select <= 4'b0110;
end
12'b1_1_1_0_0000_1000 : //read EXEC_LO
begin
dec_out_source3_mux_select <= 4'b0111;
end
12'b1_1_1_0_0001_0000 : //read EXEC_HI
begin
dec_out_source3_mux_select <= 4'b1000;
end
12'b1_1_1_0_0010_0000 : //read VCCZ
begin
dec_out_source3_mux_select <= 4'b1001;
end
12'b1_1_1_0_0100_0000 : //read EXECZ
begin
dec_out_source3_mux_select <= 4'b1010;
end
12'b1_1_1_0_1000_0000 : //read SCC
begin
dec_out_source3_mux_select <= 4'b1011;
end
default:
begin
dec_out_source3_mux_select <= 4'bx;
end
endcase
end
assign out_vgpr_source1_rd_en = dec_vgpr_source1_rd_en && in_alu_select;
assign out_vgpr_source2_rd_en = dec_vgpr_source2_rd_en && in_alu_select;
assign out_vgpr_source3_rd_en = dec_vgpr_source3_rd_en && in_alu_select;
assign out_sgpr_rd_en = dec_sgpr_rd_en && in_alu_select;
assign out_exec_rd_en = dec_exec_rd_en && in_alu_select;
// Single cycle delay for the mux select and src_constant so
// they arrive with the rest of the data
always @ ( posedge clk or posedge rst ) begin
if(rst) begin
out_source1_mux_select <= 0;
out_source2_mux_select <= 0;
out_source3_mux_select <= 0;
out_source1_src_constant <= 0;
out_source2_src_constant <= 0;
out_source3_src_constant <= 0;
end
else begin
out_source1_mux_select <= dec_out_source1_mux_select;
out_source2_mux_select <= dec_out_source2_mux_select;
out_source3_mux_select <= dec_out_source3_mux_select;
out_source1_src_constant <= in_source1_addr[9:0];
out_source2_src_constant <= in_source2_addr[9:0];
out_source3_src_constant <= in_source3_addr[9:0];
end
end
always @* begin
casex({in_dest1_addr[11:10], in_dest2_addr[11:10]})
4'b10_??:
begin
out_vgpr_dest_addr <= in_dest1_addr;
out_sgpr_dest_addr <= in_dest2_addr;
end
4'b11_??:
begin
out_vgpr_dest_addr <= in_dest2_addr;
out_sgpr_dest_addr <= in_dest1_addr;
end
4'b??_10:
begin
out_vgpr_dest_addr <= in_dest2_addr;
out_sgpr_dest_addr <= in_dest1_addr;
end
4'b??_11:
begin
out_vgpr_dest_addr <= in_dest1_addr;
out_sgpr_dest_addr <= in_dest2_addr;
end
default:
begin
out_vgpr_dest_addr <= 12'bx;
out_sgpr_dest_addr <= 12'bx;
end
endcase
end
generate
if (MODULE == `MODULE_SIMD)
simd_instr_decoder simd_instr_decoder
(
.in_sgpr_dest_addr(out_sgpr_dest_addr),
.in_opcode(in_opcode),
.out_vcc_wr_en(dec_vcc_wr_en),
.out_vgpr_wr_en(dec_vgpr_wr_en),
.out_sgpr_wr_en(dec_sgpr_wr_en)
);
else if (MODULE == `MODULE_SIMF)
simf_instr_decoder simf_instr_decoder
(
.in_sgpr_dest_addr(out_sgpr_dest_addr),
.in_opcode(in_opcode),
.out_vcc_wr_en(dec_vcc_wr_en),
.out_vgpr_wr_en(dec_vgpr_wr_en),
.out_sgpr_wr_en(dec_sgpr_wr_en)
);
endgenerate
alu_fsm alu_fsm
(
.in_alu_select(in_alu_select_flopped),
.out_alu_start(out_alu_start),
.in_valu_done(in_valu_done),
.out_alu_ready(out_alu_ready),
.RD(RD),
.EX(EX),
.WB(WB),
.clk(clk),
.rst(rst)
);
always @ (RD) begin
casex(RD)
1'b0 :
begin
out_src_buffer_wr_en <= 1'b0;
end
1'b1 :
begin
out_src_buffer_wr_en <= 1'b1;
end
default:
begin
out_src_buffer_wr_en <= 1'bx;
end
endcase
end
always @ (EX or in_opcode) begin
casex(EX)
1'b0 :
begin
out_alu_control <= 32'd0;
end
1'b1 :
begin
out_alu_control <= in_opcode;
end
default :
begin
out_alu_control <= 32'dx;
end
endcase
end
always @ (WB or dec_vcc_wr_en or dec_vgpr_wr_en or dec_sgpr_wr_en) begin
casex(WB)
1'b0 :
begin
out_vcc_wr_en <= 1'b0;
out_instr_done <= 1'b0;
out_vgpr_wr_en <= 1'b0;
out_sgpr_wr_en <= 1'b0;
end
1'b1 :
begin
out_vcc_wr_en <= dec_vcc_wr_en;
out_instr_done <= 1'b1;
out_vgpr_wr_en <= dec_vgpr_wr_en;
out_sgpr_wr_en <= dec_sgpr_wr_en;
end
default :
begin
out_vcc_wr_en <= 1'bx;
out_instr_done <= 1'bx;
out_vgpr_wr_en <= 1'bx;
out_sgpr_wr_en <= 1'bx;
end
endcase
end
endmodule
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: tx_engine
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: Tx engine wrapper file. Connects
// accompanying fifos to the TX TRN State Machine module.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// Modification by zjs, 2009-6-18, pending
// (1) move posted packet generator and non-posted packet generator out --- done
// (2) add dma write data fifo --------------- done
// (3) modify tx sm
// scheduling -------------------------- done
// disable write dma done -------------- done
// register/memory read ---------------- done
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module tx_engine(
input clk,
// input rst,
// input hostreset,
input full_rst,
input soft_rst,
/// Jiansong: new interface added for register read / memory read operation
//interface to DMA control wrapper, for register data
input [31:0] Mrd_data_in, // 32 bits register read assumed
output [11:0] Mrd_data_addr,
//interface to PCIE Endpoint Block Plus
input [15:0] pcie_id,
output [63:0] trn_td,
output [7:0] trn_trem_n,
output trn_tsof_n,
output trn_teof_n,
output trn_tsrc_rdy_n,
output trn_tsrc_dsc_n,
input trn_tdst_rdy_n,
input trn_tdst_dsc_n,
output trn_terrfwd_n,
input [2:0] trn_tbuf_av,
/// Jiansong: interface to non_posted_pkt_gen
input non_posted_fifo_wren,
input [63:0] non_posted_fifo_data,
/// Jiansong: interface to posted_pkt_gen
input posted_fifo_wren,
input [63:0] posted_fifo_data,
output posted_fifo_full,
/// Jiansong: interface from posted_pkt_gen to dma write data fifo
input [63:0] dma_write_data_fifo_data,
input dma_write_data_fifo_wren,
output dma_write_data_fifo_full,
/// Jiansong: keep completion logic in TX engine
//interface to RX Engine
input [6:0] bar_hit,
input MRd,
input MWr,
input [31:0] MEM_addr,
input [15:0] MEM_req_id,
input [7:0] MEM_tag,
input header_fields_valid,
// Jiansong: input from rx_monitor
input rd_dma_start, //indicates the start of a read dma xfer
input [12:3] dmarxs //size of the complete transfer
// input [9:0] np_rx_cnt_qw,
// input transferstart,
// input Wait_for_TX_desc
// debug interface
// output [31:0] Debug21RX2,
// output [31:0] Debug25RX6,
// output [7:0] FIFOErrors
);
wire posted_hdr_fifo_rden;
wire [63:0] posted_hdr_fifo;
wire posted_hdr_fifo_empty;
wire non_posted_hdr_fifo_rden;
wire [63:0] non_posted_hdr_fifo;
wire non_posted_hdr_fifo_empty;
wire non_posted_hdr_fifo_full;
wire comp_fifo_wren;
wire [63:0] comp_fifo_data;
wire comp_hdr_fifo_rden;
wire [63:0] comp_hdr_fifo;
wire comp_hdr_fifo_empty;
wire comp_hdr_fifo_full;
/// Jiansong: posted data fifo interface
wire [63:0] posted_data_fifo_data;
wire posted_data_fifo_rden;
wire posted_data_fifo_empty;
wire posted_data_fifo_real_full;
/// Jiansong
wire rst_tx;
// /// FIFO errors
// reg p_hdr_fifo_overflow;
// reg p_hdr_fifo_underflow;
// reg p_data_fifo_overflow;
// reg p_data_fifo_underflow;
// reg cmp_hdr_fifo_overflow;
// reg cmp_hdr_fifo_underflow;
// reg np_hdr_fifo_overflow;
// reg np_hdr_fifo_underflow;
// assign FIFOErrors[0] = p_hdr_fifo_overflow;
// assign FIFOErrors[1] = p_hdr_fifo_underflow;
// assign FIFOErrors[2] = p_data_fifo_overflow;
// assign FIFOErrors[3] = p_data_fifo_underflow;
// assign FIFOErrors[4] = cmp_hdr_fifo_overflow;
// assign FIFOErrors[5] = cmp_hdr_fifo_underflow;
// assign FIFOErrors[6] = np_hdr_fifo_overflow;
// assign FIFOErrors[7] = np_hdr_fifo_underflow;
//
// always@(posedge clk) begin
// if (rst_tx)
// p_hdr_fifo_overflow <= 1'b0;
// else if (posted_fifo_full & posted_fifo_wren)
// p_hdr_fifo_overflow <= 1'b1;
// else
// p_hdr_fifo_overflow <= p_hdr_fifo_overflow;
// end
// always@(posedge clk) begin
// if (rst_tx)
// p_hdr_fifo_underflow <= 1'b0;
// else if (posted_hdr_fifo_empty & posted_hdr_fifo_rden)
// p_hdr_fifo_underflow <= 1'b1;
// else
// p_hdr_fifo_underflow <= p_hdr_fifo_underflow;
// end
// always@(posedge clk) begin
// if (rst_tx)
// p_data_fifo_overflow <= 1'b0;
// else if (posted_data_fifo_real_full & dma_write_data_fifo_wren)
// p_data_fifo_overflow <= 1'b1;
// else
// p_data_fifo_overflow <= p_data_fifo_overflow;
// end
// always@(posedge clk) begin
// if (rst_tx)
// p_data_fifo_underflow <= 1'b0;
// else if (posted_data_fifo_empty & posted_data_fifo_rden)
// p_data_fifo_underflow <= 1'b1;
// else
// p_data_fifo_underflow <= p_data_fifo_underflow;
// end
// always@(posedge clk) begin
// if (rst_tx)
// cmp_hdr_fifo_overflow <= 1'b0;
// else if (comp_hdr_fifo_full & comp_fifo_wren)
// cmp_hdr_fifo_overflow <= 1'b1;
// else
// cmp_hdr_fifo_overflow <= cmp_hdr_fifo_overflow;
// end
// always@(posedge clk) begin
// if (rst_tx)
// cmp_hdr_fifo_underflow <= 1'b0;
// else if (comp_hdr_fifo_empty & comp_hdr_fifo_rden)
// cmp_hdr_fifo_underflow <= 1'b1;
// else
// cmp_hdr_fifo_underflow <= cmp_hdr_fifo_underflow;
// end
// always@(posedge clk) begin
// if (rst_tx)
// np_hdr_fifo_overflow <= 1'b0;
// else if (non_posted_hdr_fifo_full & non_posted_fifo_wren)
// np_hdr_fifo_overflow <= 1'b1;
// else
// np_hdr_fifo_overflow <= np_hdr_fifo_overflow;
// end
// always@(posedge clk) begin
// if (rst_tx)
// np_hdr_fifo_underflow <= 1'b0;
// else if (non_posted_hdr_fifo_empty & non_posted_hdr_fifo_rden)
// np_hdr_fifo_underflow <= 1'b1;
// else
// np_hdr_fifo_underflow <= np_hdr_fifo_underflow;
// end
/// Jiansong: timing solution, what does it mean?
// //register and dup wr_dma_start_one for 250 MHz timing;
// (*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg wr_dma_start_one_reg1,
// wr_dma_start_one_reg2;
//// reg wr_dma_start_one_reg1;
/// Jiansong: why the depth is 128? Performance consideration?
/// Jiansong: full signal is never used
// Fifo is a 64 x 128 coregen fifo made out of distributed ram
a64_128_distram_fifo a64_128_distram_fifo_p(
.clk(clk),
.rst(rst_tx),
//interface to posted_pkt_gen
.din(posted_fifo_data),
.wr_en(posted_fifo_wren),
//// .full(posted_hdr_fifo_full),
.full(posted_fifo_full),
//interface to tx_trn_sm
.dout(posted_hdr_fifo),
.rd_en(posted_hdr_fifo_rden),
.empty(posted_hdr_fifo_empty)
);
/// Jiansong: full signal is never used
//Fifo is a 64 x 64 coregen fifo made out of distributed ram
a64_64_distram_fifo a64_64_distram_fifo_np(
.clk(clk),
.rst(rst_tx),
//inteface to non_posted_pkt_gen
.din(non_posted_fifo_data),
.wr_en(non_posted_fifo_wren),
.full(non_posted_hdr_fifo_full),
//interface to tx_trn_sm
.dout(non_posted_hdr_fifo),
.rd_en(non_posted_hdr_fifo_rden),
.empty(non_posted_hdr_fifo_empty)
);
// Instantiate the completer packet generator
completer_pkt_gen completer_pkt_gen_inst (
.clk(clk),
.rst(rst_tx),
//interface to RX Engine (except comp_id from PCIe block)
.bar_hit(bar_hit[6:0]),
.comp_req(MRd & header_fields_valid),
.MEM_addr(MEM_addr[31:0]),
.MEM_req_id(MEM_req_id[15:0]),
.comp_id(pcie_id[15:0]), //req_id becomes completer id
.MEM_tag(MEM_tag[7:0]),
//inteface to completion header fifo (a64_64_distram_fifo_comp)
.comp_fifo_wren(comp_fifo_wren),
.comp_fifo_data(comp_fifo_data[63:0])
);
//Fifo is a 64 x 64 coregen fifo made out of distributed ram
a64_64_distram_fifo a64_64_distram_fifo_comp(
.clk(clk),
.rst(rst_tx),
//interface to completer_pkt_gen
.din(comp_fifo_data[63:0]),
.wr_en(comp_fifo_wren),
.full(comp_hdr_fifo_full),
//interface to tx_trn_sm
.dout(comp_hdr_fifo),
.rd_en(comp_hdr_fifo_rden),
.empty(comp_hdr_fifo_empty)
);
/// Jiansong: Data TRN DMA Write FIFO, pending
//Instantiate the Data TRN DMA Write FIFO
//This is an 4KB FIFO constructed of BRAM
//Provides buffering for RX data and RX descriptor
data_trn_dma_write_fifo data_trn_dma_write_fifo_inst(
.din (dma_write_data_fifo_data),
.rd_en (posted_data_fifo_rden),
.rst (rst_tx),
.clk (clk),
.wr_en (dma_write_data_fifo_wren),
.dout (posted_data_fifo_data),
.empty (posted_data_fifo_empty),
.full (posted_data_fifo_real_full),
.prog_full (dma_write_data_fifo_full)
);
//Instantiate the TRN interface state machine
tx_trn_sm tx_trn_sm_inst (
.clk(clk),
// .rst_in(rst),
// .hostreset_in(hostreset),
.full_rst(full_rst),
.soft_rst(soft_rst),
.rst_out(rst_tx),
//interface to the header fifos
.posted_hdr_fifo(posted_hdr_fifo),
.posted_hdr_fifo_rden(posted_hdr_fifo_rden),
.posted_hdr_fifo_empty(posted_hdr_fifo_empty),
.nonposted_hdr_fifo(non_posted_hdr_fifo),
.nonposted_hdr_fifo_rden(non_posted_hdr_fifo_rden),
.nonposted_hdr_fifo_empty(non_posted_hdr_fifo_empty),
.comp_hdr_fifo(comp_hdr_fifo),
.comp_hdr_fifo_empty(comp_hdr_fifo_empty),
.comp_hdr_fifo_rden(comp_hdr_fifo_rden),
/// Jiansong: posted data fifo interface
.posted_data_fifo_data(posted_data_fifo_data),
.posted_data_fifo_rden(posted_data_fifo_rden),
.posted_data_fifo_empty(posted_data_fifo_empty),
.Mrd_data_addr(Mrd_data_addr),
.Mrd_data_in(Mrd_data_in),
//interface to PCIe Endpoint Block Plus TX TRN
.trn_td(trn_td[63:0]), //O [63:0]
.trn_trem_n(trn_trem_n[7:0]), //O [7:0]
.trn_tsof_n(trn_tsof_n), //O
.trn_teof_n(trn_teof_n), //O
.trn_tsrc_rdy_n(trn_tsrc_rdy_n), //O
.trn_tsrc_dsc_n(trn_tsrc_dsc_n), //O
.trn_tdst_rdy_n(trn_tdst_rdy_n), //I
.trn_tdst_dsc_n(trn_tdst_dsc_n), //I
.trn_terrfwd_n(trn_terrfwd_n), //O
.trn_tbuf_av(trn_tbuf_av[2:0]), //I [3:0]
/// Jiansong: input from rx_monitor
.rd_dma_start(rd_dma_start),
.dmarxs(dmarxs)
// .np_rx_cnt_qw(np_rx_cnt_qw),
// .transferstart (transferstart),
// .Wait_for_TX_desc(Wait_for_TX_desc)
// debug interface
// .Debug21RX2(Debug21RX2),
// .Debug25RX6(Debug25RX6)
);
endmodule
|
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's IC TAGs ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instatiation of instruction cache tag rams ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_ic_tag.v,v $
// Revision 1.1 2008/05/07 22:43:22 daughtry
// Initial Demo RTL check-in
//
// Revision 1.7 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.6 2004/04/08 11:00:46 simont
// Add support for 512B instruction cache.
//
// Revision 1.5 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.3 2002/10/24 22:19:04 mohor
// Signal scanb_eni renamed to scanb_en
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_ic_tag(
// Clock and reset
clk, rst,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Internal i/f
addr, en, we, datain, tag_v, tag
);
parameter dw = `OR1200_ICTAG_W;
parameter aw = `OR1200_ICTAG;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Internal i/f
//
input [aw-1:0] addr;
input en;
input we;
input [dw-1:0] datain;
output tag_v;
output [dw-2:0] tag;
`ifdef OR1200_NO_IC
//
// Insn cache not implemented
//
assign tag = {dw-1{1'b0}};
assign tag_v = 1'b0;
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`else
//
// Instantiation of TAG RAM block
//
`ifdef OR1200_IC_1W_512B
or1200_spram_32x24 ic_tag0(
`endif
`ifdef OR1200_IC_1W_4KB
or1200_spram_256x21 ic_tag0(
`endif
`ifdef OR1200_IC_1W_8KB
or1200_spram_512x20 ic_tag0(
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.clk(clk),
.rst(rst),
.ce(en),
.we(we),
.oe(1'b1),
.addr(addr),
.di(datain),
.doq({tag, tag_v})
);
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21O_TB_V
`define SKY130_FD_SC_HDLL__A21O_TB_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a21o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1 = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1 = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 B1 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 B1 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hdll__a21o dut (.A1(A1), .A2(A2), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21O_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_2_V
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_2_V
/**
* lpflow_isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog wrapper for lpflow_isobufsrc with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_isobufsrc.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_isobufsrc_2 (
X ,
SLEEP,
A ,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input SLEEP;
input A ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__lpflow_isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_isobufsrc_2 (
X ,
SLEEP,
A
);
output X ;
input SLEEP;
input A ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__lpflow_isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_2_V
|
//========================================================================
// Verilog Components: Registers
//========================================================================
// Note that we place the register output earlier in the port list since
// this is one place we might actually want to use positional port
// binding like this:
//
// wire [p_nbits-1:0] result_B;
// vc_Reg#(p_nbits) result_AB( clk, result_B, result_A );
`ifndef VC_REGS_V
`define VC_REGS_V
`include "vc-assert.v"
//------------------------------------------------------------------------
// Postive-edge triggered flip-flop
//------------------------------------------------------------------------
module vc_Reg
#(
parameter p_nbits = 1
)(
input clk, // Clock input
output [p_nbits-1:0] q, // Data output
input [p_nbits-1:0] d // Data input (sampled on rising clk edge)
);
reg q;
always @( posedge clk )
q <= d;
endmodule
//------------------------------------------------------------------------
// Postive-edge triggered flip-flop with reset
//------------------------------------------------------------------------
module vc_ResetReg
#(
parameter p_nbits = 1,
parameter p_reset_value = 0
)(
input clk, // Clock input
input reset, // Sync reset input (sampled on rising edge)
output [p_nbits-1:0] q, // Data output
input [p_nbits-1:0] d // Data input (sampled on rising clk edge)
);
reg q;
always @( posedge clk )
q <= reset ? p_reset_value : d;
endmodule
//------------------------------------------------------------------------
// Postive-edge triggered flip-flop with enable
//------------------------------------------------------------------------
module vc_EnReg
#(
parameter p_nbits = 1
)(
input clk, // Clock input
input reset, // Sync reset input (sampled on rising edge)
output [p_nbits-1:0] q, // Data output
input [p_nbits-1:0] d, // Data input (sampled on rising clk edge)
input en // Enable input (sampled on rising clk edge)
);
reg q;
always @( posedge clk )
if ( en )
q <= d;
// Assertions
always @( posedge clk )
if ( !reset )
`VC_ASSERT_NOT_X( en );
endmodule
//------------------------------------------------------------------------
// Postive-edge triggered flip-flop with enable and reset
//------------------------------------------------------------------------
module vc_EnResetReg
#(
parameter p_nbits = 1,
parameter p_reset_value = 0
)(
input clk, // Clock input
input reset, // Sync reset input (sampled on rising edge)
output [p_nbits-1:0] q, // Data output
input [p_nbits-1:0] d, // Data input (sampled on rising clk edge)
input en // Enable input (sampled on rising clk edge)
);
reg q;
always @( posedge clk )
if ( reset || en )
q <= reset ? p_reset_value : d;
// Assertions
always @( posedge clk )
if ( !reset )
`VC_ASSERT_NOT_X( en );
endmodule
`endif /* VC_REGS_V */
|
(* abc9_lut=1, lib_whitebox *)
module LUT1 (
output O,
input I0
);
parameter [1:0] INIT = 0;
parameter EQN = "(I0)";
// These timings are for PolarPro 3E; other families will need updating.
specify
(I0 => O) = 698; // FS -> FZ
endspecify
assign O = I0 ? INIT[1] : INIT[0];
endmodule
// TZ TSL TAB
(* abc9_lut=2, lib_whitebox *)
module LUT2 (
output O,
input I0, I1
);
parameter [3:0] INIT = 4'h0;
parameter EQN = "(I0)";
// These timings are for PolarPro 3E; other families will need updating.
specify
(I0 => O) = 1251; // TAB -> TZ
(I1 => O) = 1406; // TSL -> TZ
endspecify
wire [1:0] s1 = I1 ? INIT[3:2] : INIT[1:0];
assign O = I0 ? s1[1] : s1[0];
endmodule
(* abc9_lut=2, lib_whitebox *)
module LUT3 (
output O,
input I0, I1, I2
);
parameter [7:0] INIT = 8'h0;
parameter EQN = "(I0)";
// These timings are for PolarPro 3E; other families will need updating.
specify
(I0 => O) = 1251; // TAB -> TZ
(I1 => O) = 1406; // TSL -> TZ
(I2 => O) = 1699; // ('TA1', 'TA2', 'TB1', 'TB2') -> TZ
endspecify
wire [3:0] s2 = I2 ? INIT[7:4] : INIT[3:0];
wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0];
assign O = I0 ? s1[1] : s1[0];
endmodule
(* abc9_lut=4, lib_whitebox *)
module LUT4 (
output O,
input I0, I1, I2, I3
);
parameter [15:0] INIT = 16'h0;
parameter EQN = "(I0)";
// These timings are for PolarPro 3E; other families will need updating.
specify
(I0 => O) = 995; // TBS -> CZ
(I1 => O) = 1437; // ('TAB', 'BAB') -> CZ
(I2 => O) = 1593; // ('TSL', 'BSL') -> CZ
(I3 => O) = 1887; // ('TA1', 'TA2', 'TB1', 'TB2', 'BA1', 'BA2', 'BB1', 'BB2') -> CZ
endspecify
wire [7:0] s3 = I3 ? INIT[15:8] : INIT[7:0];
wire [3:0] s2 = I2 ? s3[7:4] : s3[3:0];
wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0];
assign O = I0 ? s1[1] : s1[0];
endmodule
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
///////////////////////////////////////////////////////////////////////////////
// Title : DDR controller Command Queue
//
// File : alt_ddrx_command_queue.v
//
// Abstract : Store incoming commands
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module alt_ddrx_cmd_queue
# (parameter MEM_IF_CSR_COL_WIDTH = 4,
MEM_IF_CSR_ROW_WIDTH = 5,
MEM_IF_CSR_BANK_WIDTH = 2,
MEM_IF_CSR_CS_WIDTH = 2,
CTL_CMD_QUEUE_DEPTH = 4,
CTL_LOOK_AHEAD_DEPTH = 4,
MEM_IF_ROW_WIDTH = 16,
MEM_IF_COL_WIDTH = 12,
MEM_IF_BA_WIDTH = 3,
MEM_IF_CHIP_BITS = 2,
LOCAL_ADDR_WIDTH = 33,
DWIDTH_RATIO = 4,
ENABLE_BURST_MERGE = 1,
MIN_COL = 8,
MIN_ROW = 12,
MIN_BANK = 2,
MIN_CS = 1
)
(
//input
ctl_clk ,
ctl_reset_n ,
read_req_to_cmd_queue ,
write_req_to_cmd_queue ,
local_size ,
local_autopch_req ,
local_multicast ,
local_cs_addr ,
local_bank_addr ,
local_row_addr ,
local_col_addr ,
//input from State Machine
fetch,
//output
cmd_fifo_empty,
cmd_fifo_full,
cmd_fifo_wren,
cmd0_is_a_read,
cmd0_is_a_write,
cmd0_autopch_req,
cmd0_burstcount,
cmd0_chip_addr,
cmd0_row_addr,
cmd0_bank_addr,
cmd0_col_addr,
cmd0_is_valid,
cmd0_multicast_req,
cmd1_is_a_read,
cmd1_is_a_write,
cmd1_chip_addr,
cmd1_row_addr,
cmd1_bank_addr,
cmd1_is_valid,
cmd1_multicast_req,
cmd2_is_a_read,
cmd2_is_a_write,
cmd2_chip_addr,
cmd2_row_addr,
cmd2_bank_addr,
cmd2_is_valid,
cmd2_multicast_req,
cmd3_is_a_read,
cmd3_is_a_write,
cmd3_chip_addr,
cmd3_row_addr,
cmd3_bank_addr,
cmd3_is_valid,
cmd3_multicast_req,
cmd4_is_a_read,
cmd4_is_a_write,
cmd4_is_valid,
cmd4_chip_addr,
cmd4_row_addr,
cmd4_bank_addr,
cmd4_multicast_req,
cmd5_is_a_read,
cmd5_is_a_write,
cmd5_is_valid,
cmd5_chip_addr,
cmd5_row_addr,
cmd5_bank_addr,
cmd5_multicast_req,
cmd6_is_a_read,
cmd6_is_a_write,
cmd6_is_valid,
cmd6_chip_addr,
cmd6_row_addr,
cmd6_bank_addr,
cmd6_multicast_req,
cmd7_is_a_read,
cmd7_is_a_write,
cmd7_is_valid,
cmd7_chip_addr,
cmd7_row_addr,
cmd7_bank_addr,
cmd7_multicast_req
);
localparam LOCAL_SIZE_WIDTH = 2;
localparam BUFFER_WIDTH = 1 + 1 + 1 + 1 + LOCAL_SIZE_WIDTH + MEM_IF_CHIP_BITS + MEM_IF_BA_WIDTH + MEM_IF_ROW_WIDTH + MEM_IF_COL_WIDTH;
localparam THIS_ENTRY_WIDTH = 1 + 1 + 1 + MEM_IF_CHIP_BITS + MEM_IF_BA_WIDTH + MEM_IF_ROW_WIDTH + MEM_IF_COL_WIDTH;
localparam MAX_COL = MEM_IF_COL_WIDTH;
localparam MAX_ROW = MEM_IF_ROW_WIDTH;
localparam MAX_BANK = MEM_IF_BA_WIDTH;
localparam MAX_CS = MEM_IF_CHIP_BITS;
input ctl_clk ; // controller clock
input ctl_reset_n ; // controller reset_n, synchronous to ctl_clk
input read_req_to_cmd_queue ;
input write_req_to_cmd_queue ;
input [LOCAL_SIZE_WIDTH-1:0] local_size ;
input local_autopch_req ;
input local_multicast ;
input [MEM_IF_CHIP_BITS-1:0] local_cs_addr ;
input [MEM_IF_ROW_WIDTH-1:0] local_row_addr ;
input [MEM_IF_BA_WIDTH-1:0] local_bank_addr ;
input [MEM_IF_COL_WIDTH-1:0] local_col_addr ;
output cmd_fifo_empty ;
output cmd_fifo_full ;
output cmd_fifo_wren ;
//input from State Machine
input fetch;
output cmd0_is_valid;
output cmd0_is_a_read;
output cmd0_is_a_write;
output cmd0_autopch_req;
output [LOCAL_SIZE_WIDTH-1:0] cmd0_burstcount;
output [MEM_IF_CHIP_BITS-1:0] cmd0_chip_addr;
output [MEM_IF_ROW_WIDTH-1:0] cmd0_row_addr;
output [MEM_IF_BA_WIDTH-1:0] cmd0_bank_addr;
output [MEM_IF_COL_WIDTH-1:0] cmd0_col_addr;
output cmd0_multicast_req;
output cmd1_is_valid;
output cmd1_is_a_read;
output cmd1_is_a_write;
output [MEM_IF_CHIP_BITS-1:0] cmd1_chip_addr;
output [MEM_IF_ROW_WIDTH-1:0] cmd1_row_addr;
output [MEM_IF_BA_WIDTH-1:0] cmd1_bank_addr;
output cmd1_multicast_req;
output cmd2_is_valid;
output cmd2_is_a_read;
output cmd2_is_a_write;
output [MEM_IF_CHIP_BITS-1:0] cmd2_chip_addr;
output [MEM_IF_ROW_WIDTH-1:0] cmd2_row_addr;
output [MEM_IF_BA_WIDTH-1:0] cmd2_bank_addr;
output cmd2_multicast_req;
output cmd3_is_valid;
output cmd3_is_a_read;
output cmd3_is_a_write;
output [MEM_IF_CHIP_BITS-1:0] cmd3_chip_addr;
output [MEM_IF_ROW_WIDTH-1:0] cmd3_row_addr;
output [MEM_IF_BA_WIDTH-1:0] cmd3_bank_addr;
output cmd3_multicast_req;
output cmd4_is_a_read;
output cmd4_is_a_write;
output cmd4_is_valid;
output [MEM_IF_CHIP_BITS-1:0] cmd4_chip_addr;
output [MEM_IF_ROW_WIDTH-1:0] cmd4_row_addr;
output [MEM_IF_BA_WIDTH-1:0] cmd4_bank_addr;
output cmd4_multicast_req;
output cmd5_is_a_read;
output cmd5_is_a_write;
output cmd5_is_valid;
output [MEM_IF_CHIP_BITS-1:0] cmd5_chip_addr;
output [MEM_IF_ROW_WIDTH-1:0] cmd5_row_addr;
output [MEM_IF_BA_WIDTH-1:0] cmd5_bank_addr;
output cmd5_multicast_req;
output cmd6_is_a_read;
output cmd6_is_a_write;
output cmd6_is_valid;
output [MEM_IF_CHIP_BITS-1:0] cmd6_chip_addr;
output [MEM_IF_ROW_WIDTH-1:0] cmd6_row_addr;
output [MEM_IF_BA_WIDTH-1:0] cmd6_bank_addr;
output cmd6_multicast_req;
output cmd7_is_a_read;
output cmd7_is_a_write;
output cmd7_is_valid;
output [MEM_IF_CHIP_BITS-1:0] cmd7_chip_addr;
output [MEM_IF_ROW_WIDTH-1:0] cmd7_row_addr;
output [MEM_IF_BA_WIDTH-1:0] cmd7_bank_addr;
output cmd7_multicast_req;
integer n;
integer j;
integer k;
integer m;
reg [BUFFER_WIDTH-1:0] pipe[CTL_CMD_QUEUE_DEPTH-1:0];
reg pipefull[CTL_CMD_QUEUE_DEPTH-1:0];
reg [LOCAL_SIZE_WIDTH-1:0] last_size;
reg last_read_req;
reg last_write_req;
reg last_multicast;
reg [MEM_IF_CHIP_BITS-1:0] last_chip_addr;
reg [MEM_IF_ROW_WIDTH-1:0] last_row_addr;
reg [MEM_IF_BA_WIDTH-1:0] last_bank_addr;
reg [MEM_IF_COL_WIDTH-1:0] last_col_addr;
reg [LOCAL_SIZE_WIDTH-1:0] last2_size;
reg last2_read_req;
reg last2_write_req;
reg last2_multicast;
reg [MEM_IF_CHIP_BITS-1:0] last2_chip_addr;
reg [MEM_IF_ROW_WIDTH-1:0] last2_row_addr;
reg [MEM_IF_BA_WIDTH-1:0] last2_bank_addr;
reg [MEM_IF_COL_WIDTH-1:0] last2_col_addr;
wire [MEM_IF_CHIP_BITS-1:0] cs_addr ;
wire [MEM_IF_ROW_WIDTH-1:0] row_addr ;
wire [MEM_IF_BA_WIDTH-1:0] bank_addr;
wire [MEM_IF_COL_WIDTH-1:0] col_addr ;
wire read_req_to_cmd_queue ;
wire write_req_to_cmd_queue ;
wire local_autopch_req ;
wire local_multicast;
wire local_multicast_gated;
wire [LOCAL_SIZE_WIDTH-1:0] local_size;
wire fetch;
wire [BUFFER_WIDTH-1:0] buffer_input;
wire wreq_to_fifo;
wire [MEM_IF_CHIP_BITS-1:0] pipe_chip_addr [CTL_CMD_QUEUE_DEPTH-1:0];
wire [MEM_IF_ROW_WIDTH-1:0] pipe_row_addr [CTL_CMD_QUEUE_DEPTH-1:0];
wire [MEM_IF_BA_WIDTH-1:0] pipe_bank_addr [CTL_CMD_QUEUE_DEPTH-1:0];
wire [MEM_IF_COL_WIDTH-1:0] pipe_col_addr [CTL_CMD_QUEUE_DEPTH-1:0];
wire pipe_read_req [CTL_CMD_QUEUE_DEPTH-1:0];
wire pipe_write_req [CTL_CMD_QUEUE_DEPTH-1:0];
wire pipe_autopch_req [CTL_CMD_QUEUE_DEPTH-1:0];
wire pipe_multicast_req [CTL_CMD_QUEUE_DEPTH-1:0];
wire [LOCAL_SIZE_WIDTH-1:0] pipe_burstcount [CTL_CMD_QUEUE_DEPTH-1:0];
reg [log2(CTL_CMD_QUEUE_DEPTH)-1:0] last;
reg [log2(CTL_CMD_QUEUE_DEPTH)-1:0] last_minus_one;
reg [log2(CTL_CMD_QUEUE_DEPTH)-1:0] last_minus_two;
wire can_merge;
wire cmd_fifo_wren;
wire cmd0_is_valid;
wire cmd0_is_a_read;
wire cmd0_is_a_write;
wire cmd0_autopch_req;
wire [LOCAL_SIZE_WIDTH-1:0] cmd0_burstcount;
wire [MEM_IF_CHIP_BITS-1:0] cmd0_chip_addr;
wire [MEM_IF_ROW_WIDTH-1:0] cmd0_row_addr;
wire [MEM_IF_BA_WIDTH-1:0] cmd0_bank_addr;
wire [MEM_IF_COL_WIDTH-1:0] cmd0_col_addr;
wire cmd0_multicast_req;
wire cmd1_is_valid;
wire cmd1_is_a_read;
wire cmd1_is_a_write;
wire [MEM_IF_CHIP_BITS-1:0] cmd1_chip_addr;
wire [MEM_IF_ROW_WIDTH-1:0] cmd1_row_addr;
wire [MEM_IF_BA_WIDTH-1:0] cmd1_bank_addr;
wire cmd1_multicast_req;
wire cmd2_is_valid;
wire cmd2_is_a_read;
wire cmd2_is_a_write;
wire [MEM_IF_CHIP_BITS-1:0] cmd2_chip_addr;
wire [MEM_IF_ROW_WIDTH-1:0] cmd2_row_addr;
wire [MEM_IF_BA_WIDTH-1:0] cmd2_bank_addr;
wire cmd2_multicast_req;
wire cmd3_is_valid;
wire cmd3_is_a_read;
wire cmd3_is_a_write;
wire [MEM_IF_CHIP_BITS-1:0] cmd3_chip_addr;
wire [MEM_IF_ROW_WIDTH-1:0] cmd3_row_addr;
wire [MEM_IF_BA_WIDTH-1:0] cmd3_bank_addr;
wire cmd3_multicast_req;
wire cmd4_is_a_read;
wire cmd4_is_a_write;
wire cmd4_is_valid;
wire [MEM_IF_CHIP_BITS-1:0] cmd4_chip_addr;
wire [MEM_IF_ROW_WIDTH-1:0] cmd4_row_addr;
wire [MEM_IF_BA_WIDTH-1:0] cmd4_bank_addr;
wire cmd4_multicast_req;
wire cmd5_is_a_read;
wire cmd5_is_a_write;
wire cmd5_is_valid;
wire [MEM_IF_CHIP_BITS-1:0] cmd5_chip_addr;
wire [MEM_IF_ROW_WIDTH-1:0] cmd5_row_addr;
wire [MEM_IF_BA_WIDTH-1:0] cmd5_bank_addr;
wire cmd5_multicast_req;
wire cmd6_is_a_read;
wire cmd6_is_a_write;
wire cmd6_is_valid;
wire [MEM_IF_CHIP_BITS-1:0] cmd6_chip_addr;
wire [MEM_IF_ROW_WIDTH-1:0] cmd6_row_addr;
wire [MEM_IF_BA_WIDTH-1:0] cmd6_bank_addr;
wire cmd6_multicast_req;
wire cmd7_is_a_read;
wire cmd7_is_a_write;
wire cmd7_is_valid;
wire [MEM_IF_CHIP_BITS-1:0] cmd7_chip_addr;
wire [MEM_IF_ROW_WIDTH-1:0] cmd7_row_addr;
wire [MEM_IF_BA_WIDTH-1:0] cmd7_bank_addr;
wire cmd7_multicast_req;
genvar i;
assign cs_addr = local_cs_addr;
assign bank_addr = local_bank_addr;
assign row_addr = local_row_addr;
assign col_addr = local_col_addr;
// gate multicast request with write request, we only support multicast write
assign local_multicast_gated = local_multicast & write_req_to_cmd_queue;
// mapping of buffer_input
assign buffer_input = {read_req_to_cmd_queue,write_req_to_cmd_queue,local_multicast_gated,local_autopch_req,local_size,cs_addr,row_addr,bank_addr,col_addr};
//====================== Bus to output signals mapping =======================
//pipe address
generate begin
for(i=0; i<CTL_CMD_QUEUE_DEPTH; i=i+1) begin : pipe_loop
assign pipe_read_req[i] = pipe[i][BUFFER_WIDTH-1];
assign pipe_write_req[i] = pipe[i][BUFFER_WIDTH-2];
assign pipe_multicast_req[i] = pipe[i][BUFFER_WIDTH-3];
assign pipe_autopch_req[i] = pipe[i][BUFFER_WIDTH-4];
assign pipe_burstcount[i] = pipe[i][LOCAL_SIZE_WIDTH + MEM_IF_CHIP_BITS + MEM_IF_ROW_WIDTH + MEM_IF_BA_WIDTH + MEM_IF_COL_WIDTH - 1 : MEM_IF_CHIP_BITS + MEM_IF_ROW_WIDTH + MEM_IF_BA_WIDTH + MEM_IF_COL_WIDTH];
assign pipe_chip_addr[i] = pipe[i][MEM_IF_CHIP_BITS + MEM_IF_ROW_WIDTH + MEM_IF_BA_WIDTH + MEM_IF_COL_WIDTH - 1 : MEM_IF_ROW_WIDTH + MEM_IF_BA_WIDTH + MEM_IF_COL_WIDTH];
assign pipe_row_addr[i] = pipe[i][MEM_IF_ROW_WIDTH + MEM_IF_BA_WIDTH + MEM_IF_COL_WIDTH - 1 : MEM_IF_BA_WIDTH + MEM_IF_COL_WIDTH];
assign pipe_bank_addr[i] = pipe[i][MEM_IF_BA_WIDTH + MEM_IF_COL_WIDTH - 1 : MEM_IF_COL_WIDTH];
assign pipe_col_addr[i] = pipe[i][MEM_IF_COL_WIDTH - 1 : 0];
end
end
endgenerate
assign cmd0_is_valid = pipefull[0];
assign cmd0_is_a_read = pipe_read_req [0];
assign cmd0_is_a_write = pipe_write_req [0];
assign cmd0_autopch_req = pipe_autopch_req[0];
assign cmd0_burstcount = pipe_burstcount [0];
assign cmd0_chip_addr = pipe_chip_addr [0];
assign cmd0_row_addr = pipe_row_addr [0];
assign cmd0_bank_addr = pipe_bank_addr [0];
assign cmd0_col_addr = pipe_col_addr [0];
assign cmd0_multicast_req = pipe_multicast_req [0];
generate
if (CTL_LOOK_AHEAD_DEPTH > 0)
begin
assign cmd1_is_valid = pipefull[1];
assign cmd1_is_a_read = pipe_read_req [1];
assign cmd1_is_a_write = pipe_write_req [1];
assign cmd1_chip_addr = pipe_chip_addr [1];
assign cmd1_row_addr = pipe_row_addr [1];
assign cmd1_bank_addr = pipe_bank_addr [1];
assign cmd1_multicast_req = pipe_multicast_req [1];
end
else
begin
assign cmd1_is_valid = 0;
assign cmd1_is_a_read = 0;
assign cmd1_is_a_write = 0;
assign cmd1_chip_addr = 0;
assign cmd1_row_addr = 0;
assign cmd1_bank_addr = 0;
assign cmd1_multicast_req = 0;
end
endgenerate
generate
if (CTL_LOOK_AHEAD_DEPTH > 2)
begin
assign cmd2_is_valid = pipefull[2];
assign cmd2_is_a_read = pipe_read_req [2];
assign cmd2_is_a_write = pipe_write_req [2];
assign cmd2_chip_addr = pipe_chip_addr [2];
assign cmd2_row_addr = pipe_row_addr [2];
assign cmd2_bank_addr = pipe_bank_addr [2];
assign cmd2_multicast_req = pipe_multicast_req [2];
assign cmd3_is_valid = pipefull[3];
assign cmd3_is_a_read = pipe_read_req [3];
assign cmd3_is_a_write = pipe_write_req [3];
assign cmd3_chip_addr = pipe_chip_addr [3];
assign cmd3_row_addr = pipe_row_addr [3];
assign cmd3_bank_addr = pipe_bank_addr [3];
assign cmd3_multicast_req = pipe_multicast_req [3];
end
else
begin
assign cmd2_is_valid = 0;
assign cmd2_is_a_read = 0;
assign cmd2_is_a_write = 0;
assign cmd2_chip_addr = 0;
assign cmd2_row_addr = 0;
assign cmd2_bank_addr = 0;
assign cmd2_multicast_req = 0;
assign cmd3_is_valid = 0;
assign cmd3_is_a_read = 0;
assign cmd3_is_a_write = 0;
assign cmd3_chip_addr = 0;
assign cmd3_row_addr = 0;
assign cmd3_bank_addr = 0;
assign cmd3_multicast_req = 0;
end
endgenerate
generate
if (CTL_LOOK_AHEAD_DEPTH > 4)
begin
assign cmd4_is_valid = pipefull[4];
assign cmd4_is_a_read = pipe_read_req [4];
assign cmd4_is_a_write = pipe_write_req[4];
assign cmd4_chip_addr = pipe_chip_addr[4];
assign cmd4_row_addr = pipe_row_addr [4];
assign cmd4_bank_addr = pipe_bank_addr[4];
assign cmd4_multicast_req = pipe_multicast_req [4];
assign cmd5_is_valid = pipefull[5];
assign cmd5_is_a_read = pipe_read_req [5];
assign cmd5_is_a_write = pipe_write_req[5];
assign cmd5_chip_addr = pipe_chip_addr[5];
assign cmd5_row_addr = pipe_row_addr [5];
assign cmd5_bank_addr = pipe_bank_addr[5];
assign cmd5_multicast_req = pipe_multicast_req [5];
end
else
begin
assign cmd4_is_valid = 0;
assign cmd4_is_a_read = 0;
assign cmd4_is_a_write = 0;
assign cmd4_chip_addr = 0;
assign cmd4_row_addr = 0;
assign cmd4_bank_addr = 0;
assign cmd4_multicast_req = 0;
assign cmd5_is_valid = 0;
assign cmd5_is_a_read = 0;
assign cmd5_is_a_write = 0;
assign cmd5_chip_addr = 0;
assign cmd5_row_addr = 0;
assign cmd5_bank_addr = 0;
assign cmd5_multicast_req = 0;
end
endgenerate
generate
if (CTL_LOOK_AHEAD_DEPTH > 6)
begin
assign cmd6_is_valid = pipefull[6];
assign cmd6_is_a_read = pipe_read_req [6];
assign cmd6_is_a_write = pipe_write_req[6];
assign cmd6_chip_addr = pipe_chip_addr[6];
assign cmd6_row_addr = pipe_row_addr [6];
assign cmd6_bank_addr = pipe_bank_addr[6];
assign cmd6_multicast_req = pipe_multicast_req [6];
assign cmd7_is_valid = pipefull[7];
assign cmd7_is_a_read = pipe_read_req [7];
assign cmd7_is_a_write = pipe_write_req[7];
assign cmd7_chip_addr = pipe_chip_addr[7];
assign cmd7_row_addr = pipe_row_addr [7];
assign cmd7_bank_addr = pipe_bank_addr[7];
assign cmd7_multicast_req = pipe_multicast_req [7];
end
else
begin
assign cmd6_is_valid = 0;
assign cmd6_is_a_read = 0;
assign cmd6_is_a_write = 0;
assign cmd6_chip_addr = 0;
assign cmd6_row_addr = 0;
assign cmd6_bank_addr = 0;
assign cmd6_multicast_req = 0;
assign cmd7_is_valid = 0;
assign cmd7_is_a_read = 0;
assign cmd7_is_a_write = 0;
assign cmd7_chip_addr = 0;
assign cmd7_row_addr = 0;
assign cmd7_bank_addr = 0;
assign cmd7_multicast_req = 0;
end
endgenerate
//====================== end of Bus to output signals mapping ================
//====================== sequential address detector ========================
//Last pipeline entry
always @(posedge ctl_clk or negedge ctl_reset_n) begin
if (!ctl_reset_n) begin
last_read_req <= 1'b0;
last_write_req <= 1'b0;
last_chip_addr <= {MEM_IF_CHIP_BITS{1'b0}};
last_row_addr <= {MEM_IF_ROW_WIDTH{1'b0}};
last_bank_addr <= {MEM_IF_BA_WIDTH{1'b0}};
last_col_addr <= {MEM_IF_COL_WIDTH{1'b0}};
last_size <= {LOCAL_SIZE_WIDTH{1'b0}};
last_multicast <= 1'b0;
end
else if (wreq_to_fifo) begin
last_read_req <= read_req_to_cmd_queue;
last_write_req <= write_req_to_cmd_queue;
last_multicast <= local_multicast_gated;
last_chip_addr <= cs_addr;
last_bank_addr <= bank_addr;
last_row_addr <= row_addr;
last_col_addr <= col_addr;
last_size <= local_size;
end
else if (can_merge)
last_size <= 2;
end
//Second last pipeline entry
always @(posedge ctl_clk or negedge ctl_reset_n) begin
if (!ctl_reset_n) begin
last2_read_req <= 1'b0;
last2_write_req <= 1'b0;
last2_chip_addr <= {MEM_IF_CHIP_BITS{1'b0}};
last2_row_addr <= {MEM_IF_ROW_WIDTH{1'b0}};
last2_bank_addr <= {MEM_IF_BA_WIDTH{1'b0}};
last2_col_addr <= {MEM_IF_COL_WIDTH{1'b0}};
last2_size <= {LOCAL_SIZE_WIDTH{1'b0}};
last2_multicast <= 1'b0;
end
else if (wreq_to_fifo) begin
last2_read_req <= last_read_req;
last2_write_req <= last_write_req;
last2_multicast <= last_multicast;
last2_chip_addr <= last_chip_addr;
last2_bank_addr <= last_bank_addr;
last2_row_addr <= last_row_addr;
last2_col_addr <= last_col_addr;
last2_size <= last_size;
end
end
always @(posedge ctl_clk or negedge ctl_reset_n) begin
if (!ctl_reset_n) begin
last <= 0;
last_minus_one <= 0;
last_minus_two <= 0;
end
else
if (fetch) begin // fetch and write
if (can_merge && last != 1)
begin
if (wreq_to_fifo)
begin
last <= last - 1;
last_minus_one <= last - 2;
last_minus_two <= last - 3;
end
else
begin
last <= last - 2;
last_minus_one <= last - 3;
last_minus_two <= last - 4;
end
end
else
begin
if (wreq_to_fifo) begin
// do nothing
end
else if (last != 0)
begin
last <= last - 1;
last_minus_one <= last - 2;
last_minus_two <= last - 3;
end
end
end
else if (wreq_to_fifo) begin // write only
if (can_merge)
begin
// do nothing
end
else
if (!cmd_fifo_empty)
begin
last <= last + 1;
last_minus_one <= last;
last_minus_two <= last - 1;
end
end
else if (can_merge)
begin
last <= last - 1;
last_minus_one <= last - 2;
last_minus_two <= last - 3;
end
end
assign can_merge = (ENABLE_BURST_MERGE == 1) ?
last != 0
& pipefull[last]
& last2_read_req == last_read_req
& last2_write_req == last_write_req
& last2_multicast == last_multicast
& last2_chip_addr == last_chip_addr
& last2_bank_addr == last_bank_addr
& last2_row_addr == last_row_addr
& ((DWIDTH_RATIO == 2) ? (last2_col_addr[MEM_IF_COL_WIDTH-1 : 2] == last_col_addr[MEM_IF_COL_WIDTH-1 : 2]) : (last2_col_addr[MEM_IF_COL_WIDTH-1 : 3] == last_col_addr[MEM_IF_COL_WIDTH-1 : 3]) )
& ((DWIDTH_RATIO == 2) ? (last2_col_addr[1] == 0 & last_col_addr[1] == 1) : (last2_col_addr[2] == 0 & last_col_addr[2] == 1) )
& last2_size == 1 & last_size == 1
:
1'b0;
//=================== end of sequential address detector ====================
//=============================== queue ===================================
// avalon_write_req & avalon_read_req is AND with internal_ready in alt_ddrx_avalon_if.v
assign wreq_to_fifo = (read_req_to_cmd_queue) | (write_req_to_cmd_queue);
assign cmd_fifo_wren = (read_req_to_cmd_queue) | (write_req_to_cmd_queue);
assign cmd_fifo_empty = !pipefull[0];
assign cmd_fifo_full = pipefull[CTL_CMD_QUEUE_DEPTH-1];
//pipefull and pipe register chain
//feed 0 to pipefull entry that is empty
always @(posedge ctl_clk or negedge ctl_reset_n) begin
if (!ctl_reset_n) begin
for(j=0; j<CTL_CMD_QUEUE_DEPTH; j=j+1) begin
pipefull[j] <= 1'b0;
pipe[j] <= 0;
end
end
else
if (fetch) begin // fetch and write
if (can_merge && last != 1)
begin
for(j=0; j<CTL_CMD_QUEUE_DEPTH-1; j=j+1) begin
if(pipefull[j] == 1'b1 & pipefull[j+1] == 1'b0) begin
pipefull[j] <= 1'b0;
end
else if (j == last_minus_one) begin
pipefull[j] <= wreq_to_fifo;
pipe[j] <= buffer_input;
end
else if (j == last_minus_two) begin
pipe[j] <= {pipe[j+1][BUFFER_WIDTH-1:BUFFER_WIDTH-4],2'd2,pipe[j+1][BUFFER_WIDTH-7:0]};
end
else begin
pipefull[j] <= pipefull[j+1];
pipe[j] <= pipe[j+1];
end
end
pipefull[CTL_CMD_QUEUE_DEPTH-1] <= 1'b0;
pipe[CTL_CMD_QUEUE_DEPTH-1] <= pipe[CTL_CMD_QUEUE_DEPTH-1] & buffer_input;
end
else
begin
for(j=0; j<CTL_CMD_QUEUE_DEPTH-1; j=j+1) begin
if(pipefull[j] == 1'b1 & pipefull[j+1] == 1'b0) begin
pipefull[j] <= wreq_to_fifo;
pipe[j] <= buffer_input;
end
else begin
pipefull[j] <= pipefull[j+1];
pipe[j] <= pipe[j+1];
end
end
pipefull[CTL_CMD_QUEUE_DEPTH-1] <= pipefull[CTL_CMD_QUEUE_DEPTH-1] & wreq_to_fifo;
pipe[CTL_CMD_QUEUE_DEPTH-1] <= pipe[CTL_CMD_QUEUE_DEPTH-1] & buffer_input;
end
end
else if (wreq_to_fifo) begin // write only
if (can_merge)
begin
pipe[last] <= buffer_input;
pipe[last_minus_one][LOCAL_SIZE_WIDTH + MEM_IF_CHIP_BITS + MEM_IF_ROW_WIDTH + MEM_IF_BA_WIDTH + MEM_IF_COL_WIDTH - 1 : MEM_IF_CHIP_BITS + MEM_IF_ROW_WIDTH + MEM_IF_BA_WIDTH + MEM_IF_COL_WIDTH] <= 2;
end
else
begin
for(j=1; j<CTL_CMD_QUEUE_DEPTH; j=j+1) begin
if(pipefull[j-1] == 1'b1 & pipefull[j] == 1'b0) begin
pipefull[j] <= 1'b1;
pipe[j] <= buffer_input;
end
end
if(pipefull[0] == 1'b0) begin
pipefull[0] <= 1'b1;
pipe[0] <= buffer_input;
end
end
end
else if (can_merge)
begin
for(j=0; j<CTL_CMD_QUEUE_DEPTH-1; j=j+1) begin
if(pipefull[j] == 1'b1 & pipefull[j+1] == 1'b0)
pipefull[j] <= 1'b0;
else
pipefull[j] <= pipefull[j+1];
end
pipefull[CTL_CMD_QUEUE_DEPTH-1] <= 1'b0;
pipe[last_minus_one][LOCAL_SIZE_WIDTH + MEM_IF_CHIP_BITS + MEM_IF_ROW_WIDTH + MEM_IF_BA_WIDTH + MEM_IF_COL_WIDTH - 1 : MEM_IF_CHIP_BITS + MEM_IF_ROW_WIDTH + MEM_IF_BA_WIDTH + MEM_IF_COL_WIDTH] <= 2;
end
end
//============================ end of queue ===============================
function integer log2; //constant function
input integer value;
begin
for (log2=0; value>0; log2=log2+1)
value = value>>1;
log2 = log2 - 1;
end
endfunction
endmodule
|
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_asinpi_s5 (
enable,
clock,
dataa,
result);
input enable;
input clock;
input [31:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
fp_arcsinpi_s5 inst (
.en (enable),
.areset(1'b0),
.clk(clock),
.a(dataa),
.q(sub_wire0));
endmodule
|
`timescale 1ns / 1ps
`include "zpu_core_defines.v"
/* MODULE: zpu_core
DESCRIPTION: Contains ZPU cpu
AUTHOR: Antonio J. Anton (aj <at> anro-ingenieros.com)
REVISION HISTORY:
Revision 1.0, 14/09/2009
Initial public release
COPYRIGHT:
Copyright (c) 2009 Antonio J. Anton
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.*/
// --------- MICROPROGRAMMED ZPU CORE ---------------
// all signals are polled on clk rising edge
// all signals positive
module zpu_core (
`ifdef ENABLE_CPU_INTERRUPTS
interrupt, // interrupt request
`endif
clk, // clock on rising edge
reset, // reset on rising edge
mem_read, // request memory read
mem_write, // request memory write
mem_done, // memory operation completed
mem_addr, // memory address
mem_data_read, // data readed
mem_data_write, // data written
byte_select // byte select on memory operation
);
input clk;
input reset;
output mem_read;
output mem_write;
input mem_done;
input [31:0] mem_data_read;
output [31:0] mem_data_write;
output [31:0] mem_addr;
output [3:0] byte_select;
`ifdef ENABLE_CPU_INTERRUPTS
input interrupt;
`endif
wire clk;
wire reset;
wire mem_read;
wire mem_write;
wire mem_done;
wire [31:0] mem_data_read;
wire [31:0] mem_data_write;
wire [31:0] mem_addr;
`ifdef ENABLE_CPU_INTERRUPTS
wire interrupt;
`endif
`ifdef ENABLE_BYTE_SELECT
// ------ unaligned byte/halfword memory operations -----
/// TODO: think rewriting into microcode or in a less resource wasting way
reg [3:0] byte_select;
wire byte_op;
wire halfw_op;
reg [31:0] mem_data_read_int; // aligned data from memory
reg [31:0] mem_data_write_out; // write data already aligned
wire [31:0] mem_data_write_int; // write data from cpu to be aligned
// --- byte select logic ---
always @(mem_addr[1:0] or byte_op or halfw_op)
begin
casez( { mem_addr[1:0], byte_op, halfw_op } )
4'b00_1_? : byte_select <= 4'b0001; // byte select
4'b01_1_? : byte_select <= 4'b0010;
4'b10_1_? : byte_select <= 4'b0100;
4'b11_1_? : byte_select <= 4'b1000;
4'b0?_0_1 : byte_select <= 4'b0011; // half word select
4'b1?_0_1 : byte_select <= 4'b1100;
default : byte_select <= 4'b1111; // word select
endcase
end
// --- input data to cpu ---
always @(mem_data_read or mem_addr[1:0] or byte_op or halfw_op)
begin
casez( { mem_addr[1:0], byte_op, halfw_op } )
4'b00_1_? : mem_data_read_int <= { 24'b0, mem_data_read[7:0] }; // 8 bit read
4'b01_1_? : mem_data_read_int <= { 24'b0, mem_data_read[15:8] };
4'b10_1_? : mem_data_read_int <= { 24'b0, mem_data_read[23:16] };
4'b11_1_? : mem_data_read_int <= { 24'b0, mem_data_read[31:24] };
4'b0?_0_1 : mem_data_read_int <= { 16'b0, mem_data_read[7:0], mem_data_read[15:8] }; // 16 bit read
4'b1?_0_1 : mem_data_read_int <= { 16'b0, mem_data_read[23:16], mem_data_read[31:24] };
default : mem_data_read_int <= { mem_data_read[7:0], mem_data_read[15:8], mem_data_read[23:16], mem_data_read[31:24] }; // 32 bit access (default)
endcase
end
// --- output data from cpu ---
assign mem_data_write = mem_data_write_out;
always @(mem_data_write_int or mem_addr[1:0] or byte_op or halfw_op)
begin
casez( {mem_addr[1:0], byte_op, halfw_op } )
4'b00_1_? : mem_data_write_out <= { 24'bX, mem_data_write_int[7:0] }; // 8 bit write
4'b01_1_? : mem_data_write_out <= { 16'bX, mem_data_write_int[7:0], 8'bX };
4'b10_1_? : mem_data_write_out <= { 8'bX, mem_data_write_int[7:0], 16'bX };
4'b11_1_? : mem_data_write_out <= { mem_data_write_int[7:0], 24'bX };
4'b0?_0_1 : mem_data_write_out <= { 16'bX, mem_data_write_int[7:0], mem_data_write_int[15:8] }; // 16 bit write
4'b1?_0_1 : mem_data_write_out <= { mem_data_write_int[7:0], mem_data_write_int[15:8], 16'bX };
default : mem_data_write_out <= { mem_data_write_int[7:0], mem_data_write_int[15:8], mem_data_write_int[23:16], mem_data_write_int[31:24] };
endcase
end
`else
// -------- only 32 bit memory access --------
wire [3:0] byte_select = 4'b1111; // all memory operations are 32 bit wide
wire [31:0] mem_data_read_int; // no byte/halfword memory access by HW
wire [31:0] mem_data_write_int; // byte and halfword memory access must be emulated
// ----- reorder bytes due to MSB-LSB configuration -----
assign mem_data_read_int = { mem_data_read[7:0], mem_data_read[15:8], mem_data_read[23:16], mem_data_read[31:24] };
assign mem_data_write = { mem_data_write_int[7:0], mem_data_write_int[15:8], mem_data_write_int[23:16], mem_data_write_int[31:24] };
`endif
// ------ datapath registers and connections -----------
reg [31:0] pc; // program counter (byte align)
reg [31:0] sp; // stack counter (word align)
reg [31:0] a; // operand (address_out, data_out, alu_in)
reg [31:0] b; // operand (address_out)
reg idim; // im opcode being processed
reg [7:0] opcode; // opcode being processed
reg [31:2] pc_cached; // cached PC
reg [31:0] opcode_cache; // cached opcodes (current word)
`ifdef ENABLE_CPU_INTERRUPTS
reg int_requested; // interrupt has been requested
reg on_interrupt; // serving interrupt
wire exit_interrupt; // microcode says this is poppc_interrupt
wire enter_interrupt; // microcode says we are entering interrupt
`endif
wire [1:0] sel_opcode = pc[1:0]; // which opcode is selected
wire sel_read; // mux for data-in
wire [1:0] sel_alu; // mux for alu
wire [1:0] sel_addr; // mux for addr
wire w_pc; // write PC
`ifdef ENABLE_PC_INCREMENT
wire w_pc_increment; // write PC+1
`endif
wire w_sp; // write SP
wire w_a; // write A (from ALU result)
wire w_a_mem; // write A (from MEM read)
wire w_b; // write B
wire w_op; // write OPCODE (opcode cache)
wire set_idim; // set IDIM
wire clear_idim; // clear IDIM
wire is_op_cached = (pc[31:2] == pc_cached) ? 1'b1 : 1'b0; // is opcode available?
wire a_is_zero; // A == 0
wire a_is_neg; // A[31] == 1
wire busy; // busy signal to microcode sequencer (stalls cpu)
reg [`MC_MEM_BITS-1:0] mc_pc; // microcode PC
initial mc_pc <= `MC_ADDR_RESET-1;
wire [`MC_BITS-1:0] mc_op; // current microcode operation
// memory addr / write ports
assign mem_addr = (sel_addr == `SEL_ADDR_SP) ? sp :
(sel_addr == `SEL_ADDR_A) ? a :
(sel_addr == `SEL_ADDR_B) ? b : pc;
assign mem_data_write_int = a; // only A can be written to memory
// ------- alu instantiation -------
wire [31:0] alu_a;
wire [31:0] alu_b;
wire [31:0] alu_r;
wire [`ALU_OP_WIDTH-1:0] alu_op;
wire alu_done;
// alu inputs multiplexors
// constant in microcode is sign extended (in order to implement substractions like adds)
assign alu_a = (sel_read == `SEL_READ_DATA) ? mem_data_read_int : mem_addr;
assign alu_b = (sel_alu == `SEL_ALU_MC_CONST) ? { {25{mc_op[`P_ADDR+6]}} , mc_op[`P_ADDR+6:`P_ADDR] } : // most priority
(sel_alu == `SEL_ALU_A) ? a :
(sel_alu == `SEL_ALU_B) ? b : { {24{1'b0}} , opcode }; // `SEL_ALU_OPCODE is less priority
zpu_core_alu alu(
.alu_a(alu_a),
.alu_b(alu_b),
.alu_r(alu_r),
.alu_op(alu_op),
.flag_idim(idim),
.clk(clk),
.done(alu_done)
);
// -------- pc : program counter --------
always @(posedge clk)
begin
if(w_pc) pc <= alu_r;
`ifdef ENABLE_PC_INCREMENT // microcode optimization
else if(w_pc_increment) pc <= pc + 1; // usually pc=pc+1
`endif
end
// -------- sp : stack pointer --------
always @(posedge clk)
begin
if(w_sp) sp <= alu_r;
end
// -------- a : acumulator register ---------
always @(posedge clk)
begin
if(w_a) a <= alu_r;
else if(w_a_mem) a <= mem_data_read_int;
end
// alu results over a register instead of alu result
// in order to improve speed
assign a_is_zero = (a == 0);
assign a_is_neg = a[31];
// -------- b : auxiliary register ---------
always @(posedge clk)
begin
if(w_b) b <= alu_r;
end
// -------- opcode and opcode_cache --------
always @(posedge clk)
begin
if(w_op)
begin
opcode_cache <= alu_r; // store all opcodes in the word
pc_cached <= pc[31:2]; // store PC address of cached opcodes
end
end
// -------- opcode : based on pc[1:0] ---------
always @(sel_opcode or opcode_cache) // select current opcode from
begin // the cached opcode word
case(sel_opcode)
0 : opcode <= opcode_cache[31:24];
1 : opcode <= opcode_cache[23:16];
2 : opcode <= opcode_cache[15:8];
3 : opcode <= opcode_cache[7:0];
endcase
end
// ------- idim : immediate opcode handling ----------
always @(posedge clk)
begin
if(set_idim) idim <= 1'b1;
else if(clear_idim) idim <= 1'b0;
end
`ifdef ENABLE_CPU_INTERRUPTS
// ------ on interrupt status bit -----
always @(posedge clk)
begin
if(reset | exit_interrupt) on_interrupt <= 1'b0;
else if(enter_interrupt) on_interrupt <= 1'b1;
end
`endif
// ------ microcode execution unit --------
assign sel_read = mc_op[`P_SEL_READ]; // map datapath signals with microcode program bits
assign sel_alu = mc_op[`P_SEL_ALU+1:`P_SEL_ALU];
assign sel_addr = mc_op[`P_SEL_ADDR+1:`P_SEL_ADDR];
assign alu_op = mc_op[`P_ALU+3:`P_ALU];
assign w_sp = mc_op[`P_W_SP] & ~busy;
assign w_pc = mc_op[`P_W_PC] & ~busy;
assign w_a = mc_op[`P_W_A] & ~busy;
assign w_a_mem = mc_op[`P_W_A_MEM] & ~busy;
assign w_b = mc_op[`P_W_B] & ~busy;
assign w_op = mc_op[`P_W_OPCODE] & ~busy;
assign mem_read = mc_op[`P_MEM_R];
assign mem_write = mc_op[`P_MEM_W];
assign set_idim = mc_op[`P_SET_IDIM] & ~busy;
assign clear_idim= mc_op[`P_CLEAR_IDIM] & ~busy;
`ifdef ENABLE_BYTE_SELECT
assign byte_op = mc_op[`P_BYTE];
assign halfw_op = mc_op[`P_HALFWORD];
`endif
`ifdef ENABLE_PC_INCREMENT
assign w_pc_increment = mc_op[`P_PC_INCREMENT] & ~busy;
`endif
`ifdef ENABLE_CPU_INTERRUPTS
assign exit_interrupt = mc_op[`P_EXIT_INT] & ~busy;
assign enter_interrupt = mc_op[`P_ENTER_INT] & ~busy;
`endif
wire cond_op_not_cached = mc_op[`P_OP_NOT_CACHED]; // conditional: true if opcode not cached
wire cond_a_zero = mc_op[`P_A_ZERO]; // conditional: true if A is zero
wire cond_a_neg = mc_op[`P_A_NEG]; // conditional: true if A is negative
wire decode = mc_op[`P_DECODE]; // decode means jumps to apropiate microcode based on zpu opcode
wire branch = mc_op[`P_BRANCH]; // unconditional jump inside microcode
wire [`MC_MEM_BITS-1:0] mc_goto = { mc_op[`P_ADDR+6:`P_ADDR], 2'b00 }; // microcode goto (goto = high 7 bits)
wire [`MC_MEM_BITS-1:0] mc_entry = { opcode[6:0], 2'b00 }; // microcode entry point for opcode
reg [`MC_MEM_BITS-1:0] next_mc_pc; // next microcode operation to be executed
initial next_mc_pc <= `MC_ADDR_RESET-1;
wire cond_branch = (cond_op_not_cached & ~is_op_cached) | // sum of all conditionals
(cond_a_zero & a_is_zero) |
(cond_a_neg & a_is_neg);
assign busy = ((mem_read | mem_write) & ~mem_done) | ~alu_done; // busy signal for microcode sequencer
// ------- handle interrupts ---------
`ifdef ENABLE_CPU_INTERRUPTS
always @(posedge clk)
begin
if(reset | on_interrupt) int_requested <= 0;
else if(interrupt & ~on_interrupt & ~int_requested) int_requested <= 1; // interrupt requested
end
`endif
// ----- calculate next microcode address (next, decode, branch, specific opcode, etc.) -----
always @(reset or mc_pc or mc_goto or opcode[7:4] or idim or
decode or branch or cond_branch or mc_entry or busy
`ifdef ENABLE_CPU_INTERRUPTS
or int_requested
`endif
)
begin
// default, next microcode instruction
next_mc_pc <= mc_pc + 1;
if(reset) next_mc_pc <= `MC_ADDR_RESET;
else if(~busy)
begin
// get next microcode instruction
if(branch | cond_branch) next_mc_pc <= mc_goto;
else if(decode) // decode: entry point of a new zpu opcode
begin
`ifdef ENABLE_CPU_INTERRUPTS
if(int_requested & ~idim) next_mc_pc <= `MC_ADDR_INTERRUPT; // microde to enter interrupt mode
else
`endif
if(opcode[7] == `OP_IM) next_mc_pc <= (idim ? `MC_ADDR_IM_IDIM : `MC_ADDR_IM_NOIDIM);
else if(opcode[7:5] == `OP_STORESP) next_mc_pc <= `MC_ADDR_STORESP;
else if(opcode[7:5] == `OP_LOADSP) next_mc_pc <= `MC_ADDR_LOADSP;
else if(opcode[7:4] == `OP_ADDSP) next_mc_pc <= `MC_ADDR_ADDSP;
else next_mc_pc <= mc_entry; // includes EMULATE opcodes
end
end
else next_mc_pc <= mc_pc; // in case of cpu stalled (busy=1)
end
// set microcode program counter
always @(posedge clk) mc_pc <= next_mc_pc;
// ----- microcode program ------
zpu_core_rom microcode (
.addr(next_mc_pc),
.data(mc_op),
.clk(clk)
);
// -------------- ZPU debugger --------------------
`ifdef ZPU_CORE_DEBUG
//synthesis translate_off
// ---- register operation dump ----
always @(posedge clk)
begin
if(~reset)
begin
if(w_pc) $display("zpu_core: set PC=0x%h", alu.alu_r);
`ifdef ENABLE_PC_INCREMENT
if(w_pc_increment) $display("zpu_core: set PC=0x%h (PC+1)", pc);
`endif
if(w_sp) $display("zpu_core: set SP=0x%h", alu.alu_r);
if(w_a) $display("zpu_core: set A=0x%h", alu.alu_r);
if(w_a_mem) $display("zpu_core: set A=0x%h (from MEM)", mem_data_read_int);
if(w_b) $display("zpu_core: set B=0x%h", alu.alu_r);
if(w_op & ~is_op_cached) $display("zpu_core: set opcode_cache=0x%h, pc_cached=0x%h", alu.alu_r, {pc[31:2], 2'b0});
`ifdef ENABLE_CPU_INTERRUPTS
if(~busy & mc_pc == `MC_ADDR_INTERRUPT) $display("zpu_core: ***** ENTERING INTERRUPT MICROCODE ******");
if(~busy & exit_interrupt) $display("zpu_core: ***** INTERRUPT FLAG CLEARED *****");
if(~busy & enter_interrupt) $display("zpu_core: ***** INTERRUPT FLAG SET *****");
`endif
if(set_idim & ~idim) $display("zpu_core: IDIM=1");
if(clear_idim & idim) $display("zpu_core: IDIM=0");
// ---- microcode debug ----
`ifdef ZPU_CORE_DEBUG_MICROCODE
if(~busy)
begin
$display("zpu_core: mc_op[%d]=0b%b", mc_pc, mc_op);
if(branch) $display("zpu_core: microcode: branch=%d", mc_goto);
if(cond_branch) $display("zpu_core: microcode: CONDITION branch=%d", mc_goto);
if(decode) $display("zpu_core: decoding opcode=0x%h (0b%b) : branch to=%d ", opcode, opcode, mc_entry);
end
else $display("zpu_core: busy");
`endif
// ---- cpu abort in case of unaligned memory access ---
`ifdef ASSERT_NON_ALIGNMENT
/* unaligned word access (except PC) */
if(sel_addr != `SEL_ADDR_PC & mem_addr[1:0] != 2'b00 & (mem_read | mem_write) & !byte_op & !halfw_op)
begin
$display("zpu_core: unaligned word operation at addr=0x%x", mem_addr);
$finish;
end
/* unaligned halfword access */
if(mem_addr[0] & (mem_read | mem_write) & !byte_op & halfw_op)
begin
$display("zpu_core: unaligned halfword operation at addr=0x%x", mem_addr);
$finish;
end
`endif
end
end
// ----- opcode dissasembler ------
always @(posedge clk)
begin
if(~busy)
case(mc_pc)
0 : begin
$display("zpu_core: ------ breakpoint ------");
$finish;
end
4 : $display("zpu_core: ------ shiftleft ------");
8 : $display("zpu_core: ------ pushsp ------");
12 : $display("zpu_core: ------ popint ------");
16 : $display("zpu_core: ------ poppc ------");
20 : $display("zpu_core: ------ add ------");
24 : $display("zpu_core: ------ and ------");
28 : $display("zpu_core: ------ or ------");
32 : $display("zpu_core: ------ load ------");
36 : $display("zpu_core: ------ not ------");
40 : $display("zpu_core: ------ flip ------");
44 : $display("zpu_core: ------ nop ------");
48 : $display("zpu_core: ------ store ------");
52 : $display("zpu_core: ------ popsp ------");
56 : $display("zpu_core: ------ ipsum ------");
60 : $display("zpu_core: ------ sncpy ------");
`MC_ADDR_IM_NOIDIM : $display("zpu_core: ------ im 0x%h (1st) ------", opcode[6:0] );
`MC_ADDR_IM_IDIM : $display("zpu_core: ------ im 0x%h (cont) ------", opcode[6:0] );
`MC_ADDR_STORESP : $display("zpu_core: ------ storesp 0x%h ------", { ~opcode[4], opcode[3:0], 2'b0 } );
`MC_ADDR_LOADSP : $display("zpu_core: ------ loadsp 0x%h ------", { ~opcode[4], opcode[3:0], 2'b0 } );
`MC_ADDR_ADDSP : $display("zpu_core: ------ addsp 0x%h ------", { ~opcode[4], opcode[3:0], 2'b0 } );
`MC_ADDR_EMULATE : $display("zpu_core: ------ emulate 0x%h ------", b[2:0]); // opcode[5:0] );
128 : $display("zpu_core: ------ mcpy ------");
132 : $display("zpu_core: ------ mset ------");
136 : $display("zpu_core: ------ loadh ------");
140 : $display("zpu_core: ------ storeh ------");
144 : $display("zpu_core: ------ lessthan ------");
148 : $display("zpu_core: ------ lessthanorequal ------");
152 : $display("zpu_core: ------ ulessthan ------");
156 : $display("zpu_core: ------ ulessthanorequal ------");
160 : $display("zpu_core: ------ swap ------");
164 : $display("zpu_core: ------ mult ------");
168 : $display("zpu_core: ------ lshiftright ------");
172 : $display("zpu_core: ------ ashiftleft ------");
176 : $display("zpu_core: ------ ashiftright ------");
180 : $display("zpu_core: ------ call ------");
184 : $display("zpu_core: ------ eq ------");
188 : $display("zpu_core: ------ neq ------");
192 : $display("zpu_core: ------ neg ------");
196 : $display("zpu_core: ------ sub ------");
200 : $display("zpu_core: ------ xor ------");
204 : $display("zpu_core: ------ loadb ------");
208 : $display("zpu_core: ------ storeb ------");
212 : $display("zpu_core: ------ div ------");
216 : $display("zpu_core: ------ mod ------");
220 : $display("zpu_core: ------ eqbranch ------");
224 : $display("zpu_core: ------ neqbranch ------");
228 : $display("zpu_core: ------ poppcrel ------");
232 : $display("zpu_core: ------ config ------");
236 : $display("zpu_core: ------ pushpc ------");
240 : $display("zpu_core: ------ syscall_emulate ------");
244 : $display("zpu_core: ------ pushspadd ------");
248 : $display("zpu_core: ------ halfmult ------");
252 : $display("zpu_core: ------ callpcrel ------");
//default : $display("zpu_core: mc_pc=0x%h", decode_mcpc);
endcase
end
//synthesis translate_on
`endif
endmodule
// --------- ZPU CORE ALU UNIT ---------------
module zpu_core_alu(
alu_a, // parameter A
alu_b, // parameter B
alu_r, // computed result
flag_idim, // for IMM alu op
alu_op, // ALU operation
clk, // clock for syncronous multicycle operations
done // done signal for alu operation
);
input [31:0] alu_a;
input [31:0] alu_b;
input [`ALU_OP_WIDTH-1:0] alu_op;
input flag_idim;
output [31:0] alu_r;
input clk;
output done;
wire [31:0] alu_a;
wire [31:0] alu_b;
wire [`ALU_OP_WIDTH-1:0] alu_op;
wire flag_idim;
reg [31:0] alu_r;
wire clk;
reg done;
`ifdef ENABLE_MULT
// implement 32 bit pipeline multiplier
reg mul_running;
reg [2:0] mul_counter;
wire mul_done = (mul_counter == 3);
reg [31:0] mul_result, mul_tmp1;
reg [31:0] a_in, b_in;
always@(posedge clk)
begin
a_in <= 0;
b_in <= 0;
mul_tmp1 <= 0;
mul_result <= 0;
mul_counter <= 0;
if(mul_running)
begin // infer pipeline multiplier
a_in <= alu_a;
b_in <= alu_b;
mul_tmp1 <= a_in * b_in;
mul_result <= mul_tmp1;
mul_counter <= mul_counter + 1;
end
end
`endif
`ifdef ENABLE_DIV
// implement 32 bit divider
// Unsigned/Signed division based on Patterson and Hennessy's algorithm.
// Description: Calculates quotient. The "sign" input determines whether
// signs (two's complement) should be taken into consideration.
// references: http://www.ece.lsu.edu/ee3755/2002/l07.html
reg [63:0] qr;
wire [33:0] diff;
wire [31:0] quotient;
wire [31:0] dividend;
wire [31:0] divider;
reg [6:0] bit;
wire div_done;
reg div_running;
reg divide_sign;
reg negative_output;
assign div_done = !bit;
assign diff = qr[63:31] - {1'b0, divider};
assign quotient = (!negative_output) ? qr[31:0] : ~qr[31:0] + 1'b1;
assign dividend = (!divide_sign || !alu_a[31]) ? alu_a : ~alu_a + 1'b1;
assign divider = (!divide_sign || !alu_b[31]) ? alu_b : ~alu_b + 1'b1;
always@(posedge clk)
begin
bit <= 7'b1_000000; // divider stopped
if(div_running)
begin
if(bit[6]) // divider started: initialize registers
begin
bit <= 7'd32;
qr <= { 32'd0, dividend };
negative_output <= divide_sign && ((alu_b[31] && !alu_a[31]) || (!alu_b[31] && alu_a[31]));
end
else // step by step divide
begin
if( diff[32] ) qr <= { qr[62:0], 1'd0 };
else qr <= { diff[31:0], qr[30:0], 1'd1 };
bit <= bit - 1;
end
end
end
`endif
`ifdef ENABLE_BARREL
// implement 32 bit barrel shift
// alu_b[6] == 1 ? left(only arithmetic) : right
// alu_b[5] == 1 ? logical : arithmetic
reg bs_running;
reg [31:0] bs_result;
reg [4:0] bs_counter; // 5 bits
wire bs_left = alu_b[6];
wire bs_logical = alu_b[5];
wire [4:0] bs_moves = alu_b[4:0];
wire bs_done = (bs_counter == bs_moves);
always @(posedge clk)
begin
bs_counter <= 0;
bs_result <= alu_a;
if(bs_running)
begin
if(bs_left) bs_result <= { bs_result[30:0], 1'b0 }; // shift left
else
begin
if(bs_logical) bs_result <= { 1'b0, bs_result[31:1] }; // shift logical right
else bs_result <= { bs_result[31], bs_result[31], bs_result[30:1] };// shift arithmetic right
end
bs_counter <= bs_counter + 1;
end
end
`endif
// ----- alu add/sub -----
reg [31:0] alu_b_tmp;
always @(alu_b or alu_op)
begin
alu_b_tmp <= alu_b; // by default, ALU_B as is
if(alu_op == `ALU_PLUS_OFFSET) alu_b_tmp <= { {25{1'b0}}, ~alu_b[4], alu_b[3:0], 2'b0 }; // ALU_B is an offset if ALU_PLUS_OFFSET operation
end
reg [31:0] alu_r_addsub; // compute R=A+B or A-B based on opcode (ALU_PLUSxx / ALU_SUB-CMP)
always @(alu_a or alu_b_tmp or alu_op)
begin
`ifdef ENABLE_CMP
if(alu_op == `ALU_CMP_SIGNED || alu_op == `ALU_CMP_UNSIGNED) // in case of sub or cmp --> operation is '-'
begin
alu_r_addsub <= alu_a - alu_b_tmp;
end
else
`endif
begin
alu_r_addsub <= alu_a + alu_b_tmp; // by default '+' operation
end
end
`ifdef ENABLE_CMP
// handle overflow/underflow exceptions in ALU_CMP_SIGNED
reg cmp_exception;
always @(alu_a[31] or alu_b[31] or alu_r_addsub[31])
begin
cmp_exception <= 0;
if( (alu_a[31] == 0 && alu_b[31] == 1 && alu_r_addsub[31] == 1) ||
(alu_a[31] == 1 && alu_b[31] == 0 && alu_r_addsub[31] == 0) ) cmp_exception <= 1;
end
`endif
// ----- alu operation selection -----
always @(alu_a or alu_b or alu_op or flag_idim or alu_r_addsub
`ifdef ENABLE_CMP
or cmp_exception
`endif
`ifdef ENABLE_MULT
or mul_done or mul_result
`endif
`ifdef ENABLE_BARREL
or bs_done or bs_result
`endif
`ifdef ENABLE_DIV
or div_done or div_result
`endif
)
begin
done <= 1; // default alu operations are 1 cycle
`ifdef ENABLE_MULT
mul_running <= 0;
`endif
`ifdef ENABLE_BARREL
bs_running <= 0;
`endif
`ifdef ENABLE_DIV
div_running <= 0;
`endif
alu_r <= alu_r_addsub; // ALU_PLUS, ALU_PLUS_OFFSET, ALU_SUB and part of ALU_CMP
case(alu_op)
`ALU_NOP : alu_r <= alu_a;
`ALU_NOP_B : alu_r <= alu_b;
`ALU_AND : alu_r <= alu_a & alu_b;
`ALU_OR : alu_r <= alu_a | alu_b;
`ALU_NOT : alu_r <= ~alu_a;
`ALU_FLIP : alu_r <= { alu_a[0], alu_a[1], alu_a[2], alu_a[3], alu_a[4], alu_a[5], alu_a[6], alu_a[7],
alu_a[8],alu_a[9],alu_a[10],alu_a[11],alu_a[12],alu_a[13],alu_a[14],alu_a[15],
alu_a[16],alu_a[17],alu_a[18],alu_a[19],alu_a[20],alu_a[21],alu_a[22],alu_a[23],
alu_a[24],alu_a[25],alu_a[26],alu_a[27],alu_a[28],alu_a[29],alu_a[30],alu_a[31] };
`ALU_IM : if(flag_idim) alu_r <= { alu_a[24:0], alu_b[6:0] };
else alu_r <= { {25{alu_b[6]}}, alu_b[6:0] };
`ifdef ENABLE_CMP
`ALU_CMP_UNSIGNED:if( (alu_a[31] == alu_b[31] && cmp_exception) ||
(alu_a[31] != alu_b[31] && ~cmp_exception) )
begin
alu_r[31] <= ~alu_r_addsub[31];
end
`ALU_CMP_SIGNED : if(cmp_exception)
begin
alu_r[31] <= ~alu_r_addsub[31];
end
`endif
`ifdef ENABLE_XOR
`ALU_XOR : alu_r <= alu_a ^ alu_b;
`endif
`ifdef ENABLE_A_SHIFT
`ALU_A_SHIFT_RIGHT: alu_r <= { alu_a[31], alu_a[31], alu_a[30:1] }; // arithmetic shift left
`endif
`ifdef ENABLE_MULT
`ALU_MULT : begin
mul_running <= ~mul_done;
done <= mul_done;
alu_r <= mul_result;
end
`endif
`ifdef ENABLE_BARREL
`ALU_BARREL : begin
bs_running <= ~bs_done;
done <= bs_done;
alu_r <= bs_result;
end
`endif
`ifdef ENABLE_DIV
`ALU_DIV : begin
div_running<= ~div_done;
done <= div_done;
alu_r <= quotient;
end
`ALU_MOD : begin
div_running<= ~div_done;
done <= div_done;
alu_r <= qr[31:0];
end
`endif
endcase
end
endmodule
|
(** * Equiv: Program Equivalence *)
Require Export Imp.
(** *** Some general advice for working on exercises:
- Most of the Coq proofs we ask you to do are similar to proofs
that we've provided. Before starting to work on the homework
problems, take the time to work through our proofs (both
informally, on paper, and in Coq) and make sure you understand
them in detail. This will save you a lot of time.
- The Coq proofs we're doing now are sufficiently complicated that
it is more or less impossible to complete them simply by random
experimentation or "following your nose." You need to start
with an idea about why the property is true and how the proof is
going to go. The best way to do this is to write out at least a
sketch of an informal proof on paper -- one that intuitively
convinces you of the truth of the theorem -- before starting to
work on the formal one. Alternately, grab a friend and try to
convince them that the theorem is true; then try to formalize
your explanation.
- Use automation to save work! Some of the proofs in this
chapter's exercises are pretty long if you try to write out all
the cases explicitly. *)
(* ####################################################### *)
(** * Behavioral Equivalence *)
(** In the last chapter, we investigated the correctness of a very
simple program transformation: the [optimize_0plus] function. The
programming language we were considering was the first version of
the language of arithmetic expressions -- with no variables -- so
in that setting it was very easy to define what it _means_ for a
program transformation to be correct: it should always yield a
program that evaluates to the same number as the original.
To go further and talk about the correctness of program
transformations in the full Imp language, we need to consider the
role of variables and state. *)
(* ####################################################### *)
(** ** Definitions *)
(** For [aexp]s and [bexp]s with variables, the definition we want is
clear. We say
that two [aexp]s or [bexp]s are _behaviorally equivalent_ if they
evaluate to the same result _in every state_. *)
Definition aequiv (a1 a2 : aexp) : Prop :=
forall (st:state),
aeval st a1 = aeval st a2.
Definition bequiv (b1 b2 : bexp) : Prop :=
forall (st:state),
beval st b1 = beval st b2.
(** For commands, the situation is a little more subtle. We can't
simply say "two commands are behaviorally equivalent if they
evaluate to the same ending state whenever they are started in the
same initial state," because some commands (in some starting
states) don't terminate in any final state at all! What we need
instead is this: two commands are behaviorally equivalent if, for
any given starting state, they either both diverge or both
terminate in the same final state. A compact way to express this
is "if the first one terminates in a particular state then so does
the second, and vice versa." *)
Definition cequiv (c1 c2 : com) : Prop :=
forall (st st' : state),
(c1 / st || st') <-> (c2 / st || st').
(** **** Exercise: 2 stars (equiv_classes) *)
(** Given the following programs, group together those that are
equivalent in [Imp]. Your answer should be given as a list of
lists, where each sub-list represents a group of equivalent
programs. For example, if you think programs (a) through (h) are
all equivalent to each other, but not to (i), your answer should
look like this:
[ [prog_a;prog_b;prog_c;prog_d;prog_e;prog_f;prog_g;prog_h] ;
[prog_i] ]
Write down your answer below in the definition of [equiv_classes]. *)
Definition prog_a : com :=
WHILE BNot (BLe (AId X) (ANum 0)) DO
X ::= APlus (AId X) (ANum 1)
END.
Definition prog_b : com :=
IFB BEq (AId X) (ANum 0) THEN
X ::= APlus (AId X) (ANum 1);;
Y ::= ANum 1
ELSE
Y ::= ANum 0
FI;;
X ::= AMinus (AId X) (AId Y);;
Y ::= ANum 0.
Definition prog_c : com :=
SKIP.
Definition prog_d : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
X ::= APlus (AMult (AId X) (AId Y)) (ANum 1)
END.
Definition prog_e : com :=
Y ::= ANum 0.
Definition prog_f : com :=
Y ::= APlus (AId X) (ANum 1);;
WHILE BNot (BEq (AId X) (AId Y)) DO
Y ::= APlus (AId X) (ANum 1)
END.
Definition prog_g : com :=
WHILE BTrue DO
SKIP
END.
Definition prog_h : com :=
WHILE BNot (BEq (AId X) (AId X)) DO
X ::= APlus (AId X) (ANum 1)
END.
Definition prog_i : com :=
WHILE BNot (BEq (AId X) (AId Y)) DO
X ::= APlus (AId Y) (ANum 1)
END.
Definition equiv_classes : list (list com) :=
(* FILL IN HERE *) admit.
(* GRADE_TEST 2: check_equiv_classes equiv_classes *)
(** [] *)
(* ####################################################### *)
(** ** Examples *)
(** Here are some simple examples of equivalences of arithmetic
and boolean expressions. *)
Theorem aequiv_example:
aequiv (AMinus (AId X) (AId X)) (ANum 0).
Proof.
intros st. simpl. omega.
Qed.
Theorem bequiv_example:
bequiv (BEq (AMinus (AId X) (AId X)) (ANum 0)) BTrue.
Proof.
intros st. unfold beval.
rewrite aequiv_example. reflexivity.
Qed.
(** For examples of command equivalence, let's start by looking at
some trivial program transformations involving [SKIP]: *)
Theorem skip_left: forall c,
cequiv
(SKIP;; c)
c.
Proof.
(* WORKED IN CLASS *)
intros c st st'.
split; intros H.
Case "->".
inversion H. subst.
inversion H2. subst.
assumption.
Case "<-".
apply E_Seq with st.
apply E_Skip.
assumption.
Qed.
(** **** Exercise: 2 stars (skip_right) *)
(** Prove that adding a SKIP after a command results in an equivalent
program *)
Theorem skip_right: forall c,
cequiv
(c;; SKIP)
c.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Similarly, here is a simple transformations that simplifies [IFB]
commands: *)
Theorem IFB_true_simple: forall c1 c2,
cequiv
(IFB BTrue THEN c1 ELSE c2 FI)
c1.
Proof.
intros c1 c2.
split; intros H.
Case "->".
inversion H; subst. assumption. inversion H5.
Case "<-".
apply E_IfTrue. reflexivity. assumption. Qed.
(** Of course, few programmers would be tempted to write a conditional
whose guard is literally [BTrue]. A more interesting case is when
the guard is _equivalent_ to true:
_Theorem_: If [b] is equivalent to [BTrue], then [IFB b THEN c1
ELSE c2 FI] is equivalent to [c1].
*)
(** *** *)
(**
_Proof_:
- ([->]) We must show, for all [st] and [st'], that if [IFB b
THEN c1 ELSE c2 FI / st || st'] then [c1 / st || st'].
Proceed by cases on the rules that could possibly have been
used to show [IFB b THEN c1 ELSE c2 FI / st || st'], namely
[E_IfTrue] and [E_IfFalse].
- Suppose the final rule rule in the derivation of [IFB b THEN
c1 ELSE c2 FI / st || st'] was [E_IfTrue]. We then have, by
the premises of [E_IfTrue], that [c1 / st || st']. This is
exactly what we set out to prove.
- On the other hand, suppose the final rule in the derivation
of [IFB b THEN c1 ELSE c2 FI / st || st'] was [E_IfFalse].
We then know that [beval st b = false] and [c2 / st || st'].
Recall that [b] is equivalent to [BTrue], i.e. forall [st],
[beval st b = beval st BTrue]. In particular, this means
that [beval st b = true], since [beval st BTrue = true]. But
this is a contradiction, since [E_IfFalse] requires that
[beval st b = false]. Thus, the final rule could not have
been [E_IfFalse].
- ([<-]) We must show, for all [st] and [st'], that if [c1 / st
|| st'] then [IFB b THEN c1 ELSE c2 FI / st || st'].
Since [b] is equivalent to [BTrue], we know that [beval st b] =
[beval st BTrue] = [true]. Together with the assumption that
[c1 / st || st'], we can apply [E_IfTrue] to derive [IFB b THEN
c1 ELSE c2 FI / st || st']. []
Here is the formal version of this proof: *)
Theorem IFB_true: forall b c1 c2,
bequiv b BTrue ->
cequiv
(IFB b THEN c1 ELSE c2 FI)
c1.
Proof.
intros b c1 c2 Hb.
split; intros H.
Case "->".
inversion H; subst.
SCase "b evaluates to true".
assumption.
SCase "b evaluates to false (contradiction)".
unfold bequiv in Hb. simpl in Hb.
rewrite Hb in H5.
inversion H5.
Case "<-".
apply E_IfTrue; try assumption.
unfold bequiv in Hb. simpl in Hb.
rewrite Hb. reflexivity. Qed.
(** **** Exercise: 2 stars (IFB_false) *)
Theorem IFB_false: forall b c1 c2,
bequiv b BFalse ->
cequiv
(IFB b THEN c1 ELSE c2 FI)
c2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (swap_if_branches) *)
(** Show that we can swap the branches of an IF by negating its
condition *)
Theorem swap_if_branches: forall b e1 e2,
cequiv
(IFB b THEN e1 ELSE e2 FI)
(IFB BNot b THEN e2 ELSE e1 FI).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** *** *)
(** For [WHILE] loops, we can give a similar pair of theorems. A loop
whose guard is equivalent to [BFalse] is equivalent to [SKIP],
while a loop whose guard is equivalent to [BTrue] is equivalent to
[WHILE BTrue DO SKIP END] (or any other non-terminating program).
The first of these facts is easy. *)
Theorem WHILE_false : forall b c,
bequiv b BFalse ->
cequiv
(WHILE b DO c END)
SKIP.
Proof.
intros b c Hb. split; intros H.
Case "->".
inversion H; subst.
SCase "E_WhileEnd".
apply E_Skip.
SCase "E_WhileLoop".
rewrite Hb in H2. inversion H2.
Case "<-".
inversion H; subst.
apply E_WhileEnd.
rewrite Hb.
reflexivity. Qed.
(** **** Exercise: 2 stars, advanced, optional (WHILE_false_informal) *)
(** Write an informal proof of [WHILE_false].
(* FILL IN HERE *)
[]
*)
(** *** *)
(** To prove the second fact, we need an auxiliary lemma stating that
[WHILE] loops whose guards are equivalent to [BTrue] never
terminate:
_Lemma_: If [b] is equivalent to [BTrue], then it cannot be the
case that [(WHILE b DO c END) / st || st'].
_Proof_: Suppose that [(WHILE b DO c END) / st || st']. We show,
by induction on a derivation of [(WHILE b DO c END) / st || st'],
that this assumption leads to a contradiction.
- Suppose [(WHILE b DO c END) / st || st'] is proved using rule
[E_WhileEnd]. Then by assumption [beval st b = false]. But
this contradicts the assumption that [b] is equivalent to
[BTrue].
- Suppose [(WHILE b DO c END) / st || st'] is proved using rule
[E_WhileLoop]. Then we are given the induction hypothesis
that [(WHILE b DO c END) / st || st'] is contradictory, which
is exactly what we are trying to prove!
- Since these are the only rules that could have been used to
prove [(WHILE b DO c END) / st || st'], the other cases of
the induction are immediately contradictory. [] *)
Lemma WHILE_true_nonterm : forall b c st st',
bequiv b BTrue ->
~( (WHILE b DO c END) / st || st' ).
Proof.
(* WORKED IN CLASS *)
intros b c st st' Hb.
intros H.
remember (WHILE b DO c END) as cw eqn:Heqcw.
ceval_cases (induction H) Case;
(* Most rules don't apply, and we can rule them out
by inversion *)
inversion Heqcw; subst; clear Heqcw.
(* The two interesting cases are the ones for WHILE loops: *)
Case "E_WhileEnd". (* contradictory -- b is always true! *)
unfold bequiv in Hb.
(* [rewrite] is able to instantiate the quantifier in [st] *)
rewrite Hb in H. inversion H.
Case "E_WhileLoop". (* immediate from the IH *)
apply IHceval2. reflexivity. Qed.
(** **** Exercise: 2 stars, optional (WHILE_true_nonterm_informal) *)
(** Explain what the lemma [WHILE_true_nonterm] means in English.
(* FILL IN HERE *)
*)
(** [] *)
(** **** Exercise: 2 stars (WHILE_true) *)
(** Prove the following theorem. _Hint_: You'll want to use
[WHILE_true_nonterm] here. *)
Theorem WHILE_true: forall b c,
bequiv b BTrue ->
cequiv
(WHILE b DO c END)
(WHILE BTrue DO SKIP END).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
Theorem loop_unrolling: forall b c,
cequiv
(WHILE b DO c END)
(IFB b THEN (c;; WHILE b DO c END) ELSE SKIP FI).
Proof.
(* WORKED IN CLASS *)
intros b c st st'.
split; intros Hce.
Case "->".
inversion Hce; subst.
SCase "loop doesn't run".
apply E_IfFalse. assumption. apply E_Skip.
SCase "loop runs".
apply E_IfTrue. assumption.
apply E_Seq with (st' := st'0). assumption. assumption.
Case "<-".
inversion Hce; subst.
SCase "loop runs".
inversion H5; subst.
apply E_WhileLoop with (st' := st'0).
assumption. assumption. assumption.
SCase "loop doesn't run".
inversion H5; subst. apply E_WhileEnd. assumption. Qed.
(** **** Exercise: 2 stars, optional (seq_assoc) *)
Theorem seq_assoc : forall c1 c2 c3,
cequiv ((c1;;c2);;c3) (c1;;(c2;;c3)).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** ** The Functional Equivalence Axiom *)
(** Finally, let's look at simple equivalences involving assignments.
For example, we might expect to be able to show that [X ::= AId X]
is equivalent to [SKIP]. However, when we try to show it, we get
stuck in an interesting way. *)
Theorem identity_assignment_first_try : forall (X:id),
cequiv (X ::= AId X) SKIP.
Proof.
intros. split; intro H.
Case "->".
inversion H; subst. simpl.
replace (update st X (st X)) with st.
constructor.
(* Stuck... *) Abort.
(** Here we're stuck. The goal looks reasonable, but in fact it is not
provable! If we look back at the set of lemmas we proved about
[update] in the last chapter, we can see that lemma [update_same]
almost does the job, but not quite: it says that the original and
updated states agree at all values, but this is not the same thing
as saying that they are [=] in Coq's sense! *)
(** What is going on here? Recall that our states are just
functions from identifiers to values. For Coq, functions are only
equal when their definitions are syntactically the same, modulo
simplification. (This is the only way we can legally apply the
[refl_equal] constructor of the inductively defined proposition
[eq]!) In practice, for functions built up by repeated uses of the
[update] operation, this means that two functions can be proven
equal only if they were constructed using the _same_ [update]
operations, applied in the same order. In the theorem above, the
sequence of updates on the first parameter [cequiv] is one longer
than for the second parameter, so it is no wonder that the
equality doesn't hold. *)
(** *** *)
(** This problem is actually quite general. If we try to prove other
simple facts, such as
cequiv (X ::= X + 1;;
X ::= X + 1)
(X ::= X + 2)
or
cequiv (X ::= 1;; Y ::= 2)
(y ::= 2;; X ::= 1)
we'll get stuck in the same way: we'll have two functions that
behave the same way on all inputs, but cannot be proven to be [eq]
to each other.
The reasoning principle we would like to use in these situations
is called _functional extensionality_:
forall x, f x = g x
-------------------
f = g
Although this principle is not derivable in Coq's built-in logic,
it is safe to add it as an additional _axiom_. *)
Axiom functional_extensionality : forall {X Y: Type} {f g : X -> Y},
(forall (x: X), f x = g x) -> f = g.
(** It can be shown that adding this axiom doesn't introduce any
inconsistencies into Coq. (In this way, it is similar to adding
one of the classical logic axioms, such as [excluded_middle].) *)
(** With the benefit of this axiom we can prove our theorem. *)
Theorem identity_assignment : forall (X:id),
cequiv
(X ::= AId X)
SKIP.
Proof.
intros. split; intro H.
Case "->".
inversion H; subst. simpl.
replace (update st X (st X)) with st.
constructor.
apply functional_extensionality. intro.
rewrite update_same; reflexivity.
Case "<-".
inversion H; subst.
assert (st' = (update st' X (st' X))).
apply functional_extensionality. intro.
rewrite update_same; reflexivity.
rewrite H0 at 2.
constructor. reflexivity.
Qed.
(** **** Exercise: 2 stars (assign_aequiv) *)
Theorem assign_aequiv : forall X e,
aequiv (AId X) e ->
cequiv SKIP (X ::= e).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ####################################################### *)
(** * Properties of Behavioral Equivalence *)
(** We now turn to developing some of the properties of the program
equivalences we have defined. *)
(* ####################################################### *)
(** ** Behavioral Equivalence is an Equivalence *)
(** First, we verify that the equivalences on [aexps], [bexps], and
[com]s really are _equivalences_ -- i.e., that they are reflexive,
symmetric, and transitive. The proofs are all easy. *)
Lemma refl_aequiv : forall (a : aexp), aequiv a a.
Proof.
intros a st. reflexivity. Qed.
Lemma sym_aequiv : forall (a1 a2 : aexp),
aequiv a1 a2 -> aequiv a2 a1.
Proof.
intros a1 a2 H. intros st. symmetry. apply H. Qed.
Lemma trans_aequiv : forall (a1 a2 a3 : aexp),
aequiv a1 a2 -> aequiv a2 a3 -> aequiv a1 a3.
Proof.
unfold aequiv. intros a1 a2 a3 H12 H23 st.
rewrite (H12 st). rewrite (H23 st). reflexivity. Qed.
Lemma refl_bequiv : forall (b : bexp), bequiv b b.
Proof.
unfold bequiv. intros b st. reflexivity. Qed.
Lemma sym_bequiv : forall (b1 b2 : bexp),
bequiv b1 b2 -> bequiv b2 b1.
Proof.
unfold bequiv. intros b1 b2 H. intros st. symmetry. apply H. Qed.
Lemma trans_bequiv : forall (b1 b2 b3 : bexp),
bequiv b1 b2 -> bequiv b2 b3 -> bequiv b1 b3.
Proof.
unfold bequiv. intros b1 b2 b3 H12 H23 st.
rewrite (H12 st). rewrite (H23 st). reflexivity. Qed.
Lemma refl_cequiv : forall (c : com), cequiv c c.
Proof.
unfold cequiv. intros c st st'. apply iff_refl. Qed.
Lemma sym_cequiv : forall (c1 c2 : com),
cequiv c1 c2 -> cequiv c2 c1.
Proof.
unfold cequiv. intros c1 c2 H st st'.
assert (c1 / st || st' <-> c2 / st || st') as H'.
SCase "Proof of assertion". apply H.
apply iff_sym. assumption.
Qed.
Lemma iff_trans : forall (P1 P2 P3 : Prop),
(P1 <-> P2) -> (P2 <-> P3) -> (P1 <-> P3).
Proof.
intros P1 P2 P3 H12 H23.
inversion H12. inversion H23.
split; intros A.
apply H1. apply H. apply A.
apply H0. apply H2. apply A. Qed.
Lemma trans_cequiv : forall (c1 c2 c3 : com),
cequiv c1 c2 -> cequiv c2 c3 -> cequiv c1 c3.
Proof.
unfold cequiv. intros c1 c2 c3 H12 H23 st st'.
apply iff_trans with (c2 / st || st'). apply H12. apply H23. Qed.
(* ######################################################## *)
(** ** Behavioral Equivalence is a Congruence *)
(** Less obviously, behavioral equivalence is also a _congruence_.
That is, the equivalence of two subprograms implies the
equivalence of the larger programs in which they are embedded:
aequiv a1 a1'
-----------------------------
cequiv (i ::= a1) (i ::= a1')
cequiv c1 c1'
cequiv c2 c2'
------------------------
cequiv (c1;;c2) (c1';;c2')
...and so on.
(Note that we are using the inference rule notation here not as
part of a definition, but simply to write down some valid
implications in a readable format. We prove these implications
below.) *)
(** We will see a concrete example of why these congruence
properties are important in the following section (in the proof of
[fold_constants_com_sound]), but the main idea is that they allow
us to replace a small part of a large program with an equivalent
small part and know that the whole large programs are equivalent
_without_ doing an explicit proof about the non-varying parts --
i.e., the "proof burden" of a small change to a large program is
proportional to the size of the change, not the program. *)
Theorem CAss_congruence : forall i a1 a1',
aequiv a1 a1' ->
cequiv (CAss i a1) (CAss i a1').
Proof.
intros i a1 a2 Heqv st st'.
split; intros Hceval.
Case "->".
inversion Hceval. subst. apply E_Ass.
rewrite Heqv. reflexivity.
Case "<-".
inversion Hceval. subst. apply E_Ass.
rewrite Heqv. reflexivity. Qed.
(** The congruence property for loops is a little more interesting,
since it requires induction.
_Theorem_: Equivalence is a congruence for [WHILE] -- that is, if
[b1] is equivalent to [b1'] and [c1] is equivalent to [c1'], then
[WHILE b1 DO c1 END] is equivalent to [WHILE b1' DO c1' END].
_Proof_: Suppose [b1] is equivalent to [b1'] and [c1] is
equivalent to [c1']. We must show, for every [st] and [st'], that
[WHILE b1 DO c1 END / st || st'] iff [WHILE b1' DO c1' END / st
|| st']. We consider the two directions separately.
- ([->]) We show that [WHILE b1 DO c1 END / st || st'] implies
[WHILE b1' DO c1' END / st || st'], by induction on a
derivation of [WHILE b1 DO c1 END / st || st']. The only
nontrivial cases are when the final rule in the derivation is
[E_WhileEnd] or [E_WhileLoop].
- [E_WhileEnd]: In this case, the form of the rule gives us
[beval st b1 = false] and [st = st']. But then, since
[b1] and [b1'] are equivalent, we have [beval st b1' =
false], and [E-WhileEnd] applies, giving us [WHILE b1' DO
c1' END / st || st'], as required.
- [E_WhileLoop]: The form of the rule now gives us [beval st
b1 = true], with [c1 / st || st'0] and [WHILE b1 DO c1
END / st'0 || st'] for some state [st'0], with the
induction hypothesis [WHILE b1' DO c1' END / st'0 ||
st'].
Since [c1] and [c1'] are equivalent, we know that [c1' /
st || st'0]. And since [b1] and [b1'] are equivalent, we
have [beval st b1' = true]. Now [E-WhileLoop] applies,
giving us [WHILE b1' DO c1' END / st || st'], as
required.
- ([<-]) Similar. [] *)
Theorem CWhile_congruence : forall b1 b1' c1 c1',
bequiv b1 b1' -> cequiv c1 c1' ->
cequiv (WHILE b1 DO c1 END) (WHILE b1' DO c1' END).
Proof.
(* WORKED IN CLASS *)
unfold bequiv,cequiv.
intros b1 b1' c1 c1' Hb1e Hc1e st st'.
split; intros Hce.
Case "->".
remember (WHILE b1 DO c1 END) as cwhile eqn:Heqcwhile.
induction Hce; inversion Heqcwhile; subst.
SCase "E_WhileEnd".
apply E_WhileEnd. rewrite <- Hb1e. apply H.
SCase "E_WhileLoop".
apply E_WhileLoop with (st' := st').
SSCase "show loop runs". rewrite <- Hb1e. apply H.
SSCase "body execution".
apply (Hc1e st st'). apply Hce1.
SSCase "subsequent loop execution".
apply IHHce2. reflexivity.
Case "<-".
remember (WHILE b1' DO c1' END) as c'while eqn:Heqc'while.
induction Hce; inversion Heqc'while; subst.
SCase "E_WhileEnd".
apply E_WhileEnd. rewrite -> Hb1e. apply H.
SCase "E_WhileLoop".
apply E_WhileLoop with (st' := st').
SSCase "show loop runs". rewrite -> Hb1e. apply H.
SSCase "body execution".
apply (Hc1e st st'). apply Hce1.
SSCase "subsequent loop execution".
apply IHHce2. reflexivity. Qed.
(** **** Exercise: 3 stars, optional (CSeq_congruence) *)
Theorem CSeq_congruence : forall c1 c1' c2 c2',
cequiv c1 c1' -> cequiv c2 c2' ->
cequiv (c1;;c2) (c1';;c2').
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (CIf_congruence) *)
Theorem CIf_congruence : forall b b' c1 c1' c2 c2',
bequiv b b' -> cequiv c1 c1' -> cequiv c2 c2' ->
cequiv (IFB b THEN c1 ELSE c2 FI) (IFB b' THEN c1' ELSE c2' FI).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** *** *)
(** For example, here are two equivalent programs and a proof of their
equivalence... *)
Example congruence_example:
cequiv
(* Program 1: *)
(X ::= ANum 0;;
IFB (BEq (AId X) (ANum 0))
THEN
Y ::= ANum 0
ELSE
Y ::= ANum 42
FI)
(* Program 2: *)
(X ::= ANum 0;;
IFB (BEq (AId X) (ANum 0))
THEN
Y ::= AMinus (AId X) (AId X) (* <--- changed here *)
ELSE
Y ::= ANum 42
FI).
Proof.
apply CSeq_congruence.
apply refl_cequiv.
apply CIf_congruence.
apply refl_bequiv.
apply CAss_congruence. unfold aequiv. simpl.
symmetry. apply minus_diag.
apply refl_cequiv.
Qed.
(* ####################################################### *)
(** * Program Transformations *)
(** A _program transformation_ is a function that takes a program
as input and produces some variant of the program as its
output. Compiler optimizations such as constant folding are
a canonical example, but there are many others. *)
(** A program transformation is _sound_ if it preserves the
behavior of the original program.
We can define a notion of soundness for translations of
[aexp]s, [bexp]s, and [com]s. *)
Definition atrans_sound (atrans : aexp -> aexp) : Prop :=
forall (a : aexp),
aequiv a (atrans a).
Definition btrans_sound (btrans : bexp -> bexp) : Prop :=
forall (b : bexp),
bequiv b (btrans b).
Definition ctrans_sound (ctrans : com -> com) : Prop :=
forall (c : com),
cequiv c (ctrans c).
(* ######################################################## *)
(** ** The Constant-Folding Transformation *)
(** An expression is _constant_ when it contains no variable
references.
Constant folding is an optimization that finds constant
expressions and replaces them by their values. *)
Fixpoint fold_constants_aexp (a : aexp) : aexp :=
match a with
| ANum n => ANum n
| AId i => AId i
| APlus a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) => ANum (n1 + n2)
| (a1', a2') => APlus a1' a2'
end
| AMinus a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) => ANum (n1 - n2)
| (a1', a2') => AMinus a1' a2'
end
| AMult a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) => ANum (n1 * n2)
| (a1', a2') => AMult a1' a2'
end
end.
Example fold_aexp_ex1 :
fold_constants_aexp
(AMult (APlus (ANum 1) (ANum 2)) (AId X))
= AMult (ANum 3) (AId X).
Proof. reflexivity. Qed.
(** Note that this version of constant folding doesn't eliminate
trivial additions, etc. -- we are focusing attention on a single
optimization for the sake of simplicity. It is not hard to
incorporate other ways of simplifying expressions; the definitions
and proofs just get longer. *)
Example fold_aexp_ex2 :
fold_constants_aexp
(AMinus (AId X) (APlus (AMult (ANum 0) (ANum 6)) (AId Y)))
= AMinus (AId X) (APlus (ANum 0) (AId Y)).
Proof. reflexivity. Qed.
(** *** *)
(** Not only can we lift [fold_constants_aexp] to [bexp]s (in the
[BEq] and [BLe] cases), we can also find constant _boolean_
expressions and reduce them in-place. *)
Fixpoint fold_constants_bexp (b : bexp) : bexp :=
match b with
| BTrue => BTrue
| BFalse => BFalse
| BEq a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) => if beq_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BEq a1' a2'
end
| BLe a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) => if ble_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BLe a1' a2'
end
| BNot b1 =>
match (fold_constants_bexp b1) with
| BTrue => BFalse
| BFalse => BTrue
| b1' => BNot b1'
end
| BAnd b1 b2 =>
match (fold_constants_bexp b1, fold_constants_bexp b2) with
| (BTrue, BTrue) => BTrue
| (BTrue, BFalse) => BFalse
| (BFalse, BTrue) => BFalse
| (BFalse, BFalse) => BFalse
| (b1', b2') => BAnd b1' b2'
end
end.
Example fold_bexp_ex1 :
fold_constants_bexp (BAnd BTrue (BNot (BAnd BFalse BTrue)))
= BTrue.
Proof. reflexivity. Qed.
Example fold_bexp_ex2 :
fold_constants_bexp
(BAnd (BEq (AId X) (AId Y))
(BEq (ANum 0)
(AMinus (ANum 2) (APlus (ANum 1) (ANum 1)))))
= BAnd (BEq (AId X) (AId Y)) BTrue.
Proof. reflexivity. Qed.
(** *** *)
(** To fold constants in a command, we apply the appropriate folding
functions on all embedded expressions. *)
Fixpoint fold_constants_com (c : com) : com :=
match c with
| SKIP =>
SKIP
| i ::= a =>
CAss i (fold_constants_aexp a)
| c1 ;; c2 =>
(fold_constants_com c1) ;; (fold_constants_com c2)
| IFB b THEN c1 ELSE c2 FI =>
match fold_constants_bexp b with
| BTrue => fold_constants_com c1
| BFalse => fold_constants_com c2
| b' => IFB b' THEN fold_constants_com c1
ELSE fold_constants_com c2 FI
end
| WHILE b DO c END =>
match fold_constants_bexp b with
| BTrue => WHILE BTrue DO SKIP END
| BFalse => SKIP
| b' => WHILE b' DO (fold_constants_com c) END
end
end.
(** *** *)
Example fold_com_ex1 :
fold_constants_com
(* Original program: *)
(X ::= APlus (ANum 4) (ANum 5);;
Y ::= AMinus (AId X) (ANum 3);;
IFB BEq (AMinus (AId X) (AId Y)) (APlus (ANum 2) (ANum 4)) THEN
SKIP
ELSE
Y ::= ANum 0
FI;;
IFB BLe (ANum 0) (AMinus (ANum 4) (APlus (ANum 2) (ANum 1))) THEN
Y ::= ANum 0
ELSE
SKIP
FI;;
WHILE BEq (AId Y) (ANum 0) DO
X ::= APlus (AId X) (ANum 1)
END)
= (* After constant folding: *)
(X ::= ANum 9;;
Y ::= AMinus (AId X) (ANum 3);;
IFB BEq (AMinus (AId X) (AId Y)) (ANum 6) THEN
SKIP
ELSE
(Y ::= ANum 0)
FI;;
Y ::= ANum 0;;
WHILE BEq (AId Y) (ANum 0) DO
X ::= APlus (AId X) (ANum 1)
END).
Proof. reflexivity. Qed.
(* ################################################### *)
(** ** Soundness of Constant Folding *)
(** Now we need to show that what we've done is correct. *)
(** Here's the proof for arithmetic expressions: *)
Theorem fold_constants_aexp_sound :
atrans_sound fold_constants_aexp.
Proof.
unfold atrans_sound. intros a. unfold aequiv. intros st.
aexp_cases (induction a) Case; simpl;
(* ANum and AId follow immediately *)
try reflexivity;
(* APlus, AMinus, and AMult follow from the IH
and the observation that
aeval st (APlus a1 a2)
= ANum ((aeval st a1) + (aeval st a2))
= aeval st (ANum ((aeval st a1) + (aeval st a2)))
(and similarly for AMinus/minus and AMult/mult) *)
try (destruct (fold_constants_aexp a1);
destruct (fold_constants_aexp a2);
rewrite IHa1; rewrite IHa2; reflexivity). Qed.
(** **** Exercise: 3 stars, optional (fold_bexp_Eq_informal) *)
(** Here is an informal proof of the [BEq] case of the soundness
argument for boolean expression constant folding. Read it
carefully and compare it to the formal proof that follows. Then
fill in the [BLe] case of the formal proof (without looking at the
[BEq] case, if possible).
_Theorem_: The constant folding function for booleans,
[fold_constants_bexp], is sound.
_Proof_: We must show that [b] is equivalent to [fold_constants_bexp],
for all boolean expressions [b]. Proceed by induction on [b]. We
show just the case where [b] has the form [BEq a1 a2].
In this case, we must show
beval st (BEq a1 a2)
= beval st (fold_constants_bexp (BEq a1 a2)).
There are two cases to consider:
- First, suppose [fold_constants_aexp a1 = ANum n1] and
[fold_constants_aexp a2 = ANum n2] for some [n1] and [n2].
In this case, we have
fold_constants_bexp (BEq a1 a2)
= if beq_nat n1 n2 then BTrue else BFalse
and
beval st (BEq a1 a2)
= beq_nat (aeval st a1) (aeval st a2).
By the soundness of constant folding for arithmetic
expressions (Lemma [fold_constants_aexp_sound]), we know
aeval st a1
= aeval st (fold_constants_aexp a1)
= aeval st (ANum n1)
= n1
and
aeval st a2
= aeval st (fold_constants_aexp a2)
= aeval st (ANum n2)
= n2,
so
beval st (BEq a1 a2)
= beq_nat (aeval a1) (aeval a2)
= beq_nat n1 n2.
Also, it is easy to see (by considering the cases [n1 = n2] and
[n1 <> n2] separately) that
beval st (if beq_nat n1 n2 then BTrue else BFalse)
= if beq_nat n1 n2 then beval st BTrue else beval st BFalse
= if beq_nat n1 n2 then true else false
= beq_nat n1 n2.
So
beval st (BEq a1 a2)
= beq_nat n1 n2.
= beval st (if beq_nat n1 n2 then BTrue else BFalse),
]]
as required.
- Otherwise, one of [fold_constants_aexp a1] and
[fold_constants_aexp a2] is not a constant. In this case, we
must show
beval st (BEq a1 a2)
= beval st (BEq (fold_constants_aexp a1)
(fold_constants_aexp a2)),
which, by the definition of [beval], is the same as showing
beq_nat (aeval st a1) (aeval st a2)
= beq_nat (aeval st (fold_constants_aexp a1))
(aeval st (fold_constants_aexp a2)).
But the soundness of constant folding for arithmetic
expressions ([fold_constants_aexp_sound]) gives us
aeval st a1 = aeval st (fold_constants_aexp a1)
aeval st a2 = aeval st (fold_constants_aexp a2),
completing the case. []
*)
Theorem fold_constants_bexp_sound:
btrans_sound fold_constants_bexp.
Proof.
unfold btrans_sound. intros b. unfold bequiv. intros st.
bexp_cases (induction b) Case;
(* BTrue and BFalse are immediate *)
try reflexivity.
Case "BEq".
(* Doing induction when there are a lot of constructors makes
specifying variable names a chore, but Coq doesn't always
choose nice variable names. We can rename entries in the
context with the [rename] tactic: [rename a into a1] will
change [a] to [a1] in the current goal and context. *)
rename a into a1. rename a0 into a2. simpl.
remember (fold_constants_aexp a1) as a1' eqn:Heqa1'.
remember (fold_constants_aexp a2) as a2' eqn:Heqa2'.
replace (aeval st a1) with (aeval st a1') by
(subst a1'; rewrite <- fold_constants_aexp_sound; reflexivity).
replace (aeval st a2) with (aeval st a2') by
(subst a2'; rewrite <- fold_constants_aexp_sound; reflexivity).
destruct a1'; destruct a2'; try reflexivity.
(* The only interesting case is when both a1 and a2
become constants after folding *)
simpl. destruct (beq_nat n n0); reflexivity.
Case "BLe".
(* FILL IN HERE *) admit.
Case "BNot".
simpl. remember (fold_constants_bexp b) as b' eqn:Heqb'.
rewrite IHb.
destruct b'; reflexivity.
Case "BAnd".
simpl.
remember (fold_constants_bexp b1) as b1' eqn:Heqb1'.
remember (fold_constants_bexp b2) as b2' eqn:Heqb2'.
rewrite IHb1. rewrite IHb2.
destruct b1'; destruct b2'; reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars (fold_constants_com_sound) *)
(** Complete the [WHILE] case of the following proof. *)
Theorem fold_constants_com_sound :
ctrans_sound fold_constants_com.
Proof.
unfold ctrans_sound. intros c.
com_cases (induction c) Case; simpl.
Case "SKIP". apply refl_cequiv.
Case "::=". apply CAss_congruence. apply fold_constants_aexp_sound.
Case ";;". apply CSeq_congruence; assumption.
Case "IFB".
assert (bequiv b (fold_constants_bexp b)).
SCase "Pf of assertion". apply fold_constants_bexp_sound.
destruct (fold_constants_bexp b) eqn:Heqb;
(* If the optimization doesn't eliminate the if, then the result
is easy to prove from the IH and fold_constants_bexp_sound *)
try (apply CIf_congruence; assumption).
SCase "b always true".
apply trans_cequiv with c1; try assumption.
apply IFB_true; assumption.
SCase "b always false".
apply trans_cequiv with c2; try assumption.
apply IFB_false; assumption.
Case "WHILE".
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################################## *)
(** *** Soundness of (0 + n) Elimination, Redux *)
(** **** Exercise: 4 stars, advanced, optional (optimize_0plus) *)
(** Recall the definition [optimize_0plus] from Imp.v:
Fixpoint optimize_0plus (e:aexp) : aexp :=
match e with
| ANum n =>
ANum n
| APlus (ANum 0) e2 =>
optimize_0plus e2
| APlus e1 e2 =>
APlus (optimize_0plus e1) (optimize_0plus e2)
| AMinus e1 e2 =>
AMinus (optimize_0plus e1) (optimize_0plus e2)
| AMult e1 e2 =>
AMult (optimize_0plus e1) (optimize_0plus e2)
end.
Note that this function is defined over the old [aexp]s,
without states.
Write a new version of this function that accounts for variables,
and analogous ones for [bexp]s and commands:
optimize_0plus_aexp
optimize_0plus_bexp
optimize_0plus_com
Prove that these three functions are sound, as we did for
[fold_constants_*]. (Make sure you use the congruence lemmas in
the proof of [optimize_0plus_com] -- otherwise it will be _long_!)
Then define an optimizer on commands that first folds
constants (using [fold_constants_com]) and then eliminates [0 + n]
terms (using [optimize_0plus_com]).
- Give a meaningful example of this optimizer's output.
- Prove that the optimizer is sound. (This part should be _very_
easy.) *)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** * Proving That Programs Are _Not_ Equivalent *)
(** Suppose that [c1] is a command of the form [X ::= a1;; Y ::= a2]
and [c2] is the command [X ::= a1;; Y ::= a2'], where [a2'] is
formed by substituting [a1] for all occurrences of [X] in [a2].
For example, [c1] and [c2] might be:
c1 = (X ::= 42 + 53;;
Y ::= Y + X)
c2 = (X ::= 42 + 53;;
Y ::= Y + (42 + 53))
Clearly, this _particular_ [c1] and [c2] are equivalent. Is this
true in general? *)
(** We will see in a moment that it is not, but it is worthwhile
to pause, now, and see if you can find a counter-example on your
own. *)
(** Here, formally, is the function that substitutes an arithmetic
expression for each occurrence of a given variable in another
expression: *)
Fixpoint subst_aexp (i : id) (u : aexp) (a : aexp) : aexp :=
match a with
| ANum n => ANum n
| AId i' => if eq_id_dec i i' then u else AId i'
| APlus a1 a2 => APlus (subst_aexp i u a1) (subst_aexp i u a2)
| AMinus a1 a2 => AMinus (subst_aexp i u a1) (subst_aexp i u a2)
| AMult a1 a2 => AMult (subst_aexp i u a1) (subst_aexp i u a2)
end.
Example subst_aexp_ex :
subst_aexp X (APlus (ANum 42) (ANum 53)) (APlus (AId Y) (AId X)) =
(APlus (AId Y) (APlus (ANum 42) (ANum 53))).
Proof. reflexivity. Qed.
(** And here is the property we are interested in, expressing the
claim that commands [c1] and [c2] as described above are
always equivalent. *)
Definition subst_equiv_property := forall i1 i2 a1 a2,
cequiv (i1 ::= a1;; i2 ::= a2)
(i1 ::= a1;; i2 ::= subst_aexp i1 a1 a2).
(** *** *)
(** Sadly, the property does _not_ always hold.
_Theorem_: It is not the case that, for all [i1], [i2], [a1],
and [a2],
cequiv (i1 ::= a1;; i2 ::= a2)
(i1 ::= a1;; i2 ::= subst_aexp i1 a1 a2).
]]
_Proof_: Suppose, for a contradiction, that for all [i1], [i2],
[a1], and [a2], we have
cequiv (i1 ::= a1;; i2 ::= a2)
(i1 ::= a1;; i2 ::= subst_aexp i1 a1 a2).
Consider the following program:
X ::= APlus (AId X) (ANum 1);; Y ::= AId X
Note that
(X ::= APlus (AId X) (ANum 1);; Y ::= AId X)
/ empty_state || st1,
where [st1 = { X |-> 1, Y |-> 1 }].
By our assumption, we know that
cequiv (X ::= APlus (AId X) (ANum 1);; Y ::= AId X)
(X ::= APlus (AId X) (ANum 1);; Y ::= APlus (AId X) (ANum 1))
so, by the definition of [cequiv], we have
(X ::= APlus (AId X) (ANum 1);; Y ::= APlus (AId X) (ANum 1))
/ empty_state || st1.
But we can also derive
(X ::= APlus (AId X) (ANum 1);; Y ::= APlus (AId X) (ANum 1))
/ empty_state || st2,
where [st2 = { X |-> 1, Y |-> 2 }]. Note that [st1 <> st2]; this
is a contradiction, since [ceval] is deterministic! [] *)
Theorem subst_inequiv :
~ subst_equiv_property.
Proof.
unfold subst_equiv_property.
intros Contra.
(* Here is the counterexample: assuming that [subst_equiv_property]
holds allows us to prove that these two programs are
equivalent... *)
remember (X ::= APlus (AId X) (ANum 1);;
Y ::= AId X)
as c1.
remember (X ::= APlus (AId X) (ANum 1);;
Y ::= APlus (AId X) (ANum 1))
as c2.
assert (cequiv c1 c2) by (subst; apply Contra).
(* ... allows us to show that the command [c2] can terminate
in two different final states:
st1 = {X |-> 1, Y |-> 1}
st2 = {X |-> 1, Y |-> 2}. *)
remember (update (update empty_state X 1) Y 1) as st1.
remember (update (update empty_state X 1) Y 2) as st2.
assert (H1: c1 / empty_state || st1);
assert (H2: c2 / empty_state || st2);
try (subst;
apply E_Seq with (st' := (update empty_state X 1));
apply E_Ass; reflexivity).
apply H in H1.
(* Finally, we use the fact that evaluation is deterministic
to obtain a contradiction. *)
assert (Hcontra: st1 = st2)
by (apply (ceval_deterministic c2 empty_state); assumption).
assert (Hcontra': st1 Y = st2 Y)
by (rewrite Hcontra; reflexivity).
subst. inversion Hcontra'. Qed.
(** **** Exercise: 4 stars, optional (better_subst_equiv) *)
(** The equivalence we had in mind above was not complete nonsense --
it was actually almost right. To make it correct, we just need to
exclude the case where the variable [X] occurs in the
right-hand-side of the first assignment statement. *)
Inductive var_not_used_in_aexp (X:id) : aexp -> Prop :=
| VNUNum: forall n, var_not_used_in_aexp X (ANum n)
| VNUId: forall Y, X <> Y -> var_not_used_in_aexp X (AId Y)
| VNUPlus: forall a1 a2,
var_not_used_in_aexp X a1 ->
var_not_used_in_aexp X a2 ->
var_not_used_in_aexp X (APlus a1 a2)
| VNUMinus: forall a1 a2,
var_not_used_in_aexp X a1 ->
var_not_used_in_aexp X a2 ->
var_not_used_in_aexp X (AMinus a1 a2)
| VNUMult: forall a1 a2,
var_not_used_in_aexp X a1 ->
var_not_used_in_aexp X a2 ->
var_not_used_in_aexp X (AMult a1 a2).
Lemma aeval_weakening : forall i st a ni,
var_not_used_in_aexp i a ->
aeval (update st i ni) a = aeval st a.
Proof.
(* FILL IN HERE *) Admitted.
(** Using [var_not_used_in_aexp], formalize and prove a correct verson
of [subst_equiv_property]. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, optional (inequiv_exercise) *)
(** Prove that an infinite loop is not equivalent to [SKIP] *)
Theorem inequiv_exercise:
~ cequiv (WHILE BTrue DO SKIP END) SKIP.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** * Extended exercise: Non-deterministic Imp *)
(** As we have seen (in theorem [ceval_deterministic] in the Imp
chapter), Imp's evaluation relation is deterministic. However,
_non_-determinism is an important part of the definition of many
real programming languages. For example, in many imperative
languages (such as C and its relatives), the order in which
function arguments are evaluated is unspecified. The program
fragment
x = 0;;
f(++x, x)
might call [f] with arguments [(1, 0)] or [(1, 1)], depending how
the compiler chooses to order things. This can be a little
confusing for programmers, but it gives the compiler writer useful
freedom.
In this exercise, we will extend Imp with a simple
non-deterministic command and study how this change affects
program equivalence. The new command has the syntax [HAVOC X],
where [X] is an identifier. The effect of executing [HAVOC X] is
to assign an _arbitrary_ number to the variable [X],
non-deterministically. For example, after executing the program:
HAVOC Y;;
Z ::= Y * 2
the value of [Y] can be any number, while the value of [Z] is
twice that of [Y] (so [Z] is always even). Note that we are not
saying anything about the _probabilities_ of the outcomes -- just
that there are (infinitely) many different outcomes that can
possibly happen after executing this non-deterministic code.
In a sense a variable on which we do [HAVOC] roughly corresponds
to an unitialized variable in the C programming language. After
the [HAVOC] the variable holds a fixed but arbitrary number. Most
sources of nondeterminism in language definitions are there
precisely because programmers don't care which choice is made (and
so it is good to leave it open to the compiler to choose whichever
will run faster).
We call this new language _Himp_ (``Imp extended with [HAVOC]''). *)
Module Himp.
(** To formalize the language, we first add a clause to the definition of
commands. *)
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CHavoc : id -> com. (* <---- new *)
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";;"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "HAVOC" ].
Notation "'SKIP'" :=
CSkip.
Notation "X '::=' a" :=
(CAss X a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'HAVOC' l" := (CHavoc l) (at level 60).
(** **** Exercise: 2 stars (himp_ceval) *)
(** Now, we must extend the operational semantics. We have provided
a template for the [ceval] relation below, specifying the big-step
semantics. What rule(s) must be added to the definition of [ceval]
to formalize the behavior of the [HAVOC] command? *)
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st : state, SKIP / st || st
| E_Ass : forall (st : state) (a1 : aexp) (n : nat) (X : id),
aeval st a1 = n -> (X ::= a1) / st || update st X n
| E_Seq : forall (c1 c2 : com) (st st' st'' : state),
c1 / st || st' -> c2 / st' || st'' -> (c1 ;; c2) / st || st''
| E_IfTrue : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = true ->
c1 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = false ->
c2 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall (b1 : bexp) (st : state) (c1 : com),
beval st b1 = false -> (WHILE b1 DO c1 END) / st || st
| E_WhileLoop : forall (st st' st'' : state) (b1 : bexp) (c1 : com),
beval st b1 = true ->
c1 / st || st' ->
(WHILE b1 DO c1 END) / st' || st'' ->
(WHILE b1 DO c1 END) / st || st''
(* FILL IN HERE *)
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
(* FILL IN HERE *)
].
(** As a sanity check, the following claims should be provable for
your definition: *)
Example havoc_example1 : (HAVOC X) / empty_state || update empty_state X 0.
Proof.
(* FILL IN HERE *) Admitted.
Example havoc_example2 :
(SKIP;; HAVOC Z) / empty_state || update empty_state Z 42.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Finally, we repeat the definition of command equivalence from above: *)
Definition cequiv (c1 c2 : com) : Prop := forall st st' : state,
c1 / st || st' <-> c2 / st || st'.
(** This definition still makes perfect sense in the case of always
terminating programs, so let's apply it to prove some
non-deterministic programs equivalent or non-equivalent. *)
(** **** Exercise: 3 stars (havoc_swap) *)
(** Are the following two programs equivalent? *)
Definition pXY :=
HAVOC X;; HAVOC Y.
Definition pYX :=
HAVOC Y;; HAVOC X.
(** If you think they are equivalent, prove it. If you think they are
not, prove that. *)
Theorem pXY_cequiv_pYX :
cequiv pXY pYX \/ ~cequiv pXY pYX.
Proof. (* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, optional (havoc_copy) *)
(** Are the following two programs equivalent? *)
Definition ptwice :=
HAVOC X;; HAVOC Y.
Definition pcopy :=
HAVOC X;; Y ::= AId X.
(** If you think they are equivalent, then prove it. If you think they
are not, then prove that. (Hint: You may find the [assert] tactic
useful.) *)
Theorem ptwice_cequiv_pcopy :
cequiv ptwice pcopy \/ ~cequiv ptwice pcopy.
Proof. (* FILL IN HERE *) Admitted.
(** [] *)
(** The definition of program equivalence we are using here has some
subtle consequences on programs that may loop forever. What
[cequiv] says is that the set of possible _terminating_ outcomes
of two equivalent programs is the same. However, in a language
with non-determinism, like Himp, some programs always terminate,
some programs always diverge, and some programs can
non-deterministically terminate in some runs and diverge in
others. The final part of the following exercise illustrates this
phenomenon.
*)
(** **** Exercise: 5 stars, advanced (p1_p2_equiv) *)
(** Prove that p1 and p2 are equivalent. In this and the following
exercises, try to understand why the [cequiv] definition has the
behavior it has on these examples. *)
Definition p1 : com :=
WHILE (BNot (BEq (AId X) (ANum 0))) DO
HAVOC Y;;
X ::= APlus (AId X) (ANum 1)
END.
Definition p2 : com :=
WHILE (BNot (BEq (AId X) (ANum 0))) DO
SKIP
END.
(** Intuitively, the programs have the same termination
behavior: either they loop forever, or they terminate in the
same state they started in. We can capture the termination
behavior of p1 and p2 individually with these lemmas: *)
Lemma p1_may_diverge : forall st st', st X <> 0 ->
~ p1 / st || st'.
Proof. (* FILL IN HERE *) Admitted.
Lemma p2_may_diverge : forall st st', st X <> 0 ->
~ p2 / st || st'.
Proof.
(* FILL IN HERE *) Admitted.
(** You should use these lemmas to prove that p1 and p2 are actually
equivalent. *)
Theorem p1_p2_equiv : cequiv p1 p2.
Proof. (* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, advanced (p3_p4_inquiv) *)
(** Prove that the following programs are _not_ equivalent. *)
Definition p3 : com :=
Z ::= ANum 1;;
WHILE (BNot (BEq (AId X) (ANum 0))) DO
HAVOC X;;
HAVOC Z
END.
Definition p4 : com :=
X ::= (ANum 0);;
Z ::= (ANum 1).
Theorem p3_p4_inequiv : ~ cequiv p3 p4.
Proof. (* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 5 stars, advanced, optional (p5_p6_equiv) *)
Definition p5 : com :=
WHILE (BNot (BEq (AId X) (ANum 1))) DO
HAVOC X
END.
Definition p6 : com :=
X ::= ANum 1.
Theorem p5_p6_equiv : cequiv p5 p6.
Proof. (* FILL IN HERE *) Admitted.
(** [] *)
End Himp.
(* ####################################################### *)
(** * Doing Without Extensionality (Advanced) *)
(** Purists might object to using the [functional_extensionality]
axiom. In general, it can be quite dangerous to add axioms,
particularly several at once (as they may be mutually
inconsistent). In fact, [functional_extensionality] and
[excluded_middle] can both be assumed without any problems, but
some Coq users prefer to avoid such "heavyweight" general
techniques, and instead craft solutions for specific problems that
stay within Coq's standard logic.
For our particular problem here, rather than extending the
definition of equality to do what we want on functions
representing states, we could instead give an explicit notion of
_equivalence_ on states. For example: *)
Definition stequiv (st1 st2 : state) : Prop :=
forall (X:id), st1 X = st2 X.
Notation "st1 '~' st2" := (stequiv st1 st2) (at level 30).
(** It is easy to prove that [stequiv] is an _equivalence_ (i.e., it
is reflexive, symmetric, and transitive), so it partitions the set
of all states into equivalence classes. *)
(** **** Exercise: 1 star, optional (stequiv_refl) *)
Lemma stequiv_refl : forall (st : state),
st ~ st.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, optional (stequiv_sym) *)
Lemma stequiv_sym : forall (st1 st2 : state),
st1 ~ st2 ->
st2 ~ st1.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, optional (stequiv_trans) *)
Lemma stequiv_trans : forall (st1 st2 st3 : state),
st1 ~ st2 ->
st2 ~ st3 ->
st1 ~ st3.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Another useful fact... *)
(** **** Exercise: 1 star, optional (stequiv_update) *)
Lemma stequiv_update : forall (st1 st2 : state),
st1 ~ st2 ->
forall (X:id) (n:nat),
update st1 X n ~ update st2 X n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** It is then straightforward to show that [aeval] and [beval] behave
uniformly on all members of an equivalence class: *)
(** **** Exercise: 2 stars, optional (stequiv_aeval) *)
Lemma stequiv_aeval : forall (st1 st2 : state),
st1 ~ st2 ->
forall (a:aexp), aeval st1 a = aeval st2 a.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional (stequiv_beval) *)
Lemma stequiv_beval : forall (st1 st2 : state),
st1 ~ st2 ->
forall (b:bexp), beval st1 b = beval st2 b.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** We can also characterize the behavior of [ceval] on equivalent
states (this result is a bit more complicated to write down
because [ceval] is a relation). *)
Lemma stequiv_ceval: forall (st1 st2 : state),
st1 ~ st2 ->
forall (c: com) (st1': state),
(c / st1 || st1') ->
exists st2' : state,
((c / st2 || st2') /\ st1' ~ st2').
Proof.
intros st1 st2 STEQV c st1' CEV1. generalize dependent st2.
induction CEV1; intros st2 STEQV.
Case "SKIP".
exists st2. split.
constructor.
assumption.
Case ":=".
exists (update st2 x n). split.
constructor. rewrite <- H. symmetry. apply stequiv_aeval.
assumption. apply stequiv_update. assumption.
Case ";".
destruct (IHCEV1_1 st2 STEQV) as [st2' [P1 EQV1]].
destruct (IHCEV1_2 st2' EQV1) as [st2'' [P2 EQV2]].
exists st2''. split.
apply E_Seq with st2'; assumption.
assumption.
Case "IfTrue".
destruct (IHCEV1 st2 STEQV) as [st2' [P EQV]].
exists st2'. split.
apply E_IfTrue. rewrite <- H. symmetry. apply stequiv_beval.
assumption. assumption. assumption.
Case "IfFalse".
destruct (IHCEV1 st2 STEQV) as [st2' [P EQV]].
exists st2'. split.
apply E_IfFalse. rewrite <- H. symmetry. apply stequiv_beval.
assumption. assumption. assumption.
Case "WhileEnd".
exists st2. split.
apply E_WhileEnd. rewrite <- H. symmetry. apply stequiv_beval.
assumption. assumption.
Case "WhileLoop".
destruct (IHCEV1_1 st2 STEQV) as [st2' [P1 EQV1]].
destruct (IHCEV1_2 st2' EQV1) as [st2'' [P2 EQV2]].
exists st2''. split.
apply E_WhileLoop with st2'. rewrite <- H. symmetry.
apply stequiv_beval. assumption. assumption. assumption.
assumption.
Qed.
(** Now we need to redefine [cequiv] to use [~] instead of [=]. It is
not completely trivial to do this in a way that keeps the
definition simple and symmetric, but here is one approach (thanks
to Andrew McCreight). We first define a looser variant of [||]
that "folds in" the notion of equivalence. *)
Reserved Notation "c1 '/' st '||'' st'" (at level 40, st at level 39).
Inductive ceval' : com -> state -> state -> Prop :=
| E_equiv : forall c st st' st'',
c / st || st' ->
st' ~ st'' ->
c / st ||' st''
where "c1 '/' st '||'' st'" := (ceval' c1 st st').
(** Now the revised definition of [cequiv'] looks familiar: *)
Definition cequiv' (c1 c2 : com) : Prop :=
forall (st st' : state),
(c1 / st ||' st') <-> (c2 / st ||' st').
(** A sanity check shows that the original notion of command
equivalence is at least as strong as this new one. (The converse
is not true, naturally.) *)
Lemma cequiv__cequiv' : forall (c1 c2: com),
cequiv c1 c2 -> cequiv' c1 c2.
Proof.
unfold cequiv, cequiv'; split; intros.
inversion H0 ; subst. apply E_equiv with st'0.
apply (H st st'0); assumption. assumption.
inversion H0 ; subst. apply E_equiv with st'0.
apply (H st st'0). assumption. assumption.
Qed.
(** **** Exercise: 2 stars, optional (identity_assignment') *)
(** Finally, here is our example once more... (You can complete the
proof.) *)
Example identity_assignment' :
cequiv' SKIP (X ::= AId X).
Proof.
unfold cequiv'. intros. split; intros.
Case "->".
inversion H; subst; clear H. inversion H0; subst.
apply E_equiv with (update st'0 X (st'0 X)).
constructor. reflexivity. apply stequiv_trans with st'0.
unfold stequiv. intros. apply update_same.
reflexivity. assumption.
Case "<-".
(* FILL IN HERE *) Admitted.
(** [] *)
(** On the whole, this explicit equivalence approach is considerably
harder to work with than relying on functional
extensionality. (Coq does have an advanced mechanism called
"setoids" that makes working with equivalences somewhat easier, by
allowing them to be registered with the system so that standard
rewriting tactics work for them almost as well as for equalities.)
But it is worth knowing about, because it applies even in
situations where the equivalence in question is _not_ over
functions. For example, if we chose to represent state mappings
as binary search trees, we would need to use an explicit
equivalence of this kind. *)
(* ####################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 4 stars, optional (for_while_equiv) *)
(** This exercise extends the optional [add_for_loop] exercise from
Imp.v, where you were asked to extend the language of commands
with C-style [for] loops. Prove that the command:
for (c1 ; b ; c2) {
c3
}
is equivalent to:
c1 ;
WHILE b DO
c3 ;
c2
END
*)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, optional (swap_noninterfering_assignments) *)
Theorem swap_noninterfering_assignments: forall l1 l2 a1 a2,
l1 <> l2 ->
var_not_used_in_aexp l1 a2 ->
var_not_used_in_aexp l2 a1 ->
cequiv
(l1 ::= a1;; l2 ::= a2)
(l2 ::= a2;; l1 ::= a1).
Proof.
(* Hint: You'll need [functional_extensionality] *)
(* FILL IN HERE *) Admitted.
(** [] *)
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2011 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
`define is_near_real(a,b) (( ((a)<(b)) ? (b)-(a) : (a)-(b)) < (((a)/(b))*0.0001))
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
real r;
reg [31:0] v32;
reg [63:0] v64;
reg [95:0] v96;
initial begin
// verilator lint_off REALCVT
v32 = -1.5;
v64 = -1.5;
v96 = -1.5;
// verilator lint_on REALCVT
`checkh(v32, 32'hfffffffe);
`checkh(v64, 64'hfffffffffffffffe);
`checkh(v96, 96'hfffffffffffffffffffffffe);
// verilator lint_off REALCVT
v32 = 12456789012345678912345.5;
v64 = 12456789012345678912345.5;
v96 = 12456789012345678912345.5;
// verilator lint_on REALCVT
`checkh(v32, 32'he5400000);
`checkh(v64, 64'h48acb7d4e5400000);
`checkh(v96, 96'h000002a348acb7d4e5400000);
// verilator lint_off REALCVT
v32 = -12456789012345678912345.5;
v64 = -12456789012345678912345.5;
v96 = -12456789012345678912345.5;
// verilator lint_on REALCVT
`checkh(v32, 32'h1ac00000);
`checkh(v64, 64'hb753482b1ac00000);
`checkh(v96, 96'hfffffd5cb753482b1ac00000);
end
// Test loop
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc == 10) begin
r <= 0;
end
else if (cyc == 11) begin
// verilator lint_off REALCVT
v32 = r;
v64 = r;
v96 = r;
// verilator lint_on REALCVT
`checkh(v32, '0);
`checkh(v64, '0);
`checkh(v96, '0);
end
else if (cyc == 20) begin
r <= -5.24567;
end
else if (cyc == 21) begin
// verilator lint_off REALCVT
v32 = r;
v64 = r;
v96 = r;
// verilator lint_on REALCVT
`checkh(v32, 32'hfffffffb);
`checkh(v64, 64'hfffffffffffffffb);
`checkh(v96, 96'hfffffffffffffffffffffffb);
end
else if (cyc == 30) begin
r <= 12456789012345678912345.5;
end
else if (cyc == 31) begin
// verilator lint_off REALCVT
v32 = r;
v64 = r;
v96 = r;
// verilator lint_on REALCVT
`checkh(v32, 32'he5400000);
`checkh(v64, 64'h48acb7d4e5400000);
`checkh(v96, 96'h000002a348acb7d4e5400000);
end
else if (cyc == 99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_nios2_gen2_0_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
(** * Smallstep: Small-step Operational Semantics *)
Set Warnings "-notation-overridden,-parsing".
Require Import Coq.Arith.Arith.
Require Import Coq.Arith.EqNat.
Require Import Coq.omega.Omega.
Require Import Coq.Lists.List.
Import ListNotations.
Require Import Maps.
Require Import Imp.
(** The evaluators we have seen so far (for [aexp]s, [bexp]s,
commands, ...) have been formulated in a "big-step" style: they
specify how a given expression can be evaluated to its final
value (or a command plus a store to a final store) "all in one big
step."
This style is simple and natural for many purposes -- indeed,
Gilles Kahn, who popularized it, called it _natural semantics_.
But there are some things it does not do well. In particular, it
does not give us a natural way of talking about _concurrent_
programming languages, where the semantics of a program -- i.e.,
the essence of how it behaves -- is not just which input states
get mapped to which output states, but also includes the
intermediate states that it passes through along the way, since
these states can also be observed by concurrently executing code.
Another shortcoming of the big-step style is more technical, but
critical in many situations. Suppose we want to define a variant
of Imp where variables could hold _either_ numbers _or_ lists of
numbers. In the syntax of this extended language, it will be
possible to write strange expressions like [2 + nil], and our
semantics for arithmetic expressions will then need to say
something about how such expressions behave. One possibility is
to maintain the convention that every arithmetic expressions
evaluates to some number by choosing some way of viewing a list as
a number -- e.g., by specifying that a list should be interpreted
as [0] when it occurs in a context expecting a number. But this
is really a bit of a hack.
A much more natural approach is simply to say that the behavior of
an expression like [2+nil] is _undefined_ -- i.e., it doesn't
evaluate to any result at all. And we can easily do this: we just
have to formulate [aeval] and [beval] as [Inductive] propositions
rather than Fixpoints, so that we can make them partial functions
instead of total ones.
Now, however, we encounter a serious deficiency. In this
language, a command might fail to map a given starting state to
any ending state for _two quite different reasons_: either because
the execution gets into an infinite loop or because, at some
point, the program tries to do an operation that makes no sense,
such as adding a number to a list, so that none of the evaluation
rules can be applied.
These two outcomes -- nontermination vs. getting stuck in an
erroneous configuration -- are quite different. In particular, we
want to allow the first (permitting the possibility of infinite
loops is the price we pay for the convenience of programming with
general looping constructs like [while]) but prevent the
second (which is just wrong), for example by adding some form of
_typechecking_ to the language. Indeed, this will be a major
topic for the rest of the course. As a first step, we need a way
of presenting the semantics that allows us to distinguish
nontermination from erroneous "stuck states."
So, for lots of reasons, we'd like to have a finer-grained way of
defining and reasoning about program behaviors. This is the topic
of the present chapter. We replace the "big-step" [eval] relation
with a "small-step" relation that specifies, for a given program,
how the "atomic steps" of computation are performed. *)
(* ################################################################# *)
(** * A Toy Language *)
(** To save space in the discussion, let's go back to an
incredibly simple language containing just constants and
addition. (We use single letters -- [C] and [P] (for Command and
Plus) -- as constructor names, for brevity.) At the end of the
chapter, we'll see how to apply the same techniques to the full
Imp language. *)
Inductive tm : Type :=
| C : nat -> tm (* Constant *)
| P : tm -> tm -> tm. (* Plus *)
(** Here is a standard evaluator for this language, written in
the big-step style that we've been using up to this point. *)
Fixpoint evalF (t : tm) : nat :=
match t with
| C n => n
| P a1 a2 => evalF a1 + evalF a2
end.
(** Here is the same evaluator, written in exactly the same
style, but formulated as an inductively defined relation. Again,
we use the notation [t \\ n] for "[t] evaluates to [n]." *)
(**
-------- (E_Const)
C n \\ n
t1 \\ n1
t2 \\ n2
------------------ (E_Plus)
P t1 t2 \\ n1 + n2
*)
Reserved Notation " t '\\' n " (at level 50, left associativity).
Inductive eval : tm -> nat -> Prop :=
| E_Const : forall n,
C n \\ n
| E_Plus : forall t1 t2 n1 n2,
t1 \\ n1 ->
t2 \\ n2 ->
P t1 t2 \\ (n1 + n2)
where " t '\\' n " := (eval t n).
Module SimpleArith1.
(** Now, here is the corresponding _small-step_ evaluation relation. *)
(**
------------------------------- (ST_PlusConstConst)
P (C n1) (C n2) ==> C (n1 + n2)
t1 ==> t1'
-------------------- (ST_Plus1)
P t1 t2 ==> P t1' t2
t2 ==> t2'
--------------------------- (ST_Plus2)
P (C n1) t2 ==> P (C n1) t2'
*)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall n1 t2 t2',
t2 ==> t2' ->
P (C n1) t2 ==> P (C n1) t2'
where " t '==>' t' " := (step t t').
(** Things to notice:
- We are defining just a single reduction step, in which
one [P] node is replaced by its value.
- Each step finds the _leftmost_ [P] node that is ready to
go (both of its operands are constants) and rewrites it in
place. The first rule tells how to rewrite this [P] node
itself; the other two rules tell how to find it.
- A term that is just a constant cannot take a step. *)
(** Let's pause and check a couple of examples of reasoning with
the [step] relation... *)
(** If [t1] can take a step to [t1'], then [P t1 t2] steps
to [P t1' t2]: *)
Example test_step_1 :
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>
P
(C (0 + 3))
(P (C 2) (C 4)).
Proof.
apply ST_Plus1. apply ST_PlusConstConst. Qed.
(** **** Exercise: 1 star (test_step_2) *)
(** Right-hand sides of sums can take a step only when the
left-hand side is finished: if [t2] can take a step to [t2'],
then [P (C n) t2] steps to [P (C n)
t2']: *)
Example test_step_2 :
P
(C 0)
(P
(C 2)
(P (C 0) (C 3)))
==>
P
(C 0)
(P
(C 2)
(C (0 + 3))).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End SimpleArith1.
(* ################################################################# *)
(** * Relations *)
(** We will be working with several different single-step relations,
so it is helpful to generalize a bit and state a few definitions
and theorems about relations in general. (The optional chapter
[Rel.v] develops some of these ideas in a bit more detail; it may
be useful if the treatment here is too dense.)
A _binary relation_ on a set [X] is a family of propositions
parameterized by two elements of [X] -- i.e., a proposition about
pairs of elements of [X]. *)
Definition relation (X: Type) := X->X->Prop.
(** Our main examples of such relations in this chapter will be
the single-step reduction relation, [==>], and its multi-step
variant, [==>*] (defined below), but there are many other
examples -- e.g., the "equals," "less than," "less than or equal
to," and "is the square of" relations on numbers, and the "prefix
of" relation on lists and strings. *)
(** One simple property of the [==>] relation is that, like the
big-step evaluation relation for Imp, it is _deterministic_.
_Theorem_: For each [t], there is at most one [t'] such that [t]
steps to [t'] ([t ==> t'] is provable). Formally, this is the
same as saying that [==>] is deterministic. *)
(** _Proof sketch_: We show that if [x] steps to both [y1] and
[y2], then [y1] and [y2] are equal, by induction on a derivation
of [step x y1]. There are several cases to consider, depending on
the last rule used in this derivation and the last rule in the
given derivation of [step x y2].
- If both are [ST_PlusConstConst], the result is immediate.
- The cases when both derivations end with [ST_Plus1] or
[ST_Plus2] follow by the induction hypothesis.
- It cannot happen that one is [ST_PlusConstConst] and the other
is [ST_Plus1] or [ST_Plus2], since this would imply that [x]
has the form [P t1 t2] where both [t1] and [t2] are
constants (by [ST_PlusConstConst]) _and_ one of [t1] or [t2]
has the form [P _].
- Similarly, it cannot happen that one is [ST_Plus1] and the
other is [ST_Plus2], since this would imply that [x] has the
form [P t1 t2] where [t1] has both the form [P t11 t12] and the
form [C n]. [] *)
(** Formally: *)
Definition deterministic {X: Type} (R: relation X) :=
forall x y1 y2 : X, R x y1 -> R x y2 -> y1 = y2.
Module SimpleArith2.
Import SimpleArith1.
Theorem step_deterministic:
deterministic step.
Proof.
unfold deterministic. intros x y1 y2 Hy1 Hy2.
generalize dependent y2.
induction Hy1; intros y2 Hy2.
- (* ST_PlusConstConst *) inversion Hy2.
+ (* ST_PlusConstConst *) reflexivity.
+ (* ST_Plus1 *) inversion H2.
+ (* ST_Plus2 *) inversion H2.
- (* ST_Plus1 *) inversion Hy2.
+ (* ST_PlusConstConst *)
rewrite <- H0 in Hy1. inversion Hy1.
+ (* ST_Plus1 *)
rewrite <- (IHHy1 t1'0).
reflexivity. assumption.
+ (* ST_Plus2 *)
rewrite <- H in Hy1. inversion Hy1.
- (* ST_Plus2 *) inversion Hy2.
+ (* ST_PlusConstConst *)
rewrite <- H1 in Hy1. inversion Hy1.
+ (* ST_Plus1 *) inversion H2.
+ (* ST_Plus2 *)
rewrite <- (IHHy1 t2'0).
reflexivity. assumption.
Qed.
End SimpleArith2.
(** There is some annoying repetition in this proof. Each use of
[inversion Hy2] results in three subcases, only one of which is
relevant (the one that matches the current case in the induction
on [Hy1]). The other two subcases need to be dismissed by finding
the contradiction among the hypotheses and doing inversion on it.
The following custom tactic, called [solve_by_inverts], can be
helpful in such cases. It will solve the goal if it can be solved
by inverting some hypothesis; otherwise, it fails. *)
Ltac solve_by_inverts n :=
match goal with | H : ?T |- _ =>
match type of T with Prop =>
solve [
inversion H;
match n with S (S (?n')) => subst; solve_by_inverts (S n') end ]
end end.
(** The details of how this works are not important for now, but it
illustrates the power of Coq's [Ltac] language for
programmatically defining special-purpose tactics. It looks
through the current proof state for a hypothesis [H] (the first
[match]) of type [Prop] (the second [match]) such that performing
inversion on [H] (followed by a recursive invocation of the same
tactic, if its argument [n] is greater than one) completely solves
the current goal. If no such hypothesis exists, it fails.
We will usually want to call [solve_by_inverts] with argument
[1] (especially as larger arguments can lead to very slow proof
checking), so we define [solve_by_invert] as a shorthand for this
case. *)
Ltac solve_by_invert :=
solve_by_inverts 1.
(** Let's see how a proof of the previous theorem can be simplified
using this tactic... *)
Module SimpleArith3.
Import SimpleArith1.
Theorem step_deterministic_alt: deterministic step.
Proof.
intros x y1 y2 Hy1 Hy2.
generalize dependent y2.
induction Hy1; intros y2 Hy2;
inversion Hy2; subst; try solve_by_invert.
- (* ST_PlusConstConst *) reflexivity.
- (* ST_Plus1 *)
apply IHHy1 in H2. rewrite H2. reflexivity.
- (* ST_Plus2 *)
apply IHHy1 in H2. rewrite H2. reflexivity.
Qed.
End SimpleArith3.
(* ================================================================= *)
(** ** Values *)
(** Next, it will be useful to slightly reformulate the
definition of single-step reduction by stating it in terms of
"values." *)
(** It is useful to think of the [==>] relation as defining an
_abstract machine_:
- At any moment, the _state_ of the machine is a term.
- A _step_ of the machine is an atomic unit of computation --
here, a single "add" operation.
- The _halting states_ of the machine are ones where there is no
more computation to be done. *)
(** We can then execute a term [t] as follows:
- Take [t] as the starting state of the machine.
- Repeatedly use the [==>] relation to find a sequence of
machine states, starting with [t], where each state steps to
the next.
- When no more reduction is possible, "read out" the final state
of the machine as the result of execution. *)
(** Intuitively, it is clear that the final states of the
machine are always terms of the form [C n] for some [n].
We call such terms _values_. *)
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n).
(** Having introduced the idea of values, we can use it in the
definition of the [==>] relation to write [ST_Plus2] rule in a
slightly more elegant way: *)
(**
------------------------------- (ST_PlusConstConst)
P (C n1) (C n2) ==> C (n1 + n2)
t1 ==> t1'
-------------------- (ST_Plus1)
P t1 t2 ==> P t1' t2
value v1
t2 ==> t2'
-------------------- (ST_Plus2)
P v1 t2 ==> P v1 t2'
*)
(** Again, the variable names here carry important information:
by convention, [v1] ranges only over values, while [t1] and [t2]
range over arbitrary terms. (Given this convention, the explicit
[value] hypothesis is arguably redundant. We'll keep it for now,
to maintain a close correspondence between the informal and Coq
versions of the rules, but later on we'll drop it in informal
rules for brevity.) *)
(** Here are the formal rules: *)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2)
==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 -> (* <----- n.b. *)
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
(** **** Exercise: 3 stars, recommended (redo_determinism) *)
(** As a sanity check on this change, let's re-verify determinism.
_Proof sketch_: We must show that if [x] steps to both [y1] and
[y2], then [y1] and [y2] are equal. Consider the final rules used
in the derivations of [step x y1] and [step x y2].
- If both are [ST_PlusConstConst], the result is immediate.
- It cannot happen that one is [ST_PlusConstConst] and the other
is [ST_Plus1] or [ST_Plus2], since this would imply that [x] has
the form [P t1 t2] where both [t1] and [t2] are constants (by
[ST_PlusConstConst]) _and_ one of [t1] or [t2] has the form [P _].
- Similarly, it cannot happen that one is [ST_Plus1] and the other
is [ST_Plus2], since this would imply that [x] has the form [P
t1 t2] where [t1] both has the form [P t11 t12] and is a
value (hence has the form [C n]).
- The cases when both derivations end with [ST_Plus1] or
[ST_Plus2] follow by the induction hypothesis. [] *)
(** Most of this proof is the same as the one above. But to get
maximum benefit from the exercise you should try to write your
formal version from scratch and just use the earlier one if you
get stuck. *)
Theorem step_deterministic :
deterministic step.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ================================================================= *)
(** ** Strong Progress and Normal Forms *)
(** The definition of single-step reduction for our toy language
is fairly simple, but for a larger language it would be easy to
forget one of the rules and accidentally create a situation where
some term cannot take a step even though it has not been
completely reduced to a value. The following theorem shows that
we did not, in fact, make such a mistake here. *)
(** _Theorem_ (_Strong Progress_): If [t] is a term, then either [t]
is a value or else there exists a term [t'] such that [t ==> t']. *)
(** _Proof_: By induction on [t].
- Suppose [t = C n]. Then [t] is a value.
- Suppose [t = P t1 t2], where (by the IH) [t1] either is a value
or can step to some [t1'], and where [t2] is either a value or
can step to some [t2']. We must show [P t1 t2] is either a value
or steps to some [t'].
- If [t1] and [t2] are both values, then [t] can take a step, by
[ST_PlusConstConst].
- If [t1] is a value and [t2] can take a step, then so can [t],
by [ST_Plus2].
- If [t1] can take a step, then so can [t], by [ST_Plus1]. []
Or, formally: *)
Theorem strong_progress : forall t,
value t \/ (exists t', t ==> t').
Proof.
induction t.
- (* C *) left. apply v_const.
- (* P *) right. inversion IHt1.
+ (* l *) inversion IHt2.
* (* l *) inversion H. inversion H0.
exists (C (n + n0)).
apply ST_PlusConstConst.
* (* r *) inversion H0 as [t' H1].
exists (P t1 t').
apply ST_Plus2. apply H. apply H1.
+ (* r *) inversion H as [t' H0].
exists (P t' t2).
apply ST_Plus1. apply H0. Qed.
(** This important property is called _strong progress_, because
every term either is a value or can "make progress" by stepping to
some other term. (The qualifier "strong" distinguishes it from a
more refined version that we'll see in later chapters, called
just _progress_.) *)
(** The idea of "making progress" can be extended to tell us something
interesting about values: in this language, values are exactly the
terms that _cannot_ make progress in this sense.
To state this observation formally, let's begin by giving a name
to terms that cannot make progress. We'll call them _normal
forms_. *)
Definition normal_form {X:Type} (R:relation X) (t:X) : Prop :=
~ exists t', R t t'.
(** Note that this definition specifies what it is to be a normal form
for an _arbitrary_ relation [R] over an arbitrary set [X], not
just for the particular single-step reduction relation over terms
that we are interested in at the moment. We'll re-use the same
terminology for talking about other relations later in the
course. *)
(** We can use this terminology to generalize the observation we made
in the strong progress theorem: in this language, normal forms and
values are actually the same thing. *)
Lemma value_is_nf : forall v,
value v -> normal_form step v.
Proof.
unfold normal_form. intros v H. inversion H.
intros contra. inversion contra. inversion H1.
Qed.
Lemma nf_is_value : forall t,
normal_form step t -> value t.
Proof. (* a corollary of [strong_progress]... *)
unfold normal_form. intros t H.
assert (G : value t \/ exists t', t ==> t').
{ apply strong_progress. }
inversion G.
+ (* l *) apply H0.
+ (* r *) exfalso. apply H. assumption. Qed.
Corollary nf_same_as_value : forall t,
normal_form step t <-> value t.
Proof.
split. apply nf_is_value. apply value_is_nf. Qed.
(** Why is this interesting?
Because [value] is a syntactic concept -- it is defined by looking
at the form of a term -- while [normal_form] is a semantic one --
it is defined by looking at how the term steps. It is not obvious
that these concepts should coincide! Indeed, we could easily have
written the definitions so that they would _not_ coincide. *)
(** **** Exercise: 3 stars, optional (value_not_same_as_normal_form1) *)
(** We might, for example, mistakenly define [value] so that it
includes some terms that are not finished reducing. *)
(** (Even if you don't work this exercise and the following ones
in Coq, make sure you can think of an example of such a term.) *)
Module Temp1.
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n)
| v_funny : forall t1 n2, (* <---- *)
value (P t1 (C n2)).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
Lemma value_not_same_as_normal_form :
exists v, value v /\ ~ normal_form step v.
Proof.
(* FILL IN HERE *) Admitted.
End Temp1.
(** [] *)
(** **** Exercise: 2 stars, optional (value_not_same_as_normal_form2) *)
(** Alternatively, we might mistakenly define [step] so that it
permits something designated as a value to reduce further. *)
Module Temp2.
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_Funny : forall n, (* <---- *)
C n ==> P (C n) (C 0)
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
Lemma value_not_same_as_normal_form :
exists v, value v /\ ~ normal_form step v.
Proof.
(* FILL IN HERE *) Admitted.
End Temp2.
(** [] *)
(** **** Exercise: 3 stars, optional (value_not_same_as_normal_form3) *)
(** Finally, we might define [value] and [step] so that there is some
term that is not a value but that cannot take a step in the [step]
relation. Such terms are said to be _stuck_. In this case this is
caused by a mistake in the semantics, but we will also see
situations where, even in a correct language definition, it makes
sense to allow some terms to be stuck. *)
Module Temp3.
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
where " t '==>' t' " := (step t t').
(** (Note that [ST_Plus2] is missing.) *)
Lemma value_not_same_as_normal_form :
exists t, ~ value t /\ normal_form step t.
Proof.
(* FILL IN HERE *) Admitted.
End Temp3.
(** [] *)
(* ----------------------------------------------------------------- *)
(** *** Additional Exercises *)
Module Temp4.
(** Here is another very simple language whose terms, instead of being
just addition expressions and numbers, are just the booleans true
and false and a conditional expression... *)
Inductive tm : Type :=
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Inductive value : tm -> Prop :=
| v_true : value ttrue
| v_false : value tfalse.
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
where " t '==>' t' " := (step t t').
(** **** Exercise: 1 starM (smallstep_bools) *)
(** Which of the following propositions are provable? (This is just a
thought exercise, but for an extra challenge feel free to prove
your answers in Coq.) *)
Definition bool_step_prop1 :=
tfalse ==> tfalse.
(* FILL IN HERE *)
Definition bool_step_prop2 :=
tif
ttrue
(tif ttrue ttrue ttrue)
(tif tfalse tfalse tfalse)
==>
ttrue.
(* FILL IN HERE *)
Definition bool_step_prop3 :=
tif
(tif ttrue ttrue ttrue)
(tif ttrue ttrue ttrue)
tfalse
==>
tif
ttrue
(tif ttrue ttrue ttrue)
tfalse.
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, optional (progress_bool) *)
(** Just as we proved a progress theorem for plus expressions, we can
do so for boolean expressions, as well. *)
Theorem strong_progress : forall t,
value t \/ (exists t', t ==> t').
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional (step_deterministic) *)
Theorem step_deterministic :
deterministic step.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
Module Temp5.
(** **** Exercise: 2 stars (smallstep_bool_shortcut) *)
(** Suppose we want to add a "short circuit" to the step relation for
boolean expressions, so that it can recognize when the [then] and
[else] branches of a conditional are the same value (either
[ttrue] or [tfalse]) and reduce the whole conditional to this
value in a single step, even if the guard has not yet been reduced
to a value. For example, we would like this proposition to be
provable:
tif
(tif ttrue ttrue ttrue)
tfalse
tfalse
==>
tfalse.
*)
(** Write an extra clause for the step relation that achieves this
effect and prove [bool_step_prop4]. *)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
(* FILL IN HERE *)
where " t '==>' t' " := (step t t').
Definition bool_step_prop4 :=
tif
(tif ttrue ttrue ttrue)
tfalse
tfalse
==>
tfalse.
Example bool_step_prop4_holds :
bool_step_prop4.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (properties_of_altered_step) *)
(** It can be shown that the determinism and strong progress theorems
for the step relation in the lecture notes also hold for the
definition of step given above. After we add the clause
[ST_ShortCircuit]...
- Is the [step] relation still deterministic? Write yes or no and
briefly (1 sentence) explain your answer.
Optional: prove your answer correct in Coq. *)
(* FILL IN HERE *)
(**
- Does a strong progress theorem hold? Write yes or no and
briefly (1 sentence) explain your answer.
Optional: prove your answer correct in Coq.
*)
(* FILL IN HERE *)
(**
- In general, is there any way we could cause strong progress to
fail if we took away one or more constructors from the original
step relation? Write yes or no and briefly (1 sentence) explain
your answer.
(* FILL IN HERE *)
*)
(** [] *)
End Temp5.
End Temp4.
(* ################################################################# *)
(** * Multi-Step Reduction *)
(** We've been working so far with the _single-step reduction_
relation [==>], which formalizes the individual steps of an
abstract machine for executing programs.
We can use the same machine to reduce programs to completion -- to
find out what final result they yield. This can be formalized as
follows:
- First, we define a _multi-step reduction relation_ [==>*], which
relates terms [t] and [t'] if [t] can reach [t'] by any number
(including zero) of single reduction steps.
- Then we define a "result" of a term [t] as a normal form that
[t] can reach by multi-step reduction. *)
(** Since we'll want to reuse the idea of multi-step reduction many
times, let's take a little extra trouble and define it
generically.
Given a relation [R], we define a relation [multi R], called the
_multi-step closure of [R]_ as follows. *)
Inductive multi {X:Type} (R: relation X) : relation X :=
| multi_refl : forall (x : X), multi R x x
| multi_step : forall (x y z : X),
R x y ->
multi R y z ->
multi R x z.
(** (In the \CHAPV1{Rel} chapter of _Logical Foundations_ and the Coq standard
library, this relation is called [clos_refl_trans_1n]. We give it a shorter
name here for the sake of readability.)
The effect of this definition is that [multi R] relates two
elements [x] and [y] if
- [x = y], or
- [R x y], or
- there is some nonempty sequence [z1], [z2], ..., [zn] such that
R x z1
R z1 z2
...
R zn y.
Thus, if [R] describes a single-step of computation, then [z1]...[zn]
is the sequence of intermediate steps of computation between [x] and
[y]. *)
(** We write [==>*] for the [multi step] relation on terms. *)
Notation " t '==>*' t' " := (multi step t t') (at level 40).
(** The relation [multi R] has several crucial properties.
First, it is obviously _reflexive_ (that is, [forall x, multi R x
x]). In the case of the [==>*] (i.e., [multi step]) relation, the
intuition is that a term can execute to itself by taking zero
steps of execution.
Second, it contains [R] -- that is, single-step executions are a
particular case of multi-step executions. (It is this fact that
justifies the word "closure" in the term "multi-step closure of
[R].") *)
Theorem multi_R : forall (X:Type) (R:relation X) (x y : X),
R x y -> (multi R) x y.
Proof.
intros X R x y H.
apply multi_step with y. apply H. apply multi_refl. Qed.
(** Third, [multi R] is _transitive_. *)
Theorem multi_trans :
forall (X:Type) (R: relation X) (x y z : X),
multi R x y ->
multi R y z ->
multi R x z.
Proof.
intros X R x y z G H.
induction G.
- (* multi_refl *) assumption.
- (* multi_step *)
apply multi_step with y. assumption.
apply IHG. assumption. Qed.
(** In particular, for the [multi step] relation on terms, if
[t1==>*t2] and [t2==>*t3], then [t1==>*t3]. *)
(* ================================================================= *)
(** ** Examples *)
(** Here's a specific instance of the [multi step] relation: *)
Lemma test_multistep_1:
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>*
C ((0 + 3) + (2 + 4)).
Proof.
apply multi_step with
(P (C (0 + 3))
(P (C 2) (C 4))).
apply ST_Plus1. apply ST_PlusConstConst.
apply multi_step with
(P (C (0 + 3))
(C (2 + 4))).
apply ST_Plus2. apply v_const.
apply ST_PlusConstConst.
apply multi_R.
apply ST_PlusConstConst. Qed.
(** Here's an alternate proof of the same fact that uses [eapply] to
avoid explicitly constructing all the intermediate terms. *)
Lemma test_multistep_1':
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>*
C ((0 + 3) + (2 + 4)).
Proof.
eapply multi_step. apply ST_Plus1. apply ST_PlusConstConst.
eapply multi_step. apply ST_Plus2. apply v_const.
apply ST_PlusConstConst.
eapply multi_step. apply ST_PlusConstConst.
apply multi_refl. Qed.
(** **** Exercise: 1 star, optional (test_multistep_2) *)
Lemma test_multistep_2:
C 3 ==>* C 3.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, optional (test_multistep_3) *)
Lemma test_multistep_3:
P (C 0) (C 3)
==>*
P (C 0) (C 3).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (test_multistep_4) *)
Lemma test_multistep_4:
P
(C 0)
(P
(C 2)
(P (C 0) (C 3)))
==>*
P
(C 0)
(C (2 + (0 + 3))).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ================================================================= *)
(** ** Normal Forms Again *)
(** If [t] reduces to [t'] in zero or more steps and [t'] is a
normal form, we say that "[t'] is a normal form of [t]." *)
Definition step_normal_form := normal_form step.
Definition normal_form_of (t t' : tm) :=
(t ==>* t' /\ step_normal_form t').
(** We have already seen that, for our language, single-step reduction is
deterministic -- i.e., a given term can take a single step in
at most one way. It follows from this that, if [t] can reach
a normal form, then this normal form is unique. In other words, we
can actually pronounce [normal_form t t'] as "[t'] is _the_
normal form of [t]." *)
(** **** Exercise: 3 stars, optional (normal_forms_unique) *)
Theorem normal_forms_unique:
deterministic normal_form_of.
Proof.
(* We recommend using this initial setup as-is! *)
unfold deterministic. unfold normal_form_of.
intros x y1 y2 P1 P2.
inversion P1 as [P11 P12]; clear P1.
inversion P2 as [P21 P22]; clear P2.
generalize dependent y2.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Indeed, something stronger is true for this language (though not
for all languages): the reduction of _any_ term [t] will
eventually reach a normal form -- i.e., [normal_form_of] is a
_total_ function. Formally, we say the [step] relation is
_normalizing_. *)
Definition normalizing {X:Type} (R:relation X) :=
forall t, exists t',
(multi R) t t' /\ normal_form R t'.
(** To prove that [step] is normalizing, we need a couple of lemmas.
First, we observe that, if [t] reduces to [t'] in many steps, then
the same sequence of reduction steps within [t] is also possible
when [t] appears as the left-hand child of a [P] node, and
similarly when [t] appears as the right-hand child of a [P]
node whose left-hand child is a value. *)
Lemma multistep_congr_1 : forall t1 t1' t2,
t1 ==>* t1' ->
P t1 t2 ==>* P t1' t2.
Proof.
intros t1 t1' t2 H. induction H.
- (* multi_refl *) apply multi_refl.
- (* multi_step *) apply multi_step with (P y t2).
apply ST_Plus1. apply H.
apply IHmulti. Qed.
(** **** Exercise: 2 stars (multistep_congr_2) *)
Lemma multistep_congr_2 : forall t1 t2 t2',
value t1 ->
t2 ==>* t2' ->
P t1 t2 ==>* P t1 t2'.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** With these lemmas in hand, the main proof is a straightforward
induction.
_Theorem_: The [step] function is normalizing -- i.e., for every
[t] there exists some [t'] such that [t] steps to [t'] and [t'] is
a normal form.
_Proof sketch_: By induction on terms. There are two cases to
consider:
- [t = C n] for some [n]. Here [t] doesn't take a step, and we
have [t' = t]. We can derive the left-hand side by reflexivity
and the right-hand side by observing (a) that values are normal
forms (by [nf_same_as_value]) and (b) that [t] is a value (by
[v_const]).
- [t = P t1 t2] for some [t1] and [t2]. By the IH, [t1] and [t2]
have normal forms [t1'] and [t2']. Recall that normal forms are
values (by [nf_same_as_value]); we know that [t1' = C n1] and
[t2' = C n2], for some [n1] and [n2]. We can combine the [==>*]
derivations for [t1] and [t2] using [multi_congr_1] and
[multi_congr_2] to prove that [P t1 t2] reduces in many steps to
[C (n1 + n2)].
It is clear that our choice of [t' = C (n1 + n2)] is a value,
which is in turn a normal form. [] *)
Theorem step_normalizing :
normalizing step.
Proof.
unfold normalizing.
induction t.
- (* C *)
exists (C n).
split.
+ (* l *) apply multi_refl.
+ (* r *)
(* We can use [rewrite] with "iff" statements, not
just equalities: *)
rewrite nf_same_as_value. apply v_const.
- (* P *)
destruct IHt1 as [t1' [H11 H12]].
destruct IHt2 as [t2' [H21 H22]].
rewrite nf_same_as_value in H12. rewrite nf_same_as_value in H22.
inversion H12 as [n1 H]. inversion H22 as [n2 H'].
rewrite <- H in H11.
rewrite <- H' in H21.
exists (C (n1 + n2)).
split.
+ (* l *)
apply multi_trans with (P (C n1) t2).
* apply multistep_congr_1. apply H11.
* apply multi_trans with
(P (C n1) (C n2)).
{ apply multistep_congr_2. apply v_const. apply H21. }
{ apply multi_R. apply ST_PlusConstConst. }
+ (* r *)
rewrite nf_same_as_value. apply v_const. Qed.
(* ================================================================= *)
(** ** Equivalence of Big-Step and Small-Step *)
(** Having defined the operational semantics of our tiny programming
language in two different ways (big-step and small-step), it makes
sense to ask whether these definitions actually define the same
thing! They do, though it takes a little work to show it. The
details are left as an exercise. *)
(** **** Exercise: 3 stars (eval__multistep) *)
Theorem eval__multistep : forall t n,
t \\ n -> t ==>* C n.
(** The key ideas in the proof can be seen in the following picture:
P t1 t2 ==> (by ST_Plus1)
P t1' t2 ==> (by ST_Plus1)
P t1'' t2 ==> (by ST_Plus1)
...
P (C n1) t2 ==> (by ST_Plus2)
P (C n1) t2' ==> (by ST_Plus2)
P (C n1) t2'' ==> (by ST_Plus2)
...
P (C n1) (C n2) ==> (by ST_PlusConstConst)
C (n1 + n2)
That is, the multistep reduction of a term of the form [P t1 t2]
proceeds in three phases:
- First, we use [ST_Plus1] some number of times to reduce [t1]
to a normal form, which must (by [nf_same_as_value]) be a
term of the form [C n1] for some [n1].
- Next, we use [ST_Plus2] some number of times to reduce [t2]
to a normal form, which must again be a term of the form [C
n2] for some [n2].
- Finally, we use [ST_PlusConstConst] one time to reduce [P (C
n1) (C n2)] to [C (n1 + n2)]. *)
(** To formalize this intuition, you'll need to use the congruence
lemmas from above (you might want to review them now, so that
you'll be able to recognize when they are useful), plus some basic
properties of [==>*]: that it is reflexive, transitive, and
includes [==>]. *)
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (eval__multistep_inf) *)
(** Write a detailed informal version of the proof of [eval__multistep].
(* FILL IN HERE *)
[]
*)
(** For the other direction, we need one lemma, which establishes a
relation between single-step reduction and big-step evaluation. *)
(** **** Exercise: 3 stars (step__eval) *)
Lemma step__eval : forall t t' n,
t ==> t' ->
t' \\ n ->
t \\ n.
Proof.
intros t t' n Hs. generalize dependent n.
(* FILL IN HERE *) Admitted.
(** [] *)
(** The fact that small-step reduction implies big-step evaluation is
now straightforward to prove, once it is stated correctly.
The proof proceeds by induction on the multi-step reduction
sequence that is buried in the hypothesis [normal_form_of t t']. *)
(** Make sure you understand the statement before you start to
work on the proof. *)
(** **** Exercise: 3 stars (multistep__eval) *)
Theorem multistep__eval : forall t t',
normal_form_of t t' -> exists n, t' = C n /\ t \\ n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ================================================================= *)
(** ** Additional Exercises *)
(** **** Exercise: 3 stars, optional (interp_tm) *)
(** Remember that we also defined big-step evaluation of terms as a
function [evalF]. Prove that it is equivalent to the existing
semantics. (Hint: we just proved that [eval] and [multistep] are
equivalent, so logically it doesn't matter which you choose.
One will be easier than the other, though!) *)
Theorem evalF_eval : forall t n,
evalF t = n <-> t \\ n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 starsM (combined_properties) *)
(** We've considered arithmetic and conditional expressions
separately. This exercise explores how the two interact. *)
Module Combined.
Inductive tm : Type :=
| C : nat -> tm
| P : tm -> tm -> tm
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n)
| v_true : value ttrue
| v_false : value tfalse.
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
where " t '==>' t' " := (step t t').
(** Earlier, we separately proved for both plus- and if-expressions...
- that the step relation was deterministic, and
- a strong progress lemma, stating that every term is either a
value or can take a step.
Prove or disprove these two properties for the combined language. *)
(* FILL IN HERE *)
End Combined.
(** [] *)
(* ################################################################# *)
(** * Small-Step Imp *)
(** Now for a more serious example: a small-step version of the Imp
operational semantics. *)
(** The small-step reduction relations for arithmetic and
boolean expressions are straightforward extensions of the tiny
language we've been working up to now. To make them easier to
read, we introduce the symbolic notations [==>a] and [==>b] for
the arithmetic and boolean step relations. *)
Inductive aval : aexp -> Prop :=
| av_num : forall n, aval (ANum n).
(** We are not actually going to bother to define boolean
values, since they aren't needed in the definition of [==>b]
below (why?), though they might be if our language were a bit
larger (why?). *)
Reserved Notation " t '/' st '==>a' t' "
(at level 40, st at level 39).
Inductive astep : state -> aexp -> aexp -> Prop :=
| AS_Id : forall st i,
AId i / st ==>a ANum (st i)
| AS_Plus : forall st n1 n2,
APlus (ANum n1) (ANum n2) / st ==>a ANum (n1 + n2)
| AS_Plus1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(APlus a1 a2) / st ==>a (APlus a1' a2)
| AS_Plus2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(APlus v1 a2) / st ==>a (APlus v1 a2')
| AS_Minus : forall st n1 n2,
(AMinus (ANum n1) (ANum n2)) / st ==>a (ANum (minus n1 n2))
| AS_Minus1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(AMinus a1 a2) / st ==>a (AMinus a1' a2)
| AS_Minus2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(AMinus v1 a2) / st ==>a (AMinus v1 a2')
| AS_Mult : forall st n1 n2,
(AMult (ANum n1) (ANum n2)) / st ==>a (ANum (mult n1 n2))
| AS_Mult1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(AMult a1 a2) / st ==>a (AMult a1' a2)
| AS_Mult2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(AMult v1 a2) / st ==>a (AMult v1 a2')
where " t '/' st '==>a' t' " := (astep st t t').
Reserved Notation " t '/' st '==>b' t' "
(at level 40, st at level 39).
Inductive bstep : state -> bexp -> bexp -> Prop :=
| BS_Eq : forall st n1 n2,
(BEq (ANum n1) (ANum n2)) / st ==>b
(if (beq_nat n1 n2) then BTrue else BFalse)
| BS_Eq1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(BEq a1 a2) / st ==>b (BEq a1' a2)
| BS_Eq2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(BEq v1 a2) / st ==>b (BEq v1 a2')
| BS_LtEq : forall st n1 n2,
(BLe (ANum n1) (ANum n2)) / st ==>b
(if (leb n1 n2) then BTrue else BFalse)
| BS_LtEq1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(BLe a1 a2) / st ==>b (BLe a1' a2)
| BS_LtEq2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(BLe v1 a2) / st ==>b (BLe v1 a2')
| BS_NotTrue : forall st,
(BNot BTrue) / st ==>b BFalse
| BS_NotFalse : forall st,
(BNot BFalse) / st ==>b BTrue
| BS_NotStep : forall st b1 b1',
b1 / st ==>b b1' ->
(BNot b1) / st ==>b (BNot b1')
| BS_AndTrueTrue : forall st,
(BAnd BTrue BTrue) / st ==>b BTrue
| BS_AndTrueFalse : forall st,
(BAnd BTrue BFalse) / st ==>b BFalse
| BS_AndFalse : forall st b2,
(BAnd BFalse b2) / st ==>b BFalse
| BS_AndTrueStep : forall st b2 b2',
b2 / st ==>b b2' ->
(BAnd BTrue b2) / st ==>b (BAnd BTrue b2')
| BS_AndStep : forall st b1 b1' b2,
b1 / st ==>b b1' ->
(BAnd b1 b2) / st ==>b (BAnd b1' b2)
where " t '/' st '==>b' t' " := (bstep st t t').
(** The semantics of commands is the interesting part. We need two
small tricks to make it work:
- We use [SKIP] as a "command value" -- i.e., a command that
has reached a normal form.
- An assignment command reduces to [SKIP] (and an updated
state).
- The sequencing command waits until its left-hand
subcommand has reduced to [SKIP], then throws it away so
that reduction can continue with the right-hand
subcommand.
- We reduce a [WHILE] command by transforming it into a
conditional followed by the same [WHILE]. *)
(** (There are other ways of achieving the effect of the latter
trick, but they all share the feature that the original [WHILE]
command needs to be saved somewhere while a single copy of the loop
body is being reduced.) *)
Reserved Notation " t '/' st '==>' t' '/' st' "
(at level 40, st at level 39, t' at level 39).
Inductive cstep : (com * state) -> (com * state) -> Prop :=
| CS_AssStep : forall st i a a',
a / st ==>a a' ->
(i ::= a) / st ==> (i ::= a') / st
| CS_Ass : forall st i n,
(i ::= (ANum n)) / st ==> SKIP / (t_update st i n)
| CS_SeqStep : forall st c1 c1' st' c2,
c1 / st ==> c1' / st' ->
(c1 ;; c2) / st ==> (c1' ;; c2) / st'
| CS_SeqFinish : forall st c2,
(SKIP ;; c2) / st ==> c2 / st
| CS_IfTrue : forall st c1 c2,
IFB BTrue THEN c1 ELSE c2 FI / st ==> c1 / st
| CS_IfFalse : forall st c1 c2,
IFB BFalse THEN c1 ELSE c2 FI / st ==> c2 / st
| CS_IfStep : forall st b b' c1 c2,
b / st ==>b b' ->
IFB b THEN c1 ELSE c2 FI / st
==> (IFB b' THEN c1 ELSE c2 FI) / st
| CS_While : forall st b c1,
(WHILE b DO c1 END) / st
==> (IFB b THEN (c1;; (WHILE b DO c1 END)) ELSE SKIP FI) / st
where " t '/' st '==>' t' '/' st' " := (cstep (t,st) (t',st')).
(* ################################################################# *)
(** * Concurrent Imp *)
(** Finally, to show the power of this definitional style, let's
enrich Imp with a new form of command that runs two subcommands in
parallel and terminates when both have terminated. To reflect the
unpredictability of scheduling, the actions of the subcommands may
be interleaved in any order, but they share the same memory and
can communicate by reading and writing the same variables. *)
Module CImp.
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
(* New: *)
| CPar : com -> com -> com.
Notation "'SKIP'" :=
CSkip.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' b 'THEN' c1 'ELSE' c2 'FI'" :=
(CIf b c1 c2) (at level 80, right associativity).
Notation "'PAR' c1 'WITH' c2 'END'" :=
(CPar c1 c2) (at level 80, right associativity).
Inductive cstep : (com * state) -> (com * state) -> Prop :=
(* Old part *)
| CS_AssStep : forall st i a a',
a / st ==>a a' ->
(i ::= a) / st ==> (i ::= a') / st
| CS_Ass : forall st i n,
(i ::= (ANum n)) / st ==> SKIP / (t_update st i n)
| CS_SeqStep : forall st c1 c1' st' c2,
c1 / st ==> c1' / st' ->
(c1 ;; c2) / st ==> (c1' ;; c2) / st'
| CS_SeqFinish : forall st c2,
(SKIP ;; c2) / st ==> c2 / st
| CS_IfTrue : forall st c1 c2,
(IFB BTrue THEN c1 ELSE c2 FI) / st ==> c1 / st
| CS_IfFalse : forall st c1 c2,
(IFB BFalse THEN c1 ELSE c2 FI) / st ==> c2 / st
| CS_IfStep : forall st b b' c1 c2,
b /st ==>b b' ->
(IFB b THEN c1 ELSE c2 FI) / st
==> (IFB b' THEN c1 ELSE c2 FI) / st
| CS_While : forall st b c1,
(WHILE b DO c1 END) / st
==> (IFB b THEN (c1;; (WHILE b DO c1 END)) ELSE SKIP FI) / st
(* New part: *)
| CS_Par1 : forall st c1 c1' c2 st',
c1 / st ==> c1' / st' ->
(PAR c1 WITH c2 END) / st ==> (PAR c1' WITH c2 END) / st'
| CS_Par2 : forall st c1 c2 c2' st',
c2 / st ==> c2' / st' ->
(PAR c1 WITH c2 END) / st ==> (PAR c1 WITH c2' END) / st'
| CS_ParDone : forall st,
(PAR SKIP WITH SKIP END) / st ==> SKIP / st
where " t '/' st '==>' t' '/' st' " := (cstep (t,st) (t',st')).
Definition cmultistep := multi cstep.
Notation " t '/' st '==>*' t' '/' st' " :=
(multi cstep (t,st) (t',st'))
(at level 40, st at level 39, t' at level 39).
(** Among the many interesting properties of this language is the fact
that the following program can terminate with the variable [X] set
to any value. *)
Definition par_loop : com :=
PAR
Y ::= ANum 1
WITH
WHILE BEq (AId Y) (ANum 0) DO
X ::= APlus (AId X) (ANum 1)
END
END.
(** In particular, it can terminate with [X] set to [0]: *)
Example par_loop_example_0:
exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = 0.
Proof.
eapply ex_intro. split.
unfold par_loop.
eapply multi_step. apply CS_Par1.
apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
eapply multi_refl.
reflexivity. Qed.
(** It can also terminate with [X] set to [2]: *)
Example par_loop_example_2:
exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = 2.
Proof.
eapply ex_intro. split.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfTrue.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_SeqFinish.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfTrue.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_Ass.
eapply multi_step. apply CS_Par1. apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_SeqFinish.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
eapply multi_refl.
reflexivity. Qed.
(** More generally... *)
(** **** Exercise: 3 stars, optional (par_body_n__Sn) *)
Lemma par_body_n__Sn : forall n st,
st X = n /\ st Y = 0 ->
par_loop / st ==>* par_loop / (t_update st X (S n)).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (par_body_n) *)
Lemma par_body_n : forall n st,
st X = 0 /\ st Y = 0 ->
exists st',
par_loop / st ==>* par_loop / st' /\ st' X = n /\ st' Y = 0.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** ... the above loop can exit with [X] having any value
whatsoever. *)
Theorem par_loop_any_X:
forall n, exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = n.
Proof.
intros n.
destruct (par_body_n n empty_state).
split; unfold t_update; reflexivity.
rename x into st.
inversion H as [H' [HX HY]]; clear H.
exists (t_update st Y 1). split.
eapply multi_trans with (par_loop,st). apply H'.
eapply multi_step. apply CS_Par1. apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id. rewrite t_update_eq.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
apply multi_refl.
rewrite t_update_neq. assumption. intro X; inversion X.
Qed.
End CImp.
(* ################################################################# *)
(** * A Small-Step Stack Machine *)
(** Our last example is a small-step semantics for the stack machine
example from the \CHAPV1{Imp} chapter of _Logical Foundations_. *)
Definition stack := list nat.
Definition prog := list sinstr.
Inductive stack_step : state -> prog * stack -> prog * stack -> Prop :=
| SS_Push : forall st stk n p',
stack_step st (SPush n :: p', stk) (p', n :: stk)
| SS_Load : forall st stk i p',
stack_step st (SLoad i :: p', stk) (p', st i :: stk)
| SS_Plus : forall st stk n m p',
stack_step st (SPlus :: p', n::m::stk) (p', (m+n)::stk)
| SS_Minus : forall st stk n m p',
stack_step st (SMinus :: p', n::m::stk) (p', (m-n)::stk)
| SS_Mult : forall st stk n m p',
stack_step st (SMult :: p', n::m::stk) (p', (m*n)::stk).
Theorem stack_step_deterministic : forall st,
deterministic (stack_step st).
Proof.
unfold deterministic. intros st x y1 y2 H1 H2.
induction H1; inversion H2; reflexivity.
Qed.
Definition stack_multistep st := multi (stack_step st).
(** **** Exercise: 3 stars, advanced (compiler_is_correct) *)
(** Remember the definition of [compile] for [aexp] given in the
\CHAPV1{Imp} chapter of _Logical Foundations_. We want now to
prove [compile] correct with respect to the stack machine.
State what it means for the compiler to be correct according to
the stack machine small step semantics and then prove it. *)
Definition compiler_is_correct_statement : Prop
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Theorem compiler_is_correct : compiler_is_correct_statement.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** $Date: 2017-05-24 10:56:51 -0400 (Wed, 24 May 2017) $ *)
|
//////////////////////////////////////////////////////////////////////////////////
// NPCG_Toggle_way_CE_timer for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: NPCG_Toggle_way_CE_timer
// Module Name: NPCG_Toggle_way_CE_timer
// File Name: NPCG_Toggle_way_CE_timer.v
//
// Version: v1.0.0
//
// Description: Way chip enable timer
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module NPCG_Toggle_way_CE_timer
#
(
parameter NumberOfWays = 8
)
(
iSystemClock ,
iReset ,
iWorkingWay ,
ibCMDLast ,
ibCMDLast_SCC ,
iTargetWay ,
oCMDHold
);
input iSystemClock ;
input iReset ;
input [NumberOfWays - 1:0] iWorkingWay ;
input ibCMDLast ;
input ibCMDLast_SCC ;
input [NumberOfWays - 1:0] iTargetWay ;
output oCMDHold ;
wire wWay0_Deasserted ;
wire wWay1_Deasserted ;
wire wWay2_Deasserted ;
wire wWay3_Deasserted ;
wire wWay4_Deasserted ;
wire wWay5_Deasserted ;
wire wWay6_Deasserted ;
wire wWay7_Deasserted ;
reg [3:0] rWay0_Timer ;
reg [3:0] rWay1_Timer ;
reg [3:0] rWay2_Timer ;
reg [3:0] rWay3_Timer ;
reg [3:0] rWay4_Timer ;
reg [3:0] rWay5_Timer ;
reg [3:0] rWay6_Timer ;
reg [3:0] rWay7_Timer ;
wire wWay0_Ready ;
wire wWay1_Ready ;
wire wWay2_Ready ;
wire wWay3_Ready ;
wire wWay4_Ready ;
wire wWay5_Ready ;
wire wWay6_Ready ;
wire wWay7_Ready ;
wire wWay0_Targeted ;
wire wWay1_Targeted ;
wire wWay2_Targeted ;
wire wWay3_Targeted ;
wire wWay4_Targeted ;
wire wWay5_Targeted ;
wire wWay6_Targeted ;
wire wWay7_Targeted ;
assign wWay0_Deasserted = (~ibCMDLast_SCC) & ibCMDLast & iWorkingWay[0];
assign wWay1_Deasserted = (~ibCMDLast_SCC) & ibCMDLast & iWorkingWay[1];
assign wWay2_Deasserted = (~ibCMDLast_SCC) & ibCMDLast & iWorkingWay[2];
assign wWay3_Deasserted = (~ibCMDLast_SCC) & ibCMDLast & iWorkingWay[3];
assign wWay4_Deasserted = (~ibCMDLast_SCC) & ibCMDLast & iWorkingWay[4];
assign wWay5_Deasserted = (~ibCMDLast_SCC) & ibCMDLast & iWorkingWay[5];
assign wWay6_Deasserted = (~ibCMDLast_SCC) & ibCMDLast & iWorkingWay[6];
assign wWay7_Deasserted = (~ibCMDLast_SCC) & ibCMDLast & iWorkingWay[7];
assign wWay0_Ready = (rWay0_Timer[3:0] == 4'b1110); // 14 cycle -> 140 ns
assign wWay1_Ready = (rWay1_Timer[3:0] == 4'b1110);
assign wWay2_Ready = (rWay2_Timer[3:0] == 4'b1110);
assign wWay3_Ready = (rWay3_Timer[3:0] == 4'b1110);
assign wWay4_Ready = (rWay4_Timer[3:0] == 4'b1110);
assign wWay5_Ready = (rWay5_Timer[3:0] == 4'b1110);
assign wWay6_Ready = (rWay6_Timer[3:0] == 4'b1110);
assign wWay7_Ready = (rWay7_Timer[3:0] == 4'b1110);
always @ (posedge iSystemClock, posedge iReset) begin
if (iReset) begin
rWay0_Timer[3:0] <= 4'b1110;
rWay1_Timer[3:0] <= 4'b1110;
rWay2_Timer[3:0] <= 4'b1110;
rWay3_Timer[3:0] <= 4'b1110;
rWay4_Timer[3:0] <= 4'b1110;
rWay5_Timer[3:0] <= 4'b1110;
rWay6_Timer[3:0] <= 4'b1110;
rWay7_Timer[3:0] <= 4'b1110;
end else begin
rWay0_Timer[3:0] <= (wWay0_Deasserted)? 4'b0000:((wWay0_Ready)? (rWay0_Timer[3:0]):(rWay0_Timer[3:0] + 1'b1));
rWay1_Timer[3:0] <= (wWay1_Deasserted)? 4'b0000:((wWay1_Ready)? (rWay1_Timer[3:0]):(rWay1_Timer[3:0] + 1'b1));
rWay2_Timer[3:0] <= (wWay2_Deasserted)? 4'b0000:((wWay2_Ready)? (rWay2_Timer[3:0]):(rWay2_Timer[3:0] + 1'b1));
rWay3_Timer[3:0] <= (wWay3_Deasserted)? 4'b0000:((wWay3_Ready)? (rWay3_Timer[3:0]):(rWay3_Timer[3:0] + 1'b1));
rWay4_Timer[3:0] <= (wWay4_Deasserted)? 4'b0000:((wWay4_Ready)? (rWay4_Timer[3:0]):(rWay4_Timer[3:0] + 1'b1));
rWay5_Timer[3:0] <= (wWay5_Deasserted)? 4'b0000:((wWay5_Ready)? (rWay5_Timer[3:0]):(rWay5_Timer[3:0] + 1'b1));
rWay6_Timer[3:0] <= (wWay6_Deasserted)? 4'b0000:((wWay6_Ready)? (rWay6_Timer[3:0]):(rWay6_Timer[3:0] + 1'b1));
rWay7_Timer[3:0] <= (wWay7_Deasserted)? 4'b0000:((wWay7_Ready)? (rWay7_Timer[3:0]):(rWay7_Timer[3:0] + 1'b1));
end
end
assign wWay0_Targeted = iTargetWay[0];
assign wWay1_Targeted = iTargetWay[1];
assign wWay2_Targeted = iTargetWay[2];
assign wWay3_Targeted = iTargetWay[3];
assign wWay4_Targeted = iTargetWay[4];
assign wWay5_Targeted = iTargetWay[5];
assign wWay6_Targeted = iTargetWay[6];
assign wWay7_Targeted = iTargetWay[7];
assign oCMDHold = (wWay0_Targeted & (~wWay0_Ready)) |
(wWay1_Targeted & (~wWay1_Ready)) |
(wWay2_Targeted & (~wWay2_Ready)) |
(wWay3_Targeted & (~wWay3_Ready)) |
(wWay4_Targeted & (~wWay4_Ready)) |
(wWay5_Targeted & (~wWay5_Ready)) |
(wWay6_Targeted & (~wWay6_Ready)) |
(wWay7_Targeted & (~wWay7_Ready)) ;
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: Sdram_FIFO.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module Sdram_FIFO (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output rdempty;
output [9:0] rdusedw;
output wrfull;
output [9:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [15:0] sub_wire1;
wire sub_wire2;
wire [9:0] sub_wire3;
wire [9:0] sub_wire4;
wire wrfull = sub_wire0;
wire [15:0] q = sub_wire1[15:0];
wire rdempty = sub_wire2;
wire [9:0] wrusedw = sub_wire3[9:0];
wire [9:0] rdusedw = sub_wire4[9:0];
dcfifo dcfifo_component (
.rdclk (rdclk),
.wrclk (wrclk),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.wrfull (sub_wire0),
.q (sub_wire1),
.rdempty (sub_wire2),
.wrusedw (sub_wire3),
.rdusedw (sub_wire4),
.rdfull (),
.wrempty ());
defparam
dcfifo_component.add_ram_output_register = "OFF",
dcfifo_component.clocks_are_synchronized = "FALSE",
dcfifo_component.intended_device_family = "Cyclone",
dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
dcfifo_component.lpm_numwords = 1024,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 16,
dcfifo_component.lpm_widthu = 10,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "1024"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "16"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: rdusedw 0 0 10 0 OUTPUT NODEFVAL "rdusedw[9..0]"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 10 0 OUTPUT NODEFVAL "wrusedw[9..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 10 0 @rdusedw 0 0 10 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 10 0 @wrusedw 0 0 10 0
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_wave*.jpg FALSE
|
module top;
reg pass;
wire [2:-1] vec1;
wire [2:-1] vec2;
wire [2:-1] vec3;
wire [2:-1] vec4;
wire [2:-1] vec5;
wire [2:-1] vec6;
assign vec1 = 4'bxxxx;
assign vec2 = 4'bxxxx;
assign vec3 = 4'bxxxx;
assign vec4 = 4'bxxxx;
assign vec5 = 4'bxxxx;
assign vec6 = 4'bxxxx;
assign vec1[1'bx] = 1'b1;
assign vec2[1'bx:0] = 1'b1;
assign vec3[0:1'bx] = 1'b1;
assign vec4[1'bx:1'bx] = 1'b1;
assign vec5[1'bx+:1] = 1'b1;
assign vec6[1'bx-:1] = 1'b1;
initial begin
pass = 1'b1;
if (vec1 !== 4'bxxx) begin
$display("Failed vec1, expected 4'bxxxx, got %b", vec1);
pass = 1'b0;
end
if (vec2 !== 4'bxxx) begin
$display("Failed vec2, expected 4'bxxxx, got %b", vec2);
pass = 1'b0;
end
if (vec3 !== 4'bxxx) begin
$display("Failed vec3, expected 4'bxxxx, got %b", vec3);
pass = 1'b0;
end
if (vec4 !== 4'bxxx) begin
$display("Failed vec4, expected 4'bxxxx, got %b", vec4);
pass = 1'b0;
end
if (vec5 !== 4'bxxx) begin
$display("Failed vec5, expected 4'bxxxx, got %b", vec5);
pass = 1'b0;
end
if (vec6 !== 4'bxxx) begin
$display("Failed vec6, expected 4'bxxxx, got %b", vec6);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// client_request_get O 70 reg
// RDY_client_request_get O 1 reg
// RDY_client_response_put O 1 reg
// RDY_server_request_put O 1 reg
// server_response_get O 65 reg
// RDY_server_response_get O 1 reg
// trace_data_out_get O 427 reg
// RDY_trace_data_out_get O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// client_response_put I 65 reg
// server_request_put I 70 reg
// EN_client_response_put I 1
// EN_server_request_put I 1
// EN_client_request_get I 1
// EN_server_response_get I 1
// EN_trace_data_out_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkDM_GPR_Tap(CLK,
RST_N,
EN_client_request_get,
client_request_get,
RDY_client_request_get,
client_response_put,
EN_client_response_put,
RDY_client_response_put,
server_request_put,
EN_server_request_put,
RDY_server_request_put,
EN_server_response_get,
server_response_get,
RDY_server_response_get,
EN_trace_data_out_get,
trace_data_out_get,
RDY_trace_data_out_get);
input CLK;
input RST_N;
// actionvalue method client_request_get
input EN_client_request_get;
output [69 : 0] client_request_get;
output RDY_client_request_get;
// action method client_response_put
input [64 : 0] client_response_put;
input EN_client_response_put;
output RDY_client_response_put;
// action method server_request_put
input [69 : 0] server_request_put;
input EN_server_request_put;
output RDY_server_request_put;
// actionvalue method server_response_get
input EN_server_response_get;
output [64 : 0] server_response_get;
output RDY_server_response_get;
// actionvalue method trace_data_out_get
input EN_trace_data_out_get;
output [426 : 0] trace_data_out_get;
output RDY_trace_data_out_get;
// signals for module outputs
wire [426 : 0] trace_data_out_get;
wire [69 : 0] client_request_get;
wire [64 : 0] server_response_get;
wire RDY_client_request_get,
RDY_client_response_put,
RDY_server_request_put,
RDY_server_response_get,
RDY_trace_data_out_get;
// ports of submodule f_req_in
wire [69 : 0] f_req_in$D_IN, f_req_in$D_OUT;
wire f_req_in$CLR,
f_req_in$DEQ,
f_req_in$EMPTY_N,
f_req_in$ENQ,
f_req_in$FULL_N;
// ports of submodule f_req_out
wire [69 : 0] f_req_out$D_IN, f_req_out$D_OUT;
wire f_req_out$CLR,
f_req_out$DEQ,
f_req_out$EMPTY_N,
f_req_out$ENQ,
f_req_out$FULL_N;
// ports of submodule f_rsp
wire [64 : 0] f_rsp$D_IN, f_rsp$D_OUT;
wire f_rsp$CLR, f_rsp$DEQ, f_rsp$EMPTY_N, f_rsp$ENQ, f_rsp$FULL_N;
// ports of submodule f_trace_data
wire [426 : 0] f_trace_data$D_IN, f_trace_data$D_OUT;
wire f_trace_data$CLR,
f_trace_data$DEQ,
f_trace_data$EMPTY_N,
f_trace_data$ENQ,
f_trace_data$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_request,
CAN_FIRE_client_request_get,
CAN_FIRE_client_response_put,
CAN_FIRE_server_request_put,
CAN_FIRE_server_response_get,
CAN_FIRE_trace_data_out_get,
WILL_FIRE_RL_request,
WILL_FIRE_client_request_get,
WILL_FIRE_client_response_put,
WILL_FIRE_server_request_put,
WILL_FIRE_server_response_get,
WILL_FIRE_trace_data_out_get;
// actionvalue method client_request_get
assign client_request_get = f_req_out$D_OUT ;
assign RDY_client_request_get = f_req_out$EMPTY_N ;
assign CAN_FIRE_client_request_get = f_req_out$EMPTY_N ;
assign WILL_FIRE_client_request_get = EN_client_request_get ;
// action method client_response_put
assign RDY_client_response_put = f_rsp$FULL_N ;
assign CAN_FIRE_client_response_put = f_rsp$FULL_N ;
assign WILL_FIRE_client_response_put = EN_client_response_put ;
// action method server_request_put
assign RDY_server_request_put = f_req_in$FULL_N ;
assign CAN_FIRE_server_request_put = f_req_in$FULL_N ;
assign WILL_FIRE_server_request_put = EN_server_request_put ;
// actionvalue method server_response_get
assign server_response_get = f_rsp$D_OUT ;
assign RDY_server_response_get = f_rsp$EMPTY_N ;
assign CAN_FIRE_server_response_get = f_rsp$EMPTY_N ;
assign WILL_FIRE_server_response_get = EN_server_response_get ;
// actionvalue method trace_data_out_get
assign trace_data_out_get = f_trace_data$D_OUT ;
assign RDY_trace_data_out_get = f_trace_data$EMPTY_N ;
assign CAN_FIRE_trace_data_out_get = f_trace_data$EMPTY_N ;
assign WILL_FIRE_trace_data_out_get = EN_trace_data_out_get ;
// submodule f_req_in
FIFO2 #(.width(32'd70), .guarded(32'd1)) f_req_in(.RST(RST_N),
.CLK(CLK),
.D_IN(f_req_in$D_IN),
.ENQ(f_req_in$ENQ),
.DEQ(f_req_in$DEQ),
.CLR(f_req_in$CLR),
.D_OUT(f_req_in$D_OUT),
.FULL_N(f_req_in$FULL_N),
.EMPTY_N(f_req_in$EMPTY_N));
// submodule f_req_out
FIFO2 #(.width(32'd70), .guarded(32'd1)) f_req_out(.RST(RST_N),
.CLK(CLK),
.D_IN(f_req_out$D_IN),
.ENQ(f_req_out$ENQ),
.DEQ(f_req_out$DEQ),
.CLR(f_req_out$CLR),
.D_OUT(f_req_out$D_OUT),
.FULL_N(f_req_out$FULL_N),
.EMPTY_N(f_req_out$EMPTY_N));
// submodule f_rsp
FIFO2 #(.width(32'd65), .guarded(32'd1)) f_rsp(.RST(RST_N),
.CLK(CLK),
.D_IN(f_rsp$D_IN),
.ENQ(f_rsp$ENQ),
.DEQ(f_rsp$DEQ),
.CLR(f_rsp$CLR),
.D_OUT(f_rsp$D_OUT),
.FULL_N(f_rsp$FULL_N),
.EMPTY_N(f_rsp$EMPTY_N));
// submodule f_trace_data
FIFO2 #(.width(32'd427), .guarded(32'd1)) f_trace_data(.RST(RST_N),
.CLK(CLK),
.D_IN(f_trace_data$D_IN),
.ENQ(f_trace_data$ENQ),
.DEQ(f_trace_data$DEQ),
.CLR(f_trace_data$CLR),
.D_OUT(f_trace_data$D_OUT),
.FULL_N(f_trace_data$FULL_N),
.EMPTY_N(f_trace_data$EMPTY_N));
// rule RL_request
assign CAN_FIRE_RL_request =
f_req_in$EMPTY_N && f_req_out$FULL_N &&
(!f_req_in$D_OUT[69] || f_trace_data$FULL_N) ;
assign WILL_FIRE_RL_request = CAN_FIRE_RL_request ;
// submodule f_req_in
assign f_req_in$D_IN = server_request_put ;
assign f_req_in$ENQ = EN_server_request_put ;
assign f_req_in$DEQ = CAN_FIRE_RL_request ;
assign f_req_in$CLR = 1'b0 ;
// submodule f_req_out
assign f_req_out$D_IN = f_req_in$D_OUT ;
assign f_req_out$ENQ = CAN_FIRE_RL_request ;
assign f_req_out$DEQ = EN_client_request_get ;
assign f_req_out$CLR = 1'b0 ;
// submodule f_rsp
assign f_rsp$D_IN = client_response_put ;
assign f_rsp$ENQ = EN_client_response_put ;
assign f_rsp$DEQ = EN_server_response_get ;
assign f_rsp$CLR = 1'b0 ;
// submodule f_trace_data
assign f_trace_data$D_IN =
{ 102'h035555555555555554AAAAAAAA,
f_req_in$D_OUT[68:0],
256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ;
assign f_trace_data$ENQ = WILL_FIRE_RL_request && f_req_in$D_OUT[69] ;
assign f_trace_data$DEQ = EN_trace_data_out_get ;
assign f_trace_data$CLR = 1'b0 ;
endmodule // mkDM_GPR_Tap
|
/*8888b. 8888888b. d8888 888b d888
d88P Y88b 888 Y88b d88888 8888b d8888
Y88b. 888 888 d88P888 88888b.d88888
"Y888b. 888 d88P d88P 888 888Y88888P888
"Y88b. 8888888P" d88P 888 888 Y888P 888
"888 888 T88b d88P 888 888 Y8P 888
Y88b d88P 888 T88b d8888888888 888 " 888
"Y8888P" 888 T88b d88P 888 888 888
8888888888 8888888 8888888888 .d88888b.
888 888 888 d88P" "Y88b
888 888 888 888 888
8888888 888 8888888 888 888
888 888 888 888 888
888 888 888 888 888
888 888 888 Y88b. .d88P
888 8888888 888 "Y88888*/
/////////////////////////////////////////////////////////////////////
// Fifo implemented on a single port SRAM. Due to the single port,
// the write operation and read operation have to be scheduled
// The catch write and catch read state are taking care of that point
// to sequentially write and read in case of simultaneous request
// from the writting and reading devices. The busy signal indicate
// that the fifo won't accept any write or read request. the writter
// and reader device have to consider the busy signal.
/////////////////////////////////////////////////////////////////////
module fifo_SRAM(
// common
input wire clk,
input wire rst_n,
// Sram pins
output wire [19:0] Addr,
inout [15:0] IO,
output reg WE_n, // Write enable_n
output reg OE_n, // Output enable_n
output wire CE_n, // Chip enable_n
output wire LB_n, // Lower Byte Control_n
output wire UB_n, // Upper Byte Control_n
// user interface
input wire [31:0] dataIn,
output wire [31:0] dataOut,
input wire user_we,
input wire user_re,
output reg data_r_rdy,
output reg busy,
output reg full,
output reg [21:0] available,
output wire [7:0] debug
);
parameter S_RESET = 4'd0;
parameter S_IDLE = 4'd1;
parameter S_CATCH_WE_1 = 4'd2;
parameter S_CATCH_WE_2 = 4'd3;
parameter S_CATCH_RE_1 = 4'd4;
parameter S_CATCH_RE_2 = 4'd5;
parameter S_WRITE_UP_READY = 4'd6;
parameter S_WRITE_UP = 4'd7;
parameter S_WRITE_LOW_READY = 4'd8;
parameter S_WRITE_LOW = 4'd9;
parameter S_READ_READY = 4'd10;
parameter S_READ_UP = 4'd11;
parameter S_READ_LOW = 4'd12;
parameter S_READ_DONE = 4'd13;
parameter MUX_FPGA_TO_SRAM = 1'b1; // tristate parameter sram data
parameter MUX_SRAM_TO_FPGA = 1'b0; // tristate parameter sram data
// max size 1024*1024 halfwords (16 bits) with a margin of 4'hF (F_FFFF - 0_000F)
parameter BUFFER_SIZE = 21'b 1_0000_0000_0000_0000_0000; // = 2^20 (or 1 << 20) = 2 MB
/*88888b. 8888888888 .d8888b. 888
888 "Y88b 888 d88P Y88b 888
888 888 888 888 888 888
888 888 8888888 888 888
888 888 888 888 888
888 888 888 888 888 888
888 .d88P 888 Y88b d88P 888
8888888P" 8888888888 "Y8888P" 888888*/
reg [3:0] next_state;
reg [19:0] read_addr;
reg [19:0] write_addr;
reg block;
reg DAT_MUX;
reg [31:0] data_IO_out_reg;
reg [31:0] data_in_reg;
reg [15:0] IO_to_SRAM;
wire [15:0] IO_from_SRAM;
wire [15:0] out_enable;
reg read_write_reg;
reg write_fifo;
reg read_fifo_start;
reg read_fifo;
wire rollback_we;
wire rollback_re;
/*888 .d8888b. .d8888b. 8888888 .d8888b. 888b 888
d88888 d88P Y88b d88P Y88b 888 d88P Y88b 8888b 888
d88P888 Y88b. Y88b. 888 888 888 88888b 888
d88P 888 "Y888b. "Y888b. 888 888 888Y88b 888
d88P 888 "Y88b. "Y88b. 888 888 88888 888 Y88b888
d88P 888 "888 "888 888 888 888 888 Y88888
d8888888888 Y88b d88P Y88b d88P 888 Y88b d88P 888 Y8888
d88P 888 "Y8888P" "Y8888P" 8888888 "Y8888P88 888 Y8*/
assign rollback_we = (write_addr == 20'hF_FFFF) ? 1'b1 : 1'b0;
assign rollback_re = (read_addr == 20'hF_FFFF) ? 1'b1 : 1'b0;
assign debug = {2'b0, rollback_re, rollback_we, next_state};
assign Addr = (DAT_MUX == MUX_FPGA_TO_SRAM) ? {write_addr} : {read_addr};
// IO tri-state write to RAM ? write to RAM High imp for reading from RAM
assign IO = (DAT_MUX == MUX_FPGA_TO_SRAM) ? IO_to_SRAM : 16'bzzzz_zzzz_zzzz_zzzz;
assign IO_from_SRAM = IO;
assign CE_n = 0; // Chip enable_n
assign UB_n = 0; // Upper Byte Control
assign LB_n = 0; // Lower Byte Control
// Data out Reg (to Read from RAM)
assign dataOut = data_IO_out_reg;
/*88888b. 8888888888 .d8888b.
888 Y88b 888 d88P Y88b
888 888 888 888 888
888 d88P 8888888 888
8888888P" 888 888 88888
888 T88b 888 888 888
888 T88b 888 Y88b d88P
888 T88b 8888888888 "Y8888P*/
// full reg
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
full <= 0;
end
else begin
full <= (available > ((BUFFER_SIZE >> 1) - 21'd512) ) ? 1'b1 : 1'b0;
end
end
// available data in the Fifo
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
available <= 0;
end
else begin
if (write_addr > read_addr)
available <= (write_addr - read_addr) >> 1;
else if (write_addr < read_addr)
available <= (BUFFER_SIZE + write_addr - read_addr) >> 1;
else
available <= 0;
end
end
// Data in Reg
always @(posedge clk or negedge rst_n) begin
if (!rst_n) data_in_reg <= 0;
else
if (user_we) data_in_reg <= dataIn;
else data_in_reg <= data_in_reg;
end
/*88888888 .d8888b. 888b d888
888 d88P Y88b 8888b d8888
888 Y88b. 88888b.d88888
8888888 "Y888b. 888Y88888P888
888 "Y88b. 888 Y888P 888
888 "888 888 Y8P 888
888 Y88b d88P 888 " 888
888 "Y8888P" 888 8*/
// FSM State register
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
next_state <= S_RESET;
DAT_MUX <= MUX_SRAM_TO_FPGA;
WE_n <= 1; // Write disabled
busy <= 0;
data_r_rdy <= 0;
write_addr <= 0;
read_addr <= 0;
read_write_reg <= 0;
data_IO_out_reg <= 0;
end
else begin
case(next_state)
////////////////////////////////////////////////////////
//////////////////// RESET /////////////////////////////
////////////////////////////////////////////////////////
S_RESET: begin // state no : 0
next_state <= S_IDLE;
DAT_MUX <= MUX_SRAM_TO_FPGA;
WE_n <= 1; // Write disabled
busy <= 0;
data_r_rdy <= 0;
write_addr <= 0;
read_addr <= 0;
read_write_reg <= 0;
data_IO_out_reg <= 0;
end
////////////////////////////////////////////////////////
///////////////////// IDLE /////////////////////////////
////////////////////////////////////////////////////////
S_IDLE: begin // state no : 1
data_r_rdy <= 0;
case ({user_re, user_we})
2'b00: begin // nothing
next_state <= S_IDLE;
busy <= 0;
read_write_reg <= 0;
end
2'b01: begin // write
next_state <= S_CATCH_RE_1;
busy <= 1;
read_write_reg <= 0;
end
2'b10: begin // read
next_state <= S_CATCH_WE_1;
busy <= 1;
read_write_reg <= 0;
end
2'b11: begin // write read
next_state <= S_WRITE_UP_READY;
DAT_MUX = MUX_FPGA_TO_SRAM;
busy <= 1;
read_write_reg <= 1;
end
default: begin
next_state <= S_IDLE;
busy <= 1;
read_write_reg <= 0;
end
endcase
end
////////////////////////////////////////////////////////
//////////////////// CATCH /////////////////////////////
////////////////////////////////////////////////////////
S_CATCH_WE_1: begin // state no : 2
if (user_we) begin
next_state <= S_WRITE_UP_READY;
DAT_MUX = MUX_FPGA_TO_SRAM;
read_write_reg <= 1;
end
else next_state <= S_CATCH_WE_2;
end
////////////////////////////////////////////////////////
S_CATCH_WE_2: begin // state no : 3
if (user_we) begin
next_state <= S_WRITE_UP_READY;
DAT_MUX = MUX_FPGA_TO_SRAM;
read_write_reg <= 1;
end
else next_state <= S_READ_READY;
end
////////////////////////////////////////////////////////
S_CATCH_RE_1: begin // state no : 4
if (user_re) begin
next_state <= S_WRITE_UP_READY;
DAT_MUX = MUX_FPGA_TO_SRAM;
read_write_reg <= 1;
end
else next_state <= S_CATCH_RE_2;
end
////////////////////////////////////////////////////////
S_CATCH_RE_2: begin // state no : 5
next_state <= S_WRITE_UP_READY;
DAT_MUX = MUX_FPGA_TO_SRAM;
if (user_re) read_write_reg <= 1;
end
////////////////////////////////////////////////////////
/////////////////// WRITE //////////////////////////////
////////////////////////////////////////////////////////
S_WRITE_UP_READY: begin // state no : 6
next_state <= S_WRITE_UP;
DAT_MUX <= MUX_FPGA_TO_SRAM;
WE_n <= 0;
OE_n <= 1;
IO_to_SRAM <= data_in_reg[31:16];
end
////////////////////////////////////////////////////////
S_WRITE_UP: begin // state no : 7
next_state <= S_WRITE_LOW_READY;
DAT_MUX <= MUX_FPGA_TO_SRAM;
WE_n <= 1;
OE_n <= 0;
write_addr <= write_addr + 20'd1;
end
////////////////////////////////////////////////////////
S_WRITE_LOW_READY: begin // state no : 8
next_state <= S_WRITE_LOW;
DAT_MUX <= MUX_FPGA_TO_SRAM;
WE_n <= 0;
OE_n <= 1;
IO_to_SRAM <= data_in_reg[15:0];
end
////////////////////////////////////////////////////////
S_WRITE_LOW: begin // state no : 9
if (read_write_reg) next_state <= S_READ_READY;
else next_state <= S_IDLE;
DAT_MUX <= MUX_SRAM_TO_FPGA;
WE_n <= 1;
OE_n <= 0;
write_addr <= write_addr + 20'd1;
end
////////////////////////////////////////////////////////
//////////////////// READ //////////////////////////////
////////////////////////////////////////////////////////
S_READ_READY: begin // state no : 10
next_state <= S_READ_UP;
WE_n <= 1;
OE_n <= 0;
DAT_MUX <= MUX_SRAM_TO_FPGA;
end
////////////////////////////////////////////////////////
S_READ_UP: begin // state no : 11
next_state <= S_READ_LOW;
data_IO_out_reg <= {IO_from_SRAM, 16'b0};
read_addr <= read_addr + 20'd1;
end
////////////////////////////////////////////////////////
S_READ_LOW: begin // state no : 12
data_IO_out_reg <= {data_IO_out_reg[31:16], IO_from_SRAM};
next_state <= S_READ_DONE;
read_addr <= read_addr + 20'd1;
end
////////////////////////////////////////////////////////
S_READ_DONE: begin // state no : 13
next_state <= S_IDLE;
data_r_rdy <= 1;
end
////////////////////////////////////////////////////////
////////////////// DEFAULT /////////////////////////////
////////////////////////////////////////////////////////
default : begin
next_state <= S_IDLE;
end
endcase
end
end
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_1kx16.v
// Megafunction Name(s):
// scfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_1kx16 (
aclr,
clock,
data,
rdreq,
wrreq,
almost_empty,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [15:0] data;
input rdreq;
input wrreq;
output almost_empty;
output empty;
output full;
output [15:0] q;
output [9:0] usedw;
wire [9:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [15:0] sub_wire3;
wire sub_wire4;
wire [9:0] usedw = sub_wire0[9:0];
wire empty = sub_wire1;
wire almost_empty = sub_wire2;
wire [15:0] q = sub_wire3[15:0];
wire full = sub_wire4;
scfifo scfifo_component (
.rdreq (rdreq),
.aclr (aclr),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.empty (sub_wire1),
.almost_empty (sub_wire2),
.q (sub_wire3),
.full (sub_wire4)
// synopsys translate_off
,
.sclr (),
.almost_full ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.almost_empty_value = 504,
scfifo_component.intended_device_family = "Cyclone",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
scfifo_component.lpm_numwords = 1024,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 16,
scfifo_component.lpm_widthu = 10,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "504"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "1024"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "504"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0
// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_wave*.jpg FALSE
|
module hps_tabby(
input coe_M1_RSTN, coe_M1_CLK,
input [21:0] coe_M1_ADDR,
inout [31:0] coe_M1_DATA,
input [3:0] coe_M1_CSN,
input [3:0] coe_M1_BEN,
input coe_M1_RDN, coe_M1_WRN,
output coe_M1_WAITN,
output [9:0] coe_M1_EINT,
output rso_MRST_reset,
output cso_MCLK_clk,
output cso_H1CLK_clk,
output cso_H2CLK_clk,
output [31:0] avm_M1_writedata,
input [31:0] avm_M1_readdata,
output [29:0] avm_M1_address,
output [3:0] avm_M1_byteenable,
output avm_M1_write,
output avm_M1_read,
output avm_M1_begintransfer,
input avm_M1_readdatavalid,
input avm_M1_waitrequest,
input [9:0] inr_EVENTS_irq
);
// rSMC_SETUP(0) = (0 << 24) + (2 << 16) + (0 << 8) + (0 << 0);
// rSMC_PULSE(0) = (0 << 24) + (6 << 16) + (0 << 8) + (2 << 0);
// rSMC_CYCLE(0) = (0 << 23) + (8 << 16) + (0 << 7) + (6 << 0);
// rSMC_MODE(0) = (0 << 28) + (0 << 24) + (1 << 20) + (8 << 16) + (2 << 12) + (0 << 8) + (2 << 4) + (1 << 1) + (1 << 0);
assign rso_MRST_reset = ~(pll_locked & coe_M1_RSTN);
assign cso_MCLK_clk = pll_clocks[0]; //133.33 MHz
assign cso_H1CLK_clk = coe_M1_CLK; //66.66 MHz
assign cso_H2CLK_clk = pll_clocks[1]; //200.00 MHz
assign coe_M1_DATA = ((!coe_M1_RDN) && (coe_M1_CSN != 4'b1111) && (!rso_MRST_reset)) ? h_rdata : 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
assign coe_M1_WAITN = (~h_wait) | (rso_MRST_reset);
assign coe_M1_EINT = inr_EVENTS_irq;
assign avm_M1_writedata = q_wdata;
assign q_rdata = avm_M1_readdata;
assign avm_M1_address = q_addr;
assign avm_M1_byteenable = q_be;
assign avm_M1_write = q_wr;
assign avm_M1_read = q_rd;
assign avm_M1_begintransfer = q_btrans;
assign q_rdvalid = avm_M1_readdatavalid;
assign q_wait = avm_M1_waitrequest;
assign q_clock = cso_MCLK_clk;
assign q_reset = rso_MRST_reset;
wire q_clock;
wire q_reset;
reg [3:0] state = 0;
reg [31:0] h_rdata = 0;
reg h_wait = 0;
reg [31:0] q_wdata = 0;
wire [31:0] q_rdata;
reg [29:0] q_addr = 0;
reg [3:0] q_be = 0;
reg q_wr = 0;
reg q_rd = 0;
reg q_btrans = 0;
wire q_rdvalid, q_wait;
reg [3:0] tmp_cs;
reg [21:0] tmp_addr;
reg [19:0] timeout = 0;
always@(posedge q_clock or posedge q_reset)
begin
if(q_reset) begin
q_addr <= 0;
q_be <= 0;
end
else begin
q_be <= ~coe_M1_BEN;
case(coe_M1_CSN)
4'b1110: begin q_addr <= {8'b00010000, coe_M1_ADDR}; end
4'b1101: begin q_addr <= {8'b00100000, coe_M1_ADDR}; end
4'b1011: begin q_addr <= {8'b00110000, coe_M1_ADDR}; end
4'b0111: begin q_addr <= {8'b01000000, coe_M1_ADDR}; end
default: begin q_addr <= 0; end
endcase
end
end
always@(posedge q_clock or posedge q_reset)
begin
if(q_reset) begin
h_rdata <= 0;
q_wdata <= 0;
q_wr <= 0;
q_rd <= 0;
q_btrans <= 0;
h_wait <= 0;
timeout <= 0;
state <= 4'd0;
end
else begin
case(state)
5'd0: begin
timeout <= 0;
if((coe_M1_CSN != 4'b1111)&&(!coe_M1_RDN)) begin
q_btrans <= 0;
q_wr <= 0;
q_rd <= 0;
h_wait <= 1;
state <= 4'd3;
end
else if((coe_M1_CSN != 4'b1111)&&(!coe_M1_WRN)) begin
q_btrans <= 0;
q_wr <= 0;
q_rd <= 0;
h_wait <= 0;
state <= 4'd8;
end
else begin
h_rdata <= 0;
q_wdata <= 0;
q_wr <= 0;
q_rd <= 0;
q_btrans <= 0;
h_wait <= 0;
state <= 4'd0;
end
end
// Read process.
4'd3: begin
tmp_addr <= coe_M1_ADDR;
tmp_cs <= coe_M1_CSN;
if((!q_wait)||(timeout == 20'hFFFFF)) begin
q_btrans <= 1;
q_rd <= 1;
timeout <= 0;
state <= 4'd4;
end
else timeout <= timeout + 1;
end
4'd4: begin
q_btrans <= 0;
q_rd <= 0;
if((q_rdvalid)||(timeout == 20'hFFFFF)) begin h_rdata <= q_rdata; h_wait <= q_wait; timeout <= 0; state <= 4'd5; end
else timeout <= timeout + 1;
end
4'd5: begin
h_wait <= q_wait;
if((tmp_addr != coe_M1_ADDR)||(tmp_cs != coe_M1_CSN)||(coe_M1_RDN)||(timeout == 20'hFFFFF)) state <= 4'd0;
else timeout <= timeout + 1;
end
// Write process.
4'd8: begin
q_wdata <= coe_M1_DATA;
if(coe_M1_WRN) begin
h_wait <= 1;
state <= 4'd9;
end
end
4'd9: begin
if((!q_wait)||(timeout == 20'hFFFFF)) begin
q_btrans <= 1;
q_wr <= 1;
timeout <= 0;
state <= 4'd10;
end
else timeout <= timeout + 1;
end
4'd10: begin
q_btrans <= 0;
q_wr <= 0;
if((!q_wait)||(timeout == 20'hFFFFF)) begin
timeout <= 0;
state <= 4'd11;
end
else timeout <= timeout + 1;
end
4'd11: begin
if((!q_wait)||(timeout == 20'hFFFFF)) begin
timeout <= 0;
h_wait <= 0;
state <= 4'd0;
end
else timeout <= timeout + 1;
end
default: begin
h_rdata <= 0;
h_wait <= 0;
q_wdata <= 0;
q_wr <= 0;
q_rd <= 0;
q_btrans <= 0;
timeout <= 0;
state <= 4'd0;
end
endcase
end
end
wire [4:0] pll_clocks;
wire pll_locked;
altpll m1_bus_pll_inst1(
.inclk (coe_M1_CLK),
.clk (pll_clocks),
.locked (pll_locked),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
m1_bus_pll_inst1.bandwidth_type = "AUTO",
m1_bus_pll_inst1.clk0_divide_by = 1,
m1_bus_pll_inst1.clk0_duty_cycle = 50,
m1_bus_pll_inst1.clk0_multiply_by = 2,
m1_bus_pll_inst1.clk0_phase_shift = "0",
m1_bus_pll_inst1.clk1_divide_by = 1,
m1_bus_pll_inst1.clk1_duty_cycle = 50,
m1_bus_pll_inst1.clk1_multiply_by = 3,
m1_bus_pll_inst1.clk1_phase_shift = "0",
m1_bus_pll_inst1.compensate_clock = "CLK0",
m1_bus_pll_inst1.inclk0_input_frequency = 15000,
m1_bus_pll_inst1.intended_device_family = "Cyclone IV E",
m1_bus_pll_inst1.lpm_hint = "CBX_MODULE_PREFIX=apll",
m1_bus_pll_inst1.lpm_type = "altpll",
m1_bus_pll_inst1.operation_mode = "NORMAL",
m1_bus_pll_inst1.pll_type = "AUTO",
m1_bus_pll_inst1.port_activeclock = "PORT_UNUSED",
m1_bus_pll_inst1.port_areset = "PORT_UNUSED",
m1_bus_pll_inst1.port_clkbad0 = "PORT_UNUSED",
m1_bus_pll_inst1.port_clkbad1 = "PORT_UNUSED",
m1_bus_pll_inst1.port_clkloss = "PORT_UNUSED",
m1_bus_pll_inst1.port_clkswitch = "PORT_UNUSED",
m1_bus_pll_inst1.port_configupdate = "PORT_UNUSED",
m1_bus_pll_inst1.port_fbin = "PORT_UNUSED",
m1_bus_pll_inst1.port_inclk0 = "PORT_USED",
m1_bus_pll_inst1.port_inclk1 = "PORT_UNUSED",
m1_bus_pll_inst1.port_locked = "PORT_USED",
m1_bus_pll_inst1.port_pfdena = "PORT_UNUSED",
m1_bus_pll_inst1.port_phasecounterselect = "PORT_UNUSED",
m1_bus_pll_inst1.port_phasedone = "PORT_UNUSED",
m1_bus_pll_inst1.port_phasestep = "PORT_UNUSED",
m1_bus_pll_inst1.port_phaseupdown = "PORT_UNUSED",
m1_bus_pll_inst1.port_pllena = "PORT_UNUSED",
m1_bus_pll_inst1.port_scanaclr = "PORT_UNUSED",
m1_bus_pll_inst1.port_scanclk = "PORT_UNUSED",
m1_bus_pll_inst1.port_scanclkena = "PORT_UNUSED",
m1_bus_pll_inst1.port_scandata = "PORT_UNUSED",
m1_bus_pll_inst1.port_scandataout = "PORT_UNUSED",
m1_bus_pll_inst1.port_scandone = "PORT_UNUSED",
m1_bus_pll_inst1.port_scanread = "PORT_UNUSED",
m1_bus_pll_inst1.port_scanwrite = "PORT_UNUSED",
m1_bus_pll_inst1.port_clk0 = "PORT_USED",
m1_bus_pll_inst1.port_clk1 = "PORT_USED",
m1_bus_pll_inst1.port_clk2 = "PORT_UNUSED",
m1_bus_pll_inst1.port_clk3 = "PORT_UNUSED",
m1_bus_pll_inst1.port_clk4 = "PORT_UNUSED",
m1_bus_pll_inst1.port_clk5 = "PORT_UNUSED",
m1_bus_pll_inst1.port_clkena0 = "PORT_UNUSED",
m1_bus_pll_inst1.port_clkena1 = "PORT_UNUSED",
m1_bus_pll_inst1.port_clkena2 = "PORT_UNUSED",
m1_bus_pll_inst1.port_clkena3 = "PORT_UNUSED",
m1_bus_pll_inst1.port_clkena4 = "PORT_UNUSED",
m1_bus_pll_inst1.port_clkena5 = "PORT_UNUSED",
m1_bus_pll_inst1.port_extclk0 = "PORT_UNUSED",
m1_bus_pll_inst1.port_extclk1 = "PORT_UNUSED",
m1_bus_pll_inst1.port_extclk2 = "PORT_UNUSED",
m1_bus_pll_inst1.port_extclk3 = "PORT_UNUSED",
m1_bus_pll_inst1.self_reset_on_loss_lock = "ON",
m1_bus_pll_inst1.width_clock = 5;
endmodule
|
module testbench;
reg clk;
reg reset;
reg Compress;
reg Decompress;
initial
begin
clk = 1'b1;
reset = 1'b1;
Decompress = 1'b0;
#30 reset = 1'b0;
#50 Compress = 1'b1;
end
always
#5 clk = ~clk;
wire [17:0] oBufferIn;
BufferIn buffin(
.Clk(clk),
.InputBuffer(RequestInputBuffer),
.oBufferIn(oBufferIn),
.EndOfFile(EOF)
);
controller ctrl(
.clk(clk),
.reset(reset),
.StringLoadZero(StringLoadZero),
.StringLoadChar(StringLoadChar),
.StringLoadBuffer(StringLoadBuffer),
.ConcatenateChar(ConcatenateChars),
.StringShiftRight(StringShiftRight),
.ConcatenateStringSize(ConcatenateStringSize),
.LoadInsertPointer(LoadInsertPointer),
.UpdateInsertPointer(UpdateInsertPointer),
.CodeLoadZero(CodeLoadZero),
.CodeIncrement(CodeIncrement),
.NotFound(NotFound),
.Found(Found),
.CharLoadBuffer(CharLoadBuffer),
.BufferInitDicPointer(BufferInitDicPointer),
.LoadDicPointer(LoadDicPointer),
.DicPointerIncrement(DicPointerIncrement),
.LoadJumpAddress(JumpLoadAddress),
.DicPointerLoadInsert(DicPointerLoadInsert),
.StringRAMLoad(StringRAMLoad),
.StringRAMZero(StringRAMZero),
.StringRAMShift(StringRAMShift),
.SetJumpAddress(SetJumpAddress),
.RequestOutBuffer(RequestOutBuffer),
.CloseBuffer(CloseBuffer),
.RAMread(RAMread),
.RAMZeroData(oRAMzeroData),
.InitRAMCode(oInitRAMCode),
.WriteString(oWriteString),
//************************ Jump conditions******************************
.Compress(Compress), // 1100
.Decompress(Decompress), // 1011
.DicPointerEqualsINsertPoniter(DicPointerEqualsInsertPointer), // 1010
.StringRAMSizeEqualsStringSize(StringRAMSizeEqualsStringSize), // 1001
.DicPointerEqualsJumpAddress(DicPointerEqualsJumpAddress), // 1000
.StringRAMSizeEqualsZero(StringRAMSizeEqualsZero), // 0111
.StringRAMEqualsString(StringRAMEqualsString), // 0110
.CodeBigger128(CodeBigger128), // 0101
.CodeEqualsZero(CodeEqualsZero), // 0100
.EndOfFile(EOF), // 0011
.FoundStatus(FoundStatus) // 0010
// Inconditional jump // 0001
// No jump // 0000
);
wire [15:0] iRAMBuffer;
wire [11:0] outBuffer;
wire [7:0] ramCode;
wire [15:0] ramString;
wire [17:0] ramDicPointer;
Registers registers(
.Clk(clk),
.InBuffer(oBufferIn),
.iRAMBuffer(iRAMBuffer),
.outBuffer(outBuffer),
.RequestInBuffer(RequestInputBuffer),
// **************** Control for String *************************************
.StringLoadZero(StringLoadZero),
.StringLoadChar(StringLoadChar),
.StringLoadBuffer(StringLoadBuffer),
.ConcatenateChar(ConcatenateChars),
.StringShiftRight(StringShiftRight),
.ConcatenateStringSize(ConcatenateStringSize),
// **************** Control for Insert Pointer *************************
.LoadInsertPointer(LoadInsertPointer),
.UpdateInsertPointer(UpdateInsertPointer),
// **************** Control for Code ***********************************
.CodeLoadZero(CodeLoadZero),
.CodeIncrement(CodeIncrement),
// **************** Control for Found **********************************
.NotFound(NotFound),
.Found(Found),
// **************** Control for Char ***********************************
.CharLoadBuffer(CharLoadBuffer),
// **************** Control for Init Dictionary Pointer ****************
.BufferInitDicPointer(BufferInitDicPointer),
// **************** Control for Dictionary Pointer *********************
.LoadDicPointer(LoadDicPointer),
.DicPointerIncrement(DicPointerIncrement),
.LoadJumpAddress(JumpLoadAddress),
.DicPointerLoadInsert(DicPointerLoadInsert),
// **************** Control for StringRAM ******************************
.StringRAMLoad(StringRAMLoad),
.StringRAMZero(StringRAMZero),
.StringRAMShift(StringRAMShift),
// **************** Control for Jumping Address ************************
.SetJumpAddress(SetJumpAddress),
// ****************** Jump conditions **********************************
.DicPointerEqualsInsertPointer(DicPointerEqualsInsertPointer),
.StringRAMSizeEqualsStringSize(StringRAMSizeEqualsStringSize),
.DicPointerEqualsJumpAddress(DicPointerEqualsJumpAddress),
.StringRAMSizeEqualsZero(StringRAMSizeEqualsZero),
.StringRAMEqualsString(StringRAMEqualsString),
.CodeBigger128(CodeBigger128),
.CodeEqualsZero(CodeEqualsZero),
.FoundStatus(FoundStatus),
// ********************* Data to RAM ***********************************
.ramCode(ramCode),
.ramString(ramString),
.ramDicPointer(ramDicPointer)
);
wire [15:0] oRAMBuffer;
RAMBuffer ramBuffer(
.RAMread(RAMread),
.RAMZeroData(oRAMzeroData),
.InitRAMCode(oInitRAMCode),
.WriteString(oWriteString),
.ramCode(ramCode),
.ramString(ramString),
.ramDicPointer(ramDicPointer),
.oRAMBuffer(oRAMBuffer)
);
BufferOut BufferOut(
.Clk(clk),
.OutputBuffer(RequestOutBuffer),
.CloseBuffer(CloseBuffer),
.iBufferOut(outBuffer)
);
endmodule
|
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_aw_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4,
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire clk ,
input wire reset ,
// Slave Interface Write Address Ports
input wire [C_ID_WIDTH-1:0] s_awid ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_awaddr ,
input wire [7:0] s_awlen ,
input wire [2:0] s_awsize ,
input wire [1:0] s_awburst ,
input wire s_awvalid ,
output wire s_awready ,
output wire m_awvalid ,
output wire [C_AXI_ADDR_WIDTH-1:0] m_awaddr ,
input wire m_awready ,
// Connections to/from axi_protocol_converter_v2_1_b2s_b_channel module
output wire b_push ,
output wire [C_ID_WIDTH-1:0] b_awid ,
output wire [7:0] b_awlen ,
input wire b_full
);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire next ;
wire next_pending ;
wire a_push;
wire incr_burst;
reg [C_ID_WIDTH-1:0] s_awid_r;
reg [7:0] s_awlen_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// Translate the AXI transaction to the MC transaction(s)
axi_protocol_converter_v2_1_b2s_cmd_translator #
(
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
)
cmd_translator_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_axaddr ( s_awaddr ) ,
.s_axlen ( s_awlen ) ,
.s_axsize ( s_awsize ) ,
.s_axburst ( s_awburst ) ,
.s_axhandshake ( s_awvalid & a_push ) ,
.m_axaddr ( m_awaddr ) ,
.incr_burst ( incr_burst ) ,
.next ( next ) ,
.next_pending ( next_pending )
);
axi_protocol_converter_v2_1_b2s_wr_cmd_fsm aw_cmd_fsm_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_awready ( s_awready ) ,
.s_awvalid ( s_awvalid ) ,
.m_awvalid ( m_awvalid ) ,
.m_awready ( m_awready ) ,
.next ( next ) ,
.next_pending ( next_pending ) ,
.b_push ( b_push ) ,
.b_full ( b_full ) ,
.a_push ( a_push )
);
assign b_awid = s_awid_r;
assign b_awlen = s_awlen_r;
always @(posedge clk) begin
s_awid_r <= s_awid ;
s_awlen_r <= s_awlen ;
end
endmodule
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21O_TB_V
`define SKY130_FD_SC_HS__A21O_TB_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a21o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 A1 = 1'b1;
#140 A2 = 1'b1;
#160 B1 = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 A1 = 1'b0;
#240 A2 = 1'b0;
#260 B1 = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 B1 = 1'b1;
#380 A2 = 1'b1;
#400 A1 = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 B1 = 1'bx;
#480 A2 = 1'bx;
#500 A1 = 1'bx;
end
sky130_fd_sc_hs__a21o dut (.A1(A1), .A2(A2), .B1(B1), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21O_TB_V
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_multi_mac_pcs_pma_gige.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_multi_mac_pcs_pma_gige_phyip.v,v $
//
// $Revision: #2 $
// $Date: 2011/01/31 $
// Check in by : $Author: wyleong $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet - 10/100/1000 MAC
//
// Description :
//
// Top Level Triple Speed Ethernet(10/100/1000) MAC with MII/GMII
// interfaces, mdio module and register space (statistic, control and
// management)
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF;SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" } *)
module altera_tse_multi_mac_pcs_pma_gige_phyip
#(
parameter USE_SYNC_RESET = 0, // Use Synchronized Reset Inputs
parameter RESET_LEVEL = 1'b 1 , // Reset Active Level
parameter ENABLE_GMII_LOOPBACK = 1, // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
parameter ENABLE_HD_LOGIC = 1, // HD_LOGIC_ENA : Enable Half Duplex Logic
parameter ENABLE_SUP_ADDR = 1, // SUP_ADDR_ENA : Enable Supplemental Addresses
parameter ENA_HASH = 1, // ENA_HASH Enable Hash Table
parameter STAT_CNT_ENA = 1, // STAT_CNT_ENA Enable Statistic Counters
parameter MDIO_CLK_DIV = 40 , // Host Clock Division - MDC Generation
parameter CORE_VERSION = 16'h3, // ALTERA Core Version
parameter CUST_VERSION = 1 , // Customer Core Version
parameter REDUCED_INTERFACE_ENA = 0, // Enable the RGMII Interface
parameter ENABLE_MDIO = 1, // Enable the MDIO Interface
parameter ENABLE_MAGIC_DETECT = 1, // Enable magic packet detection
parameter ENABLE_PADDING = 1, // Enable padding operation.
parameter ENABLE_LGTH_CHECK = 1, // Enable frame length checking.
parameter GBIT_ONLY = 1, // Enable Gigabit only operation.
parameter MBIT_ONLY = 1, // Enable Megabit (10/100) only operation.
parameter REDUCED_CONTROL = 0, // Reduced control for MAC LITE
parameter CRC32DWIDTH = 4'b 1000, // input data width (informal, not for change)
parameter CRC32GENDELAY = 3'b 110, // when the data from the generator is valid
parameter CRC32CHECK16BIT = 1'b 0, // 1 compare two times 16 bit of the CRC (adds one pipeline step)
parameter CRC32S1L2_EXTERN = 1'b0, // false: merge enable
parameter ENABLE_SHIFT16 = 0, // Enable byte stuffing at packet header
parameter ENABLE_MAC_FLOW_CTRL = 1'b1, // Option to enable flow control
parameter ENABLE_MAC_TXADDR_SET = 1'b1, // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
parameter ENABLE_MAC_RX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC RX data path
parameter ENABLE_MAC_TX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC TX data path
parameter PHY_IDENTIFIER = 32'h 00000000, // PHY Identifier
parameter DEV_VERSION = 16'h 0001 , // Customer Phy's Core Version
parameter ENABLE_SGMII = 1, // Enable SGMII logic for synthesis
parameter ENABLE_CLK_SHARING = 1, // Option to share clock for multiple channels (Clocks are rate-matched).
parameter ENABLE_REG_SHARING = 0, // Option to share register space. Uses certain hard-coded values from input.
parameter ENABLE_EXTENDED_STAT_REG = 0, // Enable a few extended statistic registers
parameter MAX_CHANNELS = 1, // The number of channels in Multi-TSE component
parameter ENABLE_PKT_CLASS = 1, // Enable Packet Classification Av-ST Interface
parameter ENABLE_RX_FIFO_STATUS = 1, // Enable Receive FIFO Almost Full status interface
parameter CHANNEL_WIDTH = 1, // The width of the channel interface
parameter EXPORT_PWRDN = 1'b0, // Option to export the Alt2gxb powerdown signal
parameter DEVICE_FAMILY = "ARRIAGX", // The device family the the core is targetted for.
parameter TRANSCEIVER_OPTION = 1'b0, // Option to select transceiver block for MAC PCS PMA Instantiation. Valid Values are 0 and 1: 0 - GXB (GIGE Mode) 1 - LVDS IO
parameter ENABLE_ALT_RECONFIG = 0, // Option to expose the altreconfig ports
parameter SYNCHRONIZER_DEPTH = 3, // Number of synchronizer
// Internal parameters
parameter STARTING_CHANNEL_NUMBER = 0,
parameter ADDR_WIDTH = (MAX_CHANNELS > 16)? 13 :
(MAX_CHANNELS > 8)? 12 :
(MAX_CHANNELS > 4)? 11 :
(MAX_CHANNELS > 2)? 10 :
(MAX_CHANNELS > 1)? 9 : 8
)
// Port List
(
// RESET / MAC REG IF / MDIO
input wire reset, // Asynchronous Reset - clk Domain
input wire clk, // 25MHz Host Interface Clock
input wire read, // Register Read Strobe
input wire write, // Register Write Strobe
input wire [ADDR_WIDTH-1:0] address, // Register Address
input wire [31:0] writedata, // Write Data for Host Bus
output wire [31:0] readdata, // Read Data to Host Bus
output wire waitrequest, // Interface Busy
output wire mdc, // 2.5MHz Inteface
input wire mdio_in, // MDIO Input
output wire mdio_out, // MDIO Output
output wire mdio_oen, // MDIO Output Enable
// DEVICE SPECIFIC SIGNALS
input wire gxb_cal_blk_clk, // GXB Calibration Clock
input wire ref_clk, // Rference Clock
// SHARED CLK SIGNALS
output wire mac_rx_clk, // Av-ST Receive Clock
output wire mac_tx_clk, // Av-ST Transmit Clock
// SHARED RX STATUS
input wire rx_afull_clk, // Almost full clk
input wire [1:0] rx_afull_data, // Almost full data
input wire rx_afull_valid, // Almost full valid
input wire [CHANNEL_WIDTH-1:0] rx_afull_channel, // Almost full channel
// CHANNEL 0
// PCS SIGNALS TO PHY
input wire rxp_0, // Differential Receive Data
output wire txp_0, // Differential Transmit Data
output wire rx_recovclkout_0, // Receiver Recovered Clock
output wire led_crs_0, // Carrier Sense
output wire led_link_0, // Valid Link
output wire led_col_0, // Collision Indication
output wire led_an_0, // Auto-Negotiation Status
output wire led_char_err_0, // Character Error
output wire led_disp_err_0, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_0, // Av-ST Receive Clock
output wire mac_tx_clk_0, // Av-ST Transmit Clock
output wire data_rx_sop_0, // Start of Packet
output wire data_rx_eop_0, // End of Packet
output wire [7:0] data_rx_data_0, // Data from FIFO
output wire [4:0] data_rx_error_0, // Receive packet error
output wire data_rx_valid_0, // Data Receive FIFO Valid
input wire data_rx_ready_0, // Data Receive Ready
output wire [4:0] pkt_class_data_0, // Frame Type Indication
output wire pkt_class_valid_0, // Frame Type Indication Valid
input wire data_tx_error_0, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_0, // Data from FIFO transmit
input wire data_tx_valid_0, // Data FIFO transmit Empty
input wire data_tx_sop_0, // Start of Packet
input wire data_tx_eop_0, // END of Packet
output wire data_tx_ready_0, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_0, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_0, // Forward Current Frame with CRC from Application
input wire xoff_gen_0, // Xoff Pause frame generate
input wire xon_gen_0, // Xon Pause frame generate
input wire magic_sleep_n_0, // Enable Sleep Mode
output wire magic_wakeup_0, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_0, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_0, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_0, // address to PHYIP management interface
input wire phy_mgmt_read_0, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_0, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_0, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_0, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_0,// writedata to PHYIP management interface
// CHANNEL 1
// PCS SIGNALS TO PHY
input wire rxp_1, // Differential Receive Data
output wire txp_1, // Differential Transmit Data
output wire rx_recovclkout_1, // Receiver Recovered Clock
output wire led_crs_1, // Carrier Sense
output wire led_link_1, // Valid Link
output wire led_col_1, // Collision Indication
output wire led_an_1, // Auto-Negotiation Status
output wire led_char_err_1, // Character Error
output wire led_disp_err_1, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_1, // Av-ST Receive Clock
output wire mac_tx_clk_1, // Av-ST Transmit Clock
output wire data_rx_sop_1, // Start of Packet
output wire data_rx_eop_1, // End of Packet
output wire [7:0] data_rx_data_1, // Data from FIFO
output wire [4:0] data_rx_error_1, // Receive packet error
output wire data_rx_valid_1, // Data Receive FIFO Valid
input wire data_rx_ready_1, // Data Receive Ready
output wire [4:0] pkt_class_data_1, // Frame Type Indication
output wire pkt_class_valid_1, // Frame Type Indication Valid
input wire data_tx_error_1, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_1, // Data from FIFO transmit
input wire data_tx_valid_1, // Data FIFO transmit Empty
input wire data_tx_sop_1, // Start of Packet
input wire data_tx_eop_1, // END of Packet
output wire data_tx_ready_1, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_1, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_1, // Forward Current Frame with CRC from Application
input wire xoff_gen_1, // Xoff Pause frame generate
input wire xon_gen_1, // Xon Pause frame generate
input wire magic_sleep_n_1, // Enable Sleep Mode
output wire magic_wakeup_1, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_1, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_1, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_1, // address to PHYIP management interface
input wire phy_mgmt_read_1, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_1, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_1, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_1, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_1,// writedata to PHYIP management interface
// CHANNEL 2
// PCS SIGNALS TO PHY
input wire rxp_2, // Differential Receive Data
output wire txp_2, // Differential Transmit Data
output wire rx_recovclkout_2, // Receiver Recovered Clock
output wire led_crs_2, // Carrier Sense
output wire led_link_2, // Valid Link
output wire led_col_2, // Collision Indication
output wire led_an_2, // Auto-Negotiation Status
output wire led_char_err_2, // Character Error
output wire led_disp_err_2, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_2, // Av-ST Receive Clock
output wire mac_tx_clk_2, // Av-ST Transmit Clock
output wire data_rx_sop_2, // Start of Packet
output wire data_rx_eop_2, // End of Packet
output wire [7:0] data_rx_data_2, // Data from FIFO
output wire [4:0] data_rx_error_2, // Receive packet error
output wire data_rx_valid_2, // Data Receive FIFO Valid
input wire data_rx_ready_2, // Data Receive Ready
output wire [4:0] pkt_class_data_2, // Frame Type Indication
output wire pkt_class_valid_2, // Frame Type Indication Valid
input wire data_tx_error_2, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_2, // Data from FIFO transmit
input wire data_tx_valid_2, // Data FIFO transmit Empty
input wire data_tx_sop_2, // Start of Packet
input wire data_tx_eop_2, // END of Packet
output wire data_tx_ready_2, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_2, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_2, // Forward Current Frame with CRC from Application
input wire xoff_gen_2, // Xoff Pause frame generate
input wire xon_gen_2, // Xon Pause frame generate
input wire magic_sleep_n_2, // Enable Sleep Mode
output wire magic_wakeup_2, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_2, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_2, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_2, // address to PHYIP management interface
input wire phy_mgmt_read_2, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_2, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_2, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_2, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_2,// writedata to PHYIP management interface
// CHANNEL 3
// PCS SIGNALS TO PHY
input wire rxp_3, // Differential Receive Data
output wire txp_3, // Differential Transmit Data
output wire rx_recovclkout_3, // Receiver Recovered Clock
output wire led_crs_3, // Carrier Sense
output wire led_link_3, // Valid Link
output wire led_col_3, // Collision Indication
output wire led_an_3, // Auto-Negotiation Status
output wire led_char_err_3, // Character Error
output wire led_disp_err_3, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_3, // Av-ST Receive Clock
output wire mac_tx_clk_3, // Av-ST Transmit Clock
output wire data_rx_sop_3, // Start of Packet
output wire data_rx_eop_3, // End of Packet
output wire [7:0] data_rx_data_3, // Data from FIFO
output wire [4:0] data_rx_error_3, // Receive packet error
output wire data_rx_valid_3, // Data Receive FIFO Valid
input wire data_rx_ready_3, // Data Receive Ready
output wire [4:0] pkt_class_data_3, // Frame Type Indication
output wire pkt_class_valid_3, // Frame Type Indication Valid
input wire data_tx_error_3, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_3, // Data from FIFO transmit
input wire data_tx_valid_3, // Data FIFO transmit Empty
input wire data_tx_sop_3, // Start of Packet
input wire data_tx_eop_3, // END of Packet
output wire data_tx_ready_3, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_3, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_3, // Forward Current Frame with CRC from Application
input wire xoff_gen_3, // Xoff Pause frame generate
input wire xon_gen_3, // Xon Pause frame generate
input wire magic_sleep_n_3, // Enable Sleep Mode
output wire magic_wakeup_3, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_3, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_3, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_3, // address to PHYIP management interface
input wire phy_mgmt_read_3, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_3, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_3, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_3, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_3,// writedata to PHYIP management interface
// CHANNEL 4
// PCS SIGNALS TO PHY
input wire rxp_4, // Differential Receive Data
output wire txp_4, // Differential Transmit Data
output wire rx_recovclkout_4, // Receiver Recovered Clock
output wire led_crs_4, // Carrier Sense
output wire led_link_4, // Valid Link
output wire led_col_4, // Collision Indication
output wire led_an_4, // Auto-Negotiation Status
output wire led_char_err_4, // Character Error
output wire led_disp_err_4, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_4, // Av-ST Receive Clock
output wire mac_tx_clk_4, // Av-ST Transmit Clock
output wire data_rx_sop_4, // Start of Packet
output wire data_rx_eop_4, // End of Packet
output wire [7:0] data_rx_data_4, // Data from FIFO
output wire [4:0] data_rx_error_4, // Receive packet error
output wire data_rx_valid_4, // Data Receive FIFO Valid
input wire data_rx_ready_4, // Data Receive Ready
output wire [4:0] pkt_class_data_4, // Frame Type Indication
output wire pkt_class_valid_4, // Frame Type Indication Valid
input wire data_tx_error_4, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_4, // Data from FIFO transmit
input wire data_tx_valid_4, // Data FIFO transmit Empty
input wire data_tx_sop_4, // Start of Packet
input wire data_tx_eop_4, // END of Packet
output wire data_tx_ready_4, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_4, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_4, // Forward Current Frame with CRC from Application
input wire xoff_gen_4, // Xoff Pause frame generate
input wire xon_gen_4, // Xon Pause frame generate
input wire magic_sleep_n_4, // Enable Sleep Mode
output wire magic_wakeup_4, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_4, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_4, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_4, // address to PHYIP management interface
input wire phy_mgmt_read_4, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_4, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_4, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_4, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_4,// writedata to PHYIP management interface
// CHANNEL 5
// PCS SIGNALS TO PHY
input wire rxp_5, // Differential Receive Data
output wire txp_5, // Differential Transmit Data
output wire rx_recovclkout_5, // Receiver Recovered Clock
output wire led_crs_5, // Carrier Sense
output wire led_link_5, // Valid Link
output wire led_col_5, // Collision Indication
output wire led_an_5, // Auto-Negotiation Status
output wire led_char_err_5, // Character Error
output wire led_disp_err_5, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_5, // Av-ST Receive Clock
output wire mac_tx_clk_5, // Av-ST Transmit Clock
output wire data_rx_sop_5, // Start of Packet
output wire data_rx_eop_5, // End of Packet
output wire [7:0] data_rx_data_5, // Data from FIFO
output wire [4:0] data_rx_error_5, // Receive packet error
output wire data_rx_valid_5, // Data Receive FIFO Valid
input wire data_rx_ready_5, // Data Receive Ready
output wire [4:0] pkt_class_data_5, // Frame Type Indication
output wire pkt_class_valid_5, // Frame Type Indication Valid
input wire data_tx_error_5, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_5, // Data from FIFO transmit
input wire data_tx_valid_5, // Data FIFO transmit Empty
input wire data_tx_sop_5, // Start of Packet
input wire data_tx_eop_5, // END of Packet
output wire data_tx_ready_5, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_5, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_5, // Forward Current Frame with CRC from Application
input wire xoff_gen_5, // Xoff Pause frame generate
input wire xon_gen_5, // Xon Pause frame generate
input wire magic_sleep_n_5, // Enable Sleep Mode
output wire magic_wakeup_5, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_5, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_5, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_5, // address to PHYIP management interface
input wire phy_mgmt_read_5, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_5, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_5, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_5, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_5,// writedata to PHYIP management interface
// CHANNEL 6
// PCS SIGNALS TO PHY
input wire rxp_6, // Differential Receive Data
output wire txp_6, // Differential Transmit Data
output wire rx_recovclkout_6, // Receiver Recovered Clock
output wire led_crs_6, // Carrier Sense
output wire led_link_6, // Valid Link
output wire led_col_6, // Collision Indication
output wire led_an_6, // Auto-Negotiation Status
output wire led_char_err_6, // Character Error
output wire led_disp_err_6, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_6, // Av-ST Receive Clock
output wire mac_tx_clk_6, // Av-ST Transmit Clock
output wire data_rx_sop_6, // Start of Packet
output wire data_rx_eop_6, // End of Packet
output wire [7:0] data_rx_data_6, // Data from FIFO
output wire [4:0] data_rx_error_6, // Receive packet error
output wire data_rx_valid_6, // Data Receive FIFO Valid
input wire data_rx_ready_6, // Data Receive Ready
output wire [4:0] pkt_class_data_6, // Frame Type Indication
output wire pkt_class_valid_6, // Frame Type Indication Valid
input wire data_tx_error_6, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_6, // Data from FIFO transmit
input wire data_tx_valid_6, // Data FIFO transmit Empty
input wire data_tx_sop_6, // Start of Packet
input wire data_tx_eop_6, // END of Packet
output wire data_tx_ready_6, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_6, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_6, // Forward Current Frame with CRC from Application
input wire xoff_gen_6, // Xoff Pause frame generate
input wire xon_gen_6, // Xon Pause frame generate
input wire magic_sleep_n_6, // Enable Sleep Mode
output wire magic_wakeup_6, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_6, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_6, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_6, // address to PHYIP management interface
input wire phy_mgmt_read_6, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_6, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_6, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_6, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_6,// writedata to PHYIP management interface
// CHANNEL 7
// PCS SIGNALS TO PHY
input wire rxp_7, // Differential Receive Data
output wire txp_7, // Differential Transmit Data
output wire rx_recovclkout_7, // Receiver Recovered Clock
output wire led_crs_7, // Carrier Sense
output wire led_link_7, // Valid Link
output wire led_col_7, // Collision Indication
output wire led_an_7, // Auto-Negotiation Status
output wire led_char_err_7, // Character Error
output wire led_disp_err_7, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_7, // Av-ST Receive Clock
output wire mac_tx_clk_7, // Av-ST Transmit Clock
output wire data_rx_sop_7, // Start of Packet
output wire data_rx_eop_7, // End of Packet
output wire [7:0] data_rx_data_7, // Data from FIFO
output wire [4:0] data_rx_error_7, // Receive packet error
output wire data_rx_valid_7, // Data Receive FIFO Valid
input wire data_rx_ready_7, // Data Receive Ready
output wire [4:0] pkt_class_data_7, // Frame Type Indication
output wire pkt_class_valid_7, // Frame Type Indication Valid
input wire data_tx_error_7, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_7, // Data from FIFO transmit
input wire data_tx_valid_7, // Data FIFO transmit Empty
input wire data_tx_sop_7, // Start of Packet
input wire data_tx_eop_7, // END of Packet
output wire data_tx_ready_7, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_7, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_7, // Forward Current Frame with CRC from Application
input wire xoff_gen_7, // Xoff Pause frame generate
input wire xon_gen_7, // Xon Pause frame generate
input wire magic_sleep_n_7, // Enable Sleep Mode
output wire magic_wakeup_7, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_7, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_7, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_7, // address to PHYIP management interface
input wire phy_mgmt_read_7, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_7, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_7, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_7, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_7,// writedata to PHYIP management interface
// CHANNEL 8
// PCS SIGNALS TO PHY
input wire rxp_8, // Differential Receive Data
output wire txp_8, // Differential Transmit Data
output wire rx_recovclkout_8, // Receiver Recovered Clock
output wire led_crs_8, // Carrier Sense
output wire led_link_8, // Valid Link
output wire led_col_8, // Collision Indication
output wire led_an_8, // Auto-Negotiation Status
output wire led_char_err_8, // Character Error
output wire led_disp_err_8, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_8, // Av-ST Receive Clock
output wire mac_tx_clk_8, // Av-ST Transmit Clock
output wire data_rx_sop_8, // Start of Packet
output wire data_rx_eop_8, // End of Packet
output wire [7:0] data_rx_data_8, // Data from FIFO
output wire [4:0] data_rx_error_8, // Receive packet error
output wire data_rx_valid_8, // Data Receive FIFO Valid
input wire data_rx_ready_8, // Data Receive Ready
output wire [4:0] pkt_class_data_8, // Frame Type Indication
output wire pkt_class_valid_8, // Frame Type Indication Valid
input wire data_tx_error_8, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_8, // Data from FIFO transmit
input wire data_tx_valid_8, // Data FIFO transmit Empty
input wire data_tx_sop_8, // Start of Packet
input wire data_tx_eop_8, // END of Packet
output wire data_tx_ready_8, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_8, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_8, // Forward Current Frame with CRC from Application
input wire xoff_gen_8, // Xoff Pause frame generate
input wire xon_gen_8, // Xon Pause frame generate
input wire magic_sleep_n_8, // Enable Sleep Mode
output wire magic_wakeup_8, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_8, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_8, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_8, // address to PHYIP management interface
input wire phy_mgmt_read_8, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_8, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_8, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_8, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_8,// writedata to PHYIP management interface
// CHANNEL 9
// PCS SIGNALS TO PHY
input wire rxp_9, // Differential Receive Data
output wire txp_9, // Differential Transmit Data
output wire rx_recovclkout_9, // Receiver Recovered Clock
output wire led_crs_9, // Carrier Sense
output wire led_link_9, // Valid Link
output wire led_col_9, // Collision Indication
output wire led_an_9, // Auto-Negotiation Status
output wire led_char_err_9, // Character Error
output wire led_disp_err_9, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_9, // Av-ST Receive Clock
output wire mac_tx_clk_9, // Av-ST Transmit Clock
output wire data_rx_sop_9, // Start of Packet
output wire data_rx_eop_9, // End of Packet
output wire [7:0] data_rx_data_9, // Data from FIFO
output wire [4:0] data_rx_error_9, // Receive packet error
output wire data_rx_valid_9, // Data Receive FIFO Valid
input wire data_rx_ready_9, // Data Receive Ready
output wire [4:0] pkt_class_data_9, // Frame Type Indication
output wire pkt_class_valid_9, // Frame Type Indication Valid
input wire data_tx_error_9, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_9, // Data from FIFO transmit
input wire data_tx_valid_9, // Data FIFO transmit Empty
input wire data_tx_sop_9, // Start of Packet
input wire data_tx_eop_9, // END of Packet
output wire data_tx_ready_9, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_9, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_9, // Forward Current Frame with CRC from Application
input wire xoff_gen_9, // Xoff Pause frame generate
input wire xon_gen_9, // Xon Pause frame generate
input wire magic_sleep_n_9, // Enable Sleep Mode
output wire magic_wakeup_9, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_9, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_9, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_9, // address to PHYIP management interface
input wire phy_mgmt_read_9, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_9, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_9, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_9, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_9,// writedata to PHYIP management interface
// CHANNEL 10
// PCS SIGNALS TO PHY
input wire rxp_10, // Differential Receive Data
output wire txp_10, // Differential Transmit Data
output wire rx_recovclkout_10, // Receiver Recovered Clock
output wire led_crs_10, // Carrier Sense
output wire led_link_10, // Valid Link
output wire led_col_10, // Collision Indication
output wire led_an_10, // Auto-Negotiation Status
output wire led_char_err_10, // Character Error
output wire led_disp_err_10, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_10, // Av-ST Receive Clock
output wire mac_tx_clk_10, // Av-ST Transmit Clock
output wire data_rx_sop_10, // Start of Packet
output wire data_rx_eop_10, // End of Packet
output wire [7:0] data_rx_data_10, // Data from FIFO
output wire [4:0] data_rx_error_10, // Receive packet error
output wire data_rx_valid_10, // Data Receive FIFO Valid
input wire data_rx_ready_10, // Data Receive Ready
output wire [4:0] pkt_class_data_10, // Frame Type Indication
output wire pkt_class_valid_10, // Frame Type Indication Valid
input wire data_tx_error_10, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_10, // Data from FIFO transmit
input wire data_tx_valid_10, // Data FIFO transmit Empty
input wire data_tx_sop_10, // Start of Packet
input wire data_tx_eop_10, // END of Packet
output wire data_tx_ready_10, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_10, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_10, // Forward Current Frame with CRC from Application
input wire xoff_gen_10, // Xoff Pause frame generate
input wire xon_gen_10, // Xon Pause frame generate
input wire magic_sleep_n_10, // Enable Sleep Mode
output wire magic_wakeup_10, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_10, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_10, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_10, // address to PHYIP management interface
input wire phy_mgmt_read_10, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_10, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_10, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_10, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_10,// writedata to PHYIP management interface
// CHANNEL 11
// PCS SIGNALS TO PHY
input wire rxp_11, // Differential Receive Data
output wire txp_11, // Differential Transmit Data
output wire rx_recovclkout_11, // Receiver Recovered Clock
output wire led_crs_11, // Carrier Sense
output wire led_link_11, // Valid Link
output wire led_col_11, // Collision Indication
output wire led_an_11, // Auto-Negotiation Status
output wire led_char_err_11, // Character Error
output wire led_disp_err_11, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_11, // Av-ST Receive Clock
output wire mac_tx_clk_11, // Av-ST Transmit Clock
output wire data_rx_sop_11, // Start of Packet
output wire data_rx_eop_11, // End of Packet
output wire [7:0] data_rx_data_11, // Data from FIFO
output wire [4:0] data_rx_error_11, // Receive packet error
output wire data_rx_valid_11, // Data Receive FIFO Valid
input wire data_rx_ready_11, // Data Receive Ready
output wire [4:0] pkt_class_data_11, // Frame Type Indication
output wire pkt_class_valid_11, // Frame Type Indication Valid
input wire data_tx_error_11, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_11, // Data from FIFO transmit
input wire data_tx_valid_11, // Data FIFO transmit Empty
input wire data_tx_sop_11, // Start of Packet
input wire data_tx_eop_11, // END of Packet
output wire data_tx_ready_11, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_11, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_11, // Forward Current Frame with CRC from Application
input wire xoff_gen_11, // Xoff Pause frame generate
input wire xon_gen_11, // Xon Pause frame generate
input wire magic_sleep_n_11, // Enable Sleep Mode
output wire magic_wakeup_11, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_11, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_11, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_11, // address to PHYIP management interface
input wire phy_mgmt_read_11, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_11, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_11, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_11, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_11,// writedata to PHYIP management interface
// CHANNEL 12
// PCS SIGNALS TO PHY
input wire rxp_12, // Differential Receive Data
output wire txp_12, // Differential Transmit Data
output wire rx_recovclkout_12, // Receiver Recovered Clock
output wire led_crs_12, // Carrier Sense
output wire led_link_12, // Valid Link
output wire led_col_12, // Collision Indication
output wire led_an_12, // Auto-Negotiation Status
output wire led_char_err_12, // Character Error
output wire led_disp_err_12, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_12, // Av-ST Receive Clock
output wire mac_tx_clk_12, // Av-ST Transmit Clock
output wire data_rx_sop_12, // Start of Packet
output wire data_rx_eop_12, // End of Packet
output wire [7:0] data_rx_data_12, // Data from FIFO
output wire [4:0] data_rx_error_12, // Receive packet error
output wire data_rx_valid_12, // Data Receive FIFO Valid
input wire data_rx_ready_12, // Data Receive Ready
output wire [4:0] pkt_class_data_12, // Frame Type Indication
output wire pkt_class_valid_12, // Frame Type Indication Valid
input wire data_tx_error_12, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_12, // Data from FIFO transmit
input wire data_tx_valid_12, // Data FIFO transmit Empty
input wire data_tx_sop_12, // Start of Packet
input wire data_tx_eop_12, // END of Packet
output wire data_tx_ready_12, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_12, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_12, // Forward Current Frame with CRC from Application
input wire xoff_gen_12, // Xoff Pause frame generate
input wire xon_gen_12, // Xon Pause frame generate
input wire magic_sleep_n_12, // Enable Sleep Mode
output wire magic_wakeup_12, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_12, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_12, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_12, // address to PHYIP management interface
input wire phy_mgmt_read_12, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_12, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_12, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_12, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_12,// writedata to PHYIP management interface
// CHANNEL 13
// PCS SIGNALS TO PHY
input wire rxp_13, // Differential Receive Data
output wire txp_13, // Differential Transmit Data
output wire rx_recovclkout_13, // Receiver Recovered Clock
output wire led_crs_13, // Carrier Sense
output wire led_link_13, // Valid Link
output wire led_col_13, // Collision Indication
output wire led_an_13, // Auto-Negotiation Status
output wire led_char_err_13, // Character Error
output wire led_disp_err_13, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_13, // Av-ST Receive Clock
output wire mac_tx_clk_13, // Av-ST Transmit Clock
output wire data_rx_sop_13, // Start of Packet
output wire data_rx_eop_13, // End of Packet
output wire [7:0] data_rx_data_13, // Data from FIFO
output wire [4:0] data_rx_error_13, // Receive packet error
output wire data_rx_valid_13, // Data Receive FIFO Valid
input wire data_rx_ready_13, // Data Receive Ready
output wire [4:0] pkt_class_data_13, // Frame Type Indication
output wire pkt_class_valid_13, // Frame Type Indication Valid
input wire data_tx_error_13, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_13, // Data from FIFO transmit
input wire data_tx_valid_13, // Data FIFO transmit Empty
input wire data_tx_sop_13, // Start of Packet
input wire data_tx_eop_13, // END of Packet
output wire data_tx_ready_13, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_13, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_13, // Forward Current Frame with CRC from Application
input wire xoff_gen_13, // Xoff Pause frame generate
input wire xon_gen_13, // Xon Pause frame generate
input wire magic_sleep_n_13, // Enable Sleep Mode
output wire magic_wakeup_13, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_13, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_13, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_13, // address to PHYIP management interface
input wire phy_mgmt_read_13, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_13, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_13, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_13, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_13,// writedata to PHYIP management interface
// CHANNEL 14
// PCS SIGNALS TO PHY
input wire rxp_14, // Differential Receive Data
output wire txp_14, // Differential Transmit Data
output wire rx_recovclkout_14, // Receiver Recovered Clock
output wire led_crs_14, // Carrier Sense
output wire led_link_14, // Valid Link
output wire led_col_14, // Collision Indication
output wire led_an_14, // Auto-Negotiation Status
output wire led_char_err_14, // Character Error
output wire led_disp_err_14, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_14, // Av-ST Receive Clock
output wire mac_tx_clk_14, // Av-ST Transmit Clock
output wire data_rx_sop_14, // Start of Packet
output wire data_rx_eop_14, // End of Packet
output wire [7:0] data_rx_data_14, // Data from FIFO
output wire [4:0] data_rx_error_14, // Receive packet error
output wire data_rx_valid_14, // Data Receive FIFO Valid
input wire data_rx_ready_14, // Data Receive Ready
output wire [4:0] pkt_class_data_14, // Frame Type Indication
output wire pkt_class_valid_14, // Frame Type Indication Valid
input wire data_tx_error_14, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_14, // Data from FIFO transmit
input wire data_tx_valid_14, // Data FIFO transmit Empty
input wire data_tx_sop_14, // Start of Packet
input wire data_tx_eop_14, // END of Packet
output wire data_tx_ready_14, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_14, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_14, // Forward Current Frame with CRC from Application
input wire xoff_gen_14, // Xoff Pause frame generate
input wire xon_gen_14, // Xon Pause frame generate
input wire magic_sleep_n_14, // Enable Sleep Mode
output wire magic_wakeup_14, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_14, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_14, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_14, // address to PHYIP management interface
input wire phy_mgmt_read_14, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_14, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_14, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_14, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_14,// writedata to PHYIP management interface
// CHANNEL 15
// PCS SIGNALS TO PHY
input wire rxp_15, // Differential Receive Data
output wire txp_15, // Differential Transmit Data
output wire rx_recovclkout_15, // Receiver Recovered Clock
output wire led_crs_15, // Carrier Sense
output wire led_link_15, // Valid Link
output wire led_col_15, // Collision Indication
output wire led_an_15, // Auto-Negotiation Status
output wire led_char_err_15, // Character Error
output wire led_disp_err_15, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_15, // Av-ST Receive Clock
output wire mac_tx_clk_15, // Av-ST Transmit Clock
output wire data_rx_sop_15, // Start of Packet
output wire data_rx_eop_15, // End of Packet
output wire [7:0] data_rx_data_15, // Data from FIFO
output wire [4:0] data_rx_error_15, // Receive packet error
output wire data_rx_valid_15, // Data Receive FIFO Valid
input wire data_rx_ready_15, // Data Receive Ready
output wire [4:0] pkt_class_data_15, // Frame Type Indication
output wire pkt_class_valid_15, // Frame Type Indication Valid
input wire data_tx_error_15, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_15, // Data from FIFO transmit
input wire data_tx_valid_15, // Data FIFO transmit Empty
input wire data_tx_sop_15, // Start of Packet
input wire data_tx_eop_15, // END of Packet
output wire data_tx_ready_15, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_15, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_15, // Forward Current Frame with CRC from Application
input wire xoff_gen_15, // Xoff Pause frame generate
input wire xon_gen_15, // Xon Pause frame generate
input wire magic_sleep_n_15, // Enable Sleep Mode
output wire magic_wakeup_15, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_15, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_15, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_15, // address to PHYIP management interface
input wire phy_mgmt_read_15, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_15, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_15, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_15, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_15,// writedata to PHYIP management interface
// CHANNEL 16
// PCS SIGNALS TO PHY
input wire rxp_16, // Differential Receive Data
output wire txp_16, // Differential Transmit Data
output wire rx_recovclkout_16, // Receiver Recovered Clock
output wire led_crs_16, // Carrier Sense
output wire led_link_16, // Valid Link
output wire led_col_16, // Collision Indication
output wire led_an_16, // Auto-Negotiation Status
output wire led_char_err_16, // Character Error
output wire led_disp_err_16, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_16, // Av-ST Receive Clock
output wire mac_tx_clk_16, // Av-ST Transmit Clock
output wire data_rx_sop_16, // Start of Packet
output wire data_rx_eop_16, // End of Packet
output wire [7:0] data_rx_data_16, // Data from FIFO
output wire [4:0] data_rx_error_16, // Receive packet error
output wire data_rx_valid_16, // Data Receive FIFO Valid
input wire data_rx_ready_16, // Data Receive Ready
output wire [4:0] pkt_class_data_16, // Frame Type Indication
output wire pkt_class_valid_16, // Frame Type Indication Valid
input wire data_tx_error_16, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_16, // Data from FIFO transmit
input wire data_tx_valid_16, // Data FIFO transmit Empty
input wire data_tx_sop_16, // Start of Packet
input wire data_tx_eop_16, // END of Packet
output wire data_tx_ready_16, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_16, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_16, // Forward Current Frame with CRC from Application
input wire xoff_gen_16, // Xoff Pause frame generate
input wire xon_gen_16, // Xon Pause frame generate
input wire magic_sleep_n_16, // Enable Sleep Mode
output wire magic_wakeup_16, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_16, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_16, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_16, // address to PHYIP management interface
input wire phy_mgmt_read_16, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_16, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_16, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_16, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_16,// writedata to PHYIP management interface
// CHANNEL 17
// PCS SIGNALS TO PHY
input wire rxp_17, // Differential Receive Data
output wire txp_17, // Differential Transmit Data
output wire rx_recovclkout_17, // Receiver Recovered Clock
output wire led_crs_17, // Carrier Sense
output wire led_link_17, // Valid Link
output wire led_col_17, // Collision Indication
output wire led_an_17, // Auto-Negotiation Status
output wire led_char_err_17, // Character Error
output wire led_disp_err_17, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_17, // Av-ST Receive Clock
output wire mac_tx_clk_17, // Av-ST Transmit Clock
output wire data_rx_sop_17, // Start of Packet
output wire data_rx_eop_17, // End of Packet
output wire [7:0] data_rx_data_17, // Data from FIFO
output wire [4:0] data_rx_error_17, // Receive packet error
output wire data_rx_valid_17, // Data Receive FIFO Valid
input wire data_rx_ready_17, // Data Receive Ready
output wire [4:0] pkt_class_data_17, // Frame Type Indication
output wire pkt_class_valid_17, // Frame Type Indication Valid
input wire data_tx_error_17, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_17, // Data from FIFO transmit
input wire data_tx_valid_17, // Data FIFO transmit Empty
input wire data_tx_sop_17, // Start of Packet
input wire data_tx_eop_17, // END of Packet
output wire data_tx_ready_17, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_17, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_17, // Forward Current Frame with CRC from Application
input wire xoff_gen_17, // Xoff Pause frame generate
input wire xon_gen_17, // Xon Pause frame generate
input wire magic_sleep_n_17, // Enable Sleep Mode
output wire magic_wakeup_17, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_17, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_17, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_17, // address to PHYIP management interface
input wire phy_mgmt_read_17, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_17, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_17, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_17, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_17,// writedata to PHYIP management interface
// CHANNEL 18
// PCS SIGNALS TO PHY
input wire rxp_18, // Differential Receive Data
output wire txp_18, // Differential Transmit Data
output wire rx_recovclkout_18, // Receiver Recovered Clock
output wire led_crs_18, // Carrier Sense
output wire led_link_18, // Valid Link
output wire led_col_18, // Collision Indication
output wire led_an_18, // Auto-Negotiation Status
output wire led_char_err_18, // Character Error
output wire led_disp_err_18, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_18, // Av-ST Receive Clock
output wire mac_tx_clk_18, // Av-ST Transmit Clock
output wire data_rx_sop_18, // Start of Packet
output wire data_rx_eop_18, // End of Packet
output wire [7:0] data_rx_data_18, // Data from FIFO
output wire [4:0] data_rx_error_18, // Receive packet error
output wire data_rx_valid_18, // Data Receive FIFO Valid
input wire data_rx_ready_18, // Data Receive Ready
output wire [4:0] pkt_class_data_18, // Frame Type Indication
output wire pkt_class_valid_18, // Frame Type Indication Valid
input wire data_tx_error_18, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_18, // Data from FIFO transmit
input wire data_tx_valid_18, // Data FIFO transmit Empty
input wire data_tx_sop_18, // Start of Packet
input wire data_tx_eop_18, // END of Packet
output wire data_tx_ready_18, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_18, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_18, // Forward Current Frame with CRC from Application
input wire xoff_gen_18, // Xoff Pause frame generate
input wire xon_gen_18, // Xon Pause frame generate
input wire magic_sleep_n_18, // Enable Sleep Mode
output wire magic_wakeup_18, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_18, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_18, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_18, // address to PHYIP management interface
input wire phy_mgmt_read_18, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_18, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_18, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_18, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_18,// writedata to PHYIP management interface
// CHANNEL 19
// PCS SIGNALS TO PHY
input wire rxp_19, // Differential Receive Data
output wire txp_19, // Differential Transmit Data
output wire rx_recovclkout_19, // Receiver Recovered Clock
output wire led_crs_19, // Carrier Sense
output wire led_link_19, // Valid Link
output wire led_col_19, // Collision Indication
output wire led_an_19, // Auto-Negotiation Status
output wire led_char_err_19, // Character Error
output wire led_disp_err_19, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_19, // Av-ST Receive Clock
output wire mac_tx_clk_19, // Av-ST Transmit Clock
output wire data_rx_sop_19, // Start of Packet
output wire data_rx_eop_19, // End of Packet
output wire [7:0] data_rx_data_19, // Data from FIFO
output wire [4:0] data_rx_error_19, // Receive packet error
output wire data_rx_valid_19, // Data Receive FIFO Valid
input wire data_rx_ready_19, // Data Receive Ready
output wire [4:0] pkt_class_data_19, // Frame Type Indication
output wire pkt_class_valid_19, // Frame Type Indication Valid
input wire data_tx_error_19, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_19, // Data from FIFO transmit
input wire data_tx_valid_19, // Data FIFO transmit Empty
input wire data_tx_sop_19, // Start of Packet
input wire data_tx_eop_19, // END of Packet
output wire data_tx_ready_19, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_19, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_19, // Forward Current Frame with CRC from Application
input wire xoff_gen_19, // Xoff Pause frame generate
input wire xon_gen_19, // Xon Pause frame generate
input wire magic_sleep_n_19, // Enable Sleep Mode
output wire magic_wakeup_19, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_19, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_19, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_19, // address to PHYIP management interface
input wire phy_mgmt_read_19, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_19, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_19, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_19, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_19,// writedata to PHYIP management interface
// CHANNEL 20
// PCS SIGNALS TO PHY
input wire rxp_20, // Differential Receive Data
output wire txp_20, // Differential Transmit Data
output wire rx_recovclkout_20, // Receiver Recovered Clock
output wire led_crs_20, // Carrier Sense
output wire led_link_20, // Valid Link
output wire led_col_20, // Collision Indication
output wire led_an_20, // Auto-Negotiation Status
output wire led_char_err_20, // Character Error
output wire led_disp_err_20, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_20, // Av-ST Receive Clock
output wire mac_tx_clk_20, // Av-ST Transmit Clock
output wire data_rx_sop_20, // Start of Packet
output wire data_rx_eop_20, // End of Packet
output wire [7:0] data_rx_data_20, // Data from FIFO
output wire [4:0] data_rx_error_20, // Receive packet error
output wire data_rx_valid_20, // Data Receive FIFO Valid
input wire data_rx_ready_20, // Data Receive Ready
output wire [4:0] pkt_class_data_20, // Frame Type Indication
output wire pkt_class_valid_20, // Frame Type Indication Valid
input wire data_tx_error_20, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_20, // Data from FIFO transmit
input wire data_tx_valid_20, // Data FIFO transmit Empty
input wire data_tx_sop_20, // Start of Packet
input wire data_tx_eop_20, // END of Packet
output wire data_tx_ready_20, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_20, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_20, // Forward Current Frame with CRC from Application
input wire xoff_gen_20, // Xoff Pause frame generate
input wire xon_gen_20, // Xon Pause frame generate
input wire magic_sleep_n_20, // Enable Sleep Mode
output wire magic_wakeup_20, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_20, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_20, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_20, // address to PHYIP management interface
input wire phy_mgmt_read_20, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_20, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_20, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_20, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_20,// writedata to PHYIP management interface
// CHANNEL 21
// PCS SIGNALS TO PHY
input wire rxp_21, // Differential Receive Data
output wire txp_21, // Differential Transmit Data
output wire rx_recovclkout_21, // Receiver Recovered Clock
output wire led_crs_21, // Carrier Sense
output wire led_link_21, // Valid Link
output wire led_col_21, // Collision Indication
output wire led_an_21, // Auto-Negotiation Status
output wire led_char_err_21, // Character Error
output wire led_disp_err_21, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_21, // Av-ST Receive Clock
output wire mac_tx_clk_21, // Av-ST Transmit Clock
output wire data_rx_sop_21, // Start of Packet
output wire data_rx_eop_21, // End of Packet
output wire [7:0] data_rx_data_21, // Data from FIFO
output wire [4:0] data_rx_error_21, // Receive packet error
output wire data_rx_valid_21, // Data Receive FIFO Valid
input wire data_rx_ready_21, // Data Receive Ready
output wire [4:0] pkt_class_data_21, // Frame Type Indication
output wire pkt_class_valid_21, // Frame Type Indication Valid
input wire data_tx_error_21, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_21, // Data from FIFO transmit
input wire data_tx_valid_21, // Data FIFO transmit Empty
input wire data_tx_sop_21, // Start of Packet
input wire data_tx_eop_21, // END of Packet
output wire data_tx_ready_21, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_21, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_21, // Forward Current Frame with CRC from Application
input wire xoff_gen_21, // Xoff Pause frame generate
input wire xon_gen_21, // Xon Pause frame generate
input wire magic_sleep_n_21, // Enable Sleep Mode
output wire magic_wakeup_21, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_21, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_21, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_21, // address to PHYIP management interface
input wire phy_mgmt_read_21, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_21, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_21, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_21, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_21,// writedata to PHYIP management interface
// CHANNEL 22
// PCS SIGNALS TO PHY
input wire rxp_22, // Differential Receive Data
output wire txp_22, // Differential Transmit Data
output wire rx_recovclkout_22, // Receiver Recovered Clock
output wire led_crs_22, // Carrier Sense
output wire led_link_22, // Valid Link
output wire led_col_22, // Collision Indication
output wire led_an_22, // Auto-Negotiation Status
output wire led_char_err_22, // Character Error
output wire led_disp_err_22, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_22, // Av-ST Receive Clock
output wire mac_tx_clk_22, // Av-ST Transmit Clock
output wire data_rx_sop_22, // Start of Packet
output wire data_rx_eop_22, // End of Packet
output wire [7:0] data_rx_data_22, // Data from FIFO
output wire [4:0] data_rx_error_22, // Receive packet error
output wire data_rx_valid_22, // Data Receive FIFO Valid
input wire data_rx_ready_22, // Data Receive Ready
output wire [4:0] pkt_class_data_22, // Frame Type Indication
output wire pkt_class_valid_22, // Frame Type Indication Valid
input wire data_tx_error_22, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_22, // Data from FIFO transmit
input wire data_tx_valid_22, // Data FIFO transmit Empty
input wire data_tx_sop_22, // Start of Packet
input wire data_tx_eop_22, // END of Packet
output wire data_tx_ready_22, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_22, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_22, // Forward Current Frame with CRC from Application
input wire xoff_gen_22, // Xoff Pause frame generate
input wire xon_gen_22, // Xon Pause frame generate
input wire magic_sleep_n_22, // Enable Sleep Mode
output wire magic_wakeup_22, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_22, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_22, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_22, // address to PHYIP management interface
input wire phy_mgmt_read_22, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_22, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_22, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_22, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_22,// writedata to PHYIP management interface
// CHANNEL 23
// PCS SIGNALS TO PHY
input wire rxp_23, // Differential Receive Data
output wire txp_23, // Differential Transmit Data
output wire rx_recovclkout_23, // Receiver Recovered Clock
output wire led_crs_23, // Carrier Sense
output wire led_link_23, // Valid Link
output wire led_col_23, // Collision Indication
output wire led_an_23, // Auto-Negotiation Status
output wire led_char_err_23, // Character Error
output wire led_disp_err_23, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_23, // Av-ST Receive Clock
output wire mac_tx_clk_23, // Av-ST Transmit Clock
output wire data_rx_sop_23, // Start of Packet
output wire data_rx_eop_23, // End of Packet
output wire [7:0] data_rx_data_23, // Data from FIFO
output wire [4:0] data_rx_error_23, // Receive packet error
output wire data_rx_valid_23, // Data Receive FIFO Valid
input wire data_rx_ready_23, // Data Receive Ready
output wire [4:0] pkt_class_data_23, // Frame Type Indication
output wire pkt_class_valid_23, // Frame Type Indication Valid
input wire data_tx_error_23, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_23, // Data from FIFO transmit
input wire data_tx_valid_23, // Data FIFO transmit Empty
input wire data_tx_sop_23, // Start of Packet
input wire data_tx_eop_23, // END of Packet
output wire data_tx_ready_23, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_23, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_23, // Forward Current Frame with CRC from Application
input wire xoff_gen_23, // Xoff Pause frame generate
input wire xon_gen_23, // Xon Pause frame generate
input wire magic_sleep_n_23, // Enable Sleep Mode
output wire magic_wakeup_23, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_23, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_23, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_23, // address to PHYIP management interface
input wire phy_mgmt_read_23, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_23, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_23, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_23, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_23);// writedata to PHYIP management interface
wire MAC_PCS_reset;
wire [23:0] pcs_pwrdn_out_sig;
wire [23:0] gxb_pwrdn_in_sig;
wire gige_pma_reset;
wire [23:0] led_char_err_gx;
wire [23:0] link_status;
//wire [23:0] pcs_clk;
wire tx_pcs_clk_c0;
wire tx_pcs_clk_c1;
wire tx_pcs_clk_c2;
wire tx_pcs_clk_c3;
wire tx_pcs_clk_c4;
wire tx_pcs_clk_c5;
wire tx_pcs_clk_c6;
wire tx_pcs_clk_c7;
wire tx_pcs_clk_c8;
wire tx_pcs_clk_c9;
wire tx_pcs_clk_c10;
wire tx_pcs_clk_c11;
wire tx_pcs_clk_c12;
wire tx_pcs_clk_c13;
wire tx_pcs_clk_c14;
wire tx_pcs_clk_c15;
wire tx_pcs_clk_c16;
wire tx_pcs_clk_c17;
wire tx_pcs_clk_c18;
wire tx_pcs_clk_c19;
wire tx_pcs_clk_c20;
wire tx_pcs_clk_c21;
wire tx_pcs_clk_c22;
wire tx_pcs_clk_c23;
wire rx_pcs_clk_c0;
wire rx_pcs_clk_c1;
wire rx_pcs_clk_c2;
wire rx_pcs_clk_c3;
wire rx_pcs_clk_c4;
wire rx_pcs_clk_c5;
wire rx_pcs_clk_c6;
wire rx_pcs_clk_c7;
wire rx_pcs_clk_c8;
wire rx_pcs_clk_c9;
wire rx_pcs_clk_c10;
wire rx_pcs_clk_c11;
wire rx_pcs_clk_c12;
wire rx_pcs_clk_c13;
wire rx_pcs_clk_c14;
wire rx_pcs_clk_c15;
wire rx_pcs_clk_c16;
wire rx_pcs_clk_c17;
wire rx_pcs_clk_c18;
wire rx_pcs_clk_c19;
wire rx_pcs_clk_c20;
wire rx_pcs_clk_c21;
wire rx_pcs_clk_c22;
wire rx_pcs_clk_c23;
wire [23:0] rx_char_err_gx;
wire [23:0] rx_disp_err;
wire [23:0] rx_syncstatus;
wire [23:0] rx_runlengthviolation;
wire [23:0] rx_patterndetect;
wire [23:0] rx_runningdisp;
wire [23:0] rx_rmfifodatadeleted;
wire [23:0] rx_rmfifodatainserted;
wire [23:0] pcs_rx_rmfifodatadeleted;
wire [23:0] pcs_rx_rmfifodatainserted;
wire [23:0] pcs_rx_carrierdetected;
wire rx_kchar_0;
wire [7:0] rx_frame_0;
wire pcs_rx_kchar_0;
wire [7:0] pcs_rx_frame_0;
wire tx_kchar_0;
wire [7:0] tx_frame_0;
wire rx_kchar_1;
wire [7:0] rx_frame_1;
wire pcs_rx_kchar_1;
wire [7:0] pcs_rx_frame_1;
wire tx_kchar_1;
wire [7:0] tx_frame_1;
wire rx_kchar_2;
wire [7:0] rx_frame_2;
wire pcs_rx_kchar_2;
wire [7:0] pcs_rx_frame_2;
wire tx_kchar_2;
wire [7:0] tx_frame_2;
wire rx_kchar_3;
wire [7:0] rx_frame_3;
wire pcs_rx_kchar_3;
wire [7:0] pcs_rx_frame_3;
wire tx_kchar_3;
wire [7:0] tx_frame_3;
wire rx_kchar_4;
wire [7:0] rx_frame_4;
wire pcs_rx_kchar_4;
wire [7:0] pcs_rx_frame_4;
wire tx_kchar_4;
wire [7:0] tx_frame_4;
wire rx_kchar_5;
wire [7:0] rx_frame_5;
wire pcs_rx_kchar_5;
wire [7:0] pcs_rx_frame_5;
wire tx_kchar_5;
wire [7:0] tx_frame_5;
wire rx_kchar_6;
wire [7:0] rx_frame_6;
wire pcs_rx_kchar_6;
wire [7:0] pcs_rx_frame_6;
wire tx_kchar_6;
wire [7:0] tx_frame_6;
wire rx_kchar_7;
wire [7:0] rx_frame_7;
wire pcs_rx_kchar_7;
wire [7:0] pcs_rx_frame_7;
wire tx_kchar_7;
wire [7:0] tx_frame_7;
wire rx_kchar_8;
wire [7:0] rx_frame_8;
wire pcs_rx_kchar_8;
wire [7:0] pcs_rx_frame_8;
wire tx_kchar_8;
wire [7:0] tx_frame_8;
wire rx_kchar_9;
wire [7:0] rx_frame_9;
wire pcs_rx_kchar_9;
wire [7:0] pcs_rx_frame_9;
wire tx_kchar_9;
wire [7:0] tx_frame_9;
wire rx_kchar_10;
wire [7:0] rx_frame_10;
wire pcs_rx_kchar_10;
wire [7:0] pcs_rx_frame_10;
wire tx_kchar_10;
wire [7:0] tx_frame_10;
wire rx_kchar_11;
wire [7:0] rx_frame_11;
wire pcs_rx_kchar_11;
wire [7:0] pcs_rx_frame_11;
wire tx_kchar_11;
wire [7:0] tx_frame_11;
wire rx_kchar_12;
wire [7:0] rx_frame_12;
wire pcs_rx_kchar_12;
wire [7:0] pcs_rx_frame_12;
wire tx_kchar_12;
wire [7:0] tx_frame_12;
wire rx_kchar_13;
wire [7:0] rx_frame_13;
wire pcs_rx_kchar_13;
wire [7:0] pcs_rx_frame_13;
wire tx_kchar_13;
wire [7:0] tx_frame_13;
wire rx_kchar_14;
wire [7:0] rx_frame_14;
wire pcs_rx_kchar_14;
wire [7:0] pcs_rx_frame_14;
wire tx_kchar_14;
wire [7:0] tx_frame_14;
wire rx_kchar_15;
wire [7:0] rx_frame_15;
wire pcs_rx_kchar_15;
wire [7:0] pcs_rx_frame_15;
wire tx_kchar_15;
wire [7:0] tx_frame_15;
wire rx_kchar_16;
wire [7:0] rx_frame_16;
wire pcs_rx_kchar_16;
wire [7:0] pcs_rx_frame_16;
wire tx_kchar_16;
wire [7:0] tx_frame_16;
wire rx_kchar_17;
wire [7:0] rx_frame_17;
wire pcs_rx_kchar_17;
wire [7:0] pcs_rx_frame_17;
wire tx_kchar_17;
wire [7:0] tx_frame_17;
wire rx_kchar_18;
wire [7:0] rx_frame_18;
wire pcs_rx_kchar_18;
wire [7:0] pcs_rx_frame_18;
wire tx_kchar_18;
wire [7:0] tx_frame_18;
wire rx_kchar_19;
wire [7:0] rx_frame_19;
wire pcs_rx_kchar_19;
wire [7:0] pcs_rx_frame_19;
wire tx_kchar_19;
wire [7:0] tx_frame_19;
wire rx_kchar_20;
wire [7:0] rx_frame_20;
wire pcs_rx_kchar_20;
wire [7:0] pcs_rx_frame_20;
wire tx_kchar_20;
wire [7:0] tx_frame_20;
wire rx_kchar_21;
wire [7:0] rx_frame_21;
wire pcs_rx_kchar_21;
wire [7:0] pcs_rx_frame_21;
wire tx_kchar_21;
wire [7:0] tx_frame_21;
wire rx_kchar_22;
wire [7:0] rx_frame_22;
wire pcs_rx_kchar_22;
wire [7:0] pcs_rx_frame_22;
wire tx_kchar_22;
wire [7:0] tx_frame_22;
wire rx_kchar_23;
wire [7:0] rx_frame_23;
wire pcs_rx_kchar_23;
wire [7:0] pcs_rx_frame_23;
wire tx_kchar_23;
wire [7:0] tx_frame_23;
wire sd_loopback_0;
wire sd_loopback_1;
wire sd_loopback_2;
wire sd_loopback_3;
wire sd_loopback_4;
wire sd_loopback_5;
wire sd_loopback_6;
wire sd_loopback_7;
wire sd_loopback_8;
wire sd_loopback_9;
wire sd_loopback_10;
wire sd_loopback_11;
wire sd_loopback_12;
wire sd_loopback_13;
wire sd_loopback_14;
wire sd_loopback_15;
wire sd_loopback_16;
wire sd_loopback_17;
wire sd_loopback_18;
wire sd_loopback_19;
wire sd_loopback_20;
wire sd_loopback_21;
wire sd_loopback_22;
wire sd_loopback_23;
wire reset_rx_pcs_clk_c0_int;
wire reset_rx_pcs_clk_c1_int;
wire reset_rx_pcs_clk_c2_int;
wire reset_rx_pcs_clk_c3_int;
wire reset_rx_pcs_clk_c4_int;
wire reset_rx_pcs_clk_c5_int;
wire reset_rx_pcs_clk_c6_int;
wire reset_rx_pcs_clk_c7_int;
wire reset_rx_pcs_clk_c8_int;
wire reset_rx_pcs_clk_c9_int;
wire reset_rx_pcs_clk_c10_int;
wire reset_rx_pcs_clk_c11_int;
wire reset_rx_pcs_clk_c12_int;
wire reset_rx_pcs_clk_c13_int;
wire reset_rx_pcs_clk_c14_int;
wire reset_rx_pcs_clk_c15_int;
wire reset_rx_pcs_clk_c16_int;
wire reset_rx_pcs_clk_c17_int;
wire reset_rx_pcs_clk_c18_int;
wire reset_rx_pcs_clk_c19_int;
wire reset_rx_pcs_clk_c20_int;
wire reset_rx_pcs_clk_c21_int;
wire reset_rx_pcs_clk_c22_int;
wire reset_rx_pcs_clk_c23_int;
//assign pcs_clk = {pcs_clk_c23,pcs_clk_c22,pcs_clk_c21,pcs_clk_c20,pcs_clk_c19,pcs_clk_c18,pcs_clk_c17,pcs_clk_c16,pcs_clk_c15,pcs_clk_c14,pcs_clk_c13,pcs_clk_c12,pcs_clk_c11,pcs_clk_c10,pcs_clk_c9,pcs_clk_c8,pcs_clk_c7,pcs_clk_c6,pcs_clk_c5,pcs_clk_c4,pcs_clk_c3,pcs_clk_c2,pcs_clk_c1,pcs_clk_c0};
// Assign the character error and link status to top level leds
// ------------------------------------------------------------
assign led_char_err_0 = led_char_err_gx[0];
assign led_link_0 = link_status[0];
assign led_char_err_1 = led_char_err_gx[1];
assign led_link_1 = link_status[1];
assign led_char_err_2 = led_char_err_gx[2];
assign led_link_2 = link_status[2];
assign led_char_err_3 = led_char_err_gx[3];
assign led_link_3 = link_status[3];
assign led_char_err_4 = led_char_err_gx[4];
assign led_link_4 = link_status[4];
assign led_char_err_5 = led_char_err_gx[5];
assign led_link_5 = link_status[5];
assign led_char_err_6 = led_char_err_gx[6];
assign led_link_6 = link_status[6];
assign led_char_err_7 = led_char_err_gx[7];
assign led_link_7 = link_status[7];
assign led_char_err_8 = led_char_err_gx[8];
assign led_link_8 = link_status[8];
assign led_char_err_9 = led_char_err_gx[9];
assign led_link_9 = link_status[9];
assign led_char_err_10 = led_char_err_gx[10];
assign led_link_10 = link_status[10];
assign led_char_err_11 = led_char_err_gx[11];
assign led_link_11 = link_status[11];
assign led_char_err_12 = led_char_err_gx[12];
assign led_link_12 = link_status[12];
assign led_char_err_13 = led_char_err_gx[13];
assign led_link_13 = link_status[13];
assign led_char_err_14 = led_char_err_gx[14];
assign led_link_14 = link_status[14];
assign led_char_err_15 = led_char_err_gx[15];
assign led_link_15 = link_status[15];
assign led_char_err_16 = led_char_err_gx[16];
assign led_link_16 = link_status[16];
assign led_char_err_17 = led_char_err_gx[17];
assign led_link_17 = link_status[17];
assign led_char_err_18 = led_char_err_gx[18];
assign led_link_18 = link_status[18];
assign led_char_err_19 = led_char_err_gx[19];
assign led_link_19 = link_status[19];
assign led_char_err_20 = led_char_err_gx[20];
assign led_link_20 = link_status[20];
assign led_char_err_21 = led_char_err_gx[21];
assign led_link_21 = link_status[21];
assign led_char_err_22 = led_char_err_gx[22];
assign led_link_22 = link_status[22];
assign led_char_err_23 = led_char_err_gx[23];
assign led_link_23 = link_status[23];
// Instantiation of the MAC_PCS core that connects to a PMA
// --------------------------------------------------------
altera_tse_top_multi_mac_pcs_gige U_MULTI_MAC_PCS(
.reset(reset), //INPUT : ASYNCHRONOUS RESET - clk DOMAIN
.clk(clk), //INPUT : CLOCK
.read(read), //INPUT : REGISTER READ TRANSACTION
.ref_clk(ref_clk), //INPUT : REFERENCE CLOCK
.write(write), //INPUT : REGISTER WRITE TRANSACTION
.address(address), //INPUT : REGISTER ADDRESS
.writedata(writedata), //INPUT : REGISTER WRITE DATA
.readdata(readdata), //OUTPUT : REGISTER READ DATA
.waitrequest(waitrequest), //OUTPUT : TRANSACTION BUSY, ACTIVE LOW
.mdc(mdc), //OUTPUT : MDIO Clock
.mdio_out(mdio_out), //OUTPUT : Outgoing MDIO DATA
.mdio_in(mdio_in), //INPUT : Incoming MDIO DATA
.mdio_oen(mdio_oen), //OUTPUT : MDIO Output Enable
.mac_rx_clk(mac_rx_clk), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk(mac_tx_clk), //OUTPUT : Av-ST Tx Clock
.rx_afull_clk(rx_afull_clk), //INPUT : AFull Status Clock
.rx_afull_data(rx_afull_data), //INPUT : AFull Status Data
.rx_afull_valid(rx_afull_valid), //INPUT : AFull Status Valid
.rx_afull_channel(rx_afull_channel), //INPUT : AFull Status Channel
// Channel 0
.rx_carrierdetected_0(pcs_rx_carrierdetected[0]),
.rx_rmfifodatadeleted_0(pcs_rx_rmfifodatadeleted[0]),
.rx_rmfifodatainserted_0(pcs_rx_rmfifodatainserted[0]),
.rx_clkout_0(rx_pcs_clk_c0), //INPUT : Receive Clock
.tx_clkout_0(tx_pcs_clk_c0), //INPUT : Transmit Clock
.rx_kchar_0(pcs_rx_kchar_0), //INPUT : Special Character Indication
.tx_kchar_0(tx_kchar_0), //OUTPUT : Special Character Indication
.rx_frame_0(pcs_rx_frame_0), //INPUT : Frame
.tx_frame_0(tx_frame_0), //OUTPUT : Frame
.sd_loopback_0(sd_loopback_0), //OUTPUT : SERDES Loopback Enable
.powerdown_0(pcs_pwrdn_out_sig[0]), //OUTPUT : Powerdown Enable
.led_col_0(led_col_0), //OUTPUT : Collision Indication
.led_an_0(led_an_0), //OUTPUT : Auto Negotiation Status
.led_char_err_0(led_char_err_gx[0]), //INPUT : Character error
.led_crs_0(led_crs_0), //OUTPUT : Carrier sense
.led_link_0(link_status[0]), //INPUT : Valid link
.mac_rx_clk_0(mac_rx_clk_0), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_0(mac_tx_clk_0), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_0(data_rx_sop_0), //OUTPUT : Start of Packet
.data_rx_eop_0(data_rx_eop_0), //OUTPUT : End of Packet
.data_rx_data_0(data_rx_data_0), //OUTPUT : Data from FIFO
.data_rx_error_0(data_rx_error_0), //OUTPUT : Receive packet error
.data_rx_valid_0(data_rx_valid_0), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_0(data_rx_ready_0), //OUTPUT : Data Receive Ready
.pkt_class_data_0(pkt_class_data_0), //OUTPUT : Frame Type Indication
.pkt_class_valid_0(pkt_class_valid_0), //OUTPUT : Frame Type Indication Valid
.data_tx_error_0(data_tx_error_0), //INPUT : Status
.data_tx_data_0(data_tx_data_0), //INPUT : Data from FIFO transmit
.data_tx_valid_0(data_tx_valid_0), //INPUT : Data FIFO transmit Empty
.data_tx_sop_0(data_tx_sop_0), //INPUT : Start of Packet
.data_tx_eop_0(data_tx_eop_0), //INPUT : End of Packet
.data_tx_ready_0(data_tx_ready_0), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_0(tx_ff_uflow_0), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_0(tx_crc_fwd_0), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_0(xoff_gen_0), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_0(xon_gen_0), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_0(magic_sleep_n_0), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_0(magic_wakeup_0), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 1
.rx_carrierdetected_1(pcs_rx_carrierdetected[1]),
.rx_rmfifodatadeleted_1(pcs_rx_rmfifodatadeleted[1]),
.rx_rmfifodatainserted_1(pcs_rx_rmfifodatainserted[1]),
.rx_clkout_1(rx_pcs_clk_c1), //INPUT : Receive Clock
.tx_clkout_1(tx_pcs_clk_c1), //INPUT : Transmit Clock
.rx_kchar_1(pcs_rx_kchar_1), //INPUT : Special Character Indication
.tx_kchar_1(tx_kchar_1), //OUTPUT : Special Character Indication
.rx_frame_1(pcs_rx_frame_1), //INPUT : Frame
.tx_frame_1(tx_frame_1), //OUTPUT : Frame
.sd_loopback_1(sd_loopback_1), //OUTPUT : SERDES Loopback Enable
.powerdown_1(pcs_pwrdn_out_sig[1]), //OUTPUT : Powerdown Enable
.led_col_1(led_col_1), //OUTPUT : Collision Indication
.led_an_1(led_an_1), //OUTPUT : Auto Negotiation Status
.led_char_err_1(led_char_err_gx[1]), //INPUT : Character error
.led_crs_1(led_crs_1), //OUTPUT : Carrier sense
.led_link_1(link_status[1]), //INPUT : Valid link
.mac_rx_clk_1(mac_rx_clk_1), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_1(mac_tx_clk_1), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_1(data_rx_sop_1), //OUTPUT : Start of Packet
.data_rx_eop_1(data_rx_eop_1), //OUTPUT : End of Packet
.data_rx_data_1(data_rx_data_1), //OUTPUT : Data from FIFO
.data_rx_error_1(data_rx_error_1), //OUTPUT : Receive packet error
.data_rx_valid_1(data_rx_valid_1), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_1(data_rx_ready_1), //OUTPUT : Data Receive Ready
.pkt_class_data_1(pkt_class_data_1), //OUTPUT : Frame Type Indication
.pkt_class_valid_1(pkt_class_valid_1), //OUTPUT : Frame Type Indication Valid
.data_tx_error_1(data_tx_error_1), //INPUT : Status
.data_tx_data_1(data_tx_data_1), //INPUT : Data from FIFO transmit
.data_tx_valid_1(data_tx_valid_1), //INPUT : Data FIFO transmit Empty
.data_tx_sop_1(data_tx_sop_1), //INPUT : Start of Packet
.data_tx_eop_1(data_tx_eop_1), //INPUT : End of Packet
.data_tx_ready_1(data_tx_ready_1), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_1(tx_ff_uflow_1), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_1(tx_crc_fwd_1), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_1(xoff_gen_1), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_1(xon_gen_1), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_1(magic_sleep_n_1), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_1(magic_wakeup_1), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 2
.rx_carrierdetected_2(pcs_rx_carrierdetected[2]),
.rx_rmfifodatadeleted_2(pcs_rx_rmfifodatadeleted[2]),
.rx_rmfifodatainserted_2(pcs_rx_rmfifodatainserted[2]),
.rx_clkout_2(rx_pcs_clk_c2), //INPUT : Receive Clock
.tx_clkout_2(tx_pcs_clk_c2), //INPUT : Transmit Clock
.rx_kchar_2(pcs_rx_kchar_2), //INPUT : Special Character Indication
.tx_kchar_2(tx_kchar_2), //OUTPUT : Special Character Indication
.rx_frame_2(pcs_rx_frame_2), //INPUT : Frame
.tx_frame_2(tx_frame_2), //OUTPUT : Frame
.sd_loopback_2(sd_loopback_2), //OUTPUT : SERDES Loopback Enable
.powerdown_2(pcs_pwrdn_out_sig[2]), //OUTPUT : Powerdown Enable
.led_col_2(led_col_2), //OUTPUT : Collision Indication
.led_an_2(led_an_2), //OUTPUT : Auto Negotiation Status
.led_char_err_2(led_char_err_gx[2]), //INPUT : Character error
.led_crs_2(led_crs_2), //OUTPUT : Carrier sense
.led_link_2(link_status[2]), //INPUT : Valid link
.mac_rx_clk_2(mac_rx_clk_2), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_2(mac_tx_clk_2), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_2(data_rx_sop_2), //OUTPUT : Start of Packet
.data_rx_eop_2(data_rx_eop_2), //OUTPUT : End of Packet
.data_rx_data_2(data_rx_data_2), //OUTPUT : Data from FIFO
.data_rx_error_2(data_rx_error_2), //OUTPUT : Receive packet error
.data_rx_valid_2(data_rx_valid_2), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_2(data_rx_ready_2), //OUTPUT : Data Receive Ready
.pkt_class_data_2(pkt_class_data_2), //OUTPUT : Frame Type Indication
.pkt_class_valid_2(pkt_class_valid_2), //OUTPUT : Frame Type Indication Valid
.data_tx_error_2(data_tx_error_2), //INPUT : Status
.data_tx_data_2(data_tx_data_2), //INPUT : Data from FIFO transmit
.data_tx_valid_2(data_tx_valid_2), //INPUT : Data FIFO transmit Empty
.data_tx_sop_2(data_tx_sop_2), //INPUT : Start of Packet
.data_tx_eop_2(data_tx_eop_2), //INPUT : End of Packet
.data_tx_ready_2(data_tx_ready_2), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_2(tx_ff_uflow_2), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_2(tx_crc_fwd_2), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_2(xoff_gen_2), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_2(xon_gen_2), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_2(magic_sleep_n_2), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_2(magic_wakeup_2), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 3
.rx_carrierdetected_3(pcs_rx_carrierdetected[3]),
.rx_rmfifodatadeleted_3(pcs_rx_rmfifodatadeleted[3]),
.rx_rmfifodatainserted_3(pcs_rx_rmfifodatainserted[3]),
.rx_clkout_3(rx_pcs_clk_c3), //INPUT : Receive Clock
.tx_clkout_3(tx_pcs_clk_c3), //INPUT : Transmit Clock
.rx_kchar_3(pcs_rx_kchar_3), //INPUT : Special Character Indication
.tx_kchar_3(tx_kchar_3), //OUTPUT : Special Character Indication
.rx_frame_3(pcs_rx_frame_3), //INPUT : Frame
.tx_frame_3(tx_frame_3), //OUTPUT : Frame
.sd_loopback_3(sd_loopback_3), //OUTPUT : SERDES Loopback Enable
.powerdown_3(pcs_pwrdn_out_sig[3]), //OUTPUT : Powerdown Enable
.led_col_3(led_col_3), //OUTPUT : Collision Indication
.led_an_3(led_an_3), //OUTPUT : Auto Negotiation Status
.led_char_err_3(led_char_err_gx[3]), //INPUT : Character error
.led_crs_3(led_crs_3), //OUTPUT : Carrier sense
.led_link_3(link_status[3]), //INPUT : Valid link
.mac_rx_clk_3(mac_rx_clk_3), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_3(mac_tx_clk_3), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_3(data_rx_sop_3), //OUTPUT : Start of Packet
.data_rx_eop_3(data_rx_eop_3), //OUTPUT : End of Packet
.data_rx_data_3(data_rx_data_3), //OUTPUT : Data from FIFO
.data_rx_error_3(data_rx_error_3), //OUTPUT : Receive packet error
.data_rx_valid_3(data_rx_valid_3), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_3(data_rx_ready_3), //OUTPUT : Data Receive Ready
.pkt_class_data_3(pkt_class_data_3), //OUTPUT : Frame Type Indication
.pkt_class_valid_3(pkt_class_valid_3), //OUTPUT : Frame Type Indication Valid
.data_tx_error_3(data_tx_error_3), //INPUT : Status
.data_tx_data_3(data_tx_data_3), //INPUT : Data from FIFO transmit
.data_tx_valid_3(data_tx_valid_3), //INPUT : Data FIFO transmit Empty
.data_tx_sop_3(data_tx_sop_3), //INPUT : Start of Packet
.data_tx_eop_3(data_tx_eop_3), //INPUT : End of Packet
.data_tx_ready_3(data_tx_ready_3), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_3(tx_ff_uflow_3), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_3(tx_crc_fwd_3), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_3(xoff_gen_3), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_3(xon_gen_3), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_3(magic_sleep_n_3), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_3(magic_wakeup_3), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 4
.rx_carrierdetected_4(pcs_rx_carrierdetected[4]),
.rx_rmfifodatadeleted_4(pcs_rx_rmfifodatadeleted[4]),
.rx_rmfifodatainserted_4(pcs_rx_rmfifodatainserted[4]),
.rx_clkout_4(rx_pcs_clk_c4), //INPUT : Receive Clock
.tx_clkout_4(tx_pcs_clk_c4), //INPUT : Transmit Clock
.rx_kchar_4(pcs_rx_kchar_4), //INPUT : Special Character Indication
.tx_kchar_4(tx_kchar_4), //OUTPUT : Special Character Indication
.rx_frame_4(pcs_rx_frame_4), //INPUT : Frame
.tx_frame_4(tx_frame_4), //OUTPUT : Frame
.sd_loopback_4(sd_loopback_4), //OUTPUT : SERDES Loopback Enable
.powerdown_4(pcs_pwrdn_out_sig[4]), //OUTPUT : Powerdown Enable
.led_col_4(led_col_4), //OUTPUT : Collision Indication
.led_an_4(led_an_4), //OUTPUT : Auto Negotiation Status
.led_char_err_4(led_char_err_gx[4]), //INPUT : Character error
.led_crs_4(led_crs_4), //OUTPUT : Carrier sense
.led_link_4(link_status[4]), //INPUT : Valid link
.mac_rx_clk_4(mac_rx_clk_4), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_4(mac_tx_clk_4), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_4(data_rx_sop_4), //OUTPUT : Start of Packet
.data_rx_eop_4(data_rx_eop_4), //OUTPUT : End of Packet
.data_rx_data_4(data_rx_data_4), //OUTPUT : Data from FIFO
.data_rx_error_4(data_rx_error_4), //OUTPUT : Receive packet error
.data_rx_valid_4(data_rx_valid_4), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_4(data_rx_ready_4), //OUTPUT : Data Receive Ready
.pkt_class_data_4(pkt_class_data_4), //OUTPUT : Frame Type Indication
.pkt_class_valid_4(pkt_class_valid_4), //OUTPUT : Frame Type Indication Valid
.data_tx_error_4(data_tx_error_4), //INPUT : Status
.data_tx_data_4(data_tx_data_4), //INPUT : Data from FIFO transmit
.data_tx_valid_4(data_tx_valid_4), //INPUT : Data FIFO transmit Empty
.data_tx_sop_4(data_tx_sop_4), //INPUT : Start of Packet
.data_tx_eop_4(data_tx_eop_4), //INPUT : End of Packet
.data_tx_ready_4(data_tx_ready_4), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_4(tx_ff_uflow_4), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_4(tx_crc_fwd_4), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_4(xoff_gen_4), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_4(xon_gen_4), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_4(magic_sleep_n_4), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_4(magic_wakeup_4), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 5
.rx_carrierdetected_5(pcs_rx_carrierdetected[5]),
.rx_rmfifodatadeleted_5(pcs_rx_rmfifodatadeleted[5]),
.rx_rmfifodatainserted_5(pcs_rx_rmfifodatainserted[5]),
.rx_clkout_5(rx_pcs_clk_c5), //INPUT : Receive Clock
.tx_clkout_5(tx_pcs_clk_c5), //INPUT : Transmit Clock
.rx_kchar_5(pcs_rx_kchar_5), //INPUT : Special Character Indication
.tx_kchar_5(tx_kchar_5), //OUTPUT : Special Character Indication
.rx_frame_5(pcs_rx_frame_5), //INPUT : Frame
.tx_frame_5(tx_frame_5), //OUTPUT : Frame
.sd_loopback_5(sd_loopback_5), //OUTPUT : SERDES Loopback Enable
.powerdown_5(pcs_pwrdn_out_sig[5]), //OUTPUT : Powerdown Enable
.led_col_5(led_col_5), //OUTPUT : Collision Indication
.led_an_5(led_an_5), //OUTPUT : Auto Negotiation Status
.led_char_err_5(led_char_err_gx[5]), //INPUT : Character error
.led_crs_5(led_crs_5), //OUTPUT : Carrier sense
.led_link_5(link_status[5]), //INPUT : Valid link
.mac_rx_clk_5(mac_rx_clk_5), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_5(mac_tx_clk_5), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_5(data_rx_sop_5), //OUTPUT : Start of Packet
.data_rx_eop_5(data_rx_eop_5), //OUTPUT : End of Packet
.data_rx_data_5(data_rx_data_5), //OUTPUT : Data from FIFO
.data_rx_error_5(data_rx_error_5), //OUTPUT : Receive packet error
.data_rx_valid_5(data_rx_valid_5), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_5(data_rx_ready_5), //OUTPUT : Data Receive Ready
.pkt_class_data_5(pkt_class_data_5), //OUTPUT : Frame Type Indication
.pkt_class_valid_5(pkt_class_valid_5), //OUTPUT : Frame Type Indication Valid
.data_tx_error_5(data_tx_error_5), //INPUT : Status
.data_tx_data_5(data_tx_data_5), //INPUT : Data from FIFO transmit
.data_tx_valid_5(data_tx_valid_5), //INPUT : Data FIFO transmit Empty
.data_tx_sop_5(data_tx_sop_5), //INPUT : Start of Packet
.data_tx_eop_5(data_tx_eop_5), //INPUT : End of Packet
.data_tx_ready_5(data_tx_ready_5), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_5(tx_ff_uflow_5), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_5(tx_crc_fwd_5), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_5(xoff_gen_5), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_5(xon_gen_5), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_5(magic_sleep_n_5), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_5(magic_wakeup_5), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 6
.rx_carrierdetected_6(pcs_rx_carrierdetected[6]),
.rx_rmfifodatadeleted_6(pcs_rx_rmfifodatadeleted[6]),
.rx_rmfifodatainserted_6(pcs_rx_rmfifodatainserted[6]),
.rx_clkout_6(rx_pcs_clk_c6), //INPUT : Receive Clock
.tx_clkout_6(tx_pcs_clk_c6), //INPUT : Transmit Clock
.rx_kchar_6(pcs_rx_kchar_6), //INPUT : Special Character Indication
.tx_kchar_6(tx_kchar_6), //OUTPUT : Special Character Indication
.rx_frame_6(pcs_rx_frame_6), //INPUT : Frame
.tx_frame_6(tx_frame_6), //OUTPUT : Frame
.sd_loopback_6(sd_loopback_6), //OUTPUT : SERDES Loopback Enable
.powerdown_6(pcs_pwrdn_out_sig[6]), //OUTPUT : Powerdown Enable
.led_col_6(led_col_6), //OUTPUT : Collision Indication
.led_an_6(led_an_6), //OUTPUT : Auto Negotiation Status
.led_char_err_6(led_char_err_gx[6]), //INPUT : Character error
.led_crs_6(led_crs_6), //OUTPUT : Carrier sense
.led_link_6(link_status[6]), //INPUT : Valid link
.mac_rx_clk_6(mac_rx_clk_6), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_6(mac_tx_clk_6), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_6(data_rx_sop_6), //OUTPUT : Start of Packet
.data_rx_eop_6(data_rx_eop_6), //OUTPUT : End of Packet
.data_rx_data_6(data_rx_data_6), //OUTPUT : Data from FIFO
.data_rx_error_6(data_rx_error_6), //OUTPUT : Receive packet error
.data_rx_valid_6(data_rx_valid_6), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_6(data_rx_ready_6), //OUTPUT : Data Receive Ready
.pkt_class_data_6(pkt_class_data_6), //OUTPUT : Frame Type Indication
.pkt_class_valid_6(pkt_class_valid_6), //OUTPUT : Frame Type Indication Valid
.data_tx_error_6(data_tx_error_6), //INPUT : Status
.data_tx_data_6(data_tx_data_6), //INPUT : Data from FIFO transmit
.data_tx_valid_6(data_tx_valid_6), //INPUT : Data FIFO transmit Empty
.data_tx_sop_6(data_tx_sop_6), //INPUT : Start of Packet
.data_tx_eop_6(data_tx_eop_6), //INPUT : End of Packet
.data_tx_ready_6(data_tx_ready_6), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_6(tx_ff_uflow_6), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_6(tx_crc_fwd_6), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_6(xoff_gen_6), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_6(xon_gen_6), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_6(magic_sleep_n_6), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_6(magic_wakeup_6), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 7
.rx_carrierdetected_7(pcs_rx_carrierdetected[7]),
.rx_rmfifodatadeleted_7(pcs_rx_rmfifodatadeleted[7]),
.rx_rmfifodatainserted_7(pcs_rx_rmfifodatainserted[7]),
.rx_clkout_7(rx_pcs_clk_c7), //INPUT : Receive Clock
.tx_clkout_7(tx_pcs_clk_c7), //INPUT : Transmit Clock
.rx_kchar_7(pcs_rx_kchar_7), //INPUT : Special Character Indication
.tx_kchar_7(tx_kchar_7), //OUTPUT : Special Character Indication
.rx_frame_7(pcs_rx_frame_7), //INPUT : Frame
.tx_frame_7(tx_frame_7), //OUTPUT : Frame
.sd_loopback_7(sd_loopback_7), //OUTPUT : SERDES Loopback Enable
.powerdown_7(pcs_pwrdn_out_sig[7]), //OUTPUT : Powerdown Enable
.led_col_7(led_col_7), //OUTPUT : Collision Indication
.led_an_7(led_an_7), //OUTPUT : Auto Negotiation Status
.led_char_err_7(led_char_err_gx[7]), //INPUT : Character error
.led_crs_7(led_crs_7), //OUTPUT : Carrier sense
.led_link_7(link_status[7]), //INPUT : Valid link
.mac_rx_clk_7(mac_rx_clk_7), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_7(mac_tx_clk_7), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_7(data_rx_sop_7), //OUTPUT : Start of Packet
.data_rx_eop_7(data_rx_eop_7), //OUTPUT : End of Packet
.data_rx_data_7(data_rx_data_7), //OUTPUT : Data from FIFO
.data_rx_error_7(data_rx_error_7), //OUTPUT : Receive packet error
.data_rx_valid_7(data_rx_valid_7), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_7(data_rx_ready_7), //OUTPUT : Data Receive Ready
.pkt_class_data_7(pkt_class_data_7), //OUTPUT : Frame Type Indication
.pkt_class_valid_7(pkt_class_valid_7), //OUTPUT : Frame Type Indication Valid
.data_tx_error_7(data_tx_error_7), //INPUT : Status
.data_tx_data_7(data_tx_data_7), //INPUT : Data from FIFO transmit
.data_tx_valid_7(data_tx_valid_7), //INPUT : Data FIFO transmit Empty
.data_tx_sop_7(data_tx_sop_7), //INPUT : Start of Packet
.data_tx_eop_7(data_tx_eop_7), //INPUT : End of Packet
.data_tx_ready_7(data_tx_ready_7), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_7(tx_ff_uflow_7), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_7(tx_crc_fwd_7), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_7(xoff_gen_7), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_7(xon_gen_7), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_7(magic_sleep_n_7), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_7(magic_wakeup_7), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 8
.rx_carrierdetected_8(pcs_rx_carrierdetected[8]),
.rx_rmfifodatadeleted_8(pcs_rx_rmfifodatadeleted[8]),
.rx_rmfifodatainserted_8(pcs_rx_rmfifodatainserted[8]),
.rx_clkout_8(rx_pcs_clk_c8), //INPUT : Receive Clock
.tx_clkout_8(tx_pcs_clk_c8), //INPUT : Transmit Clock
.rx_kchar_8(pcs_rx_kchar_8), //INPUT : Special Character Indication
.tx_kchar_8(tx_kchar_8), //OUTPUT : Special Character Indication
.rx_frame_8(pcs_rx_frame_8), //INPUT : Frame
.tx_frame_8(tx_frame_8), //OUTPUT : Frame
.sd_loopback_8(sd_loopback_8), //OUTPUT : SERDES Loopback Enable
.powerdown_8(pcs_pwrdn_out_sig[8]), //OUTPUT : Powerdown Enable
.led_col_8(led_col_8), //OUTPUT : Collision Indication
.led_an_8(led_an_8), //OUTPUT : Auto Negotiation Status
.led_char_err_8(led_char_err_gx[8]), //INPUT : Character error
.led_crs_8(led_crs_8), //OUTPUT : Carrier sense
.led_link_8(link_status[8]), //INPUT : Valid link
.mac_rx_clk_8(mac_rx_clk_8), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_8(mac_tx_clk_8), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_8(data_rx_sop_8), //OUTPUT : Start of Packet
.data_rx_eop_8(data_rx_eop_8), //OUTPUT : End of Packet
.data_rx_data_8(data_rx_data_8), //OUTPUT : Data from FIFO
.data_rx_error_8(data_rx_error_8), //OUTPUT : Receive packet error
.data_rx_valid_8(data_rx_valid_8), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_8(data_rx_ready_8), //OUTPUT : Data Receive Ready
.pkt_class_data_8(pkt_class_data_8), //OUTPUT : Frame Type Indication
.pkt_class_valid_8(pkt_class_valid_8), //OUTPUT : Frame Type Indication Valid
.data_tx_error_8(data_tx_error_8), //INPUT : Status
.data_tx_data_8(data_tx_data_8), //INPUT : Data from FIFO transmit
.data_tx_valid_8(data_tx_valid_8), //INPUT : Data FIFO transmit Empty
.data_tx_sop_8(data_tx_sop_8), //INPUT : Start of Packet
.data_tx_eop_8(data_tx_eop_8), //INPUT : End of Packet
.data_tx_ready_8(data_tx_ready_8), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_8(tx_ff_uflow_8), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_8(tx_crc_fwd_8), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_8(xoff_gen_8), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_8(xon_gen_8), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_8(magic_sleep_n_8), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_8(magic_wakeup_8), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 9
.rx_carrierdetected_9(pcs_rx_carrierdetected[9]),
.rx_rmfifodatadeleted_9(pcs_rx_rmfifodatadeleted[9]),
.rx_rmfifodatainserted_9(pcs_rx_rmfifodatainserted[9]),
.rx_clkout_9(rx_pcs_clk_c9), //INPUT : Receive Clock
.tx_clkout_9(tx_pcs_clk_c9), //INPUT : Transmit Clock
.rx_kchar_9(pcs_rx_kchar_9), //INPUT : Special Character Indication
.tx_kchar_9(tx_kchar_9), //OUTPUT : Special Character Indication
.rx_frame_9(pcs_rx_frame_9), //INPUT : Frame
.tx_frame_9(tx_frame_9), //OUTPUT : Frame
.sd_loopback_9(sd_loopback_9), //OUTPUT : SERDES Loopback Enable
.powerdown_9(pcs_pwrdn_out_sig[9]), //OUTPUT : Powerdown Enable
.led_col_9(led_col_9), //OUTPUT : Collision Indication
.led_an_9(led_an_9), //OUTPUT : Auto Negotiation Status
.led_char_err_9(led_char_err_gx[9]), //INPUT : Character error
.led_crs_9(led_crs_9), //OUTPUT : Carrier sense
.led_link_9(link_status[9]), //INPUT : Valid link
.mac_rx_clk_9(mac_rx_clk_9), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_9(mac_tx_clk_9), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_9(data_rx_sop_9), //OUTPUT : Start of Packet
.data_rx_eop_9(data_rx_eop_9), //OUTPUT : End of Packet
.data_rx_data_9(data_rx_data_9), //OUTPUT : Data from FIFO
.data_rx_error_9(data_rx_error_9), //OUTPUT : Receive packet error
.data_rx_valid_9(data_rx_valid_9), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_9(data_rx_ready_9), //OUTPUT : Data Receive Ready
.pkt_class_data_9(pkt_class_data_9), //OUTPUT : Frame Type Indication
.pkt_class_valid_9(pkt_class_valid_9), //OUTPUT : Frame Type Indication Valid
.data_tx_error_9(data_tx_error_9), //INPUT : Status
.data_tx_data_9(data_tx_data_9), //INPUT : Data from FIFO transmit
.data_tx_valid_9(data_tx_valid_9), //INPUT : Data FIFO transmit Empty
.data_tx_sop_9(data_tx_sop_9), //INPUT : Start of Packet
.data_tx_eop_9(data_tx_eop_9), //INPUT : End of Packet
.data_tx_ready_9(data_tx_ready_9), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_9(tx_ff_uflow_9), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_9(tx_crc_fwd_9), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_9(xoff_gen_9), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_9(xon_gen_9), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_9(magic_sleep_n_9), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_9(magic_wakeup_9), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 10
.rx_carrierdetected_10(pcs_rx_carrierdetected[10]),
.rx_rmfifodatadeleted_10(pcs_rx_rmfifodatadeleted[10]),
.rx_rmfifodatainserted_10(pcs_rx_rmfifodatainserted[10]),
.rx_clkout_10(rx_pcs_clk_c10), //INPUT : Receive Clock
.tx_clkout_10(tx_pcs_clk_c10), //INPUT : Transmit Clock
.rx_kchar_10(pcs_rx_kchar_10), //INPUT : Special Character Indication
.tx_kchar_10(tx_kchar_10), //OUTPUT : Special Character Indication
.rx_frame_10(pcs_rx_frame_10), //INPUT : Frame
.tx_frame_10(tx_frame_10), //OUTPUT : Frame
.sd_loopback_10(sd_loopback_10), //OUTPUT : SERDES Loopback Enable
.powerdown_10(pcs_pwrdn_out_sig[10]), //OUTPUT : Powerdown Enable
.led_col_10(led_col_10), //OUTPUT : Collision Indication
.led_an_10(led_an_10), //OUTPUT : Auto Negotiation Status
.led_char_err_10(led_char_err_gx[10]), //INPUT : Character error
.led_crs_10(led_crs_10), //OUTPUT : Carrier sense
.led_link_10(link_status[10]), //INPUT : Valid link
.mac_rx_clk_10(mac_rx_clk_10), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_10(mac_tx_clk_10), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_10(data_rx_sop_10), //OUTPUT : Start of Packet
.data_rx_eop_10(data_rx_eop_10), //OUTPUT : End of Packet
.data_rx_data_10(data_rx_data_10), //OUTPUT : Data from FIFO
.data_rx_error_10(data_rx_error_10), //OUTPUT : Receive packet error
.data_rx_valid_10(data_rx_valid_10), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_10(data_rx_ready_10), //OUTPUT : Data Receive Ready
.pkt_class_data_10(pkt_class_data_10), //OUTPUT : Frame Type Indication
.pkt_class_valid_10(pkt_class_valid_10), //OUTPUT : Frame Type Indication Valid
.data_tx_error_10(data_tx_error_10), //INPUT : Status
.data_tx_data_10(data_tx_data_10), //INPUT : Data from FIFO transmit
.data_tx_valid_10(data_tx_valid_10), //INPUT : Data FIFO transmit Empty
.data_tx_sop_10(data_tx_sop_10), //INPUT : Start of Packet
.data_tx_eop_10(data_tx_eop_10), //INPUT : End of Packet
.data_tx_ready_10(data_tx_ready_10), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_10(tx_ff_uflow_10), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_10(tx_crc_fwd_10), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_10(xoff_gen_10), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_10(xon_gen_10), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_10(magic_sleep_n_10), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_10(magic_wakeup_10), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 11
.rx_carrierdetected_11(pcs_rx_carrierdetected[11]),
.rx_rmfifodatadeleted_11(pcs_rx_rmfifodatadeleted[11]),
.rx_rmfifodatainserted_11(pcs_rx_rmfifodatainserted[11]),
.rx_clkout_11(rx_pcs_clk_c11), //INPUT : Receive Clock
.tx_clkout_11(tx_pcs_clk_c11), //INPUT : Transmit Clock
.rx_kchar_11(pcs_rx_kchar_11), //INPUT : Special Character Indication
.tx_kchar_11(tx_kchar_11), //OUTPUT : Special Character Indication
.rx_frame_11(pcs_rx_frame_11), //INPUT : Frame
.tx_frame_11(tx_frame_11), //OUTPUT : Frame
.sd_loopback_11(sd_loopback_11), //OUTPUT : SERDES Loopback Enable
.powerdown_11(pcs_pwrdn_out_sig[11]), //OUTPUT : Powerdown Enable
.led_col_11(led_col_11), //OUTPUT : Collision Indication
.led_an_11(led_an_11), //OUTPUT : Auto Negotiation Status
.led_char_err_11(led_char_err_gx[11]), //INPUT : Character error
.led_crs_11(led_crs_11), //OUTPUT : Carrier sense
.led_link_11(link_status[11]), //INPUT : Valid link
.mac_rx_clk_11(mac_rx_clk_11), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_11(mac_tx_clk_11), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_11(data_rx_sop_11), //OUTPUT : Start of Packet
.data_rx_eop_11(data_rx_eop_11), //OUTPUT : End of Packet
.data_rx_data_11(data_rx_data_11), //OUTPUT : Data from FIFO
.data_rx_error_11(data_rx_error_11), //OUTPUT : Receive packet error
.data_rx_valid_11(data_rx_valid_11), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_11(data_rx_ready_11), //OUTPUT : Data Receive Ready
.pkt_class_data_11(pkt_class_data_11), //OUTPUT : Frame Type Indication
.pkt_class_valid_11(pkt_class_valid_11), //OUTPUT : Frame Type Indication Valid
.data_tx_error_11(data_tx_error_11), //INPUT : Status
.data_tx_data_11(data_tx_data_11), //INPUT : Data from FIFO transmit
.data_tx_valid_11(data_tx_valid_11), //INPUT : Data FIFO transmit Empty
.data_tx_sop_11(data_tx_sop_11), //INPUT : Start of Packet
.data_tx_eop_11(data_tx_eop_11), //INPUT : End of Packet
.data_tx_ready_11(data_tx_ready_11), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_11(tx_ff_uflow_11), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_11(tx_crc_fwd_11), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_11(xoff_gen_11), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_11(xon_gen_11), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_11(magic_sleep_n_11), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_11(magic_wakeup_11), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 12
.rx_carrierdetected_12(pcs_rx_carrierdetected[12]),
.rx_rmfifodatadeleted_12(pcs_rx_rmfifodatadeleted[12]),
.rx_rmfifodatainserted_12(pcs_rx_rmfifodatainserted[12]),
.rx_clkout_12(rx_pcs_clk_c12), //INPUT : Receive Clock
.tx_clkout_12(tx_pcs_clk_c12), //INPUT : Transmit Clock
.rx_kchar_12(pcs_rx_kchar_12), //INPUT : Special Character Indication
.tx_kchar_12(tx_kchar_12), //OUTPUT : Special Character Indication
.rx_frame_12(pcs_rx_frame_12), //INPUT : Frame
.tx_frame_12(tx_frame_12), //OUTPUT : Frame
.sd_loopback_12(sd_loopback_12), //OUTPUT : SERDES Loopback Enable
.powerdown_12(pcs_pwrdn_out_sig[12]), //OUTPUT : Powerdown Enable
.led_col_12(led_col_12), //OUTPUT : Collision Indication
.led_an_12(led_an_12), //OUTPUT : Auto Negotiation Status
.led_char_err_12(led_char_err_gx[12]), //INPUT : Character error
.led_crs_12(led_crs_12), //OUTPUT : Carrier sense
.led_link_12(link_status[12]), //INPUT : Valid link
.mac_rx_clk_12(mac_rx_clk_12), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_12(mac_tx_clk_12), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_12(data_rx_sop_12), //OUTPUT : Start of Packet
.data_rx_eop_12(data_rx_eop_12), //OUTPUT : End of Packet
.data_rx_data_12(data_rx_data_12), //OUTPUT : Data from FIFO
.data_rx_error_12(data_rx_error_12), //OUTPUT : Receive packet error
.data_rx_valid_12(data_rx_valid_12), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_12(data_rx_ready_12), //OUTPUT : Data Receive Ready
.pkt_class_data_12(pkt_class_data_12), //OUTPUT : Frame Type Indication
.pkt_class_valid_12(pkt_class_valid_12), //OUTPUT : Frame Type Indication Valid
.data_tx_error_12(data_tx_error_12), //INPUT : Status
.data_tx_data_12(data_tx_data_12), //INPUT : Data from FIFO transmit
.data_tx_valid_12(data_tx_valid_12), //INPUT : Data FIFO transmit Empty
.data_tx_sop_12(data_tx_sop_12), //INPUT : Start of Packet
.data_tx_eop_12(data_tx_eop_12), //INPUT : End of Packet
.data_tx_ready_12(data_tx_ready_12), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_12(tx_ff_uflow_12), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_12(tx_crc_fwd_12), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_12(xoff_gen_12), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_12(xon_gen_12), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_12(magic_sleep_n_12), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_12(magic_wakeup_12), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 13
.rx_carrierdetected_13(pcs_rx_carrierdetected[13]),
.rx_rmfifodatadeleted_13(pcs_rx_rmfifodatadeleted[13]),
.rx_rmfifodatainserted_13(pcs_rx_rmfifodatainserted[13]),
.rx_clkout_13(rx_pcs_clk_c13), //INPUT : Receive Clock
.tx_clkout_13(tx_pcs_clk_c13), //INPUT : Transmit Clock
.rx_kchar_13(pcs_rx_kchar_13), //INPUT : Special Character Indication
.tx_kchar_13(tx_kchar_13), //OUTPUT : Special Character Indication
.rx_frame_13(pcs_rx_frame_13), //INPUT : Frame
.tx_frame_13(tx_frame_13), //OUTPUT : Frame
.sd_loopback_13(sd_loopback_13), //OUTPUT : SERDES Loopback Enable
.powerdown_13(pcs_pwrdn_out_sig[13]), //OUTPUT : Powerdown Enable
.led_col_13(led_col_13), //OUTPUT : Collision Indication
.led_an_13(led_an_13), //OUTPUT : Auto Negotiation Status
.led_char_err_13(led_char_err_gx[13]), //INPUT : Character error
.led_crs_13(led_crs_13), //OUTPUT : Carrier sense
.led_link_13(link_status[13]), //INPUT : Valid link
.mac_rx_clk_13(mac_rx_clk_13), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_13(mac_tx_clk_13), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_13(data_rx_sop_13), //OUTPUT : Start of Packet
.data_rx_eop_13(data_rx_eop_13), //OUTPUT : End of Packet
.data_rx_data_13(data_rx_data_13), //OUTPUT : Data from FIFO
.data_rx_error_13(data_rx_error_13), //OUTPUT : Receive packet error
.data_rx_valid_13(data_rx_valid_13), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_13(data_rx_ready_13), //OUTPUT : Data Receive Ready
.pkt_class_data_13(pkt_class_data_13), //OUTPUT : Frame Type Indication
.pkt_class_valid_13(pkt_class_valid_13), //OUTPUT : Frame Type Indication Valid
.data_tx_error_13(data_tx_error_13), //INPUT : Status
.data_tx_data_13(data_tx_data_13), //INPUT : Data from FIFO transmit
.data_tx_valid_13(data_tx_valid_13), //INPUT : Data FIFO transmit Empty
.data_tx_sop_13(data_tx_sop_13), //INPUT : Start of Packet
.data_tx_eop_13(data_tx_eop_13), //INPUT : End of Packet
.data_tx_ready_13(data_tx_ready_13), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_13(tx_ff_uflow_13), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_13(tx_crc_fwd_13), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_13(xoff_gen_13), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_13(xon_gen_13), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_13(magic_sleep_n_13), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_13(magic_wakeup_13), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 14
.rx_carrierdetected_14(pcs_rx_carrierdetected[14]),
.rx_rmfifodatadeleted_14(pcs_rx_rmfifodatadeleted[14]),
.rx_rmfifodatainserted_14(pcs_rx_rmfifodatainserted[14]),
.rx_clkout_14(rx_pcs_clk_c14), //INPUT : Receive Clock
.tx_clkout_14(tx_pcs_clk_c14), //INPUT : Transmit Clock
.rx_kchar_14(pcs_rx_kchar_14), //INPUT : Special Character Indication
.tx_kchar_14(tx_kchar_14), //OUTPUT : Special Character Indication
.rx_frame_14(pcs_rx_frame_14), //INPUT : Frame
.tx_frame_14(tx_frame_14), //OUTPUT : Frame
.sd_loopback_14(sd_loopback_14), //OUTPUT : SERDES Loopback Enable
.powerdown_14(pcs_pwrdn_out_sig[14]), //OUTPUT : Powerdown Enable
.led_col_14(led_col_14), //OUTPUT : Collision Indication
.led_an_14(led_an_14), //OUTPUT : Auto Negotiation Status
.led_char_err_14(led_char_err_gx[14]), //INPUT : Character error
.led_crs_14(led_crs_14), //OUTPUT : Carrier sense
.led_link_14(link_status[14]), //INPUT : Valid link
.mac_rx_clk_14(mac_rx_clk_14), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_14(mac_tx_clk_14), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_14(data_rx_sop_14), //OUTPUT : Start of Packet
.data_rx_eop_14(data_rx_eop_14), //OUTPUT : End of Packet
.data_rx_data_14(data_rx_data_14), //OUTPUT : Data from FIFO
.data_rx_error_14(data_rx_error_14), //OUTPUT : Receive packet error
.data_rx_valid_14(data_rx_valid_14), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_14(data_rx_ready_14), //OUTPUT : Data Receive Ready
.pkt_class_data_14(pkt_class_data_14), //OUTPUT : Frame Type Indication
.pkt_class_valid_14(pkt_class_valid_14), //OUTPUT : Frame Type Indication Valid
.data_tx_error_14(data_tx_error_14), //INPUT : Status
.data_tx_data_14(data_tx_data_14), //INPUT : Data from FIFO transmit
.data_tx_valid_14(data_tx_valid_14), //INPUT : Data FIFO transmit Empty
.data_tx_sop_14(data_tx_sop_14), //INPUT : Start of Packet
.data_tx_eop_14(data_tx_eop_14), //INPUT : End of Packet
.data_tx_ready_14(data_tx_ready_14), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_14(tx_ff_uflow_14), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_14(tx_crc_fwd_14), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_14(xoff_gen_14), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_14(xon_gen_14), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_14(magic_sleep_n_14), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_14(magic_wakeup_14), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 15
.rx_carrierdetected_15(pcs_rx_carrierdetected[15]),
.rx_rmfifodatadeleted_15(pcs_rx_rmfifodatadeleted[15]),
.rx_rmfifodatainserted_15(pcs_rx_rmfifodatainserted[15]),
.rx_clkout_15(rx_pcs_clk_c15), //INPUT : Receive Clock
.tx_clkout_15(tx_pcs_clk_c15), //INPUT : Transmit Clock
.rx_kchar_15(pcs_rx_kchar_15), //INPUT : Special Character Indication
.tx_kchar_15(tx_kchar_15), //OUTPUT : Special Character Indication
.rx_frame_15(pcs_rx_frame_15), //INPUT : Frame
.tx_frame_15(tx_frame_15), //OUTPUT : Frame
.sd_loopback_15(sd_loopback_15), //OUTPUT : SERDES Loopback Enable
.powerdown_15(pcs_pwrdn_out_sig[15]), //OUTPUT : Powerdown Enable
.led_col_15(led_col_15), //OUTPUT : Collision Indication
.led_an_15(led_an_15), //OUTPUT : Auto Negotiation Status
.led_char_err_15(led_char_err_gx[15]), //INPUT : Character error
.led_crs_15(led_crs_15), //OUTPUT : Carrier sense
.led_link_15(link_status[15]), //INPUT : Valid link
.mac_rx_clk_15(mac_rx_clk_15), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_15(mac_tx_clk_15), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_15(data_rx_sop_15), //OUTPUT : Start of Packet
.data_rx_eop_15(data_rx_eop_15), //OUTPUT : End of Packet
.data_rx_data_15(data_rx_data_15), //OUTPUT : Data from FIFO
.data_rx_error_15(data_rx_error_15), //OUTPUT : Receive packet error
.data_rx_valid_15(data_rx_valid_15), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_15(data_rx_ready_15), //OUTPUT : Data Receive Ready
.pkt_class_data_15(pkt_class_data_15), //OUTPUT : Frame Type Indication
.pkt_class_valid_15(pkt_class_valid_15), //OUTPUT : Frame Type Indication Valid
.data_tx_error_15(data_tx_error_15), //INPUT : Status
.data_tx_data_15(data_tx_data_15), //INPUT : Data from FIFO transmit
.data_tx_valid_15(data_tx_valid_15), //INPUT : Data FIFO transmit Empty
.data_tx_sop_15(data_tx_sop_15), //INPUT : Start of Packet
.data_tx_eop_15(data_tx_eop_15), //INPUT : End of Packet
.data_tx_ready_15(data_tx_ready_15), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_15(tx_ff_uflow_15), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_15(tx_crc_fwd_15), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_15(xoff_gen_15), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_15(xon_gen_15), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_15(magic_sleep_n_15), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_15(magic_wakeup_15), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 16
.rx_carrierdetected_16(pcs_rx_carrierdetected[16]),
.rx_rmfifodatadeleted_16(pcs_rx_rmfifodatadeleted[16]),
.rx_rmfifodatainserted_16(pcs_rx_rmfifodatainserted[16]),
.rx_clkout_16(rx_pcs_clk_c16), //INPUT : Receive Clock
.tx_clkout_16(tx_pcs_clk_c16), //INPUT : Transmit Clock
.rx_kchar_16(pcs_rx_kchar_16), //INPUT : Special Character Indication
.tx_kchar_16(tx_kchar_16), //OUTPUT : Special Character Indication
.rx_frame_16(pcs_rx_frame_16), //INPUT : Frame
.tx_frame_16(tx_frame_16), //OUTPUT : Frame
.sd_loopback_16(sd_loopback_16), //OUTPUT : SERDES Loopback Enable
.powerdown_16(pcs_pwrdn_out_sig[16]), //OUTPUT : Powerdown Enable
.led_col_16(led_col_16), //OUTPUT : Collision Indication
.led_an_16(led_an_16), //OUTPUT : Auto Negotiation Status
.led_char_err_16(led_char_err_gx[16]), //INPUT : Character error
.led_crs_16(led_crs_16), //OUTPUT : Carrier sense
.led_link_16(link_status[16]), //INPUT : Valid link
.mac_rx_clk_16(mac_rx_clk_16), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_16(mac_tx_clk_16), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_16(data_rx_sop_16), //OUTPUT : Start of Packet
.data_rx_eop_16(data_rx_eop_16), //OUTPUT : End of Packet
.data_rx_data_16(data_rx_data_16), //OUTPUT : Data from FIFO
.data_rx_error_16(data_rx_error_16), //OUTPUT : Receive packet error
.data_rx_valid_16(data_rx_valid_16), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_16(data_rx_ready_16), //OUTPUT : Data Receive Ready
.pkt_class_data_16(pkt_class_data_16), //OUTPUT : Frame Type Indication
.pkt_class_valid_16(pkt_class_valid_16), //OUTPUT : Frame Type Indication Valid
.data_tx_error_16(data_tx_error_16), //INPUT : Status
.data_tx_data_16(data_tx_data_16), //INPUT : Data from FIFO transmit
.data_tx_valid_16(data_tx_valid_16), //INPUT : Data FIFO transmit Empty
.data_tx_sop_16(data_tx_sop_16), //INPUT : Start of Packet
.data_tx_eop_16(data_tx_eop_16), //INPUT : End of Packet
.data_tx_ready_16(data_tx_ready_16), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_16(tx_ff_uflow_16), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_16(tx_crc_fwd_16), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_16(xoff_gen_16), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_16(xon_gen_16), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_16(magic_sleep_n_16), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_16(magic_wakeup_16), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 17
.rx_carrierdetected_17(pcs_rx_carrierdetected[17]),
.rx_rmfifodatadeleted_17(pcs_rx_rmfifodatadeleted[17]),
.rx_rmfifodatainserted_17(pcs_rx_rmfifodatainserted[17]),
.rx_clkout_17(rx_pcs_clk_c17), //INPUT : Receive Clock
.tx_clkout_17(tx_pcs_clk_c17), //INPUT : Transmit Clock
.rx_kchar_17(pcs_rx_kchar_17), //INPUT : Special Character Indication
.tx_kchar_17(tx_kchar_17), //OUTPUT : Special Character Indication
.rx_frame_17(pcs_rx_frame_17), //INPUT : Frame
.tx_frame_17(tx_frame_17), //OUTPUT : Frame
.sd_loopback_17(sd_loopback_17), //OUTPUT : SERDES Loopback Enable
.powerdown_17(pcs_pwrdn_out_sig[17]), //OUTPUT : Powerdown Enable
.led_col_17(led_col_17), //OUTPUT : Collision Indication
.led_an_17(led_an_17), //OUTPUT : Auto Negotiation Status
.led_char_err_17(led_char_err_gx[17]), //INPUT : Character error
.led_crs_17(led_crs_17), //OUTPUT : Carrier sense
.led_link_17(link_status[17]), //INPUT : Valid link
.mac_rx_clk_17(mac_rx_clk_17), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_17(mac_tx_clk_17), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_17(data_rx_sop_17), //OUTPUT : Start of Packet
.data_rx_eop_17(data_rx_eop_17), //OUTPUT : End of Packet
.data_rx_data_17(data_rx_data_17), //OUTPUT : Data from FIFO
.data_rx_error_17(data_rx_error_17), //OUTPUT : Receive packet error
.data_rx_valid_17(data_rx_valid_17), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_17(data_rx_ready_17), //OUTPUT : Data Receive Ready
.pkt_class_data_17(pkt_class_data_17), //OUTPUT : Frame Type Indication
.pkt_class_valid_17(pkt_class_valid_17), //OUTPUT : Frame Type Indication Valid
.data_tx_error_17(data_tx_error_17), //INPUT : Status
.data_tx_data_17(data_tx_data_17), //INPUT : Data from FIFO transmit
.data_tx_valid_17(data_tx_valid_17), //INPUT : Data FIFO transmit Empty
.data_tx_sop_17(data_tx_sop_17), //INPUT : Start of Packet
.data_tx_eop_17(data_tx_eop_17), //INPUT : End of Packet
.data_tx_ready_17(data_tx_ready_17), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_17(tx_ff_uflow_17), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_17(tx_crc_fwd_17), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_17(xoff_gen_17), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_17(xon_gen_17), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_17(magic_sleep_n_17), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_17(magic_wakeup_17), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 18
.rx_carrierdetected_18(pcs_rx_carrierdetected[18]),
.rx_rmfifodatadeleted_18(pcs_rx_rmfifodatadeleted[18]),
.rx_rmfifodatainserted_18(pcs_rx_rmfifodatainserted[18]),
.rx_clkout_18(rx_pcs_clk_c18), //INPUT : Receive Clock
.tx_clkout_18(tx_pcs_clk_c18), //INPUT : Transmit Clock
.rx_kchar_18(pcs_rx_kchar_18), //INPUT : Special Character Indication
.tx_kchar_18(tx_kchar_18), //OUTPUT : Special Character Indication
.rx_frame_18(pcs_rx_frame_18), //INPUT : Frame
.tx_frame_18(tx_frame_18), //OUTPUT : Frame
.sd_loopback_18(sd_loopback_18), //OUTPUT : SERDES Loopback Enable
.powerdown_18(pcs_pwrdn_out_sig[18]), //OUTPUT : Powerdown Enable
.led_col_18(led_col_18), //OUTPUT : Collision Indication
.led_an_18(led_an_18), //OUTPUT : Auto Negotiation Status
.led_char_err_18(led_char_err_gx[18]), //INPUT : Character error
.led_crs_18(led_crs_18), //OUTPUT : Carrier sense
.led_link_18(link_status[18]), //INPUT : Valid link
.mac_rx_clk_18(mac_rx_clk_18), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_18(mac_tx_clk_18), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_18(data_rx_sop_18), //OUTPUT : Start of Packet
.data_rx_eop_18(data_rx_eop_18), //OUTPUT : End of Packet
.data_rx_data_18(data_rx_data_18), //OUTPUT : Data from FIFO
.data_rx_error_18(data_rx_error_18), //OUTPUT : Receive packet error
.data_rx_valid_18(data_rx_valid_18), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_18(data_rx_ready_18), //OUTPUT : Data Receive Ready
.pkt_class_data_18(pkt_class_data_18), //OUTPUT : Frame Type Indication
.pkt_class_valid_18(pkt_class_valid_18), //OUTPUT : Frame Type Indication Valid
.data_tx_error_18(data_tx_error_18), //INPUT : Status
.data_tx_data_18(data_tx_data_18), //INPUT : Data from FIFO transmit
.data_tx_valid_18(data_tx_valid_18), //INPUT : Data FIFO transmit Empty
.data_tx_sop_18(data_tx_sop_18), //INPUT : Start of Packet
.data_tx_eop_18(data_tx_eop_18), //INPUT : End of Packet
.data_tx_ready_18(data_tx_ready_18), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_18(tx_ff_uflow_18), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_18(tx_crc_fwd_18), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_18(xoff_gen_18), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_18(xon_gen_18), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_18(magic_sleep_n_18), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_18(magic_wakeup_18), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 19
.rx_carrierdetected_19(pcs_rx_carrierdetected[19]),
.rx_rmfifodatadeleted_19(pcs_rx_rmfifodatadeleted[19]),
.rx_rmfifodatainserted_19(pcs_rx_rmfifodatainserted[19]),
.rx_clkout_19(rx_pcs_clk_c19), //INPUT : Receive Clock
.tx_clkout_19(tx_pcs_clk_c19), //INPUT : Transmit Clock
.rx_kchar_19(pcs_rx_kchar_19), //INPUT : Special Character Indication
.tx_kchar_19(tx_kchar_19), //OUTPUT : Special Character Indication
.rx_frame_19(pcs_rx_frame_19), //INPUT : Frame
.tx_frame_19(tx_frame_19), //OUTPUT : Frame
.sd_loopback_19(sd_loopback_19), //OUTPUT : SERDES Loopback Enable
.powerdown_19(pcs_pwrdn_out_sig[19]), //OUTPUT : Powerdown Enable
.led_col_19(led_col_19), //OUTPUT : Collision Indication
.led_an_19(led_an_19), //OUTPUT : Auto Negotiation Status
.led_char_err_19(led_char_err_gx[19]), //INPUT : Character error
.led_crs_19(led_crs_19), //OUTPUT : Carrier sense
.led_link_19(link_status[19]), //INPUT : Valid link
.mac_rx_clk_19(mac_rx_clk_19), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_19(mac_tx_clk_19), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_19(data_rx_sop_19), //OUTPUT : Start of Packet
.data_rx_eop_19(data_rx_eop_19), //OUTPUT : End of Packet
.data_rx_data_19(data_rx_data_19), //OUTPUT : Data from FIFO
.data_rx_error_19(data_rx_error_19), //OUTPUT : Receive packet error
.data_rx_valid_19(data_rx_valid_19), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_19(data_rx_ready_19), //OUTPUT : Data Receive Ready
.pkt_class_data_19(pkt_class_data_19), //OUTPUT : Frame Type Indication
.pkt_class_valid_19(pkt_class_valid_19), //OUTPUT : Frame Type Indication Valid
.data_tx_error_19(data_tx_error_19), //INPUT : Status
.data_tx_data_19(data_tx_data_19), //INPUT : Data from FIFO transmit
.data_tx_valid_19(data_tx_valid_19), //INPUT : Data FIFO transmit Empty
.data_tx_sop_19(data_tx_sop_19), //INPUT : Start of Packet
.data_tx_eop_19(data_tx_eop_19), //INPUT : End of Packet
.data_tx_ready_19(data_tx_ready_19), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_19(tx_ff_uflow_19), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_19(tx_crc_fwd_19), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_19(xoff_gen_19), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_19(xon_gen_19), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_19(magic_sleep_n_19), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_19(magic_wakeup_19), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 20
.rx_carrierdetected_20(pcs_rx_carrierdetected[20]),
.rx_rmfifodatadeleted_20(pcs_rx_rmfifodatadeleted[20]),
.rx_rmfifodatainserted_20(pcs_rx_rmfifodatainserted[20]),
.rx_clkout_20(rx_pcs_clk_c20), //INPUT : Receive Clock
.tx_clkout_20(tx_pcs_clk_c20), //INPUT : Transmit Clock
.rx_kchar_20(pcs_rx_kchar_20), //INPUT : Special Character Indication
.tx_kchar_20(tx_kchar_20), //OUTPUT : Special Character Indication
.rx_frame_20(pcs_rx_frame_20), //INPUT : Frame
.tx_frame_20(tx_frame_20), //OUTPUT : Frame
.sd_loopback_20(sd_loopback_20), //OUTPUT : SERDES Loopback Enable
.powerdown_20(pcs_pwrdn_out_sig[20]), //OUTPUT : Powerdown Enable
.led_col_20(led_col_20), //OUTPUT : Collision Indication
.led_an_20(led_an_20), //OUTPUT : Auto Negotiation Status
.led_char_err_20(led_char_err_gx[20]), //INPUT : Character error
.led_crs_20(led_crs_20), //OUTPUT : Carrier sense
.led_link_20(link_status[20]), //INPUT : Valid link
.mac_rx_clk_20(mac_rx_clk_20), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_20(mac_tx_clk_20), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_20(data_rx_sop_20), //OUTPUT : Start of Packet
.data_rx_eop_20(data_rx_eop_20), //OUTPUT : End of Packet
.data_rx_data_20(data_rx_data_20), //OUTPUT : Data from FIFO
.data_rx_error_20(data_rx_error_20), //OUTPUT : Receive packet error
.data_rx_valid_20(data_rx_valid_20), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_20(data_rx_ready_20), //OUTPUT : Data Receive Ready
.pkt_class_data_20(pkt_class_data_20), //OUTPUT : Frame Type Indication
.pkt_class_valid_20(pkt_class_valid_20), //OUTPUT : Frame Type Indication Valid
.data_tx_error_20(data_tx_error_20), //INPUT : Status
.data_tx_data_20(data_tx_data_20), //INPUT : Data from FIFO transmit
.data_tx_valid_20(data_tx_valid_20), //INPUT : Data FIFO transmit Empty
.data_tx_sop_20(data_tx_sop_20), //INPUT : Start of Packet
.data_tx_eop_20(data_tx_eop_20), //INPUT : End of Packet
.data_tx_ready_20(data_tx_ready_20), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_20(tx_ff_uflow_20), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_20(tx_crc_fwd_20), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_20(xoff_gen_20), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_20(xon_gen_20), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_20(magic_sleep_n_20), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_20(magic_wakeup_20), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 21
.rx_carrierdetected_21(pcs_rx_carrierdetected[21]),
.rx_rmfifodatadeleted_21(pcs_rx_rmfifodatadeleted[21]),
.rx_rmfifodatainserted_21(pcs_rx_rmfifodatainserted[21]),
.rx_clkout_21(rx_pcs_clk_c21), //INPUT : Receive Clock
.tx_clkout_21(tx_pcs_clk_c21), //INPUT : Transmit Clock
.rx_kchar_21(pcs_rx_kchar_21), //INPUT : Special Character Indication
.tx_kchar_21(tx_kchar_21), //OUTPUT : Special Character Indication
.rx_frame_21(pcs_rx_frame_21), //INPUT : Frame
.tx_frame_21(tx_frame_21), //OUTPUT : Frame
.sd_loopback_21(sd_loopback_21), //OUTPUT : SERDES Loopback Enable
.powerdown_21(pcs_pwrdn_out_sig[21]), //OUTPUT : Powerdown Enable
.led_col_21(led_col_21), //OUTPUT : Collision Indication
.led_an_21(led_an_21), //OUTPUT : Auto Negotiation Status
.led_char_err_21(led_char_err_gx[21]), //INPUT : Character error
.led_crs_21(led_crs_21), //OUTPUT : Carrier sense
.led_link_21(link_status[21]), //INPUT : Valid link
.mac_rx_clk_21(mac_rx_clk_21), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_21(mac_tx_clk_21), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_21(data_rx_sop_21), //OUTPUT : Start of Packet
.data_rx_eop_21(data_rx_eop_21), //OUTPUT : End of Packet
.data_rx_data_21(data_rx_data_21), //OUTPUT : Data from FIFO
.data_rx_error_21(data_rx_error_21), //OUTPUT : Receive packet error
.data_rx_valid_21(data_rx_valid_21), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_21(data_rx_ready_21), //OUTPUT : Data Receive Ready
.pkt_class_data_21(pkt_class_data_21), //OUTPUT : Frame Type Indication
.pkt_class_valid_21(pkt_class_valid_21), //OUTPUT : Frame Type Indication Valid
.data_tx_error_21(data_tx_error_21), //INPUT : Status
.data_tx_data_21(data_tx_data_21), //INPUT : Data from FIFO transmit
.data_tx_valid_21(data_tx_valid_21), //INPUT : Data FIFO transmit Empty
.data_tx_sop_21(data_tx_sop_21), //INPUT : Start of Packet
.data_tx_eop_21(data_tx_eop_21), //INPUT : End of Packet
.data_tx_ready_21(data_tx_ready_21), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_21(tx_ff_uflow_21), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_21(tx_crc_fwd_21), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_21(xoff_gen_21), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_21(xon_gen_21), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_21(magic_sleep_n_21), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_21(magic_wakeup_21), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 22
.rx_carrierdetected_22(pcs_rx_carrierdetected[22]),
.rx_rmfifodatadeleted_22(pcs_rx_rmfifodatadeleted[22]),
.rx_rmfifodatainserted_22(pcs_rx_rmfifodatainserted[22]),
.rx_clkout_22(rx_pcs_clk_c22), //INPUT : Receive Clock
.tx_clkout_22(tx_pcs_clk_c22), //INPUT : Transmit Clock
.rx_kchar_22(pcs_rx_kchar_22), //INPUT : Special Character Indication
.tx_kchar_22(tx_kchar_22), //OUTPUT : Special Character Indication
.rx_frame_22(pcs_rx_frame_22), //INPUT : Frame
.tx_frame_22(tx_frame_22), //OUTPUT : Frame
.sd_loopback_22(sd_loopback_22), //OUTPUT : SERDES Loopback Enable
.powerdown_22(pcs_pwrdn_out_sig[22]), //OUTPUT : Powerdown Enable
.led_col_22(led_col_22), //OUTPUT : Collision Indication
.led_an_22(led_an_22), //OUTPUT : Auto Negotiation Status
.led_char_err_22(led_char_err_gx[22]), //INPUT : Character error
.led_crs_22(led_crs_22), //OUTPUT : Carrier sense
.led_link_22(link_status[22]), //INPUT : Valid link
.mac_rx_clk_22(mac_rx_clk_22), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_22(mac_tx_clk_22), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_22(data_rx_sop_22), //OUTPUT : Start of Packet
.data_rx_eop_22(data_rx_eop_22), //OUTPUT : End of Packet
.data_rx_data_22(data_rx_data_22), //OUTPUT : Data from FIFO
.data_rx_error_22(data_rx_error_22), //OUTPUT : Receive packet error
.data_rx_valid_22(data_rx_valid_22), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_22(data_rx_ready_22), //OUTPUT : Data Receive Ready
.pkt_class_data_22(pkt_class_data_22), //OUTPUT : Frame Type Indication
.pkt_class_valid_22(pkt_class_valid_22), //OUTPUT : Frame Type Indication Valid
.data_tx_error_22(data_tx_error_22), //INPUT : Status
.data_tx_data_22(data_tx_data_22), //INPUT : Data from FIFO transmit
.data_tx_valid_22(data_tx_valid_22), //INPUT : Data FIFO transmit Empty
.data_tx_sop_22(data_tx_sop_22), //INPUT : Start of Packet
.data_tx_eop_22(data_tx_eop_22), //INPUT : End of Packet
.data_tx_ready_22(data_tx_ready_22), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_22(tx_ff_uflow_22), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_22(tx_crc_fwd_22), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_22(xoff_gen_22), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_22(xon_gen_22), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_22(magic_sleep_n_22), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_22(magic_wakeup_22), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 23
.rx_carrierdetected_23(pcs_rx_carrierdetected[23]),
.rx_rmfifodatadeleted_23(pcs_rx_rmfifodatadeleted[23]),
.rx_rmfifodatainserted_23(pcs_rx_rmfifodatainserted[23]),
.rx_clkout_23(rx_pcs_clk_c23), //INPUT : Receive Clock
.tx_clkout_23(tx_pcs_clk_c23), //INPUT : Transmit Clock
.rx_kchar_23(pcs_rx_kchar_23), //INPUT : Special Character Indication
.tx_kchar_23(tx_kchar_23), //OUTPUT : Special Character Indication
.rx_frame_23(pcs_rx_frame_23), //INPUT : Frame
.tx_frame_23(tx_frame_23), //OUTPUT : Frame
.sd_loopback_23(sd_loopback_23), //OUTPUT : SERDES Loopback Enable
.powerdown_23(pcs_pwrdn_out_sig[23]), //OUTPUT : Powerdown Enable
.led_col_23(led_col_23), //OUTPUT : Collision Indication
.led_an_23(led_an_23), //OUTPUT : Auto Negotiation Status
.led_char_err_23(led_char_err_gx[23]), //INPUT : Character error
.led_crs_23(led_crs_23), //OUTPUT : Carrier sense
.led_link_23(link_status[23]), //INPUT : Valid link
.mac_rx_clk_23(mac_rx_clk_23), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_23(mac_tx_clk_23), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_23(data_rx_sop_23), //OUTPUT : Start of Packet
.data_rx_eop_23(data_rx_eop_23), //OUTPUT : End of Packet
.data_rx_data_23(data_rx_data_23), //OUTPUT : Data from FIFO
.data_rx_error_23(data_rx_error_23), //OUTPUT : Receive packet error
.data_rx_valid_23(data_rx_valid_23), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_23(data_rx_ready_23), //OUTPUT : Data Receive Ready
.pkt_class_data_23(pkt_class_data_23), //OUTPUT : Frame Type Indication
.pkt_class_valid_23(pkt_class_valid_23), //OUTPUT : Frame Type Indication Valid
.data_tx_error_23(data_tx_error_23), //INPUT : Status
.data_tx_data_23(data_tx_data_23), //INPUT : Data from FIFO transmit
.data_tx_valid_23(data_tx_valid_23), //INPUT : Data FIFO transmit Empty
.data_tx_sop_23(data_tx_sop_23), //INPUT : Start of Packet
.data_tx_eop_23(data_tx_eop_23), //INPUT : End of Packet
.data_tx_ready_23(data_tx_ready_23), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_23(tx_ff_uflow_23), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_23(tx_crc_fwd_23), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_23(xoff_gen_23), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_23(xon_gen_23), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_23(magic_sleep_n_23), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_23(magic_wakeup_23)); //OUTPUT : MAC WAKE-UP INDICATION
defparam
U_MULTI_MAC_PCS.USE_SYNC_RESET = USE_SYNC_RESET,
U_MULTI_MAC_PCS.RESET_LEVEL = RESET_LEVEL,
U_MULTI_MAC_PCS.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
U_MULTI_MAC_PCS.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
U_MULTI_MAC_PCS.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
U_MULTI_MAC_PCS.ENA_HASH = ENA_HASH,
U_MULTI_MAC_PCS.STAT_CNT_ENA = STAT_CNT_ENA,
U_MULTI_MAC_PCS.CORE_VERSION = CORE_VERSION,
U_MULTI_MAC_PCS.CUST_VERSION = CUST_VERSION,
U_MULTI_MAC_PCS.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
U_MULTI_MAC_PCS.ENABLE_MDIO = ENABLE_MDIO,
U_MULTI_MAC_PCS.MDIO_CLK_DIV = MDIO_CLK_DIV,
U_MULTI_MAC_PCS.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
U_MULTI_MAC_PCS.ENABLE_PADDING = ENABLE_PADDING,
U_MULTI_MAC_PCS.ENABLE_LGTH_CHECK = ENABLE_LGTH_CHECK,
U_MULTI_MAC_PCS.GBIT_ONLY = GBIT_ONLY,
U_MULTI_MAC_PCS.MBIT_ONLY = MBIT_ONLY,
U_MULTI_MAC_PCS.REDUCED_CONTROL = REDUCED_CONTROL,
U_MULTI_MAC_PCS.CRC32DWIDTH = CRC32DWIDTH,
U_MULTI_MAC_PCS.CRC32GENDELAY = CRC32GENDELAY,
U_MULTI_MAC_PCS.CRC32CHECK16BIT = CRC32CHECK16BIT,
U_MULTI_MAC_PCS.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
U_MULTI_MAC_PCS.ENABLE_SHIFT16 = ENABLE_SHIFT16,
U_MULTI_MAC_PCS.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
U_MULTI_MAC_PCS.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
U_MULTI_MAC_PCS.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
U_MULTI_MAC_PCS.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN,
U_MULTI_MAC_PCS.PHY_IDENTIFIER = PHY_IDENTIFIER,
U_MULTI_MAC_PCS.DEV_VERSION = DEV_VERSION,
U_MULTI_MAC_PCS.ENABLE_SGMII = ENABLE_SGMII,
U_MULTI_MAC_PCS.MAX_CHANNELS = MAX_CHANNELS,
U_MULTI_MAC_PCS.CHANNEL_WIDTH = CHANNEL_WIDTH,
U_MULTI_MAC_PCS.ENABLE_RX_FIFO_STATUS = ENABLE_RX_FIFO_STATUS,
U_MULTI_MAC_PCS.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
U_MULTI_MAC_PCS.ENABLE_CLK_SHARING = ENABLE_CLK_SHARING,
U_MULTI_MAC_PCS.ENABLE_REG_SHARING = ENABLE_REG_SHARING;
// #######################################################################
// ############### CHANNEL 0 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 0)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch0_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c0_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_0
(
.clk(rx_pcs_clk_c0),
.reset(reset_rx_pcs_clk_c0_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_0),
.alt_sync(rx_syncstatus[0]),
.alt_disperr(rx_disp_err[0]),
.alt_ctrldetect(rx_kchar_0),
.alt_errdetect(rx_char_err_gx[0]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[0]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[0]),
.alt_runlengthviolation(rx_runlengthviolation[0]),
.alt_patterndetect(rx_patterndetect[0]),
.alt_runningdisp(rx_runningdisp[0]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_0),
.altpcs_sync(link_status[0]),
.altpcs_disperr(led_disp_err_0),
.altpcs_ctrldetect(pcs_rx_kchar_0),
.altpcs_errdetect(led_char_err_gx[0]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[0]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[0]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[0])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_0.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_0
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_0),
.phy_mgmt_read(phy_mgmt_read_0),
.phy_mgmt_readdata(phy_mgmt_readdata_0),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_0),
.phy_mgmt_write(phy_mgmt_write_0),
.phy_mgmt_writedata(phy_mgmt_writedata_0),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_0),
.rx_serial_data(rxp_0),
.rx_runningdisp(rx_runningdisp[0]),
.rx_disperr(rx_disp_err[0]),
.rx_errdetect(rx_char_err_gx[0]),
.rx_patterndetect(rx_patterndetect[0]),
.rx_syncstatus(rx_syncstatus[0]),
.tx_clkout(tx_pcs_clk_c0),
.rx_clkout(rx_pcs_clk_c0),
.tx_parallel_data(tx_frame_0),
.tx_datak(tx_kchar_0),
.rx_parallel_data(rx_frame_0),
.rx_datak(rx_kchar_0),
.rx_rlv(rx_runlengthviolation[0]),
.rx_recovclkout(rx_recovclkout_0),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[0]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[0]),
.reconfig_togxb(reconfig_togxb_0),
.reconfig_fromgxb(reconfig_fromgxb_0)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_0.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_0.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_0.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_0 = {92{1'b0}};
assign led_char_err_gx[0] = 1'b0;
assign link_status[0] = 1'b0;
assign led_disp_err_0 = 1'b0;
assign txp_0 = 1'b0;
assign rx_recovclkout_0= 1'b0;
assign phy_mgmt_readdata_0 = 32'b0;
assign phy_mgmt_waitrequest_0 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 1 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 1)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch1_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c1_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_1
(
.clk(rx_pcs_clk_c1),
.reset(reset_rx_pcs_clk_c1_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_1),
.alt_sync(rx_syncstatus[1]),
.alt_disperr(rx_disp_err[1]),
.alt_ctrldetect(rx_kchar_1),
.alt_errdetect(rx_char_err_gx[1]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[1]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[1]),
.alt_runlengthviolation(rx_runlengthviolation[1]),
.alt_patterndetect(rx_patterndetect[1]),
.alt_runningdisp(rx_runningdisp[1]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_1),
.altpcs_sync(link_status[1]),
.altpcs_disperr(led_disp_err_1),
.altpcs_ctrldetect(pcs_rx_kchar_1),
.altpcs_errdetect(led_char_err_gx[1]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[1]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[1]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[1])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_1.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_1
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_1),
.phy_mgmt_read(phy_mgmt_read_1),
.phy_mgmt_readdata(phy_mgmt_readdata_1),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_1),
.phy_mgmt_write(phy_mgmt_write_1),
.phy_mgmt_writedata(phy_mgmt_writedata_1),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_1),
.rx_serial_data(rxp_1),
.rx_runningdisp(rx_runningdisp[1]),
.rx_disperr(rx_disp_err[1]),
.rx_errdetect(rx_char_err_gx[1]),
.rx_patterndetect(rx_patterndetect[1]),
.rx_syncstatus(rx_syncstatus[1]),
.tx_clkout(tx_pcs_clk_c1),
.rx_clkout(rx_pcs_clk_c1),
.tx_parallel_data(tx_frame_1),
.tx_datak(tx_kchar_1),
.rx_parallel_data(rx_frame_1),
.rx_datak(rx_kchar_1),
.rx_rlv(rx_runlengthviolation[1]),
.rx_recovclkout(rx_recovclkout_1),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[1]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[1]),
.reconfig_togxb(reconfig_togxb_1),
.reconfig_fromgxb(reconfig_fromgxb_1)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_1.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_1.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_1.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_1 = {92{1'b0}};
assign led_char_err_gx[1] = 1'b0;
assign link_status[1] = 1'b0;
assign led_disp_err_1 = 1'b0;
assign txp_1 = 1'b0;
assign rx_recovclkout_1= 1'b0;
assign phy_mgmt_readdata_1 = 32'b0;
assign phy_mgmt_waitrequest_1 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 2 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 2)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch2_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c2_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_2
(
.clk(rx_pcs_clk_c2),
.reset(reset_rx_pcs_clk_c2_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_2),
.alt_sync(rx_syncstatus[2]),
.alt_disperr(rx_disp_err[2]),
.alt_ctrldetect(rx_kchar_2),
.alt_errdetect(rx_char_err_gx[2]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[2]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[2]),
.alt_runlengthviolation(rx_runlengthviolation[2]),
.alt_patterndetect(rx_patterndetect[2]),
.alt_runningdisp(rx_runningdisp[2]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_2),
.altpcs_sync(link_status[2]),
.altpcs_disperr(led_disp_err_2),
.altpcs_ctrldetect(pcs_rx_kchar_2),
.altpcs_errdetect(led_char_err_gx[2]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[2]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[2]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[2])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_2.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_2
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_2),
.phy_mgmt_read(phy_mgmt_read_2),
.phy_mgmt_readdata(phy_mgmt_readdata_2),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_2),
.phy_mgmt_write(phy_mgmt_write_2),
.phy_mgmt_writedata(phy_mgmt_writedata_2),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_2),
.rx_serial_data(rxp_2),
.rx_runningdisp(rx_runningdisp[2]),
.rx_disperr(rx_disp_err[2]),
.rx_errdetect(rx_char_err_gx[2]),
.rx_patterndetect(rx_patterndetect[2]),
.rx_syncstatus(rx_syncstatus[2]),
.tx_clkout(tx_pcs_clk_c2),
.rx_clkout(rx_pcs_clk_c2),
.tx_parallel_data(tx_frame_2),
.tx_datak(tx_kchar_2),
.rx_parallel_data(rx_frame_2),
.rx_datak(rx_kchar_2),
.rx_rlv(rx_runlengthviolation[2]),
.rx_recovclkout(rx_recovclkout_2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[2]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[2]),
.reconfig_togxb(reconfig_togxb_2),
.reconfig_fromgxb(reconfig_fromgxb_2)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_2.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_2.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_2.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_2 = {92{1'b0}};
assign led_char_err_gx[2] = 1'b0;
assign link_status[2] = 1'b0;
assign led_disp_err_2 = 1'b0;
assign txp_2 = 1'b0;
assign rx_recovclkout_2= 1'b0;
assign phy_mgmt_readdata_2 = 32'b0;
assign phy_mgmt_waitrequest_2 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 3 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 3)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch3_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c3_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_3
(
.clk(rx_pcs_clk_c3),
.reset(reset_rx_pcs_clk_c3_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_3),
.alt_sync(rx_syncstatus[3]),
.alt_disperr(rx_disp_err[3]),
.alt_ctrldetect(rx_kchar_3),
.alt_errdetect(rx_char_err_gx[3]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[3]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[3]),
.alt_runlengthviolation(rx_runlengthviolation[3]),
.alt_patterndetect(rx_patterndetect[3]),
.alt_runningdisp(rx_runningdisp[3]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_3),
.altpcs_sync(link_status[3]),
.altpcs_disperr(led_disp_err_3),
.altpcs_ctrldetect(pcs_rx_kchar_3),
.altpcs_errdetect(led_char_err_gx[3]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[3]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[3]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[3])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_3.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_3
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_3),
.phy_mgmt_read(phy_mgmt_read_3),
.phy_mgmt_readdata(phy_mgmt_readdata_3),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_3),
.phy_mgmt_write(phy_mgmt_write_3),
.phy_mgmt_writedata(phy_mgmt_writedata_3),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_3),
.rx_serial_data(rxp_3),
.rx_runningdisp(rx_runningdisp[3]),
.rx_disperr(rx_disp_err[3]),
.rx_errdetect(rx_char_err_gx[3]),
.rx_patterndetect(rx_patterndetect[3]),
.rx_syncstatus(rx_syncstatus[3]),
.tx_clkout(tx_pcs_clk_c3),
.rx_clkout(rx_pcs_clk_c3),
.tx_parallel_data(tx_frame_3),
.tx_datak(tx_kchar_3),
.rx_parallel_data(rx_frame_3),
.rx_datak(rx_kchar_3),
.rx_rlv(rx_runlengthviolation[3]),
.rx_recovclkout(rx_recovclkout_3),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[3]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[3]),
.reconfig_togxb(reconfig_togxb_3),
.reconfig_fromgxb(reconfig_fromgxb_3)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_3.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_3.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_3.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_3 = {92{1'b0}};
assign led_char_err_gx[3] = 1'b0;
assign link_status[3] = 1'b0;
assign led_disp_err_3 = 1'b0;
assign txp_3 = 1'b0;
assign rx_recovclkout_3= 1'b0;
assign phy_mgmt_readdata_3 = 32'b0;
assign phy_mgmt_waitrequest_3 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 4 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 4)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch4_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c4_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_4
(
.clk(rx_pcs_clk_c4),
.reset(reset_rx_pcs_clk_c4_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_4),
.alt_sync(rx_syncstatus[4]),
.alt_disperr(rx_disp_err[4]),
.alt_ctrldetect(rx_kchar_4),
.alt_errdetect(rx_char_err_gx[4]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[4]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[4]),
.alt_runlengthviolation(rx_runlengthviolation[4]),
.alt_patterndetect(rx_patterndetect[4]),
.alt_runningdisp(rx_runningdisp[4]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_4),
.altpcs_sync(link_status[4]),
.altpcs_disperr(led_disp_err_4),
.altpcs_ctrldetect(pcs_rx_kchar_4),
.altpcs_errdetect(led_char_err_gx[4]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[4]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[4]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[4])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_4.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_4
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_4),
.phy_mgmt_read(phy_mgmt_read_4),
.phy_mgmt_readdata(phy_mgmt_readdata_4),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_4),
.phy_mgmt_write(phy_mgmt_write_4),
.phy_mgmt_writedata(phy_mgmt_writedata_4),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_4),
.rx_serial_data(rxp_4),
.rx_runningdisp(rx_runningdisp[4]),
.rx_disperr(rx_disp_err[4]),
.rx_errdetect(rx_char_err_gx[4]),
.rx_patterndetect(rx_patterndetect[4]),
.rx_syncstatus(rx_syncstatus[4]),
.tx_clkout(tx_pcs_clk_c4),
.rx_clkout(rx_pcs_clk_c4),
.tx_parallel_data(tx_frame_4),
.tx_datak(tx_kchar_4),
.rx_parallel_data(rx_frame_4),
.rx_datak(rx_kchar_4),
.rx_rlv(rx_runlengthviolation[4]),
.rx_recovclkout(rx_recovclkout_4),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[4]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[4]),
.reconfig_togxb(reconfig_togxb_4),
.reconfig_fromgxb(reconfig_fromgxb_4)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_4.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_4.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_4.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_4 = {92{1'b0}};
assign led_char_err_gx[4] = 1'b0;
assign link_status[4] = 1'b0;
assign led_disp_err_4 = 1'b0;
assign txp_4 = 1'b0;
assign rx_recovclkout_4= 1'b0;
assign phy_mgmt_readdata_4 = 32'b0;
assign phy_mgmt_waitrequest_4 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 5 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 5)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch5_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c5_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_5
(
.clk(rx_pcs_clk_c5),
.reset(reset_rx_pcs_clk_c5_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_5),
.alt_sync(rx_syncstatus[5]),
.alt_disperr(rx_disp_err[5]),
.alt_ctrldetect(rx_kchar_5),
.alt_errdetect(rx_char_err_gx[5]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[5]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[5]),
.alt_runlengthviolation(rx_runlengthviolation[5]),
.alt_patterndetect(rx_patterndetect[5]),
.alt_runningdisp(rx_runningdisp[5]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_5),
.altpcs_sync(link_status[5]),
.altpcs_disperr(led_disp_err_5),
.altpcs_ctrldetect(pcs_rx_kchar_5),
.altpcs_errdetect(led_char_err_gx[5]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[5]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[5]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[5])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_5.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_5
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_5),
.phy_mgmt_read(phy_mgmt_read_5),
.phy_mgmt_readdata(phy_mgmt_readdata_5),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_5),
.phy_mgmt_write(phy_mgmt_write_5),
.phy_mgmt_writedata(phy_mgmt_writedata_5),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_5),
.rx_serial_data(rxp_5),
.rx_runningdisp(rx_runningdisp[5]),
.rx_disperr(rx_disp_err[5]),
.rx_errdetect(rx_char_err_gx[5]),
.rx_patterndetect(rx_patterndetect[5]),
.rx_syncstatus(rx_syncstatus[5]),
.tx_clkout(tx_pcs_clk_c5),
.rx_clkout(rx_pcs_clk_c5),
.tx_parallel_data(tx_frame_5),
.tx_datak(tx_kchar_5),
.rx_parallel_data(rx_frame_5),
.rx_datak(rx_kchar_5),
.rx_rlv(rx_runlengthviolation[5]),
.rx_recovclkout(rx_recovclkout_5),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[5]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[5]),
.reconfig_togxb(reconfig_togxb_5),
.reconfig_fromgxb(reconfig_fromgxb_5)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_5.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_5.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_5.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_5 = {92{1'b0}};
assign led_char_err_gx[5] = 1'b0;
assign link_status[5] = 1'b0;
assign led_disp_err_5 = 1'b0;
assign txp_5 = 1'b0;
assign rx_recovclkout_5= 1'b0;
assign phy_mgmt_readdata_5 = 32'b0;
assign phy_mgmt_waitrequest_5 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 6 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 6)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch6_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c6_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_6
(
.clk(rx_pcs_clk_c6),
.reset(reset_rx_pcs_clk_c6_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_6),
.alt_sync(rx_syncstatus[6]),
.alt_disperr(rx_disp_err[6]),
.alt_ctrldetect(rx_kchar_6),
.alt_errdetect(rx_char_err_gx[6]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[6]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[6]),
.alt_runlengthviolation(rx_runlengthviolation[6]),
.alt_patterndetect(rx_patterndetect[6]),
.alt_runningdisp(rx_runningdisp[6]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_6),
.altpcs_sync(link_status[6]),
.altpcs_disperr(led_disp_err_6),
.altpcs_ctrldetect(pcs_rx_kchar_6),
.altpcs_errdetect(led_char_err_gx[6]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[6]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[6]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[6])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_6.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_6
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_6),
.phy_mgmt_read(phy_mgmt_read_6),
.phy_mgmt_readdata(phy_mgmt_readdata_6),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_6),
.phy_mgmt_write(phy_mgmt_write_6),
.phy_mgmt_writedata(phy_mgmt_writedata_6),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_6),
.rx_serial_data(rxp_6),
.rx_runningdisp(rx_runningdisp[6]),
.rx_disperr(rx_disp_err[6]),
.rx_errdetect(rx_char_err_gx[6]),
.rx_patterndetect(rx_patterndetect[6]),
.rx_syncstatus(rx_syncstatus[6]),
.tx_clkout(tx_pcs_clk_c6),
.rx_clkout(rx_pcs_clk_c6),
.tx_parallel_data(tx_frame_6),
.tx_datak(tx_kchar_6),
.rx_parallel_data(rx_frame_6),
.rx_datak(rx_kchar_6),
.rx_rlv(rx_runlengthviolation[6]),
.rx_recovclkout(rx_recovclkout_6),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[6]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[6]),
.reconfig_togxb(reconfig_togxb_6),
.reconfig_fromgxb(reconfig_fromgxb_6)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_6.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_6.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_6.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_6 = {92{1'b0}};
assign led_char_err_gx[6] = 1'b0;
assign link_status[6] = 1'b0;
assign led_disp_err_6 = 1'b0;
assign txp_6 = 1'b0;
assign rx_recovclkout_6= 1'b0;
assign phy_mgmt_readdata_6 = 32'b0;
assign phy_mgmt_waitrequest_6 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 7 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 7)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch7_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c7_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_7
(
.clk(rx_pcs_clk_c7),
.reset(reset_rx_pcs_clk_c7_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_7),
.alt_sync(rx_syncstatus[7]),
.alt_disperr(rx_disp_err[7]),
.alt_ctrldetect(rx_kchar_7),
.alt_errdetect(rx_char_err_gx[7]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[7]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[7]),
.alt_runlengthviolation(rx_runlengthviolation[7]),
.alt_patterndetect(rx_patterndetect[7]),
.alt_runningdisp(rx_runningdisp[7]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_7),
.altpcs_sync(link_status[7]),
.altpcs_disperr(led_disp_err_7),
.altpcs_ctrldetect(pcs_rx_kchar_7),
.altpcs_errdetect(led_char_err_gx[7]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[7]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[7]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[7])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_7.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_7
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_7),
.phy_mgmt_read(phy_mgmt_read_7),
.phy_mgmt_readdata(phy_mgmt_readdata_7),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_7),
.phy_mgmt_write(phy_mgmt_write_7),
.phy_mgmt_writedata(phy_mgmt_writedata_7),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_7),
.rx_serial_data(rxp_7),
.rx_runningdisp(rx_runningdisp[7]),
.rx_disperr(rx_disp_err[7]),
.rx_errdetect(rx_char_err_gx[7]),
.rx_patterndetect(rx_patterndetect[7]),
.rx_syncstatus(rx_syncstatus[7]),
.tx_clkout(tx_pcs_clk_c7),
.rx_clkout(rx_pcs_clk_c7),
.tx_parallel_data(tx_frame_7),
.tx_datak(tx_kchar_7),
.rx_parallel_data(rx_frame_7),
.rx_datak(rx_kchar_7),
.rx_rlv(rx_runlengthviolation[7]),
.rx_recovclkout(rx_recovclkout_7),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[7]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[7]),
.reconfig_togxb(reconfig_togxb_7),
.reconfig_fromgxb(reconfig_fromgxb_7)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_7.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_7.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_7.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_7 = {92{1'b0}};
assign led_char_err_gx[7] = 1'b0;
assign link_status[7] = 1'b0;
assign led_disp_err_7 = 1'b0;
assign txp_7 = 1'b0;
assign rx_recovclkout_7= 1'b0;
assign phy_mgmt_readdata_7 = 32'b0;
assign phy_mgmt_waitrequest_7 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 8 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 8)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch8_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c8_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_8
(
.clk(rx_pcs_clk_c8),
.reset(reset_rx_pcs_clk_c8_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_8),
.alt_sync(rx_syncstatus[8]),
.alt_disperr(rx_disp_err[8]),
.alt_ctrldetect(rx_kchar_8),
.alt_errdetect(rx_char_err_gx[8]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[8]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[8]),
.alt_runlengthviolation(rx_runlengthviolation[8]),
.alt_patterndetect(rx_patterndetect[8]),
.alt_runningdisp(rx_runningdisp[8]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_8),
.altpcs_sync(link_status[8]),
.altpcs_disperr(led_disp_err_8),
.altpcs_ctrldetect(pcs_rx_kchar_8),
.altpcs_errdetect(led_char_err_gx[8]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[8]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[8]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[8])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_8.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_8
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_8),
.phy_mgmt_read(phy_mgmt_read_8),
.phy_mgmt_readdata(phy_mgmt_readdata_8),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_8),
.phy_mgmt_write(phy_mgmt_write_8),
.phy_mgmt_writedata(phy_mgmt_writedata_8),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_8),
.rx_serial_data(rxp_8),
.rx_runningdisp(rx_runningdisp[8]),
.rx_disperr(rx_disp_err[8]),
.rx_errdetect(rx_char_err_gx[8]),
.rx_patterndetect(rx_patterndetect[8]),
.rx_syncstatus(rx_syncstatus[8]),
.tx_clkout(tx_pcs_clk_c8),
.rx_clkout(rx_pcs_clk_c8),
.tx_parallel_data(tx_frame_8),
.tx_datak(tx_kchar_8),
.rx_parallel_data(rx_frame_8),
.rx_datak(rx_kchar_8),
.rx_rlv(rx_runlengthviolation[8]),
.rx_recovclkout(rx_recovclkout_8),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[8]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[8]),
.reconfig_togxb(reconfig_togxb_8),
.reconfig_fromgxb(reconfig_fromgxb_8)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_8.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_8.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_8.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_8 = {92{1'b0}};
assign led_char_err_gx[8] = 1'b0;
assign link_status[8] = 1'b0;
assign led_disp_err_8 = 1'b0;
assign txp_8 = 1'b0;
assign rx_recovclkout_8= 1'b0;
assign phy_mgmt_readdata_8 = 32'b0;
assign phy_mgmt_waitrequest_8 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 9 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 9)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch9_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c9_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_9
(
.clk(rx_pcs_clk_c9),
.reset(reset_rx_pcs_clk_c9_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_9),
.alt_sync(rx_syncstatus[9]),
.alt_disperr(rx_disp_err[9]),
.alt_ctrldetect(rx_kchar_9),
.alt_errdetect(rx_char_err_gx[9]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[9]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[9]),
.alt_runlengthviolation(rx_runlengthviolation[9]),
.alt_patterndetect(rx_patterndetect[9]),
.alt_runningdisp(rx_runningdisp[9]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_9),
.altpcs_sync(link_status[9]),
.altpcs_disperr(led_disp_err_9),
.altpcs_ctrldetect(pcs_rx_kchar_9),
.altpcs_errdetect(led_char_err_gx[9]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[9]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[9]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[9])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_9.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_9
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_9),
.phy_mgmt_read(phy_mgmt_read_9),
.phy_mgmt_readdata(phy_mgmt_readdata_9),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_9),
.phy_mgmt_write(phy_mgmt_write_9),
.phy_mgmt_writedata(phy_mgmt_writedata_9),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_9),
.rx_serial_data(rxp_9),
.rx_runningdisp(rx_runningdisp[9]),
.rx_disperr(rx_disp_err[9]),
.rx_errdetect(rx_char_err_gx[9]),
.rx_patterndetect(rx_patterndetect[9]),
.rx_syncstatus(rx_syncstatus[9]),
.tx_clkout(tx_pcs_clk_c9),
.rx_clkout(rx_pcs_clk_c9),
.tx_parallel_data(tx_frame_9),
.tx_datak(tx_kchar_9),
.rx_parallel_data(rx_frame_9),
.rx_datak(rx_kchar_9),
.rx_rlv(rx_runlengthviolation[9]),
.rx_recovclkout(rx_recovclkout_9),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[9]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[9]),
.reconfig_togxb(reconfig_togxb_9),
.reconfig_fromgxb(reconfig_fromgxb_9)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_9.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_9.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_9.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_9 = {92{1'b0}};
assign led_char_err_gx[9] = 1'b0;
assign link_status[9] = 1'b0;
assign led_disp_err_9 = 1'b0;
assign txp_9 = 1'b0;
assign rx_recovclkout_9= 1'b0;
assign phy_mgmt_readdata_9 = 32'b0;
assign phy_mgmt_waitrequest_9 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 10 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 10)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch10_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c10_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_10
(
.clk(rx_pcs_clk_c10),
.reset(reset_rx_pcs_clk_c10_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_10),
.alt_sync(rx_syncstatus[10]),
.alt_disperr(rx_disp_err[10]),
.alt_ctrldetect(rx_kchar_10),
.alt_errdetect(rx_char_err_gx[10]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[10]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[10]),
.alt_runlengthviolation(rx_runlengthviolation[10]),
.alt_patterndetect(rx_patterndetect[10]),
.alt_runningdisp(rx_runningdisp[10]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_10),
.altpcs_sync(link_status[10]),
.altpcs_disperr(led_disp_err_10),
.altpcs_ctrldetect(pcs_rx_kchar_10),
.altpcs_errdetect(led_char_err_gx[10]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[10]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[10]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[10])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_10.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_10
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_10),
.phy_mgmt_read(phy_mgmt_read_10),
.phy_mgmt_readdata(phy_mgmt_readdata_10),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_10),
.phy_mgmt_write(phy_mgmt_write_10),
.phy_mgmt_writedata(phy_mgmt_writedata_10),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_10),
.rx_serial_data(rxp_10),
.rx_runningdisp(rx_runningdisp[10]),
.rx_disperr(rx_disp_err[10]),
.rx_errdetect(rx_char_err_gx[10]),
.rx_patterndetect(rx_patterndetect[10]),
.rx_syncstatus(rx_syncstatus[10]),
.tx_clkout(tx_pcs_clk_c10),
.rx_clkout(rx_pcs_clk_c10),
.tx_parallel_data(tx_frame_10),
.tx_datak(tx_kchar_10),
.rx_parallel_data(rx_frame_10),
.rx_datak(rx_kchar_10),
.rx_rlv(rx_runlengthviolation[10]),
.rx_recovclkout(rx_recovclkout_10),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[10]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[10]),
.reconfig_togxb(reconfig_togxb_10),
.reconfig_fromgxb(reconfig_fromgxb_10)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_10.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_10.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_10.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_10 = {92{1'b0}};
assign led_char_err_gx[10] = 1'b0;
assign link_status[10] = 1'b0;
assign led_disp_err_10 = 1'b0;
assign txp_10 = 1'b0;
assign rx_recovclkout_10= 1'b0;
assign phy_mgmt_readdata_10 = 32'b0;
assign phy_mgmt_waitrequest_10 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 11 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 11)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch11_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c11_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_11
(
.clk(rx_pcs_clk_c11),
.reset(reset_rx_pcs_clk_c11_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_11),
.alt_sync(rx_syncstatus[11]),
.alt_disperr(rx_disp_err[11]),
.alt_ctrldetect(rx_kchar_11),
.alt_errdetect(rx_char_err_gx[11]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[11]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[11]),
.alt_runlengthviolation(rx_runlengthviolation[11]),
.alt_patterndetect(rx_patterndetect[11]),
.alt_runningdisp(rx_runningdisp[11]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_11),
.altpcs_sync(link_status[11]),
.altpcs_disperr(led_disp_err_11),
.altpcs_ctrldetect(pcs_rx_kchar_11),
.altpcs_errdetect(led_char_err_gx[11]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[11]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[11]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[11])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_11.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_11
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_11),
.phy_mgmt_read(phy_mgmt_read_11),
.phy_mgmt_readdata(phy_mgmt_readdata_11),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_11),
.phy_mgmt_write(phy_mgmt_write_11),
.phy_mgmt_writedata(phy_mgmt_writedata_11),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_11),
.rx_serial_data(rxp_11),
.rx_runningdisp(rx_runningdisp[11]),
.rx_disperr(rx_disp_err[11]),
.rx_errdetect(rx_char_err_gx[11]),
.rx_patterndetect(rx_patterndetect[11]),
.rx_syncstatus(rx_syncstatus[11]),
.tx_clkout(tx_pcs_clk_c11),
.rx_clkout(rx_pcs_clk_c11),
.tx_parallel_data(tx_frame_11),
.tx_datak(tx_kchar_11),
.rx_parallel_data(rx_frame_11),
.rx_datak(rx_kchar_11),
.rx_rlv(rx_runlengthviolation[11]),
.rx_recovclkout(rx_recovclkout_11),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[11]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[11]),
.reconfig_togxb(reconfig_togxb_11),
.reconfig_fromgxb(reconfig_fromgxb_11)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_11.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_11.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_11.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_11 = {92{1'b0}};
assign led_char_err_gx[11] = 1'b0;
assign link_status[11] = 1'b0;
assign led_disp_err_11 = 1'b0;
assign txp_11 = 1'b0;
assign rx_recovclkout_11= 1'b0;
assign phy_mgmt_readdata_11 = 32'b0;
assign phy_mgmt_waitrequest_11 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 12 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 12)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch12_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c12_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_12
(
.clk(rx_pcs_clk_c12),
.reset(reset_rx_pcs_clk_c12_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_12),
.alt_sync(rx_syncstatus[12]),
.alt_disperr(rx_disp_err[12]),
.alt_ctrldetect(rx_kchar_12),
.alt_errdetect(rx_char_err_gx[12]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[12]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[12]),
.alt_runlengthviolation(rx_runlengthviolation[12]),
.alt_patterndetect(rx_patterndetect[12]),
.alt_runningdisp(rx_runningdisp[12]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_12),
.altpcs_sync(link_status[12]),
.altpcs_disperr(led_disp_err_12),
.altpcs_ctrldetect(pcs_rx_kchar_12),
.altpcs_errdetect(led_char_err_gx[12]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[12]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[12]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[12])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_12.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_12
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_12),
.phy_mgmt_read(phy_mgmt_read_12),
.phy_mgmt_readdata(phy_mgmt_readdata_12),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_12),
.phy_mgmt_write(phy_mgmt_write_12),
.phy_mgmt_writedata(phy_mgmt_writedata_12),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_12),
.rx_serial_data(rxp_12),
.rx_runningdisp(rx_runningdisp[12]),
.rx_disperr(rx_disp_err[12]),
.rx_errdetect(rx_char_err_gx[12]),
.rx_patterndetect(rx_patterndetect[12]),
.rx_syncstatus(rx_syncstatus[12]),
.tx_clkout(tx_pcs_clk_c12),
.rx_clkout(rx_pcs_clk_c12),
.tx_parallel_data(tx_frame_12),
.tx_datak(tx_kchar_12),
.rx_parallel_data(rx_frame_12),
.rx_datak(rx_kchar_12),
.rx_rlv(rx_runlengthviolation[12]),
.rx_recovclkout(rx_recovclkout_12),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[12]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[12]),
.reconfig_togxb(reconfig_togxb_12),
.reconfig_fromgxb(reconfig_fromgxb_12)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_12.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_12.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_12.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_12 = {92{1'b0}};
assign led_char_err_gx[12] = 1'b0;
assign link_status[12] = 1'b0;
assign led_disp_err_12 = 1'b0;
assign txp_12 = 1'b0;
assign rx_recovclkout_12= 1'b0;
assign phy_mgmt_readdata_12 = 32'b0;
assign phy_mgmt_waitrequest_12 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 13 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 13)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch13_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c13_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_13
(
.clk(rx_pcs_clk_c13),
.reset(reset_rx_pcs_clk_c13_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_13),
.alt_sync(rx_syncstatus[13]),
.alt_disperr(rx_disp_err[13]),
.alt_ctrldetect(rx_kchar_13),
.alt_errdetect(rx_char_err_gx[13]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[13]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[13]),
.alt_runlengthviolation(rx_runlengthviolation[13]),
.alt_patterndetect(rx_patterndetect[13]),
.alt_runningdisp(rx_runningdisp[13]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_13),
.altpcs_sync(link_status[13]),
.altpcs_disperr(led_disp_err_13),
.altpcs_ctrldetect(pcs_rx_kchar_13),
.altpcs_errdetect(led_char_err_gx[13]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[13]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[13]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[13])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_13.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_13
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_13),
.phy_mgmt_read(phy_mgmt_read_13),
.phy_mgmt_readdata(phy_mgmt_readdata_13),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_13),
.phy_mgmt_write(phy_mgmt_write_13),
.phy_mgmt_writedata(phy_mgmt_writedata_13),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_13),
.rx_serial_data(rxp_13),
.rx_runningdisp(rx_runningdisp[13]),
.rx_disperr(rx_disp_err[13]),
.rx_errdetect(rx_char_err_gx[13]),
.rx_patterndetect(rx_patterndetect[13]),
.rx_syncstatus(rx_syncstatus[13]),
.tx_clkout(tx_pcs_clk_c13),
.rx_clkout(rx_pcs_clk_c13),
.tx_parallel_data(tx_frame_13),
.tx_datak(tx_kchar_13),
.rx_parallel_data(rx_frame_13),
.rx_datak(rx_kchar_13),
.rx_rlv(rx_runlengthviolation[13]),
.rx_recovclkout(rx_recovclkout_13),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[13]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[13]),
.reconfig_togxb(reconfig_togxb_13),
.reconfig_fromgxb(reconfig_fromgxb_13)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_13.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_13.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_13.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_13 = {92{1'b0}};
assign led_char_err_gx[13] = 1'b0;
assign link_status[13] = 1'b0;
assign led_disp_err_13 = 1'b0;
assign txp_13 = 1'b0;
assign rx_recovclkout_13= 1'b0;
assign phy_mgmt_readdata_13 = 32'b0;
assign phy_mgmt_waitrequest_13 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 14 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 14)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch14_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c14_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_14
(
.clk(rx_pcs_clk_c14),
.reset(reset_rx_pcs_clk_c14_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_14),
.alt_sync(rx_syncstatus[14]),
.alt_disperr(rx_disp_err[14]),
.alt_ctrldetect(rx_kchar_14),
.alt_errdetect(rx_char_err_gx[14]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[14]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[14]),
.alt_runlengthviolation(rx_runlengthviolation[14]),
.alt_patterndetect(rx_patterndetect[14]),
.alt_runningdisp(rx_runningdisp[14]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_14),
.altpcs_sync(link_status[14]),
.altpcs_disperr(led_disp_err_14),
.altpcs_ctrldetect(pcs_rx_kchar_14),
.altpcs_errdetect(led_char_err_gx[14]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[14]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[14]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[14])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_14.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_14
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_14),
.phy_mgmt_read(phy_mgmt_read_14),
.phy_mgmt_readdata(phy_mgmt_readdata_14),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_14),
.phy_mgmt_write(phy_mgmt_write_14),
.phy_mgmt_writedata(phy_mgmt_writedata_14),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_14),
.rx_serial_data(rxp_14),
.rx_runningdisp(rx_runningdisp[14]),
.rx_disperr(rx_disp_err[14]),
.rx_errdetect(rx_char_err_gx[14]),
.rx_patterndetect(rx_patterndetect[14]),
.rx_syncstatus(rx_syncstatus[14]),
.tx_clkout(tx_pcs_clk_c14),
.rx_clkout(rx_pcs_clk_c14),
.tx_parallel_data(tx_frame_14),
.tx_datak(tx_kchar_14),
.rx_parallel_data(rx_frame_14),
.rx_datak(rx_kchar_14),
.rx_rlv(rx_runlengthviolation[14]),
.rx_recovclkout(rx_recovclkout_14),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[14]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[14]),
.reconfig_togxb(reconfig_togxb_14),
.reconfig_fromgxb(reconfig_fromgxb_14)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_14.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_14.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_14.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_14 = {92{1'b0}};
assign led_char_err_gx[14] = 1'b0;
assign link_status[14] = 1'b0;
assign led_disp_err_14 = 1'b0;
assign txp_14 = 1'b0;
assign rx_recovclkout_14= 1'b0;
assign phy_mgmt_readdata_14 = 32'b0;
assign phy_mgmt_waitrequest_14 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 15 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 15)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch15_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c15_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_15
(
.clk(rx_pcs_clk_c15),
.reset(reset_rx_pcs_clk_c15_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_15),
.alt_sync(rx_syncstatus[15]),
.alt_disperr(rx_disp_err[15]),
.alt_ctrldetect(rx_kchar_15),
.alt_errdetect(rx_char_err_gx[15]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[15]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[15]),
.alt_runlengthviolation(rx_runlengthviolation[15]),
.alt_patterndetect(rx_patterndetect[15]),
.alt_runningdisp(rx_runningdisp[15]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_15),
.altpcs_sync(link_status[15]),
.altpcs_disperr(led_disp_err_15),
.altpcs_ctrldetect(pcs_rx_kchar_15),
.altpcs_errdetect(led_char_err_gx[15]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[15]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[15]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[15])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_15.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_15
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_15),
.phy_mgmt_read(phy_mgmt_read_15),
.phy_mgmt_readdata(phy_mgmt_readdata_15),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_15),
.phy_mgmt_write(phy_mgmt_write_15),
.phy_mgmt_writedata(phy_mgmt_writedata_15),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_15),
.rx_serial_data(rxp_15),
.rx_runningdisp(rx_runningdisp[15]),
.rx_disperr(rx_disp_err[15]),
.rx_errdetect(rx_char_err_gx[15]),
.rx_patterndetect(rx_patterndetect[15]),
.rx_syncstatus(rx_syncstatus[15]),
.tx_clkout(tx_pcs_clk_c15),
.rx_clkout(rx_pcs_clk_c15),
.tx_parallel_data(tx_frame_15),
.tx_datak(tx_kchar_15),
.rx_parallel_data(rx_frame_15),
.rx_datak(rx_kchar_15),
.rx_rlv(rx_runlengthviolation[15]),
.rx_recovclkout(rx_recovclkout_15),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[15]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[15]),
.reconfig_togxb(reconfig_togxb_15),
.reconfig_fromgxb(reconfig_fromgxb_15)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_15.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_15.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_15.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_15 = {92{1'b0}};
assign led_char_err_gx[15] = 1'b0;
assign link_status[15] = 1'b0;
assign led_disp_err_15 = 1'b0;
assign txp_15 = 1'b0;
assign rx_recovclkout_15= 1'b0;
assign phy_mgmt_readdata_15 = 32'b0;
assign phy_mgmt_waitrequest_15 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 16 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 16)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch16_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c16_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_16
(
.clk(rx_pcs_clk_c16),
.reset(reset_rx_pcs_clk_c16_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_16),
.alt_sync(rx_syncstatus[16]),
.alt_disperr(rx_disp_err[16]),
.alt_ctrldetect(rx_kchar_16),
.alt_errdetect(rx_char_err_gx[16]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[16]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[16]),
.alt_runlengthviolation(rx_runlengthviolation[16]),
.alt_patterndetect(rx_patterndetect[16]),
.alt_runningdisp(rx_runningdisp[16]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_16),
.altpcs_sync(link_status[16]),
.altpcs_disperr(led_disp_err_16),
.altpcs_ctrldetect(pcs_rx_kchar_16),
.altpcs_errdetect(led_char_err_gx[16]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[16]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[16]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[16])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_16.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_16
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_16),
.phy_mgmt_read(phy_mgmt_read_16),
.phy_mgmt_readdata(phy_mgmt_readdata_16),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_16),
.phy_mgmt_write(phy_mgmt_write_16),
.phy_mgmt_writedata(phy_mgmt_writedata_16),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_16),
.rx_serial_data(rxp_16),
.rx_runningdisp(rx_runningdisp[16]),
.rx_disperr(rx_disp_err[16]),
.rx_errdetect(rx_char_err_gx[16]),
.rx_patterndetect(rx_patterndetect[16]),
.rx_syncstatus(rx_syncstatus[16]),
.tx_clkout(tx_pcs_clk_c16),
.rx_clkout(rx_pcs_clk_c16),
.tx_parallel_data(tx_frame_16),
.tx_datak(tx_kchar_16),
.rx_parallel_data(rx_frame_16),
.rx_datak(rx_kchar_16),
.rx_rlv(rx_runlengthviolation[16]),
.rx_recovclkout(rx_recovclkout_16),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[16]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[16]),
.reconfig_togxb(reconfig_togxb_16),
.reconfig_fromgxb(reconfig_fromgxb_16)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_16.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_16.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_16.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_16 = {92{1'b0}};
assign led_char_err_gx[16] = 1'b0;
assign link_status[16] = 1'b0;
assign led_disp_err_16 = 1'b0;
assign txp_16 = 1'b0;
assign rx_recovclkout_16= 1'b0;
assign phy_mgmt_readdata_16 = 32'b0;
assign phy_mgmt_waitrequest_16 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 17 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 17)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch17_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c17_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_17
(
.clk(rx_pcs_clk_c17),
.reset(reset_rx_pcs_clk_c17_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_17),
.alt_sync(rx_syncstatus[17]),
.alt_disperr(rx_disp_err[17]),
.alt_ctrldetect(rx_kchar_17),
.alt_errdetect(rx_char_err_gx[17]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[17]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[17]),
.alt_runlengthviolation(rx_runlengthviolation[17]),
.alt_patterndetect(rx_patterndetect[17]),
.alt_runningdisp(rx_runningdisp[17]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_17),
.altpcs_sync(link_status[17]),
.altpcs_disperr(led_disp_err_17),
.altpcs_ctrldetect(pcs_rx_kchar_17),
.altpcs_errdetect(led_char_err_gx[17]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[17]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[17]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[17])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_17.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_17
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_17),
.phy_mgmt_read(phy_mgmt_read_17),
.phy_mgmt_readdata(phy_mgmt_readdata_17),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_17),
.phy_mgmt_write(phy_mgmt_write_17),
.phy_mgmt_writedata(phy_mgmt_writedata_17),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_17),
.rx_serial_data(rxp_17),
.rx_runningdisp(rx_runningdisp[17]),
.rx_disperr(rx_disp_err[17]),
.rx_errdetect(rx_char_err_gx[17]),
.rx_patterndetect(rx_patterndetect[17]),
.rx_syncstatus(rx_syncstatus[17]),
.tx_clkout(tx_pcs_clk_c17),
.rx_clkout(rx_pcs_clk_c17),
.tx_parallel_data(tx_frame_17),
.tx_datak(tx_kchar_17),
.rx_parallel_data(rx_frame_17),
.rx_datak(rx_kchar_17),
.rx_rlv(rx_runlengthviolation[17]),
.rx_recovclkout(rx_recovclkout_17),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[17]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[17]),
.reconfig_togxb(reconfig_togxb_17),
.reconfig_fromgxb(reconfig_fromgxb_17)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_17.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_17.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_17.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_17 = {92{1'b0}};
assign led_char_err_gx[17] = 1'b0;
assign link_status[17] = 1'b0;
assign led_disp_err_17 = 1'b0;
assign txp_17 = 1'b0;
assign rx_recovclkout_17= 1'b0;
assign phy_mgmt_readdata_17 = 32'b0;
assign phy_mgmt_waitrequest_17 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 18 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 18)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch18_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c18_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_18
(
.clk(rx_pcs_clk_c18),
.reset(reset_rx_pcs_clk_c18_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_18),
.alt_sync(rx_syncstatus[18]),
.alt_disperr(rx_disp_err[18]),
.alt_ctrldetect(rx_kchar_18),
.alt_errdetect(rx_char_err_gx[18]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[18]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[18]),
.alt_runlengthviolation(rx_runlengthviolation[18]),
.alt_patterndetect(rx_patterndetect[18]),
.alt_runningdisp(rx_runningdisp[18]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_18),
.altpcs_sync(link_status[18]),
.altpcs_disperr(led_disp_err_18),
.altpcs_ctrldetect(pcs_rx_kchar_18),
.altpcs_errdetect(led_char_err_gx[18]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[18]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[18]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[18])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_18.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_18
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_18),
.phy_mgmt_read(phy_mgmt_read_18),
.phy_mgmt_readdata(phy_mgmt_readdata_18),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_18),
.phy_mgmt_write(phy_mgmt_write_18),
.phy_mgmt_writedata(phy_mgmt_writedata_18),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_18),
.rx_serial_data(rxp_18),
.rx_runningdisp(rx_runningdisp[18]),
.rx_disperr(rx_disp_err[18]),
.rx_errdetect(rx_char_err_gx[18]),
.rx_patterndetect(rx_patterndetect[18]),
.rx_syncstatus(rx_syncstatus[18]),
.tx_clkout(tx_pcs_clk_c18),
.rx_clkout(rx_pcs_clk_c18),
.tx_parallel_data(tx_frame_18),
.tx_datak(tx_kchar_18),
.rx_parallel_data(rx_frame_18),
.rx_datak(rx_kchar_18),
.rx_rlv(rx_runlengthviolation[18]),
.rx_recovclkout(rx_recovclkout_18),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[18]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[18]),
.reconfig_togxb(reconfig_togxb_18),
.reconfig_fromgxb(reconfig_fromgxb_18)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_18.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_18.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_18.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_18 = {92{1'b0}};
assign led_char_err_gx[18] = 1'b0;
assign link_status[18] = 1'b0;
assign led_disp_err_18 = 1'b0;
assign txp_18 = 1'b0;
assign rx_recovclkout_18= 1'b0;
assign phy_mgmt_readdata_18 = 32'b0;
assign phy_mgmt_waitrequest_18 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 19 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 19)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch19_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c19_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_19
(
.clk(rx_pcs_clk_c19),
.reset(reset_rx_pcs_clk_c19_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_19),
.alt_sync(rx_syncstatus[19]),
.alt_disperr(rx_disp_err[19]),
.alt_ctrldetect(rx_kchar_19),
.alt_errdetect(rx_char_err_gx[19]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[19]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[19]),
.alt_runlengthviolation(rx_runlengthviolation[19]),
.alt_patterndetect(rx_patterndetect[19]),
.alt_runningdisp(rx_runningdisp[19]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_19),
.altpcs_sync(link_status[19]),
.altpcs_disperr(led_disp_err_19),
.altpcs_ctrldetect(pcs_rx_kchar_19),
.altpcs_errdetect(led_char_err_gx[19]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[19]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[19]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[19])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_19.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_19
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_19),
.phy_mgmt_read(phy_mgmt_read_19),
.phy_mgmt_readdata(phy_mgmt_readdata_19),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_19),
.phy_mgmt_write(phy_mgmt_write_19),
.phy_mgmt_writedata(phy_mgmt_writedata_19),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_19),
.rx_serial_data(rxp_19),
.rx_runningdisp(rx_runningdisp[19]),
.rx_disperr(rx_disp_err[19]),
.rx_errdetect(rx_char_err_gx[19]),
.rx_patterndetect(rx_patterndetect[19]),
.rx_syncstatus(rx_syncstatus[19]),
.tx_clkout(tx_pcs_clk_c19),
.rx_clkout(rx_pcs_clk_c19),
.tx_parallel_data(tx_frame_19),
.tx_datak(tx_kchar_19),
.rx_parallel_data(rx_frame_19),
.rx_datak(rx_kchar_19),
.rx_rlv(rx_runlengthviolation[19]),
.rx_recovclkout(rx_recovclkout_19),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[19]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[19]),
.reconfig_togxb(reconfig_togxb_19),
.reconfig_fromgxb(reconfig_fromgxb_19)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_19.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_19.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_19.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_19 = {92{1'b0}};
assign led_char_err_gx[19] = 1'b0;
assign link_status[19] = 1'b0;
assign led_disp_err_19 = 1'b0;
assign txp_19 = 1'b0;
assign rx_recovclkout_19= 1'b0;
assign phy_mgmt_readdata_19 = 32'b0;
assign phy_mgmt_waitrequest_19 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 20 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 20)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch20_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c20_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_20
(
.clk(rx_pcs_clk_c20),
.reset(reset_rx_pcs_clk_c20_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_20),
.alt_sync(rx_syncstatus[20]),
.alt_disperr(rx_disp_err[20]),
.alt_ctrldetect(rx_kchar_20),
.alt_errdetect(rx_char_err_gx[20]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[20]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[20]),
.alt_runlengthviolation(rx_runlengthviolation[20]),
.alt_patterndetect(rx_patterndetect[20]),
.alt_runningdisp(rx_runningdisp[20]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_20),
.altpcs_sync(link_status[20]),
.altpcs_disperr(led_disp_err_20),
.altpcs_ctrldetect(pcs_rx_kchar_20),
.altpcs_errdetect(led_char_err_gx[20]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[20]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[20]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[20])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_20.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_20
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_20),
.phy_mgmt_read(phy_mgmt_read_20),
.phy_mgmt_readdata(phy_mgmt_readdata_20),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_20),
.phy_mgmt_write(phy_mgmt_write_20),
.phy_mgmt_writedata(phy_mgmt_writedata_20),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_20),
.rx_serial_data(rxp_20),
.rx_runningdisp(rx_runningdisp[20]),
.rx_disperr(rx_disp_err[20]),
.rx_errdetect(rx_char_err_gx[20]),
.rx_patterndetect(rx_patterndetect[20]),
.rx_syncstatus(rx_syncstatus[20]),
.tx_clkout(tx_pcs_clk_c20),
.rx_clkout(rx_pcs_clk_c20),
.tx_parallel_data(tx_frame_20),
.tx_datak(tx_kchar_20),
.rx_parallel_data(rx_frame_20),
.rx_datak(rx_kchar_20),
.rx_rlv(rx_runlengthviolation[20]),
.rx_recovclkout(rx_recovclkout_20),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[20]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[20]),
.reconfig_togxb(reconfig_togxb_20),
.reconfig_fromgxb(reconfig_fromgxb_20)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_20.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_20.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_20.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_20 = {92{1'b0}};
assign led_char_err_gx[20] = 1'b0;
assign link_status[20] = 1'b0;
assign led_disp_err_20 = 1'b0;
assign txp_20 = 1'b0;
assign rx_recovclkout_20= 1'b0;
assign phy_mgmt_readdata_20 = 32'b0;
assign phy_mgmt_waitrequest_20 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 21 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 21)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch21_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c21_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_21
(
.clk(rx_pcs_clk_c21),
.reset(reset_rx_pcs_clk_c21_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_21),
.alt_sync(rx_syncstatus[21]),
.alt_disperr(rx_disp_err[21]),
.alt_ctrldetect(rx_kchar_21),
.alt_errdetect(rx_char_err_gx[21]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[21]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[21]),
.alt_runlengthviolation(rx_runlengthviolation[21]),
.alt_patterndetect(rx_patterndetect[21]),
.alt_runningdisp(rx_runningdisp[21]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_21),
.altpcs_sync(link_status[21]),
.altpcs_disperr(led_disp_err_21),
.altpcs_ctrldetect(pcs_rx_kchar_21),
.altpcs_errdetect(led_char_err_gx[21]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[21]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[21]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[21])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_21.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_21
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_21),
.phy_mgmt_read(phy_mgmt_read_21),
.phy_mgmt_readdata(phy_mgmt_readdata_21),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_21),
.phy_mgmt_write(phy_mgmt_write_21),
.phy_mgmt_writedata(phy_mgmt_writedata_21),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_21),
.rx_serial_data(rxp_21),
.rx_runningdisp(rx_runningdisp[21]),
.rx_disperr(rx_disp_err[21]),
.rx_errdetect(rx_char_err_gx[21]),
.rx_patterndetect(rx_patterndetect[21]),
.rx_syncstatus(rx_syncstatus[21]),
.tx_clkout(tx_pcs_clk_c21),
.rx_clkout(rx_pcs_clk_c21),
.tx_parallel_data(tx_frame_21),
.tx_datak(tx_kchar_21),
.rx_parallel_data(rx_frame_21),
.rx_datak(rx_kchar_21),
.rx_rlv(rx_runlengthviolation[21]),
.rx_recovclkout(rx_recovclkout_21),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[21]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[21]),
.reconfig_togxb(reconfig_togxb_21),
.reconfig_fromgxb(reconfig_fromgxb_21)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_21.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_21.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_21.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_21 = {92{1'b0}};
assign led_char_err_gx[21] = 1'b0;
assign link_status[21] = 1'b0;
assign led_disp_err_21 = 1'b0;
assign txp_21 = 1'b0;
assign rx_recovclkout_21= 1'b0;
assign phy_mgmt_readdata_21 = 32'b0;
assign phy_mgmt_waitrequest_21 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 22 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 22)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch22_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c22_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_22
(
.clk(rx_pcs_clk_c22),
.reset(reset_rx_pcs_clk_c22_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_22),
.alt_sync(rx_syncstatus[22]),
.alt_disperr(rx_disp_err[22]),
.alt_ctrldetect(rx_kchar_22),
.alt_errdetect(rx_char_err_gx[22]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[22]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[22]),
.alt_runlengthviolation(rx_runlengthviolation[22]),
.alt_patterndetect(rx_patterndetect[22]),
.alt_runningdisp(rx_runningdisp[22]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_22),
.altpcs_sync(link_status[22]),
.altpcs_disperr(led_disp_err_22),
.altpcs_ctrldetect(pcs_rx_kchar_22),
.altpcs_errdetect(led_char_err_gx[22]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[22]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[22]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[22])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_22.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_22
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_22),
.phy_mgmt_read(phy_mgmt_read_22),
.phy_mgmt_readdata(phy_mgmt_readdata_22),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_22),
.phy_mgmt_write(phy_mgmt_write_22),
.phy_mgmt_writedata(phy_mgmt_writedata_22),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_22),
.rx_serial_data(rxp_22),
.rx_runningdisp(rx_runningdisp[22]),
.rx_disperr(rx_disp_err[22]),
.rx_errdetect(rx_char_err_gx[22]),
.rx_patterndetect(rx_patterndetect[22]),
.rx_syncstatus(rx_syncstatus[22]),
.tx_clkout(tx_pcs_clk_c22),
.rx_clkout(rx_pcs_clk_c22),
.tx_parallel_data(tx_frame_22),
.tx_datak(tx_kchar_22),
.rx_parallel_data(rx_frame_22),
.rx_datak(rx_kchar_22),
.rx_rlv(rx_runlengthviolation[22]),
.rx_recovclkout(rx_recovclkout_22),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[22]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[22]),
.reconfig_togxb(reconfig_togxb_22),
.reconfig_fromgxb(reconfig_fromgxb_22)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_22.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_22.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_22.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_22 = {92{1'b0}};
assign led_char_err_gx[22] = 1'b0;
assign link_status[22] = 1'b0;
assign led_disp_err_22 = 1'b0;
assign txp_22 = 1'b0;
assign rx_recovclkout_22= 1'b0;
assign phy_mgmt_readdata_22 = 32'b0;
assign phy_mgmt_waitrequest_22 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 23 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 23)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch23_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c23_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_23
(
.clk(rx_pcs_clk_c23),
.reset(reset_rx_pcs_clk_c23_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_23),
.alt_sync(rx_syncstatus[23]),
.alt_disperr(rx_disp_err[23]),
.alt_ctrldetect(rx_kchar_23),
.alt_errdetect(rx_char_err_gx[23]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[23]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[23]),
.alt_runlengthviolation(rx_runlengthviolation[23]),
.alt_patterndetect(rx_patterndetect[23]),
.alt_runningdisp(rx_runningdisp[23]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_23),
.altpcs_sync(link_status[23]),
.altpcs_disperr(led_disp_err_23),
.altpcs_ctrldetect(pcs_rx_kchar_23),
.altpcs_errdetect(led_char_err_gx[23]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[23]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[23]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[23])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_23.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_23
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_23),
.phy_mgmt_read(phy_mgmt_read_23),
.phy_mgmt_readdata(phy_mgmt_readdata_23),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_23),
.phy_mgmt_write(phy_mgmt_write_23),
.phy_mgmt_writedata(phy_mgmt_writedata_23),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_23),
.rx_serial_data(rxp_23),
.rx_runningdisp(rx_runningdisp[23]),
.rx_disperr(rx_disp_err[23]),
.rx_errdetect(rx_char_err_gx[23]),
.rx_patterndetect(rx_patterndetect[23]),
.rx_syncstatus(rx_syncstatus[23]),
.tx_clkout(tx_pcs_clk_c23),
.rx_clkout(rx_pcs_clk_c23),
.tx_parallel_data(tx_frame_23),
.tx_datak(tx_kchar_23),
.rx_parallel_data(rx_frame_23),
.rx_datak(rx_kchar_23),
.rx_rlv(rx_runlengthviolation[23]),
.rx_recovclkout(rx_recovclkout_23),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[23]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[23]),
.reconfig_togxb(reconfig_togxb_23),
.reconfig_fromgxb(reconfig_fromgxb_23)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_23.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_23.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_23.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_23 = {92{1'b0}};
assign led_char_err_gx[23] = 1'b0;
assign link_status[23] = 1'b0;
assign led_disp_err_23 = 1'b0;
assign txp_23 = 1'b0;
assign rx_recovclkout_23= 1'b0;
assign phy_mgmt_readdata_23 = 32'b0;
assign phy_mgmt_waitrequest_23 = 1'b0;
end
endgenerate
endmodule // module altera_tse_multi_mac_pcs_pma_gige_phyip
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O221A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__O221A_FUNCTIONAL_PP_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o221a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
and and0 (and0_out_X , or0_out, or1_out, C1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O221A_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O32A_2_V
`define SKY130_FD_SC_LS__O32A_2_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o32a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o32a_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o32a_2 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O32A_2_V
|
// ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014
//
// vg93 interface
/*
This file is part of ZX-Evo Base Configuration firmware.
ZX-Evo Base Configuration firmware is free software:
you can redistribute it and/or modify it under the terms of
the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
ZX-Evo Base Configuration firmware is distributed in the hope that
it will be useful, but WITHOUT ANY WARRANTY; without even
the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with ZX-Evo Base Configuration firmware.
If not, see <http://www.gnu.org/licenses/>.
*/
// #1F - vg93 command/state reg {0,0} - not here!
// #3F - vg93 track register {0,1} - not here!
// #5F - vg93 sector register {1,0} - not here!
// #7F - vg93 data register {1,1} - not here!
// #FF - output "system" reg/input (DRQ+IRQ) reg
// output: d6 - FM/MFM - NOT USED ANYWHERE! -> skipped
// d4 - disk side - inverted out
// d3 - head load - for HRDY pin of vg93
// d2 - /RESET for vg93 - must be zero at system reset
// d1:d0 - disk drive select - to the 74138
// input: d7 - /INTRQ - resynced at CPU clock
// d6 - /DRQ - .....................
//
// current limitations:
// 1. read clock regenerator is made of simple counter, as in pentagon128
// 1. write precompensation is based only on SL/SR/TR43 signals
`include "../include/tune.v"
module vg93(
input zclk, // Z80 cpu clock
input rst_n,
input fclk, // fpga 28 MHz clock
output vg_clk,
output reg vg_res_n,
input [7:0] din, // data input from CPU
output intrq,drq, // output signals for the read #FF (not here)
input vg_wrFF, // when TRDOS port #FF written - positive strobe
output reg vg_hrdy,
output wire vg_rclk,
output wire vg_rawr,
output reg [1:0] vg_a, // disk drive selection
output reg vg_wrd,
output reg vg_side,
input step, // step signal from VG93
input vg_sl,vg_sr,vg_tr43,
input rdat_n,
input vg_wf_de,
input vg_drq,
input vg_irq,
input vg_wd
);
localparam WRDELAY_OUTER_LEFT = 4'd4;
localparam WRDELAY_OUTER_RIGHT = 4'd11;
localparam WRDELAY_INNER_LEFT = 4'd0; // minimal delay is for maximum shift left
localparam WRDELAY_INNER_RIGHT = 4'd14; // maximal delay is for maximum shift right
localparam WRDELAY_STANDARD = 4'd7; // no-shift
reg [2:0] vgclk_div7;
wire vgclk_strobe7;
reg [1:0] vgclk_div4;
reg [2:0] step_pulse;
reg [2:0] drq_pulse;
wire step_pospulse;
wire drq_pospulse;
reg turbo_state;
reg [1:0] intrq_sync;
reg [1:0] drq_sync;
reg [1:0] sl_sync,sr_sync,tr43_sync;
reg [2:0] wd_sync;
wire sl,sr,tr43,wd;
reg [3:0] wrdelay_cnt;
wire delay_end;
reg [3:0] wrwidth_cnt;
wire wrwidth_ena;
// reg [4:0] rdat_sync;
// reg rdat_edge1, rdat_edge2;
// wire rdat;
// reg [3:0] rwidth_cnt;
// wire rwidth_ena;
// reg [5:0] rclk_cnt;
// wire rclk_strobe;
// VG93 clocking and turbo-mode
always @(posedge fclk)
begin
step_pulse[2:0] <= { step_pulse[1:0], step};
drq_pulse[2:0] <= { drq_pulse[1:0], vg_drq};
end
assign step_pospulse = ( step_pulse[1] & (~step_pulse[2]) );
assign drq_pospulse = ( drq_pulse[1] & ( ~drq_pulse[2]) );
always @(posedge fclk,negedge rst_n)
begin
if( !rst_n )
turbo_state <= 1'b0;
else
begin
if( drq_pospulse )
turbo_state <= 1'b0;
else if( step_pospulse )
turbo_state <= 1'b1;
end
end
assign vgclk_strobe7 = (vgclk_div7[2:1] == 2'b11); // 28/7=4MHz freq strobe
always @(posedge fclk)
begin
if( vgclk_strobe7 )
vgclk_div7 <= 3'd0;
else
vgclk_div7 <= vgclk_div7 + 3'd1;
end
always @(posedge fclk)
begin
if( vgclk_strobe7 )
begin
vgclk_div4[0] <= ~vgclk_div4[1];
if( turbo_state )
vgclk_div4[1] <= ~vgclk_div4[1];
else
vgclk_div4[1] <= vgclk_div4[0];
end
end
assign vg_clk = vgclk_div4[1];
// input/output for TR-DOS port #FF
always @(posedge zclk, negedge rst_n) // CHANGE IF GO TO THE positive/negative strobes instead of zclk!
begin
if( !rst_n )
vg_res_n <= 1'b0;
else if( vg_wrFF )
{ vg_side, vg_hrdy, vg_res_n, vg_a } <= { (~din[4]),din[3],din[2],din[1:0] };
end
always @(posedge zclk)
begin
intrq_sync[1:0] <= {intrq_sync[0],vg_irq};
drq_sync[1:0] <= {drq_sync[0],vg_drq};
end
assign intrq = intrq_sync[1];
assign drq = drq_sync[1];
// write precompensation
// delay times are as in WRDELAY_* parameters, vg_wrd width is always 7 clocks
always @(posedge fclk)
begin
sl_sync[1:0] <= { sl_sync[0], vg_sl };
sr_sync[1:0] <= { sr_sync[0], vg_sr };
tr43_sync[1:0] <= { tr43_sync[0], vg_tr43 };
wd_sync[2:0] <= { wd_sync[1:0], vg_wd };
end
assign sl = sl_sync[1]; // just state signals
assign sr = sr_sync[1]; //
assign tr43 = tr43_sync[1]; //
assign wd = wd_sync[1] & (~wd_sync[2]); // strobe: beginning of vg_wd
// make delay
always @(posedge fclk)
begin
if( wd )
case( {sl, tr43, sr} )
3'b100: // shift left, outer tracks
wrdelay_cnt <= WRDELAY_OUTER_LEFT;
3'b001: // shift right, outer tracks
wrdelay_cnt <= WRDELAY_OUTER_RIGHT;
3'b110: // shift left, inner tracks
wrdelay_cnt <= WRDELAY_INNER_LEFT;
3'b011: // shift right, inner tracks
wrdelay_cnt <= WRDELAY_INNER_RIGHT;
default: // no shift
wrdelay_cnt <= WRDELAY_STANDARD;
endcase
else if( !delay_end )
wrdelay_cnt <= wrdelay_cnt - 4'd1;
end
assign delay_end = (wrdelay_cnt==4'd0);
// make vg_wdr impulse after a delay
always @(posedge fclk)
if( wrwidth_ena )
begin
if( wd )
wrwidth_cnt <= 4'd0;
else
wrwidth_cnt <= wrwidth_cnt + 4'd1;
end
assign wrwidth_ena = wd | ( delay_end & (~wrwidth_cnt[3]) );
always @(posedge fclk)
vg_wrd <= | wrwidth_cnt[2:0]; // only 7 clocks is the lendth of vg_wrd
/* fapch_counter dpll
(
.fclk (fclk ),
.rdat_n (rdat_n ),
.vg_rclk(vg_rclk),
.vg_rawr(vg_rawr)
);
*/
fapch_zek dpll
(
.fclk (fclk ),
.rdat_n (rdat_n ),
.vg_rclk(vg_rclk),
.vg_rawr(vg_rawr)
);
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 15:19:38 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ led_controller_design_led_controller_0_1_stub.v
// Design : led_controller_design_led_controller_0_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "led_controller_v1_0,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(LEDs_out, s00_axi_awaddr, s00_axi_awprot,
s00_axi_awvalid, s00_axi_awready, s00_axi_wdata, s00_axi_wstrb, s00_axi_wvalid,
s00_axi_wready, s00_axi_bresp, s00_axi_bvalid, s00_axi_bready, s00_axi_araddr,
s00_axi_arprot, s00_axi_arvalid, s00_axi_arready, s00_axi_rdata, s00_axi_rresp,
s00_axi_rvalid, s00_axi_rready, s00_axi_aclk, s00_axi_aresetn)
/* synthesis syn_black_box black_box_pad_pin="LEDs_out[7:0],s00_axi_awaddr[3:0],s00_axi_awprot[2:0],s00_axi_awvalid,s00_axi_awready,s00_axi_wdata[31:0],s00_axi_wstrb[3:0],s00_axi_wvalid,s00_axi_wready,s00_axi_bresp[1:0],s00_axi_bvalid,s00_axi_bready,s00_axi_araddr[3:0],s00_axi_arprot[2:0],s00_axi_arvalid,s00_axi_arready,s00_axi_rdata[31:0],s00_axi_rresp[1:0],s00_axi_rvalid,s00_axi_rready,s00_axi_aclk,s00_axi_aresetn" */;
output [7:0]LEDs_out;
input [3:0]s00_axi_awaddr;
input [2:0]s00_axi_awprot;
input s00_axi_awvalid;
output s00_axi_awready;
input [31:0]s00_axi_wdata;
input [3:0]s00_axi_wstrb;
input s00_axi_wvalid;
output s00_axi_wready;
output [1:0]s00_axi_bresp;
output s00_axi_bvalid;
input s00_axi_bready;
input [3:0]s00_axi_araddr;
input [2:0]s00_axi_arprot;
input s00_axi_arvalid;
output s00_axi_arready;
output [31:0]s00_axi_rdata;
output [1:0]s00_axi_rresp;
output s00_axi_rvalid;
input s00_axi_rready;
input s00_axi_aclk;
input s00_axi_aresetn;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRDLXTP_PP_SYMBOL_V
`define SKY130_FD_SC_LP__SRDLXTP_PP_SYMBOL_V
/**
* srdlxtp: ????.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__srdlxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input SLEEP_B,
input KAPWR ,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRDLXTP_PP_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:39:29 10/01/2015
// Design Name:
// Module Name: Zero_InfMult_Unit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Zero_InfMult_Unit
//SINGLE PRECISION PARAMETERS
# (parameter W = 32)
//DOUBLE PRECISION PARAMETERS
/* # (parameter W = 64) */
(
input wire clk,
input wire rst,
input wire load,
input wire [W-2:0] Data_A,
input wire [W-2:0] Data_B,
output wire zero_m_flag
);
//Wires/////////////////////
wire or_1, or_2;
wire [W-2:0] zero_comp;
wire zero_reg;
////////////////////////////
Comparator_Equal #(.S(W-1)) Data_A_Comp (
.Data_A(Data_A),
.Data_B(zero_comp),
.equal_sgn(or_1)
);
Comparator_Equal #(.S(W-1)) Data_B_Comp (
.Data_A(zero_comp),
.Data_B(Data_B),
.equal_sgn(or_2)
);
RegisterAdd #(.W(1)) Zero_Info_Mult ( //Data X input register
.clk(clk),
.rst(rst),
.load(load),
.D(zero_reg),
.Q(zero_m_flag)
);
assign zero_reg = or_1 || or_2;
generate
if (W == 32)
assign zero_comp = 31'd0;
else
assign zero_comp = 63'd0;
endgenerate
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2005 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Source Synchronous Input Deserializer without delay element
// /___/ /\ Filename : ISERDES_NODELAY.v
// \ \ / \ Timestamp : Fri Oct 21 10:31:45 PDT 2005
// \___\/\___\
//
// Revision:
// 10/21/05 - Initial version.
// 02/28/06 - CR 226003 -- Added Parameter Types (integer/real)
// 06/16/06 - Added new port CLKB
// 10/13/06 - Fixed CR 426606
// 07/07/07 - Added wire declaration for internal signals
// 09/10/07 - CR 447760 Added Strict DRC for BITSLIP and INTERFACE_TYPE combinations
// 12/03/07 - CR 454107 Added DRC warnings for INTERFACE_TYPE, DATA_RATE and DATA_WIDTH combinations
// 01/12/11 - CR 589496 changed some internal parameters to localparams
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module ISERDES_NODELAY (Q1, Q2, Q3, Q4, Q5, Q6, SHIFTOUT1, SHIFTOUT2,
BITSLIP, CE1, CE2, CLK, CLKB, CLKDIV, D, OCLK, RST, SHIFTIN1, SHIFTIN2);
parameter BITSLIP_ENABLE = "FALSE";
parameter DATA_RATE = "DDR";
parameter integer DATA_WIDTH = 4;
parameter INIT_Q1 = 1'b0;
parameter INIT_Q2 = 1'b0;
parameter INIT_Q3 = 1'b0;
parameter INIT_Q4 = 1'b0;
parameter INTERFACE_TYPE = "MEMORY";
parameter integer NUM_CE = 2;
parameter SERDES_MODE = "MASTER";
output Q1;
output Q2;
output Q3;
output Q4;
output Q5;
output Q6;
output SHIFTOUT1;
output SHIFTOUT2;
input BITSLIP;
input CE1;
input CE2;
input CLK;
input CLKB;
input CLKDIV;
input D;
input OCLK;
input RST;
input SHIFTIN1;
input SHIFTIN2;
localparam SRVAL_Q1 = 1'b0;
localparam SRVAL_Q2 = 1'b0;
localparam SRVAL_Q3 = 1'b0;
localparam SRVAL_Q4 = 1'b0;
tri0 GSR = glbl.GSR;
reg [1:0] sel;
reg [3:0] data_width_int;
reg bts_q1, bts_q2, bts_q3;
reg c23, c45, c67;
reg ce1r, ce2r;
reg dataq1rnk2, dataq2rnk2, dataq3rnk2;
reg dataq3rnk1, dataq4rnk1, dataq5rnk1, dataq6rnk1;
reg dataq4rnk2, dataq5rnk2, dataq6rnk2;
reg ice, memmux, q2pmux;
reg mux, mux1, muxc;
reg notifier;
reg clkdiv_int, clkdivmux;
reg o_out = 0, q1_out = 0, q2_out = 0, q3_out = 0, q4_out = 0, q5_out = 0, q6_out = 0;
reg q1rnk2, q2rnk2, q3rnk2, q4rnk2, q5rnk2, q6rnk2;
reg q1rnk3, q2rnk3, q3rnk3, q4rnk3, q5rnk3, q6rnk3;
reg q4rnk1, q5rnk1, q6rnk1, q6prnk1;
reg num_ce_int;
reg qr1, qr2, qhc1, qhc2, qlc1, qlc2;
reg shiftn2_in, shiftn1_in;
reg q1rnk1, q2nrnk1, q1prnk1, q2prnk1, q3rnk1;
reg serdes_mode_int, data_rate_int, bitslip_enable_int;
wire o_delay;
reg rev_in = 0;
wire shiftout1_out, shiftout2_out;
wire [1:0] sel1;
wire [2:0] bsmux;
wire [3:0] selrnk3;
wire bitslip_in;
wire ce1_in;
wire ce2_in;
wire clk_in;
wire clkb_in;
wire clkdiv_in;
wire d_in;
wire dlyce_in;
wire dlyinc_in;
wire dlyrst_in;
wire gsr_in;
wire oclk_in;
wire sr_in;
wire shiftin1_in;
wire shiftin2_in;
buf b_q1 (Q1, q1_out);
buf b_q2 (Q2, q2_out);
buf b_q3 (Q3, q3_out);
buf b_q4 (Q4, q4_out);
buf b_q5 (Q5, q5_out);
buf b_q6 (Q6, q6_out);
buf b_shiftout1 (SHIFTOUT1, shiftout1_out);
buf b_shiftout2 (SHIFTOUT2, shiftout2_out);
buf b_bitslip (bitslip_in, BITSLIP);
buf b_ce1 (ce1_in, CE1);
buf b_ce2 (ce2_in, CE2);
buf b_clk (clk_in, CLK);
buf b_clkb (clkb_in, CLKB);
buf b_clkdiv (clkdiv_in, CLKDIV);
buf b_d (d_in, D);
buf b_gsr (gsr_in, GSR);
buf b_oclk (oclk_in, OCLK);
buf b_sr (sr_in, RST);
buf b_shiftin1 (shiftin1_in, SHIFTIN1);
buf b_shiftin2 (shiftin2_in, SHIFTIN2);
// workaround for XSIM
wire rev_in_AND_NOT_sr_in = rev_in & !sr_in;
wire NOT_rev_in_AND_sr_in = !rev_in & sr_in;
// WARNING !!!: This model may not work properly if the
// following parameters are changed.
// xilinx_internal_parameter on
// Parameter declarations for delays
localparam ffinp = 300;
localparam mxinp1 = 60;
localparam mxinp2 = 120;
// Delay parameters
localparam ffice = 300;
localparam mxice = 60;
// Delay parameter assignment
localparam ffbsc = 300;
localparam mxbsc = 60;
localparam mxinp1_my = 0;
// xilinx_internal_parameter off
// --------CR 454107 DRC Warning -- INTERFACE_TYPE / DATA_RATE / DATA_WIDTH combinations ------------------
task CR454107_msg;
begin
$display("DRC Warning : The combination of INTERFACE_TYPE, DATA_RATE and DATA_WIDTH values on instance %m is not recommended.\n");
$display("The current settings are : INTERFACE_TYPE = %s, DATA_RATE = %s and DATA_WIDTH = %d\n", INTERFACE_TYPE, DATA_RATE, DATA_WIDTH);
$display("The recommended combinations of values are :\n");
$display("NETWORKING SDR 2, 3, 4, 5, 6, 7, 8\n");
$display("NETWORKING DDR 4, 6, 8, 10\n");
$display("MEMORY SDR None\n");
$display("MEMORY DDR 4\n");
end
endtask // CR454107_msg
initial begin
// --------CR 454107 DRC Warning -- INTERFACE_TYPE / DATA_RATE / DATA_WIDTH combinations ------------------
case (INTERFACE_TYPE)
"NETWORKING" :
case(DATA_RATE)
"SDR" :
case(DATA_WIDTH)
2, 3, 4, 5, 6, 7, 8 : ;
default : CR454107_msg;
endcase // DATA_WIDTH
"DDR" :
case(DATA_WIDTH)
4, 6, 8, 10 : ;
default : CR454107_msg;
endcase // DATA_WIDTH
default : ;
endcase // DATA_RATE
"MEMORY" :
case(DATA_RATE)
"DDR" :
case(DATA_WIDTH)
4 : ;
default : CR454107_msg;
endcase // DATA_WIDTH
default : CR454107_msg;
endcase // DATA_RATE
default : ;
endcase // INTERFACE_TYPE
// --------CR 447760 DRC -- BITSLIP - INTERFACE_TYPE combination ------------------
if((INTERFACE_TYPE == "MEMORY") && (BITSLIP_ENABLE == "TRUE")) begin
$display("Attribute Syntax Error: BITSLIP_ENABLE is currently set to TRUE when INTERFACE_TYPE is set to MEMORY. This is an invalid configuration.");
$finish;
end
else if((INTERFACE_TYPE == "NETWORKING") && (BITSLIP_ENABLE == "FALSE")) begin
$display ("Attribute Syntax Error: BITSLIP_ENABLE is currently set to FALSE when INTERFACE_TYPE is set to NETWORKING. If BITSLIP is not intended to be used, please set BITSLIP_ENABLE to TRUE and tie the BITSLIP port to ground.");
$finish;
end
//------------------------------------------------------------------------------------
case (SERDES_MODE)
"MASTER" : serdes_mode_int <= 1'b0;
"SLAVE" : serdes_mode_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute SERDES_MODE on ISERDES_NODELAY instance %m is set to %s. Legal values for this attribute are MASTER or SLAVE", SERDES_MODE);
$finish;
end
endcase // case(SERDES_MODE)
case (DATA_RATE)
"SDR" : data_rate_int <= 1'b1;
"DDR" : data_rate_int <= 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DATA_RATE on ISERDES_NODELAY instance %m is set to %s. Legal values for this attribute are SDR or DDR", DATA_RATE);
$finish;
end
endcase // case(DATA_RATE)
case (BITSLIP_ENABLE)
"FALSE" : bitslip_enable_int <= 1'b0;
"TRUE" : bitslip_enable_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute BITSLIP_ENABLE on ISERDES_NODELAY instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", BITSLIP_ENABLE);
$finish;
end
endcase // case(BITSLIP_ENABLE)
case (DATA_WIDTH)
2, 3, 4, 5, 6, 7, 8, 10 : data_width_int = DATA_WIDTH[3:0];
default : begin
$display("Attribute Syntax Error : The attribute DATA_WIDTH on ISERDES_NODELAY instance %m is set to %d. Legal values for this attribute are 2, 3, 4, 5, 6, 7, 8, or 10", DATA_WIDTH);
$finish;
end
endcase // case(DATA_WIDTH)
case (NUM_CE)
1 : num_ce_int <= 1'b0;
2 : num_ce_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute NUM_CE on ISERDES_NODELAY instance %m is set to %d. Legal values for this attribute are 1 or 2", NUM_CE);
$finish;
end
endcase // case(NUM_CE)
end // initial begin
assign sel1 = {serdes_mode_int, data_rate_int};
assign selrnk3 = {1'b1, bitslip_enable_int, 2'b00};
assign bsmux = {bitslip_enable_int, data_rate_int, muxc};
// GSR
always @(gsr_in) begin
if (gsr_in == 1'b1) begin
assign bts_q3 = 1'b0;
assign bts_q2 = 1'b0;
assign bts_q1 = 1'b0;
assign clkdiv_int = 1'b0;
assign ce1r = 1'b0;
assign ce2r = 1'b0;
assign q1rnk1 = INIT_Q1;
assign q2nrnk1 = INIT_Q2;
assign q1prnk1 = INIT_Q3;
assign q2prnk1 = INIT_Q4;
assign q3rnk1 = 1'b0;
assign q4rnk1 = 1'b0;
assign q5rnk1 = 1'b0;
assign q6rnk1 = 1'b0;
assign q6prnk1 = 1'b0;
assign q6rnk2 = 1'b0;
assign q5rnk2 = 1'b0;
assign q4rnk2 = 1'b0;
assign q3rnk2 = 1'b0;
assign q2rnk2 = 1'b0;
assign q1rnk2 = 1'b0;
assign q6rnk3 = 1'b0;
assign q5rnk3 = 1'b0;
assign q4rnk3 = 1'b0;
assign q3rnk3 = 1'b0;
assign q2rnk3 = 1'b0;
assign q1rnk3 = 1'b0;
end
else if (gsr_in == 1'b0) begin
deassign bts_q3;
deassign bts_q2;
deassign bts_q1;
deassign clkdiv_int;
deassign ce1r;
deassign ce2r;
deassign q1rnk1;
deassign q2nrnk1;
deassign q1prnk1;
deassign q2prnk1;
deassign q3rnk1;
deassign q4rnk1;
deassign q5rnk1;
deassign q6rnk1;
deassign q6prnk1;
deassign q6rnk2;
deassign q5rnk2;
deassign q4rnk2;
deassign q3rnk2;
deassign q2rnk2;
deassign q1rnk2;
deassign q6rnk3;
deassign q5rnk3;
deassign q4rnk3;
deassign q3rnk3;
deassign q2rnk3;
deassign q1rnk3;
end // if (gsr_in == 1'b0)
end // always @ (gsr_in)
// to workaround the glitches generated by mux of assign delay above
// always @(delay_count)
// delay_count_int <= #0 delay_count;
assign o_delay = d_in;
// 1st rank of registers
// Asynchronous Operation
always @(posedge clk_in or posedge rev_in or posedge sr_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
// 1st flop in rank 1 that is full featured
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q1 == 1'b1))
q1rnk1 <= # ffinp SRVAL_Q1;
else if (rev_in == 1'b1)
q1rnk1 <= # ffinp !SRVAL_Q1;
else if (ice == 1'b1)
q1rnk1 <= # ffinp o_delay;
end // always @ (posedge clk_in or posedge rev_in or posedge sr_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
always @(posedge clk_in or posedge sr_in) begin
// rest of flops which are not full featured and don't have clock options
if (sr_in == 1'b1) begin
q5rnk1 <= # ffinp 1'b0;
q6rnk1 <= # ffinp 1'b0;
q6prnk1 <= # ffinp 1'b0;
end
else begin
q5rnk1 <= # ffinp dataq5rnk1;
q6rnk1 <= # ffinp dataq6rnk1;
q6prnk1 <= # ffinp q6rnk1;
end
end // always @ (posedge clk_in or sr_in)
// 2nd flop in rank 1
// Asynchronous Operation
always @(posedge clkb_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q2 == 1'b1))
q2nrnk1 <= # ffinp SRVAL_Q2;
else if (rev_in == 1'b1)
q2nrnk1 <= # ffinp !SRVAL_Q2;
else if (ice == 1'b1)
q2nrnk1 <= # ffinp o_delay;
end // always @ (posedge clkb_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// 4th flop in rank 1 operating on the posedge for networking
// Asynchronous Operation
always @(posedge q2pmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q4 == 1'b1))
q2prnk1 <= # ffinp SRVAL_Q4;
else if (rev_in == 1'b1)
q2prnk1 <= # ffinp !SRVAL_Q4;
else if (ice == 1'b1)
q2prnk1 <= # ffinp q2nrnk1;
end // always @ (posedge q2pmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// 3rd flop in 2nd rank which is full featured and has
// a choice of being clocked by oclk or clk
// Asynchronous Operation
always @(posedge memmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q3 == 1'b1))
q1prnk1 <= # ffinp SRVAL_Q3;
else if (rev_in == 1'b1)
q1prnk1 <= # ffinp !SRVAL_Q3;
else if (ice == 1'b1)
q1prnk1 <= # ffinp q1rnk1;
end // always @ (posedge memmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// 5th and 6th flops in rank 1 which are not full featured but can be clocked
// by either clk or oclk
always @(posedge memmux or posedge sr_in) begin
if (sr_in == 1'b1) begin
q3rnk1 <= # ffinp 1'b0;
q4rnk1 <= # ffinp 1'b0;
end
else begin
q3rnk1 <= # ffinp dataq3rnk1;
q4rnk1 <= # ffinp dataq4rnk1;
end
end // always @ (posedge memmux or posedge sr_in)
//////////////////////////////////////////
// Mux elements for the 1st rank
////////////////////////////////////////
// Optional inverter for q2p (4th flop in rank1)
always @ (memmux) begin
case (INTERFACE_TYPE)
"MEMORY" : q2pmux <= # mxinp1 !memmux;
"NETWORKING" : q2pmux <= # mxinp1 memmux;
default: q2pmux <= # mxinp1 !memmux;
endcase
end // always @ (memmux)
// 4 clock muxs in first rank
always @(clk_in or oclk_in) begin
case (INTERFACE_TYPE)
"MEMORY" : memmux <= # mxinp1 oclk_in;
"NETWORKING" : memmux <= # mxinp1 clk_in;
default : begin
$display("Attribute Syntax Error : The attribute INTERFACE_TYPE on ISERDES_NODELAY instance %m is set to %s. Legal values for this attribute are MEMORY or NETWORKING", INTERFACE_TYPE);
$finish;
end
endcase // case(INTERFACE_TYPE)
end // always @(clk_in or oclk_in)
// data input mux for q3, q4, q5 and q6
always @(sel1 or q1prnk1 or shiftin1_in or shiftin2_in) begin
case (sel1)
2'b00 : dataq3rnk1 <= # mxinp1 q1prnk1;
2'b01 : dataq3rnk1 <= # mxinp1 q1prnk1;
2'b10 : dataq3rnk1 <= # mxinp1 shiftin2_in;
2'b11 : dataq3rnk1 <= # mxinp1 shiftin1_in;
default : dataq3rnk1 <= # mxinp1 q1prnk1;
endcase // case(sel1)
end // always @(sel1 or q1prnk1 or SHIFTIN1 or SHIFTIN2)
always @(sel1 or q2prnk1 or q3rnk1 or shiftin1_in) begin
case (sel1)
2'b00 : dataq4rnk1 <= # mxinp1 q2prnk1;
2'b01 : dataq4rnk1 <= # mxinp1 q3rnk1;
2'b10 : dataq4rnk1 <= # mxinp1 shiftin1_in;
2'b11 : dataq4rnk1 <= # mxinp1 q3rnk1;
default : dataq4rnk1 <= # mxinp1 q2prnk1;
endcase // case(sel1)
end // always @(sel1 or q2prnk1 or q3rnk1 or SHIFTIN1)
always @(data_rate_int or q3rnk1 or q4rnk1) begin
case (data_rate_int)
1'b0 : dataq5rnk1 <= # mxinp1 q3rnk1;
1'b1 : dataq5rnk1 <= # mxinp1 q4rnk1;
default : dataq5rnk1 <= # mxinp1 q4rnk1;
endcase // case(DATA_RATE)
end
always @(data_rate_int or q4rnk1 or q5rnk1) begin
case (data_rate_int)
1'b0 : dataq6rnk1 <= # mxinp1 q4rnk1;
1'b1 : dataq6rnk1 <= # mxinp1 q5rnk1;
default : dataq6rnk1 <= # mxinp1 q5rnk1;
endcase // case(DATA_RATE)
end
// 2nd rank of registers
// clkdivmux to pass clkdiv_int or CLKDIV to rank 2
always @(bitslip_enable_int or clkdiv_int or clkdiv_in) begin
case (bitslip_enable_int)
1'b0 : clkdivmux <= # mxinp1 clkdiv_in;
1'b1 : clkdivmux <= # mxinp1 clkdiv_int;
default : clkdivmux <= # mxinp1 clkdiv_in;
endcase // case(BITSLIP_ENABLE)
end // always @(clkdiv_int or clkdiv_in)
// Asynchronous Operation
always @(posedge clkdivmux or posedge sr_in) begin
if (sr_in == 1'b1) begin
q1rnk2 <= # ffinp 1'b0;
q2rnk2 <= # ffinp 1'b0;
q3rnk2 <= # ffinp 1'b0;
q4rnk2 <= # ffinp 1'b0;
q5rnk2 <= # ffinp 1'b0;
q6rnk2 <= # ffinp 1'b0;
end
else begin
q1rnk2 <= # ffinp dataq1rnk2;
q2rnk2 <= # ffinp dataq2rnk2;
q3rnk2 <= # ffinp dataq3rnk2;
q4rnk2 <= # ffinp dataq4rnk2;
q5rnk2 <= # ffinp dataq5rnk2;
q6rnk2 <= # ffinp dataq6rnk2;
end
end // always @ (posedge clkdivmux or sr_in)
// Data mux for 2nd rank of flops
// Delay for mux set to 120
always @(bsmux or q1rnk1 or q1prnk1 or q2prnk1) begin
casex (bsmux)
3'b00X : dataq1rnk2 <= # mxinp2 q2prnk1;
3'b100 : dataq1rnk2 <= # mxinp2 q2prnk1;
3'b101 : dataq1rnk2 <= # mxinp2 q1prnk1;
3'bX1X : dataq1rnk2 <= # mxinp2 q1rnk1;
default : dataq1rnk2 <= # mxinp2 q2prnk1;
endcase // casex(bsmux)
end // always @(bsmux or q1rnk1 or q1prnk1 or q2prnk1)
always @(bsmux or q1prnk1 or q4rnk1) begin
casex (bsmux)
3'b00X : dataq2rnk2 <= # mxinp2 q1prnk1;
3'b100 : dataq2rnk2 <= # mxinp2 q1prnk1;
3'b101 : dataq2rnk2 <= # mxinp2 q4rnk1;
3'bX1X : dataq2rnk2 <= # mxinp2 q1prnk1;
default : dataq2rnk2 <= # mxinp2 q1prnk1;
endcase // casex(bsmux)
end // always @(bsmux or q1prnk1 or q4rnk1)
always @(bsmux or q3rnk1 or q4rnk1) begin
casex (bsmux)
3'b00X : dataq3rnk2 <= # mxinp2 q4rnk1;
3'b100 : dataq3rnk2 <= # mxinp2 q4rnk1;
3'b101 : dataq3rnk2 <= # mxinp2 q3rnk1;
3'bX1X : dataq3rnk2 <= # mxinp2 q3rnk1;
default : dataq3rnk2 <= # mxinp2 q4rnk1;
endcase // casex(bsmux)
end // always @(bsmux or q3rnk1 or q4rnk1)
always @(bsmux or q3rnk1 or q4rnk1 or q6rnk1) begin
casex (bsmux)
3'b00X : dataq4rnk2 <= # mxinp2 q3rnk1;
3'b100 : dataq4rnk2 <= # mxinp2 q3rnk1;
3'b101 : dataq4rnk2 <= # mxinp2 q6rnk1;
3'bX1X : dataq4rnk2 <= # mxinp2 q4rnk1;
default : dataq4rnk2 <= # mxinp2 q3rnk1;
endcase // casex(bsmux)
end // always @(bsmux or q3rnk1 or q4rnk1 or q6rnk1)
always @(bsmux or q5rnk1 or q6rnk1) begin
casex (bsmux)
3'b00X : dataq5rnk2 <= # mxinp2 q6rnk1;
3'b100 : dataq5rnk2 <= # mxinp2 q6rnk1;
3'b101 : dataq5rnk2 <= # mxinp2 q5rnk1;
3'bX1X : dataq5rnk2 <= # mxinp2 q5rnk1;
default : dataq5rnk2 <= # mxinp2 q6rnk1;
endcase // casex(bsmux)
end // always @(bsmux or q5rnk1 or q6rnk1)
always @(bsmux or q5rnk1 or q6rnk1 or q6prnk1) begin
casex (bsmux)
3'b00X : dataq6rnk2 <= # mxinp2 q5rnk1;
3'b100 : dataq6rnk2 <= # mxinp2 q5rnk1;
3'b101 : dataq6rnk2 <= # mxinp2 q6prnk1;
3'bX1X : dataq6rnk2 <= # mxinp2 q6rnk1;
default : dataq6rnk2 <= # mxinp2 q5rnk1;
endcase // casex(bsmux)
end // always @(bsmux or q5rnk1 or q6rnk1 or q6prnk1)
// 3rd rank of registers
// Asynchronous Operation
always @(posedge clkdiv_in or posedge sr_in) begin
if (sr_in == 1'b1) begin
q1rnk3 <= # ffinp 1'b0;
q2rnk3 <= # ffinp 1'b0;
q3rnk3 <= # ffinp 1'b0;
q4rnk3 <= # ffinp 1'b0;
q5rnk3 <= # ffinp 1'b0;
q6rnk3 <= # ffinp 1'b0;
end
else begin
q1rnk3 <= # ffinp q1rnk2;
q2rnk3 <= # ffinp q2rnk2;
q3rnk3 <= # ffinp q3rnk2;
q4rnk3 <= # ffinp q4rnk2;
q5rnk3 <= # ffinp q5rnk2;
q6rnk3 <= # ffinp q6rnk2;
end
end // always @ (posedge clkdiv_in or posedge sr_in)
// Outputs
assign shiftout2_out = q5rnk1;
assign shiftout1_out = q6rnk1;
always @(selrnk3 or q1rnk1 or q1prnk1 or q1rnk2 or q1rnk3) begin
casex (selrnk3)
4'b0X00 : q1_out <= # mxinp1_my q1prnk1;
4'b0X01 : q1_out <= # mxinp1_my q1rnk1;
4'b0X10 : q1_out <= # mxinp1_my q1rnk1;
4'b10XX : q1_out <= # mxinp1_my q1rnk2;
4'b11XX : q1_out <= # mxinp1_my q1rnk3;
default : q1_out <= # mxinp1_my q1rnk2;
endcase // casex(selrnk3)
end // always @(selrnk3 or q1rnk1 or q1prnk1 or q1rnk2 or q1rnk3)
always @(selrnk3 or q2nrnk1 or q2prnk1 or q2rnk2 or q2rnk3) begin
casex (selrnk3)
4'b0X00 : q2_out <= # mxinp1_my q2prnk1;
4'b0X01 : q2_out <= # mxinp1_my q2prnk1;
4'b0X10 : q2_out <= # mxinp1_my q2nrnk1;
4'b10XX : q2_out <= # mxinp1_my q2rnk2;
4'b11XX : q2_out <= # mxinp1_my q2rnk3;
default : q2_out <= # mxinp1_my q2rnk2;
endcase // casex(selrnk3)
end // always @(selrnk3 or q2nrnk1 or q2prnk1 or q2rnk2 or q2rnk3)
always @(bitslip_enable_int or q3rnk2 or q3rnk3) begin
case (bitslip_enable_int)
1'b0 : q3_out <= # mxinp1_my q3rnk2;
1'b1 : q3_out <= # mxinp1_my q3rnk3;
endcase // case(BITSLIP_ENABLE)
end // always @ (q3rnk2 or q3rnk3)
always @(bitslip_enable_int or q4rnk2 or q4rnk3) begin
casex (bitslip_enable_int)
1'b0 : q4_out <= # mxinp1_my q4rnk2;
1'b1 : q4_out <= # mxinp1_my q4rnk3;
endcase // casex(BITSLIP_ENABLE)
end // always @ (q4rnk2 or q4rnk3)
always @(bitslip_enable_int or q5rnk2 or q5rnk3) begin
casex (bitslip_enable_int)
1'b0 : q5_out <= # mxinp1_my q5rnk2;
1'b1 : q5_out <= # mxinp1_my q5rnk3;
endcase // casex(BITSLIP_ENABLE)
end // always @ (q5rnk2 or q5rnk3)
always @(bitslip_enable_int or q6rnk2 or q6rnk3) begin
casex (bitslip_enable_int)
1'b0 : q6_out <= # mxinp1_my q6rnk2;
1'b1 : q6_out <= # mxinp1_my q6rnk3;
endcase // casex(BITSLIP_ENABLE)
end // always @ (q6rnk2 or q6rnk3)
// Set value of counter in bitslip controller
always @(data_rate_int or data_width_int) begin
casex ({data_rate_int, data_width_int})
5'b00100 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b00110 : begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b01000 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end
5'b01010 : begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end
5'b10010 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b10011 : begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b10100 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end
5'b10101 : begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end
5'b10110 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b10; end
5'b10111 : begin c23=1'b0; c45=1'b0; c67=1'b1; sel=2'b10; end
5'b11000 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b11; end
default : begin
$display("DATA_WIDTH %d and DATA_RATE %s at %t is an illegal value", DATA_WIDTH, DATA_RATE, $time);
$finish;
end
endcase
end // always @ (data_rate_int or data_width_int)
///////////////////////////////////////////
// Bit slip controler
///////////////////////////////////////////
// Divide by 2 - 8 counter
// Asynchronous Operation
always @ (posedge qr2 or negedge clk_in) begin
if (qr2 == 1'b1) begin
clkdiv_int <= # ffbsc 1'b0;
bts_q1 <= # ffbsc 1'b0;
bts_q2 <= # ffbsc 1'b0;
bts_q3 <= # ffbsc 1'b0;
end
else if (qhc1 == 1'b0) begin
bts_q3 <= # ffbsc bts_q2;
bts_q2 <= # ffbsc (!(!clkdiv_int & !bts_q2) & bts_q1);
bts_q1 <= # ffbsc clkdiv_int;
clkdiv_int <= # ffbsc mux;
end
end // always @ (posedge qr2 or negedge clk_in)
// Synchronous Operation
always @ (negedge clk_in) begin
if (qr2 == 1'b1) begin
clkdiv_int <= # ffbsc 1'b0;
bts_q1 <= # ffbsc 1'b0;
bts_q2 <= # ffbsc 1'b0;
bts_q3 <= # ffbsc 1'b0;
end
else if (qhc1 == 1'b1) begin
clkdiv_int <= # ffbsc clkdiv_int;
bts_q1 <= # ffbsc bts_q1;
bts_q2 <= # ffbsc bts_q2;
bts_q3 <= # ffbsc bts_q3;
end
else begin
bts_q3 <= # ffbsc bts_q2;
bts_q2 <= # ffbsc (!(!clkdiv_int & !bts_q2) & bts_q1);
bts_q1 <= # ffbsc clkdiv_int;
clkdiv_int <= # ffbsc mux;
end
end // always @ (negedge clk_in)
// 4:1 selector mux and divider selections
always @ (sel or c23 or c45 or c67 or clkdiv_int or bts_q1 or bts_q2 or bts_q3) begin
case (sel)
2'b00 : mux <= # mxbsc !(clkdiv_int | (c23 & bts_q1));
2'b01 : mux <= # mxbsc !(bts_q1 | (c45 & bts_q2));
2'b10 : mux <= # mxbsc !(bts_q2 | (c67 & bts_q3));
2'b11 : mux <= # mxbsc !bts_q3;
default : mux <= # mxbsc !(clkdiv_int | (c23 & bts_q1));
endcase
end // always @ (sel or c23 or c45 or c67 or clkdiv_int or bts_q1 or bts_q2 or bts_q3)
// Bitslip control logic
// Low speed control flop
// Asynchronous Operation
always @ (posedge qr1 or posedge clkdiv_in) begin
if (qr1 == 1'b1) begin
qlc1 <= # ffbsc 1'b0;
qlc2 <= # ffbsc 1'b0;
end
else if (bitslip_in == 1'b0) begin
qlc1 <= # ffbsc qlc1;
qlc2 <= # ffbsc 1'b0;
end
else begin
qlc1 <= # ffbsc !qlc1;
qlc2 <= # ffbsc (bitslip_in & mux1);
end
end // always @ (posedge qr1 or posedge clkdiv_in)
// Mux to select between sdr "1" and ddr "0"
always @ (data_rate_int or qlc1) begin
case (data_rate_int)
1'b0 : mux1 <= # mxbsc qlc1;
1'b1 : mux1 <= # mxbsc 1'b1;
endcase
end
// High speed control flop
// Asynchronous Operation
always @ (posedge qr2 or negedge clk_in) begin
if (qr2 == 1'b1) begin
qhc1 <= # ffbsc 1'b0;
qhc2 <= # ffbsc 1'b0;
end
else begin
qhc1 <= # ffbsc (qlc2 & !qhc2);
qhc2 <= # ffbsc qlc2;
end
end // always @ (posedge qr2 or negedge clk_in)
// Mux that drives control line of mux in front
// of 2nd rank of flops
always @ (data_rate_int or mux1) begin
case (data_rate_int)
1'b0 : muxc <= # mxbsc mux1;
1'b1 : muxc <= # mxbsc 1'b0;
endcase
end
// Asynchronous set flops
// Low speed reset flop
// Asynchronous Operation
always @ (posedge sr_in or posedge clkdiv_in) begin
if (sr_in == 1'b1)
qr1 <= # ffbsc 1'b1;
else
qr1 <= # ffbsc 1'b0;
end // always @ (posedge sr_in or posedge clkdiv_in)
// High speed reset flop
// Asynchronous Operation
always @ (posedge sr_in or negedge clk_in) begin
if (sr_in == 1'b1)
qr2 <= # ffbsc 1'b1;
else
qr2 <= # ffbsc qr1;
end // always @ (posedge sr_in or negedge clk_in)
/////////////////////////////////////////////
// ICE
///////////////////////////////////////////
// Asynchronous Operation
always @ (posedge clkdiv_in or posedge sr_in) begin
if (sr_in == 1'b1) begin
ce1r <= # ffice 1'b0;
ce2r <= # ffice 1'b0;
end
else begin
ce1r <= # ffice ce1_in;
ce2r <= # ffice ce2_in;
end
end // always @ (posedge clkdiv_in or posedge sr_in)
// Output mux ice
always @ (num_ce_int or clkdiv_in or ce1_in or ce1r or ce2r) begin
case ({num_ce_int, clkdiv_in})
2'b00 : ice <= # mxice ce1_in;
2'b01 : ice <= # mxice ce1_in;
// 426606
2'b10 : ice <= # mxice ce2r;
2'b11 : ice <= # mxice ce1r;
default : ice <= # mxice ce1_in;
endcase
end
//*** Timing Checks Start here
specify
(CLKDIV => Q1) = (100:100:100, 100:100:100);
(CLKDIV => Q2) = (100:100:100, 100:100:100);
(CLKDIV => Q3) = (100:100:100, 100:100:100);
(CLKDIV => Q4) = (100:100:100, 100:100:100);
(CLKDIV => Q5) = (100:100:100, 100:100:100);
(CLKDIV => Q6) = (100:100:100, 100:100:100);
specparam PATHPULSE$ = 0;
endspecify
endmodule // ISERDES_NODELAY
`endcelldefine
|
module RegisterFileTestBench2;
parameter sim_time = 750*2; // Num of Cycles * 2
reg [31:0] in,Pcin;
reg [19:0] RSLCT;
reg Clk, RESET, LOADPC, LOAD,IR_CU;
wire [31:0] Rn,Rm,Rs,PCout;
//RegisterFile(input [31:0] in,Pcin,input [19:0] RSLCT,input Clk, RESET, LOADPC, LOAD,IR_CU, output [31:0] Rn,Rm,Rs,PCout);
RegisterFile RF(in,Pcin,RSLCT,Clk, RESET, LOADPC, LOAD,IR_CU, Rn,Rm,Rs,PCout);
initial fork
//Clk 0
Clk = 0 ; RESET = 1 ; Pcin = 32'bz ; in = 32'bz ; LOADPC = 0 ; LOAD = 0 ;IR_CU = 1 ; RSLCT[3:0] = 0 ; RSLCT[7:4] = 0 ; RSLCT[11:8] = 0 ; RSLCT[15:12] = 0 ; RSLCT[19:16] = 0 ;
//Clk 1 (Rising Edge)
#1 RESET = 0 ; #1 Pcin = 32'bz ; #1 in = 1 ; #1 LOADPC = 0 ; #1 LOAD = 1 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0 ; #1 RSLCT[7:4] = 0 ; #1 RSLCT[11:8] = 0 ; #1 RSLCT[15:12] = 0 ; #1 RSLCT[19:16] = 0 ;
//Clk 0 (Falling Edge)
#2 Pcin = 32'bz ; #2 in = 1 ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ; #2 RSLCT[3:0] = 0 ; #2 RSLCT[7:4] = 0 ; #2 RSLCT[11:8] = 0 ; #2 RSLCT[15:12] = 0 ; #2 RSLCT[19:16] = 0 ;
//Clk 1 (Rising Edge)
#3 Pcin = 32'bz ; #3 in = Rn ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ; #3 RSLCT[3:0] = 0 ; #3 RSLCT[7:4] = 0 ; #3 RSLCT[11:8] = 0 ; #3 RSLCT[15:12] = 1 ; #3 RSLCT[19:16] = 0 ;
//Clk 0 (Falling Edge)
#4 Pcin = 32'bz ; #4 in = Rn ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ; #4 RSLCT[3:0] = 0 ; #4 RSLCT[7:4] = 0 ; #4 RSLCT[11:8] = 0 ; #4 RSLCT[15:12] = 1 ; #4 RSLCT[19:16] = 0 ;
//Clk 1 (Rising Edge)
#5 Pcin = 32'bz ; #5 in = Rn ; #5 LOADPC = 0 ; #5 LOAD = 1 ; #5 IR_CU = 1 ; #5 RSLCT[3:0] = 0 ; #5 RSLCT[7:4] = 0 ; #5 RSLCT[11:8] = 0 ; #5 RSLCT[15:12] = 2 ; #5 RSLCT[19:16] = 0 ;
//Clk 0 (Falling Edge)
#6 Pcin = 32'bz ; #6 in = Rn ; #6 LOADPC = 0 ; #6 LOAD = 1 ; #6 IR_CU = 1 ; #6 RSLCT[3:0] = 0 ; #6 RSLCT[7:4] = 0 ; #6 RSLCT[11:8] = 0 ; #6 RSLCT[15:12] = 2 ; #6 RSLCT[19:16] = 0 ;
join
always
#1 Clk = ~Clk;
initial #sim_time $finish;
initial begin
$dumpfile("RegisterFileTestBench2.vcd");
$dumpvars(0,RegisterFileTestBench2);
$display(" Test Results" );
$monitor("time = %3d ,Pcin = %3d , in = %3d , LOADPC = %3d , LOAD = %3d , IR_CU = %3d , RSLCT = %3d , Rn = %3d ,Rm = %3d ,Rs = %3d ,PCout = %3d",$time,Pcin, in, LOADPC, LOAD, IR_CU, RSLCT,Rn,Rm,Rs,PCout);
end
endmodule
//iverilog Buffer32_32.v Decoder4x16.v Multiplexer2x1_32b.v Register.v RegisterFile.v RegisterFileTestBench2.v |
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1 ns / 1 ps
/*
* Synchronizes an asyncronous signal to a given clock by using a pipeline of
* two registers.
*/
module sync_signal #(
parameter WIDTH=1, // width of the input and output signals
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire [WIDTH-1:0] in,
output wire [WIDTH-1:0] out
);
reg [WIDTH-1:0] sync_reg[N-1:0];
/*
* The synchronized output is the last register in the pipeline.
*/
assign out = sync_reg[N-1];
integer k;
always @(posedge clk) begin
sync_reg[0] <= in;
for (k = 1; k < N; k = k + 1) begin
sync_reg[k] <= sync_reg[k-1];
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
//
// This is a copy of t_param.v with the parentheses around the module parameters
// removed.
module t (/*AUTOARG*/
// Inputs
clk
);
parameter PAR = 3;
m1 #PAR m1();
m3 #PAR m3();
mnooverride #10 mno();
input clk;
integer cyc=1;
reg [4:0] bitsel;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
bitsel = 0;
if (PAR[bitsel]!==1'b1) $stop;
bitsel = 1;
if (PAR[bitsel]!==1'b1) $stop;
bitsel = 2;
if (PAR[bitsel]!==1'b0) $stop;
end
if (cyc==1) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module m1;
localparam PAR1MINUS1 = PAR1DUP-2-1;
localparam PAR1DUP = PAR1+2; // Check we propagate parameters properly
parameter PAR1 = 0;
m2 #PAR1MINUS1 m2 ();
endmodule
module m2;
parameter PAR2 = 10;
initial begin
$display("%x",PAR2);
if (PAR2 !== 2) $stop;
end
endmodule
module m3;
localparam LOC = 13;
parameter PAR = 10;
initial begin
$display("%x %x",LOC,PAR);
if (LOC !== 13) $stop;
if (PAR !== 3) $stop;
end
endmodule
module mnooverride;
localparam LOC = 13;
parameter PAR = 10;
initial begin
$display("%x %x",LOC,PAR);
if (LOC !== 13) $stop;
if (PAR !== 10) $stop;
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Thu Sep 28 10:19:23 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_rx_inst_sim_netlist.v
// Design : fifo_generator_rx_inst
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "fifo_generator_rx_inst,fifo_generator_v13_1_2,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(clk,
rst,
din,
wr_en,
rd_en,
dout,
full,
empty);
(* x_interface_info = "xilinx.com:signal:clock:1.0 core_clk CLK" *) input clk;
input rst;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *) input [63:0]din;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *) output [63:0]dout;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_en;
wire rst;
wire wr_en;
wire NLW_U0_almost_empty_UNCONNECTED;
wire NLW_U0_almost_full_UNCONNECTED;
wire NLW_U0_axi_ar_dbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_overflow_UNCONNECTED;
wire NLW_U0_axi_ar_prog_empty_UNCONNECTED;
wire NLW_U0_axi_ar_prog_full_UNCONNECTED;
wire NLW_U0_axi_ar_sbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_underflow_UNCONNECTED;
wire NLW_U0_axi_aw_dbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_overflow_UNCONNECTED;
wire NLW_U0_axi_aw_prog_empty_UNCONNECTED;
wire NLW_U0_axi_aw_prog_full_UNCONNECTED;
wire NLW_U0_axi_aw_sbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_underflow_UNCONNECTED;
wire NLW_U0_axi_b_dbiterr_UNCONNECTED;
wire NLW_U0_axi_b_overflow_UNCONNECTED;
wire NLW_U0_axi_b_prog_empty_UNCONNECTED;
wire NLW_U0_axi_b_prog_full_UNCONNECTED;
wire NLW_U0_axi_b_sbiterr_UNCONNECTED;
wire NLW_U0_axi_b_underflow_UNCONNECTED;
wire NLW_U0_axi_r_dbiterr_UNCONNECTED;
wire NLW_U0_axi_r_overflow_UNCONNECTED;
wire NLW_U0_axi_r_prog_empty_UNCONNECTED;
wire NLW_U0_axi_r_prog_full_UNCONNECTED;
wire NLW_U0_axi_r_sbiterr_UNCONNECTED;
wire NLW_U0_axi_r_underflow_UNCONNECTED;
wire NLW_U0_axi_w_dbiterr_UNCONNECTED;
wire NLW_U0_axi_w_overflow_UNCONNECTED;
wire NLW_U0_axi_w_prog_empty_UNCONNECTED;
wire NLW_U0_axi_w_prog_full_UNCONNECTED;
wire NLW_U0_axi_w_sbiterr_UNCONNECTED;
wire NLW_U0_axi_w_underflow_UNCONNECTED;
wire NLW_U0_axis_dbiterr_UNCONNECTED;
wire NLW_U0_axis_overflow_UNCONNECTED;
wire NLW_U0_axis_prog_empty_UNCONNECTED;
wire NLW_U0_axis_prog_full_UNCONNECTED;
wire NLW_U0_axis_sbiterr_UNCONNECTED;
wire NLW_U0_axis_underflow_UNCONNECTED;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_m_axi_arvalid_UNCONNECTED;
wire NLW_U0_m_axi_awvalid_UNCONNECTED;
wire NLW_U0_m_axi_bready_UNCONNECTED;
wire NLW_U0_m_axi_rready_UNCONNECTED;
wire NLW_U0_m_axi_wlast_UNCONNECTED;
wire NLW_U0_m_axi_wvalid_UNCONNECTED;
wire NLW_U0_m_axis_tlast_UNCONNECTED;
wire NLW_U0_m_axis_tvalid_UNCONNECTED;
wire NLW_U0_overflow_UNCONNECTED;
wire NLW_U0_prog_empty_UNCONNECTED;
wire NLW_U0_prog_full_UNCONNECTED;
wire NLW_U0_rd_rst_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_s_axis_tready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire NLW_U0_underflow_UNCONNECTED;
wire NLW_U0_valid_UNCONNECTED;
wire NLW_U0_wr_ack_UNCONNECTED;
wire NLW_U0_wr_rst_busy_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED;
wire [9:0]NLW_U0_data_count_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED;
wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED;
wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED;
wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED;
wire [9:0]NLW_U0_rd_data_count_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED;
wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED;
wire [9:0]NLW_U0_wr_data_count_UNCONNECTED;
(* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *)
(* C_APPLICATION_TYPE_WACH = "0" *)
(* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *)
(* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *)
(* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *)
(* C_AXIS_TYPE = "0" *)
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_COMMON_CLOCK = "1" *)
(* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "10" *)
(* C_DEFAULT_VALUE = "BlankString" *)
(* C_DIN_WIDTH = "64" *)
(* C_DIN_WIDTH_AXIS = "1" *)
(* C_DIN_WIDTH_RACH = "32" *)
(* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "1" *)
(* C_DIN_WIDTH_WDCH = "64" *)
(* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *)
(* C_DOUT_WIDTH = "64" *)
(* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *)
(* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "kintex7" *)
(* C_FULL_FLAGS_RST_VAL = "1" *)
(* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *)
(* C_HAS_AXIS_TDATA = "1" *)
(* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *)
(* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *)
(* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *)
(* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *)
(* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *)
(* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *)
(* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *)
(* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "1" *)
(* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *)
(* C_HAS_UNDERFLOW = "0" *)
(* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "0" *)
(* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "0" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "1" *)
(* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *)
(* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_INIT_WR_PNTR_VAL = "0" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *)
(* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *)
(* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *)
(* C_PRELOAD_REGS = "0" *)
(* C_PRIM_FIFO_TYPE = "1kx36" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *)
(* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *)
(* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "1022" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "1021" *)
(* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *)
(* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *)
(* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "10" *)
(* C_RD_DEPTH = "1024" *)
(* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "10" *)
(* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *)
(* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *)
(* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SELECT_XPM = "0" *)
(* C_SYNCHRONIZER_STAGE = "2" *)
(* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "10" *)
(* C_WR_DEPTH = "1024" *)
(* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *)
(* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "10" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "10" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 U0
(.almost_empty(NLW_U0_almost_empty_UNCONNECTED),
.almost_full(NLW_U0_almost_full_UNCONNECTED),
.axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]),
.axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED),
.axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED),
.axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED),
.axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]),
.axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED),
.axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED),
.axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]),
.axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]),
.axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED),
.axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED),
.axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED),
.axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]),
.axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED),
.axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED),
.axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]),
.axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]),
.axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED),
.axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED),
.axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED),
.axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]),
.axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED),
.axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED),
.axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]),
.axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]),
.axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED),
.axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED),
.axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED),
.axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]),
.axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED),
.axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED),
.axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]),
.axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]),
.axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED),
.axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED),
.axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED),
.axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]),
.axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED),
.axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED),
.axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]),
.axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]),
.axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(NLW_U0_axis_overflow_UNCONNECTED),
.axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED),
.axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED),
.axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]),
.axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED),
.axis_underflow(NLW_U0_axis_underflow_UNCONNECTED),
.axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]),
.backup(1'b0),
.backup_marker(1'b0),
.clk(clk),
.data_count(NLW_U0_data_count_UNCONNECTED[9:0]),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]),
.m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]),
.m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]),
.m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(1'b0),
.m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED),
.m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]),
.m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]),
.m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]),
.m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(1'b0),
.m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED),
.m_axi_bid(1'b0),
.m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED),
.m_axi_bresp({1'b0,1'b0}),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rid(1'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED),
.m_axi_rresp({1'b0,1'b0}),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]),
.m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED),
.m_axi_wready(1'b0),
.m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]),
.m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED),
.m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]),
.m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]),
.m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]),
.m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]),
.m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED),
.m_axis_tready(1'b0),
.m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]),
.m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]),
.m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED),
.overflow(NLW_U0_overflow_UNCONNECTED),
.prog_empty(NLW_U0_prog_empty_UNCONNECTED),
.prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full(NLW_U0_prog_full_UNCONNECTED),
.prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.rd_clk(1'b0),
.rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[9:0]),
.rd_en(rd_en),
.rd_rst(1'b0),
.rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED),
.rst(rst),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot({1'b0,1'b0,1'b0}),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot({1'b0,1'b0,1'b0}),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axis_tdest(1'b0),
.s_axis_tid(1'b0),
.s_axis_tkeep(1'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED),
.s_axis_tstrb(1'b0),
.s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
.s_axis_tvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.srst(1'b0),
.underflow(NLW_U0_underflow_UNCONNECTED),
.valid(NLW_U0_valid_UNCONNECTED),
.wr_ack(NLW_U0_wr_ack_UNCONNECTED),
.wr_clk(1'b0),
.wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[9:0]),
.wr_en(wr_en),
.wr_rst(1'b0),
.wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
(dout,
clk,
WEA,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[9] ,
din);
output [63:0]dout;
input clk;
input [0:0]WEA;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]Q;
input [9:0]\gc0.count_d1_reg[9] ;
input [63:0]din;
wire [9:0]Q;
wire [0:0]WEA;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [0:0]out;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width \ramloop[0].ram.r
(.Q(Q),
.WEA(WEA),
.clk(clk),
.din(din[35:0]),
.dout(dout[35:0]),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.out(out),
.tmp_ram_rd_en(tmp_ram_rd_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.Q(Q),
.WEA(WEA),
.clk(clk),
.din(din[63:36]),
.dout(dout[63:36]),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.out(out),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
(dout,
clk,
WEA,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[9] ,
din);
output [35:0]dout;
input clk;
input [0:0]WEA;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]Q;
input [9:0]\gc0.count_d1_reg[9] ;
input [35:0]din;
wire [9:0]Q;
wire [0:0]WEA;
wire clk;
wire [35:0]din;
wire [35:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [0:0]out;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.Q(Q),
.WEA(WEA),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.out(out),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0
(dout,
clk,
WEA,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[9] ,
din);
output [27:0]dout;
input clk;
input [0:0]WEA;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]Q;
input [9:0]\gc0.count_d1_reg[9] ;
input [27:0]din;
wire [9:0]Q;
wire [0:0]WEA;
wire clk;
wire [27:0]din;
wire [27:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [0:0]out;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram
(.Q(Q),
.WEA(WEA),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.out(out),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
(dout,
clk,
WEA,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[9] ,
din);
output [35:0]dout;
input clk;
input [0:0]WEA;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]Q;
input [9:0]\gc0.count_d1_reg[9] ;
input [35:0]din;
wire [9:0]Q;
wire [0:0]WEA;
wire clk;
wire [35:0]din;
wire [35:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [0:0]out;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[9] ,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({din[34:27],din[25:18],din[16:9],din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({din[35],din[26],din[17],din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({dout[34:27],dout[25:18],dout[16:9],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({dout[35],dout[26],dout[17],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(WEA),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(out),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({WEA,WEA,WEA,WEA}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0
(dout,
clk,
WEA,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[9] ,
din);
output [27:0]dout;
input clk;
input [0:0]WEA;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]Q;
input [9:0]\gc0.count_d1_reg[9] ;
input [27:0]din;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ;
wire [9:0]Q;
wire [0:0]WEA;
wire clk;
wire [27:0]din;
wire [27:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [0:0]out;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[9] ,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,din[27:21],1'b0,din[20:14],1'b0,din[13:7],1'b0,din[6:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53 ,dout[27:21],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61 ,dout[20:14],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69 ,dout[13:7],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ,dout[6:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(WEA),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(out),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({WEA,WEA,WEA,WEA}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
(dout,
clk,
WEA,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[9] ,
din);
output [63:0]dout;
input clk;
input [0:0]WEA;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]Q;
input [9:0]\gc0.count_d1_reg[9] ;
input [63:0]din;
wire [9:0]Q;
wire [0:0]WEA;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [0:0]out;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr \valid.cstr
(.Q(Q),
.WEA(WEA),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.out(out),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4
(dout,
clk,
WEA,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[9] ,
din);
output [63:0]dout;
input clk;
input [0:0]WEA;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]Q;
input [9:0]\gc0.count_d1_reg[9] ;
input [63:0]din;
wire [9:0]Q;
wire [0:0]WEA;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [0:0]out;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth inst_blk_mem_gen
(.Q(Q),
.WEA(WEA),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.out(out),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth
(dout,
clk,
WEA,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[9] ,
din);
output [63:0]dout;
input clk;
input [0:0]WEA;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]Q;
input [9:0]\gc0.count_d1_reg[9] ;
input [63:0]din;
wire [9:0]Q;
wire [0:0]WEA;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [0:0]out;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.Q(Q),
.WEA(WEA),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.out(out),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare
(ram_full_comb,
v1_reg,
wr_en,
comp1,
wr_rst_busy,
out,
ram_empty_fb_i_reg);
output ram_full_comb;
input [4:0]v1_reg;
input wr_en;
input comp1;
input wr_rst_busy;
input out;
input [0:0]ram_empty_fb_i_reg;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire comp0;
wire comp1;
wire out;
wire [0:0]ram_empty_fb_i_reg;
wire ram_full_comb;
wire [4:0]v1_reg;
wire wr_en;
wire wr_rst_busy;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp0}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg[4]}));
LUT6 #(
.INIT(64'h0055000000FFC0C0))
ram_full_fb_i_i_1
(.I0(comp0),
.I1(wr_en),
.I2(comp1),
.I3(wr_rst_busy),
.I4(out),
.I5(ram_empty_fb_i_reg),
.O(ram_full_comb));
endmodule
(* ORIG_REF_NAME = "compare" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3
(comp1,
v1_reg_0);
output comp1;
input [4:0]v1_reg_0;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire comp1;
wire [4:0]v1_reg_0;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg_0[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg_0[4]}));
endmodule
(* ORIG_REF_NAME = "compare" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4
(ram_empty_i_reg,
\gcc0.gc0.count_d1_reg[0] ,
\gcc0.gc0.count_d1_reg[2] ,
\gcc0.gc0.count_d1_reg[4] ,
\gcc0.gc0.count_d1_reg[6] ,
\gcc0.gc0.count_d1_reg[8] ,
rd_en,
out,
comp1,
wr_en,
ram_full_fb_i_reg);
output ram_empty_i_reg;
input \gcc0.gc0.count_d1_reg[0] ;
input \gcc0.gc0.count_d1_reg[2] ;
input \gcc0.gc0.count_d1_reg[4] ;
input \gcc0.gc0.count_d1_reg[6] ;
input \gcc0.gc0.count_d1_reg[8] ;
input rd_en;
input out;
input comp1;
input wr_en;
input ram_full_fb_i_reg;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire comp0;
wire comp1;
wire \gcc0.gc0.count_d1_reg[0] ;
wire \gcc0.gc0.count_d1_reg[2] ;
wire \gcc0.gc0.count_d1_reg[4] ;
wire \gcc0.gc0.count_d1_reg[6] ;
wire \gcc0.gc0.count_d1_reg[8] ;
wire out;
wire ram_empty_i_reg;
wire ram_full_fb_i_reg;
wire rd_en;
wire wr_en;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S({\gcc0.gc0.count_d1_reg[6] ,\gcc0.gc0.count_d1_reg[4] ,\gcc0.gc0.count_d1_reg[2] ,\gcc0.gc0.count_d1_reg[0] }));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp0}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],\gcc0.gc0.count_d1_reg[8] }));
LUT6 #(
.INIT(64'hFCF0FCF05050FCF0))
ram_empty_fb_i_i_1
(.I0(comp0),
.I1(rd_en),
.I2(out),
.I3(comp1),
.I4(wr_en),
.I5(ram_full_fb_i_reg),
.O(ram_empty_i_reg));
endmodule
(* ORIG_REF_NAME = "compare" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5
(comp1,
v1_reg);
output comp1;
input [4:0]v1_reg;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire comp1;
wire [4:0]v1_reg;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg[4]}));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo
(wr_rst_busy,
dout,
empty,
full,
rd_en,
wr_en,
clk,
din,
rst);
output wr_rst_busy;
output [63:0]dout;
output empty;
output full;
input rd_en;
input wr_en;
input clk;
input [63:0]din;
input rst;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire \gntv_or_sync_fifo.gl0.rd_n_2 ;
wire \gntv_or_sync_fifo.gl0.wr_n_0 ;
wire \gntv_or_sync_fifo.gl0.wr_n_18 ;
wire \gntv_or_sync_fifo.gl0.wr_n_19 ;
wire \gntv_or_sync_fifo.gl0.wr_n_2 ;
wire \gntv_or_sync_fifo.gl0.wr_n_20 ;
wire \gntv_or_sync_fifo.gl0.wr_n_21 ;
wire \gntv_or_sync_fifo.gl0.wr_n_22 ;
wire [4:0]\grss.rsts/c2/v1_reg ;
wire [9:0]p_0_out;
wire [9:0]p_11_out;
wire p_2_out;
wire rd_en;
wire [9:0]rd_pntr_plus1;
wire [2:0]rd_rst_i;
wire rst;
wire rst_full_ff_i;
wire tmp_ram_rd_en;
wire wr_en;
wire wr_rst_busy;
wire [1:1]wr_rst_i;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic \gntv_or_sync_fifo.gl0.rd
(.AR(rd_rst_i[2]),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (p_0_out),
.E(\gntv_or_sync_fifo.gl0.rd_n_2 ),
.Q(rd_pntr_plus1),
.clk(clk),
.empty(empty),
.\gcc0.gc0.count_d1_reg[0] (\gntv_or_sync_fifo.gl0.wr_n_18 ),
.\gcc0.gc0.count_d1_reg[2] (\gntv_or_sync_fifo.gl0.wr_n_19 ),
.\gcc0.gc0.count_d1_reg[4] (\gntv_or_sync_fifo.gl0.wr_n_20 ),
.\gcc0.gc0.count_d1_reg[6] (\gntv_or_sync_fifo.gl0.wr_n_21 ),
.\gcc0.gc0.count_d1_reg[8] (\gntv_or_sync_fifo.gl0.wr_n_22 ),
.out(p_2_out),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_0 ),
.rd_en(rd_en),
.v1_reg(\grss.rsts/c2/v1_reg ),
.wr_en(wr_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic \gntv_or_sync_fifo.gl0.wr
(.AR(wr_rst_i),
.E(\gntv_or_sync_fifo.gl0.rd_n_2 ),
.Q(p_11_out),
.WEA(\gntv_or_sync_fifo.gl0.wr_n_2 ),
.clk(clk),
.full(full),
.\gc0.count_d1_reg[9] (p_0_out),
.\gc0.count_reg[9] (rd_pntr_plus1),
.\grstd1.grst_full.grst_f.rst_d2_reg (rst_full_ff_i),
.out(\gntv_or_sync_fifo.gl0.wr_n_0 ),
.ram_empty_i_reg(\gntv_or_sync_fifo.gl0.wr_n_18 ),
.ram_empty_i_reg_0(\gntv_or_sync_fifo.gl0.wr_n_19 ),
.ram_empty_i_reg_1(\gntv_or_sync_fifo.gl0.wr_n_20 ),
.ram_empty_i_reg_2(\gntv_or_sync_fifo.gl0.wr_n_21 ),
.ram_empty_i_reg_3(\gntv_or_sync_fifo.gl0.wr_n_22 ),
.v1_reg(\grss.rsts/c2/v1_reg ),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory \gntv_or_sync_fifo.mem
(.Q(p_11_out),
.WEA(\gntv_or_sync_fifo.gl0.wr_n_2 ),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (p_0_out),
.out(rd_rst_i[0]),
.tmp_ram_rd_en(tmp_ram_rd_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo rstblk
(.clk(clk),
.\gc0.count_reg[1] ({rd_rst_i[2],rd_rst_i[0]}),
.\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_ff_i),
.out(wr_rst_i),
.ram_empty_fb_i_reg(p_2_out),
.rd_en(rd_en),
.rst(rst),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_rst_busy(wr_rst_busy));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top
(wr_rst_busy,
dout,
empty,
full,
rd_en,
wr_en,
clk,
din,
rst);
output wr_rst_busy;
output [63:0]dout;
output empty;
output full;
input rd_en;
input wr_en;
input clk;
input [63:0]din;
input rst;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_en;
wire rst;
wire wr_en;
wire wr_rst_busy;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo \grf.rf
(.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.rst(rst),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
(* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "1" *) (* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "10" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "64" *)
(* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "1" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "64" *) (* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "kintex7" *) (* C_FULL_FLAGS_RST_VAL = "1" *) (* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *) (* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "1" *) (* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "0" *) (* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "0" *) (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) (* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *) (* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "1kx36" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *) (* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "1022" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "1021" *) (* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "10" *)
(* C_RD_DEPTH = "1024" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "10" *)
(* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SELECT_XPM = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *) (* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *) (* C_USE_ECC = "0" *) (* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *) (* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "10" *)
(* C_WR_DEPTH = "1024" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "10" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2
(backup,
backup_marker,
clk,
rst,
srst,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
prog_empty_thresh,
prog_empty_thresh_assert,
prog_empty_thresh_negate,
prog_full_thresh,
prog_full_thresh_assert,
prog_full_thresh_negate,
int_clk,
injectdbiterr,
injectsbiterr,
sleep,
dout,
full,
almost_full,
wr_ack,
overflow,
empty,
almost_empty,
valid,
underflow,
data_count,
rd_data_count,
wr_data_count,
prog_full,
prog_empty,
sbiterr,
dbiterr,
wr_rst_busy,
rd_rst_busy,
m_aclk,
s_aclk,
s_aresetn,
m_aclk_en,
s_aclk_en,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awregion,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arregion,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
axi_aw_injectsbiterr,
axi_aw_injectdbiterr,
axi_aw_prog_full_thresh,
axi_aw_prog_empty_thresh,
axi_aw_data_count,
axi_aw_wr_data_count,
axi_aw_rd_data_count,
axi_aw_sbiterr,
axi_aw_dbiterr,
axi_aw_overflow,
axi_aw_underflow,
axi_aw_prog_full,
axi_aw_prog_empty,
axi_w_injectsbiterr,
axi_w_injectdbiterr,
axi_w_prog_full_thresh,
axi_w_prog_empty_thresh,
axi_w_data_count,
axi_w_wr_data_count,
axi_w_rd_data_count,
axi_w_sbiterr,
axi_w_dbiterr,
axi_w_overflow,
axi_w_underflow,
axi_w_prog_full,
axi_w_prog_empty,
axi_b_injectsbiterr,
axi_b_injectdbiterr,
axi_b_prog_full_thresh,
axi_b_prog_empty_thresh,
axi_b_data_count,
axi_b_wr_data_count,
axi_b_rd_data_count,
axi_b_sbiterr,
axi_b_dbiterr,
axi_b_overflow,
axi_b_underflow,
axi_b_prog_full,
axi_b_prog_empty,
axi_ar_injectsbiterr,
axi_ar_injectdbiterr,
axi_ar_prog_full_thresh,
axi_ar_prog_empty_thresh,
axi_ar_data_count,
axi_ar_wr_data_count,
axi_ar_rd_data_count,
axi_ar_sbiterr,
axi_ar_dbiterr,
axi_ar_overflow,
axi_ar_underflow,
axi_ar_prog_full,
axi_ar_prog_empty,
axi_r_injectsbiterr,
axi_r_injectdbiterr,
axi_r_prog_full_thresh,
axi_r_prog_empty_thresh,
axi_r_data_count,
axi_r_wr_data_count,
axi_r_rd_data_count,
axi_r_sbiterr,
axi_r_dbiterr,
axi_r_overflow,
axi_r_underflow,
axi_r_prog_full,
axi_r_prog_empty,
axis_injectsbiterr,
axis_injectdbiterr,
axis_prog_full_thresh,
axis_prog_empty_thresh,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count,
axis_sbiterr,
axis_dbiterr,
axis_overflow,
axis_underflow,
axis_prog_full,
axis_prog_empty);
input backup;
input backup_marker;
input clk;
input rst;
input srst;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [63:0]din;
input wr_en;
input rd_en;
input [9:0]prog_empty_thresh;
input [9:0]prog_empty_thresh_assert;
input [9:0]prog_empty_thresh_negate;
input [9:0]prog_full_thresh;
input [9:0]prog_full_thresh_assert;
input [9:0]prog_full_thresh_negate;
input int_clk;
input injectdbiterr;
input injectsbiterr;
input sleep;
output [63:0]dout;
output full;
output almost_full;
output wr_ack;
output overflow;
output empty;
output almost_empty;
output valid;
output underflow;
output [9:0]data_count;
output [9:0]rd_data_count;
output [9:0]wr_data_count;
output prog_full;
output prog_empty;
output sbiterr;
output dbiterr;
output wr_rst_busy;
output rd_rst_busy;
input m_aclk;
input s_aclk;
input s_aresetn;
input m_aclk_en;
input s_aclk_en;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [3:0]s_axi_awregion;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [63:0]s_axi_wdata;
input [7:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
output [0:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output [3:0]m_axi_awregion;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [3:0]s_axi_arregion;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [63:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [0:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output [3:0]m_axi_arregion;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input [0:0]s_axis_tstrb;
input [0:0]s_axis_tkeep;
input s_axis_tlast;
input [0:0]s_axis_tid;
input [0:0]s_axis_tdest;
input [3:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output [0:0]m_axis_tstrb;
output [0:0]m_axis_tkeep;
output m_axis_tlast;
output [0:0]m_axis_tid;
output [0:0]m_axis_tdest;
output [3:0]m_axis_tuser;
input axi_aw_injectsbiterr;
input axi_aw_injectdbiterr;
input [3:0]axi_aw_prog_full_thresh;
input [3:0]axi_aw_prog_empty_thresh;
output [4:0]axi_aw_data_count;
output [4:0]axi_aw_wr_data_count;
output [4:0]axi_aw_rd_data_count;
output axi_aw_sbiterr;
output axi_aw_dbiterr;
output axi_aw_overflow;
output axi_aw_underflow;
output axi_aw_prog_full;
output axi_aw_prog_empty;
input axi_w_injectsbiterr;
input axi_w_injectdbiterr;
input [9:0]axi_w_prog_full_thresh;
input [9:0]axi_w_prog_empty_thresh;
output [10:0]axi_w_data_count;
output [10:0]axi_w_wr_data_count;
output [10:0]axi_w_rd_data_count;
output axi_w_sbiterr;
output axi_w_dbiterr;
output axi_w_overflow;
output axi_w_underflow;
output axi_w_prog_full;
output axi_w_prog_empty;
input axi_b_injectsbiterr;
input axi_b_injectdbiterr;
input [3:0]axi_b_prog_full_thresh;
input [3:0]axi_b_prog_empty_thresh;
output [4:0]axi_b_data_count;
output [4:0]axi_b_wr_data_count;
output [4:0]axi_b_rd_data_count;
output axi_b_sbiterr;
output axi_b_dbiterr;
output axi_b_overflow;
output axi_b_underflow;
output axi_b_prog_full;
output axi_b_prog_empty;
input axi_ar_injectsbiterr;
input axi_ar_injectdbiterr;
input [3:0]axi_ar_prog_full_thresh;
input [3:0]axi_ar_prog_empty_thresh;
output [4:0]axi_ar_data_count;
output [4:0]axi_ar_wr_data_count;
output [4:0]axi_ar_rd_data_count;
output axi_ar_sbiterr;
output axi_ar_dbiterr;
output axi_ar_overflow;
output axi_ar_underflow;
output axi_ar_prog_full;
output axi_ar_prog_empty;
input axi_r_injectsbiterr;
input axi_r_injectdbiterr;
input [9:0]axi_r_prog_full_thresh;
input [9:0]axi_r_prog_empty_thresh;
output [10:0]axi_r_data_count;
output [10:0]axi_r_wr_data_count;
output [10:0]axi_r_rd_data_count;
output axi_r_sbiterr;
output axi_r_dbiterr;
output axi_r_overflow;
output axi_r_underflow;
output axi_r_prog_full;
output axi_r_prog_empty;
input axis_injectsbiterr;
input axis_injectdbiterr;
input [9:0]axis_prog_full_thresh;
input [9:0]axis_prog_empty_thresh;
output [10:0]axis_data_count;
output [10:0]axis_wr_data_count;
output [10:0]axis_rd_data_count;
output axis_sbiterr;
output axis_dbiterr;
output axis_overflow;
output axis_underflow;
output axis_prog_full;
output axis_prog_empty;
wire \<const0> ;
wire \<const1> ;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_en;
wire rst;
wire wr_en;
wire wr_rst_busy;
assign almost_empty = \<const0> ;
assign almost_full = \<const0> ;
assign axi_ar_data_count[4] = \<const0> ;
assign axi_ar_data_count[3] = \<const0> ;
assign axi_ar_data_count[2] = \<const0> ;
assign axi_ar_data_count[1] = \<const0> ;
assign axi_ar_data_count[0] = \<const0> ;
assign axi_ar_dbiterr = \<const0> ;
assign axi_ar_overflow = \<const0> ;
assign axi_ar_prog_empty = \<const1> ;
assign axi_ar_prog_full = \<const0> ;
assign axi_ar_rd_data_count[4] = \<const0> ;
assign axi_ar_rd_data_count[3] = \<const0> ;
assign axi_ar_rd_data_count[2] = \<const0> ;
assign axi_ar_rd_data_count[1] = \<const0> ;
assign axi_ar_rd_data_count[0] = \<const0> ;
assign axi_ar_sbiterr = \<const0> ;
assign axi_ar_underflow = \<const0> ;
assign axi_ar_wr_data_count[4] = \<const0> ;
assign axi_ar_wr_data_count[3] = \<const0> ;
assign axi_ar_wr_data_count[2] = \<const0> ;
assign axi_ar_wr_data_count[1] = \<const0> ;
assign axi_ar_wr_data_count[0] = \<const0> ;
assign axi_aw_data_count[4] = \<const0> ;
assign axi_aw_data_count[3] = \<const0> ;
assign axi_aw_data_count[2] = \<const0> ;
assign axi_aw_data_count[1] = \<const0> ;
assign axi_aw_data_count[0] = \<const0> ;
assign axi_aw_dbiterr = \<const0> ;
assign axi_aw_overflow = \<const0> ;
assign axi_aw_prog_empty = \<const1> ;
assign axi_aw_prog_full = \<const0> ;
assign axi_aw_rd_data_count[4] = \<const0> ;
assign axi_aw_rd_data_count[3] = \<const0> ;
assign axi_aw_rd_data_count[2] = \<const0> ;
assign axi_aw_rd_data_count[1] = \<const0> ;
assign axi_aw_rd_data_count[0] = \<const0> ;
assign axi_aw_sbiterr = \<const0> ;
assign axi_aw_underflow = \<const0> ;
assign axi_aw_wr_data_count[4] = \<const0> ;
assign axi_aw_wr_data_count[3] = \<const0> ;
assign axi_aw_wr_data_count[2] = \<const0> ;
assign axi_aw_wr_data_count[1] = \<const0> ;
assign axi_aw_wr_data_count[0] = \<const0> ;
assign axi_b_data_count[4] = \<const0> ;
assign axi_b_data_count[3] = \<const0> ;
assign axi_b_data_count[2] = \<const0> ;
assign axi_b_data_count[1] = \<const0> ;
assign axi_b_data_count[0] = \<const0> ;
assign axi_b_dbiterr = \<const0> ;
assign axi_b_overflow = \<const0> ;
assign axi_b_prog_empty = \<const1> ;
assign axi_b_prog_full = \<const0> ;
assign axi_b_rd_data_count[4] = \<const0> ;
assign axi_b_rd_data_count[3] = \<const0> ;
assign axi_b_rd_data_count[2] = \<const0> ;
assign axi_b_rd_data_count[1] = \<const0> ;
assign axi_b_rd_data_count[0] = \<const0> ;
assign axi_b_sbiterr = \<const0> ;
assign axi_b_underflow = \<const0> ;
assign axi_b_wr_data_count[4] = \<const0> ;
assign axi_b_wr_data_count[3] = \<const0> ;
assign axi_b_wr_data_count[2] = \<const0> ;
assign axi_b_wr_data_count[1] = \<const0> ;
assign axi_b_wr_data_count[0] = \<const0> ;
assign axi_r_data_count[10] = \<const0> ;
assign axi_r_data_count[9] = \<const0> ;
assign axi_r_data_count[8] = \<const0> ;
assign axi_r_data_count[7] = \<const0> ;
assign axi_r_data_count[6] = \<const0> ;
assign axi_r_data_count[5] = \<const0> ;
assign axi_r_data_count[4] = \<const0> ;
assign axi_r_data_count[3] = \<const0> ;
assign axi_r_data_count[2] = \<const0> ;
assign axi_r_data_count[1] = \<const0> ;
assign axi_r_data_count[0] = \<const0> ;
assign axi_r_dbiterr = \<const0> ;
assign axi_r_overflow = \<const0> ;
assign axi_r_prog_empty = \<const1> ;
assign axi_r_prog_full = \<const0> ;
assign axi_r_rd_data_count[10] = \<const0> ;
assign axi_r_rd_data_count[9] = \<const0> ;
assign axi_r_rd_data_count[8] = \<const0> ;
assign axi_r_rd_data_count[7] = \<const0> ;
assign axi_r_rd_data_count[6] = \<const0> ;
assign axi_r_rd_data_count[5] = \<const0> ;
assign axi_r_rd_data_count[4] = \<const0> ;
assign axi_r_rd_data_count[3] = \<const0> ;
assign axi_r_rd_data_count[2] = \<const0> ;
assign axi_r_rd_data_count[1] = \<const0> ;
assign axi_r_rd_data_count[0] = \<const0> ;
assign axi_r_sbiterr = \<const0> ;
assign axi_r_underflow = \<const0> ;
assign axi_r_wr_data_count[10] = \<const0> ;
assign axi_r_wr_data_count[9] = \<const0> ;
assign axi_r_wr_data_count[8] = \<const0> ;
assign axi_r_wr_data_count[7] = \<const0> ;
assign axi_r_wr_data_count[6] = \<const0> ;
assign axi_r_wr_data_count[5] = \<const0> ;
assign axi_r_wr_data_count[4] = \<const0> ;
assign axi_r_wr_data_count[3] = \<const0> ;
assign axi_r_wr_data_count[2] = \<const0> ;
assign axi_r_wr_data_count[1] = \<const0> ;
assign axi_r_wr_data_count[0] = \<const0> ;
assign axi_w_data_count[10] = \<const0> ;
assign axi_w_data_count[9] = \<const0> ;
assign axi_w_data_count[8] = \<const0> ;
assign axi_w_data_count[7] = \<const0> ;
assign axi_w_data_count[6] = \<const0> ;
assign axi_w_data_count[5] = \<const0> ;
assign axi_w_data_count[4] = \<const0> ;
assign axi_w_data_count[3] = \<const0> ;
assign axi_w_data_count[2] = \<const0> ;
assign axi_w_data_count[1] = \<const0> ;
assign axi_w_data_count[0] = \<const0> ;
assign axi_w_dbiterr = \<const0> ;
assign axi_w_overflow = \<const0> ;
assign axi_w_prog_empty = \<const1> ;
assign axi_w_prog_full = \<const0> ;
assign axi_w_rd_data_count[10] = \<const0> ;
assign axi_w_rd_data_count[9] = \<const0> ;
assign axi_w_rd_data_count[8] = \<const0> ;
assign axi_w_rd_data_count[7] = \<const0> ;
assign axi_w_rd_data_count[6] = \<const0> ;
assign axi_w_rd_data_count[5] = \<const0> ;
assign axi_w_rd_data_count[4] = \<const0> ;
assign axi_w_rd_data_count[3] = \<const0> ;
assign axi_w_rd_data_count[2] = \<const0> ;
assign axi_w_rd_data_count[1] = \<const0> ;
assign axi_w_rd_data_count[0] = \<const0> ;
assign axi_w_sbiterr = \<const0> ;
assign axi_w_underflow = \<const0> ;
assign axi_w_wr_data_count[10] = \<const0> ;
assign axi_w_wr_data_count[9] = \<const0> ;
assign axi_w_wr_data_count[8] = \<const0> ;
assign axi_w_wr_data_count[7] = \<const0> ;
assign axi_w_wr_data_count[6] = \<const0> ;
assign axi_w_wr_data_count[5] = \<const0> ;
assign axi_w_wr_data_count[4] = \<const0> ;
assign axi_w_wr_data_count[3] = \<const0> ;
assign axi_w_wr_data_count[2] = \<const0> ;
assign axi_w_wr_data_count[1] = \<const0> ;
assign axi_w_wr_data_count[0] = \<const0> ;
assign axis_data_count[10] = \<const0> ;
assign axis_data_count[9] = \<const0> ;
assign axis_data_count[8] = \<const0> ;
assign axis_data_count[7] = \<const0> ;
assign axis_data_count[6] = \<const0> ;
assign axis_data_count[5] = \<const0> ;
assign axis_data_count[4] = \<const0> ;
assign axis_data_count[3] = \<const0> ;
assign axis_data_count[2] = \<const0> ;
assign axis_data_count[1] = \<const0> ;
assign axis_data_count[0] = \<const0> ;
assign axis_dbiterr = \<const0> ;
assign axis_overflow = \<const0> ;
assign axis_prog_empty = \<const1> ;
assign axis_prog_full = \<const0> ;
assign axis_rd_data_count[10] = \<const0> ;
assign axis_rd_data_count[9] = \<const0> ;
assign axis_rd_data_count[8] = \<const0> ;
assign axis_rd_data_count[7] = \<const0> ;
assign axis_rd_data_count[6] = \<const0> ;
assign axis_rd_data_count[5] = \<const0> ;
assign axis_rd_data_count[4] = \<const0> ;
assign axis_rd_data_count[3] = \<const0> ;
assign axis_rd_data_count[2] = \<const0> ;
assign axis_rd_data_count[1] = \<const0> ;
assign axis_rd_data_count[0] = \<const0> ;
assign axis_sbiterr = \<const0> ;
assign axis_underflow = \<const0> ;
assign axis_wr_data_count[10] = \<const0> ;
assign axis_wr_data_count[9] = \<const0> ;
assign axis_wr_data_count[8] = \<const0> ;
assign axis_wr_data_count[7] = \<const0> ;
assign axis_wr_data_count[6] = \<const0> ;
assign axis_wr_data_count[5] = \<const0> ;
assign axis_wr_data_count[4] = \<const0> ;
assign axis_wr_data_count[3] = \<const0> ;
assign axis_wr_data_count[2] = \<const0> ;
assign axis_wr_data_count[1] = \<const0> ;
assign axis_wr_data_count[0] = \<const0> ;
assign data_count[9] = \<const0> ;
assign data_count[8] = \<const0> ;
assign data_count[7] = \<const0> ;
assign data_count[6] = \<const0> ;
assign data_count[5] = \<const0> ;
assign data_count[4] = \<const0> ;
assign data_count[3] = \<const0> ;
assign data_count[2] = \<const0> ;
assign data_count[1] = \<const0> ;
assign data_count[0] = \<const0> ;
assign dbiterr = \<const0> ;
assign m_axi_araddr[31] = \<const0> ;
assign m_axi_araddr[30] = \<const0> ;
assign m_axi_araddr[29] = \<const0> ;
assign m_axi_araddr[28] = \<const0> ;
assign m_axi_araddr[27] = \<const0> ;
assign m_axi_araddr[26] = \<const0> ;
assign m_axi_araddr[25] = \<const0> ;
assign m_axi_araddr[24] = \<const0> ;
assign m_axi_araddr[23] = \<const0> ;
assign m_axi_araddr[22] = \<const0> ;
assign m_axi_araddr[21] = \<const0> ;
assign m_axi_araddr[20] = \<const0> ;
assign m_axi_araddr[19] = \<const0> ;
assign m_axi_araddr[18] = \<const0> ;
assign m_axi_araddr[17] = \<const0> ;
assign m_axi_araddr[16] = \<const0> ;
assign m_axi_araddr[15] = \<const0> ;
assign m_axi_araddr[14] = \<const0> ;
assign m_axi_araddr[13] = \<const0> ;
assign m_axi_araddr[12] = \<const0> ;
assign m_axi_araddr[11] = \<const0> ;
assign m_axi_araddr[10] = \<const0> ;
assign m_axi_araddr[9] = \<const0> ;
assign m_axi_araddr[8] = \<const0> ;
assign m_axi_araddr[7] = \<const0> ;
assign m_axi_araddr[6] = \<const0> ;
assign m_axi_araddr[5] = \<const0> ;
assign m_axi_araddr[4] = \<const0> ;
assign m_axi_araddr[3] = \<const0> ;
assign m_axi_araddr[2] = \<const0> ;
assign m_axi_araddr[1] = \<const0> ;
assign m_axi_araddr[0] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arprot[2] = \<const0> ;
assign m_axi_arprot[1] = \<const0> ;
assign m_axi_arprot[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_arvalid = \<const0> ;
assign m_axi_awaddr[31] = \<const0> ;
assign m_axi_awaddr[30] = \<const0> ;
assign m_axi_awaddr[29] = \<const0> ;
assign m_axi_awaddr[28] = \<const0> ;
assign m_axi_awaddr[27] = \<const0> ;
assign m_axi_awaddr[26] = \<const0> ;
assign m_axi_awaddr[25] = \<const0> ;
assign m_axi_awaddr[24] = \<const0> ;
assign m_axi_awaddr[23] = \<const0> ;
assign m_axi_awaddr[22] = \<const0> ;
assign m_axi_awaddr[21] = \<const0> ;
assign m_axi_awaddr[20] = \<const0> ;
assign m_axi_awaddr[19] = \<const0> ;
assign m_axi_awaddr[18] = \<const0> ;
assign m_axi_awaddr[17] = \<const0> ;
assign m_axi_awaddr[16] = \<const0> ;
assign m_axi_awaddr[15] = \<const0> ;
assign m_axi_awaddr[14] = \<const0> ;
assign m_axi_awaddr[13] = \<const0> ;
assign m_axi_awaddr[12] = \<const0> ;
assign m_axi_awaddr[11] = \<const0> ;
assign m_axi_awaddr[10] = \<const0> ;
assign m_axi_awaddr[9] = \<const0> ;
assign m_axi_awaddr[8] = \<const0> ;
assign m_axi_awaddr[7] = \<const0> ;
assign m_axi_awaddr[6] = \<const0> ;
assign m_axi_awaddr[5] = \<const0> ;
assign m_axi_awaddr[4] = \<const0> ;
assign m_axi_awaddr[3] = \<const0> ;
assign m_axi_awaddr[2] = \<const0> ;
assign m_axi_awaddr[1] = \<const0> ;
assign m_axi_awaddr[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[2] = \<const0> ;
assign m_axi_awprot[1] = \<const0> ;
assign m_axi_awprot[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_awvalid = \<const0> ;
assign m_axi_bready = \<const0> ;
assign m_axi_rready = \<const0> ;
assign m_axi_wdata[63] = \<const0> ;
assign m_axi_wdata[62] = \<const0> ;
assign m_axi_wdata[61] = \<const0> ;
assign m_axi_wdata[60] = \<const0> ;
assign m_axi_wdata[59] = \<const0> ;
assign m_axi_wdata[58] = \<const0> ;
assign m_axi_wdata[57] = \<const0> ;
assign m_axi_wdata[56] = \<const0> ;
assign m_axi_wdata[55] = \<const0> ;
assign m_axi_wdata[54] = \<const0> ;
assign m_axi_wdata[53] = \<const0> ;
assign m_axi_wdata[52] = \<const0> ;
assign m_axi_wdata[51] = \<const0> ;
assign m_axi_wdata[50] = \<const0> ;
assign m_axi_wdata[49] = \<const0> ;
assign m_axi_wdata[48] = \<const0> ;
assign m_axi_wdata[47] = \<const0> ;
assign m_axi_wdata[46] = \<const0> ;
assign m_axi_wdata[45] = \<const0> ;
assign m_axi_wdata[44] = \<const0> ;
assign m_axi_wdata[43] = \<const0> ;
assign m_axi_wdata[42] = \<const0> ;
assign m_axi_wdata[41] = \<const0> ;
assign m_axi_wdata[40] = \<const0> ;
assign m_axi_wdata[39] = \<const0> ;
assign m_axi_wdata[38] = \<const0> ;
assign m_axi_wdata[37] = \<const0> ;
assign m_axi_wdata[36] = \<const0> ;
assign m_axi_wdata[35] = \<const0> ;
assign m_axi_wdata[34] = \<const0> ;
assign m_axi_wdata[33] = \<const0> ;
assign m_axi_wdata[32] = \<const0> ;
assign m_axi_wdata[31] = \<const0> ;
assign m_axi_wdata[30] = \<const0> ;
assign m_axi_wdata[29] = \<const0> ;
assign m_axi_wdata[28] = \<const0> ;
assign m_axi_wdata[27] = \<const0> ;
assign m_axi_wdata[26] = \<const0> ;
assign m_axi_wdata[25] = \<const0> ;
assign m_axi_wdata[24] = \<const0> ;
assign m_axi_wdata[23] = \<const0> ;
assign m_axi_wdata[22] = \<const0> ;
assign m_axi_wdata[21] = \<const0> ;
assign m_axi_wdata[20] = \<const0> ;
assign m_axi_wdata[19] = \<const0> ;
assign m_axi_wdata[18] = \<const0> ;
assign m_axi_wdata[17] = \<const0> ;
assign m_axi_wdata[16] = \<const0> ;
assign m_axi_wdata[15] = \<const0> ;
assign m_axi_wdata[14] = \<const0> ;
assign m_axi_wdata[13] = \<const0> ;
assign m_axi_wdata[12] = \<const0> ;
assign m_axi_wdata[11] = \<const0> ;
assign m_axi_wdata[10] = \<const0> ;
assign m_axi_wdata[9] = \<const0> ;
assign m_axi_wdata[8] = \<const0> ;
assign m_axi_wdata[7] = \<const0> ;
assign m_axi_wdata[6] = \<const0> ;
assign m_axi_wdata[5] = \<const0> ;
assign m_axi_wdata[4] = \<const0> ;
assign m_axi_wdata[3] = \<const0> ;
assign m_axi_wdata[2] = \<const0> ;
assign m_axi_wdata[1] = \<const0> ;
assign m_axi_wdata[0] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const0> ;
assign m_axi_wstrb[7] = \<const0> ;
assign m_axi_wstrb[6] = \<const0> ;
assign m_axi_wstrb[5] = \<const0> ;
assign m_axi_wstrb[4] = \<const0> ;
assign m_axi_wstrb[3] = \<const0> ;
assign m_axi_wstrb[2] = \<const0> ;
assign m_axi_wstrb[1] = \<const0> ;
assign m_axi_wstrb[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = \<const0> ;
assign m_axis_tdata[7] = \<const0> ;
assign m_axis_tdata[6] = \<const0> ;
assign m_axis_tdata[5] = \<const0> ;
assign m_axis_tdata[4] = \<const0> ;
assign m_axis_tdata[3] = \<const0> ;
assign m_axis_tdata[2] = \<const0> ;
assign m_axis_tdata[1] = \<const0> ;
assign m_axis_tdata[0] = \<const0> ;
assign m_axis_tdest[0] = \<const0> ;
assign m_axis_tid[0] = \<const0> ;
assign m_axis_tkeep[0] = \<const0> ;
assign m_axis_tlast = \<const0> ;
assign m_axis_tstrb[0] = \<const0> ;
assign m_axis_tuser[3] = \<const0> ;
assign m_axis_tuser[2] = \<const0> ;
assign m_axis_tuser[1] = \<const0> ;
assign m_axis_tuser[0] = \<const0> ;
assign m_axis_tvalid = \<const0> ;
assign overflow = \<const0> ;
assign prog_empty = \<const0> ;
assign prog_full = \<const0> ;
assign rd_data_count[9] = \<const0> ;
assign rd_data_count[8] = \<const0> ;
assign rd_data_count[7] = \<const0> ;
assign rd_data_count[6] = \<const0> ;
assign rd_data_count[5] = \<const0> ;
assign rd_data_count[4] = \<const0> ;
assign rd_data_count[3] = \<const0> ;
assign rd_data_count[2] = \<const0> ;
assign rd_data_count[1] = \<const0> ;
assign rd_data_count[0] = \<const0> ;
assign rd_rst_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_rdata[63] = \<const0> ;
assign s_axi_rdata[62] = \<const0> ;
assign s_axi_rdata[61] = \<const0> ;
assign s_axi_rdata[60] = \<const0> ;
assign s_axi_rdata[59] = \<const0> ;
assign s_axi_rdata[58] = \<const0> ;
assign s_axi_rdata[57] = \<const0> ;
assign s_axi_rdata[56] = \<const0> ;
assign s_axi_rdata[55] = \<const0> ;
assign s_axi_rdata[54] = \<const0> ;
assign s_axi_rdata[53] = \<const0> ;
assign s_axi_rdata[52] = \<const0> ;
assign s_axi_rdata[51] = \<const0> ;
assign s_axi_rdata[50] = \<const0> ;
assign s_axi_rdata[49] = \<const0> ;
assign s_axi_rdata[48] = \<const0> ;
assign s_axi_rdata[47] = \<const0> ;
assign s_axi_rdata[46] = \<const0> ;
assign s_axi_rdata[45] = \<const0> ;
assign s_axi_rdata[44] = \<const0> ;
assign s_axi_rdata[43] = \<const0> ;
assign s_axi_rdata[42] = \<const0> ;
assign s_axi_rdata[41] = \<const0> ;
assign s_axi_rdata[40] = \<const0> ;
assign s_axi_rdata[39] = \<const0> ;
assign s_axi_rdata[38] = \<const0> ;
assign s_axi_rdata[37] = \<const0> ;
assign s_axi_rdata[36] = \<const0> ;
assign s_axi_rdata[35] = \<const0> ;
assign s_axi_rdata[34] = \<const0> ;
assign s_axi_rdata[33] = \<const0> ;
assign s_axi_rdata[32] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_wready = \<const0> ;
assign s_axis_tready = \<const0> ;
assign sbiterr = \<const0> ;
assign underflow = \<const0> ;
assign valid = \<const0> ;
assign wr_ack = \<const0> ;
assign wr_data_count[9] = \<const0> ;
assign wr_data_count[8] = \<const0> ;
assign wr_data_count[7] = \<const0> ;
assign wr_data_count[6] = \<const0> ;
assign wr_data_count[5] = \<const0> ;
assign wr_data_count[4] = \<const0> ;
assign wr_data_count[3] = \<const0> ;
assign wr_data_count[2] = \<const0> ;
assign wr_data_count[1] = \<const0> ;
assign wr_data_count[0] = \<const0> ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth inst_fifo_gen
(.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.rst(rst),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth
(wr_rst_busy,
dout,
empty,
full,
rd_en,
wr_en,
clk,
din,
rst);
output wr_rst_busy;
output [63:0]dout;
output empty;
output full;
input rd_en;
input wr_en;
input clk;
input [63:0]din;
input rst;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_en;
wire rst;
wire wr_en;
wire wr_rst_busy;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top \gconvfifo.rf
(.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.rst(rst),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory
(dout,
clk,
WEA,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[9] ,
din);
output [63:0]dout;
input clk;
input [0:0]WEA;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]Q;
input [9:0]\gc0.count_d1_reg[9] ;
input [63:0]din;
wire [9:0]Q;
wire [0:0]WEA;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [0:0]out;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 \gbm.gbmg.gbmga.ngecc.bmg
(.Q(Q),
.WEA(WEA),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.out(out),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr
(Q,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
E,
clk,
AR);
output [9:0]Q;
output [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
input [0:0]E;
input clk;
input [0:0]AR;
wire [0:0]AR;
wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire [0:0]E;
wire [9:0]Q;
wire clk;
wire \gc0.count[9]_i_2_n_0 ;
wire [9:0]plusOp;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1
(.I0(Q[0]),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[2]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(plusOp[2]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[3]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(plusOp[3]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gc0.count[4]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(plusOp[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\gc0.count[5]_i_1
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[4]),
.I5(Q[5]),
.O(plusOp[5]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\gc0.count[6]_i_1
(.I0(\gc0.count[9]_i_2_n_0 ),
.I1(Q[6]),
.O(plusOp[6]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[7]_i_1
(.I0(\gc0.count[9]_i_2_n_0 ),
.I1(Q[6]),
.I2(Q[7]),
.O(plusOp[7]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[8]_i_1
(.I0(Q[6]),
.I1(\gc0.count[9]_i_2_n_0 ),
.I2(Q[7]),
.I3(Q[8]),
.O(plusOp[8]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gc0.count[9]_i_1
(.I0(Q[7]),
.I1(\gc0.count[9]_i_2_n_0 ),
.I2(Q[6]),
.I3(Q[8]),
.I4(Q[9]),
.O(plusOp[9]));
LUT6 #(
.INIT(64'h8000000000000000))
\gc0.count[9]_i_2
(.I0(Q[5]),
.I1(Q[3]),
.I2(Q[1]),
.I3(Q[0]),
.I4(Q[2]),
.I5(Q[4]),
.O(\gc0.count[9]_i_2_n_0 ));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(clk),
.CE(E),
.CLR(AR),
.D(Q[0]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(clk),
.CE(E),
.CLR(AR),
.D(Q[1]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(clk),
.CE(E),
.CLR(AR),
.D(Q[2]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(clk),
.CE(E),
.CLR(AR),
.D(Q[3]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[4]
(.C(clk),
.CE(E),
.CLR(AR),
.D(Q[4]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[5]
(.C(clk),
.CE(E),
.CLR(AR),
.D(Q[5]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[6]
(.C(clk),
.CE(E),
.CLR(AR),
.D(Q[6]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[7]
(.C(clk),
.CE(E),
.CLR(AR),
.D(Q[7]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[8]
(.C(clk),
.CE(E),
.CLR(AR),
.D(Q[8]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[9]
(.C(clk),
.CE(E),
.CLR(AR),
.D(Q[9]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [9]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(clk),
.CE(E),
.D(plusOp[0]),
.PRE(AR),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[4]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[5]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[6]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[7]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[8]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[9]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp[9]),
.Q(Q[9]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic
(out,
empty,
E,
Q,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
\gcc0.gc0.count_d1_reg[0] ,
\gcc0.gc0.count_d1_reg[2] ,
\gcc0.gc0.count_d1_reg[4] ,
\gcc0.gc0.count_d1_reg[6] ,
\gcc0.gc0.count_d1_reg[8] ,
v1_reg,
clk,
AR,
rd_en,
wr_en,
ram_full_fb_i_reg);
output out;
output empty;
output [0:0]E;
output [9:0]Q;
output [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
input \gcc0.gc0.count_d1_reg[0] ;
input \gcc0.gc0.count_d1_reg[2] ;
input \gcc0.gc0.count_d1_reg[4] ;
input \gcc0.gc0.count_d1_reg[6] ;
input \gcc0.gc0.count_d1_reg[8] ;
input [4:0]v1_reg;
input clk;
input [0:0]AR;
input rd_en;
input wr_en;
input ram_full_fb_i_reg;
wire [0:0]AR;
wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire [0:0]E;
wire [9:0]Q;
wire clk;
wire empty;
wire \gcc0.gc0.count_d1_reg[0] ;
wire \gcc0.gc0.count_d1_reg[2] ;
wire \gcc0.gc0.count_d1_reg[4] ;
wire \gcc0.gc0.count_d1_reg[6] ;
wire \gcc0.gc0.count_d1_reg[8] ;
wire out;
wire ram_full_fb_i_reg;
wire rd_en;
wire [4:0]v1_reg;
wire wr_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss \grss.rsts
(.AR(AR),
.E(E),
.clk(clk),
.empty(empty),
.\gcc0.gc0.count_d1_reg[0] (\gcc0.gc0.count_d1_reg[0] ),
.\gcc0.gc0.count_d1_reg[2] (\gcc0.gc0.count_d1_reg[2] ),
.\gcc0.gc0.count_d1_reg[4] (\gcc0.gc0.count_d1_reg[4] ),
.\gcc0.gc0.count_d1_reg[6] (\gcc0.gc0.count_d1_reg[6] ),
.\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.rd_en(rd_en),
.v1_reg(v1_reg),
.wr_en(wr_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr rpntr
(.AR(AR),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ),
.E(E),
.Q(Q),
.clk(clk));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss
(out,
empty,
E,
\gcc0.gc0.count_d1_reg[0] ,
\gcc0.gc0.count_d1_reg[2] ,
\gcc0.gc0.count_d1_reg[4] ,
\gcc0.gc0.count_d1_reg[6] ,
\gcc0.gc0.count_d1_reg[8] ,
v1_reg,
clk,
AR,
rd_en,
wr_en,
ram_full_fb_i_reg);
output out;
output empty;
output [0:0]E;
input \gcc0.gc0.count_d1_reg[0] ;
input \gcc0.gc0.count_d1_reg[2] ;
input \gcc0.gc0.count_d1_reg[4] ;
input \gcc0.gc0.count_d1_reg[6] ;
input \gcc0.gc0.count_d1_reg[8] ;
input [4:0]v1_reg;
input clk;
input [0:0]AR;
input rd_en;
input wr_en;
input ram_full_fb_i_reg;
wire [0:0]AR;
wire [0:0]E;
wire c1_n_0;
wire clk;
wire comp1;
wire \gcc0.gc0.count_d1_reg[0] ;
wire \gcc0.gc0.count_d1_reg[2] ;
wire \gcc0.gc0.count_d1_reg[4] ;
wire \gcc0.gc0.count_d1_reg[6] ;
wire \gcc0.gc0.count_d1_reg[8] ;
(* DONT_TOUCH *) wire ram_empty_fb_i;
(* DONT_TOUCH *) wire ram_empty_i;
wire ram_full_fb_i_reg;
wire rd_en;
wire [4:0]v1_reg;
wire wr_en;
assign empty = ram_empty_i;
assign out = ram_empty_fb_i;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 c1
(.comp1(comp1),
.\gcc0.gc0.count_d1_reg[0] (\gcc0.gc0.count_d1_reg[0] ),
.\gcc0.gc0.count_d1_reg[2] (\gcc0.gc0.count_d1_reg[2] ),
.\gcc0.gc0.count_d1_reg[4] (\gcc0.gc0.count_d1_reg[4] ),
.\gcc0.gc0.count_d1_reg[6] (\gcc0.gc0.count_d1_reg[6] ),
.\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ),
.out(ram_empty_fb_i),
.ram_empty_i_reg(c1_n_0),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.rd_en(rd_en),
.wr_en(wr_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 c2
(.comp1(comp1),
.v1_reg(v1_reg));
LUT2 #(
.INIT(4'h2))
\gc0.count_d1[9]_i_1
(.I0(rd_en),
.I1(ram_empty_fb_i),
.O(E));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(clk),
.CE(1'b1),
.D(c1_n_0),
.PRE(AR),
.Q(ram_empty_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(clk),
.CE(1'b1),
.D(c1_n_0),
.PRE(AR),
.Q(ram_empty_i));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo
(out,
\gc0.count_reg[1] ,
\grstd1.grst_full.grst_f.rst_d3_reg_0 ,
wr_rst_busy,
tmp_ram_rd_en,
clk,
rst,
ram_empty_fb_i_reg,
rd_en);
output [0:0]out;
output [1:0]\gc0.count_reg[1] ;
output \grstd1.grst_full.grst_f.rst_d3_reg_0 ;
output wr_rst_busy;
output tmp_ram_rd_en;
input clk;
input rst;
input ram_empty_fb_i_reg;
input rd_en;
wire clk;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ;
wire p_7_out;
wire p_8_out;
wire ram_empty_fb_i_reg;
wire rd_en;
wire rd_rst_asreg;
(* DONT_TOUCH *) wire [2:0]rd_rst_reg;
wire rst;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire tmp_ram_rd_en;
wire wr_rst_asreg;
(* DONT_TOUCH *) wire [2:0]wr_rst_reg;
assign \gc0.count_reg[1] [1] = rd_rst_reg[2];
assign \gc0.count_reg[1] [0] = rd_rst_reg[0];
assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2;
assign out[0] = wr_rst_reg[1];
assign wr_rst_busy = rst_d3;
LUT3 #(
.INIT(8'hBA))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2
(.I0(rd_rst_reg[0]),
.I1(ram_empty_fb_i_reg),
.I2(rd_en),
.O(tmp_ram_rd_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst_wr_reg2),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(clk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst_wr_reg2),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(clk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst_wr_reg2),
.Q(rst_d3));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst
(.clk(clk),
.in0(rd_rst_asreg),
.\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg (\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ),
.out(p_7_out));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst
(.clk(clk),
.in0(wr_rst_asreg),
.\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg (\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ),
.out(p_8_out));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.clk(clk),
.in0(rd_rst_asreg),
.out(p_7_out));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.clk(clk),
.in0(wr_rst_asreg),
.out(p_8_out));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ),
.PRE(rst_rd_reg2),
.Q(rd_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(clk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(rst),
.Q(rst_rd_reg2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(clk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(rst),
.Q(rst_wr_reg2));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ),
.PRE(rst_wr_reg2),
.Q(wr_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[2]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff
(out,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ,
in0,
clk);
output out;
output \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ;
input [0:0]in0;
input clk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire clk;
wire [0:0]in0;
wire \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1
(.I0(in0),
.I1(Q_reg),
.O(\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0
(out,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ,
in0,
clk);
output out;
output \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ;
input [0:0]in0;
input clk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire clk;
wire [0:0]in0;
wire \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1
(.I0(in0),
.I1(Q_reg),
.O(\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1
(AS,
out,
clk,
in0);
output [0:0]AS;
input out;
input clk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire clk;
wire [0:0]in0;
wire out;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2
(AS,
out,
clk,
in0);
output [0:0]AS;
input out;
input clk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire clk;
wire [0:0]in0;
wire out;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr
(v1_reg_0,
Q,
v1_reg,
v1_reg_1,
ram_empty_i_reg,
ram_empty_i_reg_0,
ram_empty_i_reg_1,
ram_empty_i_reg_2,
ram_empty_i_reg_3,
\gc0.count_d1_reg[9] ,
\gc0.count_reg[9] ,
E,
clk,
AR);
output [4:0]v1_reg_0;
output [9:0]Q;
output [4:0]v1_reg;
output [4:0]v1_reg_1;
output ram_empty_i_reg;
output ram_empty_i_reg_0;
output ram_empty_i_reg_1;
output ram_empty_i_reg_2;
output ram_empty_i_reg_3;
input [9:0]\gc0.count_d1_reg[9] ;
input [9:0]\gc0.count_reg[9] ;
input [0:0]E;
input clk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [9:0]Q;
wire clk;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gc0.count_reg[9] ;
wire \gcc0.gc0.count[9]_i_2_n_0 ;
wire [9:0]p_12_out;
wire [9:0]plusOp__0;
wire ram_empty_i_reg;
wire ram_empty_i_reg_0;
wire ram_empty_i_reg_1;
wire ram_empty_i_reg_2;
wire ram_empty_i_reg_3;
wire [4:0]v1_reg;
wire [4:0]v1_reg_0;
wire [4:0]v1_reg_1;
LUT1 #(
.INIT(2'h1))
\gcc0.gc0.count[0]_i_1
(.I0(p_12_out[0]),
.O(plusOp__0[0]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\gcc0.gc0.count[1]_i_1
(.I0(p_12_out[0]),
.I1(p_12_out[1]),
.O(plusOp__0[1]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h78))
\gcc0.gc0.count[2]_i_1
(.I0(p_12_out[0]),
.I1(p_12_out[1]),
.I2(p_12_out[2]),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h7F80))
\gcc0.gc0.count[3]_i_1
(.I0(p_12_out[1]),
.I1(p_12_out[0]),
.I2(p_12_out[2]),
.I3(p_12_out[3]),
.O(plusOp__0[3]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gcc0.gc0.count[4]_i_1
(.I0(p_12_out[2]),
.I1(p_12_out[0]),
.I2(p_12_out[1]),
.I3(p_12_out[3]),
.I4(p_12_out[4]),
.O(plusOp__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\gcc0.gc0.count[5]_i_1
(.I0(p_12_out[3]),
.I1(p_12_out[1]),
.I2(p_12_out[0]),
.I3(p_12_out[2]),
.I4(p_12_out[4]),
.I5(p_12_out[5]),
.O(plusOp__0[5]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\gcc0.gc0.count[6]_i_1
(.I0(\gcc0.gc0.count[9]_i_2_n_0 ),
.I1(p_12_out[6]),
.O(plusOp__0[6]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h78))
\gcc0.gc0.count[7]_i_1
(.I0(\gcc0.gc0.count[9]_i_2_n_0 ),
.I1(p_12_out[6]),
.I2(p_12_out[7]),
.O(plusOp__0[7]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h7F80))
\gcc0.gc0.count[8]_i_1
(.I0(p_12_out[6]),
.I1(\gcc0.gc0.count[9]_i_2_n_0 ),
.I2(p_12_out[7]),
.I3(p_12_out[8]),
.O(plusOp__0[8]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gcc0.gc0.count[9]_i_1
(.I0(p_12_out[7]),
.I1(\gcc0.gc0.count[9]_i_2_n_0 ),
.I2(p_12_out[6]),
.I3(p_12_out[8]),
.I4(p_12_out[9]),
.O(plusOp__0[9]));
LUT6 #(
.INIT(64'h8000000000000000))
\gcc0.gc0.count[9]_i_2
(.I0(p_12_out[5]),
.I1(p_12_out[3]),
.I2(p_12_out[1]),
.I3(p_12_out[0]),
.I4(p_12_out[2]),
.I5(p_12_out[4]),
.O(\gcc0.gc0.count[9]_i_2_n_0 ));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[0]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[1]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[2]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[3]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[4]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[5]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[6]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[7]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[8]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[9]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[9]),
.Q(Q[9]));
FDPE #(
.INIT(1'b1))
\gcc0.gc0.count_reg[0]
(.C(clk),
.CE(E),
.D(plusOp__0[0]),
.PRE(AR),
.Q(p_12_out[0]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[1]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[1]),
.Q(p_12_out[1]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[2]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[2]),
.Q(p_12_out[2]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[3]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[3]),
.Q(p_12_out[3]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[4]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[4]),
.Q(p_12_out[4]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[5]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[5]),
.Q(p_12_out[5]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[6]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[6]),
.Q(p_12_out[6]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[7]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[7]),
.Q(p_12_out[7]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[8]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[8]),
.Q(p_12_out[8]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[9]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[9]),
.Q(p_12_out[9]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1
(.I0(Q[0]),
.I1(\gc0.count_d1_reg[9] [0]),
.I2(Q[1]),
.I3(\gc0.count_d1_reg[9] [1]),
.O(v1_reg_0[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__0
(.I0(Q[0]),
.I1(\gc0.count_reg[9] [0]),
.I2(Q[1]),
.I3(\gc0.count_reg[9] [1]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__1
(.I0(p_12_out[0]),
.I1(\gc0.count_d1_reg[9] [0]),
.I2(p_12_out[1]),
.I3(\gc0.count_d1_reg[9] [1]),
.O(v1_reg_1[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__2
(.I0(Q[0]),
.I1(\gc0.count_d1_reg[9] [0]),
.I2(Q[1]),
.I3(\gc0.count_d1_reg[9] [1]),
.O(ram_empty_i_reg));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1
(.I0(Q[2]),
.I1(\gc0.count_d1_reg[9] [2]),
.I2(Q[3]),
.I3(\gc0.count_d1_reg[9] [3]),
.O(v1_reg_0[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__0
(.I0(Q[2]),
.I1(\gc0.count_reg[9] [2]),
.I2(Q[3]),
.I3(\gc0.count_reg[9] [3]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__1
(.I0(p_12_out[2]),
.I1(\gc0.count_d1_reg[9] [2]),
.I2(p_12_out[3]),
.I3(\gc0.count_d1_reg[9] [3]),
.O(v1_reg_1[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__2
(.I0(Q[2]),
.I1(\gc0.count_d1_reg[9] [2]),
.I2(Q[3]),
.I3(\gc0.count_d1_reg[9] [3]),
.O(ram_empty_i_reg_0));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1
(.I0(Q[4]),
.I1(\gc0.count_d1_reg[9] [4]),
.I2(Q[5]),
.I3(\gc0.count_d1_reg[9] [5]),
.O(v1_reg_0[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__0
(.I0(Q[4]),
.I1(\gc0.count_reg[9] [4]),
.I2(Q[5]),
.I3(\gc0.count_reg[9] [5]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__1
(.I0(p_12_out[4]),
.I1(\gc0.count_d1_reg[9] [4]),
.I2(p_12_out[5]),
.I3(\gc0.count_d1_reg[9] [5]),
.O(v1_reg_1[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__2
(.I0(Q[4]),
.I1(\gc0.count_d1_reg[9] [4]),
.I2(Q[5]),
.I3(\gc0.count_d1_reg[9] [5]),
.O(ram_empty_i_reg_1));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1
(.I0(Q[6]),
.I1(\gc0.count_d1_reg[9] [6]),
.I2(Q[7]),
.I3(\gc0.count_d1_reg[9] [7]),
.O(v1_reg_0[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__0
(.I0(Q[6]),
.I1(\gc0.count_reg[9] [6]),
.I2(Q[7]),
.I3(\gc0.count_reg[9] [7]),
.O(v1_reg[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__1
(.I0(p_12_out[6]),
.I1(\gc0.count_d1_reg[9] [6]),
.I2(p_12_out[7]),
.I3(\gc0.count_d1_reg[9] [7]),
.O(v1_reg_1[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__2
(.I0(Q[6]),
.I1(\gc0.count_d1_reg[9] [6]),
.I2(Q[7]),
.I3(\gc0.count_d1_reg[9] [7]),
.O(ram_empty_i_reg_2));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1
(.I0(Q[8]),
.I1(\gc0.count_d1_reg[9] [8]),
.I2(Q[9]),
.I3(\gc0.count_d1_reg[9] [9]),
.O(v1_reg_0[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__0
(.I0(Q[8]),
.I1(\gc0.count_reg[9] [8]),
.I2(Q[9]),
.I3(\gc0.count_reg[9] [9]),
.O(v1_reg[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__1
(.I0(p_12_out[8]),
.I1(\gc0.count_d1_reg[9] [8]),
.I2(p_12_out[9]),
.I3(\gc0.count_d1_reg[9] [9]),
.O(v1_reg_1[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__2
(.I0(Q[8]),
.I1(\gc0.count_d1_reg[9] [8]),
.I2(Q[9]),
.I3(\gc0.count_d1_reg[9] [9]),
.O(ram_empty_i_reg_3));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic
(out,
full,
WEA,
Q,
v1_reg,
ram_empty_i_reg,
ram_empty_i_reg_0,
ram_empty_i_reg_1,
ram_empty_i_reg_2,
ram_empty_i_reg_3,
clk,
\grstd1.grst_full.grst_f.rst_d2_reg ,
wr_en,
\gc0.count_d1_reg[9] ,
\gc0.count_reg[9] ,
wr_rst_busy,
E,
AR);
output out;
output full;
output [0:0]WEA;
output [9:0]Q;
output [4:0]v1_reg;
output ram_empty_i_reg;
output ram_empty_i_reg_0;
output ram_empty_i_reg_1;
output ram_empty_i_reg_2;
output ram_empty_i_reg_3;
input clk;
input \grstd1.grst_full.grst_f.rst_d2_reg ;
input wr_en;
input [9:0]\gc0.count_d1_reg[9] ;
input [9:0]\gc0.count_reg[9] ;
input wr_rst_busy;
input [0:0]E;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [9:0]Q;
wire [0:0]WEA;
wire [4:0]\c0/v1_reg ;
wire [4:0]\c1/v1_reg ;
wire clk;
wire full;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gc0.count_reg[9] ;
wire \grstd1.grst_full.grst_f.rst_d2_reg ;
wire out;
wire ram_empty_i_reg;
wire ram_empty_i_reg_0;
wire ram_empty_i_reg_1;
wire ram_empty_i_reg_2;
wire ram_empty_i_reg_3;
wire [4:0]v1_reg;
wire wr_en;
wire wr_rst_busy;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss \gwss.wsts
(.E(WEA),
.clk(clk),
.full(full),
.\grstd1.grst_full.grst_f.rst_d2_reg (\grstd1.grst_full.grst_f.rst_d2_reg ),
.out(out),
.ram_empty_fb_i_reg(E),
.v1_reg(\c0/v1_reg ),
.v1_reg_0(\c1/v1_reg ),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr wpntr
(.AR(AR),
.E(WEA),
.Q(Q),
.clk(clk),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gc0.count_reg[9] (\gc0.count_reg[9] ),
.ram_empty_i_reg(ram_empty_i_reg),
.ram_empty_i_reg_0(ram_empty_i_reg_0),
.ram_empty_i_reg_1(ram_empty_i_reg_1),
.ram_empty_i_reg_2(ram_empty_i_reg_2),
.ram_empty_i_reg_3(ram_empty_i_reg_3),
.v1_reg(v1_reg),
.v1_reg_0(\c0/v1_reg ),
.v1_reg_1(\c1/v1_reg ));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss
(out,
full,
E,
v1_reg,
v1_reg_0,
clk,
\grstd1.grst_full.grst_f.rst_d2_reg ,
wr_en,
wr_rst_busy,
ram_empty_fb_i_reg);
output out;
output full;
output [0:0]E;
input [4:0]v1_reg;
input [4:0]v1_reg_0;
input clk;
input \grstd1.grst_full.grst_f.rst_d2_reg ;
input wr_en;
input wr_rst_busy;
input [0:0]ram_empty_fb_i_reg;
wire [0:0]E;
wire clk;
wire comp1;
wire \grstd1.grst_full.grst_f.rst_d2_reg ;
(* DONT_TOUCH *) wire ram_afull_fb;
(* DONT_TOUCH *) wire ram_afull_i;
wire [0:0]ram_empty_fb_i_reg;
wire ram_full_comb;
(* DONT_TOUCH *) wire ram_full_fb_i;
(* DONT_TOUCH *) wire ram_full_i;
wire [4:0]v1_reg;
wire [4:0]v1_reg_0;
wire wr_en;
wire wr_rst_busy;
assign full = ram_full_i;
assign out = ram_full_fb_i;
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1
(.I0(wr_en),
.I1(ram_full_fb_i),
.O(E));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare c0
(.comp1(comp1),
.out(ram_full_fb_i),
.ram_empty_fb_i_reg(ram_empty_fb_i_reg),
.ram_full_comb(ram_full_comb),
.v1_reg(v1_reg),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 c1
(.comp1(comp1),
.v1_reg_0(v1_reg_0));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(1'b1),
.O(ram_afull_i));
LUT1 #(
.INIT(2'h2))
i_1
(.I0(1'b1),
.O(ram_afull_fb));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(clk),
.CE(1'b1),
.D(ram_full_comb),
.PRE(\grstd1.grst_full.grst_f.rst_d2_reg ),
.Q(ram_full_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(clk),
.CE(1'b1),
.D(ram_full_comb),
.PRE(\grstd1.grst_full.grst_f.rst_d2_reg ),
.Q(ram_full_i));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
Copyright (c) 2015-2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for wb_reg
*/
module test_wb_reg;
// Parameters
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 32;
parameter SELECT_WIDTH = 4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] wbm_adr_i = 0;
reg [DATA_WIDTH-1:0] wbm_dat_i = 0;
reg wbm_we_i = 0;
reg [SELECT_WIDTH-1:0] wbm_sel_i = 0;
reg wbm_stb_i = 0;
reg wbm_cyc_i = 0;
reg [DATA_WIDTH-1:0] wbs_dat_i = 0;
reg wbs_ack_i = 0;
reg wbs_err_i = 0;
reg wbs_rty_i = 0;
// Outputs
wire [DATA_WIDTH-1:0] wbm_dat_o;
wire wbm_ack_o;
wire wbm_err_o;
wire wbm_rty_o;
wire [ADDR_WIDTH-1:0] wbs_adr_o;
wire [DATA_WIDTH-1:0] wbs_dat_o;
wire wbs_we_o;
wire [SELECT_WIDTH-1:0] wbs_sel_o;
wire wbs_stb_o;
wire wbs_cyc_o;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
wbm_adr_i,
wbm_dat_i,
wbm_we_i,
wbm_sel_i,
wbm_stb_i,
wbm_cyc_i,
wbs_dat_i,
wbs_ack_i,
wbs_err_i,
wbs_rty_i
);
$to_myhdl(
wbm_dat_o,
wbm_ack_o,
wbm_err_o,
wbm_rty_o,
wbs_adr_o,
wbs_dat_o,
wbs_we_o,
wbs_sel_o,
wbs_stb_o,
wbs_cyc_o
);
// dump file
$dumpfile("test_wb_reg.lxt");
$dumpvars(0, test_wb_reg);
end
wb_reg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.SELECT_WIDTH(SELECT_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
.wbm_adr_i(wbm_adr_i),
.wbm_dat_i(wbm_dat_i),
.wbm_dat_o(wbm_dat_o),
.wbm_we_i(wbm_we_i),
.wbm_sel_i(wbm_sel_i),
.wbm_stb_i(wbm_stb_i),
.wbm_ack_o(wbm_ack_o),
.wbm_err_o(wbm_err_o),
.wbm_rty_o(wbm_rty_o),
.wbm_cyc_i(wbm_cyc_i),
.wbs_adr_o(wbs_adr_o),
.wbs_dat_i(wbs_dat_i),
.wbs_dat_o(wbs_dat_o),
.wbs_we_o(wbs_we_o),
.wbs_sel_o(wbs_sel_o),
.wbs_stb_o(wbs_stb_o),
.wbs_ack_i(wbs_ack_i),
.wbs_err_i(wbs_err_i),
.wbs_rty_i(wbs_rty_i),
.wbs_cyc_o(wbs_cyc_o)
);
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_8_rxeq_scan.v
// Version : 1.7
//------------------------------------------------------------------------------
// Filename : rxeq_scan.v
// Description : PIPE RX Equalization Eye Scan Module for 7 Series Transceiver
// Version : 18.0
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- RXEQ Eye Scan Module ----------------------------------------------
module pcie_7x_v1_8_rxeq_scan #
(
parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
parameter PCIE_RXEQ_MODE_GEN3 = 1, // PCIe RX equalization mode
parameter CONVERGE_MAX = 22'd3125000 // Convergence max count
)
(
//---------- Input -------------------------------------
input RXEQSCAN_CLK,
input RXEQSCAN_RST_N,
input [ 1:0] RXEQSCAN_CONTROL,
input [ 2:0] RXEQSCAN_PRESET,
input RXEQSCAN_PRESET_VALID,
input [ 3:0] RXEQSCAN_TXPRESET,
input [17:0] RXEQSCAN_TXCOEFF,
input RXEQSCAN_NEW_TXCOEFF_REQ,
input [ 5:0] RXEQSCAN_FS,
input [ 5:0] RXEQSCAN_LF,
//---------- Output ------------------------------------
output RXEQSCAN_PRESET_DONE,
output [17:0] RXEQSCAN_NEW_TXCOEFF,
output RXEQSCAN_NEW_TXCOEFF_DONE,
output RXEQSCAN_LFFS_SEL,
output RXEQSCAN_ADAPT_DONE
);
//---------- Input Register ----------------------------
reg [ 2:0] preset_reg1;
reg preset_valid_reg1;
reg [ 3:0] txpreset_reg1;
reg [17:0] txcoeff_reg1;
reg new_txcoeff_req_reg1;
reg [ 5:0] fs_reg1;
reg [ 5:0] lf_reg1;
reg [ 2:0] preset_reg2;
reg preset_valid_reg2;
reg [ 3:0] txpreset_reg2;
reg [17:0] txcoeff_reg2;
reg new_txcoeff_req_reg2;
reg [ 5:0] fs_reg2;
reg [ 5:0] lf_reg2;
//---------- Internal Signals --------------------------
reg adapt_done_cnt = 1'd0;
//---------- Output Register ---------------------------
reg preset_done = 1'd0;
reg [21:0] converge_cnt = 22'd0;
reg [17:0] new_txcoeff = 18'd0;
reg new_txcoeff_done = 1'd0;
reg lffs_sel = 1'd0;
reg adapt_done = 1'd0;
reg [ 3:0] fsm = 4'd0;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 4'b0001;
localparam FSM_PRESET = 4'b0010;
localparam FSM_CONVERGE = 4'b0100;
localparam FSM_NEW_TXCOEFF_REQ = 4'b1000;
//---------- Simulation Speedup ------------------------
// Gen3: 32 bits / PCLK : 1 million bits / X PCLK
// X =
//------------------------------------------------------
localparam converge_max_cnt = (PCIE_SIM_MODE == "TRUE") ? 22'd1000 : CONVERGE_MAX;
//---------- Input FF ----------------------------------------------------------
always @ (posedge RXEQSCAN_CLK)
begin
if (!RXEQSCAN_RST_N)
begin
//---------- 1st Stage FF --------------------------
preset_reg1 <= 3'd0;
preset_valid_reg1 <= 1'd0;
txpreset_reg1 <= 4'd0;
txcoeff_reg1 <= 18'd0;
new_txcoeff_req_reg1 <= 1'd0;
fs_reg1 <= 6'd0;
lf_reg1 <= 6'd0;
//---------- 2nd Stage FF --------------------------
preset_reg2 <= 3'd0;
preset_valid_reg2 <= 1'd0;
txpreset_reg2 <= 4'd0;
txcoeff_reg2 <= 18'd0;
new_txcoeff_req_reg2 <= 1'd0;
fs_reg2 <= 6'd0;
lf_reg2 <= 6'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
preset_reg1 <= RXEQSCAN_PRESET;
preset_valid_reg1 <= RXEQSCAN_PRESET_VALID;
txpreset_reg1 <= RXEQSCAN_TXPRESET;
txcoeff_reg1 <= RXEQSCAN_TXCOEFF;
new_txcoeff_req_reg1 <= RXEQSCAN_NEW_TXCOEFF_REQ;
fs_reg1 <= RXEQSCAN_FS;
lf_reg1 <= RXEQSCAN_LF;
//---------- 2nd Stage FF --------------------------
preset_reg2 <= preset_reg1;
preset_valid_reg2 <= preset_valid_reg1;
txpreset_reg2 <= txpreset_reg1;
txcoeff_reg2 <= txcoeff_reg1;
new_txcoeff_req_reg2 <= new_txcoeff_req_reg1;
fs_reg2 <= fs_reg1;
lf_reg2 <= lf_reg1;
end
end
//---------- Eye Scan ----------------------------------------------------------
always @ (posedge RXEQSCAN_CLK)
begin
if (!RXEQSCAN_RST_N)
begin
fsm <= FSM_IDLE;
preset_done <= 1'd0;
converge_cnt <= 22'd0;
new_txcoeff <= 18'd0;
new_txcoeff_done <= 1'd0;
lffs_sel <= 1'd0;
adapt_done <= 1'd0;
adapt_done_cnt <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
//---------- Process RXEQ Preset ---------------
if (preset_valid_reg2)
begin
fsm <= FSM_PRESET;
preset_done <= 1'd1;
converge_cnt <= 22'd0;
new_txcoeff <= new_txcoeff;
new_txcoeff_done <= 1'd0;
lffs_sel <= 1'd0;
adapt_done <= 1'd0;
adapt_done_cnt <= adapt_done_cnt;
end
//---------- Request New TX Coefficient --------
else if (new_txcoeff_req_reg2)
begin
fsm <= FSM_CONVERGE;
preset_done <= 1'd0;
converge_cnt <= 22'd0;
new_txcoeff <= (PCIE_RXEQ_MODE_GEN3 == 0) ? txcoeff_reg2 : 18'd4;
new_txcoeff_done <= 1'd0;
lffs_sel <= (PCIE_RXEQ_MODE_GEN3 == 0) ? 1'd0 : 1'd1;
adapt_done <= 1'd0;
adapt_done_cnt <= adapt_done_cnt;
end
//---------- Default ---------------------------
else
begin
fsm <= FSM_IDLE;
preset_done <= 1'd0;
converge_cnt <= 22'd0;
new_txcoeff <= new_txcoeff;
new_txcoeff_done <= 1'd0;
lffs_sel <= 1'd0;
adapt_done <= 1'd0;
adapt_done_cnt <= adapt_done_cnt;
end
end
//---------- Process RXEQ Preset -------------------
FSM_PRESET :
begin
fsm <= (!preset_valid_reg2) ? FSM_IDLE : FSM_PRESET;
preset_done <= 1'd1;
converge_cnt <= 22'd0;
new_txcoeff <= new_txcoeff;
new_txcoeff_done <= 1'd0;
lffs_sel <= 1'd0;
adapt_done <= 1'd0;
adapt_done_cnt <= adapt_done_cnt;
end
//---------- Wait for Convergence ------------------
FSM_CONVERGE :
begin
if ((adapt_done_cnt == 1'd0) && (RXEQSCAN_CONTROL == 2'd2))
begin
fsm <= FSM_NEW_TXCOEFF_REQ;
preset_done <= 1'd0;
converge_cnt <= 22'd0;
new_txcoeff <= new_txcoeff;
new_txcoeff_done <= 1'd0;
lffs_sel <= lffs_sel;
adapt_done <= 1'd0;
adapt_done_cnt <= adapt_done_cnt;
end
else
begin
fsm <= (converge_cnt == converge_max_cnt) ? FSM_NEW_TXCOEFF_REQ : FSM_CONVERGE;
preset_done <= 1'd0;
converge_cnt <= converge_cnt + 1'd1;
new_txcoeff <= new_txcoeff;
new_txcoeff_done <= 1'd0;
lffs_sel <= lffs_sel;
adapt_done <= 1'd0;
adapt_done_cnt <= adapt_done_cnt;
end
end
//---------- Request New TX Coefficient ------------
FSM_NEW_TXCOEFF_REQ :
begin
if (!new_txcoeff_req_reg2)
begin
fsm <= FSM_IDLE;
preset_done <= 1'd0;
converge_cnt <= 22'd0;
new_txcoeff <= new_txcoeff;
new_txcoeff_done <= 1'd0;
lffs_sel <= lffs_sel;
adapt_done <= 1'd0;
adapt_done_cnt <= (RXEQSCAN_CONTROL == 2'd3) ? 1'd0 : adapt_done_cnt + 1'd1;
end
else
begin
fsm <= FSM_NEW_TXCOEFF_REQ;
preset_done <= 1'd0;
converge_cnt <= 22'd0;
new_txcoeff <= new_txcoeff;
new_txcoeff_done <= 1'd1;
lffs_sel <= lffs_sel;
adapt_done <= (adapt_done_cnt == 1'd1) || (RXEQSCAN_CONTROL == 2'd3);
adapt_done_cnt <= adapt_done_cnt;
end
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_IDLE;
preset_done <= 1'd0;
converge_cnt <= 22'd0;
new_txcoeff <= 18'd0;
new_txcoeff_done <= 1'd0;
lffs_sel <= 1'd0;
adapt_done <= 1'd0;
adapt_done_cnt <= 1'd0;
end
endcase
end
end
//---------- RXEQ Eye Scan Output ----------------------------------------------
assign RXEQSCAN_PRESET_DONE = preset_done;
assign RXEQSCAN_NEW_TXCOEFF = new_txcoeff;
assign RXEQSCAN_NEW_TXCOEFF_DONE = new_txcoeff_done;
assign RXEQSCAN_LFFS_SEL = lffs_sel;
assign RXEQSCAN_ADAPT_DONE = adapt_done;
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : rank_cntrl.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
//*****************************************************************************
// This block is responsible for managing various rank level timing
// parameters. For now, only Four Activate Window (FAW) and Write
// To Read delay are implemented here.
//
// Each rank machine generates its own inhbt_act_faw_r and inhbt_rd.
// These per rank machines are driven into the bank machines. Each
// bank machines selects the correct inhibits based on the rank
// of its current request.
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v2_3_rank_cntrl #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter BURST_MODE = "8", // Burst length
parameter DQRD2DQWR_DLY = 2, // RD->WR DQ Bus Delay
parameter CL = 5, // Read CAS latency
parameter CWL = 5, // Write CAS latency
parameter ID = 0, // Unique ID for each instance
parameter nBANK_MACHS = 4, // # bank machines in MC
parameter nCK_PER_CLK = 2, // DRAM clock : MC clock
parameter nFAW = 30, // four activate window (CKs)
parameter nREFRESH_BANK = 8, // # REF commands to pull-in
parameter nRRD = 4, // ACT->ACT period (CKs)
parameter nWTR = 4, // Internal write->read
// delay (CKs)
parameter PERIODIC_RD_TIMER_DIV = 20, // Maintenance prescaler divisor
// for periodic read timer
parameter RANK_BM_BV_WIDTH = 16, // Width required to broadcast a
// single bit rank signal among
// all the bank machines
parameter RANK_WIDTH = 2, // # of bits to count ranks
parameter RANKS = 4, // # of ranks of DRAM
parameter REFRESH_TIMER_DIV = 39 // Maintenance prescaler divivor
// for refresh timer
)
(
// Maintenance requests
output periodic_rd_request,
output wire refresh_request,
// Inhibit signals
output reg inhbt_act_faw_r,
output reg inhbt_rd,
output reg inhbt_wr,
// System Inputs
input clk,
input rst,
// User maintenance requests
input app_periodic_rd_req,
input app_ref_req,
// Inputs
input [RANK_BM_BV_WIDTH-1:0] act_this_rank_r,
input clear_periodic_rd_request,
input col_rd_wr,
input init_calib_complete,
input insert_maint_r1,
input maint_prescaler_tick_r,
input [RANK_WIDTH-1:0] maint_rank_r,
input maint_zq_r,
input maint_sre_r,
input maint_srx_r,
input [(RANKS*nBANK_MACHS)-1:0] rank_busy_r,
input refresh_tick,
input [nBANK_MACHS-1:0] sending_col,
input [nBANK_MACHS-1:0] sending_row,
input [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r,
input [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r
);
//***************************************************************************
// RRD configuration. The bank machines have a mechanism to prevent RAS to
// RAS on adjacent fabric CLK states to the same rank. When
// nCK_PER_CLK == 1, this translates to a minimum of 2 for nRRD, 4 for nRRD
// when nCK_PER_CLK == 2 and 8 for nRRD when nCK_PER_CLK == 4. Some of the
// higher clock rate DDR3 DRAMs have nRRD > 4. The additional RRD inhibit
// is worked into the inhbt_faw signal.
//***************************************************************************
localparam nADD_RRD = nRRD -
(
(nCK_PER_CLK == 1) ? 2 :
(nCK_PER_CLK == 2) ? 4 :
/*(nCK_PER_CLK == 4)*/ 8
);
// divide by nCK_PER_CLK and add a cycle if there's a remainder
localparam nRRD_CLKS =
(nCK_PER_CLK == 1) ? nADD_RRD :
(nCK_PER_CLK == 2) ? ((nADD_RRD/2)+(nADD_RRD%2)) :
/*(nCK_PER_CLK == 4)*/ ((nADD_RRD/4)+((nADD_RRD%4) ? 1 : 0));
// take binary log to obtain counter width and add a tick for the idle cycle
localparam ADD_RRD_CNTR_WIDTH = clogb2(nRRD_CLKS + /* idle state */ 1);
//***************************************************************************
// Internal signals
//***************************************************************************
reg act_this_rank;
integer i; // loop invariant
//***************************************************************************
// Function clogb2
// Description:
// This function performs binary logarithm and rounds up
// Inputs:
// size: integer to perform binary log upon
// Outputs:
// clogb2: result of binary logarithm, rounded up
//***************************************************************************
function integer clogb2 (input integer size);
begin
size = size - 1;
// increment clogb2 from 1 for each bit in size
for (clogb2 = 1; size > 1; clogb2 = clogb2 + 1)
size = size >> 1;
end
endfunction // clogb2
//***************************************************************************
// Determine if this rank has been activated. act_this_rank_r is a
// registered bit vector from individual bank machines indicating the
// corresponding bank machine is sending
// an activate. Timing is improved with this method.
//***************************************************************************
always @(/*AS*/act_this_rank_r or sending_row) begin
act_this_rank = 1'b0;
for (i = 0; i < nBANK_MACHS; i = i + 1)
act_this_rank =
act_this_rank || (sending_row[i] && act_this_rank_r[(i*RANKS)+ID]);
end
reg add_rrd_inhbt = 1'b0;
generate
if (nADD_RRD > 0 && ADD_RRD_CNTR_WIDTH > 1) begin :add_rdd1
reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_ns;
reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_r;
always @(/*AS*/act_this_rank or add_rrd_r or rst) begin
add_rrd_ns = add_rrd_r;
if (rst) add_rrd_ns = {ADD_RRD_CNTR_WIDTH{1'b0}};
else
if (act_this_rank)
add_rrd_ns = nRRD_CLKS[0+:ADD_RRD_CNTR_WIDTH];
else if (|add_rrd_r) add_rrd_ns =
add_rrd_r - {{ADD_RRD_CNTR_WIDTH-1{1'b0}}, 1'b1};
end
always @(posedge clk) add_rrd_r <= #TCQ add_rrd_ns;
always @(/*AS*/add_rrd_ns) add_rrd_inhbt = |add_rrd_ns;
end // add_rdd1
else if (nADD_RRD > 0) begin :add_rdd0
reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_ns;
reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_r;
always @(/*AS*/act_this_rank or add_rrd_r or rst) begin
add_rrd_ns = add_rrd_r;
if (rst) add_rrd_ns = {ADD_RRD_CNTR_WIDTH{1'b0}};
else
if (act_this_rank)
add_rrd_ns = nRRD_CLKS[0+:ADD_RRD_CNTR_WIDTH];
else if (|add_rrd_r) add_rrd_ns =
add_rrd_r - {1'b1};
end
always @(posedge clk) add_rrd_r <= #TCQ add_rrd_ns;
always @(/*AS*/add_rrd_ns) add_rrd_inhbt = |add_rrd_ns;
end // add_rdd0
endgenerate
// Compute inhbt_act_faw_r. Only allow a limited number of activates
// in a window. Both the number of activates and the window are
// configurable. This depends on the RRD mechanism to prevent
// two consecutive activates to the same rank.
//
// Subtract three from the specified nFAW. Subtract three because:
// -Zero for the delay into the SRL is really one state.
// -Sending_row is used to trigger the delay. Sending_row is one
// state delayed from the arb.
// -inhbt_act_faw_r is registered to make timing work, hence the
// generation needs to be one state early.
localparam nFAW_CLKS = (nCK_PER_CLK == 1)
? nFAW
: (nCK_PER_CLK == 2) ? ((nFAW/2) + (nFAW%2)) :
((nFAW/4) + ((nFAW%4) ? 1 : 0));
generate
begin : inhbt_act_faw
wire act_delayed;
wire [4:0] shift_depth = nFAW_CLKS[4:0] - 5'd3;
SRLC32E #(.INIT(32'h00000000) ) SRLC32E0
(.Q(act_delayed), // SRL data output
.Q31(), // SRL cascade output pin
.A(shift_depth), // 5-bit shift depth select input
.CE(1'b1), // Clock enable input
.CLK(clk), // Clock input
.D(act_this_rank) // SRL data input
);
reg [2:0] faw_cnt_ns;
reg [2:0] faw_cnt_r;
reg inhbt_act_faw_ns;
always @(/*AS*/act_delayed or act_this_rank or add_rrd_inhbt
or faw_cnt_r or rst) begin
if (rst) faw_cnt_ns = 3'b0;
else begin
faw_cnt_ns = faw_cnt_r;
if (act_this_rank) faw_cnt_ns = faw_cnt_r + 3'b1;
if (act_delayed) faw_cnt_ns = faw_cnt_ns - 3'b1;
end
inhbt_act_faw_ns = (faw_cnt_ns == 3'h4) || add_rrd_inhbt;
end
always @(posedge clk) faw_cnt_r <= #TCQ faw_cnt_ns;
always @(posedge clk) inhbt_act_faw_r <= #TCQ inhbt_act_faw_ns;
end // block: inhbt_act_faw
endgenerate
// In the DRAM spec, tWTR starts from CK following the end of the data
// burst. Since we don't directly have that spec, the wtr timer is
// based on when the CAS write command is sent to the DRAM.
//
// To compute the wtr timer value, first compute the time from the write command
// to the read command. This is CWL + data_time + nWTR.
//
// Two is subtracted from the required wtr time since the timer
// starts two states after the arbitration cycle.
localparam ONE = 1;
localparam TWO = 2;
localparam CASWR2CASRD = CWL + (BURST_MODE == "4" ? 2 : 4) + nWTR;
localparam CASWR2CASRD_CLKS = (nCK_PER_CLK == 1)
? CASWR2CASRD :
(nCK_PER_CLK == 2)
? ((CASWR2CASRD / 2) + (CASWR2CASRD % 2)) :
((CASWR2CASRD / 4) + ((CASWR2CASRD % 4) ? 1 :0));
localparam WTR_CNT_WIDTH = clogb2(CASWR2CASRD_CLKS);
generate
begin : wtr_timer
reg write_this_rank;
always @(/*AS*/sending_col or wr_this_rank_r) begin
write_this_rank = 1'b0;
for (i = 0; i < nBANK_MACHS; i = i + 1)
write_this_rank =
write_this_rank || (sending_col[i] && wr_this_rank_r[(i*RANKS)+ID]);
end
reg [WTR_CNT_WIDTH-1:0] wtr_cnt_r;
reg [WTR_CNT_WIDTH-1:0] wtr_cnt_ns;
always @(/*AS*/rst or write_this_rank or wtr_cnt_r)
if (rst) wtr_cnt_ns = {WTR_CNT_WIDTH{1'b0}};
else begin
wtr_cnt_ns = wtr_cnt_r;
if (write_this_rank) wtr_cnt_ns =
CASWR2CASRD_CLKS[WTR_CNT_WIDTH-1:0] - ONE[WTR_CNT_WIDTH-1:0];
else if (|wtr_cnt_r) wtr_cnt_ns = wtr_cnt_r - ONE[WTR_CNT_WIDTH-1:0];
end
wire inhbt_rd_ns = |wtr_cnt_ns;
always @(posedge clk) wtr_cnt_r <= #TCQ wtr_cnt_ns;
always @(inhbt_rd_ns) inhbt_rd = inhbt_rd_ns;
end
endgenerate
// In the DRAM spec (with AL = 0), the read-to-write command delay is implied to
// be CL + data_time + 2 tCK - CWL. The CL + data_time - CWL terms ensure the
// read and write data do not collide on the DQ bus. The 2 tCK ensures a gap
// between them. Here, we allow the user to tune this fixed term via the
// DQRD2DQWR_DLY parameter. There's a potential for optimization by relocating
// this to the rank_common module, since this is a DQ/DQS bus-level requirement,
// not a per-rank requirement.
localparam CASRD2CASWR = CL + (BURST_MODE == "4" ? 2 : 4) + DQRD2DQWR_DLY - CWL;
localparam CASRD2CASWR_CLKS = (nCK_PER_CLK == 1)
? CASRD2CASWR :
(nCK_PER_CLK == 2)
? ((CASRD2CASWR / 2) + (CASRD2CASWR % 2)) :
((CASRD2CASWR / 4) + ((CASRD2CASWR % 4) ? 1 :0));
localparam RTW_CNT_WIDTH = clogb2(CASRD2CASWR_CLKS);
generate
begin : rtw_timer
reg read_this_rank;
always @(/*AS*/sending_col or rd_this_rank_r) begin
read_this_rank = 1'b0;
for (i = 0; i < nBANK_MACHS; i = i + 1)
read_this_rank =
read_this_rank || (sending_col[i] && rd_this_rank_r[(i*RANKS)+ID]);
end
reg [RTW_CNT_WIDTH-1:0] rtw_cnt_r;
reg [RTW_CNT_WIDTH-1:0] rtw_cnt_ns;
always @(/*AS*/rst or col_rd_wr or sending_col or rtw_cnt_r)
if (rst) rtw_cnt_ns = {RTW_CNT_WIDTH{1'b0}};
else begin
rtw_cnt_ns = rtw_cnt_r;
if (col_rd_wr && |sending_col) rtw_cnt_ns =
CASRD2CASWR_CLKS[RTW_CNT_WIDTH-1:0] - ONE[RTW_CNT_WIDTH-1:0];
else if (|rtw_cnt_r) rtw_cnt_ns = rtw_cnt_r - ONE[RTW_CNT_WIDTH-1:0];
end
wire inhbt_wr_ns = |rtw_cnt_ns;
always @(posedge clk) rtw_cnt_r <= #TCQ rtw_cnt_ns;
always @(inhbt_wr_ns) inhbt_wr = inhbt_wr_ns;
end
endgenerate
// Refresh request generation. Implement a "refresh bank". Referred
// to as pullin-in refresh in the JEDEC spec.
// The refresh_rank_r counter increments when a refresh to this
// rank has been decoded. In the up direction, the count saturates
// at nREFRESH_BANK. As specified in the JEDEC spec, nREFRESH_BANK
// is normally eight. The counter decrements with each refresh_tick,
// saturating at zero. A refresh will be requests when the rank is
// not busy and refresh_rank_r != nREFRESH_BANK, or refresh_rank_r
// equals zero.
localparam REFRESH_BANK_WIDTH = clogb2(nREFRESH_BANK + 1);
generate begin : refresh_generation
reg my_rank_busy;
always @(/*AS*/rank_busy_r) begin
my_rank_busy = 1'b0;
for (i=0; i < nBANK_MACHS; i=i+1)
my_rank_busy = my_rank_busy || rank_busy_r[(i*RANKS)+ID];
end
wire my_refresh =
insert_maint_r1 && ~maint_zq_r && ~maint_sre_r && ~maint_srx_r &&
(maint_rank_r == ID[RANK_WIDTH-1:0]);
reg [REFRESH_BANK_WIDTH-1:0] refresh_bank_r;
reg [REFRESH_BANK_WIDTH-1:0] refresh_bank_ns;
always @(/*AS*/app_ref_req or init_calib_complete or my_refresh
or refresh_bank_r or refresh_tick)
if (~init_calib_complete)
if (REFRESH_TIMER_DIV == 0)
refresh_bank_ns = nREFRESH_BANK[0+:REFRESH_BANK_WIDTH];
else refresh_bank_ns = {REFRESH_BANK_WIDTH{1'b0}};
else
case ({my_refresh, refresh_tick, app_ref_req})
3'b000, 3'b110, 3'b101, 3'b111 : refresh_bank_ns = refresh_bank_r;
3'b010, 3'b001, 3'b011 : refresh_bank_ns =
(|refresh_bank_r)?
refresh_bank_r - ONE[0+:REFRESH_BANK_WIDTH]:
refresh_bank_r;
3'b100 : refresh_bank_ns =
refresh_bank_r + ONE[0+:REFRESH_BANK_WIDTH];
endcase // case ({my_refresh, refresh_tick})
always @(posedge clk) refresh_bank_r <= #TCQ refresh_bank_ns;
`ifdef MC_SVA
refresh_bank_overflow: assert property (@(posedge clk)
(rst || (refresh_bank_r <= nREFRESH_BANK)));
refresh_bank_underflow: assert property (@(posedge clk)
(rst || ~(~|refresh_bank_r && ~my_refresh && refresh_tick)));
refresh_hi_priority: cover property (@(posedge clk)
(rst && ~|refresh_bank_ns && (refresh_bank_r ==
ONE[0+:REFRESH_BANK_WIDTH])));
refresh_bank_full: cover property (@(posedge clk)
(rst && (refresh_bank_r ==
nREFRESH_BANK[0+:REFRESH_BANK_WIDTH])));
`endif
assign refresh_request = init_calib_complete &&
(~|refresh_bank_r ||
((refresh_bank_r != nREFRESH_BANK[0+:REFRESH_BANK_WIDTH]) && ~my_rank_busy));
end
endgenerate
// Periodic read request generation.
localparam PERIODIC_RD_TIMER_WIDTH = clogb2(PERIODIC_RD_TIMER_DIV + /*idle state*/ 1);
generate begin : periodic_rd_generation
if ( PERIODIC_RD_TIMER_DIV != 0 ) begin // enable periodic reads
reg read_this_rank;
always @(/*AS*/rd_this_rank_r or sending_col) begin
read_this_rank = 1'b0;
for (i = 0; i < nBANK_MACHS; i = i + 1)
read_this_rank =
read_this_rank || (sending_col[i] && rd_this_rank_r[(i*RANKS)+ID]);
end
reg read_this_rank_r;
reg read_this_rank_r1;
always @(posedge clk) read_this_rank_r <= #TCQ read_this_rank;
always @(posedge clk) read_this_rank_r1 <= #TCQ read_this_rank_r;
wire int_read_this_rank = read_this_rank &&
(((nCK_PER_CLK == 4) && read_this_rank_r) ||
((nCK_PER_CLK != 4) && read_this_rank_r1));
reg periodic_rd_cntr1_ns;
reg periodic_rd_cntr1_r;
always @(/*AS*/clear_periodic_rd_request or periodic_rd_cntr1_r) begin
periodic_rd_cntr1_ns = periodic_rd_cntr1_r;
if (clear_periodic_rd_request)
periodic_rd_cntr1_ns = periodic_rd_cntr1_r + 1'b1;
end
always @(posedge clk) begin
if (rst) periodic_rd_cntr1_r <= #TCQ 1'b0;
else periodic_rd_cntr1_r <= #TCQ periodic_rd_cntr1_ns;
end
reg [PERIODIC_RD_TIMER_WIDTH-1:0] periodic_rd_timer_r;
reg [PERIODIC_RD_TIMER_WIDTH-1:0] periodic_rd_timer_ns;
always @(/*AS*/init_calib_complete or maint_prescaler_tick_r
or periodic_rd_timer_r or int_read_this_rank) begin
periodic_rd_timer_ns = periodic_rd_timer_r;
if (~init_calib_complete)
periodic_rd_timer_ns = {PERIODIC_RD_TIMER_WIDTH{1'b0}};
else if (int_read_this_rank)
periodic_rd_timer_ns =
PERIODIC_RD_TIMER_DIV[0+:PERIODIC_RD_TIMER_WIDTH];
else if (|periodic_rd_timer_r && maint_prescaler_tick_r)
periodic_rd_timer_ns =
periodic_rd_timer_r - ONE[0+:PERIODIC_RD_TIMER_WIDTH];
end
always @(posedge clk) periodic_rd_timer_r <= #TCQ periodic_rd_timer_ns;
wire periodic_rd_timer_one = maint_prescaler_tick_r &&
(periodic_rd_timer_r == ONE[0+:PERIODIC_RD_TIMER_WIDTH]);
reg periodic_rd_request_r;
wire periodic_rd_request_ns = ~rst &&
((app_periodic_rd_req && init_calib_complete) ||
((PERIODIC_RD_TIMER_DIV != 0) && ~init_calib_complete) ||
// (~(read_this_rank || clear_periodic_rd_request) &&
(~((int_read_this_rank) || (clear_periodic_rd_request && periodic_rd_cntr1_r)) &&
(periodic_rd_request_r || periodic_rd_timer_one)));
always @(posedge clk) periodic_rd_request_r <=
#TCQ periodic_rd_request_ns;
`ifdef MC_SVA
read_clears_periodic_rd_request: cover property (@(posedge clk)
(rst && (periodic_rd_request_r && read_this_rank)));
`endif
assign periodic_rd_request = init_calib_complete && periodic_rd_request_r;
end else
assign periodic_rd_request = 1'b0; //to disable periodic reads
end
endgenerate
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// sqrt_pipelined.v
// Created: 4.2.2012
// Modified: 4.5.2012
//
// Implements a fixed-point parameterized pipelined square root
// operation on an unsigned input of any bit length. The number of
// stages in the pipeline is equal to the number of output bits in the
// computation. This pipelien sustains a throughput of one computation
// per clock cycle.
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module sqrt_pipelined
(
input clk, // clock
input reset_n, // asynchronous reset
input start, // optional start signal
input [INPUT_BITS-1:0] radicand, // unsigned radicand
output reg data_valid, // optional data valid signal
output reg [OUTPUT_BITS-1:0] root // unsigned root
);
// WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP
// LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE
// OVERWRITTEN!
parameter
INPUT_BITS = 16; // number of input bits (any integer)
localparam
OUTPUT_BITS = INPUT_BITS / 2 + INPUT_BITS % 2; // number of output bits
reg [OUTPUT_BITS-1:0] start_gen; // valid data propagation
reg [OUTPUT_BITS*INPUT_BITS-1:0] root_gen; // root values
reg [OUTPUT_BITS*INPUT_BITS-1:0] radicand_gen; // radicand values
wire [OUTPUT_BITS*INPUT_BITS-1:0] mask_gen; // mask values
// This is the first stage of the pipeline.
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
start_gen[0] <= 0;
radicand_gen[INPUT_BITS-1:0] <= 0;
root_gen[INPUT_BITS-1:0] <= 0;
end
else begin
start_gen[0] <= start;
if ( mask_gen[INPUT_BITS-1:0] <= radicand ) begin
radicand_gen[INPUT_BITS-1:0] <= radicand - mask_gen[INPUT_BITS-1:0];
root_gen[INPUT_BITS-1:0] <= mask_gen[INPUT_BITS-1:0];
end
else begin
radicand_gen[INPUT_BITS-1:0] <= radicand;
root_gen[INPUT_BITS-1:0] <= 0;
end
end
end
// Main generate loop to create the masks and pipeline stages.
generate
genvar i;
// Generate all the mask values. These are built up in the
// following fashion:
// LAST MASK: 0x00...001
// 0x00...004 Increasing # OUTPUT_BITS
// 0x00...010 |
// 0x00...040 v
// ...
// FIRST MASK: 0x10...000 # masks == # OUTPUT_BITS
//
// Note that the first mask used can either be of the 0x1... or
// 0x4... variety. This is purely determined by the number of
// computation stages. However, the last mask used will always be
// 0x1 and the second to last mask used will always be 0x4.
for (i = 0; i < OUTPUT_BITS; i = i + 1) begin: mask_4
if (i % 2) // i is odd, this is a 4 mask
assign mask_gen[INPUT_BITS*(OUTPUT_BITS-i)-1:INPUT_BITS*(OUTPUT_BITS-i-1)] = 4 << 4 * (i/2);
else // i is even, this is a 1 mask
assign mask_gen[INPUT_BITS*(OUTPUT_BITS-i)-1:INPUT_BITS*(OUTPUT_BITS-i-1)] = 1 << 4 * (i/2);
end
// Generate all the pipeline stages to compute the square root of
// the input radicand stream. The general approach is to compare
// the current values of the root plus the mask to the
// radicand. If root/mask sum is greater than the radicand,
// subtract the mask and the root from the radicand and store the
// radicand for the next stage. Additionally, the root is
// increased by the value of the mask and stored for the next
// stage. If this test fails, then the radicand and the root
// retain their value through to the next stage. The one weird
// thing is that the mask indices appear to be incremented by one
// additional position. This is not the case, however, because the
// first mask is used in the first stage (always block after the
// generate statement).
for (i = 0; i < OUTPUT_BITS - 1; i = i + 1) begin: pipeline
always @ (posedge clk or negedge reset_n) begin : pipeline_stage
if (!reset_n) begin
start_gen[i+1] <= 0;
radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= 0;
root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= 0;
end
else begin
start_gen[i+1] <= start_gen[i];
if ((root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] +
mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)]) <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i]) begin
radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] -
mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] -
root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i];
root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= (root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] >> 1) +
mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)];
end
else begin
radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i];
root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] >> 1;
end
end
end
end
endgenerate
// This is the final stage which just implements a rounding
// operation. This stage could be tacked on as a combinational logic
// stage, but who cares about latency, anyway? This is NOT a true
// rounding stage. In order to add convergent rounding, you need to
// increase the input bit width by 2 (increase the number of
// pipeline stages by 1) and implement rounding in the module that
// instantiates this one.
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
data_valid <= 0;
root <= 0;
end
else begin
data_valid <= start_gen[OUTPUT_BITS-1];
if (root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS] > root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS])
root <= root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS] + 1;
else
root <= root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS];
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [31:0] a, b, c, d, e, f, g, h;
always @ (*) begin // Test Verilog 2001 (*)
// verilator lint_off COMBDLY
c <= a | b;
// verilator lint_on COMBDLY
end
always @ (posedge (clk)) begin // always bug 2008/4/18
d <= a | b;
end
always @ ((d)) begin // always bug 2008/4/18
e = d;
end
parameter CONSTANT = 1;
always @ (e, 1'b0, CONSTANT) begin // not technically legal, see bug412
f = e;
end
always @ (1'b0, CONSTANT, f) begin // not technically legal, see bug412
g = f;
end
always @ ({CONSTANT, g}) begin // bug745
h = g;
end
//always @ ((posedge b) or (a or b)) begin // note both illegal
always @ (posedge clk) begin
if (cyc!=0) begin
cyc<=cyc+1;
if (cyc==1) begin
a <= 32'hfeed0000;
b <= 32'h0000face;
end
if (cyc==2) begin
if (c != 32'hfeedface) $stop;
end
if (cyc==3) begin
if (h != 32'hfeedface) $stop;
end
if (cyc==7) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: System Verilog test of a complete CPU
//
// This code instantiates and runs a simple CPU written in System Verilog.
//
// This file ONLY is placed into the Public Domain, for any use, without
// warranty.
// Contributed 2012 by M W Lund, Atmel Corporation and Jeremy Bennett, Embecosm.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
/*AUTOWIRE*/
// **************************************************************************
// Regs and Wires
// **************************************************************************
reg rst;
integer rst_count;
integer clk_count;
testbench testbench_i (/*AUTOINST*/
// Inputs
.clk (clk),
.rst (rst));
// **************************************************************************
// Reset Generation
// **************************************************************************
initial begin
rst = 1'b1;
rst_count = 0;
end
always @( posedge clk ) begin
if (rst_count < 2) begin
rst_count++;
end
else begin
rst = 1'b0;
end
end
// **************************************************************************
// Drive simulation for 500 clock cycles
// **************************************************************************
initial begin
`ifdef TEST_VERBOSE
$display( "[testbench] - Start of simulation ----------------------- " );
`endif
clk_count = 0;
end
always @( posedge clk ) begin
if (90 == clk_count) begin
$finish ();
end
else begin
clk_count++;
end
end
final begin
`ifdef TEST_VERBOSE
$display( "[testbench] - End of simulation ------------------------- " );
`endif
$write("*-* All Finished *-*\n");
end
endmodule
module testbench (/*AUTOARG*/
// Inputs
clk, rst
);
input clk;
input rst;
// **************************************************************************
// Local parameters
// **************************************************************************
localparam
NUMPADS = $size( pinout );
// **************************************************************************
// Regs and Wires
// **************************************************************************
// **** Pinout ****
`ifdef VERILATOR // see t_tri_array
wire [NUMPADS:1] pad; // GPIO Pads (PORT{A,...,R}).
`else
wire pad [1:NUMPADS]; // GPIO Pads (PORT{A,...,R}).
`endif
// **************************************************************************
// Regs and Wires, Automatics
// **************************************************************************
/*AUTOWIRE*/
// **************************************************************************
// Includes (Testbench extensions)
// **************************************************************************
// N/A
// **************************************************************************
// Chip Instance
// **************************************************************************
chip
i_chip
(
/*AUTOINST*/
// Inouts
.pad (pad[NUMPADS:1]),
// Inputs
.clk (clk),
.rst (rst));
endmodule // test
// Local Variables:
// verilog-library-directories:("." "t_sv_cpu_code")
// End:
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__NOR2_BEHAVIORAL_PP_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__nor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , A, B );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2_BEHAVIORAL_PP_V |
`timescale 1ns/10ps
//`include "pmsm.v"
module pmsmtb;
reg [3:0] npm0, npm1, npm2, npm3;
reg clk, reset;
wire [3:0] pm0, pm1, pm2, pm3;
pmsm pmsm1(npm0, npm1, npm2, npm3, pm0, pm1, pm2, pm3, clk, reset);
initial
begin
npm0=4'd0; npm1=4'd1; npm2=4'd2; npm3=4'd3;
clk=1'b0; reset=1'b0;
#10;
clk=1'b1; reset=1'b0; // posedge clk
#10;
clk=1'b0; reset=1'b1;
#10;
clk=1'b1; reset=1'b1; // posedge clk
#10;
clk=1'b0; reset=1'b0;
#10;
clk=1'b1; reset=1'b0; // posedge clk
#10;
npm0=4'd2; npm1=4'd3; npm2=4'd5; npm3=4'd9;
clk=1'b0; reset=1'b0;
#10;
clk=1'b1; reset=1'b0; // posedge clk
#10;
npm0=4'd5; npm1=4'd1; npm2=4'd15; npm3=4'd3;
clk=1'b0; reset=1'b0;
#10;
clk=1'b1; reset=1'b0; // posedge clk
#10;
end
initial
begin
$shm_open("pmsm.shm");
$shm_probe("AC");
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:30:28 11/17/2015
// Design Name: I2C_Top
// Module Name: C:/Users/Camilo/Documents/Xilinx_Workspace/I2C_Module/top_tst.v
// Project Name: I2C_Module
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: I2C_Top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module top_tst;
// Inputs
reg clk;
reg clk_frame;
reg rst;
reg en;
reg start;
reg stop;
reg ack_o;
reg rw;
reg [7:0] out_byte;
// Outputs
wire busy;
wire err;
wire [7:0] in_byte;
wire SCL;
// Bidirs
wire SDA;
reg SDA_in, SDA_out, SDA_oen;
assign SDA = SDA_oen? 1'bz : SDA_out;
// Instantiate the Unit Under Test (UUT)
I2C_Top uut (
.clk(clk),
.clk_frame(clk_frame),
.rst(rst),
.en(en),
.start(start),
.stop(stop),
.ack_o(ack_o),
.rw(rw),
.out_byte(out_byte),
.busy(busy),
.err(err),
.in_byte(in_byte),
.SCL(SCL),
.SDA(SDA)
);
initial begin
// Initialize Inputs
clk = 0;
clk_frame = 0;
rst = 1;
en = 0;
start = 0;
stop = 0;
ack_o = 1;
rw = 0;
out_byte = 0;
SDA_oen = 1;
// Wait 100 ns for global reset to finish
#100;
rst = 0;
// Add stimulus here
out_byte = 8'hAA;
#115;
en = 1;
start = 1;
stop = 0;
#150;
en = 0;
start = 0;
out_byte = 8'h00;
#3750;
SDA_oen = 0;
SDA_out = 0;
#355;
SDA_out = 1;
en = 1;
rw = 0;
#3625;
SDA_oen = 1;
SDA_out = 0;
end
always #5 clk = ~clk;
always #55 clk_frame = ~clk_frame;
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
`include "~/ee577b/syn/src/control.h"
/*
*ALU Functions Included (in order coded below):
* ADD
* AND
* NOT
* OR
* XOR
* SUB
* PRM
*
*Other Functions:
* LD (NOP)
* WMV (ADD)
* WST (NOP)
*/
/**
* Reference:
* Nestoras Tzartzanis, EE 577B Verilog Example, Jan 25, 1996
* http://www-scf.usc.edu/~ee577/tutorial/verilog/alu.v
*/
/**
* Note that all instructions are 32-bits, and that Big-Endian
* byte and bit labeling is used. Hence, a[0] is the most
* significant bit, and a[31] is the least significant bit.
*
* Use of casex and casez may affect functionality, and produce
* larger and slower designs that omit the full_case directive
*
* Reference:
* Don Mills and Clifford E. Cummings, "RTL Coding Styles That
* Yield Simulation and Synthesis Mismatches", SNUG 1999
*
* ALU is a combinational logic block without clock signals
*/
// Behavioral model for the ALU
module alu (reg_A,reg_B,ctrl_ww,alu_op,result);
// Output signals...
// Result from copmputing an arithmetic or logical operation
output [0:127] result;
// Input signals
input [0:127] reg_A;
input [0:127] reg_B;
// Control signal bits - ww
input [0:1] ctrl_ww;
input [0:4] alu_op;
// Defining constants: parameter [name_of_constant] = value;
parameter max_128_bits = 128'hffffffffffffffffffffffffffffffff;
// Declare "reg" signals:
reg [0:127] result;
reg [0:127] p_pdt;
// Temporary reg variables for WW=8, for 8-bit multiplication
reg [0:15] p_pdt8a;
reg [0:15] p_pdt8a2;
reg [0:15] p_pdt8b;
reg [0:15] p_pdt8b2;
reg [0:15] p_pdt8c;
reg [0:15] p_pdt8c2;
reg [0:15] p_pdt8d;
reg [0:15] p_pdt8d2;
reg [0:15] p_pdt8e;
reg [0:15] p_pdt8e2;
reg [0:15] p_pdt8f;
reg [0:15] p_pdt8f2;
reg [0:15] p_pdt8g;
reg [0:15] p_pdt8g2;
reg [0:15] p_pdt8h;
reg [0:15] p_pdt8h2;
// Temporary reg variables for WW=16, for 16-bit multiplication
reg [0:31] p_pdt16a;
reg [0:31] p_pdt16a2;
reg [0:31] p_pdt16a3;
reg [0:31] p_pdt16b;
reg [0:31] p_pdt16b2;
reg [0:31] p_pdt16c;
reg [0:31] p_pdt16c2;
reg [0:31] p_pdt16d;
reg [0:31] p_pdt16d2;
integer sgn;
integer i;
integer j;
always @(reg_A or reg_B or ctrl_ww or alu_op)
begin
p_pdt=128'd0;
p_pdt8a=16'd0;
p_pdt8a2=16'd0;
p_pdt8b=16'd0;
p_pdt8b2=16'd0;
p_pdt8c=16'd0;
p_pdt8c2=16'd0;
p_pdt8d=16'd0;
p_pdt8d2=16'd0;
p_pdt8e=16'd0;
p_pdt8e2=16'd0;
p_pdt8f=16'd0;
p_pdt8f2=16'd0;
p_pdt8g=16'd0;
p_pdt8g2=16'd0;
p_pdt8h=16'd0;
p_pdt8h2=16'd0;
p_pdt16a=32'd0;
p_pdt16a2=32'd0;
p_pdt16b=32'd0;
p_pdt16b2=32'd0;
p_pdt16c=32'd0;
p_pdt16c2=32'd0;
p_pdt16d=32'd0;
p_pdt16d2=32'd0;
/**
* Based on the assigned arithmetic or logic instruction,
* carry out the appropriate function on the operands
*/
case(alu_op)
/**
* In computer science, a logical shift is a shift operator
* that shifts all the bits of its operand. Unlike an
* arithmetic shift, a logical shift does not preserve
* a number's sign bit or distinguish a number's exponent
* from its mantissa; every bit in the operand is simply
* moved a given number of bit positions, and the vacant
* bit-positions are filled in, generally with zeros
* (compare with a circular shift).
*
* SRL,SLL,Srli,sra,srai...
*/
// ================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
// ================================================
// ADD instruction
`aluwadd:
begin
case(ctrl_ww)
`w8: // aluwadd AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
result[8:15]<=reg_A[8:15]+reg_B[8:15];
result[16:23]<=reg_A[16:23]+reg_B[16:23];
result[24:31]<=reg_A[24:31]+reg_B[24:31];
result[32:39]<=reg_A[32:39]+reg_B[32:39];
result[40:47]<=reg_A[40:47]+reg_B[40:47];
result[48:55]<=reg_A[48:55]+reg_B[48:55];
result[56:63]<=reg_A[56:63]+reg_B[56:63];
result[64:71]<=reg_A[64:71]+reg_B[64:71];
result[72:79]<=reg_A[72:79]+reg_B[72:79];
result[80:87]<=reg_A[80:87]+reg_B[80:87];
result[88:95]<=reg_A[88:95]+reg_B[88:95];
result[96:103]<=reg_A[96:103]+reg_B[96:103];
result[104:111]<=reg_A[104:111]+reg_B[104:111];
result[112:119]<=reg_A[112:119]+reg_B[112:119];
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
result[16:31]<=reg_A[16:31]+reg_B[16:31];
result[32:47]<=reg_A[32:47]+reg_B[32:47];
result[48:63]<=reg_A[48:63]+reg_B[48:63];
result[64:79]<=reg_A[64:79]+reg_B[64:79];
result[80:95]<=reg_A[80:95]+reg_B[80:95];
result[96:111]<=reg_A[96:111]+reg_B[96:111];
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
result[32:63]<=reg_A[32:63]+reg_B[32:63];
result[64:95]<=reg_A[64:95]+reg_B[64:95];
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default: // aluwadd AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
// ================================================
// AND instruction
`aluwand:
begin
case(ctrl_ww)
`w8: // aluwand AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
result[8:15]<=reg_A[8:15]®_B[8:15];
result[16:23]<=reg_A[16:23]®_B[16:23];
result[24:31]<=reg_A[24:31]®_B[24:31];
result[32:39]<=reg_A[32:39]®_B[32:39];
result[40:47]<=reg_A[40:47]®_B[40:47];
result[48:55]<=reg_A[48:55]®_B[48:55];
result[56:63]<=reg_A[56:63]®_B[56:63];
result[64:71]<=reg_A[64:71]®_B[64:71];
result[72:79]<=reg_A[72:79]®_B[72:79];
result[80:87]<=reg_A[80:87]®_B[80:87];
result[88:95]<=reg_A[88:95]®_B[88:95];
result[96:103]<=reg_A[96:103]®_B[96:103];
result[104:111]<=reg_A[104:111]®_B[104:111];
result[112:119]<=reg_A[112:119]®_B[112:119];
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
result[16:31]<=reg_A[16:31]®_B[16:31];
result[32:47]<=reg_A[32:47]®_B[32:47];
result[48:63]<=reg_A[48:63]®_B[48:63];
result[64:79]<=reg_A[64:79]®_B[64:79];
result[80:95]<=reg_A[80:95]®_B[80:95];
result[96:111]<=reg_A[96:111]®_B[96:111];
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
result[32:63]<=reg_A[32:63]®_B[32:63];
result[64:95]<=reg_A[64:95]®_B[64:95];
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default: // aluwand AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
// ==============================================
// ================================================
// NOT instruction
`aluwnot:
begin
case(ctrl_ww)
`w8: // aluwnot AND `aa AND `w8
begin
result[0:7]<=~reg_A[0:7];
result[8:15]<=~reg_A[8:15];
result[16:23]<=~reg_A[16:23];
result[24:31]<=~reg_A[24:31];
result[32:39]<=~reg_A[32:39];
result[40:47]<=~reg_A[40:47];
result[48:55]<=~reg_A[48:55];
result[56:63]<=~reg_A[56:63];
result[64:71]<=~reg_A[64:71];
result[72:79]<=~reg_A[72:79];
result[80:87]<=~reg_A[80:87];
result[88:95]<=~reg_A[88:95];
result[96:103]<=~reg_A[96:103];
result[104:111]<=~reg_A[104:111];
result[112:119]<=~reg_A[112:119];
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `aa AND `w16
begin
result[0:15]<=~reg_A[0:15];
result[16:31]<=~reg_A[16:31];
result[32:47]<=~reg_A[32:47];
result[48:63]<=~reg_A[48:63];
result[64:79]<=~reg_A[64:79];
result[80:95]<=~reg_A[80:95];
result[96:111]<=~reg_A[96:111];
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `aa AND `w32
begin
result[0:31]<=~reg_A[0:31];
result[32:63]<=~reg_A[32:63];
result[64:95]<=~reg_A[64:95];
result[96:127]<=~reg_A[96:127];
end
default: // aluwnot AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
// ================================================
// OR instruction
`aluwor:
begin
case(ctrl_ww)
`w8: // aluwor AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
result[8:15]<=reg_A[8:15]|reg_B[8:15];
result[16:23]<=reg_A[16:23]|reg_B[16:23];
result[24:31]<=reg_A[24:31]|reg_B[24:31];
result[32:39]<=reg_A[32:39]|reg_B[32:39];
result[40:47]<=reg_A[40:47]|reg_B[40:47];
result[48:55]<=reg_A[48:55]|reg_B[48:55];
result[56:63]<=reg_A[56:63]|reg_B[56:63];
result[64:71]<=reg_A[64:71]|reg_B[64:71];
result[72:79]<=reg_A[72:79]|reg_B[72:79];
result[80:87]<=reg_A[80:87]|reg_B[80:87];
result[88:95]<=reg_A[88:95]|reg_B[88:95];
result[96:103]<=reg_A[96:103]|reg_B[96:103];
result[104:111]<=reg_A[104:111]|reg_B[104:111];
result[112:119]<=reg_A[112:119]|reg_B[112:119];
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
result[16:31]<=reg_A[16:31]|reg_B[16:31];
result[32:47]<=reg_A[32:47]|reg_B[32:47];
result[48:63]<=reg_A[48:63]|reg_B[48:63];
result[64:79]<=reg_A[64:79]|reg_B[64:79];
result[80:95]<=reg_A[80:95]|reg_B[80:95];
result[96:111]<=reg_A[96:111]|reg_B[96:111];
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
result[32:63]<=reg_A[32:63]|reg_B[32:63];
result[64:95]<=reg_A[64:95]|reg_B[64:95];
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default: // aluwor AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
// ========================================================
// XOR instruction
`aluwxor:
begin
case(ctrl_ww)
`w8: // aluwxor AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
result[8:15]<=reg_A[8:15]^reg_B[8:15];
result[16:23]<=reg_A[16:23]^reg_B[16:23];
result[24:31]<=reg_A[24:31]^reg_B[24:31];
result[32:39]<=reg_A[32:39]^reg_B[32:39];
result[40:47]<=reg_A[40:47]^reg_B[40:47];
result[48:55]<=reg_A[48:55]^reg_B[48:55];
result[56:63]<=reg_A[56:63]^reg_B[56:63];
result[64:71]<=reg_A[64:71]^reg_B[64:71];
result[72:79]<=reg_A[72:79]^reg_B[72:79];
result[80:87]<=reg_A[80:87]^reg_B[80:87];
result[88:95]<=reg_A[88:95]^reg_B[88:95];
result[96:103]<=reg_A[96:103]^reg_B[96:103];
result[104:111]<=reg_A[104:111]^reg_B[104:111];
result[112:119]<=reg_A[112:119]^reg_B[112:119];
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
result[16:31]<=reg_A[16:31]^reg_B[16:31];
result[32:47]<=reg_A[32:47]^reg_B[32:47];
result[48:63]<=reg_A[48:63]^reg_B[48:63];
result[64:79]<=reg_A[64:79]^reg_B[64:79];
result[80:95]<=reg_A[80:95]^reg_B[80:95];
result[96:111]<=reg_A[96:111]^reg_B[96:111];
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
result[32:63]<=reg_A[32:63]^reg_B[32:63];
result[64:95]<=reg_A[64:95]^reg_B[64:95];
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default: // aluwxor AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
// ======================================================
// SUB instruction
`aluwsub:
begin
case(ctrl_ww)
`w8: // aluwsub AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
result[8:15]<=reg_A[8:15]-reg_B[8:15];
result[16:23]<=reg_A[16:23]-reg_B[16:23];
result[24:31]<=reg_A[24:31]-reg_B[24:31];
result[32:39]<=reg_A[32:39]-reg_B[32:39];
result[40:47]<=reg_A[40:47]-reg_B[40:47];
result[48:55]<=reg_A[48:55]-reg_B[48:55];
result[56:63]<=reg_A[56:63]-reg_B[56:63];
result[64:71]<=reg_A[64:71]-reg_B[64:71];
result[72:79]<=reg_A[72:79]-reg_B[72:79];
result[80:87]<=reg_A[80:87]-reg_B[80:87];
result[88:95]<=reg_A[88:95]-reg_B[88:95];
result[96:103]<=reg_A[96:103]-reg_B[96:103];
result[104:111]<=reg_A[104:111]-reg_B[104:111];
result[112:119]<=reg_A[112:119]-reg_B[112:119];
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
result[16:31]<=reg_A[16:31]-reg_B[16:31];
result[32:47]<=reg_A[32:47]-reg_B[32:47];
result[48:63]<=reg_A[48:63]-reg_B[48:63];
result[64:79]<=reg_A[64:79]-reg_B[64:79];
result[80:95]<=reg_A[80:95]-reg_B[80:95];
result[96:111]<=reg_A[96:111]-reg_B[96:111];
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
result[32:63]<=reg_A[32:63]-reg_B[32:63];
result[64:95]<=reg_A[64:95]-reg_B[64:95];
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default: // aluwsub AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
// ==============================================================
// PRM instruction
`aluwprm:
begin
case(reg_B[4:7]) //byte0
4'd0:
result[0:7]<=reg_A[0:7];
4'd1:
result[0:7]<=reg_A[8:15];
4'd2:
result[0:7]<=reg_A[16:23];
4'd3:
result[0:7]<=reg_A[24:31];
4'd4:
result[0:7]<=reg_A[32:39];
4'd5:
result[0:7]<=reg_A[40:47];
4'd6:
result[0:7]<=reg_A[48:55];
4'd7:
result[0:7]<=reg_A[56:63];
4'd8:
result[0:7]<=reg_A[64:71];
4'd9:
result[0:7]<=reg_A[72:79];
4'd10:
result[0:7]<=reg_A[80:87];
4'd11:
result[0:7]<=reg_A[88:95];
4'd12:
result[0:7]<=reg_A[96:103];
4'd13:
result[0:7]<=reg_A[104:111];
4'd14:
result[0:7]<=reg_A[112:119];
4'd15:
result[0:7]<=reg_A[120:127];
endcase
case(reg_B[12:15]) //byte1
4'd0:
result[8:15]<=reg_A[0:7];
4'd1:
result[8:15]<=reg_A[8:15];
4'd2:
result[8:15]<=reg_A[16:23];
4'd3:
result[8:15]<=reg_A[24:31];
4'd4:
result[8:15]<=reg_A[32:39];
4'd5:
result[8:15]<=reg_A[40:47];
4'd6:
result[8:15]<=reg_A[48:55];
4'd7:
result[8:15]<=reg_A[56:63];
4'd8:
result[8:15]<=reg_A[64:71];
4'd9:
result[8:15]<=reg_A[72:79];
4'd10:
result[8:15]<=reg_A[80:87];
4'd11:
result[8:15]<=reg_A[88:95];
4'd12:
result[8:15]<=reg_A[96:103];
4'd13:
result[8:15]<=reg_A[104:111];
4'd14:
result[8:15]<=reg_A[112:119];
4'd15:
result[8:15]<=reg_A[120:127];
endcase
case(reg_B[20:23]) //byte2
4'd0:
result[16:23]<=reg_A[0:7];
4'd1:
result[16:23]<=reg_A[8:15];
4'd2:
result[16:23]<=reg_A[16:23];
4'd3:
result[16:23]<=reg_A[24:31];
4'd4:
result[16:23]<=reg_A[32:39];
4'd5:
result[16:23]<=reg_A[40:47];
4'd6:
result[16:23]<=reg_A[48:55];
4'd7:
result[16:23]<=reg_A[56:63];
4'd8:
result[16:23]<=reg_A[64:71];
4'd9:
result[16:23]<=reg_A[72:79];
4'd10:
result[16:23]<=reg_A[80:87];
4'd11:
result[16:23]<=reg_A[88:95];
4'd12:
result[16:23]<=reg_A[96:103];
4'd13:
result[16:23]<=reg_A[104:111];
4'd14:
result[16:23]<=reg_A[112:119];
4'd15:
result[16:23]<=reg_A[120:127];
endcase
case(reg_B[28:31]) //byte3
4'd0:
result[24:31]<=reg_A[0:7];
4'd1:
result[24:31]<=reg_A[8:15];
4'd2:
result[24:31]<=reg_A[16:23];
4'd3:
result[24:31]<=reg_A[24:31];
4'd4:
result[24:31]<=reg_A[32:39];
4'd5:
result[24:31]<=reg_A[40:47];
4'd6:
result[24:31]<=reg_A[48:55];
4'd7:
result[24:31]<=reg_A[56:63];
4'd8:
result[24:31]<=reg_A[64:71];
4'd9:
result[24:31]<=reg_A[72:79];
4'd10:
result[24:31]<=reg_A[80:87];
4'd11:
result[24:31]<=reg_A[88:95];
4'd12:
result[24:31]<=reg_A[96:103];
4'd13:
result[24:31]<=reg_A[104:111];
4'd14:
result[24:31]<=reg_A[112:119];
4'd15:
result[24:31]<=reg_A[120:127];
endcase
case(reg_B[36:39]) //byte4
4'd0:
result[32:39]<=reg_A[0:7];
4'd1:
result[32:39]<=reg_A[8:15];
4'd2:
result[32:39]<=reg_A[16:23];
4'd3:
result[32:39]<=reg_A[24:31];
4'd4:
result[32:39]<=reg_A[32:39];
4'd5:
result[32:39]<=reg_A[40:47];
4'd6:
result[32:39]<=reg_A[48:55];
4'd7:
result[32:39]<=reg_A[56:63];
4'd8:
result[32:39]<=reg_A[64:71];
4'd9:
result[32:39]<=reg_A[72:79];
4'd10:
result[32:39]<=reg_A[80:87];
4'd11:
result[32:39]<=reg_A[88:95];
4'd12:
result[32:39]<=reg_A[96:103];
4'd13:
result[32:39]<=reg_A[104:111];
4'd14:
result[32:39]<=reg_A[112:119];
4'd15:
result[32:39]<=reg_A[120:127];
endcase
case(reg_B[44:47]) //byte5
4'd0:
result[40:47]<=reg_A[0:7];
4'd1:
result[40:47]<=reg_A[8:15];
4'd2:
result[40:47]<=reg_A[16:23];
4'd3:
result[40:47]<=reg_A[24:31];
4'd4:
result[40:47]<=reg_A[32:39];
4'd5:
result[40:47]<=reg_A[40:47];
4'd6:
result[40:47]<=reg_A[48:55];
4'd7:
result[40:47]<=reg_A[56:63];
4'd8:
result[40:47]<=reg_A[64:71];
4'd9:
result[40:47]<=reg_A[72:79];
4'd10:
result[40:47]<=reg_A[80:87];
4'd11:
result[40:47]<=reg_A[88:95];
4'd12:
result[40:47]<=reg_A[96:103];
4'd13:
result[40:47]<=reg_A[104:111];
4'd14:
result[40:47]<=reg_A[112:119];
4'd15:
result[40:47]<=reg_A[120:127];
endcase
case(reg_B[52:55]) //byte6
4'd0:
result[48:55]<=reg_A[0:7];
4'd1:
result[48:55]<=reg_A[8:15];
4'd2:
result[48:55]<=reg_A[16:23];
4'd3:
result[48:55]<=reg_A[24:31];
4'd4:
result[48:55]<=reg_A[32:39];
4'd5:
result[48:55]<=reg_A[40:47];
4'd6:
result[48:55]<=reg_A[48:55];
4'd7:
result[48:55]<=reg_A[56:63];
4'd8:
result[48:55]<=reg_A[64:71];
4'd9:
result[48:55]<=reg_A[72:79];
4'd10:
result[48:55]<=reg_A[80:87];
4'd11:
result[48:55]<=reg_A[88:95];
4'd12:
result[48:55]<=reg_A[96:103];
4'd13:
result[48:55]<=reg_A[104:111];
4'd14:
result[48:55]<=reg_A[112:119];
4'd15:
result[48:55]<=reg_A[120:127];
endcase
case(reg_B[60:63]) //byte7
4'd0:
result[56:63]<=reg_A[0:7];
4'd1:
result[56:63]<=reg_A[8:15];
4'd2:
result[56:63]<=reg_A[16:23];
4'd3:
result[56:63]<=reg_A[24:31];
4'd4:
result[56:63]<=reg_A[32:39];
4'd5:
result[56:63]<=reg_A[40:47];
4'd6:
result[56:63]<=reg_A[48:55];
4'd7:
result[56:63]<=reg_A[56:63];
4'd8:
result[56:63]<=reg_A[64:71];
4'd9:
result[56:63]<=reg_A[72:79];
4'd10:
result[56:63]<=reg_A[80:87];
4'd11:
result[56:63]<=reg_A[88:95];
4'd12:
result[56:63]<=reg_A[96:103];
4'd13:
result[56:63]<=reg_A[104:111];
4'd14:
result[56:63]<=reg_A[112:119];
4'd15:
result[56:63]<=reg_A[120:127];
endcase
case(reg_B[68:71]) //byte8
4'd0:
result[64:71]<=reg_A[0:7];
4'd1:
result[64:71]<=reg_A[8:15];
4'd2:
result[64:71]<=reg_A[16:23];
4'd3:
result[64:71]<=reg_A[24:31];
4'd4:
result[64:71]<=reg_A[32:39];
4'd5:
result[64:71]<=reg_A[40:47];
4'd6:
result[64:71]<=reg_A[48:55];
4'd7:
result[64:71]<=reg_A[56:63];
4'd8:
result[64:71]<=reg_A[64:71];
4'd9:
result[64:71]<=reg_A[72:79];
4'd10:
result[64:71]<=reg_A[80:87];
4'd11:
result[64:71]<=reg_A[88:95];
4'd12:
result[64:71]<=reg_A[96:103];
4'd13:
result[64:71]<=reg_A[104:111];
4'd14:
result[64:71]<=reg_A[112:119];
4'd15:
result[64:71]<=reg_A[120:127];
endcase
case(reg_B[76:79]) //byte9
4'd0:
result[72:79]<=reg_A[0:7];
4'd1:
result[72:79]<=reg_A[8:15];
4'd2:
result[72:79]<=reg_A[16:23];
4'd3:
result[72:79]<=reg_A[24:31];
4'd4:
result[72:79]<=reg_A[32:39];
4'd5:
result[72:79]<=reg_A[40:47];
4'd6:
result[72:79]<=reg_A[48:55];
4'd7:
result[72:79]<=reg_A[56:63];
4'd8:
result[72:79]<=reg_A[64:71];
4'd9:
result[72:79]<=reg_A[72:79];
4'd10:
result[72:79]<=reg_A[80:87];
4'd11:
result[72:79]<=reg_A[88:95];
4'd12:
result[72:79]<=reg_A[96:103];
4'd13:
result[72:79]<=reg_A[104:111];
4'd14:
result[72:79]<=reg_A[112:119];
4'd15:
result[72:79]<=reg_A[120:127];
endcase
case(reg_B[84:87]) //byte10
4'd0:
result[80:87]<=reg_A[0:7];
4'd1:
result[80:87]<=reg_A[8:15];
4'd2:
result[80:87]<=reg_A[16:23];
4'd3:
result[80:87]<=reg_A[24:31];
4'd4:
result[80:87]<=reg_A[32:39];
4'd5:
result[80:87]<=reg_A[40:47];
4'd6:
result[80:87]<=reg_A[48:55];
4'd7:
result[80:87]<=reg_A[56:63];
4'd8:
result[80:87]<=reg_A[64:71];
4'd9:
result[80:87]<=reg_A[72:79];
4'd10:
result[80:87]<=reg_A[80:87];
4'd11:
result[80:87]<=reg_A[88:95];
4'd12:
result[80:87]<=reg_A[96:103];
4'd13:
result[80:87]<=reg_A[104:111];
4'd14:
result[80:87]<=reg_A[112:119];
4'd15:
result[80:87]<=reg_A[120:127];
endcase
case(reg_B[92:95]) //byte11
4'd0:
result[88:95]<=reg_A[0:7];
4'd1:
result[88:95]<=reg_A[8:15];
4'd2:
result[88:95]<=reg_A[16:23];
4'd3:
result[88:95]<=reg_A[24:31];
4'd4:
result[88:95]<=reg_A[32:39];
4'd5:
result[88:95]<=reg_A[40:47];
4'd6:
result[88:95]<=reg_A[48:55];
4'd7:
result[88:95]<=reg_A[56:63];
4'd8:
result[88:95]<=reg_A[64:71];
4'd9:
result[88:95]<=reg_A[72:79];
4'd10:
result[88:95]<=reg_A[80:87];
4'd11:
result[88:95]<=reg_A[88:95];
4'd12:
result[88:95]<=reg_A[96:103];
4'd13:
result[88:95]<=reg_A[104:111];
4'd14:
result[88:95]<=reg_A[112:119];
4'd15:
result[88:95]<=reg_A[120:127];
endcase
case(reg_B[100:103]) //byte12
4'd0:
result[96:103]<=reg_A[0:7];
4'd1:
result[96:103]<=reg_A[8:15];
4'd2:
result[96:103]<=reg_A[16:23];
4'd3:
result[96:103]<=reg_A[24:31];
4'd4:
result[96:103]<=reg_A[32:39];
4'd5:
result[96:103]<=reg_A[40:47];
4'd6:
result[96:103]<=reg_A[48:55];
4'd7:
result[96:103]<=reg_A[56:63];
4'd8:
result[96:103]<=reg_A[64:71];
4'd9:
result[96:103]<=reg_A[72:79];
4'd10:
result[96:103]<=reg_A[80:87];
4'd11:
result[96:103]<=reg_A[88:95];
4'd12:
result[96:103]<=reg_A[96:103];
4'd13:
result[96:103]<=reg_A[104:111];
4'd14:
result[96:103]<=reg_A[112:119];
4'd15:
result[96:103]<=reg_A[120:127];
endcase
case(reg_B[108:111]) //byte13
4'd0:
result[104:111]<=reg_A[0:7];
4'd1:
result[104:111]<=reg_A[8:15];
4'd2:
result[104:111]<=reg_A[16:23];
4'd3:
result[104:111]<=reg_A[24:31];
4'd4:
result[104:111]<=reg_A[32:39];
4'd5:
result[104:111]<=reg_A[40:47];
4'd6:
result[104:111]<=reg_A[48:55];
4'd7:
result[104:111]<=reg_A[56:63];
4'd8:
result[104:111]<=reg_A[64:71];
4'd9:
result[104:111]<=reg_A[72:79];
4'd10:
result[104:111]<=reg_A[80:87];
4'd11:
result[104:111]<=reg_A[88:95];
4'd12:
result[104:111]<=reg_A[96:103];
4'd13:
result[104:111]<=reg_A[104:111];
4'd14:
result[104:111]<=reg_A[112:119];
4'd15:
result[104:111]<=reg_A[120:127];
endcase
case(reg_B[116:119]) //byte14
4'd0:
result[112:119]<=reg_A[112:119];
4'd1:
result[112:119]<=reg_A[8:15];
4'd2:
result[112:119]<=reg_A[16:23];
4'd3:
result[112:119]<=reg_A[24:31];
4'd4:
result[112:119]<=reg_A[32:39];
4'd5:
result[112:119]<=reg_A[40:47];
4'd6:
result[112:119]<=reg_A[48:55];
4'd7:
result[112:119]<=reg_A[56:63];
4'd8:
result[112:119]<=reg_A[64:71];
4'd9:
result[112:119]<=reg_A[72:79];
4'd10:
result[112:119]<=reg_A[80:87];
4'd11:
result[112:119]<=reg_A[88:95];
4'd12:
result[112:119]<=reg_A[96:103];
4'd13:
result[112:119]<=reg_A[104:111];
4'd14:
result[112:119]<=reg_A[112:119];
4'd15:
result[112:119]<=reg_A[120:127];
endcase
case(reg_B[124:127]) //byte15
4'd0:
result[120:127]<=reg_A[0:7];
4'd1:
result[120:127]<=reg_A[8:15];
4'd2:
result[120:127]<=reg_A[16:23];
4'd3:
result[120:127]<=reg_A[24:31];
4'd4:
result[120:127]<=reg_A[32:39];
4'd5:
result[120:127]<=reg_A[40:47];
4'd6:
result[120:127]<=reg_A[48:55];
4'd7:
result[120:127]<=reg_A[56:63];
4'd8:
result[120:127]<=reg_A[64:71];
4'd9:
result[120:127]<=reg_A[72:79];
4'd10:
result[120:127]<=reg_A[80:87];
4'd11:
result[120:127]<=reg_A[88:95];
4'd12:
result[120:127]<=reg_A[96:103];
4'd13:
result[120:127]<=reg_A[104:111];
4'd14:
result[120:127]<=reg_A[112:119];
4'd15:
result[120:127]<=reg_A[120:127];
endcase
end
// ==================================================================
default:
begin
// Default arithmetic/logic operation
result<=128'd0;
end
endcase
end
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_convert_with_rounding_8(clock, resetn, dataa, result, valid_in, valid_out, stall_in, stall_out, enable);
// Latency = 4.
parameter UNSIGNED = 1;
parameter ROUNDING_MODE = 0;
parameter HIGH_CAPACITY = 1;
// Rounding mode values are:
// 0 - round to nearest even
// 1 - round to nearest with ties away from zero
// 2 - round towards zero (truncation)
// 3 - round up
// 4 - round down
input clock;
input enable, resetn;
input [31:0] dataa;
output [7:0] result;
input valid_in, stall_in;
output stall_out, valid_out;
// STAGE 0 - extract input data into format we can work with.
wire sign_0;
wire [7:0] exp_0;
wire [22:0] man_0;
wire [23:0] implied_man_0;
assign {sign_0, exp_0, man_0} = dataa;
assign implied_man_0 = (|exp_0) ? {1'b1, man_0} : 24'd0;
// STAGE 1
reg sign_c1;
reg [10:0] man_c1;
reg [8:0] shift_amount_c1;
reg [7:0] exp_c1;
reg valid_c1;
wire stall_c1;
wire enable_c1;
assign stall_out = stall_c1 & valid_c1;
assign enable_c1 = (HIGH_CAPACITY == 1) ? (~stall_c1 | ~valid_c1) : enable;
always @( posedge clock or negedge resetn)
begin
if( ~resetn )
begin
sign_c1 <= 1'bx;
man_c1 <= 11'dx;
shift_amount_c1 <= 9'dx;
exp_c1 <= 8'dx;
valid_c1 <= 1'b0;
end
else if (enable_c1)
begin
sign_c1 <= sign_0;
valid_c1 <= valid_in;
if (UNSIGNED == 1)
begin
man_c1 <= {implied_man_0[23:14], |implied_man_0[13:0]};
shift_amount_c1 <= 9'd134 - exp_0;
end
else
begin
man_c1 <= {1'b0, implied_man_0[23:15], |implied_man_0[14:0]};
shift_amount_c1 <= 9'd133 - exp_0;
end
exp_c1 <= exp_0;
end
end
// STAGE 2
reg sign_c2;
reg [10:0] extended_mantissa_c2;
reg [2:0] shift_amount_c2;
reg valid_c2;
wire stall_c2;
wire enable_c2 = (HIGH_CAPACITY == 1) ? (~stall_c2 | ~valid_c2) : enable;
assign stall_c1 = stall_c2 & valid_c2;
always @( posedge clock or negedge resetn)
begin
if (~resetn)
begin
sign_c2 <= 1'bx;
extended_mantissa_c2 <= 11'dx;
shift_amount_c2 <= 3'dx;
valid_c2 <= 1'b0;
end
else if (enable_c2)
begin
sign_c2 <= sign_c1;
valid_c2 <= valid_c1;
shift_amount_c2 <= (shift_amount_c1[2:0]) & {3{(~(&exp_c1)) & ~shift_amount_c1[8]}};
// Now handle the corner cases of NaN and INF. Make it maximum positive or negative integer depending on the sign.
// Then handle overflow and regular shifting.
if ((UNSIGNED == 1) && (exp_c1 == 8'hff))
extended_mantissa_c2 <= {8'hff, 3'd0};
else if ((UNSIGNED == 0) && (exp_c1 == 8'hff))
extended_mantissa_c2 <= {8'h7f + sign_c1, 3'd0};
else if (shift_amount_c1[8])
extended_mantissa_c2 <= {(UNSIGNED == 0) ? 8'h7f + sign_c1 : 8'hff, 3'd0}; // Overflow/Saturation.
else if (|shift_amount_c1[7:4])
begin
// Shift by more than 16+
sign_c2 <= sign_c1 & (|man_c1);
extended_mantissa_c2 <= {10'd0, |man_c1};
end
else if (|shift_amount_c1[3])
begin
// Shift by 8+
extended_mantissa_c2 <= {8'd0, man_c1[10:9], |man_c1[8:0]};
end
else
extended_mantissa_c2 <= man_c1;
end
end
// STAGE 3
reg [10:0] extended_mantissa_c3;
reg valid_c3;
reg sign_c3;
wire stall_c3;
wire enable_c3 = (HIGH_CAPACITY == 1) ? (~valid_c3 | ~stall_c3) : enable;
assign stall_c2 = valid_c3 & stall_c3;
always @( posedge clock or negedge resetn)
begin
if (~resetn)
begin
extended_mantissa_c3 <= 35'dx;
sign_c3 <= 1'bx;
valid_c3 <= 1'b0;
end
else if (enable_c3)
begin
valid_c3 <= valid_c2;
sign_c3 <= sign_c2;
case (shift_amount_c2)
3'b111: extended_mantissa_c3 <= {7'd0, extended_mantissa_c2[10:8], |extended_mantissa_c2[7:0]};
3'b110: extended_mantissa_c3 <= {6'd0, extended_mantissa_c2[10:7], |extended_mantissa_c2[6:0]};
3'b101: extended_mantissa_c3 <= {5'd0, extended_mantissa_c2[10:6], |extended_mantissa_c2[5:0]};
3'b100: extended_mantissa_c3 <= {4'd0, extended_mantissa_c2[10:5], |extended_mantissa_c2[4:0]};
3'b011: extended_mantissa_c3 <= {3'd0, extended_mantissa_c2[10:4], |extended_mantissa_c2[3:0]};
3'b010: extended_mantissa_c3 <= {2'd0, extended_mantissa_c2[10:3], |extended_mantissa_c2[2:0]};
3'b001: extended_mantissa_c3 <= {1'd0, extended_mantissa_c2[10:2], |extended_mantissa_c2[1:0]};
3'b000: extended_mantissa_c3 <= extended_mantissa_c2;
endcase
end
end
// STAGE 4
reg [8:0] result_c4;
reg valid_c4;
wire stall_c4;
wire enable_c4 = (HIGH_CAPACITY == 1) ? (~valid_c4 | ~stall_c4) : enable;
assign stall_c3 = valid_c4 & stall_c4;
assign stall_c4 = stall_in;
always @( posedge clock or negedge resetn)
begin
if (~resetn)
begin
result_c4 <= 9'dx;
valid_c4 <= 1'b0;
end
else if (enable_c4)
begin
valid_c4 <= valid_c3;
case(ROUNDING_MODE)
2:
begin // 2 is round to zero
if (UNSIGNED == 0)
begin
result_c4 <= ({9{sign_c3}} ^ (extended_mantissa_c3[10:3])) + sign_c3;
end
else
begin
result_c4 <= (sign_c3) ? 8'd0 : extended_mantissa_c3[10:3];
end
end
4:
begin // 4 is round down
if (|extended_mantissa_c3[2:0])
begin
if (UNSIGNED == 0)
begin
result_c4 <= (sign_c3) ? (({9{sign_c3}} ^ (extended_mantissa_c3[10:3] + 1'b1)) + 1'b1) : extended_mantissa_c3[10:3];
end
else
begin
result_c4 <= (sign_c3) ? 8'd0 : extended_mantissa_c3[10:3];
end
end
else
begin
if (UNSIGNED == 0)
result_c4 <= ({9{sign_c3}} ^ extended_mantissa_c3[10:3]) + sign_c3;
else
result_c4 <= {8{~sign_c3}} & extended_mantissa_c3[10:3];
end
end
3:
begin // 3 is round up
if (|extended_mantissa_c3[2:0])
begin
if (UNSIGNED == 0)
begin
result_c4 <= (sign_c3) ? (({9{sign_c3}} ^ extended_mantissa_c3[10:3]) + 1'b1) : (extended_mantissa_c3[10:3] + 1'b1);
end
else
begin
result_c4 <= (sign_c3) ? 8'd0 : extended_mantissa_c3[10:3] + 1'b1;
end
end
else
begin
if (UNSIGNED == 0)
result_c4 <= ({9{sign_c3}} ^ extended_mantissa_c3[10:3]) + sign_c3;
else
result_c4 <= {8{~sign_c3}} & extended_mantissa_c3[10:3];
end
end
1:
begin // 1 is round to nearest with ties rounded away from zero.
if (extended_mantissa_c3[2])
begin
if (UNSIGNED == 0)
begin
result_c4 <= ({9{sign_c3}} ^ (extended_mantissa_c3[10:3] + 1'b1)) + sign_c3;
end
else
begin
result_c4 <= (sign_c3) ? 8'd0 : extended_mantissa_c3[10:3] + 1'b1;
end
end
else
begin
if (UNSIGNED == 0)
result_c4 <= ({9{sign_c3}} ^ extended_mantissa_c3[10:3]) + sign_c3;
else
result_c4 <= {8{~sign_c3}} & extended_mantissa_c3[10:3];
end
end
default:
begin // 0 and default are round to nearest even
if ((extended_mantissa_c3[3:0] == 4'hc) | (extended_mantissa_c3[2] & (|extended_mantissa_c3[1:0])))
begin
if (UNSIGNED == 0)
begin
result_c4 <= ({9{sign_c3}} ^ (extended_mantissa_c3[10:3] + 1'b1)) + sign_c3;
end
else
begin
result_c4 <= (sign_c3) ? 8'd0 : extended_mantissa_c3[10:3] + 1'b1;
end
end
else
begin
if (UNSIGNED == 0)
result_c4 <= ({9{sign_c3}} ^ extended_mantissa_c3[10:3]) + sign_c3;
else
result_c4 <= {8{~sign_c3}} & extended_mantissa_c3[10:3];
end
end
endcase
end
end
// handle saturation here too, just in case rounding went over the limit of the expected range.
assign result = (UNSIGNED == 1) ? ({8{result_c4[8]}} | result_c4) : ((result_c4[8] ^ result_c4[7]) ? {result_c4[8], {7{~result_c4[8]}}} : result_c4[7:0]);
assign valid_out = valid_c4;
endmodule
|
module test;
// The SystemVerilog standard requires that the right side of a logical operator
// is not evaluated under certain conditions.
// For && if the left hand side is false the right hand side is not evalualted
// For || if the left hand side is true the right hand side is not evalualted
wire a0 = 1'b0;
wire a1 = 1'b1;
wire ax = 1'bx;
wire az = 1'bz;
integer b;
logic [1:0] c;
bit failed = 1'b0;
initial begin
// AND with first parameter 1'b0
b = 0;
c = 2'b00;
if (a0 && b++ && ++b)
c = 2'b01;
failed |= b !== 0;
failed |= c !== 2'b00;
c = a0 && b++ && ++b;
failed |= b !== 0;
failed |= c !== 2'b00;
// AND with first parameter 1'b1
b = 0;
c = 2'b00;
if (a1 && b++ && ++b)
c = 2'b01;
failed |= b !== 1;
failed |= c !== 2'b00;
c = a1 && b++ && ++b;
failed |= b !== 3;
failed |= c !== 2'b01;
// AND with first parameter 1'bz
b = 0;
c = 2'b00;
if (az && b++ && ++b)
c = 2'b01;
failed |= b !== 1;
failed |= c !== 2'b00;
c = az && b++ && ++b;
failed |= b !== 3;
failed |= c !== 2'b0x;
// AND with first parameter 1'bz
b = 0;
c = 0;
if (ax && b++ && ++b)
c = 2'b01;
failed |= b !== 1;
failed |= c !== 2'b00;
c = ax && b++ && ++b;
failed |= b !== 3;
failed |= c !== 2'b0x;
// OR with first parameter 1'b0
b = 0;
c = 0;
if (a0 || b++ || ++b)
c = 2'b01;
failed |= b !== 2;
failed |= c !== 2'b01;
c = a0 || b++ || ++b;
failed |= b !== 3;
failed |= c !== 2'b01;
// OR with first parameter 1'b1
b = 0;
c = 2'b00;
if (a1 || b++ || ++b)
c = 2'b01;
failed |= b !== 0;
failed |= c !== 2'b01;
c = a1 || b++ || ++b;
failed |= b !== 0;
failed |= c !== 2'b01;
// OR with first parameter 1'bz
b = 0;
c = 2'b00;
if (az || b++ || ++b)
c = 2'b01;
failed |= b !== 2;
failed |= c !== 2'b01;
b = 0;
c = az || b++;
failed |= b !== 1;
failed |= c !== 2'b0x;
// OR with first parameter 1'bz
b = 0;
c = 0;
if (ax || b++ || ++b)
c = 2'b01;
failed |= b !== 2;
failed |= c !== 2'b01;
b = 0;
c = ax || b++;
failed |= b !== 1;
failed |= c !== 2'b0x;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : mc.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
//*****************************************************************************
// Top level memory sequencer structural block. This block
// instantiates the rank, bank, and column machines.
//*****************************************************************************
`timescale 1ps/1ps
module mc #
(
parameter TCQ = 100, // clk->out delay(sim only)
parameter ADDR_CMD_MODE = "1T", // registered or
// 1Tfered mem?
parameter BANK_WIDTH = 3, // bank address width
parameter BM_CNT_WIDTH = 2, // # BM counter width
// i.e., log2(nBANK_MACHS)
parameter BURST_MODE = "8", // Burst length
parameter CL = 5, // Read CAS latency
// (in clk cyc)
parameter CMD_PIPE_PLUS1 = "ON", // add register stage
// between MC and PHY
parameter COL_WIDTH = 12, // column address width
parameter CS_WIDTH = 4, // # of unique CS outputs
parameter CWL = 5, // Write CAS latency
// (in clk cyc)
parameter DATA_BUF_ADDR_WIDTH = 8, // User request tag (e.g.
// user src/dest buf addr)
parameter DATA_BUF_OFFSET_WIDTH = 1, // User buffer offset width
parameter DATA_WIDTH = 64, // Data bus width
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_TYPE = "DDR3", // Memory I/F type:
// "DDR3", "DDR2"
parameter ECC = "OFF", // ECC ON/OFF?
parameter ECC_WIDTH = 8, // # of ECC bits
parameter MAINT_PRESCALER_PERIOD= 200000, // maintenance period (ps)
parameter MC_ERR_ADDR_WIDTH = 31, // # of error address bits
parameter nBANK_MACHS = 4, // # of bank machines (BM)
parameter nCK_PER_CLK = 4, // DRAM clock : MC clock
// frequency ratio
parameter nCS_PER_RANK = 1, // # of unique CS outputs
// per rank
parameter nREFRESH_BANK = 1, // # of REF cmds to pull-in
parameter nSLOTS = 1, // # DIMM slots in system
parameter ORDERING = "NORM", // request ordering mode
parameter PAYLOAD_WIDTH = 64, // Width of data payload
// from PHY
parameter RANK_WIDTH = 2, // # of bits to count ranks
parameter RANKS = 4, // # of ranks of DRAM
parameter REG_CTRL = "ON", // "ON" for registered DIMM
parameter ROW_WIDTH = 16, // row address width
parameter RTT_NOM = "40", // Nominal ODT value
parameter RTT_WR = "120", // Write ODT value
parameter SLOT_0_CONFIG = 8'b0000_0101, // ranks allowed in slot 0
parameter SLOT_1_CONFIG = 8'b0000_1010, // ranks allowed in slot 1
parameter STARVE_LIMIT = 2, // max # of times a user
// request is allowed to
// lose arbitration when
// reordering is enabled
parameter tCK = 2500, // memory clk period(ns)
parameter tFAW = 40000, // four activate window(ns)
parameter tRAS = 37500, // ACT->PRE cmd period (ns)
parameter tRCD = 12500, // ACT->R/W delay (ns)
parameter tREFI = 7800000, // average periodic
// refresh interval(ns)
parameter tRFC = 110000, // REF->ACT/REF delay (ns)
parameter tRP = 12500, // PRE cmd period (ns)
parameter tRRD = 10000, // ACT->ACT period (ns)
parameter tRTP = 7500, // Read->PRE cmd delay (ns)
parameter tWTR = 7500, // Internal write->read
// delay (ns)
parameter tZQCS = 64, // ZQCS cmd period (CKs)
parameter tZQI = 128_000_000 // ZQCS interval (ns)
)
(
// System inputs
input clk,
input rst,
// Physical memory slot presence
input [7:0] slot_0_present,
input [7:0] slot_1_present,
// Native Interface
input [2:0] cmd,
input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr,
input hi_priority,
input size,
input [BANK_WIDTH-1:0] bank,
input [COL_WIDTH-1:0] col,
input [RANK_WIDTH-1:0] rank,
input [ROW_WIDTH-1:0] row,
input use_addr,
input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data,
input [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask,
output accept,
output accept_ns,
output [BM_CNT_WIDTH-1:0] bank_mach_next,
output wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data,
output [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr,
output rd_data_en,
output rd_data_end,
output [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset,
output reg [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr,
output reg wr_data_en,
output reg [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset,
// ECC interface
input correct_en,
input [2*nCK_PER_CLK-1:0] raw_not_ecc,
output [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr,
output [2*nCK_PER_CLK-1:0] ecc_single,
output [2*nCK_PER_CLK-1:0] ecc_multiple,
// User maintenance requests
input app_periodic_rd_req,
input app_ref_req,
input app_zq_req,
// MC <==> PHY Interface
output reg [nCK_PER_CLK-1:0] mc_ras_n,
output reg [nCK_PER_CLK-1:0] mc_cas_n,
output reg [nCK_PER_CLK-1:0] mc_we_n,
output reg [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,
output reg [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,
output reg [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,
output wire mc_reset_n,
output wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata,
output wire [2*nCK_PER_CLK*DQ_WIDTH/8-1:0]mc_wrdata_mask,
output reg mc_wrdata_en,
output wire mc_cmd_wren,
output wire mc_ctl_wren,
output reg [2:0] mc_cmd,
output reg [5:0] mc_data_offset,
output reg [1:0] mc_cas_slot,
output reg [3:0] mc_aux_out0,
output reg [3:0] mc_aux_out1,
output reg [1:0] mc_rank_cnt,
input phy_mc_ctl_full,
input phy_mc_cmd_full,
input phy_mc_data_full,
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rd_data,
input phy_rddata_valid,
input init_calib_complete,
input [6*RANKS-1:0] calib_rd_data_offset
);
assign mc_reset_n = 1'b1; // never reset memory
assign mc_cmd_wren = 1'b1; // always write CMD FIFO(issue DSEL when idle)
assign mc_ctl_wren = 1'b1; // always write CTL FIFO(issue nondata when idle)
// Ensure there is always at least one rank present during operation
`ifdef MC_SVA
ranks_present: assert property
(@(posedge clk) (rst || (|(slot_0_present | slot_1_present))));
`endif
//***************************************************************************
// PHY, datapath, control, bus turnaround delay configuration
//***************************************************************************
localparam nWR_EN2CNFG_RD = 0; // write-enable -> read io_config delay
localparam nWR_EN2CNFG_WR = 0; // write-enable -> write io_config delay
localparam nCNFG2RD_EN = 0; // io_config -> read-enable delay
localparam nCNFG2WR = 0; // io_config -> write delay
localparam nRD_EN2CNFG_WR = 0; // read-enable -> write io_config delay
// Reserved. Do not change.
localparam nPHY_WRLAT = 2;
// always delay write data control unless ECC mode is enabled
localparam DELAY_WR_DATA_CNTRL = ECC == "ON" ? 0 : 1;
// Ensure that write control is delayed for appropriate CWL
/*`ifdef MC_SVA
delay_wr_data_zero_CWL_le_6: assert property
(@(posedge clk) ((CWL > 6) || (DELAY_WR_DATA_CNTRL == 0)));
`endif*/
// Never retrieve WR_DATA_ADDR early
localparam EARLY_WR_DATA_ADDR = "OFF";
//***************************************************************************
// Convert timing parameters from time to clock cycles
//***************************************************************************
localparam nRP = cdiv(tRP, tCK);
localparam nRCD = cdiv(tRCD, tCK);
localparam nRAS = cdiv(tRAS, tCK);
localparam nFAW = cdiv(tFAW, tCK);
localparam nRFC = cdiv(tRFC, tCK);
// Convert tWR. As per specification, write recover for autoprecharge
// cycles doesn't support values of 9 and 11. Round up 9 to 10 and 11 to 12
localparam nWR_CK = cdiv(15000, tCK) ;
localparam nWR = (nWR_CK == 9) ? 10 : (nWR_CK == 11) ? 12 : nWR_CK;
// tRRD, tWTR at tRTP have a 4 cycle floor in DDR3 and 2 cycle floor in DDR2
localparam nRRD_CK = cdiv(tRRD, tCK);
localparam nRRD = (DRAM_TYPE == "DDR3") ? (nRRD_CK < 4) ? 4 : nRRD_CK
: (nRRD_CK < 2) ? 2 : nRRD_CK;
localparam nWTR_CK = cdiv(tWTR, tCK);
localparam nWTR = (DRAM_TYPE == "DDR3") ? (nWTR_CK < 4) ? 4 : nWTR_CK
: (nWTR_CK < 2) ? 2 : nWTR_CK;
localparam nRTP_CK = cdiv(tRTP, tCK);
localparam nRTP = (DRAM_TYPE == "DDR3") ? (nRTP_CK < 4) ? 4 : nRTP_CK
: (nRTP_CK < 2) ? 2 : nRTP_CK;
// Add a cycle to CWL for the register in RDIMM devices
localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL;
//***************************************************************************
// Set up maintenance counter dividers
//***************************************************************************
// CK clock divisor to generate maintenance prescaler period (round down)
localparam MAINT_PRESCALER_DIV = MAINT_PRESCALER_PERIOD / (tCK*nCK_PER_CLK);
// Maintenance prescaler divisor for refresh timer. Essentially, this is
// just (tREFI / MAINT_PRESCALER_PERIOD), but we must account for the worst
// case delay from the time we get a tick from the refresh counter to the
// time that we can actually issue the REF command. Thus, subtract tRCD, CL,
// data burst time and tRP for each implemented bank machine to ensure that
// all transactions can complete before tREFI expires
localparam REFRESH_TIMER_DIV = (tREFI-((tRCD+((CL+4)*tCK)+tRP)*nBANK_MACHS))
/ MAINT_PRESCALER_PERIOD;
// Periodic read (RESERVED - not currently required or supported in 7 series)
// tPRDI should only be set to 0
localparam tPRDI = 0; // Do NOT change.
localparam PERIODIC_RD_TIMER_DIV = tPRDI / MAINT_PRESCALER_PERIOD;
// Convert maintenance prescaler from ps to ns
localparam MAINT_PRESCALER_PERIOD_NS = MAINT_PRESCALER_PERIOD / 1000;
// Maintenance prescaler divisor for ZQ calibration (ZQCS) timer
localparam ZQ_TIMER_DIV = tZQI / MAINT_PRESCALER_PERIOD_NS;
// Bus width required to broadcast a single bit rank signal among all the
// bank machines - 1 bit per rank, per bank
localparam RANK_BM_BV_WIDTH = nBANK_MACHS * RANKS;
//***************************************************************************
// Reserved feature control.
//***************************************************************************
// Open page wait mode is reserved.
// nOP_WAIT is the number of states a bank machine will park itself
// on an otherwise inactive open page before closing the page. If
// nOP_WAIT == 0, open page wait mode is disabled. If nOP_WAIT == -1,
// the bank machine will remain parked until the pool of idle bank machines
// are less than LOW_IDLE_CNT. At which point parked bank machines
// are selected to exit until the number of idle bank machines exceeds the
// LOW_IDLE_CNT.
localparam nOP_WAIT = 0; // Open page mode
localparam LOW_IDLE_CNT = 0; // Low idle bank machine threshold
//***************************************************************************
// Internal wires
//***************************************************************************
wire [RANK_BM_BV_WIDTH-1:0] act_this_rank_r;
wire [ROW_WIDTH-1:0] col_a;
wire [BANK_WIDTH-1:0] col_ba;
wire [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr;
wire col_periodic_rd;
wire [RANK_WIDTH-1:0] col_ra;
wire col_rmw;
wire col_rd_wr;
wire [ROW_WIDTH-1:0] col_row;
wire col_size;
wire [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr;
wire dq_busy_data;
wire ecc_status_valid;
wire [RANKS-1:0] inhbt_act_faw_r;
wire inhbt_rd_config;
wire [RANKS-1:0] inhbt_rd_r;
wire [RANKS-1:0] inhbt_wr_r;
wire inhbt_wr_config;
wire insert_maint_r1;
wire [RANK_WIDTH-1:0] maint_rank_r;
wire maint_req_r;
wire maint_wip_r;
wire maint_zq_r;
wire periodic_rd_ack_r;
wire periodic_rd_r;
wire [RANK_WIDTH-1:0] periodic_rd_rank_r;
wire [(RANKS*nBANK_MACHS)-1:0] rank_busy_r;
wire rd_rmw;
wire [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r;
wire [nBANK_MACHS-1:0] sending_col;
wire [nBANK_MACHS-1:0] sending_row;
wire sent_col;
wire wr_ecc_buf;
wire [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r;
wire [RANKS-1:0] wtr_inhbt_config_r;
// MC/PHY optional pipeline stage support
wire [nCK_PER_CLK-1:0] mc_ras_n_ns;
wire [nCK_PER_CLK-1:0] mc_cas_n_ns;
wire [nCK_PER_CLK-1:0] mc_we_n_ns;
wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address_ns;
wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank_ns;
wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n_ns;
wire [3:0] mc_aux_out0_ns;
wire [3:0] mc_aux_out1_ns;
wire [1:0] mc_rank_cnt_ns = col_ra;
wire [2:0] mc_cmd_ns;
wire [5:0] mc_data_offset_ns;
wire [1:0] mc_cas_slot_ns;
wire mc_wrdata_en_ns;
wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr_ns;
wire wr_data_en_ns;
wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset_ns;
wire [RANK_WIDTH:0] io_config_ns;
wire io_config_strobe_ns;
integer i;
//***************************************************************************
// Function cdiv
// Description:
// This function performs ceiling division (divide and round-up)
// Inputs:
// num: integer to be divided
// div: divisor
// Outputs:
// cdiv: result of ceiling division (num/div, rounded up)
//***************************************************************************
function integer cdiv (input integer num, input integer div);
begin
// perform division, then add 1 if and only if remainder is non-zero
cdiv = (num/div) + (((num%div)>0) ? 1 : 0);
end
endfunction // cdiv
//***************************************************************************
// Optional pipeline register stage on MC/PHY interface
//***************************************************************************
generate
if (CMD_PIPE_PLUS1 == "ON") begin : cmd_pipe_plus // register interface
always @(posedge clk) begin
mc_address <= #TCQ mc_address_ns;
mc_bank <= #TCQ mc_bank_ns;
mc_cas_n <= #TCQ mc_cas_n_ns;
mc_cs_n <= #TCQ mc_cs_n_ns;
mc_aux_out0 <= #TCQ mc_aux_out0_ns;
mc_aux_out1 <= #TCQ mc_aux_out1_ns;
mc_cmd <= #TCQ mc_cmd_ns;
mc_ras_n <= #TCQ mc_ras_n_ns;
mc_we_n <= #TCQ mc_we_n_ns;
mc_data_offset <= #TCQ mc_data_offset_ns;
mc_cas_slot <= #TCQ mc_cas_slot_ns;
mc_wrdata_en <= #TCQ mc_wrdata_en_ns;
mc_rank_cnt <= #TCQ mc_rank_cnt_ns;
wr_data_addr <= #TCQ wr_data_addr_ns;
wr_data_en <= #TCQ wr_data_en_ns;
wr_data_offset <= #TCQ wr_data_offset_ns;
end // always @ (posedge clk)
end // block: cmd_pipe_plus
else begin : cmd_pipe_plus0 // don't register interface
always @( mc_address or mc_aux_out0 or mc_aux_out1 or mc_bank or
mc_cas_n or mc_cmd or mc_cs_n or mc_data_offset or
mc_rank_cnt or mc_ras_n or mc_we_n or mc_wrdata_en or
wr_data_addr or wr_data_en or wr_data_offset)
begin
mc_address = #TCQ mc_address_ns;
mc_bank = #TCQ mc_bank_ns;
mc_cas_n = #TCQ mc_cas_n_ns;
mc_cs_n = #TCQ mc_cs_n_ns;
mc_aux_out0 = #TCQ mc_aux_out0_ns;
mc_aux_out1 = #TCQ mc_aux_out1_ns;
mc_cmd = #TCQ mc_cmd_ns;
mc_ras_n = #TCQ mc_ras_n_ns;
mc_we_n = #TCQ mc_we_n_ns;
mc_data_offset = #TCQ mc_data_offset_ns;
mc_cas_slot = #TCQ mc_cas_slot_ns;
mc_wrdata_en = #TCQ mc_wrdata_en_ns;
mc_rank_cnt = #TCQ mc_rank_cnt_ns;
wr_data_addr = #TCQ wr_data_addr_ns;
wr_data_en = #TCQ wr_data_en_ns;
wr_data_offset = #TCQ wr_data_offset_ns;
end // always @ (...
end // block: cmd_pipe_plus0
endgenerate
//***************************************************************************
// Manage rank-level timing and maintanence
//***************************************************************************
rank_mach #
(
// Parameters
.BURST_MODE (BURST_MODE),
.CL (CL),
.CWL (CWL),
.CS_WIDTH (CS_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.MAINT_PRESCALER_DIV (MAINT_PRESCALER_DIV),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nFAW (nFAW),
.nREFRESH_BANK (nREFRESH_BANK),
.nRRD (nRRD),
.nWTR (nWTR),
.PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV),
.RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.REFRESH_TIMER_DIV (REFRESH_TIMER_DIV),
.ZQ_TIMER_DIV (ZQ_TIMER_DIV)
)
rank_mach0
(
// Outputs
.inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]),
.inhbt_rd_r (inhbt_rd_r[RANKS-1:0]),
.inhbt_wr_r (inhbt_wr_r[RANKS-1:0]),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_req_r (maint_req_r),
.maint_zq_r (maint_zq_r),
.periodic_rd_r (periodic_rd_r),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
.wtr_inhbt_config_r (wtr_inhbt_config_r[RANKS-1:0]),
// Inputs
.act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.app_periodic_rd_req (app_periodic_rd_req),
.app_ref_req (app_ref_req),
.app_zq_req (app_zq_req),
.clk (clk),
.init_calib_complete (init_calib_complete),
.insert_maint_r1 (insert_maint_r1),
.maint_wip_r (maint_wip_r),
.periodic_rd_ack_r (periodic_rd_ack_r),
.rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]),
.rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.rst (rst),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]),
.wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0])
);
//***************************************************************************
// Manage requests, reordering and bank timing
//***************************************************************************
bank_mach#
(
// Parameters
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.COL_WIDTH (COL_WIDTH),
.CS_WIDTH (CS_WIDTH),
.CWL (CWL_M),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),
.ECC (ECC),
.LOW_IDLE_CNT (LOW_IDLE_CNT),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nCNFG2RD_EN (nCNFG2RD_EN),
.nCNFG2WR (nCNFG2WR),
.nCS_PER_RANK (nCS_PER_RANK),
.nOP_WAIT (nOP_WAIT),
.nRAS (nRAS),
.nRCD (nRCD),
.nRFC (nRFC),
.nRP (nRP),
.nRTP (nRTP),
.nSLOTS (nSLOTS),
.nWR (nWR),
.ORDERING (ORDERING),
.RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ROW_WIDTH (ROW_WIDTH),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.STARVE_LIMIT (STARVE_LIMIT),
.tZQCS (tZQCS)
)
bank_mach0
(
// Outputs
.accept (accept),
.accept_ns (accept_ns),
.act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.bank_mach_next (bank_mach_next[BM_CNT_WIDTH-1:0]),
.col_a (col_a[ROW_WIDTH-1:0]),
.col_ba (col_ba[BANK_WIDTH-1:0]),
.col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.col_periodic_rd (col_periodic_rd),
.col_ra (col_ra[RANK_WIDTH-1:0]),
.col_rmw (col_rmw),
.col_rd_wr (col_rd_wr),
.col_row (col_row[ROW_WIDTH-1:0]),
.col_size (col_size),
.col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.mc_bank (mc_bank_ns),
.mc_address (mc_address_ns),
.mc_ras_n (mc_ras_n_ns),
.mc_cas_n (mc_cas_n_ns),
.mc_we_n (mc_we_n_ns),
.mc_cs_n (mc_cs_n_ns),
.mc_aux_out0 (mc_aux_out0_ns),
.mc_aux_out1 (mc_aux_out1_ns),
.mc_cmd (mc_cmd_ns),
.mc_data_offset (mc_data_offset_ns),
.mc_cas_slot (mc_cas_slot_ns),
.insert_maint_r1 (insert_maint_r1),
.io_config (io_config_ns[RANK_WIDTH:0]),
.io_config_strobe (io_config_strobe_ns),
.maint_wip_r (maint_wip_r),
.periodic_rd_ack_r (periodic_rd_ack_r),
.rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]),
.rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.sent_col (sent_col),
.wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
// Inputs
.bank (bank[BANK_WIDTH-1:0]),
.calib_rddata_offset (calib_rd_data_offset[5:0]),
.clk (clk),
.cmd (cmd[2:0]),
.col (col[COL_WIDTH-1:0]),
.data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.init_calib_complete (init_calib_complete),
.phy_rddata_valid (phy_rddata_valid),
.dq_busy_data (dq_busy_data),
.hi_priority (hi_priority),
.inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]),
.inhbt_rd_config (inhbt_rd_config),
.inhbt_rd_r (inhbt_rd_r[RANKS-1:0]),
.inhbt_wr_r (inhbt_wr_r[RANKS-1:0]),
.inhbt_wr_config (inhbt_wr_config),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_req_r (maint_req_r),
.maint_zq_r (maint_zq_r),
.periodic_rd_r (periodic_rd_r),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
.rank (rank[RANK_WIDTH-1:0]),
.rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.rd_rmw (rd_rmw),
.row (row[ROW_WIDTH-1:0]),
.rst (rst),
.size (size),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]),
.use_addr (use_addr),
.wtr_inhbt_config_r (wtr_inhbt_config_r[RANKS-1:0])
);
//***************************************************************************
// Manage DQ bus
//***************************************************************************
col_mach #
(
// Parameters
.TCQ (TCQ),
.BANK_WIDTH (BANK_WIDTH),
.BURST_MODE (BURST_MODE),
.COL_WIDTH (COL_WIDTH),
.CS_WIDTH (CS_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH),
.DELAY_WR_DATA_CNTRL (DELAY_WR_DATA_CNTRL),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),
.ECC (ECC),
.MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.nPHY_WRLAT (nPHY_WRLAT),
.nRD_EN2CNFG_WR (nRD_EN2CNFG_WR),
.nWR_EN2CNFG_RD (nWR_EN2CNFG_RD),
.nWR_EN2CNFG_WR (nWR_EN2CNFG_WR),
.RANK_WIDTH (RANK_WIDTH),
.ROW_WIDTH (ROW_WIDTH)
)
col_mach0
(
// Outputs
.mc_wrdata_en (mc_wrdata_en_ns),
.dq_busy_data (dq_busy_data),
.ecc_err_addr (ecc_err_addr[MC_ERR_ADDR_WIDTH-1:0]),
.ecc_status_valid (ecc_status_valid),
.inhbt_rd_config (inhbt_rd_config),
.inhbt_wr_config (inhbt_wr_config),
.rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.rd_data_en (rd_data_en),
.rd_data_end (rd_data_end),
.rd_data_offset (rd_data_offset),
.rd_rmw (rd_rmw),
.wr_data_addr (wr_data_addr_ns),
.wr_data_en (wr_data_en_ns),
.wr_data_offset (wr_data_offset_ns),
.wr_ecc_buf (wr_ecc_buf),
// Inputs
.clk (clk),
.rst (rst),
.col_a (col_a[ROW_WIDTH-1:0]),
.col_ba (col_ba[BANK_WIDTH-1:0]),
.col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.col_periodic_rd (col_periodic_rd),
.col_ra (col_ra[RANK_WIDTH-1:0]),
.col_rmw (col_rmw),
.col_rd_wr (col_rd_wr),
.col_row (col_row[ROW_WIDTH-1:0]),
.col_size (col_size),
.col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.phy_rddata_valid (phy_rddata_valid),
.io_config (io_config_ns),
.sent_col (sent_col)
);
//***************************************************************************
// Implement ECC
//***************************************************************************
// Total ECC word length = ECC code width + Data width
localparam CODE_WIDTH = DATA_WIDTH + ECC_WIDTH;
generate
if (ECC == "OFF") begin : ecc_off
assign rd_data = phy_rd_data;
assign mc_wrdata = wr_data;
assign mc_wrdata_mask = wr_data_mask;
assign ecc_single = 4'b0;
assign ecc_multiple = 4'b0;
end
else begin : ecc_on
wire [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;
wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data;
// Merge and encode
ecc_merge_enc #
(
// Parameters
.TCQ (TCQ),
.CODE_WIDTH (CODE_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.ECC_WIDTH (ECC_WIDTH),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK)
)
ecc_merge_enc0
(
// Outputs
.mc_wrdata (mc_wrdata),
.mc_wrdata_mask (mc_wrdata_mask),
// Inputs
.clk (clk),
.rst (rst),
.h_rows (h_rows),
.rd_merge_data (rd_merge_data),
.raw_not_ecc (raw_not_ecc),
.wr_data (wr_data),
.wr_data_mask (wr_data_mask)
);
// Decode and fix
ecc_dec_fix #
(
// Parameters
.TCQ (TCQ),
.CODE_WIDTH (CODE_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.ECC_WIDTH (ECC_WIDTH),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK)
)
ecc_dec_fix0
(
// Outputs
.ecc_multiple (ecc_multiple),
.ecc_single (ecc_single),
.rd_data (rd_data),
// Inputs
.clk (clk),
.rst (rst),
.correct_en (correct_en),
.phy_rddata (phy_rd_data),
.ecc_status_valid (ecc_status_valid),
.h_rows (h_rows)
);
// ECC Buffer
ecc_buf #
(
// Parameters
.TCQ (TCQ),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK)
)
ecc_buf0
(
// Outputs
.rd_merge_data (rd_merge_data),
// Inputs
.clk (clk),
.rst (rst),
.rd_data (rd_data),
.rd_data_addr (rd_data_addr),
.rd_data_offset (rd_data_offset),
.wr_data_addr (wr_data_addr),
.wr_data_offset (wr_data_offset),
.wr_ecc_buf (wr_ecc_buf)
);
// Generate ECC table
ecc_gen #
(
// Parameters
.CODE_WIDTH (CODE_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.ECC_WIDTH (ECC_WIDTH)
)
ecc_gen0
(
// Outputs
.h_rows (h_rows)
);
`ifdef DISPLAY_H_MATRIX
integer i;
always @(negedge rst) begin
$display ("**********************************************");
$display ("H Matrix:");
for (i=0; i<ECC_WIDTH; i=i+1)
$display ("%b", h_rows[i*CODE_WIDTH+:CODE_WIDTH]);
$display ("**********************************************");
end
`endif
end
endgenerate
endmodule // mc
|
/*
* land2 - a verilog test for logical and operator && in boolean context
*
*
* Copyright (C) 1999 Stephen G. Tell
* Portions inspired by qmark.v by Steven Wilson ([email protected])
* Modified by SDW to self test.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this software; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 59 Temple Place, Suite 330,
* Boston, MA 02111-1307 USA
*/
module land2;
reg Clk;
reg a;
reg b;
reg c;
reg error;
wire q;
wire q_calc;
tand tand_m(q, q_calc, a, b, c);
initial Clk = 0;
always #10 Clk = ~Clk;
always @(posedge Clk)
begin
#1;
if(q != q_calc)
begin
$display("FAILED - expr && using %b%b%b is %b s/b %b",
a, b, c, q,q_calc);
error = 1;
end
end
reg [3:0] bvec;
integer xa;
integer xb;
integer xc;
initial begin
bvec = 4'bzx10 ;
error = 0;
for(xa = 0; xa <= 3; xa = xa + 1)
for(xb = 0; xb <= 3; xb = xb + 1)
for(xc = 0; xc <= 3; xc = xc + 1)
begin
@(posedge Clk)
a = bvec[xa];
b = bvec[xb];
c = bvec[xc];
end // for (var3 = 0; var3 <= 3; var3 = var3 + 1)
if(error == 0 ) $display("PASSED");
$finish;
end
endmodule
module tand(q, q_calc, a, b, c);
output q;
output q_calc;
input a;
input b;
input c;
wire q = ( (a===b) && (b===c) );
reg q_calc;
always @(a or b or c)
begin
if(a === b)
begin
if( b === c)
q_calc = 1'b1;
else
q_calc = 1'b0;
end
else
q_calc = 1'b0;
end
endmodule // foo
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2020 by Yutetsu TAKATSUKASA.
// SPDX-License-Identifier: CC0-1.0
logic [7:0] should_show_warning_global0 /* verilator split_var */;
logic [7:0] should_show_warning_global1 [1:0] /* verilator split_var */;
interface ifs;
logic [7:0] should_show_warning_ifs0 /* verilator split_var */;
logic [7:0] should_show_warning_ifs1 [1:0] /* verilator split_var */;
endinterface
module t();
// The following variables can not be splitted. will see warnings.
real should_show_warning0 /*verilator split_var*/;
string should_show_warning1 /*verilator split_var*/;
wire should_show_warning2 /*verilator split_var*/;
logic [3:0] addr;
logic [7:0] rd_data0, rd_data1, rd_data2;
logic [1:0] public_signal /*verilator public*/ /*verilator split_var*/;
sub0 i_sub0(.addr(addr), .rd_data(rd_data0));
sub1 i_sub1(.addr(addr), .rd_data(rd_data2));
sub2 i_sub2;
sub3 i_sub3;
ifs i_ifs();
function int bad_func(inout logic [3:0] inout_port /*verilator split_var*/,
ref logic [7:0] ref_port /*verilator split_var*/);
return 0;
endfunction
initial begin
logic [7:0] loop_idx /*verilator split_var*/;
addr = 0;
addr = 1;
i_sub0.cannot_split1[0] = 0;
i_sub0.cannot_split1[1] = bad_func(addr, rd_data0);
for (loop_idx = 0; loop_idx < 8'd4; loop_idx = loop_idx + 2) begin
addr += 1;
end
$finish;
end
endmodule
module sub0(input [3:0]addr, output logic [7:0] rd_data);
logic [7:0] cannot_split0[0:15] /*verilator split_var*/;
logic [7:0] cannot_split1[0:15] /*verilator split_var*/;
always_comb
rd_data = cannot_split0[addr];
endmodule
module sub1(input [3:0]addr, output logic [7:0] rd_data);
genvar cannot_split_genvar /*verilator split_var*/;
logic [15:0] [8:0] cannot_split /*verilator split_var*/;
always_comb begin
logic [8:0] rd_tmp /*verilator split_var*/ = cannot_split[addr];
rd_data = rd_tmp[{3'b0, addr[0]}+:8];
end
endmodule
module sub2; // from t_bitsel_wire_array_bad.v
// a and b are arrays of length 1.
wire a[0:0] /* verilator split_var */ ; // Array of nets
wire b[0:0] /* verilator split_var */ ;
assign a = 1'b0; // Only net assignment allowed
assign b = a[0]; // Only net assignment allowed
endmodule
module sub3; // from t_select_bad_range3.v
logic [7:0] inwires [12:10] /* verilator split_var */;
wire [7:0] outwires [12:10] /* verilator split_var */;
assign outwires[10] = inwires[11];
assign outwires[11] = inwires[12];
assign outwires[12] = inwires[13]; // must be an error here
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the ALU
// Import the modules that will be tested for in this testbench
`include "mult.v"
`include "control.h"
// IMPORTANT: To run this, try: ncverilog -f alu.f +gui
module tb_alu();
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the ALU
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// result output signal
wire [0:127] res;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// reg_A
reg [0:127] r_A;
// reg_B
reg [0:127] r_B;
// Control signal bits - ww; ctrl_ww
reg [0:1] c_ww;
/**
* Control signal bits - determine which arithmetic or logic
* operation to perform; alu_op
*/
reg [0:4] a_op;
// Bus/Signal to contain the expected output/result
reg [0:127] e_r;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
//parameter size_of_input = 6'd32;
// ============================================================
/**
* Instantiate an instance of alu() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "rg"
*/
alu a_l_u (
// instance_name(signal name),
// Signal name can be the same as the instance name
// alu (reg_A,reg_B,ctrl_ppp,ctrl_ww,alu_op,result)
r_A,r_B,c_ww,a_op,res);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
// aluwmuleu AND w8
/*
r_A=31'h0402050f;
r_B=31'h0301020c;
e_r=31'h000c0006;
c_ww=`w8;
a_op=`aluwmuleu;
*/
r_A=128'h0402030405060708f00a0b0cff0eff00;
r_B=128'h03010202030303031004f505ff09fe10;
e_r=128'h000c0006000f00150f000a87fe01fd02;
c_ww=`w8;
a_op=`aluwmuleu;
#10
// aluwmuleu AND w16
r_A=128'h000100020000ffff000f10bff103ffff;
r_B=128'h000200040006ffff000c100000120014;
e_r=128'h0000000200000000000000b40010f236;
c_ww=`w16;
a_op=`aluwmuleu;
// ======================================
#10
// aluwmulou AND w8
r_A=128'h0102030405060708090aff0c0dff0fff;
r_B=128'h01010202030303031004040508000fff;
e_r=128'h00020008001200180028003c0000fe01;
c_ww=`w8;
a_op=`aluwmulou;
#10
// aluwmulou AND w16
r_A=128'h0001000200000008000f10bff103ffff;
r_B=128'h0002000400060008000c001000120014;
e_r=128'h000000080000004000010bf00013ffec;
c_ww=`w16;
a_op=`aluwmulou;
// ======================================
#10
// aluwmulos AND w8
/*
r_A=128'h010330405060708090aff0c0dff0ff02;
r_B=128'h01fa0202030303031004040508000f08;
*/
r_A=128'h0180010501f9015301040100013c0100;
r_B=128'h017f010901fa010001fd01f101b80100;
e_r=128'hc080002d002a0000fff40000ef200000;
c_ww=`w8;
a_op=`aluwmulos;
#10
// aluwmulos AND w16
r_A=128'h1111000211118000111120541111fff9;
r_B=128'hffff0004ffff7fffffff0000fffffffd;
e_r=128'h00000008c00080000000000000000015;
c_ww=`w16;
a_op=`aluwmulos;
// ======================================
#10
// aluwmules AND w8
/*
r_A=128'h0180010501f9015301040100013c0100;
r_B=128'h017f010901fa010001fd01f101b80100;
*/
r_A=128'h80010501f9015301040100013c010001;
r_B=128'h7f010901fa010001fd01f101b8010001;
e_r=128'hc080002d002a0000fff40000ef200000;
c_ww=`w8;
a_op=`aluwmules;
#10
// aluwmules AND w16
/*
r_A=128'h1111000211118000111120541111fff9;
r_B=128'hffff0004ffff7fffffff0000fffffffd;
*/
r_A=128'h000211118000111120541111fff91111;
r_B=128'h0004ffff7fffffff0000fffffffdffff;
e_r=128'h00000008c00080000000000000000015;
c_ww=`w16;
a_op=`aluwmules;
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XOR2_FUNCTIONAL_V
`define SKY130_FD_SC_HS__XOR2_FUNCTIONAL_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__xor2 (
VPWR,
VGND,
X ,
A ,
B
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
input B ;
// Local signals
wire xor0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , B, A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__XOR2_FUNCTIONAL_V |
/***************************************************************************************************
** fpga_nes/hw/src/cpu/apu/apu_pulse.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* APU noise channel.
***************************************************************************************************/
`timescale 1ps / 1ps
module apu_pulse
#(
parameter [0:0] CHANNEL = 1'b0 // Pulse channel 0 or 1
)
(
input wire clk_in, // system clock signal
input wire rst_in, // reset signal
input wire en_in, // enable (via $4015)
input wire cpu_cycle_pulse_in, // 1 clk pulse on every cpu cycle
input wire lc_pulse_in, // 1 clk pulse for every length counter decrement
input wire eg_pulse_in, // 1 clk pulse for every env gen update
input wire [1:0] a_in, // control register addr (i.e. $400C - $400F)
input wire [7:0] d_in, // control register write value
input wire wr_in, // enable control register write
output wire [3:0] pulse_out, // pulse channel output
output wire active_out // pulse channel active (length counter > 0)
);
//
// Envelope
//
wire envelope_generator_wr;
wire envelope_generator_restart;
wire [3:0] envelope_generator_out;
apu_envelope_generator envelope_generator(
.clk_in(clk_in),
.rst_in(rst_in),
.eg_pulse_in(eg_pulse_in),
.env_in(d_in[5:0]),
.env_wr_in(envelope_generator_wr),
.env_restart(envelope_generator_restart),
.env_out(envelope_generator_out)
);
assign envelope_generator_wr = wr_in && (a_in == 2'b00);
assign envelope_generator_restart = wr_in && (a_in == 2'b11);
//
// Timer
//
reg [10:0] q_timer_period, d_timer_period;
wire timer_pulse;
always @(posedge clk_in)
begin
if (rst_in)
q_timer_period <= 11'h000;
else
q_timer_period <= d_timer_period;
end
apu_div #(.PERIOD_BITS(12)) timer(
.clk_in(clk_in),
.rst_in(rst_in),
.pulse_in(cpu_cycle_pulse_in),
.reload_in(1'b0),
.period_in({ q_timer_period, 1'b0 }),
.pulse_out(timer_pulse)
);
//
// Sequencer
//
wire [3:0] sequencer_out;
reg [1:0] q_duty;
wire [1:0] d_duty;
reg [2:0] q_sequencer_cnt;
wire [2:0] d_sequencer_cnt;
wire seq_bit;
always @(posedge clk_in)
begin
if (rst_in)
begin
q_duty <= 2'h0;
q_sequencer_cnt <= 3'h0;
end
else
begin
q_duty <= d_duty;
q_sequencer_cnt <= d_sequencer_cnt;
end
end
assign d_duty = (wr_in && (a_in == 2'b00)) ? d_in[7:6] : q_duty;
assign d_sequencer_cnt = (timer_pulse) ? q_sequencer_cnt - 3'h1 : q_sequencer_cnt;
assign seq_bit = (q_duty == 2'h0) ? &q_sequencer_cnt[2:0] :
(q_duty == 2'h1) ? &q_sequencer_cnt[2:1] :
(q_duty == 2'h2) ? q_sequencer_cnt[2] : ~&q_sequencer_cnt[2:1];
assign sequencer_out = (seq_bit) ? envelope_generator_out : 4'h0;
//
// Sweep
//
reg q_sweep_reload;
wire d_sweep_reload;
reg [7:0] q_sweep_reg;
wire [7:0] d_sweep_reg;
always @(posedge clk_in)
begin
if (rst_in)
begin
q_sweep_reg <= 8'h00;
q_sweep_reload <= 1'b0;
end
else
begin
q_sweep_reg <= d_sweep_reg;
q_sweep_reload <= d_sweep_reload;
end
end
assign d_sweep_reg = (wr_in && (a_in == 2'b01)) ? d_in : q_sweep_reg;
assign d_sweep_reload = (wr_in && (a_in == 2'b01)) ? 1'b1 :
(lc_pulse_in) ? 1'b0 : q_sweep_reload;
wire sweep_divider_reload;
wire sweep_divider_pulse;
reg sweep_silence;
reg [11:0] sweep_target_period;
apu_div #(.PERIOD_BITS(3)) sweep_divider(
.clk_in(clk_in),
.rst_in(rst_in),
.pulse_in(lc_pulse_in),
.reload_in(sweep_divider_reload),
.period_in(q_sweep_reg[6:4]),
.pulse_out(sweep_divider_pulse)
);
assign sweep_divider_reload = lc_pulse_in & q_sweep_reload;
always @*
begin
sweep_target_period =
(!q_sweep_reg[3]) ? q_timer_period + (q_timer_period >> q_sweep_reg[2:0]) :
q_timer_period + ~(q_timer_period >> q_sweep_reg[2:0]) + CHANNEL;
sweep_silence = (q_timer_period[10:3] == 8'h00) || sweep_target_period[11];
if (wr_in && (a_in == 2'b10))
d_timer_period = { q_timer_period[10:8], d_in };
else if (wr_in && (a_in == 2'b11))
d_timer_period = { d_in[2:0], q_timer_period[7:0] };
else if (sweep_divider_pulse && q_sweep_reg[7] && !sweep_silence && (q_sweep_reg[2:0] != 3'h0))
d_timer_period = sweep_target_period[10:0];
else
d_timer_period = q_timer_period;
end
//
// Length Counter
//
reg q_length_counter_halt;
wire d_length_counter_halt;
always @(posedge clk_in)
begin
if (rst_in)
begin
q_length_counter_halt <= 1'b0;
end
else
begin
q_length_counter_halt <= d_length_counter_halt;
end
end
assign d_length_counter_halt = (wr_in && (a_in == 2'b00)) ? d_in[5] : q_length_counter_halt;
wire length_counter_wr;
wire length_counter_en;
apu_length_counter length_counter(
.clk_in(clk_in),
.rst_in(rst_in),
.en_in(en_in),
.halt_in(q_length_counter_halt),
.length_pulse_in(lc_pulse_in),
.length_in(d_in[7:3]),
.length_wr_in(length_counter_wr),
.en_out(length_counter_en)
);
assign length_counter_wr = wr_in && (a_in == 2'b11);
assign pulse_out = (length_counter_en && !sweep_silence) ? sequencer_out : 4'h0;
assign active_out = length_counter_en;
endmodule
|
`include "defines.v"
`include "HRnode.v"
`timescale 1ns/1ps
/*module HRnode
#(parameter addr = 4'b0010)
(
input `control_w port0_i,
input `control_w port1_i,
input `control_w port0_local_i,
input `control_w port1_local_i,
output portl0_ack,
output portl1_ack,
input clk,
input rst,
output `control_w port0_o,
output `control_w port1_o,
output `control_w port0_local_o,
output `control_w port1_local_o
);*/
module tb(
);
wire ack0, ack1;
reg clk, rst;
reg `control_w flit0c, flit1c, flitl0, flitl1;
wire `control_w port0_co, port1_co, portl0_co, portl1_co;
HRnode r(
.clk(clk),
.rst(rst),
.port0_i(flit0c), .port0_o(port0_co),
.port1_i(flit1c), .port1_o(port1_co),
.port0_local_i(flitl0), .port0_local_o(portl0_co),
.port1_local_i(flitl1), .port1_local_o(portl1_co),
.portl0_ack(ack0), .portl1_ack(ack1)
);
initial begin
//$set_toggle_region(tb.r);
//$toggle_start();
clk = 0;
rst = 0;
flit0c = 144'h0123456789abcdef0123456789abcdef1852;
flit1c = 144'h0123456789abcdef0123456789abcdef1852;
flitl0 = 144'h0123456789abcdef0123456789abcdef1855;
flitl1 = 144'h0123456789abcdef0123456789abcdef1851;
#1;
clk = 1;
#1;
clk = 0;
$display("clk = %d\n, port0 %04x\n, port1 %04x\n, portl0_co %04x\n, portl1_co %04x\n, portl0_ack %04x\n, portl1_ack %04x\n",
clk, port0_co, port1_co, portl0_co, portl1_co, ack0, ack1);
//$toggle_stop();
//$toggle_report("./calf_backward_1.saif", 1.0e-9, "tb.r");
//$finish;
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_b2s.v
//
// Description:
// To handle AXI4 transactions to external memory on Virtex-6 architectures
// requires a bridge to convert the AXI4 transactions to the memory
// controller(MC) user interface. The MC user interface has bidirectional
// data path and supports data width of 256/128/64/32 bits.
// The bridge is designed to allow AXI4 IP masters to communicate with
// the MC user interface.
//
//
// Specifications:
// AXI4 Slave Side:
// Configurable data width of 32, 64, 128, 256
// Read acceptance depth is:
// Write acceptance depth is:
//
// Structure:
// axi_protocol_converter_v2_1_b2s
// WRITE_BUNDLE
// aw_channel_0
// cmd_translator_0
// rd_cmd_fsm_0
// w_channel_0
// b_channel_0
// READ_BUNDLE
// ar_channel_0
// cmd_translator_0
// rd_cmd_fsm_0
// r_channel_0
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s #(
parameter C_S_AXI_PROTOCOL = 0,
// Width of all master and slave ID signals.
// Range: >= 1.
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 30,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire aclk ,
input wire aresetn ,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr ,
input wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [2:0] s_axi_awsize ,
input wire [1:0] s_axi_awburst ,
input wire [2:0] s_axi_awprot ,
input wire s_axi_awvalid ,
output wire s_axi_awready ,
// Slave Interface Write Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata ,
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb ,
input wire s_axi_wlast ,
input wire s_axi_wvalid ,
output wire s_axi_wready ,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid ,
output wire [1:0] s_axi_bresp ,
output wire s_axi_bvalid ,
input wire s_axi_bready ,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr ,
input wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [2:0] s_axi_arsize ,
input wire [1:0] s_axi_arburst ,
input wire [2:0] s_axi_arprot ,
input wire s_axi_arvalid ,
output wire s_axi_arready ,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid ,
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata ,
output wire [1:0] s_axi_rresp ,
output wire s_axi_rlast ,
output wire s_axi_rvalid ,
input wire s_axi_rready ,
// Slave Interface Write Address Ports
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr ,
output wire [2:0] m_axi_awprot ,
output wire m_axi_awvalid ,
input wire m_axi_awready ,
// Slave Interface Write Data Ports
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata ,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb ,
output wire m_axi_wvalid ,
input wire m_axi_wready ,
// Slave Interface Write Response Ports
input wire [1:0] m_axi_bresp ,
input wire m_axi_bvalid ,
output wire m_axi_bready ,
// Slave Interface Read Address Ports
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr ,
output wire [2:0] m_axi_arprot ,
output wire m_axi_arvalid ,
input wire m_axi_arready ,
// Slave Interface Read Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata ,
input wire [1:0] m_axi_rresp ,
input wire m_axi_rvalid ,
output wire m_axi_rready
);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
reg areset_d1;
always @(posedge aclk)
areset_d1 <= ~aresetn;
// AW/W/B channel internal communication
wire b_push;
wire [C_AXI_ID_WIDTH-1:0] b_awid;
wire [7:0] b_awlen;
wire b_full;
wire [C_AXI_ID_WIDTH-1:0] si_rs_awid;
wire [C_AXI_ADDR_WIDTH-1:0] si_rs_awaddr;
wire [8-1:0] si_rs_awlen;
wire [3-1:0] si_rs_awsize;
wire [2-1:0] si_rs_awburst;
wire [3-1:0] si_rs_awprot;
wire si_rs_awvalid;
wire si_rs_awready;
wire [C_AXI_DATA_WIDTH-1:0] si_rs_wdata;
wire [C_AXI_DATA_WIDTH/8-1:0] si_rs_wstrb;
wire si_rs_wlast;
wire si_rs_wvalid;
wire si_rs_wready;
wire [C_AXI_ID_WIDTH-1:0] si_rs_bid;
wire [2-1:0] si_rs_bresp;
wire si_rs_bvalid;
wire si_rs_bready;
wire [C_AXI_ID_WIDTH-1:0] si_rs_arid;
wire [C_AXI_ADDR_WIDTH-1:0] si_rs_araddr;
wire [8-1:0] si_rs_arlen;
wire [3-1:0] si_rs_arsize;
wire [2-1:0] si_rs_arburst;
wire [3-1:0] si_rs_arprot;
wire si_rs_arvalid;
wire si_rs_arready;
wire [C_AXI_ID_WIDTH-1:0] si_rs_rid;
wire [C_AXI_DATA_WIDTH-1:0] si_rs_rdata;
wire [2-1:0] si_rs_rresp;
wire si_rs_rlast;
wire si_rs_rvalid;
wire si_rs_rready;
wire [C_AXI_ADDR_WIDTH-1:0] rs_mi_awaddr;
wire rs_mi_awvalid;
wire rs_mi_awready;
wire [C_AXI_DATA_WIDTH-1:0] rs_mi_wdata;
wire [C_AXI_DATA_WIDTH/8-1:0] rs_mi_wstrb;
wire rs_mi_wvalid;
wire rs_mi_wready;
wire [2-1:0] rs_mi_bresp;
wire rs_mi_bvalid;
wire rs_mi_bready;
wire [C_AXI_ADDR_WIDTH-1:0] rs_mi_araddr;
wire rs_mi_arvalid;
wire rs_mi_arready;
wire [C_AXI_DATA_WIDTH-1:0] rs_mi_rdata;
wire [2-1:0] rs_mi_rresp;
wire rs_mi_rvalid;
wire rs_mi_rready;
axi_register_slice_v2_1_axi_register_slice #(
.C_AXI_PROTOCOL ( C_S_AXI_PROTOCOL ) ,
.C_AXI_ID_WIDTH ( C_AXI_ID_WIDTH ) ,
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_AXI_DATA_WIDTH ( C_AXI_DATA_WIDTH ) ,
.C_AXI_SUPPORTS_USER_SIGNALS ( 0 ) ,
.C_AXI_AWUSER_WIDTH ( 1 ) ,
.C_AXI_ARUSER_WIDTH ( 1 ) ,
.C_AXI_WUSER_WIDTH ( 1 ) ,
.C_AXI_RUSER_WIDTH ( 1 ) ,
.C_AXI_BUSER_WIDTH ( 1 ) ,
.C_REG_CONFIG_AW ( 1 ) ,
.C_REG_CONFIG_AR ( 1 ) ,
.C_REG_CONFIG_W ( 0 ) ,
.C_REG_CONFIG_R ( 1 ) ,
.C_REG_CONFIG_B ( 1 )
) SI_REG (
.aresetn ( aresetn ) ,
.aclk ( aclk ) ,
.s_axi_awid ( s_axi_awid ) ,
.s_axi_awaddr ( s_axi_awaddr ) ,
.s_axi_awlen ( s_axi_awlen ) ,
.s_axi_awsize ( s_axi_awsize ) ,
.s_axi_awburst ( s_axi_awburst ) ,
.s_axi_awlock ( {((C_S_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}} ) ,
.s_axi_awcache ( 4'h0 ) ,
.s_axi_awprot ( s_axi_awprot ) ,
.s_axi_awqos ( 4'h0 ) ,
.s_axi_awuser ( 1'b0 ) ,
.s_axi_awvalid ( s_axi_awvalid ) ,
.s_axi_awready ( s_axi_awready ) ,
.s_axi_awregion ( 4'h0 ) ,
.s_axi_wid ( {C_AXI_ID_WIDTH{1'b0}} ) ,
.s_axi_wdata ( s_axi_wdata ) ,
.s_axi_wstrb ( s_axi_wstrb ) ,
.s_axi_wlast ( s_axi_wlast ) ,
.s_axi_wuser ( 1'b0 ) ,
.s_axi_wvalid ( s_axi_wvalid ) ,
.s_axi_wready ( s_axi_wready ) ,
.s_axi_bid ( s_axi_bid ) ,
.s_axi_bresp ( s_axi_bresp ) ,
.s_axi_buser ( ) ,
.s_axi_bvalid ( s_axi_bvalid ) ,
.s_axi_bready ( s_axi_bready ) ,
.s_axi_arid ( s_axi_arid ) ,
.s_axi_araddr ( s_axi_araddr ) ,
.s_axi_arlen ( s_axi_arlen ) ,
.s_axi_arsize ( s_axi_arsize ) ,
.s_axi_arburst ( s_axi_arburst ) ,
.s_axi_arlock ( {((C_S_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}} ) ,
.s_axi_arcache ( 4'h0 ) ,
.s_axi_arprot ( s_axi_arprot ) ,
.s_axi_arqos ( 4'h0 ) ,
.s_axi_aruser ( 1'b0 ) ,
.s_axi_arvalid ( s_axi_arvalid ) ,
.s_axi_arready ( s_axi_arready ) ,
.s_axi_arregion ( 4'h0 ) ,
.s_axi_rid ( s_axi_rid ) ,
.s_axi_rdata ( s_axi_rdata ) ,
.s_axi_rresp ( s_axi_rresp ) ,
.s_axi_rlast ( s_axi_rlast ) ,
.s_axi_ruser ( ) ,
.s_axi_rvalid ( s_axi_rvalid ) ,
.s_axi_rready ( s_axi_rready ) ,
.m_axi_awid ( si_rs_awid ) ,
.m_axi_awaddr ( si_rs_awaddr ) ,
.m_axi_awlen ( si_rs_awlen[((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] ) ,
.m_axi_awsize ( si_rs_awsize ) ,
.m_axi_awburst ( si_rs_awburst ) ,
.m_axi_awlock ( ) ,
.m_axi_awcache ( ) ,
.m_axi_awprot ( si_rs_awprot ) ,
.m_axi_awqos ( ) ,
.m_axi_awuser ( ) ,
.m_axi_awvalid ( si_rs_awvalid ) ,
.m_axi_awready ( si_rs_awready ) ,
.m_axi_awregion ( ) ,
.m_axi_wid ( ) ,
.m_axi_wdata ( si_rs_wdata ) ,
.m_axi_wstrb ( si_rs_wstrb ) ,
.m_axi_wlast ( si_rs_wlast ) ,
.m_axi_wuser ( ) ,
.m_axi_wvalid ( si_rs_wvalid ) ,
.m_axi_wready ( si_rs_wready ) ,
.m_axi_bid ( si_rs_bid ) ,
.m_axi_bresp ( si_rs_bresp ) ,
.m_axi_buser ( 1'b0 ) ,
.m_axi_bvalid ( si_rs_bvalid ) ,
.m_axi_bready ( si_rs_bready ) ,
.m_axi_arid ( si_rs_arid ) ,
.m_axi_araddr ( si_rs_araddr ) ,
.m_axi_arlen ( si_rs_arlen[((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] ) ,
.m_axi_arsize ( si_rs_arsize ) ,
.m_axi_arburst ( si_rs_arburst ) ,
.m_axi_arlock ( ) ,
.m_axi_arcache ( ) ,
.m_axi_arprot ( si_rs_arprot ) ,
.m_axi_arqos ( ) ,
.m_axi_aruser ( ) ,
.m_axi_arvalid ( si_rs_arvalid ) ,
.m_axi_arready ( si_rs_arready ) ,
.m_axi_arregion ( ) ,
.m_axi_rid ( si_rs_rid ) ,
.m_axi_rdata ( si_rs_rdata ) ,
.m_axi_rresp ( si_rs_rresp ) ,
.m_axi_rlast ( si_rs_rlast ) ,
.m_axi_ruser ( 1'b0 ) ,
.m_axi_rvalid ( si_rs_rvalid ) ,
.m_axi_rready ( si_rs_rready )
);
generate
if (C_AXI_SUPPORTS_WRITE == 1) begin : WR
axi_protocol_converter_v2_1_b2s_aw_channel #
(
.C_ID_WIDTH ( C_AXI_ID_WIDTH ),
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
)
aw_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.s_awid ( si_rs_awid ) ,
.s_awaddr ( si_rs_awaddr ) ,
.s_awlen ( (C_S_AXI_PROTOCOL == 1) ? {4'h0,si_rs_awlen[3:0]} : si_rs_awlen),
.s_awsize ( si_rs_awsize ) ,
.s_awburst ( si_rs_awburst ) ,
.s_awvalid ( si_rs_awvalid ) ,
.s_awready ( si_rs_awready ) ,
.m_awvalid ( rs_mi_awvalid ) ,
.m_awaddr ( rs_mi_awaddr ) ,
.m_awready ( rs_mi_awready ) ,
.b_push ( b_push ) ,
.b_awid ( b_awid ) ,
.b_awlen ( b_awlen ) ,
.b_full ( b_full )
);
axi_protocol_converter_v2_1_b2s_b_channel #
(
.C_ID_WIDTH ( C_AXI_ID_WIDTH )
)
b_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.s_bid ( si_rs_bid ) ,
.s_bresp ( si_rs_bresp ) ,
.s_bvalid ( si_rs_bvalid ) ,
.s_bready ( si_rs_bready ) ,
.m_bready ( rs_mi_bready ) ,
.m_bvalid ( rs_mi_bvalid ) ,
.m_bresp ( rs_mi_bresp ) ,
.b_push ( b_push ) ,
.b_awid ( b_awid ) ,
.b_awlen ( b_awlen ) ,
.b_full ( b_full ) ,
.b_resp_rdy ( si_rs_awready )
);
end else begin : NO_WR
assign rs_mi_awaddr = {C_AXI_ADDR_WIDTH{1'b0}};
assign rs_mi_awvalid = 1'b0;
assign si_rs_awready = 1'b0;
assign rs_mi_wdata = {C_AXI_DATA_WIDTH{1'b0}};
assign rs_mi_wstrb = {C_AXI_DATA_WIDTH/8{1'b0}};
assign rs_mi_wvalid = 1'b0;
assign si_rs_wready = 1'b0;
assign rs_mi_bready = 1'b0;
assign si_rs_bvalid = 1'b0;
assign si_rs_bresp = 2'b00;
assign si_rs_bid = {C_AXI_ID_WIDTH{1'b0}};
end
endgenerate
// AR/R channel communication
wire r_push ;
wire [C_AXI_ID_WIDTH-1:0] r_arid ;
wire r_rlast ;
wire r_full ;
generate
if (C_AXI_SUPPORTS_READ == 1) begin : RD
axi_protocol_converter_v2_1_b2s_ar_channel #
(
.C_ID_WIDTH ( C_AXI_ID_WIDTH ),
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
)
ar_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.s_arid ( si_rs_arid ) ,
.s_araddr ( si_rs_araddr ) ,
.s_arlen ( (C_S_AXI_PROTOCOL == 1) ? {4'h0,si_rs_arlen[3:0]} : si_rs_arlen),
.s_arsize ( si_rs_arsize ) ,
.s_arburst ( si_rs_arburst ) ,
.s_arvalid ( si_rs_arvalid ) ,
.s_arready ( si_rs_arready ) ,
.m_arvalid ( rs_mi_arvalid ) ,
.m_araddr ( rs_mi_araddr ) ,
.m_arready ( rs_mi_arready ) ,
.r_push ( r_push ) ,
.r_arid ( r_arid ) ,
.r_rlast ( r_rlast ) ,
.r_full ( r_full )
);
axi_protocol_converter_v2_1_b2s_r_channel #
(
.C_ID_WIDTH ( C_AXI_ID_WIDTH ),
.C_DATA_WIDTH ( C_AXI_DATA_WIDTH )
)
r_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.s_rid ( si_rs_rid ) ,
.s_rdata ( si_rs_rdata ) ,
.s_rresp ( si_rs_rresp ) ,
.s_rlast ( si_rs_rlast ) ,
.s_rvalid ( si_rs_rvalid ) ,
.s_rready ( si_rs_rready ) ,
.m_rvalid ( rs_mi_rvalid ) ,
.m_rready ( rs_mi_rready ) ,
.m_rdata ( rs_mi_rdata ) ,
.m_rresp ( rs_mi_rresp ) ,
.r_push ( r_push ) ,
.r_full ( r_full ) ,
.r_arid ( r_arid ) ,
.r_rlast ( r_rlast )
);
end else begin : NO_RD
assign rs_mi_araddr = {C_AXI_ADDR_WIDTH{1'b0}};
assign rs_mi_arvalid = 1'b0;
assign si_rs_arready = 1'b0;
assign si_rs_rlast = 1'b1;
assign si_rs_rdata = {C_AXI_DATA_WIDTH{1'b0}};
assign si_rs_rvalid = 1'b0;
assign si_rs_rresp = 2'b00;
assign si_rs_rid = {C_AXI_ID_WIDTH{1'b0}};
assign rs_mi_rready = 1'b0;
end
endgenerate
axi_register_slice_v2_1_axi_register_slice #(
.C_AXI_PROTOCOL ( 2 ) ,
.C_AXI_ID_WIDTH ( 1 ) ,
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_AXI_DATA_WIDTH ( C_AXI_DATA_WIDTH ) ,
.C_AXI_SUPPORTS_USER_SIGNALS ( 0 ) ,
.C_AXI_AWUSER_WIDTH ( 1 ) ,
.C_AXI_ARUSER_WIDTH ( 1 ) ,
.C_AXI_WUSER_WIDTH ( 1 ) ,
.C_AXI_RUSER_WIDTH ( 1 ) ,
.C_AXI_BUSER_WIDTH ( 1 ) ,
.C_REG_CONFIG_AW ( 0 ) ,
.C_REG_CONFIG_AR ( 0 ) ,
.C_REG_CONFIG_W ( 0 ) ,
.C_REG_CONFIG_R ( 0 ) ,
.C_REG_CONFIG_B ( 0 )
) MI_REG (
.aresetn ( aresetn ) ,
.aclk ( aclk ) ,
.s_axi_awid ( 1'b0 ) ,
.s_axi_awaddr ( rs_mi_awaddr ) ,
.s_axi_awlen ( 8'h00 ) ,
.s_axi_awsize ( 3'b000 ) ,
.s_axi_awburst ( 2'b01 ) ,
.s_axi_awlock ( 1'b0 ) ,
.s_axi_awcache ( 4'h0 ) ,
.s_axi_awprot ( si_rs_awprot ) ,
.s_axi_awqos ( 4'h0 ) ,
.s_axi_awuser ( 1'b0 ) ,
.s_axi_awvalid ( rs_mi_awvalid ) ,
.s_axi_awready ( rs_mi_awready ) ,
.s_axi_awregion ( 4'h0 ) ,
.s_axi_wid ( 1'b0 ) ,
.s_axi_wdata ( si_rs_wdata ) ,
.s_axi_wstrb ( si_rs_wstrb ) ,
.s_axi_wlast ( 1'b1 ) ,
.s_axi_wuser ( 1'b0 ) ,
.s_axi_wvalid ( si_rs_wvalid ) ,
.s_axi_wready ( si_rs_wready ) ,
.s_axi_bid ( ) ,
.s_axi_bresp ( rs_mi_bresp ) ,
.s_axi_buser ( ) ,
.s_axi_bvalid ( rs_mi_bvalid ) ,
.s_axi_bready ( rs_mi_bready ) ,
.s_axi_arid ( 1'b0 ) ,
.s_axi_araddr ( rs_mi_araddr ) ,
.s_axi_arlen ( 8'h00 ) ,
.s_axi_arsize ( 3'b000 ) ,
.s_axi_arburst ( 2'b01 ) ,
.s_axi_arlock ( 1'b0 ) ,
.s_axi_arcache ( 4'h0 ) ,
.s_axi_arprot ( si_rs_arprot ) ,
.s_axi_arqos ( 4'h0 ) ,
.s_axi_aruser ( 1'b0 ) ,
.s_axi_arvalid ( rs_mi_arvalid ) ,
.s_axi_arready ( rs_mi_arready ) ,
.s_axi_arregion ( 4'h0 ) ,
.s_axi_rid ( ) ,
.s_axi_rdata ( rs_mi_rdata ) ,
.s_axi_rresp ( rs_mi_rresp ) ,
.s_axi_rlast ( ) ,
.s_axi_ruser ( ) ,
.s_axi_rvalid ( rs_mi_rvalid ) ,
.s_axi_rready ( rs_mi_rready ) ,
.m_axi_awid ( ) ,
.m_axi_awaddr ( m_axi_awaddr ) ,
.m_axi_awlen ( ) ,
.m_axi_awsize ( ) ,
.m_axi_awburst ( ) ,
.m_axi_awlock ( ) ,
.m_axi_awcache ( ) ,
.m_axi_awprot ( m_axi_awprot ) ,
.m_axi_awqos ( ) ,
.m_axi_awuser ( ) ,
.m_axi_awvalid ( m_axi_awvalid ) ,
.m_axi_awready ( m_axi_awready ) ,
.m_axi_awregion ( ) ,
.m_axi_wid ( ) ,
.m_axi_wdata ( m_axi_wdata ) ,
.m_axi_wstrb ( m_axi_wstrb ) ,
.m_axi_wlast ( ) ,
.m_axi_wuser ( ) ,
.m_axi_wvalid ( m_axi_wvalid ) ,
.m_axi_wready ( m_axi_wready ) ,
.m_axi_bid ( 1'b0 ) ,
.m_axi_bresp ( m_axi_bresp ) ,
.m_axi_buser ( 1'b0 ) ,
.m_axi_bvalid ( m_axi_bvalid ) ,
.m_axi_bready ( m_axi_bready ) ,
.m_axi_arid ( ) ,
.m_axi_araddr ( m_axi_araddr ) ,
.m_axi_arlen ( ) ,
.m_axi_arsize ( ) ,
.m_axi_arburst ( ) ,
.m_axi_arlock ( ) ,
.m_axi_arcache ( ) ,
.m_axi_arprot ( m_axi_arprot ) ,
.m_axi_arqos ( ) ,
.m_axi_aruser ( ) ,
.m_axi_arvalid ( m_axi_arvalid ) ,
.m_axi_arready ( m_axi_arready ) ,
.m_axi_arregion ( ) ,
.m_axi_rid ( 1'b0 ) ,
.m_axi_rdata ( m_axi_rdata ) ,
.m_axi_rresp ( m_axi_rresp ) ,
.m_axi_rlast ( 1'b1 ) ,
.m_axi_ruser ( 1'b0 ) ,
.m_axi_rvalid ( m_axi_rvalid ) ,
.m_axi_rready ( m_axi_rready )
);
endmodule
`default_nettype wire
|
module main(CLOCK_50, KEY, LEDR, SW, UART_RXD, UART_TXD);
input CLOCK_50;
input KEY[3:0];
output [17:0] LEDR;
input [17:0] SW;
input UART_RXD;
output UART_TXD;
integer i;
// Regs
reg [7:0] current_value, value_into_genetico;
reg [10:0] current_circuit_les[8:0];
reg [3:0] current_circuit_outs[1:0];
// Wires
wire [31:0] data_to_send, rs232_received_data;
wire [7:0] mem_out, genetico_out;
wire rx_done, tx_done, tx_send, start_sampling, start_sending, mem_write,
finished_sampling, finished_sending, mem_addr, fetch_value, serial_reset,
insert_value, done_receiving, set_current_circuit;
wire [15:0] sampler_mem_addr, sender_mem_addr;
wire [7:0] received_data[199:0];
assign LEDR[7:0] = current_value;
assign LEDR[17:10] = genetico_out;
assign data_to_send = {24'b0, mem_out};
always @(posedge CLOCK_50) begin
if (fetch_value)
current_value <= received_data[1];
if (insert_value)
value_into_genetico <= current_value;
if (set_current_circuit) begin
for (i = 0; i < 9; i = i + 1) begin
current_circuit_les[i][10:8] <= received_data[(i * 3) + 1][2:0];
current_circuit_les[i][7:4] <= received_data[(i * 3) + 2][3:0];
current_circuit_les[i][3:0] <= received_data[(i * 3) + 3][3:0];
end
for (i = 0; i < 2; i = i + 1) begin
current_circuit_outs[i] <= received_data[i + 27 + 1][3:0];
end
end
end
sampler sampler(
.iClock(CLOCK_50),
.iReset(~KEY[1]),
.iStartSignal(start_sampling),
.oAddress(sampler_mem_addr),
.oFinished(finished_sampling)
);
sender sender(
.iClock(CLOCK_50),
.iReset(~KEY[1]),
.iTxDone(tx_done),
.iStartSignal(start_sending),
.oAddress(sender_mem_addr),
.oFinished(finished_sending),
.oTxSend(tx_send)
);
main_fsm fsm(
.iClock(CLOCK_50),
.iReset(~KEY[1]),
.iDoneReceiving(done_receiving),
.iReceivedData(received_data),
.iSamplingDone(finished_sampling),
.iSendingDone(finished_sending),
.oMemWrite(mem_write),
.oMemAddr(mem_addr),
.oStartSampling(start_sampling),
.oStartSending(start_sending),
.oFetchValue(fetch_value),
.oSetCurrentCircuit(set_current_circuit),
.oInsertValue(insert_value),
.oResetSerial(serial_reset)
);
memoria memoria(
.address(mem_addr ? sender_mem_addr : sampler_mem_addr),
.clock(CLOCK_50),
.data(genetico_out),
.wren(mem_write),
.q(mem_out)
);
data_receiver data_receiver(
.iClock(CLOCK_50),
.iReset(~KEY[1]),
.iRxDone(rx_done),
.iReceivedData(rs232_received_data),
.oResultData(received_data),
.oDoneReceiving(done_receiving)
);
uart rs232(
.sys_clk(CLOCK_50),
.sys_rst(~KEY[1] | serial_reset),
.csr_a(14'b0),
.csr_we(tx_send),
.csr_di(data_to_send),
.csr_do(rs232_received_data),
.rx_irq(rx_done),
.tx_irq(tx_done),
.uart_rx(UART_RXD),
.uart_tx(UART_TXD)
);
genetico genetico(
.conf_les(current_circuit_les),
.conf_outs(current_circuit_outs),
.in(value_into_genetico),
.out(genetico_out)
);
endmodule |
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the users design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// 503-286-8001 (other locations)
//
// web: http://www.latticesemi.com/
// email: [email protected]
//
// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_adder.v
// Title : Integer adder / subtractor with comparison flag generation
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
`include "lm32_include.v"
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_adder (
// ----- Inputs -------
adder_op_x,
adder_op_x_n,
operand_0_x,
operand_1_x,
// ----- Outputs -------
adder_result_x,
adder_carry_n_x,
adder_overflow_x
);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input adder_op_x; // Operating to perform, 0 for addition, 1 for subtraction
input adder_op_x_n; // Inverted version of adder_op_x
input [`LM32_WORD_RNG] operand_0_x; // Operand to add, or subtract from
input [`LM32_WORD_RNG] operand_1_x; // Opearnd to add, or subtract by
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output [`LM32_WORD_RNG] adder_result_x; // Result of addition or subtraction
wire [`LM32_WORD_RNG] adder_result_x;
output adder_carry_n_x; // Inverted carry
wire adder_carry_n_x;
output adder_overflow_x; // Indicates if overflow occured, only valid for subtractions
reg adder_overflow_x;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
wire a_sign; // Sign (i.e. positive or negative) of operand 0
wire b_sign; // Sign of operand 1
wire result_sign; // Sign of result
/////////////////////////////////////////////////////
// Instantiations
/////////////////////////////////////////////////////
lm32_addsub addsub (
// ----- Inputs -----
.DataA (operand_0_x),
.DataB (operand_1_x),
.Cin (adder_op_x),
.Add_Sub (adder_op_x_n),
// ----- Ouputs -----
.Result (adder_result_x),
.Cout (adder_carry_n_x)
);
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
// Extract signs of operands and result
assign a_sign = operand_0_x[`LM32_WORD_WIDTH-1];
assign b_sign = operand_1_x[`LM32_WORD_WIDTH-1];
assign result_sign = adder_result_x[`LM32_WORD_WIDTH-1];
// Determine whether an overflow occured when performing a subtraction
always @(*)
begin
// +ve - -ve = -ve -> overflow
// -ve - +ve = +ve -> overflow
if ( (!a_sign & b_sign & result_sign)
|| (a_sign & !b_sign & !result_sign)
)
adder_overflow_x = `TRUE;
else
adder_overflow_x = `FALSE;
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: iodelay_ctrl.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// This module instantiates the IDELAYCTRL primitive, which continously
// calibrates the IODELAY elements in the region to account for varying
// environmental conditions. A 200MHz or 300MHz reference clock (depending
// on the desired IODELAY tap resolution) must be supplied
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: iodelay_ctrl.v,v 1.1 2011/06/02 08:34:56 mishra Exp $
**$Date: 2011/06/02 08:34:56 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/clocking/iodelay_ctrl.v,v $
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v2_3_iodelay_ctrl #
(
parameter TCQ = 100,
// clk->out delay (sim only)
parameter IODELAY_GRP0 = "IODELAY_MIG0",
// May be assigned unique name when
// multiple IP cores used in design
parameter IODELAY_GRP1 = "IODELAY_MIG1",
// May be assigned unique name when
// multiple IP cores used in design
parameter REFCLK_TYPE = "DIFFERENTIAL",
// Reference clock type
// "DIFFERENTIAL","SINGLE_ENDED"
// NO_BUFFER, USE_SYSTEM_CLOCK
parameter SYSCLK_TYPE = "DIFFERENTIAL",
// input clock type
// DIFFERENTIAL, SINGLE_ENDED,
// NO_BUFFER
parameter SYS_RST_PORT = "FALSE",
// "TRUE" - if pin is selected for sys_rst
// and IBUF will be instantiated.
// "FALSE" - if pin is not selected for sys_rst
parameter RST_ACT_LOW = 1,
// Reset input polarity
// (0 = active high, 1 = active low)
parameter DIFF_TERM_REFCLK = "TRUE",
// Differential Termination
parameter FPGA_SPEED_GRADE = 1,
// FPGA speed grade
parameter REF_CLK_MMCM_IODELAY_CTRL = "FALSE"
)
(
input clk_ref_p,
input clk_ref_n,
input clk_ref_i,
input sys_rst,
output [1:0] clk_ref,
output sys_rst_o,
output [1:0] iodelay_ctrl_rdy
);
// # of clock cycles to delay deassertion of reset. Needs to be a fairly
// high number not so much for metastability protection, but to give time
// for reset (i.e. stable clock cycles) to propagate through all state
// machines and to all control signals (i.e. not all control signals have
// resets, instead they rely on base state logic being reset, and the effect
// of that reset propagating through the logic). Need this because we may not
// be getting stable clock cycles while reset asserted (i.e. since reset
// depends on DCM lock status)
// COMMENTED, RC, 01/13/09 - causes pack error in MAP w/ larger #
localparam RST_SYNC_NUM = 15;
// localparam RST_SYNC_NUM = 25;
wire clk_ref_ibufg;
wire clk_ref_mmcm_300;
wire clk_ref_mmcm_400;
wire mmcm_clkfbout;
wire mmcm_Locked;
wire [1:0] rst_ref;
reg [RST_SYNC_NUM-1:0] rst_ref_sync_r [1:0] /* synthesis syn_maxfan = 10 */;
wire rst_tmp_idelay;
wire sys_rst_act_hi;
//***************************************************************************
// If the pin is selected for sys_rst in GUI, IBUF will be instantiated.
// If the pin is not selected in GUI, sys_rst signal is expected to be
// driven internally.
generate
if (SYS_RST_PORT == "TRUE")
IBUF u_sys_rst_ibuf
(
.I (sys_rst),
.O (sys_rst_o)
);
else
assign sys_rst_o = sys_rst;
endgenerate
// Possible inversion of system reset as appropriate
assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst_o: sys_rst_o;
//***************************************************************************
// 1) Input buffer for IDELAYCTRL reference clock - handle either a
// differential or single-ended input. Global clock buffer is used to
// drive the rest of FPGA logic.
// 2) For NO_BUFFER option, Reference clock will be driven from internal
// clock i.e., clock is driven from fabric. Input buffers and Global
// clock buffers will not be instaitaed.
// 3) For USE_SYSTEM_CLOCK, input buffer output of system clock will be used
// as the input reference clock. Global clock buffer is used to drive
// the rest of FPGA logic.
//***************************************************************************
generate
if (REFCLK_TYPE == "DIFFERENTIAL") begin: diff_clk_ref
IBUFGDS #
(
.DIFF_TERM (DIFF_TERM_REFCLK),
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_clk_ref
(
.I (clk_ref_p),
.IB (clk_ref_n),
.O (clk_ref_ibufg)
);
end else if (REFCLK_TYPE == "SINGLE_ENDED") begin : se_clk_ref
IBUFG #
(
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_clk_ref
(
.I (clk_ref_i),
.O (clk_ref_ibufg)
);
end else if ((REFCLK_TYPE == "NO_BUFFER") ||
(REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE == "NO_BUFFER")) begin : clk_ref_noibuf_nobuf
assign clk_ref_ibufg = clk_ref_i;
end else if (REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE != "NO_BUFFER") begin : clk_ref_noibuf
assign clk_ref_ibufg = clk_ref_i;
end
endgenerate
// reference clock 300MHz and 400MHz generation with MMCM
generate
if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin: clk_ref_mmcm_gen
MMCME2_ADV
#(.BANDWIDTH ("HIGH"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("INTERNAL"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (6),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (4),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (3),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (5),
.REF_JITTER1 (0.000))
mmcm_i
// Output clocks
(.CLKFBOUT (mmcm_clkfbout),
.CLKFBOUTB (),
.CLKOUT0 (clk_ref_mmcm_300),
.CLKOUT0B (),
.CLKOUT1 (clk_ref_mmcm_400),
.CLKOUT1B (),
.CLKOUT2 (),
.CLKOUT2B (),
.CLKOUT3 (),
.CLKOUT3B (),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKOUT6 (),
// Input clock control
.CLKFBIN (mmcm_clkfbout),
.CLKIN1 (clk_ref_ibufg),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (),
.DRDY (),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (mmcm_Locked),
.CLKINSTOPPED (),
.CLKFBSTOPPED (),
.PWRDWN (1'b0),
.RST (sys_rst_act_hi));
end
endgenerate
generate
if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin : clk_ref_300_400_en
if(FPGA_SPEED_GRADE == 1) begin: clk_ref_300
BUFG u_bufg_clk_ref_300
(
.O (clk_ref[1]),
.I (clk_ref_mmcm_300)
);
end else if (FPGA_SPEED_GRADE == 2 || FPGA_SPEED_GRADE == 3) begin: clk_ref_400
BUFG u_bufg_clk_ref_400
(
.O (clk_ref[1]),
.I (clk_ref_mmcm_400)
);
end
end
endgenerate
generate
if ((REFCLK_TYPE == "DIFFERENTIAL") ||
(REFCLK_TYPE == "SINGLE_ENDED") ||
(REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE != "NO_BUFFER")) begin: clk_ref_200
BUFG u_bufg_clk_ref
(
.O (clk_ref[0]),
.I (clk_ref_ibufg)
);
end else begin: clk_ref_200_no_buffer
assign clk_ref[0] = clk_ref_i;
end
endgenerate
//*****************************************************************
// IDELAYCTRL reset
// This assumes an external clock signal driving the IDELAYCTRL
// blocks. Otherwise, if a PLL drives IDELAYCTRL, then the PLL
// lock signal will need to be incorporated in this.
//*****************************************************************
// Add PLL lock if PLL drives IDELAYCTRL in user design
assign rst_tmp_idelay = sys_rst_act_hi;
generate
if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin: rst_ref_gen_1
always @(posedge clk_ref[1] or posedge rst_tmp_idelay)
if (rst_tmp_idelay)
rst_ref_sync_r[1] <= #TCQ {RST_SYNC_NUM{1'b1}};
else
rst_ref_sync_r[1] <= #TCQ rst_ref_sync_r[1] << 1;
assign rst_ref[1] = rst_ref_sync_r[1][RST_SYNC_NUM-1];
end
endgenerate
always @(posedge clk_ref[0] or posedge rst_tmp_idelay)
if (rst_tmp_idelay)
rst_ref_sync_r[0] <= #TCQ {RST_SYNC_NUM{1'b1}};
else
rst_ref_sync_r[0] <= #TCQ rst_ref_sync_r[0] << 1;
assign rst_ref[0] = rst_ref_sync_r[0][RST_SYNC_NUM-1];
//*****************************************************************
generate
if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin: idelayctrl_gen_1
(* IODELAY_GROUP = IODELAY_GRP1 *) IDELAYCTRL u_idelayctrl_300_400
(
.RDY (iodelay_ctrl_rdy[1]),
.REFCLK (clk_ref[1]),
.RST (rst_ref[1])
);
end
endgenerate
(* IODELAY_GROUP = IODELAY_GRP0 *) IDELAYCTRL u_idelayctrl_200
(
.RDY (iodelay_ctrl_rdy[0]),
.REFCLK (clk_ref[0]),
.RST (rst_ref[0])
);
endmodule
|
module wb_data_resize
#(parameter aw = 32, //Address width
parameter mdw = 32, //Master Data Width
parameter sdw = 8) //Slave Data Width
(//Wishbone Master interface
input [aw-1:0] wbm_adr_i,
input [mdw-1:0] wbm_dat_i,
input [3:0] wbm_sel_i,
input wbm_we_i,
input wbm_cyc_i,
input wbm_stb_i,
input [2:0] wbm_cti_i,
input [1:0] wbm_bte_i,
output [mdw-1:0] wbm_dat_o,
output wbm_ack_o,
output wbm_err_o,
output wbm_rty_o,
// Wishbone Slave interface
output [aw-1:0] wbs_adr_o,
output [sdw-1:0] wbs_dat_o,
output wbs_we_o,
output wbs_cyc_o,
output wbs_stb_o,
output [2:0] wbs_cti_o,
output [1:0] wbs_bte_o,
input [sdw-1:0] wbs_dat_i,
input wbs_ack_i,
input wbs_err_i,
input wbs_rty_i);
assign wbs_adr_o[aw-1:2] = wbm_adr_i[aw-1:2];
assign wbs_adr_o[1:0] = wbm_sel_i[3] ? 2'd0 :
wbm_sel_i[2] ? 2'd1 :
wbm_sel_i[1] ? 2'd2 : 2'd3;
assign wbs_dat_o = wbm_sel_i[3] ? wbm_dat_i[31:24] :
wbm_sel_i[2] ? wbm_dat_i[23:16] :
wbm_sel_i[1] ? wbm_dat_i[15:8] :
wbm_sel_i[0] ? wbm_dat_i[7:0] : 8'b0;
assign wbs_we_o = wbm_we_i;
assign wbs_cyc_o = wbm_cyc_i;
assign wbs_stb_o = wbm_stb_i;
assign wbs_cti_o = wbm_cti_i;
assign wbs_bte_o = wbm_bte_i;
assign wbm_dat_o = (wbm_sel_i[3]) ? {wbs_dat_i, 24'd0} :
(wbm_sel_i[2]) ? {8'd0 , wbs_dat_i, 16'd0} :
(wbm_sel_i[1]) ? {16'd0, wbs_dat_i, 8'd0} :
{24'd0, wbs_dat_i};
assign wbm_ack_o = wbs_ack_i;
assign wbm_err_o = wbs_err_i;
assign wbm_rty_o = wbs_rty_i;
endmodule
|
Require Export Ch10_Smallstep.
Inductive Sec : Type :=
| L : Sec
| H : Sec.
Inductive Ty : Type :=
| an : RawTy -> Sec -> Ty
with RawTy : Type :=
| int : RawTy
| fn : Ty -> Sec -> Ty -> RawTy
| unit : RawTy
| ref : Ty -> RawTy.
Scheme Ty_mut := Induction for Ty Sort Prop
with RawTy_ := Induction for RawTy Sort Prop.
(*###subtyping###*)
Inductive subsum_r : Sec -> Sec -> Prop :=
| sub_refl: forall b : Sec,
subsum_r b b
| sub_LH: subsum_r L H
.
Lemma subsum_r_trans: forall a b c,
subsum_r a b ->
subsum_r b c ->
subsum_r a c.
Proof. intros. inversion H0. subst. inversion H1. subst.
apply sub_refl. apply sub_LH. destruct c. apply sub_refl.
apply sub_LH.
Qed.
Reserved Notation "T '<:' U" (at level 40).
Inductive subtyping : Ty -> Ty -> Prop :=
| subt_int: forall b b',
subsum_r b b' ->
(an int b) <: (an int b')
| subt_fn: forall b b' pc pc' T1 T1' T2 T2',
subsum_r b b' ->
subsum_r pc' pc ->
T1' <: T1 ->
T2 <: T2' ->
(an (fn T1 pc T2) b) <: (an (fn T1' pc' T2') b')
| subt_unit: forall b b',
subsum_r b b' ->
(an unit b) <: (an unit b')
| subt_ref: forall b b' T,
subsum_r b b' ->
(an (ref T) b) <: (an (ref T) b')
where "t1 '<:' t2" := (subtyping t1 t2).
Lemma subtyping_refl: forall T,
T <: T.
Proof. apply (Ty_mut (fun T => T <: T) (fun RT => forall b, (an RT b) <: (an RT b))).
intros. apply H0.
intros. apply subt_int. apply sub_refl.
intros. apply subt_fn. apply sub_refl. apply sub_refl. apply H0. apply H1.
intros. apply subt_unit. apply sub_refl.
intros. apply subt_ref. apply sub_refl.
Qed.
Lemma subtyping_trans: forall y z x z',
x <: y -> z <: x -> y <: z' -> z <: z'.
Proof. intros. generalize dependent z. generalize dependent z'. induction H0.
Case ("int").
intros. inversion H2. subst. inversion H1. subst. apply subt_int. apply subsum_r_trans with (a:=b0)(b:=b)(c:=b')in H6.
apply subsum_r_trans with (a:=b0)(b:=b')(c:=b'0) in H6. apply H6. apply H4. apply H0.
Case ("fn").
intros. inversion H2. subst. inversion H3. subst.
apply subt_fn. apply subsum_r_trans with (a:=b0)(b:=b)(c:=b') in H13.
apply subsum_r_trans with (a:=b0)(b:=b')(c:=b'0) in H13. apply H13. apply H8. apply H0.
apply subsum_r_trans with (a:=pc'0)(b:=pc')(c:=pc)in H10. apply subsum_r_trans with (a:=pc'0)(b:=pc)(c:=pc0)in H10.
apply H10. apply H14. apply H1.
apply IHsubtyping1. apply H15. apply H11.
apply IHsubtyping2. apply H12. apply H16.
Case ("unit").
intros. inversion H1. subst. inversion H2. subst. apply subt_unit.
apply subsum_r_trans with (a:=b0)(b:=b)(c:=b')in H5. apply subsum_r_trans with (a:=b0)(b:=b')(c:=b'0)in H5.
apply H5. apply H4. apply H0.
Case ("ref").
intros. inversion H2. inversion H1. subst. apply subt_ref.
apply subsum_r_trans with (a:=b1)(b:=b)(c:=b')in H9. apply subsum_r_trans with (a:=b1)(b:=b')(c:=b'0)in H9.
apply H9. apply H6. apply H0.
Qed.
(*variable environment*)
(*############typing context############*)
Definition context := id -> option Ty.
Definition empty_context : context :=
fun _ => None.
Definition Cupdate (St : context) (X:id) (T : option Ty) : context :=
fun X' => if beq_id X X' then T else St X'.
(*#######some useful theorems regarding [Cupdate]#########*)
Theorem Cupdate_eq : forall T X St,
(Cupdate St X T) X = T.
Proof.
intros. unfold Cupdate. rewrite<-beq_id_refl. reflexivity.
Qed.
Theorem Cupdate_neq : forall X2 X1 T St,
beq_id X2 X1 = false ->
(Cupdate St X2 T) X1 = (St X1).
Proof.
intros. unfold Cupdate. rewrite H0. reflexivity.
Qed.
Theorem Cupdate_shadow : forall T1 T2 X1 X2 (f : context),
(Cupdate (Cupdate f X2 T1) X2 T2) X1 = (Cupdate f X2 T2) X1.
Proof.
intros. unfold Cupdate. destruct (beq_id X2 X1). reflexivity.
reflexivity.
Qed.
Theorem Cupdate_same : forall T1 X1 X2 (f : context),
f X1 = T1 ->
(Cupdate f X1 T1) X2 = f X2.
Proof.
intros. unfold Cupdate. remember (beq_id X1 X2) as D. destruct D.
Case ("true"). apply beq_id_eq in HeqD. subst. reflexivity.
reflexivity.
Qed.
Theorem Cupdate_permute : forall T1 T2 X1 X2 X3 f,
beq_id X2 X1 = false ->
(Cupdate (Cupdate f X2 T1) X1 T2) X3 = (Cupdate (Cupdate f X1 T2) X2 T1) X3.
Proof.
intros. unfold Cupdate. remember (beq_id X1 X3) as D1. remember (beq_id X2 X3) as D2.
destruct D1.
Case ("D1=true"). destruct D2.
SCase ("D2=true"). apply beq_id_false_not_eq in H0. apply beq_id_eq in HeqD1.
apply beq_id_eq in HeqD2. rewrite<-HeqD2 in HeqD1.
unfold not in H0. symmetry in HeqD1. apply H0 in HeqD1.
inversion HeqD1.
SCase ("D2=false"). reflexivity.
Case ("D1=false"). destruct D2.
SCase ("D2=true"). reflexivity.
SCase ("D2=false"). reflexivity.
Qed.
(*end typing context*)
(*heap_Ty*)
Definition heap_Ty := list Ty.
Fixpoint heap_Tlookup (n:nat)(ht:heap_Ty): option Ty :=
match ht , n with
| nil , _ => None (*default return*)
| h::t , 0 => Some h
| h::t , S n' =>heap_Tlookup n' t
end.
(*end heap_Ty*)
(*functional extensionality*)
Axiom functional_extensionality : forall {X Y: Type} {f g : X -> Y},
(forall (x: X), f x = g x) -> f = g.
(*end*)
Module SecLang.
(*syntax*)
Inductive tm : Type :=
| tvar : id -> tm
| tprot : Sec -> tm -> tm
| tcon : nat -> Sec -> tm
| tabs : id -> Ty -> tm -> Sec -> tm
| tapp : tm -> tm -> tm
(*#####new terms######*)
| tunit : Sec -> tm
| tref : Ty -> tm -> Sec -> tm (*[Ty] as the initial type*)
| tderef : tm -> tm
| tloc : Ty -> option nat -> Sec -> tm(*[Ty] as the "access type"*)
(**
Note that regarding the type of the referred location in [tloc] we use
[option nat] instead of [nat]
*)
| tassign : tm -> tm -> tm.
(*values*)
(*###values###*)
Inductive value : tm -> Prop :=
| v_c : forall b n,
value (tcon n b)
| v_f : forall n T e b,
value (tabs (Id n) T e b)
| v_u : forall b,
value (tunit b)
| v_l : forall n T b,
value (tloc T (Some n) b).
(*###heaps###*)
Definition heap := list (tm*Ty).
Definition emp_hp:= @nil (tm*Ty).
(*###some useful functions###*)
(*###lookup function and some lemmas###*)
Fixpoint heap_lookup (n:nat)(st:heap):(option (tm*Ty)):=
match st , n with
| nil , _ =>None
| h::t , 0 => Some h
| h::t , S n' =>heap_lookup n' t
end.
(*extract the result of [heap_lookup]*)
Definition efst (p:option(tm*Ty)) : tm :=
match p with
| None => tvar (Id 100)
| Some (t , T) => t
end.
Definition esnd (p:option(tm*Ty)) : Ty :=
match p with
| None => an unit L
| Some (t, T) => T
end.
Fixpoint snoc {A:Type} (l:list A) (x:A) : list A :=
match l with
| nil => x :: nil
| h :: t => h :: snoc t x
end.
Lemma length_snoc:forall A (l:list A) x,
length (snoc l x) = S (length l).
Proof.
intros. generalize dependent x. induction l.
Case ("nil"). intros. simpl. reflexivity.
Case ("h::t"). intros. simpl. specialize (IHl x). rewrite->IHl.
reflexivity.
Qed.
Lemma lt_snoc_1 : forall n m,
S n <= S m -> n <= m.
Proof.
intros n m. generalize dependent n. induction m as [|m'].
Case ("m=0"). intros. destruct n as [|n'].
SCase ("n=0"). apply le_n.
SCase ("n=S n'"). inversion H0. inversion H2.
Case ("m=S m'"). intros. inversion H0. apply le_n. apply le_S.
apply IHm'. apply H2.
Qed.
Lemma lt_snoc: forall (l:heap) x (n:nat),
n < length l ->
heap_lookup n l = heap_lookup n (snoc l x).
Proof.
intros l. induction l.
Case ("nil"). intros. simpl in H0. inversion H0.
Case ("h::t"). intros. simpl. destruct n. reflexivity. simpl.
apply IHl. simpl in H0. apply lt_snoc_1 in H0.
apply H0.
Qed.
Lemma eq_snoc: forall (l:heap) x,
heap_lookup (length l) (snoc l x) = Some x.
Proof.
intros l. induction l.
Case ("nil"). intros. simpl. reflexivity.
Case ("h::t"). intros. simpl. specialize (IHl x).
apply IHl.
Qed.
(*###replace function and some lemmas###*)
Fixpoint heap_replace n x (l:heap): heap :=
match l , n with
| nil , _ =>nil
| h::t , 0 => x::t
| h::t , S n' =>h :: (heap_replace n' x t)
end.
Lemma replace_nil: forall n x,
heap_replace n x nil = nil.
Proof.
intros. destruct n. simpl. reflexivity. simpl. reflexivity. Qed.
Lemma length_replace: forall n x (l:heap),
length (heap_replace n x l) = length l.
Proof.
intros. generalize dependent n. generalize dependent x. induction l.
Case ("nil"). intros. simpl. rewrite->replace_nil. simpl. reflexivity.
Case ("h::t"). intros. simpl. destruct n. simpl. reflexivity.
simpl. specialize (IHl x n). rewrite->IHl. reflexivity.
Qed.
Lemma lookup_replace_eq: forall l t st,
l < length st ->
heap_lookup l (heap_replace l t st) = Some t.
Proof.
intros. generalize dependent l. generalize dependent t.
induction st.
Case ("nil"). intros. destruct l. simpl in H0. inversion H0. simpl in H0. inversion H0.
Case ("h::t"). intros. destruct l. simpl. reflexivity.
simpl. apply IHst. simpl in H0. unfold lt. unfold lt in H0.
apply lt_snoc_1 in H0. apply H0.
Qed.
Lemma lookup_replace_neq: forall l1 l2 t st,
l1 <> l2 ->
heap_lookup l1 (heap_replace l2 t st) = heap_lookup l1 st.
Proof.
intros. generalize dependent l1. generalize dependent l2. generalize dependent t.
induction st.
Case ("nil"). intros. rewrite->replace_nil. reflexivity.
Case ("h::t"). intros. destruct l2. destruct l1. simpl. assert (0=0). reflexivity.
apply H0 in H1. inversion H1. simpl. reflexivity. simpl.
destruct l1. reflexivity. apply IHst.
intros T. assert (l1 = l2 -> S l1 = S l2). intros. subst. reflexivity.
apply H1 in T. apply H0 in T. inversion T.
Qed.
(*###########*)
(*###end heap###*)
(*###substitution###*)
Fixpoint subst (x:id) (s:tm) (t:tm): tm :=
match t with
(*variables*)
| tvar x' =>
if beq_id x x' then s else t
(*protects*)
| tprot b t' =>
tprot b (subst x s t')
(*abstractions*)
| tabs x' T t1 b =>
tabs x' T (if beq_id x x' then t1 else (subst x s t1)) b
(*constants*)
| tcon n b => tcon n b
(*applications*)
| tapp t1 t2 =>
tapp (subst x s t1) (subst x s t2)
(*units*)
| tunit b => tunit b
(*tref*)
| tref T t1 b => tref T (subst x s t1) b
(*tderef*)
| tderef t1 => tderef (subst x s t1)
(*tloc*)
| tloc T N b => tloc T N b
(*assignments*)
| tassign t1 t2 => tassign (subst x s t1)(subst x s t2)
end.
Notation "'[' x ':=' s ']' t" := (subst x s t) (at level 20).
(*###reduction relation###*)
(*###"join" functions###*)
Definition joins (b1:Sec) (b2:Sec): Sec :=
match b1 with
| L => b2
| H => H
end.
Fixpoint joinVS (T:tm) (b:Sec): option tm :=
match T , b with
| tvar x , _ => None
| tprot b e , _ => None
| tcon n b , L => Some (tcon n b)
| tcon n b , H => Some (tcon n H)
| tabs x T e b , L => Some (tabs x T e b)
| tabs x T e b , H => Some (tabs x T e H)
| tapp t1 t2 , _ => None
| tunit b , L => Some (tunit b)
| tunit b , H => Some (tunit H)
| tref T e b , _ => None
| tderef e , _ => None
| tloc T N b , L => Some (tloc T N b)
| tloc T N b , H => Some (tloc T N H)
| tassign t1 t2 , _ => None
end.
(*############*)
Definition extract (t:option Ty) : Ty :=
match t with
| Some T => T
| None => an unit L (*default type*)
end.
(*############*)
Definition extractT (t:option tm) : tm :=
match t with
| Some e => e
| None => tvar (Id 100)
end.
Definition joinvs (T:tm) (b:Sec): tm :=
extractT (joinVS T b).
Definition joinTs (T:Ty)(b:Sec) : Ty :=
match T , b with
| an rt s , L => an rt s
| an rt s , H => an rt H
end.
(*"get-label" functions*)
Fixpoint Label (t:tm) : option Sec :=
match t with
| tvar x => None
| tprot H t => Some H
| tprot L t => Label t
| tcon n b => Some b
| tabs x T e b => Some b
| tapp t1 t2 => None
| tunit b => Some b
| tref T e b => None
| tderef e => None
| tloc T N b => Some b
| tassign t1 t2 => None
end.
Definition eLabel (s:option Sec) : Sec :=
match s with
| Some s' => s'
| None => L
end.
Definition label (t:tm) : Sec :=
eLabel (Label t).
Definition labelT (T:Ty) : Sec:=
match T with
| an rt b => b
end.
(**
Now,we impose upon the language a relation which restricts the
form of expressions we are interested in when doing reduction.
Specifically we want to exclude from our consideration expression
which contains pointers whose referred location is out of range,
e.g. tapp t1 (tloc T n L) where n is equal or greater than the length
of the current heap
*)
(*well formed expressions*)
Inductive well_formed : tm -> nat -> Prop :=
| wf_tvar:forall (x:id)(hp:nat),
well_formed (tvar x) hp
| wf_tcon:forall (b:Sec)(n:nat)(hp:nat),
well_formed (tcon n b) hp
| wf_tunit:forall (b:Sec)(hp:nat),
well_formed (tunit b) hp
| wf_tloc:forall (T:Ty)(n:nat)(b:Sec)(hp:nat),
n < hp ->
well_formed (tloc T (Some n) b) hp
| wf_tprot:forall b t (hp:nat),
well_formed t hp ->
well_formed (tprot b t) hp
| wf_tabs:forall x T e b hp,
well_formed e hp ->
well_formed (tabs x T e b) hp
| wf_tapp:forall t1 t2 hp,
well_formed t1 hp ->
well_formed t2 hp ->
well_formed (tapp t1 t2) hp
| wf_tref:forall (T:Ty) (e:tm) (b:Sec) (hp:nat),
well_formed e hp ->
well_formed (tref T e b) hp
| wf_tderef:forall e hp,
well_formed e hp ->
well_formed (tderef e) hp
| wf_tassign:forall t1 t2 hp,
well_formed t1 hp ->
well_formed t2 hp ->
well_formed (tassign t1 t2) hp.
(*some examples of well-formed expressions*)
Example well_formed_1:
well_formed (tvar (Id 0)) 0.
Proof. apply wf_tvar.
Qed.
Example well_formed_2:
well_formed (tprot H (tloc (an int L) (Some 0) L)) 1.
Proof. apply wf_tprot. apply wf_tloc. apply le_n.
Qed.
Example well_formed_3:forall hp,
well_formed (tcon 0 H) hp.
Proof. intros. apply wf_tcon.
Qed.
Example well_formed_4:forall hp,
well_formed (tunit L) hp.
Proof. intros. apply wf_tunit.
Qed.
Example well_formed_5:
well_formed (tabs (Id 0)(an int L)(tderef (tloc (an int L) (Some 0) H)) L) 1.
Proof. apply wf_tabs. apply wf_tderef. apply wf_tloc. apply le_n.
Qed.
Example well_formed_6:forall hp,
well_formed (tref (an int L) (tcon 0 L) H) hp.
Proof. intros. apply wf_tref. apply wf_tcon.
Qed.
Example well_formed_7:
well_formed (tassign (tloc (an int L) (Some 0) L)(tcon 1 L)) 1.
Proof. apply wf_tassign. apply wf_tloc. apply le_n. apply wf_tcon.
Qed.
(*some examples of ill-formed expression*)
Example ill_formed_1:
~well_formed (tloc (an int L) (Some 0) L) 0.
Proof. intros contra. inversion contra. inversion H4.
Qed.
Example ill_formed_2:
~well_formed (tapp (tref (an int L) (tcon 1 L) L)(tloc (an int L) (Some 1) L)) 1.
Proof. intros contra. inversion contra. inversion H4. inversion H9. inversion H11.
Qed.
Example ill_formed_3:
~well_formed (tassign (tloc (an int L) (Some 1) L)(tapp (tabs (Id 0)(an int L)(tvar (Id 0)) L)(tcon 1 L))) 1.
Proof. intros contra. inversion contra. inversion H2. inversion H9. inversion H11.
Qed.
(*some lemmas regarding [well_formed]*)
Lemma well_formed_extend:forall t hp,
well_formed t hp ->
well_formed t (S hp).
Proof. intros t. induction t.
Case ("tvar"). intros. apply wf_tvar.
Case ("tprot"). intros. inversion H0. apply wf_tprot. apply IHt. apply H4.
Case ("tcon"). intros. apply wf_tcon.
Case ("tabs"). intros. inversion H0. apply wf_tabs. apply IHt. apply H6.
Case ("tapp"). intros. inversion H0. apply wf_tapp. apply IHt1. apply H3.
apply IHt2. apply H5.
Case ("tunit"). intros. apply wf_tunit.
Case ("tref"). intros. apply wf_tref. apply IHt. inversion H0. apply H5.
Case ("tderef"). intros. apply wf_tderef. apply IHt. inversion H0. apply H2.
Case ("tloc"). intros. destruct o. apply wf_tloc. inversion H0.
apply le_S. apply H5. inversion H0.
Case ("tassign"). intros. apply wf_tassign. apply IHt1. inversion H0. apply H3. apply IHt2. inversion H0.
apply H5.
Qed.
(**
Also,we restrict the heap at the beginning of our reduction such that
each and every element within the heap is well-foremed according to
the heap itself,
*)
(*heap well_formed*)
Inductive heap_well_formed : heap -> nat -> Prop :=
| nil_hwf:forall n,
heap_well_formed nil n
| one_hwf:forall t0 t T n,
heap_well_formed t n ->
well_formed t0 n ->
heap_well_formed ((t0,T) :: t) n.
(*some lemmas regarding [heap_well_formed]*)
Lemma heap_well_formed_extend'': forall n m,
n <= m -> S n <= S m.
Proof.
intros. induction H0. apply le_n. apply le_S. apply IHle.
Qed.
Lemma heap_well_formed_extend':forall (T:Type)(l:nat) (hp:list T),
l <= length hp ->
l <> length hp ->
l < length hp.
Proof. intros. unfold not in H1. unfold lt. inversion H0. apply H1 in H2. inversion H2.
apply heap_well_formed_extend'' in H3. apply H3. Qed.
Lemma heap_well_formed_extend:forall hp t T n,
heap_well_formed hp n->
well_formed t n ->
heap_well_formed (snoc hp (t,T)) (S n).
Proof. intros hp. induction hp.
Case ("nil"). intros. simpl. apply one_hwf. apply nil_hwf. apply well_formed_extend. apply H1.
Case ("h::t"). intros. simpl. destruct a. apply one_hwf. apply IHhp. inversion H0. apply H6.
apply H1. inversion H0. subst. apply well_formed_extend. apply H7.
Qed.
Lemma heap_well_formed_shrink:forall hp a n,
heap_well_formed (a :: hp) n ->
heap_well_formed hp n.
Proof. intros. inversion H0. apply H3.
Qed.
Lemma lt_same_F' : forall n m,
S n <= S m -> n <= m.
Proof. intros. generalize dependent n. induction m.
intros. destruct n. apply le_n. inversion H0. inversion H2.
intros. inversion H0. apply le_n. apply le_S. apply IHm in H2.
apply H2. Qed.
Lemma lt_same_F:forall n,
n < n -> False.
Proof. intros. induction n. inversion H0. unfold lt in H0. unfold lt in IHn.
apply lt_same_F' in H0. apply IHn in H0. inversion H0. Qed.
Lemma heap_well_formed_replace:forall hp t T n n',
well_formed t n ->
heap_well_formed hp n ->
n' < length hp ->
heap_well_formed (heap_replace n' (t,T) hp) n.
Proof. intros hp. induction hp.
Case ("nil"). intros. simpl in H2. destruct n'. apply lt_same_F in H2. inversion H2. inversion H2.
Case ("h::t"). intros. destruct n'. simpl. apply one_hwf. inversion H1. apply H5. apply H0. simpl.
destruct a. apply one_hwf. apply IHhp. apply H0. inversion H1. apply H7. simpl in H2.
apply lt_same_F' in H2. apply H2. inversion H1. apply H8.
Qed.
(**
Note that the reason for having this additional restriction upon the heap is
that when the heap is extended we have to make sure that the projection of the
elements on the heap before the allocation is the same as that of those on the
heap after the allocation,
project_conf'_hp (project_hp heap)(project_hp heap)
=
project_conf'_hp (project_hp heap)(project_hp (snoc heap v)),
where [v] stands for a low value
*)
(**
Note regarding the reduction relation, there are few modifications made,
a. [st_refv]
1. the cell being written is guarded by both the security context and
the label of the allocation
2. moreover,we have to guarantee that the label of the cell being written
subsums that of its type
b. [st_assign]
1. the label of the resulting unit is the joint of PC and the label of the pointer
2. the label of the cell written to the heap has to be guarded by that of its type
3. the label of the cell on the heap being over-written equals the joint of the label
of the referred type and that of the replacing value
Note [a.2] and [b.2] together guarantee that for every pair in heap, the label of
the first element subsums that of the second one. This extra condition imposed upon
our typing system allows us to reintroduce "the condition" without sacrificing [progress]
c. [st_ref]
1. the security_context where the sub-term is reduced has to be guarded by
the label of the pointer for when we have a high pointer we have to make
sure that we also write high value to the heap so that our projection function
can successfully handle this case in the sense that the resulting reduction
is allowed in [LowLang]
Note that there are two types of over-writing we care for in the system,
1. a low cell being over-written by a low value
tassign (tloc (an int L) 0 L)(tcon 1 L) / ((tcon 0 L,an int L) :: nil)
==L=>
tunit L / ((tcon 1 L,an int L) :: nil)
2. a high cell being over-written by a high value
tassign (tloc (an int L) 0 L)(tcon 1 H) / ((tcon 0 H,an int L) :: nil)
==L=>
tunit L / ((tcon 1 H,an int L) :: nil)
##########################################################################
the remaining two cases are left out currently,
3. a high cell being over-written by a low value
tassign (tloc (an int L) 0 L)(tcon 1 L) / ((tcon 0 H,an int L) :: nil)
==L=>
tunit L / ((tcon 1 L,an int L) :: nil)
4. a low cell being over-written by a high value
tassign (tloc (an int L) 0 L)(tcon 1 H) / ((tcon 0 L,an int L) :: nil)
==L=>
tunit L / ((tcon 1 H,an int L) :: nil)
##########################################################################
*)
(**
Now in addition to the above analysis,we also require that the expression we
are concerned with before reduction is well-formed. This is already adequate for
us to exclude from consideration all expression involved in the reduction process
which are ill-formed for the heap can only be extended in the process.
*)
(*##########*)
Reserved Notation "t1 '/' hp '==' PC '=>' t2 '/' hp'"
(at level 40, hp at level 39, t2 at level 39, PC at level 39).
Inductive step : tm * heap -> Sec -> tm * heap -> Prop :=
| st_prot: forall b PC t t' hp hp',
heap_well_formed hp (length hp)-> (*additional requirement*)
well_formed t (length hp) -> (*additional requirement*)
t / hp == (joins PC b) => t' / hp' ->
tprot b t / hp == PC => tprot b t' / hp'
| st_protv: forall b v hp PC,
heap_well_formed hp (length hp) -> (*additional requirement*)
well_formed v (length hp) -> (*additional requirement*)
value v ->
tprot b v / hp == PC => joinvs v b / hp
| st_appabs: forall x T e b PC hp v,
heap_well_formed hp (length hp) -> (*additional requirement*)
well_formed v (length hp) -> (*additional requirement*)
well_formed e (length hp) -> (*additional requirement*)
value v ->
tapp (tabs x T e b) v / hp == PC => tprot b ([x := v]e) / hp
| st_app1: forall t1 t1' t2 PC hp hp',
heap_well_formed hp (length hp) -> (*additional requirement*)
well_formed t1 (length hp) -> (*additional requirement*)
well_formed t2 (length hp) -> (*additional requirement*)
t1 / hp == PC => t1' / hp' ->
tapp t1 t2 / hp == PC => tapp t1' t2 / hp'
| st_app2: forall v1 t2 t2' PC hp hp',
heap_well_formed hp (length hp) -> (*additional requirement*)
well_formed v1 (length hp) -> (*additional requirement*)
well_formed t2 (length hp) -> (*additional requirement*)
value v1 ->
t2 / hp == PC => t2' / hp' ->
tapp v1 t2 / hp == PC => tapp v1 t2' / hp'
| st_refv: forall T v v' b b' b'' b''' PC hp hp',
heap_well_formed hp (length hp) -> (*additional requirement*)
well_formed v (length hp) -> (*additional requirement*)
value v ->
b' = labelT T ->
b'' = joins b PC -> (*join PC with label of the pointer*)
b''' =joins b' b'' ->(*then join with the label of the type of the pointer*)
v' = joinvs v b''' ->
hp' = snoc hp (v',T) ->
tref T v b / hp == PC => tloc T (Some (length hp)) b / hp'
| st_ref: forall T t t' b PC hp hp',
heap_well_formed hp (length hp) -> (*additional requirement*)
well_formed t (length hp) -> (*additional requirement*)
t / hp == (joins PC b) => t' / hp' ->
tref T t b / hp == PC => tref T t' b / hp'
| st_derefloc: forall T n b PC hp t,
heap_well_formed hp (length hp) -> (*additional requirement*)
n < length hp ->
t = efst (heap_lookup n hp) ->
tderef (tloc T (Some n) b) / hp == PC => tprot b t / hp
| st_deref: forall t t' hp hp' PC,
heap_well_formed hp (length hp) -> (*additional requirement*)
well_formed t (length hp) -> (*additional requirement*)
t / hp == PC => t' / hp' ->
tderef t / hp == PC => tderef t' / hp'
| st_assign: forall v v' T T' b b' b'' b''' l n PC hp hp',
heap_well_formed hp (length hp) -> (*additional requirement*)
well_formed v (length hp) -> (*additional requirement*)
n < length hp -> (* heap_lookup n hp = some e'*)
value v ->
l = label v ->
b' = labelT T ->
b'' = joins PC b ->
joins l b' = label (efst (heap_lookup n hp)) ->
subsum_r b'' (label (efst (heap_lookup n hp))) ->
b'''= joins b' b'' ->
T' = joinTs T b'' ->
v' = joinvs v b''' ->
hp' = heap_replace n (v',T') hp ->
tassign (tloc T (Some n) b) v / hp == PC => tunit b'' / hp'
| st_assign1: forall t1 t1' t2 PC hp hp',
heap_well_formed hp (length hp) -> (*additional requirement*)
well_formed t1 (length hp) -> (*additional requirement*)
well_formed t2 (length hp) -> (*additional requirement*)
t1 / hp == PC => t1' / hp' ->
tassign t1 t2 / hp == PC => tassign t1' t2 / hp'
| st_assign2: forall v1 t2 t2' PC hp hp',
heap_well_formed hp (length hp) -> (*additional requirement*)
well_formed v1 (length hp) -> (*additional requirement*)
well_formed t2 (length hp) -> (*additional requirement*)
value v1 ->
t2 / hp == PC => t2' / hp' ->
tassign v1 t2 / hp == PC => tassign v1 t2' / hp'
where "t1 '/' hp '==' PC '=>' t2 '/' hp'" := (step (t1,hp) PC (t2,hp')).
(*###multi-step reduction###*)
Definition Relation (X: Type) := X->Sec->X->Prop.
Inductive Multi {X:Type} (R: Relation X) : Relation X :=
| Multi_refl : forall (x : X)(b : Sec), Multi R x b x
| Multi_step : forall (x y z : X)(b : Sec),
R x b y ->
Multi R y b z ->
Multi R x b z.
Definition Multistep := (Multi step).
Notation "t1 '/' hp '==' PC '=>*' t2 '/' hp'" := (Multistep (t1,hp) PC (t2,hp'))
(at level 40, hp at level 39, t2 at level 39, PC at level 39).
Definition stuck_term (s:tm) (hp:heap) (PC:Sec) : Prop :=
(~exists e', step (s,hp) PC e') /\ (~value s).
(*Some reduction examples*)
Example test_step_1:
tref (an int L)(tcon 0 L) L / emp_hp
==L=>
tloc (an int L) (Some 0) L / ((tcon 0 L,an int L) :: emp_hp).
Proof. apply st_refv with (v':=tcon 0 L)(b':=L)(b'':=L)(b''':=L).
apply nil_hwf.
apply wf_tcon. apply v_c. reflexivity.
reflexivity. reflexivity. reflexivity. reflexivity. Qed.
Example test_step_2:forall hp,
heap_well_formed hp (length hp) ->
tref (an int L)(tcon 0 L) H / hp
==L=>
tloc (an int L) (Some (length hp)) H / snoc hp (tcon 0 H,an int L).
Proof. intros. apply st_refv with (v':=tcon 0 H)(b':=L)(b'':=H)(b''':=H).
apply H0.
apply wf_tcon.
apply v_c. reflexivity. reflexivity. reflexivity. reflexivity. reflexivity.
Qed.
Example test_step_3:forall hp,
heap_well_formed hp (length hp) ->
tref (an int H)(tcon 0 L) L / hp
==L=>
tloc (an int H) (Some (length hp)) L / snoc hp (tcon 0 H,an int H).
Proof. intros. apply st_refv with (v':=tcon 0 H)(b':=H)(b'':=L)(b''':=H).
apply H0.
apply wf_tcon.
apply v_c. reflexivity. reflexivity. reflexivity. reflexivity. reflexivity.
Qed.
Example test_step_4:forall hp,
heap_well_formed hp (length hp) ->
tref (an int L)(tcon 0 H) L / hp
==L=>
tloc (an int L) (Some (length hp)) L / snoc hp (tcon 0 H,an int L).
Proof. intros. apply st_refv with (v':=tcon 0 H)(b':=L)(b'':=L)(b''':=L).
apply H0.
apply wf_tcon.
apply v_c. reflexivity. reflexivity. reflexivity. reflexivity. reflexivity.
Qed.
Lemma test_step_5'': forall n m,
n <= m -> S n <= S m.
Proof.
intros. induction H0. apply le_n. apply le_S. apply IHle.
Qed.
Lemma test_step_5':forall (T:Type)(l:nat) (hp:list T),
l <= length hp ->
l <> length hp ->
l < length hp.
Proof. intros. unfold not in H1. unfold lt. inversion H0. apply H1 in H2. inversion H2.
apply test_step_5'' in H3. apply H3. Qed.
Example test_step_5:forall hp,
heap_well_formed hp (length hp) ->
tprot H (tref (an int H)(tcon 0 L) L) / hp
==L=>*
tloc (an int H) (Some (length hp)) H / snoc hp (tcon 0 H,an int H).
Proof. intros. apply Multi_step with (y:=(tprot H (tloc (an int H)(Some (length hp)) L),(snoc hp (tcon 0 H,an int H)))).
apply st_prot.
apply H0.
apply wf_tref. apply wf_tcon.
apply st_refv with (v':=tcon 0 H)(b':=H)(b'':=H)(b''':=H).
apply H0.
apply wf_tcon.
apply v_c. reflexivity. reflexivity. reflexivity.
reflexivity. reflexivity.
apply Multi_step with (y:=(tloc (an int H) (Some (length hp)) H,(snoc hp (tcon 0 H,an int H)))). apply st_protv.
rewrite->length_snoc.
apply heap_well_formed_extend. apply H0. apply wf_tcon.
apply wf_tloc. rewrite->length_snoc. apply le_n. apply v_l.
apply Multi_refl. Qed.
Example test_step_6:forall hp,
heap_well_formed hp (length hp) ->
tprot L (tref (an int H)(tcon 0 L)L) / hp
==L=>*
tloc (an int H) (Some (length hp)) L / snoc hp (tcon 0 H,an int H).
Proof. intros. apply Multi_step with (y:=(tprot L (tloc (an int H) (Some (length hp)) L),(snoc hp (tcon 0 H,an int H)))).
apply st_prot. apply H0. apply wf_tref. apply wf_tcon.
apply st_refv with (v':=tcon 0 H)(b':=H)(b'':=L)(b''':=H). apply H0. apply wf_tcon.
apply v_c. reflexivity. reflexivity. reflexivity.
reflexivity. reflexivity.
apply Multi_step with (y:=(tloc (an int H) (Some (length hp)) L,(snoc hp (tcon 0 H,an int H)))). apply st_protv. rewrite->length_snoc.
apply heap_well_formed_extend.
apply H0. apply wf_tcon.
apply wf_tloc. rewrite->length_snoc. apply le_n.
apply v_l. apply Multi_refl. Qed.
(*a low cell is being over-written by a low value*)
Example test_step_7:
tassign (tloc (an int L) (Some 0) L)(tcon 1 L) / ((tcon 0 L,an int L) :: emp_hp)
==L=>
tunit L / ((tcon 1 L,an int L) :: emp_hp).
Proof. apply st_assign with (v':=tcon 1 L)(T':=an int L)(b':=L)(b''':=L)(l:=L).
assert (snoc emp_hp (tcon 0 L,an int L)=((tcon 0 L,an int L) :: emp_hp)). reflexivity. rewrite<-H0.
rewrite->length_snoc.
apply heap_well_formed_extend. apply nil_hwf. apply wf_tcon.
apply wf_tcon.
apply le_n. apply v_c. reflexivity. reflexivity.
reflexivity. reflexivity. apply sub_refl. reflexivity. reflexivity. reflexivity. reflexivity.
Qed.
(*high cell being over-written by a high value*)
Example test_step_8:
tassign (tloc (an int H) (Some 0) L)(tcon 1 H) / ((tcon 0 H,an int H) :: emp_hp)
==L=>
tunit L / ((tcon 1 H,an int H) :: emp_hp).
Proof. apply st_assign with (v':=tcon 1 H)(T':=an int H)(b':=H)(b''':=H)(l:=H).
assert ((tcon 0 H,an int H) :: emp_hp = snoc emp_hp (tcon 0 H,an int H)). reflexivity.
rewrite->H0. rewrite->length_snoc. apply heap_well_formed_extend. apply nil_hwf. apply wf_tcon.
apply wf_tcon.
apply le_n. apply v_c.
reflexivity. reflexivity. reflexivity. reflexivity. apply sub_LH. reflexivity. reflexivity. reflexivity. reflexivity.
Qed.
(*high cell being over-written by a low value*)
Example test_step_9:
stuck_term (tassign (tloc (an int L) (Some 0) L)(tcon 1 L)) ((tcon 0 H,an int L) :: emp_hp) L.
Proof. split. intros contra. inversion contra. inversion H0. subst.
simpl in H13. inversion H13.
inversion H9. inversion H10. intros contra. inversion contra.
Qed.
(*low cell being over-written by high value
*)
Example test_step_9':
stuck_term (tassign (tloc (an int L) (Some 0) L)(tcon 1 H)) ((tcon 0 L,an int L) :: emp_hp) L.
Proof. split. intros contra. inversion contra. inversion H0. subst. inversion H13. inversion H9.
inversion H10. intros contra. inversion contra.
Qed.
Example test_step_10:
stuck_term (tassign (tloc (an int L) (Some 0) H)(tcon 1 L)) ((tcon 0 L,an int H) :: emp_hp) L.
Proof. split. intros contra. inversion contra. inversion H0. subst. inversion H14. inversion H9. inversion H10.
intros contra. inversion contra.
Qed.
Example test_step_11:
stuck_term (tassign (tloc (an int L) (Some 0) L)(tcon 1 L)) ((tcon 0 L,an int L) :: emp_hp) H.
Proof. split. intros contra. inversion contra. inversion H0. subst. simpl in H14. inversion H14. inversion H9.
inversion H10. intros contra. inversion contra.
Qed.
Example test_step_12:
stuck_term (tassign (tloc (an int L) (Some 0) H)(tcon 1 L))((tcon 0 L,an int L) :: emp_hp) H.
Proof. split. intros contra. inversion contra. inversion H0. subst. simpl in H14. inversion H14. inversion H9. inversion H10.
intros contra. inversion contra.
Qed.
Example test_step_13:
tref (an (ref (an int L)) L) (tref (an int L)(tcon 0 L) L) H / nil
==L=>
tref (an (ref (an int L)) L) (tloc (an int L) (Some 0) L) H / ((tcon 0 H,an int L) :: nil).
Proof. apply st_ref. apply nil_hwf. apply wf_tref. apply wf_tcon.
apply st_refv with (v':=tcon 0 H)(b':=L)(b'':=H)(b''':=H). apply nil_hwf. apply wf_tcon.
apply v_c. reflexivity. reflexivity. reflexivity. reflexivity.
reflexivity.
Qed.
(**
Note that it is clear from the above examples that when a cell is being written the label
of the cell subsums that of its type. This is necessary for us to restore the restriction
for security upgrading without sacrificing [progress]
*)
(**
Note that by including extra condition in [st_assign], we can
no longer have the following property,
forall PC PC' t hp,
exists c,t / hp ==PC=> c -> exists c', t / hp ==PC'=> c'.
Consider the following configuration,
tassign (tloc (an int L) 0 L)(tcon 1 L) / ((tcon 0 L,an int L) :: emp_hp)
it is reducible under [L] while it is not under [H].
Actually,we can only argue that if a configuration is reducible under [H] then
it is also under [L]. See the following lemma.
*)
Lemma HL_scontext:forall s hp,
(exists e',step (s,hp) H e') ->
exists e',step (s,hp) L e'.
Proof.
intros s. induction s.
Case ("tvar"). intros. inversion H0. inversion H1.
Case ("tprot"). intros. inversion H0. inversion H1. subst. destruct s.
simpl in H9. assert (exists e',step (s0,hp) H e'). exists (t',hp').
apply H9. apply IHs in H2. inversion H2. destruct x. exists (tprot L t,h).
apply st_prot. apply H5. apply H8. simpl. apply H3. simpl in H9. exists (tprot H t',hp').
apply st_prot. apply H5. apply H8. simpl. apply H9. subst. exists (joinvs s0 s,hp). apply st_protv.
apply H5. apply H8.
apply H9.
Case ("tcon"). intros. inversion H0. inversion H1.
Case ("tabs"). intros. inversion H0. inversion H1.
Case ("tapp"). intros. inversion H0. inversion H1.
subst. exists (tprot b ([x0:=s2]e),hp). apply st_appabs. apply H5. apply H6. apply H9.
apply H10.
subst. assert (exists e',step (s1,hp) H e'). exists (t1',hp').
apply H10. apply IHs1 in H2. inversion H2. destruct x.
exists (tapp t s2,h). apply st_app1. apply H5. apply H6. apply H9. apply H3.
subst.
assert (exists e',step (s2,hp) H e'). exists (t2',hp'). apply H11.
apply IHs2 in H2. inversion H2. destruct x. exists (tapp s1 t,h).
apply st_app2. apply H5. apply H6. apply H7. apply H10. apply H3.
Case ("tunit"). intros. inversion H0. inversion H1.
Case ("tref"). intros. inversion H0. inversion H1. subst.
exists (tloc t (Some (length hp)) s0,snoc hp (joinvs s (joins (labelT t)(joins s0 L)),t)). apply st_refv with (v':=joinvs s (joins (labelT t)(joins s0 L)))(b':=labelT t)(b'':=joins s0 L)(b''':=joins (labelT t)(joins s0 L)).
apply H6.
apply H7. apply H8.
reflexivity. reflexivity. reflexivity. reflexivity. reflexivity. subst. destruct s0. simpl in H10.
assert (exists e',step (s,hp) H e'). exists (t',hp'). apply H10. apply IHs in H2. inversion H2.
destruct x. exists (tref t t0 L,h). apply st_ref. apply H8. apply H9. simpl. apply H3. simpl in H10. exists (tref t t' H,hp').
apply st_ref. apply H8. apply H9. simpl. apply H10.
Case ("tderef"). intros. inversion H0. inversion H1. subst. exists (tprot b (efst (heap_lookup n hp)),hp).
apply st_derefloc. apply H4. apply H5. reflexivity. subst. assert (exists e',step (s,hp) H e'). exists (t',hp').
apply H8. apply IHs in H2. inversion H2. destruct x. exists (tderef t,h). apply st_deref. apply H4. apply H5. apply H3.
Case ("tloc"). intros. inversion H0. inversion H1.
Case ("tassign"). intros. inversion H0. inversion H1. subst. exists (tunit (joins L b),heap_replace n (joinvs s2 (joins (labelT T)(joins L b)), joinTs T (joins L b)) hp).
apply st_assign with (v':=joinvs s2 (joins (labelT T)(joins L b)))(T':=joinTs T (joins L b))(b':=labelT T)(b''':=joins (labelT T)(joins L b))(l:=label s2). apply H5. apply H6. apply H7. apply H8. reflexivity. reflexivity. reflexivity.
apply H12. simpl.
apply subsum_r_trans with (a:= b)(b:= H)(c:=label (efst (heap_lookup n hp))). destruct b. apply sub_LH. apply sub_refl. simpl in H13. apply H13. reflexivity. reflexivity. reflexivity. reflexivity.
assert (exists e',step (s1,hp) H e'). exists (t1',hp'). apply H10. apply IHs1 in H11. inversion H11.
destruct x0. exists (tassign t s2,h ). apply st_assign1. apply H5. apply H6. apply H9. apply H12. subst. assert (exists e',step (s2,hp) H e'). exists (t2',hp').
apply H11. apply IHs2 in H2. inversion H2. destruct x. exists (tassign s1 t,h). apply st_assign2. apply H5. apply H6. apply H7. apply H10. apply H3.
Qed.
(*generalization of the above lemma*)
Lemma prot_scontext:forall s hp PC b,
(exists e', step (s,hp) (joins PC b) e') ->
exists e',step (s,hp) PC e'.
Proof.
intros. destruct PC. destruct b. simpl in H0. apply H0.
simpl in H0. apply HL_scontext. apply H0. simpl in H0.
apply H0.
Qed.
(*typing rule*)
(*typing relation*)
(**
Note that we make one change above in [st_ref] so that the evaluation of
the subterm in allocation is under the security context guarded by the label
of the allocation,
[st_ref]:forall T t t' b PC hp hp',
t / hp == (joins PC b) => t' / hp' ->
tref T t b / hp == PC => tref T t' b / hp'
this is some what similar to the reduction rule of protection when the
protected subterm is not a value.
Now we show that we have to modify [t_ref] as well in the following typing rule
so as to make the whole system sound. For without it [preservation breaks down],
[t_ref]: forall pc Gamma HT t T b b',
has_type (joins pc b) Gamma HT t T ->
b' = joins pc b ->
subsum_r b' (labelT T) ->
has_type pc Gamma HT (tref T t b) (an (ref T) b)
To see why we have to modify our typing rule consider the following legit reduction
sequence,
tref (an (ref (an int L)) L) (tref (an int L)(tcon 0 L) L) H / nil
==L=>
tref (an (ref (an int L)) L) (tloc (an int L) 0 L) H / ((tcon 0 H,an int L) :: nil),
according to [t_ref] we know that
has_type L empty_context []
(tref (an int L)(tcon 0 L) L)
(an (ref (an int L)) L)
which implies that
has_type L empty_context []
(tref (an (ref (an int L)) L) (tref (an int L)(tcon 0 L) L) H)
(an (ref (an (ref (an int L)) L)) H)
now we reduce it according to [st_ref] we have,
tref (an (ref (an int L)) L) (tloc (an int L) 0 L) H / ((tcon 0 H,an int L) :: nil)
and given the new heap_typing,HT',as [an int L] we again have the resulting term as
well-typed,
has_type L empty_context [an int L]
(tref (an (ref (an int L)) L) (tloc (an int L) 0 L) H)
(an (ref (an (ref (an int L)) L)) H)
however the [heap_well_typed] breaks down,
~has_typed pc empty_context HT
(tcon 0 H)
(an int L).
One way to fix it is to have the following typing rule,
[t_ref]: forall pc Gamma HT t T b b',
has_type (joins pc b) Gamma HT t T ->
b' = joins pc b ->
subsum_r b' (labelT T) ->
has_type pc Gamma HT (tref T t b) (an (ref T) b)
which renders the term before reduction ill-typed.
Qed.
*)
Inductive has_type : Sec -> context -> heap_Ty -> tm -> Ty -> Prop :=
| t_var : forall pc Gamma HT x T,
Gamma x = Some T ->
has_type pc Gamma HT (tvar x) T
| t_con : forall pc Gamma HT n b,
has_type pc Gamma HT (tcon n b) (an int b)
| t_unit: forall pc Gamma HT b,
has_type pc Gamma HT (tunit b) (an unit b)
| t_loc: forall pc Gamma HT T n b,
heap_Tlookup n HT = Some T ->
has_type pc Gamma HT (tloc T (Some n) b) (an (ref T) b)
| t_abs: forall pc pc' Gamma HT x T e b T',
has_type pc' (Cupdate Gamma x (Some T)) HT e T' ->
has_type pc Gamma HT (tabs x T e b) (an (fn T pc' T') b)
| t_prot: forall pc Gamma HT t b T T',
has_type (joins pc b) Gamma HT t T ->
T' = joinTs T b ->
has_type pc Gamma HT (tprot b t) T'
| t_app: forall pc Gamma HT T1 T2 T2' b t1 t2,
has_type pc Gamma HT t1 (an (fn T1 (joins pc b) T2) b) ->
has_type pc Gamma HT t2 T1 ->
joinTs T2 b = T2' ->
has_type pc Gamma HT (tapp t1 t2) T2'
| t_ref: forall pc Gamma HT t T b b',
has_type (joins pc b) Gamma HT t T ->
b' = joins pc b ->
subsum_r b' (labelT T)->
has_type pc Gamma HT (tref T t b) (an (ref T) b)
| t_deref: forall pc Gamma HT t T T' b,
has_type pc Gamma HT t (an (ref T) b) ->
T' = joinTs T b ->
has_type pc Gamma HT (tderef t) T'
| t_assign: forall pc Gamma HT t1 t2 b b' T,
b' = labelT T ->
subsum_r (joins pc b) b' ->
has_type pc Gamma HT t1 (an (ref T) b) ->
has_type pc Gamma HT t2 T ->
has_type pc Gamma HT (tassign t1 t2) (an unit b')
| t_sub: forall pc pc' Gamma HT t T T',
has_type pc Gamma HT t T ->
subsum_r pc' pc ->
T <: T' ->
has_type pc' Gamma HT t T'
.
(*###inversion of [has_type]###*)
(*inversion of [has_type pc Gamma HT (tvar x) T]*)
Lemma inversion_tvar: forall pc Gamma HT x T,
has_type pc Gamma HT (tvar x) T ->
exists T0, (Gamma x = Some T0)/\(T0 <: T).
Proof. intros. remember (tvar x) as t. induction H0.
inversion Heqt. subst. exists T. split. apply H0. apply subtyping_refl.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt.
inversion Heqt. inversion Heqt. inversion Heqt.
apply IHhas_type in Heqt. inversion Heqt. exists x0. split. inversion H3.
apply H4. inversion H3. apply subtyping_trans with (x:=T)(y:=T). apply subtyping_refl.
apply H5. apply H2.
Qed.
(*inversion of [has_type pc Gamma HT (tabs x T1 e b) T]*)
Lemma inversion_tabs: forall pc Gamma HT x T1 T e b,
has_type pc Gamma HT (tabs x T1 e b) T ->
exists T1', exists T2, exists T2', exists pc', exists pc'', exists pc''', exists b',
(has_type pc' Gamma HT (tabs x T1 e b) (an (fn T1 pc'' T2) b)) /\
(has_type pc'' (Cupdate Gamma x (Some T1)) HT e T2) /\(subsum_r pc''' pc'')/\(subsum_r pc pc')/\
(T1'<:T1)/\(T2<:T2')/\(subsum_r b b')/\((an (fn T1' pc''' T2') b') <: T).
Proof. intros. remember (tabs x T1 e b) as t. induction H0. inversion Heqt. inversion Heqt. inversion Heqt.
inversion Heqt. inversion Heqt. subst. exists T1. exists T'. exists T'. exists pc. exists pc'. exists pc'. exists b.
split. apply t_abs with (b:=b)(pc:=pc) in H0. apply H0.
split. apply H0. split. apply sub_refl. split. apply sub_refl. split. apply subtyping_refl. split. apply subtyping_refl. split. apply sub_refl. apply subtyping_refl.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. apply IHhas_type in Heqt. inversion Heqt. exists x0. inversion H3. exists x1. inversion H4. exists x2.
inversion H5. exists x3. inversion H6. exists x4. inversion H7. exists x5. inversion H8. exists x6. split. apply H9. split. apply H9. split. apply H9. split. apply subsum_r_trans with (a:=pc')(b:=pc)(c:=x3).
apply H1. apply H9. split. apply H9. split. apply H9. split. apply H9.
apply subtyping_trans with (x:=T)(y:=T). apply subtyping_refl. apply H9. apply H2.
Qed.
(*inversion of [has_type pc Gamma HT (tcon n b) T]*)
Lemma inversion_tcon: forall pc Gamma HT T n b,
has_type pc Gamma HT (tcon n b) T ->
exists T', exists T'', exists b',
(T' = an int b)/\(T'' = an int b')/\(subsum_r b b')/\(T'' <: T).
Proof.
intros. remember (tcon n b) as t. induction H0.
inversion Heqt. inversion Heqt. subst. exists (an int b). exists (an int b).
exists b. split. reflexivity. split. reflexivity. split. apply sub_refl.
apply subt_int. apply sub_refl. inversion Heqt. inversion Heqt. inversion Heqt.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt.
apply IHhas_type in Heqt. inversion Heqt. exists x. inversion H3.
exists x0. inversion H4. exists x1.
inversion H5. split. apply H6. inversion H7. split. apply H8. inversion H9. split. apply H10.
apply subtyping_trans with (x:=T)(y:=T). apply subtyping_refl. apply H11. apply H2.
Qed.
(*inversion of [has_type pc Gamma HT (tunit b) T]*)
Lemma inversion_tunit:forall pc Gamma HT T b,
has_type pc Gamma HT (tunit b) T ->
exists T', exists T'', exists b',
(T'=an unit b)/\(T''=an unit b')/\(subsum_r b b')/\(T''<:T).
Proof. intros. remember (tunit b) as t. induction H0. inversion Heqt. inversion Heqt. inversion Heqt.
subst. exists (an unit b). exists (an unit b). exists b. split. reflexivity. split. reflexivity. split.
apply sub_refl. apply subt_unit. apply sub_refl. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt.
inversion Heqt. inversion Heqt. inversion Heqt. apply IHhas_type in Heqt. inversion Heqt. exists x. inversion H3.
exists x0. inversion H4. exists x1. split. apply H5. split. apply H5. split. apply H5. apply subtyping_trans with (x:=T)(y:=T).
apply subtyping_refl. apply H5. apply H2. Qed.
(*inversion of [has_type pc Gamma HT (tloc T N b)(an (ref T) b)]*)
Lemma inversion_tloc:forall pc Gamma HT N T1 b T,
has_type pc Gamma HT (tloc T1 N b) T ->
exists n, exists T', exists T'', exists b',
(N = Some n)/\
(heap_Tlookup n HT = Some T1)/\(T'=an (ref T1) b)/\(T''=an (ref T1) b')/\(subsum_r b b')/\(T''<:T).
Proof. intros. remember (tloc T1 N b) as t. induction H0. inversion Heqt. inversion Heqt.
inversion Heqt. inversion Heqt. subst. exists n. exists (an (ref T1) b). exists (an (ref T1) b).
exists b. split. reflexivity. split. apply H0. split. reflexivity. split. reflexivity. split. apply sub_refl. apply subtyping_refl. inversion Heqt. inversion Heqt.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. apply IHhas_type in Heqt. inversion Heqt. exists x. inversion H3. exists x0.
inversion H4. exists x1. inversion H5. exists x2. split. apply H6. split. apply H6. split. apply H6. split. apply H6. split. apply H6. apply subtyping_trans with (x:=T)(y:=T).
apply subtyping_refl. apply H6. apply H2. Qed.
(*inversion of [has_type pc Gamma HT (tprot b t) T]*)
Lemma inversion_tprot:forall pc Gamma HT t T b,
has_type pc Gamma HT (tprot b t) T ->
exists T', exists T'', exists pc',
((joinTs T' b) <: T) /\(has_type pc' Gamma HT t T'')/\(subsum_r (joins pc b) pc')/\(T'' <: T').
Proof. intros. remember (tprot b t) as e. induction H0. inversion Heqe.
inversion Heqe. inversion Heqe. inversion Heqe. inversion Heqe. inversion Heqe. subst.
exists T. exists T. exists (joins pc b). split. apply subtyping_refl. split. apply H0.
split. apply sub_refl. apply subtyping_refl.
inversion Heqe. inversion Heqe. inversion Heqe. inversion Heqe.
apply IHhas_type in Heqe. inversion Heqe. exists x. inversion H3. exists x0. inversion H4.
exists x1. split. apply subtyping_trans with (x:=T)(y:=T). apply subtyping_refl. apply H5.
apply H2. split. apply H5. split. destruct pc. destruct pc'. simpl. simpl in H5. apply H5.
inversion H1. simpl in H5. destruct pc'. simpl. destruct b. apply subsum_r_trans with (a:=L)(b:=H)(c:=x1).
apply sub_LH. apply H5. apply H5. simpl. apply H5. apply H5.
Qed.
(*inversion of [has_type pc Gamma HT (tapp t1 t2) T]*)
Lemma inversion_tapp: forall pc Gamma HT t1 t2 T2,
has_type pc Gamma HT (tapp t1 t2) T2 ->
exists T1', exists T2', exists b', exists T1'', exists T1''', exists T2'', exists b'', exists pc', exists sp', exists sp'',
(sp'=joins pc' b')/\has_type pc' Gamma HT t1 (an (fn T1' sp' T2') b')/\((an (fn T1' sp' T2') b')<:(an (fn T1'' sp'' T2'') b''))/\
(has_type pc' Gamma HT t2 T1''')/\(T1''' <: T1'')/\(subsum_r pc pc')/\
((joinTs T2'' b'')<:T2).
Proof. intros. remember (tapp t1 t2) as t. induction H0.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt.
subst. exists T1. exists T2. exists b. exists T1. exists T1. exists T2. exists b. exists pc. exists (joins pc b). exists (joins pc b). split. reflexivity.
split. apply H0_. split. apply subtyping_refl. split. apply H0_0. split. apply subtyping_refl. split. destruct b. destruct pc. simpl.
apply sub_refl. simpl. apply sub_refl. destruct pc. simpl. apply sub_refl. apply sub_refl. apply subtyping_refl. inversion Heqt. inversion Heqt. inversion Heqt.
apply IHhas_type in Heqt. inversion Heqt. exists x. inversion H3.
exists x0. inversion H4. exists x1. inversion H5. exists x2. inversion H6. exists x3. inversion H7. exists x4.
inversion H8. exists x5. inversion H9. exists x6. inversion H10. exists x7. inversion H11. exists x8. split. apply H12.
split. apply H12. split. apply H12. split. apply H12. split. apply H12. split. apply subsum_r_trans with (a:=pc')(b:=pc)(c:=x6).
apply H1. apply H12. apply subtyping_trans with (x:=T)(y:=T).
apply subtyping_refl. apply H12. apply H2. Qed.
(*inversion of [has_type pc Gamma HT (tref T1 t b) T]*)
Lemma inversion_tref:forall pc Gamma HT T1 T t b,
has_type pc Gamma HT (tref T1 t b) T ->
exists pc', exists pc'', exists T1', exists T1'', exists b',
(has_type pc'' Gamma HT (tref T1 t b)(an (ref T1) b))/\
(subsum_r b b')/\(subsum_r pc pc'')/\
((an (ref T1) b')<:T)/\
(has_type pc' Gamma HT t T1')/\(T1' <: T1'')/\(T1''<:T1)/\
(subsum_r (joins pc'' b) pc')/\
(subsum_r (joins pc'' b) (labelT T1')).
Proof. intros. remember (tref T1 t b) as e. induction H0. inversion Heqe.
inversion Heqe. inversion Heqe. inversion Heqe. inversion Heqe. inversion Heqe.
inversion Heqe. inversion Heqe. subst. exists (joins pc b). exists pc. exists T1. exists T1.
exists b. split. apply t_ref with (b':=joins pc b). apply H0. reflexivity. apply H2. split. apply sub_refl. split. apply sub_refl.
split. apply subtyping_refl. split. apply H0. split. apply subtyping_refl. split. apply subtyping_refl. split. apply sub_refl. apply H2.
inversion Heqe. inversion Heqe.
apply IHhas_type in Heqe. inversion Heqe. exists x. inversion H3. exists x0. inversion H4. exists x1. inversion H5. exists x2. inversion H6. exists x3.
split. apply H7. split. apply H7. split. apply subsum_r_trans with (a:=pc')(b:=pc)(c:=x0). apply H1. apply H7. split. apply subtyping_trans with (x:=T)(y:=T).
apply subtyping_refl. apply H7. apply H2. apply H7.
Qed.
(*inversion of [has_type pc Gamma HT (tderef t) T]*)
Lemma inversion_tderef:forall pc Gamma HT t T,
has_type pc Gamma HT (tderef t) T ->
exists pc', exists T1, exists b', exists b'',
has_type pc' Gamma HT t (an (ref T1) b')/\(subsum_r b' b'')/\
((joinTs T1 b'')<:T)/\(subsum_r pc pc').
Proof. intros. remember (tderef t) as e. induction H0. inversion Heqe. inversion Heqe. inversion Heqe. inversion Heqe. inversion Heqe.
inversion Heqe. inversion Heqe. inversion Heqe. inversion Heqe. subst. exists pc. exists T. exists b. exists b. split. apply H0. split.
apply sub_refl. split. apply subtyping_refl. apply sub_refl. inversion Heqe.
apply IHhas_type in Heqe. inversion Heqe. exists x. inversion H3. exists x0. inversion H4. exists x1.
inversion H5. exists x2. split. apply H6. split. apply H6. split. apply subtyping_trans with (x:=T)(y:=T).
apply subtyping_refl. apply H6. apply H2. apply subsum_r_trans with (a:=pc')(b:=pc)(c:=x).
apply H1. apply H6. Qed.
(*inversion of [has_type pc Gamma HT (tassign t1 t2) T]*)
Lemma inversion_tassign:forall pc Gamma HT t1 t2 T,
has_type pc Gamma HT (tassign t1 t2) T ->
exists pc',exists T1, exists T1', exists b,
has_type pc' Gamma HT (tassign t1 t2)(an unit (labelT T1))/\
has_type pc' Gamma HT t1 (an (ref T1) b)/\
has_type pc' Gamma HT t2 T1'/\
(T1'<:T1)/\(subsum_r pc pc')/\(subsum_r (joins pc' b)(labelT T1))/\
((an unit (labelT T1))<:T).
Proof. intros. remember (tassign t1 t2) as t. induction H0. inversion Heqt.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. subst. exists pc.
exists T. exists T. exists b. split. apply t_assign with (b:=b)(T:=T). reflexivity. apply H1.
apply H0_. apply H0_0. split. apply H0_. split. apply H0_0. split. apply subtyping_refl. split.
apply sub_refl. split. apply H1. apply subtyping_refl. apply IHhas_type in Heqt.
inversion Heqt. exists x. inversion H3. exists x0. inversion H4. exists x1. inversion H5. exists x2.
split. apply H6. split. apply H6. split. apply H6. split. apply H6. split. apply subsum_r_trans with (a:=pc')(b:=pc)(c:=x).
apply H1. apply H6. split. apply H6. apply subtyping_trans with (x:=T)(y:=T). apply subtyping_refl. apply H6. apply H2. Qed.
(*#############################*)
(*######Properties########*)
(**
There are two important type safety properties we want to investigate,
a.Progress
forall Gamma T t t' st,
has_type Gamma t T ->
value t \/ exists t', t / st ==> t' / st
That is well-typed terms never get stuck
b. type preservation
forall Gamma t t' st T,
has_type Gamma t T ->
t / st ==> t' / st ->
has_type Gamma t' T
*)
(*############type preserversion############*)
(*#################auxiliary theorems##########*)
(*##########s_p_t_1##############*)
(*Firstly we use the following proposition to describe free variables*)
Inductive free_var : id -> tm -> Prop :=
| e_tvar : forall x,
free_var x (tvar x)
| e_tprot : forall x b t,
free_var x t ->
free_var x (tprot b t)
| e_tapp1 : forall x e1 e2,
free_var x e1 ->
free_var x (tapp e1 e2)
| e_tapp2 : forall x e1 e2,
free_var x e2 ->
free_var x (tapp e1 e2)
| e_tabs : forall x y e T b,
y <> x ->
free_var x e ->
free_var x (tabs y T e b)
| e_tref :forall x T t b,
free_var x t ->
free_var x (tref T t b)
| e_tderef:forall x t,
free_var x t ->
free_var x (tderef t)
| e_tassign1:forall x t1 t2,
free_var x t1 ->
free_var x (tassign t1 t2)
| e_tassign2:forall x t1 t2,
free_var x t2 ->
free_var x (tassign t1 t2)
.
(*some auxiliary lemmas*)
Theorem beq_id_eq : forall i1 i2,
true = beq_id i1 i2 -> i1 = i2.
Proof.
intros. unfold beq_id in H0. destruct i1. destruct i2. symmetry in H0.
apply beq_nat_true in H0. subst. reflexivity.
Qed.
Theorem not_eq_beq_id_false : forall i1 i2,
i1 <> i2 -> beq_id i1 i2 = false.
Proof.
intros. unfold beq_id. destruct i1. destruct i2. apply beq_nat_false_iff.
intros C. apply H0. subst. reflexivity.
Qed.
Theorem beq_id_refl : forall X,
true = beq_id X X.
Proof.
intros. destruct X.
apply beq_nat_refl. Qed.
(*end*)
(*####any_term_typable_under_empty context is closed####*)
Lemma term_typable_empty_closed_1:forall pc Gamma HT x t T,
free_var x t ->
has_type pc Gamma HT t T ->
exists T',Gamma x = Some T'.
Proof. intros. generalize dependent T. generalize dependent Gamma.
generalize dependent HT. generalize dependent pc.
induction H0.
Case ("tvar").
intros. apply inversion_tvar in H1. inversion H1. inversion H0.
exists x0. apply H2.
Case ("tprot").
intros. apply inversion_tprot in H1. inversion H1. inversion H2.
inversion H3. inversion H4. inversion H6.
apply IHfree_var in H7. inversion H7. exists x3. apply H9.
Case ("tapp1").
intros. apply inversion_tapp in H1. inversion H1. inversion H2.
inversion H3. inversion H4. inversion H5. inversion H6. inversion H7.
inversion H8. inversion H9. inversion H10. inversion H11. inversion H13.
apply IHfree_var in H14. inversion H14. exists x10.
apply H16.
Case ("tapp2").
intros. apply inversion_tapp in H1. inversion H1. inversion H2.
inversion H3. inversion H4. inversion H5. inversion H6. inversion H7.
inversion H8. inversion H9. inversion H10. inversion H11. inversion H13.
inversion H15. inversion H17.
apply IHfree_var in H18. inversion H18. exists x10. apply H20.
Case ("tabs").
intros. apply inversion_tabs in H2. inversion H2. inversion H3. inversion H4.
inversion H5. inversion H6. inversion H7. inversion H8. inversion H9. inversion H11.
apply IHfree_var in H12. inversion H12.
apply not_eq_beq_id_false in H0. apply Cupdate_neq with (T:=Some T)(St:=Gamma)in H0.
rewrite->H0 in H14. exists x7. apply H14.
Case ("tref").
intros. apply inversion_tref in H1. inversion H1. inversion H2. inversion H3. inversion H4.
inversion H5. inversion H6. inversion H8. inversion H10. inversion H12. inversion H14.
apply IHfree_var in H15. apply H15.
Case ("tderef").
intros. apply inversion_tderef in H1. inversion H1. inversion H2. inversion H3. inversion H4.
inversion H5. apply IHfree_var in H6. inversion H6. exists x4. apply H8.
Case ("tassign1").
intros. apply inversion_tassign in H1. inversion H1. inversion H2. inversion H3. inversion H4.
inversion H5. inversion H7. apply IHfree_var in H8. inversion H8. exists x4. apply H10.
Case ("tassign2").
intros. apply inversion_tassign in H1. inversion H1. inversion H2. inversion H3. inversion H4.
inversion H5. inversion H7. inversion H9. apply IHfree_var in H10. inversion H10. exists x4.
apply H12.
Qed.
Corollary term_typable_empty_closed: forall t pc HT T,
has_type pc empty_context HT t T ->
forall x, ~free_var x t.
Proof. intros t. induction t.
Case ("tvar").
intros. apply inversion_tvar in H0. inversion H0. inversion H1.
inversion H2.
Case ("tprot").
intros. apply inversion_tprot in H0. inversion H0. inversion H1. inversion H2.
inversion H3. inversion H5. apply IHt with (x:=x)in H6.
intros contra. inversion contra. subst. apply H6 in H10. inversion H10.
Case ("tcon").
intros. intros contra. inversion contra.
Case ("tabs").
intros. apply inversion_tabs in H0. inversion H0. inversion H1. inversion H2. inversion H3.
inversion H4. inversion H5. inversion H6. inversion H7. inversion H9.
intros contra. inversion contra. subst.
apply term_typable_empty_closed_1 with (T:=x1)(Gamma:=Cupdate empty_context i (Some t))(pc:=x4)(HT:=HT)in H18.
inversion H18. apply not_eq_beq_id_false in H15. apply Cupdate_neq with (T:=Some t)(St:=empty_context)in H15.
rewrite->H15 in H12. inversion H12. apply H10.
Case ("tapp").
intros. apply inversion_tapp in H0. inversion H0. inversion H1. inversion H2. inversion H3.
inversion H4. inversion H5. inversion H6. inversion H7. inversion H8. inversion H9.
inversion H10. inversion H12. inversion H14. inversion H16.
apply IHt1 with (x:=x)in H13. apply IHt2 with(x:=x) in H17. intros contra. inversion contra.
subst. apply H13 in H21. inversion H21. apply H17 in H21. inversion H21.
Case ("tunit").
intros. intros contra. inversion contra.
Case ("tref").
intros. apply inversion_tref in H0. inversion H0. inversion H1. inversion H2. inversion H3. inversion H4. inversion H5. inversion H7.
inversion H9. inversion H11. inversion H13. apply IHt with (x:=x)in H14. intros contra. inversion contra. apply H14 in H18.
inversion H18.
Case ("tderef").
intros. apply inversion_tderef in H0. inversion H0. inversion H1. inversion H2. inversion H3. inversion H4. apply IHt with(x:=x) in H5.
intros contra. inversion contra. apply H5 in H9. inversion H9.
Case ("tloc").
intros. intros contra. inversion contra.
Case ("tassign").
intros. apply inversion_tassign in H0. inversion H0. inversion H1. inversion H2. inversion H3. inversion H4. inversion H6. inversion H8.
apply IHt1 with (x:=x) in H7. apply IHt2 with (x:=x) in H9. intros contra. inversion contra. subst. apply H7 in H13. inversion H13.
apply H9 in H13. inversion H13.
Qed.
Corollary change_context: forall pc Gamma Gamma' HT t T,
has_type pc Gamma HT t T ->
(forall x, free_var x t -> Gamma x = Gamma' x) ->
has_type pc Gamma' HT t T.
Proof.
intros. generalize dependent Gamma'. induction H0.
Case ("t_var").
intros. apply t_var. rewrite<-H0. symmetry. apply H1.
apply e_tvar.
Case ("t_con").
intros. apply t_con.
Case ("tunit").
intros. apply t_unit.
Case ("tloc").
intros. apply t_loc. apply H0.
Case ("t_abs").
intros. apply t_abs. apply IHhas_type. intros. remember (beq_id x x0) as BB.
destruct BB. apply beq_id_eq in HeqBB. rewrite->HeqBB. rewrite->Cupdate_eq.
rewrite->Cupdate_eq. reflexivity. inversion HeqBB. symmetry in H4.
apply Cupdate_neq with (T:=Some T)(St:=Gamma) in H4. rewrite->H4.
inversion HeqBB. symmetry in H5. apply Cupdate_neq with (T:=Some T)(St:=Gamma') in H5.
rewrite->H5. clear H4. clear H5. apply H1. apply e_tabs. intros contra. rewrite->contra in HeqBB.
rewrite<-beq_id_refl in HeqBB. inversion HeqBB. apply H2.
Case ("t_prot").
intros. apply t_prot with (T:=T). apply IHhas_type. intros. apply H2.
apply e_tprot. apply H3. apply H1.
Case ("t_app").
intros. apply t_app with (T1:=T1)(T2:=T2)(b:=b). apply IHhas_type1. intros. apply H1. apply e_tapp1.
apply H2. apply IHhas_type2. intros. apply H1. apply e_tapp2. apply H2.
apply H0.
Case ("t_tref").
intros. apply t_ref with (b':=joins pc b). apply IHhas_type. intros. apply H3. apply e_tref. apply H4. reflexivity. subst.
apply H2.
Case ("t_deref").
intros. apply t_deref with (T:=T)(b:=b). apply IHhas_type. intros. apply H2. apply e_tderef. apply H3.
apply H1.
Case ("t_assign").
intros. apply t_assign with (b:=b)(T:=T). apply H0. apply H1. apply IHhas_type1. intros. apply H2.
apply e_tassign1. apply H3. apply IHhas_type2. intros. apply H2. apply e_tassign2. apply H3.
Case ("t_sub").
intros. apply t_sub with(pc:=pc) (T:=T). apply IHhas_type. apply H3. apply H1.
apply H2.
Qed.
Theorem s_p_t_1: forall t pc Gamma HT T,
has_type pc empty_context HT t T ->
has_type pc Gamma HT t T.
Proof. intros. apply change_context with (Gamma':=Gamma)in H0.
apply H0. intros. apply term_typable_empty_closed with (x:=x)in H0.
apply H0 in H1. inversion H1.
Qed.
(*################s_p_t_1################*)
(**
Recall that in [step], we specify that substitution can only take place if
the second argument of the application is reduced to be a value which is
closed and typable under both high and low security context.
In the following Theorem, we assume that the term used to replace bounded
variables is value.
*)
Lemma value_pc:forall pc pc' Gamma HT v T,
value v ->
has_type pc Gamma HT v T ->
has_type pc' Gamma HT v T.
Proof. intros. generalize dependent pc'. induction H1.
Case("tvar").
inversion H0.
Case("tcon").
intros. apply t_con.
Case("tunit").
intros. apply t_unit.
Case("tloc").
intros. apply t_loc. apply H1.
Case("tabs").
intros. apply t_abs. apply H1.
Case("tprot").
inversion H0.
Case("tapp").
inversion H0.
Case("tref").
inversion H0.
Case("tderef").
inversion H0.
Case("tassign").
inversion H0.
Case("sub").
intros. apply t_sub with (pc:=pc'0)(T:=T). apply IHhas_type. apply H0.
apply sub_refl. apply H3.
Qed.
Theorem substitution_preserves_typing: forall pc Gamma HT x v2 T1 T2 e,
value v2 ->
has_type pc empty_context HT v2 T1 ->
has_type pc (Cupdate Gamma x (Some T1)) HT e T2 ->
has_type pc Gamma HT ([x := v2]e) T2.
Proof. intros. generalize dependent pc. generalize dependent HT.
generalize dependent Gamma. generalize dependent x.
generalize dependent v2. generalize dependent T1. generalize dependent
T2. induction e.
Case ("tvar").
intros. apply inversion_tvar in H2. inversion H2. inversion H3.
remember (beq_id x i) as BB.
destruct BB. apply beq_id_eq in HeqBB. rewrite->HeqBB in H4.
rewrite->Cupdate_eq in H4. inversion H4. subst. simpl. rewrite<-beq_id_refl.
apply s_p_t_1. apply t_sub with (pc:=pc)(T:=x0). apply H1. apply sub_refl. apply H5.
symmetry in HeqBB. simpl. rewrite->HeqBB. destruct i. apply t_sub with (pc:=pc)(T:=x0).
apply t_var. apply Cupdate_neq with (T:=Some T1)(St:=Gamma)in HeqBB.
rewrite->HeqBB in H4. apply H4. apply sub_refl. apply H5.
Case ("tprot").
intros. simpl. apply inversion_tprot in H2. inversion H2. inversion H3.
inversion H4. inversion H5. inversion H7. apply t_sub with (pc:=pc)(T:=joinTs x0 s). apply t_prot with (T:=x0) . apply IHe with (T1:=T1).
apply H0. apply value_pc with (pc:=pc). apply H0. apply H1.
subst. apply t_sub with (pc:=x2)(T:=x1). apply H8. apply H9. apply H9. reflexivity. apply sub_refl. apply H6.
Case ("tcon").
intros. simpl. apply inversion_tcon in H2. inversion H2. inversion H3. inversion H4. inversion H5. inversion H7.
inversion H9. subst. destruct T2. destruct r. inversion H11. subst. apply t_sub with (pc:=pc)(T:=an int s). apply t_con.
apply sub_refl. apply subt_int. apply subsum_r_trans with (a:=s)(b:=x2)(c:=s0). apply H10. apply H12. inversion H11.
inversion H11. inversion H11.
Case ("tabs").
intros. simpl. remember (beq_id x i) as BB. destruct BB. apply inversion_tabs in H2.
inversion H2. inversion H3. inversion H4. inversion H5. inversion H6. inversion H7.
inversion H8. inversion H9. inversion H11. inversion H13. inversion H15. inversion H17.
inversion H19. inversion H21. destruct T2. destruct r. inversion H23. apply t_sub with (pc:=pc)(T:=an (fn t0 s1 t1) x6).
apply t_sub with (pc:=pc)(T:=an (fn t0 s1 t1) s). apply t_sub with (pc:=pc)(T:=an (fn x0 s1 t1) s). apply t_sub with (pc:=pc)(T:=an (fn t s1 t1) s).
apply t_sub with (pc:=pc)(T:=an (fn t x5 t1) s). apply t_sub with (pc:=pc)(T:=an (fn t x4 t1) s).
apply t_abs. apply t_sub with (pc:=x4)(T:=x2). apply t_sub with (pc:=x4)(T:=x1). apply beq_id_eq in HeqBB. rewrite->HeqBB in H12.
assert (Cupdate Gamma i (Some t) = Cupdate (Cupdate Gamma i (Some T1)) i (Some t)).
apply functional_extensionality. intros. remember (beq_id i x7) as CC. destruct CC.
apply beq_id_eq in HeqCC. rewrite->HeqCC. rewrite->Cupdate_eq.
rewrite->Cupdate_eq. reflexivity. symmetry in HeqCC. inversion HeqCC. inversion HeqCC.
apply Cupdate_neq with (T:= Some t)(St:=Gamma ) in HeqCC. rewrite->HeqCC.
apply Cupdate_neq with (T:= Some t)(St:=Cupdate Gamma i (Some T1)) in H25.
rewrite->H25. apply Cupdate_neq with (T:=Some T1)(St:=Gamma) in H26. rewrite->H26.
reflexivity. rewrite->H24. apply H12. apply sub_refl. apply H20. apply sub_refl. inversion H23. apply H35.
apply sub_refl. apply subt_fn. apply sub_refl. apply H14. apply subtyping_refl. apply subtyping_refl.
apply sub_refl. apply subt_fn. apply sub_refl. inversion H23. apply H33. apply subtyping_refl. apply subtyping_refl.
apply sub_refl. apply subt_fn. apply sub_refl. apply sub_refl. apply H18. apply subtyping_refl. apply sub_refl.
apply subt_fn. apply sub_refl. apply sub_refl. inversion H23. apply H34. apply subtyping_refl. apply sub_refl.
apply subt_fn. apply H22. apply sub_refl. apply subtyping_refl. apply subtyping_refl. apply sub_refl. apply subt_fn.
inversion H23. apply H29. apply sub_refl. apply subtyping_refl. apply subtyping_refl. inversion H23. inversion H23.
apply inversion_tabs in H2. inversion H2. inversion H3. inversion H4. inversion H5.
inversion H6. inversion H7. inversion H8. inversion H9. inversion H11. inversion H13. inversion H15.
inversion H17. inversion H19. inversion H21. destruct T2. destruct r. inversion H23.
apply t_sub with (pc:=pc)(T:=an (fn t0 s1 t1) x6). apply t_sub with (pc:=pc)(T:=an (fn t0 s1 t1) s).
apply t_sub with (pc:=pc)(T:=an (fn x0 s1 t1) s). apply t_sub with (pc:=pc)(T:=an (fn t s1 t1) s).
apply t_abs. apply IHe with (T1:=T1). apply H0. apply value_pc with (pc:=pc). apply H0. apply H1.
apply t_sub with (pc:=s1)(T:=x2). apply t_sub with (pc:=s1)(T:=x1). apply t_sub with (pc:=x5)(T:=x1).
apply t_sub with (pc:=x4)(T:=x1).
assert (Cupdate (Cupdate Gamma x (Some T1)) i (Some t) = Cupdate (Cupdate Gamma i (Some t)) x (Some T1)).
apply functional_extensionality. intros. remember (beq_id x x7) as AA.
remember (beq_id i x7) as BB. destruct AA. destruct BB. apply beq_id_eq in HeqAA.
apply beq_id_eq in HeqBB0. rewrite->HeqAA in HeqBB. rewrite->HeqBB0 in HeqBB.
rewrite<-beq_id_refl in HeqBB. inversion HeqBB. apply beq_id_eq in HeqAA. rewrite->HeqAA.
rewrite->Cupdate_eq. rewrite->HeqAA in HeqBB. symmetry in HeqBB. apply Cupdate_permute with (T1:=Some T1)(T2:=Some t)(X3:=x7)(f:=Gamma) in HeqBB.
rewrite->HeqBB. rewrite->Cupdate_eq. reflexivity. destruct BB. apply beq_id_eq in HeqBB0. rewrite->HeqBB0. rewrite->Cupdate_eq.
symmetry in HeqAA. apply Cupdate_permute with (T1:=Some T1)(T2:=Some t)(X3:=x7)(f:=Gamma) in HeqAA.
rewrite<-HeqAA. rewrite->Cupdate_eq. reflexivity. symmetry in HeqBB0. inversion HeqBB0.
apply Cupdate_neq with (T:=Some t)(St:=Cupdate Gamma x (Some T1))in HeqBB0.
rewrite->HeqBB0. symmetry in HeqAA. inversion HeqAA.
apply Cupdate_neq with (T:=Some T1)(St:=Gamma) in HeqAA.
rewrite->HeqAA. apply Cupdate_neq with (T:=Some T1)(St:=Cupdate Gamma i (Some t)) in H26.
rewrite->H26. apply Cupdate_neq with (T:=Some t)(St:=Gamma) in H25. rewrite->H25. reflexivity.
rewrite<-H24. apply H12.
apply H14. apply subtyping_refl. inversion H23. inversion H33. apply sub_refl. apply sub_LH.
apply subtyping_refl. apply sub_refl. apply H20. apply sub_refl. inversion H23. apply H35.
apply sub_refl. apply subt_fn. apply sub_refl. apply sub_refl.
apply H18. apply subtyping_refl. apply sub_refl. apply subt_fn. apply sub_refl. apply sub_refl.
inversion H23. apply H34. apply subtyping_refl. apply sub_refl. apply subt_fn. apply H22. apply sub_refl.
apply subtyping_refl. apply subtyping_refl. apply sub_refl. apply subt_fn. inversion H23. apply H29. apply sub_refl.
apply subtyping_refl. apply subtyping_refl. inversion H23. inversion H23.
Case ("tapp").
intros. simpl. apply inversion_tapp in H2. inversion H2. inversion H3. inversion H4. inversion H5. inversion H6.
inversion H7. inversion H8. inversion H9. inversion H10. inversion H11. inversion H12. inversion H14. inversion H16.
inversion H18.
apply t_sub with (pc:=pc)(T:=joinTs x5 x2).
apply t_app with (T1:=x4)(T2:=x5)(b:=x2).
apply IHe1 with (T1:=T1). apply H0. apply H1. apply t_sub with (pc:=x7)(T:= an (fn x4 (joins pc x2) x5) x2).
apply t_sub with (pc:=x7)(T:=an (fn x3 (joins pc x2) x5) x2). apply t_sub with (pc:=x7)(T:=an (fn x0(joins pc x2)x5)x2).
apply t_sub with (pc:=x7)(T:=an (fn x0 x8 x5) x2). apply t_sub with (pc:=x7)(T:=an (fn x0 x8 x1) x2).
apply H15. apply sub_refl. apply subt_fn. apply sub_refl. apply sub_refl. apply subtyping_refl. inversion H17. apply H32.
apply sub_refl. apply subt_fn. apply sub_refl. assert (subsum_r (joins pc x2) x8). rewrite->H13. destruct pc. destruct x7.
simpl. apply sub_refl. simpl. destruct x2. apply sub_LH. apply sub_refl. destruct x7. inversion H20. inversion H22. inversion H23.
simpl. apply sub_refl. apply H21. apply subtyping_refl. apply subtyping_refl. apply sub_refl. apply subt_fn. apply sub_refl. apply sub_refl.
inversion H17. apply H31. apply subtyping_refl. apply sub_refl. apply subt_fn. apply sub_refl. apply sub_refl. apply H20. apply subtyping_refl.
apply H20. apply subtyping_refl.
apply IHe2 with (T1:=T1). apply H0. apply H1. apply t_sub with (pc:=x7)(T:=x4). apply H19. inversion H20. apply H22.
apply subtyping_refl. reflexivity. apply sub_refl. assert (joinTs x5 x2 <: T2). apply subtyping_trans with (x:=joinTs x5 x6)(y:=joinTs x5 x6).
apply subtyping_refl. destruct x2. destruct x6. apply subtyping_refl. destruct x5. simpl. destruct r. apply subt_int. destruct s. apply sub_LH.
apply sub_refl. apply subt_fn. destruct s. apply sub_LH. apply sub_refl. apply sub_refl. apply subtyping_refl. apply subtyping_refl. apply subt_unit.
destruct s. apply sub_LH. apply sub_refl. apply subt_ref. destruct s. apply sub_LH. apply sub_refl. destruct x6. inversion H17. inversion H26. apply subtyping_refl.
apply H20. apply H21.
Case ("tunit").
intros. simpl. apply inversion_tunit in H2. inversion H2. inversion H3. inversion H4. inversion H5. inversion H7.
inversion H9. subst. destruct T2. destruct r. inversion H11. inversion H11. apply t_sub with (pc:=pc)(T:=an unit x2).
apply t_sub with (pc:=pc)(T:=an unit s). apply t_unit. apply sub_refl. apply subt_unit. apply H9. apply sub_refl. apply H11. inversion H11.
Case ("tref").
intros. simpl. apply inversion_tref in H2. inversion H2. inversion H3. inversion H4. inversion H5. inversion H6. inversion H7.
inversion H9. inversion H11. inversion H13. destruct T2. destruct r. inversion H14. inversion H14. inversion H14. apply t_sub with (pc:=pc)(T:=an (ref t0) x4).
apply t_sub with (pc:=pc)(T:=an (ref t0) s). inversion H14. subst. apply t_ref with (b':=joins pc s). apply IHe with (T1:=T1).
apply H0. apply value_pc with (pc:=pc). apply H0. apply H1. apply t_sub with (pc:=joins x1 s)(T:=x3). apply t_sub with (pc:=x0)(T:=x2). apply H15. apply H13.
apply H15. destruct pc. destruct x1. destruct s. apply sub_refl. apply sub_refl. destruct s. apply sub_LH. apply sub_refl. destruct x1. inversion H12. apply sub_refl.
apply H15. reflexivity. apply subsum_r_trans with (a:=joins pc s)(b:=joins x1 s)(c:=labelT t0). destruct pc. destruct x1. destruct s. apply sub_refl. apply sub_refl.
destruct s. apply sub_LH. apply sub_refl. destruct x1. inversion H12. apply sub_refl. apply subsum_r_trans with (a:=joins x1 s)(b:=labelT x2)(c:=labelT t0).
apply H15. apply subsum_r_trans with (a:=labelT x2)(b:=labelT x3)(c:=labelT t0). inversion H15. inversion H18. destruct x2. destruct x3. inversion H19. simpl. apply H22.
simpl. apply H25. simpl. apply H22. simpl. apply H22. inversion H15. inversion H18. inversion H20. destruct x3. destruct t0. inversion H21. simpl. apply H24. simpl. apply H27.
simpl. apply H24. simpl. apply H24. apply sub_refl. apply subt_ref. apply H10. apply sub_refl. apply subt_ref. inversion H14. apply H17.
Case ("tderef").
intros. simpl. apply inversion_tderef in H2. inversion H2. inversion H3. inversion H4. inversion H5.
apply t_sub with (pc:=pc)(T:=joinTs x1 x3).
apply t_deref with (T:=x1)(b:=x3). apply IHe with (T1:=T1).
apply H0. apply H1. apply t_sub with (pc:=x0)(T:=an (ref x1) x3). apply t_sub with (pc:=x0)(T:=an (ref x1) x2).
apply H6. apply sub_refl. apply subt_ref. apply H6. apply H6. apply subtyping_refl. reflexivity. apply sub_refl.
apply H6.
Case ("tloc").
intros. simpl. destruct o. apply inversion_tloc in H2. inversion H2. inversion H3. inversion H4. inversion H5. inversion H6.
inversion H8. inversion H10. inversion H12. inversion H14. subst. apply t_sub with (pc:=pc)(T:=an (ref t) x3). apply t_sub with (pc:=pc)(T:=an (ref t) s).
apply t_loc. inversion H7. subst. apply H6. apply sub_refl. apply subt_ref. apply H15. apply sub_refl. apply H6. apply inversion_tloc in H2. inversion H2.
inversion H3. inversion H4. inversion H5. inversion H6. inversion H7.
Case ("tassign").
intros. simpl. apply inversion_tassign in H2. inversion H2. inversion H3. inversion H4. inversion H5. apply t_sub with (pc:=pc)(T:=an unit (labelT x1)).
apply t_assign with (b:=x3)(T:=x1). reflexivity. apply subsum_r_trans with (a:=joins pc x3)(b:=joins x0 x3)(c:=labelT x1). destruct pc. destruct x0.
simpl. apply sub_refl. simpl. destruct x3. apply sub_LH. apply sub_refl. destruct x0. inversion H6. inversion H8. inversion H10. inversion H12. inversion H14.
inversion H15. simpl. apply sub_refl. apply H6. apply IHe1 with (T1:=T1). apply H0. apply H1. apply t_sub with (pc:=x0)(T:=an (ref x1) x3). apply H6.
apply H6. apply subtyping_refl. apply IHe2 with (T1:=T1). apply H0. apply H1. apply t_sub with (pc:=x0)(T:=x2). apply H6. apply H6. apply H6. apply sub_refl.
apply H6.
Qed.
(*heap_well_typed*)
Definition heap_well_typed (HT:heap_Ty) (hp:heap) :=
length HT = length hp /\
(*every value on the heap must be well-formed*)
(heap_well_formed hp (length hp))/\
(forall pc l, l < length hp ->
(*two additional constraints*)
(value (efst (heap_lookup l hp)))/\
extract (heap_Tlookup l HT) <: esnd (heap_lookup l hp) /\
subsum_r (labelT (esnd (heap_lookup l hp))) (label(efst (heap_lookup l hp))) /\
has_type pc empty_context HT (efst(heap_lookup l hp)) (extract (heap_Tlookup l HT))).
(**
Note the reason for having the additional constraint which requires for a well_typed a heap
typing is that the type on the heap subsums the corresponding typing in the heap typing.
Consider the following example which illustrates a well-typed stuck configuration,
has_type H empty_context [an int H] (tassign (tloc (an int H) 0 L)(tcon 1 L)) (an unit H)
with [(tcon 0 L,an int L)] as hp we have,
heap_well_typed [an int H] [(tcon 0 L,an int L)] for
a. has_type pc empty_context [an int H] (tcon 0 L)(an int H)
b. the label of the type on the heap is guarded by that of its type
c. they have the same length
Now,according to [progress] and set [PC=H] we should have,
exists p, tassign (tloc (an int H) 0 L)(tcon 1 L) / (tcon 0 L,an int L)
==H=> p
and according to [st_assign],we acctually have,
stuck_term (tassign (tloc (an int H) 0 L)(tcon 1 L)) [(tcon 0 L,an int L)] H.
Qed.
*)
(*Some instances of consistent heap typing [HT] w.r.t. some heap [hp]*)
Example test_heap_well_typed_1:
heap_well_typed (an int L :: an unit H :: an (fn (an int L) H (an int L)) L :: an (ref (an int L)) H :: nil)
((tcon 0 L,an int L) :: (tunit H,an unit H) :: (tabs (Id 0)(an int L)(tcon 0 L) L,an (fn (an int L) H (an int L)) L) :: (tloc (an int L) (Some 0) H,an (ref (an int L)) H) :: nil).
Proof. split. simpl. reflexivity. split. apply one_hwf. apply one_hwf. apply one_hwf. apply one_hwf. apply nil_hwf.
simpl. apply wf_tloc. apply le_S. apply le_S. apply le_S. apply le_n.
simpl. apply wf_tabs. apply wf_tcon. simpl. apply wf_tunit. simpl. apply wf_tcon.
split.
simpl in H0. inversion H0. simpl. apply v_l. inversion H2. simpl. apply v_f. inversion H4. simpl. apply v_u. inversion H6. simpl. apply v_c. inversion H8.
split. simpl in H0. inversion H0. simpl. apply subtyping_refl. inversion H2. simpl. apply subtyping_refl. inversion H4. simpl. apply subtyping_refl.
inversion H6. simpl. apply subtyping_refl. inversion H8.
split. simpl in H0. inversion H0. simpl. apply sub_refl. inversion H2. simpl. apply sub_refl. inversion H4. simpl. apply sub_refl.
inversion H6. simpl. apply sub_refl. inversion H8.
simpl in H0. inversion H0. simpl. apply t_loc. simpl. reflexivity. inversion H2. simpl. apply t_abs. apply t_con. inversion H4. simpl. apply t_unit. inversion H6. simpl.
apply t_con. inversion H8.
Qed.
Example test_heap_well_typed_2:
~heap_well_typed (an int L :: an unit H :: an (ref (an int L)) L :: nil)
((tcon 1 L,an int L) :: (tunit H,an unit H) :: nil).
Proof. intros contra. inversion contra. inversion H0. Qed.
Example test_heap_well_typed_3:
~heap_well_typed (an int L :: nil)
((tcon 0 H,an int H) :: nil).
Proof. intros contra. inversion contra. inversion H1. specialize (H3 H 0). simpl in H3.
assert (0 < 1). apply le_n. apply H3 in H4. inversion H4. inversion H6. inversion H8.
apply inversion_tcon in H10.
inversion H10. inversion H11. inversion H12. inversion H13. inversion H15.
inversion H17. subst. destruct x1. inversion H18. inversion H19. inversion H20.
Qed.
(*continue from here*)
Example test_heap_well_typed_4:
~heap_well_typed (an int L :: an unit H :: (an (ref (an int L)) L) :: nil)
((tcon 1 L,an int L) :: (tunit L,an unit H) :: (tloc (an int L) (Some 0) L,an (ref (an int L)) L) :: nil).
Proof. intros contra. inversion contra. inversion H1. specialize (H3 L 1). simpl in H3. assert (1<3). apply le_S. apply le_n. apply H3 in H4.
inversion H4. inversion H6. inversion H8. inversion H9.
Qed.
Example test_heap_well_typed_5:
~heap_well_typed ((an int H) :: nil)((tcon 0 L,an int L) :: nil).
Proof. intros contra. inversion contra. inversion H1. specialize (H3 L 0). simpl in H3. assert (0<1). apply le_n. apply H3 in H4.
inversion H4. inversion H6. inversion H7. inversion H11.
Qed.
(*heap extends*)
Inductive extends : heap_Ty -> heap_Ty -> Prop :=
| extends_nil : forall HT',
extends HT' nil
| extends_cons : forall x HT' HT,
extends HT' HT ->
extends (x::HT') (x::HT).
(*lemmas about extended contexts*)
Lemma zero_n:forall n,
0<=n.
Proof. intros. induction n. apply le_n. apply le_S.
apply IHn. Qed.
Lemma n_iff_Sn_left: forall n m,
n <= m -> S n <= S m.
Proof.
intros. induction H0. apply le_n. apply le_S. apply IHle.
Qed.
Lemma n_iff_Sn_right : forall n m,
S n <= S m -> n <= m.
Proof. intros. generalize dependent n. induction m.
intros. destruct n. apply le_n. inversion H0. inversion H2.
intros. inversion H0. apply le_n. apply le_S. apply IHm in H2.
apply H2. Qed.
Theorem n_iff_Sn : forall n m,
n <= m <-> S n <= S m.
Proof.
intros. split.
Case ("->"). apply n_iff_Sn_left.
Case ("<-"). apply n_iff_Sn_right.
Qed.
Lemma extends_lookup_last:forall hp p,
heap_lookup (length hp)(snoc hp p) = Some p.
Proof. intros hp. induction hp.
Case ("nil"). intros. simpl. reflexivity.
Case ("hd::t"). intros. simpl. apply IHhp.
Qed.
Lemma extends_Tlookup_last:forall HT T,
heap_Tlookup (length HT)(snoc HT T) = Some T.
Proof. intros HT. induction HT.
Case ("nil"). intros. simpl. reflexivity.
Case ("hd::t"). intros. simpl. apply IHHT.
Qed.
Lemma extends_lookup:forall l hp p,
l < length hp ->
heap_lookup l hp = heap_lookup l (snoc hp p).
Proof.
intros. generalize dependent hp. generalize dependent p. induction l.
intros. destruct hp. simpl in H0. inversion H0. simpl. reflexivity.
intros. destruct hp. simpl in H0. inversion H0. simpl in H0. unfold lt in H0.
apply n_iff_Sn_right in H0. simpl. apply IHl. unfold lt. apply H0. Qed.
Lemma extends_Tlookup:forall l HT HT',
l < length HT ->
extends HT' HT ->
heap_Tlookup l HT' = heap_Tlookup l HT.
Proof.
intros. generalize dependent l. induction H1.
Case ("extends_nil"). intros. destruct l. simpl in H0. inversion H0. simpl in H0.
inversion H0.
Case ("extends_cons"). intros. destruct l. reflexivity. apply IHextends. simpl in H0.
unfold lt in H0. unfold lt. apply n_iff_Sn in H0.
apply H0.
Qed.
Lemma length_extends:forall l HT HT',
l < length HT ->
extends HT' HT ->
l < length HT'.
Proof.
intros. generalize dependent l. induction H1.
intros. destruct l. unfold lt in H0. inversion H0. inversion H0.
intros. destruct l. admit. unfold lt. simpl. apply n_iff_Sn_left.
apply IHextends. simpl in H0. apply n_iff_Sn_right in H0. apply H0.
Qed.
Lemma extends_snoc: forall HT T,
extends (snoc HT T) HT.
Proof.
intros. generalize dependent T. induction HT.
intros. simpl. apply extends_nil.
intros. simpl. apply extends_cons. specialize (IHHT T). apply IHHT.
Qed.
Lemma extends_refl: forall HT,
extends HT HT.
Proof.
intros. induction HT. apply extends_nil. apply extends_cons.
apply IHHT. Qed.
Lemma extends_trans:forall HT HT' HT'',
extends HT' HT ->
extends HT'' HT' ->
extends HT'' HT.
Proof. intros. generalize dependent HT''. induction H0.
Case ("extends_nil"). intros. apply extends_nil.
Case ("extends_cons"). intros. destruct HT''. inversion H1. inversion H1.
apply extends_cons. apply IHextends. apply H3.
Qed.
Lemma change_HT':forall HT n T,
heap_Tlookup n HT = Some T ->
n < length HT.
Proof. intros. generalize dependent HT. generalize dependent T.
induction n. intros. destruct HT. simpl in H0. inversion H0. simpl.
apply n_iff_Sn_left. apply zero_n.
intros. destruct HT. simpl in H0. inversion H0. simpl in H0. apply IHn in H0.
unfold lt in H0. unfold lt. simpl. apply n_iff_Sn_left. apply H0. Qed.
Lemma change_HT: forall HT HT' pc Gamma t T,
extends HT' HT ->
has_type pc Gamma HT t T ->
has_type pc Gamma HT' t T.
Proof. intros. generalize dependent HT'. induction H1.
Case ("t_var"). intros. apply t_var. apply H0.
Case ("t_con"). intros. apply t_con.
Case ("t_unit"). intros. apply t_unit.
Case ("t_loc"). intros. apply t_loc. rewrite<-H0. apply extends_Tlookup.
apply change_HT' with (T:=T). apply H0. apply H1.
Case ("t_tabs"). intros. apply t_abs. apply IHhas_type. apply H0.
Case ("t_prot"). intros. subst. apply t_prot with (T:=T). apply IHhas_type. apply H2.
reflexivity.
Case ("t_app"). intros. subst. apply t_app with (T1:=T1)(T2:=T2)(b:=b). apply IHhas_type1. apply H1.
apply IHhas_type2. apply H1. reflexivity.
Case ("t_ref"). intros. apply t_ref with(b':=joins pc b). apply IHhas_type. apply H3. reflexivity. subst. apply H2.
Case ("t_deref"). intros. subst. apply t_deref with (T:=T)(b:=b). apply IHhas_type. apply H2. reflexivity.
Case ("t_assign"). intros. apply t_assign with (b:=b)(T:=T). apply H0. apply H1. apply IHhas_type1. apply H2.
apply IHhas_type2. apply H2.
Case ("t_sub"). intros. apply IHhas_type in H3. apply t_sub with (pc:=pc)(T:=T). apply H3. apply H0. apply H2.
Qed.
(*#######################end###################*)
(*preservation*)
(*some auxiliary lemmas*)
Lemma joins_refl:forall a b,
joins a b = joins b a.
Proof. intros. destruct a. destruct b. reflexivity.
reflexivity. destruct b. reflexivity. reflexivity.
Qed.
Lemma joins_subsum:forall a b,
subsum_r a b ->
joins a b = b.
Proof. intros. destruct a. destruct b. reflexivity. reflexivity.
destruct b. inversion H0. reflexivity.
Qed.
Lemma subsum_guard:forall a b,
subsum_r a (joins a b).
Proof. destruct a. destruct b. apply sub_refl. apply sub_LH. destruct b.
apply sub_refl. apply sub_refl. Qed.
Lemma joins_b:forall s1 s2 b,
subsum_r s1 s2 ->
subsum_r (joins s1 b)(joins s2 b).
Proof. intros. destruct s1. destruct s2. destruct b.
simpl. apply sub_refl. simpl. apply sub_refl. destruct b. simpl. apply sub_LH.
simpl. apply sub_refl. destruct b. destruct s2. inversion H0. simpl. apply H0.
destruct s2. inversion H0. simpl. apply sub_refl. Qed.
Lemma subsum_joins:forall a b c,
subsum_r a c ->
subsum_r b c ->
subsum_r (joins a b) c.
Proof. intros. destruct a. destruct b. destruct c.
simpl. apply sub_refl. simpl. apply sub_LH. destruct c. inversion H1. simpl. apply sub_refl.
destruct c. inversion H0. destruct b. simpl. apply sub_refl. simpl. apply sub_refl.
Qed.
Lemma subsum_equal:forall a b,
subsum_r a b ->
subsum_r b a ->
a = b.
Proof. intros. destruct a. destruct b. reflexivity. inversion H1. destruct b. inversion H0. reflexivity.
Qed.
Lemma subsum_low:forall a,
subsum_r a L ->
a = L.
Proof. intros. destruct a. reflexivity. inversion H0.
Qed.
Lemma joinTs_b:forall r s b,
joinTs (an r s) b = an r (joins s b).
Proof. intros. destruct s. destruct b. simpl. reflexivity.
simpl. reflexivity. simpl. destruct b. reflexivity. reflexivity.
Qed.
Lemma join_tcon_b:forall n s b,
joinvs (tcon n s) b = tcon n (joins s b).
Proof. intros. destruct b. destruct s. simpl. reflexivity. simpl. reflexivity.
destruct s. simpl. reflexivity. simpl. reflexivity.
Qed.
Lemma join_tabs_b:forall n T e s b,
joinvs (tabs (Id n) T e s) b = tabs (Id n) T e (joins s b).
Proof. destruct s. destruct b. simpl. reflexivity. simpl. reflexivity.
intros. destruct b. simpl. reflexivity. simpl. reflexivity. Qed.
Lemma join_tunit_b:forall s b,
joinvs (tunit s) b = tunit (joins s b).
Proof. intros. destruct s. destruct b. simpl. reflexivity. simpl. reflexivity.
destruct b. simpl. reflexivity. simpl. reflexivity. Qed.
Lemma join_tloc_b:forall T N s b,
joinvs (tloc T N s) b = tloc T N (joins s b).
Proof. intros. destruct s. destruct b. simpl. reflexivity. simpl. reflexivity.
destruct b. simpl. reflexivity. simpl. reflexivity. Qed.
Lemma join_tcon_H:forall n b,
joinvs (tcon n H) b = tcon n H.
Proof. intros. destruct b. reflexivity. reflexivity.
Qed.
Lemma join_tabs_H:forall x T e b,
joinvs (tabs x T e H) b = tabs x T e H.
Proof. intros. destruct b. reflexivity. reflexivity.
Qed.
Lemma join_tunit_H:forall b,
joinvs (tunit H) b = tunit H.
Proof. intros. destruct b. reflexivity. reflexivity.
Qed.
Lemma join_tloc_H:forall T N b,
joinvs (tloc T N H) b = tloc T N H.
Proof. intros. destruct b. reflexivity. reflexivity.
Qed.
Lemma label_joinvs:forall t a,
value t ->
label (joinvs t a) = joins (label t) a.
Proof. intros. inversion H0. rewrite->join_tcon_b. reflexivity. rewrite->join_tabs_b. simpl.
reflexivity. rewrite->join_tunit_b. reflexivity. rewrite->join_tloc_b. reflexivity.
Qed.
Lemma joinTs_same:forall T,
joinTs T (labelT T) = T.
Proof. intros. destruct T. simpl. destruct s. reflexivity. reflexivity.
Qed.
Lemma sub_T_b:forall a b r,
subsum_r a b ->
an r a <: an r b.
Proof. intros. destruct r. apply subt_int. apply H0. apply subt_fn. apply H0. apply sub_refl.
apply subtyping_refl. apply subtyping_refl. apply subt_unit. apply H0. apply subt_ref. apply H0.
Qed.
Lemma joinTs_subtyping_s:forall T b' b,
subsum_r b' b ->
joinTs T b' <: joinTs T b.
Proof. intros. inversion H0. apply subtyping_refl. destruct T. simpl.
destruct r. destruct s. apply subt_int. apply sub_LH. apply subtyping_refl.
destruct s. apply subt_fn. apply sub_LH. apply sub_refl. apply subtyping_refl.
apply subtyping_refl. apply subtyping_refl. apply subt_unit. destruct s. apply sub_LH.
apply sub_refl. apply subt_ref. destruct s. apply sub_LH. apply sub_refl.
Qed.
Lemma joinTs_subtyping_T:forall T1 T2 b,
T1 <: T2 ->
joinTs T1 b <: joinTs T2 b.
Proof. intros. destruct T1. destruct T2. rewrite->joinTs_b. rewrite->joinTs_b.
inversion H0. subst. apply subt_int. apply joins_b. apply H2. subst. apply subt_fn.
apply joins_b. apply H5. apply H6. apply H7. apply H8. subst. apply subt_unit.
apply joins_b. apply H2. subst. apply subt_ref. apply joins_b. apply H2. Qed.
Lemma subtyping_subsum:forall T1 T2,
T1 <: T2 ->
subsum_r (labelT T1)(labelT T2).
Proof. intros. inversion H0. subst. simpl. apply H1. subst. simpl. apply H1.
subst. simpl. apply H1. subst. simpl. apply H1.
Qed.
Lemma joins_subtyping_1:forall s1 s1' s2,
subsum_r s1 s1' ->
subsum_r (joins s1 s2)(joins s1' s2).
Proof. intros. destruct s1. destruct s1'. destruct s2. simpl. apply sub_refl.
simpl. apply sub_refl. simpl. destruct s2. apply sub_LH. apply sub_refl. destruct s1'.
inversion H0. simpl. apply sub_refl. Qed.
Lemma joins_subtyping_2:forall s1 s2 s2',
subsum_r s2 s2' ->
subsum_r (joins s1 s2)(joins s1 s2').
Proof. intros. destruct s1. destruct s2. destruct s2'. simpl. apply sub_refl. simpl. apply sub_LH.
destruct s2'. inversion H0. simpl. apply sub_refl. simpl. apply sub_refl. Qed.
Lemma value_b:forall t b,
value t ->
value (joinvs t b).
Proof. intros. inversion H0. rewrite->join_tcon_b. apply v_c. rewrite->join_tabs_b. apply v_f.
rewrite->join_tunit_b. apply v_u. rewrite->join_tloc_b. apply v_l. Qed.
Lemma has_type_value_joinvs:forall pc b Gamma HT t T,
value t ->
subsum_r pc b ->
subsum_r b (labelT T) ->
has_type pc Gamma HT t T ->
has_type pc Gamma HT (joinvs t b) T.
Proof. intros. inversion H0.
Case ("tcon").
intros. rewrite->join_tcon_b. subst. apply inversion_tcon in H3. inversion H3. inversion H4.
inversion H5. inversion H6. inversion H8. inversion H10. subst. destruct T. destruct r.
simpl in H2. apply t_sub with (pc:=pc)(T:=an int (joins b0 b)). apply t_con. apply sub_refl.
apply subt_int. apply subsum_joins. apply subsum_r_trans with (a:=b0)(b:=x1)(c:=s). apply H6.
inversion H12. apply H13. apply H2. inversion H12.
inversion H12. inversion H12.
Case ("tabs").
intros. rewrite->join_tabs_b. subst. apply inversion_tabs in H3. inversion H3. inversion H4. inversion H5.
inversion H6. inversion H7. inversion H8. inversion H9. inversion H10. inversion H12. inversion H14.
inversion H16. inversion H18. inversion H20. inversion H22. destruct T. destruct r. inversion H24.
simpl in H2. apply t_sub with (pc:=pc)(T:=an (fn t s0 t0) (joins b0 b)). apply t_sub with (pc:=pc)(T:=an (fn x s0 t0)(joins b0 b)).
apply t_sub with (pc:=pc)(T:=an (fn T0 s0 t0) (joins b0 b)). apply t_abs. apply t_sub with (pc:=x4)(T:=x1). apply t_sub with (pc:=x3)(T:=x0).
apply H13. apply H15. apply H21. inversion H24. apply H34. inversion H24. apply H36. apply sub_refl. apply subt_fn. apply sub_refl. apply sub_refl.
apply H19. apply subtyping_refl. apply sub_refl. apply subt_fn. apply sub_refl. apply sub_refl. inversion H24. apply H35. apply subtyping_refl. apply sub_refl.
apply subt_fn. apply subsum_joins. apply subsum_r_trans with (a:=b0)(b:=x5)(c:=s). apply H23. inversion H24. apply H30. apply H2. apply sub_refl. apply subtyping_refl.
apply subtyping_refl. inversion H24. inversion H24.
Case ("tunit").
intros. rewrite->join_tunit_b. subst. apply inversion_tunit in H3. inversion H3. inversion H4. inversion H5. inversion H6. inversion H8. inversion H10.
subst. destruct T. destruct r. inversion H12. inversion H12. apply t_sub with (pc:=pc)(T:=an unit (joins b0 b)).
apply t_unit. apply sub_refl. apply subt_unit. apply subsum_joins. apply subsum_r_trans with (a:=b0)(b:=x1)(c:=s). apply H6. inversion H12. apply H13.
simpl in H2. apply H2. inversion H12.
Case ("tloc").
intros. rewrite->join_tloc_b. subst. apply inversion_tloc in H3. inversion H3. inversion H4. inversion H5. inversion H6. inversion H7. inversion H9. inversion H11. inversion H13. inversion H15. subst.
destruct T. destruct r. inversion H17. inversion H17. inversion H17. inversion H17. subst. simpl in H2. apply t_sub with (pc:=pc)(T:=an (ref t) (joins b0 b)). apply t_loc. inversion H8. subst.
apply H7. apply sub_refl. apply subt_ref. apply subsum_joins. apply subsum_r_trans with (a:=b0)(b:=x2)(c:=s). apply H11. inversion H17. apply H18. apply H2.
Qed.
Lemma has_type_joinvs_sub:forall pc b b' Gamma HT t T,
value t ->
subsum_r b b' ->
has_type pc Gamma HT (joinvs t b') T ->
has_type pc Gamma HT (joinvs t b) T.
Proof. intros. inversion H0.
Case ("tcon").
rewrite->join_tcon_b. subst. rewrite->join_tcon_b in H2. apply inversion_tcon in H2. inversion H2. inversion H3. inversion H4. inversion H5. inversion H7.
inversion H9. subst. destruct T. destruct r. apply t_sub with (pc:=pc)(T:=an int x1). apply t_sub with (pc:=pc)(T:=an int (joins b0 b')).
apply t_sub with (pc:=pc)(T:=an int (joins b0 b)). apply t_con. apply sub_refl. apply subt_int. apply joins_subtyping_2. apply H1. apply sub_refl. apply subt_int.
apply H5. apply sub_refl. apply H11. inversion H11. inversion H11. inversion H11.
Case ("tabs").
rewrite->join_tabs_b. subst. rewrite->join_tabs_b in H2. apply inversion_tabs in H2. inversion H2. inversion H3. inversion H4. inversion H5. inversion H6. inversion H7.
inversion H8. inversion H9. inversion H11. inversion H13. inversion H15. inversion H17. inversion H19. inversion H21. destruct T. destruct r. inversion H23. apply t_sub with (pc:=pc)(T:=an (fn t s0 t0) x5).
apply t_sub with (pc:=pc)(T:=an (fn t s0 t0) (joins b0 b')). apply t_sub with (pc:=pc)(T:=an (fn t s0 t0)(joins b0 b)). apply t_sub with (pc:=pc)(T:=an (fn x s0 t0)(joins b0 b)).
apply t_sub with (pc:=pc)(T:=an (fn T0 s0 t0)(joins b0 b)). apply t_abs. apply t_sub with (pc:=x4)(T:=x1). apply t_sub with (pc:=x3)(T:=x0). apply H12. apply H14. apply H20. inversion H23. apply H33.
inversion H23. apply H35. apply sub_refl. apply subt_fn. apply sub_refl. apply sub_refl. apply H18. apply subtyping_refl. apply sub_refl. apply subt_fn. apply sub_refl. apply sub_refl. inversion H23. inversion H34. subst.
apply H34. subst. apply H34. subst. apply H34. subst. apply H34. apply subtyping_refl. apply sub_refl. apply subt_fn. apply joins_subtyping_2. apply H1. apply sub_refl. apply subtyping_refl. apply subtyping_refl. apply sub_refl.
apply subt_fn. apply H22. apply sub_refl. apply subtyping_refl. apply subtyping_refl. apply sub_refl. apply subt_fn. inversion H23. apply H29. apply sub_refl. apply subtyping_refl. apply subtyping_refl. inversion H23. inversion H23.
Case ("tunit").
rewrite->join_tunit_b. subst. rewrite->join_tunit_b in H2. apply inversion_tunit in H2. inversion H2. inversion H3. inversion H4. inversion H5. inversion H7. inversion H9. subst. destruct T. destruct r. inversion H11. inversion H11.
apply t_sub with (pc:=pc)(T:=an unit x1). apply t_sub with (pc:=pc)(T:=an unit (joins b0 b')). apply t_sub with (pc:=pc)(T:=an unit (joins b0 b)). apply t_unit. apply sub_refl. apply subt_unit. apply joins_subtyping_2. apply H1. apply sub_refl.
apply subt_unit. apply H5. apply sub_refl. apply H11. inversion H11.
Case ("tloc").
rewrite->join_tloc_b. subst. rewrite->join_tloc_b in H2. apply inversion_tloc in H2. inversion H2. inversion H3. inversion H4. inversion H5. inversion H6. inversion H8. inversion H10. inversion H12. inversion H14. subst. destruct T. destruct r. inversion H16. inversion H16. inversion H16.
inversion H16. subst. apply t_sub with (pc:=pc)(T:=an (ref t) x2). apply t_sub with (pc:=pc)(T:=an (ref t) (joins b0 b')).
apply t_sub with (pc:=pc)(T:=an (ref t) (joins b0 b)). apply t_loc. inversion H7. subst. apply H6. apply sub_refl. apply subt_ref. apply joins_subtyping_2. apply H1. apply sub_refl. apply subt_ref. apply H10. apply sub_refl. apply subt_ref. inversion H16. apply H17.
Qed.
Lemma has_type_joinvs_b:forall pc HT t T b,
value t ->
has_type pc empty_context HT t T ->
has_type pc empty_context HT (joinvs t b) (joinTs T b).
Proof.
intros. inversion H0.
Case ("tcon").
intros. rewrite->join_tcon_b. subst. apply inversion_tcon in H1. inversion H1. inversion H2. inversion H3. inversion H4. inversion H6.
inversion H8. subst. destruct T. destruct r. rewrite->joinTs_b. apply t_sub with (pc:=pc)(T:=an int (joins b0 b)). apply t_con. apply sub_refl.
apply subt_int. apply joins_subtyping_1. apply subsum_r_trans with (a:=b0)(b:=x1)(c:=s). apply H9. inversion H10. apply H11. inversion H10.
inversion H10. inversion H10.
Case ("tabs").
intros. rewrite->join_tabs_b. subst. apply inversion_tabs in H1. inversion H1. inversion H2. inversion H3. inversion H4. inversion H5. inversion H6.
inversion H7. inversion H8. inversion H10. inversion H12. inversion H14. inversion H16. inversion H18. inversion H20. destruct T. destruct r. inversion H22.
rewrite->joinTs_b. apply t_sub with (pc:=pc)(T:=an (fn t s0 t0) (joins b0 b)). apply t_sub with (pc:=pc)(T:=an (fn x s0 t0) (joins b0 b)).
apply t_sub with (pc:=pc)(T:=an (fn T0 s0 t0)(joins b0 b)). apply t_abs. apply t_sub with (pc:=x4)(T:=x1). apply t_sub with (pc:=x3)(T:=x0).
apply H11. inversion H13. apply sub_refl. apply sub_LH. apply H19. inversion H22. apply H32. inversion H22. apply H34. apply sub_refl. apply subt_fn. apply sub_refl.
apply sub_refl. apply H17. apply subtyping_refl. apply sub_refl. apply subt_fn. apply sub_refl. apply sub_refl. inversion H22. apply H33. apply subtyping_refl. apply sub_refl.
apply subt_fn. apply joins_subtyping_1. apply subsum_r_trans with (a:=b0)(b:=x5)(c:=s). apply H21. inversion H22. apply H28. apply sub_refl. apply subtyping_refl. apply subtyping_refl.
inversion H22. inversion H22.
Case ("tunit").
intros. rewrite->join_tunit_b. subst. apply inversion_tunit in H1. inversion H1. inversion H2. inversion H3. inversion H4. inversion H6. inversion H8. subst. destruct T. destruct r. inversion H10.
inversion H10. rewrite->joinTs_b. apply t_sub with (pc:=pc)(T:=an unit (joins b0 b)). apply t_unit. apply sub_refl. apply subt_unit. apply joins_subtyping_1. apply subsum_r_trans with (a:=b0)(b:=x1)(c:=s).
apply H9. inversion H10. apply H11. inversion H10.
Case ("tloc").
intros. rewrite->join_tloc_b. subst. apply inversion_tloc in H1. inversion H1. inversion H2. inversion H3. inversion H4. inversion H5. inversion H7. inversion H9.
inversion H11. inversion H13. subst. destruct T. destruct r. inversion H15. inversion H15. inversion H15. rewrite->joinTs_b. inversion H15. subst. apply t_sub with (pc:=pc)(T:=an (ref t)(joins b0 b)).
apply t_loc. inversion H6. subst. apply H5. apply sub_refl. apply subt_ref. apply joins_subtyping_1. apply subsum_r_trans with (a:=b0)(b:=x2)(c:=s). apply H9. inversion H15. apply H16.
Qed.
Lemma l_lt_hp:forall (T:Type)(l:nat) (hp:list T),
l <= length hp ->
l <> length hp ->
l < length hp.
Proof. intros. unfold not in H1. unfold lt. inversion H0. apply H1 in H2. inversion H2.
apply n_iff_Sn_left. apply H3. Qed.
Lemma labelT_subsum_labelt:forall pc HT t T,
value t ->
has_type pc empty_context HT t T ->
subsum_r (label t)(labelT T).
Proof. intros. inversion H0.
Case ("tcon"). subst. apply inversion_tcon in H1. inversion H1. inversion H2. inversion H3. inversion H4.
inversion H6. inversion H8. subst. apply subtyping_subsum in H10. simpl in H10. apply subsum_r_trans with (a:=label (tcon n b))(b:=x1)(c:=labelT T).
compute. apply H9. apply H10.
Case ("tabs"). subst. apply inversion_tabs in H1. inversion H1. inversion H2. inversion H3. inversion H4. inversion H5. inversion H6. inversion H7. inversion H8.
inversion H10. inversion H12. inversion H14. inversion H16. inversion H18. inversion H20. apply subtyping_subsum in H22. simpl in H22. compute. destruct T. simpl in H22.
apply subsum_r_trans with (a:=b)(b:=x5)(c:=s). apply H21. apply H22.
Case ("tunit"). subst. apply inversion_tunit in H1. inversion H1. inversion H2. inversion H3. inversion H4. inversion H6. inversion H8. subst. apply subtyping_subsum in H10. simpl in H10.
apply subsum_r_trans with (a:=label (tunit b))(b:=x1)(c:=labelT T). compute. apply H9. apply H10.
Case ("tloc"). subst. apply inversion_tloc in H1. inversion H1. inversion H2. inversion H3. inversion H4. inversion H5. inversion H7. inversion H9. inversion H11. inversion H13. subst. apply subtyping_subsum in H15. simpl in H15.
apply subsum_r_trans with (a:=label (tloc T0 (Some n) b))(b:=x2)(c:=labelT T). compute. apply H9. apply H15.
Qed.
(**
Lemma well_formed_heap_extend:forall t hp C,
well_formed t hp ->
well_formed t (snoc hp C).
Proof. intros t. induction t.
Case ("tvar"). intros. apply wf_tvar.
Case ("tprot"). intros. apply wf_tprot. apply IHt. inversion H0. apply H4.
Case ("tcon"). intros. apply wf_tcon.
Case ("tabs"). intros. apply wf_tabs. apply IHt. inversion H0. apply H6.
Case ("tapp"). intros. apply wf_tapp. apply IHt1. inversion H0. apply H3.
apply IHt2. inversion H0. apply H5.
Case ("tunit"). intros. apply wf_tunit.
Case ("tref"). intros. apply wf_tref. apply IHt. inversion H0. apply H5.
Case ("tderef"). intros. apply wf_tderef. apply IHt. inversion H0. apply H2.
Case ("tloc"). intros. destruct o. apply wf_tloc. rewrite->length_snoc. apply le_S. inversion H0. apply H5.
inversion H0.
Case ("tassign"). intros. apply wf_tassign. apply IHt1. inversion H0. apply H3. apply IHt2. inversion H0.
apply H5.
Qed.
*)
(**
Lemma well_formed_heap_replace:forall t hp C x,
well_formed t hp ->
well_formed t (heap_replace x C hp).
Proof. intros t. induction t.
Case ("tvar"). intros. apply wf_tvar.
Case ("tprot"). intros. apply wf_tprot. apply IHt. inversion H0. apply H4.
Case ("tcon"). intros. apply wf_tcon.
Case ("tabs"). intros. apply wf_tabs. apply IHt. inversion H0. apply H6.
Case ("tapp"). intros. apply wf_tapp. apply IHt1. inversion H0. apply H3. apply IHt2. inversion H0.
apply H5.
Case ("tunit"). intros. apply wf_tunit.
Case ("tref"). intros. apply wf_tref. apply IHt. inversion H0. apply H5.
Case ("tderef"). intros. apply wf_tderef. apply IHt. inversion H0. apply H2.
Case ("tloc"). intros. destruct o. apply wf_tloc. rewrite->length_replace. inversion H0.
apply H5. inversion H0.
Case ("tassign"). intros. apply wf_tassign. apply IHt1. inversion H0. apply H3. apply IHt2. inversion H0.
apply H5.
Qed.
*)
(**
Lemma well_formed_joinvs_b:forall t hp b C,
value t ->
well_formed t hp ->
well_formed (joinvs t b) (snoc hp C).
Proof. intros. inversion H0.
Case ("tcon"). subst. rewrite->join_tcon_b. apply wf_tcon.
Case ("tabs"). subst. rewrite->join_tabs_b. apply wf_tabs. inversion H1. subst. apply well_formed_heap_extend.
apply H7.
Case ("tunit"). rewrite->join_tunit_b. apply wf_tunit.
Case ("tloc"). rewrite->join_tloc_b. apply wf_tloc. subst. inversion H1. subst. rewrite->length_snoc. apply le_S.
apply H6.
Qed.
*)
Lemma well_formed_b:forall t hp b,
value t ->
well_formed t hp ->
well_formed (joinvs t b) hp.
Proof. intros. inversion H0.
Case ("tcon"). subst. rewrite->join_tcon_b. apply wf_tcon.
Case ("tabs"). subst. rewrite->join_tabs_b. apply wf_tabs.
inversion H1. apply H7.
Case ("tunit"). subst. rewrite->join_tunit_b. apply wf_tunit.
Case ("tloc"). subst. rewrite->join_tloc_b. apply wf_tloc. inversion H1.
apply H6.
Qed.
(*type preservation*)
Theorem preservation:forall pc PC HT t t' T hp hp',
has_type pc empty_context HT t T ->
heap_well_typed HT hp ->
t / hp ==PC=> t' / hp' ->
subsum_r PC pc ->
exists HT',
(extends HT' HT /\
has_type pc empty_context HT' t' T /\
heap_well_typed HT' hp').
Proof.
intros. remember (@empty_context) as context. generalize dependent hp.
generalize dependent hp'. generalize dependent t'. generalize dependent PC.
induction H0.
Case ("t_var").
intros. inversion H2.
Case ("t_con").
intros. inversion H2.
Case ("t_unit").
intros. inversion H2.
Case ("t_loc").
intros. inversion H2.
Case ("t_abs").
intros. inversion H2.
Case ("t_prot").
intros. inversion H4. subst. apply IHhas_type in H13. inversion H13. exists x.
split. apply H1. split. apply t_prot with (T:=T). apply H1. reflexivity. apply H1.
reflexivity. apply joins_subtyping_1. apply H3. apply H2.
subst. exists HT. split. apply extends_refl. split. apply value_pc with (pc:=joins pc b).
apply value_b. apply H13. apply has_type_joinvs_b. apply H13. apply H0. apply H2.
Case ("t_app").
intros. inversion H2. subst. exists HT. split. apply extends_refl. split. apply inversion_tabs in H0_. inversion H0_. inversion H0. inversion H4. inversion H5. inversion H6. inversion H7. inversion H8.
inversion H9. inversion H15. inversion H17. inversion H19. inversion H21. inversion H23. inversion H25.
apply t_sub with (pc:=pc)(T:=joinTs T2 x6). apply t_sub with (pc:=pc)(T:=joinTs T2 b0). apply t_prot with (T:=T2).
apply t_sub with (pc:=x5)(T:=T2). apply t_sub with (pc:=x4)(T:=T2). apply t_sub with (pc:=x4)(T:=x2). apply t_sub with (pc:=x4)(T:=x1). apply value_pc with (pc':=x4) in H0_0.
apply t_sub with (pc':=x4)(T':=x0)in H0_0. apply t_sub with (pc':=x4)(T':=T) in H0_0. apply substitution_preserves_typing with (T1:=T). apply H13. apply H0_0. apply H16. apply sub_refl.
apply H22. apply sub_refl. inversion H27. apply H38. apply H13. apply sub_refl. apply H24. apply sub_refl.
inversion H27. apply H39. apply H18. apply subtyping_refl. apply subsum_r_trans with (a:=joins pc b0)(b:=joins pc b)(c:=x5). apply subsum_r_trans with (a:=joins pc b0)(b:=joins pc x6)(c:=joins pc b).
apply joins_subtyping_2. apply H26. apply joins_subtyping_2. inversion H27. apply H33. inversion H27. apply H37. apply subtyping_refl. reflexivity. apply sub_refl. apply joinTs_subtyping_s. apply H26. apply sub_refl.
apply joinTs_subtyping_s. inversion H27. apply H33. apply H1. subst.
apply IHhas_type1 in H13. inversion H13. exists x. split. apply H0. split. apply t_app with (T1:=T1)(T2:=T2)(b:=b). apply H0. apply change_HT with (HT:=HT). apply H0. apply H0_0. reflexivity. apply H0. reflexivity. apply H3. apply H1.
subst. apply IHhas_type2 in H14. inversion H14. exists x. split. apply H0. split. apply t_app with (T1:=T1)(T2:=T2)(b:=b). apply change_HT with (HT:=HT). apply H0. apply H0_. apply H0. reflexivity. apply H0. reflexivity. apply H3.
apply H1.
Case ("t_ref").
intros. inversion H5. subst. exists (snoc HT T). split. apply extends_snoc. split. apply t_loc. inversion H4.
rewrite<-H1. rewrite->extends_Tlookup_last. reflexivity. split.
rewrite->length_snoc. rewrite->length_snoc. inversion H4. rewrite->H1. reflexivity.
inversion H4. split. rewrite->length_snoc. apply heap_well_formed_extend. apply H6. apply well_formed_b. apply H14. apply H13.
(*continue from here*)
intros. remember (beq_nat l (length hp)) as CC. destruct CC. apply beq_nat_eq in HeqCC. rewrite->HeqCC. assert (heap_Tlookup (length hp)(snoc HT T) = heap_Tlookup (length HT)(snoc HT T)).
rewrite<-H1. reflexivity. rewrite->H8. rewrite->extends_Tlookup_last. simpl. rewrite->extends_lookup_last. simpl. split. apply value_b. apply H14. split. apply subtyping_refl. split.
rewrite->joins_refl.
assert (subsum_r (joins PC b)(labelT T)). apply subsum_r_trans with (a:=joins PC b)(b:=joins pc b)(c:=labelT T). apply joins_subtyping_1. apply H3. apply H2.
apply joins_subsum in H9. assert (joins PC b = joins b PC). rewrite->joins_refl. reflexivity. rewrite->H10 in H9. rewrite->H9. inversion H14. subst. rewrite->join_tcon_b. assert (label (tcon n (joins b0 (labelT T)))=joins b0 (labelT T)). reflexivity.
rewrite->joins_refl. compute. apply subsum_guard. rewrite->join_tabs_b. rewrite->joins_refl. compute. apply subsum_guard. rewrite->join_tunit_b. rewrite->joins_refl. compute. apply subsum_guard. rewrite->join_tloc_b. rewrite->joins_refl. compute. apply subsum_guard.
apply change_HT with (HT:=HT). apply extends_snoc. apply value_pc with (pc:=joins pc b). apply value_b. apply H14. apply t_sub with (pc:=joins pc b)(T:=joinTs T (joins (labelT T)(joins b PC))).
apply has_type_joinvs_b. apply H14. apply H0. apply sub_refl. assert (subsum_r (joins b PC)(labelT T)). apply subsum_r_trans with (a:=joins b PC)(b:=joins b pc)(c:=labelT T). apply joins_subtyping_2. apply H3. rewrite->joins_refl.
apply H2. apply joins_subsum in H9. rewrite->joins_refl. rewrite->H9. destruct T. simpl. destruct s. apply subtyping_refl. apply subtyping_refl.
symmetry in HeqCC. apply beq_nat_false in HeqCC. unfold lt in H7. rewrite ->length_snoc in H7. apply n_iff_Sn_right in H7. assert (l < length hp). apply l_lt_hp. apply H7. apply HeqCC. clear H7. clear HeqCC. assert (l <length hp). apply H8. assert (l <length hp).
apply H8. rewrite<-H1 in H8. apply extends_lookup with (p:=(joinvs t (joins (labelT T)(joins b PC)),T))in H7. rewrite<-H7. apply extends_Tlookup with (HT':=snoc HT T) in H8. rewrite->H8. split. inversion H6. specialize (H11 pc0 l). apply H11 in H9. apply H9. split.
inversion H6. specialize (H11 pc0 l). apply H11 in H9. apply H9. split.
inversion H6. specialize (H11 pc0 l). apply H11 in H9. apply H9.
inversion H6. specialize (H11 pc0 l). apply H11 in H9.
apply change_HT with (HT:=HT). apply extends_snoc. apply H9.
apply extends_snoc. subst. destruct b. rewrite->joins_refl in H15. simpl in H15.
apply IHhas_type in H15. inversion H15. exists x. split. apply H1. split. apply t_ref with (b':=joins pc L). apply H1. reflexivity. apply H2. apply H1. reflexivity. rewrite->joins_refl. simpl. apply H3. apply H4. rewrite->joins_refl in H15. simpl in H15.
apply IHhas_type in H15. inversion H15. exists x. split. apply H1. split. apply t_ref with (b':=joins pc H). apply H1. reflexivity. apply H2. apply H1. reflexivity. rewrite->joins_refl. simpl. apply sub_refl. apply H4.
Case ("t_deref").
intros. inversion H4. subst. exists HT. split. apply extends_refl. split. apply inversion_tloc in H0. inversion H0. inversion H1. inversion H5. inversion H6. inversion H7. inversion H9. inversion H13. inversion H15. inversion H17.
subst. apply t_sub with (pc:=pc)(T:=joinTs T x2). apply t_sub with (pc:=pc)(T:=joinTs T b0). apply t_prot with (T:=T). inversion H19. subst. inversion H2. inversion H20. apply H22 with (pc:=joins pc b0)in H11. inversion H7. inversion H23. subst. rewrite->H12 in H11. simpl in H11.
inversion H11. inversion H26. inversion H28. apply H30.
reflexivity. apply sub_refl. apply joinTs_subtyping_s. apply H13. apply sub_refl. apply joinTs_subtyping_s. inversion H19. apply H16. apply H2. subst.
apply IHhas_type in H12. inversion H12. exists x. split. apply H1. split. apply t_deref with (T:=T)(b:=b). apply H1. reflexivity. apply H1. reflexivity. apply H3. apply H2.
Case ("t_assign").
intros. inversion H4. subst. exists HT. split. apply extends_refl. split. apply t_sub with (pc:=pc)(T:=an unit (joins pc b)).
apply t_sub with (pc:=pc)(T:=an unit (joins PC b)). apply t_sub with (pc:=pc)(T:=an unit (joins PC b0)). apply t_unit. apply sub_refl. apply subt_unit. apply joins_subtyping_2. apply inversion_tloc in H0_. inversion H0_. inversion H0. inversion H5. inversion H6. inversion H7. inversion H9. inversion H15. inversion H19. inversion H21. subst. inversion H23. subst.
apply subsum_r_trans with (a:=b0)(b:=x2)(c:=b). apply H15. inversion H23. apply H24. apply sub_refl. apply subt_unit. apply joins_subtyping_1. apply H3. apply sub_refl. apply subt_unit. apply H1. split. inversion H2.
rewrite->H0. rewrite->length_replace. reflexivity. split. rewrite->length_replace.
apply heap_well_formed_replace. apply well_formed_b. apply H13. apply H11. apply H10. apply H12.
intros. remember (beq_nat l n) as CC. destruct CC.
apply beq_nat_eq in HeqCC. subst. apply lookup_replace_eq with (t:=(joinvs t2 (joins (labelT T0) (joins PC b0)),joinTs T0 (joins PC b0)))in H12. rewrite->H12. simpl. apply inversion_tloc in H0_. inversion H0_. inversion H5. inversion H6.
inversion H7. inversion H8. inversion H14. inversion H16. inversion H20. inversion H22. subst. inversion H9. subst. rewrite->H15. simpl. split.
apply value_b. apply H13.
split.
assert(subsum_r (joins PC b0)(labelT T0)). apply subsum_r_trans with (a:=joins PC b0)(b:=joins pc b0)(c:=labelT T0). apply joins_subtyping_1. apply H3. apply subsum_r_trans with (a:=joins pc b0)(b:=joins pc b)(c:=labelT T0).
apply joins_subtyping_2. apply subsum_r_trans with (a:=b0)(b:=x2)(c:=b). apply H8. inversion H24. apply H21. inversion H24. apply H1. apply joins_subsum in H19. assert (joins (labelT T0)(joins PC b0) = joins (joins PC b0)(labelT T0)). rewrite->joins_refl. reflexivity. destruct T0. rewrite->joinTs_b. simpl in H19. rewrite->joins_refl in H19. rewrite->H19. apply subtyping_refl.
split.
assert(subsum_r (joins PC b0)(labelT T0)). apply subsum_r_trans with (a:=joins PC b0)(b:=joins pc b0)(c:=labelT T0). apply joins_subtyping_1. apply H3. apply subsum_r_trans with (a:=joins pc b0)(b:=joins pc b)(c:=labelT T0).
apply joins_subtyping_2. apply subsum_r_trans with (a:=b0)(b:=x2)(c:=b). apply H8. inversion H24. apply H21. inversion H24. apply H1. apply joins_subsum in H19. destruct T0. rewrite->joinTs_b. simpl in H19. rewrite->joins_refl in H19. rewrite->H19. simpl. rewrite->H19.
inversion H13.
rewrite->join_tcon_b. assert (label (tcon n (joins b1 s)) = joins b1 s). reflexivity. rewrite->H25. rewrite->joins_refl. apply subsum_guard. rewrite->join_tabs_b. assert (label (tabs (Id n) T0 e (joins b1 s)) = joins b1 s). reflexivity. rewrite->H25.
rewrite->joins_refl. apply subsum_guard. rewrite->join_tunit_b. assert (label (tunit (joins b1 s)) = joins b1 s). reflexivity. rewrite->H25. rewrite->joins_refl. apply subsum_guard.
rewrite->join_tloc_b. assert (label (tloc T0 (Some n) (joins b1 s)) = joins b1 s). reflexivity. rewrite->H25. rewrite->joins_refl. apply subsum_guard.
apply value_pc with (pc:=pc). apply value_b. apply H13. apply t_sub with (pc:=pc)(T:=joinTs T0 (joins (labelT T0)(joins PC b0))).
apply has_type_joinvs_b. apply H13. inversion H24. apply H0_0. apply sub_refl. assert (subsum_r (joins PC b0)(labelT T0)). apply subsum_r_trans with (a:=joins PC b0)(b:=joins pc b)(c:=labelT T0). apply subsum_r_trans with (a:=joins PC b0)(b:=joins PC b)(c:=joins pc b). apply joins_subtyping_2. apply subsum_r_trans with (a:=b0)(b:=x2)(c:=b). apply H8. inversion H24. apply H21. apply joins_subtyping_1.
apply H3. inversion H24. subst. apply H1. apply joins_subsum in H19. rewrite->joins_refl in H19. rewrite->H19. rewrite->joinTs_same. apply subtyping_refl. subst.
symmetry in HeqCC. apply beq_nat_false in HeqCC. rewrite->length_replace in H0. apply lookup_replace_neq with (t:=(joinvs t2 (joins (labelT T0)(joins PC b0)),joinTs T0 (joins PC b0)))(st:=hp) in HeqCC. rewrite->HeqCC. split. inversion H2. inversion H6. specialize (H8 pc0 l). apply H8 in H0. apply H0.
split. inversion H2. inversion H6. specialize (H8 pc0 l). apply H8 in H0. apply H0. split. inversion H2. inversion H6. specialize (H8 pc0 l). apply H8 in H0. apply H0. inversion H2. inversion H6. specialize (H8 pc0 l). apply H8 in H0. apply H0.
subst.
apply IHhas_type1 in H14. inversion H14. exists x. split. apply H0. split. apply t_assign with (b:=b)(T:=T). reflexivity. apply H1. apply H0. apply change_HT with (HT:=HT). apply H0. apply H0_0. apply H0. reflexivity. apply H3. apply H2. subst.
apply IHhas_type2 in H15. inversion H15. exists x. split. apply H0. split. apply t_assign with (b:=b)(T:=T). reflexivity. apply H1. apply change_HT with (HT:=HT). apply H0. apply H0_. apply H0. apply H0. reflexivity. apply H3. apply H2.
Case ("t_sub").
intros. apply IHhas_type in H5. inversion H5. exists x. split. apply H6. split. apply t_sub with (pc:=pc)(T:=T). apply H6. apply H1. apply H2. apply H6. apply Heqcontext. apply subsum_r_trans with (a:=PC)(b:=pc')(c:=pc). apply H3. apply H1. apply H4.
Qed.
(*generalization of preservation*)
Theorem type_uniqueness:forall x z PC pc HT T,
has_type pc empty_context HT (fst x) T ->
heap_well_typed HT (snd x) ->
subsum_r PC pc ->
Multistep x PC z ->
(exists HT',
extends HT' HT /\
heap_well_typed HT' (snd z) /\
has_type pc empty_context HT'(fst z) T).
Proof. intros. generalize dependent pc. generalize dependent HT. induction H3.
Case ("multi_refl"). intros. exists HT. admit.
Case ("multi_step"). intros. apply preservation with (PC:=b)(t':=fst y)(hp:=snd x)(hp':=snd y)in H2.
inversion H2. inversion H5. inversion H7. apply IHMulti with (pc:=pc)in H9.
inversion H9. exists x1. split. apply extends_trans with (HT':=x0). apply H6.
apply H10. apply H10. apply H8. apply H4. apply H1. destruct x. destruct y. apply H0.
apply H4.
Qed.
(*progress*)
(*one auxiliary lemma*)
Lemma well_typed_well_formed:forall pc HT hp t T,
has_type pc empty_context HT t T ->
heap_well_typed HT hp ->
well_formed t (length hp).
Proof. intros. generalize dependent hp. induction H0.
Case ("t_var"). intros. apply wf_tvar.
Case ("t_con"). intros. apply wf_tcon.
Case ("t_unit"). intros. apply wf_tunit.
Case ("t_loc"). intros. apply wf_tloc. inversion H1. rewrite<-H2. apply change_HT' with (T:=T).
apply H0.
Case ("t_abs"). intros. apply wf_tabs. apply IHhas_type. apply H1.
Case ("t_prot"). intros. apply wf_tprot. apply IHhas_type. apply H2.
Case ("t_app"). intros. apply wf_tapp. apply IHhas_type1. apply H1. apply IHhas_type2.
apply H1.
Case ("t_ref"). intros. apply wf_tref. apply IHhas_type. apply H3.
Case ("t_deref"). intros. apply wf_tderef. apply IHhas_type. apply H2.
Case ("t_assign"). intros. apply wf_tassign. apply IHhas_type1. apply H2.
apply IHhas_type2. apply H2.
Case ("t_sub"). intros. apply IHhas_type. apply H3.
Qed.
Theorem progress: forall t T pc PC HT hp,
has_type pc empty_context HT t T ->
heap_well_typed HT hp ->
subsum_r PC pc ->
value t \/ (exists p, step (t,hp) PC p).
Proof. intros. remember (@empty_context) as context. generalize dependent hp.
generalize dependent PC. induction H0.
Case ("t_var").
intros. subst. inversion H0.
Case ("t_con").
intros. subst. left. apply v_c.
Case ("t_unit").
intros. subst. left. apply v_u.
Case ("t_loc").
intros. subst. left. apply v_l.
Case ("t_abs").
intros. subst. left. destruct x. apply v_f.
Case ("t_prot").
intros. subst. right. assert (heap_well_typed HT hp). apply H3. apply IHhas_type with (PC:=joins PC b)in H1.
inversion H1. exists (joinvs t b,hp). apply st_protv. inversion H3. apply H6.
apply well_typed_well_formed with (hp:=hp)in H0. apply H0. apply H3.
apply H4. inversion H4. destruct x. exists (tprot b t0,h).
apply st_prot. inversion H3. apply H7.
apply well_typed_well_formed with (hp:=hp) in H0. apply H0. apply H3.
apply H5. reflexivity. apply joins_subtyping_1. apply H2.
Case ("t_app").
intros. subst. right. assert (heap_well_typed HT hp). apply H1.
assert (heap_well_typed HT hp). apply H1.
apply IHhas_type1 with (PC:=PC) in H1.
apply IHhas_type2 with (PC:=PC) in H0. inversion H1. inversion H0. inversion H4. subst. apply inversion_tcon in H0_.
inversion H0_. inversion H6. inversion H7. inversion H8. inversion H10. inversion H12. subst. inversion H14.
subst. exists (tprot b0 ([(Id n ) := t2]e),hp). apply st_appabs. inversion H3. apply H7.
apply well_typed_well_formed with (hp:=hp)in H0_0. apply H0_0. apply H3. apply well_typed_well_formed with (hp:=hp)in H0_.
inversion H0_. apply H11. apply H3.
apply H5. subst. apply inversion_tunit in H0_.
inversion H0_. inversion H6. inversion H7. inversion H8. inversion H10. inversion H12. subst. inversion H14.
subst. apply inversion_tloc in H0_. inversion H0_. inversion H6. inversion H7. inversion H8. inversion H9. inversion H11. inversion H13.
inversion H15. inversion H17. subst. inversion H19. inversion H5. destruct x. exists (tapp t1 t,h). apply st_app2. inversion H3. apply H8.
apply well_typed_well_formed with (hp:=hp) in H0_.
apply H0_. apply H3. apply well_typed_well_formed with (hp:=hp) in H0_0. apply H0_0. apply H3.
apply H4. apply H6.
inversion H4. destruct x. exists (tapp t t2,h). apply st_app1. inversion H3. apply H7.
apply well_typed_well_formed with (hp:=hp) in H0_.
apply H0_. apply H3.
apply well_typed_well_formed with (hp:=hp) in H0_0. apply H0_0. apply H3.
apply H5. reflexivity. apply H2. reflexivity. apply H2.
Case ("t_ref").
intros. subst. right. assert (heap_well_typed HT hp). apply H4. apply IHhas_type with (PC:=PC)in H1. inversion H1.
exists (tloc T (Some (length hp)) b,snoc hp (joinvs t (joins (labelT T)(joins b PC)),T)). apply st_refv with (v':=joinvs t (joins (labelT T)(joins b PC)))(b':=labelT T)(b'':=joins b PC)(b''':= joins (labelT T)(joins b PC)).
inversion H4. apply H7.
apply well_typed_well_formed with (hp:=hp) in H0. apply H0. apply H4.
apply H5. reflexivity. reflexivity. reflexivity. reflexivity. reflexivity. destruct b. inversion H5. destruct x. exists (tref T t0 L,h).
apply st_ref. inversion H4. apply H8.
apply well_typed_well_formed with (hp:=hp) in H0. apply H0. apply H4.
rewrite->joins_refl. simpl. apply H6. assert (empty_context=empty_context). reflexivity. apply IHhas_type with (PC:=H)(hp:=hp) in H6. inversion H6.
exists (tloc T (Some (length hp)) H,snoc hp (joinvs t H,T)). apply st_refv with (v':=joinvs t H)(b':=labelT T)(b'':=H)(b''':=H).
inversion H4. apply H9.
apply well_typed_well_formed with (hp:=hp) in H0. apply H0. apply H4.
apply H7. reflexivity. reflexivity. rewrite->joins_refl. reflexivity. reflexivity. reflexivity.
inversion H7. destruct x. exists (tref T t0 H,h). apply st_ref.
inversion H4. apply H10.
apply well_typed_well_formed with (hp:=hp) in H0. apply H0. apply H4.
rewrite->joins_refl. simpl. apply H8. rewrite->joins_refl. simpl. apply sub_refl. apply H4. reflexivity. apply subsum_r_trans with (a:=PC)(b:=pc)(c:=joins pc b).
apply H3. apply subsum_guard.
Case ("t_deref").
intros. subst. right. assert (heap_well_typed HT hp). apply H3. apply IHhas_type with (PC:=PC)in H1. inversion H1.
inversion H4. subst. apply inversion_tcon in H0. inversion H0. inversion H5. inversion H6.
inversion H7. inversion H9. inversion H11. subst. inversion H13. subst. apply inversion_tabs in H0. inversion H0. inversion H5. inversion H6. inversion H7.
inversion H8. inversion H9. inversion H10. inversion H11. inversion H13. inversion H15. inversion H17. inversion H19. inversion H21. inversion H23. inversion H25.
subst. apply inversion_tunit in H0. inversion H0. inversion H5. inversion H6. inversion H7. inversion H9. inversion H11. subst. inversion H13. subst. apply inversion_tloc in H0.
inversion H0. inversion H5. inversion H6. inversion H7. inversion H8. inversion H9. inversion H10. apply change_HT' in H11. exists (tprot b0 (efst (heap_lookup x hp)),hp). apply st_derefloc. inversion H3.
apply H15. inversion H3. rewrite->H14 in H11. apply H11. reflexivity.
inversion H4. destruct x. exists (tderef t0,h). apply st_deref. inversion H3. apply H7.
apply well_typed_well_formed with (hp:=hp) in H0. apply H0. apply H3.
apply H5. reflexivity. apply H2.
Case ("t_assign").
intros. subst. right. assert (heap_well_typed HT hp). apply H3. assert (heap_well_typed HT hp). apply H3.
apply IHhas_type1 with (PC:=PC)in H0. apply IHhas_type2 with (PC:=PC)in H4. inversion H0. inversion H4. inversion H5. subst. apply inversion_tcon in H0_. inversion H0_. inversion H7. inversion H8.
inversion H9. inversion H11. inversion H13. subst. inversion H15. subst. apply inversion_tabs in H0_. inversion H0_. inversion H7. inversion H8. inversion H9. inversion H10.
inversion H11. inversion H12. inversion H13. inversion H15. inversion H17. inversion H19. inversion H21. inversion H23. inversion H25. inversion H27. subst. apply inversion_tunit in H0_. inversion H0_.
inversion H7. inversion H8. inversion H9. inversion H11. inversion H13. subst. inversion H15. subst. apply inversion_tloc in H0_. inversion H0_. inversion H7. inversion H8. inversion H9. inversion H10. inversion H11. subst. inversion H12. apply change_HT' in H13.
exists (tunit (joins PC b0),heap_replace x (joinvs t2 (joins (labelT T0)(joins PC b0)),joinTs T0 (joins PC b0)) hp). apply st_assign with (v':=joinvs t2 (joins(labelT T0)(joins PC b0)))(T':=joinTs T0 (joins PC b0))(b':=labelT T0)(b''':=joins (labelT T0)(joins PC b0))(l:=label t2). inversion H3.
apply H16.
apply well_typed_well_formed with (hp:=hp) in H0_0. apply H0_0. apply H3. inversion H3.
rewrite<-H15. apply H13. apply H6.
reflexivity. reflexivity. reflexivity. inversion H3.
assert (value t2). apply H6. apply labelT_subsum_labelt with (pc:=pc)(HT:=HT)(T:=T) in H17. inversion H14. inversion H19. inversion H21. subst. inversion H23. subst. apply joins_subsum in H17. rewrite->H17. inversion H16. specialize (H24 pc x). rewrite->H15 in H13. apply H24 in H13. inversion H10. inversion H26. rewrite->H27 in H13. simpl in H13. inversion H13. inversion H30. inversion H32.
apply subtyping_subsum in H31. inversion H32. assert (subsum_r (labelT T)(label (efst (heap_lookup x hp)))). apply subsum_r_trans with (a:=labelT T)(b:=labelT (esnd (heap_lookup x hp)))(c:=label (efst (heap_lookup x hp))). apply H31. apply H33. inversion H32. assert (subsum_r (label (efst (heap_lookup x hp)))(labelT T)). apply labelT_subsum_labelt with (pc:=pc)(HT:=HT).
apply H29. apply H36. apply subsum_equal. apply H37. apply H40. apply H0_0.
inversion H3. inversion H12. inversion H16. specialize (H20 L x). rewrite->H17 in H20. rewrite->H15 in H13. apply H20 in H13. inversion H13. simpl in H22. inversion H18. inversion H24. inversion H26. subst. inversion H28. subst.
apply subsum_r_trans with (a:=joins PC b0)(b:=labelT T)(c:=label (efst (heap_lookup x hp))). assert (subsum_r (joins PC b0)(labelT T)). apply subsum_r_trans with (a:=joins PC b0)(b:=joins pc b0)(c:=labelT T). apply joins_subtyping_1. apply H2. apply subsum_r_trans with (a:=joins pc b0)(b:=joins pc b)(c:=labelT T). apply joins_subtyping_2.
apply subsum_r_trans with (a:=b0)(b:=x2)(c:=b). apply H18. inversion H28. apply H29. apply H1. apply H23.
apply subsum_r_trans with (a:=labelT T)(b:=labelT (esnd (heap_lookup x hp)))(c:=label (efst (heap_lookup x hp))). inversion H22. inversion H29. apply subtyping_subsum in H23. apply H23. apply H13. reflexivity. reflexivity. reflexivity. reflexivity.
(**
inversion H30. rewrite->H32. apply labelT_subsum_labelt with (pc:=pc)(HT:=HT)(T:=T) in H27. rewrite<-H32 in H27. rewrite<-H32. apply subsum_low in H27. symmetry. apply H27. apply H34. apply H0_0.
inversion H3. inversion H12. specialize (H16 L x). rewrite->H17 in H16. rewrite->H15 in H13. apply H16 in H13. inversion H13. simpl in H19. inversion H18. inversion H22. inversion H24. subst. inversion H26. subst.
apply subsum_r_trans with (a:=joins PC b0)(b:=labelT T)(c:=label (efst (heap_lookup x hp))). assert (subsum_r (joins PC b0)(labelT T)). apply subsum_r_trans with (a:=joins PC b0)(b:=joins pc b0)(c:=labelT T). apply joins_subtyping_1. apply H2. apply subsum_r_trans with (a:=joins pc b0)(b:=joins pc b)(c:=labelT T). apply joins_subtyping_2.
apply subsum_r_trans with (a:=b0)(b:=x2)(c:=b). apply H14. inversion H20. apply H23. apply H1. apply H21.
apply subsum_r_trans with (a:=labelT T)(b:=labelT (esnd (heap_lookup x hp)))(c:=label (efst (heap_lookup x hp))). inversion H20. simpl in H21. apply subtyping_subsum in H21. apply H21. apply H13. reflexivity. reflexivity. reflexivity. reflexivity.
*)
inversion H6. destruct x. exists (tassign t1 t,h). apply st_assign2.
inversion H3. apply H9.
apply well_typed_well_formed with (hp:=hp) in H0_. apply H0_. apply H3. apply well_typed_well_formed with (hp:=hp) in H0_0. apply H0_0. apply H3.
apply H5. apply H7. inversion H5. destruct x.
exists (tassign t t2,h). apply st_assign1.
inversion H3. apply H8.
apply well_typed_well_formed with (hp:=hp) in H0_. apply H0_. apply H3. apply well_typed_well_formed with (hp:=hp) in H0_0. apply H0_0. apply H3.
apply H6. reflexivity. apply H2. reflexivity. apply H2.
Case ("t_sub").
intros. assert (subsum_r PC pc). apply subsum_r_trans with (a:=PC)(b:=pc')(c:=pc). apply H3. apply H1.
apply IHhas_type with (PC:=PC)in H4. apply H4. apply Heqcontext. apply H5.
Qed.
(*##########determinism#########*)
Theorem determinism: forall t t' t'' hp hp' hp'' PC,
t / hp ==PC=> t' / hp' ->
t / hp ==PC=> t'' / hp'' ->
(t' = t''/\hp' = hp'').
Proof. intros t. induction t.
Case ("tvar").
intros. inversion H0.
Case ("tprot").
intros. inversion H0. subst. inversion H1. subst.
apply IHt with (t':=t'0)(t'':=t')(hp'':=hp'')in H10. inversion H10. subst.
split. reflexivity. reflexivity. apply H13. subst. inversion H13. subst. inversion H10.
subst. inversion H10. subst. inversion H10. subst. inversion H10. subst. inversion H1. subst.
inversion H10. subst. inversion H13. subst. inversion H13. subst. inversion H13. subst. inversion H13.
subst. split. reflexivity. reflexivity.
Case ("tcon").
intros. inversion H0.
Case ("tabs").
intros. inversion H0.
Case ("tapp").
intros. inversion H0. inversion H1. subst. inversion H12. subst. split.
reflexivity. reflexivity. subst. inversion H21. subst. inversion H11. subst. inversion H22.
subst. inversion H22. subst. inversion H22. subst. inversion H22. subst. inversion H1. subst.
inversion H11. subst.
apply IHt1 with (t':=t1')(t'':=t1'0)(hp'':=hp'') in H11. inversion H11. subst. split. reflexivity.
reflexivity. apply H15. subst. inversion H15. subst. inversion H11. subst. inversion H11. subst. inversion H11.
subst. inversion H11. subst. inversion H1. subst. inversion H16. subst. inversion H12. subst. inversion H12.
subst. inversion H12. subst. inversion H12. subst. inversion H11. subst. inversion H16. subst. inversion H16.
subst. inversion H16. subst. inversion H16. subst.
apply IHt2 with (t':=t2')(t'':=t2'0)(hp'':=hp'')in H12. inversion H12. subst. split. reflexivity. reflexivity.
apply H17.
Case ("tunit").
intros. inversion H0.
Case ("tref").
intros. inversion H0. subst. inversion H1. subst. split. reflexivity. reflexivity. subst. inversion H10. subst.
inversion H14. subst. inversion H14. subst. inversion H14. subst. inversion H14. subst. inversion H1. subst. inversion H13. subst.
inversion H11. subst. inversion H11. subst. inversion H11. subst. inversion H11. subst. specialize (IHt t'0 t' hp hp' hp''). apply IHt in H14.
inversion H14. subst. split. reflexivity. reflexivity. apply H11.
Case ("tderef").
intros. inversion H0. inversion H1. subst. inversion H10. subst. split. reflexivity. reflexivity. subst. inversion H17. subst. inversion H1. subst.
inversion H9. subst. apply IHt with (t':=t'0)(t'':=t')(hp'':=hp'') in H9. inversion H9. subst. split. reflexivity. reflexivity. apply H12.
Case ("tloc").
intros. inversion H0.
Case ("tassign").
intros. inversion H0. subst. inversion H1. subst. split. reflexivity. reflexivity. subst. inversion H17. subst. inversion H10. subst. inversion H18. subst. inversion H18.
subst. inversion H18. subst. inversion H18. subst. inversion H1. subst. inversion H11. subst.
specialize (IHt1 t1' t1'0 hp hp' hp'' PC). apply IHt1 in H11. inversion H11. subst.
split. reflexivity. reflexivity. apply H15. subst. inversion H15. subst. inversion H11. subst. inversion H11. subst. inversion H11. subst. inversion H11. subst. inversion H1. subst.
inversion H15. subst. inversion H12. subst. inversion H12. subst. inversion H12. subst. inversion H12. subst. inversion H11. subst. inversion H16. subst. inversion H16. subst. inversion H16.
subst. inversion H14. subst. inversion H16. subst. specialize (IHt2 t2' t2'0 hp hp' hp'' PC). apply IHt2 in H12. inversion H12. subst. split. reflexivity. reflexivity. apply H17.
Qed.
(*############soundness############*)
Corollary soundness : forall pc PC HT p p' T,
has_type pc empty_context HT (fst p) T ->
heap_well_typed HT (snd p) ->
Multistep p PC p' ->
subsum_r PC pc ->
~((~exists p'', step p' PC p'')/\(~ value (fst p'))).
Proof.
intros. remember (@empty_context) as context. generalize dependent pc. generalize dependent HT.
generalize dependent T. induction H2.
Case ("multi_refl").
intros. subst. intros contra. inversion contra.
apply progress with (PC:=b)(hp:=snd x) in H0. inversion H0.
SCase ("left"). apply H4 in H5. inversion H5.
SCase ("right"). destruct x. apply H2 in H5. inversion H5. apply H1. apply H3.
Case ("multi_step"). subst. intros. apply preservation with (PC:=b)(t':=fst y)(hp:=snd x)(hp':=snd y)in H3.
inversion H3. inversion H5. inversion H7. apply IHMulti with (T:=T)(pc:=pc) in H9. apply H9. apply H8.
apply H4. apply H1. destruct x. destruct y. apply H0. apply H4.
Qed.
End SecLang.
Module LowLang.
(*syntax*)
Inductive tm : Type :=
| tvar : id -> tm
(*| tprot : Sec -> tm -> tm*)
| tcon : nat -> tm
| tabs : id -> Ty -> tm -> tm
| tapp : tm -> tm -> tm
(*#####new terms######*)
| tunit : tm
| tref : Ty -> tm -> tm (*[Ty] as the initial type*)
| tderef : tm -> tm
| tloc : Ty -> option nat -> tm(*[Ty] as the "access type"*)
| tassign : tm -> tm -> tm
(*####one additional terms meant to be typed with high security####*)
| tH : tm.
(**
Note that there is no [tprot] in [LowLang]. For the projection of a
term protected by [H] is always [tH] while the projection of terms
protected by [L] is just that of themselves
*)
(**
Also note that the referred location in [tloc] is typed as [option nat] where
we use [None] indicating a pointer to a high value on the heap in [SecLang] while
[Some n] indicating a pointer to a low value on the projected heap given that [n]
is smaller than the length of the projected heap
*)
(*well-formed term in [LowLang]*)
(*well formed expressions*)
(**
Here,a term is well-formed given a natural number which stands for
the length of the heap in [SecLang]
*)
Inductive well_formed : tm -> nat -> Prop :=
| wf_tvar:forall (x:id)(hp:nat),
well_formed (tvar x) hp
| wf_tcon:forall (n:nat)(hp:nat),
well_formed (tcon n) hp
| wf_tunit:forall (hp:nat),
well_formed tunit hp
| wf_tloc:forall (T:Ty)(n:nat)(hp:nat),
n < hp ->
well_formed (tloc T (Some n)) hp
| wf_tabs:forall x T e hp,
well_formed e hp ->
well_formed (tabs x T e) hp
| wf_tapp:forall t1 t2 hp,
well_formed t1 hp ->
well_formed t2 hp ->
well_formed (tapp t1 t2) hp
| wf_tref:forall (T:Ty) (e:tm) (hp:nat),
well_formed e hp ->
well_formed (tref T e) hp
| wf_tderef:forall e hp,
well_formed e hp ->
well_formed (tderef e) hp
| wf_tassign:forall t1 t2 hp,
well_formed t1 hp ->
well_formed t2 hp ->
well_formed (tassign t1 t2) hp
| wf_tH:forall hp,
well_formed tH hp.
(*value*)
Inductive value : tm -> Prop :=
| v_c : forall n,
value (tcon n)
| v_f : forall n T e,
value (tabs (Id n) T e)
| v_u : value tunit
| v_l : forall N T,
value (tloc T N)
| v_H : value tH
.
(*heap*)
Definition heap := list (tm*Ty).
Definition emp_hp:= @nil (tm*Ty).
(*some useful functions*)
(*###lookup function and some lemmas###*)
Fixpoint heap_lookup (n:nat)(st:heap):(option (tm*Ty)):=
match st , n with
| nil , _ =>None
| h::t , 0 => Some h
| h::t , S n' =>heap_lookup n' t
end.
(*extract the result of [heap_lookup]*)
Definition efst (p:option(tm*Ty)) : tm :=
match p with
| None => tvar (Id 100)
| Some (t , T) => t
end.
Definition esnd (p:option(tm*Ty)) : Ty :=
match p with
| None => an unit L
| Some (t, T) => T
end.
Fixpoint snoc {A:Type} (l:list A) (x:A) : list A :=
match l with
| nil => x :: nil
| h :: t => h :: snoc t x
end.
Lemma length_snoc:forall A (l:list A) x,
length (snoc l x) = S (length l).
Proof.
intros. generalize dependent x. induction l.
Case ("nil"). intros. simpl. reflexivity.
Case ("h::t"). intros. simpl. specialize (IHl x). rewrite->IHl.
reflexivity.
Qed.
Lemma lt_snoc_1 : forall n m,
S n <= S m -> n <= m.
Proof.
intros n m. generalize dependent n. induction m as [|m'].
Case ("m=0"). intros. destruct n as [|n'].
SCase ("n=0"). apply le_n.
SCase ("n=S n'"). inversion H0. inversion H2.
Case ("m=S m'"). intros. inversion H0. apply le_n. apply le_S.
apply IHm'. apply H2.
Qed.
Lemma lt_snoc: forall (l:heap) x (n:nat),
n < length l ->
heap_lookup n l = heap_lookup n (snoc l x).
Proof.
intros l. induction l.
Case ("nil"). intros. simpl in H0. inversion H0.
Case ("h::t"). intros. simpl. destruct n. reflexivity. simpl.
apply IHl. simpl in H0. apply lt_snoc_1 in H0.
apply H0.
Qed.
Lemma eq_snoc: forall (l:heap) x,
heap_lookup (length l) (snoc l x) = Some x.
Proof.
intros l. induction l.
Case ("nil"). intros. simpl. reflexivity.
Case ("h::t"). intros. simpl. specialize (IHl x).
apply IHl.
Qed.
(*###replace function and some lemmas###*)
Fixpoint heap_replace n x (l:heap): heap :=
match l , n with
| nil , _ =>nil
| h::t , 0 => x::t
| h::t , S n' =>h :: (heap_replace n' x t)
end.
Lemma replace_nil: forall n x,
heap_replace n x nil = nil.
Proof.
intros. destruct n. simpl. reflexivity. simpl. reflexivity. Qed.
Lemma length_replace: forall n x (l:heap),
length (heap_replace n x l) = length l.
Proof.
intros. generalize dependent n. generalize dependent x. induction l.
Case ("nil"). intros. simpl. rewrite->replace_nil. simpl. reflexivity.
Case ("h::t"). intros. simpl. destruct n. simpl. reflexivity.
simpl. specialize (IHl x n). rewrite->IHl. reflexivity.
Qed.
Lemma lookup_replace_eq: forall l t st,
l < length st ->
heap_lookup l (heap_replace l t st) = Some t.
Proof.
intros. generalize dependent l. generalize dependent t.
induction st.
Case ("nil"). intros. destruct l. simpl in H0. inversion H0. simpl in H0. inversion H0.
Case ("h::t"). intros. destruct l. simpl. reflexivity.
simpl. apply IHst. simpl in H0. unfold lt. unfold lt in H0.
apply lt_snoc_1 in H0. apply H0.
Qed.
Lemma lookup_replace_neq: forall l1 l2 t st,
l1 <> l2 ->
heap_lookup l1 (heap_replace l2 t st) = heap_lookup l1 st.
Proof.
intros. generalize dependent l1. generalize dependent l2. generalize dependent t.
induction st.
Case ("nil"). intros. rewrite->replace_nil. reflexivity.
Case ("h::t"). intros. destruct l2. destruct l1. simpl. assert (0=0). reflexivity.
apply H0 in H1. inversion H1. simpl. reflexivity. simpl.
destruct l1. reflexivity. apply IHst.
intros T. assert (l1 = l2 -> S l1 = S l2). intros. subst. reflexivity.
apply H1 in T. apply H0 in T. inversion T.
Qed.
(*substitution*)
Fixpoint subst (x:id) (s:tm) (t:tm): tm :=
match t with
(*variables*)
| tvar x' =>
if beq_id x x' then s else t
(*abstractions*)
| tabs x' T t1 =>
tabs x' T (if beq_id x x' then t1 else (subst x s t1))
(*constants*)
| tcon n => tcon n
(*applications*)
| tapp t1 t2 =>
tapp (subst x s t1) (subst x s t2)
(*units*)
| tunit => tunit
(*tref*)
| tref T t1 => tref T (subst x s t1)
(*tderef*)
| tderef t1 => tderef (subst x s t1)
(*tloc*)
| tloc T N => tloc T N
(*assignments*)
| tassign t1 t2 => tassign (subst x s t1)(subst x s t2)
(*high value*)
| tH => tH
end.
Notation "'[' x ':=' s ']' t" := (subst x s t) (at level 20).
Definition labelT (T:Ty) : Sec:=
match T with
| an rt b => b
end.
Reserved Notation "t1 '/' hp '==' PC '=>' t2 '/' hp'"
(at level 40, hp at level 39, t2 at level 39, PC at level 39).
(**
Note currently all terms are without any security labels and as will be
specified below in the type relation all terms except [tH] can be typed
as low and high while [tH] can only be typed as low.
*)
(**
Regarding the reduction relation,
a. application
In [LowLang], we preserve both [st_app1] [st_app2] and [st_appabs] to deal with
cases where either of the subterms of the application are reducible or the first
term of the application which is a low abstraction is applied to a value. In addition,
we have [st_apptH] to deal with cases where a high abstraction is being applied to
a value. In such cases,since the result is always being protected by [H] we should
have it as follows,
[st_apptH]:forall v PC hp,
value v ->
tapp tH v / hp ==PC=> tH / hp
b. reference
in [LowLang], we preserve both [st_ref] and [st_refv] to deal with cases where either the
subterm is reducible or the subterm is a low value and both the label of the referred
tpye and PC have to be low for the new cell being written onto the heap is being
protected by both [labelT T] and [PC] and after reduction the heap is extended by
the pair of the guarded low value and the referred type. In addtion we also have
to deal with cases where a high value actually gets written onto the heap either
because the value itself is [tH] or the join of [PC] and [labelT T] is [H]. In such
cases, the heaps before and after the reduction are the same while we replace the
referred location to [None] to signal the fact that in [LowLang],all
high values in a heap are referred to via [None] which is the default value of the referred
location.
[st_reftH]:forall v PC T hp,
value v ->
v = tH \/ PC = H \/ LabelT T = H ->
tref T v / hp ==PC=> tloc T None / hp
Note that we only consider three cases of assignment in [LowLang],
1. a high cell is being over-written by a high value
2. a low cell is being over-written by a low value
It should be noted that we do not deal with cases where a high cell is being over-written
by a low value and a low cell is being over-written by a high value. Such cases are ruled out by explicitly prohibiting any upgrading
and downgrading in [SecLang]
c. dereference
as illustrated in [b.],the ways how we write a low value and a high value are
different in that the low cell being written onto the heap is always referred
to via a location which is within range while all high values are actually not
being written onto the heap for in [LowLang] we want to abstract away all high
level side-effect. Instead, we rewrite the referred location as [None] so as to
signal cases where high value is being written onto the heap.
Hence we should have the following reduction rules besides [st_deref] where the
subterm is reducible,
[st_derefloc]:forall n hp T hp PC,
n < length hp ->
v = efst (heap_lookup n hp) ->
tderef (tloc T (Some n)) / hp ==PC=> v / hp
[st_derefloctH]:
tderef (tloc T None) / hp ==PC=> tH / hp
the case where the subterm is [tH] is simple for it must
correspond to the dereference of a high location in [SecLang] where the
result of the reduction is protected by [H] the projection of which is [tH],
[st_dereftH]:
tderef tH / hp ==PC=> tH / hp
d. assignment
the reduction rule in cases where each of its subterms is reducible is not different
from [st_assign1] and [st_assign2] in [SecLang]. Now in regard with cases where
a cell on the heap is being over-written by some value it is not necessary for us
to deal with cases where either a high cell is being over-written by a low value or
a low cell is being over-written by a high value. They are ruled out by prohibiting any
upgrading and downgrading in [SecLang].
Now in [LowLang],we only need to consider two cases of assignment,
a. a low cell is being over-written by a low value
[st_assign]:forall n hp v T PC
n < length hp ->
value v ->
v <> tH ->
PC = labelT T = L ->
hp'=heap_replace n (v,T) hp ->
tassign ((tloc T )(Some n)) v / hp ==PC=>tunit / hp'
b. a high cell is being over-written by a high value
when security context is low
[st_assigntH_L]:forall hp v T PC hp,
value v ->
v = tH \/ labelT T = H ->
PC = L ->
tassign (tloc T None) v / hp ==PC=> tunit / hp
c. a high cell is being over-written by a high value
when security context is high
[st_assigntH_H]:forall n hp v PC T hp,
n = length hp ->
value v ->
PC = H ->
tassign (tloc T None) v / hp ==PC=> tH / hp
the case where the pointer through which heap cell is updated is high would
mean either over-writing a low cell with a high value or a high cell with a
high value where the former case bring us difficulty for the projection of
a high pointer according to our projection function destroys all info. regarding
the location of the relevent low cell which we would like to get rid of through
projection. Yet,we need not consider this case for condition that the cell being
over-written must be guarded by the joint of [PC] and the label of the pointer for
the reduction to proceed. Then we have,
[st_assignHP]:forall
value v ->
tassign tH v / hp ==PC=> tH / hp
*)
Inductive step : tm * heap -> Sec -> tm * heap -> Prop :=
| st_appabs: forall x T e PC hp v,
value v ->
tapp (tabs x T e) v / hp == PC => [x := v]e / hp
| st_app1: forall t1 t1' t2 PC hp hp',
t1 / hp == PC => t1' / hp' ->
tapp t1 t2 / hp == PC => tapp t1' t2 / hp'
| st_app2: forall v1 t2 t2' PC hp hp',
value v1 ->
t2 / hp == PC => t2' / hp' ->
tapp v1 t2 / hp == PC => tapp v1 t2' / hp'
(*application were a high abstraction is being applied*)
| st_apptH:forall v hp PC,
value v ->
tapp tH v / hp ==PC=> tH / hp
(*writing a new low cell*)
| st_refv: forall T v PC hp hp',
value v ->
v <> tH ->
labelT T = L ->
PC = L ->
hp' = snoc hp (v,T) ->
tref T v / hp == PC => tloc T (Some (length hp)) / hp'
(*writing a new high cell*)
| st_reftH:forall v PC T hp,
value v ->
v = tH \/ PC = H \/ labelT T = H ->
tref T v / hp ==PC=> tloc T None / hp
| st_ref: forall T t t' PC hp hp',
t / hp == PC => t' / hp' ->
tref T t / hp == PC => tref T t' / hp'
(*dereferencing a low cell on the heap*)
| st_derefloc: forall T n PC hp v,
n < length hp ->
v = efst (heap_lookup n hp) ->
tderef (tloc T (Some n)) / hp == PC => v / hp
(*dereferencing a high cell on the heap*)
| st_derefloctH:forall hp T PC,
tderef (tloc T None) / hp == PC => tH / hp
| st_deref: forall t t' hp hp' PC,
t / hp == PC => t' / hp' ->
tderef t / hp == PC => tderef t' / hp'
(*dereferencing a high loction*)
| st_dereftH:forall hp PC,
tderef tH / hp ==PC=> tH / hp
(*low cell is being over-written by a low value*)
| st_assign: forall v T n PC hp hp',
n < length hp -> (* heap_lookup n hp = some e'*)
value v ->
v <> tH ->
PC = L /\ labelT T = L ->
hp' = heap_replace n (v,T) hp ->
tassign (tloc T (Some n)) v / hp == PC => tunit / hp'
(*high cell is being over-written by a high value when [PC] is L*)
| st_assigntH_L:forall hp v PC T,
value v ->
PC = L ->
v = tH \/ labelT T = H ->
tassign (tloc T None) v / hp ==PC=> tunit / hp
(*high cell is being over-written by a high value when [PC] is H*)
| st_assigntH_H:forall hp v PC T,
value v ->
PC = H ->
tassign (tloc T None) v / hp ==PC=> tH / hp
(*a high pointer*)
| st_assignHP:forall v hp PC,
value v ->
tassign tH v / hp ==PC=> tH / hp
| st_assign1: forall t1 t1' t2 PC hp hp',
t1 / hp == PC => t1' / hp' ->
tassign t1 t2 / hp == PC => tassign t1' t2 / hp'
| st_assign2: forall v1 t2 t2' PC hp hp',
value v1 ->
t2 / hp == PC => t2' / hp' ->
tassign v1 t2 / hp == PC => tassign v1 t2' / hp'
where "t1 '/' hp '==' PC '=>' t2 '/' hp'" := (step (t1,hp) PC (t2,hp')).
(*###multi-step reduction###*)
Definition Relation (X: Type) := X->Sec->X->Prop.
Inductive Multi {X:Type} (R: Relation X) : Relation X :=
| Multi_refl : forall (x : X)(b : Sec), Multi R x b x
| Multi_step : forall (x y z : X)(b : Sec),
R x b y ->
Multi R y b z ->
Multi R x b z.
Definition Multistep := (Multi step).
Notation "t1 '/' hp '==' PC '=>*' t2 '/' hp'" := (Multistep (t1,hp) PC (t2,hp'))
(at level 40, hp at level 39, t2 at level 39, PC at level 39).
Theorem multi_trans:forall t t' t'' hp hp' hp'' pc,
Multistep (t,hp) pc (t',hp') ->
Multistep (t',hp') pc (t'',hp'') ->
Multistep (t,hp) pc (t'',hp'').
Proof.
intros. induction H0. apply H1. apply IHMulti in H1.
apply Multi_step with y. apply H0. apply H1.
Qed.
(*some reduction samples*)
Example test_step_1:forall hp PC,
tapp tH (tcon 0) / hp ==PC=> tH / hp.
Proof. intros. apply st_apptH. apply v_c. Qed.
Example test_step_2:forall PC hp,
tref (an int L) tH / hp ==PC=>tloc (an int L) None / hp.
Proof. intros. apply st_reftH. apply v_H. left. reflexivity. Qed.
Example test_step_3:forall hp,
tref (an int L)(tcon 0) / hp ==L=> tloc (an int L) (Some (length hp)) / snoc hp (tcon 0,an int L).
Proof. intros. apply st_refv. apply v_c. intros contra. inversion contra. reflexivity. reflexivity.
reflexivity. Qed.
Example test_step_4:forall PC,
tderef (tloc (an int H) (Some 0)) / ((tcon 0,an int H) :: nil)
==PC=>
tcon 0 / ((tcon 0,an int H) :: nil).
Proof. intros. apply st_derefloc. apply le_n. reflexivity. Qed.
Example test_step_5:forall hp PC,
tderef (tloc (an int H) None) / hp
==PC=>
tH / hp.
Proof. intros. apply st_derefloctH. Qed.
Example test_step_6:forall hp PC,
tderef tH / hp ==PC=> tH / hp.
Proof. apply st_dereftH. Qed.
Example test_step_7:
tassign (tloc (an int L) (Some 0))(tcon 1) / ((tcon 0,an int L) :: nil)
==L=>
tunit / ((tcon 1,an int L) :: nil).
Proof. apply st_assign. apply le_n. apply v_c. intros contra. inversion contra.
split. reflexivity. reflexivity. reflexivity. Qed.
Example test_step_8:forall hp,
tassign (tloc (an int L) None) tH / hp
==L=>
tunit / hp.
Proof. intros. apply st_assigntH_L. apply v_H. reflexivity. left.
reflexivity. Qed.
Example test_step_9:forall hp,
tassign (tloc (an int H) None) (tcon 1) / hp
==L=>
tunit / hp.
Proof. intros. apply st_assigntH_L. apply v_c. reflexivity. right.
reflexivity. Qed.
Example test_step_10:forall hp,
tassign (tloc (an int L) None)(tcon 1) / hp
==H=>
tH / hp.
Proof. intros. apply st_assigntH_H. apply v_c. reflexivity. Qed.
Example test_step_11:forall hp PC,
tassign tH (tcon 1) / hp ==PC=> tH / hp.
Proof. intros. apply st_assignHP. apply v_c. Qed.
Example test_step_12:forall hp,
tapp (tassign (tloc (an int L) None)(tcon 1))(tderef (tloc (an int H) None)) / hp
==H=>*
tH / hp.
Proof. intros.
apply Multi_step with (y:=(tapp tH (tderef (tloc (an int H) None)),hp)).
apply st_app1. apply st_assigntH_H. apply v_c. reflexivity.
apply Multi_step with (y:=(tapp tH tH,hp)).
apply st_app2. apply v_H. apply st_derefloctH.
apply Multi_step with (y:=(tH,hp)).
apply st_apptH. apply v_H.
apply Multi_refl.
Qed.
Example test_step_13:forall PC hp,
tref (an int H)(tapp tH (tcon 0)) / hp
==PC=>*
tloc (an int H) None / hp.
Proof. intros.
apply Multi_step with (y:=(tref (an int H)(tH),hp)).
apply st_ref. apply st_apptH. apply v_c.
apply Multi_step with (y:=(tloc (an int H) None,hp)).
apply st_reftH. apply v_H. left. reflexivity.
apply Multi_refl.
Qed.
Example test_step_14:forall hp,
tderef (tref (an int L)(tcon 0)) / hp
==H=>*
tH / hp.
Proof. intros.
apply Multi_step with (y:=(tderef (tloc (an int L) None),hp)).
apply st_deref. apply st_reftH. apply v_c. right. left. reflexivity.
apply Multi_step with (y:=(tH,hp)).
apply st_derefloctH. apply Multi_refl.
Qed.
Example test_step_15:forall hp,
tassign (tref (an int L) tH)(tapp tH (tcon 0)) / hp
==L=>*
tunit / hp.
Proof. intros.
apply Multi_step with (y:=(tassign(tloc (an int L) None)(tapp tH (tcon 0)),hp)).
apply st_assign1. apply st_reftH. apply v_H. left. reflexivity.
apply Multi_step with (y:=(tassign (tloc (an int L) None) tH,hp)).
apply st_assign2. apply v_l. apply st_apptH. apply v_c.
apply Multi_step with (y:=(tunit,hp)).
apply st_assigntH_L. apply v_H. reflexivity. left. reflexivity.
apply Multi_refl.
Qed.
(**
Note we might thought that in [LowLang],the securtiy context can be freely modified
if we know that some configuration is reducible under some security context.
This is,however,not the case. Consider the following reduction under high
security context where a high cell is being over-written by a high value,
tassign (tloc (an int L) None)(tcon 1) / hp
==H=>
tH / hp.
If we change the security context to low, we suddenly have a stuck configuration,
tassign (tloc (an int L) None)(tcon 1) / hp ==L=> ?.
Now how about the other way round, can we argue that if a configuration is reducible
under low security context is also reducible under high security context?
The answer is still no.
Consider the following example where a low cell is being over-written by a low value,
tassign (tloc (an int L) (Some n))(tcon 1)
==L=>
tunit / heap_replace n (tcon 1,an int L) hp,where n < length hp.
Now if we change the security context to H then we get a stuck term,
tassign (tloc (an int L) (Some n))(tcon 1)
==H=>?.
In conclusion, since in [LowLang] we donot care for the cases where either a low
cell is being over-written by a high value or a high cell is being written by a
low value,the security context is not allowed to be changed at all even though we
have on our hands a reducible configuration under some security context.
*)
(*some stuck terms in [LowLang]*)
Definition stuck_term (s:tm) (hp:heap) (PC:Sec) : Prop :=
(~exists e', step (s,hp) PC e') /\ (~value s).
Lemma lt_same_F' : forall n m,
S n <= S m -> n <= m.
Proof. intros. generalize dependent n. induction m.
intros. destruct n. apply le_n. inversion H0. inversion H2.
intros. inversion H0. apply le_n. apply le_S. apply IHm in H2.
apply H2. Qed.
Lemma lt_same_F:forall n,
n < n -> False.
Proof. intros. induction n. inversion H0. unfold lt in H0. unfold lt in IHn.
apply lt_same_F' in H0. apply IHn in H0. inversion H0. Qed.
Example test_stuck_term_1:forall hp,
stuck_term (tassign (tloc (an int L) None)(tcon 1)) hp L.
Proof. intros. split. intros contra. inversion contra. inversion H0.
subst. inversion H0. subst. inversion H10. inversion H1. inversion H1.
subst. inversion H7. inversion H6. inversion H7. intros contra. inversion contra.
Qed.
Lemma test_stuck_term_2':forall {A:Type} (hp:list A),
hp <> hp -> False.
Proof. intros. apply H0. reflexivity.
Qed.
Example test_stuck_term_2:forall hp,
hp <> nil ->
stuck_term (tassign (tloc (an int L) (Some 0))(tcon 1)) hp H.
Proof. intros. split. intros contra. inversion contra. inversion H1.
inversion H11. inversion H13. inversion H7. inversion H8.
intros contra. inversion contra.
Qed.
Lemma not_equal_nat:forall (n:nat),
n <> n -> False.
Proof. intros. assert (n=n). reflexivity. apply H0 in H1.
inversion H1.
Qed.
(*typing rule*)
(*some auxiliary functions*)
Definition joinTs (T:Ty)(b:Sec) : Ty :=
match T , b with
| an rt s , L => an rt s
| an rt s , H => an rt H
end.
Definition joins (b1:Sec) (b2:Sec): Sec :=
match b1 with
| L => b2
| H => H
end.
(*typing relation*)
(**
Regarding the typing relation in [LowLang],all terms except for [tH] can be
typed with both low and high security level while [tH] can only be typed with
high security level. The typing relation itself is similar to that in [SecLang]
which consists of the programme counter,pc,the tying context,Gamma,the heap typing
,HT,the term,and the related type.
There are three cases needed discussion,
a. [t_H]
[tH] can be typed under all [pc],[Gamma],[HT],and [rt] as follows,
has_type pc Gamma HT tH (an rt H)
b. [t_loc]
Recall that in [LowLang] we only store low terms in the heap,hp,whose address,n,
satisfies that [n < length hp] while all high terms in the heap are indicated via
their address as [None]. Since the heap_typing,HT,should correspond to
the heap,hp,in a consistent way,when we type location,[tloc T N],we should consider
both reference to low terms where the referred loction is smaller than the length
of the heap_typing and high terms where the referred location is simply [None],
b.1. [t_loc_L]:forall n HT T pc Gamma,
n < length HT ->
heap_Tlookup n HT = Some T ->
has_type pc Gamma HT (tloc T (Some n))(an (ref T) L)
b.2. [t_loc_H]:forall pc Gamma HT rt,
has_type pc Gamma HT (tloc (an rt H) None)(an (ref (an rt H)) L)
c. [t_ref]
Recall the typing rule for allocation in [SecLang],the label of the allocation joined
with the programme counter must be smaller than the label of the referred type.
Such restriction still applies when we try to type allocation in [LowLang],
where the label of the allocation joined by [pc] has to be smaller than the label of
the referred type,
forall pc Gamma HT t T,
has_type pc Gamma HT t T ->
subsum_r pc (labelT T) ->
has_type pc Gamma HT (tref T t)(an (ref T) L)
*)
Inductive has_type : Sec -> context -> heap_Ty -> tm -> Ty -> Prop :=
| t_var : forall pc Gamma HT x T,
Gamma x = Some T ->
has_type pc Gamma HT (tvar x) T
| t_con : forall pc Gamma HT n,
has_type pc Gamma HT (tcon n) (an int L)
| t_unit: forall pc Gamma HT,
has_type pc Gamma HT tunit (an unit L)
(*special case*)
| t_H:forall pc Gamma HT rt,
has_type pc Gamma HT tH (an rt H)
(*special case*)
| t_loc_L:forall n HT T pc Gamma,
heap_Tlookup n HT = Some T ->
has_type pc Gamma HT (tloc T (Some n))(an (ref T) L)
| t_loc_H:forall pc Gamma HT rt,
has_type pc Gamma HT (tloc (an rt H) None) (an (ref (an rt H)) L)
| t_abs: forall pc pc' Gamma HT x T e T',
has_type pc' (Cupdate Gamma x (Some T)) HT e T' ->
has_type pc Gamma HT (tabs x T e) (an (fn T pc' T') L)
| t_app: forall pc Gamma HT T1 T2 T2' b t1 t2,
has_type pc Gamma HT t1 (an (fn T1 (joins pc b) T2) b) ->
has_type pc Gamma HT t2 T1 ->
joinTs T2 b = T2' ->
has_type pc Gamma HT (tapp t1 t2) T2'
(*special case*)
| t_ref: forall pc Gamma HT t T,
has_type pc Gamma HT t T ->
subsum_r pc (labelT T) ->
has_type pc Gamma HT (tref T t) (an (ref T) L)
| t_deref: forall pc Gamma HT t T T' b,
has_type pc Gamma HT t (an (ref T) b) ->
T' = joinTs T b ->
has_type pc Gamma HT (tderef t) T'
| t_assign: forall pc Gamma HT t1 t2 b b' T,
b' = labelT T ->
subsum_r (joins pc b) b' ->
has_type pc Gamma HT t1 (an (ref T) b) ->
has_type pc Gamma HT t2 T ->
has_type pc Gamma HT (tassign t1 t2) (an unit b')
| t_sub: forall pc pc' Gamma HT t T T',
has_type pc Gamma HT t T ->
subsum_r pc' pc ->
T <: T' ->
has_type pc' Gamma HT t T'
.
(*some examples*)
Example has_type_1:forall pc Gamma HT,
has_type pc Gamma HT tH (an int H).
Proof. intros. apply t_H. Qed.
Example has_type_2:forall pc Gamma HT,
has_type pc Gamma HT tH (an unit H).
Proof. intros. apply t_H. Qed.
Example has_type_3:forall pc Gamma HT,
has_type pc Gamma HT tH (an (ref (an int L)) H).
Proof. intros. apply t_H. Qed.
Example has_type_4:forall pc Gamma HT,
has_type pc Gamma HT tH (an (fn (an int L) L (an unit H)) H).
Proof. intros. apply t_H. Qed.
Example has_type_5:forall pc HT,
has_type pc (Cupdate empty_context (Id 0) (Some(an int H))) HT
(tvar (Id 0))
(an int H).
Proof. intros. apply t_var. rewrite->Cupdate_eq. reflexivity. Qed.
Example has_type_6:forall pc Gamma HT n,
has_type pc Gamma HT (tcon n) (an int H).
Proof. intros. apply t_sub with (pc:=pc)(T:=an int L). apply t_con.
apply sub_refl. apply subt_int. apply sub_LH. Qed.
Example has_type_7:forall pc Gamma HT,
has_type pc Gamma HT tunit (an unit H).
Proof. intros. apply t_sub with (pc:=pc)(T:=an unit L). apply t_unit.
apply sub_refl. apply subt_unit. apply sub_LH. Qed.
Example has_type_8:forall pc Gamma,
has_type pc Gamma [an int L]
(tloc (an int L) (Some 0))
(an (ref (an int L)) H).
Proof. intros. apply t_sub with (pc:=pc)(T:=an (ref (an int L)) L). apply t_loc_L.
reflexivity. apply sub_refl. apply subt_ref. apply sub_LH. Qed.
Example has_type_9:forall pc Gamma rt,
has_type pc Gamma []
(tloc (an rt H) None)
(an (ref (an rt H)) H).
Proof. intros. apply t_sub with (pc:=pc)(T:=an (ref (an rt H)) L). apply t_loc_H.
apply sub_refl. apply subt_ref. apply sub_LH. Qed.
Example has_type_10:forall Gamma HT,
has_type L Gamma HT
(tref (an int H) (tcon 0))
(an (ref (an int H)) H).
Proof. intros. apply t_sub with (pc:=L)(T:=an (ref (an int H)) L). apply t_ref.
apply t_sub with (pc:=L)(T:=an int L). apply t_con. apply sub_refl. apply subt_int. apply sub_LH.
apply sub_LH. apply sub_refl. apply subt_ref. apply sub_LH.
Qed.
Example has_type_10':forall Gamma HT,
has_type H Gamma HT
(tref (an int H) tH)
(an (ref (an int H)) H).
Proof. intros. apply t_sub with (pc:=H)(T:=an (ref (an int H)) L). apply t_ref. apply t_H. apply sub_refl.
apply sub_refl. apply subt_ref. apply sub_LH.
Qed.
Example has_type_11:forall Gamma HT,
has_type L Gamma HT
(tref (an int L)(tcon 0))
(an (ref (an int L)) L).
Proof. intros. apply t_ref. apply t_con. apply sub_refl.
Qed.
Example has_type_12:forall Gamma HT,
has_type L Gamma HT
(tref (an int L)(tcon 0))
(an (ref (an int L)) H).
Proof. intros. apply t_sub with (pc:=L)(T:=an (ref (an int L)) L). apply t_ref. apply t_con.
apply sub_refl. apply sub_refl. apply subt_ref. apply sub_LH.
Qed.
Example has_type_13:forall Gamma HT pc,
has_type pc Gamma HT
(tabs (Id 0)(an unit H)(tref (an int H)(tcon 0)))
(an (fn (an unit H) H (an (ref (an int H)) L)) H).
Proof. intros. apply t_sub with (pc:=pc)(T:=an (fn (an unit H) H (an (ref (an int H)) L)) L).
apply t_abs. apply t_ref. apply t_sub with (pc:=H)(T:=an int L). apply t_con.
apply sub_refl. apply subt_int. apply sub_LH. apply sub_refl. apply sub_refl.
apply subt_fn. apply sub_LH. apply sub_refl. apply subt_unit. apply sub_refl.
apply subt_ref. apply sub_refl. Qed.
Example has_type_14:forall Gamma HT,
has_type L Gamma HT
(tapp (tabs (Id 0)(an int H)(tvar (Id 0)))(tcon 0))
(an int H).
Proof. intros. apply t_app with (T1:=an int H)(T2:=an int H)(b:=H).
simpl. apply t_sub with (pc:=L)(T:=an (fn (an int H) H (an int H)) L).
apply t_abs. apply t_var. rewrite->Cupdate_eq. reflexivity. apply sub_refl.
apply subt_fn. apply sub_LH. apply sub_refl. apply subt_int. apply sub_refl.
apply subt_int. apply sub_refl. apply t_sub with (pc:=L)(T:=an int L). apply t_con.
apply sub_refl. apply subt_int. apply sub_LH. reflexivity. Qed.
Example has_type_15:forall Gamma HT,
has_type L Gamma HT
(tapp (tabs (Id 0)(an int H)(tvar (Id 0)))(tcon 0))
(an int H).
Proof. intros. apply t_app with (T1:=an int H)(T2:=an int H)(b:=L).
apply t_abs. apply t_var. rewrite->Cupdate_eq. reflexivity. apply t_sub with (pc:=L)(T:=an int L).
apply t_con. apply sub_refl. apply subt_int. apply sub_LH. reflexivity. Qed.
Example has_type_15':forall Gamma HT,
has_type L Gamma HT
(tapp tH (tcon 0))
(an int H).
Proof. intros. apply t_app with (T1:=an int L)(T2:=an int L)(b:=H). apply t_H. apply t_con.
reflexivity.
Qed.
Example has_type_16:forall pc Gamma,
has_type pc Gamma [an int L]
(tderef (tloc (an int L) (Some 0)))
(an int H).
Proof. intros. apply t_deref with (T:=an int L)(b:=H). apply t_sub with (pc:=pc)(T:=an (ref (an int L)) L).
apply t_loc_L. reflexivity. apply sub_refl. apply subt_ref. apply sub_LH. reflexivity.
Qed.
Example has_type_17:forall pc Gamma,
has_type pc Gamma [an int L]
(tderef (tloc (an int L) (Some 0)))
(an int L).
Proof. intros. apply t_deref with (T:=an int L)(b:=L). apply t_loc_L. reflexivity. reflexivity.
Qed.
Example has_type_18:forall pc Gamma rt,
has_type pc Gamma []
(tderef (tloc (an rt H) None))
(an rt H).
Proof. intros. apply t_deref with (T:=an rt H)(b:=L). apply t_loc_H. reflexivity.
Qed.
Example has_type_19:forall pc Gamma rt,
has_type pc Gamma []
(tderef (tloc (an rt H) None))
(an rt H).
Proof. intros. apply t_deref with (T:=an rt H)(b:=H). apply t_sub with (pc:=pc)(T:=an (ref (an rt H)) L).
apply t_loc_H. apply sub_refl. apply subt_ref. apply sub_LH. reflexivity.
Qed.
Example has_type_19':forall pc Gamma rt,
has_type pc Gamma []
(tderef tH)
(an rt H).
Proof. intros. apply t_deref with (T:=an rt L)(b:=H). apply t_H. reflexivity.
Qed.
Example has_type_20:forall Gamma HT,
has_type H Gamma HT
(tassign (tref (an int H)(tcon 0))(tcon 1))
(an unit H).
Proof. intros. apply t_assign with (b:=L)(T:=an int H). reflexivity. apply sub_refl.
apply t_ref. apply t_sub with (pc:=H)(T:=an int L). apply t_con. apply sub_refl.
apply subt_int. apply sub_LH. apply sub_refl. apply t_sub with (pc:=H)(T:=an int L).
apply t_con. apply sub_refl. apply subt_int. apply sub_LH. Qed.
Example has_type_21:forall Gamma HT,
has_type L Gamma HT
(tassign (tref (an int L)(tcon 0))(tcon 1))
(an unit L).
Proof. intros. apply t_assign with (b:=L)(T:=an int L). reflexivity. apply sub_refl.
apply t_ref. apply t_con. apply sub_refl. apply t_con.
Qed.
Example has_type_21':forall Gamma HT,
has_type L Gamma HT
(tassign tH (tcon 1))
(an unit H).
Proof. intros. apply t_assign with (b:=H)(T:=an int H). reflexivity. apply sub_refl. apply t_H.
apply t_sub with (pc:=L)(T:=an int L). apply t_con. apply sub_refl. apply subt_int. apply sub_LH.
Qed.
(*###inversion of [has_type]###*)
(*inversion of [has_type pc Gamma HT tH T]*)
Lemma inversion_tH:forall pc Gamma HT T,
has_type pc Gamma HT tH T ->
exists rt,
(an rt H) <: T.
Proof. intros. remember tH as t. induction H0. inversion Heqt. inversion Heqt. inversion Heqt.
exists rt. destruct rt. apply subt_int. apply sub_refl. apply subt_fn. apply sub_refl. apply sub_refl.
apply subtyping_refl. apply subtyping_refl. apply subt_unit. apply sub_refl. apply subt_ref. apply sub_refl.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt.
apply IHhas_type in Heqt. inversion Heqt. exists x. apply subtyping_trans with (x:=T)(y:=T). apply subtyping_refl.
apply H3. apply H2.
Qed.
(*inversion of [has_type pc Gamma HT (tvar x) T]*)
Lemma inversion_tvar: forall pc Gamma HT x T,
has_type pc Gamma HT (tvar x) T ->
exists T0, (Gamma x = Some T0)/\(T0 <: T).
Proof. intros. remember (tvar x) as t. induction H0.
inversion Heqt. subst. exists T. split. apply H0. apply subtyping_refl.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt.
apply IHhas_type in Heqt. inversion Heqt. exists x0. split. inversion H3.
apply H4. inversion H3. apply subtyping_trans with (x:=T)(y:=T). apply subtyping_refl.
apply H5. apply H2.
Qed.
(*inversion of [has_type pc Gamma HT (tabs x T1 e b) T]*)
Lemma inversion_tabs: forall pc Gamma HT x T1 T e,
has_type pc Gamma HT (tabs x T1 e) T ->
exists T1', exists T2, exists T2', exists pc', exists pc'', exists pc''', exists b,
(has_type pc' Gamma HT (tabs x T1 e) (an (fn T1 pc'' T2) L)) /\
(has_type pc'' (Cupdate Gamma x (Some T1)) HT e T2) /\(subsum_r pc''' pc'')/\(subsum_r pc pc')/\
(T1'<:T1)/\(T2<:T2')/\(subsum_r L b)/\((an (fn T1' pc''' T2') b) <: T).
Proof. intros. remember (tabs x T1 e) as t. induction H0. inversion Heqt. inversion Heqt. inversion Heqt.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. subst.
exists T1. exists T'. exists T'. exists pc. exists pc'. exists pc'. exists L. split. apply t_abs. apply H0.
split. apply H0. split. apply sub_refl. split. apply sub_refl. split. apply subtyping_refl. split. apply subtyping_refl.
split. apply sub_refl. apply subt_fn. apply sub_refl. apply sub_refl. apply subtyping_refl. apply subtyping_refl.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. apply IHhas_type in Heqt. inversion Heqt. exists x0.
inversion H4. exists x1. inversion H5. exists x2. inversion H6. exists x3. inversion H7. exists x4. inversion H8. exists x5. inversion H9.
exists x6. split. apply t_abs. apply H10. split. apply H10. split. apply H10. split. apply subsum_r_trans with (a:=pc')(b:=pc)(c:=x3).
apply H1. apply H10. split. apply H10. split. apply H10. split. apply H10. apply subtyping_trans with (x:=T)(y:=T). apply subtyping_refl.
apply H10. apply H2.
Qed.
(*inversion of [has_type pc Gamma HT (tcon n b) T]*)
Lemma inversion_tcon: forall pc Gamma HT T n,
has_type pc Gamma HT (tcon n) T ->
exists T', exists T'', exists b,
(T' = an int L)/\(T'' = an int b)/\(subsum_r L b)/\(T'' <: T).
Proof.
intros. remember (tcon n) as t. induction H0.
inversion Heqt. inversion Heqt. subst. exists (an int L). exists (an int L).
exists L. split. reflexivity. split. reflexivity. split. apply sub_refl.
apply subt_int. apply sub_refl. inversion Heqt. inversion Heqt. inversion Heqt.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt.
inversion Heqt.
apply IHhas_type in Heqt. inversion Heqt. exists x. inversion H3.
exists x0. inversion H4. exists x1. split. apply H5. split. apply H5. split. apply H5.
apply subtyping_trans with (x:=T)(y:=T). apply subtyping_refl. apply H5. apply H2.
Qed.
(*inversion of [has_type pc Gamma HT (tunit b) T]*)
Lemma inversion_tunit:forall pc Gamma HT T,
has_type pc Gamma HT tunit T ->
exists T', exists T'', exists b,
(T'=an unit L)/\(T''=an unit b)/\(subsum_r L b)/\(T''<:T).
Proof. intros. remember tunit as t. induction H0. inversion Heqt. inversion Heqt.
exists (an unit L). exists (an unit L). exists L. split. reflexivity. split. reflexivity. split.
apply sub_refl. apply subt_unit. apply sub_refl. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt.
apply IHhas_type in Heqt. inversion Heqt. exists x. inversion H3.
exists x0. inversion H4. exists x1. split. apply H5. split. apply H5. split. apply H5. apply subtyping_trans with (x:=T)(y:=T).
apply subtyping_refl. apply H5. apply H2.
Qed.
(**
inversion of [has_type pc Gamma HT (tloc T (Some n)) T']
where n <= length HT
*)
Lemma inversion_tloc_L:forall pc Gamma HT n T1 T,
has_type pc Gamma HT (tloc T1 (Some n)) T ->
exists T', exists T'', exists b,
(heap_Tlookup n HT = Some T1)/\(T'=an (ref T1) L)/\(T''=an (ref T1) b)/\(subsum_r L b)/\(T''<:T).
Proof. intros. remember (tloc T1 (Some n)) as t. induction H0. inversion Heqt. inversion Heqt. inversion Heqt.
inversion Heqt. inversion Heqt. subst. exists (an (ref T1) L). exists (an (ref T1) L). exists L. split.
apply H0. split. reflexivity. split. reflexivity. split. apply sub_refl. apply subtyping_refl.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. apply IHhas_type in Heqt. inversion Heqt.
exists x. inversion H3. exists x0. inversion H4. exists x1. split. apply H5. split. apply H5. split. apply H5. split. apply H5.
apply subtyping_trans with (x:=T)(y:=T). apply subtyping_refl. apply H5. apply H2.
Qed.
(*inversion of [has_type pc Gamma HT (tloc T None) T']*)
Lemma inversion_tloc_H:forall pc Gamma HT T1 T,
has_type pc Gamma HT (tloc T1 None) T ->
exists T', exists T'', exists b, exists rt,
(T1=an rt H)/\
(T'=an (ref (an rt H)) L)/\(T''=an (ref (an rt H)) b)/\(subsum_r L b)/\(T''<:T).
Proof. intros. remember (tloc T1 None) as t. induction H0. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt.
inversion Heqt. subst. exists (an (ref (an rt H)) L). exists (an (ref (an rt H)) L). exists L. exists rt. split. reflexivity. split. reflexivity. split. reflexivity.
split. apply sub_refl. apply subtyping_refl. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt.
apply IHhas_type in Heqt. inversion Heqt. exists x.
inversion H3. exists x0. inversion H4. exists x1. inversion H5. exists x2. split. apply H6. split. apply H6. split. apply H6. split. apply H6.
apply subtyping_trans with (x:=T)(y:=T). apply subtyping_refl.
apply H6. apply H2.
Qed.
(*inversion of [has_type pc Gamma HT (tapp t1 t2) T]*)
Lemma inversion_tapp: forall pc Gamma HT t1 t2 T2,
has_type pc Gamma HT (tapp t1 t2) T2 ->
exists T1', exists T2', exists b', exists T1'', exists T1''', exists T2'', exists b'', exists pc', exists sp', exists sp'',
(sp'=joins pc' b')/\has_type pc' Gamma HT t1 (an (fn T1' sp' T2') b')/\((an (fn T1' sp' T2') b')<:(an (fn T1'' sp'' T2'') b''))/\
(has_type pc' Gamma HT t2 T1''')/\(T1''' <: T1'')/\(subsum_r pc pc')/\
((joinTs T2'' b'')<:T2).
Proof. intros. remember (tapp t1 t2) as t. induction H0.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt.
subst. exists T1. exists T2. exists b. exists T1. exists T1. exists T2. exists b. exists pc. exists (joins pc b). exists (joins pc b). split. reflexivity.
split. apply H0_. split. apply subtyping_refl. split. apply H0_0. split. apply subtyping_refl. split. apply sub_refl. apply subtyping_refl.
inversion Heqt. inversion Heqt. inversion Heqt. apply IHhas_type in Heqt. inversion Heqt. exists x. inversion H3. exists x0. inversion H4. exists x1. inversion H5. exists x2.
inversion H6. exists x3. inversion H7. exists x4. inversion H8. exists x5. inversion H9. exists x6. inversion H10. exists x7. inversion H11. exists x8.
split. apply H12. split. apply H12. split. apply H12. split. apply H12. split. apply H12. split. apply subsum_r_trans with (a:=pc')(b:=pc)(c:=x6). apply H1. apply H12. apply subtyping_trans with (x:=T)(y:=T).
apply subtyping_refl. apply H12. apply H2.
Qed.
(*inversion of [has_type pc Gamma HT (tref T1 t b) T]*)
Lemma inversion_tref:forall pc Gamma HT T1 T t,
has_type pc Gamma HT (tref T1 t) T ->
exists pc', exists T1', exists T1'', exists b,
(subsum_r L b)/\
((an (ref T1) b)<:T)/\
(has_type pc' Gamma HT t T1')/\(T1' <: T1'')/\(subsum_r pc pc')/\(T1''<:T1)/\
(subsum_r pc' (labelT T1')).
Proof. intros. remember (tref T1 t) as e. induction H0. inversion Heqe. inversion Heqe. inversion Heqe.
inversion Heqe. inversion Heqe. inversion Heqe. inversion Heqe. inversion Heqe. inversion Heqe. subst.
exists pc. exists T1. exists T1. exists L. split. apply sub_refl. split. apply subtyping_refl.
split. apply H0. split. apply subtyping_refl. split. apply sub_refl. split. apply subtyping_refl. apply H1.
inversion Heqe. inversion Heqe. apply IHhas_type in Heqe. inversion Heqe. exists x. inversion H3. exists x0.
inversion H4. exists x1. inversion H5. exists x2. split. apply H6. split.
apply subtyping_trans with (x:=T)(y:=T). apply subtyping_refl. apply H6. apply H2. split. apply H6.
split. apply H6. split. apply subsum_r_trans with (a:=pc')(b:=pc)(c:=x). apply H1. apply H6. split. apply H6.
apply H6.
Qed.
(*inversion of [has_type pc Gamma HT (tderef t) T]*)
Lemma inversion_tderef:forall pc Gamma HT t T,
has_type pc Gamma HT (tderef t) T ->
exists pc', exists T1, exists b', exists b'',
has_type pc' Gamma HT t (an (ref T1) b')/\(subsum_r b' b'')/\
((joinTs T1 b'')<:T)/\(subsum_r pc pc').
Proof. intros. remember (tderef t) as e. induction H0. inversion Heqe. inversion Heqe. inversion Heqe. inversion Heqe. inversion Heqe.
inversion Heqe. inversion Heqe. inversion Heqe. inversion Heqe. inversion Heqe. subst. exists pc. exists T. exists b. exists b. split. apply H0. split.
apply sub_refl. split. apply subtyping_refl. apply sub_refl. inversion Heqe.
apply IHhas_type in Heqe. inversion Heqe. exists x. inversion H3. exists x0. inversion H4. exists x1.
inversion H5. exists x2. split. apply H6. split. apply H6. split. apply subtyping_trans with (x:=T)(y:=T).
apply subtyping_refl. apply H6. apply H2. apply subsum_r_trans with (a:=pc')(b:=pc)(c:=x).
apply H1. apply H6.
Qed.
(*inversion of [has_type pc Gamma HT (tassign t1 t2) T]*)
Lemma inversion_tassign:forall pc Gamma HT t1 t2 T,
has_type pc Gamma HT (tassign t1 t2) T ->
exists pc',exists T1, exists T1', exists b,
has_type pc' Gamma HT (tassign t1 t2)(an unit (labelT T1))/\
has_type pc' Gamma HT t1 (an (ref T1) b)/\
has_type pc' Gamma HT t2 T1'/\
(T1'<:T1)/\(subsum_r pc pc')/\(subsum_r (joins pc' b)(labelT T1))/\
((an unit (labelT T1))<:T).
Proof. intros. remember (tassign t1 t2) as t. induction H0. inversion Heqt.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt.
inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. inversion Heqt. subst. exists pc.
exists T. exists T. exists b. split. apply t_assign with (b:=b)(T:=T). reflexivity. apply H1.
apply H0_. apply H0_0. split. apply H0_. split. apply H0_0. split. apply subtyping_refl. split.
apply sub_refl. split. apply H1. apply subtyping_refl. apply IHhas_type in Heqt.
inversion Heqt. exists x. inversion H3. exists x0. inversion H4. exists x1. inversion H5. exists x2.
split. apply H6. split. apply H6. split. apply H6. split. apply H6. split. apply subsum_r_trans with (a:=pc')(b:=pc)(c:=x).
apply H1. apply H6. split. apply H6. apply subtyping_trans with (x:=T)(y:=T). apply subtyping_refl. apply H6. apply H2.
Qed.
(*#############################*)
(*some examples of ill-typed terms*)
Example ill_typed_1:forall pc HT,
~has_type pc empty_context HT
(tvar (Id 0))
(an int L).
Proof. intros. intros contra. apply inversion_tvar in contra. inversion contra. inversion H0.
inversion H1.
Qed.
Example ill_typed_2:forall pc Gamma HT,
~has_type pc Gamma HT
(tcon 0)
(an unit H).
Proof. intros. intros contra. apply inversion_tcon in contra. inversion contra. inversion H0. inversion H1.
inversion H2. inversion H4. inversion H6. subst. inversion H8.
Qed.
Example ill_typed_3:forall pc Gamma HT,
~has_type pc Gamma HT
tunit
(an int L).
Proof. intros. intros contra. apply inversion_tunit in contra. inversion contra. inversion H0. inversion H1.
inversion H2. inversion H4. inversion H6. subst. inversion H8.
Qed.
Example ill_typed_4:forall pc Gamma HT rt,
~has_type pc Gamma HT
tH
(an rt L).
Proof. intros. intros contra. apply inversion_tH in contra. inversion contra. inversion H0. inversion H2.
inversion H5. inversion H2. inversion H2.
Qed.
Example ill_typed_5:forall pc Gamma,
~has_type pc Gamma [an int L]
(tloc (an int L) (Some 1))
(an (ref (an int L)) H).
Proof. intros. intros contra. apply inversion_tloc_L in contra. inversion contra.
inversion H0. inversion H1. inversion H2. simpl in H3. inversion H3.
Qed.
Example ill_typed_6:forall pc Gamma,
~has_type pc Gamma [an int L]
(tloc (an int H) (Some 0))
(an (ref (an int L)) H).
Proof. intros. intros contra. apply inversion_tloc_L in contra. inversion contra.
inversion H0. inversion H1. inversion H2. simpl in H3. inversion H3.
Qed.
Example ill_typed_7:forall pc Gamma HT,
~has_type pc Gamma HT
(tabs (Id 0)(an int L)(tvar (Id 0)))
(an int L).
Proof. intros. intros contra. apply inversion_tabs in contra. inversion contra.
inversion H0. inversion H1. inversion H2. inversion H3. inversion H4. inversion H5.
inversion H6. inversion H8. inversion H10. inversion H12. inversion H14. inversion H16.
inversion H18. inversion H20.
Qed.
Example ill_typed_8:forall pc Gamma HT,
~has_type pc Gamma HT
(tabs (Id 0)(an int H)(tref (an int L)(tcon 0)))
(an (fn (an int H) H (an (ref (an int L)) H)) H).
Proof. intros. intros contra. apply inversion_tabs in contra. inversion contra. inversion H0.
inversion H1. inversion H2. inversion H3. inversion H4. inversion H5. inversion H6. inversion H8.
inversion H10. inversion H12. inversion H14. inversion H16. inversion H18. inversion H20. subst. destruct x4.
inversion H30. destruct x3. inversion H11. apply inversion_tref in H9. inversion H9. inversion H21. inversion H22.
inversion H23. inversion H24. inversion H27. inversion H29. inversion H34. inversion H36. inversion H38.
apply inversion_tcon in H33. inversion H33. inversion H41. inversion H42. inversion H43. inversion H45. inversion H47.
rewrite->H46 in H49. destruct x4. destruct r. destruct x3. inversion H37. destruct s. inversion H40. destruct x6. destruct r.
destruct s. inversion H35. inversion H52. inversion H39. inversion H52. inversion H39. inversion H39. inversion H39. inversion H49.
inversion H49. inversion H49.
Qed.
Example ill_typed_9:forall pc Gamma HT,
~has_type pc Gamma HT
(tapp (tcon 0)(tcon 1))
(an int L).
Proof. intros. intros contra. apply inversion_tapp in contra. inversion contra. inversion H0. inversion H1. inversion H2. inversion H3.
inversion H4. inversion H5. inversion H6. inversion H7. inversion H8. inversion H9. inversion H11. apply inversion_tcon in H12. inversion H12.
inversion H14. inversion H15. inversion H16. inversion H18. inversion H20. subst. inversion H22.
Qed.
Example ill_typed_10:forall Gamma HT,
~has_type H Gamma HT
(tapp (tabs (Id 0)(an int L)(tref (an int L)(tcon 0)))(tcon 1))
(an (ref (an int L)) L).
Proof. intros. intros contra. apply inversion_tapp in contra. inversion contra. inversion H0. inversion H1. inversion H2. inversion H3. inversion H4.
inversion H5. inversion H6. inversion H7. inversion H8. inversion H9. inversion H11. inversion H13. inversion H15. inversion H17. inversion H19.
destruct x6. inversion H0. inversion H20. simpl in H10. subst. apply inversion_tabs in H12. inversion H12. inversion H10. inversion H22. inversion H23.
inversion H24. inversion H25. inversion H26. inversion H27. inversion H29. inversion H31. inversion H33. destruct x10. inversion H34. inversion H35.
inversion H37. inversion H39. inversion H41. destruct x12. inversion H51. destruct x11. inversion H32. apply inversion_tref in H30. inversion H30. inversion H54.
inversion H55. inversion H56. inversion H57. inversion H59. inversion H61. inversion H63. inversion H65. inversion H67. destruct x12. destruct r. destruct s.
destruct x11. destruct r. destruct s. destruct x10. inversion H66. inversion H69. inversion H64. inversion H72. inversion H64. inversion H64. inversion H64.
inversion H68. inversion H72. inversion H68. inversion H68. inversion H68.
Qed.
Example ill_typed_11:forall Gamma HT,
~has_type H Gamma HT
(tref (an int L)(tcon 0))
(an (ref (an int L)) H).
Proof. intros. intros contra. apply inversion_tref in contra. inversion contra. inversion H0. inversion H1. inversion H2. inversion H3. inversion H5. inversion H7.
inversion H9. inversion H11. inversion H13. destruct x1. destruct r. destruct s. destruct x0. destruct r. destruct s. destruct x. inversion H12. inversion H15.
inversion H10. inversion H18. inversion H10. inversion H10. inversion H10. inversion H14. inversion H18. inversion H14. inversion H14. inversion H14.
Qed.
Example ill_typed_12:forall pc Gamma,
~has_type pc Gamma []
(tderef (tloc (an int L) None))
(an int H).
Proof. intros. intros contra. apply inversion_tderef in contra. inversion contra. inversion H0. inversion H1. inversion H2. inversion H3.
apply inversion_tloc_H in H4. inversion H4. inversion H6. inversion H7. inversion H8. inversion H9. inversion H10.
Qed.
Example ill_typed_13:forall pc Gamma HT,
~has_type pc Gamma HT
(tassign (tcon 0)(tcon 1))
(an unit L).
Proof. intros. intros contra. apply inversion_tassign in contra. inversion contra. inversion H0. inversion H1. inversion H2. inversion H3. inversion H5.
apply inversion_tcon in H6. inversion H6. inversion H8. inversion H9. inversion H10. inversion H12. inversion H14. subst. inversion H16.
Qed.
Example ill_typed_14:forall Gamma HT n,
~has_type H Gamma HT
(tassign (tloc (an int L) (Some n))(tcon 1))
(an unit H).
Proof. intros. intros contra. apply inversion_tassign in contra. inversion contra. inversion H0. inversion H1. inversion H2. inversion H3. inversion H5.
inversion H7. inversion H9. inversion H11. destruct x. inversion H12. apply inversion_tloc_L in H6. inversion H6. inversion H14. inversion H15. inversion H16.
inversion H18. inversion H20. inversion H22. subst. inversion H24. subst. inversion H13. simpl in H19. inversion H19.
Qed.
(**
Properties of [LowLang],
a. Determinism
b. ...
*)
(*Determinism*)
Theorem determinism: forall t t' t'' hp hp' hp'' PC,
t / hp ==PC=> t' / hp' ->
t / hp ==PC=> t'' / hp'' ->
(t' = t''/\hp' = hp'').
Proof. intros t. induction t.
Case ("tvar").
intros. inversion H0.
Case ("tcon").
intros. inversion H0.
Case ("tabs").
intros. inversion H0.
Case ("tapp").
intros. inversion H0. inversion H1. subst. inversion H9. subst. split.
reflexivity. reflexivity. subst. inversion H13. subst. inversion H6. subst.
inversion H16. subst. inversion H16. subst. inversion H16. subst. inversion H16. subst. inversion H16. subst.
inversion H9. subst.
inversion H1. subst. inversion H6. subst.
apply IHt1 with (t':=t1')(t'':=t1'0)(hp'':=hp'') in H6. inversion H6. subst. split. reflexivity.
reflexivity. apply H7. subst. inversion H7. subst. inversion H6. subst. inversion H6. subst. inversion H6.
subst. inversion H6. subst. inversion H6. subst. inversion H6. subst. inversion H1. subst. inversion H7.
subst. inversion H9. subst. inversion H9. subst. inversion H9. subst. inversion H9. subst. inversion H9.
subst. inversion H6. subst. inversion H7. subst. inversion H7. subst. inversion H7. subst. inversion H7. subst.
inversion H7. subst.
apply IHt2 with (t':=t2')(t'':=t2'0)(hp'':=hp'')in H9. inversion H9. subst. split. reflexivity. reflexivity.
apply H11. subst. inversion H7. subst. inversion H9. subst. inversion H9. subst. inversion H9. subst. inversion H9. subst.
inversion H9. subst. inversion H1. subst. inversion H7. subst. inversion H6. subst. inversion H10. subst. inversion H10. subst. inversion H10. subst.
inversion H10. subst. inversion H10. subst. split. reflexivity. reflexivity.
Case ("tunit").
intros. inversion H0.
Case ("tref").
intros. inversion H0. inversion H1. subst. split. reflexivity. reflexivity. subst. inversion H20.
apply H9 in H2. inversion H2. inversion H2. inversion H3. rewrite->H10 in H3. inversion H3. subst.
inversion H7. subst.
inversion H17. subst. inversion H17. subst. inversion H17. subst. inversion H17. subst. inversion H17. subst.
inversion H1. subst. inversion H9. apply H11 in H2. inversion H2. inversion H2. inversion H3. rewrite->H12 in H3. inversion H3.
split. reflexivity. reflexivity. subst. inversion H6. subst.
inversion H9. subst. inversion H7. subst. inversion H7. subst. inversion H7. subst.
inversion H7. subst. inversion H7. subst. inversion H7. subst.
inversion H1. subst. inversion H8. subst. inversion H6. subst. inversion H6. subst. inversion H6. subst. inversion H6. subst.
inversion H6. subst. inversion H7. subst. inversion H6. subst. inversion H6. subst. inversion H6. subst. inversion H6. subst.
inversion H6. subst.
specialize (IHt t'0 t' hp hp' hp''). apply IHt in H6.
inversion H6. subst. split. reflexivity. reflexivity. apply H7.
Case ("tderef").
intros. inversion H0. inversion H1. subst. inversion H9. subst. split. reflexivity. reflexivity. subst. inversion H10. subst. inversion H12. subst.
inversion H10. subst. inversion H1. subst. split. reflexivity. reflexivity. subst. inversion H5. subst. inversion H1. subst. inversion H5. subst.
inversion H5. subst.
apply IHt with (t':=t'0)(t'':=t')(hp'':=hp'') in H5. inversion H5. subst. split. reflexivity. reflexivity. apply H6. subst. inversion H5. subst.
inversion H1. subst. inversion H5. split. reflexivity. reflexivity.
Case ("tloc").
intros. inversion H0.
Case ("tassign").
intros. inversion H0. inversion H1. subst. inversion H13. subst. split. reflexivity. reflexivity. subst. inversion H13. subst. inversion H11. inversion H2.
subst. inversion H13. subst. inversion H17. subst. inversion H9. subst.
inversion H20. subst. inversion H20. subst. inversion H20. subst. inversion H20.
subst. inversion H20. subst. inversion H1. subst. split. reflexivity. reflexivity.
subst. inversion H11. subst. inversion H6. subst. inversion H7. subst. inversion H11. subst. inversion H11. subst. inversion H11. subst. inversion H11. subst. inversion H11.
subst. inversion H1. subst. inversion H10. subst. split. reflexivity. reflexivity. subst. inversion H7. subst. inversion H6. subst. inversion H10. subst. inversion H10. subst. inversion H10. subst.
inversion H10. subst. inversion H10. subst. inversion H1. subst. split. reflexivity. reflexivity. subst. inversion H7. subst. inversion H6. subst.
inversion H10. subst. inversion H10. subst. inversion H10. subst. inversion H10. subst. inversion H10. subst. inversion H1. subst. inversion H6. subst. inversion H6. subst. inversion H6. subst. inversion H6.
subst.
specialize (IHt1 t1' t1'0 hp hp' hp'' PC). apply IHt1 in H6. inversion H6. subst.
split. reflexivity. reflexivity. apply H7. subst. inversion H7. subst. inversion H6. subst. inversion H6. subst. inversion H6. subst. inversion H6. subst. inversion H6. subst.
inversion H1. subst.
inversion H11. subst. inversion H0. inversion H7. subst. inversion H15. subst. inversion H0. inversion H7. subst. inversion H15. subst. inversion H0. inversion H7. subst. inversion H15. subst.
inversion H0. inversion H7. subst. inversion H15. subst. inversion H0. inversion H7. subst. inversion H15. subst. inversion H8. subst.
inversion H9. subst. inversion H9. subst. inversion H9. subst. inversion H9. subst. inversion H9. subst. inversion H7. subst. inversion H9.
subst. inversion H9. subst. inversion H9. subst. inversion H9. subst. inversion H9. subst. inversion H0. subst. inversion H8. subst. inversion H7. subst.
inversion H9. subst. inversion H9. subst. inversion H9. subst. inversion H9. subst. inversion H9. subst. inversion H6. subst. inversion H7. subst. inversion H7. subst. inversion H7. subst. inversion H7. subst.
inversion H7. subst.
specialize (IHt2 t2' t2'0 hp hp' hp'' PC). apply IHt2 in H9. inversion H9. subst. split. reflexivity. reflexivity. apply H11.
Case ("tH").
intros. inversion H0.
Qed.
Theorem determinism_extended:forall x y z PC,
value (fst y) ->
value (fst z) ->
Multistep x PC y ->
Multistep x PC z ->
fst y = fst z.
Proof. intros. generalize dependent z. induction H2.
intros. inversion H0. inversion H3. subst. apply H4. subst. destruct x. simpl in H4. subst.
inversion H2. inversion H3. subst. apply H4. subst. destruct x. simpl in H4. subst. inversion H2.
inversion H3. subst. apply H4. subst. destruct x. simpl in H4. subst. inversion H2.
inversion H3. subst. apply H4. subst. destruct x. simpl in H4. subst. inversion H2.
inversion H3. subst. apply H4. subst. destruct x. simpl in H4. subst. inversion H2.
intros. apply IHMulti. apply H0. apply H3. inversion H4. subst. inversion H3. subst.
destruct z0. simpl in H6. subst. inversion H1. destruct z0. simpl in H6. subst. inversion H1. destruct z0. simpl in H6. subst. inversion H1.
destruct z0. simpl in H6. subst. inversion H1. destruct z0. simpl in H6. subst. inversion H1.
subst. destruct x. destruct y. destruct y0. apply determinism with (t':=t0)(hp':=h0)(t'':=t1)(hp'':=h1)in H1. inversion H1. subst.
apply H6. apply H5.
Qed.
End LowLang.
Module Correspondence.
(*Projection function*)
(*a. projection of term*)
Fixpoint project_e (e : SecLang.tm) : LowLang.tm :=
match e with
(*variables*)
| SecLang.tvar x => LowLang.tvar x
(*constants*)
| SecLang.tcon n L => LowLang.tcon n
| SecLang.tcon n H => LowLang.tH
(*protects*)
| SecLang.tprot L e' => project_e e'
| SecLang.tprot H e' => LowLang.tH
(*abstractions*)
| SecLang.tabs x T e L => LowLang.tabs x T (project_e e)
| SecLang.tabs x T e H => LowLang.tH
(*applications*)
| SecLang.tapp t1 t2 => LowLang.tapp (project_e t1)(project_e t2)
(*unit*)
| SecLang.tunit L => LowLang.tunit
| SecLang.tunit H => LowLang.tH
(*allocation*)
| SecLang.tref T t L => LowLang.tref T (project_e t)
| SecLang.tref T t H => LowLang.tH
(*deallocation*)
| SecLang.tderef t => LowLang.tderef (project_e t)
(*location*)
| SecLang.tloc T N L => LowLang.tloc T N
| SecLang.tloc T N H => LowLang.tH
(*assignment*)
| SecLang.tassign t1 t2 => LowLang.tassign (project_e t1)(project_e t2)
end.
(*some lemma regarding [project_e]*)
Lemma project_e_subst:forall x v e,
SecLang.value v ->
project_e (SecLang.subst x v e) = LowLang.subst x (project_e v)(project_e e).
Proof. intros. generalize dependent x. generalize dependent v. induction e.
Case ("tvar"). intros. simpl. remember (beq_id x i) as CC. destruct CC. reflexivity.
reflexivity.
Case ("tprot"). intros. simpl. destruct s. apply IHe. apply H0. reflexivity.
Case ("tcon"). intros. simpl. destruct s. reflexivity. reflexivity.
Case ("tabs"). intros. simpl. destruct s. simpl. remember (beq_id x i) as CC. destruct CC.
reflexivity. apply IHe with(x:=x)in H0. rewrite<-H0. reflexivity.
reflexivity.
Case ("tapp"). intros. simpl. assert (SecLang.value v). apply H0. apply IHe1 with(x:=x)in H0.
apply IHe2 with(x:=x)in H1. rewrite->H0. rewrite->H1. reflexivity.
Case ("tunit"). intros. simpl. destruct s. reflexivity. reflexivity.
Case ("tref"). intros. simpl. destruct s. apply IHe with(x:=x)in H0. rewrite->H0. reflexivity.
reflexivity.
Case ("tderef"). intros. simpl. apply IHe with(x:=x)in H0. rewrite->H0. reflexivity.
Case ("tloc"). intros. simpl. destruct s. reflexivity. reflexivity.
Case ("tassign"). intros. simpl. assert (SecLang.value v). apply H0. apply IHe1 with(x:=x)in H0.
apply IHe2 with(x:=x)in H1. rewrite->H0. rewrite->H1. reflexivity.
Qed.
(*marked heap*)
Definition heap := list ((LowLang.tm*Ty)*(nat*nat)).
Definition emp_hp:= @nil ((LowLang.tm*Ty)*(nat*nat)).
(**
Note the marked heap is the projection of the heap in [SecLang] to a heap where
each of its member is marked with a pair of numbers indication the change of its
location in the heap
*)
(*Some examples*)
Check (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil).
(**
Note the above marked heap indicates that,
a. a Low constant in [SecLang] whose position on the heap is [0] before the
projection and [0] after the projection
b. another constant in [SecLang] whose position on the heap is [2] before the
projection and [1] after the projection
*)
(*heap_projection*)
(*firstly we generate a heap where every cell is marked according to its location on the heap*)
Fixpoint marked_heap' (hp:SecLang.heap)(n:nat) : list ((SecLang.tm*Ty)*(nat*nat)) :=
match hp , n with
| h :: t , 0 =>match h with
|(e,T)=>((e,T),(0,0)) :: (marked_heap' t 1)
end
| h :: t , n =>match h with
|(e,T)=>((e,T),(n,n)) :: (marked_heap' t (S n))
end
| nil , _ => nil
end.
(*some tests*)
Example test_marked_heap'_1:
marked_heap' ((SecLang.tcon 6 L,an int L) :: (SecLang.tcon 6 H,an int H) :: (SecLang.tcon 5 L,an int L) :: nil) 0
= ((SecLang.tcon 6 L,an int L),(0,0)) :: ((SecLang.tcon 6 H,an int H),(1,1)) :: ((SecLang.tcon 5 L,an int L),(2,2)) :: nil.
Proof. simpl. reflexivity. Qed.
Example test_marked_heap'_2:
marked_heap' ((SecLang.tcon 0 L,an int L) :: (SecLang.tcon 1 L,an int L) :: nil) 0
= ((SecLang.tcon 0 L,an int L),(0,0)) :: ((SecLang.tcon 1 L,an int L),(1,1)) :: nil.
Proof. simpl. reflexivity. Qed.
(*some lemmas regarding [marked_heap']*)
Lemma n_plus_1:forall n,
n + 1 = S n.
Proof. intros n. induction n. reflexivity. rewrite->plus_Sn_m. rewrite->IHn.
reflexivity.
Qed.
Lemma marked_heap'_hd:forall h t n,
marked_heap' (h :: t) n = (h,(n,n)) :: (marked_heap' t (n+1)).
Proof. intros. generalize dependent h. generalize dependent t. induction n.
intros. simpl. destruct h. reflexivity.
intros. simpl. destruct h. rewrite->n_plus_1. reflexivity.
Qed.
(* then we get the marked heap with only low cells on it*)
Fixpoint marked_heap (hp:list ((SecLang.tm*Ty)*(nat*nat))) (n:nat): list ((LowLang.tm*Ty)*(nat*nat)) :=
match hp with
| h :: t =>match h with
|(a,b)=>match a with
| (e,T)=>match SecLang.label e with
| H =>marked_heap t (S n)
| L =>match b with
|(n1,n2)=>match a with
|(e,T)=>((project_e e,T),(n1,n2-n)) :: (marked_heap t n)
end
end
end
end
end
| nil => nil
end.
(*some test*)
Example test_marked_heap_1:
marked_heap (((SecLang.tcon 1 L,an int L),(0,0)) :: ((SecLang.tcon 2 H,an int H),(1,1)) :: ((SecLang.tcon 3 L,an int L),(2,2)) :: ((SecLang.tcon 4 H,an int H),(3,3)) :: ((SecLang.tcon 5 L,an int L),(4,4)) :: nil) 0
= (((LowLang.tcon 1,an int L),(0,0)) :: ((LowLang.tcon 3,an int L),(2,1)) :: ((LowLang.tcon 5,an int L),(4,2)) :: nil).
Proof. simpl. reflexivity.
Qed.
(*some lemmas regarding [marked_heap]*)
Lemma marked_heap_L:forall e T n1 n2 t n,
SecLang.label e = L ->
marked_heap (((e,T),(n1,n2)) :: t) n = ((project_e e,T),(n1,n2-n)) :: (marked_heap t n).
Proof. intros. simpl. rewrite->H0. reflexivity.
Qed.
Lemma marked_heap_mark_length:forall hp n1 n2 n3 n4,
length (marked_heap(marked_heap' hp n1)n2) = length (marked_heap(marked_heap' hp n3)n4).
Proof. intros hp. induction hp.
Case ("nil"). intros. reflexivity.
Case ("h::t"). intros. destruct a. simpl. destruct n1. destruct n3. simpl. remember (SecLang.label t) as BB.
destruct BB. simpl. specialize (IHhp 1 n2 1 n4). rewrite->IHhp. reflexivity.
specialize (IHhp 1 (S n2) 1 (S n4)). rewrite->IHhp. reflexivity. simpl. remember (SecLang.label t) as BB.
destruct BB. simpl. specialize (IHhp 1 n2 (S (S n3)) n4). rewrite<-IHhp. reflexivity.
specialize (IHhp 1 (S n2)(S (S n3)) (S n4)). rewrite<-IHhp. reflexivity. destruct n3. simpl.
remember (SecLang.label t) as BB. destruct BB. simpl. specialize (IHhp (S (S n1)) n2 1 n4).
rewrite<-IHhp. reflexivity. specialize (IHhp (S (S n1)) (S n2) 1 (S n4)). rewrite<-IHhp.
reflexivity. simpl. remember (SecLang.label t) as BB. destruct BB. simpl. specialize (IHhp (S (S n1)) n2 (S (S n3)) n4).
rewrite<-IHhp. reflexivity. specialize (IHhp (S (S n1)) (S n2) (S (S n3)) (S n4)). rewrite<-IHhp.
reflexivity.
Qed.
(*look-up function regarding the marked heap*)
(**
Note: in the current segment, heaps are all marked and there are two ways of looking up
a value stored on a heap,
a. looking up via matching up query with some mark,[marked_heap_lookup]
b. looking up via the query indicating the position of some value stored on the heap
[].
*)
(*a*)
(**
The search is being done via looking for a match between a target and the first number
of some mark of the marked heap
*)
Fixpoint marked_heap_lookup (n:nat)(hp:list ((LowLang.tm*Ty)*(nat*nat))):(option (LowLang.tm*Ty)):=
match hp with
| h :: t => match h with
| (fst,snd) => match snd with
| (n1,n2) =>if beq_nat n1 n
then Some fst
else marked_heap_lookup n t
end
end
| nil => None
end.
(*extract the result of [marked_heap_lookup]*)
Definition marked_efst (p:option(LowLang.tm*Ty)) : option (LowLang.tm) :=
match p with
| None => None
| Some (t , T) => Some t
end.
(*b*)
(*heap_lookup*)
Fixpoint heap_lookup (n:nat)(hp:list ((LowLang.tm*Ty)*(nat*nat))):(option ((LowLang.tm*Ty)*(nat*nat))):=
match hp , n with
| nil , _ =>None
| h::t , 0 => Some h
| h::t , S n' =>heap_lookup n' t
end.
(*extract the result of [heap_lookup]*)
Definition efst (p:option((LowLang.tm*Ty)*(nat*nat))) : option (LowLang.tm) :=
match p with
| None => None
| Some ((t,T),N) => Some t
end.
(*the following block is regarding the "replace" function w.r.t. marked heap*)
(*#########################*)
(**
note that similar to the "lookup" functions defines in the current block,there are
two ways to replace a value on the marked heap,
a. we can either query for the first element of the mark attached to the value like
[return_smallest_match] to locate the value and then replace it
b. we can also firstly get the second value of the mark and then search for the value
on the indicated location directly essentially ignoring the marks on the heap
*)
(**
"a. marked_heap_replace"
*)
Fixpoint marked_heap_replace n (x:(LowLang.tm)*Ty) (hp:list ((LowLang.tm*Ty)*(nat*nat))): list ((LowLang.tm*Ty)*(nat*nat)) :=
match hp with
| h :: t => match h with
| (fst,snd) => match snd with
| (n1,n2) =>if beq_nat n1 n
then (x,snd)::t
else h::(marked_heap_replace n x t)
end
end
| nil => nil
end.
(*some examples*)
Example test_marked_heap_replace_1:
marked_heap_replace 3 (LowLang.tcon 1,an int L) (((LowLang.tcon 0,an int L),(0,0)):: ((LowLang.tcon 2,an int L),(3,1)) :: ((LowLang.tunit,an unit L),(4,2)) :: nil)
= (((LowLang.tcon 0,an int L),(0,0)) :: ((LowLang.tcon 1,an int L),(3,1)) :: ((LowLang.tunit,an unit L),(4,2)) :: nil).
Proof. simpl. reflexivity.
Qed.
Example test_marked_heap_replace_2:
marked_heap_replace 2 (LowLang.tcon 2,an int L) (((LowLang.tcon 0,an int L),(3,0))::((LowLang.tcon 1,an int L),(6,1))::nil)
= (((LowLang.tcon 0,an int L),(3,0))::((LowLang.tcon 1,an int L),(6,1))::nil).
Proof. simpl. reflexivity.
Qed.
(*########*)
(*backhere*)
(*########*)
(*some lemmas related to [marked_heap_replace]*)
Lemma marked_heap_replace_same:forall hp n n1 n2 p,
n < n1 ->
marked_heap_replace n p (marked_heap(marked_heap' hp n1)n2)
=(marked_heap(marked_heap' hp n1)n2).
Proof. intros hp. induction hp.
Case ("nil"). intros. reflexivity.
Case ("h::t"). intros. destruct a. simpl. destruct n1. destruct n.
apply LowLang.lt_same_F in H0. inversion H0. inversion H0.
simpl. remember (SecLang.label t) as BB. destruct BB. destruct n2.
simpl. destruct n. specialize (IHhp 0 (S (S n1)) 0 p). apply le_S in H0.
apply IHhp in H0. rewrite->H0. reflexivity. remember (beq_nat n1 n) as CC. destruct CC.
apply beq_nat_eq in HeqCC. subst. apply LowLang.lt_same_F in H0. inversion H0.
specialize (IHhp (S n) (S (S n1)) 0 p). apply le_S in H0. apply IHhp in H0. rewrite->H0.
reflexivity. simpl. destruct n. specialize (IHhp 0 (S (S n1)) (S n2) p). apply le_S in H0.
apply IHhp in H0. rewrite->H0. reflexivity. remember (beq_nat n1 n) as CC. destruct CC.
apply beq_nat_eq in HeqCC. rewrite->HeqCC in H0. apply LowLang.lt_same_F in H0. inversion H0.
specialize (IHhp (S n) (S (S n1)) (S n2) p). apply le_S in H0. apply IHhp in H0. rewrite->H0.
reflexivity. specialize (IHhp n (S (S n1)) (S n2) p). apply le_S in H0. apply IHhp in H0.
rewrite->H0. reflexivity.
Qed.
(**
"b. heap_replace"
*)
Fixpoint heap_replace n (x:(LowLang.tm)*Ty) (hp:list ((LowLang.tm*Ty)*(nat*nat))): list ((LowLang.tm*Ty)*(nat*nat)) :=
match hp , n with
| nil , _ =>nil
| h::t , 0 => match h with
|(fst,snd)=>(x,snd)::t
end
| h::t , S n' =>h :: (heap_replace n' x t)
end.
(*some examples*)
Example test_heap_replace_1:
heap_replace 2 (LowLang.tcon 1,an int L)(((LowLang.tcon 0,an int L),(7,0))::((LowLang.tcon 2,an int L),(8,1))::((LowLang.tcon 3,an int L),(9,2))::nil)
= (((LowLang.tcon 0,an int L),(7,0))::((LowLang.tcon 2,an int L),(8,1))::((LowLang.tcon 1,an int L),(9,2))::nil).
Proof. simpl. reflexivity.
Qed.
Example test_heap_replace_2:
heap_replace 3 (LowLang.tcon 1,an int L)(((LowLang.tcon 0,an int L),(3,0))::((LowLang.tcon 2,an int L),(5,1))::((LowLang.tcon 3,an int L),(6,2))::nil)
= (((LowLang.tcon 0,an int L),(3,0))::((LowLang.tcon 2,an int L),(5,1))::((LowLang.tcon 3,an int L),(6,2))::nil).
Proof. simpl. reflexivity.
Qed.
(*#########################*)
(*marked heap well-formed*)
(**
the property [marked_heap_well_formed] states that for each term on the marked heap
,it is well_formed given some natural number corresponding to the length of the
original heap in [SecLang]
*)
(*marked_heap well_formed*)
Inductive marked_heap_well_formed : list ((LowLang.tm*Ty)*(nat*nat)) -> nat -> Prop :=
| nil_mhwf:forall n,
marked_heap_well_formed nil n
| one_mhwf:forall t0 T p t n,
marked_heap_well_formed t n ->
LowLang.well_formed t0 n ->
marked_heap_well_formed (((t0,T),p) :: t) n.
(*some lemmas regarding [marked_heap_well_formed]*)
Lemma marked_heap_well_formed_shrink:forall hp a n,
marked_heap_well_formed (a :: hp) n ->
marked_heap_well_formed hp n.
Proof. intros. inversion H0. apply H3.
Qed.
(*finally we put [marked_hp'] and [marked_hp] together to get [project_hp]*)
Definition project_hp (hp:SecLang.heap) : list ((LowLang.tm*Ty)*(nat*nat)) :=
marked_heap (marked_heap' hp 0) 0.
(*some examples*)
Example test_project_hp_1:
project_hp ((SecLang.tcon 6 L,an int L) :: (SecLang.tcon 6 H,an int H) :: (SecLang.tcon 5 L,an int L) :: nil)
= (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil).
Proof. compute. reflexivity. Qed.
(**
Note the following function decides whether or not two marked heaps have the same
marks. It will be useful later on for proving "Lemma two" in Lu's paper
*)
Fixpoint same_mark (hp1:list ((LowLang.tm*Ty)*(nat*nat)))(hp2:list ((LowLang.tm*Ty)*(nat*nat))) : bool :=
match hp1 , hp2 with
| (L1,(n1,m1)) :: t1 , (L2,(n2,m2)) :: t2 =>match beq_nat n1 n2 with
| true =>match beq_nat m1 m2 with
| true =>same_mark t1 t2
| false =>false
end
| false =>false
end
| nil , h :: t =>false
| h :: t , nil =>false
| nil , nil =>true
end.
(**
There is only one case where two marked heaps are considered to have the same marks,
a. each of their corresponding marks are the same
b. these two heaps involved have the same length
See the following examples
*)
Example test_same_mark_1:
same_mark (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 7,an int L),(2,1)) :: ((LowLang.tcon 8,an int L),(5,2)) :: nil)(((LowLang.tcon 1,an int L),(0,0)) :: ((LowLang.tcon 2,an int L),(2,1)) :: ((LowLang.tcon 3,an int L),(5,2)) :: nil)
= true.
Proof. simpl. reflexivity.
Qed.
Example test_same_mark_2:
same_mark (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 7,an int L),(2,1)) :: nil)(((LowLang.tcon 1,an int L),(0,0)) :: ((LowLang.tcon 2,an int L),(2,1)) :: ((LowLang.tcon 3,an int L),(5,2)) :: nil)
= false.
Proof. simpl. reflexivity.
Qed.
Example test_same_mark_3:
same_mark (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 7,an int L),(2,1)) :: ((LowLang.tcon 8,an int L),(5,2)) :: nil)(((LowLang.tcon 1,an int L),(0,0)) :: ((LowLang.tcon 2,an int L),(2,1)) :: nil)
= false.
Proof. simpl. reflexivity.
Qed.
(*some lemmas regarding [same_mark]*)
Lemma same_mark_length:forall hp hp',
same_mark hp hp' = true ->
length hp = length hp'.
Proof. intros hp. induction hp.
intros. destruct hp'. reflexivity. simpl in H0. inversion H0. intros. destruct hp'.
destruct a. destruct p0. simpl in H0. inversion H0. destruct a. destruct p1. destruct p.
destruct p1. simpl. simpl in H0. remember (beq_nat n n1) as BB. destruct BB. remember (beq_nat n0 n2) as CC.
destruct CC. apply IHhp in H0. rewrite->H0. reflexivity. inversion H0. inversion H0.
Qed.
Lemma same_mark_refl:forall hp,
same_mark hp hp = true.
Proof. intros. induction hp. reflexivity. destruct a. destruct p0. simpl.
rewrite<-beq_nat_refl. rewrite<-beq_nat_refl. apply IHhp.
Qed.
Lemma same_mark_sym:forall hp1 hp2,
same_mark hp1 hp2 = true ->
same_mark hp2 hp1 = true.
Proof. intros. generalize dependent hp2. induction hp1.
intros. destruct hp2. reflexivity. simpl. destruct p. destruct p0. simpl in H0. inversion H0.
intros. destruct hp2. simpl. simpl in H0. destruct a. destruct p0. inversion H0.
simpl. destruct p. destruct p0. destruct a. destruct p1. remember (beq_nat n n1) as BB.
remember (beq_nat n0 n2) as CC. destruct BB. destruct CC. apply IHhp1. simpl in H0. rewrite->beq_nat_sym in HeqBB. rewrite->beq_nat_sym in HeqCC.
rewrite<-HeqBB in H0. rewrite<-HeqCC in H0. apply H0. simpl in H0. rewrite->beq_nat_sym in HeqBB. rewrite->beq_nat_sym in HeqCC. rewrite<-HeqBB in H0. rewrite<-HeqCC in H0.
inversion H0. simpl in H0. rewrite->beq_nat_sym in HeqBB. rewrite<-HeqBB in H0. inversion H0.
Qed.
Lemma same_mark_replace:forall hp1 hp2 hp3,
same_mark hp1 hp2 = true ->
same_mark hp1 hp3 = true ->
same_mark hp3 hp2 = true.
Proof. intros. generalize dependent hp2. generalize dependent hp3. induction hp1.
Case ("nil"). intros. destruct hp2. destruct hp3. reflexivity. simpl in H1. inversion H1. destruct hp3. simpl in H0. inversion H0.
simpl in H0. inversion H0.
Case ("h::t"). intros. destruct hp3. simpl in H1. inversion H1. destruct hp2. simpl in H0. destruct a. destruct p0. inversion H0.
destruct a. destruct p1. inversion H1. destruct hp2. simpl in H0. inversion H0. simpl. destruct p. destruct p0. destruct a. destruct p1. reflexivity.
simpl. destruct p. destruct p1. destruct p0. destruct p1. remember (beq_nat n n1) as BB. remember (beq_nat n0 n2) as CC. destruct BB. destruct CC.
destruct a. destruct p2. apply IHhp1. inversion H1. remember (beq_nat n3 n) as DD. destruct DD. remember (beq_nat n4 n0) as EE. destruct EE.
reflexivity. inversion H3. inversion H3.
inversion H0. remember (beq_nat n3 n1) as DD. destruct DD. remember (beq_nat n4 n2) as EE. destruct EE. reflexivity. inversion H3. inversion H3.
destruct a. destruct p2. simpl in H1. remember (beq_nat n3 n) as DD. destruct DD. remember (beq_nat n4 n0) as EE. destruct EE. apply beq_nat_eq in HeqEE.
simpl in H0. remember (beq_nat n3 n1) as FF. destruct FF. remember (beq_nat n4 n2) as GG. destruct GG. apply beq_nat_eq in HeqGG. rewrite->HeqEE in HeqGG. rewrite->HeqGG in HeqCC.
symmetry in HeqCC. apply beq_nat_false in HeqCC. assert (n2=n2). reflexivity. apply HeqCC in H2. inversion H2. inversion H0. inversion H0. inversion H1. inversion H1.
destruct a. destruct p2. simpl in H1. remember (beq_nat n3 n) as DD. destruct DD. apply beq_nat_eq in HeqDD. simpl in H0. remember (beq_nat n3 n1) as EE. destruct EE. apply beq_nat_eq in HeqEE.
rewrite->HeqDD in HeqEE. rewrite->HeqEE in HeqBB. symmetry in HeqBB. apply beq_nat_false in HeqBB. assert (n1=n1). reflexivity. apply HeqBB in H2. inversion H2.
inversion H0. inversion H1.
Qed.
(*#######try#########*)
Lemma same_mark_empty:forall hp n,
same_mark (marked_heap (marked_heap' hp n) n) [] = true ->
same_mark (marked_heap (marked_heap' hp (S n)) (S n)) [] = true.
Proof. intros. generalize dependent n. induction hp.
Case ("nil"). intros. simpl. reflexivity.
Case ("h::t"). intros. destruct a. simpl in H0. destruct n. simpl in H0. remember (SecLang.label t) as BB. destruct BB.
inversion H0. simpl. rewrite<-HeqBB. apply IHhp in H0. apply H0. simpl. simpl in H0. remember (SecLang.label t) as BB.
destruct BB. inversion H0. apply IHhp in H0. apply H0.
Qed.
(*###################*)
(*some lemmas regarding [project_hp]*)
(**
Recall the way how we get our marked heap,
firstly we have a heap from [SecLang] and we mark each cell on the heap according
to its location on the heap;then for each cell we calculate the number of high cells
on its left and then subtract it from its mark giving us the location of the cell
after we discard the high cells;lastly we apply [project_e] to all the terms on
the marked heap.
*)
(**
Consider the following example,
suppose we have
hp = [L(1),H(2),L(3),H(4),L(5)] and hp' = [L(1),H(7),L(3),H(8),L(5)]
according to [project_hp] we have,
project_hp hp = [ 1, 3, 5] = project_hp hp'
0->0 2->1 4->2
Now,we prefix both hp and hp' by (L(8)) and as a result we have,
project_hp hp = [ 8, 1, 3, 5] = project_hp hp'
0->0 1->1 3->2 5->3
while if we prefix by (H(8)) we get,
project_hp hp = [ 1, 3, 5] = project_hp hp'
1->0 3->1 4->2
.
Note how the marks of the extended heap depends upon the label of the new cell.
If it is [L] then the marks of the rest of the heap is equal to the original
ones added by one or if [H] the marks of the original one is increased only in
their first element.
Sppose we define the following two functions,
[add_both_mark] which add every mark on the heap by one
and [add_fst_mark] which add the first element of every mark on the heap by one
then we have,
a.
project_hp (a::hp) = (a,(0,0)) :: add_both_mark (project_hp hp)
when the label of is [L];
b.
project_hp (a::hp) = add_fst_mark (project_hp hp)
when the label of hp is [H].
In what follows we firstly define [add_both_mark] and [add_fst_mark] and then prove the above
two equalities.
*)
(*###########*)
(*add_both_mark*)
Fixpoint add_both_mark (hp:list ((LowLang.tm*Ty)*(nat*nat))) : list ((LowLang.tm*Ty)*(nat*nat)) :=
match hp with
| h :: t =>match h with
| (a , b) =>match b with
|(n1,n2) =>(a,(n1+1,n2+1)) :: (add_both_mark t)
end
end
| nil =>nil
end.
(*some example*)
Example test_add_both_mark_1:
add_both_mark (((LowLang.tcon 1,an int L),(0,0)) :: ((LowLang.tcon 3,an int L),(2,1)) :: ((LowLang.tcon 5,an int L),(4,2)) :: nil)
= (((LowLang.tcon 1,an int L),(1,1)) :: ((LowLang.tcon 3,an int L),(3,2)) :: ((LowLang.tcon 5,an int L),(5,3)) :: nil).
Proof. simpl. reflexivity. Qed.
(*some lemmas regarding [add_both_mark]*)
Lemma add_both_mark_hd:forall a n1 n2 t,
add_both_mark ((a,(n1,n2)) :: t) = (a,(n1+1,n2+1)) :: (add_both_mark t).
Proof. intros. simpl. reflexivity.
Qed.
Lemma Sn_n_plus_one:forall n,
S n = n + 1.
Proof. intros. induction n.
reflexivity. rewrite->plus_Sn_m. rewrite<-IHn.
reflexivity.
Qed.
Lemma n_minus_m_plus_one:forall n m,
m <= n ->
n - m + 1 = 1 + n - m.
Proof. intros. generalize dependent m. induction n.
Case ("nil"). intros. destruct m. reflexivity. inversion H0.
Case ("h::t"). intros. simpl. destruct m. rewrite<-Sn_n_plus_one.
reflexivity. destruct m. rewrite<-minus_n_O.
rewrite<-Sn_n_plus_one. reflexivity. apply LowLang.lt_snoc_1 in H0.
apply IHn in H0. rewrite->H0. rewrite->plus_comm. rewrite<-Sn_n_plus_one.
simpl. reflexivity.
Qed.
Lemma marked_heap_add_both_mark:forall hp n n',
n' <= n ->
add_both_mark (marked_heap (marked_heap' hp n) n')
=marked_heap (marked_heap' hp (n+1)) n'.
Proof. intros. generalize dependent n. generalize dependent n'. induction hp.
Case ("nil"). intros. simpl. reflexivity.
Case ("h::t"). intros. rewrite->marked_heap'_hd. rewrite->marked_heap'_hd.
destruct a. remember (SecLang.label t) as BB. destruct BB. simpl. rewrite<-HeqBB. simpl. specialize (IHhp n' (n+1)).
assert (n'<=n). apply H0. apply le_S in H0. rewrite->Sn_n_plus_one in H0. apply IHhp in H0. rewrite->H0.
rewrite->n_minus_m_plus_one. rewrite plus_comm. reflexivity. apply H1.
simpl. rewrite<-HeqBB. specialize (IHhp (S n') (n+1)). apply IHhp. apply SecLang.n_iff_Sn_left in H0.
rewrite<-Sn_n_plus_one. apply H0.
Qed.
Lemma marked_heap_add_both_mark_snoc:forall hp n1 n2 n3 n4 V T,
n2 <= n1 ->
add_both_mark (LowLang.snoc (marked_heap (marked_heap' hp n1)n2)((V,T),(n3,n4)))
=LowLang.snoc (marked_heap (marked_heap' hp (n1+1)) n2)((V,T),(S n3,S n4)).
Proof. intros hp. induction hp.
Case ("nil"). intros. simpl. rewrite->plus_comm. simpl. rewrite->plus_comm. simpl. reflexivity.
Case ("h::t"). intros. rewrite->marked_heap'_hd. rewrite->marked_heap'_hd.
destruct a. remember (SecLang.label t) as BB. destruct BB. simpl. rewrite<-HeqBB. simpl.
assert (n1+1-n2=1+n1-n2). rewrite->plus_comm. reflexivity. rewrite->H1. clear H1.
assert (n2<=n1). apply H0. apply n_minus_m_plus_one in H0. rewrite->H0. specialize (IHhp (n1+1) n2 n3 n4 V T).
apply le_S in H1. rewrite->plus_comm in IHhp. simpl in IHhp. apply IHhp in H1.
rewrite->plus_comm. simpl. rewrite<-H1. reflexivity.
simpl. rewrite<-HeqBB. specialize (IHhp (n1+1) (S n2) n3 n4 V T). rewrite->plus_comm in IHhp. simpl in IHhp.
apply SecLang.n_iff_Sn_left in H0. apply IHhp in H0. rewrite->plus_comm. simpl. apply H0.
Qed.
Lemma add_both_mark_same_mark':forall hp hp',
same_mark hp hp' = true ->
same_mark (add_both_mark hp)(add_both_mark hp') = true.
Proof. intros hp. induction hp.
Case ("nil"). intros. destruct hp'. simpl. reflexivity. inversion H0.
Case ("h::t"). intros. destruct a. destruct p0. destruct hp'. inversion H0.
destruct p0. destruct p1. simpl. simpl in H0. remember (beq_nat n n1) as BB.
destruct BB. apply beq_nat_eq in HeqBB. rewrite->HeqBB. rewrite<-beq_nat_refl.
remember (beq_nat n0 n2) as CC. destruct CC. apply beq_nat_eq in HeqCC. rewrite->HeqCC.
rewrite<-beq_nat_refl. apply IHhp. apply H0. inversion H0. inversion H0.
Qed.
Lemma add_both_mark_same_mark:forall hp hp',
same_mark (project_hp hp)(project_hp hp') = true ->
same_mark (add_both_mark (project_hp hp))(add_both_mark (project_hp hp')) = true.
Proof. intros. apply add_both_mark_same_mark'. apply H0.
Qed.
(*add_fst_mark*)
Fixpoint add_fst_mark (hp:list ((LowLang.tm*Ty)*(nat*nat))) : list ((LowLang.tm*Ty)*(nat*nat)) :=
match hp with
| h :: t =>match h with
| (a , b) =>match b with
|(n1,n2) =>(a,(n1+1,n2)) :: (add_fst_mark t)
end
end
| nil =>nil
end.
(*some example*)
Example test_add_fst_mark_1:
add_fst_mark (((LowLang.tcon 1,an int L),(0,0)) :: ((LowLang.tcon 3,an int L),(2,1)) :: ((LowLang.tcon 5,an int L),(4,2)) :: nil)
= (((LowLang.tcon 1,an int L),(1,0)) :: ((LowLang.tcon 3,an int L),(3,1)) :: ((LowLang.tcon 5,an int L),(5,2)) :: nil).
Proof. simpl. reflexivity. Qed.
Lemma marked_heap_add_fst_mark:forall hp n m,
m <= n ->
add_fst_mark (marked_heap (marked_heap' hp n) m)
=marked_heap (marked_heap' hp (n+1)) (m+1).
Proof. intros. generalize dependent n. generalize dependent m. induction hp.
Case ("nil"). intros. simpl. reflexivity.
Case ("h::t"). intros. destruct a. rewrite->marked_heap'_hd. rewrite->marked_heap'_hd.
remember (SecLang.label t) as BB. destruct BB. simpl. rewrite<-HeqBB. simpl. apply le_S in H0.
apply IHhp in H0. rewrite->Sn_n_plus_one in H0. assert (n+1-(m+1)=S n - S m). rewrite<-Sn_n_plus_one.
rewrite<-Sn_n_plus_one. reflexivity. rewrite->H1. simpl. rewrite->H0. reflexivity.
simpl. rewrite<-HeqBB. apply SecLang.n_iff_Sn_left in H0. apply IHhp in H0. rewrite->Sn_n_plus_one in H0.
rewrite->plus_Sn_m in H0. apply H0.
Qed.
Lemma marked_heap_add_fst_mark_snoc:forall hp n1 n2 n3 n4 V T,
n2 <= n1 ->
add_fst_mark (LowLang.snoc (marked_heap (marked_heap' hp n1)n2)((V,T),(n3,n4)))
=LowLang.snoc (marked_heap (marked_heap' hp (n1+1))(n2+1))((V,T),(S n3,n4)).
Proof. intros hp. induction hp.
Case ("nil"). intros. simpl. rewrite->plus_comm. simpl. reflexivity.
Case ("h::t"). intros. destruct a. rewrite->marked_heap'_hd. rewrite->marked_heap'_hd.
remember (SecLang.label t) as BB. destruct BB. simpl. rewrite<-HeqBB. simpl. specialize (IHhp (n1+1) n2 n3 n4 V T).
rewrite->plus_comm in IHhp. simpl in IHhp. apply le_S in H0. apply IHhp in H0. rewrite->plus_comm. assert (1+n1+1=S (n1+1)). reflexivity.
rewrite->H1. clear H1. assert (1+n1=S n1). reflexivity. rewrite->H1. clear H1. rewrite<-H0.
assert (n2+1=S n2). rewrite->plus_comm. reflexivity. rewrite->H1. clear H1. simpl. reflexivity.
specialize (IHhp (n1+1) (n2+1) n3 n4 V T). apply SecLang.n_iff_Sn_left in H0.
assert (n1+1=S n1). rewrite->plus_comm. reflexivity. rewrite<-H1 in H0. clear H1.
assert (n2+1=S n2). rewrite->plus_comm. reflexivity. rewrite<-H1 in H0. clear H1. apply IHhp in H0.
simpl. rewrite<-HeqBB. rewrite->plus_comm in H0. simpl in H0. rewrite->plus_comm in H0. simpl in H0.
rewrite->plus_comm. simpl. apply H0.
Qed.
Lemma add_fst_mark_same_mark':forall hp hp',
same_mark hp hp' = true ->
same_mark (add_fst_mark hp)(add_fst_mark hp') = true.
Proof. intros hp. induction hp.
Case ("nil"). intros. destruct hp'. simpl. reflexivity. inversion H0.
Case ("h::t"). intros. destruct hp'. destruct a. destruct p0. inversion H0.
destruct a. destruct p. destruct p1. destruct p2. simpl. simpl in H0.
remember (beq_nat n n1) as BB. destruct BB. apply beq_nat_eq in HeqBB.
rewrite->HeqBB. rewrite<-beq_nat_refl. remember (beq_nat n0 n2) as CC. destruct CC.
apply IHhp. apply H0. inversion H0. inversion H0.
Qed.
Lemma add_fst_mark_same_mark:forall hp hp',
same_mark (project_hp hp)(project_hp hp') = true ->
same_mark (add_fst_mark (project_hp hp))(add_fst_mark (project_hp hp')) = true.
Proof. intros. apply add_fst_mark_same_mark'. apply H0.
Qed.
(*minus_snd_mark*)
Fixpoint minus_snd_mark (hp:list ((LowLang.tm*Ty)*(nat*nat))) : list ((LowLang.tm*Ty)*(nat*nat)) :=
match hp with
| h :: t =>match h with
| (a , b) =>match b with
|(n1,n2) =>(a,(n1,n2-1)) :: (minus_snd_mark t)
end
end
| nil =>nil
end.
(*some example*)
Example test_minus_snd_mark_1:
minus_snd_mark (((LowLang.tcon 1,an int L),(0,0))::((LowLang.tcon 4,an int L),(3,1))::((LowLang.tcon 5,an int L),(4,2))::nil) =
(((LowLang.tcon 1,an int L),(0,0))::((LowLang.tcon 4,an int L),(3,0))::((LowLang.tcon 5,an int L),(4,1))::nil).
Proof. simpl. reflexivity.
Qed.
Lemma marked_heap_minus_snd_mark_1:forall n n',
n - (n' + 1) = n -n' -1.
Proof. intros n. induction n.
Case ("n=0"). reflexivity.
Case ("n=Sn''"). intros. destruct n'. simpl. reflexivity. simpl.
apply IHn.
Qed.
Lemma marked_heap_minus_snd_mark:forall hp n1 n2,
minus_snd_mark (marked_heap(marked_heap' hp n1) n2)
= (marked_heap(marked_heap' hp n1)(S n2)).
Proof. intro hp. induction hp.
Case ("nil"). intros. reflexivity.
Case ("h::t"). intros. destruct a. simpl. destruct n1. simpl.
remember (SecLang.label t) as BB. destruct BB.
simpl. specialize (IHhp 1 n2). rewrite->IHhp. reflexivity.
specialize (IHhp 1 (S n2)). rewrite->IHhp. reflexivity.
simpl. remember (SecLang.label t) as BB. destruct BB.
destruct n2. simpl. specialize (IHhp (S (S n1)) 0). rewrite->IHhp.
reflexivity. simpl. specialize (IHhp (S (S n1)) (S n2)). rewrite->IHhp.
SearchAbout minus. assert (S n2 = n2 + 1). rewrite->plus_comm. reflexivity.
rewrite->H0. clear H0. rewrite->marked_heap_minus_snd_mark_1. reflexivity.
specialize (IHhp (S (S n1)) (S n2)). rewrite->IHhp. reflexivity.
Qed.
Lemma minus_snd_mark_same_mark:forall hp hp',
same_mark hp hp' = true ->
same_mark (minus_snd_mark hp)(minus_snd_mark hp') = true.
Proof. intros hp. induction hp.
Case ("nil"). intros. destruct hp'. simpl. reflexivity. inversion H0.
Case ("h::t"). intros. destruct hp'. destruct a. destruct p0. inversion H0.
destruct a. destruct p. destruct p1. destruct p2. simpl. simpl in H0.
remember (beq_nat n n1) as BB. destruct BB. remember (beq_nat n0 n2) as CC. destruct CC.
apply beq_nat_eq in HeqCC. rewrite->HeqCC. rewrite<-beq_nat_refl. apply IHhp. apply H0.
inversion H0. inversion H0.
Qed.
(*Lemma add_both_mark_L*)
Lemma add_both_mark_L:forall e T hp,
SecLang.label e = L ->
project_hp ((e,T) :: hp) = ((project_e e,T),(0,0)) :: (add_both_mark (project_hp hp)).
Proof. intros. generalize dependent e. generalize dependent T. induction hp.
intros. simpl. unfold project_hp. unfold marked_heap'. unfold marked_heap. rewrite->H0. reflexivity.
intros. unfold project_hp. rewrite->marked_heap'_hd. simpl. rewrite->H0. destruct a. remember (SecLang.label t) as BB.
destruct BB. rewrite->marked_heap_L. simpl. rewrite<-HeqBB. rewrite->add_both_mark_hd. simpl. assert (0<=1). apply le_S.
apply le_n. apply marked_heap_add_both_mark with (hp:=hp) in H1. simpl in H1. rewrite->H1. reflexivity. symmetry. apply HeqBB.
simpl. rewrite<-HeqBB. assert (1<=1). apply le_n. apply marked_heap_add_both_mark with (hp:=hp) in H1.
rewrite->H1. reflexivity.
Qed.
(*#######################################################*)
Lemma same_mark_marked_heap:forall hp hp',
same_mark (project_hp hp)(project_hp hp') = true ->
same_mark (marked_heap (marked_heap' hp 1) 1)(marked_heap (marked_heap' hp' 1) 1) = true.
Proof. intros. assert (marked_heap (marked_heap' hp 1) 1 = add_fst_mark (project_hp hp)).
unfold project_hp. symmetry. apply marked_heap_add_fst_mark. apply le_n. rewrite->H1. clear H1.
assert (add_fst_mark (project_hp hp') = marked_heap (marked_heap' hp' 1) 1). unfold project_hp.
apply marked_heap_add_fst_mark. apply le_n. rewrite<-H1. clear H1.
apply add_fst_mark_same_mark. apply H0.
Qed.
(**
Lemma same_mark_marked_heap_generalize_1:forall n hp hp',
same_mark (marked_heap(marked_heap' hp 0)0)(marked_heap(marked_heap' hp' 0)0) = true ->
same_mark (marked_heap (marked_heap' hp 0) n)(marked_heap (marked_heap' hp' 0) n) = true.
Proof. intros n. induction n.
Case ("n=0"). intros. apply H0.
Case ("n=S n'"). intros. rewrite<-marked_heap_minus_snd_mark. rewrite<-marked_heap_minus_snd_mark.
apply minus_snd_mark_same_mark. apply IHn. apply H0.
Qed.
*)
Lemma same_mark_marked_heap_generalize:forall hp hp' n1 n2,
n2<=n1 ->
same_mark (marked_heap(marked_heap' hp 0)0)(marked_heap(marked_heap' hp' 0)0) = true ->
same_mark (marked_heap (marked_heap' hp n1) n2)(marked_heap (marked_heap' hp' n1) n2) = true.
Proof. intros. generalize dependent n2. generalize dependent hp. generalize dependent hp'.
induction n1.
Case ("n1=0"). intros. destruct n2. apply H1. inversion H0.
Case ("n1=S n"). intros. destruct n2. assert (0<=n1). apply SecLang.zero_n.
assert (S n1 = n1 +1). rewrite->plus_comm. reflexivity. rewrite->H3.
clear H3. assert (0<=n1). apply H2. apply marked_heap_add_both_mark with (hp:=hp)in H2.
rewrite<-H2. clear H2. apply marked_heap_add_both_mark with (hp:=hp') in H3. rewrite<-H3.
clear H3. apply IHn1 with (n2:=0)in H1. apply add_both_mark_same_mark'.
apply H1. apply SecLang.zero_n. apply SecLang.lt_snoc_1 in H0. assert (n2<=n1). apply H0. assert (n2<=n1). apply H0.
apply marked_heap_add_fst_mark with(hp:=hp)in H0. apply marked_heap_add_fst_mark with(hp:=hp')in H2.
assert (S n1 = n1 + 1). rewrite->plus_comm. reflexivity. rewrite->H4. clear H4. assert (S n2 = n2 + 1).
rewrite->plus_comm. reflexivity. rewrite->H4. clear H4. rewrite<-H0. clear H0. rewrite<-H2. clear H2.
apply IHn1 with (n2:=n2)in H1. apply add_fst_mark_same_mark'. apply H1. apply H3.
Qed.
(*########################################################*)
Lemma same_mark_Sameext:forall hp hp' a,
same_mark (project_hp hp)(project_hp hp') = true ->
same_mark (project_hp (a :: hp))(project_hp (a :: hp')) = true.
Proof. intros. destruct a. remember (SecLang.label t) as BB. destruct BB.
symmetry in HeqBB. assert (SecLang.label t = L). apply HeqBB.
apply add_both_mark_L with (T:=t0)(hp:=hp)in HeqBB. rewrite->HeqBB.
apply add_both_mark_L with (T:=t0)(hp:=hp')in H1. rewrite->H1.
simpl. apply add_both_mark_same_mark. apply H0. unfold project_hp.
simpl. rewrite<-HeqBB.
assert (add_fst_mark (project_hp hp) = marked_heap (marked_heap' hp 1) 1).
unfold project_hp. apply marked_heap_add_fst_mark. apply le_n. rewrite<-H1. clear H1.
assert (add_fst_mark (project_hp hp') = marked_heap (marked_heap' hp' 1) 1).
unfold project_hp. apply marked_heap_add_fst_mark. apply le_n. rewrite<-H1.
apply add_fst_mark_same_mark. apply H0.
Qed.
(*###########*)
Lemma project_hp_Sameext:forall hp hp' a,
project_hp hp = project_hp hp' ->
project_hp (a::hp) = project_hp (a::hp').
Proof. intros. destruct a. remember (SecLang.label t) as BB. destruct BB. unfold project_hp.
rewrite->marked_heap'_hd. rewrite->marked_heap'_hd. simpl. rewrite<-HeqBB. unfold project_hp in H0.
assert (0<=0). apply le_n. assert (0<=0). apply le_n. apply marked_heap_add_both_mark with (hp:=hp) in H1.
apply marked_heap_add_both_mark with (hp:=hp') in H2. simpl in H1. simpl in H2. rewrite<-H1. rewrite<-H2.
rewrite->H0. reflexivity. unfold project_hp. simpl. rewrite<-HeqBB. unfold project_hp in H0. assert (0<=0). apply le_n.
assert (0<=0). apply le_n. apply marked_heap_add_fst_mark with (hp:=hp) in H1. apply marked_heap_add_fst_mark with (hp:=hp') in H2.
simpl in H1. simpl in H2. rewrite<-H1. rewrite<-H2. rewrite->H0. reflexivity.
Qed.
(*the projection of a heap equals that of the heap itself*)
Lemma project_hp_Hextend:forall v hp T,
SecLang.value v ->
project_hp hp = project_hp (SecLang.snoc hp (SecLang.joinvs v H,T)).
Proof. intros. generalize dependent T. generalize dependent v. induction hp.
Case ("nil"). intros. simpl. inversion H0. subst. rewrite->SecLang.join_tcon_b. rewrite->SecLang.joins_refl.
simpl. compute. reflexivity. subst. rewrite->SecLang.join_tabs_b. rewrite->SecLang.joins_refl.
simpl. compute. reflexivity. subst. rewrite->SecLang.join_tunit_b. rewrite->SecLang.joins_refl.
simpl. compute. reflexivity. subst. rewrite->SecLang.join_tloc_b. rewrite->SecLang.joins_refl.
simpl. compute. reflexivity.
Case ("h::t"). intros. simpl. apply project_hp_Sameext. apply IHhp. apply H0.
Qed.
Lemma project_hp_Lextend:forall v hp T,
SecLang.value v ->
SecLang.label v = L ->
project_hp (SecLang.snoc hp (v,T)) = LowLang.snoc (project_hp hp) ((project_e v,T),(length hp,length (project_hp hp))).
Proof. intros. generalize dependent v. generalize dependent T. induction hp.
Case ("nil"). intros. unfold project_hp. simpl. rewrite->H1. reflexivity.
Case ("h::t"). intros. simpl. unfold project_hp. destruct a. simpl. remember (SecLang.label t) as BB. destruct BB.
simpl. assert (0<=0). apply le_n. apply marked_heap_add_both_mark with(hp:=SecLang.snoc hp (v,T))in H2.
simpl in H2. rewrite<-H2. clear H2. assert (0<=0). apply le_n.
apply marked_heap_add_both_mark_snoc with(hp:=hp)(n3:=length hp)(n4:=length (marked_heap(marked_heap' hp 1)0))(V:=project_e v)(T:=T)in H2.
simpl in H2. rewrite<-H2. clear H2. rewrite->marked_heap_mark_length with(n3:=0)(n4:=0). apply IHhp with(T:=T)in H0. unfold project_hp in H0.
rewrite<-H0. reflexivity. apply H1.
assert (0<=0). apply le_n. apply marked_heap_add_fst_mark with(hp:=SecLang.snoc hp (v,T))in H2.
simpl in H2. rewrite<-H2. clear H2. assert (0<=0). apply le_n.
apply marked_heap_add_fst_mark_snoc with(hp:=hp)(n3:=length hp)(n4:=length(marked_heap(marked_heap' hp 1)1))(V:=project_e v)(T:=T)in H2.
simpl in H2. rewrite<-H2. clear H2.
rewrite->marked_heap_mark_length with(n3:=0)(n4:=0). unfold project_hp in IHhp. apply IHhp with(T:=T)in H0. rewrite<-H0. reflexivity.
apply H1.
Qed.
(**
the projection of a heap equals that of the heap with some of its high cell
being over-written by a high value
*)
Lemma project_hp_Hoverwrite:forall n hp t T,
n < length hp ->
SecLang.value t ->
subsum_r H (SecLang.label (SecLang.efst (SecLang.heap_lookup n hp))) ->
project_hp hp = project_hp (SecLang.heap_replace n (SecLang.joinvs t H,T) hp).
Proof. intros. generalize dependent n. generalize dependent t. generalize dependent T. induction hp.
Case ("nil"). intros. simpl. destruct n. simpl. reflexivity. inversion H0.
Case ("h::t"). intros. destruct n. simpl. simpl in H2. destruct a. unfold project_hp. rewrite->marked_heap'_hd.
rewrite->marked_heap'_hd. simpl. inversion H2. subst. inversion H1. rewrite->SecLang.join_tcon_b.
rewrite->SecLang.joins_refl. simpl. reflexivity. rewrite->SecLang.join_tabs_b. rewrite->SecLang.joins_refl.
simpl. reflexivity. rewrite->SecLang.join_tunit_b. rewrite->SecLang.joins_refl. simpl. reflexivity.
rewrite->SecLang.join_tloc_b. rewrite->SecLang.joins_refl. simpl. reflexivity. simpl. apply project_hp_Sameext.
apply IHhp. apply H1. simpl in H0. apply LowLang.lt_snoc_1 in H0. apply H0. simpl in H2. apply H2.
Qed.
Lemma lt_S_n:forall n n',
S n < S n' ->
n < n'.
Proof. intros. apply LowLang.lt_snoc_1 in H0. apply H0.
Qed.
Lemma project_hp_Loverwrite:forall n hp t T,
n < length hp ->
SecLang.value t ->
SecLang.label t = L ->
SecLang.label (SecLang.efst (SecLang.heap_lookup n hp)) = L ->
same_mark (project_hp hp)(project_hp (SecLang.heap_replace n (t,T) hp)) = true.
Proof. intros. generalize dependent n. generalize dependent t. generalize dependent T.
induction hp.
Case ("nil"). intros. destruct n. simpl in H0. apply LowLang.lt_same_F in H0. inversion H0. inversion H0.
Case ("h::t"). intros. destruct n. simpl. simpl in H3. destruct a. apply add_both_mark_L with (T:=t1)(hp:=hp) in H3.
rewrite->H3. apply add_both_mark_L with (T:=T)(hp:=hp) in H2. rewrite->H2. simpl. apply same_mark_refl.
simpl. apply same_mark_Sameext. apply IHhp. apply H1. apply H2. simpl in H0.
apply lt_S_n. apply H0. simpl in H3. apply H3.
Qed.
(**
Now how about the projection of a heap versus that of the heap with some of its
low cell being over-written by
the projection of a heap equals that of the heap with some of its high cell
being over-written by a low value
Lemma project_hp_LHoverwrite:forall n hp t T,
n < length hp ->
SecLang.value t ->
subsum_r H (SecLang.label (SecLang.efst (SecLang.heap_lookup n hp))) ->
project_hp hp = project_hp (SecLang.heap_replace n (SecLang.joinvs t H,T) hp).
*)
(**
Note that with the help of [project_e] and [project_hp], the configuration in [SecLang] can be
converted to a term in [LowLang] and a marked heap with mark indicating the positions
of each cell both before and after the projection of the heap.
Now we finish up our job by further project the configuration,rewriting the locations in the term,
and then erasing all the marks on the heap.
Keep in mind that regarding the rewriting of referred location we have the following
two cases to consider,
a. high cell being over-written by high value
b. low cell being over-written by low value
This,as is discussed later,implies that our further projection w.r.t. the marked
heap simply erases the marks on the heap
*)
(**
Note regarding the further projection of the configuration of term and heap,let us
consider the following cases:
suppose our unprojected heap in [SecLang] as follows,
[3 L,4 H,5 H,6 L]
a. high cell being over-written by a low value
tassign (tloc (an int L) 2) 7 / [(3,(0->0)),(6,(3->1))]
"proj",
tassign (tloc (an int L) 1) 7 / [(3,(0->0)),(#,(2->1)),(6,(3->2))]
Note that if the type of the pointer is [L] and the location in [tloc] does not
match up with the first element of all markers,the rules for the game as follows,
firstly find the element whose first number is the lowest number which is bigger
than that in [tloc];then insert some arbitrary element together with its mark
to the heap;finally replace the location in [tloc] with the location of the inserted
cell on the heap
Note that we can actually use a much simply fix,
we can replace the low value with [tH],treating it as a high value and then
change the referred location to be the length of the heap,transforming the case
to the case where a high cell is being over-written by a high value
Note: for now this case is excluded from our consideration
b. high cell being over-written by a high value
tassign (tloc (an int H) 2) 7 / [(3,0->0),(6,3->1)]
"proj",
tassign (tloc (an int H) 2) 7 / [(3,0->0),(6,3->1)]
Recall [st_assign] that the value being written onto the heap is guarded also by
the label of the referred type which is [H] in this case. It follows that whatever
gets written onto the heap, it must have high label and therefore must not appear
in the projected heap. Therefore in the current case we need not further project
the configuration to change the location in [tloc] and the corresponding heap in case
where the number in [tloc] does not match up with all the marks
c. low cell being over-written by a low value
tassign (tloc (an int L) 3) 7 / [(3,0->0),(6,3->1)]
"proj"
tassign (tloc (an int L) 1) 7 / [(3,0->0),(6,3->1)]
Note that in case the number in [tloc] matches up with some mark in the heap,
we simply replace that number by the second number in the mark while leaving
the heap unchanged. By doing so we can then specify reduction rules in [LowLang]
which over-writes the corresponding cell on the heap.
In conclusion, the only case where both the marked heap and the location in [tloc]
need to be modified is that both the referred type of the pointer and the value being
written have low security.
*)
(*
Note we proceed as follows,
1. we specify some list functions to help us to manipulate our marked heap
so that we can insert cell in the heap then mark that cell with
the right mark and after that replace the location in [tloc] correctly
2. combine the projections together
*)
(*some useful list operations*)
(**
a. given a number and a marked heap return the location of the cell
whose first number is the smallest one among all that are bigger
than that number;if there is a match,however,the second number of the
mark of the matched cell is returned
the function relies upon the assumption that the input heap is such that
the first numbers of the marker are in ascending order from left to right
moreover the second number of the marker corresponds to the location of
that cell on the heap
*)
Fixpoint return_smallest_match (n:nat)(hp:list ((LowLang.tm*Ty)*(nat*nat))) : bool*(nat*nat) :=
match hp with
| h :: t => match h with
| (fst,snd) => match snd with
| (n1,n2) =>if beq_nat n1 n
then (false,(n,n2))
else return_smallest_match n t
end
end
| nil => (true,(n,n))
end.
(*some examples*)
Example test_return_smallest_match_1:
return_smallest_match 1 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: ((LowLang.tcon 7,an int L),(3,2)) :: nil)
= (true,(1,1)).
Proof. simpl. reflexivity. Qed.
(**
Note in [test_return_smallest_match_1],no match and the position of the cell the
first number of whose marker is bigger is one,hence returning [(true,1)]
*)
Example test_return_smallest_match_2:
return_smallest_match 2 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
= (false,(2,1)).
Proof. simpl. reflexivity. Qed.
(**
Note in [test_return_smallest_match_2], a match is obtained and the second number
of the marker is returned
*)
Example test_return_smallest_match_3:
return_smallest_match 100 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
= (true,(100,100)).
Proof. simpl. reflexivity. Qed.
(*some lemmas regarding [return_smallest_match]*)
Lemma return_smallest_match_true'':forall n n',
beq_nat n (n' + (S n)) = false.
Proof. intros. generalize dependent n'. induction n.
intros. rewrite->plus_comm. simpl. reflexivity. intros.
rewrite<-plus_n_Sm. simpl. apply IHn.
Qed.
Lemma return_smallest_match_true':forall hp n1 n2,
return_smallest_match ((length hp)+n1)(marked_heap(marked_heap' hp n1)n2)
=(true,(length hp + n1,length hp + n1)).
Proof. intros hp. induction hp.
Case ("nil"). intros. simpl. reflexivity.
Case ("h::t"). intros. destruct a. simpl. destruct n1. simpl. remember (SecLang.label t) as BB.
destruct BB. simpl. specialize (IHhp 1 n2). rewrite->plus_comm in IHhp. simpl in IHhp.
rewrite->plus_comm. simpl. apply IHhp. specialize (IHhp 1 (S n2)). rewrite->plus_comm in IHhp.
simpl in IHhp. rewrite->plus_comm. simpl. apply IHhp. simpl. remember (SecLang.label t) as BB.
destruct BB. destruct n2. simpl. rewrite->return_smallest_match_true''.
rewrite->plus_n_Sm. specialize (IHhp (S (S n1)) 0). apply IHhp. simpl. rewrite->return_smallest_match_true''.
rewrite->plus_n_Sm. specialize (IHhp (S (S n1)) (S n2)). apply IHhp. rewrite->plus_n_Sm. specialize (IHhp (S (S n1))(S n2)).
apply IHhp.
Qed.
Lemma return_smallest_match_true:forall hp,
return_smallest_match (length hp)(project_hp hp) = (true,(length hp,length hp)).
Proof. unfold project_hp. intros.
assert ((length hp) + 0 = length hp). rewrite->plus_comm. reflexivity.
rewrite<-H0. clear H0. apply return_smallest_match_true'.
Qed.
Lemma Hlabel_tH:forall t,
SecLang.label t = H ->
project_e t = LowLang.tH.
Proof. intros t. induction t.
Case ("tvar"). intros. inversion H0.
Case ("tprot"). intros. destruct s. simpl. assert (SecLang.label (SecLang.tprot L t) = SecLang.label t). reflexivity. rewrite->H1 in H0.
apply IHt. apply H0. simpl. reflexivity.
Case ("tcon"). intros. destruct s. inversion H0. simpl. reflexivity.
Case ("tabs"). intros. destruct s. inversion H0. simpl. reflexivity.
Case ("tapp"). intros. inversion H0.
Case ("tunit"). intros. destruct s. inversion H0. simpl. reflexivity.
Case ("tref"). intros. destruct s. inversion H0. simpl. reflexivity.
Case ("tderef"). intros. inversion H0.
Case ("tloc"). intros. destruct s. inversion H0. simpl. reflexivity.
Case ("tassign"). intros. inversion H0.
Qed.
Lemma return_smallest_match_Sn_n:forall n n0 n1 n2 hp,
fst (return_smallest_match (S n) (marked_heap (marked_heap' hp (S n0)) n1))
= fst (return_smallest_match n (marked_heap (marked_heap' hp n0) n2)).
Proof. intros. generalize dependent n. generalize dependent n0. generalize dependent n1. generalize dependent n2.
induction hp.
Case ("nil"). intros. reflexivity.
Case ("h::t"). intros. destruct a. simpl. remember (SecLang.label t) as BB. destruct BB. destruct n1. destruct n0. simpl.
destruct n. rewrite<-HeqBB. simpl. reflexivity. rewrite<-HeqBB. simpl. specialize (IHhp n2 0 1 (S n)). apply IHhp.
simpl. rewrite<-HeqBB. destruct n. destruct n2. simpl. specialize (IHhp 0 0 (S (S n0)) 0). apply IHhp. simpl.
specialize (IHhp (S n2) 0 (S (S n0)) 0). apply IHhp. destruct n2. simpl. remember (beq_nat n0 n) as CC. destruct CC.
reflexivity. specialize (IHhp 0 0 (S (S n0)) (S n)). apply IHhp. simpl. remember (beq_nat n0 n) as CC. destruct CC.
reflexivity. specialize (IHhp (S n2) 0 (S (S n0)) (S n)). apply IHhp. simpl. destruct n0. simpl. rewrite<-HeqBB. simpl.
destruct n. reflexivity. specialize (IHhp n2 (S n1) 1 (S n)). apply IHhp. simpl. rewrite<-HeqBB. destruct n2. simpl. destruct n.
specialize (IHhp 0 (S n1) (S (S n0)) 0). apply IHhp. remember (beq_nat n0 n) as CC. destruct CC. reflexivity. specialize (IHhp 0 (S n1) (S (S n0)) (S n)). apply IHhp.
simpl. destruct n. specialize (IHhp (S n2) (S n1) (S (S n0)) 0). apply IHhp. remember (beq_nat n0 n) as CC. destruct CC. reflexivity. specialize (IHhp (S n2) (S n1) (S (S n0)) (S n)). apply IHhp.
destruct n0. simpl. rewrite<-HeqBB. specialize (IHhp (S n2) (S n1) 1 n). apply IHhp. simpl. rewrite<-HeqBB. specialize (IHhp (S n2) (S n1) (S (S n0)) n). apply IHhp.
Qed.
Lemma return_smallest_match_Sn_Sn:forall n n0 n1 n2 hp,
fst (return_smallest_match (S n) (marked_heap (marked_heap' hp (S n0))(S n1)))
= fst (return_smallest_match n (marked_heap (marked_heap' hp n0) n2)).
Proof. intros. generalize dependent n. generalize dependent n0. generalize dependent n1. generalize dependent n2.
induction hp.
Case ("nil"). intros. reflexivity.
Case ("h::t"). intros. destruct a. simpl. remember (SecLang.label t) as BB. destruct BB. destruct n0. simpl. destruct n.
rewrite<-HeqBB. simpl. reflexivity. rewrite<-HeqBB. simpl. specialize (IHhp n2 n1 1 (S n)). apply IHhp.
simpl. rewrite<-HeqBB. destruct n. destruct n2. simpl. specialize (IHhp 0 n1 (S (S n0)) 0). apply IHhp. simpl.
specialize (IHhp (S n2) n1 (S (S n0)) 0). apply IHhp. destruct n2. simpl. remember (beq_nat n0 n) as CC. destruct CC.
destruct n1. reflexivity. reflexivity.
specialize (IHhp 0 n1 (S (S n0)) (S n)). apply IHhp. simpl. remember (beq_nat n0 n) as CC. destruct CC. destruct n1. reflexivity.
reflexivity. specialize (IHhp (S n2) n1 (S (S n0)) (S n)). apply IHhp. destruct n0. simpl. rewrite<-HeqBB. simpl.
specialize (IHhp (S n2) (S n1) 1 n). apply IHhp. simpl. rewrite<-HeqBB. specialize (IHhp (S n2)(S n1)(S (S n0)) n). apply IHhp.
Qed.
Lemma return_smallest_match_snd_Sn_Sn:forall n n0 n1 hp,
fst (return_smallest_match n (marked_heap (marked_heap' hp n0) n1)) = false ->
snd(snd(return_smallest_match (S n) (marked_heap (marked_heap' hp (S n0))(S n1))))
=snd(snd(return_smallest_match n (marked_heap (marked_heap' hp n0) n1))).
Proof. intros. generalize dependent n. generalize dependent n0. generalize dependent n1.
induction hp.
Case ("nil"). intros. simpl in H0. inversion H0.
Case ("h::t"). intros. destruct a. simpl. remember (SecLang.label t) as BB. destruct BB.
destruct n0. simpl. rewrite<-HeqBB. destruct n. simpl. reflexivity. simpl.
apply IHhp. simpl in H0. rewrite<-HeqBB in H0. simpl in H0. apply H0.
simpl. rewrite<-HeqBB. destruct n1. destruct n. apply IHhp. simpl in H0. rewrite<-HeqBB in H0.
simpl in H0. apply H0. remember (beq_nat n0 n) as CC. destruct CC. simpl. rewrite<-HeqCC. simpl.
reflexivity. simpl. rewrite<-HeqCC. apply IHhp. simpl in H0. rewrite<-HeqBB in H0. simpl in H0.
rewrite<-HeqCC in H0. apply H0. destruct n. simpl. apply IHhp. simpl in H0. rewrite<-HeqBB in H0.
apply H0. remember (beq_nat n0 n) as CC. destruct CC. simpl. rewrite<-HeqCC. simpl. reflexivity.
simpl. rewrite<-HeqCC. apply IHhp. simpl in H0. rewrite<-H0. rewrite<-HeqBB. simpl. rewrite<-HeqCC.
reflexivity. destruct n0. simpl. rewrite<-HeqBB. apply IHhp. simpl in H0. rewrite<-HeqBB in H0.
apply H0. simpl. rewrite<-HeqBB. apply IHhp. simpl in H0. rewrite<-HeqBB in H0. apply H0.
Qed.
Lemma return_smallest_match_snd_Sn_n:forall hp n n0 n1,
n1 <= n0 ->
snd (snd (return_smallest_match (S n) (marked_heap (marked_heap' hp (S n0)) n1)))
=S (snd (snd (return_smallest_match n (marked_heap (marked_heap' hp n0) n1)))).
Proof. intros hp. induction hp.
Case ("nil"). intros. reflexivity.
Case ("h::t"). intros. destruct a. simpl. remember (SecLang.label t) as BB. destruct BB.
destruct n1. destruct n0. simpl. rewrite<-HeqBB. simpl. destruct n. reflexivity.
specialize (IHhp (S n) 1 0). apply IHhp. apply le_S. apply le_n. simpl. rewrite<-HeqBB. simpl. destruct n.
specialize (IHhp 0 (S (S n0)) 0). apply IHhp. apply le_S. apply H0. remember (beq_nat n0 n) as CC. destruct CC.
reflexivity. specialize (IHhp (S n) (S (S n0)) 0). apply IHhp. apply le_S. apply H0. simpl.
destruct n0. simpl. rewrite<-HeqBB. simpl. destruct n. inversion H0. specialize (IHhp (S n) 1 (S n1)). apply IHhp. inversion H0.
simpl. rewrite<-HeqBB. simpl. destruct n. specialize (IHhp 0 (S (S n0)) (S n1)). apply IHhp. apply le_S. apply H0.
remember (beq_nat n0 n) as CC. destruct CC. destruct n1. rewrite<-minus_n_O. reflexivity.
simpl. rewrite->minus_Sn_m. reflexivity. apply LowLang.lt_same_F'. apply H0.
specialize (IHhp (S n) (S (S n0)) (S n1)). apply IHhp. apply le_S. apply H0. destruct n0. simpl. rewrite<-HeqBB.
specialize (IHhp n 1 (S n1)). apply IHhp. apply SecLang.n_iff_Sn_left in H0. apply H0.
simpl. rewrite<-HeqBB. specialize (IHhp n (S (S n0)) (S n1)). apply IHhp. apply SecLang.n_iff_Sn_left in H0. apply H0.
Qed.
Lemma n_le_minus_n':forall n n',
n - n' <= n.
Proof. intros. generalize dependent n'. induction n.
Case ("nil"). intros. simpl. apply le_n.
Case ("h::t"). intros. destruct n'. simpl. apply le_n. simpl. apply le_S.
apply IHn.
Qed.
Lemma return_smallest_match_fst_snd':forall n n1 n2 hp,
snd(snd(return_smallest_match n (marked_heap(marked_heap' hp n1)n2))) <= n.
Proof. intros. generalize dependent n. generalize dependent n1. generalize dependent n2.
induction hp.
Case ("nil"). intros. simpl. apply le_n.
Case ("h::t"). intros. destruct a. simpl. destruct n1. simpl. remember (SecLang.label t) as BB.
destruct BB. simpl. destruct n. simpl. apply le_n. specialize (IHhp n2 1 (S n)).
apply IHhp. specialize (IHhp (S n2) 1 n). apply IHhp. simpl. remember (SecLang.label t) as BB.
destruct BB. destruct n2. simpl. destruct n. specialize (IHhp 0 (S (S n1)) 0). apply IHhp.
remember (beq_nat n1 n) as CC. destruct CC. simpl. apply beq_nat_eq in HeqCC.
subst. apply le_n. specialize (IHhp 0 (S (S n1)) (S n)). apply IHhp. simpl. destruct n.
specialize (IHhp (S n2)(S (S n1)) 0). apply IHhp. remember (beq_nat n1 n) as CC. destruct CC.
simpl. apply beq_nat_eq in HeqCC. subst. apply le_S. apply n_le_minus_n'.
specialize (IHhp (S n2) (S (S n1)) (S n)). apply IHhp. specialize (IHhp (S n2)(S (S n1)) n). apply IHhp.
Qed.
Lemma return_smallest_match_fst_snd:forall n hp,
snd(snd(return_smallest_match n (project_hp hp))) <= n.
Proof. unfold project_hp. intros. apply return_smallest_match_fst_snd'.
Qed.
Lemma project_hp_le_length:forall hp,
length (project_hp hp) <= length hp.
Proof. intros hp. induction hp.
Case ("nil"). simpl. apply le_n.
Case ("h::t"). unfold project_hp. destruct a. simpl. remember (SecLang.label t) as BB.
destruct BB. simpl. apply SecLang.n_iff_Sn_left. rewrite->marked_heap_mark_length with (n3:=0)(n4:=0).
apply IHhp. apply le_S. rewrite->marked_heap_mark_length with (n3:=0)(n4:=0).
apply IHhp.
Qed.
Lemma return_smallest_match_project_e_true:forall n hp,
n < length hp ->
fst(return_smallest_match n (project_hp hp)) = true ->
project_e (SecLang.efst (SecLang.heap_lookup n hp)) = LowLang.tH.
Proof. intros. generalize dependent n. induction hp.
Case ("nil"). intros. simpl in H0. destruct n. apply LowLang.lt_same_F in H0. inversion H0.
inversion H0.
Case ("h::t"). intros. destruct n. destruct a. simpl. unfold project_hp in H1. simpl in H1. remember (SecLang.label t) as BB. destruct BB.
simpl in H1. inversion H1. apply Hlabel_tH. symmetry. apply HeqBB. simpl. apply IHhp. simpl in H0. apply lt_S_n in H0. apply H0.
unfold project_hp. unfold project_hp in H1. destruct a. simpl in H1. remember (SecLang.label t) as BB. destruct BB. simpl in H1.
assert (fst (return_smallest_match (S n)(marked_heap (marked_heap' hp 1) 0)) = fst (return_smallest_match n (marked_heap (marked_heap' hp 0) 0))).
apply return_smallest_match_Sn_n. rewrite<-H2. apply H1.
assert (fst (return_smallest_match (S n)(marked_heap (marked_heap' hp 1) 1)) = fst (return_smallest_match n (marked_heap (marked_heap' hp 0) 0))).
apply return_smallest_match_Sn_n. rewrite<-H2. apply H1.
Qed.
(*###################*)
Lemma return_smallest_match_hit'':forall n m,
ble_nat n m = ble_nat (S n)(S m).
Proof. intros n. induction n. intros. simpl. reflexivity.
intros. simpl. destruct m. reflexivity. reflexivity.
Qed.
Lemma return_smallest_match_hit':forall n,
ble_nat (S n) n = false.
Proof. intros. induction n. simpl. reflexivity. simpl. destruct n. reflexivity.
rewrite->return_smallest_match_hit''. apply IHn.
Qed.
(*####################*)
Lemma return_true_marked_heap:forall hp n n1 n2,
n < n1 ->
true = fst (return_smallest_match n (marked_heap (marked_heap' hp n1) n2)).
Proof. intros hp. induction hp.
Case ("nil"). intros. simpl. reflexivity.
Case ("h::t"). intros. destruct n. destruct a. simpl. destruct n1. apply LowLang.lt_same_F in H0.
inversion H0. simpl. destruct n2.
remember (SecLang.label t) as BB. destruct BB. simpl. apply IHhp. apply le_S in H0.
apply H0. apply IHhp. apply le_S in H0. apply H0.
remember (SecLang.label t) as BB. destruct BB. simpl. apply IHhp. apply le_S in H0. apply H0.
apply IHhp. apply le_S in H0. apply H0. destruct a. simpl. destruct n1. inversion H0. simpl.
destruct n2.
remember (SecLang.label t) as BB. destruct BB. simpl. assert (n<>n1). intros contra. rewrite->contra in H0.
apply LowLang.lt_same_F in H0. inversion H0. apply not_eq_beq_false in H1. rewrite->beq_nat_sym in H1. rewrite->H1.
apply IHhp. apply le_S in H0. apply H0. apply IHhp. apply le_S in H0. apply H0.
remember (SecLang.label t) as BB. destruct BB. simpl.
assert (n<>n1). intros contra. rewrite->contra in H0.
apply LowLang.lt_same_F in H0. inversion H0. apply not_eq_beq_false in H1. rewrite->beq_nat_sym in H1. rewrite->H1.
apply IHhp. apply le_S in H0. apply H0. apply IHhp. apply le_S in H0. apply H0.
Qed.
Lemma return_smallest_match_hit:forall n n' L hp,
return_smallest_match n ((L,(n,n')) :: hp) = (false,(n,n')).
Proof. intros. simpl. destruct n. reflexivity. rewrite<-beq_nat_refl.
reflexivity.
Qed.
Lemma return_smallest_match_hit_snoc':forall n n1 n2 L hp,
return_smallest_match ((length hp)+n1) (LowLang.snoc (marked_heap(marked_heap' hp n1)n2) (L,((length hp)+n1,n))) =(false,((length hp)+n1,n)).
Proof. intros. generalize dependent n. generalize dependent n1. generalize dependent n2. generalize dependent L0.
induction hp.
Case ("nil"). intros. simpl. rewrite<-beq_nat_refl. reflexivity.
Case ("h::t"). intros. destruct a. simpl. destruct n1. simpl. remember (SecLang.label t) as BB. destruct BB.
simpl. rewrite->plus_comm. simpl. specialize (IHhp L0 n2 1 n). rewrite->plus_comm in IHhp. simpl in IHhp.
apply IHhp. rewrite->plus_comm. simpl. specialize (IHhp L0 (S n2) 1 n). rewrite->plus_comm in IHhp. simpl in IHhp.
apply IHhp. simpl. remember (SecLang.label t) as BB. destruct BB. destruct n2. simpl. rewrite->return_smallest_match_true''.
rewrite->plus_n_Sm. specialize (IHhp L0 0 (S (S n1)) n). apply IHhp. simpl. rewrite->return_smallest_match_true''.
rewrite->plus_n_Sm. specialize (IHhp L0 (S n2)(S (S n1)) n). apply IHhp. rewrite->plus_n_Sm. specialize (IHhp L0 (S n2)(S (S n1)) n).
apply IHhp.
Qed.
Lemma return_smallest_match_hit_snoc:forall n L hp,
return_smallest_match (length hp)(LowLang.snoc (project_hp hp)(L,(length hp,n)))
=(false,(length hp,n)).
Proof. intros. unfold project_hp. assert (length hp = (length hp) + 0). rewrite->plus_comm. reflexivity.
rewrite->H0. clear H0. apply return_smallest_match_hit_snoc'.
Qed.
Lemma return_smallest_match_project_hp_hit:forall n hp,
n < length hp ->
SecLang.label (SecLang.efst (SecLang.heap_lookup n hp)) = L ->
fst (return_smallest_match n (project_hp hp)) = false.
Proof. intros. generalize dependent n. induction hp.
Case ("nil"). intros. destruct n. simpl in H0. apply LowLang.lt_same_F in H0. inversion H0.
simpl in H0. inversion H0.
Case ("h::t"). intros. destruct a. unfold project_hp. simpl. remember (SecLang.label t) as BB.
destruct BB. destruct n. simpl. reflexivity. simpl.
rewrite->return_smallest_match_Sn_n with (n2:=0). apply IHhp.
simpl in H0. apply lt_S_n in H0. apply H0. simpl in H1. apply H1.
destruct n. simpl in H1. rewrite<-HeqBB in H1. inversion H1.
rewrite->return_smallest_match_Sn_n with (n2:=0). apply IHhp.
simpl in H0. apply lt_S_n in H0. apply H0. simpl in H1. apply H1.
Qed.
Lemma return_smallest_match_project_hp_not_hit:forall n hp,
n < length hp ->
SecLang.label (SecLang.efst (SecLang.heap_lookup n hp)) = H ->
fst (return_smallest_match n (project_hp hp)) = true.
Proof. intros. generalize dependent n. induction hp.
Case ("nil"). intros. destruct n. simpl in H0. apply LowLang.lt_same_F in H0. inversion H0.
simpl in H0. inversion H0.
Case ("h::t"). intros. destruct a. unfold project_hp. simpl. remember (SecLang.label t) as BB.
destruct BB. simpl. destruct n. simpl in H1. rewrite<-HeqBB in H1. inversion H1.
rewrite->return_smallest_match_Sn_n with (n2:=0). apply IHhp.
simpl in H0. apply lt_S_n in H0. apply H0. simpl in H1. apply H1.
destruct n. assert (0<1). apply le_n. apply return_true_marked_heap with(hp:=hp)(n2:=1)in H2.
symmetry. apply H2.
rewrite->return_smallest_match_Sn_Sn with (n2:=0). apply IHhp.
simpl in H0. apply lt_S_n in H0. apply H0. simpl in H1. apply H1.
Qed.
Lemma return_smallest_match_F_length:forall n hp,
fst (return_smallest_match n (project_hp hp)) = false ->
n < length hp.
Proof. intros. generalize dependent n. induction hp.
Case ("nil"). intros. simpl in H0. inversion H0.
Case ("h::t"). intros. destruct a. unfold project_hp in H0. simpl in H0. remember (SecLang.label t) as BB.
destruct BB. destruct n. simpl. apply SecLang.n_iff_Sn_left. apply SecLang.zero_n.
simpl in H0. rewrite->return_smallest_match_Sn_n with(n2:=0)in H0. apply IHhp in H0.
simpl. apply SecLang.n_iff_Sn_left. apply H0. destruct n. simpl. apply SecLang.n_iff_Sn_left.
apply SecLang.zero_n. rewrite->return_smallest_match_Sn_Sn with(n2:=0) in H0. apply IHhp in H0.
simpl. apply SecLang.n_iff_Sn_left. apply H0.
Qed.
Lemma return_smallest_match_not_hit:forall n1 n2 n3 L hp,
n1 <> n2 ->
return_smallest_match n1 ((L,(n2,n3)) :: hp) = return_smallest_match n1 hp.
Proof. intros. remember (beq_nat n1 n2) as BB. destruct BB. apply beq_nat_eq in HeqBB.
rewrite->HeqBB in H0. apply LowLang.not_equal_nat in H0. inversion H0. simpl. rewrite->beq_nat_sym.
rewrite<-HeqBB. reflexivity.
Qed.
Lemma return_smallest_match_extend:forall n hp hp' a,
return_smallest_match n hp = return_smallest_match n hp' ->
return_smallest_match n (a :: hp) = return_smallest_match n (a :: hp').
Proof. intros. destruct a. destruct p0. remember (beq_nat n n0) as BB.
destruct BB. simpl. rewrite->beq_nat_sym. rewrite<-HeqBB. reflexivity.
simpl. rewrite->beq_nat_sym. rewrite<-HeqBB. apply H0.
Qed.
Lemma return_smallest_match_not_hit_snoc:forall n1 n2 n3 L hp,
n1 <> n2 ->
return_smallest_match n1 (LowLang.snoc hp (L,(n2,n3))) = return_smallest_match n1 hp.
Proof. intros. generalize dependent n1. generalize dependent n2. generalize dependent n3.
generalize dependent L0. induction hp.
intros. simpl. remember (beq_nat n2 n1) as BB. destruct BB. apply beq_nat_eq in HeqBB.
rewrite->HeqBB in H0. apply LowLang.not_equal_nat in H0. inversion H0. reflexivity.
intros. assert (LowLang.snoc (a :: hp)(L0,(n2,n3)) = a :: (LowLang.snoc hp (L0,(n2,n3)))). reflexivity.
rewrite->H1. apply return_smallest_match_extend. apply IHhp. apply H0.
Qed.
Lemma return_smallest_match_miss_one':forall n,
ble_nat n n = true.
Proof. intros. induction n. reflexivity. rewrite<-return_smallest_match_hit''. apply IHn.
Qed.
Lemma not_equal_le_S':forall n1 n2,
(S n1) <> (S n2) ->
n1 <> n2.
Proof. intros n1. destruct n1. intros. destruct n2. assert (1=1). reflexivity. apply H0 in H1. inversion H1.
intros contra. inversion contra. intros. destruct n2. intros contra. inversion contra. intros contra.
assert (S (S n1) = S (S n2)). rewrite->contra. reflexivity. apply H0 in H1. inversion H1.
Qed.
Lemma not_equal_le_S:forall n1 n2,
n1 <> n2 ->
(ble_nat (S n1) n2 = true) \/ (ble_nat (S n2) n1 = true).
Proof. intros n1. induction n1. intros. destruct n2. assert (0=0). reflexivity. apply H0 in H1.
inversion H1. left. simpl. reflexivity. intros. destruct n2. right. simpl. reflexivity.
apply not_equal_le_S' in H0. apply IHn1 in H0. inversion H0. left. rewrite<-return_smallest_match_hit''.
apply H1. right. rewrite<-return_smallest_match_hit''. apply H1.
Qed.
Lemma return_smallest_match_miss_one'':forall n1 n2,
false = ble_nat (S n1) n2 ->
false = ble_nat (S n2) n1 ->
n1 = n2.
Proof. intros. remember (beq_nat n1 n2) as BB. destruct BB. apply beq_nat_eq in HeqBB. apply HeqBB.
symmetry in HeqBB. apply beq_nat_false in HeqBB. apply not_equal_le_S in HeqBB. inversion HeqBB. rewrite->H2 in H0.
inversion H0. rewrite->H2 in H1. inversion H1.
Qed.
Lemma return_smallest_match_miss_one:forall n n1 n2 L,
n <> n1 ->
return_smallest_match n ((L,(n1,n2)) :: nil)= (true,(n,n)).
Proof. intros. simpl. remember (beq_nat n1 n) as BB. destruct BB. apply beq_nat_eq in HeqBB. symmetry in HeqBB. apply H0 in HeqBB.
inversion HeqBB. reflexivity.
Qed.
Lemma return_smallest_match_same_mark:forall hp hp' n,
same_mark hp hp' = true ->
fst (return_smallest_match n hp) = fst (return_smallest_match n hp').
Proof. intros hp. induction hp.
intros. destruct hp'. reflexivity. simpl in H0. inversion H0.
intros. destruct hp'. destruct a. destruct p0. simpl in H0. inversion H0.
destruct a. destruct p1. destruct p. destruct p1. simpl in H0.
remember (beq_nat n0 n2) as BB. remember (beq_nat n1 n3) as CC.
destruct BB. destruct CC. apply beq_nat_eq in HeqBB. apply beq_nat_eq in HeqCC.
rewrite->HeqBB. rewrite->HeqCC. remember (beq_nat n n2) as DD. destruct DD.
apply beq_nat_eq in HeqDD. rewrite->HeqDD. rewrite->return_smallest_match_hit.
rewrite->return_smallest_match_hit. reflexivity.
symmetry in HeqDD. apply beq_nat_false in HeqDD. destruct hp. destruct hp'.
assert (n<>n2). apply HeqDD. apply return_smallest_match_miss_one with (n2:=n3)(L:=p0)in HeqDD. rewrite->HeqDD.
apply return_smallest_match_miss_one with (n2:=n3)(L:=p)in H1. rewrite->H1. reflexivity. destruct p1. destruct p2. simpl in H0.
inversion H0. destruct hp'. destruct p1. destruct p2. simpl in H0. inversion H0.
assert (n<>n2). apply HeqDD. apply return_smallest_match_not_hit with (n3:=n3)(L:=p0)(hp:=p1 :: hp) in HeqDD. rewrite->HeqDD.
apply return_smallest_match_not_hit with (n3:=n3)(L:=p)(hp:=p2 :: hp') in H1. rewrite->H1. apply IHhp. apply H0.
inversion H0. inversion H0.
Qed.
Lemma return_smallest_match_same_mark':forall hp hp' n,
same_mark hp hp' = true ->
return_smallest_match n hp = return_smallest_match n hp'.
Proof. intros hp. induction hp.
intros. destruct hp'. reflexivity. simpl in H0. inversion H0.
intros. destruct hp'. destruct a. destruct p0. simpl in H0. inversion H0.
destruct a. destruct p1. destruct p. destruct p1. simpl in H0.
remember (beq_nat n0 n2) as BB. remember (beq_nat n1 n3) as CC.
destruct BB. destruct CC. apply beq_nat_eq in HeqBB. apply beq_nat_eq in HeqCC.
rewrite->HeqBB. rewrite->HeqCC. remember (beq_nat n n2) as DD. destruct DD.
apply beq_nat_eq in HeqDD. rewrite->HeqDD. rewrite->return_smallest_match_hit.
rewrite->return_smallest_match_hit. reflexivity.
symmetry in HeqDD. apply beq_nat_false in HeqDD. destruct hp. destruct hp'.
assert (n<>n2). apply HeqDD. apply return_smallest_match_miss_one with (n2:=n3)(L:=p0)in HeqDD. rewrite->HeqDD.
apply return_smallest_match_miss_one with (n2:=n3)(L:=p)in H1. rewrite->H1. reflexivity. destruct p1. destruct p2. simpl in H0.
inversion H0. destruct hp'. destruct p1. destruct p2. simpl in H0. inversion H0.
assert (n<>n2). apply HeqDD. apply return_smallest_match_not_hit with (n3:=n3)(L:=p0)(hp:=p1 :: hp) in HeqDD. rewrite->HeqDD.
apply return_smallest_match_not_hit with (n3:=n3)(L:=p)(hp:=p2 :: hp') in H1. rewrite->H1. apply IHhp. apply H0.
inversion H0. inversion H0.
Qed.
(**
Now given a position on the heap for us to insert one extra cell we have to
specify three functions before constructing the insert function for heap,
c. a function which upon a list and a number returns the prefix of the list
till indicated by that number
d. a function which upon a list and a number returns the suffix of the list
the starting point of which is indicated by that number
b. a function which upon a list increases the second number of its markers by
1,the "right shift"
*)
(*b. a function upon a list increase the second number of its markers by one*)
Fixpoint increase_snd (hp:list ((LowLang.tm*Ty)*(nat*nat))) : list ((LowLang.tm*Ty)*(nat*nat)) :=
match hp with
| h :: t => match h with
| (fst,snd) => match snd with
| (n1,n2) => (fst,(n1,n2+1)) :: (increase_snd t)
end
end
| nil => nil
end.
(*some test*)
Example test_increase_snd_1:
increase_snd (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
= (((LowLang.tcon 6,an int L),(0,1)) :: ((LowLang.tcon 5,an int L),(2,2)) :: nil).
Proof. simpl. reflexivity. Qed.
(*c. a function upon a number and a list returns the prefix of the list till
the location indicated by that number*)
(**
To finish up,we also need to over-write the last element of the list with the following pair,
((tH,an int H),(n,n2)) where [(tH,an int H)] is chosen for [tH] is typable under all
types in [LowLang] while [n] indicates the position of the cell before projection and
[n2] indicates the current position of the cell
*)
Fixpoint prefix_hp (m:nat)(n:nat)(hp:list ((LowLang.tm*Ty)*(nat*nat))) : list ((LowLang.tm*Ty)*(nat*nat)) :=
match hp , n with
| h :: t , S n' => match t with
| h' :: t' => h :: (prefix_hp m n' t)
| nil => match h with
| (fst,snd) => match snd with
| (n1,n2) => h :: ((LowLang.tH,an int H),(m,n2+1)) :: nil
end
end
end
| h :: t , 0 => match h with
| (fst,snd) => match snd with
| (n1,n2) =>((LowLang.tH,an int H),(m,n2)) :: nil
end
end
| nil , _ => nil (*this branch is never visited*)
end.
(*some examples*)
Example test_prefix_hp_1:
prefix_hp 100 1 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: ((LowLang.tcon 7,an int L),(3,2)) :: nil)
= (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tH,an int H),(100,1)) :: nil).
Proof. simpl. reflexivity. Qed.
Example test_prefix_hp_2:
prefix_hp 100 1 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
= (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tH,an int H),(100,1)) :: nil).
Proof. simpl. reflexivity. Qed.
Example test_prefix_hp_3:
prefix_hp 100 2 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
= (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: ((LowLang.tH,an int H),(100,2)) :: nil).
Proof. simpl. reflexivity. Qed.
(**
d. a function which upon a number returns its suffix starting at the cell
indicated by that number
*)
Fixpoint suffix_hp (n:nat)(hp:list ((LowLang.tm*Ty)*(nat*nat))) : list ((LowLang.tm*Ty)*(nat*nat)) :=
match hp , n with
| h :: t , S n' => suffix_hp n' t
| h :: t , 0 => h :: t
| nil , _ => nil
end.
(*some examples*)
Example test_suffix_hp_1:
suffix_hp 1 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: ((LowLang.tcon 7,an int L),(3,2)) :: nil)
= (((LowLang.tcon 5,an int L),(2,1)) :: ((LowLang.tcon 7,an int L),(3,2)) :: nil).
Proof. simpl. reflexivity. Qed.
Example test_suffix_hp_2:
suffix_hp 0 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
= (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil).
Proof. simpl. reflexivity. Qed.
Example test_suffix_hp_3:
suffix_hp 1 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
= (((LowLang.tcon 5,an int L),(2,1)) :: nil).
Proof. simpl. reflexivity. Qed.
Example test_suffix_hp_4:
suffix_hp 2 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
= nil.
Proof. simpl. reflexivity. Qed.
(**
Now we can finally specify the insert function for the heap given a number
representing the position to be inserted and the marked heap
*)
(**
Note that the first argument of the following function is a pair where the
first component of it stands for the location on the heap before projection while
the second the location after
*)
Definition insert_hp (p:nat*nat)(hp:list ((LowLang.tm*Ty)*(nat*nat))) : list ((LowLang.tm*Ty)*(nat*nat)) :=
(prefix_hp (fst p) (snd p) hp) ++ (increase_snd (suffix_hp (snd p) hp)).
(*some examples*)
Example test_insert_hp_1:
insert_hp (1,1) (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
= (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tH,an int H),(1,1)) :: ((LowLang.tcon 5,an int L),(2,2)) :: nil).
Proof. reflexivity. Qed.
Example test_insert_hp_2:
insert_hp (6,0) (((LowLang.tcon 6,an int L),(7,0)) :: ((LowLang.tcon 5,an int L),(8,1)) :: nil)
= (((LowLang.tH,an int H),(6,0)) :: ((LowLang.tcon 6,an int L),(7,1)) :: ((LowLang.tcon 5,an int L),(8,2)) :: nil).
Proof. reflexivity. Qed.
Example test_insert_hp_3:
insert_hp (100,2) (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
= (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: ((LowLang.tH,an int H),(100,2)) :: nil).
Proof. reflexivity. Qed.
(**
About [insert_hp],upon a pair of numbers indicating the locations of a cell both before and
after the projection of the heap,it insert a "dummy cell" to some location on the
projected heap
*)
(**
Note that since the case where a low cell is being over-written by a high value is
being ruled out in [SecLang],the following discussion can be ignored.
*)
(**
Note the following function will be used by the projection function for the configuraiton
to remove some element from the marked heap in order to relieve us from dealing
with heap removal in [LowLang].
Consider the following projected configuration by [project_e] and [project_hp],
tassign (tloc (an int L) 2) tH / [L(6),L(5),L(4)]
0->0 2->1 4->2
which is a case where we try to over-write a low value with a high value.
One option for us,as discussed above, is to do projection as follows,
tassign (tloc (an int L) 1) tH / [L(6),L(5),L(4)]
0->0 2->1 4->2
where we have a match and the referred location is change to the acctual location
on the heap and that is it! If we stick to this projection method,we would have
to deal with reduction in [LowLang] where the heap before the reduction is actually
longer and we would have to deal with problems like type safety,rearranging referred
location, and so forth which is entirely unnecessary if we instead use the
following projection,
tassign (tloc (an int L) 2) tH / [L(6),L(4)]
0->0 4->1
where the low cell on the heap is removed while the referred location is changed
so that it is out of range. Actually it now is exactly the same as if we have
a case where we try to over-write a high cell with a high value.
Another example which requires the above treatment,
tassign (tloc (an int H) 2) v / [L(6),L(5),L(4)]
0->0 2->1 4->2
which is being projected as
tassign (tloc (an int H) 2) v / [L(6),L(4)]
0->0 4->1
*)
(**
In order to enable our project function so that the above method can be implemented we
need the following functions,
a. a function which decrease every second element of the marks on the heap
by 1
b. a function given a natural number and a heap returns its prefix to the cell
whose right neighbour is indicated by that number
c. a function given a natural number and a heap returns its suffix starting from
the cell whose left neighbour is indicated by that number
d. a function which puts all together to remove one cell from the marked heap
*)
(*a. a function which upon a marked heap decrease every second number of the mark by one*)
Fixpoint decrease_snd (hp:list ((LowLang.tm*Ty)*(nat*nat))) : list ((LowLang.tm*Ty)*(nat*nat)) :=
match hp with
| h :: t => match h with
| (fst,snd) => match snd with
| (n1,n2) => (fst,(n1,n2-1)) :: (decrease_snd t)
end
end
| nil => nil
end.
(*some example*)
Example test_decrease_snd_1:
decrease_snd (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
=(((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,0)) :: nil).
Proof. simpl. reflexivity. Qed.
(*b. a function which upon a heap and a number returns its prefix to that number exclusive*)
Fixpoint prefix_hp_ex (n:nat)(hp:list ((LowLang.tm*Ty)*(nat*nat))) : list ((LowLang.tm*Ty)*(nat*nat)) :=
match hp , n with
| h :: t , S n' => match n' with
| S n'' => h :: (prefix_hp_ex n' t)
| 0 => h :: nil
end
| h :: t , 0 => nil
| nil , _ => nil
end.
(*some examples*)
Example test_prefix_hp_ex_1:
prefix_hp_ex 0 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
=nil.
Proof. simpl. reflexivity. Qed.
Example test_prefix_hp_ex_2:
prefix_hp_ex 1 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
=(((LowLang.tcon 6,an int L),(0,0)) :: nil).
Proof. simpl. reflexivity. Qed.
Example test_prefix_hp_ex_3:
prefix_hp_ex 100 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
= (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil).
Proof. simpl. reflexivity. Qed.
(*c. a function which upon a heap and a number returns its suffix starting from the next number*)
Fixpoint suffix_hp_ex (n:nat)(hp:list ((LowLang.tm*Ty)*(nat*nat))) : list ((LowLang.tm*Ty)*(nat*nat)) :=
match hp , n with
| h :: t , S n' => suffix_hp_ex n' t
| h :: t , 0 => t
| nil , _ => nil
end.
(*some examples*)
Example test_suffix_hp_ex_1:
suffix_hp_ex 0 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
=(((LowLang.tcon 5,an int L),(2,1)) :: nil).
Proof. simpl. reflexivity. Qed.
Example test_suffix_hp_ex_2:
suffix_hp_ex 1 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil) = nil.
Proof. simpl. reflexivity. Qed.
Example test_suffix_hp_ex_3:
suffix_hp_ex 100 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil) = nil.
Proof. simpl. reflexivity. Qed.
(*d. a function which removes one cell from the heap*)
Definition remove_hp (n:nat) (hp:list ((LowLang.tm*Ty)*(nat*nat))) : list ((LowLang.tm*Ty)*(nat*nat)) :=
(prefix_hp_ex n hp) ++ (decrease_snd (suffix_hp_ex n hp)).
(*some examples*)
Example test_remove_hp_1:
remove_hp 0 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: ((LowLang.tcon 7,an int L),(4,2)) :: nil)
=(((LowLang.tcon 5,an int L),(2,0)) :: ((LowLang.tcon 7,an int L),(4,1)) :: nil).
Proof. compute. reflexivity. Qed.
Example test_remove_hp_2:
remove_hp 1 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: ((LowLang.tcon 7,an int L),(4,2)) :: nil)
=(((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 7,an int L),(4,1)) :: nil).
Proof. compute. reflexivity. Qed.
Example test_remove_hp_3:
remove_hp 2 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: ((LowLang.tcon 7,an int L),(4,2)) :: nil)
=(((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil).
Proof. compute. reflexivity. Qed.
Example test_remove_hp_4:
remove_hp 100 (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: ((LowLang.tcon 7,an int L),(4,2)) :: nil)
=(((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: ((LowLang.tcon 7,an int L),(4,2)) :: nil).
Proof. compute. reflexivity. Qed.
(**
Now what about the case where we want to over write a high cell referred to by
a pointer whose reference type is low with a low cell?
Should we do as suggested above that we insert a dummy cell to the heap which
then will be over-written by the low value? Not a good idear for by doing so
we introduce cell in the heap whose type is not clear and who is different from
the rest of the cells on the heap in [LowLang] which brings us complications when
we try to specify reduction relation.
Consider the following projected configuration by [project_e] and [project_hp],
tassign (tloc (an int L) 1) (7) / [L(6),L(5),L(4)]
0->0 2->1 4->2
which is a case where we over write a high cell with a low value, according to
the above suggested method we insert a dummy value onto the heap at the "right"
location and then change the referred location accordingly,
tassign (tloc (an int L) 1)(7) / [L(6), *,L(5),L(4)]
0->0 1->1 2->2 4->3
such method is thoroughly discussed in the next block of comments and so we are
not going to linger on furher.
A better approach,however,requires no insertion at all!for if we want to abstract
from all operations upon high value in the heap,then we should treat the case
of over-writing high cell with low cell the same as the case of over-writing high
cell with a high value and the projected heaps both before and after the projection
should be the same to [LowLang],thus,we should have the following projected configuration,
tassign (tloc (an int L) 3)(tH) / [L(6),L(5),L(4)]
0->0 2->1 4->2
where we simply replace the value with [tH] and replace the referred location as
the length of the heap to make it out of range which signals a high value in the
heap in [LowLang]. Then it is clear that we treat this case as the same as the case
when we try over-write a high cell with a high value.
*)
(**
Now we are ready for specifying the project function of the projected configuration
by both [project_e] and [project_hp].
Let us consider the projection sequence of the following configuration,
tapp (tassign (tloc (an int L) 2 L)(L(8)))
(tassign (tloc (an int L) 5 L)(L(9))) / [L(1),L(2),H(3),H(4),H(5),H(6),L(7)]
by[project_e]&[project_hp]
==========================>
tapp (tassign (tloc (an int L) 2)(8))
(tassign (tloc (an int L) 5)(9)) / [L(1),L(2),L(7)]
0->0 1->1 6->2
by[project_conf] \a
==========================>
tapp (tassign (tloc (an int L) {#3#})(tH))
(tassign (tloc (an int L) 5)(9)) / [L(1),L(2),L(7)]
0->0 1->1 6->2
by[project_conf] \b
==========================>
tapp (tassign (tloc (an int L) 3)(tH))
(tassign (tloc (an int L) {#3#})(tH)) / [L(1),L(2),L(7)]
0->0 1->1 6->2
by[project_conf] \c
==========================>
tapp (tassign (tloc (an int L) 3)(tH))
(tassign (tloc (an int L) 3)(tH)) / [L(1),L(2),L(7)]
Note that one important point from the above projection sequence is that
the further projection of the marked heap is simply removing the marks on the heap
. It is completely independent from the projected terms under consideration.
This characteristic will simplify our task of specifying the projection function
of the configuration.
*)
(**
the project function for configuration takes a term in [LowLang] and a marked heap
and returns a configuration in [LowLang]
*)
(*one auxiliary function to erase marks on the heap*)
Fixpoint erase_hp (hp:list (((LowLang.tm)*Ty)*(nat*nat))) : LowLang.heap := (*list ((LowLang.tm)*Ty)*)
match hp with
| h :: t => match h with
| (fst,snd) =>fst :: (erase_hp t)
end
| nil => nil
end.
(*some example*)
Example test_erase_hp_1:
erase_hp (((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
= ((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L) :: nil).
Proof. simpl. reflexivity. Qed.
(*some lemmas regarding [erase_hp]*)
Lemma erase_hp_length:forall hp,
length (erase_hp hp) = length hp.
Proof. intros. induction hp. reflexivity. simpl. destruct a. simpl.
rewrite->IHhp. reflexivity.
Qed.
Lemma erase_hp_snoc:forall Hp L0 p,
erase_hp (LowLang.snoc Hp (L0,p)) = LowLang.snoc (erase_hp Hp) L0.
Proof. intros Hp. induction Hp.
Case ("nil"). intros. simpl. reflexivity.
Case ("h::t"). intros. destruct a. simpl. specialize (IHHp L0 p). rewrite->IHHp. reflexivity.
Qed.
Fixpoint project_conf'_e (e:LowLang.tm)(hp:list (((LowLang.tm)*Ty)*(nat*nat))) : (LowLang.tm) :=
match e with
| LowLang.tvar x => LowLang.tvar x
(*Block One:projection of values in [LowLang]*)
(**
Note the general principle here is that no modification is make to the value
term for their counter-parts in [SecLang] are either not reducible
or reducible high terms.
There are,however,two value terms which need to be further projected to account for
the cases where a referred location is involved,
a. [LowLang.tabs x T t] whose body needs to be projected with the marked heap
b. [LowLang.tloc T n] whose referring location needs to be modified given a marked heap
*)
| LowLang.tcon n => LowLang.tcon n
| LowLang.tabs x T t => LowLang.tabs x T (project_conf'_e t hp)
| LowLang.tunit => LowLang.tunit
| LowLang.tloc T (Some n) =>if (fst(return_smallest_match n hp))
(*no match*) then LowLang.tloc T None
(*match*) else LowLang.tloc T (Some (snd(snd(return_smallest_match n hp))))
| LowLang.tloc T None => LowLang.tloc T None
| LowLang.tH => LowLang.tH
(*End Block One*)
(*Block Two:compound expressions with only one argument*)
| LowLang.tref T t => LowLang.tref T (project_conf'_e t hp)
| LowLang.tderef t => LowLang.tderef (project_conf'_e t hp)
(*End Block Two*)
(*Block Three:compound expressions with two arguments*)
(*tapp*)
(**
Note the idea of projection here is that we first inspect the
first argument if it is not a value we project it with the marked heap leaving
the second argument unchanged;if it is however a value we proceed to inspect the
second argument;if it is a value then we project both of them;if the second is not
a value we only project the second one
*)
(**
Note the following block might be used when upgrading and downgrading are
taken into consideration
*)
(**
|LowLang.tapp t1 t2 =>match t1 with
| LowLang.tvar y =>LowLang.tapp t1 t2
| LowLang.tcon m =>LowLang.tapp t1 (project_conf'_e t2 hp)
| LowLang.tabs y T' t' =>match t2 with
| LowLang.tvar y =>LowLang.tapp t1 t2
| LowLang.tcon o =>LowLang.tapp (project_conf'_e t1 hp)(project_conf'_e t2 hp)
| LowLang.tabs z T'' t'' =>LowLang.tapp (project_conf'_e t1 hp)(project_conf'_e t2 hp)
| LowLang.tapp t1' t2' =>LowLang.tapp t1 (project_conf'_e t2 hp)
| LowLang.tunit =>LowLang.tapp (project_conf'_e t1 hp)(project_conf'_e t2 hp)
| LowLang.tref T'' t'' =>LowLang.tapp t1 (project_conf'_e t2 hp)
| LowLang.tderef t'' =>LowLang.tapp t1 (project_conf'_e t2 hp)
| LowLang.tloc T'' N =>LowLang.tapp (project_conf'_e t1 hp)(project_conf'_e t2 hp)
| LowLang.tassign t1' t2' =>LowLang.tapp t1 (project_conf'_e t2 hp)
| LowLang.tH =>LowLang.tapp (project_conf'_e t1 hp)(project_conf'_e t2 hp)
end
| LowLang.tapp t1' t2' =>LowLang.tapp (project_conf'_e t1 hp) t2
| LowLang.tunit =>LowLang.tapp t1 (project_conf'_e t2 hp)
| LowLang.tref T' t' =>LowLang.tapp (project_conf'_e t1 hp) t2
| LowLang.tderef t' =>LowLang.tapp (project_conf'_e t1 hp) t2
| LowLang.tloc T' N =>LowLang.tapp t1 (project_conf'_e t2 hp)
| LowLang.tassign t1' t2' =>LowLang.tapp (project_conf'_e t1 hp) t2
| LowLang.tH =>LowLang.tapp t1 (project_conf'_e t2 hp)
end
(*tassign*)
|LowLang.tassign t1 t2 =>match t1 with
| LowLang.tvar y =>LowLang.tassign t1 t2
| LowLang.tcon m =>LowLang.tassign t1 (project_conf'_e t2 hp)
| LowLang.tabs y T' t' =>LowLang.tassign t1 (project_conf'_e t2 hp)
| LowLang.tapp t1' t2' =>LowLang.tassign (project_conf'_e t1 hp) t2
| LowLang.tunit =>LowLang.tassign t1 (project_conf'_e t2 hp)
| LowLang.tref T' t' =>LowLang.tassign (project_conf'_e t1 hp) t2
| LowLang.tderef t' =>LowLang.tassign (project_conf'_e t1 hp) t2
| LowLang.tloc T' N =>match t2 with
| LowLang.tvar y =>LowLang.tassign t1 t2
| LowLang.tcon o =>LowLang.tassign (project_conf'_e t1 hp)(project_conf'_e t2 hp)
| LowLang.tabs z T'' t'' =>LowLang.tassign (project_conf'_e t1 hp)(project_conf'_e t2 hp)
| LowLang.tapp t1' t2' =>LowLang.tassign t1 (project_conf'_e t2 hp)
| LowLang.tunit =>LowLang.tassign (project_conf'_e t1 hp)(project_conf'_e t2 hp)
| LowLang.tref T'' t'' =>LowLang.tassign t1 (project_conf'_e t2 hp)
| LowLang.tderef t'' =>LowLang.tassign t1 (project_conf'_e t2 hp)
| LowLang.tloc T'' N =>LowLang.tassign (project_conf'_e t1 hp)(project_conf'_e t2 hp)
| LowLang.tassign t1' t2' =>LowLang.tassign t1 (project_conf'_e t2 hp)
| LowLang.tH =>LowLang.tassign (project_conf'_e t1 hp)(project_conf'_e t2 hp)
end
| LowLang.tassign t1' t2' =>LowLang.tassign (project_conf'_e t1 hp) t2
| LowLang.tH =>LowLang.tassign t1 (project_conf'_e t2 hp)
end
*)
|LowLang.tapp t1 t2 =>LowLang.tapp (project_conf'_e t1 hp)(project_conf'_e t2 hp)
|LowLang.tassign t1 t2 =>LowLang.tassign (project_conf'_e t1 hp)(project_conf'_e t2 hp)
(*End Block Three*)
end.
(*some lemmas regarding [project_conf'_e]*)
Lemma project_conf'_e_same_mark:forall t hp hp',
same_mark hp hp' = true ->
project_conf'_e t hp = project_conf'_e t hp'.
Proof. intros t. induction t.
Case ("tvar"). intros. simpl. reflexivity.
Case ("tcon"). intros. simpl. reflexivity.
Case ("tabs"). intros. simpl. apply IHt in H0. rewrite->H0. reflexivity.
Case ("tapp"). intros. simpl. assert (same_mark hp hp' = true). apply H0. apply IHt1 in H0. apply IHt2 in H1.
rewrite->H0. rewrite->H1. reflexivity.
Case ("tunit"). intros. simpl. reflexivity.
Case ("tref"). intros. simpl. apply IHt in H0. rewrite->H0. reflexivity.
Case ("tderef"). intros. apply IHt in H0. simpl. rewrite->H0. reflexivity.
Case ("tloc"). intros. simpl. destruct o. apply return_smallest_match_same_mark' with(n:=n)in H0. rewrite->H0. reflexivity. reflexivity.
Case ("tassign"). intros. simpl. assert (same_mark hp hp' = true). apply H0. apply IHt1 in H0. apply IHt2 in H1. rewrite->H0.
rewrite->H1. reflexivity.
Case ("tH"). intros. simpl. reflexivity.
Qed.
(**
Now we are in a position to calculate the "right" heap in [LowLang] with
the following projection function. The result of it then will be used to
calculate the projection of the term in [LowLang]
*)
Fixpoint project_conf'_hp (hp1:list (((LowLang.tm)*Ty)*(nat*nat))) (hp2:list (((LowLang.tm)*Ty)*(nat*nat))): list (((LowLang.tm)*Ty)*(nat*nat)) :=
match hp1 with
|h :: t => match h with
|(l,r) => match l with
|(t0,T)=>((project_conf'_e t0 hp2,T),r) :: (project_conf'_hp t hp2)
end
end
| nil => nil
end.
(**
Note some interesting properties regarding [project_conf'_hp],
1. forall hp, length hp = length (project_conf'_hp hp)
2. forall n, nth element's mark of hp is the same as that of project_conf'_hp hp
*)
Lemma same_mark_heap_proj:forall hp hp' hp'',
same_mark (project_conf'_hp hp hp')(project_conf'_hp hp hp'') = true.
Proof. intros hp. induction hp.
intros. simpl. reflexivity.
intros. destruct a. destruct p0. simpl. destruct p. simpl. rewrite<-beq_nat_refl.
rewrite<-beq_nat_refl. apply IHhp.
Qed.
Lemma project_conf'_hp_same_mark:forall hp hp' hp'',
same_mark hp' hp'' = true ->
project_conf'_hp hp hp' = project_conf'_hp hp hp''.
Proof. intros hp. induction hp.
Case ("nil"). intros. reflexivity.
Case ("h::t"). intros. destruct a. destruct p. simpl.
assert (same_mark hp' hp'' = true).
apply H0. apply project_conf'_e_same_mark with (t:=t)in H0.
rewrite->H0. apply IHhp in H1. rewrite->H1. reflexivity.
Qed.
Lemma project_conf'_hp_length:forall hp,
length (project_conf'_hp hp hp) = length hp.
Proof. intros. induction hp. simpl. reflexivity. simpl. destruct a. destruct p. simpl.
assert (same_mark (project_conf'_hp hp hp)(project_conf'_hp hp ((t,t0,p0) :: hp)) = true).
apply same_mark_heap_proj. apply same_mark_length in H0. rewrite<-H0. rewrite->IHhp. reflexivity.
Qed.
Lemma same_mark_heap:forall hp,
same_mark hp (project_conf'_hp hp hp) = true.
Proof. intros. induction hp.
simpl. reflexivity. destruct a. destruct p0. destruct p.
assert (project_conf'_hp (((t,t0),(n,n0)) :: hp)(((t,t0),(n,n0)) :: hp) = ((project_conf'_e t (((t,t0),(n,n0)) :: hp),t0),(n,n0)) :: (project_conf'_hp hp (((t,t0),(n,n0)) :: hp))).
simpl. reflexivity. rewrite->H0. clear H0. simpl. rewrite<-beq_nat_refl. rewrite<-beq_nat_refl.
simpl. rewrite->same_mark_sym. reflexivity.
assert (same_mark (project_conf'_hp hp (((t,t0),(n,n0)) :: hp))(project_conf'_hp hp hp) = true). apply same_mark_heap_proj.
apply same_mark_sym in IHhp. apply same_mark_sym in H0. apply same_mark_replace with (hp1:=project_conf'_hp hp hp). apply IHhp. apply H0.
Qed.
Lemma return_smallest_match_same_mark_false:forall n hp,
fst (return_smallest_match n (project_hp hp)) = false ->
fst (return_smallest_match n (project_conf'_hp (project_hp hp)(project_hp hp))) = false.
Proof. intros. assert (same_mark (project_hp hp)(project_conf'_hp (project_hp hp)(project_hp hp))=true).
apply same_mark_heap. apply return_smallest_match_same_mark with (n:=n)in H1. rewrite<-H1. apply H0.
Qed.
Lemma project_conf'_e_add_one_low:forall t hp L,
SecLang.well_formed t (length hp) ->
project_conf'_e (project_e t)
(project_conf'_hp (project_hp hp)(project_hp hp))
=
project_conf'_e (project_e t)
(project_conf'_hp (LowLang.snoc (project_hp hp)(L,(length hp,length (project_hp hp))))
(LowLang.snoc (project_hp hp)(L,(length hp,length (project_hp hp))))).
Proof. intros t. induction t.
Case ("tvar"). intros. simpl. reflexivity.
Case ("tprot"). intros. destruct s. simpl. inversion H0. apply IHt with (L:=L0) in H4.
rewrite->H4. reflexivity. simpl. reflexivity.
Case ("tcon"). intros. destruct s. simpl. reflexivity. simpl. reflexivity.
Case ("tabs"). intros. destruct s. simpl. inversion H0. apply IHt with (L:=L0) in H6. rewrite->H6.
reflexivity. simpl. reflexivity.
Case ("tapp"). intros. simpl. inversion H0. apply IHt1 with (L:=L0) in H3. apply IHt2 with (L:=L0) in H5.
rewrite->H3. rewrite->H5. reflexivity.
Case ("tunit"). intros. destruct s. simpl. reflexivity. simpl. reflexivity.
Case ("tref"). intros. destruct s. simpl. inversion H0. apply IHt with (L:=L0) in H5.
rewrite->H5. reflexivity. simpl. reflexivity.
Case ("tderef"). intros. simpl. inversion H0. apply IHt with (L:=L0) in H2. rewrite->H2.
reflexivity.
Case ("tloc"). intros. destruct s. assert (project_e (SecLang.tloc t o L) = LowLang.tloc t o). reflexivity.
rewrite->H1.
assert (same_mark (project_hp hp)(project_conf'_hp (project_hp hp)(project_hp hp)) = true).
apply same_mark_heap. apply project_conf'_e_same_mark with (t:=LowLang.tloc t o)in H2. rewrite<-H2.
assert (same_mark (LowLang.snoc (project_hp hp)(L0,(length hp,length (project_hp hp))))(project_conf'_hp
(LowLang.snoc (project_hp hp) (L0, (length hp, length (project_hp hp))))
(LowLang.snoc (project_hp hp) (L0, (length hp, length (project_hp hp))))
) = true). apply same_mark_heap. apply project_conf'_e_same_mark with (t:=LowLang.tloc t o)in H3.
rewrite<-H3. inversion H0. subst. remember (beq_nat n (length hp)) as BB. destruct BB. apply beq_nat_eq in HeqBB.
rewrite->HeqBB in H8. apply LowLang.lt_same_F in H8. inversion H8. symmetry in HeqBB. apply beq_nat_false in HeqBB.
apply return_smallest_match_not_hit_snoc with(n3:=length (project_hp hp))(L:=L0)(hp:=project_hp hp) in HeqBB. simpl. rewrite->HeqBB.
remember (fst (return_smallest_match n (project_hp hp))) as CC. destruct CC. reflexivity. reflexivity. simpl. reflexivity.
Case ("tassign"). intros. simpl. inversion H0. apply IHt1 with (L:=L0) in H3. rewrite->H3. apply IHt2 with (L:=L0) in H5. rewrite->H5.
reflexivity.
Qed.
(**
Lemma try:forall hp,
SecLang.heap_well_formed hp ->
(forall l L0, l < length hp
->
project_conf'_e (project_e (SecLang.efst (SecLang.heap_lookup l hp))) (project_hp hp)
=
project_conf'_e (project_e (SecLang.efst (SecLang.heap_lookup l hp))) (LowLang.snoc (project_hp hp) (L0,(length hp,length (project_hp hp))))
).
Proof. intros.
assert (same_mark (project_hp hp)(project_conf'_hp (project_hp hp)(project_hp hp)) = true).
apply same_mark_heap. apply project_conf'_e_same_mark with(t:=project_e (SecLang.efst (SecLang.heap_lookup l hp))) in H2.
rewrite->H2.
assert (same_mark (LowLang.snoc (project_hp hp)(L0,(length hp,length (project_hp hp)))) (project_conf'_hp (LowLang.snoc (project_hp hp)(L0,(length hp,length (project_hp hp))))
(LowLang.snoc (project_hp hp)(L0,(length hp,length (project_hp hp))))) = true).
apply same_mark_heap. apply project_conf'_e_same_mark with (t:=project_e (SecLang.efst (SecLang.heap_lookup l hp)))in H3.
rewrite->H3. clear H2. clear H3. apply project_conf'_e_add_one_low. apply H0 in H1. apply H1.
Qed.
*)
Lemma marked_heap_well_formed_change_mark:forall hp n n1 n2 n3 n4,
marked_heap_well_formed (marked_heap (marked_heap' hp n1) n2) n ->
marked_heap_well_formed (marked_heap (marked_heap' hp n3) n4) n.
Proof. intros hp. induction hp.
Case ("nil"). intros. simpl. apply nil_mhwf.
Case ("h::t"). intros. destruct a. assert (marked_heap' ((t,t0) :: hp) n3 = (t,t0,(n3,n3)) :: (marked_heap' hp (S n3))). simpl. destruct n3. reflexivity. reflexivity.
rewrite->H1. clear H1.
simpl. remember (SecLang.label t) as BB. destruct BB.
apply one_mhwf. simpl in H0. destruct n1. simpl in H0. rewrite<-HeqBB in H0. inversion H0. subst.
apply IHhp with (n1:=1)(n2:=n2). apply H6. simpl in H0. rewrite<-HeqBB in H0. inversion H0. subst.
apply IHhp with (n1:=S (S n1))(n2:=n2). apply H6. simpl in H0. destruct n1. simpl in H0. rewrite<-HeqBB in H0.
inversion H0. subst. apply H7. simpl in H0. rewrite<-HeqBB in H0. destruct n2. inversion H0. apply H7. inversion H0.
apply H7. simpl in H0. destruct n1. simpl in H0. rewrite<-HeqBB in H0. apply IHhp with (n1:=1)(n2:=S n2). apply H0.
simpl in H0. rewrite<-HeqBB in H0. apply IHhp with (n1:=S (S n1))(n2:=S n2). apply H0.
Qed.
Lemma SecLow_well_formed:forall t n,
SecLang.well_formed t n ->
LowLang.well_formed (project_e t) n.
Proof. intros t. induction t.
Case ("tvar"). intros. simpl. apply LowLang.wf_tvar.
Case ("tprot"). intros. destruct s. simpl. apply IHt. inversion H0. apply H4.
simpl. apply LowLang.wf_tH.
Case ("tcon"). intros. destruct s. simpl. apply LowLang.wf_tcon. simpl. apply LowLang.wf_tH.
intros. destruct s. simpl. apply LowLang.wf_tabs. apply IHt. inversion H0. apply H6.
simpl. apply LowLang.wf_tH.
Case ("tapp"). intros. simpl. apply LowLang.wf_tapp. apply IHt1. inversion H0. apply H3. apply IHt2.
inversion H0. apply H5.
Case ("tunit"). intros. destruct s. simpl. apply LowLang.wf_tunit. simpl. apply LowLang.wf_tH.
Case ("tref"). intros. destruct s. simpl. apply LowLang.wf_tref. apply IHt. inversion H0. apply H5.
simpl. apply LowLang.wf_tH.
Case ("tderef"). intros. simpl. apply LowLang.wf_tderef. apply IHt. inversion H0. apply H2.
Case ("tloc"). intros. destruct s. simpl. destruct o. apply LowLang.wf_tloc. inversion H0. apply H5.
inversion H0. simpl. apply LowLang.wf_tH.
Case ("tassign"). intros. simpl. apply LowLang.wf_tassign. apply IHt1. inversion H0. apply H3. apply IHt2.
inversion H0. apply H5.
Qed.
Lemma heap_marked_heap_well_formed:forall hp n,
SecLang.heap_well_formed hp n ->
marked_heap_well_formed (project_hp hp) n.
Proof. intros hp. induction hp.
Case ("nil"). intros. compute. apply nil_mhwf.
Case ("h::t"). intros. destruct a. unfold project_hp. simpl. unfold project_hp in IHhp.
remember (SecLang.label t) as BB. destruct BB. apply one_mhwf. inversion H0.
apply marked_heap_well_formed_change_mark with (n1:=0)(n2:=0). apply IHhp. apply H5.
inversion H0. apply SecLow_well_formed. apply H6.
apply marked_heap_well_formed_change_mark with (n1:=0)(n2:=0). apply IHhp.
inversion H0. apply H5.
Qed.
Lemma project_conf'_e_add_one_low':forall Hp t n L0,
LowLang.well_formed t n ->
project_conf'_e t Hp = project_conf'_e t (LowLang.snoc Hp (L0,(n,length Hp))).
Proof. intros. generalize dependent Hp. generalize dependent L0. generalize dependent n.
induction t.
Case ("tvar"). intros. simpl. reflexivity.
Case ("tcon"). intros. simpl. reflexivity.
Case ("tabs"). intros. simpl. inversion H0. subst. apply IHt with (L0:=L0)(Hp:=Hp) in H5.
rewrite<-H5. reflexivity.
Case ("tapp"). intros. simpl. inversion H0. subst. apply IHt1 with (L0:=L0)(Hp:=Hp)in H3.
apply IHt2 with (L0:=L0)(Hp:=Hp) in H5. rewrite<-H3. rewrite<-H5. reflexivity.
Case ("tunit"). intros. simpl. reflexivity.
Case ("tref"). intros. simpl. inversion H0. subst. apply IHt with (L0:=L0)(Hp:=Hp)in H4. rewrite<-H4.
reflexivity.
Case ("tderef"). intros. simpl. inversion H0. subst. apply IHt with (L0:=L0)(Hp:=Hp) in H2. rewrite<-H2.
reflexivity.
Case ("tloc"). intros. destruct o. simpl. inversion H0. subst. assert (n0<>n). intros contra. subst. apply LowLang.lt_same_F in H4.
inversion H4. apply return_smallest_match_not_hit_snoc with (n3:=length Hp)(L:=L0)(hp:=Hp)in H1.
rewrite->H1. reflexivity.
inversion H0.
Case ("tassign"). intros. simpl. inversion H0. subst. apply IHt1 with(L0:=L0)(Hp:=Hp)in H3.
apply IHt2 with(L0:=L0)(Hp:=Hp) in H5. rewrite<-H3. rewrite<-H5. reflexivity.
Case ("tH"). intros. simpl. reflexivity.
Qed.
Lemma project_conf'_hp_add_one_low':forall Hp Hp' n L0,
marked_heap_well_formed Hp n ->
project_conf'_hp Hp
(LowLang.snoc Hp' ((L0,(n,length Hp'))))
=project_conf'_hp Hp Hp'.
Proof. intros. generalize dependent L0. generalize dependent Hp'.
generalize dependent n. induction Hp.
Case ("nil"). intros. simpl. reflexivity.
Case ("h::t"). intros. destruct a. destruct p. simpl. assert (marked_heap_well_formed ((t,t0,p0) :: Hp) n).
apply H0. apply marked_heap_well_formed_shrink in H0.
apply IHHp with (Hp':=Hp')(L0:=L0)in H0. rewrite->H0. inversion H1. subst.
apply project_conf'_e_add_one_low' with (Hp:=Hp')(L0:=L0) in H8. rewrite->H8.
reflexivity.
Qed.
Lemma project_conf'_hp_add_one_low:forall hp L0,
SecLang.heap_well_formed hp (length hp) ->
project_conf'_hp (project_hp hp)
(LowLang.snoc (project_hp hp) ((L0,(length hp,length (project_hp hp)))))
=project_conf'_hp (project_hp hp) (project_hp hp).
Proof. intros. apply heap_marked_heap_well_formed in H0.
apply project_conf'_hp_add_one_low' with(Hp':=project_hp hp)(L0:=L0) in H0.
rewrite->H0. reflexivity.
Qed.
Lemma project_conf'_hp_snoc:forall hp hp' t T p,
project_conf'_hp
(LowLang.snoc hp ((t ,T),p))
hp'
= LowLang.snoc
(project_conf'_hp hp hp')
((project_conf'_e t hp',T),p).
Proof. intros. generalize dependent t. generalize dependent T. generalize dependent p.
generalize dependent hp'. induction hp.
Case ("nil"). intros. simpl. reflexivity.
Case ("h::t"). intros. destruct a. destruct p0. simpl. specialize (IHhp hp' p T t).
rewrite->IHhp. reflexivity.
Qed.
(*some lemmas involving [project_conf'_hp]*)
(**
Lemma erase_hp_snoc:forall v hp rt,
LowLang.value v ->
v <> LowLang.tH ->
erase_hp (project_conf'_hp (LowLang.snoc (project_hp hp)((v,an rt L),(length hp,length (project_hp hp)))) (LowLang.snoc (project_hp hp)((v,an rt L),(length hp,length (project_hp hp)))))
=LowLang.snoc (erase_hp (project_conf'_hp (project_hp hp)(project_hp hp))) ((project_conf'_e v ,an rt L).
Proof. Admitted.
*)
(*some lemmas involves [project_conf'_hp]*)
Lemma project_conf'_hp_hp_snoc:forall hp hp' v T R,
LowLang.snoc (project_conf'_hp hp hp')((project_conf'_e v hp',T),R)
=project_conf'_hp (LowLang.snoc hp ((v,T),R)) hp'.
Proof. intros hp. induction hp.
Case ("nil"). intros. simpl. reflexivity.
Case ("h::t"). intros. destruct a. destruct p. simpl. specialize (IHhp hp' v T R).
rewrite->IHhp. reflexivity.
Qed.
Lemma return_smallest_match_snoc:forall hp v T,
LowLang.value v ->
v <> LowLang.tH ->
return_smallest_match (length hp) (project_conf'_hp ((LowLang.snoc (project_hp hp)((v,T),(length hp,length (project_hp hp)))))((LowLang.snoc (project_hp hp)((v,T),(length hp,length (project_hp hp))))))
= (false,(length hp,length (project_hp hp))).
Proof. intros. rewrite->project_conf'_hp_snoc. rewrite->project_conf'_hp_hp_snoc. assert (same_mark (LowLang.snoc (project_hp hp)
(v, T, (length hp, length (project_hp hp))))(project_conf'_hp (LowLang.snoc (project_hp hp)
(v, T, (length hp, length (project_hp hp))))(LowLang.snoc (project_hp hp)
(v, T, (length hp, length (project_hp hp)))))=true). apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=length hp)in H2.
rewrite<-H2. clear H2. rewrite->return_smallest_match_hit_snoc. reflexivity.
Qed.
(*projection of configuration*)
Definition project_conf (e:LowLang.tm)(hp:list (((LowLang.tm)*Ty)*(nat*nat))): ((LowLang.tm))*(list (((LowLang.tm)*Ty))) :=
(project_conf'_e e (project_conf'_hp hp hp),erase_hp (project_conf'_hp hp hp)).
(*some examples*)
(**
Example test_project_conf_1:
project_conf (LowLang.tassign (LowLang.tloc (an int L) (Some 1))(LowLang.tcon 7))(((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
=(LowLang.tassign (LowLang.tloc (an int L) None)(LowLang.tH),((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L) :: nil)).
Proof. compute. reflexivity. Qed.
(**
Note that as explained above,the case where we try to over-write a high cell via
a pointer whose reference type is low with a low value,we simply replace the value
with [tH] and the referred location with [None],thus treating it as
the case where a high cell is being replaced by a high value.
This is illustrated in [test_project_conf_1].
*)
*)
Example test_project_conf_2:
project_conf (LowLang.tassign (LowLang.tloc (an int L) (Some 2))(LowLang.tcon 7))(((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
=(LowLang.tassign (LowLang.tloc (an int L) (Some 1))(LowLang.tcon 7),((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L) :: nil)).
Proof. compute. reflexivity. Qed.
(**
Note in case where we want to over-write a low cell via a pointer whose reference
type is low with a low value, we need not change the heap at all. We should only
replace the referred location to the acctually location on the heap where the
cell to be over-written is located.
*)
Example test_project_conf_3:
project_conf (LowLang.tassign (LowLang.tloc (an int H) (Some 1))(LowLang.tcon 7))(((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
=(LowLang.tassign (LowLang.tloc (an int H) None)(LowLang.tcon 7),((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L) :: nil)).
Proof. compute. reflexivity. Qed.
(**
Note in case where we want to over-write a high cell via a pointer whose reference
type is high with a low value,since the side effect of such operation will not
be reflected at all in projected heap, we simply replace the referred location with
[None] and leave the rest to our reduction relation in [LowLang].
*)
Example test_project_conf_4:
project_conf (LowLang.tassign (LowLang.tloc (an int L) (Some 1))(LowLang.tH))(((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
=(LowLang.tassign (LowLang.tloc (an int L) None)(LowLang.tH),((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L) :: nil)).
Proof. compute. reflexivity. Qed.
(**
Note [test_project_conf_4] is a case where a high cell is being over-written by a high value.
Suppose we have the following projected configuration by [project_e] and [project_hp],
tassign (tloc (an int L) 1)(tH) / [L(6),L(5)]
0->0 2->1
which is to over-write a high value via a pointer whose reference type is low with
a high value. Since any side effect related with high security does not show up in
the projected heap, we should have the following configuration as the result of
our [project_conf] above,
tassign (tloc (an int L) 2)(tH) / [L(6),L(5)]
*)
(**
Example test_project_conf_5:
project_conf (LowLang.tapp
(LowLang.tassign (LowLang.tloc (an int L) (Some 2))(LowLang.tcon 8))
(LowLang.tassign (LowLang.tloc (an int L) (Some 5))(LowLang.tcon 9)))
(((LowLang.tcon 1,an int L),(0,0)) :: ((LowLang.tcon 2,an int L),(1,1)) :: ((LowLang.tcon 7,an int L),(6,2)) :: nil)
= (
LowLang.tapp
(LowLang.tassign (LowLang.tloc (an int L) None)(LowLang.tH))
(LowLang.tassign (LowLang.tloc (an int L) None)(LowLang.tH)),
((LowLang.tcon 1,an int L) :: (LowLang.tcon 2,an int L) :: (LowLang.tcon 7,an int L) :: nil)).
Proof. compute. reflexivity. Qed.
*)
Example test_project_conf_5':
project_conf (LowLang.tapp (LowLang.tH) (LowLang.tloc (an int L) (Some 2)))
(((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
=(LowLang.tapp (LowLang.tH) (LowLang.tloc (an int L) (Some 1)),((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L) :: nil)).
Proof. compute. reflexivity. Qed.
Example test_project_conf_6:
project_conf (LowLang.tderef(LowLang.tloc (an int H) (Some 1)))(((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
=(LowLang.tderef(LowLang.tloc (an int H) None),((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L) :: nil)).
Proof. compute. reflexivity. Qed.
Example test_project_conf_7:
project_conf (LowLang.tderef(LowLang.tloc (an int L) (Some 2)))(((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
=(LowLang.tderef(LowLang.tloc (an int L) (Some 1)),((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L) :: nil)).
Proof. compute. reflexivity. Qed.
(**
Example test_project_conf_8:
project_conf (LowLang.tassign (LowLang.tloc (an int L) (Some 2))(LowLang.tH))(((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
=(LowLang.tassign (LowLang.tloc (an int L) (Some 1))(LowLang.tH),((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L):: nil)).
Proof. compute. reflexivity. Qed.
(**
Note that the above example is the case where a low cell is being over-written by a high value.
Since it is the case excluded specifically in [SecLang],we need not consider the projection of it
at all
*)
*)
(**
Example test_project_conf_9:
project_conf (LowLang.tassign (LowLang.tloc (an int H) (Some 2))(LowLang.tcon 7))(((LowLang.tcon 6,an int L),(0,0)) :: ((LowLang.tcon 5,an int L),(2,1)) :: nil)
=(LowLang.tassign (LowLang.tloc (an int H) (Some 1))(LowLang.tcon 7),((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L) :: nil)).
Proof. compute. reflexivity. Qed.
(**
Similar to [test_project_conf_8] where a low cell is being over-written by a high value
*)
*)
(*some lemmas regarding [project_conf']*)
Lemma project_conf'_subst:forall x v e hp,
project_conf'_e (LowLang.subst x v e) hp
= LowLang.subst x (project_conf'_e v hp) (project_conf'_e e hp).
Proof. intros. generalize dependent x. generalize dependent v. generalize dependent hp.
induction e.
Case ("tvar"). intros. simpl. remember (beq_id x i) as C. destruct C. reflexivity. reflexivity.
Case ("tcon"). intros. simpl. reflexivity.
Case ("tabs"). intros. simpl. remember (beq_id x i) as C. destruct C. reflexivity.
specialize (IHe hp v x). rewrite<-IHe. reflexivity.
Case ("tapp"). intros. simpl. specialize (IHe1 hp v x). specialize (IHe2 hp v x). rewrite->IHe1.
rewrite->IHe2. reflexivity.
Case ("tunit"). intros. simpl. reflexivity.
Case ("tref"). intros. simpl. specialize (IHe hp v x). rewrite<-IHe. reflexivity.
Case ("tderef"). intros. simpl. specialize (IHe hp v x). rewrite->IHe. reflexivity.
Case ("tloc"). intros. simpl. destruct o. remember (fst(return_smallest_match n hp)) as C. destruct C. simpl.
reflexivity. simpl. reflexivity. simpl. reflexivity.
Case ("tassign"). intros. simpl. specialize (IHe1 hp v x). specialize (IHe2 hp v x).
rewrite->IHe1. rewrite->IHe2. reflexivity.
Case ("tH"). intros. reflexivity.
Qed.
(**
Finally,we assemble the above three projection functions,[project_e],[project_hp],and [project_conf] together
*)
(*projection from a configuration in [SecLang] to one in [LowLang]*)
Definition project (c:SecLang.tm*SecLang.heap) : LowLang.tm*LowLang.heap :=
project_conf (project_e (fst c))(project_hp (snd c)).
(*some examples*)
(**
Example test_project_1:
project (SecLang.tassign (SecLang.tloc (an int L) (Some 1) L)(SecLang.tcon 7 L),((SecLang.tcon 6 L,an int L) :: (SecLang.tcon 6 H,an int H) :: (SecLang.tcon 5 L,an int L) :: nil))
= (LowLang.tassign (LowLang.tloc (an int L) None)(LowLang.tH),((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L) :: nil)).
Proof. compute. reflexivity. Qed.
*)
Example test_project_2:
project (SecLang.tassign (SecLang.tloc (an int L) (Some 2) L)(SecLang.tcon 7 L),((SecLang.tcon 6 L,an int L) :: (SecLang.tcon 6 H,an int H) :: (SecLang.tcon 5 L,an int L)::nil))
=(LowLang.tassign (LowLang.tloc (an int L) (Some 1))(LowLang.tcon 7),((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L) :: nil)).
Proof. compute. reflexivity. Qed.
Example test_project_3:
project (SecLang.tassign (SecLang.tloc (an int H) (Some 1) L)(SecLang.tcon 7 L),((SecLang.tcon 6 L,an int L) :: (SecLang.tcon 6 H,an int H) :: (SecLang.tcon 5 L,an int L) :: nil))
=(LowLang.tassign (LowLang.tloc (an int H) None)(LowLang.tcon 7),((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L) :: nil)).
Proof. compute. reflexivity. Qed.
(**
Example test_project_4:
project (SecLang.tassign (SecLang.tloc (an int L) (Some 2) L)(SecLang.tcon 7 H),((SecLang.tcon 6 L,an int L) :: (SecLang.tcon 6 H,an int H) :: (SecLang.tcon 5 L,an int L) :: nil))
=((LowLang.tassign (LowLang.tloc (an int L) (Some 1))(LowLang.tH)),((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L) :: nil)).
Proof. compute. reflexivity. Qed.
*)
(**
Example test_project_5:
project (SecLang.tassign (SecLang.tloc (an int H) (Some 2) L)(SecLang.tcon 7 L),((SecLang.tcon 6 L,an int L) :: (SecLang.tcon 6 H,an int H) :: (SecLang.tcon 5 L,an int L) :: nil))
=(LowLang.tassign (LowLang.tloc (an int H) (Some 1))(LowLang.tcon 7),((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L) :: nil)).
Proof. compute. reflexivity. Qed.
*)
Example test_project_6:
project (SecLang.tassign (SecLang.tloc (an int H) (Some 2) L)(SecLang.tcon 7 L),((SecLang.tcon 6 L,an int L) :: (SecLang.tcon 5 L,an int L) :: nil))
=(LowLang.tassign (LowLang.tloc (an int H) None)(LowLang.tcon 7),((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L) :: nil)).
Proof. compute. reflexivity. Qed.
(**
Note that in [test_project_6],the pointer is considerec to refer to high value
on the heap and that is why the referred location is projected to be [None]
*)
Example test_project_7:
project (SecLang.tassign (SecLang.tloc (an int H) (Some 4) L)(SecLang.tcon 7 L),((SecLang.tcon 6 L,an int L) :: (SecLang.tcon 6 H,an int H) :: (SecLang.tcon 5 L,an int L) :: nil))
=(LowLang.tassign (LowLang.tloc (an int H) None)(LowLang.tcon 7),((LowLang.tcon 6,an int L) :: (LowLang.tcon 5,an int L) :: nil)).
Proof. compute. reflexivity. Qed.
(**
similar to that of [test_project_6]
*)
(*some important lemmas before NI*)
(*a single-step reduction in [SecLang] can be projected to be a multi-step reduction in [LowLang]*)
Lemma proj_hp_H_same:forall t t' hp hp',
SecLang.step (t,hp) H (t',hp') ->
project_hp hp = project_hp hp'.
Proof. intros t. induction t.
Case ("tvar").
intros. inversion H0.
Case ("tprot").
intros. inversion H0. subst. simpl in H9. apply IHt with (t':=t'0). apply H9. subst.
reflexivity.
Case ("tcon").
intros. inversion H0.
Case ("tabs").
intros. inversion H0.
Case ("tapp").
intros. inversion H0. subst. reflexivity. subst. apply IHt1 with (t':=t1'). apply H10.
subst. apply IHt2 with (t':=t2'). apply H11.
Case ("tunit").
intros. inversion H0.
Case ("tref").
intros. inversion H0. subst. assert (SecLang.joins s H = SecLang.joins H s). rewrite->SecLang.joins_refl. reflexivity.
rewrite->H1. simpl. destruct t. simpl. assert (SecLang.joins s0 H = SecLang.joins H s0). rewrite->SecLang.joins_refl. reflexivity.
rewrite->H2. clear H1. clear H2. simpl. apply project_hp_Hextend with (hp:=hp)(T:=an r s0) in H9. apply H9. subst. apply IHt with (t':=t'0).
apply H10.
Case ("tderef").
intros. inversion H0. subst. reflexivity. subst. apply IHt with (t':=t'0). apply H8.
Case ("tloc").
intros. inversion H0.
Case ("tassign").
intros. inversion H0. subst. simpl. destruct T. simpl. rewrite->SecLang.joins_refl. simpl.
apply project_hp_Hoverwrite. apply H8. apply H9. simpl in H14. apply H14.
(**
Here we have to prove that a high cell being replaced by high value won't make a difference in
[project_hp]
*)
subst. apply IHt1 with (t':=t1'). apply H10. subst. apply IHt2 with (t':=t2'). apply H11.
Qed.
(*some auxialary lemmas regarding [corresp_step]*)
Lemma SecLang_value_LowLang:forall v hp,
SecLang.value v ->
LowLang.value (project_conf'_e (project_e v)(project_conf'_hp (project_hp hp)(project_hp hp))).
Proof. intros. inversion H0.
Case ("tcon"). subst. destruct b. simpl. apply LowLang.v_c. simpl. apply LowLang.v_H.
Case ("tabs"). subst. destruct b. simpl. apply LowLang.v_f. simpl. apply LowLang.v_H.
Case ("tunit"). subst. destruct b. simpl. apply LowLang.v_u. simpl. apply LowLang.v_H.
Case ("tloc"). subst. destruct b. simpl. remember (fst(return_smallest_match n(project_conf'_hp (project_hp hp) (project_hp hp)))) as C.
destruct C. apply LowLang.v_l. apply LowLang.v_l. simpl. apply LowLang.v_H.
Qed.
Lemma multi_step_app1:forall c c' t2 PC,
LowLang.Multi LowLang.step c PC c' ->
LowLang.Multi LowLang.step (LowLang.tapp (fst c) t2,snd c) PC (LowLang.tapp (fst c') t2,snd c').
Proof. intros. generalize dependent t2. induction H0.
Case ("Multi_refl"). intros. apply LowLang.Multi_refl.
Case ("Multi_step"). intros. destruct y. apply LowLang.Multi_step with (y:=(LowLang.tapp t t2,h)).
apply LowLang.st_app1. destruct x. apply H0. specialize (IHMulti t2). apply IHMulti.
Qed.
Lemma multi_step_app2:forall v1 c c' PC,
LowLang.value v1 ->
LowLang.Multi LowLang.step c PC c' ->
LowLang.Multi LowLang.step (LowLang.tapp v1 (fst c),snd c) PC (LowLang.tapp v1 (fst c'),snd c').
Proof. intros. generalize dependent v1. induction H1.
Case ("Multi_refl"). intros. apply LowLang.Multi_refl.
Case ("Multi_step"). intros. destruct y. destruct x. apply LowLang.Multi_step with (y:=(LowLang.tapp v1 t,h)).
apply LowLang.st_app2. apply H2. apply H0. apply IHMulti. apply H2.
Qed.
Lemma multi_step_ref:forall c c' PC T,
LowLang.Multi LowLang.step c PC c' ->
LowLang.Multi LowLang.step (LowLang.tref T (fst c),snd c) PC (LowLang.tref T (fst c'),snd c').
Proof. intros. generalize dependent T. induction H0.
Case ("Multi_refl"). intros. apply LowLang.Multi_refl.
Case ("Multi_step"). intros. destruct y. apply LowLang.Multi_step with (y:=(LowLang.tref T t,h)). apply LowLang.st_ref. destruct x.
apply H0. specialize (IHMulti T). apply IHMulti.
Qed.
Lemma multi_step_deref:forall c c' PC,
LowLang.Multi LowLang.step c PC c' ->
LowLang.Multi LowLang.step (LowLang.tderef (fst c),snd c) PC (LowLang.tderef (fst c'),snd c').
Proof. intros. induction H0.
Case ("Multi_refl"). intros. apply LowLang.Multi_refl.
Case ("Multi_step"). intros. destruct y. apply LowLang.Multi_step with (y:=(LowLang.tderef t,h)). apply LowLang.st_deref. destruct x.
apply H0. apply IHMulti.
Qed.
Lemma multi_step_assign1:forall c c' t2 PC,
LowLang.Multi LowLang.step c PC c' ->
LowLang.Multi LowLang.step (LowLang.tassign (fst c) t2,snd c) PC (LowLang.tassign (fst c') t2,snd c').
Proof. intros. generalize dependent t2. induction H0.
Case ("Multi_refl"). intros. apply LowLang.Multi_refl.
Case ("Multi_step"). intros. destruct y. apply LowLang.Multi_step with (y:=(LowLang.tassign t t2,h)).
apply LowLang.st_assign1. destruct x. apply H0. specialize (IHMulti t2). apply IHMulti.
Qed.
Lemma multi_step_assign2:forall v1 c c' PC,
LowLang.value v1 ->
LowLang.Multi LowLang.step c PC c' ->
LowLang.Multi LowLang.step (LowLang.tassign v1 (fst c),snd c) PC (LowLang.tassign v1 (fst c'),snd c').
Proof. intros. generalize dependent v1. induction H1.
Case ("Multi_refl"). intros. apply LowLang.Multi_refl.
Case ("Multi_step"). intros. destruct y. destruct x. apply LowLang.Multi_step with (y:=(LowLang.tassign v1 t,h)).
apply LowLang.st_assign2. apply H2. apply H0. apply IHMulti. apply H2.
Qed.
Lemma step_same_mark_or_extend:forall t t' hp hp',
SecLang.step (t,hp) L (t',hp') ->
(same_mark (project_hp hp)(project_hp hp') = true) \/
(exists L0,project_hp hp' = LowLang.snoc (project_hp hp) (L0,(length hp,length (project_hp hp)))).
Proof. intros t. induction t.
Case ("tvar"). intros. inversion H0.
Case ("tprot"). intros. inversion H0. subst. destruct s. apply IHt in H9. apply H9. simpl in H9. apply proj_hp_H_same in H9.
left. rewrite->H9. apply same_mark_refl. subst. left. apply same_mark_refl.
Case ("tcon"). intros. inversion H0.
Case ("tabs"). intros. inversion H0.
Case ("tapp"). intros. inversion H0. subst. left. apply same_mark_refl. subst. apply IHt1 in H10. apply H10. subst. apply IHt2 in H11. apply H11.
Case ("tunit"). intros. inversion H0.
Case ("tref"). intros. inversion H0. subst. destruct t. destruct s0. destruct s. simpl. inversion H9. destruct b. rewrite->SecLang.join_tcon_b.
simpl. right. exists (LowLang.tcon n,an r L). apply project_hp_Lextend. apply SecLang.v_c. reflexivity. assert (SecLang.joinvs (SecLang.tcon n H) L = SecLang.joinvs (SecLang.tcon n L) H).
reflexivity. rewrite->H2. left. subst. assert (SecLang.value (SecLang.tcon n L)). apply SecLang.v_c. apply project_hp_Hextend with (hp:=hp)(T:=an r L)in H1. rewrite<-H1. apply same_mark_refl.
destruct b. rewrite->SecLang.join_tabs_b. simpl. right. exists (LowLang.tabs (Id n) T (project_e e),an r L). apply project_hp_Lextend. apply SecLang.v_f. reflexivity. assert (SecLang.joinvs (SecLang.tabs (Id n) T e H) L = SecLang.joinvs (SecLang.tabs (Id n) T e L) H).
reflexivity. rewrite->H2. left. assert (SecLang.value (SecLang.tabs (Id n) T e L)). apply SecLang.v_f. apply project_hp_Hextend with (hp:=hp)(T:=an r L) in H3. rewrite<-H3. apply same_mark_refl. destruct b. rewrite->SecLang.join_tunit_b. simpl. right.
exists (LowLang.tunit,an r L). apply project_hp_Lextend. apply SecLang.v_u. reflexivity. assert (SecLang.joinvs (SecLang.tunit H) L = SecLang.joinvs (SecLang.tunit L) H). reflexivity. rewrite->H2. left. assert (SecLang.value (SecLang.tunit L)). apply SecLang.v_u.
apply project_hp_Hextend with (hp:=hp)(T:=an r L) in H3. rewrite<-H3. apply same_mark_refl. destruct b. rewrite->SecLang.join_tloc_b. simpl. right. exists (LowLang.tloc T (Some n),an r L). apply project_hp_Lextend. apply SecLang.v_l. reflexivity. assert (SecLang.joinvs (SecLang.tloc T (Some n) H) L = SecLang.joinvs (SecLang.tloc T (Some n) L) H).
reflexivity. rewrite->H2. left. assert (SecLang.value (SecLang.tloc T (Some n) L)). apply SecLang.v_l. apply project_hp_Hextend with (hp:=hp)(T:=an r L)in H3. rewrite<-H3. apply same_mark_refl. left. simpl. apply project_hp_Hextend with (hp:=hp)(T:=an r L) in H9. rewrite<-H9. apply same_mark_refl. left. simpl. apply project_hp_Hextend with (hp:=hp)(T:=an r H) in H9.
rewrite<-H9. apply same_mark_refl. subst. destruct s. apply IHt in H10. apply H10. simpl in H10. apply proj_hp_H_same in H10. left. rewrite->H10. apply same_mark_refl.
Case ("tderef"). intros. inversion H0. subst. left. apply same_mark_refl. subst. apply IHt in H8. apply H8.
Case ("tloc"). intros. inversion H0.
Case ("tassign"). intros. inversion H0. subst. left. destruct T. destruct s. destruct b. simpl. inversion H9. destruct b. rewrite->SecLang.join_tcon_b. simpl. subst. simpl in H13. apply project_hp_Loverwrite.
apply H8. apply SecLang.v_c. reflexivity. symmetry. apply H13. subst. simpl in H13. assert (project_hp hp = project_hp (SecLang.heap_replace n (SecLang.joinvs (SecLang.tcon n0 H) L,an r L) hp)).
assert (SecLang.joinvs (SecLang.tcon n0 H) L = SecLang.joinvs (SecLang.tcon n0 L) H). reflexivity. rewrite->H1. clear H1.
apply project_hp_Hoverwrite. apply H8. apply SecLang.v_c. rewrite<-H13. apply sub_refl. rewrite<-H1. apply same_mark_refl. subst. destruct b. rewrite->SecLang.join_tabs_b. simpl. simpl in H13. apply project_hp_Loverwrite.
apply H8. apply SecLang.v_f. reflexivity. symmetry. apply H13. simpl in H13. assert (SecLang.joinvs (SecLang.tabs (Id n0) T e H) L = SecLang.joinvs (SecLang.tabs (Id n0) T e L) H). reflexivity. rewrite->H1. clear H1.
assert (project_hp hp = project_hp (SecLang.heap_replace n (SecLang.joinvs (SecLang.tabs (Id n0) T e L) H, an r L) hp) ). apply project_hp_Hoverwrite. apply H8. apply SecLang.v_f. rewrite<-H13. apply sub_refl. rewrite->H1. apply same_mark_refl.
subst. destruct b. rewrite->SecLang.join_tunit_b. simpl. apply project_hp_Loverwrite. apply H8. apply SecLang.v_u. reflexivity. simpl in H13. rewrite<-H13. reflexivity. assert (SecLang.joinvs (SecLang.tunit H) L = SecLang.joinvs (SecLang.tunit L) H). reflexivity.
rewrite->H1. clear H1. assert (project_hp hp = project_hp (SecLang.heap_replace n (SecLang.joinvs (SecLang.tunit L) H, an r L) hp)). apply project_hp_Hoverwrite. apply H8. apply SecLang.v_u. simpl in H13. rewrite<-H13. apply sub_refl. rewrite<-H1. apply same_mark_refl.
subst. destruct b. rewrite->SecLang.join_tloc_b. simpl. apply project_hp_Loverwrite. apply H8. apply SecLang.v_l. reflexivity. simpl in H13. rewrite<-H13. reflexivity. assert (SecLang.joinvs (SecLang.tloc T (Some n0) H) L = SecLang.joinvs (SecLang.tloc T (Some n0) L) H). reflexivity.
rewrite->H1. clear H1. assert (project_hp hp = project_hp (SecLang.heap_replace n (SecLang.joinvs (SecLang.tloc T (Some n0) L) H, an r L) hp)). apply project_hp_Hoverwrite. apply H8. apply SecLang.v_l. simpl in H13. rewrite<-H13. apply sub_refl. rewrite<-H1. apply same_mark_refl.
simpl. assert (project_hp hp = project_hp (SecLang.heap_replace n (SecLang.joinvs t2 H, an r H) hp)). apply project_hp_Hoverwrite. apply H8. apply H9. simpl in H14. inversion H14. apply sub_refl. rewrite<-H1. apply same_mark_refl. assert (SecLang.joinTs (an r H)(SecLang.joins L b) = an r H). simpl.
destruct b. reflexivity. reflexivity. rewrite->H1. clear H1. simpl. assert (project_hp hp = project_hp (SecLang.heap_replace n (SecLang.joinvs t2 H, an r H) hp)). apply project_hp_Hoverwrite. apply H8. apply H9. simpl in H13. remember (SecLang.label t2) as BB. destruct BB. simpl in H13. rewrite<-H13. apply sub_refl.
simpl in H13. rewrite<-H13. apply sub_refl. rewrite<-H1. apply same_mark_refl. subst.
apply IHt1 in H10. apply H10. subst. apply IHt2 in H11. apply H11.
Qed.
(**
Note that marked_heap_lookup has to be respecified such that it searches the
marked_heap according to the first number of the relevant mark.
*)
(*some auxiliary lemmas*)
(*######################*)
Lemma n_plus_neq_n:forall n n',
n <> (n' + (S n)).
Proof. intros n. induction n. intros. intros contra. destruct n'. inversion contra. inversion contra.
intros. intros contra. rewrite<-plus_n_Sm in contra. inversion contra. apply IHn in H1. inversion H1.
Qed.
(*######################*)
(**
Note:[heap_marked_heap_low] guarantees that whenever the query function [return_smallest_match]
returns [false] upon a query [n],we know that the nth value on the marked heap is
[project_e t],given that the nth value on the heap is [t]
*)
Lemma heap_marked_heap_low':forall n t n1 n2 hp,
t = SecLang.efst (SecLang.heap_lookup n hp) ->
false = fst (return_smallest_match (n+n1) (marked_heap (marked_heap' hp n1) n2)) ->
Some (project_e t) =
marked_efst (marked_heap_lookup (n+n1)
(marked_heap (marked_heap' hp n1) n2)).
Proof. intros. generalize dependent n. generalize dependent t. generalize dependent n1. generalize dependent n2.
induction hp.
Case ("nil"). intros. simpl in H1. inversion H1.
Case ("h::t"). intros. destruct n. destruct n1. destruct a. simpl.
remember (SecLang.label t0) as BB. destruct BB. simpl. simpl in H0. subst. reflexivity.
simpl in H1. rewrite<-HeqBB in H1. assert (0<1). apply le_n. apply return_true_marked_heap with (hp:=hp)(n2:=S n2)in H2.
rewrite<-H2 in H1. inversion H1.
destruct a. simpl. destruct n2. simpl.
remember (SecLang.label t0) as BB. destruct BB. simpl. rewrite<-beq_nat_refl. simpl. simpl in H0. subst.
reflexivity. simpl in H1. rewrite<-HeqBB in H1.
assert (S n1<S (S n1)). apply le_n. apply return_true_marked_heap with (hp:=hp)(n2:=1)in H2.
rewrite<-H2 in H1. inversion H1.
remember (SecLang.label t0) as BB. destruct BB. simpl. rewrite<-beq_nat_refl. simpl. simpl in H0. subst.
reflexivity. simpl in H1. rewrite<-HeqBB in H1.
assert (S n1<S (S n1)). apply le_n. apply return_true_marked_heap with (hp:=hp)(n2:=S (S n2))in H2.
rewrite<-H2 in H1. inversion H1.
destruct a. simpl. destruct n1. simpl.
remember (SecLang.label t0) as BB. destruct BB. simpl.
rewrite->plus_n_Sm.
apply IHhp. simpl in H0. apply H0. simpl in H1. rewrite<-HeqBB in H1. simpl in H1.
rewrite->plus_n_Sm in H1. apply H1.
rewrite->plus_n_Sm.
apply IHhp. simpl in H0. apply H0. simpl in H1. rewrite<-HeqBB in H1.
rewrite->plus_n_Sm in H1. apply H1.
simpl. destruct n2.
remember (SecLang.label t0) as BB. destruct BB. simpl.
assert (n1<>n+(S n1)). apply n_plus_neq_n. apply not_eq_beq_false in H2.
rewrite->H2. clear H2.
rewrite->plus_n_Sm. apply IHhp.
simpl in H0. apply H0. simpl in H1. rewrite<-HeqBB in H1. simpl in H1.
assert (n1<>n+(S n1)). apply n_plus_neq_n. apply not_eq_beq_false in H2.
rewrite->H2 in H1. clear H2. rewrite->plus_n_Sm in H1. apply H1.
rewrite->plus_n_Sm. apply IHhp.
simpl in H0. apply H0. simpl in H1. rewrite<-HeqBB in H1.
rewrite->plus_n_Sm in H1. apply H1.
remember (SecLang.label t0) as BB. destruct BB. simpl.
assert (n1<>n+(S n1)). apply n_plus_neq_n. apply not_eq_beq_false in H2.
rewrite->H2. rewrite->plus_n_Sm.
apply IHhp. simpl in H0. apply H0. simpl in H1. rewrite<-HeqBB in H1. simpl in H1.
rewrite->H2 in H1.
rewrite->plus_n_Sm in H1. apply H1.
rewrite->plus_n_Sm. apply IHhp.
simpl in H0. apply H0.
simpl in H1. rewrite<-HeqBB in H1.
rewrite->plus_n_Sm in H1. apply H1.
Qed.
Lemma heap_marked_heap_low:forall n t hp,
t = SecLang.efst (SecLang.heap_lookup n hp) ->
false = fst (return_smallest_match n (project_hp hp)) ->
Some (project_e t) =
marked_efst (marked_heap_lookup n
(project_hp hp)).
Proof. unfold project_hp. intros. assert (n = n+0). rewrite->plus_comm. reflexivity. rewrite->H2.
clear H2. apply heap_marked_heap_low'. apply H0. rewrite->plus_comm. simpl.
apply H1.
Qed.
(**
Note: Now we are trying to show that the position of the value with the matched
mark on the marked heap is the same as the second number of the matched mark
*)
(*some auxiliary lemmas*)
(*#####################*)
Lemma marked_heap_lookup_Sn_n:forall n n0 n1 n2 hp,
marked_efst (marked_heap_lookup (S n) (marked_heap (marked_heap' hp (S n0)) n1))
= marked_efst (marked_heap_lookup n (marked_heap (marked_heap' hp n0) n2)).
Proof. intros. generalize dependent n. generalize dependent n0. generalize dependent n1. generalize dependent n2.
induction hp.
Case ("nil"). intros. reflexivity.
Case ("h::t"). intros. destruct a. simpl. remember (SecLang.label t) as BB. destruct BB. destruct n1. destruct n0. simpl.
destruct n. rewrite<-HeqBB. simpl. reflexivity. rewrite<-HeqBB. simpl. specialize (IHhp n2 0 1 (S n)). apply IHhp.
simpl. rewrite<-HeqBB. destruct n. destruct n2. simpl. specialize (IHhp 0 0 (S (S n0)) 0). apply IHhp. simpl.
specialize (IHhp (S n2) 0 (S (S n0)) 0). apply IHhp. destruct n2. simpl. remember (beq_nat n0 n) as CC. destruct CC.
reflexivity. specialize (IHhp 0 0 (S (S n0)) (S n)). apply IHhp. simpl. remember (beq_nat n0 n) as CC. destruct CC.
reflexivity. specialize (IHhp (S n2) 0 (S (S n0)) (S n)). apply IHhp. simpl. destruct n0. simpl. rewrite<-HeqBB. simpl.
destruct n. reflexivity. specialize (IHhp n2 (S n1) 1 (S n)). apply IHhp. simpl. rewrite<-HeqBB. destruct n2. simpl. destruct n.
specialize (IHhp 0 (S n1) (S (S n0)) 0). apply IHhp. remember (beq_nat n0 n) as CC. destruct CC. reflexivity. specialize (IHhp 0 (S n1) (S (S n0)) (S n)). apply IHhp.
simpl. destruct n. specialize (IHhp (S n2) (S n1) (S (S n0)) 0). apply IHhp. remember (beq_nat n0 n) as CC. destruct CC. reflexivity. specialize (IHhp (S n2) (S n1) (S (S n0)) (S n)). apply IHhp.
destruct n0. simpl. rewrite<-HeqBB. specialize (IHhp (S n2) (S n1) 1 n). apply IHhp. simpl. rewrite<-HeqBB. specialize (IHhp (S n2) (S n1) (S (S n0)) n). apply IHhp.
Qed.
Lemma heap_lookup_n_all_marks:forall hp n n1 n2 n3 n4,
efst (heap_lookup n (marked_heap (marked_heap' hp n1) n2)) =efst (heap_lookup n (marked_heap (marked_heap' hp n3) n4)).
Proof. intros hp. induction hp.
Case ("nil"). intros. reflexivity.
Case ("h::t"). intros. destruct a. simpl. destruct n1. destruct n3. simpl. remember (SecLang.label t) as BB. destruct BB.
destruct n. simpl. reflexivity. simpl. apply IHhp. apply IHhp. simpl. remember (SecLang.label t) as BB. destruct BB.
destruct n4. destruct n. simpl. reflexivity. simpl. apply IHhp. destruct n. simpl. reflexivity. simpl. apply IHhp.
apply IHhp. destruct n3. simpl. remember (SecLang.label t) as BB. destruct BB. destruct n2. destruct n. simpl. reflexivity.
simpl. apply IHhp. destruct n. simpl. reflexivity. simpl. apply IHhp. apply IHhp. simpl. remember (SecLang.label t) as BB. destruct BB.
destruct n2. destruct n4. destruct n. simpl. reflexivity. simpl. apply IHhp. destruct n. simpl. reflexivity. simpl. apply IHhp.
destruct n4. destruct n. simpl. reflexivity. simpl. apply IHhp. destruct n. simpl. reflexivity. simpl. apply IHhp.
apply IHhp.
Qed.
Lemma return_None_marked_heap_lookup:forall hp n n1 n2,
n < n1 ->
None = marked_efst (marked_heap_lookup n (marked_heap (marked_heap' hp n1) n2)).
Proof. intros hp. induction hp.
Case ("nil"). intros. simpl. reflexivity.
Case ("h::t"). intros. destruct n. destruct a. simpl. destruct n1. apply LowLang.lt_same_F in H0.
inversion H0. simpl. destruct n2.
remember (SecLang.label t) as BB. destruct BB. simpl. apply IHhp. apply le_S in H0.
apply H0. apply IHhp. apply le_S in H0. apply H0.
remember (SecLang.label t) as BB. destruct BB. simpl. apply IHhp. apply le_S in H0. apply H0.
apply IHhp. apply le_S in H0. apply H0. destruct a. simpl. destruct n1. inversion H0. simpl.
destruct n2.
remember (SecLang.label t) as BB. destruct BB. simpl. assert (n<>n1). intros contra. rewrite->contra in H0.
apply LowLang.lt_same_F in H0. inversion H0. apply not_eq_beq_false in H1. rewrite->beq_nat_sym in H1. rewrite->H1.
apply IHhp. apply le_S in H0. apply H0. apply IHhp. apply le_S in H0. apply H0.
remember (SecLang.label t) as BB. destruct BB. simpl.
assert (n<>n1). intros contra. rewrite->contra in H0.
apply LowLang.lt_same_F in H0. inversion H0. apply not_eq_beq_false in H1. rewrite->beq_nat_sym in H1. rewrite->H1.
apply IHhp. apply le_S in H0. apply H0. apply IHhp. apply le_S in H0. apply H0.
Qed.
(*#####################*)
Lemma lt_Sn_zero:forall n,
0 < S n.
Proof. intros. induction n. apply le_n. apply le_S. apply IHn.
Qed.
Lemma marked_heap_value_tws':forall n n' hp,
marked_efst (marked_heap_lookup n (marked_heap (marked_heap' hp n') n')) <> None ->
marked_efst (marked_heap_lookup n (marked_heap (marked_heap' hp n') n')) =
efst (heap_lookup (snd(snd(return_smallest_match n (marked_heap (marked_heap' hp n') n')))) (marked_heap (marked_heap' hp n') n')).
Proof. intros. generalize dependent n. generalize dependent n'. induction hp.
Case ("nil"). intros. simpl. destruct n. reflexivity. reflexivity.
Case ("h::t"). intros. destruct a. simpl. destruct n'. simpl.
remember (SecLang.label t) as BB. destruct BB. simpl. destruct n. simpl.
reflexivity. simpl in H0.
rewrite<-HeqBB in H0. simpl in H0. rewrite->marked_heap_lookup_Sn_n with (n2:=0).
assert (0<=0). apply le_n. apply return_smallest_match_snd_Sn_n with (hp:=hp)(n:=n)in H1.
rewrite->H1. clear H1. simpl. rewrite->heap_lookup_n_all_marks with(n3:=0)(n4:=0).
apply IHhp. rewrite->marked_heap_lookup_Sn_n with (n2:=0) in H0. apply H0.
apply IHhp. simpl in H0. rewrite<-HeqBB in H0. apply H0. simpl.
remember (SecLang.label t) as BB. destruct BB. simpl. destruct n.
assert (0<S n'). apply lt_Sn_zero.
apply return_None_marked_heap_lookup with(hp:=(t,t0)::hp)(n2:=S n')in H1. rewrite<-H1 in H0. assert (False).
apply H0. reflexivity. inversion H2.
remember (beq_nat n' n) as CC. destruct CC. simpl in H0. rewrite<-HeqBB in H0. simpl in H0. rewrite<-HeqCC in H0.
simpl. rewrite->minus_diag. simpl. reflexivity.
simpl. simpl in H0. rewrite<-HeqBB in H0. simpl in H0. rewrite<-HeqCC in H0.
rewrite->marked_heap_lookup_Sn_n with (n2:=S n'). assert (S n'<=S n'). apply le_n.
apply return_smallest_match_snd_Sn_n with (hp:=hp)(n:=n)in H1. rewrite->H1. clear H1. simpl.
rewrite->heap_lookup_n_all_marks with (n3:=S n')(n4:=S n'). apply IHhp. rewrite->marked_heap_lookup_Sn_n with(n2:=S n') in H0.
apply H0. apply IHhp. simpl in H0. rewrite<-HeqBB in H0. apply H0.
Qed.
Lemma marked_heap_value_tws:forall n hp,
marked_efst (marked_heap_lookup n (project_hp hp)) <> None ->
marked_efst (marked_heap_lookup n (project_hp hp)) =
efst (heap_lookup (snd(snd(return_smallest_match n (project_hp hp)))) (project_hp hp)).
Proof. unfold project_hp. intros. apply marked_heap_value_tws'. apply H0.
Qed.
(**
Now we are ready to prove the following equality,
v = efst (heap_lookup n hp) where
v = project_conf'_e (project_e t)(project_hp hp0)
n = snd(snd (return_smallest_match n (project_hp hp0)))
hp= erase_hp (project_conf'_hp (project_hp hp0)(project_hp hp0))
*)
(**
Step one,
we get started by proving some lemma where [project_e t] and
[snd(snd (return_smallest_match n (project_hp hp0)))] appear on opposite sides of
an equality,
*)
Lemma cs_derefloc_one:forall n t hp,
t = SecLang.efst (SecLang.heap_lookup n hp) ->
false = fst (return_smallest_match n (project_hp hp)) ->
Some (project_e t) =
efst (heap_lookup (snd(snd(return_smallest_match n (project_hp hp)))) (project_hp hp)).
Proof. intros. apply heap_marked_heap_low in H0. rewrite->H0. apply marked_heap_value_tws.
rewrite<-H0. intros contra. inversion contra. apply H1.
Qed.
(**
Step two,
we prove that if we use the same "query",[n],instead on the marked heap obtained
from evaluating every value on [project_hp hp] from [project_hp hp] we get a new
value obtained from evaluating the old one,[project_e t],from [project_hp hp],
*)
Lemma heap_lookup_project_conf'_hp':forall n hp hp' v,
efst (heap_lookup n hp) = Some v ->
efst (heap_lookup n (project_conf'_hp hp hp'))
= Some (project_conf'_e v hp').
Proof. intros. generalize dependent n. generalize dependent hp'. generalize dependent v.
induction hp.
Case ("nil"). intros. destruct n. simpl in H0. inversion H0. simpl in H0. inversion H0.
Case ("h::t"). intros. destruct n. destruct a. destruct p. simpl in H0. simpl. inversion H0.
reflexivity. destruct a. destruct p. simpl. apply IHhp. simpl in H0. apply H0.
Qed.
Lemma heap_lookup_project_conf'_hp:forall n hp v,
efst (heap_lookup n hp) = Some v ->
efst (heap_lookup n (project_conf'_hp hp hp))
= Some (project_conf'_e v hp).
Proof. intros. apply heap_lookup_project_conf'_hp'. apply H0.
Qed.
Lemma cs_derefloc_two':forall n t hp,
Some (project_e t) =
efst (heap_lookup (snd(snd(return_smallest_match n (project_hp hp)))) (project_hp hp)) ->
Some (project_conf'_e (project_e t)(project_hp hp)) =
efst (heap_lookup (snd(snd(return_smallest_match n (project_conf'_hp (project_hp hp)(project_hp hp))))) (project_conf'_hp (project_hp hp)(project_hp hp))).
Proof. intros. assert (same_mark (project_hp hp)(project_conf'_hp (project_hp hp)(project_hp hp)) = true). apply same_mark_heap.
apply return_smallest_match_same_mark' with (n:=n) in H1. rewrite<-H1. clear H1.
symmetry. apply heap_lookup_project_conf'_hp. symmetry. apply H0.
Qed.
Lemma cs_derefloc_two:forall n t hp,
t = SecLang.efst (SecLang.heap_lookup n hp) ->
false = fst (return_smallest_match n (project_hp hp)) ->
Some (project_conf'_e (project_e t)(project_hp hp)) =
efst (heap_lookup (snd(snd(return_smallest_match n (project_conf'_hp (project_hp hp)(project_hp hp))))) (project_conf'_hp (project_hp hp)(project_hp hp))).
Proof. intros. apply cs_derefloc_two'. apply cs_derefloc_one. apply H0. apply H1.
Qed.
(*one extra lemma related to [cs_derefloc_two]*)
(*############################################*)
Lemma heap_lookup_n_length: forall hp n v,
efst (heap_lookup n hp) = Some v ->
n < length hp.
Proof. intros hp. induction hp.
Case ("nil"). intros. destruct n. simpl in H0. inversion H0. simpl in H0. inversion H0.
Case ("h::t"). intros. destruct n. simpl. apply lt_0_Sn. simpl. apply SecLang.n_iff_Sn_left. apply IHhp with (v:=v).
simpl in H0. apply H0.
Qed.
(*############################################*)
(**
Step three,
finishing up by establishing relation between [heap_lookup] and [efst] in [LowLang]
and their counterparts in the current block,
efst (heap_lookup n hp) = Some (LowLang.efst (LowLang.heap_lookup n (erase hp)))
when there is a hit,
*)
Lemma cs_derefloc_three:forall n hp,
efst (heap_lookup n hp) <> None ->
efst (heap_lookup n hp) = Some (LowLang.efst (LowLang.heap_lookup n (erase_hp hp))).
Proof. intros. generalize dependent n. induction hp.
Case ("nil"). intros. destruct n. simpl in H0. assert (False). apply H0. reflexivity.
inversion H1. simpl in H0. assert (False). apply H0. reflexivity. inversion H1.
Case ("h::t"). intros. destruct n. destruct a. destruct p. simpl. reflexivity. simpl. destruct a.
apply IHhp. simpl in H0. apply H0.
Qed.
Lemma cs_derefloc:forall n t hp,
t = SecLang.efst (SecLang.heap_lookup n hp) ->
false = fst (return_smallest_match n (project_hp hp)) ->
project_conf'_e (project_e t)(project_hp hp) =
LowLang.efst (LowLang.heap_lookup (snd(snd(return_smallest_match n (project_hp hp)))) (erase_hp (project_conf'_hp (project_hp hp)(project_hp hp)))).
Proof. intros. apply cs_derefloc_two in H0.
assert (efst (heap_lookup(snd(snd(return_smallest_match n
(project_conf'_hp (project_hp hp) (project_hp hp)))))
(project_conf'_hp (project_hp hp) (project_hp hp)))<>None).
intros contra. rewrite<-H0 in contra. inversion contra.
apply cs_derefloc_three in H2. rewrite->H2 in H0. clear H2. inversion H0.
assert (same_mark (project_hp hp)(project_conf'_hp (project_hp hp)(project_hp hp))=true).
apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=n) in H2.
rewrite->H2. clear H2. apply H3.
apply H1.
Qed.
(**
Note the following block contains lemmas necessary to prove the sub-case,[st_assign],
in [corresp_step]
*)
(*##################*)
Lemma replace_BA_marked_heap_project_hp:forall n n1 n2 (v:SecLang.tm) (T:Ty) (hp:SecLang.heap),
n < length hp ->
SecLang.label v = SecLang.label (SecLang.efst (SecLang.heap_lookup n hp))->
marked_heap (marked_heap' (SecLang.heap_replace n (v,T) hp) n1) n2 =
marked_heap_replace (n+n1) (project_e v,T) (marked_heap (marked_heap' hp n1) n2).
Proof. intros. generalize dependent n. generalize dependent n1. generalize dependent n2.
generalize dependent v. generalize dependent T.
induction hp.
Case ("nil"). intros. simpl in H0. destruct n. apply LowLang.lt_same_F in H0. inversion H0.
inversion H0.
Case ("h::t"). intros. destruct n.
SCase ("n=0").
destruct a. simpl. simpl in H1. destruct n1. simpl.
remember (SecLang.label v) as BB. destruct BB. rewrite<-H1.
simpl. reflexivity. rewrite<-H1. assert (0<1). apply le_n.
apply marked_heap_replace_same with (hp:=hp)(n2:=S n2)(p:=(project_e v,T)) in H2.
rewrite->H2. reflexivity.
simpl. remember (SecLang.label v) as BB. destruct BB. rewrite<-H1. destruct n2. simpl.
rewrite<-beq_nat_refl. reflexivity. simpl. rewrite<-beq_nat_refl. reflexivity. rewrite<-H1.
assert ((S n1)<(S (S n1))). apply le_n. apply marked_heap_replace_same with (hp:=hp)(n2:=S n2)(p:=(project_e v,T)) in H2.
rewrite->H2. reflexivity.
SCase ("n=S n'").
destruct a. simpl. destruct n1. simpl.
remember (SecLang.label t) as BB. destruct BB. simpl.
specialize (IHhp T v n2 1 n). simpl in H0. apply SecLang.lt_same_F' in H0. apply IHhp in H0.
rewrite<-plus_n_O. rewrite->plus_comm in H0. simpl in H0. rewrite->H0. reflexivity. simpl in H1.
apply H1. rewrite->plus_comm. simpl. specialize (IHhp T v (S n2) 1 n). simpl in H0.
apply SecLang.lt_same_F' in H0. apply IHhp in H0. rewrite->plus_comm in H0. simpl in H0.
rewrite->H0. reflexivity. simpl in H1. apply H1. simpl. remember (SecLang.label t) as BB. destruct BB.
destruct n2. simpl. assert (n1<>(n+ S n1)). apply n_plus_neq_n. apply not_eq_beq_false in H2. rewrite->H2.
clear H2. specialize (IHhp T v 0 (S (S n1)) n). simpl in H0. apply SecLang.lt_same_F' in H0. apply IHhp in H0.
rewrite->plus_n_Sm. rewrite->H0. reflexivity. simpl in H1. apply H1. simpl.
assert (n1<>(n + S n1)). apply n_plus_neq_n. apply not_eq_beq_false in H2. rewrite->H2. clear H2.
specialize (IHhp T v (S n2)(S (S n1)) n). simpl in H0. apply SecLang.lt_same_F' in H0. apply IHhp in H0.
rewrite->plus_n_Sm. rewrite->H0. reflexivity. simpl in H1. apply H1. rewrite->plus_n_Sm.
simpl in H0. apply SecLang.lt_same_F' in H0. specialize (IHhp T v (S n2)(S (S n1)) n). apply IHhp in H0.
rewrite->H0. reflexivity. simpl in H1. apply H1.
Qed.
Lemma same_mark_marked_heap_replace':forall n (v:SecLang.tm) (T:Ty) (hp:SecLang.heap),
SecLang.value v ->
n < length hp ->
SecLang.label v = SecLang.label (SecLang.efst (SecLang.heap_lookup n hp))->
same_mark (marked_heap (marked_heap' hp 0)0)
(marked_heap (marked_heap' (SecLang.heap_replace n (v,T) hp)0)0) = true.
Proof. intros. inversion H0.
Case ("tcon"). destruct b. subst.
SCase ("Loverwrite"). apply project_hp_Loverwrite. apply H1. apply SecLang.v_c. reflexivity.
rewrite<-H2. reflexivity.
SCase ("Hoverwrite"). assert (project_hp hp = project_hp (SecLang.heap_replace n (SecLang.joinvs (SecLang.tcon n0 H) H,T) hp)).
apply project_hp_Hoverwrite. apply H1. apply SecLang.v_c. subst. rewrite<-H2. apply sub_refl.
rewrite->SecLang.join_tcon_H in H4. unfold project_hp in H4. rewrite<-H4.
apply same_mark_refl.
Case ("tabs"). destruct b. subst.
SCase ("Loverwrite"). apply project_hp_Loverwrite. apply H1. apply SecLang.v_f. reflexivity.
rewrite<-H2. reflexivity.
SCase ("Hoverwrite"). assert (project_hp hp = project_hp (SecLang.heap_replace n (SecLang.joinvs (SecLang.tabs (Id n0) T0 e H) H,T) hp)).
apply project_hp_Hoverwrite. apply H1. apply SecLang.v_f. subst. rewrite<-H2. apply sub_refl.
rewrite->SecLang.join_tabs_H in H4. unfold project_hp in H4. rewrite<-H4.
apply same_mark_refl.
Case ("tunit"). destruct b. subst.
SCase ("Loverwrite"). apply project_hp_Loverwrite. apply H1. apply SecLang.v_u. reflexivity.
rewrite<-H2. reflexivity.
SCase ("Hoverwrite"). assert (project_hp hp = project_hp (SecLang.heap_replace n (SecLang.joinvs (SecLang.tunit H) H,T) hp)).
apply project_hp_Hoverwrite. apply H1. apply SecLang.v_u. subst. rewrite<-H2. apply sub_refl.
rewrite->SecLang.join_tunit_H in H4. unfold project_hp in H4. rewrite<-H4.
apply same_mark_refl.
Case ("tloc"). destruct b. subst.
SCase ("Loverwrite"). apply project_hp_Loverwrite. apply H1. apply SecLang.v_l. reflexivity.
rewrite<-H2. reflexivity.
SCase ("Hoverwrite"). assert (project_hp hp = project_hp (SecLang.heap_replace n (SecLang.joinvs (SecLang.tloc T0 (Some n0) H) H,T) hp)).
apply project_hp_Hoverwrite. apply H1. apply SecLang.v_l. subst. rewrite<-H2. apply sub_refl.
rewrite->SecLang.join_tloc_H in H4. unfold project_hp in H4. rewrite<-H4.
apply same_mark_refl.
Qed.
Lemma same_mark_marked_heap_replace:forall n n1 n2 (v:SecLang.tm) (T:Ty) (hp:SecLang.heap),
n2<=n1 ->
SecLang.value v ->
n < length hp ->
SecLang.label v = SecLang.label (SecLang.efst (SecLang.heap_lookup n hp))->
same_mark (marked_heap (marked_heap' hp n1)n2)
(marked_heap (marked_heap' (SecLang.heap_replace n (v,T) hp)n1)n2) = true.
Proof. intros. apply same_mark_marked_heap_replace' with(n:=n)(T:=T)(hp:=hp) in H1.
apply same_mark_marked_heap_generalize. apply H0. apply H1. apply H2. apply H3.
Qed.
Lemma project_conf'_hp_marked_heap_replace_1:forall n v T hp,
SecLang.value v ->
n < length hp ->
SecLang.label v = SecLang.label (SecLang.efst (SecLang.heap_lookup n hp))->
project_conf'_hp (project_hp (SecLang.heap_replace n (v,T) hp))(project_hp (SecLang.heap_replace n (v,T) hp))
=project_conf'_hp (marked_heap_replace n (project_e v,T) (project_hp hp)) (project_hp hp).
Proof. intros. assert (n<length hp). apply H1. apply replace_BA_marked_heap_project_hp with (n1:=0)(n2:=0)(v:=v)(T:=T)in H1.
rewrite->plus_comm in H1. simpl in H1. unfold project_hp. rewrite<-H1.
apply same_mark_marked_heap_replace' with (n:=n)(T:=T)(hp:=hp) in H0.
apply project_conf'_hp_same_mark with (hp:=marked_heap (marked_heap' (SecLang.heap_replace n (v, T) hp) 0) 0)in H0.
rewrite<-H0. reflexivity. apply H3. apply H2. apply H2.
Qed.
Lemma project_conf'_hp_marked_heap_replace_2:forall N V T HP HP',
project_conf'_hp (marked_heap_replace N (V,T) HP) HP'
= marked_heap_replace N (project_conf'_e V HP',T)(project_conf'_hp HP HP').
Proof. intros. generalize dependent N. generalize dependent V. generalize dependent T.
generalize dependent HP'. induction HP.
Case ("nil"). intros. simpl. reflexivity.
Case ("h::t"). intros. destruct a. destruct p0. simpl. remember (beq_nat n N) as BB. destruct BB.
destruct p. simpl. rewrite<-HeqBB. reflexivity. destruct p. simpl. rewrite<-HeqBB.
specialize (IHHP HP' T V N). rewrite->IHHP. reflexivity.
Qed.
Lemma project_conf'_hp_marked_heap_replace:forall v T n hp,
SecLang.value v ->
n < length hp ->
SecLang.label v = SecLang.label (SecLang.efst (SecLang.heap_lookup n hp))->
project_conf'_hp (project_hp (SecLang.heap_replace n (v,T) hp))(project_hp (SecLang.heap_replace n (v,T) hp))
=marked_heap_replace n (project_conf'_e (project_e v) (project_conf'_hp (project_hp hp)(project_hp hp)),T)
(project_conf'_hp (project_hp hp)(project_hp hp)).
Proof. intros. apply project_conf'_hp_marked_heap_replace_1 with (n:=n)(T:=T)(hp:=hp)in H0.
assert (same_mark (project_hp hp) (project_conf'_hp (project_hp hp) (project_hp hp)) = true).
apply same_mark_heap. apply project_conf'_e_same_mark with (t:=project_e v)in H3. rewrite<-H3.
rewrite<-project_conf'_hp_marked_heap_replace_2. apply H0.
apply H1. apply H2.
Qed.
(*some auxiliary lemmas for the following lemma*)
(*##############################################*)
Lemma add_both_mark_marked_heap_replace:forall hp n n1 n2 V T,
n2<=n1 ->
marked_heap_replace (S n) (V,T) (marked_heap(marked_heap' hp (S n1))n2)
=add_both_mark (marked_heap_replace n (V,T) (marked_heap(marked_heap' hp n1)n2)).
Proof. intros hp. induction hp.
Case ("nil"). intros. reflexivity.
Case ("h::t"). intros. destruct a. simpl. remember (SecLang.label t) as BB. destruct BB.
destruct n2. destruct n1. simpl. destruct n. rewrite<-HeqBB. simpl.
assert (0<=1). apply le_S. apply le_n. apply marked_heap_add_both_mark with (hp:=hp) in H1.
simpl in H1. rewrite<-H1. reflexivity. rewrite<-HeqBB. simpl. specialize (IHhp (S n) 1 0 V T).
assert (0<=1). apply le_S. apply le_n. apply IHhp in H1. rewrite->H1. reflexivity. simpl. rewrite<-HeqBB.
destruct n. simpl. rewrite->plus_comm. simpl. specialize (IHhp 0 (S (S n1)) 0 V T). apply le_S in H0.
apply IHhp in H0. rewrite<-H0. reflexivity. remember (beq_nat n1 n) as CC. destruct CC. simpl.
rewrite<-HeqCC. simpl. rewrite->plus_comm. simpl. assert (0<=S (S n1)). apply SecLang.zero_n.
apply marked_heap_add_both_mark with (hp:=hp) in H1. rewrite->plus_comm in H1. simpl in H1. rewrite<-H1.
reflexivity. simpl. rewrite<-HeqCC. simpl. rewrite->plus_comm. simpl. specialize (IHhp (S n) (S (S n1)) 0 V T).
apply le_S in H0. apply IHhp in H0. rewrite->H0. reflexivity. destruct n1. inversion H0. simpl. rewrite<-HeqBB.
destruct n2. destruct n. simpl. rewrite<-minus_n_O. rewrite->plus_comm. simpl. specialize (IHhp 0 (S (S n1)) 1 V T).
apply le_S in H0. apply IHhp in H0. rewrite->H0. reflexivity. remember (beq_nat n1 n) as CC. destruct CC.
simpl. rewrite<-HeqCC. simpl. rewrite<-minus_n_O. rewrite->plus_comm. simpl. apply le_S in H0.
apply marked_heap_add_both_mark with (hp:=hp) in H0. rewrite->plus_comm in H0. simpl in H0. rewrite<-H0. reflexivity.
simpl. rewrite<-HeqCC. simpl. rewrite<-minus_n_O. rewrite->plus_comm. simpl. specialize (IHhp (S n) (S (S n1)) 1 V T).
apply le_S in H0. apply IHhp in H0. rewrite->H0. reflexivity. destruct n. simpl. rewrite->plus_comm. simpl. rewrite->plus_comm.
simpl. assert (S (S n2)<=S n1). apply H0. apply SecLang.lt_snoc_1 in H0. apply minus_Sn_m in H0. rewrite->H0. simpl. specialize (IHhp 0 (S (S n1)) (S (S n2)) V T).
apply SecLang.lt_snoc_1 in H1. apply le_S in H1. apply SecLang.n_iff_Sn_left in H1. apply IHhp in H1. rewrite->H1. reflexivity.
remember (beq_nat n1 n) as CC. destruct CC. simpl. rewrite<-HeqCC. simpl. rewrite->plus_comm. simpl. rewrite->plus_comm. simpl. assert (S (S n2)<=S n1). apply H0.
apply SecLang.lt_snoc_1 in H0. apply minus_Sn_m in H0. rewrite->H0. simpl. apply le_S in H1. apply marked_heap_add_both_mark with (hp:=hp) in H1. rewrite->plus_comm in H1.
simpl in H1. rewrite->H1. reflexivity. simpl. rewrite<-HeqCC. simpl. rewrite->plus_comm. simpl. rewrite->plus_comm. simpl. assert (S (S n2)<=S n1). apply H0. apply SecLang.lt_snoc_1 in H0.
apply minus_Sn_m in H0. rewrite->H0. simpl. specialize (IHhp (S n) (S (S n1)) (S (S n2)) V T). apply le_S in H1. apply IHhp in H1. rewrite->H1. reflexivity. destruct n. destruct n1.
simpl. rewrite<-HeqBB. specialize (IHhp 0 1 (S n2) V T). apply SecLang.n_iff_Sn_left in H0. apply IHhp in H0. rewrite->H0. reflexivity. simpl. rewrite<-HeqBB. specialize (IHhp 0 (S (S n1)) (S n2) V T).
apply SecLang.n_iff_Sn_left in H0. apply IHhp in H0. apply H0.
destruct n. destruct n1. simpl. rewrite<-HeqBB. specialize (IHhp 1 1 (S n2) V T). apply SecLang.n_iff_Sn_left in H0. apply IHhp in H0. apply H0.
simpl. rewrite<-HeqBB. specialize (IHhp 1 (S (S n1))(S n2) V T). apply SecLang.n_iff_Sn_left in H0. apply IHhp in H0. apply H0. destruct n1. simpl.
rewrite<-HeqBB. specialize (IHhp (S (S n)) 1 (S n2) V T). apply SecLang.n_iff_Sn_left in H0. apply IHhp in H0. apply H0. simpl. rewrite<-HeqBB.
specialize (IHhp (S (S n))(S (S n1))(S n2) V T). apply SecLang.n_iff_Sn_left in H0. apply IHhp in H0. apply H0.
Qed.
Lemma add_both_mark_heap_replace:forall hp n n1 n2 V T,
n2<=n1->
heap_replace n (V,T) (marked_heap(marked_heap' hp (S n1))n2)
=add_both_mark (heap_replace n (V,T) (marked_heap(marked_heap' hp n1)n2)).
Proof. intros hp. induction hp.
Case ("nil"). intros. destruct n. reflexivity. reflexivity.
Case ("h::t"). intros. destruct a. simpl. remember (SecLang.label t) as BB.
destruct BB. destruct n2. destruct n1. simpl. rewrite<-HeqBB.
destruct n. simpl. assert (0<=1). apply le_S. apply le_n.
apply marked_heap_add_both_mark with (hp:=hp) in H1. simpl in H1.
rewrite->H1. clear H1. reflexivity. simpl. specialize (IHhp n 1 0 V T).
apply le_S in H0. apply IHhp in H0.
rewrite->H0. reflexivity. simpl. rewrite<-HeqBB. destruct n. simpl.
rewrite->plus_comm. simpl. assert (0<=S (S n1)). apply SecLang.zero_n.
apply marked_heap_add_both_mark with (hp:=hp) in H1. rewrite->plus_comm in H1.
simpl in H1. rewrite->H1. reflexivity. simpl. rewrite->plus_comm. simpl.
specialize (IHhp n (S (S n1)) 0 V T). apply le_S in H0. apply IHhp in H0.
rewrite->H0. reflexivity.
destruct n1. inversion H0. simpl. rewrite<-HeqBB. destruct n2. destruct n.
simpl. rewrite<-minus_n_O. rewrite->plus_comm. simpl. apply le_S in H0.
apply marked_heap_add_both_mark with (hp:=hp) in H0. rewrite->plus_comm in H0.
simpl in H0. rewrite->H0. reflexivity. simpl. rewrite<-minus_n_O. rewrite->plus_comm.
simpl. specialize (IHhp n (S (S n1)) 1 V T). apply le_S in H0. apply IHhp in H0. rewrite->H0.
reflexivity. destruct n. simpl. rewrite->plus_comm. simpl. rewrite->plus_comm. simpl.
assert (S n2<=n1). apply SecLang.lt_same_F' in H0.
apply H0. apply minus_Sn_m in H1. rewrite->H1. clear H1. simpl. apply le_S in H0.
apply marked_heap_add_both_mark with (hp:=hp) in H0. rewrite->plus_comm in H0. simpl in H0.
rewrite->H0. reflexivity. simpl. rewrite->plus_comm. simpl. rewrite->plus_comm. simpl.
assert (S n2<=n1). apply SecLang.lt_same_F' in H0. apply H0. apply minus_Sn_m in H1. rewrite->H1.
clear H1. simpl. specialize (IHhp n (S (S n1))(S(S n2)) V T). apply le_S in H0. apply IHhp in H0.
rewrite->H0. reflexivity. destruct n1. destruct n. destruct n2.
assert (marked_heap((t,t0,(0,0))::marked_heap' hp 1)0=marked_heap(marked_heap' hp 1)1). simpl.
rewrite<-HeqBB. reflexivity. rewrite->H1. apply SecLang.n_iff_Sn_left in H0. specialize (IHhp 0 1 1 V T).
apply IHhp in H0. rewrite->H0. reflexivity. inversion H0. destruct n2.
assert (marked_heap((t,t0,(0,0))::marked_heap' hp 1)0=marked_heap(marked_heap' hp 1)1). simpl.
rewrite<-HeqBB. reflexivity. rewrite->H1. clear H1. apply SecLang.n_iff_Sn_left in H0.
specialize (IHhp (S n) 1 1 V T). apply IHhp in H0. apply H0. inversion H0.
assert (marked_heap((t,t0,(S n1,S n1))::marked_heap' hp (S (S n1)))n2=marked_heap(marked_heap' hp (S (S n1)))(S n2)). simpl.
rewrite<-HeqBB. reflexivity. rewrite->H1. clear H1. apply SecLang.n_iff_Sn_left in H0. specialize (IHhp n (S (S n1))(S n2) V T).
apply IHhp in H0. apply H0.
Qed.
(*##############################################*)
Lemma marked_heap_replace_heap_replace':forall n n' V T hp,
fst (return_smallest_match n (marked_heap (marked_heap' hp n') n')) = false -> (*restricted to "low to low" case*)
marked_heap_replace n (V,T) (marked_heap (marked_heap' hp n') n')
= heap_replace (snd(snd(return_smallest_match n (marked_heap (marked_heap' hp n') n'))))(V,T) (marked_heap (marked_heap' hp n') n').
Proof. intros. generalize dependent n. generalize dependent n'. generalize dependent V. generalize dependent T.
induction hp.
Case ("nil"). intros. simpl in H0. inversion H0.
Case ("h::t"). intros. destruct a. simpl. destruct n'. simpl. remember (SecLang.label t) as BB.
destruct BB. simpl. destruct n. simpl. reflexivity. assert (0<=0). apply le_n.
apply return_smallest_match_snd_Sn_n with(hp:=hp)(n:=n) in H1. rewrite->H1. clear H1.
simpl. assert (0<=0). apply le_n. apply add_both_mark_marked_heap_replace with (hp:=hp)(n:=n)(V:=V)(T:=T)in H1.
rewrite->H1. clear H1. assert (0<=0). apply le_n.
apply add_both_mark_heap_replace with (hp:=hp)(n:=snd (snd (return_smallest_match n (marked_heap (marked_heap' hp 0) 0))))(V:=V)(T:=T) in H1.
rewrite->H1. clear H1. specialize (IHhp T V 0 n). simpl in H0. rewrite<-HeqBB in H0. simpl in H0. rewrite->return_smallest_match_Sn_n with (n:=n)(n1:=0)(n2:=0)in H0.
apply IHhp in H0. rewrite->H0. reflexivity. apply IHhp. simpl in H0. rewrite<-HeqBB in H0. apply H0.
simpl.
remember (SecLang.label t) as BB. destruct BB. simpl. destruct n. assert (0<S n'). apply SecLang.n_iff_Sn_left. apply SecLang.zero_n. apply return_true_marked_heap with (hp:=((t,t0)::hp))(n2:=(S n'))in H1.
rewrite<-H1 in H0. clear H1. inversion H0. simpl. remember (beq_nat n' n) as CC. destruct CC.
simpl. rewrite->minus_diag. simpl. reflexivity. rewrite->minus_diag.
assert (S n'<=S n'). apply le_n. apply return_smallest_match_snd_Sn_n with(hp:=hp)(n:=n) in H1. rewrite->H1. clear H1. simpl.
assert (S n'<=S n'). apply le_n. apply add_both_mark_marked_heap_replace with (hp:=hp)(n:=n)(V:=V)(T:=T)in H1.
rewrite->H1. clear H1. assert (S n'<=S n'). apply le_n.
apply add_both_mark_heap_replace with (hp:=hp)(n:=snd (snd (return_smallest_match n (marked_heap (marked_heap' hp (S n')) (S n')))))(V:=V)(T:=T) in H1.
rewrite->H1. clear H1. specialize (IHhp T V (S n') n). simpl in H0. rewrite<-HeqBB in H0. simpl in H0. rewrite<-HeqCC in H0. rewrite->return_smallest_match_Sn_n with (n:=n)(n1:=S n')(n2:=S n')in H0.
apply IHhp in H0. rewrite->H0. reflexivity. apply IHhp. simpl in H0. rewrite<-HeqBB in H0. apply H0.
Qed.
Lemma marked_heap_replace_project_conf'_hp:forall n v T HP HP',
marked_heap_replace n (project_conf'_e v HP',T)(project_conf'_hp HP HP')
=project_conf'_hp (marked_heap_replace n (v,T) HP) HP'.
Proof. intros. generalize dependent n. generalize dependent v. generalize dependent T. generalize dependent HP'.
induction HP.
Case ("nil"). intros. reflexivity.
Case ("h::t"). intros. destruct a. destruct p. destruct p0. simpl. remember (beq_nat n0 n) as BB. destruct BB.
simpl. reflexivity. simpl. specialize (IHHP HP' T v n). rewrite->IHHP. reflexivity.
Qed.
Lemma heap_replace_project_conf'_hp:forall n v T HP HP',
heap_replace n (project_conf'_e v HP',T)(project_conf'_hp HP HP')
=project_conf'_hp (heap_replace n (v,T) HP) HP'.
Proof. intros. generalize dependent n. generalize dependent v. generalize dependent T.
generalize dependent HP'. induction HP.
Case ("nil"). intros. destruct n. reflexivity. reflexivity.
Case ("h::t"). intros. destruct a. destruct p. destruct p0. simpl. destruct n. simpl. reflexivity.
simpl. specialize (IHHP HP' T v n). rewrite->IHHP. reflexivity.
Qed.
Lemma marked_heap_replace_heap_replace:forall n v T hp,
fst (return_smallest_match n (project_hp hp)) = false -> (*restricted to "low to low" case*)
marked_heap_replace n (project_conf'_e (project_e v)(project_conf'_hp (project_hp hp)(project_hp hp)),T) (project_conf'_hp (project_hp hp)(project_hp hp))
= heap_replace (snd(snd(return_smallest_match n (project_conf'_hp (project_hp hp)(project_hp hp)))))
(project_conf'_e (project_e v)(project_conf'_hp (project_hp hp)(project_hp hp)),T)
(project_conf'_hp (project_hp hp)(project_hp hp)).
Proof. intros. assert (same_mark (project_hp hp)(project_conf'_hp (project_hp hp)(project_hp hp))=true). apply same_mark_heap. apply project_conf'_e_same_mark with(t:=project_e v)in H1.
rewrite<-H1. clear H1. rewrite->marked_heap_replace_project_conf'_hp.
assert (same_mark (project_hp hp)(project_conf'_hp (project_hp hp)(project_hp hp))=true). apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=n)in H1.
rewrite<-H1. clear H1. rewrite->heap_replace_project_conf'_hp. unfold project_hp in H0. apply marked_heap_replace_heap_replace' with (V:=project_e v)(T:=T)in H0. unfold project_hp.
rewrite<-H0. reflexivity.
Qed.
Lemma project_conf'_hp_heap_replace':forall v T n hp,
SecLang.value v ->
SecLang.label v = SecLang.label (SecLang.efst (SecLang.heap_lookup n hp))->
fst (return_smallest_match n (project_hp hp)) = false ->
project_conf'_hp (project_hp (SecLang.heap_replace n (v,T) hp))(project_hp (SecLang.heap_replace n (v,T) hp))
=heap_replace (snd(snd(return_smallest_match n (project_conf'_hp (project_hp hp)(project_hp hp)))))
(project_conf'_e (project_e v)(project_conf'_hp (project_hp hp)(project_hp hp)),T)
(project_conf'_hp (project_hp hp)(project_hp hp)).
Proof. intros. apply project_conf'_hp_marked_heap_replace with(T:=T)(n:=n)(hp:=hp) in H0.
apply marked_heap_replace_heap_replace with(v:=v)(T:=T)in H2. rewrite->H2 in H0. apply H0. apply return_smallest_match_F_length in H2.
apply H2. apply H1.
Qed.
Lemma project_conf'_hp_heap_replace'':forall N V T HP,
erase_hp (heap_replace N (V,T) HP)
=LowLang.heap_replace N (V,T)(erase_hp HP).
Proof. intros. generalize dependent N. generalize dependent V. generalize dependent T.
induction HP.
Case ("nil"). intros. destruct N. reflexivity. reflexivity.
Case ("h::t"). intros. destruct a. destruct p. destruct N. simpl. reflexivity.
simpl. specialize (IHHP T V N). rewrite->IHHP. reflexivity.
Qed.
Lemma project_conf'_hp_heap_replace:forall v T n hp,
SecLang.value v ->
SecLang.label v = SecLang.label (SecLang.efst (SecLang.heap_lookup n hp))->
fst (return_smallest_match n (project_hp hp)) = false ->
erase_hp (project_conf'_hp (project_hp (SecLang.heap_replace n (v,T) hp))(project_hp (SecLang.heap_replace n (v,T) hp)))
=LowLang.heap_replace (snd(snd(return_smallest_match n (project_hp hp))))
(project_conf'_e (project_e v)(project_conf'_hp (project_hp hp)(project_hp hp)),T)
(erase_hp (project_conf'_hp (project_hp hp)(project_hp hp))).
Proof. intros. assert (same_mark (project_hp hp)(project_conf'_hp (project_hp hp)(project_hp hp))=true). apply same_mark_heap.
apply return_smallest_match_same_mark' with (n:=n)in H3. rewrite->H3. clear H3. rewrite<-project_conf'_hp_heap_replace''.
apply project_conf'_hp_heap_replace' with(T:=T)(n:=n)(hp:=hp)in H0. rewrite<-H0. reflexivity.
apply H1. apply H2.
Qed.
Lemma return_smallest_match_snd_length:forall n hp,
fst (return_smallest_match n (marked_heap(marked_heap' hp 0)0)) = false ->
snd(snd(return_smallest_match n (marked_heap(marked_heap' hp 0)0))) < length (marked_heap(marked_heap' hp 0)0).
Proof. intros. generalize dependent n. induction hp.
Case ("nil"). intros. simpl in H0. inversion H0.
Case ("h::t"). intros. destruct a. simpl. remember (SecLang.label t) as BB. destruct BB. simpl. destruct n. simpl.
apply SecLang.n_iff_Sn_left. apply SecLang.zero_n. assert (0<=0). apply le_n.
apply return_smallest_match_snd_Sn_n with (hp:=hp)(n:=n) in H1. rewrite->H1. clear H1. apply SecLang.n_iff_Sn_left.
rewrite->marked_heap_mark_length with (n3:=0)(n4:=0). simpl in H0. rewrite<-HeqBB in H0. simpl in H0.
rewrite->return_smallest_match_Sn_n with (n2:=0)in H0. apply IHhp. apply H0. simpl in H0. rewrite<-HeqBB in H0.
destruct n. assert (0<1). apply le_n. apply return_true_marked_heap with (hp:=hp)(n2:=1)in H1. rewrite<-H1 in H0. clear H1.
inversion H0. assert (fst (return_smallest_match (S n)(marked_heap(marked_heap' hp 1)1))=false). apply H0.
rewrite->return_smallest_match_Sn_Sn with(n2:=0)in H1. apply return_smallest_match_snd_Sn_Sn in H1.
rewrite->H1. clear H1. rewrite->marked_heap_mark_length with(n3:=0)(n4:=0). apply IHhp.
rewrite->return_smallest_match_Sn_Sn with(n2:=0)in H0. apply H0.
Qed.
(*##################*)
Lemma corresp_step:forall e e' hp hp',
SecLang.step (e,hp) L (e',hp') ->
LowLang.Multi LowLang.step (project (e,hp)) L (project (e',hp')).
Proof. intros. induction H0. (*induction upon the reduction relation in [SecLang]*)
Case ("st_prot").
intros. destruct b. simpl. destruct PC. simpl in H0. apply IHstep. simpl in IHstep. apply IHstep.
destruct PC. simpl in IHstep. unfold project. simpl. simpl in H0. apply proj_hp_H_same in H2. rewrite->H2.
apply LowLang.Multi_refl.
unfold project. simpl. simpl in H2. apply proj_hp_H_same in H2. rewrite->H2. apply LowLang.Multi_refl.
Case ("st_protv").
destruct b. unfold project. simpl. inversion H2.
rewrite->SecLang.join_tcon_b. rewrite->SecLang.joins_refl. simpl. apply LowLang.Multi_refl. rewrite->SecLang.join_tabs_b.
rewrite->SecLang.joins_refl. simpl. apply LowLang.Multi_refl. rewrite->SecLang.join_tunit_b. rewrite->SecLang.joins_refl.
simpl. apply LowLang.Multi_refl. rewrite->SecLang.join_tloc_b. rewrite->SecLang.joins_refl. simpl. apply LowLang.Multi_refl.
inversion H2. rewrite->SecLang.join_tcon_b. rewrite->SecLang.joins_refl. simpl. apply LowLang.Multi_refl.
rewrite->SecLang.join_tabs_b. rewrite->SecLang.joins_refl. simpl. apply LowLang.Multi_refl. rewrite->SecLang.join_tunit_b.
rewrite->SecLang.joins_refl. simpl. apply LowLang.Multi_refl. rewrite->SecLang.join_tloc_b. rewrite->SecLang.joins_refl. simpl.
apply LowLang.Multi_refl.
Case ("st_appabs").
destruct b. unfold project. simpl. unfold project_conf. simpl. rewrite->project_e_subst. rewrite->project_conf'_subst.
apply LowLang.Multi_step with (y:=(LowLang.subst x
(project_conf'_e (project_e v)
(project_conf'_hp (project_hp hp0) (project_hp hp0)))
(project_conf'_e (project_e e0)
(project_conf'_hp (project_hp hp0) (project_hp hp0))),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))).
apply LowLang.st_appabs. apply SecLang_value_LowLang. apply H3. apply LowLang.Multi_refl. apply H3. unfold project. simpl. unfold project_conf.
simpl. apply LowLang.Multi_step with (y:=(LowLang.tH,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))). apply LowLang.st_apptH.
apply SecLang_value_LowLang. apply H3. apply LowLang.Multi_refl.
Case ("st_app1").
unfold project. unfold project_conf. unfold project in IHstep. unfold project_conf in IHstep. simpl. simpl in IHstep.
destruct PC.
SCase ("PC:=L"). apply step_same_mark_or_extend in H3. inversion H3.
(*case one: two heaps of the same length with identical marks*)
assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap.
assert (same_mark (project_conf'_hp (project_hp hp0) (project_hp hp0))(project_hp hp'0) = true). apply same_mark_replace with (hp1:=project_hp hp0).
apply H4. apply H5. apply same_mark_sym in H6. assert (same_mark (project_hp hp'0)(project_conf'_hp (project_hp hp'0) (project_hp hp'0)) = true).
apply same_mark_heap. assert (same_mark (project_conf'_hp (project_hp hp0) (project_hp hp0))(project_conf'_hp (project_hp hp'0) (project_hp hp'0)) = true).
apply same_mark_replace with (hp1:=project_hp hp'0). apply H7. apply H6. apply project_conf'_e_same_mark with (t:=project_e t2)in H8. rewrite->H8. clear H4.
clear H5. clear H6. clear H7. clear H8.
assert (fst (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)))). reflexivity. rewrite<-H4. clear H4.
assert (snd (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))).
reflexivity. rewrite<-H4. clear H4.
assert (fst (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)))). reflexivity. rewrite<-H4. clear H4.
assert (snd (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))).
reflexivity. rewrite<-H4. clear H4. apply multi_step_app1. apply IHstep.
(*case two: after reduction heap is expanded by one low value*)
inversion H4. assert (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)) = project_conf'_e (project_e t2)
(project_conf'_hp ((LowLang.snoc (project_hp hp0) (x, (length hp0, length (project_hp hp0))))) ((LowLang.snoc (project_hp hp0) (x, (length hp0, length (project_hp hp0))))))).
rewrite<-H5. reflexivity. rewrite->H6. assert ((project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0))) = (project_conf'_e (project_e t2)
(project_conf'_hp
(LowLang.snoc (project_hp hp0)
(x, (length hp0, length (project_hp hp0))))
(LowLang.snoc (project_hp hp0)
(x, (length hp0, length (project_hp hp0))))))). apply project_conf'_e_add_one_low. apply H2. rewrite<-H7. clear H5. clear H6. clear H7.
assert (fst (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)))). reflexivity. rewrite<-H5. clear H5.
assert (snd (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))).
reflexivity. rewrite<-H5. clear H5.
assert (fst (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)))). reflexivity. rewrite<-H5. clear H5.
assert (snd (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))).
reflexivity. rewrite<-H5. clear H5. apply multi_step_app1. apply IHstep.
SCase ("PC:=H"). apply proj_hp_H_same in H3. assert (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)) = project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp'0) (project_hp hp'0))). rewrite->H3. reflexivity. rewrite->H4. clear H4.
assert (fst (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)))). reflexivity. rewrite<-H4. clear H4.
assert (snd (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))).
reflexivity. rewrite<-H4. clear H4.
assert (fst (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)))). reflexivity. rewrite<-H4. clear H4.
assert (snd (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))).
reflexivity. rewrite<-H4. clear H4. apply multi_step_app1. apply IHstep.
Case ("tapp2").
unfold project. unfold project_conf. unfold project in IHstep. unfold project_conf in IHstep. simpl. simpl in IHstep.
destruct PC.
SCase ("PC:=L"). apply step_same_mark_or_extend in H4. inversion H4.
(*case one: two heaps of the same length with identical marks*)
assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap.
assert (same_mark (project_conf'_hp (project_hp hp0) (project_hp hp0))(project_hp hp'0) = true). apply same_mark_replace with (hp1:=project_hp hp0).
apply H5. apply H6. apply same_mark_sym in H7. assert (same_mark (project_hp hp'0)(project_conf'_hp (project_hp hp'0) (project_hp hp'0)) = true).
apply same_mark_heap. assert (same_mark (project_conf'_hp (project_hp hp0) (project_hp hp0))(project_conf'_hp (project_hp hp'0) (project_hp hp'0)) = true).
apply same_mark_replace with (hp1:=project_hp hp'0). apply H8. apply H7. apply project_conf'_e_same_mark with (t:=project_e v1)in H9. rewrite->H9. clear H5.
clear H6. clear H7. clear H8. clear H9.
assert (fst (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)))). reflexivity. rewrite<-H5. clear H5.
assert (snd (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))).
reflexivity. rewrite<-H5. clear H5.
assert (fst (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)))). reflexivity. rewrite<-H5. clear H5.
assert (snd (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))).
reflexivity. rewrite<-H5. clear H5. apply multi_step_app2. apply SecLang_value_LowLang. apply H3.
apply IHstep.
(*case two: after reduction heap is expanded by one low value*)
inversion H5. assert (project_conf'_e (project_e v1)
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)) = project_conf'_e (project_e v1)
(project_conf'_hp ((LowLang.snoc (project_hp hp0) (x, (length hp0, length (project_hp hp0))))) ((LowLang.snoc (project_hp hp0) (x, (length hp0, length (project_hp hp0))))))).
rewrite<-H6. reflexivity. rewrite->H7. assert ((project_conf'_e (project_e v1)
(project_conf'_hp (project_hp hp0) (project_hp hp0))) = (project_conf'_e (project_e v1)
(project_conf'_hp
(LowLang.snoc (project_hp hp0)
(x, (length hp0, length (project_hp hp0))))
(LowLang.snoc (project_hp hp0)
(x, (length hp0, length (project_hp hp0))))))). apply project_conf'_e_add_one_low. apply H1. rewrite<-H8. clear H6. clear H7. clear H8.
assert (fst (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)))). reflexivity. rewrite<-H6. clear H6.
assert (snd (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))).
reflexivity. rewrite<-H6. clear H6.
assert (fst (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)))). reflexivity. rewrite<-H6. clear H6.
assert (snd (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))).
reflexivity. rewrite<-H6. clear H6. apply multi_step_app2. apply SecLang_value_LowLang. apply H3.
apply IHstep.
SCase ("PC:=H"). apply proj_hp_H_same in H4. assert (project_conf'_e (project_e v1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)) = project_conf'_e (project_e v1)
(project_conf'_hp (project_hp hp'0) (project_hp hp'0))). rewrite->H4. reflexivity. rewrite->H5. clear H5.
assert (fst (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)))). reflexivity. rewrite<-H5. clear H5.
assert (snd (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))).
reflexivity. rewrite<-H5. clear H5.
assert (fst (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)))). reflexivity. rewrite<-H5. clear H5.
assert (snd (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))).
reflexivity. rewrite<-H5. clear H5. apply multi_step_app2. apply SecLang_value_LowLang. apply H3. apply IHstep.
Case ("st_refv").
subst. destruct b.
unfold project. unfold project_conf. simpl.
inversion H2.
(*v=SecLang.tcon n b*)
destruct b. destruct T. destruct s. destruct PC. simpl. rewrite->SecLang.join_tcon_b. simpl. subst.
apply project_hp_Lextend with (hp:=hp0)(T:=an r L) in H2. rewrite->H2. simpl. assert (LowLang.value (LowLang.tcon n)). apply LowLang.v_c. apply return_smallest_match_snoc with (hp:=hp0)(T:=an r L) in H3.
rewrite->H3. simpl. assert (Some (length (project_hp hp0)) = Some (length (project_conf'_hp(project_hp hp0)(project_hp hp0)))). rewrite->project_conf'_hp_length. reflexivity. rewrite->H4. clear H4.
assert (Some (length (project_conf'_hp(project_hp hp0)(project_hp hp0))) = Some (length (erase_hp (project_conf'_hp(project_hp hp0)(project_hp hp0))))). rewrite->erase_hp_length. reflexivity. rewrite->H4.
clear H4. rewrite->project_conf'_hp_snoc. simpl. apply project_conf'_hp_add_one_low with (L0:=(LowLang.tcon n,an r L))in H0. rewrite->H0. apply LowLang.Multi_step with (y:=(LowLang.tloc (an r L)
(Some
(length
(erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))))),
erase_hp
(LowLang.snoc (project_conf'_hp (project_hp hp0) (project_hp hp0))
(LowLang.tcon n, an r L, (length hp0, length (project_hp hp0)))))). apply LowLang.st_refv. apply LowLang.v_c. intros contra. inversion contra. reflexivity. reflexivity.
rewrite->erase_hp_snoc. reflexivity. apply LowLang.Multi_refl. intros contra. inversion contra. reflexivity. simpl. subst. apply project_hp_Hextend with(hp:=hp0)(T:=an r L) in H2.
rewrite<-H2. assert (same_mark (project_conf'_hp (project_hp hp0)(project_hp hp0))(project_hp hp0) = true). apply same_mark_sym. apply same_mark_heap. apply return_smallest_match_same_mark with (n:=length hp0)in H3. rewrite->H3.
rewrite->return_smallest_match_true. clear H3. assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=length hp0)in H3. rewrite<-H3.
rewrite->return_smallest_match_true. simpl. apply LowLang.Multi_step with (y:=(LowLang.tloc (an r L) None,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))). apply LowLang.st_reftH. apply LowLang.v_c. right. left. reflexivity. apply LowLang.Multi_refl. simpl. subst. apply project_hp_Hextend with(hp:=hp0)(T:=an r H) in H2. rewrite<-H2.
assert (same_mark (project_conf'_hp (project_hp hp0)(project_hp hp0))(project_hp hp0) = true). apply same_mark_sym. apply same_mark_heap. apply return_smallest_match_same_mark with (n:=length hp0)in H3. rewrite->H3.
rewrite->return_smallest_match_true. clear H3. assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=length hp0)in H3. rewrite<-H3.
rewrite->return_smallest_match_true. simpl. apply LowLang.Multi_step with (y:=((LowLang.tloc (an r H) None,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))))). apply LowLang.st_reftH. apply LowLang.v_c. right. right. reflexivity. apply LowLang.Multi_refl. subst. rewrite->SecLang.join_tcon_b. simpl. assert (SecLang.joinvs (SecLang.tcon n L) H = SecLang.tcon n H). reflexivity.
rewrite<-H3. clear H3. assert (SecLang.value (SecLang.tcon n L)). apply SecLang.v_c. apply project_hp_Hextend with(hp:=hp0)(T:=T) in H3. rewrite<-H3. clear H3.
assert (same_mark (project_conf'_hp (project_hp hp0)(project_hp hp0))(project_hp hp0) = true). apply same_mark_sym. apply same_mark_heap. apply return_smallest_match_same_mark with (n:=length hp0)in H3. rewrite->H3.
rewrite->return_smallest_match_true. clear H3. assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=length hp0)in H3. rewrite<-H3.
rewrite->return_smallest_match_true. simpl. apply LowLang.Multi_step with (y:=((LowLang.tloc T None,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))))). apply LowLang.st_reftH. apply LowLang.v_H. left. reflexivity. apply LowLang.Multi_refl.
(*v=SecLang.tabs (Id n) T0 e0 b*)
destruct b. destruct T. destruct s. destruct PC. simpl. rewrite->SecLang.join_tabs_b. simpl. subst.
apply project_hp_Lextend with (hp:=hp0)(T:=an r L) in H2. rewrite->H2. simpl. assert (LowLang.value (LowLang.tabs (Id n) T0 (project_e e0))). apply LowLang.v_f. apply return_smallest_match_snoc with (hp:=hp0)(T:=an r L) in H3.
rewrite->H3. simpl. assert (Some (length (project_hp hp0)) = Some (length (project_conf'_hp(project_hp hp0)(project_hp hp0)))). rewrite->project_conf'_hp_length. reflexivity. rewrite->H4. clear H4.
assert (Some (length (project_conf'_hp(project_hp hp0)(project_hp hp0))) = Some (length (erase_hp (project_conf'_hp(project_hp hp0)(project_hp hp0))))). rewrite->erase_hp_length. reflexivity. rewrite->H4.
clear H4. rewrite->project_conf'_hp_snoc. simpl. apply project_conf'_hp_add_one_low with (L0:=(LowLang.tabs (Id n) T0 (project_e e0),an r L))in H0. rewrite->H0. apply LowLang.Multi_step with (y:= (LowLang.tloc (an r L)
(Some
(length
(erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))))),
erase_hp
(LowLang.snoc (project_conf'_hp (project_hp hp0) (project_hp hp0))
(LowLang.tabs (Id n) T0
(project_conf'_e (project_e e0)
(LowLang.snoc (project_hp hp0)
(LowLang.tabs (Id n) T0 (project_e e0), an r L,
(length hp0, length (project_hp hp0))))), an r L,
(length hp0, length (project_hp hp0)))))).
apply LowLang.st_refv. apply LowLang.v_f. intros contra. inversion contra. reflexivity. reflexivity.
rewrite->erase_hp_snoc. inversion H1. subst. apply SecLow_well_formed in H9. apply project_conf'_e_add_one_low' with(Hp:=project_hp hp0)(L0:=(LowLang.tabs (Id n) T0 (project_e e0),an r L)) in H9. rewrite<-H9.
assert (same_mark (project_conf'_hp (project_hp hp0)(project_hp hp0))(project_hp hp0) = true). apply same_mark_sym. apply same_mark_heap. apply project_conf'_e_same_mark with (t:=project_e e0) in H4. rewrite->H4.
clear H4.
reflexivity. apply LowLang.Multi_refl. intros contra. inversion contra. reflexivity. simpl. subst. apply project_hp_Hextend with(hp:=hp0)(T:=an r L) in H2.
rewrite<-H2. assert (same_mark (project_conf'_hp (project_hp hp0)(project_hp hp0))(project_hp hp0) = true). apply same_mark_sym. apply same_mark_heap. apply return_smallest_match_same_mark with (n:=length hp0)in H3. rewrite->H3.
rewrite->return_smallest_match_true. clear H3. assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=length hp0)in H3. rewrite<-H3.
rewrite->return_smallest_match_true. simpl. apply LowLang.Multi_step with (y:=(LowLang.tloc (an r L) None,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))). apply LowLang.st_reftH. apply LowLang.v_f. right. left. reflexivity. apply LowLang.Multi_refl. simpl. subst. apply project_hp_Hextend with(hp:=hp0)(T:=an r H) in H2. rewrite<-H2.
assert (same_mark (project_conf'_hp (project_hp hp0)(project_hp hp0))(project_hp hp0) = true). apply same_mark_sym. apply same_mark_heap. apply return_smallest_match_same_mark with (n:=length hp0)in H3. rewrite->H3.
rewrite->return_smallest_match_true. clear H3. assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=length hp0)in H3. rewrite<-H3.
rewrite->return_smallest_match_true. simpl. apply LowLang.Multi_step with (y:=((LowLang.tloc (an r H) None,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))))). apply LowLang.st_reftH. apply LowLang.v_f. right. right. reflexivity. apply LowLang.Multi_refl. subst. rewrite->SecLang.join_tabs_b. simpl. assert (SecLang.joinvs (SecLang.tabs (Id n) T0 e0 L) H = SecLang.tabs (Id n) T0 e0 H). reflexivity.
rewrite<-H3. clear H3. assert (SecLang.value (SecLang.tabs (Id n) T0 e0 L)). apply SecLang.v_f. apply project_hp_Hextend with(hp:=hp0)(T:=T) in H3. rewrite<-H3. clear H3.
assert (same_mark (project_conf'_hp (project_hp hp0)(project_hp hp0))(project_hp hp0) = true). apply same_mark_sym. apply same_mark_heap. apply return_smallest_match_same_mark with (n:=length hp0)in H3. rewrite->H3.
rewrite->return_smallest_match_true. clear H3. assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=length hp0)in H3. rewrite<-H3.
rewrite->return_smallest_match_true. simpl. apply LowLang.Multi_step with (y:=((LowLang.tloc T None,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))))). apply LowLang.st_reftH. apply LowLang.v_H. left. reflexivity. apply LowLang.Multi_refl.
(*v=tunit b*)
destruct b. destruct T. destruct s. destruct PC. simpl. rewrite->SecLang.join_tunit_b. simpl. subst.
apply project_hp_Lextend with (hp:=hp0)(T:=an r L) in H2. rewrite->H2. simpl. assert (LowLang.value (LowLang.tunit)). apply LowLang.v_u. apply return_smallest_match_snoc with (hp:=hp0)(T:=an r L) in H3.
rewrite->H3. simpl. assert (Some (length (project_hp hp0)) = Some (length (project_conf'_hp(project_hp hp0)(project_hp hp0)))). rewrite->project_conf'_hp_length. reflexivity. rewrite->H4. clear H4.
assert (Some (length (project_conf'_hp(project_hp hp0)(project_hp hp0))) = Some (length (erase_hp (project_conf'_hp(project_hp hp0)(project_hp hp0))))). rewrite->erase_hp_length. reflexivity. rewrite->H4.
clear H4. rewrite->project_conf'_hp_snoc. simpl. apply project_conf'_hp_add_one_low with (L0:=(LowLang.tunit,an r L))in H0. rewrite->H0. apply LowLang.Multi_step with (y:=(LowLang.tloc (an r L)
(Some
(length
(erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))))),
erase_hp
(LowLang.snoc (project_conf'_hp (project_hp hp0) (project_hp hp0))
(LowLang.tunit, an r L, (length hp0, length (project_hp hp0)))))). apply LowLang.st_refv. apply LowLang.v_u. intros contra. inversion contra. reflexivity. reflexivity.
rewrite->erase_hp_snoc. reflexivity. apply LowLang.Multi_refl. intros contra. inversion contra. reflexivity. simpl. subst. apply project_hp_Hextend with(hp:=hp0)(T:=an r L) in H2.
rewrite<-H2. assert (same_mark (project_conf'_hp (project_hp hp0)(project_hp hp0))(project_hp hp0) = true). apply same_mark_sym. apply same_mark_heap. apply return_smallest_match_same_mark with (n:=length hp0)in H3. rewrite->H3.
rewrite->return_smallest_match_true. clear H3. assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=length hp0)in H3. rewrite<-H3.
rewrite->return_smallest_match_true. simpl. apply LowLang.Multi_step with (y:=(LowLang.tloc (an r L) None,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))). apply LowLang.st_reftH. apply LowLang.v_u. right. left. reflexivity. apply LowLang.Multi_refl. simpl. subst. apply project_hp_Hextend with(hp:=hp0)(T:=an r H) in H2. rewrite<-H2.
assert (same_mark (project_conf'_hp (project_hp hp0)(project_hp hp0))(project_hp hp0) = true). apply same_mark_sym. apply same_mark_heap. apply return_smallest_match_same_mark with (n:=length hp0)in H3. rewrite->H3.
rewrite->return_smallest_match_true. clear H3. assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=length hp0)in H3. rewrite<-H3.
rewrite->return_smallest_match_true. simpl. apply LowLang.Multi_step with (y:=((LowLang.tloc (an r H) None,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))))). apply LowLang.st_reftH. apply LowLang.v_u. right. right. reflexivity. apply LowLang.Multi_refl. subst. rewrite->SecLang.join_tunit_b. simpl. assert (SecLang.joinvs (SecLang.tunit L) H = SecLang.tunit H). reflexivity.
rewrite<-H3. clear H3. assert (SecLang.value (SecLang.tunit L)). apply SecLang.v_u. apply project_hp_Hextend with(hp:=hp0)(T:=T) in H3. rewrite<-H3. clear H3.
assert (same_mark (project_conf'_hp (project_hp hp0)(project_hp hp0))(project_hp hp0) = true). apply same_mark_sym. apply same_mark_heap. apply return_smallest_match_same_mark with (n:=length hp0)in H3. rewrite->H3.
rewrite->return_smallest_match_true. clear H3. assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=length hp0)in H3. rewrite<-H3.
rewrite->return_smallest_match_true. simpl. apply LowLang.Multi_step with (y:=((LowLang.tloc T None,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))))). apply LowLang.st_reftH. apply LowLang.v_H. left. reflexivity. apply LowLang.Multi_refl.
(*v = SecLang.tloc T0 (Some n) b *)
destruct b. destruct T. destruct s. destruct PC. simpl. rewrite->SecLang.join_tloc_b. simpl. subst.
apply project_hp_Lextend with (hp:=hp0)(T:=an r L) in H2. rewrite->H2. simpl. assert (LowLang.value (LowLang.tloc T0 (Some n))). apply LowLang.v_l. apply return_smallest_match_snoc with (hp:=hp0)(T:=an r L) in H3.
rewrite->H3. simpl. assert (Some (length (project_hp hp0)) = Some (length (project_conf'_hp(project_hp hp0)(project_hp hp0)))). rewrite->project_conf'_hp_length. reflexivity. rewrite->H4. clear H4.
assert (Some (length (project_conf'_hp(project_hp hp0)(project_hp hp0))) = Some (length (erase_hp (project_conf'_hp(project_hp hp0)(project_hp hp0))))). rewrite->erase_hp_length. reflexivity. rewrite->H4.
clear H4. rewrite->project_conf'_hp_snoc. simpl. apply project_conf'_hp_add_one_low with (L0:=(LowLang.tloc T0 (Some n),an r L))in H0. rewrite->H0. inversion H1. subst. assert (n<>length hp0). intros contra. rewrite<-contra in H8. apply LowLang.lt_same_F in H8. inversion H8.
apply return_smallest_match_not_hit_snoc with (n3:=length (project_hp hp0))(L:=(LowLang.tloc T0 (Some n),an r L))(hp:=project_hp hp0) in H4. rewrite->H4. assert (same_mark (project_conf'_hp (project_hp hp0)(project_hp hp0))(project_hp hp0) = true). apply same_mark_sym. apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=n)in H5. rewrite->H5.
clear H5.
apply LowLang.Multi_step with (y:=(LowLang.tloc (an r L)
(Some
(length
(erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))))),
erase_hp
(LowLang.snoc (project_conf'_hp (project_hp hp0) (project_hp hp0))
(if fst (return_smallest_match n (project_hp hp0))
then LowLang.tloc T0 None
else
LowLang.tloc T0
(Some (snd (snd (return_smallest_match n (project_hp hp0))))),
an r L, (length hp0, length (project_hp hp0)))))). apply LowLang.st_refv. remember (fst (return_smallest_match n (project_hp hp0))) as BB. destruct BB.
apply LowLang.v_l. apply LowLang.v_l. remember (fst (return_smallest_match n (project_hp hp0))) as BB. destruct BB.
intros contra. inversion contra. intros contra. inversion contra. reflexivity. reflexivity.
rewrite->erase_hp_snoc. reflexivity. apply LowLang.Multi_refl. intros contra. inversion contra. reflexivity. simpl. subst. apply project_hp_Hextend with(hp:=hp0)(T:=an r L) in H2.
rewrite<-H2. assert (same_mark (project_conf'_hp (project_hp hp0)(project_hp hp0))(project_hp hp0) = true). apply same_mark_sym. apply same_mark_heap. apply return_smallest_match_same_mark with (n:=length hp0)in H3. rewrite->H3.
rewrite->return_smallest_match_true. clear H3. assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=length hp0)in H3. rewrite<-H3.
rewrite->return_smallest_match_true. simpl. assert (same_mark (project_conf'_hp (project_hp hp0)(project_hp hp0))(project_hp hp0) = true). apply same_mark_sym. apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=n)in H4. rewrite->H4.
clear H4. clear H3. remember (fst (return_smallest_match n (project_hp hp0))) as BB. destruct BB.
apply LowLang.Multi_step with (y:=(LowLang.tloc (an r L) None,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))). apply LowLang.st_reftH. apply LowLang.v_l. right. left. reflexivity.
apply LowLang.Multi_refl.
apply LowLang.Multi_step with (y:=(LowLang.tloc (an r L) None,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))). apply LowLang.st_reftH. apply LowLang.v_l. right. left. reflexivity.
apply LowLang.Multi_refl.
simpl. subst. apply project_hp_Hextend with(hp:=hp0)(T:=an r H) in H2. rewrite<-H2.
assert (same_mark (project_conf'_hp (project_hp hp0)(project_hp hp0))(project_hp hp0) = true). apply same_mark_sym. apply same_mark_heap. apply return_smallest_match_same_mark with (n:=length hp0)in H3. rewrite->H3.
rewrite->return_smallest_match_true. clear H3. assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=length hp0)in H3. rewrite<-H3.
rewrite->return_smallest_match_true. simpl.
assert (same_mark (project_conf'_hp (project_hp hp0)(project_hp hp0))(project_hp hp0) = true). apply same_mark_sym. apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=n)in H4. rewrite->H4.
clear H4. clear H3. remember (fst (return_smallest_match n (project_hp hp0))) as BB. destruct BB.
apply LowLang.Multi_step with (y:=((LowLang.tloc (an r H) None,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))))). apply LowLang.st_reftH. apply LowLang.v_l. right. right. reflexivity. apply LowLang.Multi_refl.
apply LowLang.Multi_step with (y:=((LowLang.tloc (an r H) None,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))))). apply LowLang.st_reftH. apply LowLang.v_l. right. right. reflexivity. apply LowLang.Multi_refl.
subst. rewrite->SecLang.join_tloc_b. simpl. assert (SecLang.joinvs (SecLang.tloc T0 (Some n) L) H = SecLang.tloc T0 (Some n) H). reflexivity.
rewrite<-H3. clear H3. assert (SecLang.value (SecLang.tloc T0 (Some n) L)). apply SecLang.v_l. apply project_hp_Hextend with(hp:=hp0)(T:=T) in H3. rewrite<-H3. clear H3.
assert (same_mark (project_conf'_hp (project_hp hp0)(project_hp hp0))(project_hp hp0) = true). apply same_mark_sym. apply same_mark_heap. apply return_smallest_match_same_mark with (n:=length hp0)in H3. rewrite->H3.
rewrite->return_smallest_match_true. clear H3. assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=length hp0)in H3. rewrite<-H3.
rewrite->return_smallest_match_true. simpl. apply LowLang.Multi_step with (y:=((LowLang.tloc T None,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))))). apply LowLang.st_reftH. apply LowLang.v_H. left. reflexivity. apply LowLang.Multi_refl.
(*high pointer*)
unfold project. unfold project_conf. simpl. rewrite->SecLang.joins_refl. simpl. apply project_hp_Hextend with(hp:=hp0)(T:=T) in H2. rewrite<-H2. apply LowLang.Multi_refl.
Case ("st_ref").
destruct b. destruct PC. simpl in H2. unfold project. unfold project_conf. simpl. unfold project in IHstep. unfold project_conf in IHstep. simpl in IHstep.
assert (fst ( (project_conf'_e (project_e t)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))) = (project_conf'_e (project_e t)(project_conf'_hp (project_hp hp0) (project_hp hp0)))). reflexivity. rewrite<-H3. clear H3.
assert (snd ( (project_conf'_e (project_e t)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))) =erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)) ). reflexivity. rewrite<-H3. clear H3.
assert (fst ((project_conf'_e (project_e t')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0)))) =(project_conf'_e (project_e t')(project_conf'_hp (project_hp hp'0) (project_hp hp'0))) ). reflexivity. rewrite<-H3. clear H3.
assert (snd ((project_conf'_e (project_e t')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0)))) = erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0)) ). reflexivity. rewrite<-H3. clear H3.
apply multi_step_ref. apply IHstep. simpl in H2.
simpl in IHstep. unfold project. unfold project_conf. simpl. unfold project in IHstep. unfold project_conf in IHstep. simpl in IHstep.
assert (fst ( (project_conf'_e (project_e t)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))) = (project_conf'_e (project_e t)(project_conf'_hp (project_hp hp0) (project_hp hp0)))). reflexivity. rewrite<-H3. clear H3.
assert (snd ( (project_conf'_e (project_e t)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))) =erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)) ). reflexivity. rewrite<-H3. clear H3.
assert (fst ((project_conf'_e (project_e t')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0)))) =(project_conf'_e (project_e t')(project_conf'_hp (project_hp hp'0) (project_hp hp'0))) ). reflexivity. rewrite<-H3. clear H3.
assert (snd ((project_conf'_e (project_e t')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0)))) = erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0)) ). reflexivity. rewrite<-H3. clear H3.
apply multi_step_ref. apply IHstep. rewrite->SecLang.joins_refl in H2. simpl in H2. unfold project. simpl. apply proj_hp_H_same in H2. rewrite->H2. apply LowLang.Multi_refl.
Case ("st_derefloc").
destruct b. unfold project. unfold project_conf. simpl.
assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap. apply return_smallest_match_same_mark' with (n:=n)in H3. rewrite<-H3. clear H3.
assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap. apply project_conf'_e_same_mark with (t:=project_e t) in H3. rewrite<-H3. clear H3.
remember (fst (return_smallest_match n (project_hp hp0))) as BB. destruct BB. rewrite->H2. apply return_smallest_match_project_e_true in H1. rewrite->H1. apply LowLang.Multi_step with (y:=(project_conf'_e LowLang.tH (project_hp hp0),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))). apply LowLang.st_derefloctH. apply LowLang.Multi_refl. symmetry. apply HeqBB. unfold project_hp in HeqBB.
apply LowLang.Multi_step with (y:=(project_conf'_e (project_e t) (project_hp hp0),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))). apply LowLang.st_derefloc. (*referring to [marked_heap_value_tws]*)
apply cs_derefloc_two in H2. assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0))=true). apply same_mark_heap.
apply return_smallest_match_same_mark' with (n:=n) in H3. rewrite<-H3 in H2. clear H3. symmetry in H2. apply heap_lookup_n_length in H2.
rewrite->erase_hp_length. apply H2. apply HeqBB.
apply cs_derefloc in H2. apply H2. apply HeqBB. apply LowLang.Multi_refl.
unfold project. unfold project_conf. simpl. apply LowLang.Multi_step with (y:=(LowLang.tH, erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))). apply LowLang.st_dereftH. apply LowLang.Multi_refl.
Case ("st_deref").
destruct PC. unfold project. unfold project_conf. simpl. unfold project in IHstep. unfold project_conf in IHstep. simpl in IHstep.
assert (fst ( (project_conf'_e (project_e t)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))) = (project_conf'_e (project_e t)(project_conf'_hp (project_hp hp0) (project_hp hp0)))). reflexivity. rewrite<-H3. clear H3.
assert (snd ( (project_conf'_e (project_e t)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))) =erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)) ). reflexivity. rewrite<-H3. clear H3.
assert (fst ((project_conf'_e (project_e t')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0)))) =(project_conf'_e (project_e t')(project_conf'_hp (project_hp hp'0) (project_hp hp'0))) ). reflexivity. rewrite<-H3. clear H3.
assert (snd ((project_conf'_e (project_e t')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0)))) = erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0)) ). reflexivity. rewrite<-H3. clear H3.
apply multi_step_deref. apply IHstep.
unfold project. unfold project_conf. simpl. unfold project in IHstep. unfold project_conf in IHstep. simpl in IHstep.
assert (fst ( (project_conf'_e (project_e t)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))) = (project_conf'_e (project_e t)(project_conf'_hp (project_hp hp0) (project_hp hp0)))). reflexivity. rewrite<-H3. clear H3.
assert (snd ( (project_conf'_e (project_e t)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))) =erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)) ). reflexivity. rewrite<-H3. clear H3.
assert (fst ((project_conf'_e (project_e t')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0)))) =(project_conf'_e (project_e t')(project_conf'_hp (project_hp hp'0) (project_hp hp'0))) ). reflexivity. rewrite<-H3. clear H3.
assert (snd ((project_conf'_e (project_e t')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0)))) = erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0)) ). reflexivity. rewrite<-H3. clear H3.
apply multi_step_deref. apply IHstep.
Case ("st_assign").
unfold project. unfold project_conf. destruct PC. destruct b. destruct l. destruct b'. simpl. simpl in H6. rewrite->H6. simpl. simpl in H7.
(*low cell being over-written by a low value*)
apply return_smallest_match_project_hp_hit in H2. assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0))=true). apply same_mark_heap.
apply return_smallest_match_same_mark' with (n:=n) in H13. rewrite<-H13. clear H13. rewrite->H2.
apply LowLang.Multi_step with (y:=(LowLang.tunit,
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0)))). apply LowLang.st_assign. rewrite->erase_hp_length. assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0))=true).
apply same_mark_heap. apply same_mark_length in H13. rewrite<-H13. clear H13. unfold project_hp. apply return_smallest_match_snd_length. apply H2.
apply SecLang_value_LowLang. apply H3. intros contra. inversion H3.
(*tcon*) subst. compute in H4. subst. simpl in contra. inversion contra.
(*tabs*) subst. compute in H4. subst. simpl in contra. inversion contra.
(*tunit*) subst. compute in H4. subst. simpl in contra. inversion contra.
(*tloc*) subst. compute in H4. subst. simpl in contra.
remember (fst(return_smallest_match n0(project_conf'_hp (project_hp hp0) (project_hp hp0)))) as C. destruct C.
inversion contra. inversion contra.
split. reflexivity. symmetry. apply H5. subst. assert (SecLang.joinTs T L = T).
destruct T. simpl. reflexivity. rewrite->H6. clear H6.
simpl. assert (SecLang.joinvs v L= v). inversion H3.
(*tcon*) subst. rewrite->SecLang.join_tcon_b. rewrite->SecLang.joins_refl. simpl. reflexivity.
(*tabs*) subst. rewrite->SecLang.join_tabs_b. rewrite->SecLang.joins_refl. simpl. reflexivity.
(*tunit*) subst. rewrite->SecLang.join_tunit_b. rewrite->SecLang.joins_refl. simpl. reflexivity.
(*tloc*) subst. rewrite->SecLang.join_tloc_b. rewrite->SecLang.joins_refl. simpl. reflexivity.
rewrite->H6. clear H6.
apply project_conf'_hp_heap_replace. apply H3. rewrite->H4 in H7. apply H7. apply H2.
apply LowLang.Multi_refl. symmetry. apply H7.
(*high cell being over-written by a high value*)
(*when PC is low*)
(*subcase 1: v <> tH & SecLang.label T = H*)
simpl. simpl in H6. rewrite->H6. simpl in H7. assert (n<length hp0). apply H2. apply return_smallest_match_project_hp_not_hit in H2.
assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0))=true). apply same_mark_heap.
apply return_smallest_match_same_mark' with (n:=n) in H14. rewrite<-H14. clear H14. rewrite->H2. simpl in H9. subst.
apply project_hp_Hoverwrite with (t:=v)(T:=T)in H13.
assert (SecLang.joinTs T L=T). destruct T. simpl. reflexivity. rewrite->H6. clear H6. rewrite<-H13. simpl. apply LowLang.Multi_step with (y:=(LowLang.tunit,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))). apply LowLang.st_assigntH_L. apply SecLang_value_LowLang. apply H3.
reflexivity. right. symmetry. apply H5. apply LowLang.Multi_refl. apply H3. rewrite<-H7. apply sub_refl. symmetry. apply H7.
(*subcase 2: v= tH*)
simpl. simpl in H6. rewrite->H6. simpl in H7. assert (n<length hp0). apply H2. apply return_smallest_match_project_hp_not_hit in H2.
assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0))=true). apply same_mark_heap.
apply return_smallest_match_same_mark' with (n:=n) in H14. rewrite<-H14. clear H14. rewrite->H2.
apply project_hp_Hoverwrite with (t:=v)(T:=T)in H13. subst.
assert (SecLang.joinvs v (SecLang.joins (SecLang.labelT T) L)= SecLang.joinvs v H). inversion H3.
(*tcon*) subst. compute in H4. subst. rewrite->SecLang.join_tcon_H. symmetry. apply SecLang.join_tcon_H.
(*tabs*) subst. compute in H4. subst. rewrite->SecLang.join_tabs_H. symmetry. apply SecLang.join_tabs_H.
(*tunit*) subst. compute in H4. subst. rewrite->SecLang.join_tunit_H. symmetry. apply SecLang.join_tunit_H.
(*tloc*) subst. compute in H4. subst. rewrite->SecLang.join_tloc_H. symmetry. apply SecLang.join_tloc_H.
rewrite->H5. clear H5.
assert (SecLang.joinTs T L=T). destruct T. simpl. reflexivity. rewrite->H5. clear H5. rewrite<-H13. simpl. apply LowLang.Multi_step with (y:=(LowLang.tunit,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))). apply LowLang.st_assigntH_L. apply SecLang_value_LowLang. apply H3.
reflexivity. left. inversion H3. subst. compute in H4. subst. simpl. reflexivity. subst. compute in H4. subst. simpl. reflexivity. subst. compute in H4. subst. simpl. reflexivity.
subst. compute in H4. subst. simpl. reflexivity.
apply LowLang.Multi_refl. apply H3. rewrite<-H7. apply sub_refl. symmetry. apply H7.
(*high pointer*)
simpl. simpl in H6. rewrite->H6. simpl. subst. apply project_hp_Hoverwrite with (t:=v)(T:=SecLang.joinTs T H)in H2. rewrite->SecLang.joins_refl. simpl. rewrite<-H2.
apply LowLang.Multi_step with (y:=(LowLang.tH, erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))).
apply LowLang.st_assignHP. apply SecLang_value_LowLang. apply H3. apply LowLang.Multi_refl. apply H3. apply H8.
(*finishing up by casing [b],the label of the pointer*)
destruct b.
(*high cell being over-written by a high value*)
(*when PC is high*)
simpl. simpl in H6. rewrite->H6. assert (n<length hp0). apply H2. apply return_smallest_match_project_hp_not_hit in H2.
assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0))=true). apply same_mark_heap.
apply return_smallest_match_same_mark' with (n:=n) in H14. rewrite<-H14. clear H14. rewrite->H2. subst.
apply project_hp_Hoverwrite with (t:=v)(T:=SecLang.joinTs T H)in H13.
rewrite->SecLang.joins_refl. simpl.
rewrite<-H13. apply LowLang.Multi_step with (y:=(LowLang.tH,
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))). apply LowLang.st_assigntH_H. apply SecLang_value_LowLang. apply H3.
reflexivity. apply LowLang.Multi_refl. apply H3. apply H8. rewrite->H6 in H8. remember (SecLang.label (SecLang.efst (SecLang.heap_lookup n hp0))) as C.
destruct C. inversion H8. reflexivity.
(*high pointer*)
simpl. simpl in H6. rewrite->H6. simpl. subst. apply project_hp_Hoverwrite with (t:=v)(T:=SecLang.joinTs T H)in H2. rewrite->SecLang.joins_refl. simpl. rewrite<-H2.
apply LowLang.Multi_step with (y:=(LowLang.tH, erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0)))).
apply LowLang.st_assignHP. apply SecLang_value_LowLang. apply H3. apply LowLang.Multi_refl. apply H3. apply H8.
Case ("st_assign1").
unfold project. unfold project_conf. unfold project in IHstep. unfold project_conf in IHstep. simpl. simpl in IHstep.
destruct PC.
SCase ("PC:=L"). apply step_same_mark_or_extend in H3. inversion H3.
(*case one: two heaps of the same length with identical marks*)
assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap.
assert (same_mark (project_conf'_hp (project_hp hp0) (project_hp hp0))(project_hp hp'0) = true). apply same_mark_replace with (hp1:=project_hp hp0).
apply H4. apply H5. apply same_mark_sym in H6. assert (same_mark (project_hp hp'0)(project_conf'_hp (project_hp hp'0) (project_hp hp'0)) = true).
apply same_mark_heap. assert (same_mark (project_conf'_hp (project_hp hp0) (project_hp hp0))(project_conf'_hp (project_hp hp'0) (project_hp hp'0)) = true).
apply same_mark_replace with (hp1:=project_hp hp'0). apply H7. apply H6. apply project_conf'_e_same_mark with (t:=project_e t2)in H8. rewrite->H8. clear H4.
clear H5. clear H6. clear H7. clear H8.
assert (fst (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)))). reflexivity. rewrite<-H4. clear H4.
assert (snd (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))).
reflexivity. rewrite<-H4. clear H4.
assert (fst (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)))). reflexivity. rewrite<-H4. clear H4.
assert (snd (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))).
reflexivity. rewrite<-H4. clear H4. apply multi_step_assign1. apply IHstep.
(*case two: after reduction heap is expanded by one low value*)
inversion H4. assert (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)) = project_conf'_e (project_e t2)
(project_conf'_hp ((LowLang.snoc (project_hp hp0) (x, (length hp0, length (project_hp hp0))))) ((LowLang.snoc (project_hp hp0) (x, (length hp0, length (project_hp hp0))))))).
rewrite<-H5. reflexivity. rewrite->H6. assert ((project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0))) = (project_conf'_e (project_e t2)
(project_conf'_hp
(LowLang.snoc (project_hp hp0)
(x, (length hp0, length (project_hp hp0))))
(LowLang.snoc (project_hp hp0)
(x, (length hp0, length (project_hp hp0))))))). apply project_conf'_e_add_one_low. apply H2. rewrite<-H7. clear H5. clear H6. clear H7.
assert (fst (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)))). reflexivity. rewrite<-H5. clear H5.
assert (snd (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))).
reflexivity. rewrite<-H5. clear H5.
assert (fst (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)))). reflexivity. rewrite<-H5. clear H5.
assert (snd (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))).
reflexivity. rewrite<-H5. clear H5. apply multi_step_assign1. apply IHstep.
SCase ("PC:=H"). apply proj_hp_H_same in H3. assert (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)) = project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp'0) (project_hp hp'0))). rewrite->H3. reflexivity. rewrite->H4. clear H4.
assert (fst (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)))). reflexivity. rewrite<-H4. clear H4.
assert (snd (project_conf'_e (project_e t1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))).
reflexivity. rewrite<-H4. clear H4.
assert (fst (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)))). reflexivity. rewrite<-H4. clear H4.
assert (snd (project_conf'_e (project_e t1')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))).
reflexivity. rewrite<-H4. clear H4. apply multi_step_assign1. apply IHstep.
Case ("st_assign2").
unfold project. unfold project_conf. unfold project in IHstep. unfold project_conf in IHstep. simpl. simpl in IHstep.
destruct PC.
SCase ("PC:=L"). apply step_same_mark_or_extend in H4. inversion H4.
(*case one: two heaps of the same length with identical marks*)
assert (same_mark (project_hp hp0)(project_conf'_hp (project_hp hp0)(project_hp hp0)) = true). apply same_mark_heap.
assert (same_mark (project_conf'_hp (project_hp hp0) (project_hp hp0))(project_hp hp'0) = true). apply same_mark_replace with (hp1:=project_hp hp0).
apply H5. apply H6. apply same_mark_sym in H7. assert (same_mark (project_hp hp'0)(project_conf'_hp (project_hp hp'0) (project_hp hp'0)) = true).
apply same_mark_heap. assert (same_mark (project_conf'_hp (project_hp hp0) (project_hp hp0))(project_conf'_hp (project_hp hp'0) (project_hp hp'0)) = true).
apply same_mark_replace with (hp1:=project_hp hp'0). apply H8. apply H7. apply project_conf'_e_same_mark with (t:=project_e v1)in H9. rewrite->H9. clear H5.
clear H6. clear H7. clear H8. clear H9.
assert (fst (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)))). reflexivity. rewrite<-H5. clear H5.
assert (snd (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))).
reflexivity. rewrite<-H5. clear H5.
assert (fst (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)))). reflexivity. rewrite<-H5. clear H5.
assert (snd (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))).
reflexivity. rewrite<-H5. clear H5. apply multi_step_assign2. apply SecLang_value_LowLang. apply H3.
apply IHstep.
(*case two: after reduction heap is expanded by one low value*)
inversion H5. assert (project_conf'_e (project_e v1)
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)) = project_conf'_e (project_e v1)
(project_conf'_hp ((LowLang.snoc (project_hp hp0) (x, (length hp0, length (project_hp hp0))))) ((LowLang.snoc (project_hp hp0) (x, (length hp0, length (project_hp hp0))))))).
rewrite<-H6. reflexivity. rewrite->H7. assert ((project_conf'_e (project_e v1)
(project_conf'_hp (project_hp hp0) (project_hp hp0))) = (project_conf'_e (project_e v1)
(project_conf'_hp
(LowLang.snoc (project_hp hp0)
(x, (length hp0, length (project_hp hp0))))
(LowLang.snoc (project_hp hp0)
(x, (length hp0, length (project_hp hp0))))))). apply project_conf'_e_add_one_low. apply H1. rewrite<-H8. clear H6. clear H7. clear H8.
assert (fst (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)))). reflexivity. rewrite<-H6. clear H6.
assert (snd (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))).
reflexivity. rewrite<-H6. clear H6.
assert (fst (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)))). reflexivity. rewrite<-H6. clear H6.
assert (snd (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))).
reflexivity. rewrite<-H6. clear H6. apply multi_step_assign2. apply SecLang_value_LowLang. apply H3.
apply IHstep.
SCase ("PC:=H"). apply proj_hp_H_same in H4. assert (project_conf'_e (project_e v1)
(project_conf'_hp (project_hp hp0) (project_hp hp0)) = project_conf'_e (project_e v1)
(project_conf'_hp (project_hp hp'0) (project_hp hp'0))). rewrite->H4. reflexivity. rewrite->H5. clear H5.
assert (fst (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)))). reflexivity. rewrite<-H5. clear H5.
assert (snd (project_conf'_e (project_e t2)
(project_conf'_hp (project_hp hp0) (project_hp hp0)),
erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))) = erase_hp (project_conf'_hp (project_hp hp0) (project_hp hp0))).
reflexivity. rewrite<-H5. clear H5.
assert (fst (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)))). reflexivity. rewrite<-H5. clear H5.
assert (snd (project_conf'_e (project_e t2')
(project_conf'_hp (project_hp hp'0) (project_hp hp'0)),
erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))) = erase_hp (project_conf'_hp (project_hp hp'0) (project_hp hp'0))).
reflexivity. rewrite<-H5. clear H5. apply multi_step_assign2. apply SecLang_value_LowLang. apply H3. apply IHstep.
Qed.
(*Theorem 5 in Lu's paper*)
Lemma corresp_eval:forall e e' hp hp',
SecLang.Multi SecLang.step (e,hp) L (e',hp') ->
LowLang.Multi LowLang.step (project (e,hp)) L (project (e',hp')).
Proof. intros. remember L as B. induction H0. apply LowLang.Multi_refl. destruct x. destruct y. subst.
apply corresp_step in H0. unfold project in H0. unfold project_conf in H0.
apply LowLang.multi_trans with
(t':=project_conf'_e (project_e (fst (t0, h0)))(project_conf'_hp (project_hp (snd (t0, h0)))(project_hp (snd (t0, h0)))))
(hp':=erase_hp(project_conf'_hp (project_hp (snd (t0, h0)))(project_hp (snd (t0, h0))))).
apply H0. apply IHMulti. reflexivity.
Qed.
(*NI of static typing with reference*)
Theorem NI:forall x v1 v2 w1 w2 e HT pc rt hp hp' hp'',
SecLang.value v1 ->
SecLang.value v2 -> (*1*)
SecLang.has_type pc empty_context HT v1 (an rt H) -> (*3*)
SecLang.has_type pc empty_context HT v2 (an rt H) -> (*4*)
SecLang.label v1 = H ->
SecLang.label v2 = H -> (*5*)
SecLang.has_type pc (Cupdate empty_context x (Some (an rt H))) HT
e (an int L) -> (*6*)
SecLang.heap_well_typed HT hp -> (*7*) (*8*)
SecLang.value w1 ->
SecLang.value w2 -> (*2*)
SecLang.Multi SecLang.step (SecLang.subst x v1 e,hp) L (w1,hp') -> (*8*)
SecLang.Multi SecLang.step (SecLang.subst x v2 e,hp) L (w2,hp'')-> (*9*)
w1 = w2.
Proof. intros.
(*step one*)
(**
(3),(4),(6),and [substitution_preserves_typing] in [SecLang] imply that
both [SecLang.subst x v1 e] and [SecLang.subst x v2 e] are of type [an int L]
*)
assert (SecLang.has_type pc empty_context HT (SecLang.subst x v1 e) (an int L)).
apply SecLang.substitution_preserves_typing with(pc:=pc)(Gamma:=empty_context)(HT:=HT)(x:=x)(T1:=an rt H)(T2:=an int L)(e:=e) in H0.
apply H0. apply H2. apply H6.
assert (SecLang.has_type pc empty_context HT (SecLang.subst x v2 e) (an int L)).
apply SecLang.substitution_preserves_typing with(pc:=pc)(Gamma:=empty_context)(HT:=HT)(x:=x)(T1:=an rt H)(T2:=an int L)(e:=e) in H1.
apply H1. apply H3. apply H6.
(*step two*)
(**
From [H13] and [H14],obtained from step one,together with [type_uniqueness] in [SecLang]
we conclude that [w1] and [w2] are of type [an int L]
*)
assert (fst (SecLang.subst x v1 e,hp)=SecLang.subst x v1 e). reflexivity.
rewrite<-H14 in H12. clear H14.
apply SecLang.type_uniqueness with(z:=(w1,hp'))(PC:=L)in H12. simpl in H12.
assert (fst (SecLang.subst x v2 e,hp)=SecLang.subst x v2 e). reflexivity.
rewrite<-H14 in H13. clear H14.
apply SecLang.type_uniqueness with(z:=(w2,hp''))(PC:=L)in H13. simpl in H13.
(*step three*)
(**
From the conclusion of [step two] that [w1] and [w2] are of type [an int L] and
(2) we know that [w1=tcon n1 L] and [w2=tcon n2 L]
*)
assert (SecLang.value w1). apply H8. assert (SecLang.value w2). apply H9.
inversion H14. inversion H15. subst.
inversion H12. inversion H16. inversion H18. apply SecLang.inversion_tcon in H20.
inversion H20. inversion H21. inversion H22. inversion H23. inversion H25. subst.
inversion H27. inversion H26. inversion H30. subst. inversion H24. subst.
inversion H13. inversion H28. inversion H31. apply SecLang.inversion_tcon in H33.
inversion H33. inversion H34. inversion H35. inversion H36. inversion H38. subst.
inversion H40. inversion H39. inversion H43. subst. inversion H37. subst.
(*step four*)
(**
From [corresp_eval],(1),(3),(4),[project_conf'_subst],and [determinism_extended]
we conclude that [n1 = n2]. Qed.
*)
apply corresp_eval in H10. apply corresp_eval in H11.
unfold project in H10. simpl in H10. unfold project_conf in H10.
assert (SecLang.value v1). apply H0. apply project_e_subst with (x:=x)(e:=e)in H41.
rewrite->H41 in H10. clear H41. rewrite->project_conf'_subst in H10. simpl in H10.
unfold project in H11. simpl in H11. unfold project_conf in H11.
assert (SecLang.value v2). apply H1. apply project_e_subst with (x:=x)(e:=e)in H41.
rewrite->H41 in H11. clear H41. rewrite->project_conf'_subst in H11. simpl in H11.
assert (project_e v1 = LowLang.tH). inversion H0. subst. compute in H4. subst. reflexivity.
subst. compute in H4. subst. reflexivity. subst. compute in H4. subst. reflexivity.
subst. compute in H4. subst. reflexivity. rewrite->H41 in H10. clear H41. simpl in H10.
assert (project_e v2 = LowLang.tH). inversion H1. subst. compute in H5. subst. reflexivity.
subst. compute in H5. subst. reflexivity. subst. compute in H5. subst. reflexivity.
subst. compute in H5. subst. reflexivity. rewrite->H41 in H11. clear H41. simpl in H11.
assert (LowLang.value (fst(LowLang.tcon n,erase_hp (project_conf'_hp (project_hp hp') (project_hp hp'))))).
simpl. apply LowLang.v_c.
assert (LowLang.value (fst(LowLang.tcon n0,erase_hp (project_conf'_hp (project_hp hp'') (project_hp hp''))))).
simpl. apply LowLang.v_c.
apply LowLang.determinism_extended with (x:=(LowLang.subst x LowLang.tH
(project_conf'_e (project_e e)(project_conf'_hp (project_hp hp) (project_hp hp))),
erase_hp (project_conf'_hp (project_hp hp) (project_hp hp))))
(y:=(LowLang.tcon n,
erase_hp (project_conf'_hp (project_hp hp') (project_hp hp'))))
(z:=(LowLang.tcon n0,
erase_hp (project_conf'_hp (project_hp hp'') (project_hp hp''))))
(PC:=L)in H41. simpl in H41. inversion H41. reflexivity.
simpl. apply LowLang.v_c. apply H10. apply H11.
(*contradictions*)
subst. inversion H13. inversion H16. inversion H18. apply SecLang.inversion_tabs in H20.
inversion H20. inversion H21. inversion H22. inversion H23. inversion H24. inversion H25.
inversion H26. inversion H27. inversion H29. inversion H31. inversion H33. inversion H35.
inversion H37. inversion H39. inversion H41.
subst. inversion H13. inversion H16. inversion H18. apply SecLang.inversion_tunit in H20.
inversion H20. inversion H21. inversion H22. inversion H23. inversion H25. inversion H27.
subst. inversion H29.
subst. inversion H13. inversion H16. inversion H18. apply SecLang.inversion_tloc in H20.
inversion H20. inversion H21. inversion H22. inversion H23. inversion H24. inversion H26.
inversion H28. inversion H30. inversion H32. subst. inversion H34.
subst. inversion H12. inversion H16. inversion H18. apply SecLang.inversion_tabs in H20.
inversion H20. inversion H21. inversion H22. inversion H23. inversion H24. inversion H25.
inversion H26. inversion H27. inversion H29. inversion H31. inversion H33. inversion H35.
inversion H37. inversion H39. inversion H41.
subst. inversion H12. inversion H16. inversion H18. apply SecLang.inversion_tunit in H20.
inversion H20. inversion H21. inversion H22. inversion H23. inversion H25. inversion H27.
subst. inversion H29.
subst. inversion H12. inversion H16. inversion H18. apply SecLang.inversion_tloc in H20.
inversion H20. inversion H21. inversion H22. inversion H23. inversion H24. inversion H26.
inversion H28. inversion H30. inversion H32. subst. inversion H34.
(*tidy-up*)
simpl. apply H7. destruct pc. apply sub_refl. apply sub_LH. apply H11.
simpl. apply H7. destruct pc. apply sub_refl. apply sub_LH. apply H10.
Qed.
End Correspondence.
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05/26/2016 07:28:40 AM
// Design Name:
// Module Name: LZD
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module LZD#(parameter SWR=26, parameter EWR=5)(
//#(parameter SWR=55, parameter EWR=6)(
input wire clk,
input wire rst,
input wire load_i,
input wire [SWR-1:0] Add_subt_result_i,
/////////////////////////////////////////////7
output wire [EWR-1:0] Shift_Value_o
);
wire [EWR-1:0] Codec_to_Reg;
generate
case (SWR)
26:begin
Priority_Codec_32 Codec_32(
.Data_Dec_i(Add_subt_result_i),
.Data_Bin_o(Codec_to_Reg)
);
end
55:begin
Priority_Codec_64 Codec_64(
.Data_Dec_i(Add_subt_result_i),
.Data_Bin_o(Codec_to_Reg)
);
end
endcase
endgenerate
RegisterAdd #(.W(EWR)) Output_Reg(
.clk(clk),
.rst(rst),
.load(load_i),
.D(Codec_to_Reg),
.Q(Shift_Value_o)
);
endmodule
|
// niosii_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module niosii_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
niosii_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
/*############################################################################
* PROGRAMMABLE DELAY ELEMENT
*
* NOTE: NOT AVAILABLE IN HR BANKS!
*
*############################################################################
*/
module ODELAYE2 (/*AUTOARG*/
// Outputs
CNTVALUEOUT, DATAOUT,
// Inputs
C, CE, CINVCTRL, CLKIN, CNTVALUEIN, INC, LD, LDPIPEEN, ODATAIN,
REGRST
);
parameter CINVCTRL_SEL = "FALSE";
parameter DELAY_SRC = "ODATAIN";
parameter HIGH_PERFORMANCE_MODE = "FALSE";
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_ODATAIN_INVERTED = 1'b0;
parameter ODELAY_TYPE = "FIXED";
parameter integer ODELAY_VALUE = 0;
parameter PIPE_SEL = "FALSE";
parameter real REFCLK_FREQUENCY = 200.0;
parameter SIGNAL_PATTERN = "DATA";
input C; //clock for VARIABLE, VAR_LOAD,VAR_LOAD_PIPE mode
input REGRST; //reset pipeline reg to all zeroes
input LD; //loads programmed values depending on "mode"
input CE; //enable encrement/decrement function
input INC; //increment/decrement tap delays
input CINVCTRL; //dynamically inverts clock polarity
input [4:0] CNTVALUEIN; //input value from FPGA logic
input CLKIN; //clk from I/O clock mux??
input ODATAIN; //data from OSERDESE2 output
output DATAOUT; //delayed data to pin
input LDPIPEEN; //enables pipeline reg??
output [4:0] CNTVALUEOUT; //current value for FPGA logic
assign DATAOUT=ODATAIN;
endmodule // ODELAYE2
|
//#############################################################################
//# Purpose: SPI master #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module spi_master # ( parameter DEPTH = 32, // fifo depth
parameter REGS = 16, // total # of regs
parameter AW = 32, // addresss width
parameter PW = 104 // packet width
)
(
//clk,reset, cfg
input clk, // core clock
input nreset, // async active low reset
input hw_en, // hardware enable pin
//IO interface
output sclk, // spi clock
output mosi, // slave input
output ss, // slave select
input miso, // slave output
//packet to transmit
input access_in, // access from core
input [PW-1:0] packet_in, // data to core
output wait_out, // pushback from spi register
//return packet
output access_out, // readback access
output [PW-1:0] packet_out, // packet from spi register
input wait_in // pushback by core
);
//###############
//# LOCAL WIRES
//###############
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] clkdiv_reg; // From spi_master_regs of spi_master_regs.v
wire cpha; // From spi_master_regs of spi_master_regs.v
wire cpol; // From spi_master_regs of spi_master_regs.v
wire [7:0] fifo_dout; // From spi_master_fifo of spi_master_fifo.v
wire fifo_empty; // From spi_master_fifo of spi_master_fifo.v
wire fifo_prog_full; // From spi_master_fifo of spi_master_fifo.v
wire fifo_read; // From spi_master_io of spi_master_io.v
wire fifo_wait; // From spi_master_fifo of spi_master_fifo.v
wire lsbfirst; // From spi_master_regs of spi_master_regs.v
wire manual_mode; // From spi_master_regs of spi_master_regs.v
wire rx_access; // From spi_master_io of spi_master_io.v
wire [63:0] rx_data; // From spi_master_io of spi_master_io.v
wire send_data; // From spi_master_regs of spi_master_regs.v
wire spi_en; // From spi_master_regs of spi_master_regs.v
wire [2:0] spi_state; // From spi_master_io of spi_master_io.v
// End of automatics
//#####################################################
//# Master control registers
//#####################################################
spi_master_regs #(.AW(AW),
.PW(PW))
spi_master_regs (/*AUTOINST*/
// Outputs
.cpol (cpol),
.cpha (cpha),
.lsbfirst (lsbfirst),
.spi_en (spi_en),
.manual_mode (manual_mode),
.send_data (send_data),
.clkdiv_reg (clkdiv_reg[7:0]),
.wait_out (wait_out),
.access_out (access_out),
.packet_out (packet_out[PW-1:0]),
// Inputs
.clk (clk),
.nreset (nreset),
.hw_en (hw_en),
.rx_data (rx_data[63:0]),
.rx_access (rx_access),
.spi_state (spi_state[2:0]),
.fifo_prog_full (fifo_prog_full),
.fifo_wait (fifo_wait),
.access_in (access_in),
.packet_in (packet_in[PW-1:0]),
.wait_in (wait_in));
//#####################################################
//# Transmit FIFO (SPI_TX)
//#####################################################
/* spi_master_fifo AUTO_TEMPLATE (.wait_out (fifo_wait),
.fifo_dout (fifo_dout[7:0]),
);
*/
spi_master_fifo #(.AW(AW),
.PW(PW),
.DEPTH(DEPTH))
spi_master_fifo(
/*AUTOINST*/
// Outputs
.fifo_prog_full (fifo_prog_full),
.wait_out (fifo_wait), // Templated
.fifo_empty (fifo_empty),
.fifo_dout (fifo_dout[7:0]), // Templated
// Inputs
.clk (clk),
.nreset (nreset),
.spi_en (spi_en),
.access_in (access_in),
.packet_in (packet_in[PW-1:0]),
.fifo_read (fifo_read));
//#####################################################
//# SPI IO (8 bit)
//#####################################################
spi_master_io
spi_master_io (/*AUTOINST*/
// Outputs
.spi_state (spi_state[2:0]),
.fifo_read (fifo_read),
.rx_data (rx_data[63:0]),
.rx_access (rx_access),
.sclk (sclk),
.mosi (mosi),
.ss (ss),
// Inputs
.clk (clk),
.nreset (nreset),
.cpol (cpol),
.cpha (cpha),
.lsbfirst (lsbfirst),
.manual_mode (manual_mode),
.send_data (send_data),
.clkdiv_reg (clkdiv_reg[7:0]),
.fifo_dout (fifo_dout[7:0]),
.fifo_empty (fifo_empty),
.miso (miso));
endmodule // spi_master
|
// DESCRIPTION: Verilator: Verilog Test module
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
reg [2*32-1:0] w2; initial w2 = {2 {32'h12345678}};
reg [9*32-1:0] w9; initial w9 = {9 {32'h12345678}};
reg [10*32-1:0] w10; initial w10 = {10{32'h12345678}};
reg [11*32-1:0] w11; initial w11 = {11{32'h12345678}};
reg [15*32-1:0] w15; initial w15 = {15{32'h12345678}};
reg [31*32-1:0] w31; initial w31 = {31{32'h12345678}};
reg [47*32-1:0] w47; initial w47 = {47{32'h12345678}};
reg [63*32-1:0] w63; initial w63 = {63{32'h12345678}};
// Aggregate outputs into a single result vector
wire [63:0] result = (w2[63:0]
^ w9[64:1]
^ w10[65:2]
^ w11[66:3]
^ w15[67:4]
^ w31[68:5]
^ w47[69:6]
^ w63[70:7]);
// What checksum will we end up with
`define EXPECTED_SUM 64'h184cb39122d8c6e3
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
w2 <= w2 >> 1;
w9 <= w9 >> 1;
w10 <= w10 >> 1;
w11 <= w11 >> 1;
w15 <= w15 >> 1;
w31 <= w31 >> 1;
w47 <= w47 >> 1;
w63 <= w63 >> 1;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 17:16:47 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W32 ( add_sub, in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
input add_sub;
wire n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17,
n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31,
n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45,
n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59,
n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73,
n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87,
n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100,
n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111,
n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122,
n123, n124, n125, n126, n127, n128, n129, n130, n131, n132, n133,
n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144,
n145, n146, n147, n148, n149, n150, n151, n152, n153, n154, n155,
n156, n157, n158, n159, n160, n161, n162, n163, n164, n165, n166,
n167, n168, n169, n170, n171, n172, n173, n174, n175, n176, n177,
n178, n179, n180, n181, n182, n183, n184, n185, n187, n188, n189,
n190, n191, n192, n193, n194, n195, n196, n197, n198, n199, n200,
n201, n202, n203, n204, n205, n206, n207, n208, n209, n210, n211,
n212, n213, n214, n215, n216, n217, n218, n219, n220, n221, n222,
n223, n224, n225, n226, n227, n228, n229, n230, n231, n232, n233,
n234, n235, n236, n237, n238, n239, n240, n241, n242, n243, n244,
n245, n246, n247, n248, n249, n250, n251, n252, n253, n254, n255,
n256, n257, n258, n259, n260, n261, n262, n263, n264, n265, n266,
n267, n268, n269, n270, n271, n272, n273, n274, n275, n276, n277,
n278, n279, n280, n281, n282, n283, n284, n285, n286, n287, n288,
n289, n290, n291, n292, n293, n294, n295, n296, n297, n298, n299,
n300, n301, n302, n303, n304, n305, n306, n307, n308, n309, n310,
n311, n312, n313, n314, n315, n316, n317, n318, n319, n320, n321,
n322, n323, n324, n325, n326, n327, n328, n329, n330, n331, n332,
n333, n334, n335, n336, n337, n338, n339, n340, n341, n342, n343,
n344, n345, n346, n347, n348, n349, n350, n351, n352, n353;
NAND2X1TS U35 ( .A(n62), .B(n195), .Y(n192) );
INVX2TS U36 ( .A(n52), .Y(n207) );
NAND2X1TS U37 ( .A(n205), .B(n204), .Y(n206) );
NAND2X1TS U38 ( .A(n239), .B(n238), .Y(n240) );
NAND2X1TS U39 ( .A(n245), .B(n244), .Y(n246) );
NAND2X1TS U40 ( .A(n252), .B(n251), .Y(n253) );
AOI21X2TS U41 ( .A0(n258), .A1(n243), .B0(n242), .Y(n247) );
AOI21X2TS U42 ( .A0(n258), .A1(n256), .B0(n249), .Y(n254) );
CMPR32X2TS U43 ( .A(in1[6]), .B(n328), .C(n320), .CO(n318), .S(res[6]) );
NAND2X1TS U44 ( .A(n202), .B(in1[31]), .Y(n203) );
CLKINVX1TS U45 ( .A(n232), .Y(n245) );
NOR2X1TS U46 ( .A(n336), .B(in1[8]), .Y(n349) );
NAND2X4TS U47 ( .A(n59), .B(n184), .Y(n58) );
NAND2X1TS U48 ( .A(n182), .B(in1[28]), .Y(n212) );
INVX4TS U49 ( .A(n164), .Y(n59) );
CLKMX2X2TS U50 ( .A(in2[30]), .B(n190), .S0(add_sub), .Y(n191) );
MX2X1TS U51 ( .A(in2[29]), .B(n187), .S0(add_sub), .Y(n188) );
CMPR32X2TS U52 ( .A(in1[1]), .B(n70), .C(n69), .CO(n300), .S(res[1]) );
CLKMX2X2TS U53 ( .A(in2[5]), .B(n316), .S0(n315), .Y(n323) );
NAND2X2TS U54 ( .A(n158), .B(in1[22]), .Y(n251) );
NAND2X2TS U55 ( .A(n137), .B(in1[19]), .Y(n265) );
CLKMX2X2TS U56 ( .A(in2[27]), .B(n174), .S0(n315), .Y(n180) );
NOR2X4TS U57 ( .A(n137), .B(in1[19]), .Y(n264) );
NAND2BX1TS U58 ( .AN(in2[29]), .B(n189), .Y(n199) );
CLKMX2X4TS U59 ( .A(in2[21]), .B(n151), .S0(n315), .Y(n157) );
NOR2X2TS U60 ( .A(n147), .B(n185), .Y(n176) );
NOR3X4TS U61 ( .A(n147), .B(in2[28]), .C(n185), .Y(n189) );
NOR2X2TS U62 ( .A(n147), .B(n175), .Y(n173) );
NAND2X4TS U63 ( .A(n65), .B(n270), .Y(n128) );
OR2X6TS U64 ( .A(n123), .B(in1[17]), .Y(n65) );
NAND2X1TS U65 ( .A(n172), .B(n171), .Y(n175) );
NOR2X2TS U66 ( .A(n153), .B(n152), .Y(n154) );
NOR2X2TS U67 ( .A(n153), .B(in2[20]), .Y(n150) );
NOR2X4TS U68 ( .A(n147), .B(in2[24]), .Y(n168) );
NAND2X6TS U69 ( .A(n101), .B(in1[13]), .Y(n290) );
NOR2X6TS U70 ( .A(n101), .B(in1[13]), .Y(n289) );
NOR2X2TS U71 ( .A(in2[25]), .B(in2[24]), .Y(n172) );
CLKINVX2TS U72 ( .A(n147), .Y(n165) );
MX2X4TS U73 ( .A(in2[13]), .B(n98), .S0(n302), .Y(n101) );
MXI2X2TS U74 ( .A(n105), .B(n100), .S0(n302), .Y(n102) );
NOR2X2TS U75 ( .A(n14), .B(n13), .Y(n95) );
NAND2X8TS U76 ( .A(n146), .B(n145), .Y(n147) );
NOR2X2TS U77 ( .A(n22), .B(n47), .Y(n14) );
NOR2X2TS U78 ( .A(n22), .B(n7), .Y(n12) );
NAND2X2TS U79 ( .A(n89), .B(in1[11]), .Y(n341) );
OR2X4TS U80 ( .A(n83), .B(in1[9]), .Y(n339) );
OR2X2TS U81 ( .A(in2[21]), .B(in2[20]), .Y(n152) );
NAND2X1TS U82 ( .A(n105), .B(n111), .Y(n112) );
NAND2X6TS U83 ( .A(n99), .B(n107), .Y(n113) );
NOR2X1TS U84 ( .A(in2[19]), .B(in2[18]), .Y(n133) );
INVX2TS U85 ( .A(in2[14]), .Y(n105) );
BUFX4TS U86 ( .A(add_sub), .Y(n302) );
INVX2TS U87 ( .A(n306), .Y(n71) );
INVX8TS U88 ( .A(add_sub), .Y(n88) );
AND2X6TS U89 ( .A(n80), .B(n306), .Y(n81) );
INVX8TS U90 ( .A(in2[2]), .Y(n44) );
NOR2X2TS U91 ( .A(in2[11]), .B(in2[10]), .Y(n91) );
NOR2X1TS U92 ( .A(n71), .B(n79), .Y(n74) );
INVX2TS U93 ( .A(n315), .Y(n47) );
CLKXOR2X2TS U94 ( .A(n168), .B(in2[25]), .Y(n169) );
NOR2X1TS U95 ( .A(n309), .B(in2[6]), .Y(n307) );
NAND2X2TS U96 ( .A(n16), .B(n18), .Y(n15) );
MXI2X2TS U97 ( .A(n136), .B(n135), .S0(add_sub), .Y(n138) );
CLKMX2X2TS U98 ( .A(in2[28]), .B(n177), .S0(add_sub), .Y(n182) );
NAND2X1TS U99 ( .A(n138), .B(in1[20]), .Y(n260) );
INVX2TS U100 ( .A(n237), .Y(n239) );
AOI21X1TS U101 ( .A0(n65), .A1(n35), .B0(n268), .Y(n272) );
ADDHXLTS U102 ( .A(in2[0]), .B(in1[0]), .CO(n69), .S(res[0]) );
NOR2X4TS U103 ( .A(n264), .B(n259), .Y(n140) );
XNOR2X2TS U104 ( .A(n166), .B(in2[26]), .Y(n167) );
NAND2X2TS U105 ( .A(n165), .B(n172), .Y(n166) );
NOR2X4TS U106 ( .A(in2[13]), .B(in2[12]), .Y(n107) );
INVX2TS U107 ( .A(in2[15]), .Y(n111) );
XOR2X1TS U108 ( .A(n241), .B(n240), .Y(res[24]) );
NOR2X2TS U109 ( .A(n10), .B(n204), .Y(n27) );
INVX2TS U110 ( .A(n195), .Y(n196) );
INVX2TS U111 ( .A(n62), .Y(n10) );
NAND2X2TS U112 ( .A(n62), .B(n205), .Y(n198) );
OR2X4TS U113 ( .A(n191), .B(in1[30]), .Y(n62) );
OAI21X2TS U114 ( .A0(n265), .A1(n259), .B0(n260), .Y(n139) );
NOR2X2TS U115 ( .A(n129), .B(in2[18]), .Y(n130) );
NAND2X2TS U116 ( .A(n51), .B(n86), .Y(n50) );
INVX2TS U117 ( .A(n21), .Y(n13) );
INVX12TS U118 ( .A(n88), .Y(n315) );
CLKINVX6TS U119 ( .A(in2[8]), .Y(n42) );
OR2X4TS U120 ( .A(n197), .B(n56), .Y(n53) );
NOR2X4TS U121 ( .A(n210), .B(n211), .Y(n184) );
NOR2X4TS U122 ( .A(n196), .B(n27), .Y(n197) );
NOR2X2TS U123 ( .A(n198), .B(n56), .Y(n55) );
NAND2X4TS U124 ( .A(n216), .B(n64), .Y(n210) );
INVX8TS U125 ( .A(n128), .Y(n37) );
MX2X2TS U126 ( .A(in2[31]), .B(n201), .S0(add_sub), .Y(n202) );
NAND3X6TS U127 ( .A(n17), .B(n294), .C(n15), .Y(n283) );
NOR2X4TS U128 ( .A(n248), .B(n250), .Y(n243) );
NOR2X4TS U129 ( .A(n158), .B(in1[22]), .Y(n250) );
INVX2TS U130 ( .A(n269), .Y(n125) );
NAND2X4TS U131 ( .A(n336), .B(in1[8]), .Y(n350) );
XOR2X1TS U132 ( .A(n314), .B(in2[5]), .Y(n316) );
CLKMX2X2TS U133 ( .A(in2[3]), .B(n299), .S0(n315), .Y(n305) );
OR2X2TS U134 ( .A(n47), .B(in1[12]), .Y(n7) );
XOR2X1TS U135 ( .A(n254), .B(n253), .Y(res[22]) );
INVX6TS U136 ( .A(n31), .Y(n30) );
OAI21X2TS U137 ( .A0(n209), .A1(n211), .B0(n212), .Y(n183) );
AND2X2TS U138 ( .A(n224), .B(n223), .Y(n9) );
NAND2X6TS U139 ( .A(n36), .B(n127), .Y(n34) );
XOR2X1TS U140 ( .A(n293), .B(n292), .Y(res[13]) );
NAND2X6TS U141 ( .A(n37), .B(n117), .Y(n36) );
NAND2X2TS U142 ( .A(n191), .B(in1[30]), .Y(n195) );
AND2X2TS U143 ( .A(n64), .B(n220), .Y(n8) );
XOR2X1TS U144 ( .A(n296), .B(n295), .Y(res[12]) );
INVX2TS U145 ( .A(n250), .Y(n252) );
XOR2X1TS U146 ( .A(n348), .B(n347), .Y(res[10]) );
OR2X4TS U147 ( .A(n180), .B(in1[27]), .Y(n64) );
NAND3X4TS U148 ( .A(n3), .B(n18), .C(n24), .Y(n17) );
NOR2X4TS U149 ( .A(n138), .B(in1[20]), .Y(n259) );
NAND2X4TS U150 ( .A(n19), .B(n341), .Y(n16) );
XOR2X1TS U151 ( .A(n353), .B(n352), .Y(res[8]) );
NAND2X4TS U152 ( .A(n95), .B(in1[12]), .Y(n294) );
OR2X2TS U153 ( .A(n116), .B(in1[16]), .Y(n63) );
NAND2X2TS U154 ( .A(n102), .B(in1[14]), .Y(n285) );
NOR2X2TS U155 ( .A(n118), .B(in2[16]), .Y(n119) );
NAND2X4TS U156 ( .A(n339), .B(n85), .Y(n25) );
NOR2X1TS U157 ( .A(n323), .B(in1[5]), .Y(n326) );
MX2X2TS U158 ( .A(in2[7]), .B(n308), .S0(n315), .Y(n329) );
NOR4X4TS U159 ( .A(n144), .B(n152), .C(in2[23]), .D(in2[22]), .Y(n145) );
INVX8TS U160 ( .A(n208), .Y(n230) );
XOR2X1TS U161 ( .A(n221), .B(n8), .Y(res[27]) );
NAND2X4TS U162 ( .A(n162), .B(n243), .Y(n164) );
NAND2X4TS U163 ( .A(n342), .B(n20), .Y(n19) );
XOR2X4TS U164 ( .A(n51), .B(in2[10]), .Y(n45) );
XOR2X1TS U165 ( .A(n225), .B(n9), .Y(res[26]) );
AOI21X2TS U166 ( .A0(n258), .A1(n236), .B0(n235), .Y(n241) );
INVX6TS U167 ( .A(n231), .Y(n258) );
AOI21X4TS U168 ( .A0(n162), .A1(n242), .B0(n161), .Y(n163) );
OAI21X2TS U169 ( .A0(n244), .A1(n237), .B0(n238), .Y(n161) );
NOR2X4TS U170 ( .A(n94), .B(n90), .Y(n51) );
XOR2X2TS U171 ( .A(n154), .B(in2[22]), .Y(n155) );
NOR2X6TS U172 ( .A(in2[7]), .B(in2[6]), .Y(n80) );
NOR2X4TS U173 ( .A(n102), .B(in1[14]), .Y(n284) );
OAI21X4TS U174 ( .A0(n250), .A1(n255), .B0(n251), .Y(n242) );
NAND2X2TS U175 ( .A(n110), .B(in1[15]), .Y(n280) );
MX2X4TS U176 ( .A(in2[15]), .B(n109), .S0(n302), .Y(n110) );
XOR2X2TS U177 ( .A(n108), .B(in2[15]), .Y(n109) );
NAND2X2TS U178 ( .A(n106), .B(n96), .Y(n97) );
XOR2X1TS U179 ( .A(n272), .B(n271), .Y(res[18]) );
NAND2X6TS U180 ( .A(n277), .B(n63), .Y(n39) );
MXI2X4TS U181 ( .A(n42), .B(n82), .S0(n302), .Y(n336) );
MXI2X4TS U182 ( .A(n171), .B(n167), .S0(n302), .Y(n179) );
XNOR2X1TS U183 ( .A(n150), .B(in2[21]), .Y(n151) );
XNOR2X2TS U184 ( .A(n207), .B(n206), .Y(res[29]) );
XNOR2X4TS U185 ( .A(n193), .B(n192), .Y(res[30]) );
NOR2X4TS U186 ( .A(n124), .B(in1[18]), .Y(n126) );
MXI2X4TS U187 ( .A(n122), .B(n121), .S0(n302), .Y(n124) );
XNOR2X2TS U188 ( .A(n129), .B(in2[18]), .Y(n121) );
NAND2X4TS U189 ( .A(n157), .B(in1[21]), .Y(n255) );
OAI21X4TS U190 ( .A0(n230), .A1(n226), .B0(n227), .Y(n225) );
MXI2X4TS U191 ( .A(n156), .B(n155), .S0(n302), .Y(n158) );
NOR2X4TS U192 ( .A(n222), .B(n226), .Y(n216) );
MXI2X4TS U193 ( .A(n170), .B(n169), .S0(n315), .Y(n178) );
NOR2X2TS U194 ( .A(n232), .B(n237), .Y(n162) );
XNOR2X1TS U195 ( .A(n94), .B(in2[8]), .Y(n82) );
XNOR2X1TS U196 ( .A(add_sub), .B(in2[9]), .Y(n77) );
OR3X1TS U197 ( .A(n306), .B(n88), .C(in2[9]), .Y(n76) );
NOR4BX1TS U198 ( .AN(n80), .B(n79), .C(in2[9]), .D(n72), .Y(n78) );
NAND2X1TS U199 ( .A(n47), .B(in2[11]), .Y(n46) );
INVX2TS U200 ( .A(in2[11]), .Y(n49) );
XNOR2X1TS U201 ( .A(n113), .B(in2[14]), .Y(n100) );
NAND2X4TS U202 ( .A(n87), .B(in1[10]), .Y(n346) );
OR2X4TS U203 ( .A(n89), .B(in1[11]), .Y(n342) );
NOR2X2TS U204 ( .A(n182), .B(in1[28]), .Y(n211) );
INVX2TS U205 ( .A(n220), .Y(n181) );
NAND2X2TS U206 ( .A(n134), .B(n133), .Y(n144) );
NAND3XLTS U207 ( .A(n107), .B(n106), .C(n105), .Y(n108) );
MX2X4TS U208 ( .A(in2[17]), .B(n120), .S0(n315), .Y(n123) );
XNOR2X1TS U209 ( .A(n173), .B(in2[27]), .Y(n174) );
XOR2X1TS U210 ( .A(n199), .B(in2[30]), .Y(n190) );
OAI21X1TS U211 ( .A0(n332), .A1(n331), .B0(n330), .Y(n333) );
INVX2TS U212 ( .A(n346), .Y(n20) );
NOR2X1TS U213 ( .A(n21), .B(in1[12]), .Y(n11) );
NAND2X4TS U214 ( .A(n338), .B(n25), .Y(n24) );
INVX2TS U215 ( .A(n350), .Y(n85) );
INVX2TS U216 ( .A(n283), .Y(n293) );
OAI21X2TS U217 ( .A0(n284), .A1(n290), .B0(n285), .Y(n103) );
NOR2X2TS U218 ( .A(n289), .B(n284), .Y(n104) );
NOR2X4TS U219 ( .A(n110), .B(in1[15]), .Y(n279) );
NAND2X2TS U220 ( .A(n124), .B(in1[18]), .Y(n269) );
INVX2TS U221 ( .A(n126), .Y(n270) );
NAND2X4TS U222 ( .A(n123), .B(in1[17]), .Y(n273) );
NAND2X1TS U223 ( .A(n39), .B(n275), .Y(n35) );
INVX2TS U224 ( .A(n34), .Y(n28) );
NAND2X2TS U225 ( .A(n38), .B(n37), .Y(n29) );
NOR2X4TS U226 ( .A(n179), .B(in1[26]), .Y(n222) );
NAND2X2TS U227 ( .A(n178), .B(in1[25]), .Y(n227) );
NOR2X2TS U228 ( .A(n178), .B(in1[25]), .Y(n226) );
NAND2X2TS U229 ( .A(n179), .B(in1[26]), .Y(n223) );
NAND2X2TS U230 ( .A(n180), .B(in1[27]), .Y(n220) );
INVX2TS U231 ( .A(n217), .Y(n218) );
INVX2TS U232 ( .A(n194), .Y(n205) );
NOR2X2TS U233 ( .A(n188), .B(in1[29]), .Y(n194) );
NAND2X2TS U234 ( .A(n188), .B(in1[29]), .Y(n204) );
OR2X4TS U235 ( .A(in2[9]), .B(in2[8]), .Y(n90) );
NAND3X2TS U236 ( .A(n42), .B(n41), .C(n40), .Y(n72) );
CLKBUFX2TS U237 ( .A(n99), .Y(n106) );
NAND2X2TS U238 ( .A(n134), .B(n146), .Y(n129) );
NAND3X4TS U239 ( .A(n38), .B(n37), .C(n140), .Y(n31) );
NAND2X2TS U240 ( .A(n34), .B(n140), .Y(n33) );
NOR2X2TS U241 ( .A(n329), .B(in1[7]), .Y(n332) );
NAND2X2TS U242 ( .A(n47), .B(n96), .Y(n21) );
NOR2X2TS U243 ( .A(n157), .B(in1[21]), .Y(n248) );
XNOR2X1TS U244 ( .A(n309), .B(in2[6]), .Y(n310) );
INVX2TS U245 ( .A(n248), .Y(n256) );
INVX2TS U246 ( .A(n255), .Y(n249) );
NAND2X2TS U247 ( .A(n159), .B(in1[23]), .Y(n244) );
NOR2X4TS U248 ( .A(n160), .B(in1[24]), .Y(n237) );
NOR2X1TS U249 ( .A(n233), .B(n232), .Y(n236) );
INVX2TS U250 ( .A(n243), .Y(n233) );
NAND2X2TS U251 ( .A(n160), .B(in1[24]), .Y(n238) );
INVX2TS U252 ( .A(n5), .Y(n56) );
NAND2X1TS U253 ( .A(n351), .B(n350), .Y(n352) );
NAND2X1TS U254 ( .A(n339), .B(n338), .Y(n337) );
NAND2X1TS U255 ( .A(n342), .B(n341), .Y(n343) );
OAI21X1TS U256 ( .A0(n348), .A1(n345), .B0(n346), .Y(n344) );
NAND2X1TS U257 ( .A(n18), .B(n294), .Y(n296) );
AOI21X1TS U258 ( .A0(n3), .A1(n24), .B0(n16), .Y(n295) );
NAND2X1TS U259 ( .A(n291), .B(n290), .Y(n292) );
INVX2TS U260 ( .A(n289), .Y(n291) );
NAND2X1TS U261 ( .A(n286), .B(n285), .Y(n287) );
OAI21XLTS U262 ( .A0(n293), .A1(n289), .B0(n290), .Y(n288) );
INVX2TS U263 ( .A(n284), .Y(n286) );
NAND2X1TS U264 ( .A(n281), .B(n280), .Y(n282) );
INVX2TS U265 ( .A(n279), .Y(n281) );
NAND2X1TS U266 ( .A(n63), .B(n275), .Y(n276) );
XNOR2X1TS U267 ( .A(n274), .B(n35), .Y(res[17]) );
NAND2X1TS U268 ( .A(n65), .B(n273), .Y(n274) );
INVX2TS U269 ( .A(n273), .Y(n268) );
XOR2XLTS U270 ( .A(n4), .B(n267), .Y(res[19]) );
NAND2X1TS U271 ( .A(n266), .B(n265), .Y(n267) );
XNOR2X1TS U272 ( .A(n263), .B(n262), .Y(res[20]) );
NAND2X1TS U273 ( .A(n261), .B(n260), .Y(n262) );
OAI21X1TS U274 ( .A0(n4), .A1(n264), .B0(n265), .Y(n263) );
INVX2TS U275 ( .A(n259), .Y(n261) );
XNOR2X1TS U276 ( .A(n258), .B(n257), .Y(res[21]) );
NAND2X1TS U277 ( .A(n256), .B(n255), .Y(n257) );
XOR2X1TS U278 ( .A(n230), .B(n229), .Y(res[25]) );
NAND2X1TS U279 ( .A(n228), .B(n227), .Y(n229) );
INVX2TS U280 ( .A(n226), .Y(n228) );
INVX2TS U281 ( .A(n222), .Y(n224) );
INVX2TS U282 ( .A(n216), .Y(n219) );
XNOR2X1TS U283 ( .A(n215), .B(n214), .Y(res[28]) );
NAND2X1TS U284 ( .A(n213), .B(n212), .Y(n214) );
INVX2TS U285 ( .A(n211), .Y(n213) );
NAND3X2TS U286 ( .A(n54), .B(n203), .C(n53), .Y(res[32]) );
OAI21X1TS U287 ( .A0(n234), .A1(n232), .B0(n244), .Y(n235) );
NOR2X4TS U288 ( .A(n87), .B(in1[10]), .Y(n345) );
MXI2X4TS U289 ( .A(n86), .B(n45), .S0(n302), .Y(n87) );
AOI21X4TS U290 ( .A0(n283), .A1(n104), .B0(n103), .Y(n278) );
AND2X4TS U291 ( .A(n23), .B(n342), .Y(n3) );
NOR2X4TS U292 ( .A(n159), .B(in1[23]), .Y(n232) );
AND2X2TS U293 ( .A(n29), .B(n28), .Y(n4) );
OR2X2TS U294 ( .A(n202), .B(in1[31]), .Y(n5) );
INVX2TS U295 ( .A(n338), .Y(n84) );
NAND2X2TS U296 ( .A(n83), .B(in1[9]), .Y(n338) );
INVX2TS U297 ( .A(n275), .Y(n117) );
NAND2X2TS U298 ( .A(n116), .B(in1[16]), .Y(n275) );
AND2X2TS U299 ( .A(n5), .B(n203), .Y(n6) );
NOR2X4TS U300 ( .A(n12), .B(n11), .Y(n18) );
INVX2TS U301 ( .A(in2[10]), .Y(n86) );
INVX2TS U302 ( .A(n345), .Y(n23) );
XOR2X1TS U303 ( .A(n329), .B(n319), .Y(res[7]) );
MXI2X1TS U304 ( .A(n66), .B(n40), .S0(n88), .Y(n70) );
XNOR2X2TS U305 ( .A(in2[0]), .B(in2[1]), .Y(n66) );
ADDFHX2TS U306 ( .A(in1[4]), .B(n322), .CI(n317), .CO(n321), .S(res[4]) );
XOR2X4TS U307 ( .A(n26), .B(n6), .Y(res[31]) );
INVX4TS U308 ( .A(n92), .Y(n93) );
CLKXOR2X2TS U309 ( .A(n141), .B(in2[23]), .Y(n142) );
OAI21X4TS U310 ( .A0(n52), .A1(n194), .B0(n204), .Y(n193) );
XNOR2X4TS U311 ( .A(n106), .B(in2[12]), .Y(n22) );
OAI21X4TS U312 ( .A0(n52), .A1(n198), .B0(n197), .Y(n26) );
NOR2X8TS U313 ( .A(n60), .B(n57), .Y(n52) );
NOR2X8TS U314 ( .A(n32), .B(n30), .Y(n231) );
NAND2BX4TS U315 ( .AN(n139), .B(n33), .Y(n32) );
INVX8TS U316 ( .A(n39), .Y(n38) );
OAI21X4TS U317 ( .A0(n278), .A1(n279), .B0(n280), .Y(n277) );
INVX12TS U318 ( .A(in2[1]), .Y(n40) );
INVX12TS U319 ( .A(in2[0]), .Y(n41) );
NOR2X8TS U320 ( .A(n297), .B(n79), .Y(n313) );
NAND2X8TS U321 ( .A(n44), .B(n43), .Y(n79) );
INVX12TS U322 ( .A(in2[3]), .Y(n43) );
NAND2X8TS U323 ( .A(n40), .B(n41), .Y(n297) );
OAI21X4TS U324 ( .A0(n231), .A1(n164), .B0(n163), .Y(n208) );
OAI21X4TS U325 ( .A0(n48), .A1(n47), .B0(n46), .Y(n89) );
XOR2X4TS U326 ( .A(n50), .B(n49), .Y(n48) );
NOR2X4TS U327 ( .A(n231), .B(n58), .Y(n57) );
NAND2BX4TS U328 ( .AN(n52), .B(n55), .Y(n54) );
NAND2BX4TS U329 ( .AN(n183), .B(n61), .Y(n60) );
NAND2BX4TS U330 ( .AN(n163), .B(n184), .Y(n61) );
XOR2X1TS U331 ( .A(n247), .B(n246), .Y(res[23]) );
NOR2X8TS U332 ( .A(in2[5]), .B(in2[4]), .Y(n306) );
NAND2BX4TS U333 ( .AN(n144), .B(n146), .Y(n153) );
AOI21X2TS U334 ( .A0(n335), .A1(n334), .B0(n333), .Y(n353) );
NOR2X1TS U335 ( .A(n327), .B(n332), .Y(n334) );
XOR2X4TS U336 ( .A(n97), .B(in2[13]), .Y(n98) );
INVX2TS U337 ( .A(n264), .Y(n266) );
NAND2X1TS U338 ( .A(n270), .B(n269), .Y(n271) );
XNOR2X1TS U339 ( .A(n297), .B(in2[2]), .Y(n68) );
INVX2TS U340 ( .A(in2[2]), .Y(n67) );
MXI2X1TS U341 ( .A(n68), .B(n67), .S0(n88), .Y(n301) );
INVX2TS U342 ( .A(n72), .Y(n73) );
NAND4X1TS U343 ( .A(n74), .B(n80), .C(in2[9]), .D(n73), .Y(n75) );
OAI211X4TS U344 ( .A0(n78), .A1(n77), .B0(n76), .C0(n75), .Y(n83) );
NAND2X8TS U345 ( .A(n313), .B(n81), .Y(n94) );
INVX2TS U346 ( .A(in2[12]), .Y(n96) );
NOR2BX4TS U347 ( .AN(n91), .B(n90), .Y(n92) );
NOR2X8TS U348 ( .A(n94), .B(n93), .Y(n99) );
INVX2TS U349 ( .A(in2[16]), .Y(n115) );
NOR2X8TS U350 ( .A(n113), .B(n112), .Y(n146) );
XOR2X1TS U351 ( .A(n146), .B(in2[16]), .Y(n114) );
MXI2X2TS U352 ( .A(n115), .B(n114), .S0(n302), .Y(n116) );
INVX2TS U353 ( .A(n146), .Y(n118) );
XNOR2X1TS U354 ( .A(n119), .B(in2[17]), .Y(n120) );
INVX2TS U355 ( .A(in2[18]), .Y(n122) );
NOR2X2TS U356 ( .A(in2[17]), .B(in2[16]), .Y(n134) );
AOI2BB1X4TS U357 ( .A0N(n273), .A1N(n126), .B0(n125), .Y(n127) );
INVX2TS U358 ( .A(in2[19]), .Y(n132) );
XOR2X1TS U359 ( .A(n130), .B(in2[19]), .Y(n131) );
MXI2X4TS U360 ( .A(n132), .B(n131), .S0(n315), .Y(n137) );
INVX2TS U361 ( .A(in2[20]), .Y(n136) );
XNOR2X1TS U362 ( .A(n153), .B(in2[20]), .Y(n135) );
INVX2TS U363 ( .A(in2[23]), .Y(n143) );
NOR3X4TS U364 ( .A(n153), .B(in2[22]), .C(n152), .Y(n141) );
MXI2X4TS U365 ( .A(n143), .B(n142), .S0(n315), .Y(n159) );
INVX2TS U366 ( .A(in2[24]), .Y(n149) );
XNOR2X1TS U367 ( .A(n147), .B(in2[24]), .Y(n148) );
MXI2X2TS U368 ( .A(n149), .B(n148), .S0(add_sub), .Y(n160) );
INVX2TS U369 ( .A(in2[22]), .Y(n156) );
INVX2TS U370 ( .A(in2[26]), .Y(n171) );
INVX2TS U371 ( .A(in2[25]), .Y(n170) );
OR2X2TS U372 ( .A(n175), .B(in2[27]), .Y(n185) );
XNOR2X1TS U373 ( .A(n176), .B(in2[28]), .Y(n177) );
OAI21X4TS U374 ( .A0(n227), .A1(n222), .B0(n223), .Y(n217) );
AOI21X4TS U375 ( .A0(n217), .A1(n64), .B0(n181), .Y(n209) );
XNOR2X1TS U376 ( .A(n189), .B(in2[29]), .Y(n187) );
NOR2X2TS U377 ( .A(n199), .B(in2[30]), .Y(n200) );
XNOR2X1TS U378 ( .A(n200), .B(in2[31]), .Y(n201) );
OAI21X4TS U379 ( .A0(n230), .A1(n210), .B0(n209), .Y(n215) );
OAI21X4TS U380 ( .A0(n230), .A1(n219), .B0(n218), .Y(n221) );
INVX2TS U381 ( .A(n242), .Y(n234) );
XNOR2X1TS U382 ( .A(n277), .B(n276), .Y(res[16]) );
XOR2XLTS U383 ( .A(n278), .B(n282), .Y(res[15]) );
XNOR2X1TS U384 ( .A(n288), .B(n287), .Y(res[14]) );
NOR2X1TS U385 ( .A(n297), .B(in2[2]), .Y(n298) );
XNOR2X1TS U386 ( .A(n298), .B(in2[3]), .Y(n299) );
ADDFHX2TS U387 ( .A(n301), .B(in1[2]), .CI(n300), .CO(n304), .S(res[2]) );
INVX2TS U388 ( .A(in2[4]), .Y(n312) );
XNOR2X1TS U389 ( .A(n313), .B(n312), .Y(n303) );
MXI2X2TS U390 ( .A(n312), .B(n303), .S0(n302), .Y(n322) );
CMPR32X2TS U391 ( .A(in1[3]), .B(n305), .C(n304), .CO(n317), .S(res[3]) );
NAND2X1TS U392 ( .A(n313), .B(n306), .Y(n309) );
XNOR2X1TS U393 ( .A(n307), .B(in2[7]), .Y(n308) );
INVX2TS U394 ( .A(in2[6]), .Y(n311) );
MXI2X2TS U395 ( .A(n311), .B(n310), .S0(add_sub), .Y(n328) );
NAND2X1TS U396 ( .A(n313), .B(n312), .Y(n314) );
XOR2X4TS U397 ( .A(in1[7]), .B(n318), .Y(n319) );
CMPR32X2TS U398 ( .A(in1[5]), .B(n323), .C(n321), .CO(n320), .S(res[5]) );
NAND2X1TS U399 ( .A(n322), .B(in1[4]), .Y(n325) );
NAND2X1TS U400 ( .A(n323), .B(in1[5]), .Y(n324) );
OAI21X1TS U401 ( .A0(n326), .A1(n325), .B0(n324), .Y(n335) );
NOR2X1TS U402 ( .A(n328), .B(in1[6]), .Y(n327) );
NAND2X1TS U403 ( .A(n328), .B(in1[6]), .Y(n331) );
NAND2X1TS U404 ( .A(n329), .B(in1[7]), .Y(n330) );
OAI21X4TS U405 ( .A0(n353), .A1(n349), .B0(n350), .Y(n340) );
XNOR2X1TS U406 ( .A(n340), .B(n337), .Y(res[9]) );
AOI21X4TS U407 ( .A0(n340), .A1(n339), .B0(n84), .Y(n348) );
XNOR2X1TS U408 ( .A(n344), .B(n343), .Y(res[11]) );
NAND2X1TS U409 ( .A(n23), .B(n346), .Y(n347) );
INVX2TS U410 ( .A(n349), .Y(n351) );
initial $sdf_annotate("Approx_adder_ACAIIN16Q8_syn.sdf");
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: fpu_in2_gt_in1_frac.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////////////
//
// Fraction comparison of two inputs that can have any value.
//
///////////////////////////////////////////////////////////////////////////////
module fpu_in2_gt_in1_frac (
din1,
din2,
sngop,
expadd11,
expeq,
din2_neq_din1,
din2_gt_din1,
din2_gt1_din1
);
input [54:0] din1; // input 1- fraction
input [54:0] din2; // input 2- fraction
input sngop; // single precision inputs
input expadd11; // exponent sign bit
input expeq; // exponent are equal
output din2_neq_din1; // input 2 != input 1- fraction
output din2_gt_din1; // input 2 > input 1- fraction
output din2_gt1_din1; // input 2 > input 1
wire din2_neq_din1_54_52;
wire din2_gt_din1_54_52;
wire din2_neq_din1_51_50;
wire din2_gt_din1_51_50;
wire din2_neq_din1_49_48;
wire din2_gt_din1_49_48;
wire din2_neq_din1_47_45;
wire din2_gt_din1_47_45;
wire din2_neq_din1_44_42;
wire din2_gt_din1_44_42;
wire din2_neq_din1_41_39;
wire din2_gt_din1_41_39;
wire din2_neq_din1_38_36;
wire din2_gt_din1_38_36;
wire din2_neq_din1_35_33;
wire din2_gt_din1_35_33;
wire din2_neq_din1_32_30;
wire din2_gt_din1_32_30;
wire din2_neq_din1_29_27;
wire din2_gt_din1_29_27;
wire din2_neq_din1_26_24;
wire din2_gt_din1_26_24;
wire din2_neq_din1_23_21;
wire din2_gt_din1_23_21;
wire din2_neq_din1_20_18;
wire din2_gt_din1_20_18;
wire din2_neq_din1_17_15;
wire din2_gt_din1_17_15;
wire din2_neq_din1_14_12;
wire din2_gt_din1_14_12;
wire din2_neq_din1_11_9;
wire din2_gt_din1_11_9;
wire din2_neq_din1_8_6;
wire din2_gt_din1_8_6;
wire din2_neq_din1_5_3;
wire din2_gt_din1_5_3;
wire din2_neq_din1_2_0;
wire din2_gt_din1_2_0;
wire din2_neq_din1_51_45;
wire din2_gt_din1_51_45;
wire din2_neq_din1_44_36;
wire din2_gt_din1_44_36;
wire din2_neq_din1_35_27;
wire din2_gt_din1_35_27;
wire din2_neq_din1_26_18;
wire din2_gt_din1_26_18;
wire din2_neq_din1_17_9;
wire din2_gt_din1_17_9;
wire din2_neq_din1_8_0;
wire din2_gt_din1_8_0;
wire din2_neq_din1_51_27;
wire din2_gt_din1_51_27;
wire din2_neq_din1_26_0;
wire din2_gt_din1_26_0;
wire din2_neq_din1;
wire din2_gt_din1;
wire din2_gt1_din1;
fpu_in2_gt_in1_3b fpu_in2_gt_in1_54_52 (
.din1 (din1[54:52]),
.din2 (din2[54:52]),
.din2_neq_din1 (din2_neq_din1_54_52),
.din2_gt_din1 (din2_gt_din1_54_52)
);
fpu_in2_gt_in1_2b fpu_in2_gt_in1_51_50 (
.din1 (din1[51:50]),
.din2 (din2[51:50]),
.din2_neq_din1 (din2_neq_din1_51_50),
.din2_gt_din1 (din2_gt_din1_51_50)
);
fpu_in2_gt_in1_2b fpu_in2_gt_in1_49_48 (
.din1 (din1[49:48]),
.din2 (din2[49:48]),
.din2_neq_din1 (din2_neq_din1_49_48),
.din2_gt_din1 (din2_gt_din1_49_48)
);
fpu_in2_gt_in1_3b fpu_in2_gt_in1_47_45 (
.din1 (din1[47:45]),
.din2 (din2[47:45]),
.din2_neq_din1 (din2_neq_din1_47_45),
.din2_gt_din1 (din2_gt_din1_47_45)
);
fpu_in2_gt_in1_3b fpu_in2_gt_in1_44_42 (
.din1 (din1[44:42]),
.din2 (din2[44:42]),
.din2_neq_din1 (din2_neq_din1_44_42),
.din2_gt_din1 (din2_gt_din1_44_42)
);
fpu_in2_gt_in1_3b fpu_in2_gt_in1_41_39 (
.din1 (din1[41:39]),
.din2 (din2[41:39]),
.din2_neq_din1 (din2_neq_din1_41_39),
.din2_gt_din1 (din2_gt_din1_41_39)
);
fpu_in2_gt_in1_3b fpu_in2_gt_in1_38_36 (
.din1 (din1[38:36]),
.din2 (din2[38:36]),
.din2_neq_din1 (din2_neq_din1_38_36),
.din2_gt_din1 (din2_gt_din1_38_36)
);
fpu_in2_gt_in1_3b fpu_in2_gt_in1_35_33 (
.din1 (din1[35:33]),
.din2 (din2[35:33]),
.din2_neq_din1 (din2_neq_din1_35_33),
.din2_gt_din1 (din2_gt_din1_35_33)
);
fpu_in2_gt_in1_3b fpu_in2_gt_in1_32_30 (
.din1 (din1[32:30]),
.din2 (din2[32:30]),
.din2_neq_din1 (din2_neq_din1_32_30),
.din2_gt_din1 (din2_gt_din1_32_30)
);
fpu_in2_gt_in1_3b fpu_in2_gt_in1_29_27 (
.din1 (din1[29:27]),
.din2 (din2[29:27]),
.din2_neq_din1 (din2_neq_din1_29_27),
.din2_gt_din1 (din2_gt_din1_29_27)
);
fpu_in2_gt_in1_3b fpu_in2_gt_in1_26_24 (
.din1 (din1[26:24]),
.din2 (din2[26:24]),
.din2_neq_din1 (din2_neq_din1_26_24),
.din2_gt_din1 (din2_gt_din1_26_24)
);
fpu_in2_gt_in1_3b fpu_in2_gt_in1_23_21 (
.din1 (din1[23:21]),
.din2 (din2[23:21]),
.din2_neq_din1 (din2_neq_din1_23_21),
.din2_gt_din1 (din2_gt_din1_23_21)
);
fpu_in2_gt_in1_3b fpu_in2_gt_in1_20_18 (
.din1 (din1[20:18]),
.din2 (din2[20:18]),
.din2_neq_din1 (din2_neq_din1_20_18),
.din2_gt_din1 (din2_gt_din1_20_18)
);
fpu_in2_gt_in1_3b fpu_in2_gt_in1_17_15 (
.din1 (din1[17:15]),
.din2 (din2[17:15]),
.din2_neq_din1 (din2_neq_din1_17_15),
.din2_gt_din1 (din2_gt_din1_17_15)
);
fpu_in2_gt_in1_3b fpu_in2_gt_in1_14_12 (
.din1 (din1[14:12]),
.din2 (din2[14:12]),
.din2_neq_din1 (din2_neq_din1_14_12),
.din2_gt_din1 (din2_gt_din1_14_12)
);
fpu_in2_gt_in1_3b fpu_in2_gt_in1_11_9 (
.din1 (din1[11:9]),
.din2 (din2[11:9]),
.din2_neq_din1 (din2_neq_din1_11_9),
.din2_gt_din1 (din2_gt_din1_11_9)
);
fpu_in2_gt_in1_3b fpu_in2_gt_in1_8_6 (
.din1 (din1[8:6]),
.din2 (din2[8:6]),
.din2_neq_din1 (din2_neq_din1_8_6),
.din2_gt_din1 (din2_gt_din1_8_6)
);
fpu_in2_gt_in1_3b fpu_in2_gt_in1_5_3 (
.din1 (din1[5:3]),
.din2 (din2[5:3]),
.din2_neq_din1 (din2_neq_din1_5_3),
.din2_gt_din1 (din2_gt_din1_5_3)
);
fpu_in2_gt_in1_3b fpu_in2_gt_in1_2_0 (
.din1 (din1[2:0]),
.din2 (din2[2:0]),
.din2_neq_din1 (din2_neq_din1_2_0),
.din2_gt_din1 (din2_gt_din1_2_0)
);
fpu_in2_gt_in1_3to1 fpu_in2_gt_in1_51_45 (
.din2_neq_din1_hi (din2_neq_din1_51_50),
.din2_gt_din1_hi (din2_gt_din1_51_50),
.din2_neq_din1_mid (din2_neq_din1_49_48),
.din2_gt_din1_mid (din2_gt_din1_49_48),
.din2_neq_din1_lo (din2_neq_din1_47_45),
.din2_gt_din1_lo (din2_gt_din1_47_45),
.din2_neq_din1 (din2_neq_din1_51_45),
.din2_gt_din1 (din2_gt_din1_51_45)
);
fpu_in2_gt_in1_3to1 fpu_in2_gt_in1_44_36 (
.din2_neq_din1_hi (din2_neq_din1_44_42),
.din2_gt_din1_hi (din2_gt_din1_44_42),
.din2_neq_din1_mid (din2_neq_din1_41_39),
.din2_gt_din1_mid (din2_gt_din1_41_39),
.din2_neq_din1_lo (din2_neq_din1_38_36),
.din2_gt_din1_lo (din2_gt_din1_38_36),
.din2_neq_din1 (din2_neq_din1_44_36),
.din2_gt_din1 (din2_gt_din1_44_36)
);
fpu_in2_gt_in1_3to1 fpu_in2_gt_in1_35_27 (
.din2_neq_din1_hi (din2_neq_din1_35_33),
.din2_gt_din1_hi (din2_gt_din1_35_33),
.din2_neq_din1_mid (din2_neq_din1_32_30),
.din2_gt_din1_mid (din2_gt_din1_32_30),
.din2_neq_din1_lo (din2_neq_din1_29_27),
.din2_gt_din1_lo (din2_gt_din1_29_27),
.din2_neq_din1 (din2_neq_din1_35_27),
.din2_gt_din1 (din2_gt_din1_35_27)
);
fpu_in2_gt_in1_3to1 fpu_in2_gt_in1_26_18 (
.din2_neq_din1_hi (din2_neq_din1_26_24),
.din2_gt_din1_hi (din2_gt_din1_26_24),
.din2_neq_din1_mid (din2_neq_din1_23_21),
.din2_gt_din1_mid (din2_gt_din1_23_21),
.din2_neq_din1_lo (din2_neq_din1_20_18),
.din2_gt_din1_lo (din2_gt_din1_20_18),
.din2_neq_din1 (din2_neq_din1_26_18),
.din2_gt_din1 (din2_gt_din1_26_18)
);
fpu_in2_gt_in1_3to1 fpu_in2_gt_in1_17_9 (
.din2_neq_din1_hi (din2_neq_din1_17_15),
.din2_gt_din1_hi (din2_gt_din1_17_15),
.din2_neq_din1_mid (din2_neq_din1_14_12),
.din2_gt_din1_mid (din2_gt_din1_14_12),
.din2_neq_din1_lo (din2_neq_din1_11_9),
.din2_gt_din1_lo (din2_gt_din1_11_9),
.din2_neq_din1 (din2_neq_din1_17_9),
.din2_gt_din1 (din2_gt_din1_17_9)
);
fpu_in2_gt_in1_3to1 fpu_in2_gt_in1_8_0 (
.din2_neq_din1_hi (din2_neq_din1_8_6),
.din2_gt_din1_hi (din2_gt_din1_8_6),
.din2_neq_din1_mid (din2_neq_din1_5_3),
.din2_gt_din1_mid (din2_gt_din1_5_3),
.din2_neq_din1_lo (din2_neq_din1_2_0),
.din2_gt_din1_lo (din2_gt_din1_2_0),
.din2_neq_din1 (din2_neq_din1_8_0),
.din2_gt_din1 (din2_gt_din1_8_0)
);
fpu_in2_gt_in1_3to1 fpu_in2_gt_in1_51_27 (
.din2_neq_din1_hi (din2_neq_din1_51_45),
.din2_gt_din1_hi (din2_gt_din1_51_45),
.din2_neq_din1_mid (din2_neq_din1_44_36),
.din2_gt_din1_mid (din2_gt_din1_44_36),
.din2_neq_din1_lo (din2_neq_din1_35_27),
.din2_gt_din1_lo (din2_gt_din1_35_27),
.din2_neq_din1 (din2_neq_din1_51_27),
.din2_gt_din1 (din2_gt_din1_51_27)
);
fpu_in2_gt_in1_3to1 fpu_in2_gt_in1_26_0 (
.din2_neq_din1_hi (din2_neq_din1_26_18),
.din2_gt_din1_hi (din2_gt_din1_26_18),
.din2_neq_din1_mid (din2_neq_din1_17_9),
.din2_gt_din1_mid (din2_gt_din1_17_9),
.din2_neq_din1_lo (din2_neq_din1_8_0),
.din2_gt_din1_lo (din2_gt_din1_8_0),
.din2_neq_din1 (din2_neq_din1_26_0),
.din2_gt_din1 (din2_gt_din1_26_0)
);
assign din2_neq_din1= din2_neq_din1_51_27
|| din2_neq_din1_26_0
|| (din2_neq_din1_54_52 && sngop);
assign din2_gt_din1= (din2_neq_din1_54_52 && din2_gt_din1_54_52
&& sngop)
|| ((!(din2_neq_din1_54_52 && sngop))
&& din2_neq_din1_51_27 && din2_gt_din1_51_27)
|| ((!(din2_neq_din1_54_52 && sngop))
&& (!din2_neq_din1_51_27)
&& din2_gt_din1_26_0);
assign din2_gt1_din1= expadd11
|| (din2_gt_din1 && expeq);
endmodule
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:00:10 11/17/2012
// Design Name:
// Module Name: CRC8_gen
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module CRC8_gen(
input [47:0] D,
output [7:0] NewCRC
);
assign NewCRC[0] = D[46] ^ D[42] ^ D[41] ^ D[37] ^ D[36] ^ D[35] ^ D[34] ^
D[33] ^ D[31] ^ D[30] ^ D[29] ^ D[27] ^ D[26] ^ D[24] ^
D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^
D[8] ^ D[7] ^ D[6] ^ D[3] ^ D[1] ^ D[0];
assign NewCRC[1] = D[47] ^ D[43] ^ D[42] ^ D[38] ^ D[37] ^ D[36] ^ D[35] ^
D[34] ^ D[32] ^ D[31] ^ D[30] ^ D[28] ^ D[27] ^ D[25] ^
D[21] ^ D[19] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^
D[9] ^ D[8] ^ D[7] ^ D[4] ^ D[2] ^ D[1];
assign NewCRC[2] = D[46] ^ D[44] ^ D[43] ^ D[42] ^ D[41] ^ D[39] ^ D[38] ^
D[34] ^ D[32] ^ D[30] ^ D[28] ^ D[27] ^ D[24] ^ D[22] ^
D[19] ^ D[14] ^ D[13] ^ D[10] ^ D[9] ^ D[7] ^ D[6] ^
D[5] ^ D[2] ^ D[1] ^ D[0];
assign NewCRC[3] = D[47] ^ D[45] ^ D[44] ^ D[43] ^ D[42] ^ D[40] ^ D[39] ^
D[35] ^ D[33] ^ D[31] ^ D[29] ^ D[28] ^ D[25] ^ D[23] ^
D[20] ^ D[15] ^ D[14] ^ D[11] ^ D[10] ^ D[8] ^ D[7] ^
D[6] ^ D[3] ^ D[2] ^ D[1];
assign NewCRC[4] = D[45] ^ D[44] ^ D[43] ^ D[42] ^ D[40] ^ D[37] ^ D[35] ^
D[33] ^ D[32] ^ D[31] ^ D[27] ^ D[21] ^ D[20] ^ D[18] ^
D[17] ^ D[14] ^ D[13] ^ D[12] ^ D[11] ^ D[9] ^ D[6] ^
D[4] ^ D[2] ^ D[1] ^ D[0];
assign NewCRC[5] = D[46] ^ D[45] ^ D[44] ^ D[43] ^ D[41] ^ D[38] ^ D[36] ^
D[34] ^ D[33] ^ D[32] ^ D[28] ^ D[22] ^ D[21] ^ D[19] ^
D[18] ^ D[15] ^ D[14] ^ D[13] ^ D[12] ^ D[10] ^ D[7] ^
D[5] ^ D[3] ^ D[2] ^ D[1];
assign NewCRC[6] = D[47] ^ D[45] ^ D[44] ^ D[41] ^ D[39] ^ D[36] ^ D[31] ^
D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[23] ^ D[22] ^ D[19] ^
D[18] ^ D[17] ^ D[11] ^ D[7] ^ D[4] ^ D[2] ^ D[1] ^
D[0];
assign NewCRC[7] = D[45] ^ D[41] ^ D[40] ^ D[36] ^ D[35] ^ D[34] ^ D[33] ^
D[32] ^ D[30] ^ D[29] ^ D[28] ^ D[26] ^ D[25] ^ D[23] ^
D[19] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^ D[12] ^
D[7] ^ D[6] ^ D[5] ^ D[2] ^ D[0];
endmodule
|
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altfp_log CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix V" PIPELINE=34 WIDTH_EXP=11 WIDTH_MAN=52 clk_en clock data result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix V" PIPELINE=1 SHIFTDIR="LEFT" WIDTH=64 WIDTHDIST=6 aclr clk_en clock data distance result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//synthesis_resources = reg 65
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altbarrel_shift_qud
(
aclr,
clk_en,
clock,
data,
distance,
result) ;
input aclr;
input clk_en;
input clock;
input [63:0] data;
input [5:0] distance;
output [63:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dir_pipe;
reg [63:0] sbit_piper1d;
wire [6:0] dir_w;
wire direction_w;
wire [31:0] pad_w;
wire [447:0] sbit_w;
wire [5:0] sel_w;
wire [383:0] smux_w;
// synopsys translate_off
initial
dir_pipe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dir_pipe <= 1'b0;
else if (clk_en == 1'b1) dir_pipe <= {dir_w[5]};
// synopsys translate_off
initial
sbit_piper1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sbit_piper1d <= 64'b0;
else if (clk_en == 1'b1) sbit_piper1d <= smux_w[383:320];
assign
dir_w = {dir_pipe[0], dir_w[4:0], direction_w},
direction_w = 1'b0,
pad_w = {32{1'b0}},
result = sbit_w[447:384],
sbit_w = {sbit_piper1d, smux_w[319:0], data},
sel_w = {distance[5:0]},
smux_w = {((({64{(sel_w[5] & (~ dir_w[5]))}} & {sbit_w[351:320], pad_w[31:0]}) | ({64{(sel_w[5] & dir_w[5])}} & {pad_w[31:0], sbit_w[383:352]})) | ({64{(~ sel_w[5])}} & sbit_w[383:320])), ((({64{(sel_w[4] & (~ dir_w[4]))}} & {sbit_w[303:256], pad_w[15:0]}) | ({64{(sel_w[4] & dir_w[4])}} & {pad_w[15:0], sbit_w[319:272]})) | ({64{(~ sel_w[4])}} & sbit_w[319:256])), ((({64{(sel_w[3] & (~ dir_w[3]))}} & {sbit_w[247:192], pad_w[7:0]}) | ({64{(sel_w[3] & dir_w[3])}} & {pad_w[7:0], sbit_w[255:200]})) | ({64{(~ sel_w[3])}} & sbit_w[255:192])), ((({64{(sel_w[2] & (~ dir_w[2]))}} & {sbit_w[187:128], pad_w[3:0]}) | ({64{(sel_w[2] & dir_w[2])}} & {pad_w[3:0], sbit_w[191:132]})) | ({64{(~ sel_w[2])}} & sbit_w[191:128])), ((({64{(sel_w[1] & (~ dir_w[1]))}} & {sbit_w[125:64], pad_w[1:0]}) | ({64{(sel_w[1] & dir_w[1])}} & {pad_w[1:0], sbit_w[127:66]})) | ({64{(~ sel_w[1])}} & sbit_w[127:64])), ((({64{(sel_w[0] & (~ dir_w[0]))}} & {sbit_w[62:0], pad_w[0]}) | ({64{(sel_w[0] & dir_w[0])}} & {pad_w[0], sbit_w[63:1]})) | ({64{(~ sel_w[0])}} & sbit_w[63:0]))};
endmodule //acl_fp_log_s5_double_altbarrel_shift_qud
//altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix V" SHIFTDIR="LEFT" WIDTH=128 WIDTHDIST=7 data distance result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altbarrel_shift_edb
(
data,
distance,
result) ;
input [127:0] data;
input [6:0] distance;
output [127:0] result;
wire [7:0] dir_w;
wire direction_w;
wire [63:0] pad_w;
wire [1023:0] sbit_w;
wire [6:0] sel_w;
wire [895:0] smux_w;
assign
dir_w = {dir_w[6:0], direction_w},
direction_w = 1'b0,
pad_w = {64{1'b0}},
result = sbit_w[1023:896],
sbit_w = {smux_w[895:0], data},
sel_w = {distance[6:0]},
smux_w = {((({128{(sel_w[6] & (~ dir_w[6]))}} & {sbit_w[831:768], pad_w[63:0]}) | ({128{(sel_w[6] & dir_w[6])}} & {pad_w[63:0], sbit_w[895:832]})) | ({128{(~ sel_w[6])}} & sbit_w[895:768])), ((({128{(sel_w[5] & (~ dir_w[5]))}} & {sbit_w[735:640], pad_w[31:0]}) | ({128{(sel_w[5] & dir_w[5])}} & {pad_w[31:0], sbit_w[767:672]})) | ({128{(~ sel_w[5])}} & sbit_w[767:640])), ((({128{(sel_w[4] & (~ dir_w[4]))}} & {sbit_w[623:512], pad_w[15:0]}) | ({128{(sel_w[4] & dir_w[4])}} & {pad_w[15:0], sbit_w[639:528]})) | ({128{(~ sel_w[4])}} & sbit_w[639:512])), ((({128{(sel_w[3] & (~ dir_w[3]))}} & {sbit_w[503:384], pad_w[7:0]}) | ({128{(sel_w[3] & dir_w[3])}} & {pad_w[7:0], sbit_w[511:392]})) | ({128{(~ sel_w[3])}} & sbit_w[511:384])), ((({128{(sel_w[2] & (~ dir_w[2]))}} & {sbit_w[379:256], pad_w[3:0]}) | ({128{(sel_w[2] & dir_w[2])}} & {pad_w[3:0], sbit_w[383:260]})) | ({128{(~ sel_w[2])}} & sbit_w[383:256])), ((({128{(sel_w[1] & (~ dir_w[1]))}} & {sbit_w[253:128], pad_w[1:0]}) | ({128{(sel_w[1] & dir_w[1])}} & {pad_w[1:0], sbit_w[255:130]})) | ({128{(~ sel_w[1])}} & sbit_w[255:128])), ((({128{(sel_w[0] & (~ dir_w[0]))}} & {sbit_w[126:0], pad_w[0]}) | ({128{(sel_w[0] & dir_w[0])}} & {pad_w[0], sbit_w[127:1]})) | ({128{(~ sel_w[0])}} & sbit_w[127:0]))};
endmodule //acl_fp_log_s5_double_altbarrel_shift_edb
//altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix V" PIPELINE=1 SHIFTDIR="RIGHT" WIDTH=64 WIDTHDIST=6 aclr clk_en clock data distance result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//synthesis_resources = reg 65
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altbarrel_shift_d2e
(
aclr,
clk_en,
clock,
data,
distance,
result) ;
input aclr;
input clk_en;
input clock;
input [63:0] data;
input [5:0] distance;
output [63:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dir_pipe;
reg [63:0] sbit_piper1d;
wire [6:0] dir_w;
wire direction_w;
wire [31:0] pad_w;
wire [447:0] sbit_w;
wire [5:0] sel_w;
wire [383:0] smux_w;
// synopsys translate_off
initial
dir_pipe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dir_pipe <= 1'b0;
else if (clk_en == 1'b1) dir_pipe <= {dir_w[5]};
// synopsys translate_off
initial
sbit_piper1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sbit_piper1d <= 64'b0;
else if (clk_en == 1'b1) sbit_piper1d <= smux_w[383:320];
assign
dir_w = {dir_pipe[0], dir_w[4:0], direction_w},
direction_w = 1'b1,
pad_w = {32{1'b0}},
result = sbit_w[447:384],
sbit_w = {sbit_piper1d, smux_w[319:0], data},
sel_w = {distance[5:0]},
smux_w = {((({64{(sel_w[5] & (~ dir_w[5]))}} & {sbit_w[351:320], pad_w[31:0]}) | ({64{(sel_w[5] & dir_w[5])}} & {pad_w[31:0], sbit_w[383:352]})) | ({64{(~ sel_w[5])}} & sbit_w[383:320])), ((({64{(sel_w[4] & (~ dir_w[4]))}} & {sbit_w[303:256], pad_w[15:0]}) | ({64{(sel_w[4] & dir_w[4])}} & {pad_w[15:0], sbit_w[319:272]})) | ({64{(~ sel_w[4])}} & sbit_w[319:256])), ((({64{(sel_w[3] & (~ dir_w[3]))}} & {sbit_w[247:192], pad_w[7:0]}) | ({64{(sel_w[3] & dir_w[3])}} & {pad_w[7:0], sbit_w[255:200]})) | ({64{(~ sel_w[3])}} & sbit_w[255:192])), ((({64{(sel_w[2] & (~ dir_w[2]))}} & {sbit_w[187:128], pad_w[3:0]}) | ({64{(sel_w[2] & dir_w[2])}} & {pad_w[3:0], sbit_w[191:132]})) | ({64{(~ sel_w[2])}} & sbit_w[191:128])), ((({64{(sel_w[1] & (~ dir_w[1]))}} & {sbit_w[125:64], pad_w[1:0]}) | ({64{(sel_w[1] & dir_w[1])}} & {pad_w[1:0], sbit_w[127:66]})) | ({64{(~ sel_w[1])}} & sbit_w[127:64])), ((({64{(sel_w[0] & (~ dir_w[0]))}} & {sbit_w[62:0], pad_w[0]}) | ({64{(sel_w[0] & dir_w[0])}} & {pad_w[0], sbit_w[63:1]})) | ({64{(~ sel_w[0])}} & sbit_w[63:0]))};
endmodule //acl_fp_log_s5_double_altbarrel_shift_d2e
//altfp_log_and_or CBX_AUTO_BLACKBOX="ALL" LUT_INPUT_COUNT=6 OPERATION="AND" PIPELINE=3 WIDTH=11 aclr clken clock data result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = reg 4
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_and_or_rab
(
aclr,
clken,
clock,
data,
result) ;
input aclr;
input clken;
input clock;
input [10:0] data;
output result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [10:0] data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [1:0] connection_dffe0;
reg [0:0] connection_dffe1;
reg connection_dffe2;
wire [10:0] connection_r0_w;
wire [1:0] connection_r1_w;
wire [0:0] connection_r2_w;
wire [10:0] operation_r1_w;
wire [1:0] operation_r2_w;
// synopsys translate_off
initial
connection_dffe0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe0 <= 2'b0;
else if (clken == 1'b1) connection_dffe0 <= {operation_r1_w[10], operation_r1_w[5]};
// synopsys translate_off
initial
connection_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe1 <= 1'b0;
else if (clken == 1'b1) connection_dffe1 <= {operation_r2_w[1]};
// synopsys translate_off
initial
connection_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe2 <= 1'b0;
else if (clken == 1'b1) connection_dffe2 <= connection_r2_w[0];
assign
connection_r0_w = data,
connection_r1_w = connection_dffe0,
connection_r2_w = connection_dffe1,
operation_r1_w = {(operation_r1_w[9] & connection_r0_w[10]), (operation_r1_w[8] & connection_r0_w[9]), (operation_r1_w[7] & connection_r0_w[8]), (operation_r1_w[6] & connection_r0_w[7]), connection_r0_w[6], (operation_r1_w[4] & connection_r0_w[5]), (operation_r1_w[3] & connection_r0_w[4]), (operation_r1_w[2] & connection_r0_w[3]), (operation_r1_w[1] & connection_r0_w[2]), (operation_r1_w[0] & connection_r0_w[1]), connection_r0_w[0]},
operation_r2_w = {(operation_r2_w[0] & connection_r1_w[1]), connection_r1_w[0]},
result = connection_dffe2;
endmodule //acl_fp_log_s5_double_altfp_log_and_or_rab
//altfp_log_and_or CBX_AUTO_BLACKBOX="ALL" LUT_INPUT_COUNT=6 OPERATION="OR" PIPELINE=3 WIDTH=11 aclr clken clock data result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = reg 4
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_and_or_98b
(
aclr,
clken,
clock,
data,
result) ;
input aclr;
input clken;
input clock;
input [10:0] data;
output result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [10:0] data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [1:0] connection_dffe0;
reg [0:0] connection_dffe1;
reg connection_dffe2;
wire [10:0] connection_r0_w;
wire [1:0] connection_r1_w;
wire [0:0] connection_r2_w;
wire [10:0] operation_r1_w;
wire [1:0] operation_r2_w;
// synopsys translate_off
initial
connection_dffe0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe0 <= 2'b0;
else if (clken == 1'b1) connection_dffe0 <= {operation_r1_w[10], operation_r1_w[5]};
// synopsys translate_off
initial
connection_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe1 <= 1'b0;
else if (clken == 1'b1) connection_dffe1 <= {operation_r2_w[1]};
// synopsys translate_off
initial
connection_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe2 <= 1'b0;
else if (clken == 1'b1) connection_dffe2 <= connection_r2_w[0];
assign
connection_r0_w = data,
connection_r1_w = connection_dffe0,
connection_r2_w = connection_dffe1,
operation_r1_w = {(operation_r1_w[9] | connection_r0_w[10]), (operation_r1_w[8] | connection_r0_w[9]), (operation_r1_w[7] | connection_r0_w[8]), (operation_r1_w[6] | connection_r0_w[7]), connection_r0_w[6], (operation_r1_w[4] | connection_r0_w[5]), (operation_r1_w[3] | connection_r0_w[4]), (operation_r1_w[2] | connection_r0_w[3]), (operation_r1_w[1] | connection_r0_w[2]), (operation_r1_w[0] | connection_r0_w[1]), connection_r0_w[0]},
operation_r2_w = {(operation_r2_w[0] | connection_r1_w[1]), connection_r1_w[0]},
result = connection_dffe2;
endmodule //acl_fp_log_s5_double_altfp_log_and_or_98b
//altfp_log_and_or CBX_AUTO_BLACKBOX="ALL" LUT_INPUT_COUNT=6 OPERATION="OR" PIPELINE=3 WIDTH=52 aclr clken clock data result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = reg 12
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_and_or_e8b
(
aclr,
clken,
clock,
data,
result) ;
input aclr;
input clken;
input clock;
input [51:0] data;
output result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [51:0] data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [8:0] connection_dffe0;
reg [1:0] connection_dffe1;
reg [0:0] connection_dffe2;
wire [51:0] connection_r0_w;
wire [8:0] connection_r1_w;
wire [1:0] connection_r2_w;
wire [0:0] connection_r3_w;
wire [51:0] operation_r1_w;
wire [8:0] operation_r2_w;
wire [1:0] operation_r3_w;
// synopsys translate_off
initial
connection_dffe0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe0 <= 9'b0;
else if (clken == 1'b1) connection_dffe0 <= {operation_r1_w[51], operation_r1_w[47], operation_r1_w[41], operation_r1_w[35], operation_r1_w[29], operation_r1_w[23], operation_r1_w[17], operation_r1_w[11], operation_r1_w[5]};
// synopsys translate_off
initial
connection_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe1 <= 2'b0;
else if (clken == 1'b1) connection_dffe1 <= {operation_r2_w[8], operation_r2_w[5]};
// synopsys translate_off
initial
connection_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe2 <= 1'b0;
else if (clken == 1'b1) connection_dffe2 <= {operation_r3_w[1]};
assign
connection_r0_w = data,
connection_r1_w = connection_dffe0,
connection_r2_w = connection_dffe1,
connection_r3_w = connection_dffe2,
operation_r1_w = {(operation_r1_w[50] | connection_r0_w[51]), (operation_r1_w[49] | connection_r0_w[50]), (operation_r1_w[48] | connection_r0_w[49]), connection_r0_w[48], (operation_r1_w[46] | connection_r0_w[47]), (operation_r1_w[45] | connection_r0_w[46]), (operation_r1_w[44] | connection_r0_w[45]), (operation_r1_w[43] | connection_r0_w[44]), (operation_r1_w[42] | connection_r0_w[43]), connection_r0_w[42], (operation_r1_w[40] | connection_r0_w[41]), (operation_r1_w[39] | connection_r0_w[40]), (operation_r1_w[38] | connection_r0_w[39]), (operation_r1_w[37] | connection_r0_w[38]), (operation_r1_w[36] | connection_r0_w[37]), connection_r0_w[36], (operation_r1_w[34] | connection_r0_w[35]), (operation_r1_w[33] | connection_r0_w[34]), (operation_r1_w[32] | connection_r0_w[33]), (operation_r1_w[31] | connection_r0_w[32]), (operation_r1_w[30] | connection_r0_w[31]), connection_r0_w[30], (operation_r1_w[28] | connection_r0_w[29]), (operation_r1_w[27] | connection_r0_w[28]), (operation_r1_w[26] | connection_r0_w[27]), (operation_r1_w[25] | connection_r0_w[26]), (operation_r1_w[24] | connection_r0_w[25]), connection_r0_w[24], (operation_r1_w[22] | connection_r0_w[23]), (operation_r1_w[21] | connection_r0_w[22]), (operation_r1_w[20] | connection_r0_w[21]), (operation_r1_w[19] | connection_r0_w[20]), (operation_r1_w[18] | connection_r0_w[19]), connection_r0_w[18], (operation_r1_w[16] | connection_r0_w[17]), (operation_r1_w[15] | connection_r0_w[16]), (operation_r1_w[14] | connection_r0_w[15]), (operation_r1_w[13] | connection_r0_w[14]), (operation_r1_w[12] | connection_r0_w[13]), connection_r0_w[12], (operation_r1_w[10] | connection_r0_w[11]), (operation_r1_w[9] | connection_r0_w[10]), (operation_r1_w[8] | connection_r0_w[9]), (operation_r1_w[7] | connection_r0_w[8]), (operation_r1_w[6] | connection_r0_w[7]), connection_r0_w[6], (operation_r1_w[4] | connection_r0_w[5]), (operation_r1_w[3] | connection_r0_w[4]), (operation_r1_w[2] | connection_r0_w[3]), (operation_r1_w[1] | connection_r0_w[2]), (operation_r1_w[0] | connection_r0_w[1]
), connection_r0_w[0]},
operation_r2_w = {(operation_r2_w[7] | connection_r1_w[8]), (operation_r2_w[6] | connection_r1_w[7]), connection_r1_w[6], (operation_r2_w[4] | connection_r1_w[5]), (operation_r2_w[3] | connection_r1_w[4]), (operation_r2_w[2] | connection_r1_w[3]), (operation_r2_w[1] | connection_r1_w[2]), (operation_r2_w[0] | connection_r1_w[1]), connection_r1_w[0]},
operation_r3_w = {(operation_r3_w[0] | connection_r2_w[1]), connection_r2_w[0]},
result = connection_r3_w[0];
endmodule //acl_fp_log_s5_double_altfp_log_and_or_e8b
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=83 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_r0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [82:0] dataa;
input [82:0] datab;
output [82:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [82:0] dataa;
tri0 [82:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [41:0] wire_csa_lower_result;
wire [40:0] wire_csa_upper0_result;
wire [40:0] wire_csa_upper1_result;
wire [82:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[41:0]),
.datab(datab[41:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 42,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[82:42]),
.datab(datab[82:42]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 41,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[82:42]),
.datab(datab[82:42]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 41,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({41{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({41{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_r0e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=63 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_p0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [62:0] dataa;
input [62:0] datab;
output [62:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [62:0] dataa;
tri0 [62:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [31:0] wire_csa_lower_result;
wire [30:0] wire_csa_upper0_result;
wire [30:0] wire_csa_upper1_result;
wire [62:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[31:0]),
.datab(datab[31:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 32,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[62:32]),
.datab(datab[62:32]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 31,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[62:32]),
.datab(datab[62:32]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 31,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({31{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({31{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_p0e
//altfp_log_csa CARRY_SELECT="NO" CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=11 dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_aoc
(
dataa,
datab,
result) ;
input [10:0] dataa;
input [10:0] datab;
output [10:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [10:0] dataa;
tri0 [10:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [10:0] wire_add_sub1_result;
wire [10:0] result_w;
lpm_add_sub add_sub1
(
.cout(),
.dataa(dataa),
.datab(datab),
.overflow(),
.result(wire_add_sub1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub1.lpm_direction = "SUB",
add_sub1.lpm_representation = "UNSIGNED",
add_sub1.lpm_width = 11,
add_sub1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = wire_add_sub1_result;
endmodule //acl_fp_log_s5_double_altfp_log_csa_aoc
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=26 dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_i4b
(
dataa,
datab,
result) ;
input [25:0] dataa;
input [25:0] datab;
output [25:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [25:0] dataa;
tri0 [25:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [12:0] wire_csa_lower_result;
wire [12:0] wire_csa_upper0_result;
wire [12:0] wire_csa_upper1_result;
wire [25:0] result_w;
lpm_add_sub csa_lower
(
.cout(wire_csa_lower_cout),
.dataa(dataa[12:0]),
.datab(datab[12:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "SUB",
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 13,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.cin(1'b0),
.cout(),
.dataa(dataa[25:13]),
.datab(datab[25:13]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "SUB",
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 13,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.cin(1'b1),
.cout(),
.dataa(dataa[25:13]),
.datab(datab[25:13]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "SUB",
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 13,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({13{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({13{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_i4b
//altfp_log_csa CARRY_SELECT="NO" CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=7 dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_vmc
(
dataa,
datab,
result) ;
input [6:0] dataa;
input [6:0] datab;
output [6:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [6:0] dataa;
tri0 [6:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [6:0] wire_add_sub2_result;
wire [6:0] result_w;
lpm_add_sub add_sub2
(
.cout(),
.dataa(dataa),
.datab(datab),
.overflow(),
.result(wire_add_sub2_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub2.lpm_direction = "SUB",
add_sub2.lpm_representation = "UNSIGNED",
add_sub2.lpm_width = 7,
add_sub2.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = wire_add_sub2_result;
endmodule //acl_fp_log_s5_double_altfp_log_csa_vmc
//altfp_log_csa CARRY_SELECT="NO" CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=55 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_plf
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [54:0] dataa;
input [54:0] datab;
output [54:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [54:0] dataa;
tri0 [54:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [54:0] wire_add_sub3_result;
wire [54:0] result_w;
lpm_add_sub add_sub3
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa),
.datab(datab),
.overflow(),
.result(wire_add_sub3_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub3.lpm_direction = "SUB",
add_sub3.lpm_pipeline = 1,
add_sub3.lpm_representation = "UNSIGNED",
add_sub3.lpm_width = 55,
add_sub3.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = wire_add_sub3_result;
endmodule //acl_fp_log_s5_double_altfp_log_csa_plf
//altfp_log_csa CARRY_SELECT="NO" CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=2 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=11 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_ilf
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [10:0] dataa;
input [10:0] datab;
output [10:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [10:0] dataa;
tri0 [10:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [10:0] wire_add_sub4_result;
wire [10:0] result_w;
lpm_add_sub add_sub4
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa),
.datab(datab),
.overflow(),
.result(wire_add_sub4_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub4.lpm_direction = "SUB",
add_sub4.lpm_pipeline = 2,
add_sub4.lpm_representation = "UNSIGNED",
add_sub4.lpm_width = 11,
add_sub4.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = wire_add_sub4_result;
endmodule //acl_fp_log_s5_double_altfp_log_csa_ilf
//altfp_log_rr_block CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix V" WIDTH_ALMOSTLOG=83 WIDTH_Y0=54 WIDTH_Z=55 a0_in aclr almostlog clk_en clock y0_in z
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=60 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_m0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [59:0] dataa;
input [59:0] datab;
output [59:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [59:0] dataa;
tri0 [59:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [29:0] wire_csa_lower_result;
wire [29:0] wire_csa_upper0_result;
wire [29:0] wire_csa_upper1_result;
wire [59:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[29:0]),
.datab(datab[29:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 30,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[59:30]),
.datab(datab[59:30]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 30,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[59:30]),
.datab(datab[59:30]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 30,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({30{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({30{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_m0e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=69 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_v0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [68:0] dataa;
input [68:0] datab;
output [68:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [68:0] dataa;
tri0 [68:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [34:0] wire_csa_lower_result;
wire [33:0] wire_csa_upper0_result;
wire [33:0] wire_csa_upper1_result;
wire [68:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[34:0]),
.datab(datab[34:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 35,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[68:35]),
.datab(datab[68:35]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 34,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[68:35]),
.datab(datab[68:35]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 34,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({34{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({34{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_v0e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=70 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_n0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [69:0] dataa;
input [69:0] datab;
output [69:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [69:0] dataa;
tri0 [69:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [34:0] wire_csa_lower_result;
wire [34:0] wire_csa_upper0_result;
wire [34:0] wire_csa_upper1_result;
wire [69:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[34:0]),
.datab(datab[34:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 35,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[69:35]),
.datab(datab[69:35]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 35,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[69:35]),
.datab(datab[69:35]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 35,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({35{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({35{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_n0e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=67 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_t0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [66:0] dataa;
input [66:0] datab;
output [66:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [66:0] dataa;
tri0 [66:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [33:0] wire_csa_lower_result;
wire [32:0] wire_csa_upper0_result;
wire [32:0] wire_csa_upper1_result;
wire [66:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[33:0]),
.datab(datab[33:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 34,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[66:34]),
.datab(datab[66:34]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 33,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[66:34]),
.datab(datab[66:34]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 33,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({33{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({33{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_t0e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=64 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_q0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [63:0] dataa;
input [63:0] datab;
output [63:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [63:0] dataa;
tri0 [63:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [31:0] wire_csa_lower_result;
wire [31:0] wire_csa_upper0_result;
wire [31:0] wire_csa_upper1_result;
wire [63:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[31:0]),
.datab(datab[31:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 32,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[63:32]),
.datab(datab[63:32]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 32,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[63:32]),
.datab(datab[63:32]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 32,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({32{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({32{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_q0e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=61 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_o0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [60:0] dataa;
input [60:0] datab;
output [60:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [60:0] dataa;
tri0 [60:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [30:0] wire_csa_lower_result;
wire [29:0] wire_csa_upper0_result;
wire [29:0] wire_csa_upper1_result;
wire [60:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[30:0]),
.datab(datab[30:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 31,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[60:31]),
.datab(datab[60:31]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 30,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[60:31]),
.datab(datab[60:31]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 30,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({30{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({30{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_o0e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=58 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_u0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [57:0] dataa;
input [57:0] datab;
output [57:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [57:0] dataa;
tri0 [57:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [28:0] wire_csa_lower_result;
wire [28:0] wire_csa_upper0_result;
wire [28:0] wire_csa_upper1_result;
wire [57:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[28:0]),
.datab(datab[28:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 29,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[57:29]),
.datab(datab[57:29]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 29,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[57:29]),
.datab(datab[57:29]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 29,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({29{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({29{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_u0e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=55 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_s0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [54:0] dataa;
input [54:0] datab;
output [54:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [54:0] dataa;
tri0 [54:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [27:0] wire_csa_lower_result;
wire [26:0] wire_csa_upper0_result;
wire [26:0] wire_csa_upper1_result;
wire [54:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[27:0]),
.datab(datab[27:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 28,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[54:28]),
.datab(datab[54:28]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 27,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[54:28]),
.datab(datab[54:28]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 27,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({27{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({27{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_s0e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=60 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_n1e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [59:0] dataa;
input [59:0] datab;
output [59:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [59:0] dataa;
tri0 [59:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [29:0] wire_csa_lower_result;
wire [29:0] wire_csa_upper0_result;
wire [29:0] wire_csa_upper1_result;
wire [59:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[29:0]),
.datab(datab[29:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "SUB",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 30,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[59:30]),
.datab(datab[59:30]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "SUB",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 30,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[59:30]),
.datab(datab[59:30]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "SUB",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 30,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({30{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({30{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_n1e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=69 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_02e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [68:0] dataa;
input [68:0] datab;
output [68:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [68:0] dataa;
tri0 [68:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [34:0] wire_csa_lower_result;
wire [33:0] wire_csa_upper0_result;
wire [33:0] wire_csa_upper1_result;
wire [68:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[34:0]),
.datab(datab[34:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "SUB",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 35,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[68:35]),
.datab(datab[68:35]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "SUB",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 34,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[68:35]),
.datab(datab[68:35]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "SUB",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 34,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({34{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({34{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_02e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=70 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_o1e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [69:0] dataa;
input [69:0] datab;
output [69:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [69:0] dataa;
tri0 [69:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [34:0] wire_csa_lower_result;
wire [34:0] wire_csa_upper0_result;
wire [34:0] wire_csa_upper1_result;
wire [69:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[34:0]),
.datab(datab[34:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "SUB",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 35,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[69:35]),
.datab(datab[69:35]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "SUB",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 35,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[69:35]),
.datab(datab[69:35]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "SUB",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 35,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({35{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({35{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_o1e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=67 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_u1e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [66:0] dataa;
input [66:0] datab;
output [66:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [66:0] dataa;
tri0 [66:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [33:0] wire_csa_lower_result;
wire [32:0] wire_csa_upper0_result;
wire [32:0] wire_csa_upper1_result;
wire [66:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[33:0]),
.datab(datab[33:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "SUB",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 34,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[66:34]),
.datab(datab[66:34]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "SUB",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 33,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[66:34]),
.datab(datab[66:34]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "SUB",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 33,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({33{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({33{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_u1e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=64 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_r1e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [63:0] dataa;
input [63:0] datab;
output [63:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [63:0] dataa;
tri0 [63:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [31:0] wire_csa_lower_result;
wire [31:0] wire_csa_upper0_result;
wire [31:0] wire_csa_upper1_result;
wire [63:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[31:0]),
.datab(datab[31:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "SUB",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 32,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[63:32]),
.datab(datab[63:32]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "SUB",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 32,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[63:32]),
.datab(datab[63:32]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "SUB",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 32,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({32{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({32{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_r1e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=61 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_p1e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [60:0] dataa;
input [60:0] datab;
output [60:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [60:0] dataa;
tri0 [60:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [30:0] wire_csa_lower_result;
wire [29:0] wire_csa_upper0_result;
wire [29:0] wire_csa_upper1_result;
wire [60:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[30:0]),
.datab(datab[30:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "SUB",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 31,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[60:31]),
.datab(datab[60:31]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "SUB",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 30,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[60:31]),
.datab(datab[60:31]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "SUB",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 30,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({30{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({30{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_p1e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=58 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_v1e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [57:0] dataa;
input [57:0] datab;
output [57:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [57:0] dataa;
tri0 [57:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [28:0] wire_csa_lower_result;
wire [28:0] wire_csa_upper0_result;
wire [28:0] wire_csa_upper1_result;
wire [57:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[28:0]),
.datab(datab[28:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "SUB",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 29,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[57:29]),
.datab(datab[57:29]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "SUB",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 29,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[57:29]),
.datab(datab[57:29]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "SUB",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 29,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({29{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({29{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_v1e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=55 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_s1e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [54:0] dataa;
input [54:0] datab;
output [54:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [54:0] dataa;
tri0 [54:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [27:0] wire_csa_lower_result;
wire [26:0] wire_csa_upper0_result;
wire [26:0] wire_csa_upper1_result;
wire [54:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[27:0]),
.datab(datab[27:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "SUB",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 28,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[54:28]),
.datab(datab[54:28]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "SUB",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 27,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[54:28]),
.datab(datab[54:28]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "SUB",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 27,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({27{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({27{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_s1e
//synthesis_resources = lpm_add_sub 72 lpm_mult 9 lpm_mux 10 reg 2344
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_range_reduction_3sd
(
a0_in,
aclr,
almostlog,
clk_en,
clock,
y0_in,
z) ;
input [4:0] a0_in;
input aclr;
output [82:0] almostlog;
input clk_en;
input clock;
input [53:0] y0_in;
output [54:0] z;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [82:0] wire_add0_1_result;
wire [82:0] wire_add0_2_result;
wire [82:0] wire_add0_3_result;
wire [82:0] wire_add0_4_result;
wire [82:0] wire_add0_5_result;
wire [82:0] wire_add0_6_result;
wire [82:0] wire_add0_7_result;
wire [82:0] wire_add0_8_result;
wire [59:0] wire_add1_1_result;
wire [68:0] wire_add1_2_result;
wire [69:0] wire_add1_3_result;
wire [66:0] wire_add1_4_result;
wire [63:0] wire_add1_5_result;
wire [60:0] wire_add1_6_result;
wire [57:0] wire_add1_7_result;
wire [54:0] wire_add1_8_result;
wire [59:0] wire_sub1_1_result;
wire [68:0] wire_sub1_2_result;
wire [69:0] wire_sub1_3_result;
wire [66:0] wire_sub1_4_result;
wire [63:0] wire_sub1_5_result;
wire [60:0] wire_sub1_6_result;
wire [57:0] wire_sub1_7_result;
wire [54:0] wire_sub1_8_result;
reg [4:0] A_pipe0_reg0;
reg [4:0] A_pipe0_reg1;
reg [3:0] A_wire1_reg0;
reg [3:0] A_wire2_reg0;
reg [3:0] A_wire3_reg0;
reg [3:0] A_wire4_reg0;
reg [3:0] A_wire5_reg0;
reg [3:0] A_wire6_reg0;
reg [3:0] A_wire7_reg0;
reg [3:0] A_wire8_reg0;
reg [49:0] B_wire1_reg0;
reg [55:0] B_wire2_reg0;
reg [64:0] B_wire3_reg0;
reg [65:0] B_wire4_reg0;
reg [62:0] B_wire5_reg0;
reg [59:0] B_wire6_reg0;
reg [56:0] B_wire7_reg0;
reg [53:0] B_wire8_reg0;
reg [82:0] S_pipe22_reg0;
reg [82:0] S_pipe23_reg0;
reg [82:0] S_pipe24_reg0;
reg [82:0] S_pipe25_reg0;
reg [82:0] S_pipe26_reg0;
reg [82:0] S_pipe27_reg0;
reg [82:0] S_pipe28_reg0;
reg [82:0] S_pipe29_reg0;
reg [82:0] S_wire1_reg0;
reg [82:0] S_wire2_reg0;
reg [82:0] S_wire3_reg0;
reg [82:0] S_wire4_reg0;
reg [82:0] S_wire5_reg0;
reg [82:0] S_wire6_reg0;
reg [82:0] S_wire7_reg0;
reg [82:0] S_wire8_reg0;
reg [53:0] Z_wire1_reg0;
reg [59:0] Z_wire2_reg0;
reg [68:0] Z_wire3_reg0;
reg [69:0] Z_wire4_reg0;
reg [66:0] Z_wire5_reg0;
reg [63:0] Z_wire6_reg0;
reg [60:0] Z_wire7_reg0;
reg [57:0] Z_wire8_reg0;
wire [59:0] wire_mult0_result;
wire [57:0] wire_mult1_result;
wire [63:0] wire_mult2_result;
wire [66:0] wire_mult3_result;
wire [60:0] wire_mult4_result;
wire [54:0] wire_mult5_result;
wire [48:0] wire_mult6_result;
wire [42:0] wire_mult7_result;
wire [36:0] wire_mult8_result;
wire [5:0] wire_InvTable0_result;
wire [82:0] wire_LogTable0_result;
wire [78:0] wire_LogTable1_result;
wire [75:0] wire_LogTable2_result;
wire [72:0] wire_LogTable3_result;
wire [69:0] wire_LogTable4_result;
wire [66:0] wire_LogTable5_result;
wire [63:0] wire_LogTable6_result;
wire [60:0] wire_LogTable7_result;
wire [57:0] wire_LogTable8_result;
wire [3:0] A1_is_all_zero;
wire [3:0] A1_is_not_zero;
wire [3:0] A_all_zero2;
wire [3:0] A_all_zero3;
wire [3:0] A_all_zero4;
wire [3:0] A_all_zero5;
wire [3:0] A_all_zero6;
wire [3:0] A_all_zero7;
wire [3:0] A_all_zero8;
wire [4:0] A_pipe0;
wire [3:0] A_pipe11;
wire [3:0] A_pipe12;
wire [3:0] A_pipe13;
wire [3:0] A_pipe14;
wire [3:0] A_pipe15;
wire [3:0] A_pipe16;
wire [3:0] A_pipe17;
wire [3:0] A_pipe18;
wire [4:0] A_wire0;
wire [3:0] A_wire1;
wire [3:0] A_wire2;
wire [3:0] A_wire3;
wire [3:0] A_wire4;
wire [3:0] A_wire5;
wire [3:0] A_wire6;
wire [3:0] A_wire7;
wire [3:0] A_wire8;
wire [59:0] B_pad_wire1;
wire [68:0] B_pad_wire2;
wire [69:0] B_pad_wire3;
wire [66:0] B_pad_wire4;
wire [63:0] B_pad_wire5;
wire [60:0] B_pad_wire6;
wire [57:0] B_pad_wire7;
wire [54:0] B_pad_wire8;
wire [49:0] B_pipe1;
wire [55:0] B_pipe2;
wire [64:0] B_pipe3;
wire [65:0] B_pipe4;
wire [62:0] B_pipe5;
wire [59:0] B_pipe6;
wire [56:0] B_pipe7;
wire [53:0] B_pipe8;
wire [49:0] B_wire1;
wire [55:0] B_wire2;
wire [64:0] B_wire3;
wire [65:0] B_wire4;
wire [62:0] B_wire5;
wire [59:0] B_wire6;
wire [56:0] B_wire7;
wire [53:0] B_wire8;
wire [59:0] epsZ_pad_wire1;
wire [68:0] epsZ_pad_wire2;
wire [69:0] epsZ_pad_wire3;
wire [66:0] epsZ_pad_wire4;
wire [63:0] epsZ_pad_wire5;
wire [60:0] epsZ_pad_wire6;
wire [57:0] epsZ_pad_wire7;
wire [54:0] epsZ_pad_wire8;
wire [59:0] epsZ_wire1;
wire [68:0] epsZ_wire2;
wire [80:0] epsZ_wire3;
wire [84:0] epsZ_wire4;
wire [84:0] epsZ_wire5;
wire [84:0] epsZ_wire6;
wire [84:0] epsZ_wire7;
wire [84:0] epsZ_wire8;
wire [5:0] InvA0;
wire [82:0] L_wire0;
wire [78:0] L_wire1;
wire [75:0] L_wire2;
wire [72:0] L_wire3;
wire [69:0] L_wire4;
wire [66:0] L_wire5;
wire [63:0] L_wire6;
wire [60:0] L_wire7;
wire [57:0] L_wire8;
wire [59:0] mux0_data0;
wire [59:0] mux0_data1;
wire [59:0] P_pad_wire1;
wire [68:0] P_pad_wire2;
wire [69:0] P_pad_wire3;
wire [66:0] P_pad_wire4;
wire [63:0] P_pad_wire5;
wire [60:0] P_pad_wire6;
wire [57:0] P_pad_wire7;
wire [54:0] P_pad_wire8;
wire [59:0] P_wire0;
wire [57:0] P_wire1;
wire [63:0] P_wire2;
wire [66:0] P_wire3;
wire [60:0] P_wire4;
wire [54:0] P_wire5;
wire [48:0] P_wire6;
wire [42:0] P_wire7;
wire [36:0] P_wire8;
wire [82:0] S_pipe11;
wire [82:0] S_pipe12;
wire [82:0] S_pipe13;
wire [82:0] S_pipe14;
wire [82:0] S_pipe15;
wire [82:0] S_pipe16;
wire [82:0] S_pipe17;
wire [82:0] S_pipe18;
wire [82:0] S_pipe22;
wire [82:0] S_pipe23;
wire [82:0] S_pipe24;
wire [82:0] S_pipe25;
wire [82:0] S_pipe26;
wire [82:0] S_pipe27;
wire [82:0] S_pipe28;
wire [82:0] S_pipe29;
wire [82:0] S_wire1;
wire [82:0] S_wire2;
wire [82:0] S_wire3;
wire [82:0] S_wire4;
wire [82:0] S_wire5;
wire [82:0] S_wire6;
wire [82:0] S_wire7;
wire [82:0] S_wire8;
wire [82:0] S_wire9;
wire [53:0] Z_pipe1;
wire [59:0] Z_pipe2;
wire [68:0] Z_pipe3;
wire [69:0] Z_pipe4;
wire [66:0] Z_pipe5;
wire [63:0] Z_pipe6;
wire [60:0] Z_pipe7;
wire [57:0] Z_pipe8;
wire [53:0] Z_wire1;
wire [59:0] Z_wire2;
wire [68:0] Z_wire3;
wire [69:0] Z_wire4;
wire [66:0] Z_wire5;
wire [63:0] Z_wire6;
wire [60:0] Z_wire7;
wire [57:0] Z_wire8;
wire [54:0] Z_wire9;
wire [53:0] ZM_wire1;
wire [59:0] ZM_wire2;
wire [62:0] ZM_wire3;
wire [56:0] ZM_wire4;
wire [50:0] ZM_wire5;
wire [44:0] ZM_wire6;
wire [38:0] ZM_wire7;
wire [32:0] ZM_wire8;
acl_fp_log_s5_double_altfp_log_csa_r0e add0_1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(S_pipe11),
.datab({{4{1'b0}}, L_wire1}),
.result(wire_add0_1_result));
acl_fp_log_s5_double_altfp_log_csa_r0e add0_2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(S_pipe12),
.datab({{7{1'b0}}, L_wire2}),
.result(wire_add0_2_result));
acl_fp_log_s5_double_altfp_log_csa_r0e add0_3
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(S_pipe13),
.datab({{10{1'b0}}, L_wire3}),
.result(wire_add0_3_result));
acl_fp_log_s5_double_altfp_log_csa_r0e add0_4
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(S_pipe14),
.datab({{13{1'b0}}, L_wire4}),
.result(wire_add0_4_result));
acl_fp_log_s5_double_altfp_log_csa_r0e add0_5
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(S_pipe15),
.datab({{16{1'b0}}, L_wire5}),
.result(wire_add0_5_result));
acl_fp_log_s5_double_altfp_log_csa_r0e add0_6
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(S_pipe16),
.datab({{19{1'b0}}, L_wire6}),
.result(wire_add0_6_result));
acl_fp_log_s5_double_altfp_log_csa_r0e add0_7
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(S_pipe17),
.datab({{22{1'b0}}, L_wire7}),
.result(wire_add0_7_result));
acl_fp_log_s5_double_altfp_log_csa_r0e add0_8
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(S_pipe18),
.datab({{25{1'b0}}, L_wire8}),
.result(wire_add0_8_result));
acl_fp_log_s5_double_altfp_log_csa_m0e add1_1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(B_pad_wire1),
.datab(epsZ_pad_wire1),
.result(wire_add1_1_result));
acl_fp_log_s5_double_altfp_log_csa_v0e add1_2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(B_pad_wire2),
.datab(epsZ_pad_wire2),
.result(wire_add1_2_result));
acl_fp_log_s5_double_altfp_log_csa_n0e add1_3
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(B_pad_wire3),
.datab(epsZ_pad_wire3),
.result(wire_add1_3_result));
acl_fp_log_s5_double_altfp_log_csa_t0e add1_4
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(B_pad_wire4),
.datab(epsZ_pad_wire4),
.result(wire_add1_4_result));
acl_fp_log_s5_double_altfp_log_csa_q0e add1_5
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(B_pad_wire5),
.datab(epsZ_pad_wire5),
.result(wire_add1_5_result));
acl_fp_log_s5_double_altfp_log_csa_o0e add1_6
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(B_pad_wire6),
.datab(epsZ_pad_wire6),
.result(wire_add1_6_result));
acl_fp_log_s5_double_altfp_log_csa_u0e add1_7
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(B_pad_wire7),
.datab(epsZ_pad_wire7),
.result(wire_add1_7_result));
acl_fp_log_s5_double_altfp_log_csa_s0e add1_8
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(B_pad_wire8),
.datab(epsZ_pad_wire8),
.result(wire_add1_8_result));
acl_fp_log_s5_double_altfp_log_csa_n1e sub1_1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(wire_add1_1_result),
.datab(P_pad_wire1),
.result(wire_sub1_1_result));
acl_fp_log_s5_double_altfp_log_csa_02e sub1_2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(wire_add1_2_result),
.datab(P_pad_wire2),
.result(wire_sub1_2_result));
acl_fp_log_s5_double_altfp_log_csa_o1e sub1_3
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(wire_add1_3_result),
.datab(P_pad_wire3),
.result(wire_sub1_3_result));
acl_fp_log_s5_double_altfp_log_csa_u1e sub1_4
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(wire_add1_4_result),
.datab(P_pad_wire4),
.result(wire_sub1_4_result));
acl_fp_log_s5_double_altfp_log_csa_r1e sub1_5
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(wire_add1_5_result),
.datab(P_pad_wire5),
.result(wire_sub1_5_result));
acl_fp_log_s5_double_altfp_log_csa_p1e sub1_6
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(wire_add1_6_result),
.datab(P_pad_wire6),
.result(wire_sub1_6_result));
acl_fp_log_s5_double_altfp_log_csa_v1e sub1_7
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(wire_add1_7_result),
.datab(P_pad_wire7),
.result(wire_sub1_7_result));
acl_fp_log_s5_double_altfp_log_csa_s1e sub1_8
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(wire_add1_8_result),
.datab(P_pad_wire8),
.result(wire_sub1_8_result));
// synopsys translate_off
initial
A_pipe0_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_pipe0_reg0 <= 5'b0;
else if (clk_en == 1'b1) A_pipe0_reg0 <= A_pipe0;
// synopsys translate_off
initial
A_pipe0_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_pipe0_reg1 <= 5'b0;
else if (clk_en == 1'b1) A_pipe0_reg1 <= A_pipe0_reg0;
// synopsys translate_off
initial
A_wire1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_wire1_reg0 <= 4'b0;
else if (clk_en == 1'b1) A_wire1_reg0 <= A_wire1;
// synopsys translate_off
initial
A_wire2_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_wire2_reg0 <= 4'b0;
else if (clk_en == 1'b1) A_wire2_reg0 <= A_wire2;
// synopsys translate_off
initial
A_wire3_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_wire3_reg0 <= 4'b0;
else if (clk_en == 1'b1) A_wire3_reg0 <= A_wire3;
// synopsys translate_off
initial
A_wire4_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_wire4_reg0 <= 4'b0;
else if (clk_en == 1'b1) A_wire4_reg0 <= A_wire4;
// synopsys translate_off
initial
A_wire5_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_wire5_reg0 <= 4'b0;
else if (clk_en == 1'b1) A_wire5_reg0 <= A_wire5;
// synopsys translate_off
initial
A_wire6_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_wire6_reg0 <= 4'b0;
else if (clk_en == 1'b1) A_wire6_reg0 <= A_wire6;
// synopsys translate_off
initial
A_wire7_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_wire7_reg0 <= 4'b0;
else if (clk_en == 1'b1) A_wire7_reg0 <= A_wire7;
// synopsys translate_off
initial
A_wire8_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_wire8_reg0 <= 4'b0;
else if (clk_en == 1'b1) A_wire8_reg0 <= A_wire8;
// synopsys translate_off
initial
B_wire1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) B_wire1_reg0 <= 50'b0;
else if (clk_en == 1'b1) B_wire1_reg0 <= B_wire1;
// synopsys translate_off
initial
B_wire2_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) B_wire2_reg0 <= 56'b0;
else if (clk_en == 1'b1) B_wire2_reg0 <= B_wire2;
// synopsys translate_off
initial
B_wire3_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) B_wire3_reg0 <= 65'b0;
else if (clk_en == 1'b1) B_wire3_reg0 <= B_wire3;
// synopsys translate_off
initial
B_wire4_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) B_wire4_reg0 <= 66'b0;
else if (clk_en == 1'b1) B_wire4_reg0 <= B_wire4;
// synopsys translate_off
initial
B_wire5_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) B_wire5_reg0 <= 63'b0;
else if (clk_en == 1'b1) B_wire5_reg0 <= B_wire5;
// synopsys translate_off
initial
B_wire6_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) B_wire6_reg0 <= 60'b0;
else if (clk_en == 1'b1) B_wire6_reg0 <= B_wire6;
// synopsys translate_off
initial
B_wire7_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) B_wire7_reg0 <= 57'b0;
else if (clk_en == 1'b1) B_wire7_reg0 <= B_wire7;
// synopsys translate_off
initial
B_wire8_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) B_wire8_reg0 <= 54'b0;
else if (clk_en == 1'b1) B_wire8_reg0 <= B_wire8;
// synopsys translate_off
initial
S_pipe22_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_pipe22_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_pipe22_reg0 <= S_pipe22;
// synopsys translate_off
initial
S_pipe23_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_pipe23_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_pipe23_reg0 <= S_pipe23;
// synopsys translate_off
initial
S_pipe24_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_pipe24_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_pipe24_reg0 <= S_pipe24;
// synopsys translate_off
initial
S_pipe25_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_pipe25_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_pipe25_reg0 <= S_pipe25;
// synopsys translate_off
initial
S_pipe26_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_pipe26_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_pipe26_reg0 <= S_pipe26;
// synopsys translate_off
initial
S_pipe27_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_pipe27_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_pipe27_reg0 <= S_pipe27;
// synopsys translate_off
initial
S_pipe28_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_pipe28_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_pipe28_reg0 <= S_pipe28;
// synopsys translate_off
initial
S_pipe29_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_pipe29_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_pipe29_reg0 <= S_pipe29;
// synopsys translate_off
initial
S_wire1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_wire1_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_wire1_reg0 <= S_wire1;
// synopsys translate_off
initial
S_wire2_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_wire2_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_wire2_reg0 <= S_wire2;
// synopsys translate_off
initial
S_wire3_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_wire3_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_wire3_reg0 <= S_wire3;
// synopsys translate_off
initial
S_wire4_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_wire4_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_wire4_reg0 <= S_wire4;
// synopsys translate_off
initial
S_wire5_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_wire5_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_wire5_reg0 <= S_wire5;
// synopsys translate_off
initial
S_wire6_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_wire6_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_wire6_reg0 <= S_wire6;
// synopsys translate_off
initial
S_wire7_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_wire7_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_wire7_reg0 <= S_wire7;
// synopsys translate_off
initial
S_wire8_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_wire8_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_wire8_reg0 <= S_wire8;
// synopsys translate_off
initial
Z_wire1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z_wire1_reg0 <= 54'b0;
else if (clk_en == 1'b1) Z_wire1_reg0 <= Z_wire1;
// synopsys translate_off
initial
Z_wire2_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z_wire2_reg0 <= 60'b0;
else if (clk_en == 1'b1) Z_wire2_reg0 <= Z_wire2;
// synopsys translate_off
initial
Z_wire3_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z_wire3_reg0 <= 69'b0;
else if (clk_en == 1'b1) Z_wire3_reg0 <= Z_wire3;
// synopsys translate_off
initial
Z_wire4_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z_wire4_reg0 <= 70'b0;
else if (clk_en == 1'b1) Z_wire4_reg0 <= Z_wire4;
// synopsys translate_off
initial
Z_wire5_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z_wire5_reg0 <= 67'b0;
else if (clk_en == 1'b1) Z_wire5_reg0 <= Z_wire5;
// synopsys translate_off
initial
Z_wire6_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z_wire6_reg0 <= 64'b0;
else if (clk_en == 1'b1) Z_wire6_reg0 <= Z_wire6;
// synopsys translate_off
initial
Z_wire7_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z_wire7_reg0 <= 61'b0;
else if (clk_en == 1'b1) Z_wire7_reg0 <= Z_wire7;
// synopsys translate_off
initial
Z_wire8_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z_wire8_reg0 <= 58'b0;
else if (clk_en == 1'b1) Z_wire8_reg0 <= Z_wire8;
lpm_mult mult0
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(InvA0),
.datab(y0_in),
.result(wire_mult0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult0.lpm_pipeline = 2,
mult0.lpm_representation = "UNSIGNED",
mult0.lpm_widtha = 6,
mult0.lpm_widthb = 54,
mult0.lpm_widthp = 60,
mult0.lpm_type = "lpm_mult";
lpm_mult mult1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(A_wire1),
.datab(ZM_wire1),
.result(wire_mult1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult1.lpm_pipeline = 2,
mult1.lpm_representation = "UNSIGNED",
mult1.lpm_widtha = 4,
mult1.lpm_widthb = 54,
mult1.lpm_widthp = 58,
mult1.lpm_type = "lpm_mult";
lpm_mult mult2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(A_wire2),
.datab(ZM_wire2),
.result(wire_mult2_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult2.lpm_pipeline = 2,
mult2.lpm_representation = "UNSIGNED",
mult2.lpm_widtha = 4,
mult2.lpm_widthb = 60,
mult2.lpm_widthp = 64,
mult2.lpm_type = "lpm_mult";
lpm_mult mult3
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(A_wire3),
.datab(ZM_wire3),
.result(wire_mult3_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult3.lpm_pipeline = 2,
mult3.lpm_representation = "UNSIGNED",
mult3.lpm_widtha = 4,
mult3.lpm_widthb = 63,
mult3.lpm_widthp = 67,
mult3.lpm_type = "lpm_mult";
lpm_mult mult4
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(A_wire4),
.datab(ZM_wire4),
.result(wire_mult4_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult4.lpm_pipeline = 2,
mult4.lpm_representation = "UNSIGNED",
mult4.lpm_widtha = 4,
mult4.lpm_widthb = 57,
mult4.lpm_widthp = 61,
mult4.lpm_type = "lpm_mult";
lpm_mult mult5
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(A_wire5),
.datab(ZM_wire5),
.result(wire_mult5_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult5.lpm_pipeline = 2,
mult5.lpm_representation = "UNSIGNED",
mult5.lpm_widtha = 4,
mult5.lpm_widthb = 51,
mult5.lpm_widthp = 55,
mult5.lpm_type = "lpm_mult";
lpm_mult mult6
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(A_wire6),
.datab(ZM_wire6),
.result(wire_mult6_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult6.lpm_pipeline = 2,
mult6.lpm_representation = "UNSIGNED",
mult6.lpm_widtha = 4,
mult6.lpm_widthb = 45,
mult6.lpm_widthp = 49,
mult6.lpm_type = "lpm_mult";
lpm_mult mult7
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(A_wire7),
.datab(ZM_wire7),
.result(wire_mult7_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult7.lpm_pipeline = 2,
mult7.lpm_representation = "UNSIGNED",
mult7.lpm_widtha = 4,
mult7.lpm_widthb = 39,
mult7.lpm_widthp = 43,
mult7.lpm_type = "lpm_mult";
lpm_mult mult8
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(A_wire8),
.datab(ZM_wire8),
.result(wire_mult8_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult8.lpm_pipeline = 2,
mult8.lpm_representation = "UNSIGNED",
mult8.lpm_widtha = 4,
mult8.lpm_widthb = 33,
mult8.lpm_widthp = 37,
mult8.lpm_type = "lpm_mult";
lpm_mux InvTable0
(
.data({6'b100001, {2{6'b100010}}, {2{6'b100011}}, {2{6'b100100}}, 6'b100101, {2{6'b100110}}, 6'b100111, 6'b101000, {2{6'b101001}}, 6'b101010, 6'b101011, 6'b010110, {2{6'b010111}}, {2{6'b011000}}, {2{6'b011001}}, 6'b011010, {2{6'b011011}}, 6'b011100, 6'b011101, 6'b011110, 6'b011111, {2{6'b100000}}}),
.result(wire_InvTable0_result),
.sel(a0_in)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
InvTable0.lpm_size = 32,
InvTable0.lpm_width = 6,
InvTable0.lpm_widths = 5,
InvTable0.lpm_type = "lpm_mux";
lpm_mux LogTable0
(
.data({83'b11111000000111110101100100111100011000011111001100111111111011001100000111000001000, {2{83'b11110000011110101110011110011111111101110100111010101100110011110100000110011011011}}, {2{83'b11101001000011110010110101110101000110101001010010110100011001000001101101100110011}}, {2{83'b11100001110110001111100010010001110101010000110100011010000101100001010101111000001}}, 83'b11011010110101010101101000001111110000000001010110111001011001111111010001000111001, {2{83'b11010100000000011001111100011110101100001101100001011000011011110001100000111100000}}, 83'b11001101010110110100101011000110000101110101001010010111000100110111110110011111001, 83'b11000110111000000001000001110000110010101100101110111100101001111011010001001111111, {2{83'b11000000100011011100111100100101010000111000001110101010111001010101010101110011010}}, 83'b10111010011000101000110101010001010100010110011111000111111100011000110011100000110, 83'b10110100010111000111010100010100011110111000101100111101100011110100110011011011101, 83'b01011111111010111110100011101111011000000101010001101111101101111001101111110110110, {2{83'b01010100100010101011100000011100111000101000111101011111001110000100000010110010011}}, {2{83'b01001001101001011000100001000100110100110110111001001001111000001110111110101101110}}, {2{83'b00111111001100100011100011011001011001110110011011110010111110110011001010000011001}}, 83'b00110101001001111101101001111001000101011011001111000110110111100101011111010100111, {2{83'b00101011011111101000000011010110101010000111101101100011111101110000010100100101110}}, 83'b00100010001011110001110100000100010011111100100011110111101111000110011100010110100, 83'b00011001001100110101111001011101010110010100100110001000101011100001110101011110101, 83'b00010000100001011001100010110101100111100011101000000110100010001010001111111101100, 83'b00001000001000001010111011000100111100111010001000100010001110000000101110011110001, {2{{83{1'b0}}}}}),
.result(wire_LogTable0_result),
.sel(A_wire0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable0.lpm_size = 32,
LogTable0.lpm_width = 83,
LogTable0.lpm_widths = 5,
LogTable0.lpm_type = "lpm_mux";
lpm_mux LogTable1
(
.data({79'b1110011001011011100111100110111011101101100101100101110000110110111000001001111, 79'b1101010101110111100101101000011111011000100001111110000011010001101010011101110, 79'b1100010010100101010100001010010011111101100110100001100110101000101111101001011, 79'b1011001111100100101001111001011010100101110110101100001000001000001001111100110, 79'b1010001100110101011101101010000101101111000111110100110001100100010100100001000, 79'b1001001010010111100110010111110001101000110000011111010011010111000000010000110, 79'b1000001000001010111011000100111100111010001000100010001110000000101110011110001, 79'b0111000110001111010010111011000001010010101010111100011000110001111111001111010, 79'b0110100101010111110101010010001100010111000100001111110001111011000001101001011, 79'b0101100011110101100001011110000110100100001011110101011111100111000100101011001, 79'b0100100010100011111011000111111110101000101110001001111100011001010000100100110, 79'b0011100001100010111001110000100110001110101111100000110011000000001100010000010, 79'b0010100000110010010100111111001011010000011001011101111100011101010101110100000, 79'b0001100000010010000100100001010001011000011010110101010000001110000010100101110, 79'b0000100000000010000000001010101011101010110001000100111011110011100000110011100, {79{1'b0}}}),
.result(wire_LogTable1_result),
.sel(A_pipe11)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable1.lpm_size = 16,
LogTable1.lpm_width = 79,
LogTable1.lpm_widths = 4,
LogTable1.lpm_type = "lpm_mux";
lpm_mux LogTable2
(
.data({76'b1110100011010011001111110110100010100111001100001111110101111111001001110100, 76'b1101100010110111000011100000110011011110011000000001100101010100010111011111, 76'b1100100010011100111000111000001001010110011011011110010110000111001001101001, 76'b1011100010000100101111110100011010010111010101011001111111111010110110101110, 76'b1010100001101110101000001101011101011010010000110010101110000000011000110100, 76'b1001100001011010100001111011001010001001011110100101100010011110100100010001, 76'b1000100001001000011100110101011001000000001111100011110111011110011100000010, 76'b0111100000111000011000110100000011001010101110001001111110001111111000010011, 76'b0110100000101010010101101111000010100101111000010110011011111010110110000100, 76'b0101100000011110010011011110010001111111011001100010100011110001101001010111, 76'b0100100000010100010001111001101100110101100100011011101110111000101110000001, 76'b0011100000001100010000111001001111010111001100111101110000111000010101010011, 76'b0010100000000110010000010100110110100011100010001110001001101100110001111100, 76'b0001100000000010010000000100100000001010001000011000010100001001100101101001, 76'b0000100000000000010000000000001010101010110010101010110001000100010110011001, {76{1'b0}}}),
.result(wire_LogTable2_result),
.sel(A_pipe12)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable2.lpm_size = 16,
LogTable2.lpm_width = 76,
LogTable2.lpm_widths = 4,
LogTable2.lpm_type = "lpm_mux";
lpm_mux LogTable3
(
.data({73'b1110100000011010010010111111100011100010001000011011011101101010000110000, 73'b1101100000010110110010110011010010100001110101001111100011100100101010000, 73'b1100100000010011100010101000101101101010000101111010001111001010011101000, 73'b1011100000010000100010011111101100111001101100010011100100000000010101011, 73'b1010100000001101110010011000001000001111100000010100110000110100010101011, 73'b1001100000001011010010010001110111101010011111111000001001011100010001010, 73'b1000100000001001000010001100110011001001101110111001000000110100011100100, 73'b0111100000000111000010001000110010101100010111010011100010111110011110101, 73'b0110100000000101010010000101101110010001101001000100101111000000001111101, 73'b0101100000000011110010000011011101111000111010001010010001000010111100001, 73'b0100100000000010100010000001111001100001100110100010011100010010010000000, 73'b0011100000000001100010000000111001001011010000001100000100111011101010100, 73'b0010100000000000110010000000010100110101011111000110011010001101110111111, 73'b0001100000000000010010000000000100100000000001010001000000011000010011010, 73'b0000100000000000000010000000000000001010101010101011101010101010110001000, {73{1'b0}}}),
.result(wire_LogTable3_result),
.sel(A_pipe13)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable3.lpm_size = 16,
LogTable3.lpm_width = 73,
LogTable3.lpm_widths = 4,
LogTable3.lpm_type = "lpm_mux";
lpm_mux LogTable4
(
.data({70'b1110100000000011010010010000111111100001001010111010110111010010001000, 70'b1101100000000010110110010000110011010000110000001110000011100110010110, 70'b1100100000000010011100010000101000101100010110100101101010100001000110, 70'b1011100000000010000100010000011111101011111101110111111011111010011110, 70'b1010100000000001101110010000011000000111100101111011110111101011101101, 70'b1001100000000001011010010000010001110111001110101001001101101111000111, 70'b1000100000000001001000010000001100110010110111111000011101111111111111, 70'b0111100000000000111000010000001000110010100001100010111000011010100010, 70'b0110100000000000101010010000000101101110001011100010011100111011101110, 70'b0101100000000000011110010000000011011101110101110001111011100001010000, 70'b0100100000000000010100010000000001111001100000001100110100001001011100, 70'b0011100000000000001100010000000000111001001010101111010110110011000100, 70'b0010100000000000000110010000000000010100110101010110100011011101011010, 70'b0001100000000000000010010000000000000100100000000000001010001000000000, 70'b0000100000000000000000010000000000000000001010101010101010110010101010, {70{1'b0}}}),
.result(wire_LogTable4_result),
.sel(A_pipe14)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable4.lpm_size = 16,
LogTable4.lpm_width = 70,
LogTable4.lpm_widths = 4,
LogTable4.lpm_type = "lpm_mux";
lpm_mux LogTable5
(
.data({67'b1110100000000000011010010010000000111111100000111000000010000000101, 67'b1101100000000000010110110010000000110011010000100010000001101111110, 67'b1100100000000000010011100010000000101000101100001100001010000010001, 67'b1011100000000000010000100010000000011111101011110110011001101001111, 67'b1010100000000000001101110010000000011000000111100000101111011110110, 67'b1001100000000000001011010010000000010001110111001011001010011110111, 67'b1000100000000000001001000010000000001100110010110101101001101110010, 67'b0111100000000000000111000010000000001000110010100000001100010111000, 67'b0110100000000000000101010010000000000101101110001010110001101000111, 67'b0101100000000000000011110010000000000011011101110101011000111010000, 67'b0100100000000000000010100010000000000001111001100000000001100110100, 67'b0011100000000000000001100010000000000000111001001010101011010000001, 67'b0010100000000000000000110010000000000000010100110101010101011111000, 67'b0001100000000000000000010010000000000000000100100000000000000001010, 67'b0000100000000000000000000010000000000000000000001010101010101010101, {67{1'b0}}}),
.result(wire_LogTable5_result),
.sel(A_pipe15)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable5.lpm_size = 16,
LogTable5.lpm_width = 67,
LogTable5.lpm_widths = 4,
LogTable5.lpm_type = "lpm_mux";
lpm_mux LogTable6
(
.data({64'b1110100000000000000011010010010000000000111111100000110101101010, 64'b1101100000000000000010110110010000000000110011010000100000010000, 64'b1100100000000000000010011100010000000000101000101100001010110110, 64'b1011100000000000000010000100010000000000011111101011110101011101, 64'b1010100000000000000001101110010000000000011000000111100000000101, 64'b1001100000000000000001011010010000000000010001110111001010101110, 64'b1000100000000000000001001000010000000000001100110010110101010111, 64'b0111100000000000000000111000010000000000001000110010100000000001, 64'b0110100000000000000000101010010000000000000101101110001010101011, 64'b0101100000000000000000011110010000000000000011011101110101010101, 64'b0100100000000000000000010100010000000000000001111001100000000000, 64'b0011100000000000000000001100010000000000000000111001001010101010, 64'b0010100000000000000000000110010000000000000000010100110101010101, 64'b0001100000000000000000000010010000000000000000000100100000000000, 64'b0000100000000000000000000000010000000000000000000000001010101010, {64{1'b0}}}),
.result(wire_LogTable6_result),
.sel(A_pipe16)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable6.lpm_size = 16,
LogTable6.lpm_width = 64,
LogTable6.lpm_widths = 4,
LogTable6.lpm_type = "lpm_mux";
lpm_mux LogTable7
(
.data({61'b1110100000000000000000011010010010000000000000111111100000110, 61'b1101100000000000000000010110110010000000000000110011010000100, 61'b1100100000000000000000010011100010000000000000101000101100001, 61'b1011100000000000000000010000100010000000000000011111101011110, 61'b1010100000000000000000001101110010000000000000011000000111100, 61'b1001100000000000000000001011010010000000000000010001110111001, 61'b1000100000000000000000001001000010000000000000001100110010110, 61'b0111100000000000000000000111000010000000000000001000110010100, 61'b0110100000000000000000000101010010000000000000000101101110001, 61'b0101100000000000000000000011110010000000000000000011011101110, 61'b0100100000000000000000000010100010000000000000000001111001100, 61'b0011100000000000000000000001100010000000000000000000111001001, 61'b0010100000000000000000000000110010000000000000000000010100110, 61'b0001100000000000000000000000010010000000000000000000000100100, 61'b0000100000000000000000000000000010000000000000000000000000001, {61{1'b0}}}),
.result(wire_LogTable7_result),
.sel(A_pipe17)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable7.lpm_size = 16,
LogTable7.lpm_width = 61,
LogTable7.lpm_widths = 4,
LogTable7.lpm_type = "lpm_mux";
lpm_mux LogTable8
(
.data({58'b1110100000000000000000000011010010010000000000000000111111, 58'b1101100000000000000000000010110110010000000000000000110011, 58'b1100100000000000000000000010011100010000000000000000101000, 58'b1011100000000000000000000010000100010000000000000000011111, 58'b1010100000000000000000000001101110010000000000000000011000, 58'b1001100000000000000000000001011010010000000000000000010001, 58'b1000100000000000000000000001001000010000000000000000001100, 58'b0111100000000000000000000000111000010000000000000000001000, 58'b0110100000000000000000000000101010010000000000000000000101, 58'b0101100000000000000000000000011110010000000000000000000011, 58'b0100100000000000000000000000010100010000000000000000000001, 58'b0011100000000000000000000000001100010000000000000000000000, 58'b0010100000000000000000000000000110010000000000000000000000, 58'b0001100000000000000000000000000010010000000000000000000000, 58'b0000100000000000000000000000000000010000000000000000000000, {58{1'b0}}}),
.result(wire_LogTable8_result),
.sel(A_pipe18)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable8.lpm_size = 16,
LogTable8.lpm_width = 58,
LogTable8.lpm_widths = 4,
LogTable8.lpm_type = "lpm_mux";
assign
A1_is_all_zero = {(A_pipe11[3] | A1_is_all_zero[2]), (A_pipe11[2] | A1_is_all_zero[1]), (A_pipe11[1] | A1_is_all_zero[0]), A_pipe11[0]},
A1_is_not_zero = {((~ A_pipe11[3]) & A1_is_not_zero[2]), (A_pipe11[2] | A1_is_not_zero[1]), (A_pipe11[1] | A1_is_not_zero[0]), A_pipe11[0]},
A_all_zero2 = {((~ A_pipe12[3]) & A_all_zero2[2]), ((~ A_pipe12[2]) & A_all_zero2[1]), ((~ A_pipe12[1]) & A_all_zero2[0]), (~ A_pipe12[0])},
A_all_zero3 = {((~ A_pipe13[3]) & A_all_zero3[2]), ((~ A_pipe13[2]) & A_all_zero3[1]), ((~ A_pipe13[1]) & A_all_zero3[0]), (~ A_pipe13[0])},
A_all_zero4 = {((~ A_pipe14[3]) & A_all_zero4[2]), ((~ A_pipe14[2]) & A_all_zero4[1]), ((~ A_pipe14[1]) & A_all_zero4[0]), (~ A_pipe14[0])},
A_all_zero5 = {((~ A_pipe15[3]) & A_all_zero5[2]), ((~ A_pipe15[2]) & A_all_zero5[1]), ((~ A_pipe15[1]) & A_all_zero5[0]), (~ A_pipe15[0])},
A_all_zero6 = {((~ A_pipe16[3]) & A_all_zero6[2]), ((~ A_pipe16[2]) & A_all_zero6[1]), ((~ A_pipe16[1]) & A_all_zero6[0]), (~ A_pipe16[0])},
A_all_zero7 = {((~ A_pipe17[3]) & A_all_zero7[2]), ((~ A_pipe17[2]) & A_all_zero7[1]), ((~ A_pipe17[1]) & A_all_zero7[0]), (~ A_pipe17[0])},
A_all_zero8 = {((~ A_pipe18[3]) & A_all_zero8[2]), ((~ A_pipe18[2]) & A_all_zero8[1]), ((~ A_pipe18[1]) & A_all_zero8[0]), (~ A_pipe18[0])},
A_pipe0 = a0_in,
A_pipe11 = A_wire1_reg0,
A_pipe12 = A_wire2_reg0,
A_pipe13 = A_wire3_reg0,
A_pipe14 = A_wire4_reg0,
A_pipe15 = A_wire5_reg0,
A_pipe16 = A_wire6_reg0,
A_pipe17 = A_wire7_reg0,
A_pipe18 = A_wire8_reg0,
A_wire0 = A_pipe0_reg1,
A_wire1 = Z_wire1[53:50],
A_wire2 = Z_wire2[59:56],
A_wire3 = Z_wire3[68:65],
A_wire4 = Z_wire4[69:66],
A_wire5 = Z_wire5[66:63],
A_wire6 = Z_wire6[63:60],
A_wire7 = Z_wire7[60:57],
A_wire8 = Z_wire8[57:54],
almostlog = S_wire9,
B_pad_wire1 = {1'b0, B_pipe1, {9{1'b0}}},
B_pad_wire2 = {1'b0, B_pipe2, {12{1'b0}}},
B_pad_wire3 = {1'b0, B_pipe3, {4{1'b0}}},
B_pad_wire4 = {1'b0, B_pipe4},
B_pad_wire5 = {1'b0, B_pipe5},
B_pad_wire6 = {1'b0, B_pipe6},
B_pad_wire7 = {1'b0, B_pipe7},
B_pad_wire8 = {1'b0, B_pipe8},
B_pipe1 = B_wire1_reg0,
B_pipe2 = B_wire2_reg0,
B_pipe3 = B_wire3_reg0,
B_pipe4 = B_wire4_reg0,
B_pipe5 = B_wire5_reg0,
B_pipe6 = B_wire6_reg0,
B_pipe7 = B_wire7_reg0,
B_pipe8 = B_wire8_reg0,
B_wire1 = Z_wire1[49:0],
B_wire2 = Z_wire2[55:0],
B_wire3 = Z_wire3[64:0],
B_wire4 = Z_wire4[65:0],
B_wire5 = Z_wire5[62:0],
B_wire6 = Z_wire6[59:0],
B_wire7 = Z_wire7[56:0],
B_wire8 = Z_wire8[53:0],
epsZ_pad_wire1 = epsZ_wire1[59:0],
epsZ_pad_wire2 = epsZ_wire2[68:0],
epsZ_pad_wire3 = epsZ_wire3[80:11],
epsZ_pad_wire4 = epsZ_wire4[84:18],
epsZ_pad_wire5 = epsZ_wire5[84:21],
epsZ_pad_wire6 = epsZ_wire6[84:24],
epsZ_pad_wire7 = epsZ_wire7[84:27],
epsZ_pad_wire8 = epsZ_wire8[84:30],
epsZ_wire1 = ({60{A1_is_all_zero[3]}} & (({60{(~ A1_is_not_zero[3])}} & mux0_data0) | ({60{A1_is_not_zero[3]}} & mux0_data1))),
epsZ_wire2 = {1'b0, (~ A_all_zero2[3]), {7{1'b0}}, ({60{(~ A_all_zero2[3])}} & Z_pipe2)},
epsZ_wire3 = {1'b0, (~ A_all_zero3[3]), {10{1'b0}}, ({69{(~ A_all_zero3[3])}} & Z_pipe3)},
epsZ_wire4 = {1'b0, (~ A_all_zero4[3]), {13{1'b0}}, ({70{(~ A_all_zero4[3])}} & Z_pipe4)},
epsZ_wire5 = {1'b0, (~ A_all_zero5[3]), {16{1'b0}}, ({67{(~ A_all_zero5[3])}} & Z_pipe5)},
epsZ_wire6 = {1'b0, (~ A_all_zero6[3]), {19{1'b0}}, ({64{(~ A_all_zero6[3])}} & Z_pipe6)},
epsZ_wire7 = {1'b0, (~ A_all_zero7[3]), {22{1'b0}}, ({61{(~ A_all_zero7[3])}} & Z_pipe7)},
epsZ_wire8 = {1'b0, (~ A_all_zero8[3]), {25{1'b0}}, ({58{(~ A_all_zero8[3])}} & Z_pipe8)},
InvA0 = wire_InvTable0_result,
L_wire0 = wire_LogTable0_result,
L_wire1 = wire_LogTable1_result,
L_wire2 = wire_LogTable2_result,
L_wire3 = wire_LogTable3_result,
L_wire4 = wire_LogTable4_result,
L_wire5 = wire_LogTable5_result,
L_wire6 = wire_LogTable6_result,
L_wire7 = wire_LogTable7_result,
L_wire8 = wire_LogTable8_result,
mux0_data0 = {1'b1, {4{1'b0}}, Z_pipe1, 1'b0},
mux0_data1 = {1'b0, 1'b1, {4{1'b0}}, Z_pipe1},
P_pad_wire1 = {1'b0, P_wire1, 1'b0},
P_pad_wire2 = {{4{1'b0}}, P_wire2, 1'b0},
P_pad_wire3 = {{7{1'b0}}, P_wire3[66:4]},
P_pad_wire4 = {{10{1'b0}}, P_wire4[60:4]},
P_pad_wire5 = {{13{1'b0}}, P_wire5[54:4]},
P_pad_wire6 = {{16{1'b0}}, P_wire6[48:4]},
P_pad_wire7 = {{19{1'b0}}, P_wire7[42:4]},
P_pad_wire8 = {{22{1'b0}}, P_wire8[36:4]},
P_wire0 = wire_mult0_result,
P_wire1 = wire_mult1_result,
P_wire2 = wire_mult2_result,
P_wire3 = wire_mult3_result,
P_wire4 = wire_mult4_result,
P_wire5 = wire_mult5_result,
P_wire6 = wire_mult6_result,
P_wire7 = wire_mult7_result,
P_wire8 = wire_mult8_result,
S_pipe11 = S_wire1_reg0,
S_pipe12 = S_wire2_reg0,
S_pipe13 = S_wire3_reg0,
S_pipe14 = S_wire4_reg0,
S_pipe15 = S_wire5_reg0,
S_pipe16 = S_wire6_reg0,
S_pipe17 = S_wire7_reg0,
S_pipe18 = S_wire8_reg0,
S_pipe22 = wire_add0_1_result,
S_pipe23 = wire_add0_2_result,
S_pipe24 = wire_add0_3_result,
S_pipe25 = wire_add0_4_result,
S_pipe26 = wire_add0_5_result,
S_pipe27 = wire_add0_6_result,
S_pipe28 = wire_add0_7_result,
S_pipe29 = wire_add0_8_result,
S_wire1 = L_wire0,
S_wire2 = S_pipe22_reg0,
S_wire3 = S_pipe23_reg0,
S_wire4 = S_pipe24_reg0,
S_wire5 = S_pipe25_reg0,
S_wire6 = S_pipe26_reg0,
S_wire7 = S_pipe27_reg0,
S_wire8 = S_pipe28_reg0,
S_wire9 = S_pipe29_reg0,
z = Z_wire9,
Z_pipe1 = Z_wire1_reg0,
Z_pipe2 = Z_wire2_reg0,
Z_pipe3 = Z_wire3_reg0,
Z_pipe4 = Z_wire4_reg0,
Z_pipe5 = Z_wire5_reg0,
Z_pipe6 = Z_wire6_reg0,
Z_pipe7 = Z_wire7_reg0,
Z_pipe8 = Z_wire8_reg0,
Z_wire1 = P_wire0[53:0],
Z_wire2 = wire_sub1_1_result,
Z_wire3 = wire_sub1_2_result,
Z_wire4 = wire_sub1_3_result,
Z_wire5 = wire_sub1_4_result,
Z_wire6 = wire_sub1_5_result,
Z_wire7 = wire_sub1_6_result,
Z_wire8 = wire_sub1_7_result,
Z_wire9 = wire_sub1_8_result,
ZM_wire1 = Z_wire1,
ZM_wire2 = Z_wire2,
ZM_wire3 = Z_wire3[68:6],
ZM_wire4 = Z_wire4[69:13],
ZM_wire5 = Z_wire5[66:16],
ZM_wire6 = Z_wire6[63:19],
ZM_wire7 = Z_wire7[60:22],
ZM_wire8 = Z_wire8[57:25];
endmodule //acl_fp_log_s5_double_range_reduction_3sd
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" PIPELINE=1 WIDTH=128 WIDTHAD=7 aclr clk_en clock data q
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" PIPELINE=0 WIDTH=64 WIDTHAD=6 data q
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=32 WIDTHAD=5 data q
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q zero
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q zero
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q zero
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q zero
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altpriority_encoder_3e8
(
data,
q,
zero) ;
input [1:0] data;
output [0:0] q;
output zero;
assign
q = {data[1]},
zero = (~ (data[0] | data[1]));
endmodule //acl_fp_log_s5_double_altpriority_encoder_3e8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altpriority_encoder_6e8
(
data,
q,
zero) ;
input [3:0] data;
output [1:0] q;
output zero;
wire [0:0] wire_altpriority_encoder15_q;
wire wire_altpriority_encoder15_zero;
wire [0:0] wire_altpriority_encoder16_q;
wire wire_altpriority_encoder16_zero;
acl_fp_log_s5_double_altpriority_encoder_3e8 altpriority_encoder15
(
.data(data[1:0]),
.q(wire_altpriority_encoder15_q),
.zero(wire_altpriority_encoder15_zero));
acl_fp_log_s5_double_altpriority_encoder_3e8 altpriority_encoder16
(
.data(data[3:2]),
.q(wire_altpriority_encoder16_q),
.zero(wire_altpriority_encoder16_zero));
assign
q = {(~ wire_altpriority_encoder16_zero), ((wire_altpriority_encoder16_zero & wire_altpriority_encoder15_q) | ((~ wire_altpriority_encoder16_zero) & wire_altpriority_encoder16_q))},
zero = (wire_altpriority_encoder15_zero & wire_altpriority_encoder16_zero);
endmodule //acl_fp_log_s5_double_altpriority_encoder_6e8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altpriority_encoder_be8
(
data,
q,
zero) ;
input [7:0] data;
output [2:0] q;
output zero;
wire [1:0] wire_altpriority_encoder13_q;
wire wire_altpriority_encoder13_zero;
wire [1:0] wire_altpriority_encoder14_q;
wire wire_altpriority_encoder14_zero;
acl_fp_log_s5_double_altpriority_encoder_6e8 altpriority_encoder13
(
.data(data[3:0]),
.q(wire_altpriority_encoder13_q),
.zero(wire_altpriority_encoder13_zero));
acl_fp_log_s5_double_altpriority_encoder_6e8 altpriority_encoder14
(
.data(data[7:4]),
.q(wire_altpriority_encoder14_q),
.zero(wire_altpriority_encoder14_zero));
assign
q = {(~ wire_altpriority_encoder14_zero), (({2{wire_altpriority_encoder14_zero}} & wire_altpriority_encoder13_q) | ({2{(~ wire_altpriority_encoder14_zero)}} & wire_altpriority_encoder14_q))},
zero = (wire_altpriority_encoder13_zero & wire_altpriority_encoder14_zero);
endmodule //acl_fp_log_s5_double_altpriority_encoder_be8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altpriority_encoder_rf8
(
data,
q,
zero) ;
input [15:0] data;
output [3:0] q;
output zero;
wire [2:0] wire_altpriority_encoder11_q;
wire wire_altpriority_encoder11_zero;
wire [2:0] wire_altpriority_encoder12_q;
wire wire_altpriority_encoder12_zero;
acl_fp_log_s5_double_altpriority_encoder_be8 altpriority_encoder11
(
.data(data[7:0]),
.q(wire_altpriority_encoder11_q),
.zero(wire_altpriority_encoder11_zero));
acl_fp_log_s5_double_altpriority_encoder_be8 altpriority_encoder12
(
.data(data[15:8]),
.q(wire_altpriority_encoder12_q),
.zero(wire_altpriority_encoder12_zero));
assign
q = {(~ wire_altpriority_encoder12_zero), (({3{wire_altpriority_encoder12_zero}} & wire_altpriority_encoder11_q) | ({3{(~ wire_altpriority_encoder12_zero)}} & wire_altpriority_encoder12_q))},
zero = (wire_altpriority_encoder11_zero & wire_altpriority_encoder12_zero);
endmodule //acl_fp_log_s5_double_altpriority_encoder_rf8
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altpriority_encoder_3v7
(
data,
q) ;
input [1:0] data;
output [0:0] q;
assign
q = {data[1]};
endmodule //acl_fp_log_s5_double_altpriority_encoder_3v7
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altpriority_encoder_6v7
(
data,
q) ;
input [3:0] data;
output [1:0] q;
wire [0:0] wire_altpriority_encoder21_q;
wire [0:0] wire_altpriority_encoder22_q;
wire wire_altpriority_encoder22_zero;
acl_fp_log_s5_double_altpriority_encoder_3v7 altpriority_encoder21
(
.data(data[1:0]),
.q(wire_altpriority_encoder21_q));
acl_fp_log_s5_double_altpriority_encoder_3e8 altpriority_encoder22
(
.data(data[3:2]),
.q(wire_altpriority_encoder22_q),
.zero(wire_altpriority_encoder22_zero));
assign
q = {(~ wire_altpriority_encoder22_zero), ((wire_altpriority_encoder22_zero & wire_altpriority_encoder21_q) | ((~ wire_altpriority_encoder22_zero) & wire_altpriority_encoder22_q))};
endmodule //acl_fp_log_s5_double_altpriority_encoder_6v7
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altpriority_encoder_bv7
(
data,
q) ;
input [7:0] data;
output [2:0] q;
wire [1:0] wire_altpriority_encoder19_q;
wire [1:0] wire_altpriority_encoder20_q;
wire wire_altpriority_encoder20_zero;
acl_fp_log_s5_double_altpriority_encoder_6v7 altpriority_encoder19
(
.data(data[3:0]),
.q(wire_altpriority_encoder19_q));
acl_fp_log_s5_double_altpriority_encoder_6e8 altpriority_encoder20
(
.data(data[7:4]),
.q(wire_altpriority_encoder20_q),
.zero(wire_altpriority_encoder20_zero));
assign
q = {(~ wire_altpriority_encoder20_zero), (({2{wire_altpriority_encoder20_zero}} & wire_altpriority_encoder19_q) | ({2{(~ wire_altpriority_encoder20_zero)}} & wire_altpriority_encoder20_q))};
endmodule //acl_fp_log_s5_double_altpriority_encoder_bv7
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altpriority_encoder_r08
(
data,
q) ;
input [15:0] data;
output [3:0] q;
wire [2:0] wire_altpriority_encoder17_q;
wire [2:0] wire_altpriority_encoder18_q;
wire wire_altpriority_encoder18_zero;
acl_fp_log_s5_double_altpriority_encoder_bv7 altpriority_encoder17
(
.data(data[7:0]),
.q(wire_altpriority_encoder17_q));
acl_fp_log_s5_double_altpriority_encoder_be8 altpriority_encoder18
(
.data(data[15:8]),
.q(wire_altpriority_encoder18_q),
.zero(wire_altpriority_encoder18_zero));
assign
q = {(~ wire_altpriority_encoder18_zero), (({3{wire_altpriority_encoder18_zero}} & wire_altpriority_encoder17_q) | ({3{(~ wire_altpriority_encoder18_zero)}} & wire_altpriority_encoder18_q))};
endmodule //acl_fp_log_s5_double_altpriority_encoder_r08
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altpriority_encoder_q08
(
data,
q) ;
input [31:0] data;
output [4:0] q;
wire [3:0] wire_altpriority_encoder10_q;
wire wire_altpriority_encoder10_zero;
wire [3:0] wire_altpriority_encoder9_q;
acl_fp_log_s5_double_altpriority_encoder_rf8 altpriority_encoder10
(
.data(data[31:16]),
.q(wire_altpriority_encoder10_q),
.zero(wire_altpriority_encoder10_zero));
acl_fp_log_s5_double_altpriority_encoder_r08 altpriority_encoder9
(
.data(data[15:0]),
.q(wire_altpriority_encoder9_q));
assign
q = {(~ wire_altpriority_encoder10_zero), (({4{wire_altpriority_encoder10_zero}} & wire_altpriority_encoder9_q) | ({4{(~ wire_altpriority_encoder10_zero)}} & wire_altpriority_encoder10_q))};
endmodule //acl_fp_log_s5_double_altpriority_encoder_q08
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=32 WIDTHAD=5 data q zero
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altpriority_encoder_qf8
(
data,
q,
zero) ;
input [31:0] data;
output [4:0] q;
output zero;
wire [3:0] wire_altpriority_encoder23_q;
wire wire_altpriority_encoder23_zero;
wire [3:0] wire_altpriority_encoder24_q;
wire wire_altpriority_encoder24_zero;
acl_fp_log_s5_double_altpriority_encoder_rf8 altpriority_encoder23
(
.data(data[15:0]),
.q(wire_altpriority_encoder23_q),
.zero(wire_altpriority_encoder23_zero));
acl_fp_log_s5_double_altpriority_encoder_rf8 altpriority_encoder24
(
.data(data[31:16]),
.q(wire_altpriority_encoder24_q),
.zero(wire_altpriority_encoder24_zero));
assign
q = {(~ wire_altpriority_encoder24_zero), (({4{wire_altpriority_encoder24_zero}} & wire_altpriority_encoder23_q) | ({4{(~ wire_altpriority_encoder24_zero)}} & wire_altpriority_encoder24_q))},
zero = (wire_altpriority_encoder23_zero & wire_altpriority_encoder24_zero);
endmodule //acl_fp_log_s5_double_altpriority_encoder_qf8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altpriority_encoder_309
(
data,
q) ;
input [63:0] data;
output [5:0] q;
wire [4:0] wire_altpriority_encoder7_q;
wire [4:0] wire_altpriority_encoder8_q;
wire wire_altpriority_encoder8_zero;
acl_fp_log_s5_double_altpriority_encoder_q08 altpriority_encoder7
(
.data(data[31:0]),
.q(wire_altpriority_encoder7_q));
acl_fp_log_s5_double_altpriority_encoder_qf8 altpriority_encoder8
(
.data(data[63:32]),
.q(wire_altpriority_encoder8_q),
.zero(wire_altpriority_encoder8_zero));
assign
q = {(~ wire_altpriority_encoder8_zero), (({5{wire_altpriority_encoder8_zero}} & wire_altpriority_encoder7_q) | ({5{(~ wire_altpriority_encoder8_zero)}} & wire_altpriority_encoder8_q))};
endmodule //acl_fp_log_s5_double_altpriority_encoder_309
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" PIPELINE=0 WIDTH=64 WIDTHAD=6 data q zero
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altpriority_encoder_3f9
(
data,
q,
zero) ;
input [63:0] data;
output [5:0] q;
output zero;
wire [4:0] wire_altpriority_encoder25_q;
wire wire_altpriority_encoder25_zero;
wire [4:0] wire_altpriority_encoder26_q;
wire wire_altpriority_encoder26_zero;
acl_fp_log_s5_double_altpriority_encoder_qf8 altpriority_encoder25
(
.data(data[31:0]),
.q(wire_altpriority_encoder25_q),
.zero(wire_altpriority_encoder25_zero));
acl_fp_log_s5_double_altpriority_encoder_qf8 altpriority_encoder26
(
.data(data[63:32]),
.q(wire_altpriority_encoder26_q),
.zero(wire_altpriority_encoder26_zero));
assign
q = {(~ wire_altpriority_encoder26_zero), (({5{wire_altpriority_encoder26_zero}} & wire_altpriority_encoder25_q) | ({5{(~ wire_altpriority_encoder26_zero)}} & wire_altpriority_encoder26_q))},
zero = (wire_altpriority_encoder25_zero & wire_altpriority_encoder26_zero);
endmodule //acl_fp_log_s5_double_altpriority_encoder_3f9
//synthesis_resources = reg 7
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altpriority_encoder_gla
(
aclr,
clk_en,
clock,
data,
q) ;
input aclr;
input clk_en;
input clock;
input [127:0] data;
output [6:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [5:0] wire_altpriority_encoder5_q;
wire [5:0] wire_altpriority_encoder6_q;
wire wire_altpriority_encoder6_zero;
reg [6:0] pipeline_q_dffe;
wire [6:0] tmp_q_wire;
acl_fp_log_s5_double_altpriority_encoder_309 altpriority_encoder5
(
.data(data[63:0]),
.q(wire_altpriority_encoder5_q));
acl_fp_log_s5_double_altpriority_encoder_3f9 altpriority_encoder6
(
.data(data[127:64]),
.q(wire_altpriority_encoder6_q),
.zero(wire_altpriority_encoder6_zero));
// synopsys translate_off
initial
pipeline_q_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) pipeline_q_dffe <= 7'b0;
else if (clk_en == 1'b1) pipeline_q_dffe <= tmp_q_wire;
assign
q = pipeline_q_dffe,
tmp_q_wire = {(~ wire_altpriority_encoder6_zero), (({6{wire_altpriority_encoder6_zero}} & wire_altpriority_encoder5_q) | ({6{(~ wire_altpriority_encoder6_zero)}} & wire_altpriority_encoder6_q))};
endmodule //acl_fp_log_s5_double_altpriority_encoder_gla
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=64 WIDTHAD=6 data q
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altpriority_encoder_018
(
data,
q) ;
input [63:0] data;
output [5:0] q;
wire [4:0] wire_altpriority_encoder27_q;
wire [4:0] wire_altpriority_encoder28_q;
wire wire_altpriority_encoder28_zero;
acl_fp_log_s5_double_altpriority_encoder_q08 altpriority_encoder27
(
.data(data[31:0]),
.q(wire_altpriority_encoder27_q));
acl_fp_log_s5_double_altpriority_encoder_qf8 altpriority_encoder28
(
.data(data[63:32]),
.q(wire_altpriority_encoder28_q),
.zero(wire_altpriority_encoder28_zero));
assign
q = {(~ wire_altpriority_encoder28_zero), (({5{wire_altpriority_encoder28_zero}} & wire_altpriority_encoder27_q) | ({5{(~ wire_altpriority_encoder28_zero)}} & wire_altpriority_encoder28_q))};
endmodule //acl_fp_log_s5_double_altpriority_encoder_018
//synthesis_resources = altsquare 1 lpm_add_sub 89 lpm_mult 10 lpm_mux 10 mux21 63 reg 4847
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_o3b
(
clk_en,
clock,
data,
result) ;
input clk_en;
input clock;
input [63:0] data;
output [63:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [63:0] wire_Lshiftsmall_result;
wire [127:0] wire_lzc_norm_L_result;
wire [63:0] wire_Rshiftsmall_result;
wire wire_exp_nan_result;
wire wire_exp_zero_result;
wire wire_man_inf_result;
wire wire_man_nan_result;
wire [82:0] wire_add1_result;
wire [62:0] wire_add2_result;
wire [10:0] wire_exp_biase_sub_result;
wire [25:0] wire_sub1_result;
wire [10:0] wire_sub2_result;
wire [6:0] wire_sub3_result;
wire [54:0] wire_sub4_result;
wire [10:0] wire_sub5_result;
wire [10:0] wire_sub6_result;
wire [82:0] wire_range_reduction_almostlog;
wire [54:0] wire_range_reduction_z;
wire [6:0] wire_lzc_norm_E_q;
wire [5:0] wire_lzoc_q;
wire [27:0] wire_squarer_result;
reg [67:0] absELog2_pipe_reg0;
reg [67:0] absELog2_pipe_reg1;
reg [67:0] absELog2_pipe_reg2;
reg [25:0] absZ0_pipe_reg0;
reg [25:0] absZ0_pipe_reg1;
reg [25:0] absZ0_pipe_reg10;
reg [25:0] absZ0_pipe_reg11;
reg [25:0] absZ0_pipe_reg12;
reg [25:0] absZ0_pipe_reg13;
reg [25:0] absZ0_pipe_reg14;
reg [25:0] absZ0_pipe_reg15;
reg [25:0] absZ0_pipe_reg16;
reg [25:0] absZ0_pipe_reg17;
reg [25:0] absZ0_pipe_reg18;
reg [25:0] absZ0_pipe_reg19;
reg [25:0] absZ0_pipe_reg2;
reg [25:0] absZ0_pipe_reg20;
reg [25:0] absZ0_pipe_reg21;
reg [25:0] absZ0_pipe_reg22;
reg [25:0] absZ0_pipe_reg23;
reg [25:0] absZ0_pipe_reg3;
reg [25:0] absZ0_pipe_reg4;
reg [25:0] absZ0_pipe_reg5;
reg [25:0] absZ0_pipe_reg6;
reg [25:0] absZ0_pipe_reg7;
reg [25:0] absZ0_pipe_reg8;
reg [25:0] absZ0_pipe_reg9;
reg [25:0] absZ0s_pipe1_reg0;
reg [25:0] absZ0s_pipe1_reg1;
reg [25:0] absZ0s_pipe1_reg2;
reg [25:0] absZ0s_pipe1_reg3;
reg [25:0] absZ0s_reg0;
reg [82:0] almostLog_pipe_reg0;
reg [82:0] almostLog_pipe_reg1;
reg [82:0] almostLog_pipe_reg2;
reg [0:0] doRR_reg0;
reg [0:0] doRR_reg1;
reg [10:0] E0_pipe_reg0;
reg [10:0] E0_pipe_reg1;
reg [10:0] E0_pipe_reg10;
reg [10:0] E0_pipe_reg11;
reg [10:0] E0_pipe_reg12;
reg [10:0] E0_pipe_reg13;
reg [10:0] E0_pipe_reg14;
reg [10:0] E0_pipe_reg15;
reg [10:0] E0_pipe_reg16;
reg [10:0] E0_pipe_reg17;
reg [10:0] E0_pipe_reg18;
reg [10:0] E0_pipe_reg19;
reg [10:0] E0_pipe_reg2;
reg [10:0] E0_pipe_reg20;
reg [10:0] E0_pipe_reg21;
reg [10:0] E0_pipe_reg22;
reg [10:0] E0_pipe_reg23;
reg [10:0] E0_pipe_reg3;
reg [10:0] E0_pipe_reg4;
reg [10:0] E0_pipe_reg5;
reg [10:0] E0_pipe_reg6;
reg [10:0] E0_pipe_reg7;
reg [10:0] E0_pipe_reg8;
reg [10:0] E0_pipe_reg9;
reg [5:0] E_normal_pipe_reg0;
reg [0:0] exp_is_ebiase_pipe_reg0;
reg [0:0] exp_is_ebiase_pipe_reg1;
reg [0:0] exp_is_ebiase_pipe_reg2;
reg [0:0] input_is_infinity_pipe_reg0;
reg [0:0] input_is_infinity_pipe_reg1;
reg [0:0] input_is_infinity_pipe_reg10;
reg [0:0] input_is_infinity_pipe_reg11;
reg [0:0] input_is_infinity_pipe_reg12;
reg [0:0] input_is_infinity_pipe_reg13;
reg [0:0] input_is_infinity_pipe_reg14;
reg [0:0] input_is_infinity_pipe_reg15;
reg [0:0] input_is_infinity_pipe_reg16;
reg [0:0] input_is_infinity_pipe_reg17;
reg [0:0] input_is_infinity_pipe_reg18;
reg [0:0] input_is_infinity_pipe_reg19;
reg [0:0] input_is_infinity_pipe_reg2;
reg [0:0] input_is_infinity_pipe_reg20;
reg [0:0] input_is_infinity_pipe_reg21;
reg [0:0] input_is_infinity_pipe_reg22;
reg [0:0] input_is_infinity_pipe_reg23;
reg [0:0] input_is_infinity_pipe_reg24;
reg [0:0] input_is_infinity_pipe_reg25;
reg [0:0] input_is_infinity_pipe_reg26;
reg [0:0] input_is_infinity_pipe_reg27;
reg [0:0] input_is_infinity_pipe_reg28;
reg [0:0] input_is_infinity_pipe_reg29;
reg [0:0] input_is_infinity_pipe_reg3;
reg [0:0] input_is_infinity_pipe_reg30;
reg [0:0] input_is_infinity_pipe_reg4;
reg [0:0] input_is_infinity_pipe_reg5;
reg [0:0] input_is_infinity_pipe_reg6;
reg [0:0] input_is_infinity_pipe_reg7;
reg [0:0] input_is_infinity_pipe_reg8;
reg [0:0] input_is_infinity_pipe_reg9;
reg [0:0] input_is_nan_pipe_reg0;
reg [0:0] input_is_nan_pipe_reg1;
reg [0:0] input_is_nan_pipe_reg10;
reg [0:0] input_is_nan_pipe_reg11;
reg [0:0] input_is_nan_pipe_reg12;
reg [0:0] input_is_nan_pipe_reg13;
reg [0:0] input_is_nan_pipe_reg14;
reg [0:0] input_is_nan_pipe_reg15;
reg [0:0] input_is_nan_pipe_reg16;
reg [0:0] input_is_nan_pipe_reg17;
reg [0:0] input_is_nan_pipe_reg18;
reg [0:0] input_is_nan_pipe_reg19;
reg [0:0] input_is_nan_pipe_reg2;
reg [0:0] input_is_nan_pipe_reg20;
reg [0:0] input_is_nan_pipe_reg21;
reg [0:0] input_is_nan_pipe_reg22;
reg [0:0] input_is_nan_pipe_reg23;
reg [0:0] input_is_nan_pipe_reg24;
reg [0:0] input_is_nan_pipe_reg25;
reg [0:0] input_is_nan_pipe_reg26;
reg [0:0] input_is_nan_pipe_reg27;
reg [0:0] input_is_nan_pipe_reg28;
reg [0:0] input_is_nan_pipe_reg29;
reg [0:0] input_is_nan_pipe_reg3;
reg [0:0] input_is_nan_pipe_reg30;
reg [0:0] input_is_nan_pipe_reg4;
reg [0:0] input_is_nan_pipe_reg5;
reg [0:0] input_is_nan_pipe_reg6;
reg [0:0] input_is_nan_pipe_reg7;
reg [0:0] input_is_nan_pipe_reg8;
reg [0:0] input_is_nan_pipe_reg9;
reg [0:0] input_is_one_pipe_reg0;
reg [0:0] input_is_one_pipe_reg1;
reg [0:0] input_is_one_pipe_reg10;
reg [0:0] input_is_one_pipe_reg11;
reg [0:0] input_is_one_pipe_reg12;
reg [0:0] input_is_one_pipe_reg13;
reg [0:0] input_is_one_pipe_reg14;
reg [0:0] input_is_one_pipe_reg15;
reg [0:0] input_is_one_pipe_reg16;
reg [0:0] input_is_one_pipe_reg17;
reg [0:0] input_is_one_pipe_reg18;
reg [0:0] input_is_one_pipe_reg19;
reg [0:0] input_is_one_pipe_reg2;
reg [0:0] input_is_one_pipe_reg20;
reg [0:0] input_is_one_pipe_reg21;
reg [0:0] input_is_one_pipe_reg22;
reg [0:0] input_is_one_pipe_reg23;
reg [0:0] input_is_one_pipe_reg24;
reg [0:0] input_is_one_pipe_reg25;
reg [0:0] input_is_one_pipe_reg26;
reg [0:0] input_is_one_pipe_reg27;
reg [0:0] input_is_one_pipe_reg28;
reg [0:0] input_is_one_pipe_reg29;
reg [0:0] input_is_one_pipe_reg3;
reg [0:0] input_is_one_pipe_reg30;
reg [0:0] input_is_one_pipe_reg4;
reg [0:0] input_is_one_pipe_reg5;
reg [0:0] input_is_one_pipe_reg6;
reg [0:0] input_is_one_pipe_reg7;
reg [0:0] input_is_one_pipe_reg8;
reg [0:0] input_is_one_pipe_reg9;
reg [0:0] input_is_zero_pipe_reg0;
reg [0:0] input_is_zero_pipe_reg1;
reg [0:0] input_is_zero_pipe_reg10;
reg [0:0] input_is_zero_pipe_reg11;
reg [0:0] input_is_zero_pipe_reg12;
reg [0:0] input_is_zero_pipe_reg13;
reg [0:0] input_is_zero_pipe_reg14;
reg [0:0] input_is_zero_pipe_reg15;
reg [0:0] input_is_zero_pipe_reg16;
reg [0:0] input_is_zero_pipe_reg17;
reg [0:0] input_is_zero_pipe_reg18;
reg [0:0] input_is_zero_pipe_reg19;
reg [0:0] input_is_zero_pipe_reg2;
reg [0:0] input_is_zero_pipe_reg20;
reg [0:0] input_is_zero_pipe_reg21;
reg [0:0] input_is_zero_pipe_reg22;
reg [0:0] input_is_zero_pipe_reg23;
reg [0:0] input_is_zero_pipe_reg24;
reg [0:0] input_is_zero_pipe_reg25;
reg [0:0] input_is_zero_pipe_reg26;
reg [0:0] input_is_zero_pipe_reg27;
reg [0:0] input_is_zero_pipe_reg28;
reg [0:0] input_is_zero_pipe_reg29;
reg [0:0] input_is_zero_pipe_reg3;
reg [0:0] input_is_zero_pipe_reg30;
reg [0:0] input_is_zero_pipe_reg4;
reg [0:0] input_is_zero_pipe_reg5;
reg [0:0] input_is_zero_pipe_reg6;
reg [0:0] input_is_zero_pipe_reg7;
reg [0:0] input_is_zero_pipe_reg8;
reg [0:0] input_is_zero_pipe_reg9;
reg [93:0] Log_normal_normd_pipe_reg0;
reg [93:0] Log_normal_reg0;
reg [56:0] Log_small_normd_pipe_reg0;
reg [56:0] Log_small_normd_pipe_reg1;
reg [6:0] Lshiftval_reg0;
reg [6:0] Lshiftval_reg1;
reg [6:0] Lshiftval_reg2;
reg [6:0] Lshiftval_reg3;
reg [5:0] lzo_pipe1_reg0;
reg [5:0] lzo_pipe1_reg1;
reg [5:0] lzo_pipe1_reg10;
reg [5:0] lzo_pipe1_reg11;
reg [5:0] lzo_pipe1_reg12;
reg [5:0] lzo_pipe1_reg13;
reg [5:0] lzo_pipe1_reg14;
reg [5:0] lzo_pipe1_reg15;
reg [5:0] lzo_pipe1_reg16;
reg [5:0] lzo_pipe1_reg17;
reg [5:0] lzo_pipe1_reg18;
reg [5:0] lzo_pipe1_reg19;
reg [5:0] lzo_pipe1_reg2;
reg [5:0] lzo_pipe1_reg20;
reg [5:0] lzo_pipe1_reg21;
reg [5:0] lzo_pipe1_reg22;
reg [5:0] lzo_pipe1_reg23;
reg [5:0] lzo_pipe1_reg3;
reg [5:0] lzo_pipe1_reg4;
reg [5:0] lzo_pipe1_reg5;
reg [5:0] lzo_pipe1_reg6;
reg [5:0] lzo_pipe1_reg7;
reg [5:0] lzo_pipe1_reg8;
reg [5:0] lzo_pipe1_reg9;
reg [5:0] lzo_reg0;
reg [5:0] lzo_reg1;
reg [5:0] lzo_reg2;
reg [5:0] lzo_reg3;
reg [5:0] lzo_reg4;
reg [5:0] lzo_reg5;
reg [5:0] lzo_reg6;
reg [0:0] sign_data_reg0;
reg [0:0] sign_data_reg1;
reg [0:0] sign_data_reg2;
reg [0:0] small_flag_pipe_reg0;
reg [0:0] small_flag_pipe_reg1;
reg [0:0] small_flag_pipe_reg2;
reg [0:0] small_flag_pipe_reg3;
reg [0:0] small_flag_pipe_reg4;
reg [0:0] small_flag_pipe_reg5;
reg [0:0] small_flag_pipe_reg6;
reg [0:0] small_flag_pipe_reg7;
reg [0:0] small_flag_pipe_reg8;
reg [0:0] sR_pipe1_reg0;
reg [0:0] sR_pipe1_reg1;
reg [0:0] sR_pipe1_reg10;
reg [0:0] sR_pipe1_reg11;
reg [0:0] sR_pipe1_reg12;
reg [0:0] sR_pipe1_reg13;
reg [0:0] sR_pipe1_reg14;
reg [0:0] sR_pipe1_reg15;
reg [0:0] sR_pipe1_reg16;
reg [0:0] sR_pipe1_reg17;
reg [0:0] sR_pipe1_reg18;
reg [0:0] sR_pipe1_reg19;
reg [0:0] sR_pipe1_reg2;
reg [0:0] sR_pipe1_reg20;
reg [0:0] sR_pipe1_reg21;
reg [0:0] sR_pipe1_reg22;
reg [0:0] sR_pipe1_reg23;
reg [0:0] sR_pipe1_reg3;
reg [0:0] sR_pipe1_reg4;
reg [0:0] sR_pipe1_reg5;
reg [0:0] sR_pipe1_reg6;
reg [0:0] sR_pipe1_reg7;
reg [0:0] sR_pipe1_reg8;
reg [0:0] sR_pipe1_reg9;
reg [0:0] sR_pipe2_reg0;
reg [0:0] sR_pipe2_reg1;
reg [0:0] sR_pipe2_reg2;
reg [0:0] sR_pipe2_reg3;
reg [0:0] sR_pipe2_reg4;
reg [0:0] sR_pipe2_reg5;
reg [0:0] sR_pipe3_reg0;
reg [0:0] sR_pipe3_reg1;
reg [0:0] sR_pipe3_reg2;
reg [0:0] sR_pipe3_reg3;
reg [27:0] Z2o2_pipe_reg0;
reg [27:0] Z2o2_small_s_pipe_reg0;
reg [54:0] Zfinal_reg0;
reg [54:0] Zfinal_reg1;
wire [58:0] wire_addsub1_result;
wire [93:0] wire_addsub2_result;
wire [67:0] wire_mult1_result;
wire [62:0]wire_mux_result0a_dataout;
wire [10:0] absE;
wire [67:0] absELog2;
wire [93:0] absELog2_pad;
wire [67:0] absELog2_pipe;
wire [25:0] absZ0;
wire [25:0] absZ0_pipe;
wire [25:0] absZ0s;
wire [25:0] absZ0s_pipe1;
wire [25:0] absZ0s_pipe2;
wire aclr;
wire [82:0] almostLog;
wire [82:0] almostLog_pipe;
wire [10:0] data_exp_is_ebiase;
wire doRR;
wire doRR_pipe;
wire [10:0] E0;
wire [10:0] E0_is_zero;
wire [10:0] E0_pipe;
wire [1:0] E0_sub;
wire [10:0] E0offset;
wire [5:0] E_normal;
wire [5:0] E_normal_pipe;
wire [10:0] E_small;
wire [62:0] EFR;
wire [10:0] ER;
wire exp_all_one;
wire exp_all_zero;
wire [10:0] exp_biase;
wire [10:0] exp_data;
wire exp_is_ebiase;
wire exp_is_ebiase_pipe;
wire First_bit;
wire input_is_infinity;
wire input_is_infinity_pipe;
wire input_is_nan;
wire input_is_nan_pipe;
wire input_is_one;
wire input_is_one_pipe;
wire input_is_zero;
wire input_is_zero_pipe;
wire [54:0] Log1p_normal;
wire [56:0] Log2;
wire [56:0] Log_g;
wire [93:0] Log_normal;
wire [93:0] Log_normal_normd;
wire [93:0] Log_normal_normd_pipe;
wire [93:0] Log_normal_pipe;
wire [58:0] Log_small;
wire [56:0] Log_small1;
wire [56:0] Log_small2;
wire [56:0] Log_small_normd;
wire [56:0] Log_small_normd_pipe;
wire [82:0] LogF_normal;
wire [93:0] LogF_normal_pad;
wire [6:0] Lshiftval;
wire [5:0] lzo;
wire [5:0] lzo_pipe1;
wire [5:0] lzo_pipe2;
wire [53:0] man_above_half;
wire man_all_zero;
wire [53:0] man_below_half;
wire [51:0] man_data;
wire man_not_zero;
wire [5:0] pfinal_s;
wire round;
wire [6:0] Rshiftval;
wire sign_data;
wire sign_data_pipe;
wire small_flag;
wire small_flag_pipe;
wire [26:0] squarerIn;
wire [26:0] squarerIn0;
wire [26:0] squarerIn1;
wire sR;
wire sR_pipe1;
wire sR_pipe2;
wire sR_pipe3;
wire [3:0] sticky;
wire [53:0] Y0;
wire [27:0] Z2o2;
wire [27:0] Z2o2_pipe;
wire [58:0] Z2o2_small;
wire [27:0] Z2o2_small_s;
wire [27:0] Z2o2_small_s_pipe;
wire [58:0] Z_small;
wire [54:0] Zfinal;
wire [54:0] Zfinal_pipe;
acl_fp_log_s5_double_altbarrel_shift_qud Lshiftsmall
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.data({absZ0, {38{1'b0}}}),
.distance(Lshiftval[5:0]),
.result(wire_Lshiftsmall_result));
acl_fp_log_s5_double_altbarrel_shift_edb lzc_norm_L
(
.data({Log_normal_pipe, {34{1'b0}}}),
.distance((~ wire_lzc_norm_E_q)),
.result(wire_lzc_norm_L_result));
acl_fp_log_s5_double_altbarrel_shift_d2e Rshiftsmall
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.data({Z2o2, {36{1'b0}}}),
.distance(Rshiftval[5:0]),
.result(wire_Rshiftsmall_result));
acl_fp_log_s5_double_altfp_log_and_or_rab exp_nan
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.data(exp_data),
.result(wire_exp_nan_result));
acl_fp_log_s5_double_altfp_log_and_or_98b exp_zero
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.data(exp_data),
.result(wire_exp_zero_result));
acl_fp_log_s5_double_altfp_log_and_or_e8b man_inf
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.data(man_data),
.result(wire_man_inf_result));
acl_fp_log_s5_double_altfp_log_and_or_e8b man_nan
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.data(man_data),
.result(wire_man_nan_result));
acl_fp_log_s5_double_altfp_log_csa_r0e add1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa({{28{1'b0}}, Log1p_normal}),
.datab(almostLog),
.result(wire_add1_result));
acl_fp_log_s5_double_altfp_log_csa_p0e add2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa({ER, Log_g[56:5]}),
.datab({{62{1'b0}}, round}),
.result(wire_add2_result));
acl_fp_log_s5_double_altfp_log_csa_aoc exp_biase_sub
(
.dataa(exp_data),
.datab(exp_biase),
.result(wire_exp_biase_sub_result));
acl_fp_log_s5_double_altfp_log_csa_i4b sub1
(
.dataa({26{1'b0}}),
.datab(Y0[25:0]),
.result(wire_sub1_result));
acl_fp_log_s5_double_altfp_log_csa_aoc sub2
(
.dataa({11{1'b0}}),
.datab(E0),
.result(wire_sub2_result));
acl_fp_log_s5_double_altfp_log_csa_vmc sub3
(
.dataa({1'b0, lzo}),
.datab({1'b0, pfinal_s}),
.result(wire_sub3_result));
acl_fp_log_s5_double_altfp_log_csa_plf sub4
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(Zfinal_pipe),
.datab({{29{1'b0}}, Z2o2[27:2]}),
.result(wire_sub4_result));
acl_fp_log_s5_double_altfp_log_csa_ilf sub5
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa({1'b0, {8{1'b1}}, E0_sub}),
.datab({{5{1'b0}}, lzo_pipe2}),
.result(wire_sub5_result));
acl_fp_log_s5_double_altfp_log_csa_aoc sub6
(
.dataa(E0offset),
.datab({{5{1'b0}}, (~ E_normal)}),
.result(wire_sub6_result));
acl_fp_log_s5_double_range_reduction_3sd range_reduction
(
.a0_in(man_data[51:47]),
.aclr(aclr),
.almostlog(wire_range_reduction_almostlog),
.clk_en(clk_en),
.clock(clock),
.y0_in(Y0),
.z(wire_range_reduction_z));
acl_fp_log_s5_double_altpriority_encoder_gla lzc_norm_E
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.data({Log_normal, 34'b0000000000000000000000000000000001}),
.q(wire_lzc_norm_E_q));
acl_fp_log_s5_double_altpriority_encoder_018 lzoc
(
.data({({52{First_bit}} ^ Y0[52:1]), 12'b000000000001}),
.q(wire_lzoc_q));
altsquare squarer
(
.aclr(aclr),
.clock(clock),
.data(squarerIn),
.ena(clk_en),
.result(wire_squarer_result));
defparam
squarer.data_width = 27,
squarer.pipeline = 1,
squarer.representation = "UNSIGNED",
squarer.result_alignment = "MSB",
squarer.result_width = 28,
squarer.lpm_type = "altsquare";
// synopsys translate_off
initial
absELog2_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absELog2_pipe_reg0 <= 68'b0;
else if (clk_en == 1'b1) absELog2_pipe_reg0 <= absELog2_pipe;
// synopsys translate_off
initial
absELog2_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absELog2_pipe_reg1 <= 68'b0;
else if (clk_en == 1'b1) absELog2_pipe_reg1 <= absELog2_pipe_reg0;
// synopsys translate_off
initial
absELog2_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absELog2_pipe_reg2 <= 68'b0;
else if (clk_en == 1'b1) absELog2_pipe_reg2 <= absELog2_pipe_reg1;
// synopsys translate_off
initial
absZ0_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg0 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg0 <= absZ0_pipe;
// synopsys translate_off
initial
absZ0_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg1 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg1 <= absZ0_pipe_reg0;
// synopsys translate_off
initial
absZ0_pipe_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg10 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg10 <= absZ0_pipe_reg9;
// synopsys translate_off
initial
absZ0_pipe_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg11 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg11 <= absZ0_pipe_reg10;
// synopsys translate_off
initial
absZ0_pipe_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg12 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg12 <= absZ0_pipe_reg11;
// synopsys translate_off
initial
absZ0_pipe_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg13 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg13 <= absZ0_pipe_reg12;
// synopsys translate_off
initial
absZ0_pipe_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg14 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg14 <= absZ0_pipe_reg13;
// synopsys translate_off
initial
absZ0_pipe_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg15 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg15 <= absZ0_pipe_reg14;
// synopsys translate_off
initial
absZ0_pipe_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg16 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg16 <= absZ0_pipe_reg15;
// synopsys translate_off
initial
absZ0_pipe_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg17 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg17 <= absZ0_pipe_reg16;
// synopsys translate_off
initial
absZ0_pipe_reg18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg18 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg18 <= absZ0_pipe_reg17;
// synopsys translate_off
initial
absZ0_pipe_reg19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg19 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg19 <= absZ0_pipe_reg18;
// synopsys translate_off
initial
absZ0_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg2 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg2 <= absZ0_pipe_reg1;
// synopsys translate_off
initial
absZ0_pipe_reg20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg20 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg20 <= absZ0_pipe_reg19;
// synopsys translate_off
initial
absZ0_pipe_reg21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg21 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg21 <= absZ0_pipe_reg20;
// synopsys translate_off
initial
absZ0_pipe_reg22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg22 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg22 <= absZ0_pipe_reg21;
// synopsys translate_off
initial
absZ0_pipe_reg23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg23 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg23 <= absZ0_pipe_reg22;
// synopsys translate_off
initial
absZ0_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg3 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg3 <= absZ0_pipe_reg2;
// synopsys translate_off
initial
absZ0_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg4 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg4 <= absZ0_pipe_reg3;
// synopsys translate_off
initial
absZ0_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg5 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg5 <= absZ0_pipe_reg4;
// synopsys translate_off
initial
absZ0_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg6 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg6 <= absZ0_pipe_reg5;
// synopsys translate_off
initial
absZ0_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg7 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg7 <= absZ0_pipe_reg6;
// synopsys translate_off
initial
absZ0_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg8 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg8 <= absZ0_pipe_reg7;
// synopsys translate_off
initial
absZ0_pipe_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg9 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg9 <= absZ0_pipe_reg8;
// synopsys translate_off
initial
absZ0s_pipe1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0s_pipe1_reg0 <= 26'b0;
else if (clk_en == 1'b1) absZ0s_pipe1_reg0 <= absZ0s_pipe1;
// synopsys translate_off
initial
absZ0s_pipe1_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0s_pipe1_reg1 <= 26'b0;
else if (clk_en == 1'b1) absZ0s_pipe1_reg1 <= absZ0s_pipe1_reg0;
// synopsys translate_off
initial
absZ0s_pipe1_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0s_pipe1_reg2 <= 26'b0;
else if (clk_en == 1'b1) absZ0s_pipe1_reg2 <= absZ0s_pipe1_reg1;
// synopsys translate_off
initial
absZ0s_pipe1_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0s_pipe1_reg3 <= 26'b0;
else if (clk_en == 1'b1) absZ0s_pipe1_reg3 <= absZ0s_pipe1_reg2;
// synopsys translate_off
initial
absZ0s_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0s_reg0 <= 26'b0;
else if (clk_en == 1'b1) absZ0s_reg0 <= absZ0s;
// synopsys translate_off
initial
almostLog_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) almostLog_pipe_reg0 <= 83'b0;
else if (clk_en == 1'b1) almostLog_pipe_reg0 <= almostLog_pipe;
// synopsys translate_off
initial
almostLog_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) almostLog_pipe_reg1 <= 83'b0;
else if (clk_en == 1'b1) almostLog_pipe_reg1 <= almostLog_pipe_reg0;
// synopsys translate_off
initial
almostLog_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) almostLog_pipe_reg2 <= 83'b0;
else if (clk_en == 1'b1) almostLog_pipe_reg2 <= almostLog_pipe_reg1;
// synopsys translate_off
initial
doRR_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) doRR_reg0 <= 1'b0;
else if (clk_en == 1'b1) doRR_reg0 <= doRR;
// synopsys translate_off
initial
doRR_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) doRR_reg1 <= 1'b0;
else if (clk_en == 1'b1) doRR_reg1 <= doRR_reg0;
// synopsys translate_off
initial
E0_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg0 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg0 <= E0_pipe;
// synopsys translate_off
initial
E0_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg1 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg1 <= E0_pipe_reg0;
// synopsys translate_off
initial
E0_pipe_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg10 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg10 <= E0_pipe_reg9;
// synopsys translate_off
initial
E0_pipe_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg11 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg11 <= E0_pipe_reg10;
// synopsys translate_off
initial
E0_pipe_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg12 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg12 <= E0_pipe_reg11;
// synopsys translate_off
initial
E0_pipe_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg13 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg13 <= E0_pipe_reg12;
// synopsys translate_off
initial
E0_pipe_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg14 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg14 <= E0_pipe_reg13;
// synopsys translate_off
initial
E0_pipe_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg15 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg15 <= E0_pipe_reg14;
// synopsys translate_off
initial
E0_pipe_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg16 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg16 <= E0_pipe_reg15;
// synopsys translate_off
initial
E0_pipe_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg17 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg17 <= E0_pipe_reg16;
// synopsys translate_off
initial
E0_pipe_reg18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg18 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg18 <= E0_pipe_reg17;
// synopsys translate_off
initial
E0_pipe_reg19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg19 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg19 <= E0_pipe_reg18;
// synopsys translate_off
initial
E0_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg2 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg2 <= E0_pipe_reg1;
// synopsys translate_off
initial
E0_pipe_reg20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg20 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg20 <= E0_pipe_reg19;
// synopsys translate_off
initial
E0_pipe_reg21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg21 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg21 <= E0_pipe_reg20;
// synopsys translate_off
initial
E0_pipe_reg22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg22 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg22 <= E0_pipe_reg21;
// synopsys translate_off
initial
E0_pipe_reg23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg23 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg23 <= E0_pipe_reg22;
// synopsys translate_off
initial
E0_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg3 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg3 <= E0_pipe_reg2;
// synopsys translate_off
initial
E0_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg4 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg4 <= E0_pipe_reg3;
// synopsys translate_off
initial
E0_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg5 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg5 <= E0_pipe_reg4;
// synopsys translate_off
initial
E0_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg6 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg6 <= E0_pipe_reg5;
// synopsys translate_off
initial
E0_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg7 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg7 <= E0_pipe_reg6;
// synopsys translate_off
initial
E0_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg8 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg8 <= E0_pipe_reg7;
// synopsys translate_off
initial
E0_pipe_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg9 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg9 <= E0_pipe_reg8;
// synopsys translate_off
initial
E_normal_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E_normal_pipe_reg0 <= 6'b0;
else if (clk_en == 1'b1) E_normal_pipe_reg0 <= E_normal_pipe;
// synopsys translate_off
initial
exp_is_ebiase_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_is_ebiase_pipe_reg0 <= 1'b0;
else if (clk_en == 1'b1) exp_is_ebiase_pipe_reg0 <= exp_is_ebiase_pipe;
// synopsys translate_off
initial
exp_is_ebiase_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_is_ebiase_pipe_reg1 <= 1'b0;
else if (clk_en == 1'b1) exp_is_ebiase_pipe_reg1 <= exp_is_ebiase_pipe_reg0;
// synopsys translate_off
initial
exp_is_ebiase_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_is_ebiase_pipe_reg2 <= 1'b0;
else if (clk_en == 1'b1) exp_is_ebiase_pipe_reg2 <= exp_is_ebiase_pipe_reg1;
// synopsys translate_off
initial
input_is_infinity_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg0 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg0 <= input_is_infinity_pipe;
// synopsys translate_off
initial
input_is_infinity_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg1 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg1 <= input_is_infinity_pipe_reg0;
// synopsys translate_off
initial
input_is_infinity_pipe_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg10 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg10 <= input_is_infinity_pipe_reg9;
// synopsys translate_off
initial
input_is_infinity_pipe_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg11 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg11 <= input_is_infinity_pipe_reg10;
// synopsys translate_off
initial
input_is_infinity_pipe_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg12 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg12 <= input_is_infinity_pipe_reg11;
// synopsys translate_off
initial
input_is_infinity_pipe_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg13 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg13 <= input_is_infinity_pipe_reg12;
// synopsys translate_off
initial
input_is_infinity_pipe_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg14 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg14 <= input_is_infinity_pipe_reg13;
// synopsys translate_off
initial
input_is_infinity_pipe_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg15 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg15 <= input_is_infinity_pipe_reg14;
// synopsys translate_off
initial
input_is_infinity_pipe_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg16 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg16 <= input_is_infinity_pipe_reg15;
// synopsys translate_off
initial
input_is_infinity_pipe_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg17 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg17 <= input_is_infinity_pipe_reg16;
// synopsys translate_off
initial
input_is_infinity_pipe_reg18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg18 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg18 <= input_is_infinity_pipe_reg17;
// synopsys translate_off
initial
input_is_infinity_pipe_reg19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg19 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg19 <= input_is_infinity_pipe_reg18;
// synopsys translate_off
initial
input_is_infinity_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg2 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg2 <= input_is_infinity_pipe_reg1;
// synopsys translate_off
initial
input_is_infinity_pipe_reg20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg20 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg20 <= input_is_infinity_pipe_reg19;
// synopsys translate_off
initial
input_is_infinity_pipe_reg21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg21 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg21 <= input_is_infinity_pipe_reg20;
// synopsys translate_off
initial
input_is_infinity_pipe_reg22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg22 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg22 <= input_is_infinity_pipe_reg21;
// synopsys translate_off
initial
input_is_infinity_pipe_reg23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg23 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg23 <= input_is_infinity_pipe_reg22;
// synopsys translate_off
initial
input_is_infinity_pipe_reg24 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg24 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg24 <= input_is_infinity_pipe_reg23;
// synopsys translate_off
initial
input_is_infinity_pipe_reg25 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg25 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg25 <= input_is_infinity_pipe_reg24;
// synopsys translate_off
initial
input_is_infinity_pipe_reg26 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg26 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg26 <= input_is_infinity_pipe_reg25;
// synopsys translate_off
initial
input_is_infinity_pipe_reg27 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg27 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg27 <= input_is_infinity_pipe_reg26;
// synopsys translate_off
initial
input_is_infinity_pipe_reg28 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg28 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg28 <= input_is_infinity_pipe_reg27;
// synopsys translate_off
initial
input_is_infinity_pipe_reg29 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg29 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg29 <= input_is_infinity_pipe_reg28;
// synopsys translate_off
initial
input_is_infinity_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg3 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg3 <= input_is_infinity_pipe_reg2;
// synopsys translate_off
initial
input_is_infinity_pipe_reg30 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg30 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg30 <= input_is_infinity_pipe_reg29;
// synopsys translate_off
initial
input_is_infinity_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg4 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg4 <= input_is_infinity_pipe_reg3;
// synopsys translate_off
initial
input_is_infinity_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg5 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg5 <= input_is_infinity_pipe_reg4;
// synopsys translate_off
initial
input_is_infinity_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg6 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg6 <= input_is_infinity_pipe_reg5;
// synopsys translate_off
initial
input_is_infinity_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg7 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg7 <= input_is_infinity_pipe_reg6;
// synopsys translate_off
initial
input_is_infinity_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg8 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg8 <= input_is_infinity_pipe_reg7;
// synopsys translate_off
initial
input_is_infinity_pipe_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg9 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg9 <= input_is_infinity_pipe_reg8;
// synopsys translate_off
initial
input_is_nan_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg0 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg0 <= input_is_nan_pipe;
// synopsys translate_off
initial
input_is_nan_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg1 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg1 <= input_is_nan_pipe_reg0;
// synopsys translate_off
initial
input_is_nan_pipe_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg10 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg10 <= input_is_nan_pipe_reg9;
// synopsys translate_off
initial
input_is_nan_pipe_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg11 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg11 <= input_is_nan_pipe_reg10;
// synopsys translate_off
initial
input_is_nan_pipe_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg12 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg12 <= input_is_nan_pipe_reg11;
// synopsys translate_off
initial
input_is_nan_pipe_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg13 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg13 <= input_is_nan_pipe_reg12;
// synopsys translate_off
initial
input_is_nan_pipe_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg14 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg14 <= input_is_nan_pipe_reg13;
// synopsys translate_off
initial
input_is_nan_pipe_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg15 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg15 <= input_is_nan_pipe_reg14;
// synopsys translate_off
initial
input_is_nan_pipe_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg16 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg16 <= input_is_nan_pipe_reg15;
// synopsys translate_off
initial
input_is_nan_pipe_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg17 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg17 <= input_is_nan_pipe_reg16;
// synopsys translate_off
initial
input_is_nan_pipe_reg18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg18 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg18 <= input_is_nan_pipe_reg17;
// synopsys translate_off
initial
input_is_nan_pipe_reg19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg19 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg19 <= input_is_nan_pipe_reg18;
// synopsys translate_off
initial
input_is_nan_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg2 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg2 <= input_is_nan_pipe_reg1;
// synopsys translate_off
initial
input_is_nan_pipe_reg20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg20 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg20 <= input_is_nan_pipe_reg19;
// synopsys translate_off
initial
input_is_nan_pipe_reg21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg21 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg21 <= input_is_nan_pipe_reg20;
// synopsys translate_off
initial
input_is_nan_pipe_reg22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg22 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg22 <= input_is_nan_pipe_reg21;
// synopsys translate_off
initial
input_is_nan_pipe_reg23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg23 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg23 <= input_is_nan_pipe_reg22;
// synopsys translate_off
initial
input_is_nan_pipe_reg24 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg24 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg24 <= input_is_nan_pipe_reg23;
// synopsys translate_off
initial
input_is_nan_pipe_reg25 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg25 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg25 <= input_is_nan_pipe_reg24;
// synopsys translate_off
initial
input_is_nan_pipe_reg26 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg26 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg26 <= input_is_nan_pipe_reg25;
// synopsys translate_off
initial
input_is_nan_pipe_reg27 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg27 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg27 <= input_is_nan_pipe_reg26;
// synopsys translate_off
initial
input_is_nan_pipe_reg28 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg28 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg28 <= input_is_nan_pipe_reg27;
// synopsys translate_off
initial
input_is_nan_pipe_reg29 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg29 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg29 <= input_is_nan_pipe_reg28;
// synopsys translate_off
initial
input_is_nan_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg3 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg3 <= input_is_nan_pipe_reg2;
// synopsys translate_off
initial
input_is_nan_pipe_reg30 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg30 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg30 <= input_is_nan_pipe_reg29;
// synopsys translate_off
initial
input_is_nan_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg4 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg4 <= input_is_nan_pipe_reg3;
// synopsys translate_off
initial
input_is_nan_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg5 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg5 <= input_is_nan_pipe_reg4;
// synopsys translate_off
initial
input_is_nan_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg6 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg6 <= input_is_nan_pipe_reg5;
// synopsys translate_off
initial
input_is_nan_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg7 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg7 <= input_is_nan_pipe_reg6;
// synopsys translate_off
initial
input_is_nan_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg8 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg8 <= input_is_nan_pipe_reg7;
// synopsys translate_off
initial
input_is_nan_pipe_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg9 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg9 <= input_is_nan_pipe_reg8;
// synopsys translate_off
initial
input_is_one_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg0 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg0 <= input_is_one_pipe;
// synopsys translate_off
initial
input_is_one_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg1 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg1 <= input_is_one_pipe_reg0;
// synopsys translate_off
initial
input_is_one_pipe_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg10 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg10 <= input_is_one_pipe_reg9;
// synopsys translate_off
initial
input_is_one_pipe_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg11 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg11 <= input_is_one_pipe_reg10;
// synopsys translate_off
initial
input_is_one_pipe_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg12 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg12 <= input_is_one_pipe_reg11;
// synopsys translate_off
initial
input_is_one_pipe_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg13 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg13 <= input_is_one_pipe_reg12;
// synopsys translate_off
initial
input_is_one_pipe_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg14 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg14 <= input_is_one_pipe_reg13;
// synopsys translate_off
initial
input_is_one_pipe_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg15 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg15 <= input_is_one_pipe_reg14;
// synopsys translate_off
initial
input_is_one_pipe_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg16 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg16 <= input_is_one_pipe_reg15;
// synopsys translate_off
initial
input_is_one_pipe_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg17 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg17 <= input_is_one_pipe_reg16;
// synopsys translate_off
initial
input_is_one_pipe_reg18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg18 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg18 <= input_is_one_pipe_reg17;
// synopsys translate_off
initial
input_is_one_pipe_reg19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg19 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg19 <= input_is_one_pipe_reg18;
// synopsys translate_off
initial
input_is_one_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg2 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg2 <= input_is_one_pipe_reg1;
// synopsys translate_off
initial
input_is_one_pipe_reg20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg20 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg20 <= input_is_one_pipe_reg19;
// synopsys translate_off
initial
input_is_one_pipe_reg21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg21 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg21 <= input_is_one_pipe_reg20;
// synopsys translate_off
initial
input_is_one_pipe_reg22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg22 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg22 <= input_is_one_pipe_reg21;
// synopsys translate_off
initial
input_is_one_pipe_reg23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg23 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg23 <= input_is_one_pipe_reg22;
// synopsys translate_off
initial
input_is_one_pipe_reg24 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg24 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg24 <= input_is_one_pipe_reg23;
// synopsys translate_off
initial
input_is_one_pipe_reg25 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg25 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg25 <= input_is_one_pipe_reg24;
// synopsys translate_off
initial
input_is_one_pipe_reg26 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg26 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg26 <= input_is_one_pipe_reg25;
// synopsys translate_off
initial
input_is_one_pipe_reg27 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg27 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg27 <= input_is_one_pipe_reg26;
// synopsys translate_off
initial
input_is_one_pipe_reg28 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg28 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg28 <= input_is_one_pipe_reg27;
// synopsys translate_off
initial
input_is_one_pipe_reg29 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg29 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg29 <= input_is_one_pipe_reg28;
// synopsys translate_off
initial
input_is_one_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg3 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg3 <= input_is_one_pipe_reg2;
// synopsys translate_off
initial
input_is_one_pipe_reg30 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg30 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg30 <= input_is_one_pipe_reg29;
// synopsys translate_off
initial
input_is_one_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg4 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg4 <= input_is_one_pipe_reg3;
// synopsys translate_off
initial
input_is_one_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg5 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg5 <= input_is_one_pipe_reg4;
// synopsys translate_off
initial
input_is_one_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg6 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg6 <= input_is_one_pipe_reg5;
// synopsys translate_off
initial
input_is_one_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg7 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg7 <= input_is_one_pipe_reg6;
// synopsys translate_off
initial
input_is_one_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg8 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg8 <= input_is_one_pipe_reg7;
// synopsys translate_off
initial
input_is_one_pipe_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg9 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg9 <= input_is_one_pipe_reg8;
// synopsys translate_off
initial
input_is_zero_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg0 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg0 <= input_is_zero_pipe;
// synopsys translate_off
initial
input_is_zero_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg1 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg1 <= input_is_zero_pipe_reg0;
// synopsys translate_off
initial
input_is_zero_pipe_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg10 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg10 <= input_is_zero_pipe_reg9;
// synopsys translate_off
initial
input_is_zero_pipe_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg11 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg11 <= input_is_zero_pipe_reg10;
// synopsys translate_off
initial
input_is_zero_pipe_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg12 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg12 <= input_is_zero_pipe_reg11;
// synopsys translate_off
initial
input_is_zero_pipe_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg13 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg13 <= input_is_zero_pipe_reg12;
// synopsys translate_off
initial
input_is_zero_pipe_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg14 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg14 <= input_is_zero_pipe_reg13;
// synopsys translate_off
initial
input_is_zero_pipe_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg15 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg15 <= input_is_zero_pipe_reg14;
// synopsys translate_off
initial
input_is_zero_pipe_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg16 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg16 <= input_is_zero_pipe_reg15;
// synopsys translate_off
initial
input_is_zero_pipe_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg17 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg17 <= input_is_zero_pipe_reg16;
// synopsys translate_off
initial
input_is_zero_pipe_reg18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg18 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg18 <= input_is_zero_pipe_reg17;
// synopsys translate_off
initial
input_is_zero_pipe_reg19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg19 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg19 <= input_is_zero_pipe_reg18;
// synopsys translate_off
initial
input_is_zero_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg2 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg2 <= input_is_zero_pipe_reg1;
// synopsys translate_off
initial
input_is_zero_pipe_reg20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg20 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg20 <= input_is_zero_pipe_reg19;
// synopsys translate_off
initial
input_is_zero_pipe_reg21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg21 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg21 <= input_is_zero_pipe_reg20;
// synopsys translate_off
initial
input_is_zero_pipe_reg22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg22 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg22 <= input_is_zero_pipe_reg21;
// synopsys translate_off
initial
input_is_zero_pipe_reg23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg23 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg23 <= input_is_zero_pipe_reg22;
// synopsys translate_off
initial
input_is_zero_pipe_reg24 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg24 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg24 <= input_is_zero_pipe_reg23;
// synopsys translate_off
initial
input_is_zero_pipe_reg25 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg25 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg25 <= input_is_zero_pipe_reg24;
// synopsys translate_off
initial
input_is_zero_pipe_reg26 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg26 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg26 <= input_is_zero_pipe_reg25;
// synopsys translate_off
initial
input_is_zero_pipe_reg27 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg27 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg27 <= input_is_zero_pipe_reg26;
// synopsys translate_off
initial
input_is_zero_pipe_reg28 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg28 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg28 <= input_is_zero_pipe_reg27;
// synopsys translate_off
initial
input_is_zero_pipe_reg29 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg29 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg29 <= input_is_zero_pipe_reg28;
// synopsys translate_off
initial
input_is_zero_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg3 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg3 <= input_is_zero_pipe_reg2;
// synopsys translate_off
initial
input_is_zero_pipe_reg30 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg30 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg30 <= input_is_zero_pipe_reg29;
// synopsys translate_off
initial
input_is_zero_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg4 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg4 <= input_is_zero_pipe_reg3;
// synopsys translate_off
initial
input_is_zero_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg5 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg5 <= input_is_zero_pipe_reg4;
// synopsys translate_off
initial
input_is_zero_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg6 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg6 <= input_is_zero_pipe_reg5;
// synopsys translate_off
initial
input_is_zero_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg7 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg7 <= input_is_zero_pipe_reg6;
// synopsys translate_off
initial
input_is_zero_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg8 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg8 <= input_is_zero_pipe_reg7;
// synopsys translate_off
initial
input_is_zero_pipe_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg9 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg9 <= input_is_zero_pipe_reg8;
// synopsys translate_off
initial
Log_normal_normd_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Log_normal_normd_pipe_reg0 <= 94'b0;
else if (clk_en == 1'b1) Log_normal_normd_pipe_reg0 <= Log_normal_normd_pipe;
// synopsys translate_off
initial
Log_normal_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Log_normal_reg0 <= 94'b0;
else if (clk_en == 1'b1) Log_normal_reg0 <= Log_normal;
// synopsys translate_off
initial
Log_small_normd_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Log_small_normd_pipe_reg0 <= 57'b0;
else if (clk_en == 1'b1) Log_small_normd_pipe_reg0 <= Log_small_normd_pipe;
// synopsys translate_off
initial
Log_small_normd_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Log_small_normd_pipe_reg1 <= 57'b0;
else if (clk_en == 1'b1) Log_small_normd_pipe_reg1 <= Log_small_normd_pipe_reg0;
// synopsys translate_off
initial
Lshiftval_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Lshiftval_reg0 <= 7'b0;
else if (clk_en == 1'b1) Lshiftval_reg0 <= Lshiftval;
// synopsys translate_off
initial
Lshiftval_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Lshiftval_reg1 <= 7'b0;
else if (clk_en == 1'b1) Lshiftval_reg1 <= Lshiftval_reg0;
// synopsys translate_off
initial
Lshiftval_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Lshiftval_reg2 <= 7'b0;
else if (clk_en == 1'b1) Lshiftval_reg2 <= Lshiftval_reg1;
// synopsys translate_off
initial
Lshiftval_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Lshiftval_reg3 <= 7'b0;
else if (clk_en == 1'b1) Lshiftval_reg3 <= Lshiftval_reg2;
// synopsys translate_off
initial
lzo_pipe1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg0 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg0 <= lzo_pipe1;
// synopsys translate_off
initial
lzo_pipe1_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg1 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg1 <= lzo_pipe1_reg0;
// synopsys translate_off
initial
lzo_pipe1_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg10 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg10 <= lzo_pipe1_reg9;
// synopsys translate_off
initial
lzo_pipe1_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg11 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg11 <= lzo_pipe1_reg10;
// synopsys translate_off
initial
lzo_pipe1_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg12 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg12 <= lzo_pipe1_reg11;
// synopsys translate_off
initial
lzo_pipe1_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg13 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg13 <= lzo_pipe1_reg12;
// synopsys translate_off
initial
lzo_pipe1_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg14 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg14 <= lzo_pipe1_reg13;
// synopsys translate_off
initial
lzo_pipe1_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg15 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg15 <= lzo_pipe1_reg14;
// synopsys translate_off
initial
lzo_pipe1_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg16 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg16 <= lzo_pipe1_reg15;
// synopsys translate_off
initial
lzo_pipe1_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg17 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg17 <= lzo_pipe1_reg16;
// synopsys translate_off
initial
lzo_pipe1_reg18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg18 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg18 <= lzo_pipe1_reg17;
// synopsys translate_off
initial
lzo_pipe1_reg19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg19 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg19 <= lzo_pipe1_reg18;
// synopsys translate_off
initial
lzo_pipe1_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg2 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg2 <= lzo_pipe1_reg1;
// synopsys translate_off
initial
lzo_pipe1_reg20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg20 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg20 <= lzo_pipe1_reg19;
// synopsys translate_off
initial
lzo_pipe1_reg21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg21 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg21 <= lzo_pipe1_reg20;
// synopsys translate_off
initial
lzo_pipe1_reg22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg22 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg22 <= lzo_pipe1_reg21;
// synopsys translate_off
initial
lzo_pipe1_reg23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg23 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg23 <= lzo_pipe1_reg22;
// synopsys translate_off
initial
lzo_pipe1_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg3 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg3 <= lzo_pipe1_reg2;
// synopsys translate_off
initial
lzo_pipe1_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg4 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg4 <= lzo_pipe1_reg3;
// synopsys translate_off
initial
lzo_pipe1_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg5 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg5 <= lzo_pipe1_reg4;
// synopsys translate_off
initial
lzo_pipe1_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg6 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg6 <= lzo_pipe1_reg5;
// synopsys translate_off
initial
lzo_pipe1_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg7 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg7 <= lzo_pipe1_reg6;
// synopsys translate_off
initial
lzo_pipe1_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg8 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg8 <= lzo_pipe1_reg7;
// synopsys translate_off
initial
lzo_pipe1_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg9 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg9 <= lzo_pipe1_reg8;
// synopsys translate_off
initial
lzo_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg0 <= 6'b0;
else if (clk_en == 1'b1) lzo_reg0 <= lzo;
// synopsys translate_off
initial
lzo_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg1 <= 6'b0;
else if (clk_en == 1'b1) lzo_reg1 <= lzo_reg0;
// synopsys translate_off
initial
lzo_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg2 <= 6'b0;
else if (clk_en == 1'b1) lzo_reg2 <= lzo_reg1;
// synopsys translate_off
initial
lzo_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg3 <= 6'b0;
else if (clk_en == 1'b1) lzo_reg3 <= lzo_reg2;
// synopsys translate_off
initial
lzo_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg4 <= 6'b0;
else if (clk_en == 1'b1) lzo_reg4 <= lzo_reg3;
// synopsys translate_off
initial
lzo_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg5 <= 6'b0;
else if (clk_en == 1'b1) lzo_reg5 <= lzo_reg4;
// synopsys translate_off
initial
lzo_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg6 <= 6'b0;
else if (clk_en == 1'b1) lzo_reg6 <= lzo_reg5;
// synopsys translate_off
initial
sign_data_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_data_reg0 <= 1'b0;
else if (clk_en == 1'b1) sign_data_reg0 <= sign_data;
// synopsys translate_off
initial
sign_data_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_data_reg1 <= 1'b0;
else if (clk_en == 1'b1) sign_data_reg1 <= sign_data_reg0;
// synopsys translate_off
initial
sign_data_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_data_reg2 <= 1'b0;
else if (clk_en == 1'b1) sign_data_reg2 <= sign_data_reg1;
// synopsys translate_off
initial
small_flag_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg0 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg0 <= small_flag_pipe;
// synopsys translate_off
initial
small_flag_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg1 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg1 <= small_flag_pipe_reg0;
// synopsys translate_off
initial
small_flag_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg2 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg2 <= small_flag_pipe_reg1;
// synopsys translate_off
initial
small_flag_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg3 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg3 <= small_flag_pipe_reg2;
// synopsys translate_off
initial
small_flag_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg4 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg4 <= small_flag_pipe_reg3;
// synopsys translate_off
initial
small_flag_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg5 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg5 <= small_flag_pipe_reg4;
// synopsys translate_off
initial
small_flag_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg6 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg6 <= small_flag_pipe_reg5;
// synopsys translate_off
initial
small_flag_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg7 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg7 <= small_flag_pipe_reg6;
// synopsys translate_off
initial
small_flag_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg8 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg8 <= small_flag_pipe_reg7;
// synopsys translate_off
initial
sR_pipe1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg0 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg0 <= sR_pipe1;
// synopsys translate_off
initial
sR_pipe1_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg1 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg1 <= sR_pipe1_reg0;
// synopsys translate_off
initial
sR_pipe1_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg10 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg10 <= sR_pipe1_reg9;
// synopsys translate_off
initial
sR_pipe1_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg11 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg11 <= sR_pipe1_reg10;
// synopsys translate_off
initial
sR_pipe1_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg12 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg12 <= sR_pipe1_reg11;
// synopsys translate_off
initial
sR_pipe1_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg13 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg13 <= sR_pipe1_reg12;
// synopsys translate_off
initial
sR_pipe1_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg14 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg14 <= sR_pipe1_reg13;
// synopsys translate_off
initial
sR_pipe1_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg15 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg15 <= sR_pipe1_reg14;
// synopsys translate_off
initial
sR_pipe1_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg16 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg16 <= sR_pipe1_reg15;
// synopsys translate_off
initial
sR_pipe1_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg17 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg17 <= sR_pipe1_reg16;
// synopsys translate_off
initial
sR_pipe1_reg18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg18 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg18 <= sR_pipe1_reg17;
// synopsys translate_off
initial
sR_pipe1_reg19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg19 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg19 <= sR_pipe1_reg18;
// synopsys translate_off
initial
sR_pipe1_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg2 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg2 <= sR_pipe1_reg1;
// synopsys translate_off
initial
sR_pipe1_reg20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg20 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg20 <= sR_pipe1_reg19;
// synopsys translate_off
initial
sR_pipe1_reg21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg21 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg21 <= sR_pipe1_reg20;
// synopsys translate_off
initial
sR_pipe1_reg22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg22 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg22 <= sR_pipe1_reg21;
// synopsys translate_off
initial
sR_pipe1_reg23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg23 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg23 <= sR_pipe1_reg22;
// synopsys translate_off
initial
sR_pipe1_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg3 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg3 <= sR_pipe1_reg2;
// synopsys translate_off
initial
sR_pipe1_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg4 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg4 <= sR_pipe1_reg3;
// synopsys translate_off
initial
sR_pipe1_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg5 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg5 <= sR_pipe1_reg4;
// synopsys translate_off
initial
sR_pipe1_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg6 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg6 <= sR_pipe1_reg5;
// synopsys translate_off
initial
sR_pipe1_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg7 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg7 <= sR_pipe1_reg6;
// synopsys translate_off
initial
sR_pipe1_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg8 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg8 <= sR_pipe1_reg7;
// synopsys translate_off
initial
sR_pipe1_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg9 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg9 <= sR_pipe1_reg8;
// synopsys translate_off
initial
sR_pipe2_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe2_reg0 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe2_reg0 <= sR_pipe2;
// synopsys translate_off
initial
sR_pipe2_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe2_reg1 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe2_reg1 <= sR_pipe2_reg0;
// synopsys translate_off
initial
sR_pipe2_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe2_reg2 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe2_reg2 <= sR_pipe2_reg1;
// synopsys translate_off
initial
sR_pipe2_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe2_reg3 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe2_reg3 <= sR_pipe2_reg2;
// synopsys translate_off
initial
sR_pipe2_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe2_reg4 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe2_reg4 <= sR_pipe2_reg3;
// synopsys translate_off
initial
sR_pipe2_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe2_reg5 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe2_reg5 <= sR_pipe2_reg4;
// synopsys translate_off
initial
sR_pipe3_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe3_reg0 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe3_reg0 <= sR_pipe3;
// synopsys translate_off
initial
sR_pipe3_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe3_reg1 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe3_reg1 <= sR_pipe3_reg0;
// synopsys translate_off
initial
sR_pipe3_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe3_reg2 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe3_reg2 <= sR_pipe3_reg1;
// synopsys translate_off
initial
sR_pipe3_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe3_reg3 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe3_reg3 <= sR_pipe3_reg2;
// synopsys translate_off
initial
Z2o2_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z2o2_pipe_reg0 <= 28'b0;
else if (clk_en == 1'b1) Z2o2_pipe_reg0 <= Z2o2_pipe;
// synopsys translate_off
initial
Z2o2_small_s_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z2o2_small_s_pipe_reg0 <= 28'b0;
else if (clk_en == 1'b1) Z2o2_small_s_pipe_reg0 <= Z2o2_small_s_pipe;
// synopsys translate_off
initial
Zfinal_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Zfinal_reg0 <= 55'b0;
else if (clk_en == 1'b1) Zfinal_reg0 <= Zfinal;
// synopsys translate_off
initial
Zfinal_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Zfinal_reg1 <= 55'b0;
else if (clk_en == 1'b1) Zfinal_reg1 <= Zfinal_reg0;
lpm_add_sub addsub1
(
.add_sub(sR_pipe3),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(Z_small),
.datab(Z2o2_small),
.overflow(),
.result(wire_addsub1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
addsub1.lpm_pipeline = 1,
addsub1.lpm_representation = "UNSIGNED",
addsub1.lpm_width = 59,
addsub1.lpm_type = "lpm_add_sub";
lpm_add_sub addsub2
(
.add_sub((~ sR_pipe3)),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(absELog2_pad),
.datab(LogF_normal_pad),
.overflow(),
.result(wire_addsub2_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
addsub2.lpm_pipeline = 1,
addsub2.lpm_representation = "UNSIGNED",
addsub2.lpm_width = 94,
addsub2.lpm_type = "lpm_add_sub";
lpm_mult mult1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(absE),
.datab(Log2),
.result(wire_mult1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult1.lpm_pipeline = 3,
mult1.lpm_representation = "UNSIGNED",
mult1.lpm_widtha = 11,
mult1.lpm_widthb = 57,
mult1.lpm_widthp = 68,
mult1.lpm_type = "lpm_mult";
assign wire_mux_result0a_dataout = ((((input_is_zero | input_is_infinity) | input_is_nan) | input_is_one) === 1'b1) ? {{11{((~ input_is_one) | input_is_nan)}}, input_is_nan, {51{1'b0}}} : EFR;
assign
absE = (({11{(~ sR_pipe2)}} & E0) | ({11{sR_pipe2}} & wire_sub2_result)),
absELog2 = absELog2_pipe_reg2,
absELog2_pad = {absELog2, {26{1'b0}}},
absELog2_pipe = wire_mult1_result,
absZ0 = absZ0_pipe_reg23,
absZ0_pipe = (({26{(~ sR_pipe1)}} & Y0[25:0]) | ({26{sR_pipe1}} & wire_sub1_result)),
absZ0s = wire_Lshiftsmall_result[63:38],
absZ0s_pipe1 = absZ0s_reg0,
absZ0s_pipe2 = absZ0s_pipe1_reg3,
aclr = 1'b0,
almostLog = almostLog_pipe_reg2,
almostLog_pipe = wire_range_reduction_almostlog,
data_exp_is_ebiase = {((~ exp_data[10]) & data_exp_is_ebiase[9]), (exp_data[9] & data_exp_is_ebiase[8]), (exp_data[8] & data_exp_is_ebiase[7]), (exp_data[7] & data_exp_is_ebiase[6]), (exp_data[6] & data_exp_is_ebiase[5]), (exp_data[5] & data_exp_is_ebiase[4]), (exp_data[4] & data_exp_is_ebiase[3]), (exp_data[3] & data_exp_is_ebiase[2]), (exp_data[2] & data_exp_is_ebiase[1]), (exp_data[1] & data_exp_is_ebiase[0]), exp_data[0]},
doRR = Lshiftval[6],
doRR_pipe = doRR_reg1,
E0 = E0_pipe_reg23,
E0_is_zero = {((~ E0[10]) & E0_is_zero[9]), ((~ E0[9]) & E0_is_zero[8]), ((~ E0[8]) & E0_is_zero[7]), ((~ E0[7]) & E0_is_zero[6]), ((~ E0[6]) & E0_is_zero[5]), ((~ E0[5]) & E0_is_zero[4]), ((~ E0[4]) & E0_is_zero[3]), ((~ E0[3]) & E0_is_zero[2]), ((~ E0[2]) & E0_is_zero[1]), ((~ E0[1]) & E0_is_zero[0]), (~ E0[0])},
E0_pipe = wire_exp_biase_sub_result,
E0_sub = {(Log_small[58] | Log_small[57]), (Log_small[58] | (~ Log_small[57]))},
E0offset = 11'b10000001001,
E_normal = E_normal_pipe_reg0,
E_normal_pipe = wire_lzc_norm_E_q[5:0],
E_small = wire_sub5_result,
EFR = wire_add2_result,
ER = (({11{(~ small_flag)}} & wire_sub6_result) | ({11{small_flag}} & E_small)),
exp_all_one = wire_exp_nan_result,
exp_all_zero = wire_exp_zero_result,
exp_biase = {10'b0111111111, (~ First_bit)},
exp_data = data[62:52],
exp_is_ebiase = exp_is_ebiase_pipe_reg2,
exp_is_ebiase_pipe = data_exp_is_ebiase[10],
First_bit = man_data[51],
input_is_infinity = input_is_infinity_pipe_reg30,
input_is_infinity_pipe = (exp_all_one & (~ man_all_zero)),
input_is_nan = input_is_nan_pipe_reg30,
input_is_nan_pipe = ((exp_all_one & man_not_zero) | sign_data_pipe),
input_is_one = input_is_one_pipe_reg30,
input_is_one_pipe = (exp_is_ebiase & (~ man_all_zero)),
input_is_zero = input_is_zero_pipe_reg30,
input_is_zero_pipe = (~ exp_all_zero),
Log1p_normal = wire_sub4_result,
Log2 = 57'b101100010111001000010111111101111101000111001111011110011,
Log_g = (({57{(~ small_flag)}} & Log_normal_normd[92:36]) | ({57{small_flag}} & {Log_small_normd[55:0], 1'b0})),
Log_normal = wire_addsub2_result,
Log_normal_normd = Log_normal_normd_pipe_reg0,
Log_normal_normd_pipe = wire_lzc_norm_L_result[127:34],
Log_normal_pipe = Log_normal_reg0,
Log_small = wire_addsub1_result,
Log_small1 = (({57{(~ Log_small[57])}} & Log_small[56:0]) | ({57{Log_small[57]}} & Log_small[57:1])),
Log_small2 = (({57{(~ Log_small[58])}} & Log_small1) | ({57{Log_small[58]}} & Log_small[58:2])),
Log_small_normd = Log_small_normd_pipe_reg1,
Log_small_normd_pipe = Log_small2,
LogF_normal = wire_add1_result,
LogF_normal_pad = {{11{LogF_normal[82]}}, LogF_normal},
Lshiftval = wire_sub3_result,
lzo = lzo_pipe1_reg23,
lzo_pipe1 = (~ wire_lzoc_q),
lzo_pipe2 = lzo_reg6,
man_above_half = {1'b0, 1'b1, man_data},
man_all_zero = wire_man_inf_result,
man_below_half = {1'b1, man_data, 1'b0},
man_data = data[51:0],
man_not_zero = wire_man_nan_result,
pfinal_s = 6'b011100,
result = {(((sR | input_is_zero) | input_is_nan) & (~ input_is_one)), wire_mux_result0a_dataout},
round = (Log_g[4] & (Log_g[5] | sticky[3])),
Rshiftval = Lshiftval_reg3,
sign_data = data[63],
sign_data_pipe = sign_data_reg2,
small_flag = small_flag_pipe_reg8,
small_flag_pipe = ((~ doRR) & E0_is_zero[10]),
squarerIn = (({27{(~ doRR_pipe)}} & squarerIn0) | ({27{doRR_pipe}} & squarerIn1)),
squarerIn0 = {absZ0s_pipe1, 1'b0},
squarerIn1 = Zfinal[54:28],
sR = sR_pipe3_reg3,
sR_pipe1 = (~ (data_exp_is_ebiase[10] | exp_data[10])),
sR_pipe2 = sR_pipe1_reg23,
sR_pipe3 = sR_pipe2_reg5,
sticky = {(Log_g[3] | sticky[2]), (Log_g[2] | sticky[1]), (Log_g[1] | sticky[0]), Log_g[0]},
Y0 = (({54{(~ First_bit)}} & man_below_half) | ({54{First_bit}} & man_above_half)),
Z2o2 = Z2o2_pipe_reg0,
Z2o2_pipe = wire_squarer_result,
Z2o2_small = {{28{1'b0}}, Z2o2_small_s, {3{1'b0}}},
Z2o2_small_s = Z2o2_small_s_pipe_reg0,
Z2o2_small_s_pipe = wire_Rshiftsmall_result[63:36],
Z_small = {absZ0s_pipe2, {33{1'b0}}},
Zfinal = wire_range_reduction_z,
Zfinal_pipe = Zfinal_reg1;
endmodule //acl_fp_log_s5_double_altfp_log_o3b
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_log_s5_double (
enable,
clock,
dataa,
result);
input enable;
input clock;
input [63:0] dataa;
output [63:0] result;
wire [63:0] sub_wire0;
wire [63:0] result = sub_wire0[63:0];
acl_fp_log_s5_double_altfp_log_o3b acl_fp_log_s5_double_altfp_log_o3b_component (
.clk_en (enable),
.clock (clock),
.data (dataa),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altfp_log"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "34"
// Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "52"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL "data[63..0]"
// Retrieval info: CONNECT: @data 0 0 64 0 data 0 0 64 0
// Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT NODEFVAL "result[63..0]"
// Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log_s5_double.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log_s5_double.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log_s5_double.bsf TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log_s5_double_inst.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log_s5_double_bb.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log_s5_double.inc TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log_s5_double.cmp TRUE TRUE
// Retrieval info: LIB_FILE: lpm
|
module bram1_tb #(
parameter ABITS = 8, DBITS = 8, TRANSP = 0
);
reg clk;
reg [ABITS-1:0] WR_ADDR;
reg [DBITS-1:0] WR_DATA;
reg WR_EN;
reg [ABITS-1:0] RD_ADDR;
wire [DBITS-1:0] RD_DATA;
localparam [ABITS-1:0] INIT_ADDR_0 = 1234;
localparam [ABITS-1:0] INIT_ADDR_1 = 4321;
localparam [ABITS-1:0] INIT_ADDR_2 = 2**ABITS-1;
localparam [ABITS-1:0] INIT_ADDR_3 = (2**ABITS-1) / 2;
localparam [DBITS-1:0] INIT_DATA_0 = 128'h 51e152a7300e309ccb8cd06d34558f49;
localparam [DBITS-1:0] INIT_DATA_1 = 128'h 07b1fe94a530ddf3027520f9d23ab43e;
localparam [DBITS-1:0] INIT_DATA_2 = 128'h 3cedc6de43ef3f607af3193658d0eb0b;
localparam [DBITS-1:0] INIT_DATA_3 = 128'h f6bc5514a8abf1e2810df966bcc13b46;
bram1 #(
// .ABITS(ABITS),
// .DBITS(DBITS),
// .TRANSP(TRANSP)
) uut (
.clk (clk ),
.WR_ADDR(WR_ADDR),
.WR_DATA(WR_DATA),
.WR_EN (WR_EN ),
.RD_ADDR(RD_ADDR),
.RD_DATA(RD_DATA)
);
reg [63:0] xorshift64_state = 64'd88172645463325252 ^ (ABITS << 24) ^ (DBITS << 16) ^ (TRANSP << 8);
task xorshift64_next;
begin
// see page 4 of Marsaglia, George (July 2003). "Xorshift RNGs". Journal of Statistical Software 8 (14).
xorshift64_state = xorshift64_state ^ (xorshift64_state << 13);
xorshift64_state = xorshift64_state ^ (xorshift64_state >> 7);
xorshift64_state = xorshift64_state ^ (xorshift64_state << 17);
end
endtask
reg [ABITS-1:0] randaddr1;
reg [ABITS-1:0] randaddr2;
reg [ABITS-1:0] randaddr3;
function [31:0] getaddr(input [3:0] n);
begin
case (n)
0: getaddr = 0;
1: getaddr = 2**ABITS-1;
2: getaddr = 'b101 << (ABITS / 3);
3: getaddr = 'b101 << (2*ABITS / 3);
4: getaddr = 'b11011 << (ABITS / 4);
5: getaddr = 'b11011 << (2*ABITS / 4);
6: getaddr = 'b11011 << (3*ABITS / 4);
7: getaddr = randaddr1;
8: getaddr = randaddr2;
9: getaddr = randaddr3;
default: begin
getaddr = 1 << (2*n-16);
if (!getaddr) getaddr = xorshift64_state;
end
endcase
end
endfunction
reg [DBITS-1:0] memory [0:2**ABITS-1];
reg [DBITS-1:0] expected_rd, expected_rd_masked;
event error;
reg error_ind = 0;
integer i, j;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, bram1_tb);
memory[INIT_ADDR_0] = INIT_DATA_0;
memory[INIT_ADDR_1] = INIT_DATA_1;
memory[INIT_ADDR_2] = INIT_DATA_2;
memory[INIT_ADDR_3] = INIT_DATA_3;
xorshift64_next;
xorshift64_next;
xorshift64_next;
xorshift64_next;
randaddr1 = xorshift64_state;
xorshift64_next;
randaddr2 = xorshift64_state;
xorshift64_next;
randaddr3 = xorshift64_state;
xorshift64_next;
clk <= 0;
for (i = 0; i < 512; i = i+1) begin
if (i == 0) begin
WR_EN <= 0;
RD_ADDR <= INIT_ADDR_0;
end else
if (i == 1) begin
WR_EN <= 0;
RD_ADDR <= INIT_ADDR_1;
end else
if (i == 2) begin
WR_EN <= 0;
RD_ADDR <= INIT_ADDR_2;
end else
if (i == 3) begin
WR_EN <= 0;
RD_ADDR <= INIT_ADDR_3;
end else begin
if (DBITS > 64)
WR_DATA <= (xorshift64_state << (DBITS-64)) ^ xorshift64_state;
else
WR_DATA <= xorshift64_state;
xorshift64_next;
WR_ADDR <= getaddr(i < 256 ? i[7:4] : xorshift64_state[63:60]);
xorshift64_next;
RD_ADDR <= getaddr(i < 256 ? i[3:0] : xorshift64_state[59:56]);
WR_EN <= xorshift64_state[55];
xorshift64_next;
end
#1; clk <= 1;
#1; clk <= 0;
if (TRANSP) begin
if (WR_EN) memory[WR_ADDR] = WR_DATA;
expected_rd = memory[RD_ADDR];
end else begin
expected_rd = memory[RD_ADDR];
if (WR_EN) memory[WR_ADDR] = WR_DATA;
end
for (j = 0; j < DBITS; j = j+1)
expected_rd_masked[j] = expected_rd[j] !== 1'bx ? expected_rd[j] : RD_DATA[j];
$display("#OUT# %3d | WA=%x WD=%x WE=%x | RA=%x RD=%x (%x) | %s", i, WR_ADDR, WR_DATA, WR_EN, RD_ADDR, RD_DATA, expected_rd, expected_rd_masked === RD_DATA ? "ok" : "ERROR");
if (expected_rd_masked !== RD_DATA) begin -> error; error_ind = ~error_ind; end
end
end
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_alpha #(
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
output busy,
input [5:0] alpha,
input pipe_stb_i,
output pipe_ack_o,
input [15:0] color,
input [fml_depth-1-1:0] dadr, /* in 16-bit words */
input [15:0] dcolor,
output pipe_stb_o,
input pipe_ack_i,
output reg [fml_depth-1-1:0] dadr_f,
output [15:0] acolor
);
wire en;
reg valid_1;
reg valid_2;
reg valid_3;
always @(posedge sys_clk) begin
if(sys_rst) begin
valid_1 <= 1'b0;
valid_2 <= 1'b0;
valid_3 <= 1'b0;
end else if(en) begin
valid_1 <= pipe_stb_i;
valid_2 <= valid_1;
valid_3 <= valid_2;
end
end
/* Pipeline operation on three stages. */
reg [fml_depth-1-1:0] dadr_1;
reg [fml_depth-1-1:0] dadr_2;
wire [4:0] r = color[15:11];
wire [5:0] g = color[10:5];
wire [4:0] b = color[4:0];
wire [4:0] dr = dcolor[15:11];
wire [5:0] dg = dcolor[10:5];
wire [4:0] db = dcolor[4:0];
reg [10:0] r_1;
reg [11:0] g_1;
reg [10:0] b_1;
reg [10:0] dr_1;
reg [11:0] dg_1;
reg [10:0] db_1;
reg [10:0] r_2;
reg [11:0] g_2;
reg [10:0] b_2;
reg [10:0] dr_2;
reg [11:0] dg_2;
reg [10:0] db_2;
reg [10:0] r_3;
reg [11:0] g_3;
reg [10:0] b_3;
always @(posedge sys_clk) begin
if(en) begin
dadr_1 <= dadr;
dadr_2 <= dadr_1;
dadr_f <= dadr_2;
r_1 <= ({1'b0, alpha} + 7'd1)*r;
g_1 <= ({1'b0, alpha} + 7'd1)*g;
b_1 <= ({1'b0, alpha} + 7'd1)*b;
dr_1 <= (6'd63 - alpha)*dr;
dg_1 <= (6'd63 - alpha)*dg;
db_1 <= (6'd63 - alpha)*db;
r_2 <= r_1;
g_2 <= g_1;
b_2 <= b_1;
dr_2 <= dr_1;
dg_2 <= dg_1;
db_2 <= db_1;
r_3 <= r_2 + dr_2;
g_3 <= g_2 + dg_2;
b_3 <= b_2 + db_2;
end
end
assign acolor = {r_3[10:6], g_3[11:6], b_3[10:6]};
/* Pipeline management */
assign busy = valid_1 | valid_2 | valid_3;
assign pipe_ack_o = ~valid_3 | pipe_ack_i;
assign en = ~valid_3 | pipe_ack_i;
assign pipe_stb_o = valid_3;
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_arb_wr.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between 2 write requests from 2 ports.
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_arb_wr(
rstn,
sw_clk,
qos1,
qos2,
prt_dv1,
prt_dv2,
prt_data1,
prt_data2,
prt_addr1,
prt_addr2,
prt_bytes1,
prt_bytes2,
prt_ack1,
prt_ack2,
prt_qos,
prt_req,
prt_data,
prt_addr,
prt_bytes,
prt_ack
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2;
input [max_burst_bits-1:0] prt_data1,prt_data2;
input [addr_width-1:0] prt_addr1,prt_addr2;
input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2;
input prt_dv1, prt_dv2, prt_ack;
output reg prt_ack1,prt_ack2,prt_req;
output reg [max_burst_bits-1:0] prt_data;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
output reg [axi_qos_width-1:0] prt_qos;
parameter wait_req = 2'b00, serv_req1 = 2'b01, serv_req2 = 2'b10,wait_ack_low = 2'b11;
reg [1:0] state,temp_state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1'b0;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_req = 1'b0;
if(prt_dv1 && !prt_dv2) begin
state = serv_req1;
prt_req = 1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
prt_qos = qos1;
end else if(!prt_dv1 && prt_dv2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv1 && prt_dv2) begin
if(qos1 > qos2) begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end else if(qos1 < qos2) begin
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end else begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req1:begin
state = serv_req1;
prt_ack2 = 1'b0;
if(prt_ack) begin
prt_ack1 = 1'b1;
prt_req = 0;
if(prt_dv2) begin
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end else begin
// state = wait_req;
state = wait_ack_low;
end
end
end
serv_req2:begin
state = serv_req2;
prt_ack1 = 1'b0;
if(prt_ack) begin
prt_ack2 = 1'b1;
prt_req = 0;
if(prt_dv1) begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end else begin
state = wait_ack_low;
// state = wait_req;
end
end
end
wait_ack_low:begin
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
state = wait_ack_low;
if(!prt_ack)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// pipeline_registers.v
// Created: 4.4.2012
// Modified: 4.4.2012
//
// Implements a series of pipeline registers specified by the input
// parameters BIT_WIDTH and NUMBER_OF_STAGES. BIT_WIDTH determines the
// size of the signal passed through each of the pipeline
// registers. NUMBER_OF_STAGES is the number of pipeline registers
// generated. This accepts values of 0 (yes, it just passes data from
// input to output...) up to however many stages specified.
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module pipeline_registers
(
input clk,
input reset_n,
input [BIT_WIDTH-1:0] pipe_in,
output reg [BIT_WIDTH-1:0] pipe_out
);
// WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP
// LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE
// OVERWRITTEN!
parameter
BIT_WIDTH = 10,
NUMBER_OF_STAGES = 5;
// Main generate function for conditional hardware instantiation
generate
genvar i;
// Pass-through case for the odd event that no pipeline stages are
// specified.
if (NUMBER_OF_STAGES == 0) begin
always @ *
pipe_out = pipe_in;
end
// Single flop case for a single stage pipeline
else if (NUMBER_OF_STAGES == 1) begin
always @ (posedge clk or negedge reset_n)
pipe_out <= (!reset_n) ? 0 : pipe_in;
end
// Case for 2 or more pipeline stages
else begin
// Create the necessary regs
reg [BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:0] pipe_gen;
// Create logic for the initial and final pipeline registers
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
pipe_gen[BIT_WIDTH-1:0] <= 0;
pipe_out <= 0;
end
else begin
pipe_gen[BIT_WIDTH-1:0] <= pipe_in;
pipe_out <= pipe_gen[BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:BIT_WIDTH*(NUMBER_OF_STAGES-2)];
end
end
// Create the intermediate pipeline registers if there are 3 or
// more pipeline stages
for (i = 1; i < NUMBER_OF_STAGES-1; i = i + 1) begin : pipeline
always @ (posedge clk or negedge reset_n)
pipe_gen[BIT_WIDTH*(i+1)-1:BIT_WIDTH*i] <= (!reset_n) ? 0 : pipe_gen[BIT_WIDTH*i-1:BIT_WIDTH*(i-1)];
end
end
endgenerate
endmodule
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2014, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//
//-------------------------------------------------------------------
//
// Filename : ime_sad_8x8.v
// Author : Huang Lei Lei
// Created : 2014-12-08
// Description : calculate the SAD value of a 8x8 matrix
//
//-------------------------------------------------------------------
`include "enc_defines.v"
module ime_sad_8x8 (
// global
clk , rstn ,
// ena_i
enable_i ,
// ori_i
ori_i ,
/*
ori_00_i , ori_10_i , ori_20_i , ori_30_i , ori_40_i , ori_50_i , ori_60_i , ori_70_i ,
ori_01_i , ori_11_i , ori_21_i , ori_31_i , ori_41_i , ori_51_i , ori_61_i , ori_71_i ,
ori_02_i , ori_12_i , ori_22_i , ori_32_i , ori_42_i , ori_52_i , ori_62_i , ori_72_i ,
ori_03_i , ori_13_i , ori_23_i , ori_33_i , ori_43_i , ori_53_i , ori_63_i , ori_73_i ,
ori_04_i , ori_14_i , ori_24_i , ori_34_i , ori_44_i , ori_54_i , ori_64_i , ori_74_i ,
ori_05_i , ori_15_i , ori_25_i , ori_35_i , ori_45_i , ori_55_i , ori_65_i , ori_75_i ,
ori_06_i , ori_16_i , ori_26_i , ori_36_i , ori_46_i , ori_56_i , ori_66_i , ori_76_i ,
ori_07_i , ori_17_i , ori_27_i , ori_37_i , ori_47_i , ori_57_i , ori_67_i , ori_77_i ,
*/
// ref_i
ref_i ,
/*
ref_00_i , ref_10_i , ref_20_i , ref_30_i , ref_40_i , ref_50_i , ref_60_i , ref_70_i ,
ref_01_i , ref_11_i , ref_21_i , ref_31_i , ref_41_i , ref_51_i , ref_61_i , ref_71_i ,
ref_02_i , ref_12_i , ref_22_i , ref_32_i , ref_42_i , ref_52_i , ref_62_i , ref_72_i ,
ref_03_i , ref_13_i , ref_23_i , ref_33_i , ref_43_i , ref_53_i , ref_63_i , ref_73_i ,
ref_04_i , ref_14_i , ref_24_i , ref_34_i , ref_44_i , ref_54_i , ref_64_i , ref_74_i ,
ref_05_i , ref_15_i , ref_25_i , ref_35_i , ref_45_i , ref_55_i , ref_65_i , ref_75_i ,
ref_06_i , ref_16_i , ref_26_i , ref_36_i , ref_46_i , ref_56_i , ref_66_i , ref_76_i ,
ref_07_i , ref_17_i , ref_27_i , ref_37_i , ref_47_i , ref_57_i , ref_67_i , ref_77_i ,
*/
/*
// val_o
val_o ,
*/
// sad_o
sad_o
);
//*** PARAMETER DECLARATION ****************************************************
//*** INPUT/OUTPUT DECLARATION *************************************************
// global
input clk ;
input rstn ;
// ena_i
input enable_i ;
// ori_i
input [`PIXEL_WIDTH*64-1 : 0] ori_i ;
/*
input [`PIXEL_WIDTH-1 : 0] ori_00_i , ori_10_i , ori_20_i , ori_30_i ;
input [`PIXEL_WIDTH-1 : 0] ori_01_i , ori_11_i , ori_21_i , ori_31_i ;
input [`PIXEL_WIDTH-1 : 0] ori_02_i , ori_12_i , ori_22_i , ori_32_i ;
input [`PIXEL_WIDTH-1 : 0] ori_03_i , ori_13_i , ori_23_i , ori_33_i ;
input [`PIXEL_WIDTH-1 : 0] ori_04_i , ori_14_i , ori_24_i , ori_34_i ;
input [`PIXEL_WIDTH-1 : 0] ori_05_i , ori_15_i , ori_25_i , ori_35_i ;
input [`PIXEL_WIDTH-1 : 0] ori_06_i , ori_16_i , ori_26_i , ori_36_i ;
input [`PIXEL_WIDTH-1 : 0] ori_07_i , ori_17_i , ori_27_i , ori_37_i ;
input [`PIXEL_WIDTH-1 : 0] ori_40_i , ori_50_i , ori_60_i , ori_70_i ;
input [`PIXEL_WIDTH-1 : 0] ori_41_i , ori_51_i , ori_61_i , ori_71_i ;
input [`PIXEL_WIDTH-1 : 0] ori_42_i , ori_52_i , ori_62_i , ori_72_i ;
input [`PIXEL_WIDTH-1 : 0] ori_43_i , ori_53_i , ori_63_i , ori_73_i ;
input [`PIXEL_WIDTH-1 : 0] ori_44_i , ori_54_i , ori_64_i , ori_74_i ;
input [`PIXEL_WIDTH-1 : 0] ori_45_i , ori_55_i , ori_65_i , ori_75_i ;
input [`PIXEL_WIDTH-1 : 0] ori_46_i , ori_56_i , ori_66_i , ori_76_i ;
input [`PIXEL_WIDTH-1 : 0] ori_47_i , ori_57_i , ori_67_i , ori_77_i ;
*/
// ref_i
input [`PIXEL_WIDTH*64-1 : 0] ref_i ;
/*
input [`PIXEL_WIDTH-1 : 0] ref_00_i , ref_10_i , ref_20_i , ref_30_i ;
input [`PIXEL_WIDTH-1 : 0] ref_01_i , ref_11_i , ref_21_i , ref_31_i ;
input [`PIXEL_WIDTH-1 : 0] ref_02_i , ref_12_i , ref_22_i , ref_32_i ;
input [`PIXEL_WIDTH-1 : 0] ref_03_i , ref_13_i , ref_23_i , ref_33_i ;
input [`PIXEL_WIDTH-1 : 0] ref_04_i , ref_14_i , ref_24_i , ref_34_i ;
input [`PIXEL_WIDTH-1 : 0] ref_05_i , ref_15_i , ref_25_i , ref_35_i ;
input [`PIXEL_WIDTH-1 : 0] ref_06_i , ref_16_i , ref_26_i , ref_36_i ;
input [`PIXEL_WIDTH-1 : 0] ref_07_i , ref_17_i , ref_27_i , ref_37_i ;
input [`PIXEL_WIDTH-1 : 0] ref_40_i , ref_50_i , ref_60_i , ref_70_i ;
input [`PIXEL_WIDTH-1 : 0] ref_41_i , ref_51_i , ref_61_i , ref_71_i ;
input [`PIXEL_WIDTH-1 : 0] ref_42_i , ref_52_i , ref_62_i , ref_72_i ;
input [`PIXEL_WIDTH-1 : 0] ref_43_i , ref_53_i , ref_63_i , ref_73_i ;
input [`PIXEL_WIDTH-1 : 0] ref_44_i , ref_54_i , ref_64_i , ref_74_i ;
input [`PIXEL_WIDTH-1 : 0] ref_45_i , ref_55_i , ref_65_i , ref_75_i ;
input [`PIXEL_WIDTH-1 : 0] ref_46_i , ref_56_i , ref_66_i , ref_76_i ;
input [`PIXEL_WIDTH-1 : 0] ref_47_i , ref_57_i , ref_67_i , ref_77_i ;
*/
/*
// val_o
output reg val_o ;
*/
// sad_o
output reg [`PIXEL_WIDTH+6-1 : 0] sad_o ;
//*** WIRE & REG DECLARATION ***************************************************
wire [`PIXEL_WIDTH-1 : 0] ori_00_w , ori_10_w , ori_20_w , ori_30_w ;
wire [`PIXEL_WIDTH-1 : 0] ori_01_w , ori_11_w , ori_21_w , ori_31_w ;
wire [`PIXEL_WIDTH-1 : 0] ori_02_w , ori_12_w , ori_22_w , ori_32_w ;
wire [`PIXEL_WIDTH-1 : 0] ori_03_w , ori_13_w , ori_23_w , ori_33_w ;
wire [`PIXEL_WIDTH-1 : 0] ori_04_w , ori_14_w , ori_24_w , ori_34_w ;
wire [`PIXEL_WIDTH-1 : 0] ori_05_w , ori_15_w , ori_25_w , ori_35_w ;
wire [`PIXEL_WIDTH-1 : 0] ori_06_w , ori_16_w , ori_26_w , ori_36_w ;
wire [`PIXEL_WIDTH-1 : 0] ori_07_w , ori_17_w , ori_27_w , ori_37_w ;
wire [`PIXEL_WIDTH-1 : 0] ori_40_w , ori_50_w , ori_60_w , ori_70_w ;
wire [`PIXEL_WIDTH-1 : 0] ori_41_w , ori_51_w , ori_61_w , ori_71_w ;
wire [`PIXEL_WIDTH-1 : 0] ori_42_w , ori_52_w , ori_62_w , ori_72_w ;
wire [`PIXEL_WIDTH-1 : 0] ori_43_w , ori_53_w , ori_63_w , ori_73_w ;
wire [`PIXEL_WIDTH-1 : 0] ori_44_w , ori_54_w , ori_64_w , ori_74_w ;
wire [`PIXEL_WIDTH-1 : 0] ori_45_w , ori_55_w , ori_65_w , ori_75_w ;
wire [`PIXEL_WIDTH-1 : 0] ori_46_w , ori_56_w , ori_66_w , ori_76_w ;
wire [`PIXEL_WIDTH-1 : 0] ori_47_w , ori_57_w , ori_67_w , ori_77_w ;
wire [`PIXEL_WIDTH-1 : 0] ref_00_w , ref_10_w , ref_20_w , ref_30_w ;
wire [`PIXEL_WIDTH-1 : 0] ref_01_w , ref_11_w , ref_21_w , ref_31_w ;
wire [`PIXEL_WIDTH-1 : 0] ref_02_w , ref_12_w , ref_22_w , ref_32_w ;
wire [`PIXEL_WIDTH-1 : 0] ref_03_w , ref_13_w , ref_23_w , ref_33_w ;
wire [`PIXEL_WIDTH-1 : 0] ref_04_w , ref_14_w , ref_24_w , ref_34_w ;
wire [`PIXEL_WIDTH-1 : 0] ref_05_w , ref_15_w , ref_25_w , ref_35_w ;
wire [`PIXEL_WIDTH-1 : 0] ref_06_w , ref_16_w , ref_26_w , ref_36_w ;
wire [`PIXEL_WIDTH-1 : 0] ref_07_w , ref_17_w , ref_27_w , ref_37_w ;
wire [`PIXEL_WIDTH-1 : 0] ref_40_w , ref_50_w , ref_60_w , ref_70_w ;
wire [`PIXEL_WIDTH-1 : 0] ref_41_w , ref_51_w , ref_61_w , ref_71_w ;
wire [`PIXEL_WIDTH-1 : 0] ref_42_w , ref_52_w , ref_62_w , ref_72_w ;
wire [`PIXEL_WIDTH-1 : 0] ref_43_w , ref_53_w , ref_63_w , ref_73_w ;
wire [`PIXEL_WIDTH-1 : 0] ref_44_w , ref_54_w , ref_64_w , ref_74_w ;
wire [`PIXEL_WIDTH-1 : 0] ref_45_w , ref_55_w , ref_65_w , ref_75_w ;
wire [`PIXEL_WIDTH-1 : 0] ref_46_w , ref_56_w , ref_66_w , ref_76_w ;
wire [`PIXEL_WIDTH-1 : 0] ref_47_w , ref_57_w , ref_67_w , ref_77_w ;
// pixel difference
wire signed [`PIXEL_WIDTH : 0] p_d_00_w , p_d_10_w , p_d_20_w , p_d_30_w ;
wire signed [`PIXEL_WIDTH : 0] p_d_01_w , p_d_11_w , p_d_21_w , p_d_31_w ;
wire signed [`PIXEL_WIDTH : 0] p_d_02_w , p_d_12_w , p_d_22_w , p_d_32_w ;
wire signed [`PIXEL_WIDTH : 0] p_d_03_w , p_d_13_w , p_d_23_w , p_d_33_w ;
wire signed [`PIXEL_WIDTH : 0] p_d_04_w , p_d_14_w , p_d_24_w , p_d_34_w ;
wire signed [`PIXEL_WIDTH : 0] p_d_05_w , p_d_15_w , p_d_25_w , p_d_35_w ;
wire signed [`PIXEL_WIDTH : 0] p_d_06_w , p_d_16_w , p_d_26_w , p_d_36_w ;
wire signed [`PIXEL_WIDTH : 0] p_d_07_w , p_d_17_w , p_d_27_w , p_d_37_w ;
wire signed [`PIXEL_WIDTH : 0] p_d_40_w , p_d_50_w , p_d_60_w , p_d_70_w ;
wire signed [`PIXEL_WIDTH : 0] p_d_41_w , p_d_51_w , p_d_61_w , p_d_71_w ;
wire signed [`PIXEL_WIDTH : 0] p_d_42_w , p_d_52_w , p_d_62_w , p_d_72_w ;
wire signed [`PIXEL_WIDTH : 0] p_d_43_w , p_d_53_w , p_d_63_w , p_d_73_w ;
wire signed [`PIXEL_WIDTH : 0] p_d_44_w , p_d_54_w , p_d_64_w , p_d_74_w ;
wire signed [`PIXEL_WIDTH : 0] p_d_45_w , p_d_55_w , p_d_65_w , p_d_75_w ;
wire signed [`PIXEL_WIDTH : 0] p_d_46_w , p_d_56_w , p_d_66_w , p_d_76_w ;
wire signed [`PIXEL_WIDTH : 0] p_d_47_w , p_d_57_w , p_d_67_w , p_d_77_w ;
// pixel absolute difference
wire [`PIXEL_WIDTH-1 : 0] p_ad_00_w , p_ad_10_w , p_ad_20_w , p_ad_30_w ;
wire [`PIXEL_WIDTH-1 : 0] p_ad_01_w , p_ad_11_w , p_ad_21_w , p_ad_31_w ;
wire [`PIXEL_WIDTH-1 : 0] p_ad_02_w , p_ad_12_w , p_ad_22_w , p_ad_32_w ;
wire [`PIXEL_WIDTH-1 : 0] p_ad_03_w , p_ad_13_w , p_ad_23_w , p_ad_33_w ;
wire [`PIXEL_WIDTH-1 : 0] p_ad_04_w , p_ad_14_w , p_ad_24_w , p_ad_34_w ;
wire [`PIXEL_WIDTH-1 : 0] p_ad_05_w , p_ad_15_w , p_ad_25_w , p_ad_35_w ;
wire [`PIXEL_WIDTH-1 : 0] p_ad_06_w , p_ad_16_w , p_ad_26_w , p_ad_36_w ;
wire [`PIXEL_WIDTH-1 : 0] p_ad_07_w , p_ad_17_w , p_ad_27_w , p_ad_37_w ;
wire [`PIXEL_WIDTH-1 : 0] p_ad_40_w , p_ad_50_w , p_ad_60_w , p_ad_70_w ;
wire [`PIXEL_WIDTH-1 : 0] p_ad_41_w , p_ad_51_w , p_ad_61_w , p_ad_71_w ;
wire [`PIXEL_WIDTH-1 : 0] p_ad_42_w , p_ad_52_w , p_ad_62_w , p_ad_72_w ;
wire [`PIXEL_WIDTH-1 : 0] p_ad_43_w , p_ad_53_w , p_ad_63_w , p_ad_73_w ;
wire [`PIXEL_WIDTH-1 : 0] p_ad_44_w , p_ad_54_w , p_ad_64_w , p_ad_74_w ;
wire [`PIXEL_WIDTH-1 : 0] p_ad_45_w , p_ad_55_w , p_ad_65_w , p_ad_75_w ;
wire [`PIXEL_WIDTH-1 : 0] p_ad_46_w , p_ad_56_w , p_ad_66_w , p_ad_76_w ;
wire [`PIXEL_WIDTH-1 : 0] p_ad_47_w , p_ad_57_w , p_ad_67_w , p_ad_77_w ;
// level 2: 64 to 32
wire [`PIXEL_WIDTH : 0] l_2_00_w , l_2_20_w , l_2_40_w , l_2_60_w ;
wire [`PIXEL_WIDTH : 0] l_2_01_w , l_2_21_w , l_2_41_w , l_2_61_w ;
wire [`PIXEL_WIDTH : 0] l_2_02_w , l_2_22_w , l_2_42_w , l_2_62_w ;
wire [`PIXEL_WIDTH : 0] l_2_03_w , l_2_23_w , l_2_43_w , l_2_63_w ;
wire [`PIXEL_WIDTH : 0] l_2_04_w , l_2_24_w , l_2_44_w , l_2_64_w ;
wire [`PIXEL_WIDTH : 0] l_2_05_w , l_2_25_w , l_2_45_w , l_2_65_w ;
wire [`PIXEL_WIDTH : 0] l_2_06_w , l_2_26_w , l_2_46_w , l_2_66_w ;
wire [`PIXEL_WIDTH : 0] l_2_07_w , l_2_27_w , l_2_47_w , l_2_67_w ;
// level 3: 32 to 16
wire [`PIXEL_WIDTH+1 : 0] l_3_00_w , l_3_40_w ;
wire [`PIXEL_WIDTH+1 : 0] l_3_01_w , l_3_41_w ;
wire [`PIXEL_WIDTH+1 : 0] l_3_02_w , l_3_42_w ;
wire [`PIXEL_WIDTH+1 : 0] l_3_03_w , l_3_43_w ;
wire [`PIXEL_WIDTH+1 : 0] l_3_04_w , l_3_44_w ;
wire [`PIXEL_WIDTH+1 : 0] l_3_05_w , l_3_45_w ;
wire [`PIXEL_WIDTH+1 : 0] l_3_06_w , l_3_46_w ;
wire [`PIXEL_WIDTH+1 : 0] l_3_07_w , l_3_47_w ;
// level 4: 16 to 8
wire [`PIXEL_WIDTH+2 : 0] l_4_00_w ;
wire [`PIXEL_WIDTH+2 : 0] l_4_01_w ;
wire [`PIXEL_WIDTH+2 : 0] l_4_02_w ;
wire [`PIXEL_WIDTH+2 : 0] l_4_03_w ;
wire [`PIXEL_WIDTH+2 : 0] l_4_04_w ;
wire [`PIXEL_WIDTH+2 : 0] l_4_05_w ;
wire [`PIXEL_WIDTH+2 : 0] l_4_06_w ;
wire [`PIXEL_WIDTH+2 : 0] l_4_07_w ;
// level 5: 8 to 4
wire [`PIXEL_WIDTH+3 : 0] l_5_00_w ;
wire [`PIXEL_WIDTH+3 : 0] l_5_02_w ;
wire [`PIXEL_WIDTH+3 : 0] l_5_04_w ;
wire [`PIXEL_WIDTH+3 : 0] l_5_06_w ;
// level 6: 4 to 2
wire [`PIXEL_WIDTH+4 : 0] l_6_00_w ;
wire [`PIXEL_WIDTH+4 : 0] l_6_04_w ;
// level 7: 2 to 1
wire [`PIXEL_WIDTH+5 : 0] l_7_00_w ;
//*** MAIN BODY ****************************************************************
// distribution
assign { ori_00_w ,ori_10_w ,ori_20_w ,ori_30_w ,ori_40_w ,ori_50_w ,ori_60_w ,ori_70_w ,
ori_01_w ,ori_11_w ,ori_21_w ,ori_31_w ,ori_41_w ,ori_51_w ,ori_61_w ,ori_71_w ,
ori_02_w ,ori_12_w ,ori_22_w ,ori_32_w ,ori_42_w ,ori_52_w ,ori_62_w ,ori_72_w ,
ori_03_w ,ori_13_w ,ori_23_w ,ori_33_w ,ori_43_w ,ori_53_w ,ori_63_w ,ori_73_w ,
ori_04_w ,ori_14_w ,ori_24_w ,ori_34_w ,ori_44_w ,ori_54_w ,ori_64_w ,ori_74_w ,
ori_05_w ,ori_15_w ,ori_25_w ,ori_35_w ,ori_45_w ,ori_55_w ,ori_65_w ,ori_75_w ,
ori_06_w ,ori_16_w ,ori_26_w ,ori_36_w ,ori_46_w ,ori_56_w ,ori_66_w ,ori_76_w ,
ori_07_w ,ori_17_w ,ori_27_w ,ori_37_w ,ori_47_w ,ori_57_w ,ori_67_w ,ori_77_w } = ori_i ;
assign { ref_00_w ,ref_10_w ,ref_20_w ,ref_30_w ,ref_40_w ,ref_50_w ,ref_60_w ,ref_70_w ,
ref_01_w ,ref_11_w ,ref_21_w ,ref_31_w ,ref_41_w ,ref_51_w ,ref_61_w ,ref_71_w ,
ref_02_w ,ref_12_w ,ref_22_w ,ref_32_w ,ref_42_w ,ref_52_w ,ref_62_w ,ref_72_w ,
ref_03_w ,ref_13_w ,ref_23_w ,ref_33_w ,ref_43_w ,ref_53_w ,ref_63_w ,ref_73_w ,
ref_04_w ,ref_14_w ,ref_24_w ,ref_34_w ,ref_44_w ,ref_54_w ,ref_64_w ,ref_74_w ,
ref_05_w ,ref_15_w ,ref_25_w ,ref_35_w ,ref_45_w ,ref_55_w ,ref_65_w ,ref_75_w ,
ref_06_w ,ref_16_w ,ref_26_w ,ref_36_w ,ref_46_w ,ref_56_w ,ref_66_w ,ref_76_w ,
ref_07_w ,ref_17_w ,ref_27_w ,ref_37_w ,ref_47_w ,ref_57_w ,ref_67_w ,ref_77_w } = ref_i ;
// pixel difference
assign p_d_00_w = ref_00_w - ori_00_w ; assign p_d_10_w = ref_10_w - ori_10_w ; assign p_d_20_w = ref_20_w - ori_20_w ;
assign p_d_01_w = ref_01_w - ori_01_w ; assign p_d_11_w = ref_11_w - ori_11_w ; assign p_d_21_w = ref_21_w - ori_21_w ;
assign p_d_02_w = ref_02_w - ori_02_w ; assign p_d_12_w = ref_12_w - ori_12_w ; assign p_d_22_w = ref_22_w - ori_22_w ;
assign p_d_03_w = ref_03_w - ori_03_w ; assign p_d_13_w = ref_13_w - ori_13_w ; assign p_d_23_w = ref_23_w - ori_23_w ;
assign p_d_04_w = ref_04_w - ori_04_w ; assign p_d_14_w = ref_14_w - ori_14_w ; assign p_d_24_w = ref_24_w - ori_24_w ;
assign p_d_05_w = ref_05_w - ori_05_w ; assign p_d_15_w = ref_15_w - ori_15_w ; assign p_d_25_w = ref_25_w - ori_25_w ;
assign p_d_06_w = ref_06_w - ori_06_w ; assign p_d_16_w = ref_16_w - ori_16_w ; assign p_d_26_w = ref_26_w - ori_26_w ;
assign p_d_07_w = ref_07_w - ori_07_w ; assign p_d_17_w = ref_17_w - ori_17_w ; assign p_d_27_w = ref_27_w - ori_27_w ;
assign p_d_30_w = ref_30_w - ori_30_w ; assign p_d_40_w = ref_40_w - ori_40_w ; assign p_d_50_w = ref_50_w - ori_50_w ;
assign p_d_31_w = ref_31_w - ori_31_w ; assign p_d_41_w = ref_41_w - ori_41_w ; assign p_d_51_w = ref_51_w - ori_51_w ;
assign p_d_32_w = ref_32_w - ori_32_w ; assign p_d_42_w = ref_42_w - ori_42_w ; assign p_d_52_w = ref_52_w - ori_52_w ;
assign p_d_33_w = ref_33_w - ori_33_w ; assign p_d_43_w = ref_43_w - ori_43_w ; assign p_d_53_w = ref_53_w - ori_53_w ;
assign p_d_34_w = ref_34_w - ori_34_w ; assign p_d_44_w = ref_44_w - ori_44_w ; assign p_d_54_w = ref_54_w - ori_54_w ;
assign p_d_35_w = ref_35_w - ori_35_w ; assign p_d_45_w = ref_45_w - ori_45_w ; assign p_d_55_w = ref_55_w - ori_55_w ;
assign p_d_36_w = ref_36_w - ori_36_w ; assign p_d_46_w = ref_46_w - ori_46_w ; assign p_d_56_w = ref_56_w - ori_56_w ;
assign p_d_37_w = ref_37_w - ori_37_w ; assign p_d_47_w = ref_47_w - ori_47_w ; assign p_d_57_w = ref_57_w - ori_57_w ;
assign p_d_60_w = ref_60_w - ori_60_w ; assign p_d_70_w = ref_70_w - ori_70_w ;
assign p_d_61_w = ref_61_w - ori_61_w ; assign p_d_71_w = ref_71_w - ori_71_w ;
assign p_d_62_w = ref_62_w - ori_62_w ; assign p_d_72_w = ref_72_w - ori_72_w ;
assign p_d_63_w = ref_63_w - ori_63_w ; assign p_d_73_w = ref_73_w - ori_73_w ;
assign p_d_64_w = ref_64_w - ori_64_w ; assign p_d_74_w = ref_74_w - ori_74_w ;
assign p_d_65_w = ref_65_w - ori_65_w ; assign p_d_75_w = ref_75_w - ori_75_w ;
assign p_d_66_w = ref_66_w - ori_66_w ; assign p_d_76_w = ref_76_w - ori_76_w ;
assign p_d_67_w = ref_67_w - ori_67_w ; assign p_d_77_w = ref_77_w - ori_77_w ;
// pixel absolute difference
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs00 ( .a_i ( p_d_00_w ), .b_o ( p_ad_00_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs01 ( .a_i ( p_d_01_w ), .b_o ( p_ad_01_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs02 ( .a_i ( p_d_02_w ), .b_o ( p_ad_02_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs03 ( .a_i ( p_d_03_w ), .b_o ( p_ad_03_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs04 ( .a_i ( p_d_04_w ), .b_o ( p_ad_04_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs05 ( .a_i ( p_d_05_w ), .b_o ( p_ad_05_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs06 ( .a_i ( p_d_06_w ), .b_o ( p_ad_06_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs07 ( .a_i ( p_d_07_w ), .b_o ( p_ad_07_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs10 ( .a_i ( p_d_10_w ), .b_o ( p_ad_10_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs11 ( .a_i ( p_d_11_w ), .b_o ( p_ad_11_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs12 ( .a_i ( p_d_12_w ), .b_o ( p_ad_12_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs13 ( .a_i ( p_d_13_w ), .b_o ( p_ad_13_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs14 ( .a_i ( p_d_14_w ), .b_o ( p_ad_14_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs15 ( .a_i ( p_d_15_w ), .b_o ( p_ad_15_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs16 ( .a_i ( p_d_16_w ), .b_o ( p_ad_16_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs17 ( .a_i ( p_d_17_w ), .b_o ( p_ad_17_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs20 ( .a_i ( p_d_20_w ), .b_o ( p_ad_20_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs21 ( .a_i ( p_d_21_w ), .b_o ( p_ad_21_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs22 ( .a_i ( p_d_22_w ), .b_o ( p_ad_22_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs23 ( .a_i ( p_d_23_w ), .b_o ( p_ad_23_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs24 ( .a_i ( p_d_24_w ), .b_o ( p_ad_24_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs25 ( .a_i ( p_d_25_w ), .b_o ( p_ad_25_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs26 ( .a_i ( p_d_26_w ), .b_o ( p_ad_26_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs27 ( .a_i ( p_d_27_w ), .b_o ( p_ad_27_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs30 ( .a_i ( p_d_30_w ), .b_o ( p_ad_30_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs31 ( .a_i ( p_d_31_w ), .b_o ( p_ad_31_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs32 ( .a_i ( p_d_32_w ), .b_o ( p_ad_32_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs33 ( .a_i ( p_d_33_w ), .b_o ( p_ad_33_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs34 ( .a_i ( p_d_34_w ), .b_o ( p_ad_34_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs35 ( .a_i ( p_d_35_w ), .b_o ( p_ad_35_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs36 ( .a_i ( p_d_36_w ), .b_o ( p_ad_36_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs37 ( .a_i ( p_d_37_w ), .b_o ( p_ad_37_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs40 ( .a_i ( p_d_40_w ), .b_o ( p_ad_40_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs41 ( .a_i ( p_d_41_w ), .b_o ( p_ad_41_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs42 ( .a_i ( p_d_42_w ), .b_o ( p_ad_42_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs43 ( .a_i ( p_d_43_w ), .b_o ( p_ad_43_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs44 ( .a_i ( p_d_44_w ), .b_o ( p_ad_44_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs45 ( .a_i ( p_d_45_w ), .b_o ( p_ad_45_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs46 ( .a_i ( p_d_46_w ), .b_o ( p_ad_46_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs47 ( .a_i ( p_d_47_w ), .b_o ( p_ad_47_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs50 ( .a_i ( p_d_50_w ), .b_o ( p_ad_50_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs51 ( .a_i ( p_d_51_w ), .b_o ( p_ad_51_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs52 ( .a_i ( p_d_52_w ), .b_o ( p_ad_52_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs53 ( .a_i ( p_d_53_w ), .b_o ( p_ad_53_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs54 ( .a_i ( p_d_54_w ), .b_o ( p_ad_54_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs55 ( .a_i ( p_d_55_w ), .b_o ( p_ad_55_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs56 ( .a_i ( p_d_56_w ), .b_o ( p_ad_56_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs57 ( .a_i ( p_d_57_w ), .b_o ( p_ad_57_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs60 ( .a_i ( p_d_60_w ), .b_o ( p_ad_60_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs61 ( .a_i ( p_d_61_w ), .b_o ( p_ad_61_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs62 ( .a_i ( p_d_62_w ), .b_o ( p_ad_62_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs63 ( .a_i ( p_d_63_w ), .b_o ( p_ad_63_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs64 ( .a_i ( p_d_64_w ), .b_o ( p_ad_64_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs65 ( .a_i ( p_d_65_w ), .b_o ( p_ad_65_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs66 ( .a_i ( p_d_66_w ), .b_o ( p_ad_66_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs67 ( .a_i ( p_d_67_w ), .b_o ( p_ad_67_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs70 ( .a_i ( p_d_70_w ), .b_o ( p_ad_70_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs71 ( .a_i ( p_d_71_w ), .b_o ( p_ad_71_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs72 ( .a_i ( p_d_72_w ), .b_o ( p_ad_72_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs73 ( .a_i ( p_d_73_w ), .b_o ( p_ad_73_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs74 ( .a_i ( p_d_74_w ), .b_o ( p_ad_74_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs75 ( .a_i ( p_d_75_w ), .b_o ( p_ad_75_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs76 ( .a_i ( p_d_76_w ), .b_o ( p_ad_76_w ) );
abs #( .INPUT_BITS ( `PIXEL_WIDTH+1 ) ) abs77 ( .a_i ( p_d_77_w ), .b_o ( p_ad_77_w ) );
/*
assign p_ad_00_w = (p_d_00_w>0) ? p_d_00_w : -p_d_00_w ; assign p_ad_10_w = (p_d_10_w>0) ? p_d_10_w : -p_d_10_w ;
assign p_ad_01_w = (p_d_01_w>0) ? p_d_01_w : -p_d_01_w ; assign p_ad_11_w = (p_d_11_w>0) ? p_d_11_w : -p_d_11_w ;
assign p_ad_02_w = (p_d_02_w>0) ? p_d_02_w : -p_d_02_w ; assign p_ad_12_w = (p_d_12_w>0) ? p_d_12_w : -p_d_12_w ;
assign p_ad_03_w = (p_d_03_w>0) ? p_d_03_w : -p_d_03_w ; assign p_ad_13_w = (p_d_13_w>0) ? p_d_13_w : -p_d_13_w ;
assign p_ad_04_w = (p_d_04_w>0) ? p_d_04_w : -p_d_04_w ; assign p_ad_14_w = (p_d_14_w>0) ? p_d_14_w : -p_d_14_w ;
assign p_ad_05_w = (p_d_05_w>0) ? p_d_05_w : -p_d_05_w ; assign p_ad_15_w = (p_d_15_w>0) ? p_d_15_w : -p_d_15_w ;
assign p_ad_06_w = (p_d_06_w>0) ? p_d_06_w : -p_d_06_w ; assign p_ad_16_w = (p_d_16_w>0) ? p_d_16_w : -p_d_16_w ;
assign p_ad_07_w = (p_d_07_w>0) ? p_d_07_w : -p_d_07_w ; assign p_ad_17_w = (p_d_17_w>0) ? p_d_17_w : -p_d_17_w ;
assign p_ad_20_w = (p_d_20_w>0) ? p_d_20_w : -p_d_20_w ; assign p_ad_30_w = (p_d_30_w>0) ? p_d_30_w : -p_d_30_w ;
assign p_ad_21_w = (p_d_21_w>0) ? p_d_21_w : -p_d_21_w ; assign p_ad_31_w = (p_d_31_w>0) ? p_d_31_w : -p_d_31_w ;
assign p_ad_22_w = (p_d_22_w>0) ? p_d_22_w : -p_d_22_w ; assign p_ad_32_w = (p_d_32_w>0) ? p_d_32_w : -p_d_32_w ;
assign p_ad_23_w = (p_d_23_w>0) ? p_d_23_w : -p_d_23_w ; assign p_ad_33_w = (p_d_33_w>0) ? p_d_33_w : -p_d_33_w ;
assign p_ad_24_w = (p_d_24_w>0) ? p_d_24_w : -p_d_24_w ; assign p_ad_34_w = (p_d_34_w>0) ? p_d_34_w : -p_d_34_w ;
assign p_ad_25_w = (p_d_25_w>0) ? p_d_25_w : -p_d_25_w ; assign p_ad_35_w = (p_d_35_w>0) ? p_d_35_w : -p_d_35_w ;
assign p_ad_26_w = (p_d_26_w>0) ? p_d_26_w : -p_d_26_w ; assign p_ad_36_w = (p_d_36_w>0) ? p_d_36_w : -p_d_36_w ;
assign p_ad_27_w = (p_d_27_w>0) ? p_d_27_w : -p_d_27_w ; assign p_ad_37_w = (p_d_37_w>0) ? p_d_37_w : -p_d_37_w ;
assign p_ad_40_w = (p_d_40_w>0) ? p_d_40_w : -p_d_40_w ; assign p_ad_50_w = (p_d_50_w>0) ? p_d_50_w : -p_d_50_w ;
assign p_ad_41_w = (p_d_41_w>0) ? p_d_41_w : -p_d_41_w ; assign p_ad_51_w = (p_d_51_w>0) ? p_d_51_w : -p_d_51_w ;
assign p_ad_42_w = (p_d_42_w>0) ? p_d_42_w : -p_d_42_w ; assign p_ad_52_w = (p_d_52_w>0) ? p_d_52_w : -p_d_52_w ;
assign p_ad_43_w = (p_d_43_w>0) ? p_d_43_w : -p_d_43_w ; assign p_ad_53_w = (p_d_53_w>0) ? p_d_53_w : -p_d_53_w ;
assign p_ad_44_w = (p_d_44_w>0) ? p_d_44_w : -p_d_44_w ; assign p_ad_54_w = (p_d_54_w>0) ? p_d_54_w : -p_d_54_w ;
assign p_ad_45_w = (p_d_45_w>0) ? p_d_45_w : -p_d_45_w ; assign p_ad_55_w = (p_d_55_w>0) ? p_d_55_w : -p_d_55_w ;
assign p_ad_46_w = (p_d_46_w>0) ? p_d_46_w : -p_d_46_w ; assign p_ad_56_w = (p_d_56_w>0) ? p_d_56_w : -p_d_56_w ;
assign p_ad_47_w = (p_d_47_w>0) ? p_d_47_w : -p_d_47_w ; assign p_ad_57_w = (p_d_57_w>0) ? p_d_57_w : -p_d_57_w ;
assign p_ad_60_w = (p_d_60_w>0) ? p_d_60_w : -p_d_60_w ; assign p_ad_70_w = (p_d_70_w>0) ? p_d_70_w : -p_d_70_w ;
assign p_ad_61_w = (p_d_61_w>0) ? p_d_61_w : -p_d_61_w ; assign p_ad_71_w = (p_d_71_w>0) ? p_d_71_w : -p_d_71_w ;
assign p_ad_62_w = (p_d_62_w>0) ? p_d_62_w : -p_d_62_w ; assign p_ad_72_w = (p_d_72_w>0) ? p_d_72_w : -p_d_72_w ;
assign p_ad_63_w = (p_d_63_w>0) ? p_d_63_w : -p_d_63_w ; assign p_ad_73_w = (p_d_73_w>0) ? p_d_73_w : -p_d_73_w ;
assign p_ad_64_w = (p_d_64_w>0) ? p_d_64_w : -p_d_64_w ; assign p_ad_74_w = (p_d_74_w>0) ? p_d_74_w : -p_d_74_w ;
assign p_ad_65_w = (p_d_65_w>0) ? p_d_65_w : -p_d_65_w ; assign p_ad_75_w = (p_d_75_w>0) ? p_d_75_w : -p_d_75_w ;
assign p_ad_66_w = (p_d_66_w>0) ? p_d_66_w : -p_d_66_w ; assign p_ad_76_w = (p_d_76_w>0) ? p_d_76_w : -p_d_76_w ;
assign p_ad_67_w = (p_d_67_w>0) ? p_d_67_w : -p_d_67_w ; assign p_ad_77_w = (p_d_77_w>0) ? p_d_77_w : -p_d_77_w ;
*/
// level 2: 64 to 32
assign l_2_00_w = p_ad_00_w + p_ad_10_w ; assign l_2_20_w = p_ad_20_w + p_ad_30_w ;
assign l_2_01_w = p_ad_01_w + p_ad_11_w ; assign l_2_21_w = p_ad_21_w + p_ad_31_w ;
assign l_2_02_w = p_ad_02_w + p_ad_12_w ; assign l_2_22_w = p_ad_22_w + p_ad_32_w ;
assign l_2_03_w = p_ad_03_w + p_ad_13_w ; assign l_2_23_w = p_ad_23_w + p_ad_33_w ;
assign l_2_04_w = p_ad_04_w + p_ad_14_w ; assign l_2_24_w = p_ad_24_w + p_ad_34_w ;
assign l_2_05_w = p_ad_05_w + p_ad_15_w ; assign l_2_25_w = p_ad_25_w + p_ad_35_w ;
assign l_2_06_w = p_ad_06_w + p_ad_16_w ; assign l_2_26_w = p_ad_26_w + p_ad_36_w ;
assign l_2_07_w = p_ad_07_w + p_ad_17_w ; assign l_2_27_w = p_ad_27_w + p_ad_37_w ;
assign l_2_40_w = p_ad_40_w + p_ad_50_w ; assign l_2_60_w = p_ad_60_w + p_ad_70_w ;
assign l_2_41_w = p_ad_41_w + p_ad_51_w ; assign l_2_61_w = p_ad_61_w + p_ad_71_w ;
assign l_2_42_w = p_ad_42_w + p_ad_52_w ; assign l_2_62_w = p_ad_62_w + p_ad_72_w ;
assign l_2_43_w = p_ad_43_w + p_ad_53_w ; assign l_2_63_w = p_ad_63_w + p_ad_73_w ;
assign l_2_44_w = p_ad_44_w + p_ad_54_w ; assign l_2_64_w = p_ad_64_w + p_ad_74_w ;
assign l_2_45_w = p_ad_45_w + p_ad_55_w ; assign l_2_65_w = p_ad_65_w + p_ad_75_w ;
assign l_2_46_w = p_ad_46_w + p_ad_56_w ; assign l_2_66_w = p_ad_66_w + p_ad_76_w ;
assign l_2_47_w = p_ad_47_w + p_ad_57_w ; assign l_2_67_w = p_ad_67_w + p_ad_77_w ;
// level 3: 32 to 16
assign l_3_00_w = l_2_00_w + l_2_20_w ; assign l_3_40_w = l_2_40_w + l_2_60_w ;
assign l_3_01_w = l_2_01_w + l_2_21_w ; assign l_3_41_w = l_2_41_w + l_2_61_w ;
assign l_3_02_w = l_2_02_w + l_2_22_w ; assign l_3_42_w = l_2_42_w + l_2_62_w ;
assign l_3_03_w = l_2_03_w + l_2_23_w ; assign l_3_43_w = l_2_43_w + l_2_63_w ;
assign l_3_04_w = l_2_04_w + l_2_24_w ; assign l_3_44_w = l_2_44_w + l_2_64_w ;
assign l_3_05_w = l_2_05_w + l_2_25_w ; assign l_3_45_w = l_2_45_w + l_2_65_w ;
assign l_3_06_w = l_2_06_w + l_2_26_w ; assign l_3_46_w = l_2_46_w + l_2_66_w ;
assign l_3_07_w = l_2_07_w + l_2_27_w ; assign l_3_47_w = l_2_47_w + l_2_67_w ;
// level 4: 16 to 8
assign l_4_00_w = l_3_00_w + l_3_40_w ;
assign l_4_01_w = l_3_01_w + l_3_41_w ;
assign l_4_02_w = l_3_02_w + l_3_42_w ;
assign l_4_03_w = l_3_03_w + l_3_43_w ;
assign l_4_04_w = l_3_04_w + l_3_44_w ;
assign l_4_05_w = l_3_05_w + l_3_45_w ;
assign l_4_06_w = l_3_06_w + l_3_46_w ;
assign l_4_07_w = l_3_07_w + l_3_47_w ;
// level 5: 8 to 4
assign l_5_00_w = l_4_00_w + l_4_01_w ;
assign l_5_02_w = l_4_02_w + l_4_03_w ;
assign l_5_04_w = l_4_04_w + l_4_05_w ;
assign l_5_06_w = l_4_06_w + l_4_07_w ;
// level 6: 4 to 2
assign l_6_00_w = l_5_00_w + l_5_02_w ;
assign l_6_04_w = l_5_04_w + l_5_06_w ;
// level 7: 2 to 1
assign l_7_00_w = l_6_00_w + l_6_04_w ;
/*
// val_o
always @(posedge clk or negedge rstn ) begin
if( !rstn )
val_o <= 'd0 ;
else begin
val_o <= enable_i ;
end
end
*/
// sad_o
always @(posedge clk or negedge rstn ) begin
if( !rstn )
sad_o <= 'd0 ;
else if( enable_i ) begin
sad_o <= l_7_00_w ;
end
end
//*** DEBUG ********************************************************************
`ifdef DEBUG
wire debug_0 ;
wire debug_1 ;
assign debug_0 = p_d_00_w>0 ;
assign debug_1 = p_d_00_w>'d0 ;
`endif
endmodule
module abs ( // created by Yufeng Bai
a_i ,
b_o
);
parameter INPUT_BITS = `PIXEL_WIDTH ;
input [INPUT_BITS-1 : 0] a_i ;
output [INPUT_BITS-2 : 0] b_o ;
wire [INPUT_BITS-1 : 0] b_o_w ;
assign b_o_w = ({(INPUT_BITS-1){a_i[INPUT_BITS-1]}} ^ {a_i[INPUT_BITS-2:0]}) + {{(INPUT_BITS-1){1'b0}},a_i[INPUT_BITS-1]};
assign b_o = b_o_w[INPUT_BITS-2:0];
endmodule |
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: msp_debug.v
//
// *Module Description:
// MSP430 core debug utility signals
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 134 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2012-03-22 21:31:06 +0100 (Don, 22. Mär 2012) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module msp_debug (
// OUTPUTs
e_state, // Execution state
i_state, // Instruction fetch state
inst_cycle, // Cycle number within current instruction
inst_full, // Currently executed instruction (full version)
inst_number, // Instruction number since last system reset
inst_pc, // Instruction Program counter
inst_short, // Currently executed instruction (short version)
// INPUTs
mclk, // Main system clock
puc_rst // Main system reset
);
// OUTPUTs
//============
output [8*32-1:0] e_state; // Execution state
output [8*32-1:0] i_state; // Instruction fetch state
output [31:0] inst_cycle; // Cycle number within current instruction
output [8*32-1:0] inst_full; // Currently executed instruction (full version)
output [31:0] inst_number; // Instruction number since last system reset
output [15:0] inst_pc; // Instruction Program counter
output [8*32-1:0] inst_short; // Currently executed instruction (short version)
// INPUTs
//============
input mclk; // Main system clock
input puc_rst; // Main system reset
//=============================================================================
// 1) ASCII FORMATING FUNCTIONS
//=============================================================================
// This function simply concatenates two strings together, ignorning the NULL
// at the end of string2.
// The specified number of space will be inserted between string1 and string2
function [64*8-1:0] myFormat;
input [32*8-1:0] string1;
input [32*8-1:0] string2;
input [3:0] space;
integer i,j;
begin
myFormat = 0;
`ifdef VXL // no +:
`else
j = 0;
for ( i=0; i < 32; i=i+1) // Copy string2
begin
myFormat[8*i +: 8] = string2[8*i +: 8];
if ((string2[8*i +: 8] == 0) && (j == 0)) j=i;
end
for ( i=0; i < space; i=i+1) // Add spaces
myFormat[8*(j+i) +: 8] = " ";
j=j+space;
for ( i=0; i < 32; i=i+1) // Copy string1
myFormat[8*(j+i) +: 8] = string1[8*i +: 8];
`endif
end
endfunction
//=============================================================================
// 2) CONNECTIONS TO MSP430 CORE INTERNALS
//=============================================================================
wire [2:0] i_state_bin = `HIER_MODULE.openMSP430_0.frontend_0.i_state;
wire [3:0] e_state_bin = `HIER_MODULE.openMSP430_0.frontend_0.e_state;
wire decode = `HIER_MODULE.openMSP430_0.frontend_0.decode;
wire [15:0] ir = `HIER_MODULE.openMSP430_0.frontend_0.ir;
wire irq_detect = `HIER_MODULE.openMSP430_0.frontend_0.irq_detect;
wire [3:0] irq_num = `HIER_MODULE.openMSP430_0.frontend_0.irq_num;
wire [15:0] pc = `HIER_MODULE.openMSP430_0.frontend_0.pc;
//=============================================================================
// 3) GENERATE DEBUG SIGNALS
//=============================================================================
// Instruction fetch state
//=========================
reg [8*32-1:0] i_state;
always @(i_state_bin)
case(i_state_bin)
3'h0 : i_state = "IRQ_FETCH";
3'h1 : i_state = "IRQ_DONE";
3'h2 : i_state = "DEC";
3'h3 : i_state = "EXT1";
3'h4 : i_state = "EXT2";
3'h5 : i_state = "IDLE";
default : i_state = "XXXXX";
endcase
// Execution state
//=========================
reg [8*32-1:0] e_state;
always @(e_state_bin)
case(e_state_bin)
4'h2 : e_state = "IRQ_0";
4'h1 : e_state = "IRQ_1";
4'h0 : e_state = "IRQ_2";
4'h3 : e_state = "IRQ_3";
4'h4 : e_state = "IRQ_4";
4'h5 : e_state = "SRC_AD";
4'h6 : e_state = "SRC_RD";
4'h7 : e_state = "SRC_WR";
4'h8 : e_state = "DST_AD";
4'h9 : e_state = "DST_RD";
4'hA : e_state = "DST_WR";
4'hB : e_state = "EXEC";
4'hC : e_state = "JUMP";
4'hD : e_state = "IDLE";
default : e_state = "xxxx";
endcase
// Count instruction number & cycles
//====================================
reg [31:0] inst_number;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) inst_number <= 0;
else if (decode) inst_number <= inst_number+1;
reg [31:0] inst_cycle;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) inst_cycle <= 0;
else if (decode) inst_cycle <= 0;
else inst_cycle <= inst_cycle+1;
// Decode instruction
//====================================
// Buffer opcode
reg [15:0] opcode;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) opcode <= 0;
else if (decode) opcode <= ir;
// Interrupts
reg irq;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) irq <= 1'b1;
else if (decode) irq <= irq_detect;
// Instruction type
reg [8*32-1:0] inst_type;
always @(opcode or irq)
if (irq)
inst_type = "IRQ";
else
case(opcode[15:13])
3'b000 : inst_type = "SIG-OP";
3'b001 : inst_type = "JUMP";
default : inst_type = "TWO-OP";
endcase
// Instructions name
reg [8*32-1:0] inst_name;
always @(opcode or inst_type or irq_num)
if (inst_type=="IRQ")
case(irq_num[3:0])
4'b0000 : inst_name = "IRQ 0";
4'b0001 : inst_name = "IRQ 1";
4'b0010 : inst_name = "IRQ 2";
4'b0011 : inst_name = "IRQ 3";
4'b0100 : inst_name = "IRQ 4";
4'b0101 : inst_name = "IRQ 5";
4'b0110 : inst_name = "IRQ 6";
4'b0111 : inst_name = "IRQ 7";
4'b1000 : inst_name = "IRQ 8";
4'b1001 : inst_name = "IRQ 9";
4'b1010 : inst_name = "IRQ 10";
4'b1011 : inst_name = "IRQ 11";
4'b1100 : inst_name = "IRQ 12";
4'b1101 : inst_name = "IRQ 13";
4'b1110 : inst_name = "NMI";
default : inst_name = "RESET";
endcase
else if (inst_type=="SIG-OP")
case(opcode[15:7])
9'b000100_000 : inst_name = "RRC";
9'b000100_001 : inst_name = "SWPB";
9'b000100_010 : inst_name = "RRA";
9'b000100_011 : inst_name = "SXT";
9'b000100_100 : inst_name = "PUSH";
9'b000100_101 : inst_name = "CALL";
9'b000100_110 : inst_name = "RETI";
default : inst_name = "xxxx";
endcase
else if (inst_type=="JUMP")
case(opcode[15:10])
6'b001_000 : inst_name = "JNE";
6'b001_001 : inst_name = "JEQ";
6'b001_010 : inst_name = "JNC";
6'b001_011 : inst_name = "JC";
6'b001_100 : inst_name = "JN";
6'b001_101 : inst_name = "JGE";
6'b001_110 : inst_name = "JL";
6'b001_111 : inst_name = "JMP";
default : inst_name = "xxxx";
endcase
else if (inst_type=="TWO-OP")
case(opcode[15:12])
4'b0100 : inst_name = "MOV";
4'b0101 : inst_name = "ADD";
4'b0110 : inst_name = "ADDC";
4'b0111 : inst_name = "SUBC";
4'b1000 : inst_name = "SUB";
4'b1001 : inst_name = "CMP";
4'b1010 : inst_name = "DADD";
4'b1011 : inst_name = "BIT";
4'b1100 : inst_name = "BIC";
4'b1101 : inst_name = "BIS";
4'b1110 : inst_name = "XOR";
4'b1111 : inst_name = "AND";
default : inst_name = "xxxx";
endcase
// Instructions byte/word mode
reg [8*32-1:0] inst_bw;
always @(opcode or inst_type)
if (inst_type=="IRQ")
inst_bw = "";
else if (inst_type=="SIG-OP")
inst_bw = opcode[6] ? ".B" : "";
else if (inst_type=="JUMP")
inst_bw = "";
else if (inst_type=="TWO-OP")
inst_bw = opcode[6] ? ".B" : "";
// Source register
reg [8*32-1:0] inst_src;
wire [3:0] src_reg = (inst_type=="SIG-OP") ? opcode[3:0] : opcode[11:8];
always @(src_reg or inst_type)
if (inst_type=="IRQ")
inst_src = "";
else if (inst_type=="JUMP")
inst_src = "";
else if ((inst_type=="SIG-OP") || (inst_type=="TWO-OP"))
case(src_reg)
4'b0000 : inst_src = "r0";
4'b0001 : inst_src = "r1";
4'b0010 : inst_src = "r2";
4'b0011 : inst_src = "r3";
4'b0100 : inst_src = "r4";
4'b0101 : inst_src = "r5";
4'b0110 : inst_src = "r6";
4'b0111 : inst_src = "r7";
4'b1000 : inst_src = "r8";
4'b1001 : inst_src = "r9";
4'b1010 : inst_src = "r10";
4'b1011 : inst_src = "r11";
4'b1100 : inst_src = "r12";
4'b1101 : inst_src = "r13";
4'b1110 : inst_src = "r14";
default : inst_src = "r15";
endcase
// Destination register
reg [8*32-1:0] inst_dst;
always @(opcode or inst_type)
if (inst_type=="IRQ")
inst_dst = "";
else if (inst_type=="SIG-OP")
inst_dst = "";
else if (inst_type=="JUMP")
inst_dst = "";
else if (inst_type=="TWO-OP")
case(opcode[3:0])
4'b0000 : inst_dst = "r0";
4'b0001 : inst_dst = "r1";
4'b0010 : inst_dst = "r2";
4'b0011 : inst_dst = "r3";
4'b0100 : inst_dst = "r4";
4'b0101 : inst_dst = "r5";
4'b0110 : inst_dst = "r6";
4'b0111 : inst_dst = "r7";
4'b1000 : inst_dst = "r8";
4'b1001 : inst_dst = "r9";
4'b1010 : inst_dst = "r10";
4'b1011 : inst_dst = "r11";
4'b1100 : inst_dst = "r12";
4'b1101 : inst_dst = "r13";
4'b1110 : inst_dst = "r14";
default : inst_dst = "r15";
endcase
// Source Addressing mode
reg [8*32-1:0] inst_as;
always @(inst_type or src_reg or opcode or inst_src)
begin
if (inst_type=="IRQ")
inst_as = "";
else if (inst_type=="JUMP")
inst_as = "";
else if (src_reg==4'h3) // Addressing mode using R3
case (opcode[5:4])
2'b11 : inst_as = "#-1";
2'b10 : inst_as = "#2";
2'b01 : inst_as = "#1";
default: inst_as = "#0";
endcase
else if (src_reg==4'h2) // Addressing mode using R2
case (opcode[5:4])
2'b11 : inst_as = "#8";
2'b10 : inst_as = "#4";
2'b01 : inst_as = "&EDE";
default: inst_as = inst_src;
endcase
else if (src_reg==4'h0) // Addressing mode using R0
case (opcode[5:4])
2'b11 : inst_as = "#N";
2'b10 : inst_as = myFormat("@", inst_src, 0);
2'b01 : inst_as = "EDE";
default: inst_as = inst_src;
endcase
else // General Addressing mode
case (opcode[5:4])
2'b11 : begin
inst_as = myFormat("@", inst_src, 0);
inst_as = myFormat(inst_as, "+", 0);
end
2'b10 : inst_as = myFormat("@", inst_src, 0);
2'b01 : begin
inst_as = myFormat("x(", inst_src, 0);
inst_as = myFormat(inst_as, ")", 0);
end
default: inst_as = inst_src;
endcase
end
// Destination Addressing mode
reg [8*32-1:0] inst_ad;
always @(opcode or inst_type or inst_dst)
begin
if (inst_type!="TWO-OP")
inst_ad = "";
else if (opcode[3:0]==4'h2) // Addressing mode using R2
case (opcode[7])
1'b1 : inst_ad = "&EDE";
default: inst_ad = inst_dst;
endcase
else if (opcode[3:0]==4'h0) // Addressing mode using R0
case (opcode[7])
2'b1 : inst_ad = "EDE";
default: inst_ad = inst_dst;
endcase
else // General Addressing mode
case (opcode[7])
2'b1 : begin
inst_ad = myFormat("x(", inst_dst, 0);
inst_ad = myFormat(inst_ad, ")", 0);
end
default: inst_ad = inst_dst;
endcase
end
// Currently executed instruction
//================================
wire [8*32-1:0] inst_short = inst_name;
reg [8*32-1:0] inst_full;
always @(inst_type or inst_name or inst_bw or inst_as or inst_ad)
begin
inst_full = myFormat(inst_name, inst_bw, 0);
inst_full = myFormat(inst_full, inst_as, 1);
if (inst_type=="TWO-OP")
inst_full = myFormat(inst_full, ",", 0);
inst_full = myFormat(inst_full, inst_ad, 1);
if (opcode==16'h4303)
inst_full = "NOP";
if (opcode==`DBG_SWBRK_OP)
inst_full = "SBREAK";
end
// Instruction program counter
//================================
reg [15:0] inst_pc;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) inst_pc <= 16'h0000;
else if (decode) inst_pc <= pc;
endmodule // msp_debug
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Read Data Response AXI3 Slave Converter
// Forwards and re-assembles split transactions.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// r_axi3_conv
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_r_axi3_conv #
(
parameter C_FAMILY = "none",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_SUPPORT_SPLITTING = 1,
// Implement transaction splitting logic.
// Disabled whan all connected masters are AXI3 and have same or narrower data width.
parameter integer C_SUPPORT_BURSTS = 1
// Disabled when all connected masters are AxiLite,
// allowing logic to be simplified.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Command Interface
input wire cmd_valid,
input wire cmd_split,
output wire cmd_ready,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Throttling help signals.
wire cmd_ready_i;
wire pop_si_data;
wire si_stalling;
// Internal MI-side control signals.
wire M_AXI_RREADY_I;
// Internal signals for SI-side.
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID_I;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA_I;
wire [2-1:0] S_AXI_RRESP_I;
wire S_AXI_RLAST_I;
wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER_I;
wire S_AXI_RVALID_I;
wire S_AXI_RREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// Forward data from MI-Side to SI-Side while a command is available. When
// the transaction has completed the command is popped from the Command FIFO.
//
//
/////////////////////////////////////////////////////////////////////////////
// Pop word from SI-side.
assign M_AXI_RREADY_I = ~si_stalling & cmd_valid;
assign M_AXI_RREADY = M_AXI_RREADY_I;
// Indicate when there is data available @ SI-side.
assign S_AXI_RVALID_I = M_AXI_RVALID & cmd_valid;
// Get SI-side data.
assign pop_si_data = S_AXI_RVALID_I & S_AXI_RREADY_I;
// Signal that the command is done (so that it can be poped from command queue).
assign cmd_ready_i = cmd_valid & pop_si_data & M_AXI_RLAST;
assign cmd_ready = cmd_ready_i;
// Detect when MI-side is stalling.
assign si_stalling = S_AXI_RVALID_I & ~S_AXI_RREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Simple AXI signal forwarding:
//
// USER, ID, DATA and RRESP passes through untouched.
//
// LAST has to be filtered to remove any intermediate LAST (due to split
// trasactions). LAST is only removed for the first parts of a split
// transaction. When splitting is unsupported is the LAST filtering completely
// completely removed.
//
/////////////////////////////////////////////////////////////////////////////
// Calculate last, i.e. mask from split transactions.
assign S_AXI_RLAST_I = M_AXI_RLAST &
( ~cmd_split | ( C_SUPPORT_SPLITTING == 0 ) );
// Data is passed through.
assign S_AXI_RID_I = M_AXI_RID;
assign S_AXI_RUSER_I = M_AXI_RUSER;
assign S_AXI_RDATA_I = M_AXI_RDATA;
assign S_AXI_RRESP_I = M_AXI_RRESP;
/////////////////////////////////////////////////////////////////////////////
// SI-side output handling
//
/////////////////////////////////////////////////////////////////////////////
// TODO: registered?
assign S_AXI_RREADY_I = S_AXI_RREADY;
assign S_AXI_RVALID = S_AXI_RVALID_I;
assign S_AXI_RID = S_AXI_RID_I;
assign S_AXI_RDATA = S_AXI_RDATA_I;
assign S_AXI_RRESP = S_AXI_RRESP_I;
assign S_AXI_RLAST = S_AXI_RLAST_I;
assign S_AXI_RUSER = S_AXI_RUSER_I;
endmodule
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_238x128.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.1 Build 201 11/27/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module fifo_238x128 (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrempty,
wrfull,
wrusedw);
input [237:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [237:0] q;
output rdempty;
output wrempty;
output wrfull;
output [6:0] wrusedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "238"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "238"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5,"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "238"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: data 0 0 238 0 INPUT NODEFVAL data[237..0]
// Retrieval info: USED_PORT: q 0 0 238 0 OUTPUT NODEFVAL q[237..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL wrempty
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: wrusedw 0 0 7 0 OUTPUT NODEFVAL wrusedw[6..0]
// Retrieval info: CONNECT: @data 0 0 238 0 data 0 0 238 0
// Retrieval info: CONNECT: q 0 0 238 0 @q 0 0 238 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 7 0 @wrusedw 0 0 7 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_238x128.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_238x128.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_238x128.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_238x128.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_238x128_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_238x128_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_238x128_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_238x128_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module system1_input0 (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 31: 0] in_port;
input reset_n;
wire clk_en;
wire [ 31: 0] data_in;
wire [ 31: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {32 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O31A_2_V
`define SKY130_FD_SC_LS__O31A_2_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o31a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o31a_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o31a_2 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O31A_2_V
|
`timescale 1ns / 1ps
module interface_slice(
// gpio type
gpio_w_i,
gpio_w_o,
gpio_w_t,
gpio_i,
gpio_o,
gpio_t,
// iic type
scl_w_i,
scl_w_o,
scl_w_t,
sda_w_i,
sda_w_o,
sda_w_t,
scl_i,
scl_o,
scl_t,
sda_i,
sda_o,
sda_t,
// spi type
spi0_w_i,
spi0_w_o,
spi0_w_t,
spi1_w_i,
spi1_w_o,
spi1_w_t,
sck_w_i,
sck_w_o,
sck_w_t,
ss_w_i,
ss_w_o,
ss_w_t,
spi0_i,
spi0_o,
spi0_t,
spi1_i,
spi1_o,
spi1_t,
sck_i,
sck_o,
sck_t,
ss_i,
ss_o,
ss_t
);
parameter TYPE = 1;
parameter WIDTH = 1;
// gpio type
input [WIDTH-1:0] gpio_w_i;
input[WIDTH-1:0] gpio_w_o;
input[WIDTH-1:0] gpio_w_t;
output reg [WIDTH-1:0] gpio_i;
output reg [WIDTH-1:0] gpio_o;
output reg [WIDTH-1:0] gpio_t;
// iic type
input scl_w_i;
input scl_w_o;
input scl_w_t;
input sda_w_i;
input sda_w_o;
input sda_w_t;
output reg scl_i;
output reg scl_o;
output reg scl_t;
output reg sda_i;
output reg sda_o;
output reg sda_t;
// spi type
input spi0_w_i;
input spi0_w_o;
input spi0_w_t;
input spi1_w_i;
input spi1_w_o;
input spi1_w_t;
input sck_w_i;
input sck_w_o;
input sck_w_t;
input ss_w_i;
input ss_w_o;
input ss_w_t;
output reg spi0_i;
output reg spi0_o;
output reg spi0_t;
output reg spi1_i;
output reg spi1_o;
output reg spi1_t;
output reg sck_i;
output reg sck_o;
output reg sck_t;
output reg ss_i;
output reg ss_o;
output reg ss_t;
genvar i;
generate
case(TYPE)
1: begin: GPIO
for (i=0; i < WIDTH; i=i+1)
begin: GPIO_SLICE
always@(*) begin
gpio_i <= gpio_w_i;
gpio_o <= gpio_w_o;
gpio_t <= gpio_w_t;
end
end
end
2: begin: IIC
always@(*) begin
scl_i <= scl_w_i;
scl_o <= scl_w_o;
scl_t <= scl_w_t;
sda_i <= sda_w_i;
sda_o <= sda_w_o;
sda_t <= sda_w_t;
end
end
3: begin: SPI
always@(*) begin
spi0_i <= spi0_w_i;
spi0_o <= spi0_w_o;
spi0_t <= spi0_w_t;
spi1_i <= spi1_w_i;
spi1_o <= spi1_w_o;
spi1_t <= spi1_w_t;
sck_i <= sck_w_i;
sck_o <= sck_w_o;
sck_t <= sck_w_t;
ss_i <= ss_w_i;
ss_o <= ss_w_o;
ss_t <= ss_w_t;
end
end
endcase
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:09:37 08/01/2014
// Design Name:
// Module Name: main
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module main( key_input, sysclk, speaker_out, led_out );
input [8:0] key_input;
input sysclk;
//output [7:0] seven_out;
output speaker_out;
output [4:0] led_out;
wire [4:0] key_code;
wire [12:0] slow_rate;
wire slowclk;
key_encoder encoder(
.key_input(key_input),
.key_code(key_code),
.clk(sysclk)
);
/*
keytofrequency ktof(
.key_code(key_code),
.clk(sysclk),
.slow_rate(slow_rate)
);
*/
bram_decoder ktof (
.addra(key_code),
.douta(slow_rate),
.clka(sysclk)
);
clk_divider clk_divider(
.sysclk(sysclk),
.slowclk(slowclk)
);
pwm_controller pwm_ctrl(
.clk(slowclk),
.slow_rate(slow_rate),
.speaker_out(speaker_out)
);
//seven_segment seven_seg(
//.key_input(key_input[2:0]),
//.a_to_g(seven_out)
//);
led_controller led_ctrl(
.key_input(key_input[8:7]),
.led_out(led_out)
);
endmodule
|
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 4, Question 2
*/
/**
* Testbench for behavioral model for Finite State Machine model of the
* PISO convertor
*/
// Import the modules that will be tested for in this testbench
`include "piso.v"
// IMPORTANT: To run this, try: ncverilog -f piso.f +gui
module tb_piso();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the PISO convertor
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// serial_out & out_valid output signals
wire s_out,valid_op;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// load, clk, & reset_b
reg load_en,clock,reset_low;
reg [7:0] data_input;
// ============================================================
// Counter for loop to enumerate all the values of r
//integer count;
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen; Period=10ns
#5 clock = 0;
#5 clock = 1;
end
// ============================================================
/**
* Instantiate an instance of ee577bHw1q5model1() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "xor1model"
*/
PISO pisoc (
// instance_name(signal name),
// Signal name can be the same as the instance name
s_out,valid_op,data_input,load_en,reset_low,clock);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
// @ t=0; reset the sequence detector
reset_low=1'd0;
load_en=1'd1;
data_input=8'd10;
#90
reset_low=1'd1;
load_en=1'd1;
data_input=8'd13;
#90
reset_low=1'd1;
load_en=1'd1;
data_input=8'd6;
#90
reset_low=1'd1;
load_en=1'd1;
data_input=8'd5;
#90
reset_low=1'd1;
load_en=1'd1;
data_input=8'd7;
#40 // Ignored input data
reset_low=1'd1;
load_en=1'd1;
data_input=8'd3;
#30 // Reset the data again
reset_low=1'd0;
load_en=1'd1;
data_input=8'd2;
#20
reset_low=1'd1;
load_en=1'd1;
data_input=8'd15;
#90
reset_low=1'd1;
load_en=1'd1;
data_input=8'd9;
#70 // Ignored input data
reset_low=1'd1;
load_en=1'd1;
data_input=8'd14;
#90
reset_low=1'd1;
load_en=1'd1;
data_input=8'd12;
#90
reset_low=1'd1;
load_en=1'd1;
data_input=8'd10;
#90
reset_low=1'd1;
load_en=1'd0;
data_input=8'd236;
#90
reset_low=1'd1;
load_en=1'd1;
data_input=8'd174;
#90
reset_low=1'd1;
load_en=1'd1;
data_input=8'd214;
#120
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
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* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2018 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file dac_buf.v when simulating
// the core, dac_buf. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module dac_buf(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [10 : 0] addra;
input [7 : 0] dina;
input clkb;
input [8 : 0] addrb;
output [31 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(11),
.C_ADDRB_WIDTH(9),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(2048),
.C_READ_DEPTH_B(512),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(1),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(2048),
.C_WRITE_DEPTH_B(512),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
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